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drm/i915: Pass intel_crtc to update_wm functions
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
b033bb6d 59static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 60{
32608ca2
ID		 61 struct drm_i915_private *dev_priv = dev->dev_private;
62
b033bb6d 63 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 64 I915_WRITE(CHICKEN_PAR1_1,
65 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
66
b033bb6d
MK		 67 I915_WRITE(GEN8_CONFIG0,
68 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 69
70 /* WaEnableChickenDCPR:skl,bxt,kbl */
71 I915_WRITE(GEN8_CHICKEN_DCPR_1,
72 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 73
74 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 75 /* WaFbcWakeMemOn:skl,bxt,kbl */
76 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
77 DISP_FBC_WM_DIS |
78 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 79
80 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
81 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
82 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 83}
84
85static void bxt_init_clock_gating(struct drm_device *dev)
86{
fac5e23e 87 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 88
89 gen9_init_clock_gating(dev);
90
a7546159
NH		 91 /* WaDisableSDEUnitClockGating:bxt */
92 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
93 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
94
32608ca2
ID		 95 /*
96 * FIXME:
868434c5 97 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 98 */
32608ca2 99 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 100 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 101
102 /*
103 * Wa: Backlight PWM may stop in the asserted state, causing backlight
104 * to stay fully on.
105 */
106 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
107 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
108 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 109}
110
c921aba8
DV		 111static void i915_pineview_get_mem_freq(struct drm_device *dev)
112{
fac5e23e 113 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 114 u32 tmp;
115
116 tmp = I915_READ(CLKCFG);
117
118 switch (tmp & CLKCFG_FSB_MASK) {
119 case CLKCFG_FSB_533:
120 dev_priv->fsb_freq = 533; /* 133*4 */
121 break;
122 case CLKCFG_FSB_800:
123 dev_priv->fsb_freq = 800; /* 200*4 */
124 break;
125 case CLKCFG_FSB_667:
126 dev_priv->fsb_freq = 667; /* 167*4 */
127 break;
128 case CLKCFG_FSB_400:
129 dev_priv->fsb_freq = 400; /* 100*4 */
130 break;
131 }
132
133 switch (tmp & CLKCFG_MEM_MASK) {
134 case CLKCFG_MEM_533:
135 dev_priv->mem_freq = 533;
136 break;
137 case CLKCFG_MEM_667:
138 dev_priv->mem_freq = 667;
139 break;
140 case CLKCFG_MEM_800:
141 dev_priv->mem_freq = 800;
142 break;
143 }
144
145 /* detect pineview DDR3 setting */
146 tmp = I915_READ(CSHRDDR3CTL);
147 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
148}
149
150static void i915_ironlake_get_mem_freq(struct drm_device *dev)
151{
fac5e23e 152 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 153 u16 ddrpll, csipll;
154
155 ddrpll = I915_READ16(DDRMPLL1);
156 csipll = I915_READ16(CSIPLL0);
157
158 switch (ddrpll & 0xff) {
159 case 0xc:
160 dev_priv->mem_freq = 800;
161 break;
162 case 0x10:
163 dev_priv->mem_freq = 1066;
164 break;
165 case 0x14:
166 dev_priv->mem_freq = 1333;
167 break;
168 case 0x18:
169 dev_priv->mem_freq = 1600;
170 break;
171 default:
172 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
173 ddrpll & 0xff);
174 dev_priv->mem_freq = 0;
175 break;
176 }
177
20e4d407 178 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 179
180 switch (csipll & 0x3ff) {
181 case 0x00c:
182 dev_priv->fsb_freq = 3200;
183 break;
184 case 0x00e:
185 dev_priv->fsb_freq = 3733;
186 break;
187 case 0x010:
188 dev_priv->fsb_freq = 4266;
189 break;
190 case 0x012:
191 dev_priv->fsb_freq = 4800;
192 break;
193 case 0x014:
194 dev_priv->fsb_freq = 5333;
195 break;
196 case 0x016:
197 dev_priv->fsb_freq = 5866;
198 break;
199 case 0x018:
200 dev_priv->fsb_freq = 6400;
201 break;
202 default:
203 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
204 csipll & 0x3ff);
205 dev_priv->fsb_freq = 0;
206 break;
207 }
208
209 if (dev_priv->fsb_freq == 3200) {
20e4d407 210 dev_priv->ips.c_m = 0;
c921aba8 211 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 212 dev_priv->ips.c_m = 1;
c921aba8 213 } else {
20e4d407 214 dev_priv->ips.c_m = 2;
c921aba8
DV		 215 }
216}
217
b445e3b0
ED		 218static const struct cxsr_latency cxsr_latency_table[] = {
219 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
220 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
221 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
222 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
223 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
224
225 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
226 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
227 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
228 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
229 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
230
231 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
232 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
233 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
234 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
235 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
236
237 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
238 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
239 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
240 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
241 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
242
243 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
244 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
245 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
246 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
247 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
248
249 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
250 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
251 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
252 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
253 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
254};
255
44a655ca
TU		 256static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
257 bool is_ddr3,
b445e3b0
ED		 258 int fsb,
259 int mem)
260{
261 const struct cxsr_latency *latency;
262 int i;
263
264 if (fsb == 0 || mem == 0)
265 return NULL;
266
267 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
268 latency = &cxsr_latency_table[i];
269 if (is_desktop == latency->is_desktop &&
270 is_ddr3 == latency->is_ddr3 &&
271 fsb == latency->fsb_freq && mem == latency->mem_freq)
272 return latency;
273 }
274
275 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
276
277 return NULL;
278}
279
fc1ac8de
VS		 280static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
281{
282 u32 val;
283
284 mutex_lock(&dev_priv->rps.hw_lock);
285
286 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
287 if (enable)
288 val &= ~FORCE_DDR_HIGH_FREQ;
289 else
290 val |= FORCE_DDR_HIGH_FREQ;
291 val &= ~FORCE_DDR_LOW_FREQ;
292 val |= FORCE_DDR_FREQ_REQ_ACK;
293 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
294
295 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
296 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
297 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
298
299 mutex_unlock(&dev_priv->rps.hw_lock);
300}
301
cfb41411
VS		 302static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
303{
304 u32 val;
305
306 mutex_lock(&dev_priv->rps.hw_lock);
307
308 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
309 if (enable)
310 val |= DSP_MAXFIFO_PM5_ENABLE;
311 else
312 val &= ~DSP_MAXFIFO_PM5_ENABLE;
313 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
314
315 mutex_unlock(&dev_priv->rps.hw_lock);
316}
317
f4998963
VS		 318#define FW_WM(value, plane) \
319 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
320
5209b1f4 321void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 322{
91c8a326 323 struct drm_device *dev = &dev_priv->drm;
5209b1f4 324 u32 val;
b445e3b0 325
920a14b2 326 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 327 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 328 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 329 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 330 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 331 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 332 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 333 } else if (IS_PINEVIEW(dev)) {
334 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
335 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
336 I915_WRITE(DSPFW3, val);
a7a6c498 337 POSTING_READ(DSPFW3);
50a0bc90 338 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 339 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
340 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
341 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 342 POSTING_READ(FW_BLC_SELF);
50a0bc90 343 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 344 /*
345 * FIXME can't find a bit like this for 915G, and
346 * and yet it does have the related watermark in
347 * FW_BLC_SELF. What's going on?
348 */
5209b1f4
ID		 349 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
350 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
351 I915_WRITE(INSTPM, val);
a7a6c498 352 POSTING_READ(INSTPM);
5209b1f4
ID		 353 } else {
354 return;
355 }
b445e3b0 356
5209b1f4
ID		 357 DRM_DEBUG_KMS("memory self-refresh is %s\n",
358 enable ? "enabled" : "disabled");
b445e3b0
ED		 359}
360
fc1ac8de 361
b445e3b0
ED		 362/*
363 * Latency for FIFO fetches is dependent on several factors:
364 * - memory configuration (speed, channels)
365 * - chipset
366 * - current MCH state
367 * It can be fairly high in some situations, so here we assume a fairly
368 * pessimal value. It's a tradeoff between extra memory fetches (if we
369 * set this value too high, the FIFO will fetch frequently to stay full)
370 * and power consumption (set it too low to save power and we might see
371 * FIFO underruns and display "flicker").
372 *
373 * A value of 5us seems to be a good balance; safe for very low end
374 * platforms but not overly aggressive on lower latency configs.
375 */
5aef6003 376static const int pessimal_latency_ns = 5000;
b445e3b0 377
b5004720
VS		 378#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
379 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
380
381static int vlv_get_fifo_size(struct drm_device *dev,
382 enum pipe pipe, int plane)
383{
fac5e23e 384 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 385 int sprite0_start, sprite1_start, size;
386
387 switch (pipe) {
388 uint32_t dsparb, dsparb2, dsparb3;
389 case PIPE_A:
390 dsparb = I915_READ(DSPARB);
391 dsparb2 = I915_READ(DSPARB2);
392 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
393 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
394 break;
395 case PIPE_B:
396 dsparb = I915_READ(DSPARB);
397 dsparb2 = I915_READ(DSPARB2);
398 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
399 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
400 break;
401 case PIPE_C:
402 dsparb2 = I915_READ(DSPARB2);
403 dsparb3 = I915_READ(DSPARB3);
404 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
405 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
406 break;
407 default:
408 return 0;
409 }
410
411 switch (plane) {
412 case 0:
413 size = sprite0_start;
414 break;
415 case 1:
416 size = sprite1_start - sprite0_start;
417 break;
418 case 2:
419 size = 512 - 1 - sprite1_start;
420 break;
421 default:
422 return 0;
423 }
424
425 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
426 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
427 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
428 size);
429
430 return size;
431}
432
1fa61106 433static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 434{
fac5e23e 435 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 436 uint32_t dsparb = I915_READ(DSPARB);
437 int size;
438
439 size = dsparb & 0x7f;
440 if (plane)
441 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
442
443 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
444 plane ? "B" : "A", size);
445
446 return size;
447}
448
feb56b93 449static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 450{
fac5e23e 451 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 452 uint32_t dsparb = I915_READ(DSPARB);
453 int size;
454
455 size = dsparb & 0x1ff;
456 if (plane)
457 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
458 size >>= 1; /* Convert to cachelines */
459
460 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
461 plane ? "B" : "A", size);
462
463 return size;
464}
465
1fa61106 466static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 467{
fac5e23e 468 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 469 uint32_t dsparb = I915_READ(DSPARB);
470 int size;
471
472 size = dsparb & 0x7f;
473 size >>= 2; /* Convert to cachelines */
474
475 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
476 plane ? "B" : "A",
477 size);
478
479 return size;
480}
481
b445e3b0
ED		 482/* Pineview has different values for various configs */
483static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 484 .fifo_size = PINEVIEW_DISPLAY_FIFO,
485 .max_wm = PINEVIEW_MAX_WM,
486 .default_wm = PINEVIEW_DFT_WM,
487 .guard_size = PINEVIEW_GUARD_WM,
488 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 489};
490static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 491 .fifo_size = PINEVIEW_DISPLAY_FIFO,
492 .max_wm = PINEVIEW_MAX_WM,
493 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
494 .guard_size = PINEVIEW_GUARD_WM,
495 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 498 .fifo_size = PINEVIEW_CURSOR_FIFO,
499 .max_wm = PINEVIEW_CURSOR_MAX_WM,
500 .default_wm = PINEVIEW_CURSOR_DFT_WM,
501 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
502 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 505 .fifo_size = PINEVIEW_CURSOR_FIFO,
506 .max_wm = PINEVIEW_CURSOR_MAX_WM,
507 .default_wm = PINEVIEW_CURSOR_DFT_WM,
508 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
509 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 510};
511static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 512 .fifo_size = G4X_FIFO_SIZE,
513 .max_wm = G4X_MAX_WM,
514 .default_wm = G4X_MAX_WM,
515 .guard_size = 2,
516 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 517};
518static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 519 .fifo_size = I965_CURSOR_FIFO,
520 .max_wm = I965_CURSOR_MAX_WM,
521 .default_wm = I965_CURSOR_DFT_WM,
522 .guard_size = 2,
523 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 524};
b445e3b0 525static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 526 .fifo_size = I965_CURSOR_FIFO,
527 .max_wm = I965_CURSOR_MAX_WM,
528 .default_wm = I965_CURSOR_DFT_WM,
529 .guard_size = 2,
530 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 533 .fifo_size = I945_FIFO_SIZE,
534 .max_wm = I915_MAX_WM,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 538};
539static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 540 .fifo_size = I915_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 545};
9d539105 546static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 547 .fifo_size = I855GM_FIFO_SIZE,
548 .max_wm = I915_MAX_WM,
549 .default_wm = 1,
550 .guard_size = 2,
551 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 552};
9d539105
VS		 553static const struct intel_watermark_params i830_bc_wm_info = {
554 .fifo_size = I855GM_FIFO_SIZE,
555 .max_wm = I915_MAX_WM/2,
556 .default_wm = 1,
557 .guard_size = 2,
558 .cacheline_size = I830_FIFO_LINE_SIZE,
559};
feb56b93 560static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 561 .fifo_size = I830_FIFO_SIZE,
562 .max_wm = I915_MAX_WM,
563 .default_wm = 1,
564 .guard_size = 2,
565 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 566};
567
b445e3b0
ED		 568/**
569 * intel_calculate_wm - calculate watermark level
570 * @clock_in_khz: pixel clock
571 * @wm: chip FIFO params
ac484963 572 * @cpp: bytes per pixel
b445e3b0
ED		 573 * @latency_ns: memory latency for the platform
574 *
575 * Calculate the watermark level (the level at which the display plane will
576 * start fetching from memory again). Each chip has a different display
577 * FIFO size and allocation, so the caller needs to figure that out and pass
578 * in the correct intel_watermark_params structure.
579 *
580 * As the pixel clock runs, the FIFO will be drained at a rate that depends
581 * on the pixel size. When it reaches the watermark level, it'll start
582 * fetching FIFO line sized based chunks from memory until the FIFO fills
583 * past the watermark point. If the FIFO drains completely, a FIFO underrun
584 * will occur, and a display engine hang could result.
585 */
586static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
587 const struct intel_watermark_params *wm,
ac484963 588 int fifo_size, int cpp,
b445e3b0
ED		 589 unsigned long latency_ns)
590{
591 long entries_required, wm_size;
592
593 /*
594 * Note: we need to make sure we don't overflow for various clock &
595 * latency values.
596 * clocks go from a few thousand to several hundred thousand.
597 * latency is usually a few thousand
598 */
ac484963 599 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 600 1000;
601 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
602
603 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
604
605 wm_size = fifo_size - (entries_required + wm->guard_size);
606
607 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
608
609 /* Don't promote wm_size to unsigned... */
610 if (wm_size > (long)wm->max_wm)
611 wm_size = wm->max_wm;
612 if (wm_size <= 0)
613 wm_size = wm->default_wm;
d6feb196
VS		 614
615 /*
616 * Bspec seems to indicate that the value shouldn't be lower than
617 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
618 * Lets go for 8 which is the burst size since certain platforms
619 * already use a hardcoded 8 (which is what the spec says should be
620 * done).
621 */
622 if (wm_size <= 8)
623 wm_size = 8;
624
b445e3b0
ED		 625 return wm_size;
626}
627
628static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
629{
630 struct drm_crtc *crtc, *enabled = NULL;
631
70e1e0ec 632 for_each_crtc(dev, crtc) {
525b9311 633 if (intel_crtc_active(to_intel_crtc(crtc))) {
b445e3b0
ED		 634 if (enabled)
635 return NULL;
636 enabled = crtc;
637 }
638 }
639
640 return enabled;
641}
642
432081bc 643static void pineview_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 644{
432081bc 645 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 646 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 647 struct drm_crtc *crtc;
648 const struct cxsr_latency *latency;
649 u32 reg;
650 unsigned long wm;
651
50a0bc90
TU		 652 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
653 dev_priv->is_ddr3,
654 dev_priv->fsb_freq,
655 dev_priv->mem_freq);
b445e3b0
ED		 656 if (!latency) {
657 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 658 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 659 return;
660 }
661
662 crtc = single_enabled_crtc(dev);
663 if (crtc) {
7c5f93b0 664 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 665 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 666 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 667
668 /* Display SR */
669 wm = intel_calculate_wm(clock, &pineview_display_wm,
670 pineview_display_wm.fifo_size,
ac484963 671 cpp, latency->display_sr);
b445e3b0
ED		 672 reg = I915_READ(DSPFW1);
673 reg &= ~DSPFW_SR_MASK;
f4998963 674 reg |= FW_WM(wm, SR);
b445e3b0
ED		 675 I915_WRITE(DSPFW1, reg);
676 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
677
678 /* cursor SR */
679 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
680 pineview_display_wm.fifo_size,
ac484963 681 cpp, latency->cursor_sr);
b445e3b0
ED		 682 reg = I915_READ(DSPFW3);
683 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 684 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 685 I915_WRITE(DSPFW3, reg);
686
687 /* Display HPLL off SR */
688 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
689 pineview_display_hplloff_wm.fifo_size,
ac484963 690 cpp, latency->display_hpll_disable);
b445e3b0
ED		 691 reg = I915_READ(DSPFW3);
692 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 693 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 694 I915_WRITE(DSPFW3, reg);
695
696 /* cursor HPLL off SR */
697 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
698 pineview_display_hplloff_wm.fifo_size,
ac484963 699 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 700 reg = I915_READ(DSPFW3);
701 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 702 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 703 I915_WRITE(DSPFW3, reg);
704 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
705
5209b1f4 706 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 707 } else {
5209b1f4 708 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 709 }
710}
711
712static bool g4x_compute_wm0(struct drm_device *dev,
713 int plane,
714 const struct intel_watermark_params *display,
715 int display_latency_ns,
716 const struct intel_watermark_params *cursor,
717 int cursor_latency_ns,
718 int *plane_wm,
719 int *cursor_wm)
720{
721 struct drm_crtc *crtc;
4fe8590a 722 const struct drm_display_mode *adjusted_mode;
ac484963 723 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 724 int line_time_us, line_count;
725 int entries, tlb_miss;
726
727 crtc = intel_get_crtc_for_plane(dev, plane);
525b9311 728 if (!intel_crtc_active(to_intel_crtc(crtc))) {
b445e3b0
ED		 729 *cursor_wm = cursor->guard_size;
730 *plane_wm = display->guard_size;
731 return false;
732 }
733
6e3c9717 734 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 735 clock = adjusted_mode->crtc_clock;
fec8cba3 736 htotal = adjusted_mode->crtc_htotal;
6e3c9717 737 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 738 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 739
740 /* Use the small buffer method to calculate plane watermark */
ac484963 741 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 742 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
743 if (tlb_miss > 0)
744 entries += tlb_miss;
745 entries = DIV_ROUND_UP(entries, display->cacheline_size);
746 *plane_wm = entries + display->guard_size;
747 if (*plane_wm > (int)display->max_wm)
748 *plane_wm = display->max_wm;
749
750 /* Use the large buffer method to calculate cursor watermark */
922044c9 751 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 752 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 753 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 754 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
755 if (tlb_miss > 0)
756 entries += tlb_miss;
757 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
758 *cursor_wm = entries + cursor->guard_size;
759 if (*cursor_wm > (int)cursor->max_wm)
760 *cursor_wm = (int)cursor->max_wm;
761
762 return true;
763}
764
765/*
766 * Check the wm result.
767 *
768 * If any calculated watermark values is larger than the maximum value that
769 * can be programmed into the associated watermark register, that watermark
770 * must be disabled.
771 */
772static bool g4x_check_srwm(struct drm_device *dev,
773 int display_wm, int cursor_wm,
774 const struct intel_watermark_params *display,
775 const struct intel_watermark_params *cursor)
776{
777 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
778 display_wm, cursor_wm);
779
780 if (display_wm > display->max_wm) {
ae9400ca 781 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 782 display_wm, display->max_wm);
783 return false;
784 }
785
786 if (cursor_wm > cursor->max_wm) {
ae9400ca 787 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 788 cursor_wm, cursor->max_wm);
789 return false;
790 }
791
792 if (!(display_wm || cursor_wm)) {
793 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
794 return false;
795 }
796
797 return true;
798}
799
800static bool g4x_compute_srwm(struct drm_device *dev,
801 int plane,
802 int latency_ns,
803 const struct intel_watermark_params *display,
804 const struct intel_watermark_params *cursor,
805 int *display_wm, int *cursor_wm)
806{
807 struct drm_crtc *crtc;
4fe8590a 808 const struct drm_display_mode *adjusted_mode;
ac484963 809 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 810 unsigned long line_time_us;
811 int line_count, line_size;
812 int small, large;
813 int entries;
814
815 if (!latency_ns) {
816 *display_wm = *cursor_wm = 0;
817 return false;
818 }
819
820 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 821 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 822 clock = adjusted_mode->crtc_clock;
fec8cba3 823 htotal = adjusted_mode->crtc_htotal;
6e3c9717 824 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 825 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 826
922044c9 827 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 828 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 829 line_size = hdisplay * cpp;
b445e3b0
ED		 830
831 /* Use the minimum of the small and large buffer method for primary */
ac484963 832 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 833 large = line_count * line_size;
834
835 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
836 *display_wm = entries + display->guard_size;
837
838 /* calculate the self-refresh watermark for display cursor */
ac484963 839 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 840 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
841 *cursor_wm = entries + cursor->guard_size;
842
843 return g4x_check_srwm(dev,
844 *display_wm, *cursor_wm,
845 display, cursor);
846}
847
15665979
VS		 848#define FW_WM_VLV(value, plane) \
849 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
850
0018fda1
VS		 851static void vlv_write_wm_values(struct intel_crtc *crtc,
852 const struct vlv_wm_values *wm)
853{
854 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
855 enum pipe pipe = crtc->pipe;
856
857 I915_WRITE(VLV_DDL(pipe),
858 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
859 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
860 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
861 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
862
ae80152d 863 I915_WRITE(DSPFW1,
15665979
VS		 864 FW_WM(wm->sr.plane, SR) |
865 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
866 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
867 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 868 I915_WRITE(DSPFW2,
15665979
VS		 869 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
870 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
871 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 872 I915_WRITE(DSPFW3,
15665979 873 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 874
875 if (IS_CHERRYVIEW(dev_priv)) {
876 I915_WRITE(DSPFW7_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
878 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 879 I915_WRITE(DSPFW8_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
881 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 882 I915_WRITE(DSPFW9_CHV,
15665979
VS		 883 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
884 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 885 I915_WRITE(DSPHOWM,
15665979
VS		 886 FW_WM(wm->sr.plane >> 9, SR_HI) |
887 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
888 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
889 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
890 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
891 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
892 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
893 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
894 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
895 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 896 } else {
897 I915_WRITE(DSPFW7,
15665979
VS		 898 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
899 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 900 I915_WRITE(DSPHOWM,
15665979
VS		 901 FW_WM(wm->sr.plane >> 9, SR_HI) |
902 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
903 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
904 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
905 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
906 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
907 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 908 }
909
2cb389b7
VS		 910 /* zero (unused) WM1 watermarks */
911 I915_WRITE(DSPFW4, 0);
912 I915_WRITE(DSPFW5, 0);
913 I915_WRITE(DSPFW6, 0);
914 I915_WRITE(DSPHOWM1, 0);
915
ae80152d 916 POSTING_READ(DSPFW1);
0018fda1
VS		 917}
918
15665979
VS		 919#undef FW_WM_VLV
920
6eb1a681
VS		 921enum vlv_wm_level {
922 VLV_WM_LEVEL_PM2,
923 VLV_WM_LEVEL_PM5,
924 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 925};
926
262cd2e1
VS		 927/* latency must be in 0.1us units. */
928static unsigned int vlv_wm_method2(unsigned int pixel_rate,
929 unsigned int pipe_htotal,
930 unsigned int horiz_pixels,
ac484963 931 unsigned int cpp,
262cd2e1
VS		 932 unsigned int latency)
933{
934 unsigned int ret;
935
936 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 937 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 938 ret = DIV_ROUND_UP(ret, 64);
939
940 return ret;
941}
942
943static void vlv_setup_wm_latency(struct drm_device *dev)
944{
fac5e23e 945 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 946
947 /* all latencies in usec */
948 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
949
58590c14
VS		 950 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
951
262cd2e1
VS		 952 if (IS_CHERRYVIEW(dev_priv)) {
953 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
954 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 955
956 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 957 }
958}
959
960static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
961 struct intel_crtc *crtc,
962 const struct intel_plane_state *state,
963 int level)
964{
965 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 966 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 967
968 if (dev_priv->wm.pri_latency[level] == 0)
969 return USHRT_MAX;
970
936e71e3 971 if (!state->base.visible)
262cd2e1
VS		 972 return 0;
973
ac484963 974 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 975 clock = crtc->config->base.adjusted_mode.crtc_clock;
976 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
977 width = crtc->config->pipe_src_w;
978 if (WARN_ON(htotal == 0))
979 htotal = 1;
980
981 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
982 /*
983 * FIXME the formula gives values that are
984 * too big for the cursor FIFO, and hence we
985 * would never be able to use cursors. For
986 * now just hardcode the watermark.
987 */
988 wm = 63;
989 } else {
ac484963 990 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 991 dev_priv->wm.pri_latency[level] * 10);
992 }
993
994 return min_t(int, wm, USHRT_MAX);
995}
996
54f1b6e1
VS		 997static void vlv_compute_fifo(struct intel_crtc *crtc)
998{
999 struct drm_device *dev = crtc->base.dev;
1000 struct vlv_wm_state *wm_state = &crtc->wm_state;
1001 struct intel_plane *plane;
1002 unsigned int total_rate = 0;
1003 const int fifo_size = 512 - 1;
1004 int fifo_extra, fifo_left = fifo_size;
1005
1006 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1007 struct intel_plane_state *state =
1008 to_intel_plane_state(plane->base.state);
1009
1010 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1011 continue;
1012
936e71e3 1013 if (state->base.visible) {
54f1b6e1
VS		 1014 wm_state->num_active_planes++;
1015 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1016 }
1017 }
1018
1019 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020 struct intel_plane_state *state =
1021 to_intel_plane_state(plane->base.state);
1022 unsigned int rate;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1025 plane->wm.fifo_size = 63;
1026 continue;
1027 }
1028
936e71e3 1029 if (!state->base.visible) {
54f1b6e1
VS		 1030 plane->wm.fifo_size = 0;
1031 continue;
1032 }
1033
1034 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1035 plane->wm.fifo_size = fifo_size * rate / total_rate;
1036 fifo_left -= plane->wm.fifo_size;
1037 }
1038
1039 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1040
1041 /* spread the remainder evenly */
1042 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1043 int plane_extra;
1044
1045 if (fifo_left == 0)
1046 break;
1047
1048 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1049 continue;
1050
1051 /* give it all to the first plane if none are active */
1052 if (plane->wm.fifo_size == 0 &&
1053 wm_state->num_active_planes)
1054 continue;
1055
1056 plane_extra = min(fifo_extra, fifo_left);
1057 plane->wm.fifo_size += plane_extra;
1058 fifo_left -= plane_extra;
1059 }
1060
1061 WARN_ON(fifo_left != 0);
1062}
1063
262cd2e1
VS		 1064static void vlv_invert_wms(struct intel_crtc *crtc)
1065{
1066 struct vlv_wm_state *wm_state = &crtc->wm_state;
1067 int level;
1068
1069 for (level = 0; level < wm_state->num_levels; level++) {
1070 struct drm_device *dev = crtc->base.dev;
1071 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072 struct intel_plane *plane;
1073
1074 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1075 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1076
1077 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1078 switch (plane->base.type) {
1079 int sprite;
1080 case DRM_PLANE_TYPE_CURSOR:
1081 wm_state->wm[level].cursor = plane->wm.fifo_size -
1082 wm_state->wm[level].cursor;
1083 break;
1084 case DRM_PLANE_TYPE_PRIMARY:
1085 wm_state->wm[level].primary = plane->wm.fifo_size -
1086 wm_state->wm[level].primary;
1087 break;
1088 case DRM_PLANE_TYPE_OVERLAY:
1089 sprite = plane->plane;
1090 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1091 wm_state->wm[level].sprite[sprite];
1092 break;
1093 }
1094 }
1095 }
1096}
1097
26e1fe4f 1098static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1099{
1100 struct drm_device *dev = crtc->base.dev;
1101 struct vlv_wm_state *wm_state = &crtc->wm_state;
1102 struct intel_plane *plane;
1103 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1104 int level;
1105
1106 memset(wm_state, 0, sizeof(*wm_state));
1107
852eb00d 1108 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1109 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1110
1111 wm_state->num_active_planes = 0;
262cd2e1 1112
54f1b6e1 1113 vlv_compute_fifo(crtc);
262cd2e1
VS		 1114
1115 if (wm_state->num_active_planes != 1)
1116 wm_state->cxsr = false;
1117
1118 if (wm_state->cxsr) {
1119 for (level = 0; level < wm_state->num_levels; level++) {
1120 wm_state->sr[level].plane = sr_fifo_size;
1121 wm_state->sr[level].cursor = 63;
1122 }
1123 }
1124
1125 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1126 struct intel_plane_state *state =
1127 to_intel_plane_state(plane->base.state);
1128
936e71e3 1129 if (!state->base.visible)
262cd2e1
VS		 1130 continue;
1131
1132 /* normal watermarks */
1133 for (level = 0; level < wm_state->num_levels; level++) {
1134 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1135 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1136
1137 /* hack */
1138 if (WARN_ON(level == 0 && wm > max_wm))
1139 wm = max_wm;
1140
1141 if (wm > plane->wm.fifo_size)
1142 break;
1143
1144 switch (plane->base.type) {
1145 int sprite;
1146 case DRM_PLANE_TYPE_CURSOR:
1147 wm_state->wm[level].cursor = wm;
1148 break;
1149 case DRM_PLANE_TYPE_PRIMARY:
1150 wm_state->wm[level].primary = wm;
1151 break;
1152 case DRM_PLANE_TYPE_OVERLAY:
1153 sprite = plane->plane;
1154 wm_state->wm[level].sprite[sprite] = wm;
1155 break;
1156 }
1157 }
1158
1159 wm_state->num_levels = level;
1160
1161 if (!wm_state->cxsr)
1162 continue;
1163
1164 /* maxfifo watermarks */
1165 switch (plane->base.type) {
1166 int sprite, level;
1167 case DRM_PLANE_TYPE_CURSOR:
1168 for (level = 0; level < wm_state->num_levels; level++)
1169 wm_state->sr[level].cursor =
5a37ed0a 1170 wm_state->wm[level].cursor;
262cd2e1
VS		 1171 break;
1172 case DRM_PLANE_TYPE_PRIMARY:
1173 for (level = 0; level < wm_state->num_levels; level++)
1174 wm_state->sr[level].plane =
1175 min(wm_state->sr[level].plane,
1176 wm_state->wm[level].primary);
1177 break;
1178 case DRM_PLANE_TYPE_OVERLAY:
1179 sprite = plane->plane;
1180 for (level = 0; level < wm_state->num_levels; level++)
1181 wm_state->sr[level].plane =
1182 min(wm_state->sr[level].plane,
1183 wm_state->wm[level].sprite[sprite]);
1184 break;
1185 }
1186 }
1187
1188 /* clear any (partially) filled invalid levels */
58590c14 1189 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1190 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1191 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1192 }
1193
1194 vlv_invert_wms(crtc);
1195}
1196
54f1b6e1
VS		 1197#define VLV_FIFO(plane, value) \
1198 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1199
1200static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1201{
1202 struct drm_device *dev = crtc->base.dev;
1203 struct drm_i915_private *dev_priv = to_i915(dev);
1204 struct intel_plane *plane;
1205 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1206
1207 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1208 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1209 WARN_ON(plane->wm.fifo_size != 63);
1210 continue;
1211 }
1212
1213 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1214 sprite0_start = plane->wm.fifo_size;
1215 else if (plane->plane == 0)
1216 sprite1_start = sprite0_start + plane->wm.fifo_size;
1217 else
1218 fifo_size = sprite1_start + plane->wm.fifo_size;
1219 }
1220
1221 WARN_ON(fifo_size != 512 - 1);
1222
1223 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1224 pipe_name(crtc->pipe), sprite0_start,
1225 sprite1_start, fifo_size);
1226
1227 switch (crtc->pipe) {
1228 uint32_t dsparb, dsparb2, dsparb3;
1229 case PIPE_A:
1230 dsparb = I915_READ(DSPARB);
1231 dsparb2 = I915_READ(DSPARB2);
1232
1233 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1234 VLV_FIFO(SPRITEB, 0xff));
1235 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1236 VLV_FIFO(SPRITEB, sprite1_start));
1237
1238 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1239 VLV_FIFO(SPRITEB_HI, 0x1));
1240 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1241 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1242
1243 I915_WRITE(DSPARB, dsparb);
1244 I915_WRITE(DSPARB2, dsparb2);
1245 break;
1246 case PIPE_B:
1247 dsparb = I915_READ(DSPARB);
1248 dsparb2 = I915_READ(DSPARB2);
1249
1250 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1251 VLV_FIFO(SPRITED, 0xff));
1252 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1253 VLV_FIFO(SPRITED, sprite1_start));
1254
1255 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1256 VLV_FIFO(SPRITED_HI, 0xff));
1257 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1258 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1259
1260 I915_WRITE(DSPARB, dsparb);
1261 I915_WRITE(DSPARB2, dsparb2);
1262 break;
1263 case PIPE_C:
1264 dsparb3 = I915_READ(DSPARB3);
1265 dsparb2 = I915_READ(DSPARB2);
1266
1267 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1268 VLV_FIFO(SPRITEF, 0xff));
1269 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1270 VLV_FIFO(SPRITEF, sprite1_start));
1271
1272 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1273 VLV_FIFO(SPRITEF_HI, 0xff));
1274 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1275 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1276
1277 I915_WRITE(DSPARB3, dsparb3);
1278 I915_WRITE(DSPARB2, dsparb2);
1279 break;
1280 default:
1281 break;
1282 }
1283}
1284
1285#undef VLV_FIFO
1286
262cd2e1
VS		 1287static void vlv_merge_wm(struct drm_device *dev,
1288 struct vlv_wm_values *wm)
1289{
1290 struct intel_crtc *crtc;
1291 int num_active_crtcs = 0;
1292
58590c14 1293 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1294 wm->cxsr = true;
1295
1296 for_each_intel_crtc(dev, crtc) {
1297 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1298
1299 if (!crtc->active)
1300 continue;
1301
1302 if (!wm_state->cxsr)
1303 wm->cxsr = false;
1304
1305 num_active_crtcs++;
1306 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1307 }
1308
1309 if (num_active_crtcs != 1)
1310 wm->cxsr = false;
1311
6f9c784b
VS		 1312 if (num_active_crtcs > 1)
1313 wm->level = VLV_WM_LEVEL_PM2;
1314
262cd2e1
VS		 1315 for_each_intel_crtc(dev, crtc) {
1316 struct vlv_wm_state *wm_state = &crtc->wm_state;
1317 enum pipe pipe = crtc->pipe;
1318
1319 if (!crtc->active)
1320 continue;
1321
1322 wm->pipe[pipe] = wm_state->wm[wm->level];
1323 if (wm->cxsr)
1324 wm->sr = wm_state->sr[wm->level];
1325
1326 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1327 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1328 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1329 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1330 }
1331}
1332
432081bc 1333static void vlv_update_wm(struct intel_crtc *crtc)
262cd2e1 1334{
432081bc 1335 struct drm_device *dev = crtc->base.dev;
fac5e23e 1336 struct drm_i915_private *dev_priv = to_i915(dev);
432081bc 1337 enum pipe pipe = crtc->pipe;
262cd2e1
VS		 1338 struct vlv_wm_values wm = {};
1339
432081bc 1340 vlv_compute_wm(crtc);
262cd2e1
VS		 1341 vlv_merge_wm(dev, &wm);
1342
54f1b6e1
VS		 1343 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1344 /* FIXME should be part of crtc atomic commit */
432081bc 1345 vlv_pipe_set_fifo_size(crtc);
262cd2e1 1346 return;
54f1b6e1 1347 }
262cd2e1
VS		 1348
1349 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1350 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1351 chv_set_memory_dvfs(dev_priv, false);
1352
1353 if (wm.level < VLV_WM_LEVEL_PM5 &&
1354 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1355 chv_set_memory_pm5(dev_priv, false);
1356
852eb00d 1357 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1358 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1359
54f1b6e1 1360 /* FIXME should be part of crtc atomic commit */
432081bc 1361 vlv_pipe_set_fifo_size(crtc);
54f1b6e1 1362
432081bc 1363 vlv_write_wm_values(crtc, &wm);
262cd2e1
VS		 1364
1365 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1366 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1367 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1368 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1369 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1370
852eb00d 1371 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1372 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1373
1374 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1375 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1376 chv_set_memory_pm5(dev_priv, true);
1377
1378 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1379 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1380 chv_set_memory_dvfs(dev_priv, true);
1381
1382 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1383}
1384
ae80152d
VS		 1385#define single_plane_enabled(mask) is_power_of_2(mask)
1386
432081bc 1387static void g4x_update_wm(struct intel_crtc *crtc)
b445e3b0 1388{
432081bc 1389 struct drm_device *dev = crtc->base.dev;
b445e3b0 1390 static const int sr_latency_ns = 12000;
fac5e23e 1391 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1392 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1393 int plane_sr, cursor_sr;
1394 unsigned int enabled = 0;
9858425c 1395 bool cxsr_enabled;
b445e3b0 1396
51cea1f4 1397 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1398 &g4x_wm_info, pessimal_latency_ns,
1399 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1400 &planea_wm, &cursora_wm))
51cea1f4 1401 enabled |= 1 << PIPE_A;
b445e3b0 1402
51cea1f4 1403 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1404 &g4x_wm_info, pessimal_latency_ns,
1405 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1406 &planeb_wm, &cursorb_wm))
51cea1f4 1407 enabled |= 1 << PIPE_B;
b445e3b0 1408
b445e3b0
ED		 1409 if (single_plane_enabled(enabled) &&
1410 g4x_compute_srwm(dev, ffs(enabled) - 1,
1411 sr_latency_ns,
1412 &g4x_wm_info,
1413 &g4x_cursor_wm_info,
52bd02d8 1414 &plane_sr, &cursor_sr)) {
9858425c 1415 cxsr_enabled = true;
52bd02d8 1416 } else {
9858425c 1417 cxsr_enabled = false;
5209b1f4 1418 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1419 plane_sr = cursor_sr = 0;
1420 }
b445e3b0 1421
a5043453
VS		 1422 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1423 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1424 planea_wm, cursora_wm,
1425 planeb_wm, cursorb_wm,
1426 plane_sr, cursor_sr);
1427
1428 I915_WRITE(DSPFW1,
f4998963
VS		 1429 FW_WM(plane_sr, SR) |
1430 FW_WM(cursorb_wm, CURSORB) |
1431 FW_WM(planeb_wm, PLANEB) |
1432 FW_WM(planea_wm, PLANEA));
b445e3b0 1433 I915_WRITE(DSPFW2,
8c919b28 1434 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1435 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1436 /* HPLL off in SR has some issues on G4x... disable it */
1437 I915_WRITE(DSPFW3,
8c919b28 1438 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1439 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1440
1441 if (cxsr_enabled)
1442 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1443}
1444
432081bc 1445static void i965_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1446{
432081bc 1447 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1448 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1449 struct drm_crtc *crtc;
1450 int srwm = 1;
1451 int cursor_sr = 16;
9858425c 1452 bool cxsr_enabled;
b445e3b0
ED		 1453
1454 /* Calc sr entries for one plane configs */
1455 crtc = single_enabled_crtc(dev);
1456 if (crtc) {
1457 /* self-refresh has much higher latency */
1458 static const int sr_latency_ns = 12000;
124abe07 1459 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1460 int clock = adjusted_mode->crtc_clock;
fec8cba3 1461 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1462 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1463 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1464 unsigned long line_time_us;
1465 int entries;
1466
922044c9 1467 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1468
1469 /* Use ns/us then divide to preserve precision */
1470 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1471 cpp * hdisplay;
b445e3b0
ED		 1472 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1473 srwm = I965_FIFO_SIZE - entries;
1474 if (srwm < 0)
1475 srwm = 1;
1476 srwm &= 0x1ff;
1477 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1478 entries, srwm);
1479
1480 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1481 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1482 entries = DIV_ROUND_UP(entries,
1483 i965_cursor_wm_info.cacheline_size);
1484 cursor_sr = i965_cursor_wm_info.fifo_size -
1485 (entries + i965_cursor_wm_info.guard_size);
1486
1487 if (cursor_sr > i965_cursor_wm_info.max_wm)
1488 cursor_sr = i965_cursor_wm_info.max_wm;
1489
1490 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1491 "cursor %d\n", srwm, cursor_sr);
1492
9858425c 1493 cxsr_enabled = true;
b445e3b0 1494 } else {
9858425c 1495 cxsr_enabled = false;
b445e3b0 1496 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1497 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1498 }
1499
1500 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1501 srwm);
1502
1503 /* 965 has limitations... */
f4998963
VS		 1504 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1505 FW_WM(8, CURSORB) |
1506 FW_WM(8, PLANEB) |
1507 FW_WM(8, PLANEA));
1508 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1509 FW_WM(8, PLANEC_OLD));
b445e3b0 1510 /* update cursor SR watermark */
f4998963 1511 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1512
1513 if (cxsr_enabled)
1514 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1515}
1516
f4998963
VS		 1517#undef FW_WM
1518
432081bc 1519static void i9xx_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1520{
432081bc 1521 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1522 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1523 const struct intel_watermark_params *wm_info;
1524 uint32_t fwater_lo;
1525 uint32_t fwater_hi;
1526 int cwm, srwm = 1;
1527 int fifo_size;
1528 int planea_wm, planeb_wm;
1529 struct drm_crtc *crtc, *enabled = NULL;
1530
1531 if (IS_I945GM(dev))
1532 wm_info = &i945_wm_info;
5db94019 1533 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1534 wm_info = &i915_wm_info;
1535 else
9d539105 1536 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1539 crtc = intel_get_crtc_for_plane(dev, 0);
525b9311 1540 if (intel_crtc_active(to_intel_crtc(crtc))) {
241bfc38 1541 const struct drm_display_mode *adjusted_mode;
ac484963 1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1543 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1544 cpp = 4;
1545
6e3c9717 1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1547 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1548 wm_info, fifo_size, cpp,
5aef6003 1549 pessimal_latency_ns);
b445e3b0 1550 enabled = crtc;
9d539105 1551 } else {
b445e3b0 1552 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1553 if (planea_wm > (long)wm_info->max_wm)
1554 planea_wm = wm_info->max_wm;
1555 }
1556
5db94019 1557 if (IS_GEN2(dev_priv))
9d539105 1558 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1559
1560 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1561 crtc = intel_get_crtc_for_plane(dev, 1);
525b9311 1562 if (intel_crtc_active(to_intel_crtc(crtc))) {
241bfc38 1563 const struct drm_display_mode *adjusted_mode;
ac484963 1564 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1565 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1566 cpp = 4;
1567
6e3c9717 1568 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1569 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
5aef6003 1571 pessimal_latency_ns);
b445e3b0
ED		 1572 if (enabled == NULL)
1573 enabled = crtc;
1574 else
1575 enabled = NULL;
9d539105 1576 } else {
b445e3b0 1577 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1578 if (planeb_wm > (long)wm_info->max_wm)
1579 planeb_wm = wm_info->max_wm;
1580 }
b445e3b0
ED		 1581
1582 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1583
50a0bc90 1584 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1585 struct drm_i915_gem_object *obj;
2ab1bc9d 1586
59bea882 1587 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1588
1589 /* self-refresh seems busted with untiled */
3e510a8e 1590 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1591 enabled = NULL;
1592 }
1593
b445e3b0
ED		 1594 /*
1595 * Overlay gets an aggressive default since video jitter is bad.
1596 */
1597 cwm = 2;
1598
1599 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1600 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1601
1602 /* Calc sr entries for one plane configs */
1603 if (HAS_FW_BLC(dev) && enabled) {
1604 /* self-refresh has much higher latency */
1605 static const int sr_latency_ns = 6000;
124abe07 1606 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1607 int clock = adjusted_mode->crtc_clock;
fec8cba3 1608 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1609 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1610 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1611 unsigned long line_time_us;
1612 int entries;
1613
50a0bc90 1614 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056
VS		 1615 cpp = 4;
1616
922044c9 1617 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1621 cpp * hdisplay;
b445e3b0
ED		 1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
50a0bc90 1628 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1631 else
b445e3b0
ED		 1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
5209b1f4
ID		 1648 if (enabled)
1649 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1650}
1651
432081bc 1652static void i845_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1653{
432081bc 1654 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1655 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1656 struct drm_crtc *crtc;
241bfc38 1657 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1658 uint32_t fwater_lo;
1659 int planea_wm;
1660
1661 crtc = single_enabled_crtc(dev);
1662 if (crtc == NULL)
1663 return;
1664
6e3c9717 1665 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1666 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1667 &i845_wm_info,
b445e3b0 1668 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1669 4, pessimal_latency_ns);
b445e3b0
ED		 1670 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1671 fwater_lo |= (3<<8) | planea_wm;
1672
1673 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1674
1675 I915_WRITE(FW_BLC, fwater_lo);
1676}
1677
8cfb3407 1678uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1679{
fd4daa9c 1680 uint32_t pixel_rate;
801bcfff 1681
8cfb3407 1682 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1683
1684 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1685 * adjust the pixel_rate here. */
1686
8cfb3407 1687 if (pipe_config->pch_pfit.enabled) {
801bcfff 1688 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1689 uint32_t pfit_size = pipe_config->pch_pfit.size;
1690
1691 pipe_w = pipe_config->pipe_src_w;
1692 pipe_h = pipe_config->pipe_src_h;
801bcfff 1693
801bcfff
PZ		 1694 pfit_w = (pfit_size >> 16) & 0xFFFF;
1695 pfit_h = pfit_size & 0xFFFF;
1696 if (pipe_w < pfit_w)
1697 pipe_w = pfit_w;
1698 if (pipe_h < pfit_h)
1699 pipe_h = pfit_h;
1700
15126882
MR		 1701 if (WARN_ON(!pfit_w || !pfit_h))
1702 return pixel_rate;
1703
801bcfff
PZ		 1704 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1705 pfit_w * pfit_h);
1706 }
1707
1708 return pixel_rate;
1709}
1710
37126462 1711/* latency must be in 0.1us units. */
ac484963 1712static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1713{
1714 uint64_t ret;
1715
3312ba65
VS		 1716 if (WARN(latency == 0, "Latency value missing\n"))
1717 return UINT_MAX;
1718
ac484963 1719 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1720 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1721
1722 return ret;
1723}
1724
37126462 1725/* latency must be in 0.1us units. */
23297044 1726static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1727 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1728 uint32_t latency)
1729{
1730 uint32_t ret;
1731
3312ba65
VS		 1732 if (WARN(latency == 0, "Latency value missing\n"))
1733 return UINT_MAX;
15126882
MR		 1734 if (WARN_ON(!pipe_htotal))
1735 return UINT_MAX;
3312ba65 1736
801bcfff 1737 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1738 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1739 ret = DIV_ROUND_UP(ret, 64) + 2;
1740 return ret;
1741}
1742
23297044 1743static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1744 uint8_t cpp)
cca32e9a 1745{
15126882
MR		 1746 /*
1747 * Neither of these should be possible since this function shouldn't be
1748 * called if the CRTC is off or the plane is invisible. But let's be
1749 * extra paranoid to avoid a potential divide-by-zero if we screw up
1750 * elsewhere in the driver.
1751 */
ac484963 1752 if (WARN_ON(!cpp))
15126882
MR		 1753 return 0;
1754 if (WARN_ON(!horiz_pixels))
1755 return 0;
1756
ac484963 1757 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1758}
1759
820c1980 1760struct ilk_wm_maximums {
cca32e9a
PZ		 1761 uint16_t pri;
1762 uint16_t spr;
1763 uint16_t cur;
1764 uint16_t fbc;
1765};
1766
37126462
VS		 1767/*
1768 * For both WM_PIPE and WM_LP.
1769 * mem_value must be in 0.1us units.
1770 */
7221fc33 1771static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1772 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1773 uint32_t mem_value,
1774 bool is_lp)
801bcfff 1775{
ac484963
VS		 1776 int cpp = pstate->base.fb ?
1777 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1778 uint32_t method1, method2;
1779
936e71e3 1780 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1781 return 0;
1782
ac484963 1783 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1784
1785 if (!is_lp)
1786 return method1;
1787
7221fc33
MR		 1788 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1790 drm_rect_width(&pstate->base.dst),
ac484963 1791 cpp, mem_value);
cca32e9a
PZ		 1792
1793 return min(method1, method2);
801bcfff
PZ		 1794}
1795
37126462
VS		 1796/*
1797 * For both WM_PIPE and WM_LP.
1798 * mem_value must be in 0.1us units.
1799 */
7221fc33 1800static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1801 const struct intel_plane_state *pstate,
801bcfff
PZ		 1802 uint32_t mem_value)
1803{
ac484963
VS		 1804 int cpp = pstate->base.fb ?
1805 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1806 uint32_t method1, method2;
1807
936e71e3 1808 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1809 return 0;
1810
ac484963 1811 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1812 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1813 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1814 drm_rect_width(&pstate->base.dst),
ac484963 1815 cpp, mem_value);
801bcfff
PZ		 1816 return min(method1, method2);
1817}
1818
37126462
VS		 1819/*
1820 * For both WM_PIPE and WM_LP.
1821 * mem_value must be in 0.1us units.
1822 */
7221fc33 1823static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1824 const struct intel_plane_state *pstate,
801bcfff
PZ		 1825 uint32_t mem_value)
1826{
b2435692
MR		 1827 /*
1828 * We treat the cursor plane as always-on for the purposes of watermark
1829 * calculation. Until we have two-stage watermark programming merged,
1830 * this is necessary to avoid flickering.
1831 */
1832 int cpp = 4;
936e71e3 1833 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1834
b2435692 1835 if (!cstate->base.active)
801bcfff
PZ		 1836 return 0;
1837
7221fc33
MR		 1838 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1839 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1840 width, cpp, mem_value);
801bcfff
PZ		 1841}
1842
cca32e9a 1843/* Only for WM_LP. */
7221fc33 1844static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1845 const struct intel_plane_state *pstate,
1fda9882 1846 uint32_t pri_val)
cca32e9a 1847{
ac484963
VS		 1848 int cpp = pstate->base.fb ?
1849 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1850
936e71e3 1851 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1852 return 0;
1853
936e71e3 1854 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1855}
1856
158ae64f
VS		 1857static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1858{
416f4727
VS		 1859 if (INTEL_INFO(dev)->gen >= 8)
1860 return 3072;
1861 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1862 return 768;
1863 else
1864 return 512;
1865}
1866
4e975081
VS		 1867static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1868 int level, bool is_sprite)
1869{
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 /* BDW primary/sprite plane watermarks */
1872 return level == 0 ? 255 : 2047;
1873 else if (INTEL_INFO(dev)->gen >= 7)
1874 /* IVB/HSW primary/sprite plane watermarks */
1875 return level == 0 ? 127 : 1023;
1876 else if (!is_sprite)
1877 /* ILK/SNB primary plane watermarks */
1878 return level == 0 ? 127 : 511;
1879 else
1880 /* ILK/SNB sprite plane watermarks */
1881 return level == 0 ? 63 : 255;
1882}
1883
1884static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1885 int level)
1886{
1887 if (INTEL_INFO(dev)->gen >= 7)
1888 return level == 0 ? 63 : 255;
1889 else
1890 return level == 0 ? 31 : 63;
1891}
1892
1893static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1894{
1895 if (INTEL_INFO(dev)->gen >= 8)
1896 return 31;
1897 else
1898 return 15;
1899}
1900
158ae64f
VS		 1901/* Calculate the maximum primary/sprite plane watermark */
1902static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1903 int level,
240264f4 1904 const struct intel_wm_config *config,
158ae64f
VS		 1905 enum intel_ddb_partitioning ddb_partitioning,
1906 bool is_sprite)
1907{
1908 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1909
1910 /* if sprites aren't enabled, sprites get nothing */
240264f4 1911 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1912 return 0;
1913
1914 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1915 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1916 fifo_size /= INTEL_INFO(dev)->num_pipes;
1917
1918 /*
1919 * For some reason the non self refresh
1920 * FIFO size is only half of the self
1921 * refresh FIFO size on ILK/SNB.
1922 */
1923 if (INTEL_INFO(dev)->gen <= 6)
1924 fifo_size /= 2;
1925 }
1926
240264f4 1927 if (config->sprites_enabled) {
158ae64f
VS		 1928 /* level 0 is always calculated with 1:1 split */
1929 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1930 if (is_sprite)
1931 fifo_size *= 5;
1932 fifo_size /= 6;
1933 } else {
1934 fifo_size /= 2;
1935 }
1936 }
1937
1938 /* clamp to max that the registers can hold */
4e975081 1939 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1940}
1941
1942/* Calculate the maximum cursor plane watermark */
1943static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1944 int level,
1945 const struct intel_wm_config *config)
158ae64f
VS		 1946{
1947 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1948 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1949 return 64;
1950
1951 /* otherwise just report max that registers can hold */
4e975081 1952 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1953}
1954
d34ff9c6 1955static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1956 int level,
1957 const struct intel_wm_config *config,
1958 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1959 struct ilk_wm_maximums *max)
158ae64f 1960{
240264f4
VS		 1961 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1962 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1963 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1964 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1965}
1966
a3cb4048
VS		 1967static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1968 int level,
1969 struct ilk_wm_maximums *max)
1970{
1971 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1972 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1973 max->cur = ilk_cursor_wm_reg_max(dev, level);
1974 max->fbc = ilk_fbc_wm_reg_max(dev);
1975}
1976
d9395655 1977static bool ilk_validate_wm_level(int level,
820c1980 1978 const struct ilk_wm_maximums *max,
d9395655 1979 struct intel_wm_level *result)
a9786a11
VS		 1980{
1981 bool ret;
1982
1983 /* already determined to be invalid? */
1984 if (!result->enable)
1985 return false;
1986
1987 result->enable = result->pri_val <= max->pri &&
1988 result->spr_val <= max->spr &&
1989 result->cur_val <= max->cur;
1990
1991 ret = result->enable;
1992
1993 /*
1994 * HACK until we can pre-compute everything,
1995 * and thus fail gracefully if LP0 watermarks
1996 * are exceeded...
1997 */
1998 if (level == 0 && !result->enable) {
1999 if (result->pri_val > max->pri)
2000 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2001 level, result->pri_val, max->pri);
2002 if (result->spr_val > max->spr)
2003 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2004 level, result->spr_val, max->spr);
2005 if (result->cur_val > max->cur)
2006 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2007 level, result->cur_val, max->cur);
2008
2009 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2010 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2011 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2012 result->enable = true;
2013 }
2014
a9786a11
VS		 2015 return ret;
2016}
2017
d34ff9c6 2018static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2019 const struct intel_crtc *intel_crtc,
6f5ddd17 2020 int level,
7221fc33 2021 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2022 struct intel_plane_state *pristate,
2023 struct intel_plane_state *sprstate,
2024 struct intel_plane_state *curstate,
1fd527cc 2025 struct intel_wm_level *result)
6f5ddd17
VS		 2026{
2027 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2028 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2029 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2030
2031 /* WM1+ latency values stored in 0.5us units */
2032 if (level > 0) {
2033 pri_latency *= 5;
2034 spr_latency *= 5;
2035 cur_latency *= 5;
2036 }
2037
e3bddded
ML		 2038 if (pristate) {
2039 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2040 pri_latency, level);
2041 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2042 }
2043
2044 if (sprstate)
2045 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2046
2047 if (curstate)
2048 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2049
6f5ddd17
VS		 2050 result->enable = true;
2051}
2052
801bcfff 2053static uint32_t
532f7a7f 2054hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2055{
532f7a7f
VS		 2056 const struct intel_atomic_state *intel_state =
2057 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2058 const struct drm_display_mode *adjusted_mode =
2059 &cstate->base.adjusted_mode;
85a02deb 2060 u32 linetime, ips_linetime;
1f8eeabf 2061
ee91a159
MR		 2062 if (!cstate->base.active)
2063 return 0;
2064 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2065 return 0;
532f7a7f 2066 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2067 return 0;
1011d8c4 2068
1f8eeabf
ED		 2069 /* The WM are computed with base on how long it takes to fill a single
2070 * row at the given clock rate, multiplied by 8.
2071 * */
124abe07
VS		 2072 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073 adjusted_mode->crtc_clock);
2074 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2075 intel_state->cdclk);
1f8eeabf 2076
801bcfff
PZ		 2077 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2078 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2079}
2080
2af30a5c 2081static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2082{
fac5e23e 2083 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2084
5db94019 2085 if (IS_GEN9(dev_priv)) {
2af30a5c 2086 uint32_t val;
4f947386 2087 int ret, i;
5db94019 2088 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2089
2090 /* read the first set of memory latencies[0:3] */
2091 val = 0; /* data0 to be programmed to 0 for first set */
2092 mutex_lock(&dev_priv->rps.hw_lock);
2093 ret = sandybridge_pcode_read(dev_priv,
2094 GEN9_PCODE_READ_MEM_LATENCY,
2095 &val);
2096 mutex_unlock(&dev_priv->rps.hw_lock);
2097
2098 if (ret) {
2099 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2100 return;
2101 }
2102
2103 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2109 GEN9_MEM_LATENCY_LEVEL_MASK;
2110
2111 /* read the second set of memory latencies[4:7] */
2112 val = 1; /* data0 to be programmed to 1 for second set */
2113 mutex_lock(&dev_priv->rps.hw_lock);
2114 ret = sandybridge_pcode_read(dev_priv,
2115 GEN9_PCODE_READ_MEM_LATENCY,
2116 &val);
2117 mutex_unlock(&dev_priv->rps.hw_lock);
2118 if (ret) {
2119 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120 return;
2121 }
2122
2123 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
0727e40a
PZ		 2131 /*
2132 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2133 * need to be disabled. We make sure to sanitize the values out
2134 * of the punit to satisfy this requirement.
2135 */
2136 for (level = 1; level <= max_level; level++) {
2137 if (wm[level] == 0) {
2138 for (i = level + 1; i <= max_level; i++)
2139 wm[i] = 0;
2140 break;
2141 }
2142 }
2143
367294be 2144 /*
6f97235b
DL		 2145 * WaWmMemoryReadLatency:skl
2146 *
367294be 2147 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2148 * to add 2us to the various latency levels we retrieve from the
2149 * punit when level 0 response data us 0us.
367294be 2150 */
0727e40a
PZ		 2151 if (wm[0] == 0) {
2152 wm[0] += 2;
2153 for (level = 1; level <= max_level; level++) {
2154 if (wm[level] == 0)
2155 break;
367294be 2156 wm[level] += 2;
4f947386 2157 }
0727e40a
PZ		 2158 }
2159
8652744b 2160 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2161 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2162
2163 wm[0] = (sskpd >> 56) & 0xFF;
2164 if (wm[0] == 0)
2165 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2166 wm[1] = (sskpd >> 4) & 0xFF;
2167 wm[2] = (sskpd >> 12) & 0xFF;
2168 wm[3] = (sskpd >> 20) & 0x1FF;
2169 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2170 } else if (INTEL_INFO(dev)->gen >= 6) {
2171 uint32_t sskpd = I915_READ(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2174 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2175 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2176 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2177 } else if (INTEL_INFO(dev)->gen >= 5) {
2178 uint32_t mltr = I915_READ(MLTR_ILK);
2179
2180 /* ILK primary LP0 latency is 700 ns */
2181 wm[0] = 7;
2182 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2183 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2184 }
2185}
2186
5db94019
TU		 2187static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2188 uint16_t wm[5])
53615a5e
VS		 2189{
2190 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2191 if (IS_GEN5(dev_priv))
53615a5e
VS		 2192 wm[0] = 13;
2193}
2194
fd6b8f43
TU		 2195static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2196 uint16_t wm[5])
53615a5e
VS		 2197{
2198 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2199 if (IS_GEN5(dev_priv))
53615a5e
VS		 2200 wm[0] = 13;
2201
2202 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2203 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2204 wm[3] *= 2;
2205}
2206
5db94019 2207int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2208{
26ec971e 2209 /* how many WM levels are we expecting */
8652744b 2210 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2211 return 7;
8652744b 2212 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2213 return 4;
8652744b 2214 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2215 return 3;
26ec971e 2216 else
ad0d6dc4
VS		 2217 return 2;
2218}
7526ed79 2219
5db94019 2220static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2221 const char *name,
2af30a5c 2222 const uint16_t wm[8])
ad0d6dc4 2223{
5db94019 2224 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2225
2226 for (level = 0; level <= max_level; level++) {
2227 unsigned int latency = wm[level];
2228
2229 if (latency == 0) {
2230 DRM_ERROR("%s WM%d latency not provided\n",
2231 name, level);
2232 continue;
2233 }
2234
2af30a5c
PB		 2235 /*
2236 * - latencies are in us on gen9.
2237 * - before then, WM1+ latency values are in 0.5us units
2238 */
5db94019 2239 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2240 latency *= 10;
2241 else if (level > 0)
26ec971e
VS		 2242 latency *= 5;
2243
2244 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2245 name, level, wm[level],
2246 latency / 10, latency % 10);
2247 }
2248}
2249
e95a2f75
VS		 2250static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2251 uint16_t wm[5], uint16_t min)
2252{
5db94019 2253 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2254
2255 if (wm[0] >= min)
2256 return false;
2257
2258 wm[0] = max(wm[0], min);
2259 for (level = 1; level <= max_level; level++)
2260 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2261
2262 return true;
2263}
2264
2265static void snb_wm_latency_quirk(struct drm_device *dev)
2266{
fac5e23e 2267 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2268 bool changed;
2269
2270 /*
2271 * The BIOS provided WM memory latency values are often
2272 * inadequate for high resolution displays. Adjust them.
2273 */
2274 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2275 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2276 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2277
2278 if (!changed)
2279 return;
2280
2281 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2282 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2283 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2284 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2285}
2286
fa50ad61 2287static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2288{
fac5e23e 2289 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2290
2291 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2292
2293 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2294 sizeof(dev_priv->wm.pri_latency));
2295 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2296 sizeof(dev_priv->wm.pri_latency));
2297
5db94019 2298 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2299 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2300
5db94019
TU		 2301 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2302 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2303 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2304
5db94019 2305 if (IS_GEN6(dev_priv))
e95a2f75 2306 snb_wm_latency_quirk(dev);
53615a5e
VS		 2307}
2308
2af30a5c
PB		 2309static void skl_setup_wm_latency(struct drm_device *dev)
2310{
fac5e23e 2311 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2312
2313 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
5db94019 2314 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2315}
2316
ed4a6a7c
MR		 2317static bool ilk_validate_pipe_wm(struct drm_device *dev,
2318 struct intel_pipe_wm *pipe_wm)
2319{
2320 /* LP0 watermark maximums depend on this pipe alone */
2321 const struct intel_wm_config config = {
2322 .num_pipes_active = 1,
2323 .sprites_enabled = pipe_wm->sprites_enabled,
2324 .sprites_scaled = pipe_wm->sprites_scaled,
2325 };
2326 struct ilk_wm_maximums max;
2327
2328 /* LP0 watermarks always use 1/2 DDB partitioning */
2329 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2330
2331 /* At least LP0 must be valid */
2332 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2333 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2334 return false;
2335 }
2336
2337 return true;
2338}
2339
0b2ae6d7 2340/* Compute new watermarks for the pipe */
e3bddded 2341static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2342{
e3bddded
ML		 2343 struct drm_atomic_state *state = cstate->base.state;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2345 struct intel_pipe_wm *pipe_wm;
e3bddded 2346 struct drm_device *dev = state->dev;
fac5e23e 2347 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2348 struct intel_plane *intel_plane;
86c8bbbe 2349 struct intel_plane_state *pristate = NULL;
43d59eda 2350 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2351 struct intel_plane_state *curstate = NULL;
5db94019 2352 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2353 struct ilk_wm_maximums max;
0b2ae6d7 2354
e8f1f02e 2355 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2356
43d59eda 2357 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2358 struct intel_plane_state *ps;
2359
2360 ps = intel_atomic_get_existing_plane_state(state,
2361 intel_plane);
2362 if (!ps)
2363 continue;
86c8bbbe
MR		 2364
2365 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2366 pristate = ps;
86c8bbbe 2367 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2368 sprstate = ps;
86c8bbbe 2369 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2370 curstate = ps;
43d59eda
MR		 2371 }
2372
ed4a6a7c 2373 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2374 if (sprstate) {
936e71e3
VS		 2375 pipe_wm->sprites_enabled = sprstate->base.visible;
2376 pipe_wm->sprites_scaled = sprstate->base.visible &&
2377 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2378 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2379 }
2380
d81f04c5
ML		 2381 usable_level = max_level;
2382
7b39a0b7 2383 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2384 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2385 usable_level = 1;
7b39a0b7
VS		 2386
2387 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2388 if (pipe_wm->sprites_scaled)
d81f04c5 2389 usable_level = 0;
7b39a0b7 2390
86c8bbbe 2391 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2392 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2393
2394 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2395 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2396
8652744b 2397 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2398 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2399
ed4a6a7c 2400 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2401 return -EINVAL;
a3cb4048
VS		 2402
2403 ilk_compute_wm_reg_maximums(dev, 1, &max);
2404
2405 for (level = 1; level <= max_level; level++) {
71f0a626 2406 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2407
86c8bbbe 2408 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2409 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2410
2411 /*
2412 * Disable any watermark level that exceeds the
2413 * register maximums since such watermarks are
2414 * always invalid.
2415 */
71f0a626
ML		 2416 if (level > usable_level)
2417 continue;
2418
2419 if (ilk_validate_wm_level(level, &max, wm))
2420 pipe_wm->wm[level] = *wm;
2421 else
d81f04c5 2422 usable_level = level;
a3cb4048
VS		 2423 }
2424
86c8bbbe 2425 return 0;
0b2ae6d7
VS		 2426}
2427
ed4a6a7c
MR		 2428/*
2429 * Build a set of 'intermediate' watermark values that satisfy both the old
2430 * state and the new state. These can be programmed to the hardware
2431 * immediately.
2432 */
2433static int ilk_compute_intermediate_wm(struct drm_device *dev,
2434 struct intel_crtc *intel_crtc,
2435 struct intel_crtc_state *newstate)
2436{
e8f1f02e 2437 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2438 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2439 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2440
2441 /*
2442 * Start with the final, target watermarks, then combine with the
2443 * currently active watermarks to get values that are safe both before
2444 * and after the vblank.
2445 */
e8f1f02e 2446 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2447 a->pipe_enabled |= b->pipe_enabled;
2448 a->sprites_enabled |= b->sprites_enabled;
2449 a->sprites_scaled |= b->sprites_scaled;
2450
2451 for (level = 0; level <= max_level; level++) {
2452 struct intel_wm_level *a_wm = &a->wm[level];
2453 const struct intel_wm_level *b_wm = &b->wm[level];
2454
2455 a_wm->enable &= b_wm->enable;
2456 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2457 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2458 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2459 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2460 }
2461
2462 /*
2463 * We need to make sure that these merged watermark values are
2464 * actually a valid configuration themselves. If they're not,
2465 * there's no safe way to transition from the old state to
2466 * the new state, so we need to fail the atomic transaction.
2467 */
2468 if (!ilk_validate_pipe_wm(dev, a))
2469 return -EINVAL;
2470
2471 /*
2472 * If our intermediate WM are identical to the final WM, then we can
2473 * omit the post-vblank programming; only update if it's different.
2474 */
e8f1f02e 2475 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2476 newstate->wm.need_postvbl_update = false;
2477
2478 return 0;
2479}
2480
0b2ae6d7
VS		 2481/*
2482 * Merge the watermarks from all active pipes for a specific level.
2483 */
2484static void ilk_merge_wm_level(struct drm_device *dev,
2485 int level,
2486 struct intel_wm_level *ret_wm)
2487{
2488 const struct intel_crtc *intel_crtc;
2489
d52fea5b
VS		 2490 ret_wm->enable = true;
2491
d3fcc808 2492 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2493 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2494 const struct intel_wm_level *wm = &active->wm[level];
2495
2496 if (!active->pipe_enabled)
2497 continue;
0b2ae6d7 2498
d52fea5b
VS		 2499 /*
2500 * The watermark values may have been used in the past,
2501 * so we must maintain them in the registers for some
2502 * time even if the level is now disabled.
2503 */
0b2ae6d7 2504 if (!wm->enable)
d52fea5b 2505 ret_wm->enable = false;
0b2ae6d7
VS		 2506
2507 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2508 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2509 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2510 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2511 }
0b2ae6d7
VS		 2512}
2513
2514/*
2515 * Merge all low power watermarks for all active pipes.
2516 */
2517static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2518 const struct intel_wm_config *config,
820c1980 2519 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2520 struct intel_pipe_wm *merged)
2521{
fac5e23e 2522 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2523 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2524 int last_enabled_level = max_level;
0b2ae6d7 2525
0ba22e26 2526 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2527 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2528 config->num_pipes_active > 1)
1204d5ba 2529 last_enabled_level = 0;
0ba22e26 2530
6c8b6c28
VS		 2531 /* ILK: FBC WM must be disabled always */
2532 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2533
2534 /* merge each WM1+ level */
2535 for (level = 1; level <= max_level; level++) {
2536 struct intel_wm_level *wm = &merged->wm[level];
2537
2538 ilk_merge_wm_level(dev, level, wm);
2539
d52fea5b
VS		 2540 if (level > last_enabled_level)
2541 wm->enable = false;
2542 else if (!ilk_validate_wm_level(level, max, wm))
2543 /* make sure all following levels get disabled */
2544 last_enabled_level = level - 1;
0b2ae6d7
VS		 2545
2546 /*
2547 * The spec says it is preferred to disable
2548 * FBC WMs instead of disabling a WM level.
2549 */
2550 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2551 if (wm->enable)
2552 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2553 wm->fbc_val = 0;
2554 }
2555 }
6c8b6c28
VS		 2556
2557 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2558 /*
2559 * FIXME this is racy. FBC might get enabled later.
2560 * What we should check here is whether FBC can be
2561 * enabled sometime later.
2562 */
5db94019 2563 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2564 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2565 for (level = 2; level <= max_level; level++) {
2566 struct intel_wm_level *wm = &merged->wm[level];
2567
2568 wm->enable = false;
2569 }
2570 }
0b2ae6d7
VS		 2571}
2572
b380ca3c
VS		 2573static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2574{
2575 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2576 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2577}
2578
a68d68ee
VS		 2579/* The value we need to program into the WM_LPx latency field */
2580static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2581{
fac5e23e 2582 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2583
8652744b 2584 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2585 return 2 * level;
2586 else
2587 return dev_priv->wm.pri_latency[level];
2588}
2589
820c1980 2590static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2591 const struct intel_pipe_wm *merged,
609cedef 2592 enum intel_ddb_partitioning partitioning,
820c1980 2593 struct ilk_wm_values *results)
801bcfff 2594{
0b2ae6d7
VS		 2595 struct intel_crtc *intel_crtc;
2596 int level, wm_lp;
cca32e9a 2597
0362c781 2598 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2599 results->partitioning = partitioning;
cca32e9a 2600
0b2ae6d7 2601 /* LP1+ register values */
cca32e9a 2602 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2603 const struct intel_wm_level *r;
801bcfff 2604
b380ca3c 2605 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2606
0362c781 2607 r = &merged->wm[level];
cca32e9a 2608
d52fea5b
VS		 2609 /*
2610 * Maintain the watermark values even if the level is
2611 * disabled. Doing otherwise could cause underruns.
2612 */
2613 results->wm_lp[wm_lp - 1] =
a68d68ee 2614 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2615 (r->pri_val << WM1_LP_SR_SHIFT) |
2616 r->cur_val;
2617
d52fea5b
VS		 2618 if (r->enable)
2619 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2620
416f4727
VS		 2621 if (INTEL_INFO(dev)->gen >= 8)
2622 results->wm_lp[wm_lp - 1] |=
2623 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2624 else
2625 results->wm_lp[wm_lp - 1] |=
2626 r->fbc_val << WM1_LP_FBC_SHIFT;
2627
d52fea5b
VS		 2628 /*
2629 * Always set WM1S_LP_EN when spr_val != 0, even if the
2630 * level is disabled. Doing otherwise could cause underruns.
2631 */
6cef2b8a
VS		 2632 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2633 WARN_ON(wm_lp != 1);
2634 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2635 } else
2636 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2637 }
801bcfff 2638
0b2ae6d7 2639 /* LP0 register values */
d3fcc808 2640 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2641 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2642 const struct intel_wm_level *r =
2643 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2644
2645 if (WARN_ON(!r->enable))
2646 continue;
2647
ed4a6a7c 2648 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2649
0b2ae6d7
VS		 2650 results->wm_pipe[pipe] =
2651 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2652 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2653 r->cur_val;
801bcfff
PZ		 2654 }
2655}
2656
861f3389
PZ		 2657/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2658 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2659static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2660 struct intel_pipe_wm *r1,
2661 struct intel_pipe_wm *r2)
861f3389 2662{
5db94019 2663 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2664 int level1 = 0, level2 = 0;
861f3389 2665
198a1e9b
VS		 2666 for (level = 1; level <= max_level; level++) {
2667 if (r1->wm[level].enable)
2668 level1 = level;
2669 if (r2->wm[level].enable)
2670 level2 = level;
861f3389
PZ		 2671 }
2672
198a1e9b
VS		 2673 if (level1 == level2) {
2674 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2675 return r2;
2676 else
2677 return r1;
198a1e9b 2678 } else if (level1 > level2) {
861f3389
PZ		 2679 return r1;
2680 } else {
2681 return r2;
2682 }
2683}
2684
49a687c4
VS		 2685/* dirty bits used to track which watermarks need changes */
2686#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2687#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2688#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2689#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2690#define WM_DIRTY_FBC (1 << 24)
2691#define WM_DIRTY_DDB (1 << 25)
2692
055e393f 2693static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2694 const struct ilk_wm_values *old,
2695 const struct ilk_wm_values *new)
49a687c4
VS		 2696{
2697 unsigned int dirty = 0;
2698 enum pipe pipe;
2699 int wm_lp;
2700
055e393f 2701 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2702 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2703 dirty |= WM_DIRTY_LINETIME(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707
2708 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2709 dirty |= WM_DIRTY_PIPE(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713 }
2714
2715 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2716 dirty |= WM_DIRTY_FBC;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 if (old->partitioning != new->partitioning) {
2722 dirty |= WM_DIRTY_DDB;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 /* LP1+ watermarks already deemed dirty, no need to continue */
2728 if (dirty & WM_DIRTY_LP_ALL)
2729 return dirty;
2730
2731 /* Find the lowest numbered LP1+ watermark in need of an update... */
2732 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2734 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2735 break;
2736 }
2737
2738 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2739 for (; wm_lp <= 3; wm_lp++)
2740 dirty |= WM_DIRTY_LP(wm_lp);
2741
2742 return dirty;
2743}
2744
8553c18e
VS		 2745static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2746 unsigned int dirty)
801bcfff 2747{
820c1980 2748 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2749 bool changed = false;
801bcfff 2750
facd619b
VS		 2751 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2752 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2753 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2754 changed = true;
facd619b
VS		 2755 }
2756 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2757 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2758 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2759 changed = true;
facd619b
VS		 2760 }
2761 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2762 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2763 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2764 changed = true;
facd619b 2765 }
801bcfff 2766
facd619b
VS		 2767 /*
2768 * Don't touch WM1S_LP_EN here.
2769 * Doing so could cause underruns.
2770 */
6cef2b8a 2771
8553c18e
VS		 2772 return changed;
2773}
2774
2775/*
2776 * The spec says we shouldn't write when we don't need, because every write
2777 * causes WMs to be re-evaluated, expending some power.
2778 */
820c1980
ID		 2779static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2780 struct ilk_wm_values *results)
8553c18e 2781{
91c8a326 2782 struct drm_device *dev = &dev_priv->drm;
820c1980 2783 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2784 unsigned int dirty;
2785 uint32_t val;
2786
055e393f 2787 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2788 if (!dirty)
2789 return;
2790
2791 _ilk_disable_lp_wm(dev_priv, dirty);
2792
49a687c4 2793 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2794 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2795 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2796 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2797 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2798 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2799
49a687c4 2800 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2801 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2802 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2803 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2804 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2805 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2806
49a687c4 2807 if (dirty & WM_DIRTY_DDB) {
8652744b 2808 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2809 val = I915_READ(WM_MISC);
2810 if (results->partitioning == INTEL_DDB_PART_1_2)
2811 val &= ~WM_MISC_DATA_PARTITION_5_6;
2812 else
2813 val |= WM_MISC_DATA_PARTITION_5_6;
2814 I915_WRITE(WM_MISC, val);
2815 } else {
2816 val = I915_READ(DISP_ARB_CTL2);
2817 if (results->partitioning == INTEL_DDB_PART_1_2)
2818 val &= ~DISP_DATA_PARTITION_5_6;
2819 else
2820 val |= DISP_DATA_PARTITION_5_6;
2821 I915_WRITE(DISP_ARB_CTL2, val);
2822 }
1011d8c4
PZ		 2823 }
2824
49a687c4 2825 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2826 val = I915_READ(DISP_ARB_CTL);
2827 if (results->enable_fbc_wm)
2828 val &= ~DISP_FBC_WM_DIS;
2829 else
2830 val |= DISP_FBC_WM_DIS;
2831 I915_WRITE(DISP_ARB_CTL, val);
2832 }
2833
954911eb
ID		 2834 if (dirty & WM_DIRTY_LP(1) &&
2835 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2836 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2837
2838 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2839 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2840 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2841 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2842 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2843 }
801bcfff 2844
facd619b 2845 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2846 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2847 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2848 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2849 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2850 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2851
2852 dev_priv->wm.hw = *results;
801bcfff
PZ		 2853}
2854
ed4a6a7c 2855bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2856{
fac5e23e 2857 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2858
2859 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2860}
2861
656d1b89 2862#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2863
024c9045
MR		 2864/*
2865 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2866 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2867 * other universal planes are in indices 1..n. Note that this may leave unused
2868 * indices between the top "sprite" plane and the cursor.
2869 */
2870static int
2871skl_wm_plane_id(const struct intel_plane *plane)
2872{
2873 switch (plane->base.type) {
2874 case DRM_PLANE_TYPE_PRIMARY:
2875 return 0;
2876 case DRM_PLANE_TYPE_CURSOR:
2877 return PLANE_CURSOR;
2878 case DRM_PLANE_TYPE_OVERLAY:
2879 return plane->plane + 1;
2880 default:
2881 MISSING_CASE(plane->base.type);
2882 return plane->plane;
2883 }
2884}
2885
ee3d532f
PZ		 2886/*
2887 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2888 * so assume we'll always need it in order to avoid underruns.
2889 */
2890static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2891{
2892 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2893
2894 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2895 IS_KABYLAKE(dev_priv))
2896 return true;
2897
2898 return false;
2899}
2900
56feca91
PZ		 2901static bool
2902intel_has_sagv(struct drm_i915_private *dev_priv)
2903{
6e3100ec
PZ		 2904 if (IS_KABYLAKE(dev_priv))
2905 return true;
2906
2907 if (IS_SKYLAKE(dev_priv) &&
2908 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2909 return true;
2910
2911 return false;
56feca91
PZ		 2912}
2913
656d1b89
L		 2914/*
2915 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2916 * depending on power and performance requirements. The display engine access
2917 * to system memory is blocked during the adjustment time. Because of the
2918 * blocking time, having this enabled can cause full system hangs and/or pipe
2919 * underruns if we don't meet all of the following requirements:
2920 *
2921 * - <= 1 pipe enabled
2922 * - All planes can enable watermarks for latencies >= SAGV engine block time
2923 * - We're not using an interlaced display configuration
2924 */
2925int
16dcdc4e 2926intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2927{
2928 int ret;
2929
56feca91
PZ		 2930 if (!intel_has_sagv(dev_priv))
2931 return 0;
2932
2933 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2934 return 0;
2935
2936 DRM_DEBUG_KMS("Enabling the SAGV\n");
2937 mutex_lock(&dev_priv->rps.hw_lock);
2938
2939 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2940 GEN9_SAGV_ENABLE);
2941
2942 /* We don't need to wait for the SAGV when enabling */
2943 mutex_unlock(&dev_priv->rps.hw_lock);
2944
2945 /*
2946 * Some skl systems, pre-release machines in particular,
2947 * don't actually have an SAGV.
2948 */
6e3100ec 2949 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2950 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2951 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2952 return 0;
2953 } else if (ret < 0) {
2954 DRM_ERROR("Failed to enable the SAGV\n");
2955 return ret;
2956 }
2957
16dcdc4e 2958 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2959 return 0;
2960}
2961
2962static int
16dcdc4e 2963intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2964{
2965 int ret;
2966 uint32_t temp = GEN9_SAGV_DISABLE;
2967
2968 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2969 &temp);
2970 if (ret)
2971 return ret;
2972 else
2973 return temp & GEN9_SAGV_IS_DISABLED;
2974}
2975
2976int
16dcdc4e 2977intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2978{
2979 int ret, result;
2980
56feca91
PZ		 2981 if (!intel_has_sagv(dev_priv))
2982 return 0;
2983
2984 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2985 return 0;
2986
2987 DRM_DEBUG_KMS("Disabling the SAGV\n");
2988 mutex_lock(&dev_priv->rps.hw_lock);
2989
2990 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2991 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2992 mutex_unlock(&dev_priv->rps.hw_lock);
2993
2994 if (ret == -ETIMEDOUT) {
2995 DRM_ERROR("Request to disable SAGV timed out\n");
2996 return -ETIMEDOUT;
2997 }
2998
2999 /*
3000 * Some skl systems, pre-release machines in particular,
3001 * don't actually have an SAGV.
3002 */
6e3100ec 3003 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 3004 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3005 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3006 return 0;
3007 } else if (result < 0) {
3008 DRM_ERROR("Failed to disable the SAGV\n");
3009 return result;
3010 }
3011
16dcdc4e 3012 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3013 return 0;
3014}
3015
16dcdc4e 3016bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3017{
3018 struct drm_device *dev = state->dev;
3019 struct drm_i915_private *dev_priv = to_i915(dev);
3020 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3021 struct intel_crtc *crtc;
3022 struct intel_plane *plane;
d8c0fafc 3023 struct intel_crtc_state *cstate;
3024 struct skl_plane_wm *wm;
656d1b89 3025 enum pipe pipe;
d8c0fafc 3026 int level, latency;
656d1b89 3027
56feca91
PZ		 3028 if (!intel_has_sagv(dev_priv))
3029 return false;
3030
656d1b89
L		 3031 /*
3032 * SKL workaround: bspec recommends we disable the SAGV when we have
3033 * more then one pipe enabled
3034 *
3035 * If there are no active CRTCs, no additional checks need be performed
3036 */
3037 if (hweight32(intel_state->active_crtcs) == 0)
3038 return true;
3039 else if (hweight32(intel_state->active_crtcs) > 1)
3040 return false;
3041
3042 /* Since we're now guaranteed to only have one active CRTC... */
3043 pipe = ffs(intel_state->active_crtcs) - 1;
ee3d532f 3044 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d8c0fafc 3045 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3046
c89cadd5 3047 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3048 return false;
3049
ee3d532f 3050 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d8c0fafc 3051 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
ee3d532f 3052
656d1b89 3053 /* Skip this plane if it's not enabled */
d8c0fafc 3054 if (!wm->wm[0].plane_en)
656d1b89
L		 3055 continue;
3056
3057 /* Find the highest enabled wm level for this plane */
5db94019 3058 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3059 !wm->wm[level].plane_en; --level)
656d1b89
L		 3060 { }
3061
ee3d532f
PZ		 3062 latency = dev_priv->wm.skl_latency[level];
3063
3064 if (skl_needs_memory_bw_wa(intel_state) &&
3065 plane->base.state->fb->modifier[0] ==
3066 I915_FORMAT_MOD_X_TILED)
3067 latency += 15;
3068
656d1b89
L		 3069 /*
3070 * If any of the planes on this pipe don't enable wm levels
3071 * that incur memory latencies higher then 30µs we can't enable
3072 * the SAGV
3073 */
ee3d532f 3074 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3075 return false;
3076 }
3077
3078 return true;
3079}
3080
b9cec075
DL		 3081static void
3082skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3083 const struct intel_crtc_state *cstate,
c107acfe
MR		 3084 struct skl_ddb_entry *alloc, /* out */
3085 int *num_active /* out */)
b9cec075 3086{
c107acfe
MR		 3087 struct drm_atomic_state *state = cstate->base.state;
3088 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3089 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3090 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3091 unsigned int pipe_size, ddb_size;
3092 int nth_active_pipe;
c107acfe 3093
a6d3460e 3094 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3095 alloc->start = 0;
3096 alloc->end = 0;
a6d3460e 3097 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3098 return;
3099 }
3100
a6d3460e
MR		 3101 if (intel_state->active_pipe_changes)
3102 *num_active = hweight32(intel_state->active_crtcs);
3103 else
3104 *num_active = hweight32(dev_priv->active_crtcs);
3105
6f3fff60
D		 3106 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3107 WARN_ON(ddb_size == 0);
b9cec075
DL		 3108
3109 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3110
c107acfe 3111 /*
a6d3460e
MR		 3112 * If the state doesn't change the active CRTC's, then there's
3113 * no need to recalculate; the existing pipe allocation limits
3114 * should remain unchanged. Note that we're safe from racing
3115 * commits since any racing commit that changes the active CRTC
3116 * list would need to grab _all_ crtc locks, including the one
3117 * we currently hold.
c107acfe 3118 */
a6d3460e 3119 if (!intel_state->active_pipe_changes) {
ce0ba283 3120 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
a6d3460e 3121 return;
c107acfe 3122 }
a6d3460e
MR		 3123
3124 nth_active_pipe = hweight32(intel_state->active_crtcs &
3125 (drm_crtc_mask(for_crtc) - 1));
3126 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3127 alloc->start = nth_active_pipe * ddb_size / *num_active;
3128 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3129}
3130
c107acfe 3131static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3132{
c107acfe 3133 if (num_active == 1)
b9cec075
DL		 3134 return 32;
3135
3136 return 8;
3137}
3138
a269c583
DL		 3139static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3140{
3141 entry->start = reg & 0x3ff;
3142 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3143 if (entry->end)
3144 entry->end += 1;
a269c583
DL		 3145}
3146
08db6652
DL		 3147void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3148 struct skl_ddb_allocation *ddb /* out */)
a269c583 3149{
a269c583
DL		 3150 enum pipe pipe;
3151 int plane;
3152 u32 val;
3153
b10f1b20
ML		 3154 memset(ddb, 0, sizeof(*ddb));
3155
a269c583 3156 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3157 enum intel_display_power_domain power_domain;
3158
3159 power_domain = POWER_DOMAIN_PIPE(pipe);
3160 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3161 continue;
3162
8b364b41 3163 for_each_universal_plane(dev_priv, pipe, plane) {
a269c583
DL		 3164 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3165 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3166 val);
3167 }
3168
3169 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3170 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3171 val);
4d800030
ID		 3172
3173 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3174 }
3175}
3176
9c2f7a9d
KM		 3177/*
3178 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3179 * The bspec defines downscale amount as:
3180 *
3181 * """
3182 * Horizontal down scale amount = maximum[1, Horizontal source size /
3183 * Horizontal destination size]
3184 * Vertical down scale amount = maximum[1, Vertical source size /
3185 * Vertical destination size]
3186 * Total down scale amount = Horizontal down scale amount *
3187 * Vertical down scale amount
3188 * """
3189 *
3190 * Return value is provided in 16.16 fixed point form to retain fractional part.
3191 * Caller should take care of dividing & rounding off the value.
3192 */
3193static uint32_t
3194skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3195{
3196 uint32_t downscale_h, downscale_w;
3197 uint32_t src_w, src_h, dst_w, dst_h;
3198
936e71e3 3199 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3200 return DRM_PLANE_HELPER_NO_SCALING;
3201
3202 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3203 src_w = drm_rect_width(&pstate->base.src);
3204 src_h = drm_rect_height(&pstate->base.src);
3205 dst_w = drm_rect_width(&pstate->base.dst);
3206 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3207 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3208 swap(dst_w, dst_h);
3209
3210 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3211 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3212
3213 /* Provide result in 16.16 fixed point */
3214 return (uint64_t)downscale_w * downscale_h >> 16;
3215}
3216
b9cec075 3217static unsigned int
024c9045
MR		 3218skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3219 const struct drm_plane_state *pstate,
3220 int y)
b9cec075 3221{
a280f7dd 3222 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3223 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3224 uint32_t down_scale_amount, data_rate;
a280f7dd 3225 uint32_t width = 0, height = 0;
a1de91e5
MR		 3226 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3227
936e71e3 3228 if (!intel_pstate->base.visible)
a1de91e5
MR		 3229 return 0;
3230 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3231 return 0;
3232 if (y && format != DRM_FORMAT_NV12)
3233 return 0;
a280f7dd 3234
936e71e3
VS		 3235 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3236 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3237
bd2ef25d 3238 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3239 swap(width, height);
2cd601c6
CK		 3240
3241 /* for planar format */
a1de91e5 3242 if (format == DRM_FORMAT_NV12) {
2cd601c6 3243 if (y) /* y-plane data rate */
8d19d7d9 3244 data_rate = width * height *
a1de91e5 3245 drm_format_plane_cpp(format, 0);
2cd601c6 3246 else /* uv-plane data rate */
8d19d7d9 3247 data_rate = (width / 2) * (height / 2) *
a1de91e5 3248 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3249 } else {
3250 /* for packed formats */
3251 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3252 }
3253
8d19d7d9
KM		 3254 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3255
3256 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3257}
3258
3259/*
3260 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3261 * a 8192x4096@32bpp framebuffer:
3262 * 3 * 4096 * 8192 * 4 < 2^32
3263 */
3264static unsigned int
1e6ee542
ML		 3265skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3266 unsigned *plane_data_rate,
3267 unsigned *plane_y_data_rate)
b9cec075 3268{
9c74d826
MR		 3269 struct drm_crtc_state *cstate = &intel_cstate->base;
3270 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3271 struct drm_plane *plane;
024c9045 3272 const struct intel_plane *intel_plane;
c8fe32c1 3273 const struct drm_plane_state *pstate;
a1de91e5 3274 unsigned int rate, total_data_rate = 0;
9c74d826 3275 int id;
a6d3460e
MR		 3276
3277 if (WARN_ON(!state))
3278 return 0;
b9cec075 3279
a1de91e5 3280 /* Calculate and cache data rate for each plane */
c8fe32c1 3281 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
a6d3460e
MR		 3282 id = skl_wm_plane_id(to_intel_plane(plane));
3283 intel_plane = to_intel_plane(plane);
3284
a6d3460e
MR		 3285 /* packed/uv */
3286 rate = skl_plane_relative_data_rate(intel_cstate,
3287 pstate, 0);
1e6ee542
ML		 3288 plane_data_rate[id] = rate;
3289
3290 total_data_rate += rate;
a6d3460e
MR		 3291
3292 /* y-plane */
3293 rate = skl_plane_relative_data_rate(intel_cstate,
3294 pstate, 1);
1e6ee542 3295 plane_y_data_rate[id] = rate;
024c9045 3296
1e6ee542 3297 total_data_rate += rate;
b9cec075
DL		 3298 }
3299
3300 return total_data_rate;
3301}
3302
cbcfd14b
KM		 3303static uint16_t
3304skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3305 const int y)
3306{
3307 struct drm_framebuffer *fb = pstate->fb;
3308 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3309 uint32_t src_w, src_h;
3310 uint32_t min_scanlines = 8;
3311 uint8_t plane_bpp;
3312
3313 if (WARN_ON(!fb))
3314 return 0;
3315
3316 /* For packed formats, no y-plane, return 0 */
3317 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3318 return 0;
3319
3320 /* For Non Y-tile return 8-blocks */
3321 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3322 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3323 return 8;
3324
936e71e3
VS		 3325 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3326 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3327
bd2ef25d 3328 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3329 swap(src_w, src_h);
3330
3331 /* Halve UV plane width and height for NV12 */
3332 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3333 src_w /= 2;
3334 src_h /= 2;
3335 }
3336
3337 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3338 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3339 else
3340 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3341
bd2ef25d 3342 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3343 switch (plane_bpp) {
3344 case 1:
3345 min_scanlines = 32;
3346 break;
3347 case 2:
3348 min_scanlines = 16;
3349 break;
3350 case 4:
3351 min_scanlines = 8;
3352 break;
3353 case 8:
3354 min_scanlines = 4;
3355 break;
3356 default:
3357 WARN(1, "Unsupported pixel depth %u for rotation",
3358 plane_bpp);
3359 min_scanlines = 32;
3360 }
3361 }
3362
3363 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3364}
3365
49845a7a
ML		 3366static void
3367skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3368 uint16_t *minimum, uint16_t *y_minimum)
3369{
3370 const struct drm_plane_state *pstate;
3371 struct drm_plane *plane;
3372
3373 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3374 struct intel_plane *intel_plane = to_intel_plane(plane);
3375 int id = skl_wm_plane_id(intel_plane);
3376
3377 if (id == PLANE_CURSOR)
3378 continue;
3379
3380 if (!pstate->visible)
3381 continue;
3382
3383 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3384 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3385 }
3386
3387 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3388}
3389
c107acfe 3390static int
024c9045 3391skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3392 struct skl_ddb_allocation *ddb /* out */)
3393{
c107acfe 3394 struct drm_atomic_state *state = cstate->base.state;
024c9045 3395 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3396 struct drm_device *dev = crtc->dev;
3397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3398 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3399 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
49845a7a 3400 uint16_t alloc_size, start;
fefdd810
ML		 3401 uint16_t minimum[I915_MAX_PLANES] = {};
3402 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3403 unsigned int total_data_rate;
c107acfe
MR		 3404 int num_active;
3405 int id, i;
1e6ee542
ML		 3406 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3407 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3408
5a920b85
PZ		 3409 /* Clear the partitioning for disabled planes. */
3410 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3411 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3412
a6d3460e
MR		 3413 if (WARN_ON(!state))
3414 return 0;
3415
c107acfe 3416 if (!cstate->base.active) {
ce0ba283 3417 alloc->start = alloc->end = 0;
c107acfe
MR		 3418 return 0;
3419 }
3420
a6d3460e 3421 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3422 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3423 if (alloc_size == 0) {
3424 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3425 return 0;
b9cec075
DL		 3426 }
3427
49845a7a 3428 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
a6d3460e 3429
49845a7a
ML		 3430 /*
3431 * 1. Allocate the mininum required blocks for each active plane
3432 * and allocate the cursor, it doesn't require extra allocation
3433 * proportional to the data rate.
3434 */
80958155 3435
49845a7a 3436 for (i = 0; i < I915_MAX_PLANES; i++) {
c107acfe
MR		 3437 alloc_size -= minimum[i];
3438 alloc_size -= y_minimum[i];
80958155
DL		 3439 }
3440
49845a7a
ML		 3441 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3442 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3443
b9cec075 3444 /*
80958155
DL		 3445 * 2. Distribute the remaining space in proportion to the amount of
3446 * data each plane needs to fetch from memory.
b9cec075
DL		 3447 *
3448 * FIXME: we may not allocate every single block here.
3449 */
1e6ee542
ML		 3450 total_data_rate = skl_get_total_relative_data_rate(cstate,
3451 plane_data_rate,
3452 plane_y_data_rate);
a1de91e5 3453 if (total_data_rate == 0)
c107acfe 3454 return 0;
b9cec075 3455
34bb56af 3456 start = alloc->start;
1e6ee542 3457 for (id = 0; id < I915_MAX_PLANES; id++) {
2cd601c6
CK		 3458 unsigned int data_rate, y_data_rate;
3459 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3460
49845a7a
ML		 3461 if (id == PLANE_CURSOR)
3462 continue;
3463
1e6ee542 3464 data_rate = plane_data_rate[id];
b9cec075
DL		 3465
3466 /*
2cd601c6 3467 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3468 * promote the expression to 64 bits to avoid overflowing, the
3469 * result is < available as data_rate / total_data_rate < 1
3470 */
024c9045 3471 plane_blocks = minimum[id];
80958155
DL		 3472 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3473 total_data_rate);
b9cec075 3474
c107acfe
MR		 3475 /* Leave disabled planes at (0,0) */
3476 if (data_rate) {
3477 ddb->plane[pipe][id].start = start;
3478 ddb->plane[pipe][id].end = start + plane_blocks;
3479 }
b9cec075
DL		 3480
3481 start += plane_blocks;
2cd601c6
CK		 3482
3483 /*
3484 * allocation for y_plane part of planar format:
3485 */
1e6ee542 3486 y_data_rate = plane_y_data_rate[id];
a1de91e5
MR		 3487
3488 y_plane_blocks = y_minimum[id];
3489 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3490 total_data_rate);
2cd601c6 3491
c107acfe
MR		 3492 if (y_data_rate) {
3493 ddb->y_plane[pipe][id].start = start;
3494 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3495 }
a1de91e5
MR		 3496
3497 start += y_plane_blocks;
b9cec075
DL		 3498 }
3499
c107acfe 3500 return 0;
b9cec075
DL		 3501}
3502
2d41c0b5
PB		 3503/*
3504 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3505 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3506 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3507 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3508*/
ac484963 3509static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3510{
3511 uint32_t wm_intermediate_val, ret;
3512
3513 if (latency == 0)
3514 return UINT_MAX;
3515
ac484963 3516 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3517 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3518
3519 return ret;
3520}
3521
3522static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3523 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3524{
d4c2aa60 3525 uint32_t ret;
d4c2aa60 3526 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3527
3528 if (latency == 0)
3529 return UINT_MAX;
3530
2d41c0b5
PB		 3531 wm_intermediate_val = latency * pixel_rate;
3532 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3533 plane_blocks_per_line;
2d41c0b5
PB		 3534
3535 return ret;
3536}
3537
9c2f7a9d
KM		 3538static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3539 struct intel_plane_state *pstate)
3540{
3541 uint64_t adjusted_pixel_rate;
3542 uint64_t downscale_amount;
3543 uint64_t pixel_rate;
3544
3545 /* Shouldn't reach here on disabled planes... */
936e71e3 3546 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3547 return 0;
3548
3549 /*
3550 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3551 * with additional adjustments for plane-specific scaling.
3552 */
cfd7e3a2 3553 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
9c2f7a9d
KM		 3554 downscale_amount = skl_plane_downscale_amount(pstate);
3555
3556 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3557 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3558
3559 return pixel_rate;
3560}
3561
55994c2c
MR		 3562static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3563 struct intel_crtc_state *cstate,
3564 struct intel_plane_state *intel_pstate,
3565 uint16_t ddb_allocation,
3566 int level,
3567 uint16_t *out_blocks, /* out */
3568 uint8_t *out_lines, /* out */
3569 bool *enabled /* out */)
2d41c0b5 3570{
33815fa5
MR		 3571 struct drm_plane_state *pstate = &intel_pstate->base;
3572 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3573 uint32_t latency = dev_priv->wm.skl_latency[level];
3574 uint32_t method1, method2;
3575 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3576 uint32_t res_blocks, res_lines;
3577 uint32_t selected_result;
ac484963 3578 uint8_t cpp;
a280f7dd 3579 uint32_t width = 0, height = 0;
9c2f7a9d 3580 uint32_t plane_pixel_rate;
75676ed4 3581 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3582 struct intel_atomic_state *state =
3583 to_intel_atomic_state(cstate->base.state);
3584 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3585
936e71e3 3586 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3587 *enabled = false;
3588 return 0;
3589 }
2d41c0b5 3590
ee3d532f
PZ		 3591 if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3592 latency += 15;
3593
936e71e3
VS		 3594 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3595 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3596
bd2ef25d 3597 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3598 swap(width, height);
3599
ac484963 3600 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3601 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3602
61d0a04d 3603 if (drm_rotation_90_or_270(pstate->rotation)) {
1186fa85
PZ		 3604 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3605 drm_format_plane_cpp(fb->pixel_format, 1) :
3606 drm_format_plane_cpp(fb->pixel_format, 0);
3607
3608 switch (cpp) {
3609 case 1:
3610 y_min_scanlines = 16;
3611 break;
3612 case 2:
3613 y_min_scanlines = 8;
3614 break;
1186fa85
PZ		 3615 case 4:
3616 y_min_scanlines = 4;
3617 break;
86a462bc
PZ		 3618 default:
3619 MISSING_CASE(cpp);
3620 return -EINVAL;
1186fa85
PZ		 3621 }
3622 } else {
3623 y_min_scanlines = 4;
3624 }
3625
7a1a8aed
PZ		 3626 plane_bytes_per_line = width * cpp;
3627 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3628 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3629 plane_blocks_per_line =
3630 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3631 plane_blocks_per_line /= y_min_scanlines;
3632 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3633 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3634 + 1;
3635 } else {
3636 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3637 }
3638
9c2f7a9d
KM		 3639 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3640 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3641 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3642 latency,
7a1a8aed 3643 plane_blocks_per_line);
2d41c0b5 3644
75676ed4 3645 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
ee3d532f
PZ		 3646 if (apply_memory_bw_wa)
3647 y_tile_minimum *= 2;
75676ed4 3648
024c9045
MR		 3649 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3650 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3651 selected_result = max(method2, y_tile_minimum);
3652 } else {
f1db3eaf
PZ		 3653 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3654 (plane_bytes_per_line / 512 < 1))
3655 selected_result = method2;
3656 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3657 selected_result = min(method1, method2);
3658 else
3659 selected_result = method1;
3660 }
2d41c0b5 3661
d4c2aa60
TU		 3662 res_blocks = selected_result + 1;
3663 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3664
0fda6568 3665 if (level >= 1 && level <= 7) {
024c9045 3666 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3667 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3668 res_blocks += y_tile_minimum;
1186fa85 3669 res_lines += y_min_scanlines;
75676ed4 3670 } else {
0fda6568 3671 res_blocks++;
75676ed4 3672 }
0fda6568 3673 }
e6d66171 3674
55994c2c
MR		 3675 if (res_blocks >= ddb_allocation || res_lines > 31) {
3676 *enabled = false;
6b6bada7
MR		 3677
3678 /*
3679 * If there are no valid level 0 watermarks, then we can't
3680 * support this display configuration.
3681 */
3682 if (level) {
3683 return 0;
3684 } else {
3685 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3686 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3687 to_intel_crtc(cstate->base.crtc)->pipe,
3688 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3689 res_blocks, ddb_allocation, res_lines);
3690
3691 return -EINVAL;
3692 }
55994c2c 3693 }
e6d66171
DL		 3694
3695 *out_blocks = res_blocks;
3696 *out_lines = res_lines;
55994c2c 3697 *enabled = true;
2d41c0b5 3698
55994c2c 3699 return 0;
2d41c0b5
PB		 3700}
3701
f4a96752
MR		 3702static int
3703skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3704 struct skl_ddb_allocation *ddb,
3705 struct intel_crtc_state *cstate,
a62163e9 3706 struct intel_plane *intel_plane,
f4a96752
MR		 3707 int level,
3708 struct skl_wm_level *result)
2d41c0b5 3709{
f4a96752 3710 struct drm_atomic_state *state = cstate->base.state;
024c9045 3711 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3712 struct drm_plane *plane = &intel_plane->base;
3713 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3714 uint16_t ddb_blocks;
024c9045 3715 enum pipe pipe = intel_crtc->pipe;
55994c2c 3716 int ret;
a62163e9
L		 3717 int i = skl_wm_plane_id(intel_plane);
3718
3719 if (state)
3720 intel_pstate =
3721 intel_atomic_get_existing_plane_state(state,
3722 intel_plane);
024c9045 3723
f4a96752 3724 /*
a62163e9
L		 3725 * Note: If we start supporting multiple pending atomic commits against
3726 * the same planes/CRTC's in the future, plane->state will no longer be
3727 * the correct pre-state to use for the calculations here and we'll
3728 * need to change where we get the 'unchanged' plane data from.
3729 *
3730 * For now this is fine because we only allow one queued commit against
3731 * a CRTC. Even if the plane isn't modified by this transaction and we
3732 * don't have a plane lock, we still have the CRTC's lock, so we know
3733 * that no other transactions are racing with us to update it.
f4a96752 3734 */
a62163e9
L		 3735 if (!intel_pstate)
3736 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3737
a62163e9 3738 WARN_ON(!intel_pstate->base.fb);
f4a96752 3739
a62163e9 3740 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2d41c0b5 3741
a62163e9
L		 3742 ret = skl_compute_plane_wm(dev_priv,
3743 cstate,
3744 intel_pstate,
3745 ddb_blocks,
3746 level,
3747 &result->plane_res_b,
3748 &result->plane_res_l,
3749 &result->plane_en);
3750 if (ret)
3751 return ret;
f4a96752
MR		 3752
3753 return 0;
2d41c0b5
PB		 3754}
3755
407b50f3 3756static uint32_t
024c9045 3757skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3758{
30d1b5fe
PZ		 3759 uint32_t pixel_rate;
3760
024c9045 3761 if (!cstate->base.active)
407b50f3
DL		 3762 return 0;
3763
30d1b5fe
PZ		 3764 pixel_rate = ilk_pipe_pixel_rate(cstate);
3765
3766 if (WARN_ON(pixel_rate == 0))
661abfc0 3767 return 0;
407b50f3 3768
024c9045 3769 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
30d1b5fe 3770 pixel_rate);
407b50f3
DL		 3771}
3772
024c9045 3773static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3774 struct skl_wm_level *trans_wm /* out */)
407b50f3 3775{
024c9045 3776 if (!cstate->base.active)
407b50f3 3777 return;
9414f563
DL		 3778
3779 /* Until we know more, just disable transition WMs */
a62163e9 3780 trans_wm->plane_en = false;
407b50f3
DL		 3781}
3782
55994c2c
MR		 3783static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3784 struct skl_ddb_allocation *ddb,
3785 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3786{
024c9045 3787 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3788 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3789 struct intel_plane *intel_plane;
3790 struct skl_plane_wm *wm;
5db94019 3791 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3792 int ret;
2d41c0b5 3793
a62163e9
L		 3794 /*
3795 * We'll only calculate watermarks for planes that are actually
3796 * enabled, so make sure all other planes are set as disabled.
3797 */
3798 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3799
3800 for_each_intel_plane_mask(&dev_priv->drm,
3801 intel_plane,
3802 cstate->base.plane_mask) {
3803 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3804
3805 for (level = 0; level <= max_level; level++) {
3806 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3807 intel_plane, level,
3808 &wm->wm[level]);
3809 if (ret)
3810 return ret;
3811 }
3812 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3813 }
024c9045 3814 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3815
55994c2c 3816 return 0;
2d41c0b5
PB		 3817}
3818
f0f59a00
VS		 3819static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3820 i915_reg_t reg,
16160e3d
DL		 3821 const struct skl_ddb_entry *entry)
3822{
3823 if (entry->end)
3824 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3825 else
3826 I915_WRITE(reg, 0);
3827}
3828
d8c0fafc 3829static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3830 i915_reg_t reg,
3831 const struct skl_wm_level *level)
3832{
3833 uint32_t val = 0;
3834
3835 if (level->plane_en) {
3836 val |= PLANE_WM_EN;
3837 val |= level->plane_res_b;
3838 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3839 }
3840
3841 I915_WRITE(reg, val);
3842}
3843
62e0fb88 3844void skl_write_plane_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3845 const struct skl_plane_wm *wm,
3846 const struct skl_ddb_allocation *ddb,
62e0fb88
L		 3847 int plane)
3848{
3849 struct drm_crtc *crtc = &intel_crtc->base;
3850 struct drm_device *dev = crtc->dev;
3851 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3852 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3853 enum pipe pipe = intel_crtc->pipe;
3854
3855 for (level = 0; level <= max_level; level++) {
d8c0fafc 3856 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3857 &wm->wm[level]);
62e0fb88 3858 }
d8c0fafc 3859 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3860 &wm->trans_wm);
27082493
L		 3861
3862 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
d8c0fafc 3863 &ddb->plane[pipe][plane]);
27082493 3864 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
d8c0fafc 3865 &ddb->y_plane[pipe][plane]);
62e0fb88
L		 3866}
3867
3868void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3869 const struct skl_plane_wm *wm,
3870 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3871{
3872 struct drm_crtc *crtc = &intel_crtc->base;
3873 struct drm_device *dev = crtc->dev;
3874 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3875 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3876 enum pipe pipe = intel_crtc->pipe;
3877
3878 for (level = 0; level <= max_level; level++) {
d8c0fafc 3879 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3880 &wm->wm[level]);
62e0fb88 3881 }
d8c0fafc 3882 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3883
27082493 3884 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3885 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3886}
3887
45ece230 3888bool skl_wm_level_equals(const struct skl_wm_level *l1,
3889 const struct skl_wm_level *l2)
3890{
3891 if (l1->plane_en != l2->plane_en)
3892 return false;
3893
3894 /* If both planes aren't enabled, the rest shouldn't matter */
3895 if (!l1->plane_en)
3896 return true;
3897
3898 return (l1->plane_res_l == l2->plane_res_l &&
3899 l1->plane_res_b == l2->plane_res_b);
3900}
3901
27082493
L		 3902static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3903 const struct skl_ddb_entry *b)
0e8fb7ba 3904{
27082493 3905 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3906}
3907
27082493 3908bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
ce0ba283 3909 struct intel_crtc *intel_crtc)
0e8fb7ba 3910{
ce0ba283
L		 3911 struct drm_crtc *other_crtc;
3912 struct drm_crtc_state *other_cstate;
3913 struct intel_crtc *other_intel_crtc;
3914 const struct skl_ddb_entry *ddb =
3915 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3916 int i;
0e8fb7ba 3917
ce0ba283
L		 3918 for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3919 other_intel_crtc = to_intel_crtc(other_crtc);
0e8fb7ba 3920
ce0ba283 3921 if (other_intel_crtc == intel_crtc)
0e8fb7ba
DL		 3922 continue;
3923
ce0ba283 3924 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
27082493 3925 return true;
0e8fb7ba
DL		 3926 }
3927
27082493 3928 return false;
0e8fb7ba
DL		 3929}
3930
55994c2c 3931static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
03af79e0 3932 const struct skl_pipe_wm *old_pipe_wm,
55994c2c 3933 struct skl_pipe_wm *pipe_wm, /* out */
03af79e0 3934 struct skl_ddb_allocation *ddb, /* out */
55994c2c 3935 bool *changed /* out */)
2d41c0b5 3936{
f4a96752 3937 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3938 int ret;
2d41c0b5 3939
55994c2c
MR		 3940 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3941 if (ret)
3942 return ret;
2d41c0b5 3943
03af79e0 3944 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3945 *changed = false;
3946 else
3947 *changed = true;
2d41c0b5 3948
55994c2c 3949 return 0;
2d41c0b5
PB		 3950}
3951
9b613022
MR		 3952static uint32_t
3953pipes_modified(struct drm_atomic_state *state)
3954{
3955 struct drm_crtc *crtc;
3956 struct drm_crtc_state *cstate;
3957 uint32_t i, ret = 0;
3958
3959 for_each_crtc_in_state(state, crtc, cstate, i)
3960 ret |= drm_crtc_mask(crtc);
3961
3962 return ret;
3963}
3964
bb7791bd 3965static int
7f60e200
PZ		 3966skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3967{
3968 struct drm_atomic_state *state = cstate->base.state;
3969 struct drm_device *dev = state->dev;
3970 struct drm_crtc *crtc = cstate->base.crtc;
3971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3972 struct drm_i915_private *dev_priv = to_i915(dev);
3973 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3974 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3975 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3976 struct drm_plane_state *plane_state;
3977 struct drm_plane *plane;
3978 enum pipe pipe = intel_crtc->pipe;
3979 int id;
3980
3981 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3982
220b0965 3983 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
7f60e200
PZ		 3984 id = skl_wm_plane_id(to_intel_plane(plane));
3985
3986 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3987 &new_ddb->plane[pipe][id]) &&
3988 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3989 &new_ddb->y_plane[pipe][id]))
3990 continue;
3991
3992 plane_state = drm_atomic_get_plane_state(state, plane);
3993 if (IS_ERR(plane_state))
3994 return PTR_ERR(plane_state);
3995 }
3996
3997 return 0;
3998}
3999
98d39494
MR		 4000static int
4001skl_compute_ddb(struct drm_atomic_state *state)
4002{
4003 struct drm_device *dev = state->dev;
4004 struct drm_i915_private *dev_priv = to_i915(dev);
4005 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4006 struct intel_crtc *intel_crtc;
734fa01f 4007 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4008 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4009 int ret;
4010
4011 /*
4012 * If this is our first atomic update following hardware readout,
4013 * we can't trust the DDB that the BIOS programmed for us. Let's
4014 * pretend that all pipes switched active status so that we'll
4015 * ensure a full DDB recompute.
4016 */
1b54a880
MR		 4017 if (dev_priv->wm.distrust_bios_wm) {
4018 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4019 state->acquire_ctx);
4020 if (ret)
4021 return ret;
4022
98d39494
MR		 4023 intel_state->active_pipe_changes = ~0;
4024
1b54a880
MR		 4025 /*
4026 * We usually only initialize intel_state->active_crtcs if we
4027 * we're doing a modeset; make sure this field is always
4028 * initialized during the sanitization process that happens
4029 * on the first commit too.
4030 */
4031 if (!intel_state->modeset)
4032 intel_state->active_crtcs = dev_priv->active_crtcs;
4033 }
4034
98d39494
MR		 4035 /*
4036 * If the modeset changes which CRTC's are active, we need to
4037 * recompute the DDB allocation for *all* active pipes, even
4038 * those that weren't otherwise being modified in any way by this
4039 * atomic commit. Due to the shrinking of the per-pipe allocations
4040 * when new active CRTC's are added, it's possible for a pipe that
4041 * we were already using and aren't changing at all here to suddenly
4042 * become invalid if its DDB needs exceeds its new allocation.
4043 *
4044 * Note that if we wind up doing a full DDB recompute, we can't let
4045 * any other display updates race with this transaction, so we need
4046 * to grab the lock on *all* CRTC's.
4047 */
734fa01f 4048 if (intel_state->active_pipe_changes) {
98d39494 4049 realloc_pipes = ~0;
734fa01f
MR		 4050 intel_state->wm_results.dirty_pipes = ~0;
4051 }
98d39494 4052
5a920b85
PZ		 4053 /*
4054 * We're not recomputing for the pipes not included in the commit, so
4055 * make sure we start with the current state.
4056 */
4057 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4058
98d39494
MR		 4059 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4060 struct intel_crtc_state *cstate;
4061
4062 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4063 if (IS_ERR(cstate))
4064 return PTR_ERR(cstate);
4065
734fa01f 4066 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4067 if (ret)
4068 return ret;
05a76d3d 4069
7f60e200 4070 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4071 if (ret)
4072 return ret;
98d39494
MR		 4073 }
4074
4075 return 0;
4076}
4077
2722efb9
MR		 4078static void
4079skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4080 struct skl_wm_values *src,
4081 enum pipe pipe)
4082{
2722efb9
MR		 4083 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4084 sizeof(dst->ddb.y_plane[pipe]));
4085 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4086 sizeof(dst->ddb.plane[pipe]));
4087}
4088
413fc530 4089static void
4090skl_print_wm_changes(const struct drm_atomic_state *state)
4091{
4092 const struct drm_device *dev = state->dev;
4093 const struct drm_i915_private *dev_priv = to_i915(dev);
4094 const struct intel_atomic_state *intel_state =
4095 to_intel_atomic_state(state);
4096 const struct drm_crtc *crtc;
4097 const struct drm_crtc_state *cstate;
413fc530 4098 const struct intel_plane *intel_plane;
413fc530 4099 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4100 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
413fc530 4101 int id;
7570498e 4102 int i;
413fc530 4103
4104 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4105 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4106 enum pipe pipe = intel_crtc->pipe;
413fc530 4107
7570498e 4108 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
413fc530 4109 const struct skl_ddb_entry *old, *new;
4110
413fc530 4111 id = skl_wm_plane_id(intel_plane);
4112 old = &old_ddb->plane[pipe][id];
4113 new = &new_ddb->plane[pipe][id];
4114
413fc530 4115 if (skl_ddb_entry_equal(old, new))
4116 continue;
4117
7570498e
ML		 4118 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4119 intel_plane->base.base.id,
4120 intel_plane->base.name,
4121 old->start, old->end,
4122 new->start, new->end);
413fc530 4123 }
4124 }
4125}
4126
98d39494
MR		 4127static int
4128skl_compute_wm(struct drm_atomic_state *state)
4129{
4130 struct drm_crtc *crtc;
4131 struct drm_crtc_state *cstate;
734fa01f
MR		 4132 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4133 struct skl_wm_values *results = &intel_state->wm_results;
4134 struct skl_pipe_wm *pipe_wm;
98d39494 4135 bool changed = false;
734fa01f 4136 int ret, i;
98d39494
MR		 4137
4138 /*
4139 * If this transaction isn't actually touching any CRTC's, don't
4140 * bother with watermark calculation. Note that if we pass this
4141 * test, we're guaranteed to hold at least one CRTC state mutex,
4142 * which means we can safely use values like dev_priv->active_crtcs
4143 * since any racing commits that want to update them would need to
4144 * hold _all_ CRTC state mutexes.
4145 */
4146 for_each_crtc_in_state(state, crtc, cstate, i)
4147 changed = true;
4148 if (!changed)
4149 return 0;
4150
734fa01f
MR		 4151 /* Clear all dirty flags */
4152 results->dirty_pipes = 0;
4153
98d39494
MR		 4154 ret = skl_compute_ddb(state);
4155 if (ret)
4156 return ret;
4157
734fa01f
MR		 4158 /*
4159 * Calculate WM's for all pipes that are part of this transaction.
4160 * Note that the DDB allocation above may have added more CRTC's that
4161 * weren't otherwise being modified (and set bits in dirty_pipes) if
4162 * pipe allocations had to change.
4163 *
4164 * FIXME: Now that we're doing this in the atomic check phase, we
4165 * should allow skl_update_pipe_wm() to return failure in cases where
4166 * no suitable watermark values can be found.
4167 */
4168 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4169 struct intel_crtc_state *intel_cstate =
4170 to_intel_crtc_state(cstate);
03af79e0
ML		 4171 const struct skl_pipe_wm *old_pipe_wm =
4172 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
734fa01f
MR		 4173
4174 pipe_wm = &intel_cstate->wm.skl.optimal;
03af79e0
ML		 4175 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4176 &results->ddb, &changed);
734fa01f
MR		 4177 if (ret)
4178 return ret;
4179
4180 if (changed)
4181 results->dirty_pipes |= drm_crtc_mask(crtc);
4182
4183 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4184 /* This pipe's WM's did not change */
4185 continue;
4186
4187 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4188 }
4189
413fc530 4190 skl_print_wm_changes(state);
4191
98d39494
MR		 4192 return 0;
4193}
4194
432081bc 4195static void skl_update_wm(struct intel_crtc *intel_crtc)
2d41c0b5 4196{
432081bc 4197 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4198 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4199 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4200 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
432081bc 4201 struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
e8f1f02e 4202 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4203 enum pipe pipe = intel_crtc->pipe;
adda50b8 4204
432081bc 4205 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
2d41c0b5
PB		 4206 return;
4207
734fa01f 4208 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4209
2722efb9 4210 /*
27082493
L		 4211 * If this pipe isn't active already, we're going to be enabling it
4212 * very soon. Since it's safe to update a pipe's ddb allocation while
4213 * the pipe's shut off, just do so here. Already active pipes will have
4214 * their watermarks updated once we update their planes.
2722efb9 4215 */
432081bc 4216 if (intel_crtc->base.state->active_changed) {
27082493
L		 4217 int plane;
4218
2c4b49a0 4219 for_each_universal_plane(dev_priv, pipe, plane)
d8c0fafc 4220 skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4221 &results->ddb, plane);
27082493 4222
d8c0fafc 4223 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4224 &results->ddb);
27082493
L		 4225 }
4226
4227 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f 4228
ce0ba283
L		 4229 intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4230
734fa01f 4231 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4232}
4233
d890565c
VS		 4234static void ilk_compute_wm_config(struct drm_device *dev,
4235 struct intel_wm_config *config)
4236{
4237 struct intel_crtc *crtc;
4238
4239 /* Compute the currently _active_ config */
4240 for_each_intel_crtc(dev, crtc) {
4241 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4242
4243 if (!wm->pipe_enabled)
4244 continue;
4245
4246 config->sprites_enabled |= wm->sprites_enabled;
4247 config->sprites_scaled |= wm->sprites_scaled;
4248 config->num_pipes_active++;
4249 }
4250}
4251
ed4a6a7c 4252static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4253{
91c8a326 4254 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4255 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4256 struct ilk_wm_maximums max;
d890565c 4257 struct intel_wm_config config = {};
820c1980 4258 struct ilk_wm_values results = {};
77c122bc 4259 enum intel_ddb_partitioning partitioning;
261a27d1 4260
d890565c
VS		 4261 ilk_compute_wm_config(dev, &config);
4262
4263 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4264 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4265
4266 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4267 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4268 config.num_pipes_active == 1 && config.sprites_enabled) {
4269 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4270 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4271
820c1980 4272 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4273 } else {
198a1e9b 4274 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4275 }
4276
198a1e9b 4277 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4278 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4279
820c1980 4280 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4281
820c1980 4282 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4283}
4284
ed4a6a7c 4285static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4286{
ed4a6a7c
MR		 4287 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4288 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4289
ed4a6a7c 4290 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4291 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4292 ilk_program_watermarks(dev_priv);
4293 mutex_unlock(&dev_priv->wm.wm_mutex);
4294}
bf220452 4295
ed4a6a7c
MR		 4296static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4297{
4298 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4299 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4300
ed4a6a7c
MR		 4301 mutex_lock(&dev_priv->wm.wm_mutex);
4302 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4303 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4304 ilk_program_watermarks(dev_priv);
4305 }
4306 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4307}
4308
d8c0fafc 4309static inline void skl_wm_level_from_reg_val(uint32_t val,
4310 struct skl_wm_level *level)
3078999f 4311{
d8c0fafc 4312 level->plane_en = val & PLANE_WM_EN;
4313 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4314 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4315 PLANE_WM_LINES_MASK;
3078999f
PB		 4316}
4317
bf9d99ad 4318void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4319 struct skl_pipe_wm *out)
3078999f
PB		 4320{
4321 struct drm_device *dev = crtc->dev;
fac5e23e 4322 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f 4323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d8c0fafc 4324 struct intel_plane *intel_plane;
d8c0fafc 4325 struct skl_plane_wm *wm;
3078999f 4326 enum pipe pipe = intel_crtc->pipe;
d8c0fafc 4327 int level, id, max_level;
4328 uint32_t val;
3078999f 4329
5db94019 4330 max_level = ilk_wm_max_level(dev_priv);
3078999f 4331
d8c0fafc 4332 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4333 id = skl_wm_plane_id(intel_plane);
bf9d99ad 4334 wm = &out->planes[id];
3078999f 4335
d8c0fafc 4336 for (level = 0; level <= max_level; level++) {
4337 if (id != PLANE_CURSOR)
4338 val = I915_READ(PLANE_WM(pipe, id, level));
4339 else
4340 val = I915_READ(CUR_WM(pipe, level));
3078999f 4341
d8c0fafc 4342 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4343 }
3078999f 4344
d8c0fafc 4345 if (id != PLANE_CURSOR)
4346 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4347 else
4348 val = I915_READ(CUR_WM_TRANS(pipe));
4349
4350 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4351 }
4352
d8c0fafc 4353 if (!intel_crtc->active)
4354 return;
4e0963c7 4355
bf9d99ad 4356 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4357}
4358
4359void skl_wm_get_hw_state(struct drm_device *dev)
4360{
fac5e23e 4361 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4362 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4363 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4364 struct drm_crtc *crtc;
bf9d99ad 4365 struct intel_crtc *intel_crtc;
4366 struct intel_crtc_state *cstate;
3078999f 4367
a269c583 4368 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4369 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4370 intel_crtc = to_intel_crtc(crtc);
4371 cstate = to_intel_crtc_state(crtc->state);
4372
4373 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4374
03af79e0 4375 if (intel_crtc->active)
bf9d99ad 4376 hw->dirty_pipes |= drm_crtc_mask(crtc);
bf9d99ad 4377 }
a1de91e5 4378
279e99d7
MR		 4379 if (dev_priv->active_crtcs) {
4380 /* Fully recompute DDB on first atomic commit */
4381 dev_priv->wm.distrust_bios_wm = true;
4382 } else {
4383 /* Easy/common case; just sanitize DDB now if everything off */
4384 memset(ddb, 0, sizeof(*ddb));
4385 }
3078999f
PB		 4386}
4387
243e6a44
VS		 4388static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4389{
4390 struct drm_device *dev = crtc->dev;
fac5e23e 4391 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4392 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4394 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4395 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4396 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4397 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4398 [PIPE_A] = WM0_PIPEA_ILK,
4399 [PIPE_B] = WM0_PIPEB_ILK,
4400 [PIPE_C] = WM0_PIPEC_IVB,
4401 };
4402
4403 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4404 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4405 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4406
15606534
VS		 4407 memset(active, 0, sizeof(*active));
4408
3ef00284 4409 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4410
4411 if (active->pipe_enabled) {
243e6a44
VS		 4412 u32 tmp = hw->wm_pipe[pipe];
4413
4414 /*
4415 * For active pipes LP0 watermark is marked as
4416 * enabled, and LP1+ watermaks as disabled since
4417 * we can't really reverse compute them in case
4418 * multiple pipes are active.
4419 */
4420 active->wm[0].enable = true;
4421 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4422 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4423 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4424 active->linetime = hw->wm_linetime[pipe];
4425 } else {
5db94019 4426 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4427
4428 /*
4429 * For inactive pipes, all watermark levels
4430 * should be marked as enabled but zeroed,
4431 * which is what we'd compute them to.
4432 */
4433 for (level = 0; level <= max_level; level++)
4434 active->wm[level].enable = true;
4435 }
4e0963c7
MR		 4436
4437 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4438}
4439
6eb1a681
VS		 4440#define _FW_WM(value, plane) \
4441 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4442#define _FW_WM_VLV(value, plane) \
4443 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4444
4445static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4446 struct vlv_wm_values *wm)
4447{
4448 enum pipe pipe;
4449 uint32_t tmp;
4450
4451 for_each_pipe(dev_priv, pipe) {
4452 tmp = I915_READ(VLV_DDL(pipe));
4453
4454 wm->ddl[pipe].primary =
4455 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4456 wm->ddl[pipe].cursor =
4457 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4458 wm->ddl[pipe].sprite[0] =
4459 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4460 wm->ddl[pipe].sprite[1] =
4461 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4462 }
4463
4464 tmp = I915_READ(DSPFW1);
4465 wm->sr.plane = _FW_WM(tmp, SR);
4466 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4467 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4468 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4469
4470 tmp = I915_READ(DSPFW2);
4471 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4472 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4473 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4474
4475 tmp = I915_READ(DSPFW3);
4476 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4477
4478 if (IS_CHERRYVIEW(dev_priv)) {
4479 tmp = I915_READ(DSPFW7_CHV);
4480 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4481 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4482
4483 tmp = I915_READ(DSPFW8_CHV);
4484 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4485 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4486
4487 tmp = I915_READ(DSPFW9_CHV);
4488 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4489 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4490
4491 tmp = I915_READ(DSPHOWM);
4492 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4493 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4494 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4495 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4496 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4497 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4498 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4499 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4500 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4501 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4502 } else {
4503 tmp = I915_READ(DSPFW7);
4504 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4505 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4506
4507 tmp = I915_READ(DSPHOWM);
4508 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4509 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4510 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4511 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4512 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4513 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4514 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4515 }
4516}
4517
4518#undef _FW_WM
4519#undef _FW_WM_VLV
4520
4521void vlv_wm_get_hw_state(struct drm_device *dev)
4522{
4523 struct drm_i915_private *dev_priv = to_i915(dev);
4524 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4525 struct intel_plane *plane;
4526 enum pipe pipe;
4527 u32 val;
4528
4529 vlv_read_wm_values(dev_priv, wm);
4530
4531 for_each_intel_plane(dev, plane) {
4532 switch (plane->base.type) {
4533 int sprite;
4534 case DRM_PLANE_TYPE_CURSOR:
4535 plane->wm.fifo_size = 63;
4536 break;
4537 case DRM_PLANE_TYPE_PRIMARY:
4538 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4539 break;
4540 case DRM_PLANE_TYPE_OVERLAY:
4541 sprite = plane->plane;
4542 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4543 break;
4544 }
4545 }
4546
4547 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4548 wm->level = VLV_WM_LEVEL_PM2;
4549
4550 if (IS_CHERRYVIEW(dev_priv)) {
4551 mutex_lock(&dev_priv->rps.hw_lock);
4552
4553 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4554 if (val & DSP_MAXFIFO_PM5_ENABLE)
4555 wm->level = VLV_WM_LEVEL_PM5;
4556
58590c14
VS		 4557 /*
4558 * If DDR DVFS is disabled in the BIOS, Punit
4559 * will never ack the request. So if that happens
4560 * assume we don't have to enable/disable DDR DVFS
4561 * dynamically. To test that just set the REQ_ACK
4562 * bit to poke the Punit, but don't change the
4563 * HIGH/LOW bits so that we don't actually change
4564 * the current state.
4565 */
6eb1a681 4566 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4567 val |= FORCE_DDR_FREQ_REQ_ACK;
4568 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4569
4570 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4571 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4572 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4573 "assuming DDR DVFS is disabled\n");
4574 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4575 } else {
4576 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4577 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4578 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4579 }
6eb1a681
VS		 4580
4581 mutex_unlock(&dev_priv->rps.hw_lock);
4582 }
4583
4584 for_each_pipe(dev_priv, pipe)
4585 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4586 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4587 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4588
4589 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4590 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4591}
4592
243e6a44
VS		 4593void ilk_wm_get_hw_state(struct drm_device *dev)
4594{
fac5e23e 4595 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4596 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4597 struct drm_crtc *crtc;
4598
70e1e0ec 4599 for_each_crtc(dev, crtc)
243e6a44
VS		 4600 ilk_pipe_wm_get_hw_state(crtc);
4601
4602 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4603 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4604 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4605
4606 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4607 if (INTEL_INFO(dev)->gen >= 7) {
4608 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4609 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4610 }
243e6a44 4611
8652744b 4612 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4613 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4614 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4615 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4616 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4617 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4618
4619 hw->enable_fbc_wm =
4620 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4621}
4622
b445e3b0
ED		 4623/**
4624 * intel_update_watermarks - update FIFO watermark values based on current modes
4625 *
4626 * Calculate watermark values for the various WM regs based on current mode
4627 * and plane configuration.
4628 *
4629 * There are several cases to deal with here:
4630 * - normal (i.e. non-self-refresh)
4631 * - self-refresh (SR) mode
4632 * - lines are large relative to FIFO size (buffer can hold up to 2)
4633 * - lines are small relative to FIFO size (buffer can hold more than 2
4634 * lines), so need to account for TLB latency
4635 *
4636 * The normal calculation is:
4637 * watermark = dotclock * bytes per pixel * latency
4638 * where latency is platform & configuration dependent (we assume pessimal
4639 * values here).
4640 *
4641 * The SR calculation is:
4642 * watermark = (trunc(latency/line time)+1) * surface width *
4643 * bytes per pixel
4644 * where
4645 * line time = htotal / dotclock
4646 * surface width = hdisplay for normal plane and 64 for cursor
4647 * and latency is assumed to be high, as above.
4648 *
4649 * The final value programmed to the register should always be rounded up,
4650 * and include an extra 2 entries to account for clock crossings.
4651 *
4652 * We don't use the sprite, so we can ignore that. And on Crestline we have
4653 * to set the non-SR watermarks to 8.
4654 */
432081bc 4655void intel_update_watermarks(struct intel_crtc *crtc)
b445e3b0 4656{
432081bc 4657 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0
ED		 4658
4659 if (dev_priv->display.update_wm)
46ba614c 4660 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4661}
4662
e2828914 4663/*
9270388e 4664 * Lock protecting IPS related data structures
9270388e
DV		 4665 */
4666DEFINE_SPINLOCK(mchdev_lock);
4667
4668/* Global for IPS driver to get at the current i915 device. Protected by
4669 * mchdev_lock. */
4670static struct drm_i915_private *i915_mch_dev;
4671
91d14251 4672bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4673{
2b4e57bd
ED		 4674 u16 rgvswctl;
4675
9270388e
DV		 4676 assert_spin_locked(&mchdev_lock);
4677
2b4e57bd
ED		 4678 rgvswctl = I915_READ16(MEMSWCTL);
4679 if (rgvswctl & MEMCTL_CMD_STS) {
4680 DRM_DEBUG("gpu busy, RCS change rejected\n");
4681 return false; /* still busy with another command */
4682 }
4683
4684 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4685 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4686 I915_WRITE16(MEMSWCTL, rgvswctl);
4687 POSTING_READ16(MEMSWCTL);
4688
4689 rgvswctl |= MEMCTL_CMD_STS;
4690 I915_WRITE16(MEMSWCTL, rgvswctl);
4691
4692 return true;
4693}
4694
91d14251 4695static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4696{
84f1b20f 4697 u32 rgvmodectl;
2b4e57bd
ED		 4698 u8 fmax, fmin, fstart, vstart;
4699
9270388e
DV		 4700 spin_lock_irq(&mchdev_lock);
4701
84f1b20f
TU		 4702 rgvmodectl = I915_READ(MEMMODECTL);
4703
2b4e57bd
ED		 4704 /* Enable temp reporting */
4705 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4706 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4707
4708 /* 100ms RC evaluation intervals */
4709 I915_WRITE(RCUPEI, 100000);
4710 I915_WRITE(RCDNEI, 100000);
4711
4712 /* Set max/min thresholds to 90ms and 80ms respectively */
4713 I915_WRITE(RCBMAXAVG, 90000);
4714 I915_WRITE(RCBMINAVG, 80000);
4715
4716 I915_WRITE(MEMIHYST, 1);
4717
4718 /* Set up min, max, and cur for interrupt handling */
4719 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4720 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4721 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4722 MEMMODE_FSTART_SHIFT;
4723
616847e7 4724 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4725 PXVFREQ_PX_SHIFT;
4726
20e4d407
DV		 4727 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4728 dev_priv->ips.fstart = fstart;
2b4e57bd 4729
20e4d407
DV		 4730 dev_priv->ips.max_delay = fstart;
4731 dev_priv->ips.min_delay = fmin;
4732 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4733
4734 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4735 fmax, fmin, fstart);
4736
4737 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4738
4739 /*
4740 * Interrupts will be enabled in ironlake_irq_postinstall
4741 */
4742
4743 I915_WRITE(VIDSTART, vstart);
4744 POSTING_READ(VIDSTART);
4745
4746 rgvmodectl |= MEMMODE_SWMODE_EN;
4747 I915_WRITE(MEMMODECTL, rgvmodectl);
4748
9270388e 4749 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4750 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4751 mdelay(1);
2b4e57bd 4752
91d14251 4753 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4754
7d81c3e0
VS		 4755 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4756 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4757 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4758 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4759 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4760
4761 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4762}
4763
91d14251 4764static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4765{
9270388e
DV		 4766 u16 rgvswctl;
4767
4768 spin_lock_irq(&mchdev_lock);
4769
4770 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4771
4772 /* Ack interrupts, disable EFC interrupt */
4773 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4774 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4775 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4776 I915_WRITE(DEIIR, DE_PCU_EVENT);
4777 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4778
4779 /* Go back to the starting frequency */
91d14251 4780 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4781 mdelay(1);
2b4e57bd
ED		 4782 rgvswctl |= MEMCTL_CMD_STS;
4783 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4784 mdelay(1);
2b4e57bd 4785
9270388e 4786 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4787}
4788
acbe9475
DV		 4789/* There's a funny hw issue where the hw returns all 0 when reading from
4790 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4791 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4792 * all limits and the gpu stuck at whatever frequency it is at atm).
4793 */
74ef1173 4794static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4795{
7b9e0ae6 4796 u32 limits;
2b4e57bd 4797
20b46e59
DV		 4798 /* Only set the down limit when we've reached the lowest level to avoid
4799 * getting more interrupts, otherwise leave this clear. This prevents a
4800 * race in the hw when coming out of rc6: There's a tiny window where
4801 * the hw runs at the minimal clock before selecting the desired
4802 * frequency, if the down threshold expires in that window we will not
4803 * receive a down interrupt. */
2d1fe073 4804 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4805 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4806 if (val <= dev_priv->rps.min_freq_softlimit)
4807 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4808 } else {
4809 limits = dev_priv->rps.max_freq_softlimit << 24;
4810 if (val <= dev_priv->rps.min_freq_softlimit)
4811 limits |= dev_priv->rps.min_freq_softlimit << 16;
4812 }
20b46e59
DV		 4813
4814 return limits;
4815}
4816
dd75fdc8
CW		 4817static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4818{
4819 int new_power;
8a586437
AG		 4820 u32 threshold_up = 0, threshold_down = 0; /* in % */
4821 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4822
4823 new_power = dev_priv->rps.power;
4824 switch (dev_priv->rps.power) {
4825 case LOW_POWER:
a72b5623
CW		 4826 if (val > dev_priv->rps.efficient_freq + 1 &&
4827 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4828 new_power = BETWEEN;
4829 break;
4830
4831 case BETWEEN:
a72b5623
CW		 4832 if (val <= dev_priv->rps.efficient_freq &&
4833 val < dev_priv->rps.cur_freq)
dd75fdc8 4834 new_power = LOW_POWER;
a72b5623
CW		 4835 else if (val >= dev_priv->rps.rp0_freq &&
4836 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4837 new_power = HIGH_POWER;
4838 break;
4839
4840 case HIGH_POWER:
a72b5623
CW		 4841 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4842 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4843 new_power = BETWEEN;
4844 break;
4845 }
4846 /* Max/min bins are special */
aed242ff 4847 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4848 new_power = LOW_POWER;
aed242ff 4849 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4850 new_power = HIGH_POWER;
4851 if (new_power == dev_priv->rps.power)
4852 return;
4853
4854 /* Note the units here are not exactly 1us, but 1280ns. */
4855 switch (new_power) {
4856 case LOW_POWER:
4857 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4858 ei_up = 16000;
4859 threshold_up = 95;
dd75fdc8
CW		 4860
4861 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4862 ei_down = 32000;
4863 threshold_down = 85;
dd75fdc8
CW		 4864 break;
4865
4866 case BETWEEN:
4867 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4868 ei_up = 13000;
4869 threshold_up = 90;
dd75fdc8
CW		 4870
4871 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4872 ei_down = 32000;
4873 threshold_down = 75;
dd75fdc8
CW		 4874 break;
4875
4876 case HIGH_POWER:
4877 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4878 ei_up = 10000;
4879 threshold_up = 85;
dd75fdc8
CW		 4880
4881 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4882 ei_down = 32000;
4883 threshold_down = 60;
dd75fdc8
CW		 4884 break;
4885 }
4886
8a586437 4887 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4888 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4889 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4890 GT_INTERVAL_FROM_US(dev_priv,
4891 ei_up * threshold_up / 100));
8a586437
AG		 4892
4893 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4894 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4895 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4896 GT_INTERVAL_FROM_US(dev_priv,
4897 ei_down * threshold_down / 100));
4898
4899 I915_WRITE(GEN6_RP_CONTROL,
4900 GEN6_RP_MEDIA_TURBO |
4901 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4902 GEN6_RP_MEDIA_IS_GFX |
4903 GEN6_RP_ENABLE |
4904 GEN6_RP_UP_BUSY_AVG |
4905 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4906
dd75fdc8 4907 dev_priv->rps.power = new_power;
8fb55197
CW		 4908 dev_priv->rps.up_threshold = threshold_up;
4909 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4910 dev_priv->rps.last_adj = 0;
4911}
4912
2876ce73
CW		 4913static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4914{
4915 u32 mask = 0;
4916
4917 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4918 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4919 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4920 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4921
7b3c29f6
CW		 4922 mask &= dev_priv->pm_rps_events;
4923
59d02a1f 4924 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4925}
4926
b8a5ff8d
JM		 4927/* gen6_set_rps is called to update the frequency request, but should also be
4928 * called when the range (min_delay and max_delay) is modified so that we can
4929 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4930static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4931{
23eafea6 4932 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4933 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4934 return;
4935
4fc688ce 4936 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4937 WARN_ON(val > dev_priv->rps.max_freq);
4938 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4939
eb64cad1
CW		 4940 /* min/max delay may still have been modified so be sure to
4941 * write the limits value.
4942 */
4943 if (val != dev_priv->rps.cur_freq) {
4944 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4945
dc97997a 4946 if (IS_GEN9(dev_priv))
5704195c
AG		 4947 I915_WRITE(GEN6_RPNSWREQ,
4948 GEN9_FREQUENCY(val));
dc97997a 4949 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4950 I915_WRITE(GEN6_RPNSWREQ,
4951 HSW_FREQUENCY(val));
4952 else
4953 I915_WRITE(GEN6_RPNSWREQ,
4954 GEN6_FREQUENCY(val) |
4955 GEN6_OFFSET(0) |
4956 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4957 }
7b9e0ae6 4958
7b9e0ae6
CW		 4959 /* Make sure we continue to get interrupts
4960 * until we hit the minimum or maximum frequencies.
4961 */
74ef1173 4962 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4963 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4964
d5570a72
BW		 4965 POSTING_READ(GEN6_RPNSWREQ);
4966
b39fb297 4967 dev_priv->rps.cur_freq = val;
0f94592e 4968 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4969}
4970
dc97997a 4971static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4972{
ffe02b40 4973 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4974 WARN_ON(val > dev_priv->rps.max_freq);
4975 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4976
dc97997a 4977 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4978 "Odd GPU freq value\n"))
4979 val &= ~1;
4980
cd25dd5b
D		 4981 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4982
8fb55197 4983 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4984 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4985 if (!IS_CHERRYVIEW(dev_priv))
4986 gen6_set_rps_thresholds(dev_priv, val);
4987 }
ffe02b40 4988
ffe02b40
VS		 4989 dev_priv->rps.cur_freq = val;
4990 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4991}
4992
a7f6e231 4993/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4994 *
4995 * * If Gfx is Idle, then
a7f6e231
D		 4996 * 1. Forcewake Media well.
4997 * 2. Request idle freq.
4998 * 3. Release Forcewake of Media well.
76c3552f
D		 4999*/
5000static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5001{
aed242ff 5002 u32 val = dev_priv->rps.idle_freq;
5549d25f 5003
aed242ff 5004 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5005 return;
5006
a7f6e231
D		 5007 /* Wake up the media well, as that takes a lot less
5008 * power than the Render well. */
5009 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5010 valleyview_set_rps(dev_priv, val);
a7f6e231 5011 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5012}
5013
43cf3bf0
CW		 5014void gen6_rps_busy(struct drm_i915_private *dev_priv)
5015{
5016 mutex_lock(&dev_priv->rps.hw_lock);
5017 if (dev_priv->rps.enabled) {
5018 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5019 gen6_rps_reset_ei(dev_priv);
5020 I915_WRITE(GEN6_PMINTRMSK,
5021 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5022
c33d247d
CW		 5023 gen6_enable_rps_interrupts(dev_priv);
5024
2b83c4c4
MW		 5025 /* Ensure we start at the user's desired frequency */
5026 intel_set_rps(dev_priv,
5027 clamp(dev_priv->rps.cur_freq,
5028 dev_priv->rps.min_freq_softlimit,
5029 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5030 }
5031 mutex_unlock(&dev_priv->rps.hw_lock);
5032}
5033
b29c19b6
CW		 5034void gen6_rps_idle(struct drm_i915_private *dev_priv)
5035{
c33d247d
CW		 5036 /* Flush our bottom-half so that it does not race with us
5037 * setting the idle frequency and so that it is bounded by
5038 * our rpm wakeref. And then disable the interrupts to stop any
5039 * futher RPS reclocking whilst we are asleep.
5040 */
5041 gen6_disable_rps_interrupts(dev_priv);
5042
b29c19b6 5043 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5044 if (dev_priv->rps.enabled) {
dc97997a 5045 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5046 vlv_set_rps_idle(dev_priv);
7526ed79 5047 else
dc97997a 5048 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5049 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5050 I915_WRITE(GEN6_PMINTRMSK,
5051 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5052 }
8d3afd7d 5053 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5054
8d3afd7d 5055 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5056 while (!list_empty(&dev_priv->rps.clients))
5057 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5058 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5059}
5060
1854d5ca 5061void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5062 struct intel_rps_client *rps,
5063 unsigned long submitted)
b29c19b6 5064{
8d3afd7d
CW		 5065 /* This is intentionally racy! We peek at the state here, then
5066 * validate inside the RPS worker.
5067 */
67d97da3 5068 if (!(dev_priv->gt.awake &&
8d3afd7d 5069 dev_priv->rps.enabled &&
29ecd78d 5070 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5071 return;
43cf3bf0 5072
e61b9958
CW		 5073 /* Force a RPS boost (and don't count it against the client) if
5074 * the GPU is severely congested.
5075 */
d0bc54f2 5076 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5077 rps = NULL;
5078
8d3afd7d
CW		 5079 spin_lock(&dev_priv->rps.client_lock);
5080 if (rps == NULL || list_empty(&rps->link)) {
5081 spin_lock_irq(&dev_priv->irq_lock);
5082 if (dev_priv->rps.interrupts_enabled) {
5083 dev_priv->rps.client_boost = true;
c33d247d 5084 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5085 }
5086 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5087
2e1b8730
CW		 5088 if (rps != NULL) {
5089 list_add(&rps->link, &dev_priv->rps.clients);
5090 rps->boosts++;
1854d5ca
CW		 5091 } else
5092 dev_priv->rps.boosts++;
c0951f0c 5093 }
8d3afd7d 5094 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5095}
5096
dc97997a 5097void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5098{
dc97997a
CW		 5099 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5100 valleyview_set_rps(dev_priv, val);
ffe02b40 5101 else
dc97997a 5102 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5103}
5104
dc97997a 5105static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5106{
20e49366 5107 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5108 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5109}
5110
dc97997a 5111static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5112{
2030d684
AG		 5113 I915_WRITE(GEN6_RP_CONTROL, 0);
5114}
5115
dc97997a 5116static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5117{
d20d4f0c 5118 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5119 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5120 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5121}
5122
dc97997a 5123static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5124{
38807746
D		 5125 I915_WRITE(GEN6_RC_CONTROL, 0);
5126}
5127
dc97997a 5128static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5129{
98a2e5f9
D		 5130 /* we're doing forcewake before Disabling RC6,
5131 * This what the BIOS expects when going into suspend */
59bad947 5132 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5133
44fc7d5c 5134 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5135
59bad947 5136 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5137}
5138
dc97997a 5139static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5140{
dc97997a 5141 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5142 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5143 mode = GEN6_RC_CTL_RC6_ENABLE;
5144 else
5145 mode = 0;
5146 }
dc97997a 5147 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5148 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5149 "RC6 %s RC6p %s RC6pp %s\n",
5150 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5151 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5152 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5153
5154 else
b99d49cc
ID		 5155 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5156 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5157}
5158
dc97997a 5159static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5160{
72e96d64 5161 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5162 bool enable_rc6 = true;
5163 unsigned long rc6_ctx_base;
fc619841
ID		 5164 u32 rc_ctl;
5165 int rc_sw_target;
5166
5167 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5168 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5169 RC_SW_TARGET_STATE_SHIFT;
5170 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5171 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5172 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5173 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5174 rc_sw_target);
274008e8
SAK		 5175
5176 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5177 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5178 enable_rc6 = false;
5179 }
5180
5181 /*
5182 * The exact context size is not known for BXT, so assume a page size
5183 * for this check.
5184 */
5185 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5186 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5187 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5188 ggtt->stolen_reserved_size))) {
b99d49cc 5189 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5190 enable_rc6 = false;
5191 }
5192
5193 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5194 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5195 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5196 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5197 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5198 enable_rc6 = false;
5199 }
5200
fc619841
ID		 5201 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5202 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5203 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5204 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5205 enable_rc6 = false;
5206 }
5207
5208 if (!I915_READ(GEN6_GFXPAUSE)) {
5209 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5210 enable_rc6 = false;
5211 }
5212
5213 if (!I915_READ(GEN8_MISC_CTRL0)) {
5214 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5215 enable_rc6 = false;
5216 }
5217
5218 return enable_rc6;
5219}
5220
dc97997a 5221int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5222{
e7d66d89 5223 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5224 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5225 return 0;
5226
274008e8
SAK		 5227 if (!enable_rc6)
5228 return 0;
5229
dc97997a 5230 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5231 DRM_INFO("RC6 disabled by BIOS\n");
5232 return 0;
5233 }
5234
456470eb 5235 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5236 if (enable_rc6 >= 0) {
5237 int mask;
5238
dc97997a 5239 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5240 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5241 INTEL_RC6pp_ENABLE;
5242 else
5243 mask = INTEL_RC6_ENABLE;
5244
5245 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5246 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5247 "(requested %d, valid %d)\n",
5248 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5249
5250 return enable_rc6 & mask;
5251 }
2b4e57bd 5252
dc97997a 5253 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5254 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5255
5256 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5257}
5258
dc97997a 5259static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5260{
5261 /* All of these values are in units of 50MHz */
773ea9a8 5262
93ee2920 5263 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5264 if (IS_BROXTON(dev_priv)) {
773ea9a8 5265 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5266 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5267 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5268 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5269 } else {
773ea9a8 5270 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5271 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5272 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5273 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5274 }
3280e8b0 5275 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5276 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5277
93ee2920 5278 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5279 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5280 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5281 u32 ddcc_status = 0;
5282
5283 if (sandybridge_pcode_read(dev_priv,
5284 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5285 &ddcc_status) == 0)
93ee2920 5286 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5287 clamp_t(u8,
5288 ((ddcc_status >> 8) & 0xff),
5289 dev_priv->rps.min_freq,
5290 dev_priv->rps.max_freq);
93ee2920
TR		 5291 }
5292
dc97997a 5293 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5294 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5295 * the natural hardware unit for SKL
5296 */
c5e0688c
AG		 5297 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5298 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5299 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5300 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5301 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5302 }
3280e8b0
BW		 5303}
5304
3a45b05c
CW		 5305static void reset_rps(struct drm_i915_private *dev_priv,
5306 void (*set)(struct drm_i915_private *, u8))
5307{
5308 u8 freq = dev_priv->rps.cur_freq;
5309
5310 /* force a reset */
5311 dev_priv->rps.power = -1;
5312 dev_priv->rps.cur_freq = -1;
5313
5314 set(dev_priv, freq);
5315}
5316
b6fef0ef 5317/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5318static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5319{
b6fef0ef
JB		 5320 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5321
23eafea6 5322 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5323 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5324 /*
5325 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5326 * clear out the Control register just to avoid inconsitency
5327 * with debugfs interface, which will show Turbo as enabled
5328 * only and that is not expected by the User after adding the
5329 * WaGsvDisableTurbo. Apart from this there is no problem even
5330 * if the Turbo is left enabled in the Control register, as the
5331 * Up/Down interrupts would remain masked.
5332 */
dc97997a 5333 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5334 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5335 return;
5336 }
5337
0beb059a
AG		 5338 /* Program defaults and thresholds for RPS*/
5339 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5340 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5341
5342 /* 1 second timeout*/
5343 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5344 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5345
b6fef0ef 5346 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5347
0beb059a
AG		 5348 /* Leaning on the below call to gen6_set_rps to program/setup the
5349 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5350 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5351 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5352
5353 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5354}
5355
dc97997a 5356static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5357{
e2f80391 5358 struct intel_engine_cs *engine;
3b3f1650 5359 enum intel_engine_id id;
20e49366 5360 uint32_t rc6_mask = 0;
20e49366
ZW		 5361
5362 /* 1a: Software RC state - RC0 */
5363 I915_WRITE(GEN6_RC_STATE, 0);
5364
5365 /* 1b: Get forcewake during program sequence. Although the driver
5366 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5367 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5368
5369 /* 2a: Disable RC states. */
5370 I915_WRITE(GEN6_RC_CONTROL, 0);
5371
5372 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5373
5374 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5375 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5376 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5377 else
5378 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5379 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5380 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5381 for_each_engine(engine, dev_priv, id)
e2f80391 5382 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5383
1a3d1898 5384 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5385 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5386
20e49366 5387 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5388
38c23527
ZW		 5389 /* 2c: Program Coarse Power Gating Policies. */
5390 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5391 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5392
20e49366 5393 /* 3a: Enable RC6 */
dc97997a 5394 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5395 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5396 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5397 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5398 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5399 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5400 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5401 GEN7_RC_CTL_TO_MODE |
5402 rc6_mask);
3e7732a0
SAK		 5403 } else {
5404 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5405 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5406 GEN6_RC_CTL_EI_MODE(1) |
5407 rc6_mask);
3e7732a0 5408 }
20e49366 5409
cb07bae0
SK		 5410 /*
5411 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5412 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5413 */
dc97997a 5414 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5415 I915_WRITE(GEN9_PG_ENABLE, 0);
5416 else
5417 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5418 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5419
59bad947 5420 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5421}
5422
dc97997a 5423static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5424{
e2f80391 5425 struct intel_engine_cs *engine;
3b3f1650 5426 enum intel_engine_id id;
93ee2920 5427 uint32_t rc6_mask = 0;
6edee7f3
BW		 5428
5429 /* 1a: Software RC state - RC0 */
5430 I915_WRITE(GEN6_RC_STATE, 0);
5431
5432 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5433 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5434 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5435
5436 /* 2a: Disable RC states. */
5437 I915_WRITE(GEN6_RC_CONTROL, 0);
5438
6edee7f3
BW		 5439 /* 2b: Program RC6 thresholds.*/
5440 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5441 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5442 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5443 for_each_engine(engine, dev_priv, id)
e2f80391 5444 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5445 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5446 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5447 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5448 else
5449 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5450
5451 /* 3: Enable RC6 */
dc97997a 5452 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5453 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5454 intel_print_rc6_info(dev_priv, rc6_mask);
5455 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5456 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5457 GEN7_RC_CTL_TO_MODE |
5458 rc6_mask);
5459 else
5460 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5461 GEN6_RC_CTL_EI_MODE(1) |
5462 rc6_mask);
6edee7f3
BW		 5463
5464 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5465 I915_WRITE(GEN6_RPNSWREQ,
5466 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5467 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5468 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5469 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5470 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5471
5472 /* Docs recommend 900MHz, and 300 MHz respectively */
5473 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5474 dev_priv->rps.max_freq_softlimit << 24 |
5475 dev_priv->rps.min_freq_softlimit << 16);
5476
5477 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5478 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5479 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5480 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5481
5482 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5483
5484 /* 5: Enable RPS */
7526ed79
DV		 5485 I915_WRITE(GEN6_RP_CONTROL,
5486 GEN6_RP_MEDIA_TURBO |
5487 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5488 GEN6_RP_MEDIA_IS_GFX |
5489 GEN6_RP_ENABLE |
5490 GEN6_RP_UP_BUSY_AVG |
5491 GEN6_RP_DOWN_IDLE_AVG);
5492
5493 /* 6: Ring frequency + overclocking (our driver does this later */
5494
3a45b05c 5495 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5496
59bad947 5497 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5498}
5499
dc97997a 5500static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5501{
e2f80391 5502 struct intel_engine_cs *engine;
3b3f1650 5503 enum intel_engine_id id;
99ac9612 5504 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5505 u32 gtfifodbg;
2b4e57bd 5506 int rc6_mode;
b4ac5afc 5507 int ret;
2b4e57bd 5508
4fc688ce 5509 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5510
2b4e57bd
ED		 5511 /* Here begins a magic sequence of register writes to enable
5512 * auto-downclocking.
5513 *
5514 * Perhaps there might be some value in exposing these to
5515 * userspace...
5516 */
5517 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5518
5519 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5520 gtfifodbg = I915_READ(GTFIFODBG);
5521 if (gtfifodbg) {
2b4e57bd
ED		 5522 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5523 I915_WRITE(GTFIFODBG, gtfifodbg);
5524 }
5525
59bad947 5526 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5527
5528 /* disable the counters and set deterministic thresholds */
5529 I915_WRITE(GEN6_RC_CONTROL, 0);
5530
5531 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5532 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5533 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5534 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5535 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5536
3b3f1650 5537 for_each_engine(engine, dev_priv, id)
e2f80391 5538 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5539
5540 I915_WRITE(GEN6_RC_SLEEP, 0);
5541 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5542 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5543 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5544 else
5545 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5546 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5547 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5548
5a7dc92a 5549 /* Check if we are enabling RC6 */
dc97997a 5550 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5551 if (rc6_mode & INTEL_RC6_ENABLE)
5552 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5553
5a7dc92a 5554 /* We don't use those on Haswell */
dc97997a 5555 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5556 if (rc6_mode & INTEL_RC6p_ENABLE)
5557 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5558
5a7dc92a
ED		 5559 if (rc6_mode & INTEL_RC6pp_ENABLE)
5560 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5561 }
2b4e57bd 5562
dc97997a 5563 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5564
5565 I915_WRITE(GEN6_RC_CONTROL,
5566 rc6_mask |
5567 GEN6_RC_CTL_EI_MODE(1) |
5568 GEN6_RC_CTL_HW_ENABLE);
5569
dd75fdc8
CW		 5570 /* Power down if completely idle for over 50ms */
5571 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5572 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5573
3a45b05c 5574 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5575
31643d54
BW		 5576 rc6vids = 0;
5577 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5578 if (IS_GEN6(dev_priv) && ret) {
31643d54 5579 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5580 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5581 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5582 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5583 rc6vids &= 0xffff00;
5584 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5585 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5586 if (ret)
5587 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5588 }
5589
59bad947 5590 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5591}
5592
fb7404e8 5593static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5594{
5595 int min_freq = 15;
3ebecd07
CW		 5596 unsigned int gpu_freq;
5597 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5598 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5599 int scaling_factor = 180;
eda79642 5600 struct cpufreq_policy *policy;
2b4e57bd 5601
4fc688ce 5602 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5603
eda79642
BW		 5604 policy = cpufreq_cpu_get(0);
5605 if (policy) {
5606 max_ia_freq = policy->cpuinfo.max_freq;
5607 cpufreq_cpu_put(policy);
5608 } else {
5609 /*
5610 * Default to measured freq if none found, PCU will ensure we
5611 * don't go over
5612 */
2b4e57bd 5613 max_ia_freq = tsc_khz;
eda79642 5614 }
2b4e57bd
ED		 5615
5616 /* Convert from kHz to MHz */
5617 max_ia_freq /= 1000;
5618
153b4b95 5619 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5620 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5621 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5622
dc97997a 5623 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5624 /* Convert GT frequency to 50 HZ units */
5625 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5626 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5627 } else {
5628 min_gpu_freq = dev_priv->rps.min_freq;
5629 max_gpu_freq = dev_priv->rps.max_freq;
5630 }
5631
2b4e57bd
ED		 5632 /*
5633 * For each potential GPU frequency, load a ring frequency we'd like
5634 * to use for memory access. We do this by specifying the IA frequency
5635 * the PCU should use as a reference to determine the ring frequency.
5636 */
4c8c7743
AG		 5637 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5638 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5639 unsigned int ia_freq = 0, ring_freq = 0;
5640
dc97997a 5641 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5642 /*
5643 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5644 * No floor required for ring frequency on SKL.
5645 */
5646 ring_freq = gpu_freq;
dc97997a 5647 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5648 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5649 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5650 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5651 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5652 ring_freq = max(min_ring_freq, ring_freq);
5653 /* leave ia_freq as the default, chosen by cpufreq */
5654 } else {
5655 /* On older processors, there is no separate ring
5656 * clock domain, so in order to boost the bandwidth
5657 * of the ring, we need to upclock the CPU (ia_freq).
5658 *
5659 * For GPU frequencies less than 750MHz,
5660 * just use the lowest ring freq.
5661 */
5662 if (gpu_freq < min_freq)
5663 ia_freq = 800;
5664 else
5665 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5666 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5667 }
2b4e57bd 5668
42c0526c
BW		 5669 sandybridge_pcode_write(dev_priv,
5670 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5671 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5672 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5673 gpu_freq);
2b4e57bd 5674 }
2b4e57bd
ED		 5675}
5676
03af2045 5677static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5678{
5679 u32 val, rp0;
5680
5b5929cb 5681 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5682
43b67998 5683 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5684 case 8:
5685 /* (2 * 4) config */
5686 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5687 break;
5688 case 12:
5689 /* (2 * 6) config */
5690 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5691 break;
5692 case 16:
5693 /* (2 * 8) config */
5694 default:
5695 /* Setting (2 * 8) Min RP0 for any other combination */
5696 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5697 break;
095acd5f 5698 }
5b5929cb
JN		 5699
5700 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5701
2b6b3a09
D		 5702 return rp0;
5703}
5704
5705static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5706{
5707 u32 val, rpe;
5708
5709 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5710 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5711
5712 return rpe;
5713}
5714
7707df4a
D		 5715static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5716{
5717 u32 val, rp1;
5718
5b5929cb
JN		 5719 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5720 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5721
7707df4a
D		 5722 return rp1;
5723}
5724
f8f2b001
D		 5725static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5726{
5727 u32 val, rp1;
5728
5729 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5730
5731 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5732
5733 return rp1;
5734}
5735
03af2045 5736static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5737{
5738 u32 val, rp0;
5739
64936258 5740 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5741
5742 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5743 /* Clamp to max */
5744 rp0 = min_t(u32, rp0, 0xea);
5745
5746 return rp0;
5747}
5748
5749static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5750{
5751 u32 val, rpe;
5752
64936258 5753 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5754 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5755 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5756 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5757
5758 return rpe;
5759}
5760
03af2045 5761static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5762{
36146035
ID		 5763 u32 val;
5764
5765 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5766 /*
5767 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5768 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5769 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5770 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5771 * to make sure it matches what Punit accepts.
5772 */
5773 return max_t(u32, val, 0xc0);
0a073b84
JB		 5774}
5775
ae48434c
ID		 5776/* Check that the pctx buffer wasn't move under us. */
5777static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5778{
5779 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5780
5781 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5782 dev_priv->vlv_pctx->stolen->start);
5783}
5784
38807746
D		 5785
5786/* Check that the pcbr address is not empty. */
5787static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5788{
5789 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5790
5791 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5792}
5793
dc97997a 5794static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5795{
62106b4f 5796 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5797 unsigned long pctx_paddr, paddr;
38807746
D		 5798 u32 pcbr;
5799 int pctx_size = 32*1024;
5800
38807746
D		 5801 pcbr = I915_READ(VLV_PCBR);
5802 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5803 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5804 paddr = (dev_priv->mm.stolen_base +
62106b4f 5805 (ggtt->stolen_size - pctx_size));
38807746
D		 5806
5807 pctx_paddr = (paddr & (~4095));
5808 I915_WRITE(VLV_PCBR, pctx_paddr);
5809 }
ce611ef8
VS		 5810
5811 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5812}
5813
dc97997a 5814static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5815{
c9cddffc
JB		 5816 struct drm_i915_gem_object *pctx;
5817 unsigned long pctx_paddr;
5818 u32 pcbr;
5819 int pctx_size = 24*1024;
5820
5821 pcbr = I915_READ(VLV_PCBR);
5822 if (pcbr) {
5823 /* BIOS set it up already, grab the pre-alloc'd space */
5824 int pcbr_offset;
5825
5826 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5827 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5828 pcbr_offset,
190d6cd5 5829 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5830 pctx_size);
5831 goto out;
5832 }
5833
ce611ef8
VS		 5834 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5835
c9cddffc
JB		 5836 /*
5837 * From the Gunit register HAS:
5838 * The Gfx driver is expected to program this register and ensure
5839 * proper allocation within Gfx stolen memory. For example, this
5840 * register should be programmed such than the PCBR range does not
5841 * overlap with other ranges, such as the frame buffer, protected
5842 * memory, or any other relevant ranges.
5843 */
91c8a326 5844 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5845 if (!pctx) {
5846 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5847 goto out;
c9cddffc
JB		 5848 }
5849
5850 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5851 I915_WRITE(VLV_PCBR, pctx_paddr);
5852
5853out:
ce611ef8 5854 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5855 dev_priv->vlv_pctx = pctx;
5856}
5857
dc97997a 5858static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5859{
ae48434c
ID		 5860 if (WARN_ON(!dev_priv->vlv_pctx))
5861 return;
5862
f0cd5182 5863 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5864 dev_priv->vlv_pctx = NULL;
5865}
5866
c30fec65
VS		 5867static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5868{
5869 dev_priv->rps.gpll_ref_freq =
5870 vlv_get_cck_clock(dev_priv, "GPLL ref",
5871 CCK_GPLL_CLOCK_CONTROL,
5872 dev_priv->czclk_freq);
5873
5874 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5875 dev_priv->rps.gpll_ref_freq);
5876}
5877
dc97997a 5878static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5879{
2bb25c17 5880 u32 val;
4e80519e 5881
dc97997a 5882 valleyview_setup_pctx(dev_priv);
4e80519e 5883
c30fec65
VS		 5884 vlv_init_gpll_ref_freq(dev_priv);
5885
2bb25c17
VS		 5886 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5887 switch ((val >> 6) & 3) {
5888 case 0:
5889 case 1:
5890 dev_priv->mem_freq = 800;
5891 break;
5892 case 2:
5893 dev_priv->mem_freq = 1066;
5894 break;
5895 case 3:
5896 dev_priv->mem_freq = 1333;
5897 break;
5898 }
80b83b62 5899 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5900
4e80519e
ID		 5901 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5902 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5903 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5904 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5905 dev_priv->rps.max_freq);
5906
5907 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5908 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5909 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5910 dev_priv->rps.efficient_freq);
5911
f8f2b001
D		 5912 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5913 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5914 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5915 dev_priv->rps.rp1_freq);
5916
4e80519e
ID		 5917 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5918 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5919 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5920 dev_priv->rps.min_freq);
4e80519e
ID		 5921}
5922
dc97997a 5923static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5924{
2bb25c17 5925 u32 val;
2b6b3a09 5926
dc97997a 5927 cherryview_setup_pctx(dev_priv);
2b6b3a09 5928
c30fec65
VS		 5929 vlv_init_gpll_ref_freq(dev_priv);
5930
a580516d 5931 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5932 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5933 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5934
2bb25c17 5935 switch ((val >> 2) & 0x7) {
2bb25c17 5936 case 3:
2bb25c17
VS		 5937 dev_priv->mem_freq = 2000;
5938 break;
bfa7df01 5939 default:
2bb25c17
VS		 5940 dev_priv->mem_freq = 1600;
5941 break;
5942 }
80b83b62 5943 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5944
2b6b3a09
D		 5945 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5946 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5947 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5948 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5949 dev_priv->rps.max_freq);
5950
5951 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5952 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5953 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5954 dev_priv->rps.efficient_freq);
5955
7707df4a
D		 5956 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5957 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5958 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5959 dev_priv->rps.rp1_freq);
5960
5b7c91b7
D		 5961 /* PUnit validated range is only [RPe, RP0] */
5962 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5963 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5964 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5965 dev_priv->rps.min_freq);
5966
1c14762d
VS		 5967 WARN_ONCE((dev_priv->rps.max_freq |
5968 dev_priv->rps.efficient_freq |
5969 dev_priv->rps.rp1_freq |
5970 dev_priv->rps.min_freq) & 1,
5971 "Odd GPU freq values\n");
38807746
D		 5972}
5973
dc97997a 5974static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5975{
dc97997a 5976 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5977}
5978
dc97997a 5979static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5980{
e2f80391 5981 struct intel_engine_cs *engine;
3b3f1650 5982 enum intel_engine_id id;
2b6b3a09 5983 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5984
5985 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5986
297b32ec
VS		 5987 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5988 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5989 if (gtfifodbg) {
5990 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5991 gtfifodbg);
5992 I915_WRITE(GTFIFODBG, gtfifodbg);
5993 }
5994
5995 cherryview_check_pctx(dev_priv);
5996
5997 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5998 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5999 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6000
160614a2
VS		 6001 /* Disable RC states. */
6002 I915_WRITE(GEN6_RC_CONTROL, 0);
6003
38807746
D		 6004 /* 2a: Program RC6 thresholds.*/
6005 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6006 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6007 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6008
3b3f1650 6009 for_each_engine(engine, dev_priv, id)
e2f80391 6010 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6011 I915_WRITE(GEN6_RC_SLEEP, 0);
6012
f4f71c7d
D		 6013 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6014 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6015
6016 /* allows RC6 residency counter to work */
6017 I915_WRITE(VLV_COUNTER_CONTROL,
6018 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6019 VLV_MEDIA_RC6_COUNT_EN |
6020 VLV_RENDER_RC6_COUNT_EN));
6021
6022 /* For now we assume BIOS is allocating and populating the PCBR */
6023 pcbr = I915_READ(VLV_PCBR);
6024
38807746 6025 /* 3: Enable RC6 */
dc97997a
CW		 6026 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6027 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6028 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6029
6030 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6031
2b6b3a09 6032 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6033 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6034 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6035 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6036 I915_WRITE(GEN6_RP_UP_EI, 66000);
6037 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6038
6039 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6040
6041 /* 5: Enable RPS */
6042 I915_WRITE(GEN6_RP_CONTROL,
6043 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6044 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6045 GEN6_RP_ENABLE |
6046 GEN6_RP_UP_BUSY_AVG |
6047 GEN6_RP_DOWN_IDLE_AVG);
6048
3ef62342
D		 6049 /* Setting Fixed Bias */
6050 val = VLV_OVERRIDE_EN |
6051 VLV_SOC_TDP_EN |
6052 CHV_BIAS_CPU_50_SOC_50;
6053 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6054
2b6b3a09
D		 6055 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6056
8d40c3ae
VS		 6057 /* RPS code assumes GPLL is used */
6058 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6059
742f491d 6060 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6061 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6062
3a45b05c 6063 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6064
59bad947 6065 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6066}
6067
dc97997a 6068static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6069{
e2f80391 6070 struct intel_engine_cs *engine;
3b3f1650 6071 enum intel_engine_id id;
2a5913a8 6072 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6073
6074 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6075
ae48434c
ID		 6076 valleyview_check_pctx(dev_priv);
6077
297b32ec
VS		 6078 gtfifodbg = I915_READ(GTFIFODBG);
6079 if (gtfifodbg) {
f7d85c1e
JB		 6080 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6081 gtfifodbg);
0a073b84
JB		 6082 I915_WRITE(GTFIFODBG, gtfifodbg);
6083 }
6084
c8d9a590 6085 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6086 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6087
160614a2
VS		 6088 /* Disable RC states. */
6089 I915_WRITE(GEN6_RC_CONTROL, 0);
6090
cad725fe 6091 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6092 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6093 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6094 I915_WRITE(GEN6_RP_UP_EI, 66000);
6095 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6096
6097 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6098
6099 I915_WRITE(GEN6_RP_CONTROL,
6100 GEN6_RP_MEDIA_TURBO |
6101 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6102 GEN6_RP_MEDIA_IS_GFX |
6103 GEN6_RP_ENABLE |
6104 GEN6_RP_UP_BUSY_AVG |
6105 GEN6_RP_DOWN_IDLE_CONT);
6106
6107 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6108 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6109 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6110
3b3f1650 6111 for_each_engine(engine, dev_priv, id)
e2f80391 6112 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6113
2f0aa304 6114 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6115
6116 /* allows RC6 residency counter to work */
49798eb2 6117 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6118 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6119 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6120 VLV_MEDIA_RC6_COUNT_EN |
6121 VLV_RENDER_RC6_COUNT_EN));
31685c25 6122
dc97997a 6123 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6124 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6125
dc97997a 6126 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6127
a2b23fe0 6128 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6129
3ef62342
D		 6130 /* Setting Fixed Bias */
6131 val = VLV_OVERRIDE_EN |
6132 VLV_SOC_TDP_EN |
6133 VLV_BIAS_CPU_125_SOC_875;
6134 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6135
64936258 6136 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6137
8d40c3ae
VS		 6138 /* RPS code assumes GPLL is used */
6139 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6140
742f491d 6141 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6142 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6143
3a45b05c 6144 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6145
59bad947 6146 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6147}
6148
dde18883
ED		 6149static unsigned long intel_pxfreq(u32 vidfreq)
6150{
6151 unsigned long freq;
6152 int div = (vidfreq & 0x3f0000) >> 16;
6153 int post = (vidfreq & 0x3000) >> 12;
6154 int pre = (vidfreq & 0x7);
6155
6156 if (!pre)
6157 return 0;
6158
6159 freq = ((div * 133333) / ((1<<post) * pre));
6160
6161 return freq;
6162}
6163
eb48eb00
DV		 6164static const struct cparams {
6165 u16 i;
6166 u16 t;
6167 u16 m;
6168 u16 c;
6169} cparams[] = {
6170 { 1, 1333, 301, 28664 },
6171 { 1, 1066, 294, 24460 },
6172 { 1, 800, 294, 25192 },
6173 { 0, 1333, 276, 27605 },
6174 { 0, 1066, 276, 27605 },
6175 { 0, 800, 231, 23784 },
6176};
6177
f531dcb2 6178static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6179{
6180 u64 total_count, diff, ret;
6181 u32 count1, count2, count3, m = 0, c = 0;
6182 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6183 int i;
6184
02d71956
DV		 6185 assert_spin_locked(&mchdev_lock);
6186
20e4d407 6187 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6188
6189 /* Prevent division-by-zero if we are asking too fast.
6190 * Also, we don't get interesting results if we are polling
6191 * faster than once in 10ms, so just return the saved value
6192 * in such cases.
6193 */
6194 if (diff1 <= 10)
20e4d407 6195 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6196
6197 count1 = I915_READ(DMIEC);
6198 count2 = I915_READ(DDREC);
6199 count3 = I915_READ(CSIEC);
6200
6201 total_count = count1 + count2 + count3;
6202
6203 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6204 if (total_count < dev_priv->ips.last_count1) {
6205 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6206 diff += total_count;
6207 } else {
20e4d407 6208 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6209 }
6210
6211 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6212 if (cparams[i].i == dev_priv->ips.c_m &&
6213 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6214 m = cparams[i].m;
6215 c = cparams[i].c;
6216 break;
6217 }
6218 }
6219
6220 diff = div_u64(diff, diff1);
6221 ret = ((m * diff) + c);
6222 ret = div_u64(ret, 10);
6223
20e4d407
DV		 6224 dev_priv->ips.last_count1 = total_count;
6225 dev_priv->ips.last_time1 = now;
eb48eb00 6226
20e4d407 6227 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6228
6229 return ret;
6230}
6231
f531dcb2
CW		 6232unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6233{
6234 unsigned long val;
6235
dc97997a 6236 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6237 return 0;
6238
6239 spin_lock_irq(&mchdev_lock);
6240
6241 val = __i915_chipset_val(dev_priv);
6242
6243 spin_unlock_irq(&mchdev_lock);
6244
6245 return val;
6246}
6247
eb48eb00
DV		 6248unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6249{
6250 unsigned long m, x, b;
6251 u32 tsfs;
6252
6253 tsfs = I915_READ(TSFS);
6254
6255 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6256 x = I915_READ8(TR1);
6257
6258 b = tsfs & TSFS_INTR_MASK;
6259
6260 return ((m * x) / 127) - b;
6261}
6262
d972d6ee
MK		 6263static int _pxvid_to_vd(u8 pxvid)
6264{
6265 if (pxvid == 0)
6266 return 0;
6267
6268 if (pxvid >= 8 && pxvid < 31)
6269 pxvid = 31;
6270
6271 return (pxvid + 2) * 125;
6272}
6273
6274static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6275{
d972d6ee
MK		 6276 const int vd = _pxvid_to_vd(pxvid);
6277 const int vm = vd - 1125;
6278
dc97997a 6279 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6280 return vm > 0 ? vm : 0;
6281
6282 return vd;
eb48eb00
DV		 6283}
6284
02d71956 6285static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6286{
5ed0bdf2 6287 u64 now, diff, diffms;
eb48eb00
DV		 6288 u32 count;
6289
02d71956 6290 assert_spin_locked(&mchdev_lock);
eb48eb00 6291
5ed0bdf2
TG		 6292 now = ktime_get_raw_ns();
6293 diffms = now - dev_priv->ips.last_time2;
6294 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6295
6296 /* Don't divide by 0 */
eb48eb00
DV		 6297 if (!diffms)
6298 return;
6299
6300 count = I915_READ(GFXEC);
6301
20e4d407
DV		 6302 if (count < dev_priv->ips.last_count2) {
6303 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6304 diff += count;
6305 } else {
20e4d407 6306 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6307 }
6308
20e4d407
DV		 6309 dev_priv->ips.last_count2 = count;
6310 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6311
6312 /* More magic constants... */
6313 diff = diff * 1181;
6314 diff = div_u64(diff, diffms * 10);
20e4d407 6315 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6316}
6317
02d71956
DV		 6318void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6319{
dc97997a 6320 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6321 return;
6322
9270388e 6323 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6324
6325 __i915_update_gfx_val(dev_priv);
6326
9270388e 6327 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6328}
6329
f531dcb2 6330static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6331{
6332 unsigned long t, corr, state1, corr2, state2;
6333 u32 pxvid, ext_v;
6334
02d71956
DV		 6335 assert_spin_locked(&mchdev_lock);
6336
616847e7 6337 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6338 pxvid = (pxvid >> 24) & 0x7f;
6339 ext_v = pvid_to_extvid(dev_priv, pxvid);
6340
6341 state1 = ext_v;
6342
6343 t = i915_mch_val(dev_priv);
6344
6345 /* Revel in the empirically derived constants */
6346
6347 /* Correction factor in 1/100000 units */
6348 if (t > 80)
6349 corr = ((t * 2349) + 135940);
6350 else if (t >= 50)
6351 corr = ((t * 964) + 29317);
6352 else /* < 50 */
6353 corr = ((t * 301) + 1004);
6354
6355 corr = corr * ((150142 * state1) / 10000 - 78642);
6356 corr /= 100000;
20e4d407 6357 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6358
6359 state2 = (corr2 * state1) / 10000;
6360 state2 /= 100; /* convert to mW */
6361
02d71956 6362 __i915_update_gfx_val(dev_priv);
eb48eb00 6363
20e4d407 6364 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6365}
6366
f531dcb2
CW		 6367unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6368{
6369 unsigned long val;
6370
dc97997a 6371 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6372 return 0;
6373
6374 spin_lock_irq(&mchdev_lock);
6375
6376 val = __i915_gfx_val(dev_priv);
6377
6378 spin_unlock_irq(&mchdev_lock);
6379
6380 return val;
6381}
6382
eb48eb00
DV		 6383/**
6384 * i915_read_mch_val - return value for IPS use
6385 *
6386 * Calculate and return a value for the IPS driver to use when deciding whether
6387 * we have thermal and power headroom to increase CPU or GPU power budget.
6388 */
6389unsigned long i915_read_mch_val(void)
6390{
6391 struct drm_i915_private *dev_priv;
6392 unsigned long chipset_val, graphics_val, ret = 0;
6393
9270388e 6394 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6395 if (!i915_mch_dev)
6396 goto out_unlock;
6397 dev_priv = i915_mch_dev;
6398
f531dcb2
CW		 6399 chipset_val = __i915_chipset_val(dev_priv);
6400 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6401
6402 ret = chipset_val + graphics_val;
6403
6404out_unlock:
9270388e 6405 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6406
6407 return ret;
6408}
6409EXPORT_SYMBOL_GPL(i915_read_mch_val);
6410
6411/**
6412 * i915_gpu_raise - raise GPU frequency limit
6413 *
6414 * Raise the limit; IPS indicates we have thermal headroom.
6415 */
6416bool i915_gpu_raise(void)
6417{
6418 struct drm_i915_private *dev_priv;
6419 bool ret = true;
6420
9270388e 6421 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6422 if (!i915_mch_dev) {
6423 ret = false;
6424 goto out_unlock;
6425 }
6426 dev_priv = i915_mch_dev;
6427
20e4d407
DV		 6428 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6429 dev_priv->ips.max_delay--;
eb48eb00
DV		 6430
6431out_unlock:
9270388e 6432 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6433
6434 return ret;
6435}
6436EXPORT_SYMBOL_GPL(i915_gpu_raise);
6437
6438/**
6439 * i915_gpu_lower - lower GPU frequency limit
6440 *
6441 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6442 * frequency maximum.
6443 */
6444bool i915_gpu_lower(void)
6445{
6446 struct drm_i915_private *dev_priv;
6447 bool ret = true;
6448
9270388e 6449 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6450 if (!i915_mch_dev) {
6451 ret = false;
6452 goto out_unlock;
6453 }
6454 dev_priv = i915_mch_dev;
6455
20e4d407
DV		 6456 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6457 dev_priv->ips.max_delay++;
eb48eb00
DV		 6458
6459out_unlock:
9270388e 6460 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6461
6462 return ret;
6463}
6464EXPORT_SYMBOL_GPL(i915_gpu_lower);
6465
6466/**
6467 * i915_gpu_busy - indicate GPU business to IPS
6468 *
6469 * Tell the IPS driver whether or not the GPU is busy.
6470 */
6471bool i915_gpu_busy(void)
6472{
eb48eb00
DV		 6473 bool ret = false;
6474
9270388e 6475 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6476 if (i915_mch_dev)
6477 ret = i915_mch_dev->gt.awake;
9270388e 6478 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6479
6480 return ret;
6481}
6482EXPORT_SYMBOL_GPL(i915_gpu_busy);
6483
6484/**
6485 * i915_gpu_turbo_disable - disable graphics turbo
6486 *
6487 * Disable graphics turbo by resetting the max frequency and setting the
6488 * current frequency to the default.
6489 */
6490bool i915_gpu_turbo_disable(void)
6491{
6492 struct drm_i915_private *dev_priv;
6493 bool ret = true;
6494
9270388e 6495 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6496 if (!i915_mch_dev) {
6497 ret = false;
6498 goto out_unlock;
6499 }
6500 dev_priv = i915_mch_dev;
6501
20e4d407 6502 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6503
91d14251 6504 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6505 ret = false;
6506
6507out_unlock:
9270388e 6508 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6509
6510 return ret;
6511}
6512EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6513
6514/**
6515 * Tells the intel_ips driver that the i915 driver is now loaded, if
6516 * IPS got loaded first.
6517 *
6518 * This awkward dance is so that neither module has to depend on the
6519 * other in order for IPS to do the appropriate communication of
6520 * GPU turbo limits to i915.
6521 */
6522static void
6523ips_ping_for_i915_load(void)
6524{
6525 void (*link)(void);
6526
6527 link = symbol_get(ips_link_to_i915_driver);
6528 if (link) {
6529 link();
6530 symbol_put(ips_link_to_i915_driver);
6531 }
6532}
6533
6534void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6535{
02d71956
DV		 6536 /* We only register the i915 ips part with intel-ips once everything is
6537 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6538 spin_lock_irq(&mchdev_lock);
eb48eb00 6539 i915_mch_dev = dev_priv;
9270388e 6540 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6541
6542 ips_ping_for_i915_load();
6543}
6544
6545void intel_gpu_ips_teardown(void)
6546{
9270388e 6547 spin_lock_irq(&mchdev_lock);
eb48eb00 6548 i915_mch_dev = NULL;
9270388e 6549 spin_unlock_irq(&mchdev_lock);
eb48eb00 6550}
76c3552f 6551
dc97997a 6552static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6553{
dde18883
ED		 6554 u32 lcfuse;
6555 u8 pxw[16];
6556 int i;
6557
6558 /* Disable to program */
6559 I915_WRITE(ECR, 0);
6560 POSTING_READ(ECR);
6561
6562 /* Program energy weights for various events */
6563 I915_WRITE(SDEW, 0x15040d00);
6564 I915_WRITE(CSIEW0, 0x007f0000);
6565 I915_WRITE(CSIEW1, 0x1e220004);
6566 I915_WRITE(CSIEW2, 0x04000004);
6567
6568 for (i = 0; i < 5; i++)
616847e7 6569 I915_WRITE(PEW(i), 0);
dde18883 6570 for (i = 0; i < 3; i++)
616847e7 6571 I915_WRITE(DEW(i), 0);
dde18883
ED		 6572
6573 /* Program P-state weights to account for frequency power adjustment */
6574 for (i = 0; i < 16; i++) {
616847e7 6575 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6576 unsigned long freq = intel_pxfreq(pxvidfreq);
6577 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6578 PXVFREQ_PX_SHIFT;
6579 unsigned long val;
6580
6581 val = vid * vid;
6582 val *= (freq / 1000);
6583 val *= 255;
6584 val /= (127*127*900);
6585 if (val > 0xff)
6586 DRM_ERROR("bad pxval: %ld\n", val);
6587 pxw[i] = val;
6588 }
6589 /* Render standby states get 0 weight */
6590 pxw[14] = 0;
6591 pxw[15] = 0;
6592
6593 for (i = 0; i < 4; i++) {
6594 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6595 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6596 I915_WRITE(PXW(i), val);
dde18883
ED		 6597 }
6598
6599 /* Adjust magic regs to magic values (more experimental results) */
6600 I915_WRITE(OGW0, 0);
6601 I915_WRITE(OGW1, 0);
6602 I915_WRITE(EG0, 0x00007f00);
6603 I915_WRITE(EG1, 0x0000000e);
6604 I915_WRITE(EG2, 0x000e0000);
6605 I915_WRITE(EG3, 0x68000300);
6606 I915_WRITE(EG4, 0x42000000);
6607 I915_WRITE(EG5, 0x00140031);
6608 I915_WRITE(EG6, 0);
6609 I915_WRITE(EG7, 0);
6610
6611 for (i = 0; i < 8; i++)
616847e7 6612 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6613
6614 /* Enable PMON + select events */
6615 I915_WRITE(ECR, 0x80000019);
6616
6617 lcfuse = I915_READ(LCFUSE02);
6618
20e4d407 6619 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6620}
6621
dc97997a 6622void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6623{
b268c699
ID		 6624 /*
6625 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6626 * requirement.
6627 */
6628 if (!i915.enable_rc6) {
6629 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6630 intel_runtime_pm_get(dev_priv);
6631 }
e6069ca8 6632
b5163dbb 6633 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6634 mutex_lock(&dev_priv->rps.hw_lock);
6635
6636 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6637 if (IS_CHERRYVIEW(dev_priv))
6638 cherryview_init_gt_powersave(dev_priv);
6639 else if (IS_VALLEYVIEW(dev_priv))
6640 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6641 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6642 gen6_init_rps_frequencies(dev_priv);
6643
6644 /* Derive initial user preferences/limits from the hardware limits */
6645 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6646 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6647
6648 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6649 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6650
6651 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6652 dev_priv->rps.min_freq_softlimit =
6653 max_t(int,
6654 dev_priv->rps.efficient_freq,
6655 intel_freq_opcode(dev_priv, 450));
6656
99ac9612
CW		 6657 /* After setting max-softlimit, find the overclock max freq */
6658 if (IS_GEN6(dev_priv) ||
6659 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6660 u32 params = 0;
6661
6662 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6663 if (params & BIT(31)) { /* OC supported */
6664 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6665 (dev_priv->rps.max_freq & 0xff) * 50,
6666 (params & 0xff) * 50);
6667 dev_priv->rps.max_freq = params & 0xff;
6668 }
6669 }
6670
29ecd78d
CW		 6671 /* Finally allow us to boost to max by default */
6672 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6673
773ea9a8 6674 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6675 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6676
6677 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6678}
6679
dc97997a 6680void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6681{
8dac1e1f 6682 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6683 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6684
6685 if (!i915.enable_rc6)
6686 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6687}
6688
54b4f68f
CW		 6689/**
6690 * intel_suspend_gt_powersave - suspend PM work and helper threads
6691 * @dev_priv: i915 device
6692 *
6693 * We don't want to disable RC6 or other features here, we just want
6694 * to make sure any work we've queued has finished and won't bother
6695 * us while we're suspended.
6696 */
6697void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6698{
6699 if (INTEL_GEN(dev_priv) < 6)
6700 return;
6701
6702 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6703 intel_runtime_pm_put(dev_priv);
6704
6705 /* gen6_rps_idle() will be called later to disable interrupts */
6706}
6707
b7137e0c
CW		 6708void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6709{
6710 dev_priv->rps.enabled = true; /* force disabling */
6711 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6712
6713 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6714}
6715
dc97997a 6716void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6717{
b7137e0c
CW		 6718 if (!READ_ONCE(dev_priv->rps.enabled))
6719 return;
e494837a 6720
b7137e0c 6721 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6722
b7137e0c
CW		 6723 if (INTEL_GEN(dev_priv) >= 9) {
6724 gen9_disable_rc6(dev_priv);
6725 gen9_disable_rps(dev_priv);
6726 } else if (IS_CHERRYVIEW(dev_priv)) {
6727 cherryview_disable_rps(dev_priv);
6728 } else if (IS_VALLEYVIEW(dev_priv)) {
6729 valleyview_disable_rps(dev_priv);
6730 } else if (INTEL_GEN(dev_priv) >= 6) {
6731 gen6_disable_rps(dev_priv);
6732 } else if (IS_IRONLAKE_M(dev_priv)) {
6733 ironlake_disable_drps(dev_priv);
930ebb46 6734 }
b7137e0c
CW		 6735
6736 dev_priv->rps.enabled = false;
6737 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6738}
6739
b7137e0c 6740void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6741{
54b4f68f
CW		 6742 /* We shouldn't be disabling as we submit, so this should be less
6743 * racy than it appears!
6744 */
b7137e0c
CW		 6745 if (READ_ONCE(dev_priv->rps.enabled))
6746 return;
1a01ab3b 6747
b7137e0c
CW		 6748 /* Powersaving is controlled by the host when inside a VM */
6749 if (intel_vgpu_active(dev_priv))
6750 return;
0a073b84 6751
b7137e0c 6752 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6753
6754 if (IS_CHERRYVIEW(dev_priv)) {
6755 cherryview_enable_rps(dev_priv);
6756 } else if (IS_VALLEYVIEW(dev_priv)) {
6757 valleyview_enable_rps(dev_priv);
b7137e0c 6758 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6759 gen9_enable_rc6(dev_priv);
6760 gen9_enable_rps(dev_priv);
6761 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6762 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6763 } else if (IS_BROADWELL(dev_priv)) {
6764 gen8_enable_rps(dev_priv);
fb7404e8 6765 gen6_update_ring_freq(dev_priv);
b7137e0c 6766 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6767 gen6_enable_rps(dev_priv);
fb7404e8 6768 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6769 } else if (IS_IRONLAKE_M(dev_priv)) {
6770 ironlake_enable_drps(dev_priv);
6771 intel_init_emon(dev_priv);
0a073b84 6772 }
aed242ff
CW		 6773
6774 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6775 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6776
6777 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6778 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6779
54b4f68f 6780 dev_priv->rps.enabled = true;
b7137e0c
CW		 6781 mutex_unlock(&dev_priv->rps.hw_lock);
6782}
3cc134e3 6783
54b4f68f
CW		 6784static void __intel_autoenable_gt_powersave(struct work_struct *work)
6785{
6786 struct drm_i915_private *dev_priv =
6787 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6788 struct intel_engine_cs *rcs;
6789 struct drm_i915_gem_request *req;
6790
6791 if (READ_ONCE(dev_priv->rps.enabled))
6792 goto out;
6793
3b3f1650 6794 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6795 if (rcs->last_context)
6796 goto out;
6797
6798 if (!rcs->init_context)
6799 goto out;
6800
6801 mutex_lock(&dev_priv->drm.struct_mutex);
6802
6803 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6804 if (IS_ERR(req))
6805 goto unlock;
6806
6807 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6808 rcs->init_context(req);
6809
6810 /* Mark the device busy, calling intel_enable_gt_powersave() */
6811 i915_add_request_no_flush(req);
6812
6813unlock:
6814 mutex_unlock(&dev_priv->drm.struct_mutex);
6815out:
6816 intel_runtime_pm_put(dev_priv);
6817}
6818
6819void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6820{
6821 if (READ_ONCE(dev_priv->rps.enabled))
6822 return;
6823
6824 if (IS_IRONLAKE_M(dev_priv)) {
6825 ironlake_enable_drps(dev_priv);
54b4f68f 6826 intel_init_emon(dev_priv);
54b4f68f
CW		 6827 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6828 /*
6829 * PCU communication is slow and this doesn't need to be
6830 * done at any specific time, so do this out of our fast path
6831 * to make resume and init faster.
6832 *
6833 * We depend on the HW RC6 power context save/restore
6834 * mechanism when entering D3 through runtime PM suspend. So
6835 * disable RPM until RPS/RC6 is properly setup. We can only
6836 * get here via the driver load/system resume/runtime resume
6837 * paths, so the _noresume version is enough (and in case of
6838 * runtime resume it's necessary).
6839 */
6840 if (queue_delayed_work(dev_priv->wq,
6841 &dev_priv->rps.autoenable_work,
6842 round_jiffies_up_relative(HZ)))
6843 intel_runtime_pm_get_noresume(dev_priv);
6844 }
6845}
6846
3107bd48
DV		 6847static void ibx_init_clock_gating(struct drm_device *dev)
6848{
fac5e23e 6849 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6850
6851 /*
6852 * On Ibex Peak and Cougar Point, we need to disable clock
6853 * gating for the panel power sequencer or it will fail to
6854 * start up when no ports are active.
6855 */
6856 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6857}
6858
0e088b8f
VS		 6859static void g4x_disable_trickle_feed(struct drm_device *dev)
6860{
fac5e23e 6861 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6862 enum pipe pipe;
0e088b8f 6863
055e393f 6864 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6865 I915_WRITE(DSPCNTR(pipe),
6866 I915_READ(DSPCNTR(pipe)) |
6867 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6868
6869 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6870 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6871 }
6872}
6873
017636cc
VS		 6874static void ilk_init_lp_watermarks(struct drm_device *dev)
6875{
fac5e23e 6876 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6877
6878 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6879 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6880 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6881
6882 /*
6883 * Don't touch WM1S_LP_EN here.
6884 * Doing so could cause underruns.
6885 */
6886}
6887
1fa61106 6888static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6889{
fac5e23e 6890 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6891 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6892
f1e8fa56
DL		 6893 /*
6894 * Required for FBC
6895 * WaFbcDisableDpfcClockGating:ilk
6896 */
4d47e4f5
DL		 6897 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6898 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6899 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6900
6901 I915_WRITE(PCH_3DCGDIS0,
6902 MARIUNIT_CLOCK_GATE_DISABLE |
6903 SVSMUNIT_CLOCK_GATE_DISABLE);
6904 I915_WRITE(PCH_3DCGDIS1,
6905 VFMUNIT_CLOCK_GATE_DISABLE);
6906
6f1d69b0
ED		 6907 /*
6908 * According to the spec the following bits should be set in
6909 * order to enable memory self-refresh
6910 * The bit 22/21 of 0x42004
6911 * The bit 5 of 0x42020
6912 * The bit 15 of 0x45000
6913 */
6914 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6915 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6916 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6917 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6918 I915_WRITE(DISP_ARB_CTL,
6919 (I915_READ(DISP_ARB_CTL) |
6920 DISP_FBC_WM_DIS));
017636cc
VS		 6921
6922 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6923
6924 /*
6925 * Based on the document from hardware guys the following bits
6926 * should be set unconditionally in order to enable FBC.
6927 * The bit 22 of 0x42000
6928 * The bit 22 of 0x42004
6929 * The bit 7,8,9 of 0x42020.
6930 */
50a0bc90 6931 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6932 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6933 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6934 I915_READ(ILK_DISPLAY_CHICKEN1) |
6935 ILK_FBCQ_DIS);
6936 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6937 I915_READ(ILK_DISPLAY_CHICKEN2) |
6938 ILK_DPARB_GATE);
6f1d69b0
ED		 6939 }
6940
4d47e4f5
DL		 6941 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6942
6f1d69b0
ED		 6943 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6944 I915_READ(ILK_DISPLAY_CHICKEN2) |
6945 ILK_ELPIN_409_SELECT);
6946 I915_WRITE(_3D_CHICKEN2,
6947 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6948 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6949
ecdb4eb7 6950 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6951 I915_WRITE(CACHE_MODE_0,
6952 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6953
4e04632e
AG		 6954 /* WaDisable_RenderCache_OperationalFlush:ilk */
6955 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6956
0e088b8f 6957 g4x_disable_trickle_feed(dev);
bdad2b2f 6958
3107bd48
DV		 6959 ibx_init_clock_gating(dev);
6960}
6961
6962static void cpt_init_clock_gating(struct drm_device *dev)
6963{
fac5e23e 6964 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6965 int pipe;
3f704fa2 6966 uint32_t val;
3107bd48
DV		 6967
6968 /*
6969 * On Ibex Peak and Cougar Point, we need to disable clock
6970 * gating for the panel power sequencer or it will fail to
6971 * start up when no ports are active.
6972 */
cd664078
JB		 6973 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6974 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6975 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6976 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6977 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6978 /* The below fixes the weird display corruption, a few pixels shifted
6979 * downward, on (only) LVDS of some HP laptops with IVY.
6980 */
055e393f 6981 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6982 val = I915_READ(TRANS_CHICKEN2(pipe));
6983 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6984 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6985 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6986 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6987 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6988 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6989 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6990 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6991 }
3107bd48 6992 /* WADP0ClockGatingDisable */
055e393f 6993 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6994 I915_WRITE(TRANS_CHICKEN1(pipe),
6995 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6996 }
6f1d69b0
ED		 6997}
6998
1d7aaa0c
DV		 6999static void gen6_check_mch_setup(struct drm_device *dev)
7000{
fac5e23e 7001 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7002 uint32_t tmp;
7003
7004 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7005 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7006 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7007 tmp);
1d7aaa0c
DV		 7008}
7009
1fa61106 7010static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7011{
fac5e23e 7012 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7013 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7014
231e54f6 7015 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7016
7017 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7018 I915_READ(ILK_DISPLAY_CHICKEN2) |
7019 ILK_ELPIN_409_SELECT);
7020
ecdb4eb7 7021 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7022 I915_WRITE(_3D_CHICKEN,
7023 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7024
4e04632e
AG		 7025 /* WaDisable_RenderCache_OperationalFlush:snb */
7026 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7027
8d85d272
VS		 7028 /*
7029 * BSpec recoomends 8x4 when MSAA is used,
7030 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7031 *
7032 * Note that PS/WM thread counts depend on the WIZ hashing
7033 * disable bit, which we don't touch here, but it's good
7034 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7035 */
7036 I915_WRITE(GEN6_GT_MODE,
98533251 7037 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7038
017636cc 7039 ilk_init_lp_watermarks(dev);
6f1d69b0 7040
6f1d69b0 7041 I915_WRITE(CACHE_MODE_0,
50743298 7042 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7043
7044 I915_WRITE(GEN6_UCGCTL1,
7045 I915_READ(GEN6_UCGCTL1) |
7046 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7047 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7048
7049 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7050 * gating disable must be set. Failure to set it results in
7051 * flickering pixels due to Z write ordering failures after
7052 * some amount of runtime in the Mesa "fire" demo, and Unigine
7053 * Sanctuary and Tropics, and apparently anything else with
7054 * alpha test or pixel discard.
7055 *
7056 * According to the spec, bit 11 (RCCUNIT) must also be set,
7057 * but we didn't debug actual testcases to find it out.
0f846f81 7058 *
ef59318c
VS		 7059 * WaDisableRCCUnitClockGating:snb
7060 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7061 */
7062 I915_WRITE(GEN6_UCGCTL2,
7063 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7064 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7065
5eb146dd 7066 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7067 I915_WRITE(_3D_CHICKEN3,
7068 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7069
e927ecde
VS		 7070 /*
7071 * Bspec says:
7072 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7073 * 3DSTATE_SF number of SF output attributes is more than 16."
7074 */
7075 I915_WRITE(_3D_CHICKEN3,
7076 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7077
6f1d69b0
ED		 7078 /*
7079 * According to the spec the following bits should be
7080 * set in order to enable memory self-refresh and fbc:
7081 * The bit21 and bit22 of 0x42000
7082 * The bit21 and bit22 of 0x42004
7083 * The bit5 and bit7 of 0x42020
7084 * The bit14 of 0x70180
7085 * The bit14 of 0x71180
4bb35334
DL		 7086 *
7087 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7088 */
7089 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7090 I915_READ(ILK_DISPLAY_CHICKEN1) |
7091 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7092 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7093 I915_READ(ILK_DISPLAY_CHICKEN2) |
7094 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7095 I915_WRITE(ILK_DSPCLK_GATE_D,
7096 I915_READ(ILK_DSPCLK_GATE_D) |
7097 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7098 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7099
0e088b8f 7100 g4x_disable_trickle_feed(dev);
f8f2ac9a 7101
3107bd48 7102 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7103
7104 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7105}
7106
7107static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7108{
7109 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7110
3aad9059 7111 /*
46680e0a 7112 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7113 *
7114 * This actually overrides the dispatch
7115 * mode for all thread types.
7116 */
6f1d69b0
ED		 7117 reg &= ~GEN7_FF_SCHED_MASK;
7118 reg |= GEN7_FF_TS_SCHED_HW;
7119 reg |= GEN7_FF_VS_SCHED_HW;
7120 reg |= GEN7_FF_DS_SCHED_HW;
7121
7122 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7123}
7124
17a303ec
PZ		 7125static void lpt_init_clock_gating(struct drm_device *dev)
7126{
fac5e23e 7127 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7128
7129 /*
7130 * TODO: this bit should only be enabled when really needed, then
7131 * disabled when not needed anymore in order to save power.
7132 */
4f8036a2 7133 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7134 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7135 I915_READ(SOUTH_DSPCLK_GATE_D) |
7136 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7137
7138 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7139 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7140 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7141 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7142}
7143
7d708ee4
ID		 7144static void lpt_suspend_hw(struct drm_device *dev)
7145{
fac5e23e 7146 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7147
4f8036a2 7148 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7149 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7150
7151 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7152 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7153 }
7154}
7155
450174fe
ID		 7156static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7157 int general_prio_credits,
7158 int high_prio_credits)
7159{
7160 u32 misccpctl;
7161
7162 /* WaTempDisableDOPClkGating:bdw */
7163 misccpctl = I915_READ(GEN7_MISCCPCTL);
7164 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7165
7166 I915_WRITE(GEN8_L3SQCREG1,
7167 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7168 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7169
7170 /*
7171 * Wait at least 100 clocks before re-enabling clock gating.
7172 * See the definition of L3SQCREG1 in BSpec.
7173 */
7174 POSTING_READ(GEN8_L3SQCREG1);
7175 udelay(1);
7176 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7177}
7178
9498dba7
MK		 7179static void kabylake_init_clock_gating(struct drm_device *dev)
7180{
9146f308 7181 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7182
b033bb6d 7183 gen9_init_clock_gating(dev);
9498dba7
MK		 7184
7185 /* WaDisableSDEUnitClockGating:kbl */
7186 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7187 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7188 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7189
7190 /* WaDisableGamClockGating:kbl */
7191 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7192 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7193 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7194
7195 /* WaFbcNukeOnHostModify:kbl */
7196 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7197 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7198}
7199
dc00b6a0
DV		 7200static void skylake_init_clock_gating(struct drm_device *dev)
7201{
c584e2d3 7202 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7203
b033bb6d 7204 gen9_init_clock_gating(dev);
44fff99f
MK		 7205
7206 /* WAC6entrylatency:skl */
7207 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7208 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7209
7210 /* WaFbcNukeOnHostModify:skl */
7211 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7212 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7213}
7214
47c2bd97 7215static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7216{
fac5e23e 7217 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7218 enum pipe pipe;
1020a5c2 7219
7ad0dbab 7220 ilk_init_lp_watermarks(dev);
50ed5fbd 7221
ab57fff1 7222 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7223 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7224
ab57fff1 7225 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7226 I915_WRITE(CHICKEN_PAR1_1,
7227 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7228
ab57fff1 7229 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7230 for_each_pipe(dev_priv, pipe) {
07d27e20 7231 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7232 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7233 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7234 }
63801f21 7235
ab57fff1
BW		 7236 /* WaVSRefCountFullforceMissDisable:bdw */
7237 /* WaDSRefCountFullforceMissDisable:bdw */
7238 I915_WRITE(GEN7_FF_THREAD_MODE,
7239 I915_READ(GEN7_FF_THREAD_MODE) &
7240 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7241
295e8bb7
VS		 7242 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7243 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7244
7245 /* WaDisableSDEUnitClockGating:bdw */
7246 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7247 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7248
450174fe
ID		 7249 /* WaProgramL3SqcReg1Default:bdw */
7250 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7251
6d50b065
VS		 7252 /*
7253 * WaGttCachingOffByDefault:bdw
7254 * GTT cache may not work with big pages, so if those
7255 * are ever enabled GTT cache may need to be disabled.
7256 */
7257 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7258
17e0adf0
MK		 7259 /* WaKVMNotificationOnConfigChange:bdw */
7260 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7261 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7262
89d6b2b8 7263 lpt_init_clock_gating(dev);
1020a5c2
BW		 7264}
7265
cad2a2d7
ED		 7266static void haswell_init_clock_gating(struct drm_device *dev)
7267{
fac5e23e 7268 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7269
017636cc 7270 ilk_init_lp_watermarks(dev);
cad2a2d7 7271
f3fc4884
FJ		 7272 /* L3 caching of data atomics doesn't work -- disable it. */
7273 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7274 I915_WRITE(HSW_ROW_CHICKEN3,
7275 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7276
ecdb4eb7 7277 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7278 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7279 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7280 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7281
e36ea7ff
VS		 7282 /* WaVSRefCountFullforceMissDisable:hsw */
7283 I915_WRITE(GEN7_FF_THREAD_MODE,
7284 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7285
4e04632e
AG		 7286 /* WaDisable_RenderCache_OperationalFlush:hsw */
7287 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7288
fe27c606
CW		 7289 /* enable HiZ Raw Stall Optimization */
7290 I915_WRITE(CACHE_MODE_0_GEN7,
7291 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7292
ecdb4eb7 7293 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7294 I915_WRITE(CACHE_MODE_1,
7295 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7296
a12c4967
VS		 7297 /*
7298 * BSpec recommends 8x4 when MSAA is used,
7299 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7300 *
7301 * Note that PS/WM thread counts depend on the WIZ hashing
7302 * disable bit, which we don't touch here, but it's good
7303 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7304 */
7305 I915_WRITE(GEN7_GT_MODE,
98533251 7306 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7307
94411593
KG		 7308 /* WaSampleCChickenBitEnable:hsw */
7309 I915_WRITE(HALF_SLICE_CHICKEN3,
7310 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7311
ecdb4eb7 7312 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7313 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7314
90a88643
PZ		 7315 /* WaRsPkgCStateDisplayPMReq:hsw */
7316 I915_WRITE(CHICKEN_PAR1_1,
7317 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7318
17a303ec 7319 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7320}
7321
1fa61106 7322static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7323{
fac5e23e 7324 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7325 uint32_t snpcr;
6f1d69b0 7326
017636cc 7327 ilk_init_lp_watermarks(dev);
6f1d69b0 7328
231e54f6 7329 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7330
ecdb4eb7 7331 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7332 I915_WRITE(_3D_CHICKEN3,
7333 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7334
ecdb4eb7 7335 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7336 I915_WRITE(IVB_CHICKEN3,
7337 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7338 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7339
ecdb4eb7 7340 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7341 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7342 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7343 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7344
4e04632e
AG		 7345 /* WaDisable_RenderCache_OperationalFlush:ivb */
7346 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7347
ecdb4eb7 7348 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7349 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7350 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7351
ecdb4eb7 7352 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7353 I915_WRITE(GEN7_L3CNTLREG1,
7354 GEN7_WA_FOR_GEN7_L3_CONTROL);
7355 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7356 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7357 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7358 I915_WRITE(GEN7_ROW_CHICKEN2,
7359 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7360 else {
7361 /* must write both registers */
7362 I915_WRITE(GEN7_ROW_CHICKEN2,
7363 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7364 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7365 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7366 }
6f1d69b0 7367
ecdb4eb7 7368 /* WaForceL3Serialization:ivb */
61939d97
JB		 7369 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7370 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7371
1b80a19a 7372 /*
0f846f81 7373 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7374 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7375 */
7376 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7377 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7378
ecdb4eb7 7379 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7380 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7381 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7382 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7383
0e088b8f 7384 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7385
7386 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7387
22721343
CW		 7388 if (0) { /* causes HiZ corruption on ivb:gt1 */
7389 /* enable HiZ Raw Stall Optimization */
7390 I915_WRITE(CACHE_MODE_0_GEN7,
7391 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7392 }
116f2b6d 7393
ecdb4eb7 7394 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7395 I915_WRITE(CACHE_MODE_1,
7396 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7397
a607c1a4
VS		 7398 /*
7399 * BSpec recommends 8x4 when MSAA is used,
7400 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7401 *
7402 * Note that PS/WM thread counts depend on the WIZ hashing
7403 * disable bit, which we don't touch here, but it's good
7404 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7405 */
7406 I915_WRITE(GEN7_GT_MODE,
98533251 7407 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7408
20848223
BW		 7409 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7410 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7411 snpcr |= GEN6_MBC_SNPCR_MED;
7412 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7413
6e266956 7414 if (!HAS_PCH_NOP(dev_priv))
ab5c608b 7415 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7416
7417 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7418}
7419
1fa61106 7420static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7421{
fac5e23e 7422 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7423
ecdb4eb7 7424 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7425 I915_WRITE(_3D_CHICKEN3,
7426 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7427
ecdb4eb7 7428 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7429 I915_WRITE(IVB_CHICKEN3,
7430 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7431 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7432
fad7d36e 7433 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7434 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7435 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7436 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7437 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7438
4e04632e
AG		 7439 /* WaDisable_RenderCache_OperationalFlush:vlv */
7440 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7441
ecdb4eb7 7442 /* WaForceL3Serialization:vlv */
61939d97
JB		 7443 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7444 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7445
ecdb4eb7 7446 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7447 I915_WRITE(GEN7_ROW_CHICKEN2,
7448 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7449
ecdb4eb7 7450 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7451 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7452 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7453 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7454
46680e0a
VS		 7455 gen7_setup_fixed_func_scheduler(dev_priv);
7456
3c0edaeb 7457 /*
0f846f81 7458 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7459 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7460 */
7461 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7462 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7463
c98f5062
AG		 7464 /* WaDisableL3Bank2xClockGate:vlv
7465 * Disabling L3 clock gating- MMIO 940c[25] = 1
7466 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7467 I915_WRITE(GEN7_UCGCTL4,
7468 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7469
afd58e79
VS		 7470 /*
7471 * BSpec says this must be set, even though
7472 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7473 */
6b26c86d
DV		 7474 I915_WRITE(CACHE_MODE_1,
7475 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7476
da2518f9
VS		 7477 /*
7478 * BSpec recommends 8x4 when MSAA is used,
7479 * however in practice 16x4 seems fastest.
7480 *
7481 * Note that PS/WM thread counts depend on the WIZ hashing
7482 * disable bit, which we don't touch here, but it's good
7483 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7484 */
7485 I915_WRITE(GEN7_GT_MODE,
7486 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7487
031994ee
VS		 7488 /*
7489 * WaIncreaseL3CreditsForVLVB0:vlv
7490 * This is the hardware default actually.
7491 */
7492 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7493
2d809570 7494 /*
ecdb4eb7 7495 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7496 * Disable clock gating on th GCFG unit to prevent a delay
7497 * in the reporting of vblank events.
7498 */
7a0d1eed 7499 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7500}
7501
a4565da8
VS		 7502static void cherryview_init_clock_gating(struct drm_device *dev)
7503{
fac5e23e 7504 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7505
232ce337
VS		 7506 /* WaVSRefCountFullforceMissDisable:chv */
7507 /* WaDSRefCountFullforceMissDisable:chv */
7508 I915_WRITE(GEN7_FF_THREAD_MODE,
7509 I915_READ(GEN7_FF_THREAD_MODE) &
7510 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7511
7512 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7513 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7514 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7515
7516 /* WaDisableCSUnitClockGating:chv */
7517 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7518 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7519
7520 /* WaDisableSDEUnitClockGating:chv */
7521 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7522 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7523
450174fe
ID		 7524 /*
7525 * WaProgramL3SqcReg1Default:chv
7526 * See gfxspecs/Related Documents/Performance Guide/
7527 * LSQC Setting Recommendations.
7528 */
7529 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7530
6d50b065
VS		 7531 /*
7532 * GTT cache may not work with big pages, so if those
7533 * are ever enabled GTT cache may need to be disabled.
7534 */
7535 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7536}
7537
1fa61106 7538static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7539{
fac5e23e 7540 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7541 uint32_t dspclk_gate;
7542
7543 I915_WRITE(RENCLK_GATE_D1, 0);
7544 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7545 GS_UNIT_CLOCK_GATE_DISABLE |
7546 CL_UNIT_CLOCK_GATE_DISABLE);
7547 I915_WRITE(RAMCLK_GATE_D, 0);
7548 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7549 OVRUNIT_CLOCK_GATE_DISABLE |
7550 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7551 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7552 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7553 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7554
7555 /* WaDisableRenderCachePipelinedFlush */
7556 I915_WRITE(CACHE_MODE_0,
7557 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7558
4e04632e
AG		 7559 /* WaDisable_RenderCache_OperationalFlush:g4x */
7560 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7561
0e088b8f 7562 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7563}
7564
1fa61106 7565static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7566{
fac5e23e 7567 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7568
7569 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7570 I915_WRITE(RENCLK_GATE_D2, 0);
7571 I915_WRITE(DSPCLK_GATE_D, 0);
7572 I915_WRITE(RAMCLK_GATE_D, 0);
7573 I915_WRITE16(DEUC, 0);
20f94967
VS		 7574 I915_WRITE(MI_ARB_STATE,
7575 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7576
7577 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7578 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7579}
7580
1fa61106 7581static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7582{
fac5e23e 7583 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7584
7585 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7586 I965_RCC_CLOCK_GATE_DISABLE |
7587 I965_RCPB_CLOCK_GATE_DISABLE |
7588 I965_ISC_CLOCK_GATE_DISABLE |
7589 I965_FBC_CLOCK_GATE_DISABLE);
7590 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7591 I915_WRITE(MI_ARB_STATE,
7592 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7593
7594 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7595 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7596}
7597
1fa61106 7598static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7599{
fac5e23e 7600 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7601 u32 dstate = I915_READ(D_STATE);
7602
7603 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7604 DSTATE_DOT_CLOCK_GATING;
7605 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7606
7607 if (IS_PINEVIEW(dev))
7608 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7609
7610 /* IIR "flip pending" means done if this bit is set */
7611 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7612
7613 /* interrupts should cause a wake up from C3 */
3299254f 7614 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7615
7616 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7617 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7618
7619 I915_WRITE(MI_ARB_STATE,
7620 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7621}
7622
1fa61106 7623static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7624{
fac5e23e 7625 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7626
7627 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7628
7629 /* interrupts should cause a wake up from C3 */
7630 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7631 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7632
7633 I915_WRITE(MEM_MODE,
7634 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7635}
7636
1fa61106 7637static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7638{
fac5e23e 7639 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7640
7641 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7642
7643 I915_WRITE(MEM_MODE,
7644 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7645 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7646}
7647
6f1d69b0
ED		 7648void intel_init_clock_gating(struct drm_device *dev)
7649{
fac5e23e 7650 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7651
bb400da9 7652 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7653}
7654
7d708ee4
ID		 7655void intel_suspend_hw(struct drm_device *dev)
7656{
6e266956 7657 if (HAS_PCH_LPT(to_i915(dev)))
7d708ee4
ID		 7658 lpt_suspend_hw(dev);
7659}
7660
bb400da9
ID		 7661static void nop_init_clock_gating(struct drm_device *dev)
7662{
7663 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7664}
7665
7666/**
7667 * intel_init_clock_gating_hooks - setup the clock gating hooks
7668 * @dev_priv: device private
7669 *
7670 * Setup the hooks that configure which clocks of a given platform can be
7671 * gated and also apply various GT and display specific workarounds for these
7672 * platforms. Note that some GT specific workarounds are applied separately
7673 * when GPU contexts or batchbuffers start their execution.
7674 */
7675void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7676{
7677 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7678 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7679 else if (IS_KABYLAKE(dev_priv))
9498dba7 7680 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7681 else if (IS_BROXTON(dev_priv))
7682 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7683 else if (IS_BROADWELL(dev_priv))
7684 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7685 else if (IS_CHERRYVIEW(dev_priv))
7686 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7687 else if (IS_HASWELL(dev_priv))
7688 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7689 else if (IS_IVYBRIDGE(dev_priv))
7690 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7691 else if (IS_VALLEYVIEW(dev_priv))
7692 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7693 else if (IS_GEN6(dev_priv))
7694 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7695 else if (IS_GEN5(dev_priv))
7696 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7697 else if (IS_G4X(dev_priv))
7698 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7699 else if (IS_CRESTLINE(dev_priv))
7700 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7701 else if (IS_BROADWATER(dev_priv))
7702 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7703 else if (IS_GEN3(dev_priv))
7704 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7705 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7706 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7707 else if (IS_GEN2(dev_priv))
7708 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7709 else {
7710 MISSING_CASE(INTEL_DEVID(dev_priv));
7711 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7712 }
7713}
7714
1fa61106
ED		 7715/* Set up chip specific power management-related functions */
7716void intel_init_pm(struct drm_device *dev)
7717{
fac5e23e 7718 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7719
7ff0ebcc 7720 intel_fbc_init(dev_priv);
1fa61106 7721
c921aba8
DV		 7722 /* For cxsr */
7723 if (IS_PINEVIEW(dev))
7724 i915_pineview_get_mem_freq(dev);
5db94019 7725 else if (IS_GEN5(dev_priv))
c921aba8
DV		 7726 i915_ironlake_get_mem_freq(dev);
7727
1fa61106 7728 /* For FIFO watermark updates */
f5ed50cb 7729 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7730 skl_setup_wm_latency(dev);
2d41c0b5 7731 dev_priv->display.update_wm = skl_update_wm;
98d39494 7732 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7733 } else if (HAS_PCH_SPLIT(dev_priv)) {
fa50ad61 7734 ilk_setup_wm_latency(dev);
53615a5e 7735
5db94019 7736 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7737 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7738 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7739 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7740 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7741 dev_priv->display.compute_intermediate_wm =
7742 ilk_compute_intermediate_wm;
7743 dev_priv->display.initial_watermarks =
7744 ilk_initial_watermarks;
7745 dev_priv->display.optimize_watermarks =
7746 ilk_optimize_watermarks;
bd602544
VS		 7747 } else {
7748 DRM_DEBUG_KMS("Failed to read display plane latency. "
7749 "Disable CxSR\n");
7750 }
920a14b2 7751 } else if (IS_CHERRYVIEW(dev_priv)) {
262cd2e1 7752 vlv_setup_wm_latency(dev);
262cd2e1 7753 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7754 } else if (IS_VALLEYVIEW(dev_priv)) {
26e1fe4f 7755 vlv_setup_wm_latency(dev);
26e1fe4f 7756 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7757 } else if (IS_PINEVIEW(dev)) {
50a0bc90 7758 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7759 dev_priv->is_ddr3,
7760 dev_priv->fsb_freq,
7761 dev_priv->mem_freq)) {
7762 DRM_INFO("failed to find known CxSR latency "
7763 "(found ddr%s fsb freq %d, mem freq %d), "
7764 "disabling CxSR\n",
7765 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7766 dev_priv->fsb_freq, dev_priv->mem_freq);
7767 /* Disable CxSR and never update its watermark again */
5209b1f4 7768 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7769 dev_priv->display.update_wm = NULL;
7770 } else
7771 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7772 } else if (IS_G4X(dev_priv)) {
1fa61106 7773 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7774 } else if (IS_GEN4(dev_priv)) {
1fa61106 7775 dev_priv->display.update_wm = i965_update_wm;
5db94019 7776 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7777 dev_priv->display.update_wm = i9xx_update_wm;
7778 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7779 } else if (IS_GEN2(dev_priv)) {
feb56b93
DV		 7780 if (INTEL_INFO(dev)->num_pipes == 1) {
7781 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7782 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7783 } else {
7784 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7785 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7786 }
feb56b93
DV		 7787 } else {
7788 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7789 }
7790}
7791
87660502
L		 7792static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7793{
7794 uint32_t flags =
7795 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7796
7797 switch (flags) {
7798 case GEN6_PCODE_SUCCESS:
7799 return 0;
7800 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7801 case GEN6_PCODE_ILLEGAL_CMD:
7802 return -ENXIO;
7803 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7804 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7805 return -EOVERFLOW;
7806 case GEN6_PCODE_TIMEOUT:
7807 return -ETIMEDOUT;
7808 default:
7809 MISSING_CASE(flags)
7810 return 0;
7811 }
7812}
7813
7814static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7815{
7816 uint32_t flags =
7817 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7818
7819 switch (flags) {
7820 case GEN6_PCODE_SUCCESS:
7821 return 0;
7822 case GEN6_PCODE_ILLEGAL_CMD:
7823 return -ENXIO;
7824 case GEN7_PCODE_TIMEOUT:
7825 return -ETIMEDOUT;
7826 case GEN7_PCODE_ILLEGAL_DATA:
7827 return -EINVAL;
7828 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7829 return -EOVERFLOW;
7830 default:
7831 MISSING_CASE(flags);
7832 return 0;
7833 }
7834}
7835
151a49d0 7836int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7837{
87660502
L		 7838 int status;
7839
4fc688ce 7840 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7841
3f5582dd
CW		 7842 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7843 * use te fw I915_READ variants to reduce the amount of work
7844 * required when reading/writing.
7845 */
7846
7847 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7848 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7849 return -EAGAIN;
7850 }
7851
3f5582dd
CW		 7852 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7853 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7854 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7855
3f5582dd
CW		 7856 if (intel_wait_for_register_fw(dev_priv,
7857 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7858 500)) {
42c0526c
BW		 7859 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7860 return -ETIMEDOUT;
7861 }
7862
3f5582dd
CW		 7863 *val = I915_READ_FW(GEN6_PCODE_DATA);
7864 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7865
87660502
L		 7866 if (INTEL_GEN(dev_priv) > 6)
7867 status = gen7_check_mailbox_status(dev_priv);
7868 else
7869 status = gen6_check_mailbox_status(dev_priv);
7870
7871 if (status) {
7872 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7873 status);
7874 return status;
7875 }
7876
42c0526c
BW		 7877 return 0;
7878}
7879
3f5582dd 7880int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7881 u32 mbox, u32 val)
42c0526c 7882{
87660502
L		 7883 int status;
7884
4fc688ce 7885 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7886
3f5582dd
CW		 7887 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7888 * use te fw I915_READ variants to reduce the amount of work
7889 * required when reading/writing.
7890 */
7891
7892 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7893 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7894 return -EAGAIN;
7895 }
7896
3f5582dd
CW		 7897 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7898 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7899
3f5582dd
CW		 7900 if (intel_wait_for_register_fw(dev_priv,
7901 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7902 500)) {
42c0526c
BW		 7903 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7904 return -ETIMEDOUT;
7905 }
7906
3f5582dd 7907 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7908
87660502
L		 7909 if (INTEL_GEN(dev_priv) > 6)
7910 status = gen7_check_mailbox_status(dev_priv);
7911 else
7912 status = gen6_check_mailbox_status(dev_priv);
7913
7914 if (status) {
7915 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7916 status);
7917 return status;
7918 }
7919
42c0526c
BW		 7920 return 0;
7921}
a0e4e199 7922
dd06f88c
VS		 7923static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7924{
c30fec65
VS		 7925 /*
7926 * N = val - 0xb7
7927 * Slow = Fast = GPLL ref * N
7928 */
7929 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7930}
7931
b55dd647 7932static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7933{
c30fec65 7934 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7935}
7936
b55dd647 7937static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7938{
c30fec65
VS		 7939 /*
7940 * N = val / 2
7941 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7942 */
7943 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7944}
7945
b55dd647 7946static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7947{
1c14762d 7948 /* CHV needs even values */
c30fec65 7949 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7950}
7951
616bc820 7952int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7953{
2d1fe073 7954 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7955 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7956 GEN9_FREQ_SCALER);
2d1fe073 7957 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7958 return chv_gpu_freq(dev_priv, val);
2d1fe073 7959 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7960 return byt_gpu_freq(dev_priv, val);
7961 else
7962 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7963}
7964
616bc820
VS		 7965int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7966{
2d1fe073 7967 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7968 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7969 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7970 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7971 return chv_freq_opcode(dev_priv, val);
2d1fe073 7972 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7973 return byt_freq_opcode(dev_priv, val);
7974 else
500a3d2e 7975 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7976}
22b1b2f8 7977
6ad790c0
CW		 7978struct request_boost {
7979 struct work_struct work;
eed29a5b 7980 struct drm_i915_gem_request *req;
6ad790c0
CW		 7981};
7982
7983static void __intel_rps_boost_work(struct work_struct *work)
7984{
7985 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7986 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7987
f69a02c9 7988 if (!i915_gem_request_completed(req))
c033666a 7989 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7990
e8a261ea 7991 i915_gem_request_put(req);
6ad790c0
CW		 7992 kfree(boost);
7993}
7994
91d14251 7995void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7996{
7997 struct request_boost *boost;
7998
91d14251 7999 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8000 return;
8001
f69a02c9 8002 if (i915_gem_request_completed(req))
e61b9958
CW		 8003 return;
8004
6ad790c0
CW		 8005 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8006 if (boost == NULL)
8007 return;
8008
e8a261ea 8009 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8010
8011 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8012 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8013}
8014
f742a552 8015void intel_pm_setup(struct drm_device *dev)
907b28c5 8016{
fac5e23e 8017 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8018
f742a552 8019 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8020 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8021
54b4f68f
CW		 8022 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8023 __intel_autoenable_gt_powersave);
1854d5ca 8024 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8025
33688d95 8026 dev_priv->pm.suspended = false;
1f814dac 8027 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 8028}
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