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drm/i915: We implement WaFbcAsynchFlipDisableFbcQueue on ilk and snb
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
057d3860 35#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 36
f6750b3c
ED		 37/* FBC, or Frame Buffer Compression, is a technique employed to compress the
38 * framebuffer contents in-memory, aiming at reducing the required bandwidth
39 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 40 *
f6750b3c
ED		 41 * The benefits of FBC are mostly visible with solid backgrounds and
42 * variation-less patterns.
85208be0 43 *
f6750b3c
ED		 44 * FBC-related functionality can be enabled by the means of the
45 * i915.i915_enable_fbc parameter
85208be0
ED		 46 */
47
3490ea5d
CW		 48static bool intel_crtc_active(struct drm_crtc *crtc)
49{
50 /* Be paranoid as we can arrive here with only partial
51 * state retrieved from the hardware during setup.
52 */
53 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
54}
55
1fa61106 56static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 57{
58 struct drm_i915_private *dev_priv = dev->dev_private;
59 u32 fbc_ctl;
60
61 /* Disable compression */
62 fbc_ctl = I915_READ(FBC_CONTROL);
63 if ((fbc_ctl & FBC_CTL_EN) == 0)
64 return;
65
66 fbc_ctl &= ~FBC_CTL_EN;
67 I915_WRITE(FBC_CONTROL, fbc_ctl);
68
69 /* Wait for compressing bit to clear */
70 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
71 DRM_DEBUG_KMS("FBC idle timed out\n");
72 return;
73 }
74
75 DRM_DEBUG_KMS("disabled FBC\n");
76}
77
1fa61106 78static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 79{
80 struct drm_device *dev = crtc->dev;
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 struct drm_framebuffer *fb = crtc->fb;
83 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
84 struct drm_i915_gem_object *obj = intel_fb->obj;
85 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
86 int cfb_pitch;
87 int plane, i;
88 u32 fbc_ctl, fbc_ctl2;
89
5c3fe8b0 90 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 91 if (fb->pitches[0] < cfb_pitch)
92 cfb_pitch = fb->pitches[0];
93
94 /* FBC_CTL wants 64B units */
95 cfb_pitch = (cfb_pitch / 64) - 1;
96 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
97
98 /* Clear old tags */
99 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
100 I915_WRITE(FBC_TAG + (i * 4), 0);
101
102 /* Set it up... */
103 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
104 fbc_ctl2 |= plane;
105 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
106 I915_WRITE(FBC_FENCE_OFF, crtc->y);
107
108 /* enable it... */
109 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
110 if (IS_I945GM(dev))
111 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
112 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
113 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
114 fbc_ctl |= obj->fence_reg;
115 I915_WRITE(FBC_CONTROL, fbc_ctl);
116
84f44ce7
VS		 117 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
118 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 119}
120
1fa61106 121static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 122{
123 struct drm_i915_private *dev_priv = dev->dev_private;
124
125 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
126}
127
1fa61106 128static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 129{
130 struct drm_device *dev = crtc->dev;
131 struct drm_i915_private *dev_priv = dev->dev_private;
132 struct drm_framebuffer *fb = crtc->fb;
133 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
134 struct drm_i915_gem_object *obj = intel_fb->obj;
135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
136 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
137 unsigned long stall_watermark = 200;
138 u32 dpfc_ctl;
139
140 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
141 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
142 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
143
144 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
145 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
146 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
147 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
148
149 /* enable it... */
150 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
151
84f44ce7 152 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 153}
154
1fa61106 155static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 156{
157 struct drm_i915_private *dev_priv = dev->dev_private;
158 u32 dpfc_ctl;
159
160 /* Disable compression */
161 dpfc_ctl = I915_READ(DPFC_CONTROL);
162 if (dpfc_ctl & DPFC_CTL_EN) {
163 dpfc_ctl &= ~DPFC_CTL_EN;
164 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
165
166 DRM_DEBUG_KMS("disabled FBC\n");
167 }
168}
169
1fa61106 170static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 171{
172 struct drm_i915_private *dev_priv = dev->dev_private;
173
174 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
175}
176
177static void sandybridge_blit_fbc_update(struct drm_device *dev)
178{
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 u32 blt_ecoskpd;
181
182 /* Make sure blitter notifies FBC of writes */
183 gen6_gt_force_wake_get(dev_priv);
184 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
185 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
186 GEN6_BLITTER_LOCK_SHIFT;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
189 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
190 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
191 GEN6_BLITTER_LOCK_SHIFT);
192 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
193 POSTING_READ(GEN6_BLITTER_ECOSKPD);
194 gen6_gt_force_wake_put(dev_priv);
195}
196
1fa61106 197static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 198{
199 struct drm_device *dev = crtc->dev;
200 struct drm_i915_private *dev_priv = dev->dev_private;
201 struct drm_framebuffer *fb = crtc->fb;
202 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
203 struct drm_i915_gem_object *obj = intel_fb->obj;
204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
205 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
206 unsigned long stall_watermark = 200;
207 u32 dpfc_ctl;
208
209 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
210 dpfc_ctl &= DPFC_RESERVED;
211 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
212 /* Set persistent mode for front-buffer rendering, ala X. */
213 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
214 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
215 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
216
217 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
218 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
219 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
220 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 221 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 222 /* enable it... */
223 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
224
225 if (IS_GEN6(dev)) {
226 I915_WRITE(SNB_DPFC_CTL_SA,
227 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
228 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
229 sandybridge_blit_fbc_update(dev);
230 }
231
84f44ce7 232 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 233}
234
1fa61106 235static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 236{
237 struct drm_i915_private *dev_priv = dev->dev_private;
238 u32 dpfc_ctl;
239
240 /* Disable compression */
241 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
242 if (dpfc_ctl & DPFC_CTL_EN) {
243 dpfc_ctl &= ~DPFC_CTL_EN;
244 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
245
b74ea102 246 if (IS_IVYBRIDGE(dev))
7dd23ba0 247 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 248 I915_WRITE(ILK_DSPCLK_GATE_D,
249 I915_READ(ILK_DSPCLK_GATE_D) &
250 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
251
d89f2071 252 if (IS_HASWELL(dev))
7dd23ba0 253 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 254 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
255 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
256 ~HSW_DPFC_GATING_DISABLE);
257
85208be0
ED		 258 DRM_DEBUG_KMS("disabled FBC\n");
259 }
260}
261
1fa61106 262static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 263{
264 struct drm_i915_private *dev_priv = dev->dev_private;
265
266 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
267}
268
abe959c7
RV		 269static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
270{
271 struct drm_device *dev = crtc->dev;
272 struct drm_i915_private *dev_priv = dev->dev_private;
273 struct drm_framebuffer *fb = crtc->fb;
274 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
275 struct drm_i915_gem_object *obj = intel_fb->obj;
276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
277
f343c5f6 278 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 279
280 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
281 IVB_DPFC_CTL_FENCE_EN |
282 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
283
891348b2 284 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 285 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 286 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 287 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 288 I915_WRITE(ILK_DSPCLK_GATE_D,
289 I915_READ(ILK_DSPCLK_GATE_D) |
290 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 291 } else {
7dd23ba0 292 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 293 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
294 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 295 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 296 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
297 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
298 HSW_DPFC_GATING_DISABLE);
891348b2 299 }
b74ea102 300
abe959c7
RV		 301 I915_WRITE(SNB_DPFC_CTL_SA,
302 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304
305 sandybridge_blit_fbc_update(dev);
306
307 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
308}
309
85208be0
ED		 310bool intel_fbc_enabled(struct drm_device *dev)
311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.fbc_enabled)
315 return false;
316
317 return dev_priv->display.fbc_enabled(dev);
318}
319
320static void intel_fbc_work_fn(struct work_struct *__work)
321{
322 struct intel_fbc_work *work =
323 container_of(to_delayed_work(__work),
324 struct intel_fbc_work, work);
325 struct drm_device *dev = work->crtc->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327
328 mutex_lock(&dev->struct_mutex);
5c3fe8b0 329 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 330 /* Double check that we haven't switched fb without cancelling
331 * the prior work.
332 */
333 if (work->crtc->fb == work->fb) {
334 dev_priv->display.enable_fbc(work->crtc,
335 work->interval);
336
5c3fe8b0
BW		 337 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
338 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
339 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 340 }
341
5c3fe8b0 342 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 343 }
344 mutex_unlock(&dev->struct_mutex);
345
346 kfree(work);
347}
348
349static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
350{
5c3fe8b0 351 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 352 return;
353
354 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
355
356 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 357 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 358 * entirely asynchronously.
359 */
5c3fe8b0 360 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 361 /* tasklet was killed before being run, clean up */
5c3fe8b0 362 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 363
364 /* Mark the work as no longer wanted so that if it does
365 * wake-up (because the work was already running and waiting
366 * for our mutex), it will discover that is no longer
367 * necessary to run.
368 */
5c3fe8b0 369 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 370}
371
b63fb44c 372static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 373{
374 struct intel_fbc_work *work;
375 struct drm_device *dev = crtc->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377
378 if (!dev_priv->display.enable_fbc)
379 return;
380
381 intel_cancel_fbc_work(dev_priv);
382
383 work = kzalloc(sizeof *work, GFP_KERNEL);
384 if (work == NULL) {
6cdcb5e7 385 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 386 dev_priv->display.enable_fbc(crtc, interval);
387 return;
388 }
389
390 work->crtc = crtc;
391 work->fb = crtc->fb;
392 work->interval = interval;
393 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
394
5c3fe8b0 395 dev_priv->fbc.fbc_work = work;
85208be0 396
85208be0
ED		 397 /* Delay the actual enabling to let pageflipping cease and the
398 * display to settle before starting the compression. Note that
399 * this delay also serves a second purpose: it allows for a
400 * vblank to pass after disabling the FBC before we attempt
401 * to modify the control registers.
402 *
403 * A more complicated solution would involve tracking vblanks
404 * following the termination of the page-flipping sequence
405 * and indeed performing the enable as a co-routine and not
406 * waiting synchronously upon the vblank.
7457d617
DL		 407 *
408 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 409 */
410 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
411}
412
413void intel_disable_fbc(struct drm_device *dev)
414{
415 struct drm_i915_private *dev_priv = dev->dev_private;
416
417 intel_cancel_fbc_work(dev_priv);
418
419 if (!dev_priv->display.disable_fbc)
420 return;
421
422 dev_priv->display.disable_fbc(dev);
5c3fe8b0 423 dev_priv->fbc.plane = -1;
85208be0
ED		 424}
425
426/**
427 * intel_update_fbc - enable/disable FBC as needed
428 * @dev: the drm_device
429 *
430 * Set up the framebuffer compression hardware at mode set time. We
431 * enable it if possible:
432 * - plane A only (on pre-965)
433 * - no pixel mulitply/line duplication
434 * - no alpha buffer discard
435 * - no dual wide
f85da868 436 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 437 *
438 * We can't assume that any compression will take place (worst case),
439 * so the compressed buffer has to be the same size as the uncompressed
440 * one. It also must reside (along with the line length buffer) in
441 * stolen memory.
442 *
443 * We need to enable/disable FBC on a global basis.
444 */
445void intel_update_fbc(struct drm_device *dev)
446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 struct drm_crtc *crtc = NULL, *tmp_crtc;
449 struct intel_crtc *intel_crtc;
450 struct drm_framebuffer *fb;
451 struct intel_framebuffer *intel_fb;
452 struct drm_i915_gem_object *obj;
f85da868 453 unsigned int max_hdisplay, max_vdisplay;
85208be0 454
85208be0
ED		 455 if (!i915_powersave)
456 return;
457
458 if (!I915_HAS_FBC(dev))
459 return;
460
461 /*
462 * If FBC is already on, we just have to verify that we can
463 * keep it that way...
464 * Need to disable if:
465 * - more than one pipe is active
466 * - changing FBC params (stride, fence, mode)
467 * - new fb is too large to fit in compressed buffer
468 * - going to an unsupported config (interlace, pixel multiply, etc.)
469 */
470 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 471 if (intel_crtc_active(tmp_crtc) &&
472 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 473 if (crtc) {
474 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
5c3fe8b0
BW		 475 dev_priv->fbc.no_fbc_reason =
476 FBC_MULTIPLE_PIPES;
85208be0
ED		 477 goto out_disable;
478 }
479 crtc = tmp_crtc;
480 }
481 }
482
483 if (!crtc || crtc->fb == NULL) {
484 DRM_DEBUG_KMS("no output, disabling\n");
5c3fe8b0 485 dev_priv->fbc.no_fbc_reason = FBC_NO_OUTPUT;
85208be0
ED		 486 goto out_disable;
487 }
488
489 intel_crtc = to_intel_crtc(crtc);
490 fb = crtc->fb;
491 intel_fb = to_intel_framebuffer(fb);
492 obj = intel_fb->obj;
493
8a5729a3
DL		 494 if (i915_enable_fbc < 0 &&
495 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
496 DRM_DEBUG_KMS("disabled per chip default\n");
5c3fe8b0 497 dev_priv->fbc.no_fbc_reason = FBC_CHIP_DEFAULT;
8a5729a3 498 goto out_disable;
85208be0 499 }
8a5729a3 500 if (!i915_enable_fbc) {
85208be0 501 DRM_DEBUG_KMS("fbc disabled per module param\n");
5c3fe8b0 502 dev_priv->fbc.no_fbc_reason = FBC_MODULE_PARAM;
85208be0
ED		 503 goto out_disable;
504 }
85208be0
ED		 505 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
506 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
507 DRM_DEBUG_KMS("mode incompatible with compression, "
508 "disabling\n");
5c3fe8b0 509 dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED_MODE;
85208be0
ED		 510 goto out_disable;
511 }
f85da868
PZ		 512
513 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
514 max_hdisplay = 4096;
515 max_vdisplay = 2048;
516 } else {
517 max_hdisplay = 2048;
518 max_vdisplay = 1536;
519 }
520 if ((crtc->mode.hdisplay > max_hdisplay) ||
521 (crtc->mode.vdisplay > max_vdisplay)) {
85208be0 522 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
5c3fe8b0 523 dev_priv->fbc.no_fbc_reason = FBC_MODE_TOO_LARGE;
85208be0
ED		 524 goto out_disable;
525 }
891348b2
RV		 526 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
527 intel_crtc->plane != 0) {
85208be0 528 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
5c3fe8b0 529 dev_priv->fbc.no_fbc_reason = FBC_BAD_PLANE;
85208be0
ED		 530 goto out_disable;
531 }
532
533 /* The use of a CPU fence is mandatory in order to detect writes
534 * by the CPU to the scanout and trigger updates to the FBC.
535 */
536 if (obj->tiling_mode != I915_TILING_X ||
537 obj->fence_reg == I915_FENCE_REG_NONE) {
538 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
5c3fe8b0 539 dev_priv->fbc.no_fbc_reason = FBC_NOT_TILED;
85208be0
ED		 540 goto out_disable;
541 }
542
543 /* If the kernel debugger is active, always disable compression */
544 if (in_dbg_master())
545 goto out_disable;
546
11be49eb 547 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
11be49eb 548 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
5c3fe8b0 549 dev_priv->fbc.no_fbc_reason = FBC_STOLEN_TOO_SMALL;
11be49eb
CW		 550 goto out_disable;
551 }
552
85208be0
ED		 553 /* If the scanout has not changed, don't modify the FBC settings.
554 * Note that we make the fundamental assumption that the fb->obj
555 * cannot be unpinned (and have its GTT offset and fence revoked)
556 * without first being decoupled from the scanout and FBC disabled.
557 */
5c3fe8b0
BW		 558 if (dev_priv->fbc.plane == intel_crtc->plane &&
559 dev_priv->fbc.fb_id == fb->base.id &&
560 dev_priv->fbc.y == crtc->y)
85208be0
ED		 561 return;
562
563 if (intel_fbc_enabled(dev)) {
564 /* We update FBC along two paths, after changing fb/crtc
565 * configuration (modeswitching) and after page-flipping
566 * finishes. For the latter, we know that not only did
567 * we disable the FBC at the start of the page-flip
568 * sequence, but also more than one vblank has passed.
569 *
570 * For the former case of modeswitching, it is possible
571 * to switch between two FBC valid configurations
572 * instantaneously so we do need to disable the FBC
573 * before we can modify its control registers. We also
574 * have to wait for the next vblank for that to take
575 * effect. However, since we delay enabling FBC we can
576 * assume that a vblank has passed since disabling and
577 * that we can safely alter the registers in the deferred
578 * callback.
579 *
580 * In the scenario that we go from a valid to invalid
581 * and then back to valid FBC configuration we have
582 * no strict enforcement that a vblank occurred since
583 * disabling the FBC. However, along all current pipe
584 * disabling paths we do need to wait for a vblank at
585 * some point. And we wait before enabling FBC anyway.
586 */
587 DRM_DEBUG_KMS("disabling active FBC for update\n");
588 intel_disable_fbc(dev);
589 }
590
591 intel_enable_fbc(crtc, 500);
592 return;
593
594out_disable:
595 /* Multiple disables should be harmless */
596 if (intel_fbc_enabled(dev)) {
597 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
598 intel_disable_fbc(dev);
599 }
11be49eb 600 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 601}
602
c921aba8
DV		 603static void i915_pineview_get_mem_freq(struct drm_device *dev)
604{
605 drm_i915_private_t *dev_priv = dev->dev_private;
606 u32 tmp;
607
608 tmp = I915_READ(CLKCFG);
609
610 switch (tmp & CLKCFG_FSB_MASK) {
611 case CLKCFG_FSB_533:
612 dev_priv->fsb_freq = 533; /* 133*4 */
613 break;
614 case CLKCFG_FSB_800:
615 dev_priv->fsb_freq = 800; /* 200*4 */
616 break;
617 case CLKCFG_FSB_667:
618 dev_priv->fsb_freq = 667; /* 167*4 */
619 break;
620 case CLKCFG_FSB_400:
621 dev_priv->fsb_freq = 400; /* 100*4 */
622 break;
623 }
624
625 switch (tmp & CLKCFG_MEM_MASK) {
626 case CLKCFG_MEM_533:
627 dev_priv->mem_freq = 533;
628 break;
629 case CLKCFG_MEM_667:
630 dev_priv->mem_freq = 667;
631 break;
632 case CLKCFG_MEM_800:
633 dev_priv->mem_freq = 800;
634 break;
635 }
636
637 /* detect pineview DDR3 setting */
638 tmp = I915_READ(CSHRDDR3CTL);
639 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
640}
641
642static void i915_ironlake_get_mem_freq(struct drm_device *dev)
643{
644 drm_i915_private_t *dev_priv = dev->dev_private;
645 u16 ddrpll, csipll;
646
647 ddrpll = I915_READ16(DDRMPLL1);
648 csipll = I915_READ16(CSIPLL0);
649
650 switch (ddrpll & 0xff) {
651 case 0xc:
652 dev_priv->mem_freq = 800;
653 break;
654 case 0x10:
655 dev_priv->mem_freq = 1066;
656 break;
657 case 0x14:
658 dev_priv->mem_freq = 1333;
659 break;
660 case 0x18:
661 dev_priv->mem_freq = 1600;
662 break;
663 default:
664 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
665 ddrpll & 0xff);
666 dev_priv->mem_freq = 0;
667 break;
668 }
669
20e4d407 670 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 671
672 switch (csipll & 0x3ff) {
673 case 0x00c:
674 dev_priv->fsb_freq = 3200;
675 break;
676 case 0x00e:
677 dev_priv->fsb_freq = 3733;
678 break;
679 case 0x010:
680 dev_priv->fsb_freq = 4266;
681 break;
682 case 0x012:
683 dev_priv->fsb_freq = 4800;
684 break;
685 case 0x014:
686 dev_priv->fsb_freq = 5333;
687 break;
688 case 0x016:
689 dev_priv->fsb_freq = 5866;
690 break;
691 case 0x018:
692 dev_priv->fsb_freq = 6400;
693 break;
694 default:
695 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
696 csipll & 0x3ff);
697 dev_priv->fsb_freq = 0;
698 break;
699 }
700
701 if (dev_priv->fsb_freq == 3200) {
20e4d407 702 dev_priv->ips.c_m = 0;
c921aba8 703 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 704 dev_priv->ips.c_m = 1;
c921aba8 705 } else {
20e4d407 706 dev_priv->ips.c_m = 2;
c921aba8
DV		 707 }
708}
709
b445e3b0
ED		 710static const struct cxsr_latency cxsr_latency_table[] = {
711 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
712 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
713 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
714 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
715 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
716
717 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
718 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
719 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
720 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
721 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
722
723 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
724 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
725 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
726 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
727 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
728
729 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
730 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
731 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
732 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
733 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
734
735 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
736 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
737 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
738 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
739 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
740
741 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
742 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
743 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
744 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
745 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
746};
747
63c62275 748static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 749 int is_ddr3,
750 int fsb,
751 int mem)
752{
753 const struct cxsr_latency *latency;
754 int i;
755
756 if (fsb == 0 || mem == 0)
757 return NULL;
758
759 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
760 latency = &cxsr_latency_table[i];
761 if (is_desktop == latency->is_desktop &&
762 is_ddr3 == latency->is_ddr3 &&
763 fsb == latency->fsb_freq && mem == latency->mem_freq)
764 return latency;
765 }
766
767 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
768
769 return NULL;
770}
771
1fa61106 772static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 773{
774 struct drm_i915_private *dev_priv = dev->dev_private;
775
776 /* deactivate cxsr */
777 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
778}
779
780/*
781 * Latency for FIFO fetches is dependent on several factors:
782 * - memory configuration (speed, channels)
783 * - chipset
784 * - current MCH state
785 * It can be fairly high in some situations, so here we assume a fairly
786 * pessimal value. It's a tradeoff between extra memory fetches (if we
787 * set this value too high, the FIFO will fetch frequently to stay full)
788 * and power consumption (set it too low to save power and we might see
789 * FIFO underruns and display "flicker").
790 *
791 * A value of 5us seems to be a good balance; safe for very low end
792 * platforms but not overly aggressive on lower latency configs.
793 */
794static const int latency_ns = 5000;
795
1fa61106 796static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 797{
798 struct drm_i915_private *dev_priv = dev->dev_private;
799 uint32_t dsparb = I915_READ(DSPARB);
800 int size;
801
802 size = dsparb & 0x7f;
803 if (plane)
804 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
805
806 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
807 plane ? "B" : "A", size);
808
809 return size;
810}
811
1fa61106 812static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 813{
814 struct drm_i915_private *dev_priv = dev->dev_private;
815 uint32_t dsparb = I915_READ(DSPARB);
816 int size;
817
818 size = dsparb & 0x1ff;
819 if (plane)
820 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
821 size >>= 1; /* Convert to cachelines */
822
823 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
824 plane ? "B" : "A", size);
825
826 return size;
827}
828
1fa61106 829static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 830{
831 struct drm_i915_private *dev_priv = dev->dev_private;
832 uint32_t dsparb = I915_READ(DSPARB);
833 int size;
834
835 size = dsparb & 0x7f;
836 size >>= 2; /* Convert to cachelines */
837
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
839 plane ? "B" : "A",
840 size);
841
842 return size;
843}
844
1fa61106 845static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 846{
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 uint32_t dsparb = I915_READ(DSPARB);
849 int size;
850
851 size = dsparb & 0x7f;
852 size >>= 1; /* Convert to cachelines */
853
854 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
855 plane ? "B" : "A", size);
856
857 return size;
858}
859
860/* Pineview has different values for various configs */
861static const struct intel_watermark_params pineview_display_wm = {
862 PINEVIEW_DISPLAY_FIFO,
863 PINEVIEW_MAX_WM,
864 PINEVIEW_DFT_WM,
865 PINEVIEW_GUARD_WM,
866 PINEVIEW_FIFO_LINE_SIZE
867};
868static const struct intel_watermark_params pineview_display_hplloff_wm = {
869 PINEVIEW_DISPLAY_FIFO,
870 PINEVIEW_MAX_WM,
871 PINEVIEW_DFT_HPLLOFF_WM,
872 PINEVIEW_GUARD_WM,
873 PINEVIEW_FIFO_LINE_SIZE
874};
875static const struct intel_watermark_params pineview_cursor_wm = {
876 PINEVIEW_CURSOR_FIFO,
877 PINEVIEW_CURSOR_MAX_WM,
878 PINEVIEW_CURSOR_DFT_WM,
879 PINEVIEW_CURSOR_GUARD_WM,
880 PINEVIEW_FIFO_LINE_SIZE,
881};
882static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE
888};
889static const struct intel_watermark_params g4x_wm_info = {
890 G4X_FIFO_SIZE,
891 G4X_MAX_WM,
892 G4X_MAX_WM,
893 2,
894 G4X_FIFO_LINE_SIZE,
895};
896static const struct intel_watermark_params g4x_cursor_wm_info = {
897 I965_CURSOR_FIFO,
898 I965_CURSOR_MAX_WM,
899 I965_CURSOR_DFT_WM,
900 2,
901 G4X_FIFO_LINE_SIZE,
902};
903static const struct intel_watermark_params valleyview_wm_info = {
904 VALLEYVIEW_FIFO_SIZE,
905 VALLEYVIEW_MAX_WM,
906 VALLEYVIEW_MAX_WM,
907 2,
908 G4X_FIFO_LINE_SIZE,
909};
910static const struct intel_watermark_params valleyview_cursor_wm_info = {
911 I965_CURSOR_FIFO,
912 VALLEYVIEW_CURSOR_MAX_WM,
913 I965_CURSOR_DFT_WM,
914 2,
915 G4X_FIFO_LINE_SIZE,
916};
917static const struct intel_watermark_params i965_cursor_wm_info = {
918 I965_CURSOR_FIFO,
919 I965_CURSOR_MAX_WM,
920 I965_CURSOR_DFT_WM,
921 2,
922 I915_FIFO_LINE_SIZE,
923};
924static const struct intel_watermark_params i945_wm_info = {
925 I945_FIFO_SIZE,
926 I915_MAX_WM,
927 1,
928 2,
929 I915_FIFO_LINE_SIZE
930};
931static const struct intel_watermark_params i915_wm_info = {
932 I915_FIFO_SIZE,
933 I915_MAX_WM,
934 1,
935 2,
936 I915_FIFO_LINE_SIZE
937};
938static const struct intel_watermark_params i855_wm_info = {
939 I855GM_FIFO_SIZE,
940 I915_MAX_WM,
941 1,
942 2,
943 I830_FIFO_LINE_SIZE
944};
945static const struct intel_watermark_params i830_wm_info = {
946 I830_FIFO_SIZE,
947 I915_MAX_WM,
948 1,
949 2,
950 I830_FIFO_LINE_SIZE
951};
952
953static const struct intel_watermark_params ironlake_display_wm_info = {
954 ILK_DISPLAY_FIFO,
955 ILK_DISPLAY_MAXWM,
956 ILK_DISPLAY_DFTWM,
957 2,
958 ILK_FIFO_LINE_SIZE
959};
960static const struct intel_watermark_params ironlake_cursor_wm_info = {
961 ILK_CURSOR_FIFO,
962 ILK_CURSOR_MAXWM,
963 ILK_CURSOR_DFTWM,
964 2,
965 ILK_FIFO_LINE_SIZE
966};
967static const struct intel_watermark_params ironlake_display_srwm_info = {
968 ILK_DISPLAY_SR_FIFO,
969 ILK_DISPLAY_MAX_SRWM,
970 ILK_DISPLAY_DFT_SRWM,
971 2,
972 ILK_FIFO_LINE_SIZE
973};
974static const struct intel_watermark_params ironlake_cursor_srwm_info = {
975 ILK_CURSOR_SR_FIFO,
976 ILK_CURSOR_MAX_SRWM,
977 ILK_CURSOR_DFT_SRWM,
978 2,
979 ILK_FIFO_LINE_SIZE
980};
981
982static const struct intel_watermark_params sandybridge_display_wm_info = {
983 SNB_DISPLAY_FIFO,
984 SNB_DISPLAY_MAXWM,
985 SNB_DISPLAY_DFTWM,
986 2,
987 SNB_FIFO_LINE_SIZE
988};
989static const struct intel_watermark_params sandybridge_cursor_wm_info = {
990 SNB_CURSOR_FIFO,
991 SNB_CURSOR_MAXWM,
992 SNB_CURSOR_DFTWM,
993 2,
994 SNB_FIFO_LINE_SIZE
995};
996static const struct intel_watermark_params sandybridge_display_srwm_info = {
997 SNB_DISPLAY_SR_FIFO,
998 SNB_DISPLAY_MAX_SRWM,
999 SNB_DISPLAY_DFT_SRWM,
1000 2,
1001 SNB_FIFO_LINE_SIZE
1002};
1003static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1004 SNB_CURSOR_SR_FIFO,
1005 SNB_CURSOR_MAX_SRWM,
1006 SNB_CURSOR_DFT_SRWM,
1007 2,
1008 SNB_FIFO_LINE_SIZE
1009};
1010
1011
1012/**
1013 * intel_calculate_wm - calculate watermark level
1014 * @clock_in_khz: pixel clock
1015 * @wm: chip FIFO params
1016 * @pixel_size: display pixel size
1017 * @latency_ns: memory latency for the platform
1018 *
1019 * Calculate the watermark level (the level at which the display plane will
1020 * start fetching from memory again). Each chip has a different display
1021 * FIFO size and allocation, so the caller needs to figure that out and pass
1022 * in the correct intel_watermark_params structure.
1023 *
1024 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1025 * on the pixel size. When it reaches the watermark level, it'll start
1026 * fetching FIFO line sized based chunks from memory until the FIFO fills
1027 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1028 * will occur, and a display engine hang could result.
1029 */
1030static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1031 const struct intel_watermark_params *wm,
1032 int fifo_size,
1033 int pixel_size,
1034 unsigned long latency_ns)
1035{
1036 long entries_required, wm_size;
1037
1038 /*
1039 * Note: we need to make sure we don't overflow for various clock &
1040 * latency values.
1041 * clocks go from a few thousand to several hundred thousand.
1042 * latency is usually a few thousand
1043 */
1044 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1045 1000;
1046 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1047
1048 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1049
1050 wm_size = fifo_size - (entries_required + wm->guard_size);
1051
1052 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1053
1054 /* Don't promote wm_size to unsigned... */
1055 if (wm_size > (long)wm->max_wm)
1056 wm_size = wm->max_wm;
1057 if (wm_size <= 0)
1058 wm_size = wm->default_wm;
1059 return wm_size;
1060}
1061
1062static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1063{
1064 struct drm_crtc *crtc, *enabled = NULL;
1065
1066 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1067 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1068 if (enabled)
1069 return NULL;
1070 enabled = crtc;
1071 }
1072 }
1073
1074 return enabled;
1075}
1076
1fa61106 1077static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1078{
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 struct drm_crtc *crtc;
1081 const struct cxsr_latency *latency;
1082 u32 reg;
1083 unsigned long wm;
1084
1085 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1086 dev_priv->fsb_freq, dev_priv->mem_freq);
1087 if (!latency) {
1088 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1089 pineview_disable_cxsr(dev);
1090 return;
1091 }
1092
1093 crtc = single_enabled_crtc(dev);
1094 if (crtc) {
1095 int clock = crtc->mode.clock;
1096 int pixel_size = crtc->fb->bits_per_pixel / 8;
1097
1098 /* Display SR */
1099 wm = intel_calculate_wm(clock, &pineview_display_wm,
1100 pineview_display_wm.fifo_size,
1101 pixel_size, latency->display_sr);
1102 reg = I915_READ(DSPFW1);
1103 reg &= ~DSPFW_SR_MASK;
1104 reg |= wm << DSPFW_SR_SHIFT;
1105 I915_WRITE(DSPFW1, reg);
1106 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1107
1108 /* cursor SR */
1109 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1110 pineview_display_wm.fifo_size,
1111 pixel_size, latency->cursor_sr);
1112 reg = I915_READ(DSPFW3);
1113 reg &= ~DSPFW_CURSOR_SR_MASK;
1114 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1115 I915_WRITE(DSPFW3, reg);
1116
1117 /* Display HPLL off SR */
1118 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1119 pineview_display_hplloff_wm.fifo_size,
1120 pixel_size, latency->display_hpll_disable);
1121 reg = I915_READ(DSPFW3);
1122 reg &= ~DSPFW_HPLL_SR_MASK;
1123 reg |= wm & DSPFW_HPLL_SR_MASK;
1124 I915_WRITE(DSPFW3, reg);
1125
1126 /* cursor HPLL off SR */
1127 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1128 pineview_display_hplloff_wm.fifo_size,
1129 pixel_size, latency->cursor_hpll_disable);
1130 reg = I915_READ(DSPFW3);
1131 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1132 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1133 I915_WRITE(DSPFW3, reg);
1134 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1135
1136 /* activate cxsr */
1137 I915_WRITE(DSPFW3,
1138 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1139 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1140 } else {
1141 pineview_disable_cxsr(dev);
1142 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1143 }
1144}
1145
1146static bool g4x_compute_wm0(struct drm_device *dev,
1147 int plane,
1148 const struct intel_watermark_params *display,
1149 int display_latency_ns,
1150 const struct intel_watermark_params *cursor,
1151 int cursor_latency_ns,
1152 int *plane_wm,
1153 int *cursor_wm)
1154{
1155 struct drm_crtc *crtc;
1156 int htotal, hdisplay, clock, pixel_size;
1157 int line_time_us, line_count;
1158 int entries, tlb_miss;
1159
1160 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1161 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1162 *cursor_wm = cursor->guard_size;
1163 *plane_wm = display->guard_size;
1164 return false;
1165 }
1166
1167 htotal = crtc->mode.htotal;
1168 hdisplay = crtc->mode.hdisplay;
1169 clock = crtc->mode.clock;
1170 pixel_size = crtc->fb->bits_per_pixel / 8;
1171
1172 /* Use the small buffer method to calculate plane watermark */
1173 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1174 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1175 if (tlb_miss > 0)
1176 entries += tlb_miss;
1177 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1178 *plane_wm = entries + display->guard_size;
1179 if (*plane_wm > (int)display->max_wm)
1180 *plane_wm = display->max_wm;
1181
1182 /* Use the large buffer method to calculate cursor watermark */
1183 line_time_us = ((htotal * 1000) / clock);
1184 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1185 entries = line_count * 64 * pixel_size;
1186 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1187 if (tlb_miss > 0)
1188 entries += tlb_miss;
1189 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1190 *cursor_wm = entries + cursor->guard_size;
1191 if (*cursor_wm > (int)cursor->max_wm)
1192 *cursor_wm = (int)cursor->max_wm;
1193
1194 return true;
1195}
1196
1197/*
1198 * Check the wm result.
1199 *
1200 * If any calculated watermark values is larger than the maximum value that
1201 * can be programmed into the associated watermark register, that watermark
1202 * must be disabled.
1203 */
1204static bool g4x_check_srwm(struct drm_device *dev,
1205 int display_wm, int cursor_wm,
1206 const struct intel_watermark_params *display,
1207 const struct intel_watermark_params *cursor)
1208{
1209 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1210 display_wm, cursor_wm);
1211
1212 if (display_wm > display->max_wm) {
1213 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1214 display_wm, display->max_wm);
1215 return false;
1216 }
1217
1218 if (cursor_wm > cursor->max_wm) {
1219 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1220 cursor_wm, cursor->max_wm);
1221 return false;
1222 }
1223
1224 if (!(display_wm || cursor_wm)) {
1225 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1226 return false;
1227 }
1228
1229 return true;
1230}
1231
1232static bool g4x_compute_srwm(struct drm_device *dev,
1233 int plane,
1234 int latency_ns,
1235 const struct intel_watermark_params *display,
1236 const struct intel_watermark_params *cursor,
1237 int *display_wm, int *cursor_wm)
1238{
1239 struct drm_crtc *crtc;
1240 int hdisplay, htotal, pixel_size, clock;
1241 unsigned long line_time_us;
1242 int line_count, line_size;
1243 int small, large;
1244 int entries;
1245
1246 if (!latency_ns) {
1247 *display_wm = *cursor_wm = 0;
1248 return false;
1249 }
1250
1251 crtc = intel_get_crtc_for_plane(dev, plane);
1252 hdisplay = crtc->mode.hdisplay;
1253 htotal = crtc->mode.htotal;
1254 clock = crtc->mode.clock;
1255 pixel_size = crtc->fb->bits_per_pixel / 8;
1256
1257 line_time_us = (htotal * 1000) / clock;
1258 line_count = (latency_ns / line_time_us + 1000) / 1000;
1259 line_size = hdisplay * pixel_size;
1260
1261 /* Use the minimum of the small and large buffer method for primary */
1262 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1263 large = line_count * line_size;
1264
1265 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1266 *display_wm = entries + display->guard_size;
1267
1268 /* calculate the self-refresh watermark for display cursor */
1269 entries = line_count * pixel_size * 64;
1270 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1271 *cursor_wm = entries + cursor->guard_size;
1272
1273 return g4x_check_srwm(dev,
1274 *display_wm, *cursor_wm,
1275 display, cursor);
1276}
1277
1278static bool vlv_compute_drain_latency(struct drm_device *dev,
1279 int plane,
1280 int *plane_prec_mult,
1281 int *plane_dl,
1282 int *cursor_prec_mult,
1283 int *cursor_dl)
1284{
1285 struct drm_crtc *crtc;
1286 int clock, pixel_size;
1287 int entries;
1288
1289 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1290 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1291 return false;
1292
1293 clock = crtc->mode.clock; /* VESA DOT Clock */
1294 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1295
1296 entries = (clock / 1000) * pixel_size;
1297 *plane_prec_mult = (entries > 256) ?
1298 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1299 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1300 pixel_size);
1301
1302 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1303 *cursor_prec_mult = (entries > 256) ?
1304 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1305 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1306
1307 return true;
1308}
1309
1310/*
1311 * Update drain latency registers of memory arbiter
1312 *
1313 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1314 * to be programmed. Each plane has a drain latency multiplier and a drain
1315 * latency value.
1316 */
1317
1318static void vlv_update_drain_latency(struct drm_device *dev)
1319{
1320 struct drm_i915_private *dev_priv = dev->dev_private;
1321 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1322 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1323 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1324 either 16 or 32 */
1325
1326 /* For plane A, Cursor A */
1327 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1328 &cursor_prec_mult, &cursora_dl)) {
1329 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1330 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1331 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1332 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1333
1334 I915_WRITE(VLV_DDL1, cursora_prec |
1335 (cursora_dl << DDL_CURSORA_SHIFT) |
1336 planea_prec | planea_dl);
1337 }
1338
1339 /* For plane B, Cursor B */
1340 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1341 &cursor_prec_mult, &cursorb_dl)) {
1342 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1344 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1345 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1346
1347 I915_WRITE(VLV_DDL2, cursorb_prec |
1348 (cursorb_dl << DDL_CURSORB_SHIFT) |
1349 planeb_prec | planeb_dl);
1350 }
1351}
1352
1353#define single_plane_enabled(mask) is_power_of_2(mask)
1354
1fa61106 1355static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1356{
1357 static const int sr_latency_ns = 12000;
1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1360 int plane_sr, cursor_sr;
af6c4575 1361 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1362 unsigned int enabled = 0;
1363
1364 vlv_update_drain_latency(dev);
1365
51cea1f4 1366 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1367 &valleyview_wm_info, latency_ns,
1368 &valleyview_cursor_wm_info, latency_ns,
1369 &planea_wm, &cursora_wm))
51cea1f4 1370 enabled |= 1 << PIPE_A;
b445e3b0 1371
51cea1f4 1372 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1373 &valleyview_wm_info, latency_ns,
1374 &valleyview_cursor_wm_info, latency_ns,
1375 &planeb_wm, &cursorb_wm))
51cea1f4 1376 enabled |= 1 << PIPE_B;
b445e3b0 1377
b445e3b0
ED		 1378 if (single_plane_enabled(enabled) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1380 sr_latency_ns,
1381 &valleyview_wm_info,
1382 &valleyview_cursor_wm_info,
af6c4575
CW		 1383 &plane_sr, &ignore_cursor_sr) &&
1384 g4x_compute_srwm(dev, ffs(enabled) - 1,
1385 2*sr_latency_ns,
1386 &valleyview_wm_info,
1387 &valleyview_cursor_wm_info,
52bd02d8 1388 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1389 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1390 } else {
b445e3b0
ED		 1391 I915_WRITE(FW_BLC_SELF_VLV,
1392 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1393 plane_sr = cursor_sr = 0;
1394 }
b445e3b0
ED		 1395
1396 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1397 planea_wm, cursora_wm,
1398 planeb_wm, cursorb_wm,
1399 plane_sr, cursor_sr);
1400
1401 I915_WRITE(DSPFW1,
1402 (plane_sr << DSPFW_SR_SHIFT) |
1403 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1404 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1405 planea_wm);
1406 I915_WRITE(DSPFW2,
8c919b28 1407 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1408 (cursora_wm << DSPFW_CURSORA_SHIFT));
1409 I915_WRITE(DSPFW3,
8c919b28
CW		 1410 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1411 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1412}
1413
1fa61106 1414static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1415{
1416 static const int sr_latency_ns = 12000;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1419 int plane_sr, cursor_sr;
1420 unsigned int enabled = 0;
1421
51cea1f4 1422 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1423 &g4x_wm_info, latency_ns,
1424 &g4x_cursor_wm_info, latency_ns,
1425 &planea_wm, &cursora_wm))
51cea1f4 1426 enabled |= 1 << PIPE_A;
b445e3b0 1427
51cea1f4 1428 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1429 &g4x_wm_info, latency_ns,
1430 &g4x_cursor_wm_info, latency_ns,
1431 &planeb_wm, &cursorb_wm))
51cea1f4 1432 enabled |= 1 << PIPE_B;
b445e3b0 1433
b445e3b0
ED		 1434 if (single_plane_enabled(enabled) &&
1435 g4x_compute_srwm(dev, ffs(enabled) - 1,
1436 sr_latency_ns,
1437 &g4x_wm_info,
1438 &g4x_cursor_wm_info,
52bd02d8 1439 &plane_sr, &cursor_sr)) {
b445e3b0 1440 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1441 } else {
b445e3b0
ED		 1442 I915_WRITE(FW_BLC_SELF,
1443 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1444 plane_sr = cursor_sr = 0;
1445 }
b445e3b0
ED		 1446
1447 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1448 planea_wm, cursora_wm,
1449 planeb_wm, cursorb_wm,
1450 plane_sr, cursor_sr);
1451
1452 I915_WRITE(DSPFW1,
1453 (plane_sr << DSPFW_SR_SHIFT) |
1454 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1455 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1456 planea_wm);
1457 I915_WRITE(DSPFW2,
8c919b28 1458 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1459 (cursora_wm << DSPFW_CURSORA_SHIFT));
1460 /* HPLL off in SR has some issues on G4x... disable it */
1461 I915_WRITE(DSPFW3,
8c919b28 1462 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1463 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1464}
1465
1fa61106 1466static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1467{
1468 struct drm_i915_private *dev_priv = dev->dev_private;
1469 struct drm_crtc *crtc;
1470 int srwm = 1;
1471 int cursor_sr = 16;
1472
1473 /* Calc sr entries for one plane configs */
1474 crtc = single_enabled_crtc(dev);
1475 if (crtc) {
1476 /* self-refresh has much higher latency */
1477 static const int sr_latency_ns = 12000;
1478 int clock = crtc->mode.clock;
1479 int htotal = crtc->mode.htotal;
1480 int hdisplay = crtc->mode.hdisplay;
1481 int pixel_size = crtc->fb->bits_per_pixel / 8;
1482 unsigned long line_time_us;
1483 int entries;
1484
1485 line_time_us = ((htotal * 1000) / clock);
1486
1487 /* Use ns/us then divide to preserve precision */
1488 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1489 pixel_size * hdisplay;
1490 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1491 srwm = I965_FIFO_SIZE - entries;
1492 if (srwm < 0)
1493 srwm = 1;
1494 srwm &= 0x1ff;
1495 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1496 entries, srwm);
1497
1498 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1499 pixel_size * 64;
1500 entries = DIV_ROUND_UP(entries,
1501 i965_cursor_wm_info.cacheline_size);
1502 cursor_sr = i965_cursor_wm_info.fifo_size -
1503 (entries + i965_cursor_wm_info.guard_size);
1504
1505 if (cursor_sr > i965_cursor_wm_info.max_wm)
1506 cursor_sr = i965_cursor_wm_info.max_wm;
1507
1508 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1509 "cursor %d\n", srwm, cursor_sr);
1510
1511 if (IS_CRESTLINE(dev))
1512 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1513 } else {
1514 /* Turn off self refresh if both pipes are enabled */
1515 if (IS_CRESTLINE(dev))
1516 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1517 & ~FW_BLC_SELF_EN);
1518 }
1519
1520 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1521 srwm);
1522
1523 /* 965 has limitations... */
1524 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1525 (8 << 16) | (8 << 8) | (8 << 0));
1526 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1527 /* update cursor SR watermark */
1528 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1529}
1530
1fa61106 1531static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1532{
1533 struct drm_i915_private *dev_priv = dev->dev_private;
1534 const struct intel_watermark_params *wm_info;
1535 uint32_t fwater_lo;
1536 uint32_t fwater_hi;
1537 int cwm, srwm = 1;
1538 int fifo_size;
1539 int planea_wm, planeb_wm;
1540 struct drm_crtc *crtc, *enabled = NULL;
1541
1542 if (IS_I945GM(dev))
1543 wm_info = &i945_wm_info;
1544 else if (!IS_GEN2(dev))
1545 wm_info = &i915_wm_info;
1546 else
1547 wm_info = &i855_wm_info;
1548
1549 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1550 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1551 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1552 int cpp = crtc->fb->bits_per_pixel / 8;
1553 if (IS_GEN2(dev))
1554 cpp = 4;
1555
b445e3b0 1556 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1557 wm_info, fifo_size, cpp,
b445e3b0
ED		 1558 latency_ns);
1559 enabled = crtc;
1560 } else
1561 planea_wm = fifo_size - wm_info->guard_size;
1562
1563 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1564 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1565 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1566 int cpp = crtc->fb->bits_per_pixel / 8;
1567 if (IS_GEN2(dev))
1568 cpp = 4;
1569
b445e3b0 1570 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1571 wm_info, fifo_size, cpp,
b445e3b0
ED		 1572 latency_ns);
1573 if (enabled == NULL)
1574 enabled = crtc;
1575 else
1576 enabled = NULL;
1577 } else
1578 planeb_wm = fifo_size - wm_info->guard_size;
1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
1582 /*
1583 * Overlay gets an aggressive default since video jitter is bad.
1584 */
1585 cwm = 2;
1586
1587 /* Play safe and disable self-refresh before adjusting watermarks. */
1588 if (IS_I945G(dev) || IS_I945GM(dev))
1589 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1590 else if (IS_I915GM(dev))
1591 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1592
1593 /* Calc sr entries for one plane configs */
1594 if (HAS_FW_BLC(dev) && enabled) {
1595 /* self-refresh has much higher latency */
1596 static const int sr_latency_ns = 6000;
1597 int clock = enabled->mode.clock;
1598 int htotal = enabled->mode.htotal;
1599 int hdisplay = enabled->mode.hdisplay;
1600 int pixel_size = enabled->fb->bits_per_pixel / 8;
1601 unsigned long line_time_us;
1602 int entries;
1603
1604 line_time_us = (htotal * 1000) / clock;
1605
1606 /* Use ns/us then divide to preserve precision */
1607 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1608 pixel_size * hdisplay;
1609 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1610 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1611 srwm = wm_info->fifo_size - entries;
1612 if (srwm < 0)
1613 srwm = 1;
1614
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF,
1617 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1618 else if (IS_I915GM(dev))
1619 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1620 }
1621
1622 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1623 planea_wm, planeb_wm, cwm, srwm);
1624
1625 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1626 fwater_hi = (cwm & 0x1f);
1627
1628 /* Set request length to 8 cachelines per fetch */
1629 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1630 fwater_hi = fwater_hi | (1 << 8);
1631
1632 I915_WRITE(FW_BLC, fwater_lo);
1633 I915_WRITE(FW_BLC2, fwater_hi);
1634
1635 if (HAS_FW_BLC(dev)) {
1636 if (enabled) {
1637 if (IS_I945G(dev) || IS_I945GM(dev))
1638 I915_WRITE(FW_BLC_SELF,
1639 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1640 else if (IS_I915GM(dev))
1641 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1642 DRM_DEBUG_KMS("memory self refresh enabled\n");
1643 } else
1644 DRM_DEBUG_KMS("memory self refresh disabled\n");
1645 }
1646}
1647
1fa61106 1648static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1649{
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1651 struct drm_crtc *crtc;
1652 uint32_t fwater_lo;
1653 int planea_wm;
1654
1655 crtc = single_enabled_crtc(dev);
1656 if (crtc == NULL)
1657 return;
1658
1659 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1660 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1661 4, latency_ns);
b445e3b0
ED		 1662 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1663 fwater_lo |= (3<<8) | planea_wm;
1664
1665 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1666
1667 I915_WRITE(FW_BLC, fwater_lo);
1668}
1669
1670#define ILK_LP0_PLANE_LATENCY 700
1671#define ILK_LP0_CURSOR_LATENCY 1300
1672
1673/*
1674 * Check the wm result.
1675 *
1676 * If any calculated watermark values is larger than the maximum value that
1677 * can be programmed into the associated watermark register, that watermark
1678 * must be disabled.
1679 */
1680static bool ironlake_check_srwm(struct drm_device *dev, int level,
1681 int fbc_wm, int display_wm, int cursor_wm,
1682 const struct intel_watermark_params *display,
1683 const struct intel_watermark_params *cursor)
1684{
1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686
1687 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1688 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1689
1690 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1691 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1692 fbc_wm, SNB_FBC_MAX_SRWM, level);
1693
1694 /* fbc has it's own way to disable FBC WM */
1695 I915_WRITE(DISP_ARB_CTL,
1696 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1697 return false;
615aaa5f
VS		 1698 } else if (INTEL_INFO(dev)->gen >= 6) {
1699 /* enable FBC WM (except on ILK, where it must remain off) */
1700 I915_WRITE(DISP_ARB_CTL,
1701 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1702 }
1703
1704 if (display_wm > display->max_wm) {
1705 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1706 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1707 return false;
1708 }
1709
1710 if (cursor_wm > cursor->max_wm) {
1711 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1712 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1713 return false;
1714 }
1715
1716 if (!(fbc_wm || display_wm || cursor_wm)) {
1717 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1718 return false;
1719 }
1720
1721 return true;
1722}
1723
1724/*
1725 * Compute watermark values of WM[1-3],
1726 */
1727static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1728 int latency_ns,
1729 const struct intel_watermark_params *display,
1730 const struct intel_watermark_params *cursor,
1731 int *fbc_wm, int *display_wm, int *cursor_wm)
1732{
1733 struct drm_crtc *crtc;
1734 unsigned long line_time_us;
1735 int hdisplay, htotal, pixel_size, clock;
1736 int line_count, line_size;
1737 int small, large;
1738 int entries;
1739
1740 if (!latency_ns) {
1741 *fbc_wm = *display_wm = *cursor_wm = 0;
1742 return false;
1743 }
1744
1745 crtc = intel_get_crtc_for_plane(dev, plane);
1746 hdisplay = crtc->mode.hdisplay;
1747 htotal = crtc->mode.htotal;
1748 clock = crtc->mode.clock;
1749 pixel_size = crtc->fb->bits_per_pixel / 8;
1750
1751 line_time_us = (htotal * 1000) / clock;
1752 line_count = (latency_ns / line_time_us + 1000) / 1000;
1753 line_size = hdisplay * pixel_size;
1754
1755 /* Use the minimum of the small and large buffer method for primary */
1756 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1757 large = line_count * line_size;
1758
1759 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1760 *display_wm = entries + display->guard_size;
1761
1762 /*
1763 * Spec says:
1764 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1765 */
1766 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1767
1768 /* calculate the self-refresh watermark for display cursor */
1769 entries = line_count * pixel_size * 64;
1770 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1771 *cursor_wm = entries + cursor->guard_size;
1772
1773 return ironlake_check_srwm(dev, level,
1774 *fbc_wm, *display_wm, *cursor_wm,
1775 display, cursor);
1776}
1777
1fa61106 1778static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1779{
1780 struct drm_i915_private *dev_priv = dev->dev_private;
1781 int fbc_wm, plane_wm, cursor_wm;
1782 unsigned int enabled;
1783
1784 enabled = 0;
51cea1f4 1785 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1786 &ironlake_display_wm_info,
1787 ILK_LP0_PLANE_LATENCY,
1788 &ironlake_cursor_wm_info,
1789 ILK_LP0_CURSOR_LATENCY,
1790 &plane_wm, &cursor_wm)) {
1791 I915_WRITE(WM0_PIPEA_ILK,
1792 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1793 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1794 " plane %d, " "cursor: %d\n",
1795 plane_wm, cursor_wm);
51cea1f4 1796 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1797 }
1798
51cea1f4 1799 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1800 &ironlake_display_wm_info,
1801 ILK_LP0_PLANE_LATENCY,
1802 &ironlake_cursor_wm_info,
1803 ILK_LP0_CURSOR_LATENCY,
1804 &plane_wm, &cursor_wm)) {
1805 I915_WRITE(WM0_PIPEB_ILK,
1806 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1807 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1808 " plane %d, cursor: %d\n",
1809 plane_wm, cursor_wm);
51cea1f4 1810 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1811 }
1812
1813 /*
1814 * Calculate and update the self-refresh watermark only when one
1815 * display plane is used.
1816 */
1817 I915_WRITE(WM3_LP_ILK, 0);
1818 I915_WRITE(WM2_LP_ILK, 0);
1819 I915_WRITE(WM1_LP_ILK, 0);
1820
1821 if (!single_plane_enabled(enabled))
1822 return;
1823 enabled = ffs(enabled) - 1;
1824
1825 /* WM1 */
1826 if (!ironlake_compute_srwm(dev, 1, enabled,
1827 ILK_READ_WM1_LATENCY() * 500,
1828 &ironlake_display_srwm_info,
1829 &ironlake_cursor_srwm_info,
1830 &fbc_wm, &plane_wm, &cursor_wm))
1831 return;
1832
1833 I915_WRITE(WM1_LP_ILK,
1834 WM1_LP_SR_EN |
1835 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1836 (fbc_wm << WM1_LP_FBC_SHIFT) |
1837 (plane_wm << WM1_LP_SR_SHIFT) |
1838 cursor_wm);
1839
1840 /* WM2 */
1841 if (!ironlake_compute_srwm(dev, 2, enabled,
1842 ILK_READ_WM2_LATENCY() * 500,
1843 &ironlake_display_srwm_info,
1844 &ironlake_cursor_srwm_info,
1845 &fbc_wm, &plane_wm, &cursor_wm))
1846 return;
1847
1848 I915_WRITE(WM2_LP_ILK,
1849 WM2_LP_EN |
1850 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1851 (fbc_wm << WM1_LP_FBC_SHIFT) |
1852 (plane_wm << WM1_LP_SR_SHIFT) |
1853 cursor_wm);
1854
1855 /*
1856 * WM3 is unsupported on ILK, probably because we don't have latency
1857 * data for that power state
1858 */
1859}
1860
1fa61106 1861static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1862{
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1865 u32 val;
1866 int fbc_wm, plane_wm, cursor_wm;
1867 unsigned int enabled;
1868
1869 enabled = 0;
51cea1f4 1870 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1871 &sandybridge_display_wm_info, latency,
1872 &sandybridge_cursor_wm_info, latency,
1873 &plane_wm, &cursor_wm)) {
1874 val = I915_READ(WM0_PIPEA_ILK);
1875 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1876 I915_WRITE(WM0_PIPEA_ILK, val |
1877 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1878 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1879 " plane %d, " "cursor: %d\n",
1880 plane_wm, cursor_wm);
51cea1f4 1881 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1882 }
1883
51cea1f4 1884 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1885 &sandybridge_display_wm_info, latency,
1886 &sandybridge_cursor_wm_info, latency,
1887 &plane_wm, &cursor_wm)) {
1888 val = I915_READ(WM0_PIPEB_ILK);
1889 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1890 I915_WRITE(WM0_PIPEB_ILK, val |
1891 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1892 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1893 " plane %d, cursor: %d\n",
1894 plane_wm, cursor_wm);
51cea1f4 1895 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1896 }
1897
c43d0188
CW		 1898 /*
1899 * Calculate and update the self-refresh watermark only when one
1900 * display plane is used.
1901 *
1902 * SNB support 3 levels of watermark.
1903 *
1904 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1905 * and disabled in the descending order
1906 *
1907 */
1908 I915_WRITE(WM3_LP_ILK, 0);
1909 I915_WRITE(WM2_LP_ILK, 0);
1910 I915_WRITE(WM1_LP_ILK, 0);
1911
1912 if (!single_plane_enabled(enabled) ||
1913 dev_priv->sprite_scaling_enabled)
1914 return;
1915 enabled = ffs(enabled) - 1;
1916
1917 /* WM1 */
1918 if (!ironlake_compute_srwm(dev, 1, enabled,
1919 SNB_READ_WM1_LATENCY() * 500,
1920 &sandybridge_display_srwm_info,
1921 &sandybridge_cursor_srwm_info,
1922 &fbc_wm, &plane_wm, &cursor_wm))
1923 return;
1924
1925 I915_WRITE(WM1_LP_ILK,
1926 WM1_LP_SR_EN |
1927 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1928 (fbc_wm << WM1_LP_FBC_SHIFT) |
1929 (plane_wm << WM1_LP_SR_SHIFT) |
1930 cursor_wm);
1931
1932 /* WM2 */
1933 if (!ironlake_compute_srwm(dev, 2, enabled,
1934 SNB_READ_WM2_LATENCY() * 500,
1935 &sandybridge_display_srwm_info,
1936 &sandybridge_cursor_srwm_info,
1937 &fbc_wm, &plane_wm, &cursor_wm))
1938 return;
1939
1940 I915_WRITE(WM2_LP_ILK,
1941 WM2_LP_EN |
1942 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1943 (fbc_wm << WM1_LP_FBC_SHIFT) |
1944 (plane_wm << WM1_LP_SR_SHIFT) |
1945 cursor_wm);
1946
1947 /* WM3 */
1948 if (!ironlake_compute_srwm(dev, 3, enabled,
1949 SNB_READ_WM3_LATENCY() * 500,
1950 &sandybridge_display_srwm_info,
1951 &sandybridge_cursor_srwm_info,
1952 &fbc_wm, &plane_wm, &cursor_wm))
1953 return;
1954
1955 I915_WRITE(WM3_LP_ILK,
1956 WM3_LP_EN |
1957 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1958 (fbc_wm << WM1_LP_FBC_SHIFT) |
1959 (plane_wm << WM1_LP_SR_SHIFT) |
1960 cursor_wm);
1961}
1962
1963static void ivybridge_update_wm(struct drm_device *dev)
1964{
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1967 u32 val;
1968 int fbc_wm, plane_wm, cursor_wm;
1969 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1970 unsigned int enabled;
1971
1972 enabled = 0;
51cea1f4 1973 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1974 &sandybridge_display_wm_info, latency,
1975 &sandybridge_cursor_wm_info, latency,
1976 &plane_wm, &cursor_wm)) {
1977 val = I915_READ(WM0_PIPEA_ILK);
1978 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1979 I915_WRITE(WM0_PIPEA_ILK, val |
1980 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1981 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1982 " plane %d, " "cursor: %d\n",
1983 plane_wm, cursor_wm);
51cea1f4 1984 enabled |= 1 << PIPE_A;
c43d0188
CW		 1985 }
1986
51cea1f4 1987 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 1988 &sandybridge_display_wm_info, latency,
1989 &sandybridge_cursor_wm_info, latency,
1990 &plane_wm, &cursor_wm)) {
1991 val = I915_READ(WM0_PIPEB_ILK);
1992 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1993 I915_WRITE(WM0_PIPEB_ILK, val |
1994 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1995 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1996 " plane %d, cursor: %d\n",
1997 plane_wm, cursor_wm);
51cea1f4 1998 enabled |= 1 << PIPE_B;
c43d0188
CW		 1999 }
2000
51cea1f4 2001 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2002 &sandybridge_display_wm_info, latency,
2003 &sandybridge_cursor_wm_info, latency,
2004 &plane_wm, &cursor_wm)) {
2005 val = I915_READ(WM0_PIPEC_IVB);
2006 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2007 I915_WRITE(WM0_PIPEC_IVB, val |
2008 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2009 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2010 " plane %d, cursor: %d\n",
2011 plane_wm, cursor_wm);
51cea1f4 2012 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2013 }
2014
2015 /*
2016 * Calculate and update the self-refresh watermark only when one
2017 * display plane is used.
2018 *
2019 * SNB support 3 levels of watermark.
2020 *
2021 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2022 * and disabled in the descending order
2023 *
2024 */
2025 I915_WRITE(WM3_LP_ILK, 0);
2026 I915_WRITE(WM2_LP_ILK, 0);
2027 I915_WRITE(WM1_LP_ILK, 0);
2028
2029 if (!single_plane_enabled(enabled) ||
2030 dev_priv->sprite_scaling_enabled)
2031 return;
2032 enabled = ffs(enabled) - 1;
2033
2034 /* WM1 */
2035 if (!ironlake_compute_srwm(dev, 1, enabled,
2036 SNB_READ_WM1_LATENCY() * 500,
2037 &sandybridge_display_srwm_info,
2038 &sandybridge_cursor_srwm_info,
2039 &fbc_wm, &plane_wm, &cursor_wm))
2040 return;
2041
2042 I915_WRITE(WM1_LP_ILK,
2043 WM1_LP_SR_EN |
2044 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2045 (fbc_wm << WM1_LP_FBC_SHIFT) |
2046 (plane_wm << WM1_LP_SR_SHIFT) |
2047 cursor_wm);
2048
2049 /* WM2 */
2050 if (!ironlake_compute_srwm(dev, 2, enabled,
2051 SNB_READ_WM2_LATENCY() * 500,
2052 &sandybridge_display_srwm_info,
2053 &sandybridge_cursor_srwm_info,
2054 &fbc_wm, &plane_wm, &cursor_wm))
2055 return;
2056
2057 I915_WRITE(WM2_LP_ILK,
2058 WM2_LP_EN |
2059 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2060 (fbc_wm << WM1_LP_FBC_SHIFT) |
2061 (plane_wm << WM1_LP_SR_SHIFT) |
2062 cursor_wm);
2063
c43d0188 2064 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2065 if (!ironlake_compute_srwm(dev, 3, enabled,
2066 SNB_READ_WM3_LATENCY() * 500,
2067 &sandybridge_display_srwm_info,
2068 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2069 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2070 !ironlake_compute_srwm(dev, 3, enabled,
2071 2 * SNB_READ_WM3_LATENCY() * 500,
2072 &sandybridge_display_srwm_info,
2073 &sandybridge_cursor_srwm_info,
2074 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2075 return;
2076
2077 I915_WRITE(WM3_LP_ILK,
2078 WM3_LP_EN |
2079 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2080 (fbc_wm << WM1_LP_FBC_SHIFT) |
2081 (plane_wm << WM1_LP_SR_SHIFT) |
2082 cursor_wm);
2083}
2084
801bcfff
PZ		 2085static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2086 struct drm_crtc *crtc)
2087{
2088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2089 uint32_t pixel_rate, pfit_size;
2090
ff9a6750 2091 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2092
2093 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2094 * adjust the pixel_rate here. */
2095
2096 pfit_size = intel_crtc->config.pch_pfit.size;
2097 if (pfit_size) {
2098 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2099
2100 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2101 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2102 pfit_w = (pfit_size >> 16) & 0xFFFF;
2103 pfit_h = pfit_size & 0xFFFF;
2104 if (pipe_w < pfit_w)
2105 pipe_w = pfit_w;
2106 if (pipe_h < pfit_h)
2107 pipe_h = pfit_h;
2108
2109 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2110 pfit_w * pfit_h);
2111 }
2112
2113 return pixel_rate;
2114}
2115
2116static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2117 uint32_t latency)
2118{
2119 uint64_t ret;
2120
2121 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2122 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2123
2124 return ret;
2125}
2126
2127static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2128 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2129 uint32_t latency)
2130{
2131 uint32_t ret;
2132
2133 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2134 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2135 ret = DIV_ROUND_UP(ret, 64) + 2;
2136 return ret;
2137}
2138
cca32e9a
PZ		 2139static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2140 uint8_t bytes_per_pixel)
2141{
2142 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2143}
2144
801bcfff
PZ		 2145struct hsw_pipe_wm_parameters {
2146 bool active;
2147 bool sprite_enabled;
2148 uint8_t pri_bytes_per_pixel;
2149 uint8_t spr_bytes_per_pixel;
2150 uint8_t cur_bytes_per_pixel;
2151 uint32_t pri_horiz_pixels;
2152 uint32_t spr_horiz_pixels;
2153 uint32_t cur_horiz_pixels;
2154 uint32_t pipe_htotal;
2155 uint32_t pixel_rate;
2156};
2157
cca32e9a
PZ		 2158struct hsw_wm_maximums {
2159 uint16_t pri;
2160 uint16_t spr;
2161 uint16_t cur;
2162 uint16_t fbc;
2163};
2164
2165struct hsw_lp_wm_result {
2166 bool enable;
2167 bool fbc_enable;
2168 uint32_t pri_val;
2169 uint32_t spr_val;
2170 uint32_t cur_val;
2171 uint32_t fbc_val;
2172};
2173
801bcfff
PZ		 2174struct hsw_wm_values {
2175 uint32_t wm_pipe[3];
2176 uint32_t wm_lp[3];
2177 uint32_t wm_lp_spr[3];
2178 uint32_t wm_linetime[3];
cca32e9a 2179 bool enable_fbc_wm;
801bcfff
PZ		 2180};
2181
2182enum hsw_data_buf_partitioning {
2183 HSW_DATA_BUF_PART_1_2,
2184 HSW_DATA_BUF_PART_5_6,
2185};
2186
cca32e9a
PZ		 2187/* For both WM_PIPE and WM_LP. */
2188static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2189 uint32_t mem_value,
2190 bool is_lp)
801bcfff 2191{
cca32e9a
PZ		 2192 uint32_t method1, method2;
2193
801bcfff
PZ		 2194 /* TODO: for now, assume the primary plane is always enabled. */
2195 if (!params->active)
2196 return 0;
2197
cca32e9a
PZ		 2198 method1 = hsw_wm_method1(params->pixel_rate,
2199 params->pri_bytes_per_pixel,
2200 mem_value);
2201
2202 if (!is_lp)
2203 return method1;
2204
2205 method2 = hsw_wm_method2(params->pixel_rate,
2206 params->pipe_htotal,
2207 params->pri_horiz_pixels,
2208 params->pri_bytes_per_pixel,
2209 mem_value);
2210
2211 return min(method1, method2);
801bcfff
PZ		 2212}
2213
2214/* For both WM_PIPE and WM_LP. */
2215static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2216 uint32_t mem_value)
2217{
2218 uint32_t method1, method2;
2219
2220 if (!params->active || !params->sprite_enabled)
2221 return 0;
2222
2223 method1 = hsw_wm_method1(params->pixel_rate,
2224 params->spr_bytes_per_pixel,
2225 mem_value);
2226 method2 = hsw_wm_method2(params->pixel_rate,
2227 params->pipe_htotal,
2228 params->spr_horiz_pixels,
2229 params->spr_bytes_per_pixel,
2230 mem_value);
2231 return min(method1, method2);
2232}
2233
2234/* For both WM_PIPE and WM_LP. */
2235static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2236 uint32_t mem_value)
2237{
2238 if (!params->active)
2239 return 0;
2240
2241 return hsw_wm_method2(params->pixel_rate,
2242 params->pipe_htotal,
2243 params->cur_horiz_pixels,
2244 params->cur_bytes_per_pixel,
2245 mem_value);
2246}
2247
cca32e9a
PZ		 2248/* Only for WM_LP. */
2249static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2250 uint32_t pri_val,
2251 uint32_t mem_value)
2252{
2253 if (!params->active)
2254 return 0;
2255
2256 return hsw_wm_fbc(pri_val,
2257 params->pri_horiz_pixels,
2258 params->pri_bytes_per_pixel);
2259}
2260
2261static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
2262 struct hsw_pipe_wm_parameters *params,
2263 struct hsw_lp_wm_result *result)
2264{
2265 enum pipe pipe;
2266 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2267
2268 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2269 struct hsw_pipe_wm_parameters *p = &params[pipe];
2270
2271 pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
2272 spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
2273 cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
2274 fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
2275 }
2276
2277 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2278 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2279 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2280 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2281
2282 if (result->fbc_val > max->fbc) {
2283 result->fbc_enable = false;
2284 result->fbc_val = 0;
2285 } else {
2286 result->fbc_enable = true;
2287 }
2288
2289 result->enable = result->pri_val <= max->pri &&
2290 result->spr_val <= max->spr &&
2291 result->cur_val <= max->cur;
2292 return result->enable;
2293}
2294
801bcfff
PZ		 2295static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2296 uint32_t mem_value, enum pipe pipe,
2297 struct hsw_pipe_wm_parameters *params)
2298{
2299 uint32_t pri_val, cur_val, spr_val;
2300
cca32e9a 2301 pri_val = hsw_compute_pri_wm(params, mem_value, false);
801bcfff
PZ		 2302 spr_val = hsw_compute_spr_wm(params, mem_value);
2303 cur_val = hsw_compute_cur_wm(params, mem_value);
2304
2305 WARN(pri_val > 127,
2306 "Primary WM error, mode not supported for pipe %c\n",
2307 pipe_name(pipe));
2308 WARN(spr_val > 127,
2309 "Sprite WM error, mode not supported for pipe %c\n",
2310 pipe_name(pipe));
2311 WARN(cur_val > 63,
2312 "Cursor WM error, mode not supported for pipe %c\n",
2313 pipe_name(pipe));
2314
2315 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2316 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2317 cur_val;
2318}
2319
2320static uint32_t
2321hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2322{
2323 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2325 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2326 u32 linetime, ips_linetime;
1f8eeabf 2327
801bcfff
PZ		 2328 if (!intel_crtc_active(crtc))
2329 return 0;
1011d8c4 2330
1f8eeabf
ED		 2331 /* The WM are computed with base on how long it takes to fill a single
2332 * row at the given clock rate, multiplied by 8.
2333 * */
85a02deb
PZ		 2334 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2335 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2336 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2337
801bcfff
PZ		 2338 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2339 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2340}
2341
801bcfff
PZ		 2342static void hsw_compute_wm_parameters(struct drm_device *dev,
2343 struct hsw_pipe_wm_parameters *params,
cca32e9a 2344 uint32_t *wm,
861f3389
PZ		 2345 struct hsw_wm_maximums *lp_max_1_2,
2346 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4
PZ		 2347{
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct drm_crtc *crtc;
801bcfff
PZ		 2350 struct drm_plane *plane;
2351 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1011d8c4 2352 enum pipe pipe;
cca32e9a 2353 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2354
801bcfff
PZ		 2355 if ((sskpd >> 56) & 0xFF)
2356 wm[0] = (sskpd >> 56) & 0xFF;
2357 else
2358 wm[0] = sskpd & 0xF;
2359 wm[1] = ((sskpd >> 4) & 0xFF) * 5;
2360 wm[2] = ((sskpd >> 12) & 0xFF) * 5;
2361 wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
2362 wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
2363
2364 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366 struct hsw_pipe_wm_parameters *p;
2367
2368 pipe = intel_crtc->pipe;
2369 p = &params[pipe];
2370
2371 p->active = intel_crtc_active(crtc);
2372 if (!p->active)
2373 continue;
2374
cca32e9a
PZ		 2375 pipes_active++;
2376
801bcfff
PZ		 2377 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2378 p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2379 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2380 p->cur_bytes_per_pixel = 4;
2381 p->pri_horiz_pixels =
2382 intel_crtc->config.requested_mode.hdisplay;
2383 p->cur_horiz_pixels = 64;
2384 }
2385
2386 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2387 struct intel_plane *intel_plane = to_intel_plane(plane);
2388 struct hsw_pipe_wm_parameters *p;
2389
2390 pipe = intel_plane->pipe;
2391 p = &params[pipe];
2392
2393 p->sprite_enabled = intel_plane->wm.enable;
2394 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2395 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2396
2397 if (p->sprite_enabled)
2398 sprites_enabled++;
2399 }
2400
2401 if (pipes_active > 1) {
861f3389
PZ		 2402 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2403 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2404 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2405 } else {
2406 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2407 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2408 lp_max_1_2->spr = 384;
861f3389
PZ		 2409 lp_max_5_6->spr = 640;
2410 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2411 }
861f3389 2412 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2413}
2414
2415static void hsw_compute_wm_results(struct drm_device *dev,
2416 struct hsw_pipe_wm_parameters *params,
2417 uint32_t *wm,
cca32e9a 2418 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2419 struct hsw_wm_values *results)
2420{
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct drm_crtc *crtc;
cca32e9a 2423 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2424 enum pipe pipe;
cca32e9a
PZ		 2425 int level, max_level, wm_lp;
2426
2427 for (level = 1; level <= 4; level++)
2428 if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
2429 &lp_results[level - 1]))
2430 break;
2431 max_level = level - 1;
2432
2433 /* The spec says it is preferred to disable FBC WMs instead of disabling
2434 * a WM level. */
2435 results->enable_fbc_wm = true;
2436 for (level = 1; level <= max_level; level++) {
2437 if (!lp_results[level - 1].fbc_enable) {
2438 results->enable_fbc_wm = false;
2439 break;
2440 }
2441 }
2442
2443 memset(results, 0, sizeof(*results));
2444 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2445 const struct hsw_lp_wm_result *r;
801bcfff 2446
cca32e9a
PZ		 2447 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2448 if (level > max_level)
2449 break;
2450
2451 r = &lp_results[level - 1];
2452 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2453 r->fbc_val,
2454 r->pri_val,
2455 r->cur_val);
2456 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2457 }
801bcfff
PZ		 2458
2459 for_each_pipe(pipe)
2460 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2461 pipe,
2462 &params[pipe]);
1011d8c4
PZ		 2463
2464 for_each_pipe(pipe) {
2465 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2466 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2467 }
2468}
2469
861f3389
PZ		 2470/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2471 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2472static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2473 struct hsw_wm_values *r2)
861f3389
PZ		 2474{
2475 int i, val_r1 = 0, val_r2 = 0;
2476
2477 for (i = 0; i < 3; i++) {
2478 if (r1->wm_lp[i] & WM3_LP_EN)
2479 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2480 if (r2->wm_lp[i] & WM3_LP_EN)
2481 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2482 }
2483
2484 if (val_r1 == val_r2) {
2485 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2486 return r2;
2487 else
2488 return r1;
2489 } else if (val_r1 > val_r2) {
2490 return r1;
2491 } else {
2492 return r2;
2493 }
2494}
2495
801bcfff
PZ		 2496/*
2497 * The spec says we shouldn't write when we don't need, because every write
2498 * causes WMs to be re-evaluated, expending some power.
2499 */
2500static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2501 struct hsw_wm_values *results,
2502 enum hsw_data_buf_partitioning partitioning)
2503{
2504 struct hsw_wm_values previous;
2505 uint32_t val;
2506 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2507 bool prev_enable_fbc_wm;
801bcfff
PZ		 2508
2509 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2510 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2511 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2512 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2513 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2514 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2515 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2516 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2517 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2518 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2519 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2520 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2521
2522 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2523 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2524
cca32e9a
PZ		 2525 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2526
801bcfff
PZ		 2527 if (memcmp(results->wm_pipe, previous.wm_pipe,
2528 sizeof(results->wm_pipe)) == 0 &&
2529 memcmp(results->wm_lp, previous.wm_lp,
2530 sizeof(results->wm_lp)) == 0 &&
2531 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2532 sizeof(results->wm_lp_spr)) == 0 &&
2533 memcmp(results->wm_linetime, previous.wm_linetime,
2534 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2535 partitioning == prev_partitioning &&
2536 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2537 return;
2538
2539 if (previous.wm_lp[2] != 0)
2540 I915_WRITE(WM3_LP_ILK, 0);
2541 if (previous.wm_lp[1] != 0)
2542 I915_WRITE(WM2_LP_ILK, 0);
2543 if (previous.wm_lp[0] != 0)
2544 I915_WRITE(WM1_LP_ILK, 0);
2545
2546 if (previous.wm_pipe[0] != results->wm_pipe[0])
2547 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2548 if (previous.wm_pipe[1] != results->wm_pipe[1])
2549 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2550 if (previous.wm_pipe[2] != results->wm_pipe[2])
2551 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2552
2553 if (previous.wm_linetime[0] != results->wm_linetime[0])
2554 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2555 if (previous.wm_linetime[1] != results->wm_linetime[1])
2556 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2557 if (previous.wm_linetime[2] != results->wm_linetime[2])
2558 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2559
2560 if (prev_partitioning != partitioning) {
2561 val = I915_READ(WM_MISC);
2562 if (partitioning == HSW_DATA_BUF_PART_1_2)
2563 val &= ~WM_MISC_DATA_PARTITION_5_6;
2564 else
2565 val |= WM_MISC_DATA_PARTITION_5_6;
2566 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2567 }
2568
cca32e9a
PZ		 2569 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2570 val = I915_READ(DISP_ARB_CTL);
2571 if (results->enable_fbc_wm)
2572 val &= ~DISP_FBC_WM_DIS;
2573 else
2574 val |= DISP_FBC_WM_DIS;
2575 I915_WRITE(DISP_ARB_CTL, val);
2576 }
2577
801bcfff
PZ		 2578 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2579 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2580 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2581 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2582 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2583 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2584
2585 if (results->wm_lp[0] != 0)
2586 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2587 if (results->wm_lp[1] != 0)
2588 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2589 if (results->wm_lp[2] != 0)
2590 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2591}
2592
2593static void haswell_update_wm(struct drm_device *dev)
2594{
2595 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2596 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2597 struct hsw_pipe_wm_parameters params[3];
861f3389 2598 struct hsw_wm_values results_1_2, results_5_6, *best_results;
801bcfff 2599 uint32_t wm[5];
861f3389
PZ		 2600 enum hsw_data_buf_partitioning partitioning;
2601
2602 hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6);
2603
2604 hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
2605 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2606 hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
2607 &results_5_6);
2608 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2609 } else {
2610 best_results = &results_1_2;
2611 }
2612
2613 partitioning = (best_results == &results_1_2) ?
2614 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2615
861f3389 2616 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2617}
2618
526682e9
PZ		 2619static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2620 uint32_t sprite_width, int pixel_size,
2621 bool enable)
2622{
2623 struct drm_plane *plane;
2624
2625 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2626 struct intel_plane *intel_plane = to_intel_plane(plane);
2627
2628 if (intel_plane->pipe == pipe) {
2629 intel_plane->wm.enable = enable;
2630 intel_plane->wm.horiz_pixels = sprite_width + 1;
2631 intel_plane->wm.bytes_per_pixel = pixel_size;
2632 break;
2633 }
2634 }
2635
2636 haswell_update_wm(dev);
2637}
2638
b445e3b0
ED		 2639static bool
2640sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2641 uint32_t sprite_width, int pixel_size,
2642 const struct intel_watermark_params *display,
2643 int display_latency_ns, int *sprite_wm)
2644{
2645 struct drm_crtc *crtc;
2646 int clock;
2647 int entries, tlb_miss;
2648
2649 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2650 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2651 *sprite_wm = display->guard_size;
2652 return false;
2653 }
2654
2655 clock = crtc->mode.clock;
2656
2657 /* Use the small buffer method to calculate the sprite watermark */
2658 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2659 tlb_miss = display->fifo_size*display->cacheline_size -
2660 sprite_width * 8;
2661 if (tlb_miss > 0)
2662 entries += tlb_miss;
2663 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2664 *sprite_wm = entries + display->guard_size;
2665 if (*sprite_wm > (int)display->max_wm)
2666 *sprite_wm = display->max_wm;
2667
2668 return true;
2669}
2670
2671static bool
2672sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2673 uint32_t sprite_width, int pixel_size,
2674 const struct intel_watermark_params *display,
2675 int latency_ns, int *sprite_wm)
2676{
2677 struct drm_crtc *crtc;
2678 unsigned long line_time_us;
2679 int clock;
2680 int line_count, line_size;
2681 int small, large;
2682 int entries;
2683
2684 if (!latency_ns) {
2685 *sprite_wm = 0;
2686 return false;
2687 }
2688
2689 crtc = intel_get_crtc_for_plane(dev, plane);
2690 clock = crtc->mode.clock;
2691 if (!clock) {
2692 *sprite_wm = 0;
2693 return false;
2694 }
2695
2696 line_time_us = (sprite_width * 1000) / clock;
2697 if (!line_time_us) {
2698 *sprite_wm = 0;
2699 return false;
2700 }
2701
2702 line_count = (latency_ns / line_time_us + 1000) / 1000;
2703 line_size = sprite_width * pixel_size;
2704
2705 /* Use the minimum of the small and large buffer method for primary */
2706 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2707 large = line_count * line_size;
2708
2709 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2710 *sprite_wm = entries + display->guard_size;
2711
2712 return *sprite_wm > 0x3ff ? false : true;
2713}
2714
1fa61106 2715static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2716 uint32_t sprite_width, int pixel_size,
2717 bool enable)
b445e3b0
ED		 2718{
2719 struct drm_i915_private *dev_priv = dev->dev_private;
2720 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2721 u32 val;
2722 int sprite_wm, reg;
2723 int ret;
2724
4c4ff43a
PZ		 2725 if (!enable)
2726 return;
2727
b445e3b0
ED		 2728 switch (pipe) {
2729 case 0:
2730 reg = WM0_PIPEA_ILK;
2731 break;
2732 case 1:
2733 reg = WM0_PIPEB_ILK;
2734 break;
2735 case 2:
2736 reg = WM0_PIPEC_IVB;
2737 break;
2738 default:
2739 return; /* bad pipe */
2740 }
2741
2742 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2743 &sandybridge_display_wm_info,
2744 latency, &sprite_wm);
2745 if (!ret) {
84f44ce7
VS		 2746 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2747 pipe_name(pipe));
b445e3b0
ED		 2748 return;
2749 }
2750
2751 val = I915_READ(reg);
2752 val &= ~WM0_PIPE_SPRITE_MASK;
2753 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2754 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2755
2756
2757 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2758 pixel_size,
2759 &sandybridge_display_srwm_info,
2760 SNB_READ_WM1_LATENCY() * 500,
2761 &sprite_wm);
2762 if (!ret) {
84f44ce7
VS		 2763 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2764 pipe_name(pipe));
b445e3b0
ED		 2765 return;
2766 }
2767 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2768
2769 /* Only IVB has two more LP watermarks for sprite */
2770 if (!IS_IVYBRIDGE(dev))
2771 return;
2772
2773 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2774 pixel_size,
2775 &sandybridge_display_srwm_info,
2776 SNB_READ_WM2_LATENCY() * 500,
2777 &sprite_wm);
2778 if (!ret) {
84f44ce7
VS		 2779 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2780 pipe_name(pipe));
b445e3b0
ED		 2781 return;
2782 }
2783 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2784
2785 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2786 pixel_size,
2787 &sandybridge_display_srwm_info,
2788 SNB_READ_WM3_LATENCY() * 500,
2789 &sprite_wm);
2790 if (!ret) {
84f44ce7
VS		 2791 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2792 pipe_name(pipe));
b445e3b0
ED		 2793 return;
2794 }
2795 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2796}
2797
2798/**
2799 * intel_update_watermarks - update FIFO watermark values based on current modes
2800 *
2801 * Calculate watermark values for the various WM regs based on current mode
2802 * and plane configuration.
2803 *
2804 * There are several cases to deal with here:
2805 * - normal (i.e. non-self-refresh)
2806 * - self-refresh (SR) mode
2807 * - lines are large relative to FIFO size (buffer can hold up to 2)
2808 * - lines are small relative to FIFO size (buffer can hold more than 2
2809 * lines), so need to account for TLB latency
2810 *
2811 * The normal calculation is:
2812 * watermark = dotclock * bytes per pixel * latency
2813 * where latency is platform & configuration dependent (we assume pessimal
2814 * values here).
2815 *
2816 * The SR calculation is:
2817 * watermark = (trunc(latency/line time)+1) * surface width *
2818 * bytes per pixel
2819 * where
2820 * line time = htotal / dotclock
2821 * surface width = hdisplay for normal plane and 64 for cursor
2822 * and latency is assumed to be high, as above.
2823 *
2824 * The final value programmed to the register should always be rounded up,
2825 * and include an extra 2 entries to account for clock crossings.
2826 *
2827 * We don't use the sprite, so we can ignore that. And on Crestline we have
2828 * to set the non-SR watermarks to 8.
2829 */
2830void intel_update_watermarks(struct drm_device *dev)
2831{
2832 struct drm_i915_private *dev_priv = dev->dev_private;
2833
2834 if (dev_priv->display.update_wm)
2835 dev_priv->display.update_wm(dev);
2836}
2837
2838void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2839 uint32_t sprite_width, int pixel_size,
2840 bool enable)
b445e3b0
ED		 2841{
2842 struct drm_i915_private *dev_priv = dev->dev_private;
2843
2844 if (dev_priv->display.update_sprite_wm)
2845 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4c4ff43a 2846 pixel_size, enable);
b445e3b0
ED		 2847}
2848
2b4e57bd
ED		 2849static struct drm_i915_gem_object *
2850intel_alloc_context_page(struct drm_device *dev)
2851{
2852 struct drm_i915_gem_object *ctx;
2853 int ret;
2854
2855 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2856
2857 ctx = i915_gem_alloc_object(dev, 4096);
2858 if (!ctx) {
2859 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2860 return NULL;
2861 }
2862
86a1ee26 2863 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2864 if (ret) {
2865 DRM_ERROR("failed to pin power context: %d\n", ret);
2866 goto err_unref;
2867 }
2868
2869 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2870 if (ret) {
2871 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2872 goto err_unpin;
2873 }
2874
2875 return ctx;
2876
2877err_unpin:
2878 i915_gem_object_unpin(ctx);
2879err_unref:
2880 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2881 return NULL;
2882}
2883
9270388e
DV		 2884/**
2885 * Lock protecting IPS related data structures
9270388e
DV		 2886 */
2887DEFINE_SPINLOCK(mchdev_lock);
2888
2889/* Global for IPS driver to get at the current i915 device. Protected by
2890 * mchdev_lock. */
2891static struct drm_i915_private *i915_mch_dev;
2892
2b4e57bd
ED		 2893bool ironlake_set_drps(struct drm_device *dev, u8 val)
2894{
2895 struct drm_i915_private *dev_priv = dev->dev_private;
2896 u16 rgvswctl;
2897
9270388e
DV		 2898 assert_spin_locked(&mchdev_lock);
2899
2b4e57bd
ED		 2900 rgvswctl = I915_READ16(MEMSWCTL);
2901 if (rgvswctl & MEMCTL_CMD_STS) {
2902 DRM_DEBUG("gpu busy, RCS change rejected\n");
2903 return false; /* still busy with another command */
2904 }
2905
2906 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2907 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2908 I915_WRITE16(MEMSWCTL, rgvswctl);
2909 POSTING_READ16(MEMSWCTL);
2910
2911 rgvswctl |= MEMCTL_CMD_STS;
2912 I915_WRITE16(MEMSWCTL, rgvswctl);
2913
2914 return true;
2915}
2916
8090c6b9 2917static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2918{
2919 struct drm_i915_private *dev_priv = dev->dev_private;
2920 u32 rgvmodectl = I915_READ(MEMMODECTL);
2921 u8 fmax, fmin, fstart, vstart;
2922
9270388e
DV		 2923 spin_lock_irq(&mchdev_lock);
2924
2b4e57bd
ED		 2925 /* Enable temp reporting */
2926 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2927 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2928
2929 /* 100ms RC evaluation intervals */
2930 I915_WRITE(RCUPEI, 100000);
2931 I915_WRITE(RCDNEI, 100000);
2932
2933 /* Set max/min thresholds to 90ms and 80ms respectively */
2934 I915_WRITE(RCBMAXAVG, 90000);
2935 I915_WRITE(RCBMINAVG, 80000);
2936
2937 I915_WRITE(MEMIHYST, 1);
2938
2939 /* Set up min, max, and cur for interrupt handling */
2940 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2941 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2942 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2943 MEMMODE_FSTART_SHIFT;
2944
2945 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2946 PXVFREQ_PX_SHIFT;
2947
20e4d407
DV		 2948 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2949 dev_priv->ips.fstart = fstart;
2b4e57bd 2950
20e4d407
DV		 2951 dev_priv->ips.max_delay = fstart;
2952 dev_priv->ips.min_delay = fmin;
2953 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2954
2955 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2956 fmax, fmin, fstart);
2957
2958 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2959
2960 /*
2961 * Interrupts will be enabled in ironlake_irq_postinstall
2962 */
2963
2964 I915_WRITE(VIDSTART, vstart);
2965 POSTING_READ(VIDSTART);
2966
2967 rgvmodectl |= MEMMODE_SWMODE_EN;
2968 I915_WRITE(MEMMODECTL, rgvmodectl);
2969
9270388e 2970 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2971 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2972 mdelay(1);
2b4e57bd
ED		 2973
2974 ironlake_set_drps(dev, fstart);
2975
20e4d407 2976 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2977 I915_READ(0x112e0);
20e4d407
DV		 2978 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2979 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2980 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2981
2982 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2983}
2984
8090c6b9 2985static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2986{
2987 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2988 u16 rgvswctl;
2989
2990 spin_lock_irq(&mchdev_lock);
2991
2992 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2993
2994 /* Ack interrupts, disable EFC interrupt */
2995 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2996 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2997 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2998 I915_WRITE(DEIIR, DE_PCU_EVENT);
2999 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3000
3001 /* Go back to the starting frequency */
20e4d407 3002 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3003 mdelay(1);
2b4e57bd
ED		 3004 rgvswctl |= MEMCTL_CMD_STS;
3005 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3006 mdelay(1);
2b4e57bd 3007
9270388e 3008 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3009}
3010
acbe9475
DV		 3011/* There's a funny hw issue where the hw returns all 0 when reading from
3012 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3013 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3014 * all limits and the gpu stuck at whatever frequency it is at atm).
3015 */
65bccb5c 3016static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3017{
7b9e0ae6 3018 u32 limits;
2b4e57bd 3019
7b9e0ae6 3020 limits = 0;
c6a828d3
DV		 3021
3022 if (*val >= dev_priv->rps.max_delay)
3023 *val = dev_priv->rps.max_delay;
3024 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3025
3026 /* Only set the down limit when we've reached the lowest level to avoid
3027 * getting more interrupts, otherwise leave this clear. This prevents a
3028 * race in the hw when coming out of rc6: There's a tiny window where
3029 * the hw runs at the minimal clock before selecting the desired
3030 * frequency, if the down threshold expires in that window we will not
3031 * receive a down interrupt. */
c6a828d3
DV		 3032 if (*val <= dev_priv->rps.min_delay) {
3033 *val = dev_priv->rps.min_delay;
3034 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3035 }
3036
3037 return limits;
3038}
3039
3040void gen6_set_rps(struct drm_device *dev, u8 val)
3041{
3042 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3043 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3044
4fc688ce 3045 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3046 WARN_ON(val > dev_priv->rps.max_delay);
3047 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3048
c6a828d3 3049 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3050 return;
3051
92bd1bf0
RV		 3052 if (IS_HASWELL(dev))
3053 I915_WRITE(GEN6_RPNSWREQ,
3054 HSW_FREQUENCY(val));
3055 else
3056 I915_WRITE(GEN6_RPNSWREQ,
3057 GEN6_FREQUENCY(val) |
3058 GEN6_OFFSET(0) |
3059 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3060
3061 /* Make sure we continue to get interrupts
3062 * until we hit the minimum or maximum frequencies.
3063 */
3064 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3065
d5570a72
BW		 3066 POSTING_READ(GEN6_RPNSWREQ);
3067
c6a828d3 3068 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3069
3070 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3071}
3072
80814ae4
VS		 3073/*
3074 * Wait until the previous freq change has completed,
3075 * or the timeout elapsed, and then update our notion
3076 * of the current GPU frequency.
3077 */
3078static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3079{
80814ae4
VS		 3080 u32 pval;
3081
3082 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3083
e8474409
VS		 3084 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3085 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3086
3087 pval >>= 8;
3088
3089 if (pval != dev_priv->rps.cur_delay)
3090 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3091 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3092 dev_priv->rps.cur_delay,
3093 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3094
3095 dev_priv->rps.cur_delay = pval;
3096}
3097
0a073b84
JB		 3098void valleyview_set_rps(struct drm_device *dev, u8 val)
3099{
3100 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3101
3102 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3103
3104 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3105 WARN_ON(val > dev_priv->rps.max_delay);
3106 WARN_ON(val < dev_priv->rps.min_delay);
3107
80814ae4
VS		 3108 vlv_update_rps_cur_delay(dev_priv);
3109
73008b98 3110 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3111 vlv_gpu_freq(dev_priv->mem_freq,
3112 dev_priv->rps.cur_delay),
73008b98
VS		 3113 dev_priv->rps.cur_delay,
3114 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3115
3116 if (val == dev_priv->rps.cur_delay)
3117 return;
3118
ae99258f 3119 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3120
80814ae4 3121 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3122
3123 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3124}
3125
44fc7d5c 3126static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3127{
3128 struct drm_i915_private *dev_priv = dev->dev_private;
3129
2b4e57bd 3130 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3131 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3132 /* Complete PM interrupt masking here doesn't race with the rps work
3133 * item again unmasking PM interrupts because that is using a different
3134 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3135 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3136
59cdb63d 3137 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3138 dev_priv->rps.pm_iir = 0;
59cdb63d 3139 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3140
4848405c 3141 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3142}
3143
44fc7d5c 3144static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147
3148 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3149 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3150
44fc7d5c
DV		 3151 gen6_disable_rps_interrupts(dev);
3152}
3153
3154static void valleyview_disable_rps(struct drm_device *dev)
3155{
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157
3158 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3159
44fc7d5c 3160 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3161
3162 if (dev_priv->vlv_pctx) {
3163 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3164 dev_priv->vlv_pctx = NULL;
3165 }
d20d4f0c
JB		 3166}
3167
2b4e57bd
ED		 3168int intel_enable_rc6(const struct drm_device *dev)
3169{
456470eb 3170 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3171 if (i915_enable_rc6 >= 0)
3172 return i915_enable_rc6;
3173
6567d748
CW		 3174 /* Disable RC6 on Ironlake */
3175 if (INTEL_INFO(dev)->gen == 5)
3176 return 0;
2b4e57bd 3177
456470eb
DV		 3178 if (IS_HASWELL(dev)) {
3179 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3180 return INTEL_RC6_ENABLE;
456470eb 3181 }
2b4e57bd 3182
456470eb 3183 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3184 if (INTEL_INFO(dev)->gen == 6) {
3185 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3186 return INTEL_RC6_ENABLE;
3187 }
456470eb 3188
2b4e57bd
ED		 3189 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3190 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3191}
3192
44fc7d5c
DV		 3193static void gen6_enable_rps_interrupts(struct drm_device *dev)
3194{
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196
3197 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3198 WARN_ON(dev_priv->rps.pm_iir);
44fc7d5c
DV		 3199 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3200 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3201 spin_unlock_irq(&dev_priv->irq_lock);
3202 /* unmask all PM interrupts */
3203 I915_WRITE(GEN6_PMINTRMSK, 0);
3204}
3205
79f5b2c7 3206static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3207{
79f5b2c7 3208 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3209 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3210 u32 rp_state_cap;
3211 u32 gt_perf_status;
31643d54 3212 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3213 u32 gtfifodbg;
2b4e57bd 3214 int rc6_mode;
42c0526c 3215 int i, ret;
2b4e57bd 3216
4fc688ce 3217 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3218
2b4e57bd
ED		 3219 /* Here begins a magic sequence of register writes to enable
3220 * auto-downclocking.
3221 *
3222 * Perhaps there might be some value in exposing these to
3223 * userspace...
3224 */
3225 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3226
3227 /* Clear the DBG now so we don't confuse earlier errors */
3228 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3229 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3230 I915_WRITE(GTFIFODBG, gtfifodbg);
3231 }
3232
3233 gen6_gt_force_wake_get(dev_priv);
3234
7b9e0ae6
CW		 3235 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3236 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3237
31c77388
BW		 3238 /* In units of 50MHz */
3239 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3240 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3241 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3242
2b4e57bd
ED		 3243 /* disable the counters and set deterministic thresholds */
3244 I915_WRITE(GEN6_RC_CONTROL, 0);
3245
3246 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3247 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3248 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3249 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3250 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3251
b4519513
CW		 3252 for_each_ring(ring, dev_priv, i)
3253 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3254
3255 I915_WRITE(GEN6_RC_SLEEP, 0);
3256 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3257 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3258 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3259 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3260
5a7dc92a 3261 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3262 rc6_mode = intel_enable_rc6(dev_priv->dev);
3263 if (rc6_mode & INTEL_RC6_ENABLE)
3264 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3265
5a7dc92a
ED		 3266 /* We don't use those on Haswell */
3267 if (!IS_HASWELL(dev)) {
3268 if (rc6_mode & INTEL_RC6p_ENABLE)
3269 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3270
5a7dc92a
ED		 3271 if (rc6_mode & INTEL_RC6pp_ENABLE)
3272 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3273 }
2b4e57bd
ED		 3274
3275 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3276 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3277 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3278 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3279
3280 I915_WRITE(GEN6_RC_CONTROL,
3281 rc6_mask |
3282 GEN6_RC_CTL_EI_MODE(1) |
3283 GEN6_RC_CTL_HW_ENABLE);
3284
92bd1bf0
RV		 3285 if (IS_HASWELL(dev)) {
3286 I915_WRITE(GEN6_RPNSWREQ,
3287 HSW_FREQUENCY(10));
3288 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3289 HSW_FREQUENCY(12));
3290 } else {
3291 I915_WRITE(GEN6_RPNSWREQ,
3292 GEN6_FREQUENCY(10) |
3293 GEN6_OFFSET(0) |
3294 GEN6_AGGRESSIVE_TURBO);
3295 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3296 GEN6_FREQUENCY(12));
3297 }
2b4e57bd
ED		 3298
3299 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3300 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3301 dev_priv->rps.max_delay << 24 |
3302 dev_priv->rps.min_delay << 16);
5a7dc92a 3303
1ee9ae32
DV		 3304 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3305 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3306 I915_WRITE(GEN6_RP_UP_EI, 66000);
3307 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3308
2b4e57bd
ED		 3309 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3310 I915_WRITE(GEN6_RP_CONTROL,
3311 GEN6_RP_MEDIA_TURBO |
89ba829e 3312 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3313 GEN6_RP_MEDIA_IS_GFX |
3314 GEN6_RP_ENABLE |
3315 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3316 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3317
42c0526c 3318 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3319 if (!ret) {
42c0526c
BW		 3320 pcu_mbox = 0;
3321 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3322 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3323 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3324 (dev_priv->rps.max_delay & 0xff) * 50,
3325 (pcu_mbox & 0xff) * 50);
31c77388 3326 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3327 }
3328 } else {
3329 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3330 }
3331
7b9e0ae6 3332 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3333
44fc7d5c 3334 gen6_enable_rps_interrupts(dev);
2b4e57bd 3335
31643d54
BW		 3336 rc6vids = 0;
3337 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3338 if (IS_GEN6(dev) && ret) {
3339 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3340 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3341 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3342 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3343 rc6vids &= 0xffff00;
3344 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3345 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3346 if (ret)
3347 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3348 }
3349
2b4e57bd 3350 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3351}
3352
79f5b2c7 3353static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3354{
79f5b2c7 3355 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3356 int min_freq = 15;
3ebecd07
CW		 3357 unsigned int gpu_freq;
3358 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3359 int scaling_factor = 180;
3360
4fc688ce 3361 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3362
2b4e57bd
ED		 3363 max_ia_freq = cpufreq_quick_get_max(0);
3364 /*
3365 * Default to measured freq if none found, PCU will ensure we don't go
3366 * over
3367 */
3368 if (!max_ia_freq)
3369 max_ia_freq = tsc_khz;
3370
3371 /* Convert from kHz to MHz */
3372 max_ia_freq /= 1000;
3373
3ebecd07
CW		 3374 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3375 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3376 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3377
2b4e57bd
ED		 3378 /*
3379 * For each potential GPU frequency, load a ring frequency we'd like
3380 * to use for memory access. We do this by specifying the IA frequency
3381 * the PCU should use as a reference to determine the ring frequency.
3382 */
c6a828d3 3383 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3384 gpu_freq--) {
c6a828d3 3385 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3386 unsigned int ia_freq = 0, ring_freq = 0;
3387
3388 if (IS_HASWELL(dev)) {
3389 ring_freq = (gpu_freq * 5 + 3) / 4;
3390 ring_freq = max(min_ring_freq, ring_freq);
3391 /* leave ia_freq as the default, chosen by cpufreq */
3392 } else {
3393 /* On older processors, there is no separate ring
3394 * clock domain, so in order to boost the bandwidth
3395 * of the ring, we need to upclock the CPU (ia_freq).
3396 *
3397 * For GPU frequencies less than 750MHz,
3398 * just use the lowest ring freq.
3399 */
3400 if (gpu_freq < min_freq)
3401 ia_freq = 800;
3402 else
3403 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3404 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3405 }
2b4e57bd 3406
42c0526c
BW		 3407 sandybridge_pcode_write(dev_priv,
3408 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3409 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3410 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3411 gpu_freq);
2b4e57bd 3412 }
2b4e57bd
ED		 3413}
3414
0a073b84
JB		 3415int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3416{
3417 u32 val, rp0;
3418
64936258 3419 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3420
3421 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3422 /* Clamp to max */
3423 rp0 = min_t(u32, rp0, 0xea);
3424
3425 return rp0;
3426}
3427
3428static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3429{
3430 u32 val, rpe;
3431
64936258 3432 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3433 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3434 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3435 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3436
3437 return rpe;
3438}
3439
3440int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3441{
64936258 3442 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3443}
3444
52ceb908
JB		 3445static void vlv_rps_timer_work(struct work_struct *work)
3446{
3447 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3448 rps.vlv_work.work);
3449
3450 /*
3451 * Timer fired, we must be idle. Drop to min voltage state.
3452 * Note: we use RPe here since it should match the
3453 * Vmin we were shooting for. That should give us better
3454 * perf when we come back out of RC6 than if we used the
3455 * min freq available.
3456 */
3457 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3458 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3459 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3460 mutex_unlock(&dev_priv->rps.hw_lock);
3461}
3462
c9cddffc
JB		 3463static void valleyview_setup_pctx(struct drm_device *dev)
3464{
3465 struct drm_i915_private *dev_priv = dev->dev_private;
3466 struct drm_i915_gem_object *pctx;
3467 unsigned long pctx_paddr;
3468 u32 pcbr;
3469 int pctx_size = 24*1024;
3470
3471 pcbr = I915_READ(VLV_PCBR);
3472 if (pcbr) {
3473 /* BIOS set it up already, grab the pre-alloc'd space */
3474 int pcbr_offset;
3475
3476 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3477 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3478 pcbr_offset,
190d6cd5 3479 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3480 pctx_size);
3481 goto out;
3482 }
3483
3484 /*
3485 * From the Gunit register HAS:
3486 * The Gfx driver is expected to program this register and ensure
3487 * proper allocation within Gfx stolen memory. For example, this
3488 * register should be programmed such than the PCBR range does not
3489 * overlap with other ranges, such as the frame buffer, protected
3490 * memory, or any other relevant ranges.
3491 */
3492 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3493 if (!pctx) {
3494 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3495 return;
3496 }
3497
3498 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3499 I915_WRITE(VLV_PCBR, pctx_paddr);
3500
3501out:
3502 dev_priv->vlv_pctx = pctx;
3503}
3504
0a073b84
JB		 3505static void valleyview_enable_rps(struct drm_device *dev)
3506{
3507 struct drm_i915_private *dev_priv = dev->dev_private;
3508 struct intel_ring_buffer *ring;
73008b98 3509 u32 gtfifodbg, val;
0a073b84
JB		 3510 int i;
3511
3512 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3513
3514 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3515 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3516 I915_WRITE(GTFIFODBG, gtfifodbg);
3517 }
3518
c9cddffc
JB		 3519 valleyview_setup_pctx(dev);
3520
0a073b84
JB		 3521 gen6_gt_force_wake_get(dev_priv);
3522
3523 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3524 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3525 I915_WRITE(GEN6_RP_UP_EI, 66000);
3526 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3527
3528 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3529
3530 I915_WRITE(GEN6_RP_CONTROL,
3531 GEN6_RP_MEDIA_TURBO |
3532 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3533 GEN6_RP_MEDIA_IS_GFX |
3534 GEN6_RP_ENABLE |
3535 GEN6_RP_UP_BUSY_AVG |
3536 GEN6_RP_DOWN_IDLE_CONT);
3537
3538 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3539 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3540 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3541
3542 for_each_ring(ring, dev_priv, i)
3543 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3544
3545 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3546
3547 /* allows RC6 residency counter to work */
3548 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3549 I915_WRITE(GEN6_RC_CONTROL,
3550 GEN7_RC_CTL_TO_MODE);
3551
64936258 3552 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3553 switch ((val >> 6) & 3) {
3554 case 0:
3555 case 1:
3556 dev_priv->mem_freq = 800;
3557 break;
3558 case 2:
3559 dev_priv->mem_freq = 1066;
3560 break;
3561 case 3:
3562 dev_priv->mem_freq = 1333;
3563 break;
3564 }
0a073b84
JB		 3565 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3566
3567 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3568 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3569
0a073b84 3570 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3571 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3572 vlv_gpu_freq(dev_priv->mem_freq,
3573 dev_priv->rps.cur_delay),
3574 dev_priv->rps.cur_delay);
0a073b84
JB		 3575
3576 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3577 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3578 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3579 vlv_gpu_freq(dev_priv->mem_freq,
3580 dev_priv->rps.max_delay),
3581 dev_priv->rps.max_delay);
0a073b84 3582
73008b98
VS		 3583 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3584 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3585 vlv_gpu_freq(dev_priv->mem_freq,
3586 dev_priv->rps.rpe_delay),
3587 dev_priv->rps.rpe_delay);
0a073b84 3588
73008b98
VS		 3589 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3590 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3591 vlv_gpu_freq(dev_priv->mem_freq,
3592 dev_priv->rps.min_delay),
3593 dev_priv->rps.min_delay);
0a073b84 3594
73008b98
VS		 3595 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3596 vlv_gpu_freq(dev_priv->mem_freq,
3597 dev_priv->rps.rpe_delay),
3598 dev_priv->rps.rpe_delay);
0a073b84 3599
52ceb908
JB		 3600 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3601
73008b98 3602 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3603
44fc7d5c 3604 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3605
3606 gen6_gt_force_wake_put(dev_priv);
3607}
3608
930ebb46 3609void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3610{
3611 struct drm_i915_private *dev_priv = dev->dev_private;
3612
3e373948
DV		 3613 if (dev_priv->ips.renderctx) {
3614 i915_gem_object_unpin(dev_priv->ips.renderctx);
3615 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3616 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3617 }
3618
3e373948
DV		 3619 if (dev_priv->ips.pwrctx) {
3620 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3621 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3622 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3623 }
3624}
3625
930ebb46 3626static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3627{
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629
3630 if (I915_READ(PWRCTXA)) {
3631 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3632 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3633 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3634 50);
3635
3636 I915_WRITE(PWRCTXA, 0);
3637 POSTING_READ(PWRCTXA);
3638
3639 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3640 POSTING_READ(RSTDBYCTL);
3641 }
2b4e57bd
ED		 3642}
3643
3644static int ironlake_setup_rc6(struct drm_device *dev)
3645{
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647
3e373948
DV		 3648 if (dev_priv->ips.renderctx == NULL)
3649 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3650 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3651 return -ENOMEM;
3652
3e373948
DV		 3653 if (dev_priv->ips.pwrctx == NULL)
3654 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3655 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3656 ironlake_teardown_rc6(dev);
3657 return -ENOMEM;
3658 }
3659
3660 return 0;
3661}
3662
930ebb46 3663static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3664{
3665 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3666 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3667 bool was_interruptible;
2b4e57bd
ED		 3668 int ret;
3669
3670 /* rc6 disabled by default due to repeated reports of hanging during
3671 * boot and resume.
3672 */
3673 if (!intel_enable_rc6(dev))
3674 return;
3675
79f5b2c7
DV		 3676 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3677
2b4e57bd 3678 ret = ironlake_setup_rc6(dev);
79f5b2c7 3679 if (ret)
2b4e57bd 3680 return;
2b4e57bd 3681
3e960501
CW		 3682 was_interruptible = dev_priv->mm.interruptible;
3683 dev_priv->mm.interruptible = false;
3684
2b4e57bd
ED		 3685 /*
3686 * GPU can automatically power down the render unit if given a page
3687 * to save state.
3688 */
6d90c952 3689 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3690 if (ret) {
3691 ironlake_teardown_rc6(dev);
3e960501 3692 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3693 return;
3694 }
3695
6d90c952
DV		 3696 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3697 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3698 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3699 MI_MM_SPACE_GTT |
3700 MI_SAVE_EXT_STATE_EN |
3701 MI_RESTORE_EXT_STATE_EN |
3702 MI_RESTORE_INHIBIT);
3703 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3704 intel_ring_emit(ring, MI_NOOP);
3705 intel_ring_emit(ring, MI_FLUSH);
3706 intel_ring_advance(ring);
2b4e57bd
ED		 3707
3708 /*
3709 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3710 * does an implicit flush, combined with MI_FLUSH above, it should be
3711 * safe to assume that renderctx is valid
3712 */
3e960501
CW		 3713 ret = intel_ring_idle(ring);
3714 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3715 if (ret) {
def27a58 3716 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3717 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3718 return;
3719 }
3720
f343c5f6 3721 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3722 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3723}
3724
dde18883
ED		 3725static unsigned long intel_pxfreq(u32 vidfreq)
3726{
3727 unsigned long freq;
3728 int div = (vidfreq & 0x3f0000) >> 16;
3729 int post = (vidfreq & 0x3000) >> 12;
3730 int pre = (vidfreq & 0x7);
3731
3732 if (!pre)
3733 return 0;
3734
3735 freq = ((div * 133333) / ((1<<post) * pre));
3736
3737 return freq;
3738}
3739
eb48eb00
DV		 3740static const struct cparams {
3741 u16 i;
3742 u16 t;
3743 u16 m;
3744 u16 c;
3745} cparams[] = {
3746 { 1, 1333, 301, 28664 },
3747 { 1, 1066, 294, 24460 },
3748 { 1, 800, 294, 25192 },
3749 { 0, 1333, 276, 27605 },
3750 { 0, 1066, 276, 27605 },
3751 { 0, 800, 231, 23784 },
3752};
3753
f531dcb2 3754static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3755{
3756 u64 total_count, diff, ret;
3757 u32 count1, count2, count3, m = 0, c = 0;
3758 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3759 int i;
3760
02d71956
DV		 3761 assert_spin_locked(&mchdev_lock);
3762
20e4d407 3763 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3764
3765 /* Prevent division-by-zero if we are asking too fast.
3766 * Also, we don't get interesting results if we are polling
3767 * faster than once in 10ms, so just return the saved value
3768 * in such cases.
3769 */
3770 if (diff1 <= 10)
20e4d407 3771 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3772
3773 count1 = I915_READ(DMIEC);
3774 count2 = I915_READ(DDREC);
3775 count3 = I915_READ(CSIEC);
3776
3777 total_count = count1 + count2 + count3;
3778
3779 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3780 if (total_count < dev_priv->ips.last_count1) {
3781 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3782 diff += total_count;
3783 } else {
20e4d407 3784 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3785 }
3786
3787 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3788 if (cparams[i].i == dev_priv->ips.c_m &&
3789 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3790 m = cparams[i].m;
3791 c = cparams[i].c;
3792 break;
3793 }
3794 }
3795
3796 diff = div_u64(diff, diff1);
3797 ret = ((m * diff) + c);
3798 ret = div_u64(ret, 10);
3799
20e4d407
DV		 3800 dev_priv->ips.last_count1 = total_count;
3801 dev_priv->ips.last_time1 = now;
eb48eb00 3802
20e4d407 3803 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3804
3805 return ret;
3806}
3807
f531dcb2
CW		 3808unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3809{
3810 unsigned long val;
3811
3812 if (dev_priv->info->gen != 5)
3813 return 0;
3814
3815 spin_lock_irq(&mchdev_lock);
3816
3817 val = __i915_chipset_val(dev_priv);
3818
3819 spin_unlock_irq(&mchdev_lock);
3820
3821 return val;
3822}
3823
eb48eb00
DV		 3824unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3825{
3826 unsigned long m, x, b;
3827 u32 tsfs;
3828
3829 tsfs = I915_READ(TSFS);
3830
3831 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3832 x = I915_READ8(TR1);
3833
3834 b = tsfs & TSFS_INTR_MASK;
3835
3836 return ((m * x) / 127) - b;
3837}
3838
3839static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3840{
3841 static const struct v_table {
3842 u16 vd; /* in .1 mil */
3843 u16 vm; /* in .1 mil */
3844 } v_table[] = {
3845 { 0, 0, },
3846 { 375, 0, },
3847 { 500, 0, },
3848 { 625, 0, },
3849 { 750, 0, },
3850 { 875, 0, },
3851 { 1000, 0, },
3852 { 1125, 0, },
3853 { 4125, 3000, },
3854 { 4125, 3000, },
3855 { 4125, 3000, },
3856 { 4125, 3000, },
3857 { 4125, 3000, },
3858 { 4125, 3000, },
3859 { 4125, 3000, },
3860 { 4125, 3000, },
3861 { 4125, 3000, },
3862 { 4125, 3000, },
3863 { 4125, 3000, },
3864 { 4125, 3000, },
3865 { 4125, 3000, },
3866 { 4125, 3000, },
3867 { 4125, 3000, },
3868 { 4125, 3000, },
3869 { 4125, 3000, },
3870 { 4125, 3000, },
3871 { 4125, 3000, },
3872 { 4125, 3000, },
3873 { 4125, 3000, },
3874 { 4125, 3000, },
3875 { 4125, 3000, },
3876 { 4125, 3000, },
3877 { 4250, 3125, },
3878 { 4375, 3250, },
3879 { 4500, 3375, },
3880 { 4625, 3500, },
3881 { 4750, 3625, },
3882 { 4875, 3750, },
3883 { 5000, 3875, },
3884 { 5125, 4000, },
3885 { 5250, 4125, },
3886 { 5375, 4250, },
3887 { 5500, 4375, },
3888 { 5625, 4500, },
3889 { 5750, 4625, },
3890 { 5875, 4750, },
3891 { 6000, 4875, },
3892 { 6125, 5000, },
3893 { 6250, 5125, },
3894 { 6375, 5250, },
3895 { 6500, 5375, },
3896 { 6625, 5500, },
3897 { 6750, 5625, },
3898 { 6875, 5750, },
3899 { 7000, 5875, },
3900 { 7125, 6000, },
3901 { 7250, 6125, },
3902 { 7375, 6250, },
3903 { 7500, 6375, },
3904 { 7625, 6500, },
3905 { 7750, 6625, },
3906 { 7875, 6750, },
3907 { 8000, 6875, },
3908 { 8125, 7000, },
3909 { 8250, 7125, },
3910 { 8375, 7250, },
3911 { 8500, 7375, },
3912 { 8625, 7500, },
3913 { 8750, 7625, },
3914 { 8875, 7750, },
3915 { 9000, 7875, },
3916 { 9125, 8000, },
3917 { 9250, 8125, },
3918 { 9375, 8250, },
3919 { 9500, 8375, },
3920 { 9625, 8500, },
3921 { 9750, 8625, },
3922 { 9875, 8750, },
3923 { 10000, 8875, },
3924 { 10125, 9000, },
3925 { 10250, 9125, },
3926 { 10375, 9250, },
3927 { 10500, 9375, },
3928 { 10625, 9500, },
3929 { 10750, 9625, },
3930 { 10875, 9750, },
3931 { 11000, 9875, },
3932 { 11125, 10000, },
3933 { 11250, 10125, },
3934 { 11375, 10250, },
3935 { 11500, 10375, },
3936 { 11625, 10500, },
3937 { 11750, 10625, },
3938 { 11875, 10750, },
3939 { 12000, 10875, },
3940 { 12125, 11000, },
3941 { 12250, 11125, },
3942 { 12375, 11250, },
3943 { 12500, 11375, },
3944 { 12625, 11500, },
3945 { 12750, 11625, },
3946 { 12875, 11750, },
3947 { 13000, 11875, },
3948 { 13125, 12000, },
3949 { 13250, 12125, },
3950 { 13375, 12250, },
3951 { 13500, 12375, },
3952 { 13625, 12500, },
3953 { 13750, 12625, },
3954 { 13875, 12750, },
3955 { 14000, 12875, },
3956 { 14125, 13000, },
3957 { 14250, 13125, },
3958 { 14375, 13250, },
3959 { 14500, 13375, },
3960 { 14625, 13500, },
3961 { 14750, 13625, },
3962 { 14875, 13750, },
3963 { 15000, 13875, },
3964 { 15125, 14000, },
3965 { 15250, 14125, },
3966 { 15375, 14250, },
3967 { 15500, 14375, },
3968 { 15625, 14500, },
3969 { 15750, 14625, },
3970 { 15875, 14750, },
3971 { 16000, 14875, },
3972 { 16125, 15000, },
3973 };
3974 if (dev_priv->info->is_mobile)
3975 return v_table[pxvid].vm;
3976 else
3977 return v_table[pxvid].vd;
3978}
3979
02d71956 3980static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3981{
3982 struct timespec now, diff1;
3983 u64 diff;
3984 unsigned long diffms;
3985 u32 count;
3986
02d71956 3987 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3988
3989 getrawmonotonic(&now);
20e4d407 3990 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3991
3992 /* Don't divide by 0 */
3993 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3994 if (!diffms)
3995 return;
3996
3997 count = I915_READ(GFXEC);
3998
20e4d407
DV		 3999 if (count < dev_priv->ips.last_count2) {
4000 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4001 diff += count;
4002 } else {
20e4d407 4003 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4004 }
4005
20e4d407
DV		 4006 dev_priv->ips.last_count2 = count;
4007 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4008
4009 /* More magic constants... */
4010 diff = diff * 1181;
4011 diff = div_u64(diff, diffms * 10);
20e4d407 4012 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4013}
4014
02d71956
DV		 4015void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4016{
4017 if (dev_priv->info->gen != 5)
4018 return;
4019
9270388e 4020 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4021
4022 __i915_update_gfx_val(dev_priv);
4023
9270388e 4024 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4025}
4026
f531dcb2 4027static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4028{
4029 unsigned long t, corr, state1, corr2, state2;
4030 u32 pxvid, ext_v;
4031
02d71956
DV		 4032 assert_spin_locked(&mchdev_lock);
4033
c6a828d3 4034 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4035 pxvid = (pxvid >> 24) & 0x7f;
4036 ext_v = pvid_to_extvid(dev_priv, pxvid);
4037
4038 state1 = ext_v;
4039
4040 t = i915_mch_val(dev_priv);
4041
4042 /* Revel in the empirically derived constants */
4043
4044 /* Correction factor in 1/100000 units */
4045 if (t > 80)
4046 corr = ((t * 2349) + 135940);
4047 else if (t >= 50)
4048 corr = ((t * 964) + 29317);
4049 else /* < 50 */
4050 corr = ((t * 301) + 1004);
4051
4052 corr = corr * ((150142 * state1) / 10000 - 78642);
4053 corr /= 100000;
20e4d407 4054 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4055
4056 state2 = (corr2 * state1) / 10000;
4057 state2 /= 100; /* convert to mW */
4058
02d71956 4059 __i915_update_gfx_val(dev_priv);
eb48eb00 4060
20e4d407 4061 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4062}
4063
f531dcb2
CW		 4064unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4065{
4066 unsigned long val;
4067
4068 if (dev_priv->info->gen != 5)
4069 return 0;
4070
4071 spin_lock_irq(&mchdev_lock);
4072
4073 val = __i915_gfx_val(dev_priv);
4074
4075 spin_unlock_irq(&mchdev_lock);
4076
4077 return val;
4078}
4079
eb48eb00
DV		 4080/**
4081 * i915_read_mch_val - return value for IPS use
4082 *
4083 * Calculate and return a value for the IPS driver to use when deciding whether
4084 * we have thermal and power headroom to increase CPU or GPU power budget.
4085 */
4086unsigned long i915_read_mch_val(void)
4087{
4088 struct drm_i915_private *dev_priv;
4089 unsigned long chipset_val, graphics_val, ret = 0;
4090
9270388e 4091 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4092 if (!i915_mch_dev)
4093 goto out_unlock;
4094 dev_priv = i915_mch_dev;
4095
f531dcb2
CW		 4096 chipset_val = __i915_chipset_val(dev_priv);
4097 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4098
4099 ret = chipset_val + graphics_val;
4100
4101out_unlock:
9270388e 4102 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4103
4104 return ret;
4105}
4106EXPORT_SYMBOL_GPL(i915_read_mch_val);
4107
4108/**
4109 * i915_gpu_raise - raise GPU frequency limit
4110 *
4111 * Raise the limit; IPS indicates we have thermal headroom.
4112 */
4113bool i915_gpu_raise(void)
4114{
4115 struct drm_i915_private *dev_priv;
4116 bool ret = true;
4117
9270388e 4118 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4119 if (!i915_mch_dev) {
4120 ret = false;
4121 goto out_unlock;
4122 }
4123 dev_priv = i915_mch_dev;
4124
20e4d407
DV		 4125 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4126 dev_priv->ips.max_delay--;
eb48eb00
DV		 4127
4128out_unlock:
9270388e 4129 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4130
4131 return ret;
4132}
4133EXPORT_SYMBOL_GPL(i915_gpu_raise);
4134
4135/**
4136 * i915_gpu_lower - lower GPU frequency limit
4137 *
4138 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4139 * frequency maximum.
4140 */
4141bool i915_gpu_lower(void)
4142{
4143 struct drm_i915_private *dev_priv;
4144 bool ret = true;
4145
9270388e 4146 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4147 if (!i915_mch_dev) {
4148 ret = false;
4149 goto out_unlock;
4150 }
4151 dev_priv = i915_mch_dev;
4152
20e4d407
DV		 4153 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4154 dev_priv->ips.max_delay++;
eb48eb00
DV		 4155
4156out_unlock:
9270388e 4157 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4158
4159 return ret;
4160}
4161EXPORT_SYMBOL_GPL(i915_gpu_lower);
4162
4163/**
4164 * i915_gpu_busy - indicate GPU business to IPS
4165 *
4166 * Tell the IPS driver whether or not the GPU is busy.
4167 */
4168bool i915_gpu_busy(void)
4169{
4170 struct drm_i915_private *dev_priv;
f047e395 4171 struct intel_ring_buffer *ring;
eb48eb00 4172 bool ret = false;
f047e395 4173 int i;
eb48eb00 4174
9270388e 4175 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4176 if (!i915_mch_dev)
4177 goto out_unlock;
4178 dev_priv = i915_mch_dev;
4179
f047e395
CW		 4180 for_each_ring(ring, dev_priv, i)
4181 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4182
4183out_unlock:
9270388e 4184 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4185
4186 return ret;
4187}
4188EXPORT_SYMBOL_GPL(i915_gpu_busy);
4189
4190/**
4191 * i915_gpu_turbo_disable - disable graphics turbo
4192 *
4193 * Disable graphics turbo by resetting the max frequency and setting the
4194 * current frequency to the default.
4195 */
4196bool i915_gpu_turbo_disable(void)
4197{
4198 struct drm_i915_private *dev_priv;
4199 bool ret = true;
4200
9270388e 4201 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4202 if (!i915_mch_dev) {
4203 ret = false;
4204 goto out_unlock;
4205 }
4206 dev_priv = i915_mch_dev;
4207
20e4d407 4208 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4209
20e4d407 4210 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4211 ret = false;
4212
4213out_unlock:
9270388e 4214 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4215
4216 return ret;
4217}
4218EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4219
4220/**
4221 * Tells the intel_ips driver that the i915 driver is now loaded, if
4222 * IPS got loaded first.
4223 *
4224 * This awkward dance is so that neither module has to depend on the
4225 * other in order for IPS to do the appropriate communication of
4226 * GPU turbo limits to i915.
4227 */
4228static void
4229ips_ping_for_i915_load(void)
4230{
4231 void (*link)(void);
4232
4233 link = symbol_get(ips_link_to_i915_driver);
4234 if (link) {
4235 link();
4236 symbol_put(ips_link_to_i915_driver);
4237 }
4238}
4239
4240void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4241{
02d71956
DV		 4242 /* We only register the i915 ips part with intel-ips once everything is
4243 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4244 spin_lock_irq(&mchdev_lock);
eb48eb00 4245 i915_mch_dev = dev_priv;
9270388e 4246 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4247
4248 ips_ping_for_i915_load();
4249}
4250
4251void intel_gpu_ips_teardown(void)
4252{
9270388e 4253 spin_lock_irq(&mchdev_lock);
eb48eb00 4254 i915_mch_dev = NULL;
9270388e 4255 spin_unlock_irq(&mchdev_lock);
eb48eb00 4256}
8090c6b9 4257static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4258{
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 u32 lcfuse;
4261 u8 pxw[16];
4262 int i;
4263
4264 /* Disable to program */
4265 I915_WRITE(ECR, 0);
4266 POSTING_READ(ECR);
4267
4268 /* Program energy weights for various events */
4269 I915_WRITE(SDEW, 0x15040d00);
4270 I915_WRITE(CSIEW0, 0x007f0000);
4271 I915_WRITE(CSIEW1, 0x1e220004);
4272 I915_WRITE(CSIEW2, 0x04000004);
4273
4274 for (i = 0; i < 5; i++)
4275 I915_WRITE(PEW + (i * 4), 0);
4276 for (i = 0; i < 3; i++)
4277 I915_WRITE(DEW + (i * 4), 0);
4278
4279 /* Program P-state weights to account for frequency power adjustment */
4280 for (i = 0; i < 16; i++) {
4281 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4282 unsigned long freq = intel_pxfreq(pxvidfreq);
4283 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4284 PXVFREQ_PX_SHIFT;
4285 unsigned long val;
4286
4287 val = vid * vid;
4288 val *= (freq / 1000);
4289 val *= 255;
4290 val /= (127*127*900);
4291 if (val > 0xff)
4292 DRM_ERROR("bad pxval: %ld\n", val);
4293 pxw[i] = val;
4294 }
4295 /* Render standby states get 0 weight */
4296 pxw[14] = 0;
4297 pxw[15] = 0;
4298
4299 for (i = 0; i < 4; i++) {
4300 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4301 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4302 I915_WRITE(PXW + (i * 4), val);
4303 }
4304
4305 /* Adjust magic regs to magic values (more experimental results) */
4306 I915_WRITE(OGW0, 0);
4307 I915_WRITE(OGW1, 0);
4308 I915_WRITE(EG0, 0x00007f00);
4309 I915_WRITE(EG1, 0x0000000e);
4310 I915_WRITE(EG2, 0x000e0000);
4311 I915_WRITE(EG3, 0x68000300);
4312 I915_WRITE(EG4, 0x42000000);
4313 I915_WRITE(EG5, 0x00140031);
4314 I915_WRITE(EG6, 0);
4315 I915_WRITE(EG7, 0);
4316
4317 for (i = 0; i < 8; i++)
4318 I915_WRITE(PXWL + (i * 4), 0);
4319
4320 /* Enable PMON + select events */
4321 I915_WRITE(ECR, 0x80000019);
4322
4323 lcfuse = I915_READ(LCFUSE02);
4324
20e4d407 4325 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4326}
4327
8090c6b9
DV		 4328void intel_disable_gt_powersave(struct drm_device *dev)
4329{
1a01ab3b
JB		 4330 struct drm_i915_private *dev_priv = dev->dev_private;
4331
fd0c0642
DV		 4332 /* Interrupts should be disabled already to avoid re-arming. */
4333 WARN_ON(dev->irq_enabled);
4334
930ebb46 4335 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4336 ironlake_disable_drps(dev);
930ebb46 4337 ironlake_disable_rc6(dev);
0a073b84 4338 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4339 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4340 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4341 if (IS_VALLEYVIEW(dev))
4342 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4343 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4344 if (IS_VALLEYVIEW(dev))
4345 valleyview_disable_rps(dev);
4346 else
4347 gen6_disable_rps(dev);
4fc688ce 4348 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4349 }
8090c6b9
DV		 4350}
4351
1a01ab3b
JB		 4352static void intel_gen6_powersave_work(struct work_struct *work)
4353{
4354 struct drm_i915_private *dev_priv =
4355 container_of(work, struct drm_i915_private,
4356 rps.delayed_resume_work.work);
4357 struct drm_device *dev = dev_priv->dev;
4358
4fc688ce 4359 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4360
4361 if (IS_VALLEYVIEW(dev)) {
4362 valleyview_enable_rps(dev);
4363 } else {
4364 gen6_enable_rps(dev);
4365 gen6_update_ring_freq(dev);
4366 }
4fc688ce 4367 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4368}
4369
8090c6b9
DV		 4370void intel_enable_gt_powersave(struct drm_device *dev)
4371{
1a01ab3b
JB		 4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373
8090c6b9
DV		 4374 if (IS_IRONLAKE_M(dev)) {
4375 ironlake_enable_drps(dev);
4376 ironlake_enable_rc6(dev);
4377 intel_init_emon(dev);
0a073b84 4378 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4379 /*
4380 * PCU communication is slow and this doesn't need to be
4381 * done at any specific time, so do this out of our fast path
4382 * to make resume and init faster.
4383 */
4384 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4385 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4386 }
4387}
4388
3107bd48
DV		 4389static void ibx_init_clock_gating(struct drm_device *dev)
4390{
4391 struct drm_i915_private *dev_priv = dev->dev_private;
4392
4393 /*
4394 * On Ibex Peak and Cougar Point, we need to disable clock
4395 * gating for the panel power sequencer or it will fail to
4396 * start up when no ports are active.
4397 */
4398 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4399}
4400
0e088b8f
VS		 4401static void g4x_disable_trickle_feed(struct drm_device *dev)
4402{
4403 struct drm_i915_private *dev_priv = dev->dev_private;
4404 int pipe;
4405
4406 for_each_pipe(pipe) {
4407 I915_WRITE(DSPCNTR(pipe),
4408 I915_READ(DSPCNTR(pipe)) |
4409 DISPPLANE_TRICKLE_FEED_DISABLE);
4410 intel_flush_display_plane(dev_priv, pipe);
4411 }
4412}
4413
1fa61106 4414static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4415{
4416 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4417 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 4418
4419 /* Required for FBC */
4d47e4f5
DL		 4420 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4421 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4422 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4423
4424 I915_WRITE(PCH_3DCGDIS0,
4425 MARIUNIT_CLOCK_GATE_DISABLE |
4426 SVSMUNIT_CLOCK_GATE_DISABLE);
4427 I915_WRITE(PCH_3DCGDIS1,
4428 VFMUNIT_CLOCK_GATE_DISABLE);
4429
6f1d69b0
ED		 4430 /*
4431 * According to the spec the following bits should be set in
4432 * order to enable memory self-refresh
4433 * The bit 22/21 of 0x42004
4434 * The bit 5 of 0x42020
4435 * The bit 15 of 0x45000
4436 */
4437 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4438 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4439 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4440 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4441 I915_WRITE(DISP_ARB_CTL,
4442 (I915_READ(DISP_ARB_CTL) |
4443 DISP_FBC_WM_DIS));
4444 I915_WRITE(WM3_LP_ILK, 0);
4445 I915_WRITE(WM2_LP_ILK, 0);
4446 I915_WRITE(WM1_LP_ILK, 0);
4447
4448 /*
4449 * Based on the document from hardware guys the following bits
4450 * should be set unconditionally in order to enable FBC.
4451 * The bit 22 of 0x42000
4452 * The bit 22 of 0x42004
4453 * The bit 7,8,9 of 0x42020.
4454 */
4455 if (IS_IRONLAKE_M(dev)) {
4bb35334 4456 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4457 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4458 I915_READ(ILK_DISPLAY_CHICKEN1) |
4459 ILK_FBCQ_DIS);
4460 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4461 I915_READ(ILK_DISPLAY_CHICKEN2) |
4462 ILK_DPARB_GATE);
6f1d69b0
ED		 4463 }
4464
4d47e4f5
DL		 4465 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4466
6f1d69b0
ED		 4467 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4468 I915_READ(ILK_DISPLAY_CHICKEN2) |
4469 ILK_ELPIN_409_SELECT);
4470 I915_WRITE(_3D_CHICKEN2,
4471 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4472 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4473
ecdb4eb7 4474 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4475 I915_WRITE(CACHE_MODE_0,
4476 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4477
0e088b8f 4478 g4x_disable_trickle_feed(dev);
bdad2b2f 4479
3107bd48
DV		 4480 ibx_init_clock_gating(dev);
4481}
4482
4483static void cpt_init_clock_gating(struct drm_device *dev)
4484{
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 int pipe;
3f704fa2 4487 uint32_t val;
3107bd48
DV		 4488
4489 /*
4490 * On Ibex Peak and Cougar Point, we need to disable clock
4491 * gating for the panel power sequencer or it will fail to
4492 * start up when no ports are active.
4493 */
4494 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4495 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4496 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4497 /* The below fixes the weird display corruption, a few pixels shifted
4498 * downward, on (only) LVDS of some HP laptops with IVY.
4499 */
3f704fa2 4500 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4501 val = I915_READ(TRANS_CHICKEN2(pipe));
4502 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4503 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4504 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4505 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4506 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4507 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4508 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4509 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4510 }
3107bd48
DV		 4511 /* WADP0ClockGatingDisable */
4512 for_each_pipe(pipe) {
4513 I915_WRITE(TRANS_CHICKEN1(pipe),
4514 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4515 }
6f1d69b0
ED		 4516}
4517
1d7aaa0c
DV		 4518static void gen6_check_mch_setup(struct drm_device *dev)
4519{
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 uint32_t tmp;
4522
4523 tmp = I915_READ(MCH_SSKPD);
4524 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4525 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4526 DRM_INFO("This can cause pipe underruns and display issues.\n");
4527 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4528 }
4529}
4530
1fa61106 4531static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4532{
4533 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4534 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4535
231e54f6 4536 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4537
4538 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4539 I915_READ(ILK_DISPLAY_CHICKEN2) |
4540 ILK_ELPIN_409_SELECT);
4541
ecdb4eb7 4542 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4543 I915_WRITE(_3D_CHICKEN,
4544 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4545
ecdb4eb7 4546 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4547 if (IS_SNB_GT1(dev))
4548 I915_WRITE(GEN6_GT_MODE,
4549 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4550
6f1d69b0
ED		 4551 I915_WRITE(WM3_LP_ILK, 0);
4552 I915_WRITE(WM2_LP_ILK, 0);
4553 I915_WRITE(WM1_LP_ILK, 0);
4554
6f1d69b0 4555 I915_WRITE(CACHE_MODE_0,
50743298 4556 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4557
4558 I915_WRITE(GEN6_UCGCTL1,
4559 I915_READ(GEN6_UCGCTL1) |
4560 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4561 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4562
4563 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4564 * gating disable must be set. Failure to set it results in
4565 * flickering pixels due to Z write ordering failures after
4566 * some amount of runtime in the Mesa "fire" demo, and Unigine
4567 * Sanctuary and Tropics, and apparently anything else with
4568 * alpha test or pixel discard.
4569 *
4570 * According to the spec, bit 11 (RCCUNIT) must also be set,
4571 * but we didn't debug actual testcases to find it out.
0f846f81 4572 *
ecdb4eb7
DL		 4573 * Also apply WaDisableVDSUnitClockGating:snb and
4574 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4575 */
4576 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4577 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4578 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4579 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4580
4581 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4582 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4583 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4584
4585 /*
4586 * According to the spec the following bits should be
4587 * set in order to enable memory self-refresh and fbc:
4588 * The bit21 and bit22 of 0x42000
4589 * The bit21 and bit22 of 0x42004
4590 * The bit5 and bit7 of 0x42020
4591 * The bit14 of 0x70180
4592 * The bit14 of 0x71180
4bb35334
DL		 4593 *
4594 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4595 */
4596 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4597 I915_READ(ILK_DISPLAY_CHICKEN1) |
4598 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4599 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4600 I915_READ(ILK_DISPLAY_CHICKEN2) |
4601 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4602 I915_WRITE(ILK_DSPCLK_GATE_D,
4603 I915_READ(ILK_DSPCLK_GATE_D) |
4604 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4605 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4606
ecdb4eb7 4607 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4608 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4609 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4610
0e088b8f 4611 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4612
4613 /* The default value should be 0x200 according to docs, but the two
4614 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4615 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4616 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4617
4618 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4619
4620 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4621}
4622
4623static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4624{
4625 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4626
4627 reg &= ~GEN7_FF_SCHED_MASK;
4628 reg |= GEN7_FF_TS_SCHED_HW;
4629 reg |= GEN7_FF_VS_SCHED_HW;
4630 reg |= GEN7_FF_DS_SCHED_HW;
4631
41c0b3a8
BW		 4632 if (IS_HASWELL(dev_priv->dev))
4633 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4634
6f1d69b0
ED		 4635 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4636}
4637
17a303ec
PZ		 4638static void lpt_init_clock_gating(struct drm_device *dev)
4639{
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641
4642 /*
4643 * TODO: this bit should only be enabled when really needed, then
4644 * disabled when not needed anymore in order to save power.
4645 */
4646 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4647 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4648 I915_READ(SOUTH_DSPCLK_GATE_D) |
4649 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4650
4651 /* WADPOClockGatingDisable:hsw */
4652 I915_WRITE(_TRANSA_CHICKEN1,
4653 I915_READ(_TRANSA_CHICKEN1) |
4654 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4655}
4656
7d708ee4
ID		 4657static void lpt_suspend_hw(struct drm_device *dev)
4658{
4659 struct drm_i915_private *dev_priv = dev->dev_private;
4660
4661 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4662 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4663
4664 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4665 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4666 }
4667}
4668
cad2a2d7
ED		 4669static void haswell_init_clock_gating(struct drm_device *dev)
4670{
4671 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4672
4673 I915_WRITE(WM3_LP_ILK, 0);
4674 I915_WRITE(WM2_LP_ILK, 0);
4675 I915_WRITE(WM1_LP_ILK, 0);
4676
4677 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4678 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4679 */
4680 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4681
ecdb4eb7 4682 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4683 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4684 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4685
ecdb4eb7 4686 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4687 I915_WRITE(GEN7_L3CNTLREG1,
4688 GEN7_WA_FOR_GEN7_L3_CONTROL);
4689 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4690 GEN7_WA_L3_CHICKEN_MODE);
4691
ecdb4eb7 4692 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4693 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4694 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4695 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4696
0e088b8f 4697 g4x_disable_trickle_feed(dev);
cad2a2d7 4698
ecdb4eb7 4699 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4700 gen7_setup_fixed_func_scheduler(dev_priv);
4701
ecdb4eb7 4702 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4703 I915_WRITE(CACHE_MODE_1,
4704 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4705
ecdb4eb7 4706 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4707 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4708 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4709
ecdb4eb7 4710 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4711 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4712
90a88643
PZ		 4713 /* WaRsPkgCStateDisplayPMReq:hsw */
4714 I915_WRITE(CHICKEN_PAR1_1,
4715 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4716
17a303ec 4717 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4718}
4719
1fa61106 4720static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4721{
4722 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4723 uint32_t snpcr;
6f1d69b0 4724
6f1d69b0
ED		 4725 I915_WRITE(WM3_LP_ILK, 0);
4726 I915_WRITE(WM2_LP_ILK, 0);
4727 I915_WRITE(WM1_LP_ILK, 0);
4728
231e54f6 4729 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4730
ecdb4eb7 4731 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4732 I915_WRITE(_3D_CHICKEN3,
4733 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4734
ecdb4eb7 4735 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4736 I915_WRITE(IVB_CHICKEN3,
4737 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4738 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4739
ecdb4eb7 4740 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4741 if (IS_IVB_GT1(dev))
4742 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4743 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4744 else
4745 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4746 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4747
ecdb4eb7 4748 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4749 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4750 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4751
ecdb4eb7 4752 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4753 I915_WRITE(GEN7_L3CNTLREG1,
4754 GEN7_WA_FOR_GEN7_L3_CONTROL);
4755 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4756 GEN7_WA_L3_CHICKEN_MODE);
4757 if (IS_IVB_GT1(dev))
4758 I915_WRITE(GEN7_ROW_CHICKEN2,
4759 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4760 else
4761 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4762 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4763
6f1d69b0 4764
ecdb4eb7 4765 /* WaForceL3Serialization:ivb */
61939d97
JB		 4766 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4767 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4768
0f846f81
JB		 4769 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4770 * gating disable must be set. Failure to set it results in
4771 * flickering pixels due to Z write ordering failures after
4772 * some amount of runtime in the Mesa "fire" demo, and Unigine
4773 * Sanctuary and Tropics, and apparently anything else with
4774 * alpha test or pixel discard.
4775 *
4776 * According to the spec, bit 11 (RCCUNIT) must also be set,
4777 * but we didn't debug actual testcases to find it out.
4778 *
4779 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4780 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4781 */
4782 I915_WRITE(GEN6_UCGCTL2,
4783 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4784 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4785
ecdb4eb7 4786 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4787 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4788 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4789 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4790
0e088b8f 4791 g4x_disable_trickle_feed(dev);
6f1d69b0 4792
ecdb4eb7 4793 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4794 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4795 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4796
ecdb4eb7 4797 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4798 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4799
ecdb4eb7 4800 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4801 I915_WRITE(CACHE_MODE_1,
4802 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4803
4804 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4805 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4806 snpcr |= GEN6_MBC_SNPCR_MED;
4807 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4808
ab5c608b
BW		 4809 if (!HAS_PCH_NOP(dev))
4810 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4811
4812 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4813}
4814
1fa61106 4815static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4816{
4817 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 4818
d7fe0cc0 4819 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4820
ecdb4eb7 4821 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4822 I915_WRITE(_3D_CHICKEN3,
4823 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4824
ecdb4eb7 4825 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4826 I915_WRITE(IVB_CHICKEN3,
4827 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4828 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4829
ecdb4eb7 4830 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4831 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4832 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4833 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4834
ecdb4eb7 4835 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4836 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4837 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4838
ecdb4eb7 4839 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4840 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4841 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4842
ecdb4eb7 4843 /* WaForceL3Serialization:vlv */
61939d97
JB		 4844 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4845 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4846
ecdb4eb7 4847 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4848 I915_WRITE(GEN7_ROW_CHICKEN2,
4849 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4850
ecdb4eb7 4851 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4852 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4853 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4854 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4855
ecdb4eb7 4856 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4857 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4858 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4859
0f846f81
JB		 4860
4861 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4862 * gating disable must be set. Failure to set it results in
4863 * flickering pixels due to Z write ordering failures after
4864 * some amount of runtime in the Mesa "fire" demo, and Unigine
4865 * Sanctuary and Tropics, and apparently anything else with
4866 * alpha test or pixel discard.
4867 *
4868 * According to the spec, bit 11 (RCCUNIT) must also be set,
4869 * but we didn't debug actual testcases to find it out.
4870 *
4871 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4872 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4873 *
ecdb4eb7
DL		 4874 * Also apply WaDisableVDSUnitClockGating:vlv and
4875 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4876 */
4877 I915_WRITE(GEN6_UCGCTL2,
4878 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4879 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4880 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4881 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4882 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4883
e3f33d46
JB		 4884 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4885
e0d8d59b 4886 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 4887
6b26c86d
DV		 4888 I915_WRITE(CACHE_MODE_1,
4889 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4890
2d809570 4891 /*
ecdb4eb7 4892 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4893 * Disable clock gating on th GCFG unit to prevent a delay
4894 * in the reporting of vblank events.
4895 */
4e8c84a5
JB		 4896 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4897
4898 /* Conservative clock gating settings for now */
4899 I915_WRITE(0x9400, 0xffffffff);
4900 I915_WRITE(0x9404, 0xffffffff);
4901 I915_WRITE(0x9408, 0xffffffff);
4902 I915_WRITE(0x940c, 0xffffffff);
4903 I915_WRITE(0x9410, 0xffffffff);
4904 I915_WRITE(0x9414, 0xffffffff);
4905 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4906}
4907
1fa61106 4908static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4909{
4910 struct drm_i915_private *dev_priv = dev->dev_private;
4911 uint32_t dspclk_gate;
4912
4913 I915_WRITE(RENCLK_GATE_D1, 0);
4914 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4915 GS_UNIT_CLOCK_GATE_DISABLE |
4916 CL_UNIT_CLOCK_GATE_DISABLE);
4917 I915_WRITE(RAMCLK_GATE_D, 0);
4918 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4919 OVRUNIT_CLOCK_GATE_DISABLE |
4920 OVCUNIT_CLOCK_GATE_DISABLE;
4921 if (IS_GM45(dev))
4922 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4923 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4924
4925 /* WaDisableRenderCachePipelinedFlush */
4926 I915_WRITE(CACHE_MODE_0,
4927 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 4928
0e088b8f 4929 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 4930}
4931
1fa61106 4932static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4933{
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935
4936 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4937 I915_WRITE(RENCLK_GATE_D2, 0);
4938 I915_WRITE(DSPCLK_GATE_D, 0);
4939 I915_WRITE(RAMCLK_GATE_D, 0);
4940 I915_WRITE16(DEUC, 0);
20f94967
VS		 4941 I915_WRITE(MI_ARB_STATE,
4942 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4943}
4944
1fa61106 4945static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4946{
4947 struct drm_i915_private *dev_priv = dev->dev_private;
4948
4949 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4950 I965_RCC_CLOCK_GATE_DISABLE |
4951 I965_RCPB_CLOCK_GATE_DISABLE |
4952 I965_ISC_CLOCK_GATE_DISABLE |
4953 I965_FBC_CLOCK_GATE_DISABLE);
4954 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 4955 I915_WRITE(MI_ARB_STATE,
4956 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4957}
4958
1fa61106 4959static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4960{
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 u32 dstate = I915_READ(D_STATE);
4963
4964 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4965 DSTATE_DOT_CLOCK_GATING;
4966 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4967
4968 if (IS_PINEVIEW(dev))
4969 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4970
4971 /* IIR "flip pending" means done if this bit is set */
4972 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4973}
4974
1fa61106 4975static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4976{
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978
4979 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4980}
4981
1fa61106 4982static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4983{
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985
4986 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4987}
4988
6f1d69b0
ED		 4989void intel_init_clock_gating(struct drm_device *dev)
4990{
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992
4993 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4994}
4995
7d708ee4
ID		 4996void intel_suspend_hw(struct drm_device *dev)
4997{
4998 if (HAS_PCH_LPT(dev))
4999 lpt_suspend_hw(dev);
5000}
5001
15d199ea
PZ		 5002/**
5003 * We should only use the power well if we explicitly asked the hardware to
5004 * enable it, so check if it's enabled and also check if we've requested it to
5005 * be enabled.
5006 */
b97186f0
PZ		 5007bool intel_display_power_enabled(struct drm_device *dev,
5008 enum intel_display_power_domain domain)
15d199ea
PZ		 5009{
5010 struct drm_i915_private *dev_priv = dev->dev_private;
5011
b97186f0
PZ		 5012 if (!HAS_POWER_WELL(dev))
5013 return true;
5014
5015 switch (domain) {
5016 case POWER_DOMAIN_PIPE_A:
5017 case POWER_DOMAIN_TRANSCODER_EDP:
5018 return true;
5019 case POWER_DOMAIN_PIPE_B:
5020 case POWER_DOMAIN_PIPE_C:
5021 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5022 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5023 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5024 case POWER_DOMAIN_TRANSCODER_A:
5025 case POWER_DOMAIN_TRANSCODER_B:
5026 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5027 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5028 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5029 default:
5030 BUG();
5031 }
15d199ea
PZ		 5032}
5033
a38911a3 5034static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5035{
5036 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5037 bool is_enabled, enable_requested;
5038 uint32_t tmp;
d0d3e513 5039
fa42e23c
PZ		 5040 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5041 is_enabled = tmp & HSW_PWR_WELL_STATE;
5042 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5043
fa42e23c
PZ		 5044 if (enable) {
5045 if (!enable_requested)
5046 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5047
fa42e23c
PZ		 5048 if (!is_enabled) {
5049 DRM_DEBUG_KMS("Enabling power well\n");
5050 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5051 HSW_PWR_WELL_STATE), 20))
5052 DRM_ERROR("Timeout enabling power well\n");
5053 }
5054 } else {
5055 if (enable_requested) {
5056 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5057 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5058 }
5059 }
fa42e23c 5060}
d0d3e513 5061
a38911a3
WX		 5062static struct i915_power_well *hsw_pwr;
5063
5064/* Display audio driver power well request */
5065void i915_request_power_well(void)
5066{
5067 if (WARN_ON(!hsw_pwr))
5068 return;
5069
5070 spin_lock_irq(&hsw_pwr->lock);
5071 if (!hsw_pwr->count++ &&
5072 !hsw_pwr->i915_request)
5073 __intel_set_power_well(hsw_pwr->device, true);
5074 spin_unlock_irq(&hsw_pwr->lock);
5075}
5076EXPORT_SYMBOL_GPL(i915_request_power_well);
5077
5078/* Display audio driver power well release */
5079void i915_release_power_well(void)
5080{
5081 if (WARN_ON(!hsw_pwr))
5082 return;
5083
5084 spin_lock_irq(&hsw_pwr->lock);
5085 WARN_ON(!hsw_pwr->count);
5086 if (!--hsw_pwr->count &&
5087 !hsw_pwr->i915_request)
5088 __intel_set_power_well(hsw_pwr->device, false);
5089 spin_unlock_irq(&hsw_pwr->lock);
5090}
5091EXPORT_SYMBOL_GPL(i915_release_power_well);
5092
5093int i915_init_power_well(struct drm_device *dev)
5094{
5095 struct drm_i915_private *dev_priv = dev->dev_private;
5096
5097 hsw_pwr = &dev_priv->power_well;
5098
5099 hsw_pwr->device = dev;
5100 spin_lock_init(&hsw_pwr->lock);
5101 hsw_pwr->count = 0;
5102
5103 return 0;
5104}
5105
5106void i915_remove_power_well(struct drm_device *dev)
5107{
5108 hsw_pwr = NULL;
5109}
5110
5111void intel_set_power_well(struct drm_device *dev, bool enable)
5112{
5113 struct drm_i915_private *dev_priv = dev->dev_private;
5114 struct i915_power_well *power_well = &dev_priv->power_well;
5115
5116 if (!HAS_POWER_WELL(dev))
5117 return;
5118
5119 if (!i915_disable_power_well && !enable)
5120 return;
5121
5122 spin_lock_irq(&power_well->lock);
5123 power_well->i915_request = enable;
5124
5125 /* only reject "disable" power well request */
5126 if (power_well->count && !enable) {
5127 spin_unlock_irq(&power_well->lock);
5128 return;
5129 }
5130
5131 __intel_set_power_well(dev, enable);
5132 spin_unlock_irq(&power_well->lock);
5133}
5134
fa42e23c
PZ		 5135/*
5136 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5137 * when not needed anymore. We have 4 registers that can request the power well
5138 * to be enabled, and it will only be disabled if none of the registers is
5139 * requesting it to be enabled.
d0d3e513 5140 */
fa42e23c 5141void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5142{
5143 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5144
86d52df6 5145 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5146 return;
5147
fa42e23c
PZ		 5148 /* For now, we need the power well to be always enabled. */
5149 intel_set_power_well(dev, true);
d0d3e513 5150
fa42e23c
PZ		 5151 /* We're taking over the BIOS, so clear any requests made by it since
5152 * the driver is in charge now. */
5153 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5154 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5155}
5156
1fa61106
ED		 5157/* Set up chip specific power management-related functions */
5158void intel_init_pm(struct drm_device *dev)
5159{
5160 struct drm_i915_private *dev_priv = dev->dev_private;
5161
5162 if (I915_HAS_FBC(dev)) {
5163 if (HAS_PCH_SPLIT(dev)) {
5164 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5165 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5166 dev_priv->display.enable_fbc =
5167 gen7_enable_fbc;
5168 else
5169 dev_priv->display.enable_fbc =
5170 ironlake_enable_fbc;
1fa61106
ED		 5171 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5172 } else if (IS_GM45(dev)) {
5173 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5174 dev_priv->display.enable_fbc = g4x_enable_fbc;
5175 dev_priv->display.disable_fbc = g4x_disable_fbc;
5176 } else if (IS_CRESTLINE(dev)) {
5177 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5178 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5179 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5180 }
5181 /* 855GM needs testing */
5182 }
5183
c921aba8
DV		 5184 /* For cxsr */
5185 if (IS_PINEVIEW(dev))
5186 i915_pineview_get_mem_freq(dev);
5187 else if (IS_GEN5(dev))
5188 i915_ironlake_get_mem_freq(dev);
5189
1fa61106
ED		 5190 /* For FIFO watermark updates */
5191 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 5192 if (IS_GEN5(dev)) {
5193 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5194 dev_priv->display.update_wm = ironlake_update_wm;
5195 else {
5196 DRM_DEBUG_KMS("Failed to get proper latency. "
5197 "Disable CxSR\n");
5198 dev_priv->display.update_wm = NULL;
5199 }
5200 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5201 } else if (IS_GEN6(dev)) {
5202 if (SNB_READ_WM0_LATENCY()) {
5203 dev_priv->display.update_wm = sandybridge_update_wm;
5204 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5205 } else {
5206 DRM_DEBUG_KMS("Failed to read display plane latency. "
5207 "Disable CxSR\n");
5208 dev_priv->display.update_wm = NULL;
5209 }
5210 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5211 } else if (IS_IVYBRIDGE(dev)) {
1fa61106 5212 if (SNB_READ_WM0_LATENCY()) {
c43d0188 5213 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5214 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5215 } else {
5216 DRM_DEBUG_KMS("Failed to read display plane latency. "
5217 "Disable CxSR\n");
5218 dev_priv->display.update_wm = NULL;
5219 }
5220 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5221 } else if (IS_HASWELL(dev)) {
3e1f7266 5222 if (I915_READ64(MCH_SSKPD)) {
1011d8c4 5223 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5224 dev_priv->display.update_sprite_wm =
5225 haswell_update_sprite_wm;
6b8a5eeb
ED		 5226 } else {
5227 DRM_DEBUG_KMS("Failed to read display plane latency. "
5228 "Disable CxSR\n");
5229 dev_priv->display.update_wm = NULL;
5230 }
cad2a2d7 5231 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5232 } else
5233 dev_priv->display.update_wm = NULL;
5234 } else if (IS_VALLEYVIEW(dev)) {
5235 dev_priv->display.update_wm = valleyview_update_wm;
5236 dev_priv->display.init_clock_gating =
5237 valleyview_init_clock_gating;
1fa61106
ED		 5238 } else if (IS_PINEVIEW(dev)) {
5239 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5240 dev_priv->is_ddr3,
5241 dev_priv->fsb_freq,
5242 dev_priv->mem_freq)) {
5243 DRM_INFO("failed to find known CxSR latency "
5244 "(found ddr%s fsb freq %d, mem freq %d), "
5245 "disabling CxSR\n",
5246 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5247 dev_priv->fsb_freq, dev_priv->mem_freq);
5248 /* Disable CxSR and never update its watermark again */
5249 pineview_disable_cxsr(dev);
5250 dev_priv->display.update_wm = NULL;
5251 } else
5252 dev_priv->display.update_wm = pineview_update_wm;
5253 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5254 } else if (IS_G4X(dev)) {
5255 dev_priv->display.update_wm = g4x_update_wm;
5256 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5257 } else if (IS_GEN4(dev)) {
5258 dev_priv->display.update_wm = i965_update_wm;
5259 if (IS_CRESTLINE(dev))
5260 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5261 else if (IS_BROADWATER(dev))
5262 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5263 } else if (IS_GEN3(dev)) {
5264 dev_priv->display.update_wm = i9xx_update_wm;
5265 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5266 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5267 } else if (IS_I865G(dev)) {
5268 dev_priv->display.update_wm = i830_update_wm;
5269 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5270 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5271 } else if (IS_I85X(dev)) {
5272 dev_priv->display.update_wm = i9xx_update_wm;
5273 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5274 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5275 } else {
5276 dev_priv->display.update_wm = i830_update_wm;
5277 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5278 if (IS_845G(dev))
5279 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5280 else
5281 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5282 }
5283}
5284
6590190d
ED		 5285static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
5286{
5287 u32 gt_thread_status_mask;
5288
5289 if (IS_HASWELL(dev_priv->dev))
5290 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
5291 else
5292 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
5293
5294 /* w/a for a sporadic read returning 0 by waiting for the GT
5295 * thread to wake up.
5296 */
5297 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
5298 DRM_ERROR("GT thread status wait timed out\n");
5299}
5300
16995a9f
CW		 5301static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
5302{
5303 I915_WRITE_NOTRACE(FORCEWAKE, 0);
5304 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
5305}
5306
6590190d
ED		 5307static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5308{
ebd37ce1 5309 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
057d3860 5310 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5311 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5312
30771e16 5313 I915_WRITE_NOTRACE(FORCEWAKE, 1);
8dee3eea 5314 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 5315
ebd37ce1 5316 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
057d3860 5317 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5318 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5319
8693a824 5320 /* WaRsForcewakeWaitTC0:snb */
6590190d
ED		 5321 __gen6_gt_wait_for_thread_c0(dev_priv);
5322}
5323
16995a9f
CW		 5324static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
5325{
5326 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5327 /* something from same cacheline, but !FORCEWAKE_MT */
5328 POSTING_READ(ECOBUS);
16995a9f
CW		 5329}
5330
6590190d
ED		 5331static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
5332{
5333 u32 forcewake_ack;
5334
5335 if (IS_HASWELL(dev_priv->dev))
5336 forcewake_ack = FORCEWAKE_ACK_HSW;
5337 else
5338 forcewake_ack = FORCEWAKE_MT_ACK;
5339
83983c8b 5340 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
057d3860 5341 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5342 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5343
c5836c27 5344 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5345 /* something from same cacheline, but !FORCEWAKE_MT */
5346 POSTING_READ(ECOBUS);
6590190d 5347
83983c8b 5348 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
057d3860 5349 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5350 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5351
8693a824 5352 /* WaRsForcewakeWaitTC0:ivb,hsw */
6590190d
ED		 5353 __gen6_gt_wait_for_thread_c0(dev_priv);
5354}
5355
5356/*
5357 * Generally this is called implicitly by the register read function. However,
5358 * if some sequence requires the GT to not power down then this function should
5359 * be called at the beginning of the sequence followed by a call to
5360 * gen6_gt_force_wake_put() at the end of the sequence.
5361 */
5362void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5363{
5364 unsigned long irqflags;
5365
5366 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5367 if (dev_priv->forcewake_count++ == 0)
5368 dev_priv->gt.force_wake_get(dev_priv);
5369 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5370}
5371
5372void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
5373{
5374 u32 gtfifodbg;
5375 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
5376 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
5377 "MMIO read or write has been dropped %x\n", gtfifodbg))
5378 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
5379}
5380
5381static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5382{
5383 I915_WRITE_NOTRACE(FORCEWAKE, 0);
b5144075
JN		 5384 /* something from same cacheline, but !FORCEWAKE */
5385 POSTING_READ(ECOBUS);
6590190d
ED		 5386 gen6_gt_check_fifodbg(dev_priv);
5387}
5388
5389static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
5390{
c5836c27 5391 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5392 /* something from same cacheline, but !FORCEWAKE_MT */
5393 POSTING_READ(ECOBUS);
6590190d
ED		 5394 gen6_gt_check_fifodbg(dev_priv);
5395}
5396
5397/*
5398 * see gen6_gt_force_wake_get()
5399 */
5400void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5401{
5402 unsigned long irqflags;
5403
5404 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5405 if (--dev_priv->forcewake_count == 0)
5406 dev_priv->gt.force_wake_put(dev_priv);
5407 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5408}
5409
5410int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
5411{
5412 int ret = 0;
5413
5414 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
5415 int loop = 500;
5416 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5417 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
5418 udelay(10);
5419 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5420 }
5421 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
5422 ++ret;
5423 dev_priv->gt_fifo_count = fifo;
5424 }
5425 dev_priv->gt_fifo_count--;
5426
5427 return ret;
5428}
5429
16995a9f
CW		 5430static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
5431{
5432 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5433 /* something from same cacheline, but !FORCEWAKE_VLV */
5434 POSTING_READ(FORCEWAKE_ACK_VLV);
16995a9f
CW		 5435}
5436
6590190d
ED		 5437static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
5438{
83983c8b 5439 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
057d3860 5440 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5441 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5442
c5836c27 5443 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5444 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5445 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 5446
83983c8b 5447 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
057d3860 5448 FORCEWAKE_ACK_TIMEOUT_MS))
ed5de399
JB		 5449 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
5450
5451 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
5452 FORCEWAKE_KERNEL),
5453 FORCEWAKE_ACK_TIMEOUT_MS))
5454 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
6590190d 5455
8693a824 5456 /* WaRsForcewakeWaitTC0:vlv */
6590190d
ED		 5457 __gen6_gt_wait_for_thread_c0(dev_priv);
5458}
5459
5460static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
5461{
c5836c27 5462 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5463 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5464 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5465 /* The below doubles as a POSTING_READ */
5ab140a4 5466 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 5467}
5468
16995a9f
CW		 5469void intel_gt_reset(struct drm_device *dev)
5470{
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5472
5473 if (IS_VALLEYVIEW(dev)) {
5474 vlv_force_wake_reset(dev_priv);
5475 } else if (INTEL_INFO(dev)->gen >= 6) {
5476 __gen6_gt_force_wake_reset(dev_priv);
5477 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5478 __gen6_gt_force_wake_mt_reset(dev_priv);
5479 }
5480}
5481
6590190d
ED		 5482void intel_gt_init(struct drm_device *dev)
5483{
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485
5486 spin_lock_init(&dev_priv->gt_lock);
5487
16995a9f
CW		 5488 intel_gt_reset(dev);
5489
6590190d
ED		 5490 if (IS_VALLEYVIEW(dev)) {
5491 dev_priv->gt.force_wake_get = vlv_force_wake_get;
5492 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 5493 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5494 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
5495 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
5496 } else if (IS_GEN6(dev)) {
6590190d
ED		 5497 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
5498 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 5499 }
1a01ab3b
JB		 5500 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5501 intel_gen6_powersave_work);
6590190d
ED		 5502}
5503
42c0526c
BW		 5504int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5505{
4fc688ce 5506 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5507
5508 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5509 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5510 return -EAGAIN;
5511 }
5512
5513 I915_WRITE(GEN6_PCODE_DATA, *val);
5514 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5515
5516 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5517 500)) {
5518 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5519 return -ETIMEDOUT;
5520 }
5521
5522 *val = I915_READ(GEN6_PCODE_DATA);
5523 I915_WRITE(GEN6_PCODE_DATA, 0);
5524
5525 return 0;
5526}
5527
5528int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5529{
4fc688ce 5530 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5531
5532 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5533 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5534 return -EAGAIN;
5535 }
5536
5537 I915_WRITE(GEN6_PCODE_DATA, val);
5538 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5539
5540 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5541 500)) {
5542 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5543 return -ETIMEDOUT;
5544 }
5545
5546 I915_WRITE(GEN6_PCODE_DATA, 0);
5547
5548 return 0;
5549}
a0e4e199 5550
855ba3be
JB		 5551int vlv_gpu_freq(int ddr_freq, int val)
5552{
5553 int mult, base;
5554
5555 switch (ddr_freq) {
5556 case 800:
5557 mult = 20;
5558 base = 120;
5559 break;
5560 case 1066:
5561 mult = 22;
5562 base = 133;
5563 break;
5564 case 1333:
5565 mult = 21;
5566 base = 125;
5567 break;
5568 default:
5569 return -1;
5570 }
5571
5572 return ((val - 0xbd) * mult) + base;
5573}
5574
5575int vlv_freq_opcode(int ddr_freq, int val)
5576{
5577 int mult, base;
5578
5579 switch (ddr_freq) {
5580 case 800:
5581 mult = 20;
5582 base = 120;
5583 break;
5584 case 1066:
5585 mult = 22;
5586 base = 133;
5587 break;
5588 case 1333:
5589 mult = 21;
5590 base = 125;
5591 break;
5592 default:
5593 return -1;
5594 }
5595
5596 val /= mult;
5597 val -= base / mult;
5598 val += 0xbd;
5599
5600 if (val > 0xea)
5601 val = 0xea;
5602
5603 return val;
5604}
5605
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