]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/gen9: fix the WaWmMemoryReadLatency implementation
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
63c62275 255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4 342 } else if (IS_I915GM(dev)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 655 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
7c5f93b0 661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 663 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
ac484963 668 cpp, latency->display_sr);
b445e3b0
ED		 669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
ac484963 678 cpp, latency->cursor_sr);
b445e3b0
ED		 679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
ac484963 687 cpp, latency->display_hpll_disable);
b445e3b0
ED		 688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
ac484963 696 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
ac484963 720 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
ac484963 738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
ac484963 806 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 826 line_size = hdisplay * cpp;
b445e3b0
ED		 827
828 /* Use the minimum of the small and large buffer method for primary */
ac484963 829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
ac484963 836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
2cb389b7
VS		 907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
ae80152d 913 POSTING_READ(DSPFW1);
0018fda1
VS		 914}
915
15665979
VS		 916#undef FW_WM_VLV
917
6eb1a681
VS		 918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 922};
923
262cd2e1
VS		 924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
ac484963 928 unsigned int cpp,
262cd2e1
VS		 929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 934 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
fac5e23e 942 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
58590c14
VS		 947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
262cd2e1
VS		 949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 963 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
936e71e3 968 if (!state->base.visible)
262cd2e1
VS		 969 return 0;
970
ac484963 971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
ac484963 987 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
54f1b6e1
VS		 994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
936e71e3 1010 if (state->base.visible) {
54f1b6e1
VS		 1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
936e71e3 1026 if (!state->base.visible) {
54f1b6e1
VS		 1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
262cd2e1
VS		 1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
26e1fe4f 1095static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
852eb00d 1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1107
1108 wm_state->num_active_planes = 0;
262cd2e1 1109
54f1b6e1 1110 vlv_compute_fifo(crtc);
262cd2e1
VS		 1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
936e71e3 1126 if (!state->base.visible)
262cd2e1
VS		 1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
5a37ed0a 1167 wm_state->wm[level].cursor;
262cd2e1
VS		 1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
58590c14 1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
54f1b6e1
VS		 1194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
262cd2e1
VS		 1284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
58590c14 1290 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
6f9c784b
VS		 1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
262cd2e1
VS		 1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
fac5e23e 1333 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
26e1fe4f 1338 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1339 vlv_merge_wm(dev, &wm);
1340
54f1b6e1
VS		 1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1344 return;
54f1b6e1 1345 }
262cd2e1
VS		 1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
852eb00d 1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1356 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1357
54f1b6e1
VS		 1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
262cd2e1
VS		 1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
852eb00d 1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1370 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1381}
1382
ae80152d
VS		 1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
46ba614c 1385static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1386{
46ba614c 1387 struct drm_device *dev = crtc->dev;
b445e3b0 1388 static const int sr_latency_ns = 12000;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
9858425c 1393 bool cxsr_enabled;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planea_wm, &cursora_wm))
51cea1f4 1399 enabled |= 1 << PIPE_A;
b445e3b0 1400
51cea1f4 1401 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1404 &planeb_wm, &cursorb_wm))
51cea1f4 1405 enabled |= 1 << PIPE_B;
b445e3b0 1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
9858425c 1413 cxsr_enabled = true;
52bd02d8 1414 } else {
9858425c 1415 cxsr_enabled = false;
5209b1f4 1416 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0 1419
a5043453
VS		 1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
f4998963
VS		 1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
b445e3b0 1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1433 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
8c919b28 1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1437 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1441}
1442
46ba614c 1443static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1444{
46ba614c 1445 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
9858425c 1450 bool cxsr_enabled;
b445e3b0
ED		 1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
124abe07 1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1458 int clock = adjusted_mode->crtc_clock;
fec8cba3 1459 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1462 unsigned long line_time_us;
1463 int entries;
1464
922044c9 1465 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1469 cpp * hdisplay;
b445e3b0
ED		 1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
9858425c 1491 cxsr_enabled = true;
b445e3b0 1492 } else {
9858425c 1493 cxsr_enabled = false;
b445e3b0 1494 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1495 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
f4998963
VS		 1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
b445e3b0 1508 /* update cursor SR watermark */
f4998963 1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1513}
1514
f4998963
VS		 1515#undef FW_WM
1516
46ba614c 1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1518{
46ba614c 1519 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1520 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
9d539105 1534 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
ac484963 1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
6e3c9717 1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
5aef6003 1547 pessimal_latency_ns);
b445e3b0 1548 enabled = crtc;
9d539105 1549 } else {
b445e3b0 1550 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
ac484963 1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
6e3c9717 1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
5aef6003 1569 pessimal_latency_ns);
b445e3b0
ED		 1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
9d539105 1574 } else {
b445e3b0 1575 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
b445e3b0
ED		 1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
2ab1bc9d 1582 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1583 struct drm_i915_gem_object *obj;
2ab1bc9d 1584
59bea882 1585 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1586
1587 /* self-refresh seems busted with untiled */
3e510a8e 1588 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1589 enabled = NULL;
1590 }
1591
b445e3b0
ED		 1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1598 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
124abe07 1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1605 int clock = adjusted_mode->crtc_clock;
fec8cba3 1606 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1609 unsigned long line_time_us;
1610 int entries;
1611
2d1b5056
VS		 1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1619 cpp * hdisplay;
b445e3b0
ED		 1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1629 else
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
5209b1f4
ID		 1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1648}
1649
feb56b93 1650static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1651{
46ba614c 1652 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1654 struct drm_crtc *crtc;
241bfc38 1655 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
6e3c9717 1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1665 &i845_wm_info,
b445e3b0 1666 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1667 4, pessimal_latency_ns);
b445e3b0
ED		 1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
8cfb3407 1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1677{
fd4daa9c 1678 uint32_t pixel_rate;
801bcfff 1679
8cfb3407 1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
8cfb3407 1685 if (pipe_config->pch_pfit.enabled) {
801bcfff 1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
801bcfff 1691
801bcfff
PZ		 1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
15126882
MR		 1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
801bcfff
PZ		 1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
37126462 1709/* latency must be in 0.1us units. */
ac484963 1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1711{
1712 uint64_t ret;
1713
3312ba65
VS		 1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
ac484963 1717 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
37126462 1723/* latency must be in 0.1us units. */
23297044 1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1725 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
3312ba65
VS		 1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
15126882
MR		 1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
3312ba65 1734
801bcfff 1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1736 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
23297044 1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1742 uint8_t cpp)
cca32e9a 1743{
15126882
MR		 1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
ac484963 1750 if (WARN_ON(!cpp))
15126882
MR		 1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
ac484963 1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1756}
1757
820c1980 1758struct ilk_wm_maximums {
cca32e9a
PZ		 1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
37126462
VS		 1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
7221fc33 1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1770 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1771 uint32_t mem_value,
1772 bool is_lp)
801bcfff 1773{
ac484963
VS		 1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1776 uint32_t method1, method2;
1777
936e71e3 1778 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1779 return 0;
1780
ac484963 1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1782
1783 if (!is_lp)
1784 return method1;
1785
7221fc33
MR		 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1788 drm_rect_width(&pstate->base.dst),
ac484963 1789 cpp, mem_value);
cca32e9a
PZ		 1790
1791 return min(method1, method2);
801bcfff
PZ		 1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1804 uint32_t method1, method2;
1805
936e71e3 1806 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1807 return 0;
1808
ac484963 1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1812 drm_rect_width(&pstate->base.dst),
ac484963 1813 cpp, mem_value);
801bcfff
PZ		 1814 return min(method1, method2);
1815}
1816
37126462
VS		 1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
7221fc33 1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1822 const struct intel_plane_state *pstate,
801bcfff
PZ		 1823 uint32_t mem_value)
1824{
b2435692
MR		 1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
936e71e3 1831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1832
b2435692 1833 if (!cstate->base.active)
801bcfff
PZ		 1834 return 0;
1835
7221fc33
MR		 1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1838 width, cpp, mem_value);
801bcfff
PZ		 1839}
1840
cca32e9a 1841/* Only for WM_LP. */
7221fc33 1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1843 const struct intel_plane_state *pstate,
1fda9882 1844 uint32_t pri_val)
cca32e9a 1845{
ac484963
VS		 1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1848
936e71e3 1849 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1850 return 0;
1851
936e71e3 1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1853}
1854
158ae64f
VS		 1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
416f4727
VS		 1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1860 return 768;
1861 else
1862 return 512;
1863}
1864
4e975081
VS		 1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
158ae64f
VS		 1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
240264f4 1902 const struct intel_wm_config *config,
158ae64f
VS		 1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1907
1908 /* if sprites aren't enabled, sprites get nothing */
240264f4 1909 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1913 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
240264f4 1925 if (config->sprites_enabled) {
158ae64f
VS		 1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
4e975081 1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1942 int level,
1943 const struct intel_wm_config *config)
158ae64f
VS		 1944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1946 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
4e975081 1950 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1951}
1952
d34ff9c6 1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1957 struct ilk_wm_maximums *max)
158ae64f 1958{
240264f4
VS		 1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1962 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1963}
1964
a3cb4048
VS		 1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
d9395655 1975static bool ilk_validate_wm_level(int level,
820c1980 1976 const struct ilk_wm_maximums *max,
d9395655 1977 struct intel_wm_level *result)
a9786a11
VS		 1978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
a9786a11
VS		 2013 return ret;
2014}
2015
d34ff9c6 2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2017 const struct intel_crtc *intel_crtc,
6f5ddd17 2018 int level,
7221fc33 2019 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
e3bddded
ML		 2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
6f5ddd17
VS		 2048 result->enable = true;
2049}
2050
801bcfff 2051static uint32_t
532f7a7f 2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2053{
532f7a7f
VS		 2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
85a02deb 2058 u32 linetime, ips_linetime;
1f8eeabf 2059
ee91a159
MR		 2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
532f7a7f 2064 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2065 return 0;
1011d8c4 2066
1f8eeabf
ED		 2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
124abe07
VS		 2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2073 intel_state->cdclk);
1f8eeabf 2074
801bcfff
PZ		 2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2077}
2078
2af30a5c 2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2080{
fac5e23e 2081 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2082
2af30a5c
PB		 2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
4f947386 2085 int ret, i;
367294be 2086 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
4e4d3814
PZ		 2129 /*
2130 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2131 * need to be disabled. We make sure to sanitize the values out
2132 * of the punit to satisfy this requirement.
2133 */
2134 for (level = 1; level <= max_level; level++) {
2135 if (wm[level] == 0) {
2136 for (i = level + 1; i <= max_level; i++)
2137 wm[i] = 0;
2138 break;
2139 }
2140 }
2141
367294be 2142 /*
6f97235b
DL		 2143 * WaWmMemoryReadLatency:skl
2144 *
367294be 2145 * punit doesn't take into account the read latency so we need
4e4d3814
PZ		 2146 * to add 2us to the various latency levels we retrieve from the
2147 * punit when level 0 response data us 0us.
367294be 2148 */
4e4d3814
PZ		 2149 if (wm[0] == 0) {
2150 wm[0] += 2;
2151 for (level = 1; level <= max_level; level++) {
2152 if (wm[level] == 0)
2153 break;
367294be 2154 wm[level] += 2;
4f947386 2155 }
4e4d3814
PZ		 2156 }
2157
2af30a5c 2158 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2159 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2160
2161 wm[0] = (sskpd >> 56) & 0xFF;
2162 if (wm[0] == 0)
2163 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2164 wm[1] = (sskpd >> 4) & 0xFF;
2165 wm[2] = (sskpd >> 12) & 0xFF;
2166 wm[3] = (sskpd >> 20) & 0x1FF;
2167 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2168 } else if (INTEL_INFO(dev)->gen >= 6) {
2169 uint32_t sskpd = I915_READ(MCH_SSKPD);
2170
2171 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2172 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2173 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2174 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2175 } else if (INTEL_INFO(dev)->gen >= 5) {
2176 uint32_t mltr = I915_READ(MLTR_ILK);
2177
2178 /* ILK primary LP0 latency is 700 ns */
2179 wm[0] = 7;
2180 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2181 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2182 }
2183}
2184
53615a5e
VS		 2185static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2186{
2187 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2188 if (IS_GEN5(dev))
53615a5e
VS		 2189 wm[0] = 13;
2190}
2191
2192static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2195 if (IS_GEN5(dev))
53615a5e
VS		 2196 wm[0] = 13;
2197
2198 /* WaDoubleCursorLP3Latency:ivb */
2199 if (IS_IVYBRIDGE(dev))
2200 wm[3] *= 2;
2201}
2202
546c81fd 2203int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2204{
26ec971e 2205 /* how many WM levels are we expecting */
b6e742f6 2206 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2207 return 7;
2208 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2209 return 4;
26ec971e 2210 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2211 return 3;
26ec971e 2212 else
ad0d6dc4
VS		 2213 return 2;
2214}
7526ed79 2215
ad0d6dc4
VS		 2216static void intel_print_wm_latency(struct drm_device *dev,
2217 const char *name,
2af30a5c 2218 const uint16_t wm[8])
ad0d6dc4
VS		 2219{
2220 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2221
2222 for (level = 0; level <= max_level; level++) {
2223 unsigned int latency = wm[level];
2224
2225 if (latency == 0) {
2226 DRM_ERROR("%s WM%d latency not provided\n",
2227 name, level);
2228 continue;
2229 }
2230
2af30a5c
PB		 2231 /*
2232 * - latencies are in us on gen9.
2233 * - before then, WM1+ latency values are in 0.5us units
2234 */
2235 if (IS_GEN9(dev))
2236 latency *= 10;
2237 else if (level > 0)
26ec971e
VS		 2238 latency *= 5;
2239
2240 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2241 name, level, wm[level],
2242 latency / 10, latency % 10);
2243 }
2244}
2245
e95a2f75
VS		 2246static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2247 uint16_t wm[5], uint16_t min)
2248{
91c8a326 2249 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2250
2251 if (wm[0] >= min)
2252 return false;
2253
2254 wm[0] = max(wm[0], min);
2255 for (level = 1; level <= max_level; level++)
2256 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2257
2258 return true;
2259}
2260
2261static void snb_wm_latency_quirk(struct drm_device *dev)
2262{
fac5e23e 2263 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2264 bool changed;
2265
2266 /*
2267 * The BIOS provided WM memory latency values are often
2268 * inadequate for high resolution displays. Adjust them.
2269 */
2270 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2271 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2272 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2273
2274 if (!changed)
2275 return;
2276
2277 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2278 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281}
2282
fa50ad61 2283static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2284{
fac5e23e 2285 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2286
2287 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2288
2289 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2292 sizeof(dev_priv->wm.pri_latency));
2293
2294 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2295 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2296
2297 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2298 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2299 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2300
2301 if (IS_GEN6(dev))
2302 snb_wm_latency_quirk(dev);
53615a5e
VS		 2303}
2304
2af30a5c
PB		 2305static void skl_setup_wm_latency(struct drm_device *dev)
2306{
fac5e23e 2307 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2308
2309 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2310 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2311}
2312
ed4a6a7c
MR		 2313static bool ilk_validate_pipe_wm(struct drm_device *dev,
2314 struct intel_pipe_wm *pipe_wm)
2315{
2316 /* LP0 watermark maximums depend on this pipe alone */
2317 const struct intel_wm_config config = {
2318 .num_pipes_active = 1,
2319 .sprites_enabled = pipe_wm->sprites_enabled,
2320 .sprites_scaled = pipe_wm->sprites_scaled,
2321 };
2322 struct ilk_wm_maximums max;
2323
2324 /* LP0 watermarks always use 1/2 DDB partitioning */
2325 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2326
2327 /* At least LP0 must be valid */
2328 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2329 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2330 return false;
2331 }
2332
2333 return true;
2334}
2335
0b2ae6d7 2336/* Compute new watermarks for the pipe */
e3bddded 2337static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2338{
e3bddded
ML		 2339 struct drm_atomic_state *state = cstate->base.state;
2340 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2341 struct intel_pipe_wm *pipe_wm;
e3bddded 2342 struct drm_device *dev = state->dev;
fac5e23e 2343 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2344 struct intel_plane *intel_plane;
86c8bbbe 2345 struct intel_plane_state *pristate = NULL;
43d59eda 2346 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2347 struct intel_plane_state *curstate = NULL;
d81f04c5 2348 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2349 struct ilk_wm_maximums max;
0b2ae6d7 2350
e8f1f02e 2351 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2352
43d59eda 2353 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2354 struct intel_plane_state *ps;
2355
2356 ps = intel_atomic_get_existing_plane_state(state,
2357 intel_plane);
2358 if (!ps)
2359 continue;
86c8bbbe
MR		 2360
2361 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2362 pristate = ps;
86c8bbbe 2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2364 sprstate = ps;
86c8bbbe 2365 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2366 curstate = ps;
43d59eda
MR		 2367 }
2368
ed4a6a7c 2369 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2370 if (sprstate) {
936e71e3
VS		 2371 pipe_wm->sprites_enabled = sprstate->base.visible;
2372 pipe_wm->sprites_scaled = sprstate->base.visible &&
2373 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2374 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2375 }
2376
d81f04c5
ML		 2377 usable_level = max_level;
2378
7b39a0b7 2379 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2380 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2381 usable_level = 1;
7b39a0b7
VS		 2382
2383 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2384 if (pipe_wm->sprites_scaled)
d81f04c5 2385 usable_level = 0;
7b39a0b7 2386
86c8bbbe 2387 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2388 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2389
2390 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2391 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2392
a42a5719 2393 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2394 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2395
ed4a6a7c 2396 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2397 return -EINVAL;
a3cb4048
VS		 2398
2399 ilk_compute_wm_reg_maximums(dev, 1, &max);
2400
2401 for (level = 1; level <= max_level; level++) {
71f0a626 2402 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2403
86c8bbbe 2404 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2405 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2406
2407 /*
2408 * Disable any watermark level that exceeds the
2409 * register maximums since such watermarks are
2410 * always invalid.
2411 */
71f0a626
ML		 2412 if (level > usable_level)
2413 continue;
2414
2415 if (ilk_validate_wm_level(level, &max, wm))
2416 pipe_wm->wm[level] = *wm;
2417 else
d81f04c5 2418 usable_level = level;
a3cb4048
VS		 2419 }
2420
86c8bbbe 2421 return 0;
0b2ae6d7
VS		 2422}
2423
ed4a6a7c
MR		 2424/*
2425 * Build a set of 'intermediate' watermark values that satisfy both the old
2426 * state and the new state. These can be programmed to the hardware
2427 * immediately.
2428 */
2429static int ilk_compute_intermediate_wm(struct drm_device *dev,
2430 struct intel_crtc *intel_crtc,
2431 struct intel_crtc_state *newstate)
2432{
e8f1f02e 2433 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2434 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2435 int level, max_level = ilk_wm_max_level(dev);
2436
2437 /*
2438 * Start with the final, target watermarks, then combine with the
2439 * currently active watermarks to get values that are safe both before
2440 * and after the vblank.
2441 */
e8f1f02e 2442 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2443 a->pipe_enabled |= b->pipe_enabled;
2444 a->sprites_enabled |= b->sprites_enabled;
2445 a->sprites_scaled |= b->sprites_scaled;
2446
2447 for (level = 0; level <= max_level; level++) {
2448 struct intel_wm_level *a_wm = &a->wm[level];
2449 const struct intel_wm_level *b_wm = &b->wm[level];
2450
2451 a_wm->enable &= b_wm->enable;
2452 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2453 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2454 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2455 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2456 }
2457
2458 /*
2459 * We need to make sure that these merged watermark values are
2460 * actually a valid configuration themselves. If they're not,
2461 * there's no safe way to transition from the old state to
2462 * the new state, so we need to fail the atomic transaction.
2463 */
2464 if (!ilk_validate_pipe_wm(dev, a))
2465 return -EINVAL;
2466
2467 /*
2468 * If our intermediate WM are identical to the final WM, then we can
2469 * omit the post-vblank programming; only update if it's different.
2470 */
e8f1f02e 2471 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2472 newstate->wm.need_postvbl_update = false;
2473
2474 return 0;
2475}
2476
0b2ae6d7
VS		 2477/*
2478 * Merge the watermarks from all active pipes for a specific level.
2479 */
2480static void ilk_merge_wm_level(struct drm_device *dev,
2481 int level,
2482 struct intel_wm_level *ret_wm)
2483{
2484 const struct intel_crtc *intel_crtc;
2485
d52fea5b
VS		 2486 ret_wm->enable = true;
2487
d3fcc808 2488 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2489 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2490 const struct intel_wm_level *wm = &active->wm[level];
2491
2492 if (!active->pipe_enabled)
2493 continue;
0b2ae6d7 2494
d52fea5b
VS		 2495 /*
2496 * The watermark values may have been used in the past,
2497 * so we must maintain them in the registers for some
2498 * time even if the level is now disabled.
2499 */
0b2ae6d7 2500 if (!wm->enable)
d52fea5b 2501 ret_wm->enable = false;
0b2ae6d7
VS		 2502
2503 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2504 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2505 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2506 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2507 }
0b2ae6d7
VS		 2508}
2509
2510/*
2511 * Merge all low power watermarks for all active pipes.
2512 */
2513static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2514 const struct intel_wm_config *config,
820c1980 2515 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2516 struct intel_pipe_wm *merged)
2517{
fac5e23e 2518 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2519 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2520 int last_enabled_level = max_level;
0b2ae6d7 2521
0ba22e26
VS		 2522 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2523 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2524 config->num_pipes_active > 1)
1204d5ba 2525 last_enabled_level = 0;
0ba22e26 2526
6c8b6c28
VS		 2527 /* ILK: FBC WM must be disabled always */
2528 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2529
2530 /* merge each WM1+ level */
2531 for (level = 1; level <= max_level; level++) {
2532 struct intel_wm_level *wm = &merged->wm[level];
2533
2534 ilk_merge_wm_level(dev, level, wm);
2535
d52fea5b
VS		 2536 if (level > last_enabled_level)
2537 wm->enable = false;
2538 else if (!ilk_validate_wm_level(level, max, wm))
2539 /* make sure all following levels get disabled */
2540 last_enabled_level = level - 1;
0b2ae6d7
VS		 2541
2542 /*
2543 * The spec says it is preferred to disable
2544 * FBC WMs instead of disabling a WM level.
2545 */
2546 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2547 if (wm->enable)
2548 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2549 wm->fbc_val = 0;
2550 }
2551 }
6c8b6c28
VS		 2552
2553 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2554 /*
2555 * FIXME this is racy. FBC might get enabled later.
2556 * What we should check here is whether FBC can be
2557 * enabled sometime later.
2558 */
7733b49b 2559 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2560 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2561 for (level = 2; level <= max_level; level++) {
2562 struct intel_wm_level *wm = &merged->wm[level];
2563
2564 wm->enable = false;
2565 }
2566 }
0b2ae6d7
VS		 2567}
2568
b380ca3c
VS		 2569static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2570{
2571 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2572 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2573}
2574
a68d68ee
VS		 2575/* The value we need to program into the WM_LPx latency field */
2576static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2577{
fac5e23e 2578 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2579
a42a5719 2580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2581 return 2 * level;
2582 else
2583 return dev_priv->wm.pri_latency[level];
2584}
2585
820c1980 2586static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2587 const struct intel_pipe_wm *merged,
609cedef 2588 enum intel_ddb_partitioning partitioning,
820c1980 2589 struct ilk_wm_values *results)
801bcfff 2590{
0b2ae6d7
VS		 2591 struct intel_crtc *intel_crtc;
2592 int level, wm_lp;
cca32e9a 2593
0362c781 2594 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2595 results->partitioning = partitioning;
cca32e9a 2596
0b2ae6d7 2597 /* LP1+ register values */
cca32e9a 2598 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2599 const struct intel_wm_level *r;
801bcfff 2600
b380ca3c 2601 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2602
0362c781 2603 r = &merged->wm[level];
cca32e9a 2604
d52fea5b
VS		 2605 /*
2606 * Maintain the watermark values even if the level is
2607 * disabled. Doing otherwise could cause underruns.
2608 */
2609 results->wm_lp[wm_lp - 1] =
a68d68ee 2610 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2611 (r->pri_val << WM1_LP_SR_SHIFT) |
2612 r->cur_val;
2613
d52fea5b
VS		 2614 if (r->enable)
2615 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2616
416f4727
VS		 2617 if (INTEL_INFO(dev)->gen >= 8)
2618 results->wm_lp[wm_lp - 1] |=
2619 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2620 else
2621 results->wm_lp[wm_lp - 1] |=
2622 r->fbc_val << WM1_LP_FBC_SHIFT;
2623
d52fea5b
VS		 2624 /*
2625 * Always set WM1S_LP_EN when spr_val != 0, even if the
2626 * level is disabled. Doing otherwise could cause underruns.
2627 */
6cef2b8a
VS		 2628 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2629 WARN_ON(wm_lp != 1);
2630 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2631 } else
2632 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2633 }
801bcfff 2634
0b2ae6d7 2635 /* LP0 register values */
d3fcc808 2636 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2637 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2638 const struct intel_wm_level *r =
2639 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2640
2641 if (WARN_ON(!r->enable))
2642 continue;
2643
ed4a6a7c 2644 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2645
0b2ae6d7
VS		 2646 results->wm_pipe[pipe] =
2647 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2648 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2649 r->cur_val;
801bcfff
PZ		 2650 }
2651}
2652
861f3389
PZ		 2653/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2654 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2655static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2656 struct intel_pipe_wm *r1,
2657 struct intel_pipe_wm *r2)
861f3389 2658{
198a1e9b
VS		 2659 int level, max_level = ilk_wm_max_level(dev);
2660 int level1 = 0, level2 = 0;
861f3389 2661
198a1e9b
VS		 2662 for (level = 1; level <= max_level; level++) {
2663 if (r1->wm[level].enable)
2664 level1 = level;
2665 if (r2->wm[level].enable)
2666 level2 = level;
861f3389
PZ		 2667 }
2668
198a1e9b
VS		 2669 if (level1 == level2) {
2670 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2671 return r2;
2672 else
2673 return r1;
198a1e9b 2674 } else if (level1 > level2) {
861f3389
PZ		 2675 return r1;
2676 } else {
2677 return r2;
2678 }
2679}
2680
49a687c4
VS		 2681/* dirty bits used to track which watermarks need changes */
2682#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2683#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2684#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2685#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2686#define WM_DIRTY_FBC (1 << 24)
2687#define WM_DIRTY_DDB (1 << 25)
2688
055e393f 2689static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2690 const struct ilk_wm_values *old,
2691 const struct ilk_wm_values *new)
49a687c4
VS		 2692{
2693 unsigned int dirty = 0;
2694 enum pipe pipe;
2695 int wm_lp;
2696
055e393f 2697 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2698 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2699 dirty |= WM_DIRTY_LINETIME(pipe);
2700 /* Must disable LP1+ watermarks too */
2701 dirty |= WM_DIRTY_LP_ALL;
2702 }
2703
2704 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2705 dirty |= WM_DIRTY_PIPE(pipe);
2706 /* Must disable LP1+ watermarks too */
2707 dirty |= WM_DIRTY_LP_ALL;
2708 }
2709 }
2710
2711 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2712 dirty |= WM_DIRTY_FBC;
2713 /* Must disable LP1+ watermarks too */
2714 dirty |= WM_DIRTY_LP_ALL;
2715 }
2716
2717 if (old->partitioning != new->partitioning) {
2718 dirty |= WM_DIRTY_DDB;
2719 /* Must disable LP1+ watermarks too */
2720 dirty |= WM_DIRTY_LP_ALL;
2721 }
2722
2723 /* LP1+ watermarks already deemed dirty, no need to continue */
2724 if (dirty & WM_DIRTY_LP_ALL)
2725 return dirty;
2726
2727 /* Find the lowest numbered LP1+ watermark in need of an update... */
2728 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2729 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2730 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2731 break;
2732 }
2733
2734 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2735 for (; wm_lp <= 3; wm_lp++)
2736 dirty |= WM_DIRTY_LP(wm_lp);
2737
2738 return dirty;
2739}
2740
8553c18e
VS		 2741static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2742 unsigned int dirty)
801bcfff 2743{
820c1980 2744 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2745 bool changed = false;
801bcfff 2746
facd619b
VS		 2747 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2748 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2749 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2750 changed = true;
facd619b
VS		 2751 }
2752 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2753 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2754 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2755 changed = true;
facd619b
VS		 2756 }
2757 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2758 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2760 changed = true;
facd619b 2761 }
801bcfff 2762
facd619b
VS		 2763 /*
2764 * Don't touch WM1S_LP_EN here.
2765 * Doing so could cause underruns.
2766 */
6cef2b8a 2767
8553c18e
VS		 2768 return changed;
2769}
2770
2771/*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
820c1980
ID		 2775static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2776 struct ilk_wm_values *results)
8553c18e 2777{
91c8a326 2778 struct drm_device *dev = &dev_priv->drm;
820c1980 2779 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2780 unsigned int dirty;
2781 uint32_t val;
2782
055e393f 2783 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2784 if (!dirty)
2785 return;
2786
2787 _ilk_disable_lp_wm(dev_priv, dirty);
2788
49a687c4 2789 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2790 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2791 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2792 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2793 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2794 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2795
49a687c4 2796 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2798 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2800 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2801 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2802
49a687c4 2803 if (dirty & WM_DIRTY_DDB) {
a42a5719 2804 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2805 val = I915_READ(WM_MISC);
2806 if (results->partitioning == INTEL_DDB_PART_1_2)
2807 val &= ~WM_MISC_DATA_PARTITION_5_6;
2808 else
2809 val |= WM_MISC_DATA_PARTITION_5_6;
2810 I915_WRITE(WM_MISC, val);
2811 } else {
2812 val = I915_READ(DISP_ARB_CTL2);
2813 if (results->partitioning == INTEL_DDB_PART_1_2)
2814 val &= ~DISP_DATA_PARTITION_5_6;
2815 else
2816 val |= DISP_DATA_PARTITION_5_6;
2817 I915_WRITE(DISP_ARB_CTL2, val);
2818 }
1011d8c4
PZ		 2819 }
2820
49a687c4 2821 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2822 val = I915_READ(DISP_ARB_CTL);
2823 if (results->enable_fbc_wm)
2824 val &= ~DISP_FBC_WM_DIS;
2825 else
2826 val |= DISP_FBC_WM_DIS;
2827 I915_WRITE(DISP_ARB_CTL, val);
2828 }
2829
954911eb
ID		 2830 if (dirty & WM_DIRTY_LP(1) &&
2831 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2832 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2833
2834 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2835 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2836 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2837 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2838 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2839 }
801bcfff 2840
facd619b 2841 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2842 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2843 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2844 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2845 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2846 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2847
2848 dev_priv->wm.hw = *results;
801bcfff
PZ		 2849}
2850
ed4a6a7c 2851bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2852{
fac5e23e 2853 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2854
2855 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2856}
2857
656d1b89 2858#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2859
024c9045
MR		 2860/*
2861 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2862 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2863 * other universal planes are in indices 1..n. Note that this may leave unused
2864 * indices between the top "sprite" plane and the cursor.
2865 */
2866static int
2867skl_wm_plane_id(const struct intel_plane *plane)
2868{
2869 switch (plane->base.type) {
2870 case DRM_PLANE_TYPE_PRIMARY:
2871 return 0;
2872 case DRM_PLANE_TYPE_CURSOR:
2873 return PLANE_CURSOR;
2874 case DRM_PLANE_TYPE_OVERLAY:
2875 return plane->plane + 1;
2876 default:
2877 MISSING_CASE(plane->base.type);
2878 return plane->plane;
2879 }
2880}
2881
6e7fdb87
PZ		 2882static bool
2883intel_has_sagv(struct drm_i915_private *dev_priv)
2884{
17777d61
PZ		 2885 if (IS_KABYLAKE(dev_priv))
2886 return true;
2887
2888 if (IS_SKYLAKE(dev_priv) &&
2889 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2890 return true;
2891
2892 return false;
6e7fdb87
PZ		 2893}
2894
656d1b89
L		 2895/*
2896 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2897 * depending on power and performance requirements. The display engine access
2898 * to system memory is blocked during the adjustment time. Because of the
2899 * blocking time, having this enabled can cause full system hangs and/or pipe
2900 * underruns if we don't meet all of the following requirements:
2901 *
2902 * - <= 1 pipe enabled
2903 * - All planes can enable watermarks for latencies >= SAGV engine block time
2904 * - We're not using an interlaced display configuration
2905 */
2906int
674f823b 2907intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2908{
2909 int ret;
2910
6e7fdb87
PZ		 2911 if (!intel_has_sagv(dev_priv))
2912 return 0;
2913
2914 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2915 return 0;
2916
2917 DRM_DEBUG_KMS("Enabling the SAGV\n");
2918 mutex_lock(&dev_priv->rps.hw_lock);
2919
2920 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2921 GEN9_SAGV_ENABLE);
2922
2923 /* We don't need to wait for the SAGV when enabling */
2924 mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926 /*
2927 * Some skl systems, pre-release machines in particular,
2928 * don't actually have an SAGV.
2929 */
17777d61 2930 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2931 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
674f823b 2932 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2933 return 0;
2934 } else if (ret < 0) {
2935 DRM_ERROR("Failed to enable the SAGV\n");
2936 return ret;
2937 }
2938
674f823b 2939 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2940 return 0;
2941}
2942
2943static int
674f823b 2944intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2945{
2946 int ret;
2947 uint32_t temp = GEN9_SAGV_DISABLE;
2948
2949 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2950 &temp);
2951 if (ret)
2952 return ret;
2953 else
2954 return temp & GEN9_SAGV_IS_DISABLED;
2955}
2956
2957int
674f823b 2958intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2959{
2960 int ret, result;
2961
6e7fdb87
PZ		 2962 if (!intel_has_sagv(dev_priv))
2963 return 0;
2964
2965 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2966 return 0;
2967
2968 DRM_DEBUG_KMS("Disabling the SAGV\n");
2969 mutex_lock(&dev_priv->rps.hw_lock);
2970
2971 /* bspec says to keep retrying for at least 1 ms */
674f823b 2972 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2973 mutex_unlock(&dev_priv->rps.hw_lock);
2974
2975 if (ret == -ETIMEDOUT) {
2976 DRM_ERROR("Request to disable SAGV timed out\n");
2977 return -ETIMEDOUT;
2978 }
2979
2980 /*
2981 * Some skl systems, pre-release machines in particular,
2982 * don't actually have an SAGV.
2983 */
17777d61 2984 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 2985 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
674f823b 2986 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2987 return 0;
2988 } else if (result < 0) {
2989 DRM_ERROR("Failed to disable the SAGV\n");
2990 return result;
2991 }
2992
674f823b 2993 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 2994 return 0;
2995}
2996
674f823b 2997bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 2998{
2999 struct drm_device *dev = state->dev;
3000 struct drm_i915_private *dev_priv = to_i915(dev);
3001 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3002 struct drm_crtc *crtc;
3003 enum pipe pipe;
3004 int level, plane;
3005
6e7fdb87
PZ		 3006 if (!intel_has_sagv(dev_priv))
3007 return false;
3008
656d1b89
L		 3009 /*
3010 * SKL workaround: bspec recommends we disable the SAGV when we have
3011 * more then one pipe enabled
3012 *
3013 * If there are no active CRTCs, no additional checks need be performed
3014 */
3015 if (hweight32(intel_state->active_crtcs) == 0)
3016 return true;
3017 else if (hweight32(intel_state->active_crtcs) > 1)
3018 return false;
3019
3020 /* Since we're now guaranteed to only have one active CRTC... */
3021 pipe = ffs(intel_state->active_crtcs) - 1;
3022 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3023
3024 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3025 return false;
3026
3027 for_each_plane(dev_priv, pipe, plane) {
3028 /* Skip this plane if it's not enabled */
3029 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3030 continue;
3031
3032 /* Find the highest enabled wm level for this plane */
3033 for (level = ilk_wm_max_level(dev);
3034 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3035 { }
3036
3037 /*
3038 * If any of the planes on this pipe don't enable wm levels
3039 * that incur memory latencies higher then 30µs we can't enable
3040 * the SAGV
3041 */
3042 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3043 return false;
3044 }
3045
3046 return true;
3047}
3048
b9cec075
DL		 3049static void
3050skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3051 const struct intel_crtc_state *cstate,
c107acfe
MR		 3052 struct skl_ddb_entry *alloc, /* out */
3053 int *num_active /* out */)
b9cec075 3054{
c107acfe
MR		 3055 struct drm_atomic_state *state = cstate->base.state;
3056 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3057 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3058 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3059 unsigned int pipe_size, ddb_size;
3060 int nth_active_pipe;
c107acfe
MR		 3061 int pipe = to_intel_crtc(for_crtc)->pipe;
3062
a6d3460e 3063 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3064 alloc->start = 0;
3065 alloc->end = 0;
a6d3460e 3066 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3067 return;
3068 }
3069
a6d3460e
MR		 3070 if (intel_state->active_pipe_changes)
3071 *num_active = hweight32(intel_state->active_crtcs);
3072 else
3073 *num_active = hweight32(dev_priv->active_crtcs);
3074
6f3fff60
D		 3075 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3076 WARN_ON(ddb_size == 0);
b9cec075
DL		 3077
3078 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3079
c107acfe 3080 /*
a6d3460e
MR		 3081 * If the state doesn't change the active CRTC's, then there's
3082 * no need to recalculate; the existing pipe allocation limits
3083 * should remain unchanged. Note that we're safe from racing
3084 * commits since any racing commit that changes the active CRTC
3085 * list would need to grab _all_ crtc locks, including the one
3086 * we currently hold.
c107acfe 3087 */
a6d3460e
MR		 3088 if (!intel_state->active_pipe_changes) {
3089 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3090 return;
c107acfe 3091 }
a6d3460e
MR		 3092
3093 nth_active_pipe = hweight32(intel_state->active_crtcs &
3094 (drm_crtc_mask(for_crtc) - 1));
3095 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3096 alloc->start = nth_active_pipe * ddb_size / *num_active;
3097 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3098}
3099
c107acfe 3100static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3101{
c107acfe 3102 if (num_active == 1)
b9cec075
DL		 3103 return 32;
3104
3105 return 8;
3106}
3107
a269c583
DL		 3108static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3109{
3110 entry->start = reg & 0x3ff;
3111 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3112 if (entry->end)
3113 entry->end += 1;
a269c583
DL		 3114}
3115
08db6652
DL		 3116void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3117 struct skl_ddb_allocation *ddb /* out */)
a269c583 3118{
a269c583
DL		 3119 enum pipe pipe;
3120 int plane;
3121 u32 val;
3122
b10f1b20
ML		 3123 memset(ddb, 0, sizeof(*ddb));
3124
a269c583 3125 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3126 enum intel_display_power_domain power_domain;
3127
3128 power_domain = POWER_DOMAIN_PIPE(pipe);
3129 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3130 continue;
3131
dd740780 3132 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3133 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3134 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3135 val);
3136 }
3137
3138 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3139 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3140 val);
4d800030
ID		 3141
3142 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3143 }
3144}
3145
9c2f7a9d
KM		 3146/*
3147 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3148 * The bspec defines downscale amount as:
3149 *
3150 * """
3151 * Horizontal down scale amount = maximum[1, Horizontal source size /
3152 * Horizontal destination size]
3153 * Vertical down scale amount = maximum[1, Vertical source size /
3154 * Vertical destination size]
3155 * Total down scale amount = Horizontal down scale amount *
3156 * Vertical down scale amount
3157 * """
3158 *
3159 * Return value is provided in 16.16 fixed point form to retain fractional part.
3160 * Caller should take care of dividing & rounding off the value.
3161 */
3162static uint32_t
3163skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3164{
3165 uint32_t downscale_h, downscale_w;
3166 uint32_t src_w, src_h, dst_w, dst_h;
3167
936e71e3 3168 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3169 return DRM_PLANE_HELPER_NO_SCALING;
3170
3171 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3172 src_w = drm_rect_width(&pstate->base.src);
3173 src_h = drm_rect_height(&pstate->base.src);
3174 dst_w = drm_rect_width(&pstate->base.dst);
3175 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3176 if (intel_rotation_90_or_270(pstate->base.rotation))
3177 swap(dst_w, dst_h);
3178
3179 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3180 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3181
3182 /* Provide result in 16.16 fixed point */
3183 return (uint64_t)downscale_w * downscale_h >> 16;
3184}
3185
b9cec075 3186static unsigned int
024c9045
MR		 3187skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3188 const struct drm_plane_state *pstate,
3189 int y)
b9cec075 3190{
a280f7dd 3191 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3192 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3193 uint32_t down_scale_amount, data_rate;
a280f7dd 3194 uint32_t width = 0, height = 0;
a1de91e5
MR		 3195 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3196
936e71e3 3197 if (!intel_pstate->base.visible)
a1de91e5
MR		 3198 return 0;
3199 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3200 return 0;
3201 if (y && format != DRM_FORMAT_NV12)
3202 return 0;
a280f7dd 3203
936e71e3
VS		 3204 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3205 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3206
3207 if (intel_rotation_90_or_270(pstate->rotation))
3208 swap(width, height);
2cd601c6
CK		 3209
3210 /* for planar format */
a1de91e5 3211 if (format == DRM_FORMAT_NV12) {
2cd601c6 3212 if (y) /* y-plane data rate */
8d19d7d9 3213 data_rate = width * height *
a1de91e5 3214 drm_format_plane_cpp(format, 0);
2cd601c6 3215 else /* uv-plane data rate */
8d19d7d9 3216 data_rate = (width / 2) * (height / 2) *
a1de91e5 3217 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3218 } else {
3219 /* for packed formats */
3220 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3221 }
3222
8d19d7d9
KM		 3223 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3224
3225 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3226}
3227
3228/*
3229 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3230 * a 8192x4096@32bpp framebuffer:
3231 * 3 * 4096 * 8192 * 4 < 2^32
3232 */
3233static unsigned int
9c74d826 3234skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3235{
9c74d826
MR		 3236 struct drm_crtc_state *cstate = &intel_cstate->base;
3237 struct drm_atomic_state *state = cstate->state;
3238 struct drm_crtc *crtc = cstate->crtc;
3239 struct drm_device *dev = crtc->dev;
3240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3241 const struct drm_plane *plane;
024c9045 3242 const struct intel_plane *intel_plane;
a6d3460e 3243 struct drm_plane_state *pstate;
a1de91e5 3244 unsigned int rate, total_data_rate = 0;
9c74d826 3245 int id;
a6d3460e
MR		 3246 int i;
3247
3248 if (WARN_ON(!state))
3249 return 0;
b9cec075 3250
a1de91e5 3251 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3252 for_each_plane_in_state(state, plane, pstate, i) {
3253 id = skl_wm_plane_id(to_intel_plane(plane));
3254 intel_plane = to_intel_plane(plane);
3255
3256 if (intel_plane->pipe != intel_crtc->pipe)
3257 continue;
3258
3259 /* packed/uv */
3260 rate = skl_plane_relative_data_rate(intel_cstate,
3261 pstate, 0);
3262 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3263
3264 /* y-plane */
3265 rate = skl_plane_relative_data_rate(intel_cstate,
3266 pstate, 1);
3267 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3268 }
024c9045 3269
a1de91e5
MR		 3270 /* Calculate CRTC's total data rate from cached values */
3271 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3272 int id = skl_wm_plane_id(intel_plane);
024c9045 3273
a1de91e5 3274 /* packed/uv */
9c74d826
MR		 3275 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3276 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3277 }
3278
3279 return total_data_rate;
3280}
3281
cbcfd14b
KM		 3282static uint16_t
3283skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3284 const int y)
3285{
3286 struct drm_framebuffer *fb = pstate->fb;
3287 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3288 uint32_t src_w, src_h;
3289 uint32_t min_scanlines = 8;
3290 uint8_t plane_bpp;
3291
3292 if (WARN_ON(!fb))
3293 return 0;
3294
3295 /* For packed formats, no y-plane, return 0 */
3296 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3297 return 0;
3298
3299 /* For Non Y-tile return 8-blocks */
3300 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3301 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3302 return 8;
3303
936e71e3
VS		 3304 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3305 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3306
3307 if (intel_rotation_90_or_270(pstate->rotation))
3308 swap(src_w, src_h);
3309
3310 /* Halve UV plane width and height for NV12 */
3311 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3312 src_w /= 2;
3313 src_h /= 2;
3314 }
3315
3316 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3317 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3318 else
3319 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3320
3321 if (intel_rotation_90_or_270(pstate->rotation)) {
3322 switch (plane_bpp) {
3323 case 1:
3324 min_scanlines = 32;
3325 break;
3326 case 2:
3327 min_scanlines = 16;
3328 break;
3329 case 4:
3330 min_scanlines = 8;
3331 break;
3332 case 8:
3333 min_scanlines = 4;
3334 break;
3335 default:
3336 WARN(1, "Unsupported pixel depth %u for rotation",
3337 plane_bpp);
3338 min_scanlines = 32;
3339 }
3340 }
3341
3342 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3343}
3344
c107acfe 3345static int
024c9045 3346skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3347 struct skl_ddb_allocation *ddb /* out */)
3348{
c107acfe 3349 struct drm_atomic_state *state = cstate->base.state;
024c9045 3350 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3351 struct drm_device *dev = crtc->dev;
3352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3353 struct intel_plane *intel_plane;
c107acfe
MR		 3354 struct drm_plane *plane;
3355 struct drm_plane_state *pstate;
b9cec075 3356 enum pipe pipe = intel_crtc->pipe;
34bb56af 3357 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3358 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3359 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3360 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3361 unsigned int total_data_rate;
c107acfe
MR		 3362 int num_active;
3363 int id, i;
b9cec075 3364
a6d3460e
MR		 3365 if (WARN_ON(!state))
3366 return 0;
3367
c107acfe
MR		 3368 if (!cstate->base.active) {
3369 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3370 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3371 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3372 return 0;
3373 }
3374
a6d3460e 3375 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3376 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3377 if (alloc_size == 0) {
3378 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3379 return 0;
b9cec075
DL		 3380 }
3381
c107acfe 3382 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3383 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3384 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3385
3386 alloc_size -= cursor_blocks;
b9cec075 3387
80958155 3388 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3389 for_each_plane_in_state(state, plane, pstate, i) {
3390 intel_plane = to_intel_plane(plane);
3391 id = skl_wm_plane_id(intel_plane);
c107acfe 3392
a6d3460e
MR		 3393 if (intel_plane->pipe != pipe)
3394 continue;
c107acfe 3395
936e71e3 3396 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3397 minimum[id] = 0;
3398 y_minimum[id] = 0;
3399 continue;
3400 }
3401 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3402 minimum[id] = 0;
3403 y_minimum[id] = 0;
3404 continue;
c107acfe 3405 }
a6d3460e 3406
cbcfd14b
KM		 3407 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3408 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3409 }
80958155 3410
c107acfe
MR		 3411 for (i = 0; i < PLANE_CURSOR; i++) {
3412 alloc_size -= minimum[i];
3413 alloc_size -= y_minimum[i];
80958155
DL		 3414 }
3415
b9cec075 3416 /*
80958155
DL		 3417 * 2. Distribute the remaining space in proportion to the amount of
3418 * data each plane needs to fetch from memory.
b9cec075
DL		 3419 *
3420 * FIXME: we may not allocate every single block here.
3421 */
024c9045 3422 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3423 if (total_data_rate == 0)
c107acfe 3424 return 0;
b9cec075 3425
34bb56af 3426 start = alloc->start;
024c9045 3427 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3428 unsigned int data_rate, y_data_rate;
3429 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3430 int id = skl_wm_plane_id(intel_plane);
b9cec075 3431
a1de91e5 3432 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3433
3434 /*
2cd601c6 3435 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3436 * promote the expression to 64 bits to avoid overflowing, the
3437 * result is < available as data_rate / total_data_rate < 1
3438 */
024c9045 3439 plane_blocks = minimum[id];
80958155
DL		 3440 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3441 total_data_rate);
b9cec075 3442
c107acfe
MR		 3443 /* Leave disabled planes at (0,0) */
3444 if (data_rate) {
3445 ddb->plane[pipe][id].start = start;
3446 ddb->plane[pipe][id].end = start + plane_blocks;
3447 }
b9cec075
DL		 3448
3449 start += plane_blocks;
2cd601c6
CK		 3450
3451 /*
3452 * allocation for y_plane part of planar format:
3453 */
a1de91e5
MR		 3454 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3455
3456 y_plane_blocks = y_minimum[id];
3457 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3458 total_data_rate);
2cd601c6 3459
c107acfe
MR		 3460 if (y_data_rate) {
3461 ddb->y_plane[pipe][id].start = start;
3462 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3463 }
a1de91e5
MR		 3464
3465 start += y_plane_blocks;
b9cec075
DL		 3466 }
3467
c107acfe 3468 return 0;
b9cec075
DL		 3469}
3470
5cec258b 3471static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3472{
3473 /* TODO: Take into account the scalers once we support them */
2d112de7 3474 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3475}
3476
3477/*
3478 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3479 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3480 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3481 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3482*/
ac484963 3483static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3484{
3485 uint32_t wm_intermediate_val, ret;
3486
3487 if (latency == 0)
3488 return UINT_MAX;
3489
ac484963 3490 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3491 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3492
3493 return ret;
3494}
3495
3496static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3497 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3498 uint64_t tiling, uint32_t latency)
2d41c0b5 3499{
d4c2aa60
TU		 3500 uint32_t ret;
3501 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3502 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3503
3504 if (latency == 0)
3505 return UINT_MAX;
3506
ac484963 3507 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3508
3509 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3510 tiling == I915_FORMAT_MOD_Yf_TILED) {
3511 plane_bytes_per_line *= 4;
3512 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3513 plane_blocks_per_line /= 4;
055c3ff6
MR		 3514 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3515 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
0fda6568
TU		 3516 } else {
3517 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3518 }
3519
2d41c0b5
PB		 3520 wm_intermediate_val = latency * pixel_rate;
3521 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3522 plane_blocks_per_line;
2d41c0b5
PB		 3523
3524 return ret;
3525}
3526
9c2f7a9d
KM		 3527static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3528 struct intel_plane_state *pstate)
3529{
3530 uint64_t adjusted_pixel_rate;
3531 uint64_t downscale_amount;
3532 uint64_t pixel_rate;
3533
3534 /* Shouldn't reach here on disabled planes... */
936e71e3 3535 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3536 return 0;
3537
3538 /*
3539 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3540 * with additional adjustments for plane-specific scaling.
3541 */
3542 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3543 downscale_amount = skl_plane_downscale_amount(pstate);
3544
3545 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3546 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3547
3548 return pixel_rate;
3549}
3550
55994c2c
MR		 3551static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3552 struct intel_crtc_state *cstate,
3553 struct intel_plane_state *intel_pstate,
3554 uint16_t ddb_allocation,
3555 int level,
3556 uint16_t *out_blocks, /* out */
3557 uint8_t *out_lines, /* out */
3558 bool *enabled /* out */)
2d41c0b5 3559{
33815fa5
MR		 3560 struct drm_plane_state *pstate = &intel_pstate->base;
3561 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3562 uint32_t latency = dev_priv->wm.skl_latency[level];
3563 uint32_t method1, method2;
3564 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3565 uint32_t res_blocks, res_lines;
3566 uint32_t selected_result;
ac484963 3567 uint8_t cpp;
a280f7dd 3568 uint32_t width = 0, height = 0;
9c2f7a9d 3569 uint32_t plane_pixel_rate;
2d41c0b5 3570
936e71e3 3571 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3572 *enabled = false;
3573 return 0;
3574 }
2d41c0b5 3575
936e71e3
VS		 3576 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3577 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3578
33815fa5 3579 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3580 swap(width, height);
3581
ac484963 3582 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3583 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3584
3585 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3586 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3587 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3588 width,
3589 cpp,
3590 fb->modifier[0],
d4c2aa60 3591 latency);
2d41c0b5 3592
a280f7dd 3593 plane_bytes_per_line = width * cpp;
d4c2aa60 3594 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3595
024c9045
MR		 3596 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3597 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3598 uint32_t min_scanlines = 4;
3599 uint32_t y_tile_minimum;
33815fa5 3600 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3601 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3602 drm_format_plane_cpp(fb->pixel_format, 1) :
3603 drm_format_plane_cpp(fb->pixel_format, 0);
3604
ac484963 3605 switch (cpp) {
1fc0a8f7
TU		 3606 case 1:
3607 min_scanlines = 16;
3608 break;
3609 case 2:
3610 min_scanlines = 8;
3611 break;
3612 case 8:
3613 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3614 }
1fc0a8f7
TU		 3615 }
3616 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3617 selected_result = max(method2, y_tile_minimum);
3618 } else {
3619 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3620 selected_result = min(method1, method2);
3621 else
3622 selected_result = method1;
3623 }
2d41c0b5 3624
d4c2aa60
TU		 3625 res_blocks = selected_result + 1;
3626 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3627
0fda6568 3628 if (level >= 1 && level <= 7) {
024c9045
MR		 3629 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3630 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3631 res_lines += 4;
3632 else
3633 res_blocks++;
3634 }
e6d66171 3635
55994c2c
MR		 3636 if (res_blocks >= ddb_allocation || res_lines > 31) {
3637 *enabled = false;
6b6bada7
MR		 3638
3639 /*
3640 * If there are no valid level 0 watermarks, then we can't
3641 * support this display configuration.
3642 */
3643 if (level) {
3644 return 0;
3645 } else {
3646 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3647 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3648 to_intel_crtc(cstate->base.crtc)->pipe,
3649 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3650 res_blocks, ddb_allocation, res_lines);
3651
3652 return -EINVAL;
3653 }
55994c2c 3654 }
e6d66171
DL		 3655
3656 *out_blocks = res_blocks;
3657 *out_lines = res_lines;
55994c2c 3658 *enabled = true;
2d41c0b5 3659
55994c2c 3660 return 0;
2d41c0b5
PB		 3661}
3662
f4a96752
MR		 3663static int
3664skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3665 struct skl_ddb_allocation *ddb,
3666 struct intel_crtc_state *cstate,
3667 int level,
3668 struct skl_wm_level *result)
2d41c0b5 3669{
f4a96752 3670 struct drm_atomic_state *state = cstate->base.state;
024c9045 3671 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3672 struct drm_plane *plane;
024c9045 3673 struct intel_plane *intel_plane;
33815fa5 3674 struct intel_plane_state *intel_pstate;
2d41c0b5 3675 uint16_t ddb_blocks;
024c9045 3676 enum pipe pipe = intel_crtc->pipe;
55994c2c 3677 int ret;
024c9045 3678
f4a96752
MR		 3679 /*
3680 * We'll only calculate watermarks for planes that are actually
3681 * enabled, so make sure all other planes are set as disabled.
3682 */
3683 memset(result, 0, sizeof(*result));
3684
91c8a326
CW		 3685 for_each_intel_plane_mask(&dev_priv->drm,
3686 intel_plane,
3687 cstate->base.plane_mask) {
024c9045 3688 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3689
f4a96752
MR		 3690 plane = &intel_plane->base;
3691 intel_pstate = NULL;
3692 if (state)
3693 intel_pstate =
3694 intel_atomic_get_existing_plane_state(state,
3695 intel_plane);
3696
3697 /*
3698 * Note: If we start supporting multiple pending atomic commits
3699 * against the same planes/CRTC's in the future, plane->state
3700 * will no longer be the correct pre-state to use for the
3701 * calculations here and we'll need to change where we get the
3702 * 'unchanged' plane data from.
3703 *
3704 * For now this is fine because we only allow one queued commit
3705 * against a CRTC. Even if the plane isn't modified by this
3706 * transaction and we don't have a plane lock, we still have
3707 * the CRTC's lock, so we know that no other transactions are
3708 * racing with us to update it.
3709 */
3710 if (!intel_pstate)
3711 intel_pstate = to_intel_plane_state(plane->state);
3712
3713 WARN_ON(!intel_pstate->base.fb);
3714
2d41c0b5
PB		 3715 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3716
55994c2c
MR		 3717 ret = skl_compute_plane_wm(dev_priv,
3718 cstate,
3719 intel_pstate,
3720 ddb_blocks,
3721 level,
3722 &result->plane_res_b[i],
3723 &result->plane_res_l[i],
3724 &result->plane_en[i]);
3725 if (ret)
3726 return ret;
2d41c0b5 3727 }
f4a96752
MR		 3728
3729 return 0;
2d41c0b5
PB		 3730}
3731
407b50f3 3732static uint32_t
024c9045 3733skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3734{
024c9045 3735 if (!cstate->base.active)
407b50f3
DL		 3736 return 0;
3737
024c9045 3738 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3739 return 0;
407b50f3 3740
024c9045
MR		 3741 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3742 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3743}
3744
024c9045 3745static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3746 struct skl_wm_level *trans_wm /* out */)
407b50f3 3747{
024c9045 3748 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3750 struct intel_plane *intel_plane;
9414f563 3751
024c9045 3752 if (!cstate->base.active)
407b50f3 3753 return;
9414f563
DL		 3754
3755 /* Until we know more, just disable transition WMs */
024c9045
MR		 3756 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3757 int i = skl_wm_plane_id(intel_plane);
3758
9414f563 3759 trans_wm->plane_en[i] = false;
024c9045 3760 }
407b50f3
DL		 3761}
3762
55994c2c
MR		 3763static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3764 struct skl_ddb_allocation *ddb,
3765 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3766{
024c9045 3767 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3768 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3769 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3770 int ret;
2d41c0b5
PB		 3771
3772 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3773 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3774 level, &pipe_wm->wm[level]);
3775 if (ret)
3776 return ret;
2d41c0b5 3777 }
024c9045 3778 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3779
024c9045 3780 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3781
3782 return 0;
2d41c0b5
PB		 3783}
3784
3785static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3786 struct skl_pipe_wm *p_wm,
3787 struct skl_wm_values *r,
3788 struct intel_crtc *intel_crtc)
3789{
3790 int level, max_level = ilk_wm_max_level(dev);
3791 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3792 uint32_t temp;
3793 int i;
2d41c0b5
PB		 3794
3795 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3796 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3797 temp = 0;
2d41c0b5
PB		 3798
3799 temp |= p_wm->wm[level].plane_res_l[i] <<
3800 PLANE_WM_LINES_SHIFT;
3801 temp |= p_wm->wm[level].plane_res_b[i];
3802 if (p_wm->wm[level].plane_en[i])
3803 temp |= PLANE_WM_EN;
3804
3805 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3806 }
3807
3808 temp = 0;
2d41c0b5 3809
4969d33e
MR		 3810 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3811 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3812
4969d33e 3813 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3814 temp |= PLANE_WM_EN;
3815
4969d33e 3816 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3817
3818 }
3819
9414f563
DL		 3820 /* transition WMs */
3821 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3822 temp = 0;
3823 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3824 temp |= p_wm->trans_wm.plane_res_b[i];
3825 if (p_wm->trans_wm.plane_en[i])
3826 temp |= PLANE_WM_EN;
3827
3828 r->plane_trans[pipe][i] = temp;
3829 }
3830
3831 temp = 0;
4969d33e
MR		 3832 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3833 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3834 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3835 temp |= PLANE_WM_EN;
3836
4969d33e 3837 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3838
2d41c0b5
PB		 3839 r->wm_linetime[pipe] = p_wm->linetime;
3840}
3841
f0f59a00
VS		 3842static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3843 i915_reg_t reg,
16160e3d
DL		 3844 const struct skl_ddb_entry *entry)
3845{
3846 if (entry->end)
3847 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3848 else
3849 I915_WRITE(reg, 0);
3850}
3851
62e0fb88
L		 3852void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3853 const struct skl_wm_values *wm,
3854 int plane)
3855{
3856 struct drm_crtc *crtc = &intel_crtc->base;
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = to_i915(dev);
3859 int level, max_level = ilk_wm_max_level(dev);
3860 enum pipe pipe = intel_crtc->pipe;
3861
3862 for (level = 0; level <= max_level; level++) {
3863 I915_WRITE(PLANE_WM(pipe, plane, level),
3864 wm->plane[pipe][plane][level]);
3865 }
3866 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
27082493
L		 3867
3868 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3869 &wm->ddb.plane[pipe][plane]);
3870 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3871 &wm->ddb.y_plane[pipe][plane]);
62e0fb88
L		 3872}
3873
3874void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3875 const struct skl_wm_values *wm)
3876{
3877 struct drm_crtc *crtc = &intel_crtc->base;
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = to_i915(dev);
3880 int level, max_level = ilk_wm_max_level(dev);
3881 enum pipe pipe = intel_crtc->pipe;
3882
3883 for (level = 0; level <= max_level; level++) {
3884 I915_WRITE(CUR_WM(pipe, level),
3885 wm->plane[pipe][PLANE_CURSOR][level]);
3886 }
3887 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3888
27082493
L		 3889 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3890 &wm->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3891}
3892
27082493
L		 3893bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3894 const struct skl_ddb_allocation *new,
3895 enum pipe pipe)
0e8fb7ba 3896{
27082493
L		 3897 return new->pipe[pipe].start == old->pipe[pipe].start &&
3898 new->pipe[pipe].end == old->pipe[pipe].end;
0e8fb7ba
DL		 3899}
3900
27082493
L		 3901static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3902 const struct skl_ddb_entry *b)
0e8fb7ba 3903{
27082493 3904 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3905}
3906
27082493
L		 3907bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3908 const struct skl_ddb_allocation *old,
3909 const struct skl_ddb_allocation *new,
3910 enum pipe pipe)
0e8fb7ba 3911{
27082493
L		 3912 struct drm_device *dev = state->dev;
3913 struct intel_crtc *intel_crtc;
3914 enum pipe otherp;
0e8fb7ba 3915
27082493
L		 3916 for_each_intel_crtc(dev, intel_crtc) {
3917 otherp = intel_crtc->pipe;
0e8fb7ba 3918
27082493 3919 if (otherp == pipe)
0e8fb7ba
DL		 3920 continue;
3921
27082493
L		 3922 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3923 &old->pipe[otherp]))
3924 return true;
0e8fb7ba
DL		 3925 }
3926
27082493 3927 return false;
0e8fb7ba
DL		 3928}
3929
55994c2c
MR		 3930static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3931 struct skl_ddb_allocation *ddb, /* out */
3932 struct skl_pipe_wm *pipe_wm, /* out */
3933 bool *changed /* out */)
2d41c0b5 3934{
f4a96752
MR		 3935 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3936 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3937 int ret;
2d41c0b5 3938
55994c2c
MR		 3939 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3940 if (ret)
3941 return ret;
2d41c0b5 3942
4e0963c7 3943 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3944 *changed = false;
3945 else
3946 *changed = true;
2d41c0b5 3947
55994c2c 3948 return 0;
2d41c0b5
PB		 3949}
3950
9b613022
MR		 3951static uint32_t
3952pipes_modified(struct drm_atomic_state *state)
3953{
3954 struct drm_crtc *crtc;
3955 struct drm_crtc_state *cstate;
3956 uint32_t i, ret = 0;
3957
3958 for_each_crtc_in_state(state, crtc, cstate, i)
3959 ret |= drm_crtc_mask(crtc);
3960
3961 return ret;
3962}
3963
98d39494
MR		 3964static int
3965skl_compute_ddb(struct drm_atomic_state *state)
3966{
3967 struct drm_device *dev = state->dev;
3968 struct drm_i915_private *dev_priv = to_i915(dev);
3969 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3970 struct intel_crtc *intel_crtc;
734fa01f 3971 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3972 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3973 int ret;
3974
3975 /*
3976 * If this is our first atomic update following hardware readout,
3977 * we can't trust the DDB that the BIOS programmed for us. Let's
3978 * pretend that all pipes switched active status so that we'll
3979 * ensure a full DDB recompute.
3980 */
1b54a880
MR		 3981 if (dev_priv->wm.distrust_bios_wm) {
3982 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3983 state->acquire_ctx);
3984 if (ret)
3985 return ret;
3986
98d39494
MR		 3987 intel_state->active_pipe_changes = ~0;
3988
1b54a880
MR		 3989 /*
3990 * We usually only initialize intel_state->active_crtcs if we
3991 * we're doing a modeset; make sure this field is always
3992 * initialized during the sanitization process that happens
3993 * on the first commit too.
3994 */
3995 if (!intel_state->modeset)
3996 intel_state->active_crtcs = dev_priv->active_crtcs;
3997 }
3998
98d39494
MR		 3999 /*
4000 * If the modeset changes which CRTC's are active, we need to
4001 * recompute the DDB allocation for *all* active pipes, even
4002 * those that weren't otherwise being modified in any way by this
4003 * atomic commit. Due to the shrinking of the per-pipe allocations
4004 * when new active CRTC's are added, it's possible for a pipe that
4005 * we were already using and aren't changing at all here to suddenly
4006 * become invalid if its DDB needs exceeds its new allocation.
4007 *
4008 * Note that if we wind up doing a full DDB recompute, we can't let
4009 * any other display updates race with this transaction, so we need
4010 * to grab the lock on *all* CRTC's.
4011 */
734fa01f 4012 if (intel_state->active_pipe_changes) {
98d39494 4013 realloc_pipes = ~0;
734fa01f
MR		 4014 intel_state->wm_results.dirty_pipes = ~0;
4015 }
98d39494
MR		 4016
4017 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4018 struct intel_crtc_state *cstate;
4019
4020 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4021 if (IS_ERR(cstate))
4022 return PTR_ERR(cstate);
4023
734fa01f 4024 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4025 if (ret)
4026 return ret;
05a76d3d
L		 4027
4028 ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
4029 if (ret)
4030 return ret;
98d39494
MR		 4031 }
4032
4033 return 0;
4034}
4035
2722efb9
MR		 4036static void
4037skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4038 struct skl_wm_values *src,
4039 enum pipe pipe)
4040{
4041 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4042 memcpy(dst->plane[pipe], src->plane[pipe],
4043 sizeof(dst->plane[pipe]));
4044 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4045 sizeof(dst->plane_trans[pipe]));
4046
4047 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4048 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4049 sizeof(dst->ddb.y_plane[pipe]));
4050 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4051 sizeof(dst->ddb.plane[pipe]));
4052}
4053
98d39494
MR		 4054static int
4055skl_compute_wm(struct drm_atomic_state *state)
4056{
4057 struct drm_crtc *crtc;
4058 struct drm_crtc_state *cstate;
734fa01f
MR		 4059 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4060 struct skl_wm_values *results = &intel_state->wm_results;
4061 struct skl_pipe_wm *pipe_wm;
98d39494 4062 bool changed = false;
734fa01f 4063 int ret, i;
98d39494
MR		 4064
4065 /*
4066 * If this transaction isn't actually touching any CRTC's, don't
4067 * bother with watermark calculation. Note that if we pass this
4068 * test, we're guaranteed to hold at least one CRTC state mutex,
4069 * which means we can safely use values like dev_priv->active_crtcs
4070 * since any racing commits that want to update them would need to
4071 * hold _all_ CRTC state mutexes.
4072 */
4073 for_each_crtc_in_state(state, crtc, cstate, i)
4074 changed = true;
4075 if (!changed)
4076 return 0;
4077
734fa01f
MR		 4078 /* Clear all dirty flags */
4079 results->dirty_pipes = 0;
4080
98d39494
MR		 4081 ret = skl_compute_ddb(state);
4082 if (ret)
4083 return ret;
4084
734fa01f
MR		 4085 /*
4086 * Calculate WM's for all pipes that are part of this transaction.
4087 * Note that the DDB allocation above may have added more CRTC's that
4088 * weren't otherwise being modified (and set bits in dirty_pipes) if
4089 * pipe allocations had to change.
4090 *
4091 * FIXME: Now that we're doing this in the atomic check phase, we
4092 * should allow skl_update_pipe_wm() to return failure in cases where
4093 * no suitable watermark values can be found.
4094 */
4095 for_each_crtc_in_state(state, crtc, cstate, i) {
4096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4097 struct intel_crtc_state *intel_cstate =
4098 to_intel_crtc_state(cstate);
4099
4100 pipe_wm = &intel_cstate->wm.skl.optimal;
4101 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4102 &changed);
4103 if (ret)
4104 return ret;
4105
4106 if (changed)
4107 results->dirty_pipes |= drm_crtc_mask(crtc);
4108
4109 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4110 /* This pipe's WM's did not change */
4111 continue;
4112
4113 intel_cstate->update_wm_pre = true;
4114 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4115 }
4116
98d39494
MR		 4117 return 0;
4118}
4119
2d41c0b5
PB		 4120static void skl_update_wm(struct drm_crtc *crtc)
4121{
4122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4123 struct drm_device *dev = crtc->dev;
fac5e23e 4124 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4125 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4126 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4127 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4128 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4129 enum pipe pipe = intel_crtc->pipe;
adda50b8 4130
734fa01f 4131 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4132 return;
4133
734fa01f
MR		 4134 intel_crtc->wm.active.skl = *pipe_wm;
4135
4136 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4137
2722efb9 4138 /*
27082493
L		 4139 * If this pipe isn't active already, we're going to be enabling it
4140 * very soon. Since it's safe to update a pipe's ddb allocation while
4141 * the pipe's shut off, just do so here. Already active pipes will have
4142 * their watermarks updated once we update their planes.
2722efb9 4143 */
27082493
L		 4144 if (crtc->state->active_changed) {
4145 int plane;
4146
4147 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4148 skl_write_plane_wm(intel_crtc, results, plane);
4149
4150 skl_write_cursor_wm(intel_crtc, results);
4151 }
4152
4153 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4154
4155 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4156}
4157
d890565c
VS		 4158static void ilk_compute_wm_config(struct drm_device *dev,
4159 struct intel_wm_config *config)
4160{
4161 struct intel_crtc *crtc;
4162
4163 /* Compute the currently _active_ config */
4164 for_each_intel_crtc(dev, crtc) {
4165 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4166
4167 if (!wm->pipe_enabled)
4168 continue;
4169
4170 config->sprites_enabled |= wm->sprites_enabled;
4171 config->sprites_scaled |= wm->sprites_scaled;
4172 config->num_pipes_active++;
4173 }
4174}
4175
ed4a6a7c 4176static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4177{
91c8a326 4178 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4179 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4180 struct ilk_wm_maximums max;
d890565c 4181 struct intel_wm_config config = {};
820c1980 4182 struct ilk_wm_values results = {};
77c122bc 4183 enum intel_ddb_partitioning partitioning;
261a27d1 4184
d890565c
VS		 4185 ilk_compute_wm_config(dev, &config);
4186
4187 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4188 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4189
4190 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4191 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4192 config.num_pipes_active == 1 && config.sprites_enabled) {
4193 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4194 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4195
820c1980 4196 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4197 } else {
198a1e9b 4198 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4199 }
4200
198a1e9b 4201 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4202 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4203
820c1980 4204 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4205
820c1980 4206 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4207}
4208
ed4a6a7c 4209static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4210{
ed4a6a7c
MR		 4211 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4212 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4213
ed4a6a7c 4214 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4215 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4216 ilk_program_watermarks(dev_priv);
4217 mutex_unlock(&dev_priv->wm.wm_mutex);
4218}
bf220452 4219
ed4a6a7c
MR		 4220static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4221{
4222 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4223 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4224
ed4a6a7c
MR		 4225 mutex_lock(&dev_priv->wm.wm_mutex);
4226 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4227 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4228 ilk_program_watermarks(dev_priv);
4229 }
4230 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4231}
4232
3078999f
PB		 4233static void skl_pipe_wm_active_state(uint32_t val,
4234 struct skl_pipe_wm *active,
4235 bool is_transwm,
4236 bool is_cursor,
4237 int i,
4238 int level)
4239{
4240 bool is_enabled = (val & PLANE_WM_EN) != 0;
4241
4242 if (!is_transwm) {
4243 if (!is_cursor) {
4244 active->wm[level].plane_en[i] = is_enabled;
4245 active->wm[level].plane_res_b[i] =
4246 val & PLANE_WM_BLOCKS_MASK;
4247 active->wm[level].plane_res_l[i] =
4248 (val >> PLANE_WM_LINES_SHIFT) &
4249 PLANE_WM_LINES_MASK;
4250 } else {
4969d33e
MR		 4251 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4252 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4253 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4254 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4255 (val >> PLANE_WM_LINES_SHIFT) &
4256 PLANE_WM_LINES_MASK;
4257 }
4258 } else {
4259 if (!is_cursor) {
4260 active->trans_wm.plane_en[i] = is_enabled;
4261 active->trans_wm.plane_res_b[i] =
4262 val & PLANE_WM_BLOCKS_MASK;
4263 active->trans_wm.plane_res_l[i] =
4264 (val >> PLANE_WM_LINES_SHIFT) &
4265 PLANE_WM_LINES_MASK;
4266 } else {
4969d33e
MR		 4267 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4268 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4269 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4270 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4271 (val >> PLANE_WM_LINES_SHIFT) &
4272 PLANE_WM_LINES_MASK;
4273 }
4274 }
4275}
4276
4277static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4278{
4279 struct drm_device *dev = crtc->dev;
fac5e23e 4280 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4281 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4283 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4284 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4285 enum pipe pipe = intel_crtc->pipe;
4286 int level, i, max_level;
4287 uint32_t temp;
4288
4289 max_level = ilk_wm_max_level(dev);
4290
4291 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4292
4293 for (level = 0; level <= max_level; level++) {
4294 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4295 hw->plane[pipe][i][level] =
4296 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4297 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4298 }
4299
4300 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4301 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4302 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4303
3ef00284 4304 if (!intel_crtc->active)
3078999f
PB		 4305 return;
4306
2b4b9f35 4307 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4308
4309 active->linetime = hw->wm_linetime[pipe];
4310
4311 for (level = 0; level <= max_level; level++) {
4312 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4313 temp = hw->plane[pipe][i][level];
4314 skl_pipe_wm_active_state(temp, active, false,
4315 false, i, level);
4316 }
4969d33e 4317 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4318 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4319 }
4320
4321 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4322 temp = hw->plane_trans[pipe][i];
4323 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4324 }
4325
4969d33e 4326 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4327 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4328
4329 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4330}
4331
4332void skl_wm_get_hw_state(struct drm_device *dev)
4333{
fac5e23e 4334 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4335 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4336 struct drm_crtc *crtc;
4337
a269c583 4338 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4339 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4340 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4341
279e99d7
MR		 4342 if (dev_priv->active_crtcs) {
4343 /* Fully recompute DDB on first atomic commit */
4344 dev_priv->wm.distrust_bios_wm = true;
4345 } else {
4346 /* Easy/common case; just sanitize DDB now if everything off */
4347 memset(ddb, 0, sizeof(*ddb));
4348 }
3078999f
PB		 4349}
4350
243e6a44
VS		 4351static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4352{
4353 struct drm_device *dev = crtc->dev;
fac5e23e 4354 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4355 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4357 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4358 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4359 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4360 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4361 [PIPE_A] = WM0_PIPEA_ILK,
4362 [PIPE_B] = WM0_PIPEB_ILK,
4363 [PIPE_C] = WM0_PIPEC_IVB,
4364 };
4365
4366 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4367 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4368 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4369
15606534
VS		 4370 memset(active, 0, sizeof(*active));
4371
3ef00284 4372 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4373
4374 if (active->pipe_enabled) {
243e6a44
VS		 4375 u32 tmp = hw->wm_pipe[pipe];
4376
4377 /*
4378 * For active pipes LP0 watermark is marked as
4379 * enabled, and LP1+ watermaks as disabled since
4380 * we can't really reverse compute them in case
4381 * multiple pipes are active.
4382 */
4383 active->wm[0].enable = true;
4384 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4385 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4386 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4387 active->linetime = hw->wm_linetime[pipe];
4388 } else {
4389 int level, max_level = ilk_wm_max_level(dev);
4390
4391 /*
4392 * For inactive pipes, all watermark levels
4393 * should be marked as enabled but zeroed,
4394 * which is what we'd compute them to.
4395 */
4396 for (level = 0; level <= max_level; level++)
4397 active->wm[level].enable = true;
4398 }
4e0963c7
MR		 4399
4400 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4401}
4402
6eb1a681
VS		 4403#define _FW_WM(value, plane) \
4404 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4405#define _FW_WM_VLV(value, plane) \
4406 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4407
4408static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4409 struct vlv_wm_values *wm)
4410{
4411 enum pipe pipe;
4412 uint32_t tmp;
4413
4414 for_each_pipe(dev_priv, pipe) {
4415 tmp = I915_READ(VLV_DDL(pipe));
4416
4417 wm->ddl[pipe].primary =
4418 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4419 wm->ddl[pipe].cursor =
4420 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4421 wm->ddl[pipe].sprite[0] =
4422 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4423 wm->ddl[pipe].sprite[1] =
4424 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4425 }
4426
4427 tmp = I915_READ(DSPFW1);
4428 wm->sr.plane = _FW_WM(tmp, SR);
4429 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4430 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4431 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4432
4433 tmp = I915_READ(DSPFW2);
4434 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4435 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4436 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4437
4438 tmp = I915_READ(DSPFW3);
4439 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4440
4441 if (IS_CHERRYVIEW(dev_priv)) {
4442 tmp = I915_READ(DSPFW7_CHV);
4443 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4444 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4445
4446 tmp = I915_READ(DSPFW8_CHV);
4447 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4448 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4449
4450 tmp = I915_READ(DSPFW9_CHV);
4451 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4452 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4453
4454 tmp = I915_READ(DSPHOWM);
4455 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4456 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4457 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4458 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4459 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4460 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4461 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4462 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4463 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4464 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4465 } else {
4466 tmp = I915_READ(DSPFW7);
4467 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4468 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4469
4470 tmp = I915_READ(DSPHOWM);
4471 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4472 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4473 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4474 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4475 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4476 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4477 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4478 }
4479}
4480
4481#undef _FW_WM
4482#undef _FW_WM_VLV
4483
4484void vlv_wm_get_hw_state(struct drm_device *dev)
4485{
4486 struct drm_i915_private *dev_priv = to_i915(dev);
4487 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4488 struct intel_plane *plane;
4489 enum pipe pipe;
4490 u32 val;
4491
4492 vlv_read_wm_values(dev_priv, wm);
4493
4494 for_each_intel_plane(dev, plane) {
4495 switch (plane->base.type) {
4496 int sprite;
4497 case DRM_PLANE_TYPE_CURSOR:
4498 plane->wm.fifo_size = 63;
4499 break;
4500 case DRM_PLANE_TYPE_PRIMARY:
4501 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4502 break;
4503 case DRM_PLANE_TYPE_OVERLAY:
4504 sprite = plane->plane;
4505 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4506 break;
4507 }
4508 }
4509
4510 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4511 wm->level = VLV_WM_LEVEL_PM2;
4512
4513 if (IS_CHERRYVIEW(dev_priv)) {
4514 mutex_lock(&dev_priv->rps.hw_lock);
4515
4516 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4517 if (val & DSP_MAXFIFO_PM5_ENABLE)
4518 wm->level = VLV_WM_LEVEL_PM5;
4519
58590c14
VS		 4520 /*
4521 * If DDR DVFS is disabled in the BIOS, Punit
4522 * will never ack the request. So if that happens
4523 * assume we don't have to enable/disable DDR DVFS
4524 * dynamically. To test that just set the REQ_ACK
4525 * bit to poke the Punit, but don't change the
4526 * HIGH/LOW bits so that we don't actually change
4527 * the current state.
4528 */
6eb1a681 4529 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4530 val |= FORCE_DDR_FREQ_REQ_ACK;
4531 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4532
4533 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4534 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4535 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4536 "assuming DDR DVFS is disabled\n");
4537 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4538 } else {
4539 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4540 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4541 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4542 }
6eb1a681
VS		 4543
4544 mutex_unlock(&dev_priv->rps.hw_lock);
4545 }
4546
4547 for_each_pipe(dev_priv, pipe)
4548 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4549 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4550 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4551
4552 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4553 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4554}
4555
243e6a44
VS		 4556void ilk_wm_get_hw_state(struct drm_device *dev)
4557{
fac5e23e 4558 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4559 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4560 struct drm_crtc *crtc;
4561
70e1e0ec 4562 for_each_crtc(dev, crtc)
243e6a44
VS		 4563 ilk_pipe_wm_get_hw_state(crtc);
4564
4565 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4566 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4567 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4568
4569 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4570 if (INTEL_INFO(dev)->gen >= 7) {
4571 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4572 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4573 }
243e6a44 4574
a42a5719 4575 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4576 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4577 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4578 else if (IS_IVYBRIDGE(dev))
4579 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4580 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4581
4582 hw->enable_fbc_wm =
4583 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4584}
4585
b445e3b0
ED		 4586/**
4587 * intel_update_watermarks - update FIFO watermark values based on current modes
4588 *
4589 * Calculate watermark values for the various WM regs based on current mode
4590 * and plane configuration.
4591 *
4592 * There are several cases to deal with here:
4593 * - normal (i.e. non-self-refresh)
4594 * - self-refresh (SR) mode
4595 * - lines are large relative to FIFO size (buffer can hold up to 2)
4596 * - lines are small relative to FIFO size (buffer can hold more than 2
4597 * lines), so need to account for TLB latency
4598 *
4599 * The normal calculation is:
4600 * watermark = dotclock * bytes per pixel * latency
4601 * where latency is platform & configuration dependent (we assume pessimal
4602 * values here).
4603 *
4604 * The SR calculation is:
4605 * watermark = (trunc(latency/line time)+1) * surface width *
4606 * bytes per pixel
4607 * where
4608 * line time = htotal / dotclock
4609 * surface width = hdisplay for normal plane and 64 for cursor
4610 * and latency is assumed to be high, as above.
4611 *
4612 * The final value programmed to the register should always be rounded up,
4613 * and include an extra 2 entries to account for clock crossings.
4614 *
4615 * We don't use the sprite, so we can ignore that. And on Crestline we have
4616 * to set the non-SR watermarks to 8.
4617 */
46ba614c 4618void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4619{
fac5e23e 4620 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4621
4622 if (dev_priv->display.update_wm)
46ba614c 4623 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4624}
4625
e2828914 4626/*
9270388e 4627 * Lock protecting IPS related data structures
9270388e
DV		 4628 */
4629DEFINE_SPINLOCK(mchdev_lock);
4630
4631/* Global for IPS driver to get at the current i915 device. Protected by
4632 * mchdev_lock. */
4633static struct drm_i915_private *i915_mch_dev;
4634
91d14251 4635bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4636{
2b4e57bd
ED		 4637 u16 rgvswctl;
4638
9270388e
DV		 4639 assert_spin_locked(&mchdev_lock);
4640
2b4e57bd
ED		 4641 rgvswctl = I915_READ16(MEMSWCTL);
4642 if (rgvswctl & MEMCTL_CMD_STS) {
4643 DRM_DEBUG("gpu busy, RCS change rejected\n");
4644 return false; /* still busy with another command */
4645 }
4646
4647 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4648 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4649 I915_WRITE16(MEMSWCTL, rgvswctl);
4650 POSTING_READ16(MEMSWCTL);
4651
4652 rgvswctl |= MEMCTL_CMD_STS;
4653 I915_WRITE16(MEMSWCTL, rgvswctl);
4654
4655 return true;
4656}
4657
91d14251 4658static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4659{
84f1b20f 4660 u32 rgvmodectl;
2b4e57bd
ED		 4661 u8 fmax, fmin, fstart, vstart;
4662
9270388e
DV		 4663 spin_lock_irq(&mchdev_lock);
4664
84f1b20f
TU		 4665 rgvmodectl = I915_READ(MEMMODECTL);
4666
2b4e57bd
ED		 4667 /* Enable temp reporting */
4668 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4669 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4670
4671 /* 100ms RC evaluation intervals */
4672 I915_WRITE(RCUPEI, 100000);
4673 I915_WRITE(RCDNEI, 100000);
4674
4675 /* Set max/min thresholds to 90ms and 80ms respectively */
4676 I915_WRITE(RCBMAXAVG, 90000);
4677 I915_WRITE(RCBMINAVG, 80000);
4678
4679 I915_WRITE(MEMIHYST, 1);
4680
4681 /* Set up min, max, and cur for interrupt handling */
4682 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4683 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4684 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4685 MEMMODE_FSTART_SHIFT;
4686
616847e7 4687 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4688 PXVFREQ_PX_SHIFT;
4689
20e4d407
DV		 4690 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4691 dev_priv->ips.fstart = fstart;
2b4e57bd 4692
20e4d407
DV		 4693 dev_priv->ips.max_delay = fstart;
4694 dev_priv->ips.min_delay = fmin;
4695 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4696
4697 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4698 fmax, fmin, fstart);
4699
4700 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4701
4702 /*
4703 * Interrupts will be enabled in ironlake_irq_postinstall
4704 */
4705
4706 I915_WRITE(VIDSTART, vstart);
4707 POSTING_READ(VIDSTART);
4708
4709 rgvmodectl |= MEMMODE_SWMODE_EN;
4710 I915_WRITE(MEMMODECTL, rgvmodectl);
4711
9270388e 4712 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4713 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4714 mdelay(1);
2b4e57bd 4715
91d14251 4716 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4717
7d81c3e0
VS		 4718 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4719 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4720 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4721 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4722 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4723
4724 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4725}
4726
91d14251 4727static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4728{
9270388e
DV		 4729 u16 rgvswctl;
4730
4731 spin_lock_irq(&mchdev_lock);
4732
4733 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4734
4735 /* Ack interrupts, disable EFC interrupt */
4736 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4737 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4738 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4739 I915_WRITE(DEIIR, DE_PCU_EVENT);
4740 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4741
4742 /* Go back to the starting frequency */
91d14251 4743 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4744 mdelay(1);
2b4e57bd
ED		 4745 rgvswctl |= MEMCTL_CMD_STS;
4746 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4747 mdelay(1);
2b4e57bd 4748
9270388e 4749 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4750}
4751
acbe9475
DV		 4752/* There's a funny hw issue where the hw returns all 0 when reading from
4753 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4754 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4755 * all limits and the gpu stuck at whatever frequency it is at atm).
4756 */
74ef1173 4757static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4758{
7b9e0ae6 4759 u32 limits;
2b4e57bd 4760
20b46e59
DV		 4761 /* Only set the down limit when we've reached the lowest level to avoid
4762 * getting more interrupts, otherwise leave this clear. This prevents a
4763 * race in the hw when coming out of rc6: There's a tiny window where
4764 * the hw runs at the minimal clock before selecting the desired
4765 * frequency, if the down threshold expires in that window we will not
4766 * receive a down interrupt. */
2d1fe073 4767 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4768 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4769 if (val <= dev_priv->rps.min_freq_softlimit)
4770 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4771 } else {
4772 limits = dev_priv->rps.max_freq_softlimit << 24;
4773 if (val <= dev_priv->rps.min_freq_softlimit)
4774 limits |= dev_priv->rps.min_freq_softlimit << 16;
4775 }
20b46e59
DV		 4776
4777 return limits;
4778}
4779
dd75fdc8
CW		 4780static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4781{
4782 int new_power;
8a586437
AG		 4783 u32 threshold_up = 0, threshold_down = 0; /* in % */
4784 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4785
4786 new_power = dev_priv->rps.power;
4787 switch (dev_priv->rps.power) {
4788 case LOW_POWER:
a72b5623
CW		 4789 if (val > dev_priv->rps.efficient_freq + 1 &&
4790 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4791 new_power = BETWEEN;
4792 break;
4793
4794 case BETWEEN:
a72b5623
CW		 4795 if (val <= dev_priv->rps.efficient_freq &&
4796 val < dev_priv->rps.cur_freq)
dd75fdc8 4797 new_power = LOW_POWER;
a72b5623
CW		 4798 else if (val >= dev_priv->rps.rp0_freq &&
4799 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4800 new_power = HIGH_POWER;
4801 break;
4802
4803 case HIGH_POWER:
a72b5623
CW		 4804 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4805 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4806 new_power = BETWEEN;
4807 break;
4808 }
4809 /* Max/min bins are special */
aed242ff 4810 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4811 new_power = LOW_POWER;
aed242ff 4812 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4813 new_power = HIGH_POWER;
4814 if (new_power == dev_priv->rps.power)
4815 return;
4816
4817 /* Note the units here are not exactly 1us, but 1280ns. */
4818 switch (new_power) {
4819 case LOW_POWER:
4820 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4821 ei_up = 16000;
4822 threshold_up = 95;
dd75fdc8
CW		 4823
4824 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4825 ei_down = 32000;
4826 threshold_down = 85;
dd75fdc8
CW		 4827 break;
4828
4829 case BETWEEN:
4830 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4831 ei_up = 13000;
4832 threshold_up = 90;
dd75fdc8
CW		 4833
4834 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4835 ei_down = 32000;
4836 threshold_down = 75;
dd75fdc8
CW		 4837 break;
4838
4839 case HIGH_POWER:
4840 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4841 ei_up = 10000;
4842 threshold_up = 85;
dd75fdc8
CW		 4843
4844 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4845 ei_down = 32000;
4846 threshold_down = 60;
dd75fdc8
CW		 4847 break;
4848 }
4849
8a586437 4850 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4851 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4852 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4853 GT_INTERVAL_FROM_US(dev_priv,
4854 ei_up * threshold_up / 100));
8a586437
AG		 4855
4856 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4857 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4858 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4859 GT_INTERVAL_FROM_US(dev_priv,
4860 ei_down * threshold_down / 100));
4861
4862 I915_WRITE(GEN6_RP_CONTROL,
4863 GEN6_RP_MEDIA_TURBO |
4864 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4865 GEN6_RP_MEDIA_IS_GFX |
4866 GEN6_RP_ENABLE |
4867 GEN6_RP_UP_BUSY_AVG |
4868 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4869
dd75fdc8 4870 dev_priv->rps.power = new_power;
8fb55197
CW		 4871 dev_priv->rps.up_threshold = threshold_up;
4872 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4873 dev_priv->rps.last_adj = 0;
4874}
4875
2876ce73
CW		 4876static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4877{
4878 u32 mask = 0;
4879
4880 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4881 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4882 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4883 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4884
7b3c29f6
CW		 4885 mask &= dev_priv->pm_rps_events;
4886
59d02a1f 4887 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4888}
4889
b8a5ff8d
JM		 4890/* gen6_set_rps is called to update the frequency request, but should also be
4891 * called when the range (min_delay and max_delay) is modified so that we can
4892 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4893static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4894{
23eafea6 4895 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4896 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4897 return;
4898
4fc688ce 4899 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4900 WARN_ON(val > dev_priv->rps.max_freq);
4901 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4902
eb64cad1
CW		 4903 /* min/max delay may still have been modified so be sure to
4904 * write the limits value.
4905 */
4906 if (val != dev_priv->rps.cur_freq) {
4907 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4908
dc97997a 4909 if (IS_GEN9(dev_priv))
5704195c
AG		 4910 I915_WRITE(GEN6_RPNSWREQ,
4911 GEN9_FREQUENCY(val));
dc97997a 4912 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4913 I915_WRITE(GEN6_RPNSWREQ,
4914 HSW_FREQUENCY(val));
4915 else
4916 I915_WRITE(GEN6_RPNSWREQ,
4917 GEN6_FREQUENCY(val) |
4918 GEN6_OFFSET(0) |
4919 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4920 }
7b9e0ae6 4921
7b9e0ae6
CW		 4922 /* Make sure we continue to get interrupts
4923 * until we hit the minimum or maximum frequencies.
4924 */
74ef1173 4925 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4926 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4927
d5570a72
BW		 4928 POSTING_READ(GEN6_RPNSWREQ);
4929
b39fb297 4930 dev_priv->rps.cur_freq = val;
0f94592e 4931 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4932}
4933
dc97997a 4934static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4935{
ffe02b40 4936 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4937 WARN_ON(val > dev_priv->rps.max_freq);
4938 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4939
dc97997a 4940 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4941 "Odd GPU freq value\n"))
4942 val &= ~1;
4943
cd25dd5b
D		 4944 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4945
8fb55197 4946 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4947 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4948 if (!IS_CHERRYVIEW(dev_priv))
4949 gen6_set_rps_thresholds(dev_priv, val);
4950 }
ffe02b40 4951
ffe02b40
VS		 4952 dev_priv->rps.cur_freq = val;
4953 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4954}
4955
a7f6e231 4956/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4957 *
4958 * * If Gfx is Idle, then
a7f6e231
D		 4959 * 1. Forcewake Media well.
4960 * 2. Request idle freq.
4961 * 3. Release Forcewake of Media well.
76c3552f
D		 4962*/
4963static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4964{
aed242ff 4965 u32 val = dev_priv->rps.idle_freq;
5549d25f 4966
aed242ff 4967 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4968 return;
4969
a7f6e231
D		 4970 /* Wake up the media well, as that takes a lot less
4971 * power than the Render well. */
4972 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4973 valleyview_set_rps(dev_priv, val);
a7f6e231 4974 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4975}
4976
43cf3bf0
CW		 4977void gen6_rps_busy(struct drm_i915_private *dev_priv)
4978{
4979 mutex_lock(&dev_priv->rps.hw_lock);
4980 if (dev_priv->rps.enabled) {
4981 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4982 gen6_rps_reset_ei(dev_priv);
4983 I915_WRITE(GEN6_PMINTRMSK,
4984 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 4985
c33d247d
CW		 4986 gen6_enable_rps_interrupts(dev_priv);
4987
2b83c4c4
MW		 4988 /* Ensure we start at the user's desired frequency */
4989 intel_set_rps(dev_priv,
4990 clamp(dev_priv->rps.cur_freq,
4991 dev_priv->rps.min_freq_softlimit,
4992 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 4993 }
4994 mutex_unlock(&dev_priv->rps.hw_lock);
4995}
4996
b29c19b6
CW		 4997void gen6_rps_idle(struct drm_i915_private *dev_priv)
4998{
c33d247d
CW		 4999 /* Flush our bottom-half so that it does not race with us
5000 * setting the idle frequency and so that it is bounded by
5001 * our rpm wakeref. And then disable the interrupts to stop any
5002 * futher RPS reclocking whilst we are asleep.
5003 */
5004 gen6_disable_rps_interrupts(dev_priv);
5005
b29c19b6 5006 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5007 if (dev_priv->rps.enabled) {
dc97997a 5008 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5009 vlv_set_rps_idle(dev_priv);
7526ed79 5010 else
dc97997a 5011 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5012 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5013 I915_WRITE(GEN6_PMINTRMSK,
5014 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5015 }
8d3afd7d 5016 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5017
8d3afd7d 5018 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5019 while (!list_empty(&dev_priv->rps.clients))
5020 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5021 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5022}
5023
1854d5ca 5024void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5025 struct intel_rps_client *rps,
5026 unsigned long submitted)
b29c19b6 5027{
8d3afd7d
CW		 5028 /* This is intentionally racy! We peek at the state here, then
5029 * validate inside the RPS worker.
5030 */
67d97da3 5031 if (!(dev_priv->gt.awake &&
8d3afd7d 5032 dev_priv->rps.enabled &&
29ecd78d 5033 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5034 return;
43cf3bf0 5035
e61b9958
CW		 5036 /* Force a RPS boost (and don't count it against the client) if
5037 * the GPU is severely congested.
5038 */
d0bc54f2 5039 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5040 rps = NULL;
5041
8d3afd7d
CW		 5042 spin_lock(&dev_priv->rps.client_lock);
5043 if (rps == NULL || list_empty(&rps->link)) {
5044 spin_lock_irq(&dev_priv->irq_lock);
5045 if (dev_priv->rps.interrupts_enabled) {
5046 dev_priv->rps.client_boost = true;
c33d247d 5047 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5048 }
5049 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5050
2e1b8730
CW		 5051 if (rps != NULL) {
5052 list_add(&rps->link, &dev_priv->rps.clients);
5053 rps->boosts++;
1854d5ca
CW		 5054 } else
5055 dev_priv->rps.boosts++;
c0951f0c 5056 }
8d3afd7d 5057 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5058}
5059
dc97997a 5060void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5061{
dc97997a
CW		 5062 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5063 valleyview_set_rps(dev_priv, val);
ffe02b40 5064 else
dc97997a 5065 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5066}
5067
dc97997a 5068static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5069{
20e49366 5070 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5071 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5072}
5073
dc97997a 5074static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5075{
2030d684
AG		 5076 I915_WRITE(GEN6_RP_CONTROL, 0);
5077}
5078
dc97997a 5079static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5080{
d20d4f0c 5081 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5082 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5083 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5084}
5085
dc97997a 5086static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5087{
38807746
D		 5088 I915_WRITE(GEN6_RC_CONTROL, 0);
5089}
5090
dc97997a 5091static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5092{
98a2e5f9
D		 5093 /* we're doing forcewake before Disabling RC6,
5094 * This what the BIOS expects when going into suspend */
59bad947 5095 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5096
44fc7d5c 5097 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5098
59bad947 5099 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5100}
5101
dc97997a 5102static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5103{
dc97997a 5104 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5105 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5106 mode = GEN6_RC_CTL_RC6_ENABLE;
5107 else
5108 mode = 0;
5109 }
dc97997a 5110 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5111 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5112 "RC6 %s RC6p %s RC6pp %s\n",
5113 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5114 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5115 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5116
5117 else
b99d49cc
ID		 5118 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5119 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5120}
5121
dc97997a 5122static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5123{
72e96d64 5124 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5125 bool enable_rc6 = true;
5126 unsigned long rc6_ctx_base;
fc619841
ID		 5127 u32 rc_ctl;
5128 int rc_sw_target;
5129
5130 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5131 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5132 RC_SW_TARGET_STATE_SHIFT;
5133 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5134 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5135 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5136 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5137 rc_sw_target);
274008e8
SAK		 5138
5139 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5140 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5141 enable_rc6 = false;
5142 }
5143
5144 /*
5145 * The exact context size is not known for BXT, so assume a page size
5146 * for this check.
5147 */
5148 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5149 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5150 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5151 ggtt->stolen_reserved_size))) {
b99d49cc 5152 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5153 enable_rc6 = false;
5154 }
5155
5156 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5157 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5158 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5159 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5160 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5161 enable_rc6 = false;
5162 }
5163
fc619841
ID		 5164 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5165 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5166 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5167 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5168 enable_rc6 = false;
5169 }
5170
5171 if (!I915_READ(GEN6_GFXPAUSE)) {
5172 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5173 enable_rc6 = false;
5174 }
5175
5176 if (!I915_READ(GEN8_MISC_CTRL0)) {
5177 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5178 enable_rc6 = false;
5179 }
5180
5181 return enable_rc6;
5182}
5183
dc97997a 5184int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5185{
e7d66d89 5186 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5187 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5188 return 0;
5189
274008e8
SAK		 5190 if (!enable_rc6)
5191 return 0;
5192
dc97997a 5193 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5194 DRM_INFO("RC6 disabled by BIOS\n");
5195 return 0;
5196 }
5197
456470eb 5198 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5199 if (enable_rc6 >= 0) {
5200 int mask;
5201
dc97997a 5202 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5203 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5204 INTEL_RC6pp_ENABLE;
5205 else
5206 mask = INTEL_RC6_ENABLE;
5207
5208 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5209 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5210 "(requested %d, valid %d)\n",
5211 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5212
5213 return enable_rc6 & mask;
5214 }
2b4e57bd 5215
dc97997a 5216 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5217 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5218
5219 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5220}
5221
dc97997a 5222static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5223{
5224 /* All of these values are in units of 50MHz */
773ea9a8 5225
93ee2920 5226 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5227 if (IS_BROXTON(dev_priv)) {
773ea9a8 5228 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5229 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5230 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5231 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5232 } else {
773ea9a8 5233 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5234 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5235 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5236 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5237 }
3280e8b0 5238 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5239 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5240
93ee2920 5241 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5242 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5243 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5244 u32 ddcc_status = 0;
5245
5246 if (sandybridge_pcode_read(dev_priv,
5247 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5248 &ddcc_status) == 0)
93ee2920 5249 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5250 clamp_t(u8,
5251 ((ddcc_status >> 8) & 0xff),
5252 dev_priv->rps.min_freq,
5253 dev_priv->rps.max_freq);
93ee2920
TR		 5254 }
5255
dc97997a 5256 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5257 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5258 * the natural hardware unit for SKL
5259 */
c5e0688c
AG		 5260 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5261 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5262 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5263 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5264 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5265 }
3280e8b0
BW		 5266}
5267
3a45b05c
CW		 5268static void reset_rps(struct drm_i915_private *dev_priv,
5269 void (*set)(struct drm_i915_private *, u8))
5270{
5271 u8 freq = dev_priv->rps.cur_freq;
5272
5273 /* force a reset */
5274 dev_priv->rps.power = -1;
5275 dev_priv->rps.cur_freq = -1;
5276
5277 set(dev_priv, freq);
5278}
5279
b6fef0ef 5280/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5281static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5282{
b6fef0ef
JB		 5283 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5284
23eafea6 5285 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5286 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5287 /*
5288 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5289 * clear out the Control register just to avoid inconsitency
5290 * with debugfs interface, which will show Turbo as enabled
5291 * only and that is not expected by the User after adding the
5292 * WaGsvDisableTurbo. Apart from this there is no problem even
5293 * if the Turbo is left enabled in the Control register, as the
5294 * Up/Down interrupts would remain masked.
5295 */
dc97997a 5296 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5297 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5298 return;
5299 }
5300
0beb059a
AG		 5301 /* Program defaults and thresholds for RPS*/
5302 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5303 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5304
5305 /* 1 second timeout*/
5306 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5307 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5308
b6fef0ef 5309 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5310
0beb059a
AG		 5311 /* Leaning on the below call to gen6_set_rps to program/setup the
5312 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5313 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5314 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5315
5316 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5317}
5318
dc97997a 5319static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5320{
e2f80391 5321 struct intel_engine_cs *engine;
20e49366 5322 uint32_t rc6_mask = 0;
20e49366
ZW		 5323
5324 /* 1a: Software RC state - RC0 */
5325 I915_WRITE(GEN6_RC_STATE, 0);
5326
5327 /* 1b: Get forcewake during program sequence. Although the driver
5328 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5329 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5330
5331 /* 2a: Disable RC states. */
5332 I915_WRITE(GEN6_RC_CONTROL, 0);
5333
5334 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5335
5336 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5337 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5338 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5339 else
5340 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5341 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5342 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5343 for_each_engine(engine, dev_priv)
e2f80391 5344 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5345
1a3d1898 5346 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5347 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5348
20e49366 5349 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5350
38c23527
ZW		 5351 /* 2c: Program Coarse Power Gating Policies. */
5352 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5353 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5354
20e49366 5355 /* 3a: Enable RC6 */
dc97997a 5356 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5357 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5358 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5359 /* WaRsUseTimeoutMode */
dc97997a
CW		 5360 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5361 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5362 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5363 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5364 GEN7_RC_CTL_TO_MODE |
5365 rc6_mask);
3e7732a0
SAK		 5366 } else {
5367 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5368 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5369 GEN6_RC_CTL_EI_MODE(1) |
5370 rc6_mask);
3e7732a0 5371 }
20e49366 5372
cb07bae0
SK		 5373 /*
5374 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5375 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5376 */
dc97997a 5377 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5378 I915_WRITE(GEN9_PG_ENABLE, 0);
5379 else
5380 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5381 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5382
59bad947 5383 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5384}
5385
dc97997a 5386static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5387{
e2f80391 5388 struct intel_engine_cs *engine;
93ee2920 5389 uint32_t rc6_mask = 0;
6edee7f3
BW		 5390
5391 /* 1a: Software RC state - RC0 */
5392 I915_WRITE(GEN6_RC_STATE, 0);
5393
5394 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5395 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5396 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5397
5398 /* 2a: Disable RC states. */
5399 I915_WRITE(GEN6_RC_CONTROL, 0);
5400
6edee7f3
BW		 5401 /* 2b: Program RC6 thresholds.*/
5402 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5403 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5404 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5405 for_each_engine(engine, dev_priv)
e2f80391 5406 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5407 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5408 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5409 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5410 else
5411 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5412
5413 /* 3: Enable RC6 */
dc97997a 5414 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5415 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5416 intel_print_rc6_info(dev_priv, rc6_mask);
5417 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5418 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5419 GEN7_RC_CTL_TO_MODE |
5420 rc6_mask);
5421 else
5422 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5423 GEN6_RC_CTL_EI_MODE(1) |
5424 rc6_mask);
6edee7f3
BW		 5425
5426 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5427 I915_WRITE(GEN6_RPNSWREQ,
5428 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5429 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5430 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5431 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5432 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5433
5434 /* Docs recommend 900MHz, and 300 MHz respectively */
5435 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5436 dev_priv->rps.max_freq_softlimit << 24 |
5437 dev_priv->rps.min_freq_softlimit << 16);
5438
5439 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5440 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5441 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5442 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5443
5444 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5445
5446 /* 5: Enable RPS */
7526ed79
DV		 5447 I915_WRITE(GEN6_RP_CONTROL,
5448 GEN6_RP_MEDIA_TURBO |
5449 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5450 GEN6_RP_MEDIA_IS_GFX |
5451 GEN6_RP_ENABLE |
5452 GEN6_RP_UP_BUSY_AVG |
5453 GEN6_RP_DOWN_IDLE_AVG);
5454
5455 /* 6: Ring frequency + overclocking (our driver does this later */
5456
3a45b05c 5457 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5458
59bad947 5459 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5460}
5461
dc97997a 5462static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5463{
e2f80391 5464 struct intel_engine_cs *engine;
99ac9612 5465 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5466 u32 gtfifodbg;
2b4e57bd 5467 int rc6_mode;
b4ac5afc 5468 int ret;
2b4e57bd 5469
4fc688ce 5470 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5471
2b4e57bd
ED		 5472 /* Here begins a magic sequence of register writes to enable
5473 * auto-downclocking.
5474 *
5475 * Perhaps there might be some value in exposing these to
5476 * userspace...
5477 */
5478 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5479
5480 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5481 gtfifodbg = I915_READ(GTFIFODBG);
5482 if (gtfifodbg) {
2b4e57bd
ED		 5483 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5484 I915_WRITE(GTFIFODBG, gtfifodbg);
5485 }
5486
59bad947 5487 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5488
5489 /* disable the counters and set deterministic thresholds */
5490 I915_WRITE(GEN6_RC_CONTROL, 0);
5491
5492 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5493 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5494 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5495 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5496 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5497
b4ac5afc 5498 for_each_engine(engine, dev_priv)
e2f80391 5499 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5500
5501 I915_WRITE(GEN6_RC_SLEEP, 0);
5502 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5503 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5504 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5505 else
5506 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5507 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5508 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5509
5a7dc92a 5510 /* Check if we are enabling RC6 */
dc97997a 5511 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5512 if (rc6_mode & INTEL_RC6_ENABLE)
5513 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5514
5a7dc92a 5515 /* We don't use those on Haswell */
dc97997a 5516 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5517 if (rc6_mode & INTEL_RC6p_ENABLE)
5518 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5519
5a7dc92a
ED		 5520 if (rc6_mode & INTEL_RC6pp_ENABLE)
5521 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5522 }
2b4e57bd 5523
dc97997a 5524 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5525
5526 I915_WRITE(GEN6_RC_CONTROL,
5527 rc6_mask |
5528 GEN6_RC_CTL_EI_MODE(1) |
5529 GEN6_RC_CTL_HW_ENABLE);
5530
dd75fdc8
CW		 5531 /* Power down if completely idle for over 50ms */
5532 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5533 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5534
42c0526c 5535 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5536 if (ret)
42c0526c 5537 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5538
3a45b05c 5539 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5540
31643d54
BW		 5541 rc6vids = 0;
5542 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5543 if (IS_GEN6(dev_priv) && ret) {
31643d54 5544 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5545 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5546 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5547 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5548 rc6vids &= 0xffff00;
5549 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5550 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5551 if (ret)
5552 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5553 }
5554
59bad947 5555 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5556}
5557
fb7404e8 5558static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5559{
5560 int min_freq = 15;
3ebecd07
CW		 5561 unsigned int gpu_freq;
5562 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5563 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5564 int scaling_factor = 180;
eda79642 5565 struct cpufreq_policy *policy;
2b4e57bd 5566
4fc688ce 5567 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5568
eda79642
BW		 5569 policy = cpufreq_cpu_get(0);
5570 if (policy) {
5571 max_ia_freq = policy->cpuinfo.max_freq;
5572 cpufreq_cpu_put(policy);
5573 } else {
5574 /*
5575 * Default to measured freq if none found, PCU will ensure we
5576 * don't go over
5577 */
2b4e57bd 5578 max_ia_freq = tsc_khz;
eda79642 5579 }
2b4e57bd
ED		 5580
5581 /* Convert from kHz to MHz */
5582 max_ia_freq /= 1000;
5583
153b4b95 5584 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5585 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5586 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5587
dc97997a 5588 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5589 /* Convert GT frequency to 50 HZ units */
5590 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5591 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5592 } else {
5593 min_gpu_freq = dev_priv->rps.min_freq;
5594 max_gpu_freq = dev_priv->rps.max_freq;
5595 }
5596
2b4e57bd
ED		 5597 /*
5598 * For each potential GPU frequency, load a ring frequency we'd like
5599 * to use for memory access. We do this by specifying the IA frequency
5600 * the PCU should use as a reference to determine the ring frequency.
5601 */
4c8c7743
AG		 5602 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5603 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5604 unsigned int ia_freq = 0, ring_freq = 0;
5605
dc97997a 5606 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5607 /*
5608 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5609 * No floor required for ring frequency on SKL.
5610 */
5611 ring_freq = gpu_freq;
dc97997a 5612 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5613 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5614 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5615 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5616 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5617 ring_freq = max(min_ring_freq, ring_freq);
5618 /* leave ia_freq as the default, chosen by cpufreq */
5619 } else {
5620 /* On older processors, there is no separate ring
5621 * clock domain, so in order to boost the bandwidth
5622 * of the ring, we need to upclock the CPU (ia_freq).
5623 *
5624 * For GPU frequencies less than 750MHz,
5625 * just use the lowest ring freq.
5626 */
5627 if (gpu_freq < min_freq)
5628 ia_freq = 800;
5629 else
5630 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5631 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5632 }
2b4e57bd 5633
42c0526c
BW		 5634 sandybridge_pcode_write(dev_priv,
5635 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5636 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5637 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5638 gpu_freq);
2b4e57bd 5639 }
2b4e57bd
ED		 5640}
5641
03af2045 5642static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5643{
5644 u32 val, rp0;
5645
5b5929cb 5646 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5647
43b67998 5648 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5649 case 8:
5650 /* (2 * 4) config */
5651 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5652 break;
5653 case 12:
5654 /* (2 * 6) config */
5655 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5656 break;
5657 case 16:
5658 /* (2 * 8) config */
5659 default:
5660 /* Setting (2 * 8) Min RP0 for any other combination */
5661 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5662 break;
095acd5f 5663 }
5b5929cb
JN		 5664
5665 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5666
2b6b3a09
D		 5667 return rp0;
5668}
5669
5670static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5671{
5672 u32 val, rpe;
5673
5674 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5675 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5676
5677 return rpe;
5678}
5679
7707df4a
D		 5680static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5681{
5682 u32 val, rp1;
5683
5b5929cb
JN		 5684 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5685 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5686
7707df4a
D		 5687 return rp1;
5688}
5689
f8f2b001
D		 5690static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5691{
5692 u32 val, rp1;
5693
5694 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5695
5696 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5697
5698 return rp1;
5699}
5700
03af2045 5701static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5702{
5703 u32 val, rp0;
5704
64936258 5705 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5706
5707 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5708 /* Clamp to max */
5709 rp0 = min_t(u32, rp0, 0xea);
5710
5711 return rp0;
5712}
5713
5714static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5715{
5716 u32 val, rpe;
5717
64936258 5718 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5719 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5720 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5721 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5722
5723 return rpe;
5724}
5725
03af2045 5726static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5727{
36146035
ID		 5728 u32 val;
5729
5730 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5731 /*
5732 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5733 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5734 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5735 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5736 * to make sure it matches what Punit accepts.
5737 */
5738 return max_t(u32, val, 0xc0);
0a073b84
JB		 5739}
5740
ae48434c
ID		 5741/* Check that the pctx buffer wasn't move under us. */
5742static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5743{
5744 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5745
5746 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5747 dev_priv->vlv_pctx->stolen->start);
5748}
5749
38807746
D		 5750
5751/* Check that the pcbr address is not empty. */
5752static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5753{
5754 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5755
5756 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5757}
5758
dc97997a 5759static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5760{
62106b4f 5761 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5762 unsigned long pctx_paddr, paddr;
38807746
D		 5763 u32 pcbr;
5764 int pctx_size = 32*1024;
5765
38807746
D		 5766 pcbr = I915_READ(VLV_PCBR);
5767 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5768 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5769 paddr = (dev_priv->mm.stolen_base +
62106b4f 5770 (ggtt->stolen_size - pctx_size));
38807746
D		 5771
5772 pctx_paddr = (paddr & (~4095));
5773 I915_WRITE(VLV_PCBR, pctx_paddr);
5774 }
ce611ef8
VS		 5775
5776 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5777}
5778
dc97997a 5779static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5780{
c9cddffc
JB		 5781 struct drm_i915_gem_object *pctx;
5782 unsigned long pctx_paddr;
5783 u32 pcbr;
5784 int pctx_size = 24*1024;
5785
5786 pcbr = I915_READ(VLV_PCBR);
5787 if (pcbr) {
5788 /* BIOS set it up already, grab the pre-alloc'd space */
5789 int pcbr_offset;
5790
5791 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5792 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5793 pcbr_offset,
190d6cd5 5794 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5795 pctx_size);
5796 goto out;
5797 }
5798
ce611ef8
VS		 5799 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5800
c9cddffc
JB		 5801 /*
5802 * From the Gunit register HAS:
5803 * The Gfx driver is expected to program this register and ensure
5804 * proper allocation within Gfx stolen memory. For example, this
5805 * register should be programmed such than the PCBR range does not
5806 * overlap with other ranges, such as the frame buffer, protected
5807 * memory, or any other relevant ranges.
5808 */
91c8a326 5809 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5810 if (!pctx) {
5811 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5812 goto out;
c9cddffc
JB		 5813 }
5814
5815 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5816 I915_WRITE(VLV_PCBR, pctx_paddr);
5817
5818out:
ce611ef8 5819 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5820 dev_priv->vlv_pctx = pctx;
5821}
5822
dc97997a 5823static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5824{
ae48434c
ID		 5825 if (WARN_ON(!dev_priv->vlv_pctx))
5826 return;
5827
34911fd3 5828 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5829 dev_priv->vlv_pctx = NULL;
5830}
5831
c30fec65
VS		 5832static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5833{
5834 dev_priv->rps.gpll_ref_freq =
5835 vlv_get_cck_clock(dev_priv, "GPLL ref",
5836 CCK_GPLL_CLOCK_CONTROL,
5837 dev_priv->czclk_freq);
5838
5839 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5840 dev_priv->rps.gpll_ref_freq);
5841}
5842
dc97997a 5843static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5844{
2bb25c17 5845 u32 val;
4e80519e 5846
dc97997a 5847 valleyview_setup_pctx(dev_priv);
4e80519e 5848
c30fec65
VS		 5849 vlv_init_gpll_ref_freq(dev_priv);
5850
2bb25c17
VS		 5851 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5852 switch ((val >> 6) & 3) {
5853 case 0:
5854 case 1:
5855 dev_priv->mem_freq = 800;
5856 break;
5857 case 2:
5858 dev_priv->mem_freq = 1066;
5859 break;
5860 case 3:
5861 dev_priv->mem_freq = 1333;
5862 break;
5863 }
80b83b62 5864 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5865
4e80519e
ID		 5866 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5867 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5868 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5869 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5870 dev_priv->rps.max_freq);
5871
5872 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5873 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5874 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5875 dev_priv->rps.efficient_freq);
5876
f8f2b001
D		 5877 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5878 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5879 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5880 dev_priv->rps.rp1_freq);
5881
4e80519e
ID		 5882 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5883 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5884 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5885 dev_priv->rps.min_freq);
4e80519e
ID		 5886}
5887
dc97997a 5888static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5889{
2bb25c17 5890 u32 val;
2b6b3a09 5891
dc97997a 5892 cherryview_setup_pctx(dev_priv);
2b6b3a09 5893
c30fec65
VS		 5894 vlv_init_gpll_ref_freq(dev_priv);
5895
a580516d 5896 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5897 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5898 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5899
2bb25c17 5900 switch ((val >> 2) & 0x7) {
2bb25c17 5901 case 3:
2bb25c17
VS		 5902 dev_priv->mem_freq = 2000;
5903 break;
bfa7df01 5904 default:
2bb25c17
VS		 5905 dev_priv->mem_freq = 1600;
5906 break;
5907 }
80b83b62 5908 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5909
2b6b3a09
D		 5910 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5911 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5912 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5913 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5914 dev_priv->rps.max_freq);
5915
5916 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5917 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5918 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5919 dev_priv->rps.efficient_freq);
5920
7707df4a
D		 5921 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5922 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5923 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5924 dev_priv->rps.rp1_freq);
5925
5b7c91b7
D		 5926 /* PUnit validated range is only [RPe, RP0] */
5927 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5928 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5929 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5930 dev_priv->rps.min_freq);
5931
1c14762d
VS		 5932 WARN_ONCE((dev_priv->rps.max_freq |
5933 dev_priv->rps.efficient_freq |
5934 dev_priv->rps.rp1_freq |
5935 dev_priv->rps.min_freq) & 1,
5936 "Odd GPU freq values\n");
38807746
D		 5937}
5938
dc97997a 5939static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5940{
dc97997a 5941 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5942}
5943
dc97997a 5944static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5945{
e2f80391 5946 struct intel_engine_cs *engine;
2b6b3a09 5947 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5948
5949 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5950
297b32ec
VS		 5951 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5952 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5953 if (gtfifodbg) {
5954 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5955 gtfifodbg);
5956 I915_WRITE(GTFIFODBG, gtfifodbg);
5957 }
5958
5959 cherryview_check_pctx(dev_priv);
5960
5961 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5962 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5963 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5964
160614a2
VS		 5965 /* Disable RC states. */
5966 I915_WRITE(GEN6_RC_CONTROL, 0);
5967
38807746
D		 5968 /* 2a: Program RC6 thresholds.*/
5969 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5970 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5971 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5972
b4ac5afc 5973 for_each_engine(engine, dev_priv)
e2f80391 5974 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5975 I915_WRITE(GEN6_RC_SLEEP, 0);
5976
f4f71c7d
D		 5977 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5978 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5979
5980 /* allows RC6 residency counter to work */
5981 I915_WRITE(VLV_COUNTER_CONTROL,
5982 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5983 VLV_MEDIA_RC6_COUNT_EN |
5984 VLV_RENDER_RC6_COUNT_EN));
5985
5986 /* For now we assume BIOS is allocating and populating the PCBR */
5987 pcbr = I915_READ(VLV_PCBR);
5988
38807746 5989 /* 3: Enable RC6 */
dc97997a
CW		 5990 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5991 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5992 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5993
5994 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5995
2b6b3a09 5996 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5997 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5998 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5999 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6000 I915_WRITE(GEN6_RP_UP_EI, 66000);
6001 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6002
6003 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6004
6005 /* 5: Enable RPS */
6006 I915_WRITE(GEN6_RP_CONTROL,
6007 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6008 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6009 GEN6_RP_ENABLE |
6010 GEN6_RP_UP_BUSY_AVG |
6011 GEN6_RP_DOWN_IDLE_AVG);
6012
3ef62342
D		 6013 /* Setting Fixed Bias */
6014 val = VLV_OVERRIDE_EN |
6015 VLV_SOC_TDP_EN |
6016 CHV_BIAS_CPU_50_SOC_50;
6017 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6018
2b6b3a09
D		 6019 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6020
8d40c3ae
VS		 6021 /* RPS code assumes GPLL is used */
6022 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6023
742f491d 6024 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6025 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6026
3a45b05c 6027 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6028
59bad947 6029 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6030}
6031
dc97997a 6032static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6033{
e2f80391 6034 struct intel_engine_cs *engine;
2a5913a8 6035 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6036
6037 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6038
ae48434c
ID		 6039 valleyview_check_pctx(dev_priv);
6040
297b32ec
VS		 6041 gtfifodbg = I915_READ(GTFIFODBG);
6042 if (gtfifodbg) {
f7d85c1e
JB		 6043 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6044 gtfifodbg);
0a073b84
JB		 6045 I915_WRITE(GTFIFODBG, gtfifodbg);
6046 }
6047
c8d9a590 6048 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6049 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6050
160614a2
VS		 6051 /* Disable RC states. */
6052 I915_WRITE(GEN6_RC_CONTROL, 0);
6053
cad725fe 6054 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6055 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6056 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6057 I915_WRITE(GEN6_RP_UP_EI, 66000);
6058 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6059
6060 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6061
6062 I915_WRITE(GEN6_RP_CONTROL,
6063 GEN6_RP_MEDIA_TURBO |
6064 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6065 GEN6_RP_MEDIA_IS_GFX |
6066 GEN6_RP_ENABLE |
6067 GEN6_RP_UP_BUSY_AVG |
6068 GEN6_RP_DOWN_IDLE_CONT);
6069
6070 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6071 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6072 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6073
b4ac5afc 6074 for_each_engine(engine, dev_priv)
e2f80391 6075 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6076
2f0aa304 6077 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6078
6079 /* allows RC6 residency counter to work */
49798eb2 6080 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6081 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6082 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6083 VLV_MEDIA_RC6_COUNT_EN |
6084 VLV_RENDER_RC6_COUNT_EN));
31685c25 6085
dc97997a 6086 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6087 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6088
dc97997a 6089 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6090
a2b23fe0 6091 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6092
3ef62342
D		 6093 /* Setting Fixed Bias */
6094 val = VLV_OVERRIDE_EN |
6095 VLV_SOC_TDP_EN |
6096 VLV_BIAS_CPU_125_SOC_875;
6097 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6098
64936258 6099 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6100
8d40c3ae
VS		 6101 /* RPS code assumes GPLL is used */
6102 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6103
742f491d 6104 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6105 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6106
3a45b05c 6107 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6108
59bad947 6109 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6110}
6111
dde18883
ED		 6112static unsigned long intel_pxfreq(u32 vidfreq)
6113{
6114 unsigned long freq;
6115 int div = (vidfreq & 0x3f0000) >> 16;
6116 int post = (vidfreq & 0x3000) >> 12;
6117 int pre = (vidfreq & 0x7);
6118
6119 if (!pre)
6120 return 0;
6121
6122 freq = ((div * 133333) / ((1<<post) * pre));
6123
6124 return freq;
6125}
6126
eb48eb00
DV		 6127static const struct cparams {
6128 u16 i;
6129 u16 t;
6130 u16 m;
6131 u16 c;
6132} cparams[] = {
6133 { 1, 1333, 301, 28664 },
6134 { 1, 1066, 294, 24460 },
6135 { 1, 800, 294, 25192 },
6136 { 0, 1333, 276, 27605 },
6137 { 0, 1066, 276, 27605 },
6138 { 0, 800, 231, 23784 },
6139};
6140
f531dcb2 6141static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6142{
6143 u64 total_count, diff, ret;
6144 u32 count1, count2, count3, m = 0, c = 0;
6145 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6146 int i;
6147
02d71956
DV		 6148 assert_spin_locked(&mchdev_lock);
6149
20e4d407 6150 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6151
6152 /* Prevent division-by-zero if we are asking too fast.
6153 * Also, we don't get interesting results if we are polling
6154 * faster than once in 10ms, so just return the saved value
6155 * in such cases.
6156 */
6157 if (diff1 <= 10)
20e4d407 6158 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6159
6160 count1 = I915_READ(DMIEC);
6161 count2 = I915_READ(DDREC);
6162 count3 = I915_READ(CSIEC);
6163
6164 total_count = count1 + count2 + count3;
6165
6166 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6167 if (total_count < dev_priv->ips.last_count1) {
6168 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6169 diff += total_count;
6170 } else {
20e4d407 6171 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6172 }
6173
6174 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6175 if (cparams[i].i == dev_priv->ips.c_m &&
6176 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6177 m = cparams[i].m;
6178 c = cparams[i].c;
6179 break;
6180 }
6181 }
6182
6183 diff = div_u64(diff, diff1);
6184 ret = ((m * diff) + c);
6185 ret = div_u64(ret, 10);
6186
20e4d407
DV		 6187 dev_priv->ips.last_count1 = total_count;
6188 dev_priv->ips.last_time1 = now;
eb48eb00 6189
20e4d407 6190 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6191
6192 return ret;
6193}
6194
f531dcb2
CW		 6195unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6196{
6197 unsigned long val;
6198
dc97997a 6199 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6200 return 0;
6201
6202 spin_lock_irq(&mchdev_lock);
6203
6204 val = __i915_chipset_val(dev_priv);
6205
6206 spin_unlock_irq(&mchdev_lock);
6207
6208 return val;
6209}
6210
eb48eb00
DV		 6211unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6212{
6213 unsigned long m, x, b;
6214 u32 tsfs;
6215
6216 tsfs = I915_READ(TSFS);
6217
6218 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6219 x = I915_READ8(TR1);
6220
6221 b = tsfs & TSFS_INTR_MASK;
6222
6223 return ((m * x) / 127) - b;
6224}
6225
d972d6ee
MK		 6226static int _pxvid_to_vd(u8 pxvid)
6227{
6228 if (pxvid == 0)
6229 return 0;
6230
6231 if (pxvid >= 8 && pxvid < 31)
6232 pxvid = 31;
6233
6234 return (pxvid + 2) * 125;
6235}
6236
6237static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6238{
d972d6ee
MK		 6239 const int vd = _pxvid_to_vd(pxvid);
6240 const int vm = vd - 1125;
6241
dc97997a 6242 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6243 return vm > 0 ? vm : 0;
6244
6245 return vd;
eb48eb00
DV		 6246}
6247
02d71956 6248static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6249{
5ed0bdf2 6250 u64 now, diff, diffms;
eb48eb00
DV		 6251 u32 count;
6252
02d71956 6253 assert_spin_locked(&mchdev_lock);
eb48eb00 6254
5ed0bdf2
TG		 6255 now = ktime_get_raw_ns();
6256 diffms = now - dev_priv->ips.last_time2;
6257 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6258
6259 /* Don't divide by 0 */
eb48eb00
DV		 6260 if (!diffms)
6261 return;
6262
6263 count = I915_READ(GFXEC);
6264
20e4d407
DV		 6265 if (count < dev_priv->ips.last_count2) {
6266 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6267 diff += count;
6268 } else {
20e4d407 6269 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6270 }
6271
20e4d407
DV		 6272 dev_priv->ips.last_count2 = count;
6273 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6274
6275 /* More magic constants... */
6276 diff = diff * 1181;
6277 diff = div_u64(diff, diffms * 10);
20e4d407 6278 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6279}
6280
02d71956
DV		 6281void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6282{
dc97997a 6283 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6284 return;
6285
9270388e 6286 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6287
6288 __i915_update_gfx_val(dev_priv);
6289
9270388e 6290 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6291}
6292
f531dcb2 6293static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6294{
6295 unsigned long t, corr, state1, corr2, state2;
6296 u32 pxvid, ext_v;
6297
02d71956
DV		 6298 assert_spin_locked(&mchdev_lock);
6299
616847e7 6300 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6301 pxvid = (pxvid >> 24) & 0x7f;
6302 ext_v = pvid_to_extvid(dev_priv, pxvid);
6303
6304 state1 = ext_v;
6305
6306 t = i915_mch_val(dev_priv);
6307
6308 /* Revel in the empirically derived constants */
6309
6310 /* Correction factor in 1/100000 units */
6311 if (t > 80)
6312 corr = ((t * 2349) + 135940);
6313 else if (t >= 50)
6314 corr = ((t * 964) + 29317);
6315 else /* < 50 */
6316 corr = ((t * 301) + 1004);
6317
6318 corr = corr * ((150142 * state1) / 10000 - 78642);
6319 corr /= 100000;
20e4d407 6320 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6321
6322 state2 = (corr2 * state1) / 10000;
6323 state2 /= 100; /* convert to mW */
6324
02d71956 6325 __i915_update_gfx_val(dev_priv);
eb48eb00 6326
20e4d407 6327 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6328}
6329
f531dcb2
CW		 6330unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6331{
6332 unsigned long val;
6333
dc97997a 6334 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6335 return 0;
6336
6337 spin_lock_irq(&mchdev_lock);
6338
6339 val = __i915_gfx_val(dev_priv);
6340
6341 spin_unlock_irq(&mchdev_lock);
6342
6343 return val;
6344}
6345
eb48eb00
DV		 6346/**
6347 * i915_read_mch_val - return value for IPS use
6348 *
6349 * Calculate and return a value for the IPS driver to use when deciding whether
6350 * we have thermal and power headroom to increase CPU or GPU power budget.
6351 */
6352unsigned long i915_read_mch_val(void)
6353{
6354 struct drm_i915_private *dev_priv;
6355 unsigned long chipset_val, graphics_val, ret = 0;
6356
9270388e 6357 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6358 if (!i915_mch_dev)
6359 goto out_unlock;
6360 dev_priv = i915_mch_dev;
6361
f531dcb2
CW		 6362 chipset_val = __i915_chipset_val(dev_priv);
6363 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6364
6365 ret = chipset_val + graphics_val;
6366
6367out_unlock:
9270388e 6368 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6369
6370 return ret;
6371}
6372EXPORT_SYMBOL_GPL(i915_read_mch_val);
6373
6374/**
6375 * i915_gpu_raise - raise GPU frequency limit
6376 *
6377 * Raise the limit; IPS indicates we have thermal headroom.
6378 */
6379bool i915_gpu_raise(void)
6380{
6381 struct drm_i915_private *dev_priv;
6382 bool ret = true;
6383
9270388e 6384 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6385 if (!i915_mch_dev) {
6386 ret = false;
6387 goto out_unlock;
6388 }
6389 dev_priv = i915_mch_dev;
6390
20e4d407
DV		 6391 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6392 dev_priv->ips.max_delay--;
eb48eb00
DV		 6393
6394out_unlock:
9270388e 6395 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6396
6397 return ret;
6398}
6399EXPORT_SYMBOL_GPL(i915_gpu_raise);
6400
6401/**
6402 * i915_gpu_lower - lower GPU frequency limit
6403 *
6404 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6405 * frequency maximum.
6406 */
6407bool i915_gpu_lower(void)
6408{
6409 struct drm_i915_private *dev_priv;
6410 bool ret = true;
6411
9270388e 6412 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6413 if (!i915_mch_dev) {
6414 ret = false;
6415 goto out_unlock;
6416 }
6417 dev_priv = i915_mch_dev;
6418
20e4d407
DV		 6419 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6420 dev_priv->ips.max_delay++;
eb48eb00
DV		 6421
6422out_unlock:
9270388e 6423 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6424
6425 return ret;
6426}
6427EXPORT_SYMBOL_GPL(i915_gpu_lower);
6428
6429/**
6430 * i915_gpu_busy - indicate GPU business to IPS
6431 *
6432 * Tell the IPS driver whether or not the GPU is busy.
6433 */
6434bool i915_gpu_busy(void)
6435{
eb48eb00
DV		 6436 bool ret = false;
6437
9270388e 6438 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6439 if (i915_mch_dev)
6440 ret = i915_mch_dev->gt.awake;
9270388e 6441 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6442
6443 return ret;
6444}
6445EXPORT_SYMBOL_GPL(i915_gpu_busy);
6446
6447/**
6448 * i915_gpu_turbo_disable - disable graphics turbo
6449 *
6450 * Disable graphics turbo by resetting the max frequency and setting the
6451 * current frequency to the default.
6452 */
6453bool i915_gpu_turbo_disable(void)
6454{
6455 struct drm_i915_private *dev_priv;
6456 bool ret = true;
6457
9270388e 6458 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6459 if (!i915_mch_dev) {
6460 ret = false;
6461 goto out_unlock;
6462 }
6463 dev_priv = i915_mch_dev;
6464
20e4d407 6465 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6466
91d14251 6467 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6468 ret = false;
6469
6470out_unlock:
9270388e 6471 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6472
6473 return ret;
6474}
6475EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6476
6477/**
6478 * Tells the intel_ips driver that the i915 driver is now loaded, if
6479 * IPS got loaded first.
6480 *
6481 * This awkward dance is so that neither module has to depend on the
6482 * other in order for IPS to do the appropriate communication of
6483 * GPU turbo limits to i915.
6484 */
6485static void
6486ips_ping_for_i915_load(void)
6487{
6488 void (*link)(void);
6489
6490 link = symbol_get(ips_link_to_i915_driver);
6491 if (link) {
6492 link();
6493 symbol_put(ips_link_to_i915_driver);
6494 }
6495}
6496
6497void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6498{
02d71956
DV		 6499 /* We only register the i915 ips part with intel-ips once everything is
6500 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6501 spin_lock_irq(&mchdev_lock);
eb48eb00 6502 i915_mch_dev = dev_priv;
9270388e 6503 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6504
6505 ips_ping_for_i915_load();
6506}
6507
6508void intel_gpu_ips_teardown(void)
6509{
9270388e 6510 spin_lock_irq(&mchdev_lock);
eb48eb00 6511 i915_mch_dev = NULL;
9270388e 6512 spin_unlock_irq(&mchdev_lock);
eb48eb00 6513}
76c3552f 6514
dc97997a 6515static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6516{
dde18883
ED		 6517 u32 lcfuse;
6518 u8 pxw[16];
6519 int i;
6520
6521 /* Disable to program */
6522 I915_WRITE(ECR, 0);
6523 POSTING_READ(ECR);
6524
6525 /* Program energy weights for various events */
6526 I915_WRITE(SDEW, 0x15040d00);
6527 I915_WRITE(CSIEW0, 0x007f0000);
6528 I915_WRITE(CSIEW1, 0x1e220004);
6529 I915_WRITE(CSIEW2, 0x04000004);
6530
6531 for (i = 0; i < 5; i++)
616847e7 6532 I915_WRITE(PEW(i), 0);
dde18883 6533 for (i = 0; i < 3; i++)
616847e7 6534 I915_WRITE(DEW(i), 0);
dde18883
ED		 6535
6536 /* Program P-state weights to account for frequency power adjustment */
6537 for (i = 0; i < 16; i++) {
616847e7 6538 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6539 unsigned long freq = intel_pxfreq(pxvidfreq);
6540 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6541 PXVFREQ_PX_SHIFT;
6542 unsigned long val;
6543
6544 val = vid * vid;
6545 val *= (freq / 1000);
6546 val *= 255;
6547 val /= (127*127*900);
6548 if (val > 0xff)
6549 DRM_ERROR("bad pxval: %ld\n", val);
6550 pxw[i] = val;
6551 }
6552 /* Render standby states get 0 weight */
6553 pxw[14] = 0;
6554 pxw[15] = 0;
6555
6556 for (i = 0; i < 4; i++) {
6557 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6558 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6559 I915_WRITE(PXW(i), val);
dde18883
ED		 6560 }
6561
6562 /* Adjust magic regs to magic values (more experimental results) */
6563 I915_WRITE(OGW0, 0);
6564 I915_WRITE(OGW1, 0);
6565 I915_WRITE(EG0, 0x00007f00);
6566 I915_WRITE(EG1, 0x0000000e);
6567 I915_WRITE(EG2, 0x000e0000);
6568 I915_WRITE(EG3, 0x68000300);
6569 I915_WRITE(EG4, 0x42000000);
6570 I915_WRITE(EG5, 0x00140031);
6571 I915_WRITE(EG6, 0);
6572 I915_WRITE(EG7, 0);
6573
6574 for (i = 0; i < 8; i++)
616847e7 6575 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6576
6577 /* Enable PMON + select events */
6578 I915_WRITE(ECR, 0x80000019);
6579
6580 lcfuse = I915_READ(LCFUSE02);
6581
20e4d407 6582 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6583}
6584
dc97997a 6585void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6586{
b268c699
ID		 6587 /*
6588 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6589 * requirement.
6590 */
6591 if (!i915.enable_rc6) {
6592 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6593 intel_runtime_pm_get(dev_priv);
6594 }
e6069ca8 6595
b5163dbb 6596 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6597 mutex_lock(&dev_priv->rps.hw_lock);
6598
6599 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6600 if (IS_CHERRYVIEW(dev_priv))
6601 cherryview_init_gt_powersave(dev_priv);
6602 else if (IS_VALLEYVIEW(dev_priv))
6603 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6604 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6605 gen6_init_rps_frequencies(dev_priv);
6606
6607 /* Derive initial user preferences/limits from the hardware limits */
6608 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6609 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6610
6611 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6612 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6613
6614 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6615 dev_priv->rps.min_freq_softlimit =
6616 max_t(int,
6617 dev_priv->rps.efficient_freq,
6618 intel_freq_opcode(dev_priv, 450));
6619
99ac9612
CW		 6620 /* After setting max-softlimit, find the overclock max freq */
6621 if (IS_GEN6(dev_priv) ||
6622 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6623 u32 params = 0;
6624
6625 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6626 if (params & BIT(31)) { /* OC supported */
6627 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6628 (dev_priv->rps.max_freq & 0xff) * 50,
6629 (params & 0xff) * 50);
6630 dev_priv->rps.max_freq = params & 0xff;
6631 }
6632 }
6633
29ecd78d
CW		 6634 /* Finally allow us to boost to max by default */
6635 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6636
773ea9a8 6637 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6638 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6639
6640 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6641}
6642
dc97997a 6643void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6644{
8dac1e1f 6645 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6646 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6647
6648 if (!i915.enable_rc6)
6649 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6650}
6651
54b4f68f
CW		 6652/**
6653 * intel_suspend_gt_powersave - suspend PM work and helper threads
6654 * @dev_priv: i915 device
6655 *
6656 * We don't want to disable RC6 or other features here, we just want
6657 * to make sure any work we've queued has finished and won't bother
6658 * us while we're suspended.
6659 */
6660void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6661{
6662 if (INTEL_GEN(dev_priv) < 6)
6663 return;
6664
6665 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6666 intel_runtime_pm_put(dev_priv);
6667
6668 /* gen6_rps_idle() will be called later to disable interrupts */
6669}
6670
b7137e0c
CW		 6671void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6672{
6673 dev_priv->rps.enabled = true; /* force disabling */
6674 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6675
6676 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6677}
6678
dc97997a 6679void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6680{
b7137e0c
CW		 6681 if (!READ_ONCE(dev_priv->rps.enabled))
6682 return;
e494837a 6683
b7137e0c 6684 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6685
b7137e0c
CW		 6686 if (INTEL_GEN(dev_priv) >= 9) {
6687 gen9_disable_rc6(dev_priv);
6688 gen9_disable_rps(dev_priv);
6689 } else if (IS_CHERRYVIEW(dev_priv)) {
6690 cherryview_disable_rps(dev_priv);
6691 } else if (IS_VALLEYVIEW(dev_priv)) {
6692 valleyview_disable_rps(dev_priv);
6693 } else if (INTEL_GEN(dev_priv) >= 6) {
6694 gen6_disable_rps(dev_priv);
6695 } else if (IS_IRONLAKE_M(dev_priv)) {
6696 ironlake_disable_drps(dev_priv);
930ebb46 6697 }
b7137e0c
CW		 6698
6699 dev_priv->rps.enabled = false;
6700 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6701}
6702
b7137e0c 6703void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6704{
54b4f68f
CW		 6705 /* We shouldn't be disabling as we submit, so this should be less
6706 * racy than it appears!
6707 */
b7137e0c
CW		 6708 if (READ_ONCE(dev_priv->rps.enabled))
6709 return;
1a01ab3b 6710
b7137e0c
CW		 6711 /* Powersaving is controlled by the host when inside a VM */
6712 if (intel_vgpu_active(dev_priv))
6713 return;
0a073b84 6714
b7137e0c 6715 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6716
6717 if (IS_CHERRYVIEW(dev_priv)) {
6718 cherryview_enable_rps(dev_priv);
6719 } else if (IS_VALLEYVIEW(dev_priv)) {
6720 valleyview_enable_rps(dev_priv);
b7137e0c 6721 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6722 gen9_enable_rc6(dev_priv);
6723 gen9_enable_rps(dev_priv);
6724 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6725 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6726 } else if (IS_BROADWELL(dev_priv)) {
6727 gen8_enable_rps(dev_priv);
fb7404e8 6728 gen6_update_ring_freq(dev_priv);
b7137e0c 6729 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6730 gen6_enable_rps(dev_priv);
fb7404e8 6731 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6732 } else if (IS_IRONLAKE_M(dev_priv)) {
6733 ironlake_enable_drps(dev_priv);
6734 intel_init_emon(dev_priv);
0a073b84 6735 }
aed242ff
CW		 6736
6737 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6738 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6739
6740 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6741 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6742
54b4f68f 6743 dev_priv->rps.enabled = true;
b7137e0c
CW		 6744 mutex_unlock(&dev_priv->rps.hw_lock);
6745}
3cc134e3 6746
54b4f68f
CW		 6747static void __intel_autoenable_gt_powersave(struct work_struct *work)
6748{
6749 struct drm_i915_private *dev_priv =
6750 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6751 struct intel_engine_cs *rcs;
6752 struct drm_i915_gem_request *req;
6753
6754 if (READ_ONCE(dev_priv->rps.enabled))
6755 goto out;
6756
6757 rcs = &dev_priv->engine[RCS];
6758 if (rcs->last_context)
6759 goto out;
6760
6761 if (!rcs->init_context)
6762 goto out;
6763
6764 mutex_lock(&dev_priv->drm.struct_mutex);
6765
6766 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6767 if (IS_ERR(req))
6768 goto unlock;
6769
6770 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6771 rcs->init_context(req);
6772
6773 /* Mark the device busy, calling intel_enable_gt_powersave() */
6774 i915_add_request_no_flush(req);
6775
6776unlock:
6777 mutex_unlock(&dev_priv->drm.struct_mutex);
6778out:
6779 intel_runtime_pm_put(dev_priv);
6780}
6781
6782void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6783{
6784 if (READ_ONCE(dev_priv->rps.enabled))
6785 return;
6786
6787 if (IS_IRONLAKE_M(dev_priv)) {
6788 ironlake_enable_drps(dev_priv);
54b4f68f 6789 intel_init_emon(dev_priv);
54b4f68f
CW		 6790 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6791 /*
6792 * PCU communication is slow and this doesn't need to be
6793 * done at any specific time, so do this out of our fast path
6794 * to make resume and init faster.
6795 *
6796 * We depend on the HW RC6 power context save/restore
6797 * mechanism when entering D3 through runtime PM suspend. So
6798 * disable RPM until RPS/RC6 is properly setup. We can only
6799 * get here via the driver load/system resume/runtime resume
6800 * paths, so the _noresume version is enough (and in case of
6801 * runtime resume it's necessary).
6802 */
6803 if (queue_delayed_work(dev_priv->wq,
6804 &dev_priv->rps.autoenable_work,
6805 round_jiffies_up_relative(HZ)))
6806 intel_runtime_pm_get_noresume(dev_priv);
6807 }
6808}
6809
3107bd48
DV		 6810static void ibx_init_clock_gating(struct drm_device *dev)
6811{
fac5e23e 6812 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6813
6814 /*
6815 * On Ibex Peak and Cougar Point, we need to disable clock
6816 * gating for the panel power sequencer or it will fail to
6817 * start up when no ports are active.
6818 */
6819 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6820}
6821
0e088b8f
VS		 6822static void g4x_disable_trickle_feed(struct drm_device *dev)
6823{
fac5e23e 6824 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6825 enum pipe pipe;
0e088b8f 6826
055e393f 6827 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6828 I915_WRITE(DSPCNTR(pipe),
6829 I915_READ(DSPCNTR(pipe)) |
6830 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6831
6832 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6833 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6834 }
6835}
6836
017636cc
VS		 6837static void ilk_init_lp_watermarks(struct drm_device *dev)
6838{
fac5e23e 6839 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6840
6841 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6842 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6843 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6844
6845 /*
6846 * Don't touch WM1S_LP_EN here.
6847 * Doing so could cause underruns.
6848 */
6849}
6850
1fa61106 6851static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6852{
fac5e23e 6853 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6854 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6855
f1e8fa56
DL		 6856 /*
6857 * Required for FBC
6858 * WaFbcDisableDpfcClockGating:ilk
6859 */
4d47e4f5
DL		 6860 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6861 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6862 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6863
6864 I915_WRITE(PCH_3DCGDIS0,
6865 MARIUNIT_CLOCK_GATE_DISABLE |
6866 SVSMUNIT_CLOCK_GATE_DISABLE);
6867 I915_WRITE(PCH_3DCGDIS1,
6868 VFMUNIT_CLOCK_GATE_DISABLE);
6869
6f1d69b0
ED		 6870 /*
6871 * According to the spec the following bits should be set in
6872 * order to enable memory self-refresh
6873 * The bit 22/21 of 0x42004
6874 * The bit 5 of 0x42020
6875 * The bit 15 of 0x45000
6876 */
6877 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6878 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6879 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6880 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6881 I915_WRITE(DISP_ARB_CTL,
6882 (I915_READ(DISP_ARB_CTL) |
6883 DISP_FBC_WM_DIS));
017636cc
VS		 6884
6885 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6886
6887 /*
6888 * Based on the document from hardware guys the following bits
6889 * should be set unconditionally in order to enable FBC.
6890 * The bit 22 of 0x42000
6891 * The bit 22 of 0x42004
6892 * The bit 7,8,9 of 0x42020.
6893 */
6894 if (IS_IRONLAKE_M(dev)) {
4bb35334 6895 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6896 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6897 I915_READ(ILK_DISPLAY_CHICKEN1) |
6898 ILK_FBCQ_DIS);
6899 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6900 I915_READ(ILK_DISPLAY_CHICKEN2) |
6901 ILK_DPARB_GATE);
6f1d69b0
ED		 6902 }
6903
4d47e4f5
DL		 6904 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6905
6f1d69b0
ED		 6906 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6907 I915_READ(ILK_DISPLAY_CHICKEN2) |
6908 ILK_ELPIN_409_SELECT);
6909 I915_WRITE(_3D_CHICKEN2,
6910 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6911 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6912
ecdb4eb7 6913 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6914 I915_WRITE(CACHE_MODE_0,
6915 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6916
4e04632e
AG		 6917 /* WaDisable_RenderCache_OperationalFlush:ilk */
6918 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6919
0e088b8f 6920 g4x_disable_trickle_feed(dev);
bdad2b2f 6921
3107bd48
DV		 6922 ibx_init_clock_gating(dev);
6923}
6924
6925static void cpt_init_clock_gating(struct drm_device *dev)
6926{
fac5e23e 6927 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6928 int pipe;
3f704fa2 6929 uint32_t val;
3107bd48
DV		 6930
6931 /*
6932 * On Ibex Peak and Cougar Point, we need to disable clock
6933 * gating for the panel power sequencer or it will fail to
6934 * start up when no ports are active.
6935 */
cd664078
JB		 6936 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6937 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6938 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6939 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6940 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6941 /* The below fixes the weird display corruption, a few pixels shifted
6942 * downward, on (only) LVDS of some HP laptops with IVY.
6943 */
055e393f 6944 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6945 val = I915_READ(TRANS_CHICKEN2(pipe));
6946 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6947 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6948 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6949 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6950 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6951 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6952 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6953 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6954 }
3107bd48 6955 /* WADP0ClockGatingDisable */
055e393f 6956 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6957 I915_WRITE(TRANS_CHICKEN1(pipe),
6958 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6959 }
6f1d69b0
ED		 6960}
6961
1d7aaa0c
DV		 6962static void gen6_check_mch_setup(struct drm_device *dev)
6963{
fac5e23e 6964 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 6965 uint32_t tmp;
6966
6967 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6968 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6969 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6970 tmp);
1d7aaa0c
DV		 6971}
6972
1fa61106 6973static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 6974{
fac5e23e 6975 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6976 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6977
231e54f6 6978 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6979
6980 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6981 I915_READ(ILK_DISPLAY_CHICKEN2) |
6982 ILK_ELPIN_409_SELECT);
6983
ecdb4eb7 6984 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6985 I915_WRITE(_3D_CHICKEN,
6986 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6987
4e04632e
AG		 6988 /* WaDisable_RenderCache_OperationalFlush:snb */
6989 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6990
8d85d272
VS		 6991 /*
6992 * BSpec recoomends 8x4 when MSAA is used,
6993 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6994 *
6995 * Note that PS/WM thread counts depend on the WIZ hashing
6996 * disable bit, which we don't touch here, but it's good
6997 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6998 */
6999 I915_WRITE(GEN6_GT_MODE,
98533251 7000 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7001
017636cc 7002 ilk_init_lp_watermarks(dev);
6f1d69b0 7003
6f1d69b0 7004 I915_WRITE(CACHE_MODE_0,
50743298 7005 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7006
7007 I915_WRITE(GEN6_UCGCTL1,
7008 I915_READ(GEN6_UCGCTL1) |
7009 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7010 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7011
7012 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7013 * gating disable must be set. Failure to set it results in
7014 * flickering pixels due to Z write ordering failures after
7015 * some amount of runtime in the Mesa "fire" demo, and Unigine
7016 * Sanctuary and Tropics, and apparently anything else with
7017 * alpha test or pixel discard.
7018 *
7019 * According to the spec, bit 11 (RCCUNIT) must also be set,
7020 * but we didn't debug actual testcases to find it out.
0f846f81 7021 *
ef59318c
VS		 7022 * WaDisableRCCUnitClockGating:snb
7023 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7024 */
7025 I915_WRITE(GEN6_UCGCTL2,
7026 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7027 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7028
5eb146dd 7029 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7030 I915_WRITE(_3D_CHICKEN3,
7031 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7032
e927ecde
VS		 7033 /*
7034 * Bspec says:
7035 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7036 * 3DSTATE_SF number of SF output attributes is more than 16."
7037 */
7038 I915_WRITE(_3D_CHICKEN3,
7039 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7040
6f1d69b0
ED		 7041 /*
7042 * According to the spec the following bits should be
7043 * set in order to enable memory self-refresh and fbc:
7044 * The bit21 and bit22 of 0x42000
7045 * The bit21 and bit22 of 0x42004
7046 * The bit5 and bit7 of 0x42020
7047 * The bit14 of 0x70180
7048 * The bit14 of 0x71180
4bb35334
DL		 7049 *
7050 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7051 */
7052 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7053 I915_READ(ILK_DISPLAY_CHICKEN1) |
7054 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7055 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7056 I915_READ(ILK_DISPLAY_CHICKEN2) |
7057 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7058 I915_WRITE(ILK_DSPCLK_GATE_D,
7059 I915_READ(ILK_DSPCLK_GATE_D) |
7060 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7061 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7062
0e088b8f 7063 g4x_disable_trickle_feed(dev);
f8f2ac9a 7064
3107bd48 7065 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7066
7067 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7068}
7069
7070static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7071{
7072 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7073
3aad9059 7074 /*
46680e0a 7075 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7076 *
7077 * This actually overrides the dispatch
7078 * mode for all thread types.
7079 */
6f1d69b0
ED		 7080 reg &= ~GEN7_FF_SCHED_MASK;
7081 reg |= GEN7_FF_TS_SCHED_HW;
7082 reg |= GEN7_FF_VS_SCHED_HW;
7083 reg |= GEN7_FF_DS_SCHED_HW;
7084
7085 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7086}
7087
17a303ec
PZ		 7088static void lpt_init_clock_gating(struct drm_device *dev)
7089{
fac5e23e 7090 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7091
7092 /*
7093 * TODO: this bit should only be enabled when really needed, then
7094 * disabled when not needed anymore in order to save power.
7095 */
c2699524 7096 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 7097 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7098 I915_READ(SOUTH_DSPCLK_GATE_D) |
7099 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7100
7101 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7102 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7103 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7104 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7105}
7106
7d708ee4
ID		 7107static void lpt_suspend_hw(struct drm_device *dev)
7108{
fac5e23e 7109 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7110
c2699524 7111 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 7112 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7113
7114 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7115 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7116 }
7117}
7118
450174fe
ID		 7119static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7120 int general_prio_credits,
7121 int high_prio_credits)
7122{
7123 u32 misccpctl;
7124
7125 /* WaTempDisableDOPClkGating:bdw */
7126 misccpctl = I915_READ(GEN7_MISCCPCTL);
7127 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7128
7129 I915_WRITE(GEN8_L3SQCREG1,
7130 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7131 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7132
7133 /*
7134 * Wait at least 100 clocks before re-enabling clock gating.
7135 * See the definition of L3SQCREG1 in BSpec.
7136 */
7137 POSTING_READ(GEN8_L3SQCREG1);
7138 udelay(1);
7139 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7140}
7141
9498dba7
MK		 7142static void kabylake_init_clock_gating(struct drm_device *dev)
7143{
9146f308 7144 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7145
b033bb6d 7146 gen9_init_clock_gating(dev);
9498dba7
MK		 7147
7148 /* WaDisableSDEUnitClockGating:kbl */
7149 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7150 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7151 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7152
7153 /* WaDisableGamClockGating:kbl */
7154 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7155 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7156 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7157
7158 /* WaFbcNukeOnHostModify:kbl */
7159 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7160 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7161}
7162
dc00b6a0
DV		 7163static void skylake_init_clock_gating(struct drm_device *dev)
7164{
c584e2d3 7165 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7166
b033bb6d 7167 gen9_init_clock_gating(dev);
44fff99f
MK		 7168
7169 /* WAC6entrylatency:skl */
7170 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7171 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7172
7173 /* WaFbcNukeOnHostModify:skl */
7174 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7175 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7176}
7177
47c2bd97 7178static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7179{
fac5e23e 7180 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7181 enum pipe pipe;
1020a5c2 7182
7ad0dbab 7183 ilk_init_lp_watermarks(dev);
50ed5fbd 7184
ab57fff1 7185 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7186 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7187
ab57fff1 7188 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7189 I915_WRITE(CHICKEN_PAR1_1,
7190 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7191
ab57fff1 7192 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7193 for_each_pipe(dev_priv, pipe) {
07d27e20 7194 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7195 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7196 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7197 }
63801f21 7198
ab57fff1
BW		 7199 /* WaVSRefCountFullforceMissDisable:bdw */
7200 /* WaDSRefCountFullforceMissDisable:bdw */
7201 I915_WRITE(GEN7_FF_THREAD_MODE,
7202 I915_READ(GEN7_FF_THREAD_MODE) &
7203 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7204
295e8bb7
VS		 7205 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7206 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7207
7208 /* WaDisableSDEUnitClockGating:bdw */
7209 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7210 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7211
450174fe
ID		 7212 /* WaProgramL3SqcReg1Default:bdw */
7213 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7214
6d50b065
VS		 7215 /*
7216 * WaGttCachingOffByDefault:bdw
7217 * GTT cache may not work with big pages, so if those
7218 * are ever enabled GTT cache may need to be disabled.
7219 */
7220 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7221
17e0adf0
MK		 7222 /* WaKVMNotificationOnConfigChange:bdw */
7223 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7224 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7225
89d6b2b8 7226 lpt_init_clock_gating(dev);
1020a5c2
BW		 7227}
7228
cad2a2d7
ED		 7229static void haswell_init_clock_gating(struct drm_device *dev)
7230{
fac5e23e 7231 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7232
017636cc 7233 ilk_init_lp_watermarks(dev);
cad2a2d7 7234
f3fc4884
FJ		 7235 /* L3 caching of data atomics doesn't work -- disable it. */
7236 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7237 I915_WRITE(HSW_ROW_CHICKEN3,
7238 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7239
ecdb4eb7 7240 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7241 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7242 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7243 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7244
e36ea7ff
VS		 7245 /* WaVSRefCountFullforceMissDisable:hsw */
7246 I915_WRITE(GEN7_FF_THREAD_MODE,
7247 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7248
4e04632e
AG		 7249 /* WaDisable_RenderCache_OperationalFlush:hsw */
7250 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7251
fe27c606
CW		 7252 /* enable HiZ Raw Stall Optimization */
7253 I915_WRITE(CACHE_MODE_0_GEN7,
7254 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7255
ecdb4eb7 7256 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7257 I915_WRITE(CACHE_MODE_1,
7258 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7259
a12c4967
VS		 7260 /*
7261 * BSpec recommends 8x4 when MSAA is used,
7262 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7263 *
7264 * Note that PS/WM thread counts depend on the WIZ hashing
7265 * disable bit, which we don't touch here, but it's good
7266 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7267 */
7268 I915_WRITE(GEN7_GT_MODE,
98533251 7269 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7270
94411593
KG		 7271 /* WaSampleCChickenBitEnable:hsw */
7272 I915_WRITE(HALF_SLICE_CHICKEN3,
7273 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7274
ecdb4eb7 7275 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7276 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7277
90a88643
PZ		 7278 /* WaRsPkgCStateDisplayPMReq:hsw */
7279 I915_WRITE(CHICKEN_PAR1_1,
7280 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7281
17a303ec 7282 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7283}
7284
1fa61106 7285static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7286{
fac5e23e 7287 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7288 uint32_t snpcr;
6f1d69b0 7289
017636cc 7290 ilk_init_lp_watermarks(dev);
6f1d69b0 7291
231e54f6 7292 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7293
ecdb4eb7 7294 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7295 I915_WRITE(_3D_CHICKEN3,
7296 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7297
ecdb4eb7 7298 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7299 I915_WRITE(IVB_CHICKEN3,
7300 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7301 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7302
ecdb4eb7 7303 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7304 if (IS_IVB_GT1(dev))
7305 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7306 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7307
4e04632e
AG		 7308 /* WaDisable_RenderCache_OperationalFlush:ivb */
7309 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7310
ecdb4eb7 7311 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7312 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7313 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7314
ecdb4eb7 7315 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7316 I915_WRITE(GEN7_L3CNTLREG1,
7317 GEN7_WA_FOR_GEN7_L3_CONTROL);
7318 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7319 GEN7_WA_L3_CHICKEN_MODE);
7320 if (IS_IVB_GT1(dev))
7321 I915_WRITE(GEN7_ROW_CHICKEN2,
7322 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7323 else {
7324 /* must write both registers */
7325 I915_WRITE(GEN7_ROW_CHICKEN2,
7326 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7327 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7328 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7329 }
6f1d69b0 7330
ecdb4eb7 7331 /* WaForceL3Serialization:ivb */
61939d97
JB		 7332 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7333 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7334
1b80a19a 7335 /*
0f846f81 7336 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7337 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7338 */
7339 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7340 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7341
ecdb4eb7 7342 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7343 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7344 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7345 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7346
0e088b8f 7347 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7348
7349 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7350
22721343
CW		 7351 if (0) { /* causes HiZ corruption on ivb:gt1 */
7352 /* enable HiZ Raw Stall Optimization */
7353 I915_WRITE(CACHE_MODE_0_GEN7,
7354 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7355 }
116f2b6d 7356
ecdb4eb7 7357 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7358 I915_WRITE(CACHE_MODE_1,
7359 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7360
a607c1a4
VS		 7361 /*
7362 * BSpec recommends 8x4 when MSAA is used,
7363 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7364 *
7365 * Note that PS/WM thread counts depend on the WIZ hashing
7366 * disable bit, which we don't touch here, but it's good
7367 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7368 */
7369 I915_WRITE(GEN7_GT_MODE,
98533251 7370 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7371
20848223
BW		 7372 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7373 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7374 snpcr |= GEN6_MBC_SNPCR_MED;
7375 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7376
ab5c608b
BW		 7377 if (!HAS_PCH_NOP(dev))
7378 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7379
7380 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7381}
7382
1fa61106 7383static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7384{
fac5e23e 7385 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7386
ecdb4eb7 7387 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7388 I915_WRITE(_3D_CHICKEN3,
7389 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7390
ecdb4eb7 7391 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7392 I915_WRITE(IVB_CHICKEN3,
7393 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7394 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7395
fad7d36e 7396 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7397 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7398 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7399 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7400 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7401
4e04632e
AG		 7402 /* WaDisable_RenderCache_OperationalFlush:vlv */
7403 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7404
ecdb4eb7 7405 /* WaForceL3Serialization:vlv */
61939d97
JB		 7406 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7407 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7408
ecdb4eb7 7409 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7410 I915_WRITE(GEN7_ROW_CHICKEN2,
7411 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7412
ecdb4eb7 7413 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7414 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7415 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7416 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7417
46680e0a
VS		 7418 gen7_setup_fixed_func_scheduler(dev_priv);
7419
3c0edaeb 7420 /*
0f846f81 7421 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7422 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7423 */
7424 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7425 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7426
c98f5062
AG		 7427 /* WaDisableL3Bank2xClockGate:vlv
7428 * Disabling L3 clock gating- MMIO 940c[25] = 1
7429 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7430 I915_WRITE(GEN7_UCGCTL4,
7431 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7432
afd58e79
VS		 7433 /*
7434 * BSpec says this must be set, even though
7435 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7436 */
6b26c86d
DV		 7437 I915_WRITE(CACHE_MODE_1,
7438 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7439
da2518f9
VS		 7440 /*
7441 * BSpec recommends 8x4 when MSAA is used,
7442 * however in practice 16x4 seems fastest.
7443 *
7444 * Note that PS/WM thread counts depend on the WIZ hashing
7445 * disable bit, which we don't touch here, but it's good
7446 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7447 */
7448 I915_WRITE(GEN7_GT_MODE,
7449 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7450
031994ee
VS		 7451 /*
7452 * WaIncreaseL3CreditsForVLVB0:vlv
7453 * This is the hardware default actually.
7454 */
7455 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7456
2d809570 7457 /*
ecdb4eb7 7458 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7459 * Disable clock gating on th GCFG unit to prevent a delay
7460 * in the reporting of vblank events.
7461 */
7a0d1eed 7462 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7463}
7464
a4565da8
VS		 7465static void cherryview_init_clock_gating(struct drm_device *dev)
7466{
fac5e23e 7467 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7468
232ce337
VS		 7469 /* WaVSRefCountFullforceMissDisable:chv */
7470 /* WaDSRefCountFullforceMissDisable:chv */
7471 I915_WRITE(GEN7_FF_THREAD_MODE,
7472 I915_READ(GEN7_FF_THREAD_MODE) &
7473 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7474
7475 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7476 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7477 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7478
7479 /* WaDisableCSUnitClockGating:chv */
7480 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7481 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7482
7483 /* WaDisableSDEUnitClockGating:chv */
7484 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7485 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7486
450174fe
ID		 7487 /*
7488 * WaProgramL3SqcReg1Default:chv
7489 * See gfxspecs/Related Documents/Performance Guide/
7490 * LSQC Setting Recommendations.
7491 */
7492 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7493
6d50b065
VS		 7494 /*
7495 * GTT cache may not work with big pages, so if those
7496 * are ever enabled GTT cache may need to be disabled.
7497 */
7498 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7499}
7500
1fa61106 7501static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7502{
fac5e23e 7503 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7504 uint32_t dspclk_gate;
7505
7506 I915_WRITE(RENCLK_GATE_D1, 0);
7507 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7508 GS_UNIT_CLOCK_GATE_DISABLE |
7509 CL_UNIT_CLOCK_GATE_DISABLE);
7510 I915_WRITE(RAMCLK_GATE_D, 0);
7511 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7512 OVRUNIT_CLOCK_GATE_DISABLE |
7513 OVCUNIT_CLOCK_GATE_DISABLE;
7514 if (IS_GM45(dev))
7515 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7516 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7517
7518 /* WaDisableRenderCachePipelinedFlush */
7519 I915_WRITE(CACHE_MODE_0,
7520 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7521
4e04632e
AG		 7522 /* WaDisable_RenderCache_OperationalFlush:g4x */
7523 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7524
0e088b8f 7525 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7526}
7527
1fa61106 7528static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7529{
fac5e23e 7530 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7531
7532 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7533 I915_WRITE(RENCLK_GATE_D2, 0);
7534 I915_WRITE(DSPCLK_GATE_D, 0);
7535 I915_WRITE(RAMCLK_GATE_D, 0);
7536 I915_WRITE16(DEUC, 0);
20f94967
VS		 7537 I915_WRITE(MI_ARB_STATE,
7538 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7539
7540 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7541 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7542}
7543
1fa61106 7544static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7545{
fac5e23e 7546 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7547
7548 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7549 I965_RCC_CLOCK_GATE_DISABLE |
7550 I965_RCPB_CLOCK_GATE_DISABLE |
7551 I965_ISC_CLOCK_GATE_DISABLE |
7552 I965_FBC_CLOCK_GATE_DISABLE);
7553 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7554 I915_WRITE(MI_ARB_STATE,
7555 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7556
7557 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7558 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7559}
7560
1fa61106 7561static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7562{
fac5e23e 7563 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7564 u32 dstate = I915_READ(D_STATE);
7565
7566 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7567 DSTATE_DOT_CLOCK_GATING;
7568 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7569
7570 if (IS_PINEVIEW(dev))
7571 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7572
7573 /* IIR "flip pending" means done if this bit is set */
7574 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7575
7576 /* interrupts should cause a wake up from C3 */
3299254f 7577 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7578
7579 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7580 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7581
7582 I915_WRITE(MI_ARB_STATE,
7583 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7584}
7585
1fa61106 7586static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7587{
fac5e23e 7588 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7589
7590 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7591
7592 /* interrupts should cause a wake up from C3 */
7593 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7594 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7595
7596 I915_WRITE(MEM_MODE,
7597 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7598}
7599
1fa61106 7600static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7601{
fac5e23e 7602 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7603
7604 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7605
7606 I915_WRITE(MEM_MODE,
7607 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7608 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7609}
7610
6f1d69b0
ED		 7611void intel_init_clock_gating(struct drm_device *dev)
7612{
fac5e23e 7613 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7614
bb400da9 7615 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7616}
7617
7d708ee4
ID		 7618void intel_suspend_hw(struct drm_device *dev)
7619{
7620 if (HAS_PCH_LPT(dev))
7621 lpt_suspend_hw(dev);
7622}
7623
bb400da9
ID		 7624static void nop_init_clock_gating(struct drm_device *dev)
7625{
7626 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7627}
7628
7629/**
7630 * intel_init_clock_gating_hooks - setup the clock gating hooks
7631 * @dev_priv: device private
7632 *
7633 * Setup the hooks that configure which clocks of a given platform can be
7634 * gated and also apply various GT and display specific workarounds for these
7635 * platforms. Note that some GT specific workarounds are applied separately
7636 * when GPU contexts or batchbuffers start their execution.
7637 */
7638void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7639{
7640 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7641 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7642 else if (IS_KABYLAKE(dev_priv))
9498dba7 7643 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7644 else if (IS_BROXTON(dev_priv))
7645 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7646 else if (IS_BROADWELL(dev_priv))
7647 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7648 else if (IS_CHERRYVIEW(dev_priv))
7649 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7650 else if (IS_HASWELL(dev_priv))
7651 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7652 else if (IS_IVYBRIDGE(dev_priv))
7653 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7654 else if (IS_VALLEYVIEW(dev_priv))
7655 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7656 else if (IS_GEN6(dev_priv))
7657 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7658 else if (IS_GEN5(dev_priv))
7659 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7660 else if (IS_G4X(dev_priv))
7661 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7662 else if (IS_CRESTLINE(dev_priv))
7663 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7664 else if (IS_BROADWATER(dev_priv))
7665 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7666 else if (IS_GEN3(dev_priv))
7667 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7668 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7669 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7670 else if (IS_GEN2(dev_priv))
7671 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7672 else {
7673 MISSING_CASE(INTEL_DEVID(dev_priv));
7674 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7675 }
7676}
7677
1fa61106
ED		 7678/* Set up chip specific power management-related functions */
7679void intel_init_pm(struct drm_device *dev)
7680{
fac5e23e 7681 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7682
7ff0ebcc 7683 intel_fbc_init(dev_priv);
1fa61106 7684
c921aba8
DV		 7685 /* For cxsr */
7686 if (IS_PINEVIEW(dev))
7687 i915_pineview_get_mem_freq(dev);
7688 else if (IS_GEN5(dev))
7689 i915_ironlake_get_mem_freq(dev);
7690
1fa61106 7691 /* For FIFO watermark updates */
f5ed50cb 7692 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7693 skl_setup_wm_latency(dev);
2d41c0b5 7694 dev_priv->display.update_wm = skl_update_wm;
98d39494 7695 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7696 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7697 ilk_setup_wm_latency(dev);
53615a5e 7698
bd602544
VS		 7699 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7700 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7701 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7702 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7703 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7704 dev_priv->display.compute_intermediate_wm =
7705 ilk_compute_intermediate_wm;
7706 dev_priv->display.initial_watermarks =
7707 ilk_initial_watermarks;
7708 dev_priv->display.optimize_watermarks =
7709 ilk_optimize_watermarks;
bd602544
VS		 7710 } else {
7711 DRM_DEBUG_KMS("Failed to read display plane latency. "
7712 "Disable CxSR\n");
7713 }
a4565da8 7714 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7715 vlv_setup_wm_latency(dev);
262cd2e1 7716 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7717 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7718 vlv_setup_wm_latency(dev);
26e1fe4f 7719 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7720 } else if (IS_PINEVIEW(dev)) {
7721 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7722 dev_priv->is_ddr3,
7723 dev_priv->fsb_freq,
7724 dev_priv->mem_freq)) {
7725 DRM_INFO("failed to find known CxSR latency "
7726 "(found ddr%s fsb freq %d, mem freq %d), "
7727 "disabling CxSR\n",
7728 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7729 dev_priv->fsb_freq, dev_priv->mem_freq);
7730 /* Disable CxSR and never update its watermark again */
5209b1f4 7731 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7732 dev_priv->display.update_wm = NULL;
7733 } else
7734 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7735 } else if (IS_G4X(dev)) {
7736 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7737 } else if (IS_GEN4(dev)) {
7738 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7739 } else if (IS_GEN3(dev)) {
7740 dev_priv->display.update_wm = i9xx_update_wm;
7741 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7742 } else if (IS_GEN2(dev)) {
7743 if (INTEL_INFO(dev)->num_pipes == 1) {
7744 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7745 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7746 } else {
7747 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7748 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7749 }
feb56b93
DV		 7750 } else {
7751 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7752 }
7753}
7754
87660502
L		 7755static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7756{
7757 uint32_t flags =
7758 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7759
7760 switch (flags) {
7761 case GEN6_PCODE_SUCCESS:
7762 return 0;
7763 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7764 case GEN6_PCODE_ILLEGAL_CMD:
7765 return -ENXIO;
7766 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7767 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7768 return -EOVERFLOW;
7769 case GEN6_PCODE_TIMEOUT:
7770 return -ETIMEDOUT;
7771 default:
7772 MISSING_CASE(flags)
7773 return 0;
7774 }
7775}
7776
7777static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7778{
7779 uint32_t flags =
7780 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7781
7782 switch (flags) {
7783 case GEN6_PCODE_SUCCESS:
7784 return 0;
7785 case GEN6_PCODE_ILLEGAL_CMD:
7786 return -ENXIO;
7787 case GEN7_PCODE_TIMEOUT:
7788 return -ETIMEDOUT;
7789 case GEN7_PCODE_ILLEGAL_DATA:
7790 return -EINVAL;
7791 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7792 return -EOVERFLOW;
7793 default:
7794 MISSING_CASE(flags);
7795 return 0;
7796 }
7797}
7798
151a49d0 7799int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7800{
87660502
L		 7801 int status;
7802
4fc688ce 7803 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7804
3f5582dd
CW		 7805 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7806 * use te fw I915_READ variants to reduce the amount of work
7807 * required when reading/writing.
7808 */
7809
7810 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7811 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7812 return -EAGAIN;
7813 }
7814
3f5582dd
CW		 7815 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7816 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7817 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7818
3f5582dd
CW		 7819 if (intel_wait_for_register_fw(dev_priv,
7820 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7821 500)) {
42c0526c
BW		 7822 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7823 return -ETIMEDOUT;
7824 }
7825
3f5582dd
CW		 7826 *val = I915_READ_FW(GEN6_PCODE_DATA);
7827 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7828
87660502
L		 7829 if (INTEL_GEN(dev_priv) > 6)
7830 status = gen7_check_mailbox_status(dev_priv);
7831 else
7832 status = gen6_check_mailbox_status(dev_priv);
7833
7834 if (status) {
7835 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7836 status);
7837 return status;
7838 }
7839
42c0526c
BW		 7840 return 0;
7841}
7842
3f5582dd 7843int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7844 u32 mbox, u32 val)
42c0526c 7845{
87660502
L		 7846 int status;
7847
4fc688ce 7848 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7849
3f5582dd
CW		 7850 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7851 * use te fw I915_READ variants to reduce the amount of work
7852 * required when reading/writing.
7853 */
7854
7855 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7856 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7857 return -EAGAIN;
7858 }
7859
3f5582dd
CW		 7860 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7861 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7862
3f5582dd
CW		 7863 if (intel_wait_for_register_fw(dev_priv,
7864 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7865 500)) {
42c0526c
BW		 7866 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7867 return -ETIMEDOUT;
7868 }
7869
3f5582dd 7870 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7871
87660502
L		 7872 if (INTEL_GEN(dev_priv) > 6)
7873 status = gen7_check_mailbox_status(dev_priv);
7874 else
7875 status = gen6_check_mailbox_status(dev_priv);
7876
7877 if (status) {
7878 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7879 status);
7880 return status;
7881 }
7882
42c0526c
BW		 7883 return 0;
7884}
a0e4e199 7885
dd06f88c
VS		 7886static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7887{
c30fec65
VS		 7888 /*
7889 * N = val - 0xb7
7890 * Slow = Fast = GPLL ref * N
7891 */
7892 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7893}
7894
b55dd647 7895static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7896{
c30fec65 7897 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7898}
7899
b55dd647 7900static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7901{
c30fec65
VS		 7902 /*
7903 * N = val / 2
7904 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7905 */
7906 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7907}
7908
b55dd647 7909static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7910{
1c14762d 7911 /* CHV needs even values */
c30fec65 7912 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7913}
7914
616bc820 7915int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7916{
2d1fe073 7917 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7918 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7919 GEN9_FREQ_SCALER);
2d1fe073 7920 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7921 return chv_gpu_freq(dev_priv, val);
2d1fe073 7922 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7923 return byt_gpu_freq(dev_priv, val);
7924 else
7925 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7926}
7927
616bc820
VS		 7928int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7929{
2d1fe073 7930 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7931 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7932 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7933 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7934 return chv_freq_opcode(dev_priv, val);
2d1fe073 7935 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7936 return byt_freq_opcode(dev_priv, val);
7937 else
500a3d2e 7938 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7939}
22b1b2f8 7940
6ad790c0
CW		 7941struct request_boost {
7942 struct work_struct work;
eed29a5b 7943 struct drm_i915_gem_request *req;
6ad790c0
CW		 7944};
7945
7946static void __intel_rps_boost_work(struct work_struct *work)
7947{
7948 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7949 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7950
f69a02c9 7951 if (!i915_gem_request_completed(req))
c033666a 7952 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7953
e8a261ea 7954 i915_gem_request_put(req);
6ad790c0
CW		 7955 kfree(boost);
7956}
7957
91d14251 7958void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7959{
7960 struct request_boost *boost;
7961
91d14251 7962 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7963 return;
7964
f69a02c9 7965 if (i915_gem_request_completed(req))
e61b9958
CW		 7966 return;
7967
6ad790c0
CW		 7968 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7969 if (boost == NULL)
7970 return;
7971
e8a261ea 7972 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7973
7974 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7975 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7976}
7977
f742a552 7978void intel_pm_setup(struct drm_device *dev)
907b28c5 7979{
fac5e23e 7980 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 7981
f742a552 7982 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7983 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7984
54b4f68f
CW		 7985 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7986 __intel_autoenable_gt_powersave);
1854d5ca 7987 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 7988
33688d95 7989 dev_priv->pm.suspended = false;
1f814dac 7990 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7991 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7992}
ubuntu-bionic-kernel mirror