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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
f9dcb0df | 33 | #include <linux/vgaarb.h> |
f4db9321 | 34 | #include <drm/i915_powerwell.h> |
8a187455 | 35 | #include <linux/pm_runtime.h> |
85208be0 | 36 | |
dc39fff7 BW |
37 | /** |
38 | * RC6 is a special power stage which allows the GPU to enter an very | |
39 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
40 | * stage is entered automatically when the GPU is idle when RC6 support is | |
41 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
42 | * | |
43 | * There are different RC6 modes available in Intel GPU, which differentiate | |
44 | * among each other with the latency required to enter and leave RC6 and | |
45 | * voltage consumed by the GPU in different states. | |
46 | * | |
47 | * The combination of the following flags define which states GPU is allowed | |
48 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
49 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
50 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
51 | * which brings the most power savings; deeper states save more power, but | |
52 | * require higher latency to switch to and wake up. | |
53 | */ | |
54 | #define INTEL_RC6_ENABLE (1<<0) | |
55 | #define INTEL_RC6p_ENABLE (1<<1) | |
56 | #define INTEL_RC6pp_ENABLE (1<<2) | |
57 | ||
f6750b3c ED |
58 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
59 | * framebuffer contents in-memory, aiming at reducing the required bandwidth | |
60 | * during in-memory transfers and, therefore, reduce the power packet. | |
85208be0 | 61 | * |
f6750b3c ED |
62 | * The benefits of FBC are mostly visible with solid backgrounds and |
63 | * variation-less patterns. | |
85208be0 | 64 | * |
f6750b3c ED |
65 | * FBC-related functionality can be enabled by the means of the |
66 | * i915.i915_enable_fbc parameter | |
85208be0 ED |
67 | */ |
68 | ||
1fa61106 | 69 | static void i8xx_disable_fbc(struct drm_device *dev) |
85208be0 ED |
70 | { |
71 | struct drm_i915_private *dev_priv = dev->dev_private; | |
72 | u32 fbc_ctl; | |
73 | ||
74 | /* Disable compression */ | |
75 | fbc_ctl = I915_READ(FBC_CONTROL); | |
76 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
77 | return; | |
78 | ||
79 | fbc_ctl &= ~FBC_CTL_EN; | |
80 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
81 | ||
82 | /* Wait for compressing bit to clear */ | |
83 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
84 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
85 | return; | |
86 | } | |
87 | ||
88 | DRM_DEBUG_KMS("disabled FBC\n"); | |
89 | } | |
90 | ||
993495ae | 91 | static void i8xx_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
92 | { |
93 | struct drm_device *dev = crtc->dev; | |
94 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 95 | struct drm_framebuffer *fb = crtc->primary->fb; |
85208be0 ED |
96 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
97 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
98 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
99 | int cfb_pitch; | |
7f2cf220 | 100 | int i; |
159f9875 | 101 | u32 fbc_ctl; |
85208be0 | 102 | |
5c3fe8b0 | 103 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
85208be0 ED |
104 | if (fb->pitches[0] < cfb_pitch) |
105 | cfb_pitch = fb->pitches[0]; | |
106 | ||
42a430f5 VS |
107 | /* FBC_CTL wants 32B or 64B units */ |
108 | if (IS_GEN2(dev)) | |
109 | cfb_pitch = (cfb_pitch / 32) - 1; | |
110 | else | |
111 | cfb_pitch = (cfb_pitch / 64) - 1; | |
85208be0 ED |
112 | |
113 | /* Clear old tags */ | |
114 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
115 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
116 | ||
159f9875 VS |
117 | if (IS_GEN4(dev)) { |
118 | u32 fbc_ctl2; | |
119 | ||
120 | /* Set it up... */ | |
121 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
7f2cf220 | 122 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); |
159f9875 VS |
123 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
124 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
125 | } | |
85208be0 ED |
126 | |
127 | /* enable it... */ | |
993495ae VS |
128 | fbc_ctl = I915_READ(FBC_CONTROL); |
129 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
130 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
85208be0 ED |
131 | if (IS_I945GM(dev)) |
132 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
133 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
85208be0 ED |
134 | fbc_ctl |= obj->fence_reg; |
135 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
136 | ||
5cd5410e | 137 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
84f44ce7 | 138 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
85208be0 ED |
139 | } |
140 | ||
1fa61106 | 141 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
142 | { |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | ||
145 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
146 | } | |
147 | ||
993495ae | 148 | static void g4x_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
149 | { |
150 | struct drm_device *dev = crtc->dev; | |
151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 152 | struct drm_framebuffer *fb = crtc->primary->fb; |
85208be0 ED |
153 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
154 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
85208be0 ED |
156 | u32 dpfc_ctl; |
157 | ||
3fa2e0ee VS |
158 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; |
159 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
160 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
161 | else | |
162 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
85208be0 | 163 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
85208be0 | 164 | |
85208be0 ED |
165 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
166 | ||
167 | /* enable it... */ | |
fe74c1a5 | 168 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
85208be0 | 169 | |
84f44ce7 | 170 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
171 | } |
172 | ||
1fa61106 | 173 | static void g4x_disable_fbc(struct drm_device *dev) |
85208be0 ED |
174 | { |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | u32 dpfc_ctl; | |
177 | ||
178 | /* Disable compression */ | |
179 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
180 | if (dpfc_ctl & DPFC_CTL_EN) { | |
181 | dpfc_ctl &= ~DPFC_CTL_EN; | |
182 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
183 | ||
184 | DRM_DEBUG_KMS("disabled FBC\n"); | |
185 | } | |
186 | } | |
187 | ||
1fa61106 | 188 | static bool g4x_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
189 | { |
190 | struct drm_i915_private *dev_priv = dev->dev_private; | |
191 | ||
192 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
193 | } | |
194 | ||
195 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | |
196 | { | |
197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
198 | u32 blt_ecoskpd; | |
199 | ||
200 | /* Make sure blitter notifies FBC of writes */ | |
940aece4 D |
201 | |
202 | /* Blitter is part of Media powerwell on VLV. No impact of | |
203 | * his param in other platforms for now */ | |
204 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); | |
c8d9a590 | 205 | |
85208be0 ED |
206 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
207 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
208 | GEN6_BLITTER_LOCK_SHIFT; | |
209 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
210 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
211 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
212 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
213 | GEN6_BLITTER_LOCK_SHIFT); | |
214 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
215 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
c8d9a590 | 216 | |
940aece4 | 217 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); |
85208be0 ED |
218 | } |
219 | ||
993495ae | 220 | static void ironlake_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
221 | { |
222 | struct drm_device *dev = crtc->dev; | |
223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 224 | struct drm_framebuffer *fb = crtc->primary->fb; |
85208be0 ED |
225 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
226 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
85208be0 ED |
228 | u32 dpfc_ctl; |
229 | ||
46f3dab9 | 230 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); |
3fa2e0ee | 231 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
5e59f717 BW |
232 | dev_priv->fbc.threshold++; |
233 | ||
234 | switch (dev_priv->fbc.threshold) { | |
235 | case 4: | |
236 | case 3: | |
237 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
238 | break; | |
239 | case 2: | |
3fa2e0ee | 240 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
5e59f717 BW |
241 | break; |
242 | case 1: | |
3fa2e0ee | 243 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
5e59f717 BW |
244 | break; |
245 | } | |
d629336b VS |
246 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
247 | if (IS_GEN5(dev)) | |
248 | dpfc_ctl |= obj->fence_reg; | |
85208be0 | 249 | |
85208be0 | 250 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
f343c5f6 | 251 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
85208be0 ED |
252 | /* enable it... */ |
253 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
254 | ||
255 | if (IS_GEN6(dev)) { | |
256 | I915_WRITE(SNB_DPFC_CTL_SA, | |
257 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
258 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
259 | sandybridge_blit_fbc_update(dev); | |
260 | } | |
261 | ||
84f44ce7 | 262 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
263 | } |
264 | ||
1fa61106 | 265 | static void ironlake_disable_fbc(struct drm_device *dev) |
85208be0 ED |
266 | { |
267 | struct drm_i915_private *dev_priv = dev->dev_private; | |
268 | u32 dpfc_ctl; | |
269 | ||
270 | /* Disable compression */ | |
271 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
272 | if (dpfc_ctl & DPFC_CTL_EN) { | |
273 | dpfc_ctl &= ~DPFC_CTL_EN; | |
274 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
275 | ||
276 | DRM_DEBUG_KMS("disabled FBC\n"); | |
277 | } | |
278 | } | |
279 | ||
1fa61106 | 280 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
281 | { |
282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
283 | ||
284 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
285 | } | |
286 | ||
993495ae | 287 | static void gen7_enable_fbc(struct drm_crtc *crtc) |
abe959c7 RV |
288 | { |
289 | struct drm_device *dev = crtc->dev; | |
290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 291 | struct drm_framebuffer *fb = crtc->primary->fb; |
abe959c7 RV |
292 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
293 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
294 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3fa2e0ee | 295 | u32 dpfc_ctl; |
abe959c7 | 296 | |
3fa2e0ee VS |
297 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); |
298 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
5e59f717 BW |
299 | dev_priv->fbc.threshold++; |
300 | ||
301 | switch (dev_priv->fbc.threshold) { | |
302 | case 4: | |
303 | case 3: | |
304 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
305 | break; | |
306 | case 2: | |
3fa2e0ee | 307 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
5e59f717 BW |
308 | break; |
309 | case 1: | |
3fa2e0ee | 310 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
5e59f717 BW |
311 | break; |
312 | } | |
313 | ||
3fa2e0ee VS |
314 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
315 | ||
316 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
abe959c7 | 317 | |
891348b2 | 318 | if (IS_IVYBRIDGE(dev)) { |
7dd23ba0 | 319 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
2adb6db8 VS |
320 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
321 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
322 | ILK_FBCQ_DIS); | |
28554164 | 323 | } else { |
2adb6db8 | 324 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
8f670bb1 VS |
325 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), |
326 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | | |
327 | HSW_FBCQ_DIS); | |
891348b2 | 328 | } |
b74ea102 | 329 | |
abe959c7 RV |
330 | I915_WRITE(SNB_DPFC_CTL_SA, |
331 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
332 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
333 | ||
334 | sandybridge_blit_fbc_update(dev); | |
335 | ||
b19870ee | 336 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
abe959c7 RV |
337 | } |
338 | ||
85208be0 ED |
339 | bool intel_fbc_enabled(struct drm_device *dev) |
340 | { | |
341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
342 | ||
343 | if (!dev_priv->display.fbc_enabled) | |
344 | return false; | |
345 | ||
346 | return dev_priv->display.fbc_enabled(dev); | |
347 | } | |
348 | ||
349 | static void intel_fbc_work_fn(struct work_struct *__work) | |
350 | { | |
351 | struct intel_fbc_work *work = | |
352 | container_of(to_delayed_work(__work), | |
353 | struct intel_fbc_work, work); | |
354 | struct drm_device *dev = work->crtc->dev; | |
355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
356 | ||
357 | mutex_lock(&dev->struct_mutex); | |
5c3fe8b0 | 358 | if (work == dev_priv->fbc.fbc_work) { |
85208be0 ED |
359 | /* Double check that we haven't switched fb without cancelling |
360 | * the prior work. | |
361 | */ | |
f4510a27 | 362 | if (work->crtc->primary->fb == work->fb) { |
993495ae | 363 | dev_priv->display.enable_fbc(work->crtc); |
85208be0 | 364 | |
5c3fe8b0 | 365 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; |
f4510a27 | 366 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
5c3fe8b0 | 367 | dev_priv->fbc.y = work->crtc->y; |
85208be0 ED |
368 | } |
369 | ||
5c3fe8b0 | 370 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
371 | } |
372 | mutex_unlock(&dev->struct_mutex); | |
373 | ||
374 | kfree(work); | |
375 | } | |
376 | ||
377 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
378 | { | |
5c3fe8b0 | 379 | if (dev_priv->fbc.fbc_work == NULL) |
85208be0 ED |
380 | return; |
381 | ||
382 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
383 | ||
384 | /* Synchronisation is provided by struct_mutex and checking of | |
5c3fe8b0 | 385 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
85208be0 ED |
386 | * entirely asynchronously. |
387 | */ | |
5c3fe8b0 | 388 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
85208be0 | 389 | /* tasklet was killed before being run, clean up */ |
5c3fe8b0 | 390 | kfree(dev_priv->fbc.fbc_work); |
85208be0 ED |
391 | |
392 | /* Mark the work as no longer wanted so that if it does | |
393 | * wake-up (because the work was already running and waiting | |
394 | * for our mutex), it will discover that is no longer | |
395 | * necessary to run. | |
396 | */ | |
5c3fe8b0 | 397 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
398 | } |
399 | ||
993495ae | 400 | static void intel_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
401 | { |
402 | struct intel_fbc_work *work; | |
403 | struct drm_device *dev = crtc->dev; | |
404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
405 | ||
406 | if (!dev_priv->display.enable_fbc) | |
407 | return; | |
408 | ||
409 | intel_cancel_fbc_work(dev_priv); | |
410 | ||
b14c5679 | 411 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
85208be0 | 412 | if (work == NULL) { |
6cdcb5e7 | 413 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
993495ae | 414 | dev_priv->display.enable_fbc(crtc); |
85208be0 ED |
415 | return; |
416 | } | |
417 | ||
418 | work->crtc = crtc; | |
f4510a27 | 419 | work->fb = crtc->primary->fb; |
85208be0 ED |
420 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
421 | ||
5c3fe8b0 | 422 | dev_priv->fbc.fbc_work = work; |
85208be0 | 423 | |
85208be0 ED |
424 | /* Delay the actual enabling to let pageflipping cease and the |
425 | * display to settle before starting the compression. Note that | |
426 | * this delay also serves a second purpose: it allows for a | |
427 | * vblank to pass after disabling the FBC before we attempt | |
428 | * to modify the control registers. | |
429 | * | |
430 | * A more complicated solution would involve tracking vblanks | |
431 | * following the termination of the page-flipping sequence | |
432 | * and indeed performing the enable as a co-routine and not | |
433 | * waiting synchronously upon the vblank. | |
7457d617 DL |
434 | * |
435 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
85208be0 ED |
436 | */ |
437 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
438 | } | |
439 | ||
440 | void intel_disable_fbc(struct drm_device *dev) | |
441 | { | |
442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
443 | ||
444 | intel_cancel_fbc_work(dev_priv); | |
445 | ||
446 | if (!dev_priv->display.disable_fbc) | |
447 | return; | |
448 | ||
449 | dev_priv->display.disable_fbc(dev); | |
5c3fe8b0 | 450 | dev_priv->fbc.plane = -1; |
85208be0 ED |
451 | } |
452 | ||
29ebf90f CW |
453 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, |
454 | enum no_fbc_reason reason) | |
455 | { | |
456 | if (dev_priv->fbc.no_fbc_reason == reason) | |
457 | return false; | |
458 | ||
459 | dev_priv->fbc.no_fbc_reason = reason; | |
460 | return true; | |
461 | } | |
462 | ||
85208be0 ED |
463 | /** |
464 | * intel_update_fbc - enable/disable FBC as needed | |
465 | * @dev: the drm_device | |
466 | * | |
467 | * Set up the framebuffer compression hardware at mode set time. We | |
468 | * enable it if possible: | |
469 | * - plane A only (on pre-965) | |
470 | * - no pixel mulitply/line duplication | |
471 | * - no alpha buffer discard | |
472 | * - no dual wide | |
f85da868 | 473 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
85208be0 ED |
474 | * |
475 | * We can't assume that any compression will take place (worst case), | |
476 | * so the compressed buffer has to be the same size as the uncompressed | |
477 | * one. It also must reside (along with the line length buffer) in | |
478 | * stolen memory. | |
479 | * | |
480 | * We need to enable/disable FBC on a global basis. | |
481 | */ | |
482 | void intel_update_fbc(struct drm_device *dev) | |
483 | { | |
484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
485 | struct drm_crtc *crtc = NULL, *tmp_crtc; | |
486 | struct intel_crtc *intel_crtc; | |
487 | struct drm_framebuffer *fb; | |
488 | struct intel_framebuffer *intel_fb; | |
489 | struct drm_i915_gem_object *obj; | |
ef644fda | 490 | const struct drm_display_mode *adjusted_mode; |
37327abd | 491 | unsigned int max_width, max_height; |
85208be0 | 492 | |
3a77c4c4 | 493 | if (!HAS_FBC(dev)) { |
29ebf90f | 494 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); |
85208be0 | 495 | return; |
29ebf90f | 496 | } |
85208be0 | 497 | |
d330a953 | 498 | if (!i915.powersave) { |
29ebf90f CW |
499 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
500 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 | 501 | return; |
29ebf90f | 502 | } |
85208be0 ED |
503 | |
504 | /* | |
505 | * If FBC is already on, we just have to verify that we can | |
506 | * keep it that way... | |
507 | * Need to disable if: | |
508 | * - more than one pipe is active | |
509 | * - changing FBC params (stride, fence, mode) | |
510 | * - new fb is too large to fit in compressed buffer | |
511 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
512 | */ | |
70e1e0ec | 513 | for_each_crtc(dev, tmp_crtc) { |
3490ea5d | 514 | if (intel_crtc_active(tmp_crtc) && |
4c445e0e | 515 | to_intel_crtc(tmp_crtc)->primary_enabled) { |
85208be0 | 516 | if (crtc) { |
29ebf90f CW |
517 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
518 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
85208be0 ED |
519 | goto out_disable; |
520 | } | |
521 | crtc = tmp_crtc; | |
522 | } | |
523 | } | |
524 | ||
f4510a27 | 525 | if (!crtc || crtc->primary->fb == NULL) { |
29ebf90f CW |
526 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) |
527 | DRM_DEBUG_KMS("no output, disabling\n"); | |
85208be0 ED |
528 | goto out_disable; |
529 | } | |
530 | ||
531 | intel_crtc = to_intel_crtc(crtc); | |
f4510a27 | 532 | fb = crtc->primary->fb; |
85208be0 ED |
533 | intel_fb = to_intel_framebuffer(fb); |
534 | obj = intel_fb->obj; | |
ef644fda | 535 | adjusted_mode = &intel_crtc->config.adjusted_mode; |
85208be0 | 536 | |
0368920e | 537 | if (i915.enable_fbc < 0) { |
29ebf90f CW |
538 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
539 | DRM_DEBUG_KMS("disabled per chip default\n"); | |
8a5729a3 | 540 | goto out_disable; |
85208be0 | 541 | } |
d330a953 | 542 | if (!i915.enable_fbc) { |
29ebf90f CW |
543 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
544 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 ED |
545 | goto out_disable; |
546 | } | |
ef644fda VS |
547 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
548 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
29ebf90f CW |
549 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
550 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
551 | "disabling\n"); | |
85208be0 ED |
552 | goto out_disable; |
553 | } | |
f85da868 | 554 | |
032843a5 DS |
555 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { |
556 | max_width = 4096; | |
557 | max_height = 4096; | |
558 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
37327abd VS |
559 | max_width = 4096; |
560 | max_height = 2048; | |
f85da868 | 561 | } else { |
37327abd VS |
562 | max_width = 2048; |
563 | max_height = 1536; | |
f85da868 | 564 | } |
37327abd VS |
565 | if (intel_crtc->config.pipe_src_w > max_width || |
566 | intel_crtc->config.pipe_src_h > max_height) { | |
29ebf90f CW |
567 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
568 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
85208be0 ED |
569 | goto out_disable; |
570 | } | |
8f94d24b | 571 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && |
c5a44aa0 | 572 | intel_crtc->plane != PLANE_A) { |
29ebf90f | 573 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) |
c5a44aa0 | 574 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); |
85208be0 ED |
575 | goto out_disable; |
576 | } | |
577 | ||
578 | /* The use of a CPU fence is mandatory in order to detect writes | |
579 | * by the CPU to the scanout and trigger updates to the FBC. | |
580 | */ | |
581 | if (obj->tiling_mode != I915_TILING_X || | |
582 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
29ebf90f CW |
583 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) |
584 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
85208be0 ED |
585 | goto out_disable; |
586 | } | |
587 | ||
588 | /* If the kernel debugger is active, always disable compression */ | |
589 | if (in_dbg_master()) | |
590 | goto out_disable; | |
591 | ||
5e59f717 BW |
592 | if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size, |
593 | drm_format_plane_cpp(fb->pixel_format, 0))) { | |
29ebf90f CW |
594 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) |
595 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); | |
11be49eb CW |
596 | goto out_disable; |
597 | } | |
598 | ||
85208be0 ED |
599 | /* If the scanout has not changed, don't modify the FBC settings. |
600 | * Note that we make the fundamental assumption that the fb->obj | |
601 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
602 | * without first being decoupled from the scanout and FBC disabled. | |
603 | */ | |
5c3fe8b0 BW |
604 | if (dev_priv->fbc.plane == intel_crtc->plane && |
605 | dev_priv->fbc.fb_id == fb->base.id && | |
606 | dev_priv->fbc.y == crtc->y) | |
85208be0 ED |
607 | return; |
608 | ||
609 | if (intel_fbc_enabled(dev)) { | |
610 | /* We update FBC along two paths, after changing fb/crtc | |
611 | * configuration (modeswitching) and after page-flipping | |
612 | * finishes. For the latter, we know that not only did | |
613 | * we disable the FBC at the start of the page-flip | |
614 | * sequence, but also more than one vblank has passed. | |
615 | * | |
616 | * For the former case of modeswitching, it is possible | |
617 | * to switch between two FBC valid configurations | |
618 | * instantaneously so we do need to disable the FBC | |
619 | * before we can modify its control registers. We also | |
620 | * have to wait for the next vblank for that to take | |
621 | * effect. However, since we delay enabling FBC we can | |
622 | * assume that a vblank has passed since disabling and | |
623 | * that we can safely alter the registers in the deferred | |
624 | * callback. | |
625 | * | |
626 | * In the scenario that we go from a valid to invalid | |
627 | * and then back to valid FBC configuration we have | |
628 | * no strict enforcement that a vblank occurred since | |
629 | * disabling the FBC. However, along all current pipe | |
630 | * disabling paths we do need to wait for a vblank at | |
631 | * some point. And we wait before enabling FBC anyway. | |
632 | */ | |
633 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
634 | intel_disable_fbc(dev); | |
635 | } | |
636 | ||
993495ae | 637 | intel_enable_fbc(crtc); |
29ebf90f | 638 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
85208be0 ED |
639 | return; |
640 | ||
641 | out_disable: | |
642 | /* Multiple disables should be harmless */ | |
643 | if (intel_fbc_enabled(dev)) { | |
644 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
645 | intel_disable_fbc(dev); | |
646 | } | |
11be49eb | 647 | i915_gem_stolen_cleanup_compression(dev); |
85208be0 ED |
648 | } |
649 | ||
c921aba8 DV |
650 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
651 | { | |
50227e1c | 652 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
653 | u32 tmp; |
654 | ||
655 | tmp = I915_READ(CLKCFG); | |
656 | ||
657 | switch (tmp & CLKCFG_FSB_MASK) { | |
658 | case CLKCFG_FSB_533: | |
659 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
660 | break; | |
661 | case CLKCFG_FSB_800: | |
662 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
663 | break; | |
664 | case CLKCFG_FSB_667: | |
665 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
666 | break; | |
667 | case CLKCFG_FSB_400: | |
668 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
669 | break; | |
670 | } | |
671 | ||
672 | switch (tmp & CLKCFG_MEM_MASK) { | |
673 | case CLKCFG_MEM_533: | |
674 | dev_priv->mem_freq = 533; | |
675 | break; | |
676 | case CLKCFG_MEM_667: | |
677 | dev_priv->mem_freq = 667; | |
678 | break; | |
679 | case CLKCFG_MEM_800: | |
680 | dev_priv->mem_freq = 800; | |
681 | break; | |
682 | } | |
683 | ||
684 | /* detect pineview DDR3 setting */ | |
685 | tmp = I915_READ(CSHRDDR3CTL); | |
686 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
687 | } | |
688 | ||
689 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
690 | { | |
50227e1c | 691 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
692 | u16 ddrpll, csipll; |
693 | ||
694 | ddrpll = I915_READ16(DDRMPLL1); | |
695 | csipll = I915_READ16(CSIPLL0); | |
696 | ||
697 | switch (ddrpll & 0xff) { | |
698 | case 0xc: | |
699 | dev_priv->mem_freq = 800; | |
700 | break; | |
701 | case 0x10: | |
702 | dev_priv->mem_freq = 1066; | |
703 | break; | |
704 | case 0x14: | |
705 | dev_priv->mem_freq = 1333; | |
706 | break; | |
707 | case 0x18: | |
708 | dev_priv->mem_freq = 1600; | |
709 | break; | |
710 | default: | |
711 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
712 | ddrpll & 0xff); | |
713 | dev_priv->mem_freq = 0; | |
714 | break; | |
715 | } | |
716 | ||
20e4d407 | 717 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
718 | |
719 | switch (csipll & 0x3ff) { | |
720 | case 0x00c: | |
721 | dev_priv->fsb_freq = 3200; | |
722 | break; | |
723 | case 0x00e: | |
724 | dev_priv->fsb_freq = 3733; | |
725 | break; | |
726 | case 0x010: | |
727 | dev_priv->fsb_freq = 4266; | |
728 | break; | |
729 | case 0x012: | |
730 | dev_priv->fsb_freq = 4800; | |
731 | break; | |
732 | case 0x014: | |
733 | dev_priv->fsb_freq = 5333; | |
734 | break; | |
735 | case 0x016: | |
736 | dev_priv->fsb_freq = 5866; | |
737 | break; | |
738 | case 0x018: | |
739 | dev_priv->fsb_freq = 6400; | |
740 | break; | |
741 | default: | |
742 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
743 | csipll & 0x3ff); | |
744 | dev_priv->fsb_freq = 0; | |
745 | break; | |
746 | } | |
747 | ||
748 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 749 | dev_priv->ips.c_m = 0; |
c921aba8 | 750 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 751 | dev_priv->ips.c_m = 1; |
c921aba8 | 752 | } else { |
20e4d407 | 753 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
754 | } |
755 | } | |
756 | ||
b445e3b0 ED |
757 | static const struct cxsr_latency cxsr_latency_table[] = { |
758 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
759 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
760 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
761 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
762 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
763 | ||
764 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
765 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
766 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
767 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
768 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
769 | ||
770 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
771 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
772 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
773 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
774 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
775 | ||
776 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
777 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
778 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
779 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
780 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
781 | ||
782 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
783 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
784 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
785 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
786 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
787 | ||
788 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
789 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
790 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
791 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
792 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
793 | }; | |
794 | ||
63c62275 | 795 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
796 | int is_ddr3, |
797 | int fsb, | |
798 | int mem) | |
799 | { | |
800 | const struct cxsr_latency *latency; | |
801 | int i; | |
802 | ||
803 | if (fsb == 0 || mem == 0) | |
804 | return NULL; | |
805 | ||
806 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
807 | latency = &cxsr_latency_table[i]; | |
808 | if (is_desktop == latency->is_desktop && | |
809 | is_ddr3 == latency->is_ddr3 && | |
810 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
811 | return latency; | |
812 | } | |
813 | ||
814 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
815 | ||
816 | return NULL; | |
817 | } | |
818 | ||
5209b1f4 | 819 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 820 | { |
5209b1f4 ID |
821 | struct drm_device *dev = dev_priv->dev; |
822 | u32 val; | |
b445e3b0 | 823 | |
5209b1f4 ID |
824 | if (IS_VALLEYVIEW(dev)) { |
825 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
826 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { | |
827 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
828 | } else if (IS_PINEVIEW(dev)) { | |
829 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
830 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
831 | I915_WRITE(DSPFW3, val); | |
832 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { | |
833 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
834 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
835 | I915_WRITE(FW_BLC_SELF, val); | |
836 | } else if (IS_I915GM(dev)) { | |
837 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
838 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
839 | I915_WRITE(INSTPM, val); | |
840 | } else { | |
841 | return; | |
842 | } | |
843 | ||
844 | DRM_DEBUG_KMS("memory self-refresh is %s\n", | |
845 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
846 | } |
847 | ||
848 | /* | |
849 | * Latency for FIFO fetches is dependent on several factors: | |
850 | * - memory configuration (speed, channels) | |
851 | * - chipset | |
852 | * - current MCH state | |
853 | * It can be fairly high in some situations, so here we assume a fairly | |
854 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
855 | * set this value too high, the FIFO will fetch frequently to stay full) | |
856 | * and power consumption (set it too low to save power and we might see | |
857 | * FIFO underruns and display "flicker"). | |
858 | * | |
859 | * A value of 5us seems to be a good balance; safe for very low end | |
860 | * platforms but not overly aggressive on lower latency configs. | |
861 | */ | |
862 | static const int latency_ns = 5000; | |
863 | ||
1fa61106 | 864 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
865 | { |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
867 | uint32_t dsparb = I915_READ(DSPARB); | |
868 | int size; | |
869 | ||
870 | size = dsparb & 0x7f; | |
871 | if (plane) | |
872 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
873 | ||
874 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
875 | plane ? "B" : "A", size); | |
876 | ||
877 | return size; | |
878 | } | |
879 | ||
feb56b93 | 880 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
881 | { |
882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
883 | uint32_t dsparb = I915_READ(DSPARB); | |
884 | int size; | |
885 | ||
886 | size = dsparb & 0x1ff; | |
887 | if (plane) | |
888 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
889 | size >>= 1; /* Convert to cachelines */ | |
890 | ||
891 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
892 | plane ? "B" : "A", size); | |
893 | ||
894 | return size; | |
895 | } | |
896 | ||
1fa61106 | 897 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
898 | { |
899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
900 | uint32_t dsparb = I915_READ(DSPARB); | |
901 | int size; | |
902 | ||
903 | size = dsparb & 0x7f; | |
904 | size >>= 2; /* Convert to cachelines */ | |
905 | ||
906 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
907 | plane ? "B" : "A", | |
908 | size); | |
909 | ||
910 | return size; | |
911 | } | |
912 | ||
b445e3b0 ED |
913 | /* Pineview has different values for various configs */ |
914 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
915 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
916 | .max_wm = PINEVIEW_MAX_WM, | |
917 | .default_wm = PINEVIEW_DFT_WM, | |
918 | .guard_size = PINEVIEW_GUARD_WM, | |
919 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
920 | }; |
921 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
922 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
923 | .max_wm = PINEVIEW_MAX_WM, | |
924 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
925 | .guard_size = PINEVIEW_GUARD_WM, | |
926 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
927 | }; |
928 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
929 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
930 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
931 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
932 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
933 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
934 | }; |
935 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
936 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
937 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
938 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
939 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
940 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
941 | }; |
942 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
943 | .fifo_size = G4X_FIFO_SIZE, |
944 | .max_wm = G4X_MAX_WM, | |
945 | .default_wm = G4X_MAX_WM, | |
946 | .guard_size = 2, | |
947 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
948 | }; |
949 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
950 | .fifo_size = I965_CURSOR_FIFO, |
951 | .max_wm = I965_CURSOR_MAX_WM, | |
952 | .default_wm = I965_CURSOR_DFT_WM, | |
953 | .guard_size = 2, | |
954 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
955 | }; |
956 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
957 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
958 | .max_wm = VALLEYVIEW_MAX_WM, | |
959 | .default_wm = VALLEYVIEW_MAX_WM, | |
960 | .guard_size = 2, | |
961 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
962 | }; |
963 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
964 | .fifo_size = I965_CURSOR_FIFO, |
965 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
966 | .default_wm = I965_CURSOR_DFT_WM, | |
967 | .guard_size = 2, | |
968 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
969 | }; |
970 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
971 | .fifo_size = I965_CURSOR_FIFO, |
972 | .max_wm = I965_CURSOR_MAX_WM, | |
973 | .default_wm = I965_CURSOR_DFT_WM, | |
974 | .guard_size = 2, | |
975 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
976 | }; |
977 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
978 | .fifo_size = I945_FIFO_SIZE, |
979 | .max_wm = I915_MAX_WM, | |
980 | .default_wm = 1, | |
981 | .guard_size = 2, | |
982 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
983 | }; |
984 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
985 | .fifo_size = I915_FIFO_SIZE, |
986 | .max_wm = I915_MAX_WM, | |
987 | .default_wm = 1, | |
988 | .guard_size = 2, | |
989 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 990 | }; |
feb56b93 | 991 | static const struct intel_watermark_params i830_wm_info = { |
e0f0273e VS |
992 | .fifo_size = I855GM_FIFO_SIZE, |
993 | .max_wm = I915_MAX_WM, | |
994 | .default_wm = 1, | |
995 | .guard_size = 2, | |
996 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 997 | }; |
feb56b93 | 998 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
999 | .fifo_size = I830_FIFO_SIZE, |
1000 | .max_wm = I915_MAX_WM, | |
1001 | .default_wm = 1, | |
1002 | .guard_size = 2, | |
1003 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1004 | }; |
1005 | ||
b445e3b0 ED |
1006 | /** |
1007 | * intel_calculate_wm - calculate watermark level | |
1008 | * @clock_in_khz: pixel clock | |
1009 | * @wm: chip FIFO params | |
1010 | * @pixel_size: display pixel size | |
1011 | * @latency_ns: memory latency for the platform | |
1012 | * | |
1013 | * Calculate the watermark level (the level at which the display plane will | |
1014 | * start fetching from memory again). Each chip has a different display | |
1015 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
1016 | * in the correct intel_watermark_params structure. | |
1017 | * | |
1018 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
1019 | * on the pixel size. When it reaches the watermark level, it'll start | |
1020 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
1021 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
1022 | * will occur, and a display engine hang could result. | |
1023 | */ | |
1024 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
1025 | const struct intel_watermark_params *wm, | |
1026 | int fifo_size, | |
1027 | int pixel_size, | |
1028 | unsigned long latency_ns) | |
1029 | { | |
1030 | long entries_required, wm_size; | |
1031 | ||
1032 | /* | |
1033 | * Note: we need to make sure we don't overflow for various clock & | |
1034 | * latency values. | |
1035 | * clocks go from a few thousand to several hundred thousand. | |
1036 | * latency is usually a few thousand | |
1037 | */ | |
1038 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
1039 | 1000; | |
1040 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
1041 | ||
1042 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
1043 | ||
1044 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
1045 | ||
1046 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
1047 | ||
1048 | /* Don't promote wm_size to unsigned... */ | |
1049 | if (wm_size > (long)wm->max_wm) | |
1050 | wm_size = wm->max_wm; | |
1051 | if (wm_size <= 0) | |
1052 | wm_size = wm->default_wm; | |
1053 | return wm_size; | |
1054 | } | |
1055 | ||
1056 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
1057 | { | |
1058 | struct drm_crtc *crtc, *enabled = NULL; | |
1059 | ||
70e1e0ec | 1060 | for_each_crtc(dev, crtc) { |
3490ea5d | 1061 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
1062 | if (enabled) |
1063 | return NULL; | |
1064 | enabled = crtc; | |
1065 | } | |
1066 | } | |
1067 | ||
1068 | return enabled; | |
1069 | } | |
1070 | ||
46ba614c | 1071 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1072 | { |
46ba614c | 1073 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1074 | struct drm_i915_private *dev_priv = dev->dev_private; |
1075 | struct drm_crtc *crtc; | |
1076 | const struct cxsr_latency *latency; | |
1077 | u32 reg; | |
1078 | unsigned long wm; | |
1079 | ||
1080 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
1081 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
1082 | if (!latency) { | |
1083 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 1084 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1085 | return; |
1086 | } | |
1087 | ||
1088 | crtc = single_enabled_crtc(dev); | |
1089 | if (crtc) { | |
241bfc38 | 1090 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1091 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
241bfc38 DL |
1092 | int clock; |
1093 | ||
1094 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; | |
1095 | clock = adjusted_mode->crtc_clock; | |
b445e3b0 ED |
1096 | |
1097 | /* Display SR */ | |
1098 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
1099 | pineview_display_wm.fifo_size, | |
1100 | pixel_size, latency->display_sr); | |
1101 | reg = I915_READ(DSPFW1); | |
1102 | reg &= ~DSPFW_SR_MASK; | |
1103 | reg |= wm << DSPFW_SR_SHIFT; | |
1104 | I915_WRITE(DSPFW1, reg); | |
1105 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
1106 | ||
1107 | /* cursor SR */ | |
1108 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
1109 | pineview_display_wm.fifo_size, | |
1110 | pixel_size, latency->cursor_sr); | |
1111 | reg = I915_READ(DSPFW3); | |
1112 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
1113 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
1114 | I915_WRITE(DSPFW3, reg); | |
1115 | ||
1116 | /* Display HPLL off SR */ | |
1117 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
1118 | pineview_display_hplloff_wm.fifo_size, | |
1119 | pixel_size, latency->display_hpll_disable); | |
1120 | reg = I915_READ(DSPFW3); | |
1121 | reg &= ~DSPFW_HPLL_SR_MASK; | |
1122 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
1123 | I915_WRITE(DSPFW3, reg); | |
1124 | ||
1125 | /* cursor HPLL off SR */ | |
1126 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
1127 | pineview_display_hplloff_wm.fifo_size, | |
1128 | pixel_size, latency->cursor_hpll_disable); | |
1129 | reg = I915_READ(DSPFW3); | |
1130 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
1131 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
1132 | I915_WRITE(DSPFW3, reg); | |
1133 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
1134 | ||
5209b1f4 | 1135 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 1136 | } else { |
5209b1f4 | 1137 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1138 | } |
1139 | } | |
1140 | ||
1141 | static bool g4x_compute_wm0(struct drm_device *dev, | |
1142 | int plane, | |
1143 | const struct intel_watermark_params *display, | |
1144 | int display_latency_ns, | |
1145 | const struct intel_watermark_params *cursor, | |
1146 | int cursor_latency_ns, | |
1147 | int *plane_wm, | |
1148 | int *cursor_wm) | |
1149 | { | |
1150 | struct drm_crtc *crtc; | |
4fe8590a | 1151 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1152 | int htotal, hdisplay, clock, pixel_size; |
1153 | int line_time_us, line_count; | |
1154 | int entries, tlb_miss; | |
1155 | ||
1156 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1157 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
1158 | *cursor_wm = cursor->guard_size; |
1159 | *plane_wm = display->guard_size; | |
1160 | return false; | |
1161 | } | |
1162 | ||
4fe8590a | 1163 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1164 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1165 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1166 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1167 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1168 | |
1169 | /* Use the small buffer method to calculate plane watermark */ | |
1170 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
1171 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
1172 | if (tlb_miss > 0) | |
1173 | entries += tlb_miss; | |
1174 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
1175 | *plane_wm = entries + display->guard_size; | |
1176 | if (*plane_wm > (int)display->max_wm) | |
1177 | *plane_wm = display->max_wm; | |
1178 | ||
1179 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 1180 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 1181 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
7bb836dd | 1182 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
b445e3b0 ED |
1183 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1184 | if (tlb_miss > 0) | |
1185 | entries += tlb_miss; | |
1186 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1187 | *cursor_wm = entries + cursor->guard_size; | |
1188 | if (*cursor_wm > (int)cursor->max_wm) | |
1189 | *cursor_wm = (int)cursor->max_wm; | |
1190 | ||
1191 | return true; | |
1192 | } | |
1193 | ||
1194 | /* | |
1195 | * Check the wm result. | |
1196 | * | |
1197 | * If any calculated watermark values is larger than the maximum value that | |
1198 | * can be programmed into the associated watermark register, that watermark | |
1199 | * must be disabled. | |
1200 | */ | |
1201 | static bool g4x_check_srwm(struct drm_device *dev, | |
1202 | int display_wm, int cursor_wm, | |
1203 | const struct intel_watermark_params *display, | |
1204 | const struct intel_watermark_params *cursor) | |
1205 | { | |
1206 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
1207 | display_wm, cursor_wm); | |
1208 | ||
1209 | if (display_wm > display->max_wm) { | |
1210 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
1211 | display_wm, display->max_wm); | |
1212 | return false; | |
1213 | } | |
1214 | ||
1215 | if (cursor_wm > cursor->max_wm) { | |
1216 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
1217 | cursor_wm, cursor->max_wm); | |
1218 | return false; | |
1219 | } | |
1220 | ||
1221 | if (!(display_wm || cursor_wm)) { | |
1222 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
1223 | return false; | |
1224 | } | |
1225 | ||
1226 | return true; | |
1227 | } | |
1228 | ||
1229 | static bool g4x_compute_srwm(struct drm_device *dev, | |
1230 | int plane, | |
1231 | int latency_ns, | |
1232 | const struct intel_watermark_params *display, | |
1233 | const struct intel_watermark_params *cursor, | |
1234 | int *display_wm, int *cursor_wm) | |
1235 | { | |
1236 | struct drm_crtc *crtc; | |
4fe8590a | 1237 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1238 | int hdisplay, htotal, pixel_size, clock; |
1239 | unsigned long line_time_us; | |
1240 | int line_count, line_size; | |
1241 | int small, large; | |
1242 | int entries; | |
1243 | ||
1244 | if (!latency_ns) { | |
1245 | *display_wm = *cursor_wm = 0; | |
1246 | return false; | |
1247 | } | |
1248 | ||
1249 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4fe8590a | 1250 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1251 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1252 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1253 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1254 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 | 1255 | |
922044c9 | 1256 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1257 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1258 | line_size = hdisplay * pixel_size; | |
1259 | ||
1260 | /* Use the minimum of the small and large buffer method for primary */ | |
1261 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1262 | large = line_count * line_size; | |
1263 | ||
1264 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1265 | *display_wm = entries + display->guard_size; | |
1266 | ||
1267 | /* calculate the self-refresh watermark for display cursor */ | |
7bb836dd | 1268 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1269 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1270 | *cursor_wm = entries + cursor->guard_size; | |
1271 | ||
1272 | return g4x_check_srwm(dev, | |
1273 | *display_wm, *cursor_wm, | |
1274 | display, cursor); | |
1275 | } | |
1276 | ||
1277 | static bool vlv_compute_drain_latency(struct drm_device *dev, | |
1278 | int plane, | |
1279 | int *plane_prec_mult, | |
1280 | int *plane_dl, | |
1281 | int *cursor_prec_mult, | |
1282 | int *cursor_dl) | |
1283 | { | |
1284 | struct drm_crtc *crtc; | |
1285 | int clock, pixel_size; | |
1286 | int entries; | |
1287 | ||
1288 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1289 | if (!intel_crtc_active(crtc)) |
b445e3b0 ED |
1290 | return false; |
1291 | ||
241bfc38 | 1292 | clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
f4510a27 | 1293 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ |
b445e3b0 ED |
1294 | |
1295 | entries = (clock / 1000) * pixel_size; | |
1296 | *plane_prec_mult = (entries > 256) ? | |
1297 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1298 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * | |
1299 | pixel_size); | |
1300 | ||
1301 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ | |
1302 | *cursor_prec_mult = (entries > 256) ? | |
1303 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1304 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); | |
1305 | ||
1306 | return true; | |
1307 | } | |
1308 | ||
1309 | /* | |
1310 | * Update drain latency registers of memory arbiter | |
1311 | * | |
1312 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
1313 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
1314 | * latency value. | |
1315 | */ | |
1316 | ||
1317 | static void vlv_update_drain_latency(struct drm_device *dev) | |
1318 | { | |
1319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1320 | int planea_prec, planea_dl, planeb_prec, planeb_dl; | |
1321 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; | |
1322 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is | |
1323 | either 16 or 32 */ | |
1324 | ||
1325 | /* For plane A, Cursor A */ | |
1326 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, | |
1327 | &cursor_prec_mult, &cursora_dl)) { | |
1328 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1329 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; | |
1330 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1331 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; | |
1332 | ||
1333 | I915_WRITE(VLV_DDL1, cursora_prec | | |
1334 | (cursora_dl << DDL_CURSORA_SHIFT) | | |
1335 | planea_prec | planea_dl); | |
1336 | } | |
1337 | ||
1338 | /* For plane B, Cursor B */ | |
1339 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, | |
1340 | &cursor_prec_mult, &cursorb_dl)) { | |
1341 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1342 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; | |
1343 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1344 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; | |
1345 | ||
1346 | I915_WRITE(VLV_DDL2, cursorb_prec | | |
1347 | (cursorb_dl << DDL_CURSORB_SHIFT) | | |
1348 | planeb_prec | planeb_dl); | |
1349 | } | |
1350 | } | |
1351 | ||
1352 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
1353 | ||
46ba614c | 1354 | static void valleyview_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1355 | { |
46ba614c | 1356 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1357 | static const int sr_latency_ns = 12000; |
1358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1359 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1360 | int plane_sr, cursor_sr; | |
af6c4575 | 1361 | int ignore_plane_sr, ignore_cursor_sr; |
b445e3b0 ED |
1362 | unsigned int enabled = 0; |
1363 | ||
1364 | vlv_update_drain_latency(dev); | |
1365 | ||
51cea1f4 | 1366 | if (g4x_compute_wm0(dev, PIPE_A, |
b445e3b0 ED |
1367 | &valleyview_wm_info, latency_ns, |
1368 | &valleyview_cursor_wm_info, latency_ns, | |
1369 | &planea_wm, &cursora_wm)) | |
51cea1f4 | 1370 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1371 | |
51cea1f4 | 1372 | if (g4x_compute_wm0(dev, PIPE_B, |
b445e3b0 ED |
1373 | &valleyview_wm_info, latency_ns, |
1374 | &valleyview_cursor_wm_info, latency_ns, | |
1375 | &planeb_wm, &cursorb_wm)) | |
51cea1f4 | 1376 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1377 | |
b445e3b0 ED |
1378 | if (single_plane_enabled(enabled) && |
1379 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1380 | sr_latency_ns, | |
1381 | &valleyview_wm_info, | |
1382 | &valleyview_cursor_wm_info, | |
af6c4575 CW |
1383 | &plane_sr, &ignore_cursor_sr) && |
1384 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1385 | 2*sr_latency_ns, | |
1386 | &valleyview_wm_info, | |
1387 | &valleyview_cursor_wm_info, | |
52bd02d8 | 1388 | &ignore_plane_sr, &cursor_sr)) { |
5209b1f4 | 1389 | intel_set_memory_cxsr(dev_priv, true); |
52bd02d8 | 1390 | } else { |
5209b1f4 | 1391 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1392 | plane_sr = cursor_sr = 0; |
1393 | } | |
b445e3b0 ED |
1394 | |
1395 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1396 | planea_wm, cursora_wm, | |
1397 | planeb_wm, cursorb_wm, | |
1398 | plane_sr, cursor_sr); | |
1399 | ||
1400 | I915_WRITE(DSPFW1, | |
1401 | (plane_sr << DSPFW_SR_SHIFT) | | |
1402 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1403 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1404 | planea_wm); | |
1405 | I915_WRITE(DSPFW2, | |
8c919b28 | 1406 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1407 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1408 | I915_WRITE(DSPFW3, | |
8c919b28 CW |
1409 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
1410 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
b445e3b0 ED |
1411 | } |
1412 | ||
46ba614c | 1413 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1414 | { |
46ba614c | 1415 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1416 | static const int sr_latency_ns = 12000; |
1417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1418 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1419 | int plane_sr, cursor_sr; | |
1420 | unsigned int enabled = 0; | |
1421 | ||
51cea1f4 | 1422 | if (g4x_compute_wm0(dev, PIPE_A, |
b445e3b0 ED |
1423 | &g4x_wm_info, latency_ns, |
1424 | &g4x_cursor_wm_info, latency_ns, | |
1425 | &planea_wm, &cursora_wm)) | |
51cea1f4 | 1426 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1427 | |
51cea1f4 | 1428 | if (g4x_compute_wm0(dev, PIPE_B, |
b445e3b0 ED |
1429 | &g4x_wm_info, latency_ns, |
1430 | &g4x_cursor_wm_info, latency_ns, | |
1431 | &planeb_wm, &cursorb_wm)) | |
51cea1f4 | 1432 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1433 | |
b445e3b0 ED |
1434 | if (single_plane_enabled(enabled) && |
1435 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1436 | sr_latency_ns, | |
1437 | &g4x_wm_info, | |
1438 | &g4x_cursor_wm_info, | |
52bd02d8 | 1439 | &plane_sr, &cursor_sr)) { |
5209b1f4 | 1440 | intel_set_memory_cxsr(dev_priv, true); |
52bd02d8 | 1441 | } else { |
5209b1f4 | 1442 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1443 | plane_sr = cursor_sr = 0; |
1444 | } | |
b445e3b0 ED |
1445 | |
1446 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1447 | planea_wm, cursora_wm, | |
1448 | planeb_wm, cursorb_wm, | |
1449 | plane_sr, cursor_sr); | |
1450 | ||
1451 | I915_WRITE(DSPFW1, | |
1452 | (plane_sr << DSPFW_SR_SHIFT) | | |
1453 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1454 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1455 | planea_wm); | |
1456 | I915_WRITE(DSPFW2, | |
8c919b28 | 1457 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1458 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1459 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1460 | I915_WRITE(DSPFW3, | |
8c919b28 | 1461 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
b445e3b0 ED |
1462 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1463 | } | |
1464 | ||
46ba614c | 1465 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1466 | { |
46ba614c | 1467 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1468 | struct drm_i915_private *dev_priv = dev->dev_private; |
1469 | struct drm_crtc *crtc; | |
1470 | int srwm = 1; | |
1471 | int cursor_sr = 16; | |
1472 | ||
1473 | /* Calc sr entries for one plane configs */ | |
1474 | crtc = single_enabled_crtc(dev); | |
1475 | if (crtc) { | |
1476 | /* self-refresh has much higher latency */ | |
1477 | static const int sr_latency_ns = 12000; | |
4fe8590a VS |
1478 | const struct drm_display_mode *adjusted_mode = |
1479 | &to_intel_crtc(crtc)->config.adjusted_mode; | |
241bfc38 | 1480 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1481 | int htotal = adjusted_mode->crtc_htotal; |
37327abd | 1482 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1483 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1484 | unsigned long line_time_us; |
1485 | int entries; | |
1486 | ||
922044c9 | 1487 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1488 | |
1489 | /* Use ns/us then divide to preserve precision */ | |
1490 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1491 | pixel_size * hdisplay; | |
1492 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1493 | srwm = I965_FIFO_SIZE - entries; | |
1494 | if (srwm < 0) | |
1495 | srwm = 1; | |
1496 | srwm &= 0x1ff; | |
1497 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1498 | entries, srwm); | |
1499 | ||
1500 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
7bb836dd | 1501 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1502 | entries = DIV_ROUND_UP(entries, |
1503 | i965_cursor_wm_info.cacheline_size); | |
1504 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1505 | (entries + i965_cursor_wm_info.guard_size); | |
1506 | ||
1507 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1508 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1509 | ||
1510 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1511 | "cursor %d\n", srwm, cursor_sr); | |
1512 | ||
5209b1f4 | 1513 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 ED |
1514 | } else { |
1515 | /* Turn off self refresh if both pipes are enabled */ | |
5209b1f4 | 1516 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1517 | } |
1518 | ||
1519 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1520 | srwm); | |
1521 | ||
1522 | /* 965 has limitations... */ | |
1523 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
1524 | (8 << 16) | (8 << 8) | (8 << 0)); | |
1525 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); | |
1526 | /* update cursor SR watermark */ | |
1527 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1528 | } | |
1529 | ||
46ba614c | 1530 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1531 | { |
46ba614c | 1532 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1533 | struct drm_i915_private *dev_priv = dev->dev_private; |
1534 | const struct intel_watermark_params *wm_info; | |
1535 | uint32_t fwater_lo; | |
1536 | uint32_t fwater_hi; | |
1537 | int cwm, srwm = 1; | |
1538 | int fifo_size; | |
1539 | int planea_wm, planeb_wm; | |
1540 | struct drm_crtc *crtc, *enabled = NULL; | |
1541 | ||
1542 | if (IS_I945GM(dev)) | |
1543 | wm_info = &i945_wm_info; | |
1544 | else if (!IS_GEN2(dev)) | |
1545 | wm_info = &i915_wm_info; | |
1546 | else | |
feb56b93 | 1547 | wm_info = &i830_wm_info; |
b445e3b0 ED |
1548 | |
1549 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1550 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1551 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1552 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1553 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1554 | if (IS_GEN2(dev)) |
1555 | cpp = 4; | |
1556 | ||
241bfc38 DL |
1557 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1558 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1559 | wm_info, fifo_size, cpp, |
b445e3b0 ED |
1560 | latency_ns); |
1561 | enabled = crtc; | |
1562 | } else | |
1563 | planea_wm = fifo_size - wm_info->guard_size; | |
1564 | ||
1565 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1566 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1567 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1568 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1569 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1570 | if (IS_GEN2(dev)) |
1571 | cpp = 4; | |
1572 | ||
241bfc38 DL |
1573 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1574 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1575 | wm_info, fifo_size, cpp, |
b445e3b0 ED |
1576 | latency_ns); |
1577 | if (enabled == NULL) | |
1578 | enabled = crtc; | |
1579 | else | |
1580 | enabled = NULL; | |
1581 | } else | |
1582 | planeb_wm = fifo_size - wm_info->guard_size; | |
1583 | ||
1584 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1585 | ||
2ab1bc9d DV |
1586 | if (IS_I915GM(dev) && enabled) { |
1587 | struct intel_framebuffer *fb; | |
1588 | ||
1589 | fb = to_intel_framebuffer(enabled->primary->fb); | |
1590 | ||
1591 | /* self-refresh seems busted with untiled */ | |
1592 | if (fb->obj->tiling_mode == I915_TILING_NONE) | |
1593 | enabled = NULL; | |
1594 | } | |
1595 | ||
b445e3b0 ED |
1596 | /* |
1597 | * Overlay gets an aggressive default since video jitter is bad. | |
1598 | */ | |
1599 | cwm = 2; | |
1600 | ||
1601 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1602 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1603 | |
1604 | /* Calc sr entries for one plane configs */ | |
1605 | if (HAS_FW_BLC(dev) && enabled) { | |
1606 | /* self-refresh has much higher latency */ | |
1607 | static const int sr_latency_ns = 6000; | |
4fe8590a VS |
1608 | const struct drm_display_mode *adjusted_mode = |
1609 | &to_intel_crtc(enabled)->config.adjusted_mode; | |
241bfc38 | 1610 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1611 | int htotal = adjusted_mode->crtc_htotal; |
f727b490 | 1612 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; |
f4510a27 | 1613 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1614 | unsigned long line_time_us; |
1615 | int entries; | |
1616 | ||
922044c9 | 1617 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1618 | |
1619 | /* Use ns/us then divide to preserve precision */ | |
1620 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1621 | pixel_size * hdisplay; | |
1622 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1623 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1624 | srwm = wm_info->fifo_size - entries; | |
1625 | if (srwm < 0) | |
1626 | srwm = 1; | |
1627 | ||
1628 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1629 | I915_WRITE(FW_BLC_SELF, | |
1630 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1631 | else if (IS_I915GM(dev)) | |
1632 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1633 | } | |
1634 | ||
1635 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1636 | planea_wm, planeb_wm, cwm, srwm); | |
1637 | ||
1638 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1639 | fwater_hi = (cwm & 0x1f); | |
1640 | ||
1641 | /* Set request length to 8 cachelines per fetch */ | |
1642 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1643 | fwater_hi = fwater_hi | (1 << 8); | |
1644 | ||
1645 | I915_WRITE(FW_BLC, fwater_lo); | |
1646 | I915_WRITE(FW_BLC2, fwater_hi); | |
1647 | ||
5209b1f4 ID |
1648 | if (enabled) |
1649 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1650 | } |
1651 | ||
feb56b93 | 1652 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1653 | { |
46ba614c | 1654 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1655 | struct drm_i915_private *dev_priv = dev->dev_private; |
1656 | struct drm_crtc *crtc; | |
241bfc38 | 1657 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1658 | uint32_t fwater_lo; |
1659 | int planea_wm; | |
1660 | ||
1661 | crtc = single_enabled_crtc(dev); | |
1662 | if (crtc == NULL) | |
1663 | return; | |
1664 | ||
241bfc38 DL |
1665 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1666 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
feb56b93 | 1667 | &i845_wm_info, |
b445e3b0 | 1668 | dev_priv->display.get_fifo_size(dev, 0), |
b9e0bda3 | 1669 | 4, latency_ns); |
b445e3b0 ED |
1670 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1671 | fwater_lo |= (3<<8) | planea_wm; | |
1672 | ||
1673 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1674 | ||
1675 | I915_WRITE(FW_BLC, fwater_lo); | |
1676 | } | |
1677 | ||
3658729a VS |
1678 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
1679 | struct drm_crtc *crtc) | |
801bcfff PZ |
1680 | { |
1681 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fd4daa9c | 1682 | uint32_t pixel_rate; |
801bcfff | 1683 | |
241bfc38 | 1684 | pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; |
801bcfff PZ |
1685 | |
1686 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1687 | * adjust the pixel_rate here. */ | |
1688 | ||
fd4daa9c | 1689 | if (intel_crtc->config.pch_pfit.enabled) { |
801bcfff | 1690 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
fd4daa9c | 1691 | uint32_t pfit_size = intel_crtc->config.pch_pfit.size; |
801bcfff | 1692 | |
37327abd VS |
1693 | pipe_w = intel_crtc->config.pipe_src_w; |
1694 | pipe_h = intel_crtc->config.pipe_src_h; | |
801bcfff PZ |
1695 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1696 | pfit_h = pfit_size & 0xFFFF; | |
1697 | if (pipe_w < pfit_w) | |
1698 | pipe_w = pfit_w; | |
1699 | if (pipe_h < pfit_h) | |
1700 | pipe_h = pfit_h; | |
1701 | ||
1702 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1703 | pfit_w * pfit_h); | |
1704 | } | |
1705 | ||
1706 | return pixel_rate; | |
1707 | } | |
1708 | ||
37126462 | 1709 | /* latency must be in 0.1us units. */ |
23297044 | 1710 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1711 | uint32_t latency) |
1712 | { | |
1713 | uint64_t ret; | |
1714 | ||
3312ba65 VS |
1715 | if (WARN(latency == 0, "Latency value missing\n")) |
1716 | return UINT_MAX; | |
1717 | ||
801bcfff PZ |
1718 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1719 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1720 | ||
1721 | return ret; | |
1722 | } | |
1723 | ||
37126462 | 1724 | /* latency must be in 0.1us units. */ |
23297044 | 1725 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1726 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1727 | uint32_t latency) | |
1728 | { | |
1729 | uint32_t ret; | |
1730 | ||
3312ba65 VS |
1731 | if (WARN(latency == 0, "Latency value missing\n")) |
1732 | return UINT_MAX; | |
1733 | ||
801bcfff PZ |
1734 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1735 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1736 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1737 | return ret; | |
1738 | } | |
1739 | ||
23297044 | 1740 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1741 | uint8_t bytes_per_pixel) |
1742 | { | |
1743 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1744 | } | |
1745 | ||
820c1980 | 1746 | struct ilk_pipe_wm_parameters { |
801bcfff | 1747 | bool active; |
801bcfff PZ |
1748 | uint32_t pipe_htotal; |
1749 | uint32_t pixel_rate; | |
c35426d2 VS |
1750 | struct intel_plane_wm_parameters pri; |
1751 | struct intel_plane_wm_parameters spr; | |
1752 | struct intel_plane_wm_parameters cur; | |
801bcfff PZ |
1753 | }; |
1754 | ||
820c1980 | 1755 | struct ilk_wm_maximums { |
cca32e9a PZ |
1756 | uint16_t pri; |
1757 | uint16_t spr; | |
1758 | uint16_t cur; | |
1759 | uint16_t fbc; | |
1760 | }; | |
1761 | ||
240264f4 VS |
1762 | /* used in computing the new watermarks state */ |
1763 | struct intel_wm_config { | |
1764 | unsigned int num_pipes_active; | |
1765 | bool sprites_enabled; | |
1766 | bool sprites_scaled; | |
240264f4 VS |
1767 | }; |
1768 | ||
37126462 VS |
1769 | /* |
1770 | * For both WM_PIPE and WM_LP. | |
1771 | * mem_value must be in 0.1us units. | |
1772 | */ | |
820c1980 | 1773 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
cca32e9a PZ |
1774 | uint32_t mem_value, |
1775 | bool is_lp) | |
801bcfff | 1776 | { |
cca32e9a PZ |
1777 | uint32_t method1, method2; |
1778 | ||
c35426d2 | 1779 | if (!params->active || !params->pri.enabled) |
801bcfff PZ |
1780 | return 0; |
1781 | ||
23297044 | 1782 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1783 | params->pri.bytes_per_pixel, |
cca32e9a PZ |
1784 | mem_value); |
1785 | ||
1786 | if (!is_lp) | |
1787 | return method1; | |
1788 | ||
23297044 | 1789 | method2 = ilk_wm_method2(params->pixel_rate, |
cca32e9a | 1790 | params->pipe_htotal, |
c35426d2 VS |
1791 | params->pri.horiz_pixels, |
1792 | params->pri.bytes_per_pixel, | |
cca32e9a PZ |
1793 | mem_value); |
1794 | ||
1795 | return min(method1, method2); | |
801bcfff PZ |
1796 | } |
1797 | ||
37126462 VS |
1798 | /* |
1799 | * For both WM_PIPE and WM_LP. | |
1800 | * mem_value must be in 0.1us units. | |
1801 | */ | |
820c1980 | 1802 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1803 | uint32_t mem_value) |
1804 | { | |
1805 | uint32_t method1, method2; | |
1806 | ||
c35426d2 | 1807 | if (!params->active || !params->spr.enabled) |
801bcfff PZ |
1808 | return 0; |
1809 | ||
23297044 | 1810 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1811 | params->spr.bytes_per_pixel, |
801bcfff | 1812 | mem_value); |
23297044 | 1813 | method2 = ilk_wm_method2(params->pixel_rate, |
801bcfff | 1814 | params->pipe_htotal, |
c35426d2 VS |
1815 | params->spr.horiz_pixels, |
1816 | params->spr.bytes_per_pixel, | |
801bcfff PZ |
1817 | mem_value); |
1818 | return min(method1, method2); | |
1819 | } | |
1820 | ||
37126462 VS |
1821 | /* |
1822 | * For both WM_PIPE and WM_LP. | |
1823 | * mem_value must be in 0.1us units. | |
1824 | */ | |
820c1980 | 1825 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1826 | uint32_t mem_value) |
1827 | { | |
c35426d2 | 1828 | if (!params->active || !params->cur.enabled) |
801bcfff PZ |
1829 | return 0; |
1830 | ||
23297044 | 1831 | return ilk_wm_method2(params->pixel_rate, |
801bcfff | 1832 | params->pipe_htotal, |
c35426d2 VS |
1833 | params->cur.horiz_pixels, |
1834 | params->cur.bytes_per_pixel, | |
801bcfff PZ |
1835 | mem_value); |
1836 | } | |
1837 | ||
cca32e9a | 1838 | /* Only for WM_LP. */ |
820c1980 | 1839 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
1fda9882 | 1840 | uint32_t pri_val) |
cca32e9a | 1841 | { |
c35426d2 | 1842 | if (!params->active || !params->pri.enabled) |
cca32e9a PZ |
1843 | return 0; |
1844 | ||
23297044 | 1845 | return ilk_wm_fbc(pri_val, |
c35426d2 VS |
1846 | params->pri.horiz_pixels, |
1847 | params->pri.bytes_per_pixel); | |
cca32e9a PZ |
1848 | } |
1849 | ||
158ae64f VS |
1850 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1851 | { | |
416f4727 VS |
1852 | if (INTEL_INFO(dev)->gen >= 8) |
1853 | return 3072; | |
1854 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1855 | return 768; |
1856 | else | |
1857 | return 512; | |
1858 | } | |
1859 | ||
4e975081 VS |
1860 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1861 | int level, bool is_sprite) | |
1862 | { | |
1863 | if (INTEL_INFO(dev)->gen >= 8) | |
1864 | /* BDW primary/sprite plane watermarks */ | |
1865 | return level == 0 ? 255 : 2047; | |
1866 | else if (INTEL_INFO(dev)->gen >= 7) | |
1867 | /* IVB/HSW primary/sprite plane watermarks */ | |
1868 | return level == 0 ? 127 : 1023; | |
1869 | else if (!is_sprite) | |
1870 | /* ILK/SNB primary plane watermarks */ | |
1871 | return level == 0 ? 127 : 511; | |
1872 | else | |
1873 | /* ILK/SNB sprite plane watermarks */ | |
1874 | return level == 0 ? 63 : 255; | |
1875 | } | |
1876 | ||
1877 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
1878 | int level) | |
1879 | { | |
1880 | if (INTEL_INFO(dev)->gen >= 7) | |
1881 | return level == 0 ? 63 : 255; | |
1882 | else | |
1883 | return level == 0 ? 31 : 63; | |
1884 | } | |
1885 | ||
1886 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
1887 | { | |
1888 | if (INTEL_INFO(dev)->gen >= 8) | |
1889 | return 31; | |
1890 | else | |
1891 | return 15; | |
1892 | } | |
1893 | ||
158ae64f VS |
1894 | /* Calculate the maximum primary/sprite plane watermark */ |
1895 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1896 | int level, | |
240264f4 | 1897 | const struct intel_wm_config *config, |
158ae64f VS |
1898 | enum intel_ddb_partitioning ddb_partitioning, |
1899 | bool is_sprite) | |
1900 | { | |
1901 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
1902 | |
1903 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 1904 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
1905 | return 0; |
1906 | ||
1907 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 1908 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
1909 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1910 | ||
1911 | /* | |
1912 | * For some reason the non self refresh | |
1913 | * FIFO size is only half of the self | |
1914 | * refresh FIFO size on ILK/SNB. | |
1915 | */ | |
1916 | if (INTEL_INFO(dev)->gen <= 6) | |
1917 | fifo_size /= 2; | |
1918 | } | |
1919 | ||
240264f4 | 1920 | if (config->sprites_enabled) { |
158ae64f VS |
1921 | /* level 0 is always calculated with 1:1 split */ |
1922 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1923 | if (is_sprite) | |
1924 | fifo_size *= 5; | |
1925 | fifo_size /= 6; | |
1926 | } else { | |
1927 | fifo_size /= 2; | |
1928 | } | |
1929 | } | |
1930 | ||
1931 | /* clamp to max that the registers can hold */ | |
4e975081 | 1932 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
1933 | } |
1934 | ||
1935 | /* Calculate the maximum cursor plane watermark */ | |
1936 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
1937 | int level, |
1938 | const struct intel_wm_config *config) | |
158ae64f VS |
1939 | { |
1940 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 1941 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
1942 | return 64; |
1943 | ||
1944 | /* otherwise just report max that registers can hold */ | |
4e975081 | 1945 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
1946 | } |
1947 | ||
d34ff9c6 | 1948 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
1949 | int level, |
1950 | const struct intel_wm_config *config, | |
1951 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 1952 | struct ilk_wm_maximums *max) |
158ae64f | 1953 | { |
240264f4 VS |
1954 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1955 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1956 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 1957 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
1958 | } |
1959 | ||
a3cb4048 VS |
1960 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1961 | int level, | |
1962 | struct ilk_wm_maximums *max) | |
1963 | { | |
1964 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
1965 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
1966 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
1967 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1968 | } | |
1969 | ||
d9395655 | 1970 | static bool ilk_validate_wm_level(int level, |
820c1980 | 1971 | const struct ilk_wm_maximums *max, |
d9395655 | 1972 | struct intel_wm_level *result) |
a9786a11 VS |
1973 | { |
1974 | bool ret; | |
1975 | ||
1976 | /* already determined to be invalid? */ | |
1977 | if (!result->enable) | |
1978 | return false; | |
1979 | ||
1980 | result->enable = result->pri_val <= max->pri && | |
1981 | result->spr_val <= max->spr && | |
1982 | result->cur_val <= max->cur; | |
1983 | ||
1984 | ret = result->enable; | |
1985 | ||
1986 | /* | |
1987 | * HACK until we can pre-compute everything, | |
1988 | * and thus fail gracefully if LP0 watermarks | |
1989 | * are exceeded... | |
1990 | */ | |
1991 | if (level == 0 && !result->enable) { | |
1992 | if (result->pri_val > max->pri) | |
1993 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1994 | level, result->pri_val, max->pri); | |
1995 | if (result->spr_val > max->spr) | |
1996 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1997 | level, result->spr_val, max->spr); | |
1998 | if (result->cur_val > max->cur) | |
1999 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
2000 | level, result->cur_val, max->cur); | |
2001 | ||
2002 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
2003 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
2004 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
2005 | result->enable = true; | |
2006 | } | |
2007 | ||
a9786a11 VS |
2008 | return ret; |
2009 | } | |
2010 | ||
d34ff9c6 | 2011 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
6f5ddd17 | 2012 | int level, |
820c1980 | 2013 | const struct ilk_pipe_wm_parameters *p, |
1fd527cc | 2014 | struct intel_wm_level *result) |
6f5ddd17 VS |
2015 | { |
2016 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
2017 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
2018 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
2019 | ||
2020 | /* WM1+ latency values stored in 0.5us units */ | |
2021 | if (level > 0) { | |
2022 | pri_latency *= 5; | |
2023 | spr_latency *= 5; | |
2024 | cur_latency *= 5; | |
2025 | } | |
2026 | ||
2027 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
2028 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
2029 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
2030 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
2031 | result->enable = true; | |
2032 | } | |
2033 | ||
801bcfff PZ |
2034 | static uint32_t |
2035 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
2036 | { |
2037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 2038 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1011d8c4 | 2039 | struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
85a02deb | 2040 | u32 linetime, ips_linetime; |
1f8eeabf | 2041 | |
801bcfff PZ |
2042 | if (!intel_crtc_active(crtc)) |
2043 | return 0; | |
1011d8c4 | 2044 | |
1f8eeabf ED |
2045 | /* The WM are computed with base on how long it takes to fill a single |
2046 | * row at the given clock rate, multiplied by 8. | |
2047 | * */ | |
fec8cba3 JB |
2048 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
2049 | mode->crtc_clock); | |
2050 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
85a02deb | 2051 | intel_ddi_get_cdclk_freq(dev_priv)); |
1f8eeabf | 2052 | |
801bcfff PZ |
2053 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2054 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2055 | } |
2056 | ||
12b134df VS |
2057 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2058 | { | |
2059 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2060 | ||
a42a5719 | 2061 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
2062 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2063 | ||
2064 | wm[0] = (sskpd >> 56) & 0xFF; | |
2065 | if (wm[0] == 0) | |
2066 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2067 | wm[1] = (sskpd >> 4) & 0xFF; |
2068 | wm[2] = (sskpd >> 12) & 0xFF; | |
2069 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2070 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
2071 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2072 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
2073 | ||
2074 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2075 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2076 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2077 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
2078 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2079 | uint32_t mltr = I915_READ(MLTR_ILK); | |
2080 | ||
2081 | /* ILK primary LP0 latency is 700 ns */ | |
2082 | wm[0] = 7; | |
2083 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2084 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2085 | } |
2086 | } | |
2087 | ||
53615a5e VS |
2088 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2089 | { | |
2090 | /* ILK sprite LP0 latency is 1300 ns */ | |
2091 | if (INTEL_INFO(dev)->gen == 5) | |
2092 | wm[0] = 13; | |
2093 | } | |
2094 | ||
2095 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
2096 | { | |
2097 | /* ILK cursor LP0 latency is 1300 ns */ | |
2098 | if (INTEL_INFO(dev)->gen == 5) | |
2099 | wm[0] = 13; | |
2100 | ||
2101 | /* WaDoubleCursorLP3Latency:ivb */ | |
2102 | if (IS_IVYBRIDGE(dev)) | |
2103 | wm[3] *= 2; | |
2104 | } | |
2105 | ||
546c81fd | 2106 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 2107 | { |
26ec971e | 2108 | /* how many WM levels are we expecting */ |
a42a5719 | 2109 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ad0d6dc4 | 2110 | return 4; |
26ec971e | 2111 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 2112 | return 3; |
26ec971e | 2113 | else |
ad0d6dc4 VS |
2114 | return 2; |
2115 | } | |
2116 | ||
2117 | static void intel_print_wm_latency(struct drm_device *dev, | |
2118 | const char *name, | |
2119 | const uint16_t wm[5]) | |
2120 | { | |
2121 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
2122 | |
2123 | for (level = 0; level <= max_level; level++) { | |
2124 | unsigned int latency = wm[level]; | |
2125 | ||
2126 | if (latency == 0) { | |
2127 | DRM_ERROR("%s WM%d latency not provided\n", | |
2128 | name, level); | |
2129 | continue; | |
2130 | } | |
2131 | ||
2132 | /* WM1+ latency values in 0.5us units */ | |
2133 | if (level > 0) | |
2134 | latency *= 5; | |
2135 | ||
2136 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2137 | name, level, wm[level], | |
2138 | latency / 10, latency % 10); | |
2139 | } | |
2140 | } | |
2141 | ||
e95a2f75 VS |
2142 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2143 | uint16_t wm[5], uint16_t min) | |
2144 | { | |
2145 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
2146 | ||
2147 | if (wm[0] >= min) | |
2148 | return false; | |
2149 | ||
2150 | wm[0] = max(wm[0], min); | |
2151 | for (level = 1; level <= max_level; level++) | |
2152 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2153 | ||
2154 | return true; | |
2155 | } | |
2156 | ||
2157 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
2158 | { | |
2159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2160 | bool changed; | |
2161 | ||
2162 | /* | |
2163 | * The BIOS provided WM memory latency values are often | |
2164 | * inadequate for high resolution displays. Adjust them. | |
2165 | */ | |
2166 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2167 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2168 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2169 | ||
2170 | if (!changed) | |
2171 | return; | |
2172 | ||
2173 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
2174 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2175 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2176 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
2177 | } | |
2178 | ||
fa50ad61 | 2179 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2180 | { |
2181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2182 | ||
2183 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2184 | ||
2185 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2186 | sizeof(dev_priv->wm.pri_latency)); | |
2187 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2188 | sizeof(dev_priv->wm.pri_latency)); | |
2189 | ||
2190 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2191 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2192 | |
2193 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2194 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2195 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2196 | |
2197 | if (IS_GEN6(dev)) | |
2198 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
2199 | } |
2200 | ||
820c1980 | 2201 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
2a44b76b | 2202 | struct ilk_pipe_wm_parameters *p) |
1011d8c4 | 2203 | { |
7c4a395f VS |
2204 | struct drm_device *dev = crtc->dev; |
2205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2206 | enum pipe pipe = intel_crtc->pipe; | |
7c4a395f | 2207 | struct drm_plane *plane; |
1011d8c4 | 2208 | |
2a44b76b VS |
2209 | if (!intel_crtc_active(crtc)) |
2210 | return; | |
801bcfff | 2211 | |
2a44b76b VS |
2212 | p->active = true; |
2213 | p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; | |
2214 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); | |
2215 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; | |
2216 | p->cur.bytes_per_pixel = 4; | |
2217 | p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; | |
2218 | p->cur.horiz_pixels = intel_crtc->cursor_width; | |
2219 | /* TODO: for now, assume primary and cursor planes are always enabled. */ | |
2220 | p->pri.enabled = true; | |
2221 | p->cur.enabled = true; | |
7c4a395f | 2222 | |
af2b653b | 2223 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
801bcfff | 2224 | struct intel_plane *intel_plane = to_intel_plane(plane); |
801bcfff | 2225 | |
2a44b76b | 2226 | if (intel_plane->pipe == pipe) { |
7c4a395f | 2227 | p->spr = intel_plane->wm; |
2a44b76b VS |
2228 | break; |
2229 | } | |
2230 | } | |
2231 | } | |
2232 | ||
2233 | static void ilk_compute_wm_config(struct drm_device *dev, | |
2234 | struct intel_wm_config *config) | |
2235 | { | |
2236 | struct intel_crtc *intel_crtc; | |
2237 | ||
2238 | /* Compute the currently _active_ config */ | |
d3fcc808 | 2239 | for_each_intel_crtc(dev, intel_crtc) { |
2a44b76b | 2240 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
cca32e9a | 2241 | |
2a44b76b VS |
2242 | if (!wm->pipe_enabled) |
2243 | continue; | |
cca32e9a | 2244 | |
2a44b76b VS |
2245 | config->sprites_enabled |= wm->sprites_enabled; |
2246 | config->sprites_scaled |= wm->sprites_scaled; | |
2247 | config->num_pipes_active++; | |
cca32e9a | 2248 | } |
801bcfff PZ |
2249 | } |
2250 | ||
0b2ae6d7 VS |
2251 | /* Compute new watermarks for the pipe */ |
2252 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
820c1980 | 2253 | const struct ilk_pipe_wm_parameters *params, |
0b2ae6d7 VS |
2254 | struct intel_pipe_wm *pipe_wm) |
2255 | { | |
2256 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 2257 | const struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 VS |
2258 | int level, max_level = ilk_wm_max_level(dev); |
2259 | /* LP0 watermark maximums depend on this pipe alone */ | |
2260 | struct intel_wm_config config = { | |
2261 | .num_pipes_active = 1, | |
2262 | .sprites_enabled = params->spr.enabled, | |
2263 | .sprites_scaled = params->spr.scaled, | |
2264 | }; | |
820c1980 | 2265 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2266 | |
2a44b76b VS |
2267 | pipe_wm->pipe_enabled = params->active; |
2268 | pipe_wm->sprites_enabled = params->spr.enabled; | |
2269 | pipe_wm->sprites_scaled = params->spr.scaled; | |
2270 | ||
7b39a0b7 VS |
2271 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2272 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
2273 | max_level = 1; | |
2274 | ||
2275 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
2276 | if (params->spr.scaled) | |
2277 | max_level = 0; | |
2278 | ||
a3cb4048 | 2279 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
0b2ae6d7 | 2280 | |
a42a5719 | 2281 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2282 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 | 2283 | |
a3cb4048 VS |
2284 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2285 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2286 | ||
0b2ae6d7 | 2287 | /* At least LP0 must be valid */ |
a3cb4048 VS |
2288 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2289 | return false; | |
2290 | ||
2291 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2292 | ||
2293 | for (level = 1; level <= max_level; level++) { | |
2294 | struct intel_wm_level wm = {}; | |
2295 | ||
2296 | ilk_compute_wm_level(dev_priv, level, params, &wm); | |
2297 | ||
2298 | /* | |
2299 | * Disable any watermark level that exceeds the | |
2300 | * register maximums since such watermarks are | |
2301 | * always invalid. | |
2302 | */ | |
2303 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2304 | break; | |
2305 | ||
2306 | pipe_wm->wm[level] = wm; | |
2307 | } | |
2308 | ||
2309 | return true; | |
0b2ae6d7 VS |
2310 | } |
2311 | ||
2312 | /* | |
2313 | * Merge the watermarks from all active pipes for a specific level. | |
2314 | */ | |
2315 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2316 | int level, | |
2317 | struct intel_wm_level *ret_wm) | |
2318 | { | |
2319 | const struct intel_crtc *intel_crtc; | |
2320 | ||
d52fea5b VS |
2321 | ret_wm->enable = true; |
2322 | ||
d3fcc808 | 2323 | for_each_intel_crtc(dev, intel_crtc) { |
fe392efd VS |
2324 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
2325 | const struct intel_wm_level *wm = &active->wm[level]; | |
2326 | ||
2327 | if (!active->pipe_enabled) | |
2328 | continue; | |
0b2ae6d7 | 2329 | |
d52fea5b VS |
2330 | /* |
2331 | * The watermark values may have been used in the past, | |
2332 | * so we must maintain them in the registers for some | |
2333 | * time even if the level is now disabled. | |
2334 | */ | |
0b2ae6d7 | 2335 | if (!wm->enable) |
d52fea5b | 2336 | ret_wm->enable = false; |
0b2ae6d7 VS |
2337 | |
2338 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2339 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2340 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2341 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2342 | } | |
0b2ae6d7 VS |
2343 | } |
2344 | ||
2345 | /* | |
2346 | * Merge all low power watermarks for all active pipes. | |
2347 | */ | |
2348 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2349 | const struct intel_wm_config *config, |
820c1980 | 2350 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2351 | struct intel_pipe_wm *merged) |
2352 | { | |
2353 | int level, max_level = ilk_wm_max_level(dev); | |
d52fea5b | 2354 | int last_enabled_level = max_level; |
0b2ae6d7 | 2355 | |
0ba22e26 VS |
2356 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2357 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2358 | config->num_pipes_active > 1) | |
2359 | return; | |
2360 | ||
6c8b6c28 VS |
2361 | /* ILK: FBC WM must be disabled always */ |
2362 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2363 | |
2364 | /* merge each WM1+ level */ | |
2365 | for (level = 1; level <= max_level; level++) { | |
2366 | struct intel_wm_level *wm = &merged->wm[level]; | |
2367 | ||
2368 | ilk_merge_wm_level(dev, level, wm); | |
2369 | ||
d52fea5b VS |
2370 | if (level > last_enabled_level) |
2371 | wm->enable = false; | |
2372 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2373 | /* make sure all following levels get disabled */ | |
2374 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2375 | |
2376 | /* | |
2377 | * The spec says it is preferred to disable | |
2378 | * FBC WMs instead of disabling a WM level. | |
2379 | */ | |
2380 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2381 | if (wm->enable) |
2382 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2383 | wm->fbc_val = 0; |
2384 | } | |
2385 | } | |
6c8b6c28 VS |
2386 | |
2387 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2388 | /* | |
2389 | * FIXME this is racy. FBC might get enabled later. | |
2390 | * What we should check here is whether FBC can be | |
2391 | * enabled sometime later. | |
2392 | */ | |
2393 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2394 | for (level = 2; level <= max_level; level++) { | |
2395 | struct intel_wm_level *wm = &merged->wm[level]; | |
2396 | ||
2397 | wm->enable = false; | |
2398 | } | |
2399 | } | |
0b2ae6d7 VS |
2400 | } |
2401 | ||
b380ca3c VS |
2402 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2403 | { | |
2404 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2405 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2406 | } | |
2407 | ||
a68d68ee VS |
2408 | /* The value we need to program into the WM_LPx latency field */ |
2409 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2410 | { | |
2411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2412 | ||
a42a5719 | 2413 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2414 | return 2 * level; |
2415 | else | |
2416 | return dev_priv->wm.pri_latency[level]; | |
2417 | } | |
2418 | ||
820c1980 | 2419 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2420 | const struct intel_pipe_wm *merged, |
609cedef | 2421 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2422 | struct ilk_wm_values *results) |
801bcfff | 2423 | { |
0b2ae6d7 VS |
2424 | struct intel_crtc *intel_crtc; |
2425 | int level, wm_lp; | |
cca32e9a | 2426 | |
0362c781 | 2427 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2428 | results->partitioning = partitioning; |
cca32e9a | 2429 | |
0b2ae6d7 | 2430 | /* LP1+ register values */ |
cca32e9a | 2431 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2432 | const struct intel_wm_level *r; |
801bcfff | 2433 | |
b380ca3c | 2434 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2435 | |
0362c781 | 2436 | r = &merged->wm[level]; |
cca32e9a | 2437 | |
d52fea5b VS |
2438 | /* |
2439 | * Maintain the watermark values even if the level is | |
2440 | * disabled. Doing otherwise could cause underruns. | |
2441 | */ | |
2442 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2443 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2444 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2445 | r->cur_val; | |
2446 | ||
d52fea5b VS |
2447 | if (r->enable) |
2448 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2449 | ||
416f4727 VS |
2450 | if (INTEL_INFO(dev)->gen >= 8) |
2451 | results->wm_lp[wm_lp - 1] |= | |
2452 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2453 | else | |
2454 | results->wm_lp[wm_lp - 1] |= | |
2455 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2456 | ||
d52fea5b VS |
2457 | /* |
2458 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2459 | * level is disabled. Doing otherwise could cause underruns. | |
2460 | */ | |
6cef2b8a VS |
2461 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2462 | WARN_ON(wm_lp != 1); | |
2463 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2464 | } else | |
2465 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2466 | } |
801bcfff | 2467 | |
0b2ae6d7 | 2468 | /* LP0 register values */ |
d3fcc808 | 2469 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 VS |
2470 | enum pipe pipe = intel_crtc->pipe; |
2471 | const struct intel_wm_level *r = | |
2472 | &intel_crtc->wm.active.wm[0]; | |
2473 | ||
2474 | if (WARN_ON(!r->enable)) | |
2475 | continue; | |
2476 | ||
2477 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
1011d8c4 | 2478 | |
0b2ae6d7 VS |
2479 | results->wm_pipe[pipe] = |
2480 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2481 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2482 | r->cur_val; | |
801bcfff PZ |
2483 | } |
2484 | } | |
2485 | ||
861f3389 PZ |
2486 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2487 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2488 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2489 | struct intel_pipe_wm *r1, |
2490 | struct intel_pipe_wm *r2) | |
861f3389 | 2491 | { |
198a1e9b VS |
2492 | int level, max_level = ilk_wm_max_level(dev); |
2493 | int level1 = 0, level2 = 0; | |
861f3389 | 2494 | |
198a1e9b VS |
2495 | for (level = 1; level <= max_level; level++) { |
2496 | if (r1->wm[level].enable) | |
2497 | level1 = level; | |
2498 | if (r2->wm[level].enable) | |
2499 | level2 = level; | |
861f3389 PZ |
2500 | } |
2501 | ||
198a1e9b VS |
2502 | if (level1 == level2) { |
2503 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2504 | return r2; |
2505 | else | |
2506 | return r1; | |
198a1e9b | 2507 | } else if (level1 > level2) { |
861f3389 PZ |
2508 | return r1; |
2509 | } else { | |
2510 | return r2; | |
2511 | } | |
2512 | } | |
2513 | ||
49a687c4 VS |
2514 | /* dirty bits used to track which watermarks need changes */ |
2515 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2516 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2517 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2518 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2519 | #define WM_DIRTY_FBC (1 << 24) | |
2520 | #define WM_DIRTY_DDB (1 << 25) | |
2521 | ||
2522 | static unsigned int ilk_compute_wm_dirty(struct drm_device *dev, | |
820c1980 ID |
2523 | const struct ilk_wm_values *old, |
2524 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2525 | { |
2526 | unsigned int dirty = 0; | |
2527 | enum pipe pipe; | |
2528 | int wm_lp; | |
2529 | ||
2530 | for_each_pipe(pipe) { | |
2531 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { | |
2532 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2533 | /* Must disable LP1+ watermarks too */ | |
2534 | dirty |= WM_DIRTY_LP_ALL; | |
2535 | } | |
2536 | ||
2537 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2538 | dirty |= WM_DIRTY_PIPE(pipe); | |
2539 | /* Must disable LP1+ watermarks too */ | |
2540 | dirty |= WM_DIRTY_LP_ALL; | |
2541 | } | |
2542 | } | |
2543 | ||
2544 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2545 | dirty |= WM_DIRTY_FBC; | |
2546 | /* Must disable LP1+ watermarks too */ | |
2547 | dirty |= WM_DIRTY_LP_ALL; | |
2548 | } | |
2549 | ||
2550 | if (old->partitioning != new->partitioning) { | |
2551 | dirty |= WM_DIRTY_DDB; | |
2552 | /* Must disable LP1+ watermarks too */ | |
2553 | dirty |= WM_DIRTY_LP_ALL; | |
2554 | } | |
2555 | ||
2556 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2557 | if (dirty & WM_DIRTY_LP_ALL) | |
2558 | return dirty; | |
2559 | ||
2560 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2561 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2562 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2563 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2564 | break; | |
2565 | } | |
2566 | ||
2567 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2568 | for (; wm_lp <= 3; wm_lp++) | |
2569 | dirty |= WM_DIRTY_LP(wm_lp); | |
2570 | ||
2571 | return dirty; | |
2572 | } | |
2573 | ||
8553c18e VS |
2574 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2575 | unsigned int dirty) | |
801bcfff | 2576 | { |
820c1980 | 2577 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2578 | bool changed = false; |
801bcfff | 2579 | |
facd619b VS |
2580 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2581 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2582 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2583 | changed = true; |
facd619b VS |
2584 | } |
2585 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2586 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2587 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2588 | changed = true; |
facd619b VS |
2589 | } |
2590 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2591 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2592 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2593 | changed = true; |
facd619b | 2594 | } |
801bcfff | 2595 | |
facd619b VS |
2596 | /* |
2597 | * Don't touch WM1S_LP_EN here. | |
2598 | * Doing so could cause underruns. | |
2599 | */ | |
6cef2b8a | 2600 | |
8553c18e VS |
2601 | return changed; |
2602 | } | |
2603 | ||
2604 | /* | |
2605 | * The spec says we shouldn't write when we don't need, because every write | |
2606 | * causes WMs to be re-evaluated, expending some power. | |
2607 | */ | |
820c1980 ID |
2608 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2609 | struct ilk_wm_values *results) | |
8553c18e VS |
2610 | { |
2611 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2612 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2613 | unsigned int dirty; |
2614 | uint32_t val; | |
2615 | ||
2616 | dirty = ilk_compute_wm_dirty(dev, previous, results); | |
2617 | if (!dirty) | |
2618 | return; | |
2619 | ||
2620 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2621 | ||
49a687c4 | 2622 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2623 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2624 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2625 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2626 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2627 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2628 | ||
49a687c4 | 2629 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2630 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2631 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2632 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2633 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2634 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2635 | ||
49a687c4 | 2636 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2637 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2638 | val = I915_READ(WM_MISC); |
2639 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2640 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2641 | else | |
2642 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2643 | I915_WRITE(WM_MISC, val); | |
2644 | } else { | |
2645 | val = I915_READ(DISP_ARB_CTL2); | |
2646 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2647 | val &= ~DISP_DATA_PARTITION_5_6; | |
2648 | else | |
2649 | val |= DISP_DATA_PARTITION_5_6; | |
2650 | I915_WRITE(DISP_ARB_CTL2, val); | |
2651 | } | |
1011d8c4 PZ |
2652 | } |
2653 | ||
49a687c4 | 2654 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2655 | val = I915_READ(DISP_ARB_CTL); |
2656 | if (results->enable_fbc_wm) | |
2657 | val &= ~DISP_FBC_WM_DIS; | |
2658 | else | |
2659 | val |= DISP_FBC_WM_DIS; | |
2660 | I915_WRITE(DISP_ARB_CTL, val); | |
2661 | } | |
2662 | ||
954911eb ID |
2663 | if (dirty & WM_DIRTY_LP(1) && |
2664 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2665 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2666 | ||
2667 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2668 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2669 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2670 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2671 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2672 | } | |
801bcfff | 2673 | |
facd619b | 2674 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2675 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2676 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2677 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2678 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2679 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2680 | |
2681 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2682 | } |
2683 | ||
8553c18e VS |
2684 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2685 | { | |
2686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2687 | ||
2688 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2689 | } | |
2690 | ||
820c1980 | 2691 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 2692 | { |
7c4a395f | 2693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
46ba614c | 2694 | struct drm_device *dev = crtc->dev; |
801bcfff | 2695 | struct drm_i915_private *dev_priv = dev->dev_private; |
820c1980 ID |
2696 | struct ilk_wm_maximums max; |
2697 | struct ilk_pipe_wm_parameters params = {}; | |
2698 | struct ilk_wm_values results = {}; | |
77c122bc | 2699 | enum intel_ddb_partitioning partitioning; |
7c4a395f | 2700 | struct intel_pipe_wm pipe_wm = {}; |
198a1e9b | 2701 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
a485bfb8 | 2702 | struct intel_wm_config config = {}; |
7c4a395f | 2703 | |
2a44b76b | 2704 | ilk_compute_wm_parameters(crtc, ¶ms); |
7c4a395f VS |
2705 | |
2706 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
2707 | ||
2708 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
2709 | return; | |
861f3389 | 2710 | |
7c4a395f | 2711 | intel_crtc->wm.active = pipe_wm; |
861f3389 | 2712 | |
2a44b76b VS |
2713 | ilk_compute_wm_config(dev, &config); |
2714 | ||
34982fe1 | 2715 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
0ba22e26 | 2716 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
a485bfb8 VS |
2717 | |
2718 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 VS |
2719 | if (INTEL_INFO(dev)->gen >= 7 && |
2720 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
34982fe1 | 2721 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
0ba22e26 | 2722 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
0362c781 | 2723 | |
820c1980 | 2724 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 2725 | } else { |
198a1e9b | 2726 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
2727 | } |
2728 | ||
198a1e9b | 2729 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 2730 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 2731 | |
820c1980 | 2732 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 2733 | |
820c1980 | 2734 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
2735 | } |
2736 | ||
820c1980 | 2737 | static void ilk_update_sprite_wm(struct drm_plane *plane, |
adf3d35e | 2738 | struct drm_crtc *crtc, |
526682e9 | 2739 | uint32_t sprite_width, int pixel_size, |
bdd57d03 | 2740 | bool enabled, bool scaled) |
526682e9 | 2741 | { |
8553c18e | 2742 | struct drm_device *dev = plane->dev; |
adf3d35e | 2743 | struct intel_plane *intel_plane = to_intel_plane(plane); |
526682e9 | 2744 | |
adf3d35e VS |
2745 | intel_plane->wm.enabled = enabled; |
2746 | intel_plane->wm.scaled = scaled; | |
2747 | intel_plane->wm.horiz_pixels = sprite_width; | |
2748 | intel_plane->wm.bytes_per_pixel = pixel_size; | |
526682e9 | 2749 | |
8553c18e VS |
2750 | /* |
2751 | * IVB workaround: must disable low power watermarks for at least | |
2752 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
2753 | * when scaling is disabled. | |
2754 | * | |
2755 | * WaCxSRDisabledForSpriteScaling:ivb | |
2756 | */ | |
2757 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
2758 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
2759 | ||
820c1980 | 2760 | ilk_update_wm(crtc); |
526682e9 PZ |
2761 | } |
2762 | ||
243e6a44 VS |
2763 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
2764 | { | |
2765 | struct drm_device *dev = crtc->dev; | |
2766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 2767 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
2768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2769 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
2770 | enum pipe pipe = intel_crtc->pipe; | |
2771 | static const unsigned int wm0_pipe_reg[] = { | |
2772 | [PIPE_A] = WM0_PIPEA_ILK, | |
2773 | [PIPE_B] = WM0_PIPEB_ILK, | |
2774 | [PIPE_C] = WM0_PIPEC_IVB, | |
2775 | }; | |
2776 | ||
2777 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 2778 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2779 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 2780 | |
2a44b76b VS |
2781 | active->pipe_enabled = intel_crtc_active(crtc); |
2782 | ||
2783 | if (active->pipe_enabled) { | |
243e6a44 VS |
2784 | u32 tmp = hw->wm_pipe[pipe]; |
2785 | ||
2786 | /* | |
2787 | * For active pipes LP0 watermark is marked as | |
2788 | * enabled, and LP1+ watermaks as disabled since | |
2789 | * we can't really reverse compute them in case | |
2790 | * multiple pipes are active. | |
2791 | */ | |
2792 | active->wm[0].enable = true; | |
2793 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
2794 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
2795 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
2796 | active->linetime = hw->wm_linetime[pipe]; | |
2797 | } else { | |
2798 | int level, max_level = ilk_wm_max_level(dev); | |
2799 | ||
2800 | /* | |
2801 | * For inactive pipes, all watermark levels | |
2802 | * should be marked as enabled but zeroed, | |
2803 | * which is what we'd compute them to. | |
2804 | */ | |
2805 | for (level = 0; level <= max_level; level++) | |
2806 | active->wm[level].enable = true; | |
2807 | } | |
2808 | } | |
2809 | ||
2810 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
2811 | { | |
2812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 2813 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
2814 | struct drm_crtc *crtc; |
2815 | ||
70e1e0ec | 2816 | for_each_crtc(dev, crtc) |
243e6a44 VS |
2817 | ilk_pipe_wm_get_hw_state(crtc); |
2818 | ||
2819 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
2820 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
2821 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
2822 | ||
2823 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
2824 | if (INTEL_INFO(dev)->gen >= 7) { |
2825 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
2826 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
2827 | } | |
243e6a44 | 2828 | |
a42a5719 | 2829 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
2830 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
2831 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
2832 | else if (IS_IVYBRIDGE(dev)) | |
2833 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
2834 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
2835 | |
2836 | hw->enable_fbc_wm = | |
2837 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
2838 | } | |
2839 | ||
b445e3b0 ED |
2840 | /** |
2841 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
2842 | * | |
2843 | * Calculate watermark values for the various WM regs based on current mode | |
2844 | * and plane configuration. | |
2845 | * | |
2846 | * There are several cases to deal with here: | |
2847 | * - normal (i.e. non-self-refresh) | |
2848 | * - self-refresh (SR) mode | |
2849 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
2850 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
2851 | * lines), so need to account for TLB latency | |
2852 | * | |
2853 | * The normal calculation is: | |
2854 | * watermark = dotclock * bytes per pixel * latency | |
2855 | * where latency is platform & configuration dependent (we assume pessimal | |
2856 | * values here). | |
2857 | * | |
2858 | * The SR calculation is: | |
2859 | * watermark = (trunc(latency/line time)+1) * surface width * | |
2860 | * bytes per pixel | |
2861 | * where | |
2862 | * line time = htotal / dotclock | |
2863 | * surface width = hdisplay for normal plane and 64 for cursor | |
2864 | * and latency is assumed to be high, as above. | |
2865 | * | |
2866 | * The final value programmed to the register should always be rounded up, | |
2867 | * and include an extra 2 entries to account for clock crossings. | |
2868 | * | |
2869 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
2870 | * to set the non-SR watermarks to 8. | |
2871 | */ | |
46ba614c | 2872 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 2873 | { |
46ba614c | 2874 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
2875 | |
2876 | if (dev_priv->display.update_wm) | |
46ba614c | 2877 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
2878 | } |
2879 | ||
adf3d35e VS |
2880 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
2881 | struct drm_crtc *crtc, | |
4c4ff43a | 2882 | uint32_t sprite_width, int pixel_size, |
39db4a4d | 2883 | bool enabled, bool scaled) |
b445e3b0 | 2884 | { |
adf3d35e | 2885 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
b445e3b0 ED |
2886 | |
2887 | if (dev_priv->display.update_sprite_wm) | |
adf3d35e | 2888 | dev_priv->display.update_sprite_wm(plane, crtc, sprite_width, |
39db4a4d | 2889 | pixel_size, enabled, scaled); |
b445e3b0 ED |
2890 | } |
2891 | ||
2b4e57bd ED |
2892 | static struct drm_i915_gem_object * |
2893 | intel_alloc_context_page(struct drm_device *dev) | |
2894 | { | |
2895 | struct drm_i915_gem_object *ctx; | |
2896 | int ret; | |
2897 | ||
2898 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
2899 | ||
2900 | ctx = i915_gem_alloc_object(dev, 4096); | |
2901 | if (!ctx) { | |
2902 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | |
2903 | return NULL; | |
2904 | } | |
2905 | ||
c69766f2 | 2906 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
2b4e57bd ED |
2907 | if (ret) { |
2908 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
2909 | goto err_unref; | |
2910 | } | |
2911 | ||
2912 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); | |
2913 | if (ret) { | |
2914 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
2915 | goto err_unpin; | |
2916 | } | |
2917 | ||
2918 | return ctx; | |
2919 | ||
2920 | err_unpin: | |
d7f46fc4 | 2921 | i915_gem_object_ggtt_unpin(ctx); |
2b4e57bd ED |
2922 | err_unref: |
2923 | drm_gem_object_unreference(&ctx->base); | |
2b4e57bd ED |
2924 | return NULL; |
2925 | } | |
2926 | ||
9270388e DV |
2927 | /** |
2928 | * Lock protecting IPS related data structures | |
9270388e DV |
2929 | */ |
2930 | DEFINE_SPINLOCK(mchdev_lock); | |
2931 | ||
2932 | /* Global for IPS driver to get at the current i915 device. Protected by | |
2933 | * mchdev_lock. */ | |
2934 | static struct drm_i915_private *i915_mch_dev; | |
2935 | ||
2b4e57bd ED |
2936 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
2937 | { | |
2938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2939 | u16 rgvswctl; | |
2940 | ||
9270388e DV |
2941 | assert_spin_locked(&mchdev_lock); |
2942 | ||
2b4e57bd ED |
2943 | rgvswctl = I915_READ16(MEMSWCTL); |
2944 | if (rgvswctl & MEMCTL_CMD_STS) { | |
2945 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
2946 | return false; /* still busy with another command */ | |
2947 | } | |
2948 | ||
2949 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
2950 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
2951 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
2952 | POSTING_READ16(MEMSWCTL); | |
2953 | ||
2954 | rgvswctl |= MEMCTL_CMD_STS; | |
2955 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
2956 | ||
2957 | return true; | |
2958 | } | |
2959 | ||
8090c6b9 | 2960 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
2961 | { |
2962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2963 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
2964 | u8 fmax, fmin, fstart, vstart; | |
2965 | ||
9270388e DV |
2966 | spin_lock_irq(&mchdev_lock); |
2967 | ||
2b4e57bd ED |
2968 | /* Enable temp reporting */ |
2969 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
2970 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
2971 | ||
2972 | /* 100ms RC evaluation intervals */ | |
2973 | I915_WRITE(RCUPEI, 100000); | |
2974 | I915_WRITE(RCDNEI, 100000); | |
2975 | ||
2976 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
2977 | I915_WRITE(RCBMAXAVG, 90000); | |
2978 | I915_WRITE(RCBMINAVG, 80000); | |
2979 | ||
2980 | I915_WRITE(MEMIHYST, 1); | |
2981 | ||
2982 | /* Set up min, max, and cur for interrupt handling */ | |
2983 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
2984 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
2985 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
2986 | MEMMODE_FSTART_SHIFT; | |
2987 | ||
2988 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
2989 | PXVFREQ_PX_SHIFT; | |
2990 | ||
20e4d407 DV |
2991 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
2992 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 2993 | |
20e4d407 DV |
2994 | dev_priv->ips.max_delay = fstart; |
2995 | dev_priv->ips.min_delay = fmin; | |
2996 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
2997 | |
2998 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
2999 | fmax, fmin, fstart); | |
3000 | ||
3001 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
3002 | ||
3003 | /* | |
3004 | * Interrupts will be enabled in ironlake_irq_postinstall | |
3005 | */ | |
3006 | ||
3007 | I915_WRITE(VIDSTART, vstart); | |
3008 | POSTING_READ(VIDSTART); | |
3009 | ||
3010 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
3011 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
3012 | ||
9270388e | 3013 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 3014 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 3015 | mdelay(1); |
2b4e57bd ED |
3016 | |
3017 | ironlake_set_drps(dev, fstart); | |
3018 | ||
20e4d407 | 3019 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 3020 | I915_READ(0x112e0); |
20e4d407 DV |
3021 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
3022 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
3023 | getrawmonotonic(&dev_priv->ips.last_time2); | |
9270388e DV |
3024 | |
3025 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
3026 | } |
3027 | ||
8090c6b9 | 3028 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
3029 | { |
3030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
3031 | u16 rgvswctl; |
3032 | ||
3033 | spin_lock_irq(&mchdev_lock); | |
3034 | ||
3035 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
3036 | |
3037 | /* Ack interrupts, disable EFC interrupt */ | |
3038 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
3039 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
3040 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
3041 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
3042 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
3043 | ||
3044 | /* Go back to the starting frequency */ | |
20e4d407 | 3045 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 3046 | mdelay(1); |
2b4e57bd ED |
3047 | rgvswctl |= MEMCTL_CMD_STS; |
3048 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 3049 | mdelay(1); |
2b4e57bd | 3050 | |
9270388e | 3051 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
3052 | } |
3053 | ||
acbe9475 DV |
3054 | /* There's a funny hw issue where the hw returns all 0 when reading from |
3055 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
3056 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
3057 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
3058 | */ | |
6917c7b9 | 3059 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 3060 | { |
7b9e0ae6 | 3061 | u32 limits; |
2b4e57bd | 3062 | |
20b46e59 DV |
3063 | /* Only set the down limit when we've reached the lowest level to avoid |
3064 | * getting more interrupts, otherwise leave this clear. This prevents a | |
3065 | * race in the hw when coming out of rc6: There's a tiny window where | |
3066 | * the hw runs at the minimal clock before selecting the desired | |
3067 | * frequency, if the down threshold expires in that window we will not | |
3068 | * receive a down interrupt. */ | |
b39fb297 BW |
3069 | limits = dev_priv->rps.max_freq_softlimit << 24; |
3070 | if (val <= dev_priv->rps.min_freq_softlimit) | |
3071 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
20b46e59 DV |
3072 | |
3073 | return limits; | |
3074 | } | |
3075 | ||
dd75fdc8 CW |
3076 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
3077 | { | |
3078 | int new_power; | |
3079 | ||
3080 | new_power = dev_priv->rps.power; | |
3081 | switch (dev_priv->rps.power) { | |
3082 | case LOW_POWER: | |
b39fb297 | 3083 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3084 | new_power = BETWEEN; |
3085 | break; | |
3086 | ||
3087 | case BETWEEN: | |
b39fb297 | 3088 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 3089 | new_power = LOW_POWER; |
b39fb297 | 3090 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3091 | new_power = HIGH_POWER; |
3092 | break; | |
3093 | ||
3094 | case HIGH_POWER: | |
b39fb297 | 3095 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3096 | new_power = BETWEEN; |
3097 | break; | |
3098 | } | |
3099 | /* Max/min bins are special */ | |
b39fb297 | 3100 | if (val == dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 3101 | new_power = LOW_POWER; |
b39fb297 | 3102 | if (val == dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
3103 | new_power = HIGH_POWER; |
3104 | if (new_power == dev_priv->rps.power) | |
3105 | return; | |
3106 | ||
3107 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
3108 | switch (new_power) { | |
3109 | case LOW_POWER: | |
3110 | /* Upclock if more than 95% busy over 16ms */ | |
3111 | I915_WRITE(GEN6_RP_UP_EI, 12500); | |
3112 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); | |
3113 | ||
3114 | /* Downclock if less than 85% busy over 32ms */ | |
3115 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3116 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); | |
3117 | ||
3118 | I915_WRITE(GEN6_RP_CONTROL, | |
3119 | GEN6_RP_MEDIA_TURBO | | |
3120 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3121 | GEN6_RP_MEDIA_IS_GFX | | |
3122 | GEN6_RP_ENABLE | | |
3123 | GEN6_RP_UP_BUSY_AVG | | |
3124 | GEN6_RP_DOWN_IDLE_AVG); | |
3125 | break; | |
3126 | ||
3127 | case BETWEEN: | |
3128 | /* Upclock if more than 90% busy over 13ms */ | |
3129 | I915_WRITE(GEN6_RP_UP_EI, 10250); | |
3130 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); | |
3131 | ||
3132 | /* Downclock if less than 75% busy over 32ms */ | |
3133 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3134 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); | |
3135 | ||
3136 | I915_WRITE(GEN6_RP_CONTROL, | |
3137 | GEN6_RP_MEDIA_TURBO | | |
3138 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3139 | GEN6_RP_MEDIA_IS_GFX | | |
3140 | GEN6_RP_ENABLE | | |
3141 | GEN6_RP_UP_BUSY_AVG | | |
3142 | GEN6_RP_DOWN_IDLE_AVG); | |
3143 | break; | |
3144 | ||
3145 | case HIGH_POWER: | |
3146 | /* Upclock if more than 85% busy over 10ms */ | |
3147 | I915_WRITE(GEN6_RP_UP_EI, 8000); | |
3148 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); | |
3149 | ||
3150 | /* Downclock if less than 60% busy over 32ms */ | |
3151 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3152 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); | |
3153 | ||
3154 | I915_WRITE(GEN6_RP_CONTROL, | |
3155 | GEN6_RP_MEDIA_TURBO | | |
3156 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3157 | GEN6_RP_MEDIA_IS_GFX | | |
3158 | GEN6_RP_ENABLE | | |
3159 | GEN6_RP_UP_BUSY_AVG | | |
3160 | GEN6_RP_DOWN_IDLE_AVG); | |
3161 | break; | |
3162 | } | |
3163 | ||
3164 | dev_priv->rps.power = new_power; | |
3165 | dev_priv->rps.last_adj = 0; | |
3166 | } | |
3167 | ||
2876ce73 CW |
3168 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
3169 | { | |
3170 | u32 mask = 0; | |
3171 | ||
3172 | if (val > dev_priv->rps.min_freq_softlimit) | |
3173 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; | |
3174 | if (val < dev_priv->rps.max_freq_softlimit) | |
3175 | mask |= GEN6_PM_RP_UP_THRESHOLD; | |
3176 | ||
3177 | /* IVB and SNB hard hangs on looping batchbuffer | |
3178 | * if GEN6_PM_UP_EI_EXPIRED is masked. | |
3179 | */ | |
3180 | if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) | |
3181 | mask |= GEN6_PM_RP_UP_EI_EXPIRED; | |
3182 | ||
baccd458 D |
3183 | if (IS_GEN8(dev_priv->dev)) |
3184 | mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
3185 | ||
2876ce73 CW |
3186 | return ~mask; |
3187 | } | |
3188 | ||
b8a5ff8d JM |
3189 | /* gen6_set_rps is called to update the frequency request, but should also be |
3190 | * called when the range (min_delay and max_delay) is modified so that we can | |
3191 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
20b46e59 DV |
3192 | void gen6_set_rps(struct drm_device *dev, u8 val) |
3193 | { | |
3194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 3195 | |
4fc688ce | 3196 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3197 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3198 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
004777cb | 3199 | |
eb64cad1 CW |
3200 | /* min/max delay may still have been modified so be sure to |
3201 | * write the limits value. | |
3202 | */ | |
3203 | if (val != dev_priv->rps.cur_freq) { | |
3204 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 3205 | |
50e6a2a7 | 3206 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
eb64cad1 CW |
3207 | I915_WRITE(GEN6_RPNSWREQ, |
3208 | HSW_FREQUENCY(val)); | |
3209 | else | |
3210 | I915_WRITE(GEN6_RPNSWREQ, | |
3211 | GEN6_FREQUENCY(val) | | |
3212 | GEN6_OFFSET(0) | | |
3213 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 3214 | } |
7b9e0ae6 | 3215 | |
7b9e0ae6 CW |
3216 | /* Make sure we continue to get interrupts |
3217 | * until we hit the minimum or maximum frequencies. | |
3218 | */ | |
eb64cad1 | 3219 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
2876ce73 | 3220 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 3221 | |
d5570a72 BW |
3222 | POSTING_READ(GEN6_RPNSWREQ); |
3223 | ||
b39fb297 | 3224 | dev_priv->rps.cur_freq = val; |
be2cde9a | 3225 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
3226 | } |
3227 | ||
76c3552f D |
3228 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
3229 | * | |
3230 | * * If Gfx is Idle, then | |
3231 | * 1. Mask Turbo interrupts | |
3232 | * 2. Bring up Gfx clock | |
3233 | * 3. Change the freq to Rpn and wait till P-Unit updates freq | |
3234 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down | |
3235 | * 5. Unmask Turbo interrupts | |
3236 | */ | |
3237 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
3238 | { | |
5549d25f D |
3239 | struct drm_device *dev = dev_priv->dev; |
3240 | ||
3241 | /* Latest VLV doesn't need to force the gfx clock */ | |
3242 | if (dev->pdev->revision >= 0xd) { | |
3243 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
3244 | return; | |
3245 | } | |
3246 | ||
76c3552f D |
3247 | /* |
3248 | * When we are idle. Drop to min voltage state. | |
3249 | */ | |
3250 | ||
b39fb297 | 3251 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
76c3552f D |
3252 | return; |
3253 | ||
3254 | /* Mask turbo interrupt so that they will not come in between */ | |
3255 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
3256 | ||
650ad970 | 3257 | vlv_force_gfx_clock(dev_priv, true); |
76c3552f | 3258 | |
b39fb297 | 3259 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
76c3552f D |
3260 | |
3261 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, | |
b39fb297 | 3262 | dev_priv->rps.min_freq_softlimit); |
76c3552f D |
3263 | |
3264 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) | |
3265 | & GENFREQSTATUS) == 0, 5)) | |
3266 | DRM_ERROR("timed out waiting for Punit\n"); | |
3267 | ||
650ad970 | 3268 | vlv_force_gfx_clock(dev_priv, false); |
76c3552f | 3269 | |
2876ce73 CW |
3270 | I915_WRITE(GEN6_PMINTRMSK, |
3271 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
76c3552f D |
3272 | } |
3273 | ||
b29c19b6 CW |
3274 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
3275 | { | |
691bb717 DL |
3276 | struct drm_device *dev = dev_priv->dev; |
3277 | ||
b29c19b6 | 3278 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 3279 | if (dev_priv->rps.enabled) { |
691bb717 | 3280 | if (IS_VALLEYVIEW(dev)) |
76c3552f | 3281 | vlv_set_rps_idle(dev_priv); |
c0951f0c | 3282 | else |
b39fb297 | 3283 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
c0951f0c CW |
3284 | dev_priv->rps.last_adj = 0; |
3285 | } | |
b29c19b6 CW |
3286 | mutex_unlock(&dev_priv->rps.hw_lock); |
3287 | } | |
3288 | ||
3289 | void gen6_rps_boost(struct drm_i915_private *dev_priv) | |
3290 | { | |
691bb717 DL |
3291 | struct drm_device *dev = dev_priv->dev; |
3292 | ||
b29c19b6 | 3293 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 3294 | if (dev_priv->rps.enabled) { |
691bb717 | 3295 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 3296 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c0951f0c | 3297 | else |
b39fb297 | 3298 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c0951f0c CW |
3299 | dev_priv->rps.last_adj = 0; |
3300 | } | |
b29c19b6 CW |
3301 | mutex_unlock(&dev_priv->rps.hw_lock); |
3302 | } | |
3303 | ||
0a073b84 JB |
3304 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
3305 | { | |
3306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a67092a | 3307 | |
0a073b84 | 3308 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3309 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3310 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
0a073b84 | 3311 | |
73008b98 | 3312 | DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", |
b39fb297 BW |
3313 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
3314 | dev_priv->rps.cur_freq, | |
2ec3815f | 3315 | vlv_gpu_freq(dev_priv, val), val); |
0a073b84 | 3316 | |
2876ce73 CW |
3317 | if (val != dev_priv->rps.cur_freq) |
3318 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); | |
0a073b84 | 3319 | |
09c87db8 | 3320 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
0a073b84 | 3321 | |
b39fb297 | 3322 | dev_priv->rps.cur_freq = val; |
2ec3815f | 3323 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
3324 | } |
3325 | ||
0961021a BW |
3326 | static void gen8_disable_rps_interrupts(struct drm_device *dev) |
3327 | { | |
3328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3329 | ||
992f191f | 3330 | I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP); |
0961021a BW |
3331 | I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) & |
3332 | ~dev_priv->pm_rps_events); | |
3333 | /* Complete PM interrupt masking here doesn't race with the rps work | |
3334 | * item again unmasking PM interrupts because that is using a different | |
3335 | * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in | |
3336 | * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which | |
3337 | * gen8_enable_rps will clean up. */ | |
3338 | ||
3339 | spin_lock_irq(&dev_priv->irq_lock); | |
3340 | dev_priv->rps.pm_iir = 0; | |
3341 | spin_unlock_irq(&dev_priv->irq_lock); | |
3342 | ||
3343 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); | |
3344 | } | |
3345 | ||
44fc7d5c | 3346 | static void gen6_disable_rps_interrupts(struct drm_device *dev) |
2b4e57bd ED |
3347 | { |
3348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3349 | ||
2b4e57bd | 3350 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
a6706b45 D |
3351 | I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & |
3352 | ~dev_priv->pm_rps_events); | |
2b4e57bd ED |
3353 | /* Complete PM interrupt masking here doesn't race with the rps work |
3354 | * item again unmasking PM interrupts because that is using a different | |
3355 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
3356 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
3357 | ||
59cdb63d | 3358 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 | 3359 | dev_priv->rps.pm_iir = 0; |
59cdb63d | 3360 | spin_unlock_irq(&dev_priv->irq_lock); |
2b4e57bd | 3361 | |
a6706b45 | 3362 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
2b4e57bd ED |
3363 | } |
3364 | ||
44fc7d5c | 3365 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
3366 | { |
3367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3368 | ||
3369 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 3370 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
d20d4f0c | 3371 | |
0961021a BW |
3372 | if (IS_BROADWELL(dev)) |
3373 | gen8_disable_rps_interrupts(dev); | |
3374 | else | |
3375 | gen6_disable_rps_interrupts(dev); | |
44fc7d5c DV |
3376 | } |
3377 | ||
38807746 D |
3378 | static void cherryview_disable_rps(struct drm_device *dev) |
3379 | { | |
3380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3381 | ||
3382 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3383 | } | |
3384 | ||
44fc7d5c DV |
3385 | static void valleyview_disable_rps(struct drm_device *dev) |
3386 | { | |
3387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3388 | ||
3389 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
d20d4f0c | 3390 | |
44fc7d5c | 3391 | gen6_disable_rps_interrupts(dev); |
d20d4f0c JB |
3392 | } |
3393 | ||
dc39fff7 BW |
3394 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
3395 | { | |
91ca689a ID |
3396 | if (IS_VALLEYVIEW(dev)) { |
3397 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
3398 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
3399 | else | |
3400 | mode = 0; | |
3401 | } | |
dc39fff7 | 3402 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
1c79b42f BW |
3403 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
3404 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
3405 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
3406 | } |
3407 | ||
e6069ca8 | 3408 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 3409 | { |
eb4926e4 DL |
3410 | /* No RC6 before Ironlake */ |
3411 | if (INTEL_INFO(dev)->gen < 5) | |
3412 | return 0; | |
3413 | ||
e6069ca8 ID |
3414 | /* RC6 is only on Ironlake mobile not on desktop */ |
3415 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) | |
3416 | return 0; | |
3417 | ||
456470eb | 3418 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
3419 | if (enable_rc6 >= 0) { |
3420 | int mask; | |
3421 | ||
3422 | if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
3423 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | | |
3424 | INTEL_RC6pp_ENABLE; | |
3425 | else | |
3426 | mask = INTEL_RC6_ENABLE; | |
3427 | ||
3428 | if ((enable_rc6 & mask) != enable_rc6) | |
3429 | DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n", | |
8fd9c1a9 | 3430 | enable_rc6 & mask, enable_rc6, mask); |
e6069ca8 ID |
3431 | |
3432 | return enable_rc6 & mask; | |
3433 | } | |
2b4e57bd | 3434 | |
6567d748 CW |
3435 | /* Disable RC6 on Ironlake */ |
3436 | if (INTEL_INFO(dev)->gen == 5) | |
3437 | return 0; | |
2b4e57bd | 3438 | |
8bade1ad | 3439 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 3440 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
3441 | |
3442 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
3443 | } |
3444 | ||
e6069ca8 ID |
3445 | int intel_enable_rc6(const struct drm_device *dev) |
3446 | { | |
3447 | return i915.enable_rc6; | |
3448 | } | |
3449 | ||
0961021a BW |
3450 | static void gen8_enable_rps_interrupts(struct drm_device *dev) |
3451 | { | |
3452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3453 | ||
3454 | spin_lock_irq(&dev_priv->irq_lock); | |
3455 | WARN_ON(dev_priv->rps.pm_iir); | |
3456 | bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
3457 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); | |
3458 | spin_unlock_irq(&dev_priv->irq_lock); | |
3459 | } | |
3460 | ||
44fc7d5c DV |
3461 | static void gen6_enable_rps_interrupts(struct drm_device *dev) |
3462 | { | |
3463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3464 | ||
3465 | spin_lock_irq(&dev_priv->irq_lock); | |
a0b3335a | 3466 | WARN_ON(dev_priv->rps.pm_iir); |
a6706b45 D |
3467 | snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
3468 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); | |
44fc7d5c | 3469 | spin_unlock_irq(&dev_priv->irq_lock); |
44fc7d5c DV |
3470 | } |
3471 | ||
3280e8b0 BW |
3472 | static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap) |
3473 | { | |
3474 | /* All of these values are in units of 50MHz */ | |
3475 | dev_priv->rps.cur_freq = 0; | |
3476 | /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */ | |
3477 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
3478 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
3479 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
3480 | /* XXX: only BYT has a special efficient freq */ | |
3481 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; | |
3482 | /* hw_max = RP0 until we check for overclocking */ | |
3483 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
3484 | ||
3485 | /* Preserve min/max settings in case of re-init */ | |
3486 | if (dev_priv->rps.max_freq_softlimit == 0) | |
3487 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
3488 | ||
3489 | if (dev_priv->rps.min_freq_softlimit == 0) | |
3490 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
3491 | } | |
3492 | ||
6edee7f3 BW |
3493 | static void gen8_enable_rps(struct drm_device *dev) |
3494 | { | |
3495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 3496 | struct intel_engine_cs *ring; |
6edee7f3 BW |
3497 | uint32_t rc6_mask = 0, rp_state_cap; |
3498 | int unused; | |
3499 | ||
3500 | /* 1a: Software RC state - RC0 */ | |
3501 | I915_WRITE(GEN6_RC_STATE, 0); | |
3502 | ||
3503 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
3504 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
c8d9a590 | 3505 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
3506 | |
3507 | /* 2a: Disable RC states. */ | |
3508 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3509 | ||
3510 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3280e8b0 | 3511 | parse_rp_state_cap(dev_priv, rp_state_cap); |
6edee7f3 BW |
3512 | |
3513 | /* 2b: Program RC6 thresholds.*/ | |
3514 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
3515 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
3516 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3517 | for_each_ring(ring, dev_priv, unused) | |
3518 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
3519 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
3520 | if (IS_BROADWELL(dev)) |
3521 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
3522 | else | |
3523 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
3524 | |
3525 | /* 3: Enable RC6 */ | |
3526 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
3527 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 3528 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
3529 | if (IS_BROADWELL(dev)) |
3530 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
3531 | GEN7_RC_CTL_TO_MODE | | |
3532 | rc6_mask); | |
3533 | else | |
3534 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
3535 | GEN6_RC_CTL_EI_MODE(1) | | |
3536 | rc6_mask); | |
6edee7f3 BW |
3537 | |
3538 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
3539 | I915_WRITE(GEN6_RPNSWREQ, |
3540 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
3541 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
3542 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
6edee7f3 BW |
3543 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
3544 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
3545 | ||
3546 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
3547 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
b39fb297 BW |
3548 | dev_priv->rps.max_freq_softlimit << 24 | |
3549 | dev_priv->rps.min_freq_softlimit << 16); | |
6edee7f3 BW |
3550 | |
3551 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
3552 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
3553 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
3554 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
3555 | ||
3556 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
3557 | ||
3558 | /* 5: Enable RPS */ | |
3559 | I915_WRITE(GEN6_RP_CONTROL, | |
3560 | GEN6_RP_MEDIA_TURBO | | |
3561 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
7405f42c | 3562 | GEN6_RP_MEDIA_IS_GFX | |
6edee7f3 BW |
3563 | GEN6_RP_ENABLE | |
3564 | GEN6_RP_UP_BUSY_AVG | | |
3565 | GEN6_RP_DOWN_IDLE_AVG); | |
3566 | ||
3567 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
3568 | ||
3569 | gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); | |
3570 | ||
0961021a | 3571 | gen8_enable_rps_interrupts(dev); |
6edee7f3 | 3572 | |
c8d9a590 | 3573 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
3574 | } |
3575 | ||
79f5b2c7 | 3576 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 3577 | { |
79f5b2c7 | 3578 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3579 | struct intel_engine_cs *ring; |
2a5913a8 | 3580 | u32 rp_state_cap; |
7b9e0ae6 | 3581 | u32 gt_perf_status; |
d060c169 | 3582 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 3583 | u32 gtfifodbg; |
2b4e57bd | 3584 | int rc6_mode; |
42c0526c | 3585 | int i, ret; |
2b4e57bd | 3586 | |
4fc688ce | 3587 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 3588 | |
2b4e57bd ED |
3589 | /* Here begins a magic sequence of register writes to enable |
3590 | * auto-downclocking. | |
3591 | * | |
3592 | * Perhaps there might be some value in exposing these to | |
3593 | * userspace... | |
3594 | */ | |
3595 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
3596 | |
3597 | /* Clear the DBG now so we don't confuse earlier errors */ | |
3598 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
3599 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
3600 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
3601 | } | |
3602 | ||
c8d9a590 | 3603 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 3604 | |
7b9e0ae6 CW |
3605 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
3606 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
3607 | ||
3280e8b0 | 3608 | parse_rp_state_cap(dev_priv, rp_state_cap); |
dd0a1aa1 | 3609 | |
2b4e57bd ED |
3610 | /* disable the counters and set deterministic thresholds */ |
3611 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3612 | ||
3613 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
3614 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
3615 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
3616 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
3617 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
3618 | ||
b4519513 CW |
3619 | for_each_ring(ring, dev_priv, i) |
3620 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
3621 | |
3622 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
3623 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 3624 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
3625 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
3626 | else | |
3627 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 3628 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
3629 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
3630 | ||
5a7dc92a | 3631 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
3632 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
3633 | if (rc6_mode & INTEL_RC6_ENABLE) | |
3634 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
3635 | ||
5a7dc92a ED |
3636 | /* We don't use those on Haswell */ |
3637 | if (!IS_HASWELL(dev)) { | |
3638 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
3639 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 3640 | |
5a7dc92a ED |
3641 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
3642 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
3643 | } | |
2b4e57bd | 3644 | |
dc39fff7 | 3645 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
3646 | |
3647 | I915_WRITE(GEN6_RC_CONTROL, | |
3648 | rc6_mask | | |
3649 | GEN6_RC_CTL_EI_MODE(1) | | |
3650 | GEN6_RC_CTL_HW_ENABLE); | |
3651 | ||
dd75fdc8 CW |
3652 | /* Power down if completely idle for over 50ms */ |
3653 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 3654 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 3655 | |
42c0526c | 3656 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 3657 | if (ret) |
42c0526c | 3658 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
3659 | |
3660 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
3661 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
3662 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 3663 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 3664 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 3665 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
3666 | } |
3667 | ||
dd75fdc8 | 3668 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
b39fb297 | 3669 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
2b4e57bd | 3670 | |
44fc7d5c | 3671 | gen6_enable_rps_interrupts(dev); |
2b4e57bd | 3672 | |
31643d54 BW |
3673 | rc6vids = 0; |
3674 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
3675 | if (IS_GEN6(dev) && ret) { | |
3676 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
3677 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
3678 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
3679 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
3680 | rc6vids &= 0xffff00; | |
3681 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
3682 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
3683 | if (ret) | |
3684 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
3685 | } | |
3686 | ||
c8d9a590 | 3687 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
3688 | } |
3689 | ||
c2bc2fc5 | 3690 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 3691 | { |
79f5b2c7 | 3692 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 3693 | int min_freq = 15; |
3ebecd07 CW |
3694 | unsigned int gpu_freq; |
3695 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd | 3696 | int scaling_factor = 180; |
eda79642 | 3697 | struct cpufreq_policy *policy; |
2b4e57bd | 3698 | |
4fc688ce | 3699 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 3700 | |
eda79642 BW |
3701 | policy = cpufreq_cpu_get(0); |
3702 | if (policy) { | |
3703 | max_ia_freq = policy->cpuinfo.max_freq; | |
3704 | cpufreq_cpu_put(policy); | |
3705 | } else { | |
3706 | /* | |
3707 | * Default to measured freq if none found, PCU will ensure we | |
3708 | * don't go over | |
3709 | */ | |
2b4e57bd | 3710 | max_ia_freq = tsc_khz; |
eda79642 | 3711 | } |
2b4e57bd ED |
3712 | |
3713 | /* Convert from kHz to MHz */ | |
3714 | max_ia_freq /= 1000; | |
3715 | ||
153b4b95 | 3716 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
3717 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
3718 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 3719 | |
2b4e57bd ED |
3720 | /* |
3721 | * For each potential GPU frequency, load a ring frequency we'd like | |
3722 | * to use for memory access. We do this by specifying the IA frequency | |
3723 | * the PCU should use as a reference to determine the ring frequency. | |
3724 | */ | |
b39fb297 | 3725 | for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; |
2b4e57bd | 3726 | gpu_freq--) { |
b39fb297 | 3727 | int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; |
3ebecd07 CW |
3728 | unsigned int ia_freq = 0, ring_freq = 0; |
3729 | ||
46c764d4 BW |
3730 | if (INTEL_INFO(dev)->gen >= 8) { |
3731 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
3732 | ring_freq = max(min_ring_freq, gpu_freq); | |
3733 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 3734 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
3735 | ring_freq = max(min_ring_freq, ring_freq); |
3736 | /* leave ia_freq as the default, chosen by cpufreq */ | |
3737 | } else { | |
3738 | /* On older processors, there is no separate ring | |
3739 | * clock domain, so in order to boost the bandwidth | |
3740 | * of the ring, we need to upclock the CPU (ia_freq). | |
3741 | * | |
3742 | * For GPU frequencies less than 750MHz, | |
3743 | * just use the lowest ring freq. | |
3744 | */ | |
3745 | if (gpu_freq < min_freq) | |
3746 | ia_freq = 800; | |
3747 | else | |
3748 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
3749 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
3750 | } | |
2b4e57bd | 3751 | |
42c0526c BW |
3752 | sandybridge_pcode_write(dev_priv, |
3753 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
3754 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
3755 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
3756 | gpu_freq); | |
2b4e57bd | 3757 | } |
2b4e57bd ED |
3758 | } |
3759 | ||
c2bc2fc5 ID |
3760 | void gen6_update_ring_freq(struct drm_device *dev) |
3761 | { | |
3762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3763 | ||
3764 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) | |
3765 | return; | |
3766 | ||
3767 | mutex_lock(&dev_priv->rps.hw_lock); | |
3768 | __gen6_update_ring_freq(dev); | |
3769 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3770 | } | |
3771 | ||
2b6b3a09 D |
3772 | int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
3773 | { | |
3774 | u32 val, rp0; | |
3775 | ||
3776 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
3777 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
3778 | ||
3779 | return rp0; | |
3780 | } | |
3781 | ||
3782 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
3783 | { | |
3784 | u32 val, rpe; | |
3785 | ||
3786 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
3787 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
3788 | ||
3789 | return rpe; | |
3790 | } | |
3791 | ||
3792 | int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) | |
3793 | { | |
3794 | u32 val, rpn; | |
3795 | ||
3796 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
3797 | rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK; | |
3798 | return rpn; | |
3799 | } | |
3800 | ||
0a073b84 JB |
3801 | int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
3802 | { | |
3803 | u32 val, rp0; | |
3804 | ||
64936258 | 3805 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
3806 | |
3807 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
3808 | /* Clamp to max */ | |
3809 | rp0 = min_t(u32, rp0, 0xea); | |
3810 | ||
3811 | return rp0; | |
3812 | } | |
3813 | ||
3814 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
3815 | { | |
3816 | u32 val, rpe; | |
3817 | ||
64936258 | 3818 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 3819 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 3820 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
3821 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
3822 | ||
3823 | return rpe; | |
3824 | } | |
3825 | ||
3826 | int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) | |
3827 | { | |
64936258 | 3828 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
3829 | } |
3830 | ||
ae48434c ID |
3831 | /* Check that the pctx buffer wasn't move under us. */ |
3832 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
3833 | { | |
3834 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
3835 | ||
3836 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
3837 | dev_priv->vlv_pctx->stolen->start); | |
3838 | } | |
3839 | ||
38807746 D |
3840 | |
3841 | /* Check that the pcbr address is not empty. */ | |
3842 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
3843 | { | |
3844 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
3845 | ||
3846 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
3847 | } | |
3848 | ||
3849 | static void cherryview_setup_pctx(struct drm_device *dev) | |
3850 | { | |
3851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3852 | unsigned long pctx_paddr, paddr; | |
3853 | struct i915_gtt *gtt = &dev_priv->gtt; | |
3854 | u32 pcbr; | |
3855 | int pctx_size = 32*1024; | |
3856 | ||
3857 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
3858 | ||
3859 | pcbr = I915_READ(VLV_PCBR); | |
3860 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
3861 | paddr = (dev_priv->mm.stolen_base + | |
3862 | (gtt->stolen_size - pctx_size)); | |
3863 | ||
3864 | pctx_paddr = (paddr & (~4095)); | |
3865 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
3866 | } | |
3867 | } | |
3868 | ||
c9cddffc JB |
3869 | static void valleyview_setup_pctx(struct drm_device *dev) |
3870 | { | |
3871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3872 | struct drm_i915_gem_object *pctx; | |
3873 | unsigned long pctx_paddr; | |
3874 | u32 pcbr; | |
3875 | int pctx_size = 24*1024; | |
3876 | ||
17b0c1f7 ID |
3877 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
3878 | ||
c9cddffc JB |
3879 | pcbr = I915_READ(VLV_PCBR); |
3880 | if (pcbr) { | |
3881 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
3882 | int pcbr_offset; | |
3883 | ||
3884 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
3885 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
3886 | pcbr_offset, | |
190d6cd5 | 3887 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
3888 | pctx_size); |
3889 | goto out; | |
3890 | } | |
3891 | ||
3892 | /* | |
3893 | * From the Gunit register HAS: | |
3894 | * The Gfx driver is expected to program this register and ensure | |
3895 | * proper allocation within Gfx stolen memory. For example, this | |
3896 | * register should be programmed such than the PCBR range does not | |
3897 | * overlap with other ranges, such as the frame buffer, protected | |
3898 | * memory, or any other relevant ranges. | |
3899 | */ | |
3900 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
3901 | if (!pctx) { | |
3902 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
3903 | return; | |
3904 | } | |
3905 | ||
3906 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
3907 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
3908 | ||
3909 | out: | |
3910 | dev_priv->vlv_pctx = pctx; | |
3911 | } | |
3912 | ||
ae48434c ID |
3913 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
3914 | { | |
3915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3916 | ||
3917 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
3918 | return; | |
3919 | ||
3920 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
3921 | dev_priv->vlv_pctx = NULL; | |
3922 | } | |
3923 | ||
4e80519e ID |
3924 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
3925 | { | |
3926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3927 | ||
3928 | valleyview_setup_pctx(dev); | |
3929 | ||
3930 | mutex_lock(&dev_priv->rps.hw_lock); | |
3931 | ||
3932 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); | |
3933 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
3934 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
3935 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
3936 | dev_priv->rps.max_freq); | |
3937 | ||
3938 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
3939 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
3940 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
3941 | dev_priv->rps.efficient_freq); | |
3942 | ||
3943 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); | |
3944 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
3945 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
3946 | dev_priv->rps.min_freq); | |
3947 | ||
3948 | /* Preserve min/max settings in case of re-init */ | |
3949 | if (dev_priv->rps.max_freq_softlimit == 0) | |
3950 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
3951 | ||
3952 | if (dev_priv->rps.min_freq_softlimit == 0) | |
3953 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
3954 | ||
3955 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3956 | } | |
3957 | ||
38807746 D |
3958 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
3959 | { | |
2b6b3a09 D |
3960 | struct drm_i915_private *dev_priv = dev->dev_private; |
3961 | ||
38807746 | 3962 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
3963 | |
3964 | mutex_lock(&dev_priv->rps.hw_lock); | |
3965 | ||
3966 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); | |
3967 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
3968 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
3969 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
3970 | dev_priv->rps.max_freq); | |
3971 | ||
3972 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
3973 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
3974 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
3975 | dev_priv->rps.efficient_freq); | |
3976 | ||
3977 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); | |
3978 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
3979 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
3980 | dev_priv->rps.min_freq); | |
3981 | ||
3982 | /* Preserve min/max settings in case of re-init */ | |
3983 | if (dev_priv->rps.max_freq_softlimit == 0) | |
3984 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
3985 | ||
3986 | if (dev_priv->rps.min_freq_softlimit == 0) | |
3987 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
3988 | ||
3989 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
3990 | } |
3991 | ||
4e80519e ID |
3992 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
3993 | { | |
3994 | valleyview_cleanup_pctx(dev); | |
3995 | } | |
3996 | ||
38807746 D |
3997 | static void cherryview_enable_rps(struct drm_device *dev) |
3998 | { | |
3999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4000 | struct intel_engine_cs *ring; | |
2b6b3a09 | 4001 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
4002 | int i; |
4003 | ||
4004 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4005 | ||
4006 | gtfifodbg = I915_READ(GTFIFODBG); | |
4007 | if (gtfifodbg) { | |
4008 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
4009 | gtfifodbg); | |
4010 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4011 | } | |
4012 | ||
4013 | cherryview_check_pctx(dev_priv); | |
4014 | ||
4015 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
4016 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
4017 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
4018 | ||
4019 | /* 2a: Program RC6 thresholds.*/ | |
4020 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4021 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4022 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4023 | ||
4024 | for_each_ring(ring, dev_priv, i) | |
4025 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4026 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4027 | ||
4028 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
4029 | ||
4030 | /* allows RC6 residency counter to work */ | |
4031 | I915_WRITE(VLV_COUNTER_CONTROL, | |
4032 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
4033 | VLV_MEDIA_RC6_COUNT_EN | | |
4034 | VLV_RENDER_RC6_COUNT_EN)); | |
4035 | ||
4036 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
4037 | pcbr = I915_READ(VLV_PCBR); | |
4038 | ||
4039 | DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr); | |
4040 | ||
4041 | /* 3: Enable RC6 */ | |
4042 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
4043 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
4044 | rc6_mode = GEN6_RC_CTL_EI_MODE(1); | |
4045 | ||
4046 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
4047 | ||
2b6b3a09 D |
4048 | /* 4 Program defaults and thresholds for RPS*/ |
4049 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
4050 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4051 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4052 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4053 | ||
4054 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4055 | ||
7405f42c TR |
4056 | /* WaDisablePwrmtrEvent:chv (pre-production hw) */ |
4057 | I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); | |
4058 | I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); | |
4059 | ||
2b6b3a09 D |
4060 | /* 5: Enable RPS */ |
4061 | I915_WRITE(GEN6_RP_CONTROL, | |
4062 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
7405f42c | 4063 | GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ |
2b6b3a09 D |
4064 | GEN6_RP_ENABLE | |
4065 | GEN6_RP_UP_BUSY_AVG | | |
4066 | GEN6_RP_DOWN_IDLE_AVG); | |
4067 | ||
4068 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4069 | ||
4070 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
4071 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
4072 | ||
4073 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
4074 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
4075 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
4076 | dev_priv->rps.cur_freq); | |
4077 | ||
4078 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
4079 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4080 | dev_priv->rps.efficient_freq); | |
4081 | ||
4082 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
4083 | ||
38807746 D |
4084 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
4085 | } | |
4086 | ||
0a073b84 JB |
4087 | static void valleyview_enable_rps(struct drm_device *dev) |
4088 | { | |
4089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4090 | struct intel_engine_cs *ring; |
2a5913a8 | 4091 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
4092 | int i; |
4093 | ||
4094 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4095 | ||
ae48434c ID |
4096 | valleyview_check_pctx(dev_priv); |
4097 | ||
0a073b84 | 4098 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
4099 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
4100 | gtfifodbg); | |
0a073b84 JB |
4101 | I915_WRITE(GTFIFODBG, gtfifodbg); |
4102 | } | |
4103 | ||
c8d9a590 D |
4104 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
4105 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
0a073b84 JB |
4106 | |
4107 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
4108 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4109 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4110 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4111 | ||
4112 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4113 | ||
4114 | I915_WRITE(GEN6_RP_CONTROL, | |
4115 | GEN6_RP_MEDIA_TURBO | | |
4116 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4117 | GEN6_RP_MEDIA_IS_GFX | | |
4118 | GEN6_RP_ENABLE | | |
4119 | GEN6_RP_UP_BUSY_AVG | | |
4120 | GEN6_RP_DOWN_IDLE_CONT); | |
4121 | ||
4122 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
4123 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4124 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4125 | ||
4126 | for_each_ring(ring, dev_priv, i) | |
4127 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4128 | ||
2f0aa304 | 4129 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
4130 | |
4131 | /* allows RC6 residency counter to work */ | |
49798eb2 JB |
4132 | I915_WRITE(VLV_COUNTER_CONTROL, |
4133 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
4134 | VLV_MEDIA_RC6_COUNT_EN | | |
4135 | VLV_RENDER_RC6_COUNT_EN)); | |
a2b23fe0 | 4136 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 4137 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
4138 | |
4139 | intel_print_rc6_info(dev, rc6_mode); | |
4140 | ||
a2b23fe0 | 4141 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 4142 | |
64936258 | 4143 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
4144 | |
4145 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
4146 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
4147 | ||
b39fb297 | 4148 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 4149 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
b39fb297 BW |
4150 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
4151 | dev_priv->rps.cur_freq); | |
0a073b84 | 4152 | |
73008b98 | 4153 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
b39fb297 BW |
4154 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4155 | dev_priv->rps.efficient_freq); | |
0a073b84 | 4156 | |
b39fb297 | 4157 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 4158 | |
44fc7d5c | 4159 | gen6_enable_rps_interrupts(dev); |
0a073b84 | 4160 | |
c8d9a590 | 4161 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
4162 | } |
4163 | ||
930ebb46 | 4164 | void ironlake_teardown_rc6(struct drm_device *dev) |
2b4e57bd ED |
4165 | { |
4166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4167 | ||
3e373948 | 4168 | if (dev_priv->ips.renderctx) { |
d7f46fc4 | 4169 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
3e373948 DV |
4170 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
4171 | dev_priv->ips.renderctx = NULL; | |
2b4e57bd ED |
4172 | } |
4173 | ||
3e373948 | 4174 | if (dev_priv->ips.pwrctx) { |
d7f46fc4 | 4175 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
3e373948 DV |
4176 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
4177 | dev_priv->ips.pwrctx = NULL; | |
2b4e57bd ED |
4178 | } |
4179 | } | |
4180 | ||
930ebb46 | 4181 | static void ironlake_disable_rc6(struct drm_device *dev) |
2b4e57bd ED |
4182 | { |
4183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4184 | ||
4185 | if (I915_READ(PWRCTXA)) { | |
4186 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
4187 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
4188 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
4189 | 50); | |
4190 | ||
4191 | I915_WRITE(PWRCTXA, 0); | |
4192 | POSTING_READ(PWRCTXA); | |
4193 | ||
4194 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
4195 | POSTING_READ(RSTDBYCTL); | |
4196 | } | |
2b4e57bd ED |
4197 | } |
4198 | ||
4199 | static int ironlake_setup_rc6(struct drm_device *dev) | |
4200 | { | |
4201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4202 | ||
3e373948 DV |
4203 | if (dev_priv->ips.renderctx == NULL) |
4204 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); | |
4205 | if (!dev_priv->ips.renderctx) | |
2b4e57bd ED |
4206 | return -ENOMEM; |
4207 | ||
3e373948 DV |
4208 | if (dev_priv->ips.pwrctx == NULL) |
4209 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); | |
4210 | if (!dev_priv->ips.pwrctx) { | |
2b4e57bd ED |
4211 | ironlake_teardown_rc6(dev); |
4212 | return -ENOMEM; | |
4213 | } | |
4214 | ||
4215 | return 0; | |
4216 | } | |
4217 | ||
930ebb46 | 4218 | static void ironlake_enable_rc6(struct drm_device *dev) |
2b4e57bd ED |
4219 | { |
4220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4221 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e960501 | 4222 | bool was_interruptible; |
2b4e57bd ED |
4223 | int ret; |
4224 | ||
4225 | /* rc6 disabled by default due to repeated reports of hanging during | |
4226 | * boot and resume. | |
4227 | */ | |
4228 | if (!intel_enable_rc6(dev)) | |
4229 | return; | |
4230 | ||
79f5b2c7 DV |
4231 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
4232 | ||
2b4e57bd | 4233 | ret = ironlake_setup_rc6(dev); |
79f5b2c7 | 4234 | if (ret) |
2b4e57bd | 4235 | return; |
2b4e57bd | 4236 | |
3e960501 CW |
4237 | was_interruptible = dev_priv->mm.interruptible; |
4238 | dev_priv->mm.interruptible = false; | |
4239 | ||
2b4e57bd ED |
4240 | /* |
4241 | * GPU can automatically power down the render unit if given a page | |
4242 | * to save state. | |
4243 | */ | |
6d90c952 | 4244 | ret = intel_ring_begin(ring, 6); |
2b4e57bd ED |
4245 | if (ret) { |
4246 | ironlake_teardown_rc6(dev); | |
3e960501 | 4247 | dev_priv->mm.interruptible = was_interruptible; |
2b4e57bd ED |
4248 | return; |
4249 | } | |
4250 | ||
6d90c952 DV |
4251 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
4252 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 4253 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
6d90c952 DV |
4254 | MI_MM_SPACE_GTT | |
4255 | MI_SAVE_EXT_STATE_EN | | |
4256 | MI_RESTORE_EXT_STATE_EN | | |
4257 | MI_RESTORE_INHIBIT); | |
4258 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); | |
4259 | intel_ring_emit(ring, MI_NOOP); | |
4260 | intel_ring_emit(ring, MI_FLUSH); | |
4261 | intel_ring_advance(ring); | |
2b4e57bd ED |
4262 | |
4263 | /* | |
4264 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
4265 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
4266 | * safe to assume that renderctx is valid | |
4267 | */ | |
3e960501 CW |
4268 | ret = intel_ring_idle(ring); |
4269 | dev_priv->mm.interruptible = was_interruptible; | |
2b4e57bd | 4270 | if (ret) { |
def27a58 | 4271 | DRM_ERROR("failed to enable ironlake power savings\n"); |
2b4e57bd | 4272 | ironlake_teardown_rc6(dev); |
2b4e57bd ED |
4273 | return; |
4274 | } | |
4275 | ||
f343c5f6 | 4276 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
2b4e57bd | 4277 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
dc39fff7 | 4278 | |
91ca689a | 4279 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); |
2b4e57bd ED |
4280 | } |
4281 | ||
dde18883 ED |
4282 | static unsigned long intel_pxfreq(u32 vidfreq) |
4283 | { | |
4284 | unsigned long freq; | |
4285 | int div = (vidfreq & 0x3f0000) >> 16; | |
4286 | int post = (vidfreq & 0x3000) >> 12; | |
4287 | int pre = (vidfreq & 0x7); | |
4288 | ||
4289 | if (!pre) | |
4290 | return 0; | |
4291 | ||
4292 | freq = ((div * 133333) / ((1<<post) * pre)); | |
4293 | ||
4294 | return freq; | |
4295 | } | |
4296 | ||
eb48eb00 DV |
4297 | static const struct cparams { |
4298 | u16 i; | |
4299 | u16 t; | |
4300 | u16 m; | |
4301 | u16 c; | |
4302 | } cparams[] = { | |
4303 | { 1, 1333, 301, 28664 }, | |
4304 | { 1, 1066, 294, 24460 }, | |
4305 | { 1, 800, 294, 25192 }, | |
4306 | { 0, 1333, 276, 27605 }, | |
4307 | { 0, 1066, 276, 27605 }, | |
4308 | { 0, 800, 231, 23784 }, | |
4309 | }; | |
4310 | ||
f531dcb2 | 4311 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
4312 | { |
4313 | u64 total_count, diff, ret; | |
4314 | u32 count1, count2, count3, m = 0, c = 0; | |
4315 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
4316 | int i; | |
4317 | ||
02d71956 DV |
4318 | assert_spin_locked(&mchdev_lock); |
4319 | ||
20e4d407 | 4320 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
4321 | |
4322 | /* Prevent division-by-zero if we are asking too fast. | |
4323 | * Also, we don't get interesting results if we are polling | |
4324 | * faster than once in 10ms, so just return the saved value | |
4325 | * in such cases. | |
4326 | */ | |
4327 | if (diff1 <= 10) | |
20e4d407 | 4328 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
4329 | |
4330 | count1 = I915_READ(DMIEC); | |
4331 | count2 = I915_READ(DDREC); | |
4332 | count3 = I915_READ(CSIEC); | |
4333 | ||
4334 | total_count = count1 + count2 + count3; | |
4335 | ||
4336 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
4337 | if (total_count < dev_priv->ips.last_count1) { |
4338 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
4339 | diff += total_count; |
4340 | } else { | |
20e4d407 | 4341 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
4342 | } |
4343 | ||
4344 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
4345 | if (cparams[i].i == dev_priv->ips.c_m && |
4346 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
4347 | m = cparams[i].m; |
4348 | c = cparams[i].c; | |
4349 | break; | |
4350 | } | |
4351 | } | |
4352 | ||
4353 | diff = div_u64(diff, diff1); | |
4354 | ret = ((m * diff) + c); | |
4355 | ret = div_u64(ret, 10); | |
4356 | ||
20e4d407 DV |
4357 | dev_priv->ips.last_count1 = total_count; |
4358 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 4359 | |
20e4d407 | 4360 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
4361 | |
4362 | return ret; | |
4363 | } | |
4364 | ||
f531dcb2 CW |
4365 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
4366 | { | |
3d13ef2e | 4367 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
4368 | unsigned long val; |
4369 | ||
3d13ef2e | 4370 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
4371 | return 0; |
4372 | ||
4373 | spin_lock_irq(&mchdev_lock); | |
4374 | ||
4375 | val = __i915_chipset_val(dev_priv); | |
4376 | ||
4377 | spin_unlock_irq(&mchdev_lock); | |
4378 | ||
4379 | return val; | |
4380 | } | |
4381 | ||
eb48eb00 DV |
4382 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
4383 | { | |
4384 | unsigned long m, x, b; | |
4385 | u32 tsfs; | |
4386 | ||
4387 | tsfs = I915_READ(TSFS); | |
4388 | ||
4389 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
4390 | x = I915_READ8(TR1); | |
4391 | ||
4392 | b = tsfs & TSFS_INTR_MASK; | |
4393 | ||
4394 | return ((m * x) / 127) - b; | |
4395 | } | |
4396 | ||
4397 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
4398 | { | |
3d13ef2e | 4399 | struct drm_device *dev = dev_priv->dev; |
eb48eb00 DV |
4400 | static const struct v_table { |
4401 | u16 vd; /* in .1 mil */ | |
4402 | u16 vm; /* in .1 mil */ | |
4403 | } v_table[] = { | |
4404 | { 0, 0, }, | |
4405 | { 375, 0, }, | |
4406 | { 500, 0, }, | |
4407 | { 625, 0, }, | |
4408 | { 750, 0, }, | |
4409 | { 875, 0, }, | |
4410 | { 1000, 0, }, | |
4411 | { 1125, 0, }, | |
4412 | { 4125, 3000, }, | |
4413 | { 4125, 3000, }, | |
4414 | { 4125, 3000, }, | |
4415 | { 4125, 3000, }, | |
4416 | { 4125, 3000, }, | |
4417 | { 4125, 3000, }, | |
4418 | { 4125, 3000, }, | |
4419 | { 4125, 3000, }, | |
4420 | { 4125, 3000, }, | |
4421 | { 4125, 3000, }, | |
4422 | { 4125, 3000, }, | |
4423 | { 4125, 3000, }, | |
4424 | { 4125, 3000, }, | |
4425 | { 4125, 3000, }, | |
4426 | { 4125, 3000, }, | |
4427 | { 4125, 3000, }, | |
4428 | { 4125, 3000, }, | |
4429 | { 4125, 3000, }, | |
4430 | { 4125, 3000, }, | |
4431 | { 4125, 3000, }, | |
4432 | { 4125, 3000, }, | |
4433 | { 4125, 3000, }, | |
4434 | { 4125, 3000, }, | |
4435 | { 4125, 3000, }, | |
4436 | { 4250, 3125, }, | |
4437 | { 4375, 3250, }, | |
4438 | { 4500, 3375, }, | |
4439 | { 4625, 3500, }, | |
4440 | { 4750, 3625, }, | |
4441 | { 4875, 3750, }, | |
4442 | { 5000, 3875, }, | |
4443 | { 5125, 4000, }, | |
4444 | { 5250, 4125, }, | |
4445 | { 5375, 4250, }, | |
4446 | { 5500, 4375, }, | |
4447 | { 5625, 4500, }, | |
4448 | { 5750, 4625, }, | |
4449 | { 5875, 4750, }, | |
4450 | { 6000, 4875, }, | |
4451 | { 6125, 5000, }, | |
4452 | { 6250, 5125, }, | |
4453 | { 6375, 5250, }, | |
4454 | { 6500, 5375, }, | |
4455 | { 6625, 5500, }, | |
4456 | { 6750, 5625, }, | |
4457 | { 6875, 5750, }, | |
4458 | { 7000, 5875, }, | |
4459 | { 7125, 6000, }, | |
4460 | { 7250, 6125, }, | |
4461 | { 7375, 6250, }, | |
4462 | { 7500, 6375, }, | |
4463 | { 7625, 6500, }, | |
4464 | { 7750, 6625, }, | |
4465 | { 7875, 6750, }, | |
4466 | { 8000, 6875, }, | |
4467 | { 8125, 7000, }, | |
4468 | { 8250, 7125, }, | |
4469 | { 8375, 7250, }, | |
4470 | { 8500, 7375, }, | |
4471 | { 8625, 7500, }, | |
4472 | { 8750, 7625, }, | |
4473 | { 8875, 7750, }, | |
4474 | { 9000, 7875, }, | |
4475 | { 9125, 8000, }, | |
4476 | { 9250, 8125, }, | |
4477 | { 9375, 8250, }, | |
4478 | { 9500, 8375, }, | |
4479 | { 9625, 8500, }, | |
4480 | { 9750, 8625, }, | |
4481 | { 9875, 8750, }, | |
4482 | { 10000, 8875, }, | |
4483 | { 10125, 9000, }, | |
4484 | { 10250, 9125, }, | |
4485 | { 10375, 9250, }, | |
4486 | { 10500, 9375, }, | |
4487 | { 10625, 9500, }, | |
4488 | { 10750, 9625, }, | |
4489 | { 10875, 9750, }, | |
4490 | { 11000, 9875, }, | |
4491 | { 11125, 10000, }, | |
4492 | { 11250, 10125, }, | |
4493 | { 11375, 10250, }, | |
4494 | { 11500, 10375, }, | |
4495 | { 11625, 10500, }, | |
4496 | { 11750, 10625, }, | |
4497 | { 11875, 10750, }, | |
4498 | { 12000, 10875, }, | |
4499 | { 12125, 11000, }, | |
4500 | { 12250, 11125, }, | |
4501 | { 12375, 11250, }, | |
4502 | { 12500, 11375, }, | |
4503 | { 12625, 11500, }, | |
4504 | { 12750, 11625, }, | |
4505 | { 12875, 11750, }, | |
4506 | { 13000, 11875, }, | |
4507 | { 13125, 12000, }, | |
4508 | { 13250, 12125, }, | |
4509 | { 13375, 12250, }, | |
4510 | { 13500, 12375, }, | |
4511 | { 13625, 12500, }, | |
4512 | { 13750, 12625, }, | |
4513 | { 13875, 12750, }, | |
4514 | { 14000, 12875, }, | |
4515 | { 14125, 13000, }, | |
4516 | { 14250, 13125, }, | |
4517 | { 14375, 13250, }, | |
4518 | { 14500, 13375, }, | |
4519 | { 14625, 13500, }, | |
4520 | { 14750, 13625, }, | |
4521 | { 14875, 13750, }, | |
4522 | { 15000, 13875, }, | |
4523 | { 15125, 14000, }, | |
4524 | { 15250, 14125, }, | |
4525 | { 15375, 14250, }, | |
4526 | { 15500, 14375, }, | |
4527 | { 15625, 14500, }, | |
4528 | { 15750, 14625, }, | |
4529 | { 15875, 14750, }, | |
4530 | { 16000, 14875, }, | |
4531 | { 16125, 15000, }, | |
4532 | }; | |
3d13ef2e | 4533 | if (INTEL_INFO(dev)->is_mobile) |
eb48eb00 DV |
4534 | return v_table[pxvid].vm; |
4535 | else | |
4536 | return v_table[pxvid].vd; | |
4537 | } | |
4538 | ||
02d71956 | 4539 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
4540 | { |
4541 | struct timespec now, diff1; | |
4542 | u64 diff; | |
4543 | unsigned long diffms; | |
4544 | u32 count; | |
4545 | ||
02d71956 | 4546 | assert_spin_locked(&mchdev_lock); |
eb48eb00 DV |
4547 | |
4548 | getrawmonotonic(&now); | |
20e4d407 | 4549 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
eb48eb00 DV |
4550 | |
4551 | /* Don't divide by 0 */ | |
4552 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; | |
4553 | if (!diffms) | |
4554 | return; | |
4555 | ||
4556 | count = I915_READ(GFXEC); | |
4557 | ||
20e4d407 DV |
4558 | if (count < dev_priv->ips.last_count2) { |
4559 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
4560 | diff += count; |
4561 | } else { | |
20e4d407 | 4562 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
4563 | } |
4564 | ||
20e4d407 DV |
4565 | dev_priv->ips.last_count2 = count; |
4566 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
4567 | |
4568 | /* More magic constants... */ | |
4569 | diff = diff * 1181; | |
4570 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 4571 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
4572 | } |
4573 | ||
02d71956 DV |
4574 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
4575 | { | |
3d13ef2e DL |
4576 | struct drm_device *dev = dev_priv->dev; |
4577 | ||
4578 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
4579 | return; |
4580 | ||
9270388e | 4581 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
4582 | |
4583 | __i915_update_gfx_val(dev_priv); | |
4584 | ||
9270388e | 4585 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
4586 | } |
4587 | ||
f531dcb2 | 4588 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
4589 | { |
4590 | unsigned long t, corr, state1, corr2, state2; | |
4591 | u32 pxvid, ext_v; | |
4592 | ||
02d71956 DV |
4593 | assert_spin_locked(&mchdev_lock); |
4594 | ||
b39fb297 | 4595 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
eb48eb00 DV |
4596 | pxvid = (pxvid >> 24) & 0x7f; |
4597 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
4598 | ||
4599 | state1 = ext_v; | |
4600 | ||
4601 | t = i915_mch_val(dev_priv); | |
4602 | ||
4603 | /* Revel in the empirically derived constants */ | |
4604 | ||
4605 | /* Correction factor in 1/100000 units */ | |
4606 | if (t > 80) | |
4607 | corr = ((t * 2349) + 135940); | |
4608 | else if (t >= 50) | |
4609 | corr = ((t * 964) + 29317); | |
4610 | else /* < 50 */ | |
4611 | corr = ((t * 301) + 1004); | |
4612 | ||
4613 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
4614 | corr /= 100000; | |
20e4d407 | 4615 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
4616 | |
4617 | state2 = (corr2 * state1) / 10000; | |
4618 | state2 /= 100; /* convert to mW */ | |
4619 | ||
02d71956 | 4620 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 4621 | |
20e4d407 | 4622 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
4623 | } |
4624 | ||
f531dcb2 CW |
4625 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
4626 | { | |
3d13ef2e | 4627 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
4628 | unsigned long val; |
4629 | ||
3d13ef2e | 4630 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
4631 | return 0; |
4632 | ||
4633 | spin_lock_irq(&mchdev_lock); | |
4634 | ||
4635 | val = __i915_gfx_val(dev_priv); | |
4636 | ||
4637 | spin_unlock_irq(&mchdev_lock); | |
4638 | ||
4639 | return val; | |
4640 | } | |
4641 | ||
eb48eb00 DV |
4642 | /** |
4643 | * i915_read_mch_val - return value for IPS use | |
4644 | * | |
4645 | * Calculate and return a value for the IPS driver to use when deciding whether | |
4646 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
4647 | */ | |
4648 | unsigned long i915_read_mch_val(void) | |
4649 | { | |
4650 | struct drm_i915_private *dev_priv; | |
4651 | unsigned long chipset_val, graphics_val, ret = 0; | |
4652 | ||
9270388e | 4653 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4654 | if (!i915_mch_dev) |
4655 | goto out_unlock; | |
4656 | dev_priv = i915_mch_dev; | |
4657 | ||
f531dcb2 CW |
4658 | chipset_val = __i915_chipset_val(dev_priv); |
4659 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
4660 | |
4661 | ret = chipset_val + graphics_val; | |
4662 | ||
4663 | out_unlock: | |
9270388e | 4664 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4665 | |
4666 | return ret; | |
4667 | } | |
4668 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
4669 | ||
4670 | /** | |
4671 | * i915_gpu_raise - raise GPU frequency limit | |
4672 | * | |
4673 | * Raise the limit; IPS indicates we have thermal headroom. | |
4674 | */ | |
4675 | bool i915_gpu_raise(void) | |
4676 | { | |
4677 | struct drm_i915_private *dev_priv; | |
4678 | bool ret = true; | |
4679 | ||
9270388e | 4680 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4681 | if (!i915_mch_dev) { |
4682 | ret = false; | |
4683 | goto out_unlock; | |
4684 | } | |
4685 | dev_priv = i915_mch_dev; | |
4686 | ||
20e4d407 DV |
4687 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
4688 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
4689 | |
4690 | out_unlock: | |
9270388e | 4691 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4692 | |
4693 | return ret; | |
4694 | } | |
4695 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
4696 | ||
4697 | /** | |
4698 | * i915_gpu_lower - lower GPU frequency limit | |
4699 | * | |
4700 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
4701 | * frequency maximum. | |
4702 | */ | |
4703 | bool i915_gpu_lower(void) | |
4704 | { | |
4705 | struct drm_i915_private *dev_priv; | |
4706 | bool ret = true; | |
4707 | ||
9270388e | 4708 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4709 | if (!i915_mch_dev) { |
4710 | ret = false; | |
4711 | goto out_unlock; | |
4712 | } | |
4713 | dev_priv = i915_mch_dev; | |
4714 | ||
20e4d407 DV |
4715 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
4716 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
4717 | |
4718 | out_unlock: | |
9270388e | 4719 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4720 | |
4721 | return ret; | |
4722 | } | |
4723 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
4724 | ||
4725 | /** | |
4726 | * i915_gpu_busy - indicate GPU business to IPS | |
4727 | * | |
4728 | * Tell the IPS driver whether or not the GPU is busy. | |
4729 | */ | |
4730 | bool i915_gpu_busy(void) | |
4731 | { | |
4732 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 4733 | struct intel_engine_cs *ring; |
eb48eb00 | 4734 | bool ret = false; |
f047e395 | 4735 | int i; |
eb48eb00 | 4736 | |
9270388e | 4737 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4738 | if (!i915_mch_dev) |
4739 | goto out_unlock; | |
4740 | dev_priv = i915_mch_dev; | |
4741 | ||
f047e395 CW |
4742 | for_each_ring(ring, dev_priv, i) |
4743 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
4744 | |
4745 | out_unlock: | |
9270388e | 4746 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4747 | |
4748 | return ret; | |
4749 | } | |
4750 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
4751 | ||
4752 | /** | |
4753 | * i915_gpu_turbo_disable - disable graphics turbo | |
4754 | * | |
4755 | * Disable graphics turbo by resetting the max frequency and setting the | |
4756 | * current frequency to the default. | |
4757 | */ | |
4758 | bool i915_gpu_turbo_disable(void) | |
4759 | { | |
4760 | struct drm_i915_private *dev_priv; | |
4761 | bool ret = true; | |
4762 | ||
9270388e | 4763 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
4764 | if (!i915_mch_dev) { |
4765 | ret = false; | |
4766 | goto out_unlock; | |
4767 | } | |
4768 | dev_priv = i915_mch_dev; | |
4769 | ||
20e4d407 | 4770 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 4771 | |
20e4d407 | 4772 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
4773 | ret = false; |
4774 | ||
4775 | out_unlock: | |
9270388e | 4776 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4777 | |
4778 | return ret; | |
4779 | } | |
4780 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
4781 | ||
4782 | /** | |
4783 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
4784 | * IPS got loaded first. | |
4785 | * | |
4786 | * This awkward dance is so that neither module has to depend on the | |
4787 | * other in order for IPS to do the appropriate communication of | |
4788 | * GPU turbo limits to i915. | |
4789 | */ | |
4790 | static void | |
4791 | ips_ping_for_i915_load(void) | |
4792 | { | |
4793 | void (*link)(void); | |
4794 | ||
4795 | link = symbol_get(ips_link_to_i915_driver); | |
4796 | if (link) { | |
4797 | link(); | |
4798 | symbol_put(ips_link_to_i915_driver); | |
4799 | } | |
4800 | } | |
4801 | ||
4802 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
4803 | { | |
02d71956 DV |
4804 | /* We only register the i915 ips part with intel-ips once everything is |
4805 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 4806 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 4807 | i915_mch_dev = dev_priv; |
9270388e | 4808 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
4809 | |
4810 | ips_ping_for_i915_load(); | |
4811 | } | |
4812 | ||
4813 | void intel_gpu_ips_teardown(void) | |
4814 | { | |
9270388e | 4815 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 4816 | i915_mch_dev = NULL; |
9270388e | 4817 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 4818 | } |
76c3552f | 4819 | |
8090c6b9 | 4820 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
4821 | { |
4822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4823 | u32 lcfuse; | |
4824 | u8 pxw[16]; | |
4825 | int i; | |
4826 | ||
4827 | /* Disable to program */ | |
4828 | I915_WRITE(ECR, 0); | |
4829 | POSTING_READ(ECR); | |
4830 | ||
4831 | /* Program energy weights for various events */ | |
4832 | I915_WRITE(SDEW, 0x15040d00); | |
4833 | I915_WRITE(CSIEW0, 0x007f0000); | |
4834 | I915_WRITE(CSIEW1, 0x1e220004); | |
4835 | I915_WRITE(CSIEW2, 0x04000004); | |
4836 | ||
4837 | for (i = 0; i < 5; i++) | |
4838 | I915_WRITE(PEW + (i * 4), 0); | |
4839 | for (i = 0; i < 3; i++) | |
4840 | I915_WRITE(DEW + (i * 4), 0); | |
4841 | ||
4842 | /* Program P-state weights to account for frequency power adjustment */ | |
4843 | for (i = 0; i < 16; i++) { | |
4844 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
4845 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
4846 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
4847 | PXVFREQ_PX_SHIFT; | |
4848 | unsigned long val; | |
4849 | ||
4850 | val = vid * vid; | |
4851 | val *= (freq / 1000); | |
4852 | val *= 255; | |
4853 | val /= (127*127*900); | |
4854 | if (val > 0xff) | |
4855 | DRM_ERROR("bad pxval: %ld\n", val); | |
4856 | pxw[i] = val; | |
4857 | } | |
4858 | /* Render standby states get 0 weight */ | |
4859 | pxw[14] = 0; | |
4860 | pxw[15] = 0; | |
4861 | ||
4862 | for (i = 0; i < 4; i++) { | |
4863 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
4864 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
4865 | I915_WRITE(PXW + (i * 4), val); | |
4866 | } | |
4867 | ||
4868 | /* Adjust magic regs to magic values (more experimental results) */ | |
4869 | I915_WRITE(OGW0, 0); | |
4870 | I915_WRITE(OGW1, 0); | |
4871 | I915_WRITE(EG0, 0x00007f00); | |
4872 | I915_WRITE(EG1, 0x0000000e); | |
4873 | I915_WRITE(EG2, 0x000e0000); | |
4874 | I915_WRITE(EG3, 0x68000300); | |
4875 | I915_WRITE(EG4, 0x42000000); | |
4876 | I915_WRITE(EG5, 0x00140031); | |
4877 | I915_WRITE(EG6, 0); | |
4878 | I915_WRITE(EG7, 0); | |
4879 | ||
4880 | for (i = 0; i < 8; i++) | |
4881 | I915_WRITE(PXWL + (i * 4), 0); | |
4882 | ||
4883 | /* Enable PMON + select events */ | |
4884 | I915_WRITE(ECR, 0x80000019); | |
4885 | ||
4886 | lcfuse = I915_READ(LCFUSE02); | |
4887 | ||
20e4d407 | 4888 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
4889 | } |
4890 | ||
ae48434c ID |
4891 | void intel_init_gt_powersave(struct drm_device *dev) |
4892 | { | |
e6069ca8 ID |
4893 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
4894 | ||
38807746 D |
4895 | if (IS_CHERRYVIEW(dev)) |
4896 | cherryview_init_gt_powersave(dev); | |
4897 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 4898 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
4899 | } |
4900 | ||
4901 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
4902 | { | |
38807746 D |
4903 | if (IS_CHERRYVIEW(dev)) |
4904 | return; | |
4905 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 4906 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
4907 | } |
4908 | ||
156c7ca0 JB |
4909 | /** |
4910 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
4911 | * @dev: drm device | |
4912 | * | |
4913 | * We don't want to disable RC6 or other features here, we just want | |
4914 | * to make sure any work we've queued has finished and won't bother | |
4915 | * us while we're suspended. | |
4916 | */ | |
4917 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
4918 | { | |
4919 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4920 | ||
4921 | /* Interrupts should be disabled already to avoid re-arming. */ | |
e11aa362 | 4922 | WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled); |
156c7ca0 JB |
4923 | |
4924 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
4925 | ||
4926 | cancel_work_sync(&dev_priv->rps.work); | |
4927 | } | |
4928 | ||
8090c6b9 DV |
4929 | void intel_disable_gt_powersave(struct drm_device *dev) |
4930 | { | |
1a01ab3b JB |
4931 | struct drm_i915_private *dev_priv = dev->dev_private; |
4932 | ||
fd0c0642 | 4933 | /* Interrupts should be disabled already to avoid re-arming. */ |
e11aa362 | 4934 | WARN_ON(dev->irq_enabled && !dev_priv->pm.irqs_disabled); |
fd0c0642 | 4935 | |
930ebb46 | 4936 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 4937 | ironlake_disable_drps(dev); |
930ebb46 | 4938 | ironlake_disable_rc6(dev); |
38807746 | 4939 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 4940 | intel_suspend_gt_powersave(dev); |
e494837a | 4941 | |
4fc688ce | 4942 | mutex_lock(&dev_priv->rps.hw_lock); |
38807746 D |
4943 | if (IS_CHERRYVIEW(dev)) |
4944 | cherryview_disable_rps(dev); | |
4945 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
4946 | valleyview_disable_rps(dev); |
4947 | else | |
4948 | gen6_disable_rps(dev); | |
c0951f0c | 4949 | dev_priv->rps.enabled = false; |
4fc688ce | 4950 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 4951 | } |
8090c6b9 DV |
4952 | } |
4953 | ||
1a01ab3b JB |
4954 | static void intel_gen6_powersave_work(struct work_struct *work) |
4955 | { | |
4956 | struct drm_i915_private *dev_priv = | |
4957 | container_of(work, struct drm_i915_private, | |
4958 | rps.delayed_resume_work.work); | |
4959 | struct drm_device *dev = dev_priv->dev; | |
4960 | ||
4fc688ce | 4961 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 4962 | |
38807746 D |
4963 | if (IS_CHERRYVIEW(dev)) { |
4964 | cherryview_enable_rps(dev); | |
4965 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 4966 | valleyview_enable_rps(dev); |
6edee7f3 BW |
4967 | } else if (IS_BROADWELL(dev)) { |
4968 | gen8_enable_rps(dev); | |
c2bc2fc5 | 4969 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
4970 | } else { |
4971 | gen6_enable_rps(dev); | |
c2bc2fc5 | 4972 | __gen6_update_ring_freq(dev); |
0a073b84 | 4973 | } |
c0951f0c | 4974 | dev_priv->rps.enabled = true; |
4fc688ce | 4975 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
4976 | |
4977 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
4978 | } |
4979 | ||
8090c6b9 DV |
4980 | void intel_enable_gt_powersave(struct drm_device *dev) |
4981 | { | |
1a01ab3b JB |
4982 | struct drm_i915_private *dev_priv = dev->dev_private; |
4983 | ||
8090c6b9 | 4984 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 4985 | mutex_lock(&dev->struct_mutex); |
8090c6b9 DV |
4986 | ironlake_enable_drps(dev); |
4987 | ironlake_enable_rc6(dev); | |
4988 | intel_init_emon(dev); | |
dc1d0136 | 4989 | mutex_unlock(&dev->struct_mutex); |
38807746 | 4990 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
4991 | /* |
4992 | * PCU communication is slow and this doesn't need to be | |
4993 | * done at any specific time, so do this out of our fast path | |
4994 | * to make resume and init faster. | |
c6df39b5 ID |
4995 | * |
4996 | * We depend on the HW RC6 power context save/restore | |
4997 | * mechanism when entering D3 through runtime PM suspend. So | |
4998 | * disable RPM until RPS/RC6 is properly setup. We can only | |
4999 | * get here via the driver load/system resume/runtime resume | |
5000 | * paths, so the _noresume version is enough (and in case of | |
5001 | * runtime resume it's necessary). | |
1a01ab3b | 5002 | */ |
c6df39b5 ID |
5003 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
5004 | round_jiffies_up_relative(HZ))) | |
5005 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
5006 | } |
5007 | } | |
5008 | ||
c6df39b5 ID |
5009 | void intel_reset_gt_powersave(struct drm_device *dev) |
5010 | { | |
5011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5012 | ||
5013 | dev_priv->rps.enabled = false; | |
5014 | intel_enable_gt_powersave(dev); | |
5015 | } | |
5016 | ||
3107bd48 DV |
5017 | static void ibx_init_clock_gating(struct drm_device *dev) |
5018 | { | |
5019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5020 | ||
5021 | /* | |
5022 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5023 | * gating for the panel power sequencer or it will fail to | |
5024 | * start up when no ports are active. | |
5025 | */ | |
5026 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
5027 | } | |
5028 | ||
0e088b8f VS |
5029 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
5030 | { | |
5031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5032 | int pipe; | |
5033 | ||
5034 | for_each_pipe(pipe) { | |
5035 | I915_WRITE(DSPCNTR(pipe), | |
5036 | I915_READ(DSPCNTR(pipe)) | | |
5037 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
1dba99f4 | 5038 | intel_flush_primary_plane(dev_priv, pipe); |
0e088b8f VS |
5039 | } |
5040 | } | |
5041 | ||
017636cc VS |
5042 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
5043 | { | |
5044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5045 | ||
5046 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
5047 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
5048 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
5049 | ||
5050 | /* | |
5051 | * Don't touch WM1S_LP_EN here. | |
5052 | * Doing so could cause underruns. | |
5053 | */ | |
5054 | } | |
5055 | ||
1fa61106 | 5056 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5057 | { |
5058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5059 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5060 | |
f1e8fa56 DL |
5061 | /* |
5062 | * Required for FBC | |
5063 | * WaFbcDisableDpfcClockGating:ilk | |
5064 | */ | |
4d47e4f5 DL |
5065 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
5066 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
5067 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
5068 | |
5069 | I915_WRITE(PCH_3DCGDIS0, | |
5070 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5071 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5072 | I915_WRITE(PCH_3DCGDIS1, | |
5073 | VFMUNIT_CLOCK_GATE_DISABLE); | |
5074 | ||
6f1d69b0 ED |
5075 | /* |
5076 | * According to the spec the following bits should be set in | |
5077 | * order to enable memory self-refresh | |
5078 | * The bit 22/21 of 0x42004 | |
5079 | * The bit 5 of 0x42020 | |
5080 | * The bit 15 of 0x45000 | |
5081 | */ | |
5082 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5083 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5084 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 5085 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
5086 | I915_WRITE(DISP_ARB_CTL, |
5087 | (I915_READ(DISP_ARB_CTL) | | |
5088 | DISP_FBC_WM_DIS)); | |
017636cc VS |
5089 | |
5090 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
5091 | |
5092 | /* | |
5093 | * Based on the document from hardware guys the following bits | |
5094 | * should be set unconditionally in order to enable FBC. | |
5095 | * The bit 22 of 0x42000 | |
5096 | * The bit 22 of 0x42004 | |
5097 | * The bit 7,8,9 of 0x42020. | |
5098 | */ | |
5099 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 5100 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
5101 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
5102 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5103 | ILK_FBCQ_DIS); | |
5104 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5105 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5106 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
5107 | } |
5108 | ||
4d47e4f5 DL |
5109 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
5110 | ||
6f1d69b0 ED |
5111 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5112 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5113 | ILK_ELPIN_409_SELECT); | |
5114 | I915_WRITE(_3D_CHICKEN2, | |
5115 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
5116 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 5117 | |
ecdb4eb7 | 5118 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
5119 | I915_WRITE(CACHE_MODE_0, |
5120 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 5121 | |
4e04632e AG |
5122 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
5123 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5124 | ||
0e088b8f | 5125 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 5126 | |
3107bd48 DV |
5127 | ibx_init_clock_gating(dev); |
5128 | } | |
5129 | ||
5130 | static void cpt_init_clock_gating(struct drm_device *dev) | |
5131 | { | |
5132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5133 | int pipe; | |
3f704fa2 | 5134 | uint32_t val; |
3107bd48 DV |
5135 | |
5136 | /* | |
5137 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5138 | * gating for the panel power sequencer or it will fail to | |
5139 | * start up when no ports are active. | |
5140 | */ | |
cd664078 JB |
5141 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
5142 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
5143 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
5144 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
5145 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
5146 | /* The below fixes the weird display corruption, a few pixels shifted |
5147 | * downward, on (only) LVDS of some HP laptops with IVY. | |
5148 | */ | |
3f704fa2 | 5149 | for_each_pipe(pipe) { |
dc4bd2d1 PZ |
5150 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
5151 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
5152 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 5153 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 5154 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
5155 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
5156 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
5157 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
5158 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
5159 | } | |
3107bd48 DV |
5160 | /* WADP0ClockGatingDisable */ |
5161 | for_each_pipe(pipe) { | |
5162 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
5163 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
5164 | } | |
6f1d69b0 ED |
5165 | } |
5166 | ||
1d7aaa0c DV |
5167 | static void gen6_check_mch_setup(struct drm_device *dev) |
5168 | { | |
5169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5170 | uint32_t tmp; | |
5171 | ||
5172 | tmp = I915_READ(MCH_SSKPD); | |
5173 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { | |
5174 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); | |
5175 | DRM_INFO("This can cause pipe underruns and display issues.\n"); | |
5176 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); | |
5177 | } | |
5178 | } | |
5179 | ||
1fa61106 | 5180 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5181 | { |
5182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5183 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5184 | |
231e54f6 | 5185 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
5186 | |
5187 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5188 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5189 | ILK_ELPIN_409_SELECT); | |
5190 | ||
ecdb4eb7 | 5191 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
5192 | I915_WRITE(_3D_CHICKEN, |
5193 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
5194 | ||
ecdb4eb7 | 5195 | /* WaSetupGtModeTdRowDispatch:snb */ |
6547fbdb DV |
5196 | if (IS_SNB_GT1(dev)) |
5197 | I915_WRITE(GEN6_GT_MODE, | |
5198 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); | |
5199 | ||
4e04632e AG |
5200 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
5201 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5202 | ||
8d85d272 VS |
5203 | /* |
5204 | * BSpec recoomends 8x4 when MSAA is used, | |
5205 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5206 | * |
5207 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5208 | * disable bit, which we don't touch here, but it's good | |
5209 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
5210 | */ |
5211 | I915_WRITE(GEN6_GT_MODE, | |
5212 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
5213 | ||
017636cc | 5214 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 5215 | |
6f1d69b0 | 5216 | I915_WRITE(CACHE_MODE_0, |
50743298 | 5217 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
5218 | |
5219 | I915_WRITE(GEN6_UCGCTL1, | |
5220 | I915_READ(GEN6_UCGCTL1) | | |
5221 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
5222 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
5223 | ||
5224 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
5225 | * gating disable must be set. Failure to set it results in | |
5226 | * flickering pixels due to Z write ordering failures after | |
5227 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
5228 | * Sanctuary and Tropics, and apparently anything else with | |
5229 | * alpha test or pixel discard. | |
5230 | * | |
5231 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
5232 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 5233 | * |
ef59318c VS |
5234 | * WaDisableRCCUnitClockGating:snb |
5235 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
5236 | */ |
5237 | I915_WRITE(GEN6_UCGCTL2, | |
5238 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
5239 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
5240 | ||
5eb146dd | 5241 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
5242 | I915_WRITE(_3D_CHICKEN3, |
5243 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 5244 | |
e927ecde VS |
5245 | /* |
5246 | * Bspec says: | |
5247 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
5248 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
5249 | */ | |
5250 | I915_WRITE(_3D_CHICKEN3, | |
5251 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
5252 | ||
6f1d69b0 ED |
5253 | /* |
5254 | * According to the spec the following bits should be | |
5255 | * set in order to enable memory self-refresh and fbc: | |
5256 | * The bit21 and bit22 of 0x42000 | |
5257 | * The bit21 and bit22 of 0x42004 | |
5258 | * The bit5 and bit7 of 0x42020 | |
5259 | * The bit14 of 0x70180 | |
5260 | * The bit14 of 0x71180 | |
4bb35334 DL |
5261 | * |
5262 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
5263 | */ |
5264 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5265 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5266 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
5267 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5268 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5269 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
5270 | I915_WRITE(ILK_DSPCLK_GATE_D, |
5271 | I915_READ(ILK_DSPCLK_GATE_D) | | |
5272 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
5273 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 5274 | |
0e088b8f | 5275 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 5276 | |
3107bd48 | 5277 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
5278 | |
5279 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
5280 | } |
5281 | ||
5282 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
5283 | { | |
5284 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
5285 | ||
3aad9059 | 5286 | /* |
46680e0a | 5287 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
5288 | * |
5289 | * This actually overrides the dispatch | |
5290 | * mode for all thread types. | |
5291 | */ | |
6f1d69b0 ED |
5292 | reg &= ~GEN7_FF_SCHED_MASK; |
5293 | reg |= GEN7_FF_TS_SCHED_HW; | |
5294 | reg |= GEN7_FF_VS_SCHED_HW; | |
5295 | reg |= GEN7_FF_DS_SCHED_HW; | |
5296 | ||
5297 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
5298 | } | |
5299 | ||
17a303ec PZ |
5300 | static void lpt_init_clock_gating(struct drm_device *dev) |
5301 | { | |
5302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5303 | ||
5304 | /* | |
5305 | * TODO: this bit should only be enabled when really needed, then | |
5306 | * disabled when not needed anymore in order to save power. | |
5307 | */ | |
5308 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
5309 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
5310 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
5311 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
5312 | |
5313 | /* WADPOClockGatingDisable:hsw */ | |
5314 | I915_WRITE(_TRANSA_CHICKEN1, | |
5315 | I915_READ(_TRANSA_CHICKEN1) | | |
5316 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
17a303ec PZ |
5317 | } |
5318 | ||
7d708ee4 ID |
5319 | static void lpt_suspend_hw(struct drm_device *dev) |
5320 | { | |
5321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5322 | ||
5323 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
5324 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
5325 | ||
5326 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
5327 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
5328 | } | |
5329 | } | |
5330 | ||
1020a5c2 BW |
5331 | static void gen8_init_clock_gating(struct drm_device *dev) |
5332 | { | |
5333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 5334 | enum pipe pipe; |
1020a5c2 BW |
5335 | |
5336 | I915_WRITE(WM3_LP_ILK, 0); | |
5337 | I915_WRITE(WM2_LP_ILK, 0); | |
5338 | I915_WRITE(WM1_LP_ILK, 0); | |
50ed5fbd BW |
5339 | |
5340 | /* FIXME(BDW): Check all the w/a, some might only apply to | |
5341 | * pre-production hw. */ | |
5342 | ||
c8966e10 KG |
5343 | /* WaDisablePartialInstShootdown:bdw */ |
5344 | I915_WRITE(GEN8_ROW_CHICKEN, | |
5345 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); | |
5346 | ||
1411e6a5 KG |
5347 | /* WaDisableThreadStallDopClockGating:bdw */ |
5348 | /* FIXME: Unclear whether we really need this on production bdw. */ | |
5349 | I915_WRITE(GEN8_ROW_CHICKEN, | |
5350 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); | |
5351 | ||
4167e32c DL |
5352 | /* |
5353 | * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for | |
5354 | * pre-production hardware | |
5355 | */ | |
fd392b60 BW |
5356 | I915_WRITE(HALF_SLICE_CHICKEN3, |
5357 | _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS)); | |
bf66347c BW |
5358 | I915_WRITE(HALF_SLICE_CHICKEN3, |
5359 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); | |
4afe8d33 BW |
5360 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); |
5361 | ||
7f88da0c BW |
5362 | I915_WRITE(_3D_CHICKEN3, |
5363 | _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); | |
5364 | ||
a75f3628 BW |
5365 | I915_WRITE(COMMON_SLICE_CHICKEN2, |
5366 | _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); | |
5367 | ||
4c2e7a5f BW |
5368 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
5369 | _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); | |
5370 | ||
242a4018 BW |
5371 | /* WaDisableDopClockGating:bdw May not be needed for production */ |
5372 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
5373 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
5374 | ||
ab57fff1 | 5375 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 5376 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 5377 | |
ab57fff1 | 5378 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
5379 | I915_WRITE(CHICKEN_PAR1_1, |
5380 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
5381 | ||
ab57fff1 | 5382 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
07d27e20 DL |
5383 | for_each_pipe(pipe) { |
5384 | I915_WRITE(CHICKEN_PIPESL_1(pipe), | |
c7c65622 | 5385 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 5386 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 5387 | } |
63801f21 BW |
5388 | |
5389 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
5390 | * workaround for for a possible hang in the unlikely event a TLB | |
5391 | * invalidation occurs during a PSD flush. | |
5392 | */ | |
5393 | I915_WRITE(HDC_CHICKEN0, | |
5394 | I915_READ(HDC_CHICKEN0) | | |
5395 | _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); | |
ab57fff1 BW |
5396 | |
5397 | /* WaVSRefCountFullforceMissDisable:bdw */ | |
5398 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
5399 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
5400 | I915_READ(GEN7_FF_THREAD_MODE) & | |
5401 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c VS |
5402 | |
5403 | /* | |
5404 | * BSpec recommends 8x4 when MSAA is used, | |
5405 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5406 | * |
5407 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5408 | * disable bit, which we don't touch here, but it's good | |
5409 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
36075a4c VS |
5410 | */ |
5411 | I915_WRITE(GEN7_GT_MODE, | |
5412 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
295e8bb7 VS |
5413 | |
5414 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
5415 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
5416 | |
5417 | /* WaDisableSDEUnitClockGating:bdw */ | |
5418 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
5419 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 DL |
5420 | |
5421 | /* Wa4x4STCOptimizationDisable:bdw */ | |
5422 | I915_WRITE(CACHE_MODE_1, | |
5423 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); | |
1020a5c2 BW |
5424 | } |
5425 | ||
cad2a2d7 ED |
5426 | static void haswell_init_clock_gating(struct drm_device *dev) |
5427 | { | |
5428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 5429 | |
017636cc | 5430 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 5431 | |
f3fc4884 FJ |
5432 | /* L3 caching of data atomics doesn't work -- disable it. */ |
5433 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
5434 | I915_WRITE(HSW_ROW_CHICKEN3, | |
5435 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
5436 | ||
ecdb4eb7 | 5437 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
5438 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
5439 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
5440 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
5441 | ||
e36ea7ff VS |
5442 | /* WaVSRefCountFullforceMissDisable:hsw */ |
5443 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
5444 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 5445 | |
4e04632e AG |
5446 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
5447 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5448 | ||
fe27c606 CW |
5449 | /* enable HiZ Raw Stall Optimization */ |
5450 | I915_WRITE(CACHE_MODE_0_GEN7, | |
5451 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
5452 | ||
ecdb4eb7 | 5453 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
5454 | I915_WRITE(CACHE_MODE_1, |
5455 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 5456 | |
a12c4967 VS |
5457 | /* |
5458 | * BSpec recommends 8x4 when MSAA is used, | |
5459 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5460 | * |
5461 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5462 | * disable bit, which we don't touch here, but it's good | |
5463 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
5464 | */ |
5465 | I915_WRITE(GEN7_GT_MODE, | |
5466 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
5467 | ||
ecdb4eb7 | 5468 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
5469 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
5470 | ||
90a88643 PZ |
5471 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
5472 | I915_WRITE(CHICKEN_PAR1_1, | |
5473 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 5474 | |
17a303ec | 5475 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
5476 | } |
5477 | ||
1fa61106 | 5478 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5479 | { |
5480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 5481 | uint32_t snpcr; |
6f1d69b0 | 5482 | |
017636cc | 5483 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 5484 | |
231e54f6 | 5485 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 5486 | |
ecdb4eb7 | 5487 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
5488 | I915_WRITE(_3D_CHICKEN3, |
5489 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
5490 | ||
ecdb4eb7 | 5491 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
5492 | I915_WRITE(IVB_CHICKEN3, |
5493 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
5494 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
5495 | ||
ecdb4eb7 | 5496 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
5497 | if (IS_IVB_GT1(dev)) |
5498 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
5499 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 5500 | |
4e04632e AG |
5501 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
5502 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5503 | ||
ecdb4eb7 | 5504 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
5505 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
5506 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
5507 | ||
ecdb4eb7 | 5508 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
5509 | I915_WRITE(GEN7_L3CNTLREG1, |
5510 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
5511 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
5512 | GEN7_WA_L3_CHICKEN_MODE); |
5513 | if (IS_IVB_GT1(dev)) | |
5514 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
5515 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
5516 | else { |
5517 | /* must write both registers */ | |
5518 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
5519 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
5520 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
5521 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 5522 | } |
6f1d69b0 | 5523 | |
ecdb4eb7 | 5524 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
5525 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
5526 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
5527 | ||
1b80a19a | 5528 | /* |
0f846f81 | 5529 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 5530 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
5531 | */ |
5532 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 5533 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 5534 | |
ecdb4eb7 | 5535 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
5536 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
5537 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
5538 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
5539 | ||
0e088b8f | 5540 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
5541 | |
5542 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 5543 | |
22721343 CW |
5544 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
5545 | /* enable HiZ Raw Stall Optimization */ | |
5546 | I915_WRITE(CACHE_MODE_0_GEN7, | |
5547 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
5548 | } | |
116f2b6d | 5549 | |
ecdb4eb7 | 5550 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
5551 | I915_WRITE(CACHE_MODE_1, |
5552 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 5553 | |
a607c1a4 VS |
5554 | /* |
5555 | * BSpec recommends 8x4 when MSAA is used, | |
5556 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5557 | * |
5558 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5559 | * disable bit, which we don't touch here, but it's good | |
5560 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
5561 | */ |
5562 | I915_WRITE(GEN7_GT_MODE, | |
5563 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
5564 | ||
20848223 BW |
5565 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
5566 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
5567 | snpcr |= GEN6_MBC_SNPCR_MED; | |
5568 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 5569 | |
ab5c608b BW |
5570 | if (!HAS_PCH_NOP(dev)) |
5571 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
5572 | |
5573 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
5574 | } |
5575 | ||
1fa61106 | 5576 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5577 | { |
5578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
85b1d7b3 JB |
5579 | u32 val; |
5580 | ||
5581 | mutex_lock(&dev_priv->rps.hw_lock); | |
5582 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
5583 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5584 | switch ((val >> 6) & 3) { | |
5585 | case 0: | |
f64a28a7 | 5586 | case 1: |
f6d51948 | 5587 | dev_priv->mem_freq = 800; |
85b1d7b3 | 5588 | break; |
f64a28a7 | 5589 | case 2: |
f6d51948 | 5590 | dev_priv->mem_freq = 1066; |
85b1d7b3 | 5591 | break; |
f64a28a7 | 5592 | case 3: |
2325991e | 5593 | dev_priv->mem_freq = 1333; |
f64a28a7 | 5594 | break; |
85b1d7b3 JB |
5595 | } |
5596 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); | |
6f1d69b0 | 5597 | |
d7fe0cc0 | 5598 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 5599 | |
ecdb4eb7 | 5600 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
5601 | I915_WRITE(_3D_CHICKEN3, |
5602 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
5603 | ||
ecdb4eb7 | 5604 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
5605 | I915_WRITE(IVB_CHICKEN3, |
5606 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
5607 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
5608 | ||
fad7d36e | 5609 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 5610 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 5611 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
5612 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
5613 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 5614 | |
4e04632e AG |
5615 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
5616 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5617 | ||
ecdb4eb7 | 5618 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
5619 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
5620 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
5621 | ||
ecdb4eb7 | 5622 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
5623 | I915_WRITE(GEN7_ROW_CHICKEN2, |
5624 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
5625 | ||
ecdb4eb7 | 5626 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
5627 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
5628 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
5629 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
5630 | ||
46680e0a VS |
5631 | gen7_setup_fixed_func_scheduler(dev_priv); |
5632 | ||
3c0edaeb | 5633 | /* |
0f846f81 | 5634 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 5635 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
5636 | */ |
5637 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 5638 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 5639 | |
c98f5062 AG |
5640 | /* WaDisableL3Bank2xClockGate:vlv |
5641 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
5642 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
5643 | I915_WRITE(GEN7_UCGCTL4, | |
5644 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 5645 | |
e0d8d59b | 5646 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
6f1d69b0 | 5647 | |
afd58e79 VS |
5648 | /* |
5649 | * BSpec says this must be set, even though | |
5650 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
5651 | */ | |
6b26c86d DV |
5652 | I915_WRITE(CACHE_MODE_1, |
5653 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 5654 | |
031994ee VS |
5655 | /* |
5656 | * WaIncreaseL3CreditsForVLVB0:vlv | |
5657 | * This is the hardware default actually. | |
5658 | */ | |
5659 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
5660 | ||
2d809570 | 5661 | /* |
ecdb4eb7 | 5662 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
5663 | * Disable clock gating on th GCFG unit to prevent a delay |
5664 | * in the reporting of vblank events. | |
5665 | */ | |
7a0d1eed | 5666 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
5667 | } |
5668 | ||
a4565da8 VS |
5669 | static void cherryview_init_clock_gating(struct drm_device *dev) |
5670 | { | |
5671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5672 | ||
5673 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
5674 | ||
5675 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
dd811e70 VS |
5676 | |
5677 | /* WaDisablePartialInstShootdown:chv */ | |
5678 | I915_WRITE(GEN8_ROW_CHICKEN, | |
5679 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); | |
a7068025 VS |
5680 | |
5681 | /* WaDisableThreadStallDopClockGating:chv */ | |
5682 | I915_WRITE(GEN8_ROW_CHICKEN, | |
5683 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); | |
232ce337 VS |
5684 | |
5685 | /* WaVSRefCountFullforceMissDisable:chv */ | |
5686 | /* WaDSRefCountFullforceMissDisable:chv */ | |
5687 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
5688 | I915_READ(GEN7_FF_THREAD_MODE) & | |
5689 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
5690 | |
5691 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
5692 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
5693 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
5694 | |
5695 | /* WaDisableCSUnitClockGating:chv */ | |
5696 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
5697 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
5698 | |
5699 | /* WaDisableSDEUnitClockGating:chv */ | |
5700 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
5701 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
e0d34ce7 RB |
5702 | |
5703 | /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ | |
5704 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
5705 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); | |
e4443e45 VS |
5706 | |
5707 | /* WaDisableGunitClockGating:chv (pre-production hw) */ | |
5708 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) | | |
5709 | GINT_DIS); | |
5710 | ||
5711 | /* WaDisableFfDopClockGating:chv (pre-production hw) */ | |
5712 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
5713 | _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE)); | |
5714 | ||
5715 | /* WaDisableDopClockGating:chv (pre-production hw) */ | |
5716 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
5717 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
5718 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
5719 | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); | |
a4565da8 VS |
5720 | } |
5721 | ||
1fa61106 | 5722 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5723 | { |
5724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5725 | uint32_t dspclk_gate; | |
5726 | ||
5727 | I915_WRITE(RENCLK_GATE_D1, 0); | |
5728 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
5729 | GS_UNIT_CLOCK_GATE_DISABLE | | |
5730 | CL_UNIT_CLOCK_GATE_DISABLE); | |
5731 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5732 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
5733 | OVRUNIT_CLOCK_GATE_DISABLE | | |
5734 | OVCUNIT_CLOCK_GATE_DISABLE; | |
5735 | if (IS_GM45(dev)) | |
5736 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
5737 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
5738 | |
5739 | /* WaDisableRenderCachePipelinedFlush */ | |
5740 | I915_WRITE(CACHE_MODE_0, | |
5741 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 5742 | |
4e04632e AG |
5743 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
5744 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5745 | ||
0e088b8f | 5746 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
5747 | } |
5748 | ||
1fa61106 | 5749 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5750 | { |
5751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5752 | ||
5753 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
5754 | I915_WRITE(RENCLK_GATE_D2, 0); | |
5755 | I915_WRITE(DSPCLK_GATE_D, 0); | |
5756 | I915_WRITE(RAMCLK_GATE_D, 0); | |
5757 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
5758 | I915_WRITE(MI_ARB_STATE, |
5759 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
5760 | |
5761 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
5762 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
5763 | } |
5764 | ||
1fa61106 | 5765 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5766 | { |
5767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5768 | ||
5769 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
5770 | I965_RCC_CLOCK_GATE_DISABLE | | |
5771 | I965_RCPB_CLOCK_GATE_DISABLE | | |
5772 | I965_ISC_CLOCK_GATE_DISABLE | | |
5773 | I965_FBC_CLOCK_GATE_DISABLE); | |
5774 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
5775 | I915_WRITE(MI_ARB_STATE, |
5776 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
5777 | |
5778 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
5779 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
5780 | } |
5781 | ||
1fa61106 | 5782 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5783 | { |
5784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5785 | u32 dstate = I915_READ(D_STATE); | |
5786 | ||
5787 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
5788 | DSTATE_DOT_CLOCK_GATING; | |
5789 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
5790 | |
5791 | if (IS_PINEVIEW(dev)) | |
5792 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
5793 | |
5794 | /* IIR "flip pending" means done if this bit is set */ | |
5795 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
5796 | |
5797 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 5798 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
5799 | |
5800 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
5801 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
6f1d69b0 ED |
5802 | } |
5803 | ||
1fa61106 | 5804 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5805 | { |
5806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5807 | ||
5808 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
5809 | |
5810 | /* interrupts should cause a wake up from C3 */ | |
5811 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
5812 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
6f1d69b0 ED |
5813 | } |
5814 | ||
1fa61106 | 5815 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5816 | { |
5817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5818 | ||
5819 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
5820 | } | |
5821 | ||
6f1d69b0 ED |
5822 | void intel_init_clock_gating(struct drm_device *dev) |
5823 | { | |
5824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5825 | ||
5826 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
5827 | } |
5828 | ||
7d708ee4 ID |
5829 | void intel_suspend_hw(struct drm_device *dev) |
5830 | { | |
5831 | if (HAS_PCH_LPT(dev)) | |
5832 | lpt_suspend_hw(dev); | |
5833 | } | |
5834 | ||
c1ca727f ID |
5835 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
5836 | for (i = 0; \ | |
5837 | i < (power_domains)->power_well_count && \ | |
5838 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
5839 | i++) \ | |
5840 | if ((power_well)->domains & (domain_mask)) | |
5841 | ||
5842 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
5843 | for (i = (power_domains)->power_well_count - 1; \ | |
5844 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
5845 | i--) \ | |
5846 | if ((power_well)->domains & (domain_mask)) | |
5847 | ||
15d199ea PZ |
5848 | /** |
5849 | * We should only use the power well if we explicitly asked the hardware to | |
5850 | * enable it, so check if it's enabled and also check if we've requested it to | |
5851 | * be enabled. | |
5852 | */ | |
da7e29bd | 5853 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
c1ca727f ID |
5854 | struct i915_power_well *power_well) |
5855 | { | |
c1ca727f ID |
5856 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
5857 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
5858 | } | |
5859 | ||
bfafe93a ID |
5860 | bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, |
5861 | enum intel_display_power_domain domain) | |
ddf9c536 | 5862 | { |
ddf9c536 | 5863 | struct i915_power_domains *power_domains; |
b8c000d9 ID |
5864 | struct i915_power_well *power_well; |
5865 | bool is_enabled; | |
5866 | int i; | |
5867 | ||
5868 | if (dev_priv->pm.suspended) | |
5869 | return false; | |
ddf9c536 ID |
5870 | |
5871 | power_domains = &dev_priv->power_domains; | |
bfafe93a | 5872 | |
b8c000d9 | 5873 | is_enabled = true; |
bfafe93a | 5874 | |
b8c000d9 ID |
5875 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
5876 | if (power_well->always_on) | |
5877 | continue; | |
ddf9c536 | 5878 | |
bfafe93a | 5879 | if (!power_well->hw_enabled) { |
b8c000d9 ID |
5880 | is_enabled = false; |
5881 | break; | |
5882 | } | |
5883 | } | |
bfafe93a | 5884 | |
b8c000d9 | 5885 | return is_enabled; |
ddf9c536 ID |
5886 | } |
5887 | ||
da7e29bd | 5888 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
b97186f0 | 5889 | enum intel_display_power_domain domain) |
15d199ea | 5890 | { |
c1ca727f | 5891 | struct i915_power_domains *power_domains; |
bfafe93a | 5892 | bool ret; |
882244a3 | 5893 | |
c1ca727f ID |
5894 | power_domains = &dev_priv->power_domains; |
5895 | ||
c1ca727f | 5896 | mutex_lock(&power_domains->lock); |
bfafe93a | 5897 | ret = intel_display_power_enabled_unlocked(dev_priv, domain); |
c1ca727f ID |
5898 | mutex_unlock(&power_domains->lock); |
5899 | ||
bfafe93a | 5900 | return ret; |
15d199ea PZ |
5901 | } |
5902 | ||
93c73e8c ID |
5903 | /* |
5904 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
5905 | * when not needed anymore. We have 4 registers that can request the power well | |
5906 | * to be enabled, and it will only be disabled if none of the registers is | |
5907 | * requesting it to be enabled. | |
5908 | */ | |
d5e8fdc8 PZ |
5909 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
5910 | { | |
5911 | struct drm_device *dev = dev_priv->dev; | |
5912 | unsigned long irqflags; | |
5913 | ||
f9dcb0df PZ |
5914 | /* |
5915 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
5916 | * we'll get unclaimed register interrupts. This stops after we write | |
5917 | * anything to the VGA MSR register. The vgacon module uses this | |
5918 | * register all the time, so if we unbind our driver and, as a | |
5919 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
5920 | * console_unlock(). So make here we touch the VGA MSR register, making | |
5921 | * sure vgacon can keep working normally without triggering interrupts | |
5922 | * and error messages. | |
5923 | */ | |
5924 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
5925 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
5926 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
5927 | ||
d5e8fdc8 PZ |
5928 | if (IS_BROADWELL(dev)) { |
5929 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
5930 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B), | |
5931 | dev_priv->de_irq_mask[PIPE_B]); | |
5932 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B), | |
5933 | ~dev_priv->de_irq_mask[PIPE_B] | | |
5934 | GEN8_PIPE_VBLANK); | |
5935 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C), | |
5936 | dev_priv->de_irq_mask[PIPE_C]); | |
5937 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C), | |
5938 | ~dev_priv->de_irq_mask[PIPE_C] | | |
5939 | GEN8_PIPE_VBLANK); | |
5940 | POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C)); | |
5941 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
5942 | } | |
5943 | } | |
5944 | ||
da7e29bd | 5945 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
c1ca727f | 5946 | struct i915_power_well *power_well, bool enable) |
d0d3e513 | 5947 | { |
fa42e23c PZ |
5948 | bool is_enabled, enable_requested; |
5949 | uint32_t tmp; | |
d0d3e513 | 5950 | |
fa42e23c | 5951 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
6aedd1f5 PZ |
5952 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
5953 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
d0d3e513 | 5954 | |
fa42e23c PZ |
5955 | if (enable) { |
5956 | if (!enable_requested) | |
6aedd1f5 PZ |
5957 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
5958 | HSW_PWR_WELL_ENABLE_REQUEST); | |
d0d3e513 | 5959 | |
fa42e23c PZ |
5960 | if (!is_enabled) { |
5961 | DRM_DEBUG_KMS("Enabling power well\n"); | |
5962 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
6aedd1f5 | 5963 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
fa42e23c PZ |
5964 | DRM_ERROR("Timeout enabling power well\n"); |
5965 | } | |
596cc11e | 5966 | |
d5e8fdc8 | 5967 | hsw_power_well_post_enable(dev_priv); |
fa42e23c PZ |
5968 | } else { |
5969 | if (enable_requested) { | |
5970 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
9dbd8feb | 5971 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
fa42e23c | 5972 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
d0d3e513 ED |
5973 | } |
5974 | } | |
fa42e23c | 5975 | } |
d0d3e513 | 5976 | |
c6cb582e ID |
5977 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
5978 | struct i915_power_well *power_well) | |
5979 | { | |
5980 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
5981 | ||
5982 | /* | |
5983 | * We're taking over the BIOS, so clear any requests made by it since | |
5984 | * the driver is in charge now. | |
5985 | */ | |
5986 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
5987 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
5988 | } | |
5989 | ||
5990 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
5991 | struct i915_power_well *power_well) | |
5992 | { | |
c6cb582e ID |
5993 | hsw_set_power_well(dev_priv, power_well, true); |
5994 | } | |
5995 | ||
5996 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
5997 | struct i915_power_well *power_well) | |
5998 | { | |
5999 | hsw_set_power_well(dev_priv, power_well, false); | |
c6cb582e ID |
6000 | } |
6001 | ||
a45f4466 ID |
6002 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
6003 | struct i915_power_well *power_well) | |
6004 | { | |
6005 | } | |
6006 | ||
6007 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
6008 | struct i915_power_well *power_well) | |
6009 | { | |
6010 | return true; | |
6011 | } | |
6012 | ||
d2011dc8 VS |
6013 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
6014 | struct i915_power_well *power_well, bool enable) | |
77961eb9 | 6015 | { |
d2011dc8 | 6016 | enum punit_power_well power_well_id = power_well->data; |
77961eb9 ID |
6017 | u32 mask; |
6018 | u32 state; | |
6019 | u32 ctrl; | |
6020 | ||
6021 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
6022 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
6023 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
6024 | ||
6025 | mutex_lock(&dev_priv->rps.hw_lock); | |
6026 | ||
6027 | #define COND \ | |
6028 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
6029 | ||
6030 | if (COND) | |
6031 | goto out; | |
6032 | ||
6033 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
6034 | ctrl &= ~mask; | |
6035 | ctrl |= state; | |
6036 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
6037 | ||
6038 | if (wait_for(COND, 100)) | |
6039 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
6040 | state, | |
6041 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
6042 | ||
6043 | #undef COND | |
6044 | ||
6045 | out: | |
6046 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6047 | } | |
6048 | ||
6049 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
6050 | struct i915_power_well *power_well) | |
6051 | { | |
6052 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
6053 | } | |
6054 | ||
6055 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
6056 | struct i915_power_well *power_well) | |
6057 | { | |
6058 | vlv_set_power_well(dev_priv, power_well, true); | |
6059 | } | |
6060 | ||
6061 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
6062 | struct i915_power_well *power_well) | |
6063 | { | |
6064 | vlv_set_power_well(dev_priv, power_well, false); | |
6065 | } | |
6066 | ||
6067 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
6068 | struct i915_power_well *power_well) | |
6069 | { | |
6070 | int power_well_id = power_well->data; | |
6071 | bool enabled = false; | |
6072 | u32 mask; | |
6073 | u32 state; | |
6074 | u32 ctrl; | |
6075 | ||
6076 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
6077 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
6078 | ||
6079 | mutex_lock(&dev_priv->rps.hw_lock); | |
6080 | ||
6081 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
6082 | /* | |
6083 | * We only ever set the power-on and power-gate states, anything | |
6084 | * else is unexpected. | |
6085 | */ | |
6086 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
6087 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
6088 | if (state == ctrl) | |
6089 | enabled = true; | |
6090 | ||
6091 | /* | |
6092 | * A transient state at this point would mean some unexpected party | |
6093 | * is poking at the power controls too. | |
6094 | */ | |
6095 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
6096 | WARN_ON(ctrl != state); | |
6097 | ||
6098 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6099 | ||
6100 | return enabled; | |
6101 | } | |
6102 | ||
6103 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
6104 | struct i915_power_well *power_well) | |
6105 | { | |
6106 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
6107 | ||
6108 | vlv_set_power_well(dev_priv, power_well, true); | |
6109 | ||
6110 | spin_lock_irq(&dev_priv->irq_lock); | |
6111 | valleyview_enable_display_irqs(dev_priv); | |
6112 | spin_unlock_irq(&dev_priv->irq_lock); | |
6113 | ||
6114 | /* | |
0d116a29 ID |
6115 | * During driver initialization/resume we can avoid restoring the |
6116 | * part of the HW/SW state that will be inited anyway explicitly. | |
77961eb9 | 6117 | */ |
0d116a29 ID |
6118 | if (dev_priv->power_domains.initializing) |
6119 | return; | |
6120 | ||
6121 | intel_hpd_init(dev_priv->dev); | |
77961eb9 ID |
6122 | |
6123 | i915_redisable_vga_power_on(dev_priv->dev); | |
6124 | } | |
6125 | ||
6126 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, | |
6127 | struct i915_power_well *power_well) | |
6128 | { | |
77961eb9 ID |
6129 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
6130 | ||
6131 | spin_lock_irq(&dev_priv->irq_lock); | |
77961eb9 ID |
6132 | valleyview_disable_display_irqs(dev_priv); |
6133 | spin_unlock_irq(&dev_priv->irq_lock); | |
6134 | ||
77961eb9 ID |
6135 | vlv_set_power_well(dev_priv, power_well, false); |
6136 | } | |
6137 | ||
aa519f23 VS |
6138 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
6139 | struct i915_power_well *power_well) | |
6140 | { | |
6141 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
6142 | ||
6143 | /* | |
6144 | * Enable the CRI clock source so we can get at the | |
6145 | * display and the reference clock for VGA | |
6146 | * hotplug / manual detection. | |
6147 | */ | |
6148 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
6149 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
6150 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
6151 | ||
6152 | vlv_set_power_well(dev_priv, power_well, true); | |
6153 | ||
6154 | /* | |
6155 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
6156 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
6157 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
6158 | * b. The other bits such as sfr settings / modesel may all | |
6159 | * be set to 0. | |
6160 | * | |
6161 | * This should only be done on init and resume from S3 with | |
6162 | * both PLLs disabled, or we risk losing DPIO and PLL | |
6163 | * synchronization. | |
6164 | */ | |
6165 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
6166 | } | |
6167 | ||
6168 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
6169 | struct i915_power_well *power_well) | |
6170 | { | |
6171 | struct drm_device *dev = dev_priv->dev; | |
6172 | enum pipe pipe; | |
6173 | ||
6174 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
6175 | ||
6176 | for_each_pipe(pipe) | |
6177 | assert_pll_disabled(dev_priv, pipe); | |
6178 | ||
6179 | /* Assert common reset */ | |
6180 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
6181 | ||
6182 | vlv_set_power_well(dev_priv, power_well, false); | |
6183 | } | |
6184 | ||
25eaa003 ID |
6185 | static void check_power_well_state(struct drm_i915_private *dev_priv, |
6186 | struct i915_power_well *power_well) | |
6187 | { | |
6188 | bool enabled = power_well->ops->is_enabled(dev_priv, power_well); | |
6189 | ||
6190 | if (power_well->always_on || !i915.disable_power_well) { | |
6191 | if (!enabled) | |
6192 | goto mismatch; | |
6193 | ||
6194 | return; | |
6195 | } | |
6196 | ||
6197 | if (enabled != (power_well->count > 0)) | |
6198 | goto mismatch; | |
6199 | ||
6200 | return; | |
6201 | ||
6202 | mismatch: | |
6203 | WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n", | |
6204 | power_well->name, power_well->always_on, enabled, | |
6205 | power_well->count, i915.disable_power_well); | |
6206 | } | |
6207 | ||
da7e29bd | 6208 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
6765625e VS |
6209 | enum intel_display_power_domain domain) |
6210 | { | |
83c00f55 | 6211 | struct i915_power_domains *power_domains; |
c1ca727f ID |
6212 | struct i915_power_well *power_well; |
6213 | int i; | |
6765625e | 6214 | |
9e6ea71a PZ |
6215 | intel_runtime_pm_get(dev_priv); |
6216 | ||
83c00f55 ID |
6217 | power_domains = &dev_priv->power_domains; |
6218 | ||
6219 | mutex_lock(&power_domains->lock); | |
1da51581 | 6220 | |
25eaa003 ID |
6221 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
6222 | if (!power_well->count++) { | |
6223 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
c6cb582e | 6224 | power_well->ops->enable(dev_priv, power_well); |
bfafe93a | 6225 | power_well->hw_enabled = true; |
25eaa003 ID |
6226 | } |
6227 | ||
6228 | check_power_well_state(dev_priv, power_well); | |
6229 | } | |
1da51581 | 6230 | |
ddf9c536 ID |
6231 | power_domains->domain_use_count[domain]++; |
6232 | ||
83c00f55 | 6233 | mutex_unlock(&power_domains->lock); |
6765625e VS |
6234 | } |
6235 | ||
da7e29bd | 6236 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
6765625e VS |
6237 | enum intel_display_power_domain domain) |
6238 | { | |
83c00f55 | 6239 | struct i915_power_domains *power_domains; |
c1ca727f ID |
6240 | struct i915_power_well *power_well; |
6241 | int i; | |
6765625e | 6242 | |
83c00f55 ID |
6243 | power_domains = &dev_priv->power_domains; |
6244 | ||
6245 | mutex_lock(&power_domains->lock); | |
1da51581 | 6246 | |
1da51581 ID |
6247 | WARN_ON(!power_domains->domain_use_count[domain]); |
6248 | power_domains->domain_use_count[domain]--; | |
ddf9c536 | 6249 | |
70bf407c ID |
6250 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
6251 | WARN_ON(!power_well->count); | |
6252 | ||
25eaa003 ID |
6253 | if (!--power_well->count && i915.disable_power_well) { |
6254 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
bfafe93a | 6255 | power_well->hw_enabled = false; |
c6cb582e | 6256 | power_well->ops->disable(dev_priv, power_well); |
25eaa003 ID |
6257 | } |
6258 | ||
6259 | check_power_well_state(dev_priv, power_well); | |
70bf407c | 6260 | } |
1da51581 | 6261 | |
83c00f55 | 6262 | mutex_unlock(&power_domains->lock); |
9e6ea71a PZ |
6263 | |
6264 | intel_runtime_pm_put(dev_priv); | |
6765625e VS |
6265 | } |
6266 | ||
83c00f55 | 6267 | static struct i915_power_domains *hsw_pwr; |
a38911a3 WX |
6268 | |
6269 | /* Display audio driver power well request */ | |
74b0c2d7 | 6270 | int i915_request_power_well(void) |
a38911a3 | 6271 | { |
b4ed4484 ID |
6272 | struct drm_i915_private *dev_priv; |
6273 | ||
74b0c2d7 TI |
6274 | if (!hsw_pwr) |
6275 | return -ENODEV; | |
a38911a3 | 6276 | |
b4ed4484 ID |
6277 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
6278 | power_domains); | |
da7e29bd | 6279 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
74b0c2d7 | 6280 | return 0; |
a38911a3 WX |
6281 | } |
6282 | EXPORT_SYMBOL_GPL(i915_request_power_well); | |
6283 | ||
6284 | /* Display audio driver power well release */ | |
74b0c2d7 | 6285 | int i915_release_power_well(void) |
a38911a3 | 6286 | { |
b4ed4484 ID |
6287 | struct drm_i915_private *dev_priv; |
6288 | ||
74b0c2d7 TI |
6289 | if (!hsw_pwr) |
6290 | return -ENODEV; | |
a38911a3 | 6291 | |
b4ed4484 ID |
6292 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
6293 | power_domains); | |
da7e29bd | 6294 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
74b0c2d7 | 6295 | return 0; |
a38911a3 WX |
6296 | } |
6297 | EXPORT_SYMBOL_GPL(i915_release_power_well); | |
6298 | ||
c149dcb5 JN |
6299 | /* |
6300 | * Private interface for the audio driver to get CDCLK in kHz. | |
6301 | * | |
6302 | * Caller must request power well using i915_request_power_well() prior to | |
6303 | * making the call. | |
6304 | */ | |
6305 | int i915_get_cdclk_freq(void) | |
6306 | { | |
6307 | struct drm_i915_private *dev_priv; | |
6308 | ||
6309 | if (!hsw_pwr) | |
6310 | return -ENODEV; | |
6311 | ||
6312 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, | |
6313 | power_domains); | |
6314 | ||
6315 | return intel_ddi_get_cdclk_freq(dev_priv); | |
6316 | } | |
6317 | EXPORT_SYMBOL_GPL(i915_get_cdclk_freq); | |
6318 | ||
6319 | ||
efcad917 ID |
6320 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
6321 | ||
6322 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ | |
6323 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
f5938f36 | 6324 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
319be8ae ID |
6325 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
6326 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
6327 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
6328 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6329 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
6330 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6331 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
6332 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
6333 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
f5938f36 | 6334 | BIT(POWER_DOMAIN_INIT)) |
efcad917 ID |
6335 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
6336 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
6337 | BIT(POWER_DOMAIN_INIT)) | |
6338 | ||
6339 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
6340 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
6341 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
6342 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
6343 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
6344 | BIT(POWER_DOMAIN_INIT)) | |
6345 | ||
77961eb9 ID |
6346 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
6347 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
6348 | ||
6349 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
6350 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
6351 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6352 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
6353 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6354 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
6355 | BIT(POWER_DOMAIN_INIT)) | |
6356 | ||
6357 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
6358 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
6359 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6360 | BIT(POWER_DOMAIN_INIT)) | |
6361 | ||
6362 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
6363 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
6364 | BIT(POWER_DOMAIN_INIT)) | |
6365 | ||
6366 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
6367 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
6368 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6369 | BIT(POWER_DOMAIN_INIT)) | |
6370 | ||
6371 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
6372 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
6373 | BIT(POWER_DOMAIN_INIT)) | |
6374 | ||
a45f4466 ID |
6375 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
6376 | .sync_hw = i9xx_always_on_power_well_noop, | |
6377 | .enable = i9xx_always_on_power_well_noop, | |
6378 | .disable = i9xx_always_on_power_well_noop, | |
6379 | .is_enabled = i9xx_always_on_power_well_enabled, | |
6380 | }; | |
c6cb582e | 6381 | |
1c2256df ID |
6382 | static struct i915_power_well i9xx_always_on_power_well[] = { |
6383 | { | |
6384 | .name = "always-on", | |
6385 | .always_on = 1, | |
6386 | .domains = POWER_DOMAIN_MASK, | |
c6cb582e | 6387 | .ops = &i9xx_always_on_power_well_ops, |
1c2256df ID |
6388 | }, |
6389 | }; | |
6390 | ||
c6cb582e ID |
6391 | static const struct i915_power_well_ops hsw_power_well_ops = { |
6392 | .sync_hw = hsw_power_well_sync_hw, | |
6393 | .enable = hsw_power_well_enable, | |
6394 | .disable = hsw_power_well_disable, | |
6395 | .is_enabled = hsw_power_well_enabled, | |
6396 | }; | |
6397 | ||
c1ca727f | 6398 | static struct i915_power_well hsw_power_wells[] = { |
6f3ef5dd ID |
6399 | { |
6400 | .name = "always-on", | |
6401 | .always_on = 1, | |
6402 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
c6cb582e | 6403 | .ops = &i9xx_always_on_power_well_ops, |
6f3ef5dd | 6404 | }, |
c1ca727f ID |
6405 | { |
6406 | .name = "display", | |
efcad917 | 6407 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
c6cb582e | 6408 | .ops = &hsw_power_well_ops, |
c1ca727f ID |
6409 | }, |
6410 | }; | |
6411 | ||
6412 | static struct i915_power_well bdw_power_wells[] = { | |
6f3ef5dd ID |
6413 | { |
6414 | .name = "always-on", | |
6415 | .always_on = 1, | |
6416 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
c6cb582e | 6417 | .ops = &i9xx_always_on_power_well_ops, |
6f3ef5dd | 6418 | }, |
c1ca727f ID |
6419 | { |
6420 | .name = "display", | |
efcad917 | 6421 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
c6cb582e | 6422 | .ops = &hsw_power_well_ops, |
c1ca727f ID |
6423 | }, |
6424 | }; | |
6425 | ||
77961eb9 ID |
6426 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
6427 | .sync_hw = vlv_power_well_sync_hw, | |
6428 | .enable = vlv_display_power_well_enable, | |
6429 | .disable = vlv_display_power_well_disable, | |
6430 | .is_enabled = vlv_power_well_enabled, | |
6431 | }; | |
6432 | ||
aa519f23 VS |
6433 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { |
6434 | .sync_hw = vlv_power_well_sync_hw, | |
6435 | .enable = vlv_dpio_cmn_power_well_enable, | |
6436 | .disable = vlv_dpio_cmn_power_well_disable, | |
6437 | .is_enabled = vlv_power_well_enabled, | |
6438 | }; | |
6439 | ||
77961eb9 ID |
6440 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { |
6441 | .sync_hw = vlv_power_well_sync_hw, | |
6442 | .enable = vlv_power_well_enable, | |
6443 | .disable = vlv_power_well_disable, | |
6444 | .is_enabled = vlv_power_well_enabled, | |
6445 | }; | |
6446 | ||
6447 | static struct i915_power_well vlv_power_wells[] = { | |
6448 | { | |
6449 | .name = "always-on", | |
6450 | .always_on = 1, | |
6451 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
6452 | .ops = &i9xx_always_on_power_well_ops, | |
6453 | }, | |
6454 | { | |
6455 | .name = "display", | |
6456 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
6457 | .data = PUNIT_POWER_WELL_DISP2D, | |
6458 | .ops = &vlv_display_power_well_ops, | |
6459 | }, | |
77961eb9 ID |
6460 | { |
6461 | .name = "dpio-tx-b-01", | |
6462 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
6463 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
6464 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
6465 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
6466 | .ops = &vlv_dpio_power_well_ops, | |
6467 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
6468 | }, | |
6469 | { | |
6470 | .name = "dpio-tx-b-23", | |
6471 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
6472 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
6473 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
6474 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
6475 | .ops = &vlv_dpio_power_well_ops, | |
6476 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
6477 | }, | |
6478 | { | |
6479 | .name = "dpio-tx-c-01", | |
6480 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
6481 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
6482 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
6483 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
6484 | .ops = &vlv_dpio_power_well_ops, | |
6485 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
6486 | }, | |
6487 | { | |
6488 | .name = "dpio-tx-c-23", | |
6489 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
6490 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
6491 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
6492 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
6493 | .ops = &vlv_dpio_power_well_ops, | |
6494 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
6495 | }, | |
f099a3c6 JB |
6496 | { |
6497 | .name = "dpio-common", | |
6498 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
6499 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
aa519f23 | 6500 | .ops = &vlv_dpio_cmn_power_well_ops, |
f099a3c6 | 6501 | }, |
77961eb9 ID |
6502 | }; |
6503 | ||
d2011dc8 VS |
6504 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
6505 | enum punit_power_well power_well_id) | |
6506 | { | |
6507 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
6508 | struct i915_power_well *power_well; | |
6509 | int i; | |
6510 | ||
6511 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
6512 | if (power_well->data == power_well_id) | |
6513 | return power_well; | |
6514 | } | |
6515 | ||
6516 | return NULL; | |
6517 | } | |
6518 | ||
c1ca727f ID |
6519 | #define set_power_wells(power_domains, __power_wells) ({ \ |
6520 | (power_domains)->power_wells = (__power_wells); \ | |
6521 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
6522 | }) | |
6523 | ||
da7e29bd | 6524 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
a38911a3 | 6525 | { |
83c00f55 | 6526 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
c1ca727f | 6527 | |
83c00f55 | 6528 | mutex_init(&power_domains->lock); |
a38911a3 | 6529 | |
c1ca727f ID |
6530 | /* |
6531 | * The enabling order will be from lower to higher indexed wells, | |
6532 | * the disabling order is reversed. | |
6533 | */ | |
da7e29bd | 6534 | if (IS_HASWELL(dev_priv->dev)) { |
c1ca727f ID |
6535 | set_power_wells(power_domains, hsw_power_wells); |
6536 | hsw_pwr = power_domains; | |
da7e29bd | 6537 | } else if (IS_BROADWELL(dev_priv->dev)) { |
c1ca727f ID |
6538 | set_power_wells(power_domains, bdw_power_wells); |
6539 | hsw_pwr = power_domains; | |
77961eb9 ID |
6540 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
6541 | set_power_wells(power_domains, vlv_power_wells); | |
c1ca727f | 6542 | } else { |
1c2256df | 6543 | set_power_wells(power_domains, i9xx_always_on_power_well); |
c1ca727f | 6544 | } |
a38911a3 WX |
6545 | |
6546 | return 0; | |
6547 | } | |
6548 | ||
da7e29bd | 6549 | void intel_power_domains_remove(struct drm_i915_private *dev_priv) |
a38911a3 WX |
6550 | { |
6551 | hsw_pwr = NULL; | |
6552 | } | |
6553 | ||
da7e29bd | 6554 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
9cdb826c | 6555 | { |
83c00f55 ID |
6556 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
6557 | struct i915_power_well *power_well; | |
c1ca727f | 6558 | int i; |
9cdb826c | 6559 | |
83c00f55 | 6560 | mutex_lock(&power_domains->lock); |
bfafe93a | 6561 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
a45f4466 | 6562 | power_well->ops->sync_hw(dev_priv, power_well); |
bfafe93a ID |
6563 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, |
6564 | power_well); | |
6565 | } | |
83c00f55 | 6566 | mutex_unlock(&power_domains->lock); |
a38911a3 WX |
6567 | } |
6568 | ||
d2011dc8 VS |
6569 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
6570 | { | |
6571 | struct i915_power_well *cmn = | |
6572 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
6573 | struct i915_power_well *disp2d = | |
6574 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
6575 | ||
6576 | /* nothing to do if common lane is already off */ | |
6577 | if (!cmn->ops->is_enabled(dev_priv, cmn)) | |
6578 | return; | |
6579 | ||
6580 | /* If the display might be already active skip this */ | |
6581 | if (disp2d->ops->is_enabled(dev_priv, disp2d) && | |
6582 | I915_READ(DPIO_CTL) & DPIO_CMNRST) | |
6583 | return; | |
6584 | ||
6585 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
6586 | ||
6587 | /* cmnlane needs DPLL registers */ | |
6588 | disp2d->ops->enable(dev_priv, disp2d); | |
6589 | ||
6590 | /* | |
6591 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
6592 | * Need to assert and de-assert PHY SB reset by gating the | |
6593 | * common lane power, then un-gating it. | |
6594 | * Simply ungating isn't enough to reset the PHY enough to get | |
6595 | * ports and lanes running. | |
6596 | */ | |
6597 | cmn->ops->disable(dev_priv, cmn); | |
6598 | } | |
6599 | ||
da7e29bd | 6600 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
d0d3e513 | 6601 | { |
d2011dc8 | 6602 | struct drm_device *dev = dev_priv->dev; |
0d116a29 ID |
6603 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
6604 | ||
6605 | power_domains->initializing = true; | |
d2011dc8 VS |
6606 | |
6607 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { | |
6608 | mutex_lock(&power_domains->lock); | |
6609 | vlv_cmnlane_wa(dev_priv); | |
6610 | mutex_unlock(&power_domains->lock); | |
6611 | } | |
6612 | ||
fa42e23c | 6613 | /* For now, we need the power well to be always enabled. */ |
da7e29bd ID |
6614 | intel_display_set_init_power(dev_priv, true); |
6615 | intel_power_domains_resume(dev_priv); | |
0d116a29 | 6616 | power_domains->initializing = false; |
d0d3e513 ED |
6617 | } |
6618 | ||
c67a470b PZ |
6619 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
6620 | { | |
d361ae26 | 6621 | intel_runtime_pm_get(dev_priv); |
c67a470b PZ |
6622 | } |
6623 | ||
6624 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) | |
6625 | { | |
d361ae26 | 6626 | intel_runtime_pm_put(dev_priv); |
c67a470b PZ |
6627 | } |
6628 | ||
8a187455 PZ |
6629 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
6630 | { | |
6631 | struct drm_device *dev = dev_priv->dev; | |
6632 | struct device *device = &dev->pdev->dev; | |
6633 | ||
6634 | if (!HAS_RUNTIME_PM(dev)) | |
6635 | return; | |
6636 | ||
6637 | pm_runtime_get_sync(device); | |
6638 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
6639 | } | |
6640 | ||
c6df39b5 ID |
6641 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
6642 | { | |
6643 | struct drm_device *dev = dev_priv->dev; | |
6644 | struct device *device = &dev->pdev->dev; | |
6645 | ||
6646 | if (!HAS_RUNTIME_PM(dev)) | |
6647 | return; | |
6648 | ||
6649 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); | |
6650 | pm_runtime_get_noresume(device); | |
6651 | } | |
6652 | ||
8a187455 PZ |
6653 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
6654 | { | |
6655 | struct drm_device *dev = dev_priv->dev; | |
6656 | struct device *device = &dev->pdev->dev; | |
6657 | ||
6658 | if (!HAS_RUNTIME_PM(dev)) | |
6659 | return; | |
6660 | ||
6661 | pm_runtime_mark_last_busy(device); | |
6662 | pm_runtime_put_autosuspend(device); | |
6663 | } | |
6664 | ||
6665 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv) | |
6666 | { | |
6667 | struct drm_device *dev = dev_priv->dev; | |
6668 | struct device *device = &dev->pdev->dev; | |
6669 | ||
8a187455 PZ |
6670 | if (!HAS_RUNTIME_PM(dev)) |
6671 | return; | |
6672 | ||
6673 | pm_runtime_set_active(device); | |
6674 | ||
aeab0b5a ID |
6675 | /* |
6676 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
6677 | * requirement. | |
6678 | */ | |
6679 | if (!intel_enable_rc6(dev)) { | |
6680 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
6681 | return; | |
6682 | } | |
6683 | ||
8a187455 PZ |
6684 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
6685 | pm_runtime_mark_last_busy(device); | |
6686 | pm_runtime_use_autosuspend(device); | |
ba0239e0 PZ |
6687 | |
6688 | pm_runtime_put_autosuspend(device); | |
8a187455 PZ |
6689 | } |
6690 | ||
6691 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) | |
6692 | { | |
6693 | struct drm_device *dev = dev_priv->dev; | |
6694 | struct device *device = &dev->pdev->dev; | |
6695 | ||
6696 | if (!HAS_RUNTIME_PM(dev)) | |
6697 | return; | |
6698 | ||
aeab0b5a ID |
6699 | if (!intel_enable_rc6(dev)) |
6700 | return; | |
6701 | ||
8a187455 PZ |
6702 | /* Make sure we're not suspended first. */ |
6703 | pm_runtime_get_sync(device); | |
6704 | pm_runtime_disable(device); | |
6705 | } | |
6706 | ||
1fa61106 ED |
6707 | /* Set up chip specific power management-related functions */ |
6708 | void intel_init_pm(struct drm_device *dev) | |
6709 | { | |
6710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6711 | ||
3a77c4c4 | 6712 | if (HAS_FBC(dev)) { |
40045465 | 6713 | if (INTEL_INFO(dev)->gen >= 7) { |
1fa61106 | 6714 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
40045465 VS |
6715 | dev_priv->display.enable_fbc = gen7_enable_fbc; |
6716 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
6717 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
6718 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
6719 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
1fa61106 ED |
6720 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
6721 | } else if (IS_GM45(dev)) { | |
6722 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
6723 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
6724 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
40045465 | 6725 | } else { |
1fa61106 ED |
6726 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
6727 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
6728 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
993495ae VS |
6729 | |
6730 | /* This value was pulled out of someone's hat */ | |
6731 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
1fa61106 | 6732 | } |
1fa61106 ED |
6733 | } |
6734 | ||
c921aba8 DV |
6735 | /* For cxsr */ |
6736 | if (IS_PINEVIEW(dev)) | |
6737 | i915_pineview_get_mem_freq(dev); | |
6738 | else if (IS_GEN5(dev)) | |
6739 | i915_ironlake_get_mem_freq(dev); | |
6740 | ||
1fa61106 ED |
6741 | /* For FIFO watermark updates */ |
6742 | if (HAS_PCH_SPLIT(dev)) { | |
fa50ad61 | 6743 | ilk_setup_wm_latency(dev); |
53615a5e | 6744 | |
bd602544 VS |
6745 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
6746 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
6747 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
6748 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6749 | dev_priv->display.update_wm = ilk_update_wm; | |
6750 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
6751 | } else { | |
6752 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6753 | "Disable CxSR\n"); | |
6754 | } | |
6755 | ||
6756 | if (IS_GEN5(dev)) | |
1fa61106 | 6757 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 6758 | else if (IS_GEN6(dev)) |
1fa61106 | 6759 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 6760 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 6761 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 6762 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 6763 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 6764 | else if (INTEL_INFO(dev)->gen == 8) |
1020a5c2 | 6765 | dev_priv->display.init_clock_gating = gen8_init_clock_gating; |
a4565da8 VS |
6766 | } else if (IS_CHERRYVIEW(dev)) { |
6767 | dev_priv->display.update_wm = valleyview_update_wm; | |
6768 | dev_priv->display.init_clock_gating = | |
6769 | cherryview_init_clock_gating; | |
1fa61106 ED |
6770 | } else if (IS_VALLEYVIEW(dev)) { |
6771 | dev_priv->display.update_wm = valleyview_update_wm; | |
6772 | dev_priv->display.init_clock_gating = | |
6773 | valleyview_init_clock_gating; | |
1fa61106 ED |
6774 | } else if (IS_PINEVIEW(dev)) { |
6775 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6776 | dev_priv->is_ddr3, | |
6777 | dev_priv->fsb_freq, | |
6778 | dev_priv->mem_freq)) { | |
6779 | DRM_INFO("failed to find known CxSR latency " | |
6780 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6781 | "disabling CxSR\n", | |
6782 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6783 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6784 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 6785 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
6786 | dev_priv->display.update_wm = NULL; |
6787 | } else | |
6788 | dev_priv->display.update_wm = pineview_update_wm; | |
6789 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6790 | } else if (IS_G4X(dev)) { | |
6791 | dev_priv->display.update_wm = g4x_update_wm; | |
6792 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6793 | } else if (IS_GEN4(dev)) { | |
6794 | dev_priv->display.update_wm = i965_update_wm; | |
6795 | if (IS_CRESTLINE(dev)) | |
6796 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
6797 | else if (IS_BROADWATER(dev)) | |
6798 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
6799 | } else if (IS_GEN3(dev)) { | |
6800 | dev_priv->display.update_wm = i9xx_update_wm; | |
6801 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6802 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
6803 | } else if (IS_GEN2(dev)) { |
6804 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
6805 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 6806 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
6807 | } else { |
6808 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 6809 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
6810 | } |
6811 | ||
6812 | if (IS_I85X(dev) || IS_I865G(dev)) | |
6813 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
6814 | else | |
6815 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
6816 | } else { | |
6817 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
6818 | } |
6819 | } | |
6820 | ||
42c0526c BW |
6821 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
6822 | { | |
4fc688ce | 6823 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6824 | |
6825 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6826 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
6827 | return -EAGAIN; | |
6828 | } | |
6829 | ||
6830 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
6831 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6832 | ||
6833 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6834 | 500)) { | |
6835 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
6836 | return -ETIMEDOUT; | |
6837 | } | |
6838 | ||
6839 | *val = I915_READ(GEN6_PCODE_DATA); | |
6840 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6841 | ||
6842 | return 0; | |
6843 | } | |
6844 | ||
6845 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) | |
6846 | { | |
4fc688ce | 6847 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6848 | |
6849 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6850 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
6851 | return -EAGAIN; | |
6852 | } | |
6853 | ||
6854 | I915_WRITE(GEN6_PCODE_DATA, val); | |
6855 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6856 | ||
6857 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6858 | 500)) { | |
6859 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
6860 | return -ETIMEDOUT; | |
6861 | } | |
6862 | ||
6863 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6864 | ||
6865 | return 0; | |
6866 | } | |
a0e4e199 | 6867 | |
2ec3815f | 6868 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
855ba3be | 6869 | { |
07ab118b | 6870 | int div; |
855ba3be | 6871 | |
07ab118b | 6872 | /* 4 x czclk */ |
2ec3815f | 6873 | switch (dev_priv->mem_freq) { |
855ba3be | 6874 | case 800: |
07ab118b | 6875 | div = 10; |
855ba3be JB |
6876 | break; |
6877 | case 1066: | |
07ab118b | 6878 | div = 12; |
855ba3be JB |
6879 | break; |
6880 | case 1333: | |
07ab118b | 6881 | div = 16; |
855ba3be JB |
6882 | break; |
6883 | default: | |
6884 | return -1; | |
6885 | } | |
6886 | ||
2ec3815f | 6887 | return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); |
855ba3be JB |
6888 | } |
6889 | ||
2ec3815f | 6890 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 6891 | { |
07ab118b | 6892 | int mul; |
855ba3be | 6893 | |
07ab118b | 6894 | /* 4 x czclk */ |
2ec3815f | 6895 | switch (dev_priv->mem_freq) { |
855ba3be | 6896 | case 800: |
07ab118b | 6897 | mul = 10; |
855ba3be JB |
6898 | break; |
6899 | case 1066: | |
07ab118b | 6900 | mul = 12; |
855ba3be JB |
6901 | break; |
6902 | case 1333: | |
07ab118b | 6903 | mul = 16; |
855ba3be JB |
6904 | break; |
6905 | default: | |
6906 | return -1; | |
6907 | } | |
6908 | ||
2ec3815f | 6909 | return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; |
855ba3be JB |
6910 | } |
6911 | ||
f742a552 | 6912 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
6913 | { |
6914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6915 | ||
f742a552 DV |
6916 | mutex_init(&dev_priv->rps.hw_lock); |
6917 | ||
907b28c5 CW |
6918 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
6919 | intel_gen6_powersave_work); | |
5d584b2e | 6920 | |
33688d95 | 6921 | dev_priv->pm.suspended = false; |
5d584b2e | 6922 | dev_priv->pm.irqs_disabled = false; |
907b28c5 | 6923 | } |