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drm/i915: disable cpt phase pointer fdi rx workaround
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
1fa61106 47static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 48{
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 u32 fbc_ctl;
51
52 /* Disable compression */
53 fbc_ctl = I915_READ(FBC_CONTROL);
54 if ((fbc_ctl & FBC_CTL_EN) == 0)
55 return;
56
57 fbc_ctl &= ~FBC_CTL_EN;
58 I915_WRITE(FBC_CONTROL, fbc_ctl);
59
60 /* Wait for compressing bit to clear */
61 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
62 DRM_DEBUG_KMS("FBC idle timed out\n");
63 return;
64 }
65
66 DRM_DEBUG_KMS("disabled FBC\n");
67}
68
1fa61106 69static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 70{
71 struct drm_device *dev = crtc->dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
73 struct drm_framebuffer *fb = crtc->fb;
74 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
75 struct drm_i915_gem_object *obj = intel_fb->obj;
76 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
77 int cfb_pitch;
78 int plane, i;
79 u32 fbc_ctl, fbc_ctl2;
80
81 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
82 if (fb->pitches[0] < cfb_pitch)
83 cfb_pitch = fb->pitches[0];
84
85 /* FBC_CTL wants 64B units */
86 cfb_pitch = (cfb_pitch / 64) - 1;
87 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
88
89 /* Clear old tags */
90 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
91 I915_WRITE(FBC_TAG + (i * 4), 0);
92
93 /* Set it up... */
94 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
95 fbc_ctl2 |= plane;
96 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
97 I915_WRITE(FBC_FENCE_OFF, crtc->y);
98
99 /* enable it... */
100 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
101 if (IS_I945GM(dev))
102 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
103 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
104 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
105 fbc_ctl |= obj->fence_reg;
106 I915_WRITE(FBC_CONTROL, fbc_ctl);
107
108 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
109 cfb_pitch, crtc->y, intel_crtc->plane);
110}
111
1fa61106 112static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 113{
114 struct drm_i915_private *dev_priv = dev->dev_private;
115
116 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
117}
118
1fa61106 119static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 120{
121 struct drm_device *dev = crtc->dev;
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct drm_framebuffer *fb = crtc->fb;
124 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
125 struct drm_i915_gem_object *obj = intel_fb->obj;
126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
127 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
128 unsigned long stall_watermark = 200;
129 u32 dpfc_ctl;
130
131 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
132 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
133 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
134
135 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
136 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
137 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
138 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
139
140 /* enable it... */
141 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
142
143 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
144}
145
1fa61106 146static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 147{
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 u32 dpfc_ctl;
150
151 /* Disable compression */
152 dpfc_ctl = I915_READ(DPFC_CONTROL);
153 if (dpfc_ctl & DPFC_CTL_EN) {
154 dpfc_ctl &= ~DPFC_CTL_EN;
155 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
156
157 DRM_DEBUG_KMS("disabled FBC\n");
158 }
159}
160
1fa61106 161static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
166}
167
168static void sandybridge_blit_fbc_update(struct drm_device *dev)
169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171 u32 blt_ecoskpd;
172
173 /* Make sure blitter notifies FBC of writes */
174 gen6_gt_force_wake_get(dev_priv);
175 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
176 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
177 GEN6_BLITTER_LOCK_SHIFT;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
179 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
180 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
181 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
182 GEN6_BLITTER_LOCK_SHIFT);
183 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
184 POSTING_READ(GEN6_BLITTER_ECOSKPD);
185 gen6_gt_force_wake_put(dev_priv);
186}
187
1fa61106 188static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 189{
190 struct drm_device *dev = crtc->dev;
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct drm_framebuffer *fb = crtc->fb;
193 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
194 struct drm_i915_gem_object *obj = intel_fb->obj;
195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
196 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
197 unsigned long stall_watermark = 200;
198 u32 dpfc_ctl;
199
200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
201 dpfc_ctl &= DPFC_RESERVED;
202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
203 /* Set persistent mode for front-buffer rendering, ala X. */
204 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
205 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
206 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
207
208 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
209 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
210 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
211 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
212 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
213 /* enable it... */
214 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
215
216 if (IS_GEN6(dev)) {
217 I915_WRITE(SNB_DPFC_CTL_SA,
218 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
219 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
220 sandybridge_blit_fbc_update(dev);
221 }
222
223 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
224}
225
1fa61106 226static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 227{
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 u32 dpfc_ctl;
230
231 /* Disable compression */
232 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
233 if (dpfc_ctl & DPFC_CTL_EN) {
234 dpfc_ctl &= ~DPFC_CTL_EN;
235 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
236
237 DRM_DEBUG_KMS("disabled FBC\n");
238 }
239}
240
1fa61106 241static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 242{
243 struct drm_i915_private *dev_priv = dev->dev_private;
244
245 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
246}
247
248bool intel_fbc_enabled(struct drm_device *dev)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251
252 if (!dev_priv->display.fbc_enabled)
253 return false;
254
255 return dev_priv->display.fbc_enabled(dev);
256}
257
258static void intel_fbc_work_fn(struct work_struct *__work)
259{
260 struct intel_fbc_work *work =
261 container_of(to_delayed_work(__work),
262 struct intel_fbc_work, work);
263 struct drm_device *dev = work->crtc->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private;
265
266 mutex_lock(&dev->struct_mutex);
267 if (work == dev_priv->fbc_work) {
268 /* Double check that we haven't switched fb without cancelling
269 * the prior work.
270 */
271 if (work->crtc->fb == work->fb) {
272 dev_priv->display.enable_fbc(work->crtc,
273 work->interval);
274
275 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
276 dev_priv->cfb_fb = work->crtc->fb->base.id;
277 dev_priv->cfb_y = work->crtc->y;
278 }
279
280 dev_priv->fbc_work = NULL;
281 }
282 mutex_unlock(&dev->struct_mutex);
283
284 kfree(work);
285}
286
287static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
288{
289 if (dev_priv->fbc_work == NULL)
290 return;
291
292 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
293
294 /* Synchronisation is provided by struct_mutex and checking of
295 * dev_priv->fbc_work, so we can perform the cancellation
296 * entirely asynchronously.
297 */
298 if (cancel_delayed_work(&dev_priv->fbc_work->work))
299 /* tasklet was killed before being run, clean up */
300 kfree(dev_priv->fbc_work);
301
302 /* Mark the work as no longer wanted so that if it does
303 * wake-up (because the work was already running and waiting
304 * for our mutex), it will discover that is no longer
305 * necessary to run.
306 */
307 dev_priv->fbc_work = NULL;
308}
309
310void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
311{
312 struct intel_fbc_work *work;
313 struct drm_device *dev = crtc->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 if (!dev_priv->display.enable_fbc)
317 return;
318
319 intel_cancel_fbc_work(dev_priv);
320
321 work = kzalloc(sizeof *work, GFP_KERNEL);
322 if (work == NULL) {
323 dev_priv->display.enable_fbc(crtc, interval);
324 return;
325 }
326
327 work->crtc = crtc;
328 work->fb = crtc->fb;
329 work->interval = interval;
330 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
331
332 dev_priv->fbc_work = work;
333
334 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
335
336 /* Delay the actual enabling to let pageflipping cease and the
337 * display to settle before starting the compression. Note that
338 * this delay also serves a second purpose: it allows for a
339 * vblank to pass after disabling the FBC before we attempt
340 * to modify the control registers.
341 *
342 * A more complicated solution would involve tracking vblanks
343 * following the termination of the page-flipping sequence
344 * and indeed performing the enable as a co-routine and not
345 * waiting synchronously upon the vblank.
346 */
347 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
348}
349
350void intel_disable_fbc(struct drm_device *dev)
351{
352 struct drm_i915_private *dev_priv = dev->dev_private;
353
354 intel_cancel_fbc_work(dev_priv);
355
356 if (!dev_priv->display.disable_fbc)
357 return;
358
359 dev_priv->display.disable_fbc(dev);
360 dev_priv->cfb_plane = -1;
361}
362
363/**
364 * intel_update_fbc - enable/disable FBC as needed
365 * @dev: the drm_device
366 *
367 * Set up the framebuffer compression hardware at mode set time. We
368 * enable it if possible:
369 * - plane A only (on pre-965)
370 * - no pixel mulitply/line duplication
371 * - no alpha buffer discard
372 * - no dual wide
373 * - framebuffer <= 2048 in width, 1536 in height
374 *
375 * We can't assume that any compression will take place (worst case),
376 * so the compressed buffer has to be the same size as the uncompressed
377 * one. It also must reside (along with the line length buffer) in
378 * stolen memory.
379 *
380 * We need to enable/disable FBC on a global basis.
381 */
382void intel_update_fbc(struct drm_device *dev)
383{
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 struct drm_crtc *crtc = NULL, *tmp_crtc;
386 struct intel_crtc *intel_crtc;
387 struct drm_framebuffer *fb;
388 struct intel_framebuffer *intel_fb;
389 struct drm_i915_gem_object *obj;
390 int enable_fbc;
391
85208be0
ED		 392 if (!i915_powersave)
393 return;
394
395 if (!I915_HAS_FBC(dev))
396 return;
397
398 /*
399 * If FBC is already on, we just have to verify that we can
400 * keep it that way...
401 * Need to disable if:
402 * - more than one pipe is active
403 * - changing FBC params (stride, fence, mode)
404 * - new fb is too large to fit in compressed buffer
405 * - going to an unsupported config (interlace, pixel multiply, etc.)
406 */
407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
93314b5b
CW		 408 if (tmp_crtc->enabled &&
409 !to_intel_crtc(tmp_crtc)->primary_disabled &&
410 tmp_crtc->fb) {
85208be0
ED		 411 if (crtc) {
412 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
413 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
414 goto out_disable;
415 }
416 crtc = tmp_crtc;
417 }
418 }
419
420 if (!crtc || crtc->fb == NULL) {
421 DRM_DEBUG_KMS("no output, disabling\n");
422 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
423 goto out_disable;
424 }
425
426 intel_crtc = to_intel_crtc(crtc);
427 fb = crtc->fb;
428 intel_fb = to_intel_framebuffer(fb);
429 obj = intel_fb->obj;
430
431 enable_fbc = i915_enable_fbc;
432 if (enable_fbc < 0) {
433 DRM_DEBUG_KMS("fbc set to per-chip default\n");
434 enable_fbc = 1;
435 if (INTEL_INFO(dev)->gen <= 6)
436 enable_fbc = 0;
437 }
438 if (!enable_fbc) {
439 DRM_DEBUG_KMS("fbc disabled per module param\n");
440 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
441 goto out_disable;
442 }
443 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
444 DRM_DEBUG_KMS("framebuffer too large, disabling "
445 "compression\n");
446 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
447 goto out_disable;
448 }
449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
451 DRM_DEBUG_KMS("mode incompatible with compression, "
452 "disabling\n");
453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
454 goto out_disable;
455 }
456 if ((crtc->mode.hdisplay > 2048) ||
457 (crtc->mode.vdisplay > 1536)) {
458 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
460 goto out_disable;
461 }
462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
463 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
464 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
465 goto out_disable;
466 }
467
468 /* The use of a CPU fence is mandatory in order to detect writes
469 * by the CPU to the scanout and trigger updates to the FBC.
470 */
471 if (obj->tiling_mode != I915_TILING_X ||
472 obj->fence_reg == I915_FENCE_REG_NONE) {
473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
474 dev_priv->no_fbc_reason = FBC_NOT_TILED;
475 goto out_disable;
476 }
477
478 /* If the kernel debugger is active, always disable compression */
479 if (in_dbg_master())
480 goto out_disable;
481
482 /* If the scanout has not changed, don't modify the FBC settings.
483 * Note that we make the fundamental assumption that the fb->obj
484 * cannot be unpinned (and have its GTT offset and fence revoked)
485 * without first being decoupled from the scanout and FBC disabled.
486 */
487 if (dev_priv->cfb_plane == intel_crtc->plane &&
488 dev_priv->cfb_fb == fb->base.id &&
489 dev_priv->cfb_y == crtc->y)
490 return;
491
492 if (intel_fbc_enabled(dev)) {
493 /* We update FBC along two paths, after changing fb/crtc
494 * configuration (modeswitching) and after page-flipping
495 * finishes. For the latter, we know that not only did
496 * we disable the FBC at the start of the page-flip
497 * sequence, but also more than one vblank has passed.
498 *
499 * For the former case of modeswitching, it is possible
500 * to switch between two FBC valid configurations
501 * instantaneously so we do need to disable the FBC
502 * before we can modify its control registers. We also
503 * have to wait for the next vblank for that to take
504 * effect. However, since we delay enabling FBC we can
505 * assume that a vblank has passed since disabling and
506 * that we can safely alter the registers in the deferred
507 * callback.
508 *
509 * In the scenario that we go from a valid to invalid
510 * and then back to valid FBC configuration we have
511 * no strict enforcement that a vblank occurred since
512 * disabling the FBC. However, along all current pipe
513 * disabling paths we do need to wait for a vblank at
514 * some point. And we wait before enabling FBC anyway.
515 */
516 DRM_DEBUG_KMS("disabling active FBC for update\n");
517 intel_disable_fbc(dev);
518 }
519
520 intel_enable_fbc(crtc, 500);
521 return;
522
523out_disable:
524 /* Multiple disables should be harmless */
525 if (intel_fbc_enabled(dev)) {
526 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
527 intel_disable_fbc(dev);
528 }
529}
530
c921aba8
DV		 531static void i915_pineview_get_mem_freq(struct drm_device *dev)
532{
533 drm_i915_private_t *dev_priv = dev->dev_private;
534 u32 tmp;
535
536 tmp = I915_READ(CLKCFG);
537
538 switch (tmp & CLKCFG_FSB_MASK) {
539 case CLKCFG_FSB_533:
540 dev_priv->fsb_freq = 533; /* 133*4 */
541 break;
542 case CLKCFG_FSB_800:
543 dev_priv->fsb_freq = 800; /* 200*4 */
544 break;
545 case CLKCFG_FSB_667:
546 dev_priv->fsb_freq = 667; /* 167*4 */
547 break;
548 case CLKCFG_FSB_400:
549 dev_priv->fsb_freq = 400; /* 100*4 */
550 break;
551 }
552
553 switch (tmp & CLKCFG_MEM_MASK) {
554 case CLKCFG_MEM_533:
555 dev_priv->mem_freq = 533;
556 break;
557 case CLKCFG_MEM_667:
558 dev_priv->mem_freq = 667;
559 break;
560 case CLKCFG_MEM_800:
561 dev_priv->mem_freq = 800;
562 break;
563 }
564
565 /* detect pineview DDR3 setting */
566 tmp = I915_READ(CSHRDDR3CTL);
567 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
568}
569
570static void i915_ironlake_get_mem_freq(struct drm_device *dev)
571{
572 drm_i915_private_t *dev_priv = dev->dev_private;
573 u16 ddrpll, csipll;
574
575 ddrpll = I915_READ16(DDRMPLL1);
576 csipll = I915_READ16(CSIPLL0);
577
578 switch (ddrpll & 0xff) {
579 case 0xc:
580 dev_priv->mem_freq = 800;
581 break;
582 case 0x10:
583 dev_priv->mem_freq = 1066;
584 break;
585 case 0x14:
586 dev_priv->mem_freq = 1333;
587 break;
588 case 0x18:
589 dev_priv->mem_freq = 1600;
590 break;
591 default:
592 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
593 ddrpll & 0xff);
594 dev_priv->mem_freq = 0;
595 break;
596 }
597
20e4d407 598 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 599
600 switch (csipll & 0x3ff) {
601 case 0x00c:
602 dev_priv->fsb_freq = 3200;
603 break;
604 case 0x00e:
605 dev_priv->fsb_freq = 3733;
606 break;
607 case 0x010:
608 dev_priv->fsb_freq = 4266;
609 break;
610 case 0x012:
611 dev_priv->fsb_freq = 4800;
612 break;
613 case 0x014:
614 dev_priv->fsb_freq = 5333;
615 break;
616 case 0x016:
617 dev_priv->fsb_freq = 5866;
618 break;
619 case 0x018:
620 dev_priv->fsb_freq = 6400;
621 break;
622 default:
623 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
624 csipll & 0x3ff);
625 dev_priv->fsb_freq = 0;
626 break;
627 }
628
629 if (dev_priv->fsb_freq == 3200) {
20e4d407 630 dev_priv->ips.c_m = 0;
c921aba8 631 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 632 dev_priv->ips.c_m = 1;
c921aba8 633 } else {
20e4d407 634 dev_priv->ips.c_m = 2;
c921aba8
DV		 635 }
636}
637
b445e3b0
ED		 638static const struct cxsr_latency cxsr_latency_table[] = {
639 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
640 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
641 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
642 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
643 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
644
645 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
646 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
647 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
648 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
649 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
650
651 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
652 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
653 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
654 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
655 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
656
657 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
658 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
659 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
660 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
661 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
662
663 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
664 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
665 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
666 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
667 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
668
669 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
670 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
671 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
672 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
673 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
674};
675
63c62275 676static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 677 int is_ddr3,
678 int fsb,
679 int mem)
680{
681 const struct cxsr_latency *latency;
682 int i;
683
684 if (fsb == 0 || mem == 0)
685 return NULL;
686
687 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
688 latency = &cxsr_latency_table[i];
689 if (is_desktop == latency->is_desktop &&
690 is_ddr3 == latency->is_ddr3 &&
691 fsb == latency->fsb_freq && mem == latency->mem_freq)
692 return latency;
693 }
694
695 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
696
697 return NULL;
698}
699
1fa61106 700static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 701{
702 struct drm_i915_private *dev_priv = dev->dev_private;
703
704 /* deactivate cxsr */
705 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
706}
707
708/*
709 * Latency for FIFO fetches is dependent on several factors:
710 * - memory configuration (speed, channels)
711 * - chipset
712 * - current MCH state
713 * It can be fairly high in some situations, so here we assume a fairly
714 * pessimal value. It's a tradeoff between extra memory fetches (if we
715 * set this value too high, the FIFO will fetch frequently to stay full)
716 * and power consumption (set it too low to save power and we might see
717 * FIFO underruns and display "flicker").
718 *
719 * A value of 5us seems to be a good balance; safe for very low end
720 * platforms but not overly aggressive on lower latency configs.
721 */
722static const int latency_ns = 5000;
723
1fa61106 724static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 725{
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t dsparb = I915_READ(DSPARB);
728 int size;
729
730 size = dsparb & 0x7f;
731 if (plane)
732 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
733
734 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
735 plane ? "B" : "A", size);
736
737 return size;
738}
739
1fa61106 740static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 741{
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 uint32_t dsparb = I915_READ(DSPARB);
744 int size;
745
746 size = dsparb & 0x1ff;
747 if (plane)
748 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
749 size >>= 1; /* Convert to cachelines */
750
751 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
752 plane ? "B" : "A", size);
753
754 return size;
755}
756
1fa61106 757static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 uint32_t dsparb = I915_READ(DSPARB);
761 int size;
762
763 size = dsparb & 0x7f;
764 size >>= 2; /* Convert to cachelines */
765
766 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
767 plane ? "B" : "A",
768 size);
769
770 return size;
771}
772
1fa61106 773static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 774{
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 uint32_t dsparb = I915_READ(DSPARB);
777 int size;
778
779 size = dsparb & 0x7f;
780 size >>= 1; /* Convert to cachelines */
781
782 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
783 plane ? "B" : "A", size);
784
785 return size;
786}
787
788/* Pineview has different values for various configs */
789static const struct intel_watermark_params pineview_display_wm = {
790 PINEVIEW_DISPLAY_FIFO,
791 PINEVIEW_MAX_WM,
792 PINEVIEW_DFT_WM,
793 PINEVIEW_GUARD_WM,
794 PINEVIEW_FIFO_LINE_SIZE
795};
796static const struct intel_watermark_params pineview_display_hplloff_wm = {
797 PINEVIEW_DISPLAY_FIFO,
798 PINEVIEW_MAX_WM,
799 PINEVIEW_DFT_HPLLOFF_WM,
800 PINEVIEW_GUARD_WM,
801 PINEVIEW_FIFO_LINE_SIZE
802};
803static const struct intel_watermark_params pineview_cursor_wm = {
804 PINEVIEW_CURSOR_FIFO,
805 PINEVIEW_CURSOR_MAX_WM,
806 PINEVIEW_CURSOR_DFT_WM,
807 PINEVIEW_CURSOR_GUARD_WM,
808 PINEVIEW_FIFO_LINE_SIZE,
809};
810static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
811 PINEVIEW_CURSOR_FIFO,
812 PINEVIEW_CURSOR_MAX_WM,
813 PINEVIEW_CURSOR_DFT_WM,
814 PINEVIEW_CURSOR_GUARD_WM,
815 PINEVIEW_FIFO_LINE_SIZE
816};
817static const struct intel_watermark_params g4x_wm_info = {
818 G4X_FIFO_SIZE,
819 G4X_MAX_WM,
820 G4X_MAX_WM,
821 2,
822 G4X_FIFO_LINE_SIZE,
823};
824static const struct intel_watermark_params g4x_cursor_wm_info = {
825 I965_CURSOR_FIFO,
826 I965_CURSOR_MAX_WM,
827 I965_CURSOR_DFT_WM,
828 2,
829 G4X_FIFO_LINE_SIZE,
830};
831static const struct intel_watermark_params valleyview_wm_info = {
832 VALLEYVIEW_FIFO_SIZE,
833 VALLEYVIEW_MAX_WM,
834 VALLEYVIEW_MAX_WM,
835 2,
836 G4X_FIFO_LINE_SIZE,
837};
838static const struct intel_watermark_params valleyview_cursor_wm_info = {
839 I965_CURSOR_FIFO,
840 VALLEYVIEW_CURSOR_MAX_WM,
841 I965_CURSOR_DFT_WM,
842 2,
843 G4X_FIFO_LINE_SIZE,
844};
845static const struct intel_watermark_params i965_cursor_wm_info = {
846 I965_CURSOR_FIFO,
847 I965_CURSOR_MAX_WM,
848 I965_CURSOR_DFT_WM,
849 2,
850 I915_FIFO_LINE_SIZE,
851};
852static const struct intel_watermark_params i945_wm_info = {
853 I945_FIFO_SIZE,
854 I915_MAX_WM,
855 1,
856 2,
857 I915_FIFO_LINE_SIZE
858};
859static const struct intel_watermark_params i915_wm_info = {
860 I915_FIFO_SIZE,
861 I915_MAX_WM,
862 1,
863 2,
864 I915_FIFO_LINE_SIZE
865};
866static const struct intel_watermark_params i855_wm_info = {
867 I855GM_FIFO_SIZE,
868 I915_MAX_WM,
869 1,
870 2,
871 I830_FIFO_LINE_SIZE
872};
873static const struct intel_watermark_params i830_wm_info = {
874 I830_FIFO_SIZE,
875 I915_MAX_WM,
876 1,
877 2,
878 I830_FIFO_LINE_SIZE
879};
880
881static const struct intel_watermark_params ironlake_display_wm_info = {
882 ILK_DISPLAY_FIFO,
883 ILK_DISPLAY_MAXWM,
884 ILK_DISPLAY_DFTWM,
885 2,
886 ILK_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params ironlake_cursor_wm_info = {
889 ILK_CURSOR_FIFO,
890 ILK_CURSOR_MAXWM,
891 ILK_CURSOR_DFTWM,
892 2,
893 ILK_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params ironlake_display_srwm_info = {
896 ILK_DISPLAY_SR_FIFO,
897 ILK_DISPLAY_MAX_SRWM,
898 ILK_DISPLAY_DFT_SRWM,
899 2,
900 ILK_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params ironlake_cursor_srwm_info = {
903 ILK_CURSOR_SR_FIFO,
904 ILK_CURSOR_MAX_SRWM,
905 ILK_CURSOR_DFT_SRWM,
906 2,
907 ILK_FIFO_LINE_SIZE
908};
909
910static const struct intel_watermark_params sandybridge_display_wm_info = {
911 SNB_DISPLAY_FIFO,
912 SNB_DISPLAY_MAXWM,
913 SNB_DISPLAY_DFTWM,
914 2,
915 SNB_FIFO_LINE_SIZE
916};
917static const struct intel_watermark_params sandybridge_cursor_wm_info = {
918 SNB_CURSOR_FIFO,
919 SNB_CURSOR_MAXWM,
920 SNB_CURSOR_DFTWM,
921 2,
922 SNB_FIFO_LINE_SIZE
923};
924static const struct intel_watermark_params sandybridge_display_srwm_info = {
925 SNB_DISPLAY_SR_FIFO,
926 SNB_DISPLAY_MAX_SRWM,
927 SNB_DISPLAY_DFT_SRWM,
928 2,
929 SNB_FIFO_LINE_SIZE
930};
931static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
932 SNB_CURSOR_SR_FIFO,
933 SNB_CURSOR_MAX_SRWM,
934 SNB_CURSOR_DFT_SRWM,
935 2,
936 SNB_FIFO_LINE_SIZE
937};
938
939
940/**
941 * intel_calculate_wm - calculate watermark level
942 * @clock_in_khz: pixel clock
943 * @wm: chip FIFO params
944 * @pixel_size: display pixel size
945 * @latency_ns: memory latency for the platform
946 *
947 * Calculate the watermark level (the level at which the display plane will
948 * start fetching from memory again). Each chip has a different display
949 * FIFO size and allocation, so the caller needs to figure that out and pass
950 * in the correct intel_watermark_params structure.
951 *
952 * As the pixel clock runs, the FIFO will be drained at a rate that depends
953 * on the pixel size. When it reaches the watermark level, it'll start
954 * fetching FIFO line sized based chunks from memory until the FIFO fills
955 * past the watermark point. If the FIFO drains completely, a FIFO underrun
956 * will occur, and a display engine hang could result.
957 */
958static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
959 const struct intel_watermark_params *wm,
960 int fifo_size,
961 int pixel_size,
962 unsigned long latency_ns)
963{
964 long entries_required, wm_size;
965
966 /*
967 * Note: we need to make sure we don't overflow for various clock &
968 * latency values.
969 * clocks go from a few thousand to several hundred thousand.
970 * latency is usually a few thousand
971 */
972 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
973 1000;
974 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
975
976 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
977
978 wm_size = fifo_size - (entries_required + wm->guard_size);
979
980 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
981
982 /* Don't promote wm_size to unsigned... */
983 if (wm_size > (long)wm->max_wm)
984 wm_size = wm->max_wm;
985 if (wm_size <= 0)
986 wm_size = wm->default_wm;
987 return wm_size;
988}
989
990static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
991{
992 struct drm_crtc *crtc, *enabled = NULL;
993
994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
995 if (crtc->enabled && crtc->fb) {
996 if (enabled)
997 return NULL;
998 enabled = crtc;
999 }
1000 }
1001
1002 return enabled;
1003}
1004
1fa61106 1005static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1006{
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 struct drm_crtc *crtc;
1009 const struct cxsr_latency *latency;
1010 u32 reg;
1011 unsigned long wm;
1012
1013 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014 dev_priv->fsb_freq, dev_priv->mem_freq);
1015 if (!latency) {
1016 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017 pineview_disable_cxsr(dev);
1018 return;
1019 }
1020
1021 crtc = single_enabled_crtc(dev);
1022 if (crtc) {
1023 int clock = crtc->mode.clock;
1024 int pixel_size = crtc->fb->bits_per_pixel / 8;
1025
1026 /* Display SR */
1027 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028 pineview_display_wm.fifo_size,
1029 pixel_size, latency->display_sr);
1030 reg = I915_READ(DSPFW1);
1031 reg &= ~DSPFW_SR_MASK;
1032 reg |= wm << DSPFW_SR_SHIFT;
1033 I915_WRITE(DSPFW1, reg);
1034 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1035
1036 /* cursor SR */
1037 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038 pineview_display_wm.fifo_size,
1039 pixel_size, latency->cursor_sr);
1040 reg = I915_READ(DSPFW3);
1041 reg &= ~DSPFW_CURSOR_SR_MASK;
1042 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043 I915_WRITE(DSPFW3, reg);
1044
1045 /* Display HPLL off SR */
1046 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047 pineview_display_hplloff_wm.fifo_size,
1048 pixel_size, latency->display_hpll_disable);
1049 reg = I915_READ(DSPFW3);
1050 reg &= ~DSPFW_HPLL_SR_MASK;
1051 reg |= wm & DSPFW_HPLL_SR_MASK;
1052 I915_WRITE(DSPFW3, reg);
1053
1054 /* cursor HPLL off SR */
1055 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056 pineview_display_hplloff_wm.fifo_size,
1057 pixel_size, latency->cursor_hpll_disable);
1058 reg = I915_READ(DSPFW3);
1059 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061 I915_WRITE(DSPFW3, reg);
1062 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1063
1064 /* activate cxsr */
1065 I915_WRITE(DSPFW3,
1066 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1068 } else {
1069 pineview_disable_cxsr(dev);
1070 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1071 }
1072}
1073
1074static bool g4x_compute_wm0(struct drm_device *dev,
1075 int plane,
1076 const struct intel_watermark_params *display,
1077 int display_latency_ns,
1078 const struct intel_watermark_params *cursor,
1079 int cursor_latency_ns,
1080 int *plane_wm,
1081 int *cursor_wm)
1082{
1083 struct drm_crtc *crtc;
1084 int htotal, hdisplay, clock, pixel_size;
1085 int line_time_us, line_count;
1086 int entries, tlb_miss;
1087
1088 crtc = intel_get_crtc_for_plane(dev, plane);
1089 if (crtc->fb == NULL || !crtc->enabled) {
1090 *cursor_wm = cursor->guard_size;
1091 *plane_wm = display->guard_size;
1092 return false;
1093 }
1094
1095 htotal = crtc->mode.htotal;
1096 hdisplay = crtc->mode.hdisplay;
1097 clock = crtc->mode.clock;
1098 pixel_size = crtc->fb->bits_per_pixel / 8;
1099
1100 /* Use the small buffer method to calculate plane watermark */
1101 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1103 if (tlb_miss > 0)
1104 entries += tlb_miss;
1105 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106 *plane_wm = entries + display->guard_size;
1107 if (*plane_wm > (int)display->max_wm)
1108 *plane_wm = display->max_wm;
1109
1110 /* Use the large buffer method to calculate cursor watermark */
1111 line_time_us = ((htotal * 1000) / clock);
1112 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113 entries = line_count * 64 * pixel_size;
1114 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1115 if (tlb_miss > 0)
1116 entries += tlb_miss;
1117 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118 *cursor_wm = entries + cursor->guard_size;
1119 if (*cursor_wm > (int)cursor->max_wm)
1120 *cursor_wm = (int)cursor->max_wm;
1121
1122 return true;
1123}
1124
1125/*
1126 * Check the wm result.
1127 *
1128 * If any calculated watermark values is larger than the maximum value that
1129 * can be programmed into the associated watermark register, that watermark
1130 * must be disabled.
1131 */
1132static bool g4x_check_srwm(struct drm_device *dev,
1133 int display_wm, int cursor_wm,
1134 const struct intel_watermark_params *display,
1135 const struct intel_watermark_params *cursor)
1136{
1137 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138 display_wm, cursor_wm);
1139
1140 if (display_wm > display->max_wm) {
1141 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142 display_wm, display->max_wm);
1143 return false;
1144 }
1145
1146 if (cursor_wm > cursor->max_wm) {
1147 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148 cursor_wm, cursor->max_wm);
1149 return false;
1150 }
1151
1152 if (!(display_wm || cursor_wm)) {
1153 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1154 return false;
1155 }
1156
1157 return true;
1158}
1159
1160static bool g4x_compute_srwm(struct drm_device *dev,
1161 int plane,
1162 int latency_ns,
1163 const struct intel_watermark_params *display,
1164 const struct intel_watermark_params *cursor,
1165 int *display_wm, int *cursor_wm)
1166{
1167 struct drm_crtc *crtc;
1168 int hdisplay, htotal, pixel_size, clock;
1169 unsigned long line_time_us;
1170 int line_count, line_size;
1171 int small, large;
1172 int entries;
1173
1174 if (!latency_ns) {
1175 *display_wm = *cursor_wm = 0;
1176 return false;
1177 }
1178
1179 crtc = intel_get_crtc_for_plane(dev, plane);
1180 hdisplay = crtc->mode.hdisplay;
1181 htotal = crtc->mode.htotal;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 line_time_us = (htotal * 1000) / clock;
1186 line_count = (latency_ns / line_time_us + 1000) / 1000;
1187 line_size = hdisplay * pixel_size;
1188
1189 /* Use the minimum of the small and large buffer method for primary */
1190 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191 large = line_count * line_size;
1192
1193 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194 *display_wm = entries + display->guard_size;
1195
1196 /* calculate the self-refresh watermark for display cursor */
1197 entries = line_count * pixel_size * 64;
1198 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199 *cursor_wm = entries + cursor->guard_size;
1200
1201 return g4x_check_srwm(dev,
1202 *display_wm, *cursor_wm,
1203 display, cursor);
1204}
1205
1206static bool vlv_compute_drain_latency(struct drm_device *dev,
1207 int plane,
1208 int *plane_prec_mult,
1209 int *plane_dl,
1210 int *cursor_prec_mult,
1211 int *cursor_dl)
1212{
1213 struct drm_crtc *crtc;
1214 int clock, pixel_size;
1215 int entries;
1216
1217 crtc = intel_get_crtc_for_plane(dev, plane);
1218 if (crtc->fb == NULL || !crtc->enabled)
1219 return false;
1220
1221 clock = crtc->mode.clock; /* VESA DOT Clock */
1222 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1223
1224 entries = (clock / 1000) * pixel_size;
1225 *plane_prec_mult = (entries > 256) ?
1226 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1228 pixel_size);
1229
1230 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1231 *cursor_prec_mult = (entries > 256) ?
1232 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1234
1235 return true;
1236}
1237
1238/*
1239 * Update drain latency registers of memory arbiter
1240 *
1241 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242 * to be programmed. Each plane has a drain latency multiplier and a drain
1243 * latency value.
1244 */
1245
1246static void vlv_update_drain_latency(struct drm_device *dev)
1247{
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1252 either 16 or 32 */
1253
1254 /* For plane A, Cursor A */
1255 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256 &cursor_prec_mult, &cursora_dl)) {
1257 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1261
1262 I915_WRITE(VLV_DDL1, cursora_prec |
1263 (cursora_dl << DDL_CURSORA_SHIFT) |
1264 planea_prec | planea_dl);
1265 }
1266
1267 /* For plane B, Cursor B */
1268 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269 &cursor_prec_mult, &cursorb_dl)) {
1270 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1274
1275 I915_WRITE(VLV_DDL2, cursorb_prec |
1276 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277 planeb_prec | planeb_dl);
1278 }
1279}
1280
1281#define single_plane_enabled(mask) is_power_of_2(mask)
1282
1fa61106 1283static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1284{
1285 static const int sr_latency_ns = 12000;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288 int plane_sr, cursor_sr;
1289 unsigned int enabled = 0;
1290
1291 vlv_update_drain_latency(dev);
1292
1293 if (g4x_compute_wm0(dev, 0,
1294 &valleyview_wm_info, latency_ns,
1295 &valleyview_cursor_wm_info, latency_ns,
1296 &planea_wm, &cursora_wm))
1297 enabled |= 1;
1298
1299 if (g4x_compute_wm0(dev, 1,
1300 &valleyview_wm_info, latency_ns,
1301 &valleyview_cursor_wm_info, latency_ns,
1302 &planeb_wm, &cursorb_wm))
1303 enabled |= 2;
1304
1305 plane_sr = cursor_sr = 0;
1306 if (single_plane_enabled(enabled) &&
1307 g4x_compute_srwm(dev, ffs(enabled) - 1,
1308 sr_latency_ns,
1309 &valleyview_wm_info,
1310 &valleyview_cursor_wm_info,
1311 &plane_sr, &cursor_sr))
1312 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1313 else
1314 I915_WRITE(FW_BLC_SELF_VLV,
1315 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1316
1317 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1318 planea_wm, cursora_wm,
1319 planeb_wm, cursorb_wm,
1320 plane_sr, cursor_sr);
1321
1322 I915_WRITE(DSPFW1,
1323 (plane_sr << DSPFW_SR_SHIFT) |
1324 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1325 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1326 planea_wm);
1327 I915_WRITE(DSPFW2,
8c919b28 1328 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1329 (cursora_wm << DSPFW_CURSORA_SHIFT));
1330 I915_WRITE(DSPFW3,
8c919b28
CW		 1331 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1332 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1333}
1334
1fa61106 1335static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1336{
1337 static const int sr_latency_ns = 12000;
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1340 int plane_sr, cursor_sr;
1341 unsigned int enabled = 0;
1342
1343 if (g4x_compute_wm0(dev, 0,
1344 &g4x_wm_info, latency_ns,
1345 &g4x_cursor_wm_info, latency_ns,
1346 &planea_wm, &cursora_wm))
1347 enabled |= 1;
1348
1349 if (g4x_compute_wm0(dev, 1,
1350 &g4x_wm_info, latency_ns,
1351 &g4x_cursor_wm_info, latency_ns,
1352 &planeb_wm, &cursorb_wm))
1353 enabled |= 2;
1354
1355 plane_sr = cursor_sr = 0;
1356 if (single_plane_enabled(enabled) &&
1357 g4x_compute_srwm(dev, ffs(enabled) - 1,
1358 sr_latency_ns,
1359 &g4x_wm_info,
1360 &g4x_cursor_wm_info,
1361 &plane_sr, &cursor_sr))
1362 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1363 else
1364 I915_WRITE(FW_BLC_SELF,
1365 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1366
1367 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1368 planea_wm, cursora_wm,
1369 planeb_wm, cursorb_wm,
1370 plane_sr, cursor_sr);
1371
1372 I915_WRITE(DSPFW1,
1373 (plane_sr << DSPFW_SR_SHIFT) |
1374 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1375 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1376 planea_wm);
1377 I915_WRITE(DSPFW2,
8c919b28 1378 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1379 (cursora_wm << DSPFW_CURSORA_SHIFT));
1380 /* HPLL off in SR has some issues on G4x... disable it */
1381 I915_WRITE(DSPFW3,
8c919b28 1382 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1383 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1384}
1385
1fa61106 1386static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1387{
1388 struct drm_i915_private *dev_priv = dev->dev_private;
1389 struct drm_crtc *crtc;
1390 int srwm = 1;
1391 int cursor_sr = 16;
1392
1393 /* Calc sr entries for one plane configs */
1394 crtc = single_enabled_crtc(dev);
1395 if (crtc) {
1396 /* self-refresh has much higher latency */
1397 static const int sr_latency_ns = 12000;
1398 int clock = crtc->mode.clock;
1399 int htotal = crtc->mode.htotal;
1400 int hdisplay = crtc->mode.hdisplay;
1401 int pixel_size = crtc->fb->bits_per_pixel / 8;
1402 unsigned long line_time_us;
1403 int entries;
1404
1405 line_time_us = ((htotal * 1000) / clock);
1406
1407 /* Use ns/us then divide to preserve precision */
1408 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1409 pixel_size * hdisplay;
1410 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1411 srwm = I965_FIFO_SIZE - entries;
1412 if (srwm < 0)
1413 srwm = 1;
1414 srwm &= 0x1ff;
1415 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1416 entries, srwm);
1417
1418 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1419 pixel_size * 64;
1420 entries = DIV_ROUND_UP(entries,
1421 i965_cursor_wm_info.cacheline_size);
1422 cursor_sr = i965_cursor_wm_info.fifo_size -
1423 (entries + i965_cursor_wm_info.guard_size);
1424
1425 if (cursor_sr > i965_cursor_wm_info.max_wm)
1426 cursor_sr = i965_cursor_wm_info.max_wm;
1427
1428 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1429 "cursor %d\n", srwm, cursor_sr);
1430
1431 if (IS_CRESTLINE(dev))
1432 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1433 } else {
1434 /* Turn off self refresh if both pipes are enabled */
1435 if (IS_CRESTLINE(dev))
1436 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1437 & ~FW_BLC_SELF_EN);
1438 }
1439
1440 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1441 srwm);
1442
1443 /* 965 has limitations... */
1444 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1445 (8 << 16) | (8 << 8) | (8 << 0));
1446 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1447 /* update cursor SR watermark */
1448 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1449}
1450
1fa61106 1451static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1452{
1453 struct drm_i915_private *dev_priv = dev->dev_private;
1454 const struct intel_watermark_params *wm_info;
1455 uint32_t fwater_lo;
1456 uint32_t fwater_hi;
1457 int cwm, srwm = 1;
1458 int fifo_size;
1459 int planea_wm, planeb_wm;
1460 struct drm_crtc *crtc, *enabled = NULL;
1461
1462 if (IS_I945GM(dev))
1463 wm_info = &i945_wm_info;
1464 else if (!IS_GEN2(dev))
1465 wm_info = &i915_wm_info;
1466 else
1467 wm_info = &i855_wm_info;
1468
1469 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1470 crtc = intel_get_crtc_for_plane(dev, 0);
1471 if (crtc->enabled && crtc->fb) {
b9e0bda3
CW		 1472 int cpp = crtc->fb->bits_per_pixel / 8;
1473 if (IS_GEN2(dev))
1474 cpp = 4;
1475
b445e3b0 1476 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1477 wm_info, fifo_size, cpp,
b445e3b0
ED		 1478 latency_ns);
1479 enabled = crtc;
1480 } else
1481 planea_wm = fifo_size - wm_info->guard_size;
1482
1483 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1484 crtc = intel_get_crtc_for_plane(dev, 1);
1485 if (crtc->enabled && crtc->fb) {
b9e0bda3
CW		 1486 int cpp = crtc->fb->bits_per_pixel / 8;
1487 if (IS_GEN2(dev))
1488 cpp = 4;
1489
b445e3b0 1490 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1491 wm_info, fifo_size, cpp,
b445e3b0
ED		 1492 latency_ns);
1493 if (enabled == NULL)
1494 enabled = crtc;
1495 else
1496 enabled = NULL;
1497 } else
1498 planeb_wm = fifo_size - wm_info->guard_size;
1499
1500 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1501
1502 /*
1503 * Overlay gets an aggressive default since video jitter is bad.
1504 */
1505 cwm = 2;
1506
1507 /* Play safe and disable self-refresh before adjusting watermarks. */
1508 if (IS_I945G(dev) || IS_I945GM(dev))
1509 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1510 else if (IS_I915GM(dev))
1511 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1512
1513 /* Calc sr entries for one plane configs */
1514 if (HAS_FW_BLC(dev) && enabled) {
1515 /* self-refresh has much higher latency */
1516 static const int sr_latency_ns = 6000;
1517 int clock = enabled->mode.clock;
1518 int htotal = enabled->mode.htotal;
1519 int hdisplay = enabled->mode.hdisplay;
1520 int pixel_size = enabled->fb->bits_per_pixel / 8;
1521 unsigned long line_time_us;
1522 int entries;
1523
1524 line_time_us = (htotal * 1000) / clock;
1525
1526 /* Use ns/us then divide to preserve precision */
1527 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1528 pixel_size * hdisplay;
1529 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1530 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1531 srwm = wm_info->fifo_size - entries;
1532 if (srwm < 0)
1533 srwm = 1;
1534
1535 if (IS_I945G(dev) || IS_I945GM(dev))
1536 I915_WRITE(FW_BLC_SELF,
1537 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1538 else if (IS_I915GM(dev))
1539 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1540 }
1541
1542 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1543 planea_wm, planeb_wm, cwm, srwm);
1544
1545 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1546 fwater_hi = (cwm & 0x1f);
1547
1548 /* Set request length to 8 cachelines per fetch */
1549 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1550 fwater_hi = fwater_hi | (1 << 8);
1551
1552 I915_WRITE(FW_BLC, fwater_lo);
1553 I915_WRITE(FW_BLC2, fwater_hi);
1554
1555 if (HAS_FW_BLC(dev)) {
1556 if (enabled) {
1557 if (IS_I945G(dev) || IS_I945GM(dev))
1558 I915_WRITE(FW_BLC_SELF,
1559 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1560 else if (IS_I915GM(dev))
1561 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1562 DRM_DEBUG_KMS("memory self refresh enabled\n");
1563 } else
1564 DRM_DEBUG_KMS("memory self refresh disabled\n");
1565 }
1566}
1567
1fa61106 1568static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1569{
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1571 struct drm_crtc *crtc;
1572 uint32_t fwater_lo;
1573 int planea_wm;
1574
1575 crtc = single_enabled_crtc(dev);
1576 if (crtc == NULL)
1577 return;
1578
1579 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1580 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1581 4, latency_ns);
b445e3b0
ED		 1582 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1583 fwater_lo |= (3<<8) | planea_wm;
1584
1585 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1586
1587 I915_WRITE(FW_BLC, fwater_lo);
1588}
1589
1590#define ILK_LP0_PLANE_LATENCY 700
1591#define ILK_LP0_CURSOR_LATENCY 1300
1592
1593/*
1594 * Check the wm result.
1595 *
1596 * If any calculated watermark values is larger than the maximum value that
1597 * can be programmed into the associated watermark register, that watermark
1598 * must be disabled.
1599 */
1600static bool ironlake_check_srwm(struct drm_device *dev, int level,
1601 int fbc_wm, int display_wm, int cursor_wm,
1602 const struct intel_watermark_params *display,
1603 const struct intel_watermark_params *cursor)
1604{
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606
1607 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1608 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1609
1610 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1611 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1612 fbc_wm, SNB_FBC_MAX_SRWM, level);
1613
1614 /* fbc has it's own way to disable FBC WM */
1615 I915_WRITE(DISP_ARB_CTL,
1616 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1617 return false;
1618 }
1619
1620 if (display_wm > display->max_wm) {
1621 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1622 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1623 return false;
1624 }
1625
1626 if (cursor_wm > cursor->max_wm) {
1627 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1628 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1629 return false;
1630 }
1631
1632 if (!(fbc_wm || display_wm || cursor_wm)) {
1633 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1634 return false;
1635 }
1636
1637 return true;
1638}
1639
1640/*
1641 * Compute watermark values of WM[1-3],
1642 */
1643static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1644 int latency_ns,
1645 const struct intel_watermark_params *display,
1646 const struct intel_watermark_params *cursor,
1647 int *fbc_wm, int *display_wm, int *cursor_wm)
1648{
1649 struct drm_crtc *crtc;
1650 unsigned long line_time_us;
1651 int hdisplay, htotal, pixel_size, clock;
1652 int line_count, line_size;
1653 int small, large;
1654 int entries;
1655
1656 if (!latency_ns) {
1657 *fbc_wm = *display_wm = *cursor_wm = 0;
1658 return false;
1659 }
1660
1661 crtc = intel_get_crtc_for_plane(dev, plane);
1662 hdisplay = crtc->mode.hdisplay;
1663 htotal = crtc->mode.htotal;
1664 clock = crtc->mode.clock;
1665 pixel_size = crtc->fb->bits_per_pixel / 8;
1666
1667 line_time_us = (htotal * 1000) / clock;
1668 line_count = (latency_ns / line_time_us + 1000) / 1000;
1669 line_size = hdisplay * pixel_size;
1670
1671 /* Use the minimum of the small and large buffer method for primary */
1672 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1673 large = line_count * line_size;
1674
1675 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1676 *display_wm = entries + display->guard_size;
1677
1678 /*
1679 * Spec says:
1680 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1681 */
1682 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1683
1684 /* calculate the self-refresh watermark for display cursor */
1685 entries = line_count * pixel_size * 64;
1686 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1687 *cursor_wm = entries + cursor->guard_size;
1688
1689 return ironlake_check_srwm(dev, level,
1690 *fbc_wm, *display_wm, *cursor_wm,
1691 display, cursor);
1692}
1693
1fa61106 1694static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1695{
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 int fbc_wm, plane_wm, cursor_wm;
1698 unsigned int enabled;
1699
1700 enabled = 0;
1701 if (g4x_compute_wm0(dev, 0,
1702 &ironlake_display_wm_info,
1703 ILK_LP0_PLANE_LATENCY,
1704 &ironlake_cursor_wm_info,
1705 ILK_LP0_CURSOR_LATENCY,
1706 &plane_wm, &cursor_wm)) {
1707 I915_WRITE(WM0_PIPEA_ILK,
1708 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1709 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1710 " plane %d, " "cursor: %d\n",
1711 plane_wm, cursor_wm);
1712 enabled |= 1;
1713 }
1714
1715 if (g4x_compute_wm0(dev, 1,
1716 &ironlake_display_wm_info,
1717 ILK_LP0_PLANE_LATENCY,
1718 &ironlake_cursor_wm_info,
1719 ILK_LP0_CURSOR_LATENCY,
1720 &plane_wm, &cursor_wm)) {
1721 I915_WRITE(WM0_PIPEB_ILK,
1722 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1723 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1724 " plane %d, cursor: %d\n",
1725 plane_wm, cursor_wm);
1726 enabled |= 2;
1727 }
1728
1729 /*
1730 * Calculate and update the self-refresh watermark only when one
1731 * display plane is used.
1732 */
1733 I915_WRITE(WM3_LP_ILK, 0);
1734 I915_WRITE(WM2_LP_ILK, 0);
1735 I915_WRITE(WM1_LP_ILK, 0);
1736
1737 if (!single_plane_enabled(enabled))
1738 return;
1739 enabled = ffs(enabled) - 1;
1740
1741 /* WM1 */
1742 if (!ironlake_compute_srwm(dev, 1, enabled,
1743 ILK_READ_WM1_LATENCY() * 500,
1744 &ironlake_display_srwm_info,
1745 &ironlake_cursor_srwm_info,
1746 &fbc_wm, &plane_wm, &cursor_wm))
1747 return;
1748
1749 I915_WRITE(WM1_LP_ILK,
1750 WM1_LP_SR_EN |
1751 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1752 (fbc_wm << WM1_LP_FBC_SHIFT) |
1753 (plane_wm << WM1_LP_SR_SHIFT) |
1754 cursor_wm);
1755
1756 /* WM2 */
1757 if (!ironlake_compute_srwm(dev, 2, enabled,
1758 ILK_READ_WM2_LATENCY() * 500,
1759 &ironlake_display_srwm_info,
1760 &ironlake_cursor_srwm_info,
1761 &fbc_wm, &plane_wm, &cursor_wm))
1762 return;
1763
1764 I915_WRITE(WM2_LP_ILK,
1765 WM2_LP_EN |
1766 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1767 (fbc_wm << WM1_LP_FBC_SHIFT) |
1768 (plane_wm << WM1_LP_SR_SHIFT) |
1769 cursor_wm);
1770
1771 /*
1772 * WM3 is unsupported on ILK, probably because we don't have latency
1773 * data for that power state
1774 */
1775}
1776
1fa61106 1777static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1778{
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1781 u32 val;
1782 int fbc_wm, plane_wm, cursor_wm;
1783 unsigned int enabled;
1784
1785 enabled = 0;
1786 if (g4x_compute_wm0(dev, 0,
1787 &sandybridge_display_wm_info, latency,
1788 &sandybridge_cursor_wm_info, latency,
1789 &plane_wm, &cursor_wm)) {
1790 val = I915_READ(WM0_PIPEA_ILK);
1791 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1792 I915_WRITE(WM0_PIPEA_ILK, val |
1793 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1794 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1795 " plane %d, " "cursor: %d\n",
1796 plane_wm, cursor_wm);
1797 enabled |= 1;
1798 }
1799
1800 if (g4x_compute_wm0(dev, 1,
1801 &sandybridge_display_wm_info, latency,
1802 &sandybridge_cursor_wm_info, latency,
1803 &plane_wm, &cursor_wm)) {
1804 val = I915_READ(WM0_PIPEB_ILK);
1805 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1806 I915_WRITE(WM0_PIPEB_ILK, val |
1807 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1808 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1809 " plane %d, cursor: %d\n",
1810 plane_wm, cursor_wm);
1811 enabled |= 2;
1812 }
1813
461bc9b5 1814 if ((dev_priv->num_pipe == 3) &&
b445e3b0
ED		 1815 g4x_compute_wm0(dev, 2,
1816 &sandybridge_display_wm_info, latency,
1817 &sandybridge_cursor_wm_info, latency,
1818 &plane_wm, &cursor_wm)) {
1819 val = I915_READ(WM0_PIPEC_IVB);
1820 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1821 I915_WRITE(WM0_PIPEC_IVB, val |
1822 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1823 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1824 " plane %d, cursor: %d\n",
1825 plane_wm, cursor_wm);
1826 enabled |= 3;
1827 }
1828
1829 /*
1830 * Calculate and update the self-refresh watermark only when one
1831 * display plane is used.
1832 *
1833 * SNB support 3 levels of watermark.
1834 *
1835 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1836 * and disabled in the descending order
1837 *
1838 */
1839 I915_WRITE(WM3_LP_ILK, 0);
1840 I915_WRITE(WM2_LP_ILK, 0);
1841 I915_WRITE(WM1_LP_ILK, 0);
1842
1843 if (!single_plane_enabled(enabled) ||
1844 dev_priv->sprite_scaling_enabled)
1845 return;
1846 enabled = ffs(enabled) - 1;
1847
1848 /* WM1 */
1849 if (!ironlake_compute_srwm(dev, 1, enabled,
1850 SNB_READ_WM1_LATENCY() * 500,
1851 &sandybridge_display_srwm_info,
1852 &sandybridge_cursor_srwm_info,
1853 &fbc_wm, &plane_wm, &cursor_wm))
1854 return;
1855
1856 I915_WRITE(WM1_LP_ILK,
1857 WM1_LP_SR_EN |
1858 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1859 (fbc_wm << WM1_LP_FBC_SHIFT) |
1860 (plane_wm << WM1_LP_SR_SHIFT) |
1861 cursor_wm);
1862
1863 /* WM2 */
1864 if (!ironlake_compute_srwm(dev, 2, enabled,
1865 SNB_READ_WM2_LATENCY() * 500,
1866 &sandybridge_display_srwm_info,
1867 &sandybridge_cursor_srwm_info,
1868 &fbc_wm, &plane_wm, &cursor_wm))
1869 return;
1870
1871 I915_WRITE(WM2_LP_ILK,
1872 WM2_LP_EN |
1873 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1874 (fbc_wm << WM1_LP_FBC_SHIFT) |
1875 (plane_wm << WM1_LP_SR_SHIFT) |
1876 cursor_wm);
1877
1878 /* WM3 */
1879 if (!ironlake_compute_srwm(dev, 3, enabled,
1880 SNB_READ_WM3_LATENCY() * 500,
1881 &sandybridge_display_srwm_info,
1882 &sandybridge_cursor_srwm_info,
1883 &fbc_wm, &plane_wm, &cursor_wm))
1884 return;
1885
1886 I915_WRITE(WM3_LP_ILK,
1887 WM3_LP_EN |
1888 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1889 (fbc_wm << WM1_LP_FBC_SHIFT) |
1890 (plane_wm << WM1_LP_SR_SHIFT) |
1891 cursor_wm);
1892}
1893
1f8eeabf
ED		 1894static void
1895haswell_update_linetime_wm(struct drm_device *dev, int pipe,
1896 struct drm_display_mode *mode)
1897{
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 u32 temp;
1900
1901 temp = I915_READ(PIPE_WM_LINETIME(pipe));
1902 temp &= ~PIPE_WM_LINETIME_MASK;
1903
1904 /* The WM are computed with base on how long it takes to fill a single
1905 * row at the given clock rate, multiplied by 8.
1906 * */
1907 temp |= PIPE_WM_LINETIME_TIME(
1908 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
1909
1910 /* IPS watermarks are only used by pipe A, and are ignored by
1911 * pipes B and C. They are calculated similarly to the common
1912 * linetime values, except that we are using CD clock frequency
1913 * in MHz instead of pixel rate for the division.
1914 *
1915 * This is a placeholder for the IPS watermark calculation code.
1916 */
1917
1918 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
1919}
1920
b445e3b0
ED		 1921static bool
1922sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1923 uint32_t sprite_width, int pixel_size,
1924 const struct intel_watermark_params *display,
1925 int display_latency_ns, int *sprite_wm)
1926{
1927 struct drm_crtc *crtc;
1928 int clock;
1929 int entries, tlb_miss;
1930
1931 crtc = intel_get_crtc_for_plane(dev, plane);
1932 if (crtc->fb == NULL || !crtc->enabled) {
1933 *sprite_wm = display->guard_size;
1934 return false;
1935 }
1936
1937 clock = crtc->mode.clock;
1938
1939 /* Use the small buffer method to calculate the sprite watermark */
1940 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1941 tlb_miss = display->fifo_size*display->cacheline_size -
1942 sprite_width * 8;
1943 if (tlb_miss > 0)
1944 entries += tlb_miss;
1945 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1946 *sprite_wm = entries + display->guard_size;
1947 if (*sprite_wm > (int)display->max_wm)
1948 *sprite_wm = display->max_wm;
1949
1950 return true;
1951}
1952
1953static bool
1954sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1955 uint32_t sprite_width, int pixel_size,
1956 const struct intel_watermark_params *display,
1957 int latency_ns, int *sprite_wm)
1958{
1959 struct drm_crtc *crtc;
1960 unsigned long line_time_us;
1961 int clock;
1962 int line_count, line_size;
1963 int small, large;
1964 int entries;
1965
1966 if (!latency_ns) {
1967 *sprite_wm = 0;
1968 return false;
1969 }
1970
1971 crtc = intel_get_crtc_for_plane(dev, plane);
1972 clock = crtc->mode.clock;
1973 if (!clock) {
1974 *sprite_wm = 0;
1975 return false;
1976 }
1977
1978 line_time_us = (sprite_width * 1000) / clock;
1979 if (!line_time_us) {
1980 *sprite_wm = 0;
1981 return false;
1982 }
1983
1984 line_count = (latency_ns / line_time_us + 1000) / 1000;
1985 line_size = sprite_width * pixel_size;
1986
1987 /* Use the minimum of the small and large buffer method for primary */
1988 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1989 large = line_count * line_size;
1990
1991 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1992 *sprite_wm = entries + display->guard_size;
1993
1994 return *sprite_wm > 0x3ff ? false : true;
1995}
1996
1fa61106 1997static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 1998 uint32_t sprite_width, int pixel_size)
1999{
2000 struct drm_i915_private *dev_priv = dev->dev_private;
2001 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2002 u32 val;
2003 int sprite_wm, reg;
2004 int ret;
2005
2006 switch (pipe) {
2007 case 0:
2008 reg = WM0_PIPEA_ILK;
2009 break;
2010 case 1:
2011 reg = WM0_PIPEB_ILK;
2012 break;
2013 case 2:
2014 reg = WM0_PIPEC_IVB;
2015 break;
2016 default:
2017 return; /* bad pipe */
2018 }
2019
2020 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2021 &sandybridge_display_wm_info,
2022 latency, &sprite_wm);
2023 if (!ret) {
2024 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2025 pipe);
2026 return;
2027 }
2028
2029 val = I915_READ(reg);
2030 val &= ~WM0_PIPE_SPRITE_MASK;
2031 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2032 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2033
2034
2035 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2036 pixel_size,
2037 &sandybridge_display_srwm_info,
2038 SNB_READ_WM1_LATENCY() * 500,
2039 &sprite_wm);
2040 if (!ret) {
2041 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2042 pipe);
2043 return;
2044 }
2045 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2046
2047 /* Only IVB has two more LP watermarks for sprite */
2048 if (!IS_IVYBRIDGE(dev))
2049 return;
2050
2051 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2052 pixel_size,
2053 &sandybridge_display_srwm_info,
2054 SNB_READ_WM2_LATENCY() * 500,
2055 &sprite_wm);
2056 if (!ret) {
2057 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2058 pipe);
2059 return;
2060 }
2061 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2062
2063 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2064 pixel_size,
2065 &sandybridge_display_srwm_info,
2066 SNB_READ_WM3_LATENCY() * 500,
2067 &sprite_wm);
2068 if (!ret) {
2069 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2070 pipe);
2071 return;
2072 }
2073 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2074}
2075
2076/**
2077 * intel_update_watermarks - update FIFO watermark values based on current modes
2078 *
2079 * Calculate watermark values for the various WM regs based on current mode
2080 * and plane configuration.
2081 *
2082 * There are several cases to deal with here:
2083 * - normal (i.e. non-self-refresh)
2084 * - self-refresh (SR) mode
2085 * - lines are large relative to FIFO size (buffer can hold up to 2)
2086 * - lines are small relative to FIFO size (buffer can hold more than 2
2087 * lines), so need to account for TLB latency
2088 *
2089 * The normal calculation is:
2090 * watermark = dotclock * bytes per pixel * latency
2091 * where latency is platform & configuration dependent (we assume pessimal
2092 * values here).
2093 *
2094 * The SR calculation is:
2095 * watermark = (trunc(latency/line time)+1) * surface width *
2096 * bytes per pixel
2097 * where
2098 * line time = htotal / dotclock
2099 * surface width = hdisplay for normal plane and 64 for cursor
2100 * and latency is assumed to be high, as above.
2101 *
2102 * The final value programmed to the register should always be rounded up,
2103 * and include an extra 2 entries to account for clock crossings.
2104 *
2105 * We don't use the sprite, so we can ignore that. And on Crestline we have
2106 * to set the non-SR watermarks to 8.
2107 */
2108void intel_update_watermarks(struct drm_device *dev)
2109{
2110 struct drm_i915_private *dev_priv = dev->dev_private;
2111
2112 if (dev_priv->display.update_wm)
2113 dev_priv->display.update_wm(dev);
2114}
2115
1f8eeabf
ED		 2116void intel_update_linetime_watermarks(struct drm_device *dev,
2117 int pipe, struct drm_display_mode *mode)
2118{
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120
2121 if (dev_priv->display.update_linetime_wm)
2122 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2123}
2124
b445e3b0
ED		 2125void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2126 uint32_t sprite_width, int pixel_size)
2127{
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129
2130 if (dev_priv->display.update_sprite_wm)
2131 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2132 pixel_size);
2133}
2134
2b4e57bd
ED		 2135static struct drm_i915_gem_object *
2136intel_alloc_context_page(struct drm_device *dev)
2137{
2138 struct drm_i915_gem_object *ctx;
2139 int ret;
2140
2141 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2142
2143 ctx = i915_gem_alloc_object(dev, 4096);
2144 if (!ctx) {
2145 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2146 return NULL;
2147 }
2148
86a1ee26 2149 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2150 if (ret) {
2151 DRM_ERROR("failed to pin power context: %d\n", ret);
2152 goto err_unref;
2153 }
2154
2155 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2156 if (ret) {
2157 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2158 goto err_unpin;
2159 }
2160
2161 return ctx;
2162
2163err_unpin:
2164 i915_gem_object_unpin(ctx);
2165err_unref:
2166 drm_gem_object_unreference(&ctx->base);
2167 mutex_unlock(&dev->struct_mutex);
2168 return NULL;
2169}
2170
9270388e
DV		 2171/**
2172 * Lock protecting IPS related data structures
9270388e
DV		 2173 */
2174DEFINE_SPINLOCK(mchdev_lock);
2175
2176/* Global for IPS driver to get at the current i915 device. Protected by
2177 * mchdev_lock. */
2178static struct drm_i915_private *i915_mch_dev;
2179
2b4e57bd
ED		 2180bool ironlake_set_drps(struct drm_device *dev, u8 val)
2181{
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 u16 rgvswctl;
2184
9270388e
DV		 2185 assert_spin_locked(&mchdev_lock);
2186
2b4e57bd
ED		 2187 rgvswctl = I915_READ16(MEMSWCTL);
2188 if (rgvswctl & MEMCTL_CMD_STS) {
2189 DRM_DEBUG("gpu busy, RCS change rejected\n");
2190 return false; /* still busy with another command */
2191 }
2192
2193 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2194 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2195 I915_WRITE16(MEMSWCTL, rgvswctl);
2196 POSTING_READ16(MEMSWCTL);
2197
2198 rgvswctl |= MEMCTL_CMD_STS;
2199 I915_WRITE16(MEMSWCTL, rgvswctl);
2200
2201 return true;
2202}
2203
8090c6b9 2204static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2205{
2206 struct drm_i915_private *dev_priv = dev->dev_private;
2207 u32 rgvmodectl = I915_READ(MEMMODECTL);
2208 u8 fmax, fmin, fstart, vstart;
2209
9270388e
DV		 2210 spin_lock_irq(&mchdev_lock);
2211
2b4e57bd
ED		 2212 /* Enable temp reporting */
2213 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2214 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2215
2216 /* 100ms RC evaluation intervals */
2217 I915_WRITE(RCUPEI, 100000);
2218 I915_WRITE(RCDNEI, 100000);
2219
2220 /* Set max/min thresholds to 90ms and 80ms respectively */
2221 I915_WRITE(RCBMAXAVG, 90000);
2222 I915_WRITE(RCBMINAVG, 80000);
2223
2224 I915_WRITE(MEMIHYST, 1);
2225
2226 /* Set up min, max, and cur for interrupt handling */
2227 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2228 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2229 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2230 MEMMODE_FSTART_SHIFT;
2231
2232 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2233 PXVFREQ_PX_SHIFT;
2234
20e4d407
DV		 2235 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2236 dev_priv->ips.fstart = fstart;
2b4e57bd 2237
20e4d407
DV		 2238 dev_priv->ips.max_delay = fstart;
2239 dev_priv->ips.min_delay = fmin;
2240 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2241
2242 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2243 fmax, fmin, fstart);
2244
2245 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2246
2247 /*
2248 * Interrupts will be enabled in ironlake_irq_postinstall
2249 */
2250
2251 I915_WRITE(VIDSTART, vstart);
2252 POSTING_READ(VIDSTART);
2253
2254 rgvmodectl |= MEMMODE_SWMODE_EN;
2255 I915_WRITE(MEMMODECTL, rgvmodectl);
2256
9270388e 2257 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2258 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2259 mdelay(1);
2b4e57bd
ED		 2260
2261 ironlake_set_drps(dev, fstart);
2262
20e4d407 2263 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2264 I915_READ(0x112e0);
20e4d407
DV		 2265 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2266 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2267 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2268
2269 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2270}
2271
8090c6b9 2272static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2273{
2274 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2275 u16 rgvswctl;
2276
2277 spin_lock_irq(&mchdev_lock);
2278
2279 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2280
2281 /* Ack interrupts, disable EFC interrupt */
2282 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2283 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2284 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2285 I915_WRITE(DEIIR, DE_PCU_EVENT);
2286 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2287
2288 /* Go back to the starting frequency */
20e4d407 2289 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2290 mdelay(1);
2b4e57bd
ED		 2291 rgvswctl |= MEMCTL_CMD_STS;
2292 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2293 mdelay(1);
2b4e57bd 2294
9270388e 2295 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2296}
2297
acbe9475
DV		 2298/* There's a funny hw issue where the hw returns all 0 when reading from
2299 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2300 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2301 * all limits and the gpu stuck at whatever frequency it is at atm).
2302 */
65bccb5c 2303static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2304{
7b9e0ae6 2305 u32 limits;
2b4e57bd 2306
7b9e0ae6 2307 limits = 0;
c6a828d3
DV		 2308
2309 if (*val >= dev_priv->rps.max_delay)
2310 *val = dev_priv->rps.max_delay;
2311 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2312
2313 /* Only set the down limit when we've reached the lowest level to avoid
2314 * getting more interrupts, otherwise leave this clear. This prevents a
2315 * race in the hw when coming out of rc6: There's a tiny window where
2316 * the hw runs at the minimal clock before selecting the desired
2317 * frequency, if the down threshold expires in that window we will not
2318 * receive a down interrupt. */
c6a828d3
DV		 2319 if (*val <= dev_priv->rps.min_delay) {
2320 *val = dev_priv->rps.min_delay;
2321 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2322 }
2323
2324 return limits;
2325}
2326
2327void gen6_set_rps(struct drm_device *dev, u8 val)
2328{
2329 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2330 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2331
4fc688ce 2332 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 2333 WARN_ON(val > dev_priv->rps.max_delay);
2334 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2335
c6a828d3 2336 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2337 return;
2338
2339 I915_WRITE(GEN6_RPNSWREQ,
2340 GEN6_FREQUENCY(val) |
2341 GEN6_OFFSET(0) |
2342 GEN6_AGGRESSIVE_TURBO);
2343
2344 /* Make sure we continue to get interrupts
2345 * until we hit the minimum or maximum frequencies.
2346 */
2347 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2348
d5570a72
BW		 2349 POSTING_READ(GEN6_RPNSWREQ);
2350
c6a828d3 2351 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2352
2353 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2354}
2355
8090c6b9 2356static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2357{
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359
88509484 2360 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2361 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2362 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2363 I915_WRITE(GEN6_PMIER, 0);
2364 /* Complete PM interrupt masking here doesn't race with the rps work
2365 * item again unmasking PM interrupts because that is using a different
2366 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2367 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2368
c6a828d3
DV		 2369 spin_lock_irq(&dev_priv->rps.lock);
2370 dev_priv->rps.pm_iir = 0;
2371 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2372
2373 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2374}
2375
2376int intel_enable_rc6(const struct drm_device *dev)
2377{
456470eb 2378 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2379 if (i915_enable_rc6 >= 0)
2380 return i915_enable_rc6;
2381
456470eb 2382 if (INTEL_INFO(dev)->gen == 5) {
cd7988ee
DV		 2383#ifdef CONFIG_INTEL_IOMMU
2384 /* Disable rc6 on ilk if VT-d is on. */
2385 if (intel_iommu_gfx_mapped)
2386 return false;
2387#endif
456470eb
DV		 2388 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2389 return INTEL_RC6_ENABLE;
2390 }
2b4e57bd 2391
456470eb
DV		 2392 if (IS_HASWELL(dev)) {
2393 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2394 return INTEL_RC6_ENABLE;
456470eb 2395 }
2b4e57bd 2396
456470eb 2397 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2398 if (INTEL_INFO(dev)->gen == 6) {
2399 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2400 return INTEL_RC6_ENABLE;
2401 }
456470eb 2402
2b4e57bd
ED		 2403 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2404 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2405}
2406
79f5b2c7 2407static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2408{
79f5b2c7 2409 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2410 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2411 u32 rp_state_cap;
2412 u32 gt_perf_status;
31643d54 2413 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 2414 u32 gtfifodbg;
2b4e57bd 2415 int rc6_mode;
42c0526c 2416 int i, ret;
2b4e57bd 2417
4fc688ce 2418 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2419
2b4e57bd
ED		 2420 /* Here begins a magic sequence of register writes to enable
2421 * auto-downclocking.
2422 *
2423 * Perhaps there might be some value in exposing these to
2424 * userspace...
2425 */
2426 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2427
2428 /* Clear the DBG now so we don't confuse earlier errors */
2429 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2430 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2431 I915_WRITE(GTFIFODBG, gtfifodbg);
2432 }
2433
2434 gen6_gt_force_wake_get(dev_priv);
2435
7b9e0ae6
CW		 2436 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2437 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2438
2439 /* In units of 100MHz */
c6a828d3
DV		 2440 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2441 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2442 dev_priv->rps.cur_delay = 0;
7b9e0ae6 2443
2b4e57bd
ED		 2444 /* disable the counters and set deterministic thresholds */
2445 I915_WRITE(GEN6_RC_CONTROL, 0);
2446
2447 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2448 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2449 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2450 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2451 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2452
b4519513
CW		 2453 for_each_ring(ring, dev_priv, i)
2454 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2455
2456 I915_WRITE(GEN6_RC_SLEEP, 0);
2457 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2458 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2459 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2460 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2461
5a7dc92a 2462 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2463 rc6_mode = intel_enable_rc6(dev_priv->dev);
2464 if (rc6_mode & INTEL_RC6_ENABLE)
2465 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2466
5a7dc92a
ED		 2467 /* We don't use those on Haswell */
2468 if (!IS_HASWELL(dev)) {
2469 if (rc6_mode & INTEL_RC6p_ENABLE)
2470 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2471
5a7dc92a
ED		 2472 if (rc6_mode & INTEL_RC6pp_ENABLE)
2473 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2474 }
2b4e57bd
ED		 2475
2476 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2477 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2478 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2479 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2480
2481 I915_WRITE(GEN6_RC_CONTROL,
2482 rc6_mask |
2483 GEN6_RC_CTL_EI_MODE(1) |
2484 GEN6_RC_CTL_HW_ENABLE);
2485
2486 I915_WRITE(GEN6_RPNSWREQ,
2487 GEN6_FREQUENCY(10) |
2488 GEN6_OFFSET(0) |
2489 GEN6_AGGRESSIVE_TURBO);
2490 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2491 GEN6_FREQUENCY(12));
2492
2493 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2494 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 2495 dev_priv->rps.max_delay << 24 |
2496 dev_priv->rps.min_delay << 16);
5a7dc92a 2497
1ee9ae32
DV		 2498 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2499 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2500 I915_WRITE(GEN6_RP_UP_EI, 66000);
2501 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 2502
2b4e57bd
ED		 2503 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2504 I915_WRITE(GEN6_RP_CONTROL,
2505 GEN6_RP_MEDIA_TURBO |
89ba829e 2506 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2507 GEN6_RP_MEDIA_IS_GFX |
2508 GEN6_RP_ENABLE |
2509 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2510 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 2511
42c0526c
BW		 2512 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2513 if (!ret) {
2514 pcu_mbox = 0;
2515 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2516 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2517 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2518 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2519 }
2520 } else {
2521 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 2522 }
2523
7b9e0ae6 2524 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2525
2526 /* requires MSI enabled */
ff928261 2527 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 2528 spin_lock_irq(&dev_priv->rps.lock);
2529 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 2530 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 2531 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2532 /* enable all PM interrupts */
2533 I915_WRITE(GEN6_PMINTRMSK, 0);
2534
31643d54
BW		 2535 rc6vids = 0;
2536 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2537 if (IS_GEN6(dev) && ret) {
2538 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2539 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2540 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2541 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2542 rc6vids &= 0xffff00;
2543 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2544 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2545 if (ret)
2546 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2547 }
2548
2b4e57bd 2549 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2550}
2551
79f5b2c7 2552static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2553{
79f5b2c7 2554 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 2555 int min_freq = 15;
e3fef09d
JD		 2556 int gpu_freq;
2557 unsigned int ia_freq, max_ia_freq;
2b4e57bd
ED		 2558 int scaling_factor = 180;
2559
4fc688ce 2560 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2561
2b4e57bd
ED		 2562 max_ia_freq = cpufreq_quick_get_max(0);
2563 /*
2564 * Default to measured freq if none found, PCU will ensure we don't go
2565 * over
2566 */
2567 if (!max_ia_freq)
2568 max_ia_freq = tsc_khz;
2569
2570 /* Convert from kHz to MHz */
2571 max_ia_freq /= 1000;
2572
2b4e57bd
ED		 2573 /*
2574 * For each potential GPU frequency, load a ring frequency we'd like
2575 * to use for memory access. We do this by specifying the IA frequency
2576 * the PCU should use as a reference to determine the ring frequency.
2577 */
c6a828d3 2578 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 2579 gpu_freq--) {
c6a828d3 2580 int diff = dev_priv->rps.max_delay - gpu_freq;
2b4e57bd
ED		 2581
2582 /*
2583 * For GPU frequencies less than 750MHz, just use the lowest
2584 * ring freq.
2585 */
2586 if (gpu_freq < min_freq)
2587 ia_freq = 800;
2588 else
2589 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2590 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
42c0526c 2591 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2b4e57bd 2592
42c0526c
BW		 2593 sandybridge_pcode_write(dev_priv,
2594 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2595 ia_freq | gpu_freq);
2b4e57bd 2596 }
2b4e57bd
ED		 2597}
2598
930ebb46 2599void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 2600{
2601 struct drm_i915_private *dev_priv = dev->dev_private;
2602
3e373948
DV		 2603 if (dev_priv->ips.renderctx) {
2604 i915_gem_object_unpin(dev_priv->ips.renderctx);
2605 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2606 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 2607 }
2608
3e373948
DV		 2609 if (dev_priv->ips.pwrctx) {
2610 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2611 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2612 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 2613 }
2614}
2615
930ebb46 2616static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2617{
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619
2620 if (I915_READ(PWRCTXA)) {
2621 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2622 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2623 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2624 50);
2625
2626 I915_WRITE(PWRCTXA, 0);
2627 POSTING_READ(PWRCTXA);
2628
2629 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2630 POSTING_READ(RSTDBYCTL);
2631 }
2b4e57bd
ED		 2632}
2633
2634static int ironlake_setup_rc6(struct drm_device *dev)
2635{
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637
3e373948
DV		 2638 if (dev_priv->ips.renderctx == NULL)
2639 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2640 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 2641 return -ENOMEM;
2642
3e373948
DV		 2643 if (dev_priv->ips.pwrctx == NULL)
2644 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2645 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 2646 ironlake_teardown_rc6(dev);
2647 return -ENOMEM;
2648 }
2649
2650 return 0;
2651}
2652
930ebb46 2653static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2654{
2655 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 2656 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 2657 bool was_interruptible;
2b4e57bd
ED		 2658 int ret;
2659
2660 /* rc6 disabled by default due to repeated reports of hanging during
2661 * boot and resume.
2662 */
2663 if (!intel_enable_rc6(dev))
2664 return;
2665
79f5b2c7
DV		 2666 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2667
2b4e57bd 2668 ret = ironlake_setup_rc6(dev);
79f5b2c7 2669 if (ret)
2b4e57bd 2670 return;
2b4e57bd 2671
3e960501
CW		 2672 was_interruptible = dev_priv->mm.interruptible;
2673 dev_priv->mm.interruptible = false;
2674
2b4e57bd
ED		 2675 /*
2676 * GPU can automatically power down the render unit if given a page
2677 * to save state.
2678 */
6d90c952 2679 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 2680 if (ret) {
2681 ironlake_teardown_rc6(dev);
3e960501 2682 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 2683 return;
2684 }
2685
6d90c952
DV		 2686 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2687 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 2688 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 2689 MI_MM_SPACE_GTT |
2690 MI_SAVE_EXT_STATE_EN |
2691 MI_RESTORE_EXT_STATE_EN |
2692 MI_RESTORE_INHIBIT);
2693 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2694 intel_ring_emit(ring, MI_NOOP);
2695 intel_ring_emit(ring, MI_FLUSH);
2696 intel_ring_advance(ring);
2b4e57bd
ED		 2697
2698 /*
2699 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2700 * does an implicit flush, combined with MI_FLUSH above, it should be
2701 * safe to assume that renderctx is valid
2702 */
3e960501
CW		 2703 ret = intel_ring_idle(ring);
2704 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 2705 if (ret) {
2706 DRM_ERROR("failed to enable ironlake power power savings\n");
2707 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2708 return;
2709 }
2710
3e373948 2711 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 2712 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 2713}
2714
dde18883
ED		 2715static unsigned long intel_pxfreq(u32 vidfreq)
2716{
2717 unsigned long freq;
2718 int div = (vidfreq & 0x3f0000) >> 16;
2719 int post = (vidfreq & 0x3000) >> 12;
2720 int pre = (vidfreq & 0x7);
2721
2722 if (!pre)
2723 return 0;
2724
2725 freq = ((div * 133333) / ((1<<post) * pre));
2726
2727 return freq;
2728}
2729
eb48eb00
DV		 2730static const struct cparams {
2731 u16 i;
2732 u16 t;
2733 u16 m;
2734 u16 c;
2735} cparams[] = {
2736 { 1, 1333, 301, 28664 },
2737 { 1, 1066, 294, 24460 },
2738 { 1, 800, 294, 25192 },
2739 { 0, 1333, 276, 27605 },
2740 { 0, 1066, 276, 27605 },
2741 { 0, 800, 231, 23784 },
2742};
2743
f531dcb2 2744static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2745{
2746 u64 total_count, diff, ret;
2747 u32 count1, count2, count3, m = 0, c = 0;
2748 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2749 int i;
2750
02d71956
DV		 2751 assert_spin_locked(&mchdev_lock);
2752
20e4d407 2753 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 2754
2755 /* Prevent division-by-zero if we are asking too fast.
2756 * Also, we don't get interesting results if we are polling
2757 * faster than once in 10ms, so just return the saved value
2758 * in such cases.
2759 */
2760 if (diff1 <= 10)
20e4d407 2761 return dev_priv->ips.chipset_power;
eb48eb00
DV		 2762
2763 count1 = I915_READ(DMIEC);
2764 count2 = I915_READ(DDREC);
2765 count3 = I915_READ(CSIEC);
2766
2767 total_count = count1 + count2 + count3;
2768
2769 /* FIXME: handle per-counter overflow */
20e4d407
DV		 2770 if (total_count < dev_priv->ips.last_count1) {
2771 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 2772 diff += total_count;
2773 } else {
20e4d407 2774 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 2775 }
2776
2777 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 2778 if (cparams[i].i == dev_priv->ips.c_m &&
2779 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 2780 m = cparams[i].m;
2781 c = cparams[i].c;
2782 break;
2783 }
2784 }
2785
2786 diff = div_u64(diff, diff1);
2787 ret = ((m * diff) + c);
2788 ret = div_u64(ret, 10);
2789
20e4d407
DV		 2790 dev_priv->ips.last_count1 = total_count;
2791 dev_priv->ips.last_time1 = now;
eb48eb00 2792
20e4d407 2793 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 2794
2795 return ret;
2796}
2797
f531dcb2
CW		 2798unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2799{
2800 unsigned long val;
2801
2802 if (dev_priv->info->gen != 5)
2803 return 0;
2804
2805 spin_lock_irq(&mchdev_lock);
2806
2807 val = __i915_chipset_val(dev_priv);
2808
2809 spin_unlock_irq(&mchdev_lock);
2810
2811 return val;
2812}
2813
eb48eb00
DV		 2814unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2815{
2816 unsigned long m, x, b;
2817 u32 tsfs;
2818
2819 tsfs = I915_READ(TSFS);
2820
2821 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2822 x = I915_READ8(TR1);
2823
2824 b = tsfs & TSFS_INTR_MASK;
2825
2826 return ((m * x) / 127) - b;
2827}
2828
2829static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2830{
2831 static const struct v_table {
2832 u16 vd; /* in .1 mil */
2833 u16 vm; /* in .1 mil */
2834 } v_table[] = {
2835 { 0, 0, },
2836 { 375, 0, },
2837 { 500, 0, },
2838 { 625, 0, },
2839 { 750, 0, },
2840 { 875, 0, },
2841 { 1000, 0, },
2842 { 1125, 0, },
2843 { 4125, 3000, },
2844 { 4125, 3000, },
2845 { 4125, 3000, },
2846 { 4125, 3000, },
2847 { 4125, 3000, },
2848 { 4125, 3000, },
2849 { 4125, 3000, },
2850 { 4125, 3000, },
2851 { 4125, 3000, },
2852 { 4125, 3000, },
2853 { 4125, 3000, },
2854 { 4125, 3000, },
2855 { 4125, 3000, },
2856 { 4125, 3000, },
2857 { 4125, 3000, },
2858 { 4125, 3000, },
2859 { 4125, 3000, },
2860 { 4125, 3000, },
2861 { 4125, 3000, },
2862 { 4125, 3000, },
2863 { 4125, 3000, },
2864 { 4125, 3000, },
2865 { 4125, 3000, },
2866 { 4125, 3000, },
2867 { 4250, 3125, },
2868 { 4375, 3250, },
2869 { 4500, 3375, },
2870 { 4625, 3500, },
2871 { 4750, 3625, },
2872 { 4875, 3750, },
2873 { 5000, 3875, },
2874 { 5125, 4000, },
2875 { 5250, 4125, },
2876 { 5375, 4250, },
2877 { 5500, 4375, },
2878 { 5625, 4500, },
2879 { 5750, 4625, },
2880 { 5875, 4750, },
2881 { 6000, 4875, },
2882 { 6125, 5000, },
2883 { 6250, 5125, },
2884 { 6375, 5250, },
2885 { 6500, 5375, },
2886 { 6625, 5500, },
2887 { 6750, 5625, },
2888 { 6875, 5750, },
2889 { 7000, 5875, },
2890 { 7125, 6000, },
2891 { 7250, 6125, },
2892 { 7375, 6250, },
2893 { 7500, 6375, },
2894 { 7625, 6500, },
2895 { 7750, 6625, },
2896 { 7875, 6750, },
2897 { 8000, 6875, },
2898 { 8125, 7000, },
2899 { 8250, 7125, },
2900 { 8375, 7250, },
2901 { 8500, 7375, },
2902 { 8625, 7500, },
2903 { 8750, 7625, },
2904 { 8875, 7750, },
2905 { 9000, 7875, },
2906 { 9125, 8000, },
2907 { 9250, 8125, },
2908 { 9375, 8250, },
2909 { 9500, 8375, },
2910 { 9625, 8500, },
2911 { 9750, 8625, },
2912 { 9875, 8750, },
2913 { 10000, 8875, },
2914 { 10125, 9000, },
2915 { 10250, 9125, },
2916 { 10375, 9250, },
2917 { 10500, 9375, },
2918 { 10625, 9500, },
2919 { 10750, 9625, },
2920 { 10875, 9750, },
2921 { 11000, 9875, },
2922 { 11125, 10000, },
2923 { 11250, 10125, },
2924 { 11375, 10250, },
2925 { 11500, 10375, },
2926 { 11625, 10500, },
2927 { 11750, 10625, },
2928 { 11875, 10750, },
2929 { 12000, 10875, },
2930 { 12125, 11000, },
2931 { 12250, 11125, },
2932 { 12375, 11250, },
2933 { 12500, 11375, },
2934 { 12625, 11500, },
2935 { 12750, 11625, },
2936 { 12875, 11750, },
2937 { 13000, 11875, },
2938 { 13125, 12000, },
2939 { 13250, 12125, },
2940 { 13375, 12250, },
2941 { 13500, 12375, },
2942 { 13625, 12500, },
2943 { 13750, 12625, },
2944 { 13875, 12750, },
2945 { 14000, 12875, },
2946 { 14125, 13000, },
2947 { 14250, 13125, },
2948 { 14375, 13250, },
2949 { 14500, 13375, },
2950 { 14625, 13500, },
2951 { 14750, 13625, },
2952 { 14875, 13750, },
2953 { 15000, 13875, },
2954 { 15125, 14000, },
2955 { 15250, 14125, },
2956 { 15375, 14250, },
2957 { 15500, 14375, },
2958 { 15625, 14500, },
2959 { 15750, 14625, },
2960 { 15875, 14750, },
2961 { 16000, 14875, },
2962 { 16125, 15000, },
2963 };
2964 if (dev_priv->info->is_mobile)
2965 return v_table[pxvid].vm;
2966 else
2967 return v_table[pxvid].vd;
2968}
2969
02d71956 2970static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2971{
2972 struct timespec now, diff1;
2973 u64 diff;
2974 unsigned long diffms;
2975 u32 count;
2976
02d71956 2977 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 2978
2979 getrawmonotonic(&now);
20e4d407 2980 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 2981
2982 /* Don't divide by 0 */
2983 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
2984 if (!diffms)
2985 return;
2986
2987 count = I915_READ(GFXEC);
2988
20e4d407
DV		 2989 if (count < dev_priv->ips.last_count2) {
2990 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 2991 diff += count;
2992 } else {
20e4d407 2993 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 2994 }
2995
20e4d407
DV		 2996 dev_priv->ips.last_count2 = count;
2997 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 2998
2999 /* More magic constants... */
3000 diff = diff * 1181;
3001 diff = div_u64(diff, diffms * 10);
20e4d407 3002 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 3003}
3004
02d71956
DV		 3005void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3006{
3007 if (dev_priv->info->gen != 5)
3008 return;
3009
9270388e 3010 spin_lock_irq(&mchdev_lock);
02d71956
DV		 3011
3012 __i915_update_gfx_val(dev_priv);
3013
9270388e 3014 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3015}
3016
f531dcb2 3017static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3018{
3019 unsigned long t, corr, state1, corr2, state2;
3020 u32 pxvid, ext_v;
3021
02d71956
DV		 3022 assert_spin_locked(&mchdev_lock);
3023
c6a828d3 3024 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3025 pxvid = (pxvid >> 24) & 0x7f;
3026 ext_v = pvid_to_extvid(dev_priv, pxvid);
3027
3028 state1 = ext_v;
3029
3030 t = i915_mch_val(dev_priv);
3031
3032 /* Revel in the empirically derived constants */
3033
3034 /* Correction factor in 1/100000 units */
3035 if (t > 80)
3036 corr = ((t * 2349) + 135940);
3037 else if (t >= 50)
3038 corr = ((t * 964) + 29317);
3039 else /* < 50 */
3040 corr = ((t * 301) + 1004);
3041
3042 corr = corr * ((150142 * state1) / 10000 - 78642);
3043 corr /= 100000;
20e4d407 3044 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3045
3046 state2 = (corr2 * state1) / 10000;
3047 state2 /= 100; /* convert to mW */
3048
02d71956 3049 __i915_update_gfx_val(dev_priv);
eb48eb00 3050
20e4d407 3051 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3052}
3053
f531dcb2
CW		 3054unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3055{
3056 unsigned long val;
3057
3058 if (dev_priv->info->gen != 5)
3059 return 0;
3060
3061 spin_lock_irq(&mchdev_lock);
3062
3063 val = __i915_gfx_val(dev_priv);
3064
3065 spin_unlock_irq(&mchdev_lock);
3066
3067 return val;
3068}
3069
eb48eb00
DV		 3070/**
3071 * i915_read_mch_val - return value for IPS use
3072 *
3073 * Calculate and return a value for the IPS driver to use when deciding whether
3074 * we have thermal and power headroom to increase CPU or GPU power budget.
3075 */
3076unsigned long i915_read_mch_val(void)
3077{
3078 struct drm_i915_private *dev_priv;
3079 unsigned long chipset_val, graphics_val, ret = 0;
3080
9270388e 3081 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3082 if (!i915_mch_dev)
3083 goto out_unlock;
3084 dev_priv = i915_mch_dev;
3085
f531dcb2
CW		 3086 chipset_val = __i915_chipset_val(dev_priv);
3087 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3088
3089 ret = chipset_val + graphics_val;
3090
3091out_unlock:
9270388e 3092 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3093
3094 return ret;
3095}
3096EXPORT_SYMBOL_GPL(i915_read_mch_val);
3097
3098/**
3099 * i915_gpu_raise - raise GPU frequency limit
3100 *
3101 * Raise the limit; IPS indicates we have thermal headroom.
3102 */
3103bool i915_gpu_raise(void)
3104{
3105 struct drm_i915_private *dev_priv;
3106 bool ret = true;
3107
9270388e 3108 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3109 if (!i915_mch_dev) {
3110 ret = false;
3111 goto out_unlock;
3112 }
3113 dev_priv = i915_mch_dev;
3114
20e4d407
DV		 3115 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3116 dev_priv->ips.max_delay--;
eb48eb00
DV		 3117
3118out_unlock:
9270388e 3119 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3120
3121 return ret;
3122}
3123EXPORT_SYMBOL_GPL(i915_gpu_raise);
3124
3125/**
3126 * i915_gpu_lower - lower GPU frequency limit
3127 *
3128 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3129 * frequency maximum.
3130 */
3131bool i915_gpu_lower(void)
3132{
3133 struct drm_i915_private *dev_priv;
3134 bool ret = true;
3135
9270388e 3136 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3137 if (!i915_mch_dev) {
3138 ret = false;
3139 goto out_unlock;
3140 }
3141 dev_priv = i915_mch_dev;
3142
20e4d407
DV		 3143 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3144 dev_priv->ips.max_delay++;
eb48eb00
DV		 3145
3146out_unlock:
9270388e 3147 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3148
3149 return ret;
3150}
3151EXPORT_SYMBOL_GPL(i915_gpu_lower);
3152
3153/**
3154 * i915_gpu_busy - indicate GPU business to IPS
3155 *
3156 * Tell the IPS driver whether or not the GPU is busy.
3157 */
3158bool i915_gpu_busy(void)
3159{
3160 struct drm_i915_private *dev_priv;
f047e395 3161 struct intel_ring_buffer *ring;
eb48eb00 3162 bool ret = false;
f047e395 3163 int i;
eb48eb00 3164
9270388e 3165 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3166 if (!i915_mch_dev)
3167 goto out_unlock;
3168 dev_priv = i915_mch_dev;
3169
f047e395
CW		 3170 for_each_ring(ring, dev_priv, i)
3171 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3172
3173out_unlock:
9270388e 3174 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3175
3176 return ret;
3177}
3178EXPORT_SYMBOL_GPL(i915_gpu_busy);
3179
3180/**
3181 * i915_gpu_turbo_disable - disable graphics turbo
3182 *
3183 * Disable graphics turbo by resetting the max frequency and setting the
3184 * current frequency to the default.
3185 */
3186bool i915_gpu_turbo_disable(void)
3187{
3188 struct drm_i915_private *dev_priv;
3189 bool ret = true;
3190
9270388e 3191 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3192 if (!i915_mch_dev) {
3193 ret = false;
3194 goto out_unlock;
3195 }
3196 dev_priv = i915_mch_dev;
3197
20e4d407 3198 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 3199
20e4d407 3200 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 3201 ret = false;
3202
3203out_unlock:
9270388e 3204 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3205
3206 return ret;
3207}
3208EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3209
3210/**
3211 * Tells the intel_ips driver that the i915 driver is now loaded, if
3212 * IPS got loaded first.
3213 *
3214 * This awkward dance is so that neither module has to depend on the
3215 * other in order for IPS to do the appropriate communication of
3216 * GPU turbo limits to i915.
3217 */
3218static void
3219ips_ping_for_i915_load(void)
3220{
3221 void (*link)(void);
3222
3223 link = symbol_get(ips_link_to_i915_driver);
3224 if (link) {
3225 link();
3226 symbol_put(ips_link_to_i915_driver);
3227 }
3228}
3229
3230void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3231{
02d71956
DV		 3232 /* We only register the i915 ips part with intel-ips once everything is
3233 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 3234 spin_lock_irq(&mchdev_lock);
eb48eb00 3235 i915_mch_dev = dev_priv;
9270388e 3236 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3237
3238 ips_ping_for_i915_load();
3239}
3240
3241void intel_gpu_ips_teardown(void)
3242{
9270388e 3243 spin_lock_irq(&mchdev_lock);
eb48eb00 3244 i915_mch_dev = NULL;
9270388e 3245 spin_unlock_irq(&mchdev_lock);
eb48eb00 3246}
8090c6b9 3247static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3248{
3249 struct drm_i915_private *dev_priv = dev->dev_private;
3250 u32 lcfuse;
3251 u8 pxw[16];
3252 int i;
3253
3254 /* Disable to program */
3255 I915_WRITE(ECR, 0);
3256 POSTING_READ(ECR);
3257
3258 /* Program energy weights for various events */
3259 I915_WRITE(SDEW, 0x15040d00);
3260 I915_WRITE(CSIEW0, 0x007f0000);
3261 I915_WRITE(CSIEW1, 0x1e220004);
3262 I915_WRITE(CSIEW2, 0x04000004);
3263
3264 for (i = 0; i < 5; i++)
3265 I915_WRITE(PEW + (i * 4), 0);
3266 for (i = 0; i < 3; i++)
3267 I915_WRITE(DEW + (i * 4), 0);
3268
3269 /* Program P-state weights to account for frequency power adjustment */
3270 for (i = 0; i < 16; i++) {
3271 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3272 unsigned long freq = intel_pxfreq(pxvidfreq);
3273 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3274 PXVFREQ_PX_SHIFT;
3275 unsigned long val;
3276
3277 val = vid * vid;
3278 val *= (freq / 1000);
3279 val *= 255;
3280 val /= (127*127*900);
3281 if (val > 0xff)
3282 DRM_ERROR("bad pxval: %ld\n", val);
3283 pxw[i] = val;
3284 }
3285 /* Render standby states get 0 weight */
3286 pxw[14] = 0;
3287 pxw[15] = 0;
3288
3289 for (i = 0; i < 4; i++) {
3290 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3291 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3292 I915_WRITE(PXW + (i * 4), val);
3293 }
3294
3295 /* Adjust magic regs to magic values (more experimental results) */
3296 I915_WRITE(OGW0, 0);
3297 I915_WRITE(OGW1, 0);
3298 I915_WRITE(EG0, 0x00007f00);
3299 I915_WRITE(EG1, 0x0000000e);
3300 I915_WRITE(EG2, 0x000e0000);
3301 I915_WRITE(EG3, 0x68000300);
3302 I915_WRITE(EG4, 0x42000000);
3303 I915_WRITE(EG5, 0x00140031);
3304 I915_WRITE(EG6, 0);
3305 I915_WRITE(EG7, 0);
3306
3307 for (i = 0; i < 8; i++)
3308 I915_WRITE(PXWL + (i * 4), 0);
3309
3310 /* Enable PMON + select events */
3311 I915_WRITE(ECR, 0x80000019);
3312
3313 lcfuse = I915_READ(LCFUSE02);
3314
20e4d407 3315 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 3316}
3317
8090c6b9
DV		 3318void intel_disable_gt_powersave(struct drm_device *dev)
3319{
1a01ab3b
JB		 3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321
930ebb46 3322 if (IS_IRONLAKE_M(dev)) {
8090c6b9 3323 ironlake_disable_drps(dev);
930ebb46
DV		 3324 ironlake_disable_rc6(dev);
3325 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
1a01ab3b 3326 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4fc688ce 3327 mutex_lock(&dev_priv->rps.hw_lock);
8090c6b9 3328 gen6_disable_rps(dev);
4fc688ce 3329 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 3330 }
8090c6b9
DV		 3331}
3332
1a01ab3b
JB		 3333static void intel_gen6_powersave_work(struct work_struct *work)
3334{
3335 struct drm_i915_private *dev_priv =
3336 container_of(work, struct drm_i915_private,
3337 rps.delayed_resume_work.work);
3338 struct drm_device *dev = dev_priv->dev;
3339
4fc688ce 3340 mutex_lock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3341 gen6_enable_rps(dev);
3342 gen6_update_ring_freq(dev);
4fc688ce 3343 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3344}
3345
8090c6b9
DV		 3346void intel_enable_gt_powersave(struct drm_device *dev)
3347{
1a01ab3b
JB		 3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349
8090c6b9
DV		 3350 if (IS_IRONLAKE_M(dev)) {
3351 ironlake_enable_drps(dev);
3352 ironlake_enable_rc6(dev);
3353 intel_init_emon(dev);
7cf50fc8 3354 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1a01ab3b
JB		 3355 /*
3356 * PCU communication is slow and this doesn't need to be
3357 * done at any specific time, so do this out of our fast path
3358 * to make resume and init faster.
3359 */
3360 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3361 round_jiffies_up_relative(HZ));
8090c6b9
DV		 3362 }
3363}
3364
3107bd48
DV		 3365static void ibx_init_clock_gating(struct drm_device *dev)
3366{
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368
3369 /*
3370 * On Ibex Peak and Cougar Point, we need to disable clock
3371 * gating for the panel power sequencer or it will fail to
3372 * start up when no ports are active.
3373 */
3374 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3375}
3376
1fa61106 3377static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3378{
3379 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 3380 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 3381
3382 /* Required for FBC */
4d47e4f5
DL		 3383 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3384 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3385 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3386
3387 I915_WRITE(PCH_3DCGDIS0,
3388 MARIUNIT_CLOCK_GATE_DISABLE |
3389 SVSMUNIT_CLOCK_GATE_DISABLE);
3390 I915_WRITE(PCH_3DCGDIS1,
3391 VFMUNIT_CLOCK_GATE_DISABLE);
3392
6f1d69b0
ED		 3393 /*
3394 * According to the spec the following bits should be set in
3395 * order to enable memory self-refresh
3396 * The bit 22/21 of 0x42004
3397 * The bit 5 of 0x42020
3398 * The bit 15 of 0x45000
3399 */
3400 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3401 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3402 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 3403 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3404 I915_WRITE(DISP_ARB_CTL,
3405 (I915_READ(DISP_ARB_CTL) |
3406 DISP_FBC_WM_DIS));
3407 I915_WRITE(WM3_LP_ILK, 0);
3408 I915_WRITE(WM2_LP_ILK, 0);
3409 I915_WRITE(WM1_LP_ILK, 0);
3410
3411 /*
3412 * Based on the document from hardware guys the following bits
3413 * should be set unconditionally in order to enable FBC.
3414 * The bit 22 of 0x42000
3415 * The bit 22 of 0x42004
3416 * The bit 7,8,9 of 0x42020.
3417 */
3418 if (IS_IRONLAKE_M(dev)) {
3419 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3420 I915_READ(ILK_DISPLAY_CHICKEN1) |
3421 ILK_FBCQ_DIS);
3422 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3423 I915_READ(ILK_DISPLAY_CHICKEN2) |
3424 ILK_DPARB_GATE);
6f1d69b0
ED		 3425 }
3426
4d47e4f5
DL		 3427 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3428
6f1d69b0
ED		 3429 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3430 I915_READ(ILK_DISPLAY_CHICKEN2) |
3431 ILK_ELPIN_409_SELECT);
3432 I915_WRITE(_3D_CHICKEN2,
3433 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3434 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374
DV		 3435
3436 /* WaDisableRenderCachePipelinedFlush */
3437 I915_WRITE(CACHE_MODE_0,
3438 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 3439
3440 ibx_init_clock_gating(dev);
3441}
3442
3443static void cpt_init_clock_gating(struct drm_device *dev)
3444{
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 int pipe;
3447
3448 /*
3449 * On Ibex Peak and Cougar Point, we need to disable clock
3450 * gating for the panel power sequencer or it will fail to
3451 * start up when no ports are active.
3452 */
3453 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3454 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3455 DPLS_EDP_PPS_FIX_DIS);
3456 /* WADP0ClockGatingDisable */
3457 for_each_pipe(pipe) {
3458 I915_WRITE(TRANS_CHICKEN1(pipe),
3459 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3460 }
6f1d69b0
ED		 3461}
3462
1fa61106 3463static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3464{
3465 struct drm_i915_private *dev_priv = dev->dev_private;
3466 int pipe;
231e54f6 3467 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 3468
231e54f6 3469 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 3470
3471 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3472 I915_READ(ILK_DISPLAY_CHICKEN2) |
3473 ILK_ELPIN_409_SELECT);
3474
3475 I915_WRITE(WM3_LP_ILK, 0);
3476 I915_WRITE(WM2_LP_ILK, 0);
3477 I915_WRITE(WM1_LP_ILK, 0);
3478
6f1d69b0 3479 I915_WRITE(CACHE_MODE_0,
50743298 3480 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3481
3482 I915_WRITE(GEN6_UCGCTL1,
3483 I915_READ(GEN6_UCGCTL1) |
3484 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3485 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3486
3487 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3488 * gating disable must be set. Failure to set it results in
3489 * flickering pixels due to Z write ordering failures after
3490 * some amount of runtime in the Mesa "fire" demo, and Unigine
3491 * Sanctuary and Tropics, and apparently anything else with
3492 * alpha test or pixel discard.
3493 *
3494 * According to the spec, bit 11 (RCCUNIT) must also be set,
3495 * but we didn't debug actual testcases to find it out.
0f846f81
JB		 3496 *
3497 * Also apply WaDisableVDSUnitClockGating and
3498 * WaDisableRCPBUnitClockGating.
6f1d69b0
ED		 3499 */
3500 I915_WRITE(GEN6_UCGCTL2,
0f846f81 3501 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 3502 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3503 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3504
3505 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 3506 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3507 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 3508
3509 /*
3510 * According to the spec the following bits should be
3511 * set in order to enable memory self-refresh and fbc:
3512 * The bit21 and bit22 of 0x42000
3513 * The bit21 and bit22 of 0x42004
3514 * The bit5 and bit7 of 0x42020
3515 * The bit14 of 0x70180
3516 * The bit14 of 0x71180
3517 */
3518 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3519 I915_READ(ILK_DISPLAY_CHICKEN1) |
3520 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3521 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3522 I915_READ(ILK_DISPLAY_CHICKEN2) |
3523 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 3524 I915_WRITE(ILK_DSPCLK_GATE_D,
3525 I915_READ(ILK_DSPCLK_GATE_D) |
3526 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3527 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 3528
b3bf0766 3529 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3530 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3531 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3532
6f1d69b0
ED		 3533 for_each_pipe(pipe) {
3534 I915_WRITE(DSPCNTR(pipe),
3535 I915_READ(DSPCNTR(pipe)) |
3536 DISPPLANE_TRICKLE_FEED_DISABLE);
3537 intel_flush_display_plane(dev_priv, pipe);
3538 }
f8f2ac9a
BW		 3539
3540 /* The default value should be 0x200 according to docs, but the two
3541 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3542 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3543 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 3544
3545 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3546}
3547
3548static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3549{
3550 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3551
3552 reg &= ~GEN7_FF_SCHED_MASK;
3553 reg |= GEN7_FF_TS_SCHED_HW;
3554 reg |= GEN7_FF_VS_SCHED_HW;
3555 reg |= GEN7_FF_DS_SCHED_HW;
3556
3557 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3558}
3559
17a303ec
PZ		 3560static void lpt_init_clock_gating(struct drm_device *dev)
3561{
3562 struct drm_i915_private *dev_priv = dev->dev_private;
3563
3564 /*
3565 * TODO: this bit should only be enabled when really needed, then
3566 * disabled when not needed anymore in order to save power.
3567 */
3568 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3569 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3570 I915_READ(SOUTH_DSPCLK_GATE_D) |
3571 PCH_LP_PARTITION_LEVEL_DISABLE);
3572}
3573
cad2a2d7
ED		 3574static void haswell_init_clock_gating(struct drm_device *dev)
3575{
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 int pipe;
cad2a2d7
ED		 3578
3579 I915_WRITE(WM3_LP_ILK, 0);
3580 I915_WRITE(WM2_LP_ILK, 0);
3581 I915_WRITE(WM1_LP_ILK, 0);
3582
3583 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3584 * This implements the WaDisableRCZUnitClockGating workaround.
3585 */
3586 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3587
cad2a2d7
ED		 3588 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3589 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3590 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3591
3592 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3593 I915_WRITE(GEN7_L3CNTLREG1,
3594 GEN7_WA_FOR_GEN7_L3_CONTROL);
3595 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3596 GEN7_WA_L3_CHICKEN_MODE);
3597
3598 /* This is required by WaCatErrorRejectionIssue */
3599 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3600 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3601 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3602
3603 for_each_pipe(pipe) {
3604 I915_WRITE(DSPCNTR(pipe),
3605 I915_READ(DSPCNTR(pipe)) |
3606 DISPPLANE_TRICKLE_FEED_DISABLE);
3607 intel_flush_display_plane(dev_priv, pipe);
3608 }
3609
3610 gen7_setup_fixed_func_scheduler(dev_priv);
3611
3612 /* WaDisable4x2SubspanOptimization */
3613 I915_WRITE(CACHE_MODE_1,
3614 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 3615
b3bf0766
PZ		 3616 /* WaMbcDriverBootEnable */
3617 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3618 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3619
1544d9d5
ED		 3620 /* XXX: This is a workaround for early silicon revisions and should be
3621 * removed later.
3622 */
3623 I915_WRITE(WM_DBG,
3624 I915_READ(WM_DBG) |
3625 WM_DBG_DISALLOW_MULTIPLE_LP |
3626 WM_DBG_DISALLOW_SPRITE |
3627 WM_DBG_DISALLOW_MAXFIFO);
3628
17a303ec 3629 lpt_init_clock_gating(dev);
cad2a2d7
ED		 3630}
3631
1fa61106 3632static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3633{
3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 int pipe;
20848223 3636 uint32_t snpcr;
6f1d69b0 3637
6f1d69b0
ED		 3638 I915_WRITE(WM3_LP_ILK, 0);
3639 I915_WRITE(WM2_LP_ILK, 0);
3640 I915_WRITE(WM1_LP_ILK, 0);
3641
231e54f6 3642 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3643
87f8020e
JB		 3644 /* WaDisableEarlyCull */
3645 I915_WRITE(_3D_CHICKEN3,
3646 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3647
62cb944f 3648 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3649 I915_WRITE(IVB_CHICKEN3,
3650 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3651 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3652
12f3382b
JB		 3653 /* WaDisablePSDDualDispatchEnable */
3654 if (IS_IVB_GT1(dev))
3655 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3656 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3657 else
3658 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3659 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3660
6f1d69b0
ED		 3661 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3662 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3663 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3664
3665 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3666 I915_WRITE(GEN7_L3CNTLREG1,
3667 GEN7_WA_FOR_GEN7_L3_CONTROL);
3668 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 3669 GEN7_WA_L3_CHICKEN_MODE);
3670 if (IS_IVB_GT1(dev))
3671 I915_WRITE(GEN7_ROW_CHICKEN2,
3672 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3673 else
3674 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3675 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3676
6f1d69b0 3677
61939d97
JB		 3678 /* WaForceL3Serialization */
3679 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3680 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3681
0f846f81
JB		 3682 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3683 * gating disable must be set. Failure to set it results in
3684 * flickering pixels due to Z write ordering failures after
3685 * some amount of runtime in the Mesa "fire" demo, and Unigine
3686 * Sanctuary and Tropics, and apparently anything else with
3687 * alpha test or pixel discard.
3688 *
3689 * According to the spec, bit 11 (RCCUNIT) must also be set,
3690 * but we didn't debug actual testcases to find it out.
3691 *
3692 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3693 * This implements the WaDisableRCZUnitClockGating workaround.
3694 */
3695 I915_WRITE(GEN6_UCGCTL2,
3696 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3697 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3698
6f1d69b0
ED		 3699 /* This is required by WaCatErrorRejectionIssue */
3700 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3701 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3702 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3703
3704 for_each_pipe(pipe) {
3705 I915_WRITE(DSPCNTR(pipe),
3706 I915_READ(DSPCNTR(pipe)) |
3707 DISPPLANE_TRICKLE_FEED_DISABLE);
3708 intel_flush_display_plane(dev_priv, pipe);
3709 }
3710
b3bf0766 3711 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3712 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3713 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3714
6f1d69b0 3715 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f
DV		 3716
3717 /* WaDisable4x2SubspanOptimization */
3718 I915_WRITE(CACHE_MODE_1,
3719 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 3720
3721 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3722 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3723 snpcr |= GEN6_MBC_SNPCR_MED;
3724 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48
DV		 3725
3726 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3727}
3728
1fa61106 3729static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3730{
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 int pipe;
6f1d69b0
ED		 3733
3734 I915_WRITE(WM3_LP_ILK, 0);
3735 I915_WRITE(WM2_LP_ILK, 0);
3736 I915_WRITE(WM1_LP_ILK, 0);
3737
231e54f6 3738 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3739
87f8020e
JB		 3740 /* WaDisableEarlyCull */
3741 I915_WRITE(_3D_CHICKEN3,
3742 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3743
62cb944f 3744 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3745 I915_WRITE(IVB_CHICKEN3,
3746 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3747 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3748
12f3382b
JB		 3749 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3750 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3751
6f1d69b0
ED		 3752 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3753 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3754 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3755
3756 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
d0cf5ead 3757 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 3758 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3759
61939d97
JB		 3760 /* WaForceL3Serialization */
3761 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3762 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3763
8ab43976
JB		 3764 /* WaDisableDopClockGating */
3765 I915_WRITE(GEN7_ROW_CHICKEN2,
3766 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3767
5c9664d7
JB		 3768 /* WaForceL3Serialization */
3769 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3770 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3771
6f1d69b0
ED		 3772 /* This is required by WaCatErrorRejectionIssue */
3773 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3774 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3775 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3776
b3bf0766 3777 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3778 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3779 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3780
0f846f81
JB		 3781
3782 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3783 * gating disable must be set. Failure to set it results in
3784 * flickering pixels due to Z write ordering failures after
3785 * some amount of runtime in the Mesa "fire" demo, and Unigine
3786 * Sanctuary and Tropics, and apparently anything else with
3787 * alpha test or pixel discard.
3788 *
3789 * According to the spec, bit 11 (RCCUNIT) must also be set,
3790 * but we didn't debug actual testcases to find it out.
3791 *
3792 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3793 * This implements the WaDisableRCZUnitClockGating workaround.
3794 *
3795 * Also apply WaDisableVDSUnitClockGating and
3796 * WaDisableRCPBUnitClockGating.
3797 */
3798 I915_WRITE(GEN6_UCGCTL2,
3799 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 3800 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 3801 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3802 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3803 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3804
e3f33d46
JB		 3805 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3806
6f1d69b0
ED		 3807 for_each_pipe(pipe) {
3808 I915_WRITE(DSPCNTR(pipe),
3809 I915_READ(DSPCNTR(pipe)) |
3810 DISPPLANE_TRICKLE_FEED_DISABLE);
3811 intel_flush_display_plane(dev_priv, pipe);
3812 }
3813
6b26c86d
DV		 3814 I915_WRITE(CACHE_MODE_1,
3815 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f
JB		 3816
3817 /*
3818 * On ValleyView, the GUnit needs to signal the GT
3819 * when flip and other events complete. So enable
3820 * all the GUnit->GT interrupts here
3821 */
3822 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3823 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3824 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3825 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3826 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3827 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3828 PLANEA_FLIPDONE_INT_EN);
2d809570
JB		 3829
3830 /*
3831 * WaDisableVLVClockGating_VBIIssue
3832 * Disable clock gating on th GCFG unit to prevent a delay
3833 * in the reporting of vblank events.
3834 */
3835 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 3836}
3837
1fa61106 3838static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3839{
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 uint32_t dspclk_gate;
3842
3843 I915_WRITE(RENCLK_GATE_D1, 0);
3844 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3845 GS_UNIT_CLOCK_GATE_DISABLE |
3846 CL_UNIT_CLOCK_GATE_DISABLE);
3847 I915_WRITE(RAMCLK_GATE_D, 0);
3848 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3849 OVRUNIT_CLOCK_GATE_DISABLE |
3850 OVCUNIT_CLOCK_GATE_DISABLE;
3851 if (IS_GM45(dev))
3852 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3853 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 3854
3855 /* WaDisableRenderCachePipelinedFlush */
3856 I915_WRITE(CACHE_MODE_0,
3857 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 3858}
3859
1fa61106 3860static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3861{
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863
3864 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3865 I915_WRITE(RENCLK_GATE_D2, 0);
3866 I915_WRITE(DSPCLK_GATE_D, 0);
3867 I915_WRITE(RAMCLK_GATE_D, 0);
3868 I915_WRITE16(DEUC, 0);
3869}
3870
1fa61106 3871static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3872{
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874
3875 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3876 I965_RCC_CLOCK_GATE_DISABLE |
3877 I965_RCPB_CLOCK_GATE_DISABLE |
3878 I965_ISC_CLOCK_GATE_DISABLE |
3879 I965_FBC_CLOCK_GATE_DISABLE);
3880 I915_WRITE(RENCLK_GATE_D2, 0);
3881}
3882
1fa61106 3883static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3884{
3885 struct drm_i915_private *dev_priv = dev->dev_private;
3886 u32 dstate = I915_READ(D_STATE);
3887
3888 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3889 DSTATE_DOT_CLOCK_GATING;
3890 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 3891
3892 if (IS_PINEVIEW(dev))
3893 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 3894
3895 /* IIR "flip pending" means done if this bit is set */
3896 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 3897}
3898
1fa61106 3899static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3900{
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902
3903 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3904}
3905
1fa61106 3906static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3907{
3908 struct drm_i915_private *dev_priv = dev->dev_private;
3909
3910 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3911}
3912
6f1d69b0
ED		 3913void intel_init_clock_gating(struct drm_device *dev)
3914{
3915 struct drm_i915_private *dev_priv = dev->dev_private;
3916
3917 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 3918}
3919
d0d3e513
ED		 3920/* Starting with Haswell, we have different power wells for
3921 * different parts of the GPU. This attempts to enable them all.
3922 */
3923void intel_init_power_wells(struct drm_device *dev)
3924{
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 unsigned long power_wells[] = {
3927 HSW_PWR_WELL_CTL1,
3928 HSW_PWR_WELL_CTL2,
3929 HSW_PWR_WELL_CTL4
3930 };
3931 int i;
3932
3933 if (!IS_HASWELL(dev))
3934 return;
3935
3936 mutex_lock(&dev->struct_mutex);
3937
3938 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
3939 int well = I915_READ(power_wells[i]);
3940
3941 if ((well & HSW_PWR_WELL_STATE) == 0) {
3942 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
263b30d4 3943 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
d0d3e513
ED		 3944 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
3945 }
3946 }
3947
3948 mutex_unlock(&dev->struct_mutex);
3949}
3950
1fa61106
ED		 3951/* Set up chip specific power management-related functions */
3952void intel_init_pm(struct drm_device *dev)
3953{
3954 struct drm_i915_private *dev_priv = dev->dev_private;
3955
3956 if (I915_HAS_FBC(dev)) {
3957 if (HAS_PCH_SPLIT(dev)) {
3958 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
3959 dev_priv->display.enable_fbc = ironlake_enable_fbc;
3960 dev_priv->display.disable_fbc = ironlake_disable_fbc;
3961 } else if (IS_GM45(dev)) {
3962 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
3963 dev_priv->display.enable_fbc = g4x_enable_fbc;
3964 dev_priv->display.disable_fbc = g4x_disable_fbc;
3965 } else if (IS_CRESTLINE(dev)) {
3966 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
3967 dev_priv->display.enable_fbc = i8xx_enable_fbc;
3968 dev_priv->display.disable_fbc = i8xx_disable_fbc;
3969 }
3970 /* 855GM needs testing */
3971 }
3972
c921aba8
DV		 3973 /* For cxsr */
3974 if (IS_PINEVIEW(dev))
3975 i915_pineview_get_mem_freq(dev);
3976 else if (IS_GEN5(dev))
3977 i915_ironlake_get_mem_freq(dev);
3978
1fa61106
ED		 3979 /* For FIFO watermark updates */
3980 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 3981 if (IS_GEN5(dev)) {
3982 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
3983 dev_priv->display.update_wm = ironlake_update_wm;
3984 else {
3985 DRM_DEBUG_KMS("Failed to get proper latency. "
3986 "Disable CxSR\n");
3987 dev_priv->display.update_wm = NULL;
3988 }
3989 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
3990 } else if (IS_GEN6(dev)) {
3991 if (SNB_READ_WM0_LATENCY()) {
3992 dev_priv->display.update_wm = sandybridge_update_wm;
3993 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3994 } else {
3995 DRM_DEBUG_KMS("Failed to read display plane latency. "
3996 "Disable CxSR\n");
3997 dev_priv->display.update_wm = NULL;
3998 }
3999 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4000 } else if (IS_IVYBRIDGE(dev)) {
4001 /* FIXME: detect B0+ stepping and use auto training */
4002 if (SNB_READ_WM0_LATENCY()) {
4003 dev_priv->display.update_wm = sandybridge_update_wm;
4004 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4005 } else {
4006 DRM_DEBUG_KMS("Failed to read display plane latency. "
4007 "Disable CxSR\n");
4008 dev_priv->display.update_wm = NULL;
4009 }
4010 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb
ED		 4011 } else if (IS_HASWELL(dev)) {
4012 if (SNB_READ_WM0_LATENCY()) {
4013 dev_priv->display.update_wm = sandybridge_update_wm;
4014 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 4015 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 4016 } else {
4017 DRM_DEBUG_KMS("Failed to read display plane latency. "
4018 "Disable CxSR\n");
4019 dev_priv->display.update_wm = NULL;
4020 }
cad2a2d7 4021 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 4022 } else
4023 dev_priv->display.update_wm = NULL;
4024 } else if (IS_VALLEYVIEW(dev)) {
4025 dev_priv->display.update_wm = valleyview_update_wm;
4026 dev_priv->display.init_clock_gating =
4027 valleyview_init_clock_gating;
1fa61106
ED		 4028 } else if (IS_PINEVIEW(dev)) {
4029 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4030 dev_priv->is_ddr3,
4031 dev_priv->fsb_freq,
4032 dev_priv->mem_freq)) {
4033 DRM_INFO("failed to find known CxSR latency "
4034 "(found ddr%s fsb freq %d, mem freq %d), "
4035 "disabling CxSR\n",
4036 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4037 dev_priv->fsb_freq, dev_priv->mem_freq);
4038 /* Disable CxSR and never update its watermark again */
4039 pineview_disable_cxsr(dev);
4040 dev_priv->display.update_wm = NULL;
4041 } else
4042 dev_priv->display.update_wm = pineview_update_wm;
4043 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4044 } else if (IS_G4X(dev)) {
4045 dev_priv->display.update_wm = g4x_update_wm;
4046 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4047 } else if (IS_GEN4(dev)) {
4048 dev_priv->display.update_wm = i965_update_wm;
4049 if (IS_CRESTLINE(dev))
4050 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4051 else if (IS_BROADWATER(dev))
4052 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4053 } else if (IS_GEN3(dev)) {
4054 dev_priv->display.update_wm = i9xx_update_wm;
4055 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4056 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4057 } else if (IS_I865G(dev)) {
4058 dev_priv->display.update_wm = i830_update_wm;
4059 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4060 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4061 } else if (IS_I85X(dev)) {
4062 dev_priv->display.update_wm = i9xx_update_wm;
4063 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4064 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4065 } else {
4066 dev_priv->display.update_wm = i830_update_wm;
4067 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4068 if (IS_845G(dev))
4069 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4070 else
4071 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4072 }
4073}
4074
6590190d
ED		 4075static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4076{
4077 u32 gt_thread_status_mask;
4078
4079 if (IS_HASWELL(dev_priv->dev))
4080 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4081 else
4082 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4083
4084 /* w/a for a sporadic read returning 0 by waiting for the GT
4085 * thread to wake up.
4086 */
4087 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4088 DRM_ERROR("GT thread status wait timed out\n");
4089}
4090
16995a9f
CW		 4091static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4092{
4093 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4094 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4095}
4096
6590190d
ED		 4097static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4098{
4099 u32 forcewake_ack;
4100
4101 if (IS_HASWELL(dev_priv->dev))
4102 forcewake_ack = FORCEWAKE_ACK_HSW;
4103 else
4104 forcewake_ack = FORCEWAKE_ACK;
4105
057d3860
BW		 4106 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4107 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4108 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4109
c5836c27 4110 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
8dee3eea 4111 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4112
057d3860
BW		 4113 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4114 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4115 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4116
4117 __gen6_gt_wait_for_thread_c0(dev_priv);
4118}
4119
16995a9f
CW		 4120static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4121{
4122 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4123 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4124}
4125
6590190d
ED		 4126static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4127{
4128 u32 forcewake_ack;
4129
4130 if (IS_HASWELL(dev_priv->dev))
4131 forcewake_ack = FORCEWAKE_ACK_HSW;
4132 else
4133 forcewake_ack = FORCEWAKE_MT_ACK;
4134
057d3860
BW		 4135 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4136 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4137 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4138
c5836c27 4139 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
8dee3eea 4140 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4141
057d3860
BW		 4142 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4143 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4144 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4145
4146 __gen6_gt_wait_for_thread_c0(dev_priv);
4147}
4148
4149/*
4150 * Generally this is called implicitly by the register read function. However,
4151 * if some sequence requires the GT to not power down then this function should
4152 * be called at the beginning of the sequence followed by a call to
4153 * gen6_gt_force_wake_put() at the end of the sequence.
4154 */
4155void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4156{
4157 unsigned long irqflags;
4158
4159 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4160 if (dev_priv->forcewake_count++ == 0)
4161 dev_priv->gt.force_wake_get(dev_priv);
4162 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4163}
4164
4165void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4166{
4167 u32 gtfifodbg;
4168 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4169 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4170 "MMIO read or write has been dropped %x\n", gtfifodbg))
4171 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4172}
4173
4174static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4175{
4176 I915_WRITE_NOTRACE(FORCEWAKE, 0);
8dee3eea 4177 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4178 gen6_gt_check_fifodbg(dev_priv);
4179}
4180
4181static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4182{
c5836c27 4183 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
8dee3eea 4184 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4185 gen6_gt_check_fifodbg(dev_priv);
4186}
4187
4188/*
4189 * see gen6_gt_force_wake_get()
4190 */
4191void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4192{
4193 unsigned long irqflags;
4194
4195 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4196 if (--dev_priv->forcewake_count == 0)
4197 dev_priv->gt.force_wake_put(dev_priv);
4198 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4199}
4200
4201int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4202{
4203 int ret = 0;
4204
4205 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4206 int loop = 500;
4207 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4208 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4209 udelay(10);
4210 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4211 }
4212 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4213 ++ret;
4214 dev_priv->gt_fifo_count = fifo;
4215 }
4216 dev_priv->gt_fifo_count--;
4217
4218 return ret;
4219}
4220
16995a9f
CW		 4221static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4222{
4223 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4224}
4225
6590190d
ED		 4226static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4227{
057d3860
BW		 4228 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4229 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4230 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4231
c5836c27 4232 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 4233
057d3860
BW		 4234 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4235 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4236 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4237
4238 __gen6_gt_wait_for_thread_c0(dev_priv);
4239}
4240
4241static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4242{
c5836c27 4243 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5ab140a4
DV		 4244 /* The below doubles as a POSTING_READ */
4245 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 4246}
4247
16995a9f
CW		 4248void intel_gt_reset(struct drm_device *dev)
4249{
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251
4252 if (IS_VALLEYVIEW(dev)) {
4253 vlv_force_wake_reset(dev_priv);
4254 } else if (INTEL_INFO(dev)->gen >= 6) {
4255 __gen6_gt_force_wake_reset(dev_priv);
4256 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4257 __gen6_gt_force_wake_mt_reset(dev_priv);
4258 }
4259}
4260
6590190d
ED		 4261void intel_gt_init(struct drm_device *dev)
4262{
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264
4265 spin_lock_init(&dev_priv->gt_lock);
4266
16995a9f
CW		 4267 intel_gt_reset(dev);
4268
6590190d
ED		 4269 if (IS_VALLEYVIEW(dev)) {
4270 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4271 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 4272 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4273 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4274 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4275 } else if (IS_GEN6(dev)) {
6590190d
ED		 4276 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4277 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 4278 }
1a01ab3b
JB		 4279 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4280 intel_gen6_powersave_work);
6590190d
ED		 4281}
4282
42c0526c
BW		 4283int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4284{
4fc688ce 4285 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4286
4287 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4288 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4289 return -EAGAIN;
4290 }
4291
4292 I915_WRITE(GEN6_PCODE_DATA, *val);
4293 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4294
4295 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4296 500)) {
4297 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4298 return -ETIMEDOUT;
4299 }
4300
4301 *val = I915_READ(GEN6_PCODE_DATA);
4302 I915_WRITE(GEN6_PCODE_DATA, 0);
4303
4304 return 0;
4305}
4306
4307int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4308{
4fc688ce 4309 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4310
4311 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4312 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4313 return -EAGAIN;
4314 }
4315
4316 I915_WRITE(GEN6_PCODE_DATA, val);
4317 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4318
4319 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4320 500)) {
4321 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4322 return -ETIMEDOUT;
4323 }
4324
4325 I915_WRITE(GEN6_PCODE_DATA, 0);
4326
4327 return 0;
4328}
ubuntu-bionic-kernel mirror