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drm/i915: introduce intel_has_sagv()
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
63c62275 255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4 342 } else if (IS_I915GM(dev)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 655 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
7c5f93b0 661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 663 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
ac484963 668 cpp, latency->display_sr);
b445e3b0
ED		 669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
ac484963 678 cpp, latency->cursor_sr);
b445e3b0
ED		 679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
ac484963 687 cpp, latency->display_hpll_disable);
b445e3b0
ED		 688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
ac484963 696 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
ac484963 720 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
ac484963 738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
ac484963 806 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 826 line_size = hdisplay * cpp;
b445e3b0
ED		 827
828 /* Use the minimum of the small and large buffer method for primary */
ac484963 829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
ac484963 836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
2cb389b7
VS		 907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
ae80152d 913 POSTING_READ(DSPFW1);
0018fda1
VS		 914}
915
15665979
VS		 916#undef FW_WM_VLV
917
6eb1a681
VS		 918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 922};
923
262cd2e1
VS		 924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
ac484963 928 unsigned int cpp,
262cd2e1
VS		 929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 934 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
fac5e23e 942 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
58590c14
VS		 947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
262cd2e1
VS		 949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 963 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
936e71e3 968 if (!state->base.visible)
262cd2e1
VS		 969 return 0;
970
ac484963 971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
ac484963 987 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
54f1b6e1
VS		 994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
936e71e3 1010 if (state->base.visible) {
54f1b6e1
VS		 1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
936e71e3 1026 if (!state->base.visible) {
54f1b6e1
VS		 1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
262cd2e1
VS		 1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
26e1fe4f 1095static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
852eb00d 1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1107
1108 wm_state->num_active_planes = 0;
262cd2e1 1109
54f1b6e1 1110 vlv_compute_fifo(crtc);
262cd2e1
VS		 1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
936e71e3 1126 if (!state->base.visible)
262cd2e1
VS		 1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
5a37ed0a 1167 wm_state->wm[level].cursor;
262cd2e1
VS		 1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
58590c14 1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
54f1b6e1
VS		 1194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
262cd2e1
VS		 1284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
58590c14 1290 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
6f9c784b
VS		 1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
262cd2e1
VS		 1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
fac5e23e 1333 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
26e1fe4f 1338 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1339 vlv_merge_wm(dev, &wm);
1340
54f1b6e1
VS		 1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1344 return;
54f1b6e1 1345 }
262cd2e1
VS		 1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
852eb00d 1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1356 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1357
54f1b6e1
VS		 1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
262cd2e1
VS		 1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
852eb00d 1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1370 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1381}
1382
ae80152d
VS		 1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
46ba614c 1385static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1386{
46ba614c 1387 struct drm_device *dev = crtc->dev;
b445e3b0 1388 static const int sr_latency_ns = 12000;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
9858425c 1393 bool cxsr_enabled;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planea_wm, &cursora_wm))
51cea1f4 1399 enabled |= 1 << PIPE_A;
b445e3b0 1400
51cea1f4 1401 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1404 &planeb_wm, &cursorb_wm))
51cea1f4 1405 enabled |= 1 << PIPE_B;
b445e3b0 1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
9858425c 1413 cxsr_enabled = true;
52bd02d8 1414 } else {
9858425c 1415 cxsr_enabled = false;
5209b1f4 1416 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0 1419
a5043453
VS		 1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
f4998963
VS		 1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
b445e3b0 1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1433 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
8c919b28 1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1437 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1441}
1442
46ba614c 1443static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1444{
46ba614c 1445 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
9858425c 1450 bool cxsr_enabled;
b445e3b0
ED		 1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
124abe07 1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1458 int clock = adjusted_mode->crtc_clock;
fec8cba3 1459 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1462 unsigned long line_time_us;
1463 int entries;
1464
922044c9 1465 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1469 cpp * hdisplay;
b445e3b0
ED		 1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
9858425c 1491 cxsr_enabled = true;
b445e3b0 1492 } else {
9858425c 1493 cxsr_enabled = false;
b445e3b0 1494 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1495 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
f4998963
VS		 1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
b445e3b0 1508 /* update cursor SR watermark */
f4998963 1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1513}
1514
f4998963
VS		 1515#undef FW_WM
1516
46ba614c 1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1518{
46ba614c 1519 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1520 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
9d539105 1534 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
ac484963 1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
6e3c9717 1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
5aef6003 1547 pessimal_latency_ns);
b445e3b0 1548 enabled = crtc;
9d539105 1549 } else {
b445e3b0 1550 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
ac484963 1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
6e3c9717 1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
5aef6003 1569 pessimal_latency_ns);
b445e3b0
ED		 1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
9d539105 1574 } else {
b445e3b0 1575 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
b445e3b0
ED		 1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
2ab1bc9d 1582 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1583 struct drm_i915_gem_object *obj;
2ab1bc9d 1584
59bea882 1585 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1586
1587 /* self-refresh seems busted with untiled */
3e510a8e 1588 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1589 enabled = NULL;
1590 }
1591
b445e3b0
ED		 1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1598 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
124abe07 1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1605 int clock = adjusted_mode->crtc_clock;
fec8cba3 1606 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1609 unsigned long line_time_us;
1610 int entries;
1611
2d1b5056
VS		 1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1619 cpp * hdisplay;
b445e3b0
ED		 1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1629 else
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
5209b1f4
ID		 1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1648}
1649
feb56b93 1650static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1651{
46ba614c 1652 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1654 struct drm_crtc *crtc;
241bfc38 1655 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
6e3c9717 1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1665 &i845_wm_info,
b445e3b0 1666 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1667 4, pessimal_latency_ns);
b445e3b0
ED		 1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
8cfb3407 1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1677{
fd4daa9c 1678 uint32_t pixel_rate;
801bcfff 1679
8cfb3407 1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
8cfb3407 1685 if (pipe_config->pch_pfit.enabled) {
801bcfff 1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
801bcfff 1691
801bcfff
PZ		 1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
15126882
MR		 1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
801bcfff
PZ		 1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
37126462 1709/* latency must be in 0.1us units. */
ac484963 1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1711{
1712 uint64_t ret;
1713
3312ba65
VS		 1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
ac484963 1717 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
37126462 1723/* latency must be in 0.1us units. */
23297044 1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1725 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
3312ba65
VS		 1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
15126882
MR		 1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
3312ba65 1734
801bcfff 1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1736 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
23297044 1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1742 uint8_t cpp)
cca32e9a 1743{
15126882
MR		 1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
ac484963 1750 if (WARN_ON(!cpp))
15126882
MR		 1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
ac484963 1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1756}
1757
820c1980 1758struct ilk_wm_maximums {
cca32e9a
PZ		 1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
37126462
VS		 1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
7221fc33 1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1770 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1771 uint32_t mem_value,
1772 bool is_lp)
801bcfff 1773{
ac484963
VS		 1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1776 uint32_t method1, method2;
1777
936e71e3 1778 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1779 return 0;
1780
ac484963 1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1782
1783 if (!is_lp)
1784 return method1;
1785
7221fc33
MR		 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1788 drm_rect_width(&pstate->base.dst),
ac484963 1789 cpp, mem_value);
cca32e9a
PZ		 1790
1791 return min(method1, method2);
801bcfff
PZ		 1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1804 uint32_t method1, method2;
1805
936e71e3 1806 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1807 return 0;
1808
ac484963 1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1812 drm_rect_width(&pstate->base.dst),
ac484963 1813 cpp, mem_value);
801bcfff
PZ		 1814 return min(method1, method2);
1815}
1816
37126462
VS		 1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
7221fc33 1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1822 const struct intel_plane_state *pstate,
801bcfff
PZ		 1823 uint32_t mem_value)
1824{
b2435692
MR		 1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
936e71e3 1831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1832
b2435692 1833 if (!cstate->base.active)
801bcfff
PZ		 1834 return 0;
1835
7221fc33
MR		 1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1838 width, cpp, mem_value);
801bcfff
PZ		 1839}
1840
cca32e9a 1841/* Only for WM_LP. */
7221fc33 1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1843 const struct intel_plane_state *pstate,
1fda9882 1844 uint32_t pri_val)
cca32e9a 1845{
ac484963
VS		 1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1848
936e71e3 1849 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1850 return 0;
1851
936e71e3 1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1853}
1854
158ae64f
VS		 1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
416f4727
VS		 1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1860 return 768;
1861 else
1862 return 512;
1863}
1864
4e975081
VS		 1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
158ae64f
VS		 1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
240264f4 1902 const struct intel_wm_config *config,
158ae64f
VS		 1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1907
1908 /* if sprites aren't enabled, sprites get nothing */
240264f4 1909 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1913 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
240264f4 1925 if (config->sprites_enabled) {
158ae64f
VS		 1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
4e975081 1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1942 int level,
1943 const struct intel_wm_config *config)
158ae64f
VS		 1944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1946 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
4e975081 1950 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1951}
1952
d34ff9c6 1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1957 struct ilk_wm_maximums *max)
158ae64f 1958{
240264f4
VS		 1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1962 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1963}
1964
a3cb4048
VS		 1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
d9395655 1975static bool ilk_validate_wm_level(int level,
820c1980 1976 const struct ilk_wm_maximums *max,
d9395655 1977 struct intel_wm_level *result)
a9786a11
VS		 1978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
a9786a11
VS		 2013 return ret;
2014}
2015
d34ff9c6 2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2017 const struct intel_crtc *intel_crtc,
6f5ddd17 2018 int level,
7221fc33 2019 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
e3bddded
ML		 2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
6f5ddd17
VS		 2048 result->enable = true;
2049}
2050
801bcfff 2051static uint32_t
532f7a7f 2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2053{
532f7a7f
VS		 2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
85a02deb 2058 u32 linetime, ips_linetime;
1f8eeabf 2059
ee91a159
MR		 2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
532f7a7f 2064 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2065 return 0;
1011d8c4 2066
1f8eeabf
ED		 2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
124abe07
VS		 2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2073 intel_state->cdclk);
1f8eeabf 2074
801bcfff
PZ		 2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2077}
2078
2af30a5c 2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2080{
fac5e23e 2081 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2082
2af30a5c
PB		 2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
4f947386 2085 int ret, i;
367294be 2086 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
367294be 2129 /*
6f97235b
DL		 2130 * WaWmMemoryReadLatency:skl
2131 *
367294be
VK		 2132 * punit doesn't take into account the read latency so we need
2133 * to add 2us to the various latency levels we retrieve from
2134 * the punit.
2135 * - W0 is a bit special in that it's the only level that
2136 * can't be disabled if we want to have display working, so
2137 * we always add 2us there.
2138 * - For levels >=1, punit returns 0us latency when they are
2139 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2140 *
2141 * Additionally, if a level n (n > 1) has a 0us latency, all
2142 * levels m (m >= n) need to be disabled. We make sure to
2143 * sanitize the values out of the punit to satisfy this
2144 * requirement.
367294be
VK		 2145 */
2146 wm[0] += 2;
2147 for (level = 1; level <= max_level; level++)
2148 if (wm[level] != 0)
2149 wm[level] += 2;
4f947386
VK		 2150 else {
2151 for (i = level + 1; i <= max_level; i++)
2152 wm[i] = 0;
367294be 2153
4f947386
VK		 2154 break;
2155 }
2af30a5c 2156 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2157 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2158
2159 wm[0] = (sskpd >> 56) & 0xFF;
2160 if (wm[0] == 0)
2161 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2162 wm[1] = (sskpd >> 4) & 0xFF;
2163 wm[2] = (sskpd >> 12) & 0xFF;
2164 wm[3] = (sskpd >> 20) & 0x1FF;
2165 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2166 } else if (INTEL_INFO(dev)->gen >= 6) {
2167 uint32_t sskpd = I915_READ(MCH_SSKPD);
2168
2169 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2170 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2171 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2172 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2173 } else if (INTEL_INFO(dev)->gen >= 5) {
2174 uint32_t mltr = I915_READ(MLTR_ILK);
2175
2176 /* ILK primary LP0 latency is 700 ns */
2177 wm[0] = 7;
2178 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2179 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2180 }
2181}
2182
53615a5e
VS		 2183static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184{
2185 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2186 if (IS_GEN5(dev))
53615a5e
VS		 2187 wm[0] = 13;
2188}
2189
2190static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2191{
2192 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2193 if (IS_GEN5(dev))
53615a5e
VS		 2194 wm[0] = 13;
2195
2196 /* WaDoubleCursorLP3Latency:ivb */
2197 if (IS_IVYBRIDGE(dev))
2198 wm[3] *= 2;
2199}
2200
546c81fd 2201int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2202{
26ec971e 2203 /* how many WM levels are we expecting */
b6e742f6 2204 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2205 return 7;
2206 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2207 return 4;
26ec971e 2208 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2209 return 3;
26ec971e 2210 else
ad0d6dc4
VS		 2211 return 2;
2212}
7526ed79 2213
ad0d6dc4
VS		 2214static void intel_print_wm_latency(struct drm_device *dev,
2215 const char *name,
2af30a5c 2216 const uint16_t wm[8])
ad0d6dc4
VS		 2217{
2218 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2219
2220 for (level = 0; level <= max_level; level++) {
2221 unsigned int latency = wm[level];
2222
2223 if (latency == 0) {
2224 DRM_ERROR("%s WM%d latency not provided\n",
2225 name, level);
2226 continue;
2227 }
2228
2af30a5c
PB		 2229 /*
2230 * - latencies are in us on gen9.
2231 * - before then, WM1+ latency values are in 0.5us units
2232 */
2233 if (IS_GEN9(dev))
2234 latency *= 10;
2235 else if (level > 0)
26ec971e
VS		 2236 latency *= 5;
2237
2238 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2239 name, level, wm[level],
2240 latency / 10, latency % 10);
2241 }
2242}
2243
e95a2f75
VS		 2244static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2245 uint16_t wm[5], uint16_t min)
2246{
91c8a326 2247 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2248
2249 if (wm[0] >= min)
2250 return false;
2251
2252 wm[0] = max(wm[0], min);
2253 for (level = 1; level <= max_level; level++)
2254 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2255
2256 return true;
2257}
2258
2259static void snb_wm_latency_quirk(struct drm_device *dev)
2260{
fac5e23e 2261 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2262 bool changed;
2263
2264 /*
2265 * The BIOS provided WM memory latency values are often
2266 * inadequate for high resolution displays. Adjust them.
2267 */
2268 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2269 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2270 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2271
2272 if (!changed)
2273 return;
2274
2275 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2276 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2277 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2278 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2279}
2280
fa50ad61 2281static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2282{
fac5e23e 2283 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2284
2285 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2286
2287 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2288 sizeof(dev_priv->wm.pri_latency));
2289 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291
2292 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2293 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2294
2295 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2296 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2297 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2298
2299 if (IS_GEN6(dev))
2300 snb_wm_latency_quirk(dev);
53615a5e
VS		 2301}
2302
2af30a5c
PB		 2303static void skl_setup_wm_latency(struct drm_device *dev)
2304{
fac5e23e 2305 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2306
2307 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2308 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2309}
2310
ed4a6a7c
MR		 2311static bool ilk_validate_pipe_wm(struct drm_device *dev,
2312 struct intel_pipe_wm *pipe_wm)
2313{
2314 /* LP0 watermark maximums depend on this pipe alone */
2315 const struct intel_wm_config config = {
2316 .num_pipes_active = 1,
2317 .sprites_enabled = pipe_wm->sprites_enabled,
2318 .sprites_scaled = pipe_wm->sprites_scaled,
2319 };
2320 struct ilk_wm_maximums max;
2321
2322 /* LP0 watermarks always use 1/2 DDB partitioning */
2323 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2324
2325 /* At least LP0 must be valid */
2326 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2327 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2328 return false;
2329 }
2330
2331 return true;
2332}
2333
0b2ae6d7 2334/* Compute new watermarks for the pipe */
e3bddded 2335static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2336{
e3bddded
ML		 2337 struct drm_atomic_state *state = cstate->base.state;
2338 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2339 struct intel_pipe_wm *pipe_wm;
e3bddded 2340 struct drm_device *dev = state->dev;
fac5e23e 2341 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2342 struct intel_plane *intel_plane;
86c8bbbe 2343 struct intel_plane_state *pristate = NULL;
43d59eda 2344 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2345 struct intel_plane_state *curstate = NULL;
d81f04c5 2346 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2347 struct ilk_wm_maximums max;
0b2ae6d7 2348
e8f1f02e 2349 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2350
43d59eda 2351 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2352 struct intel_plane_state *ps;
2353
2354 ps = intel_atomic_get_existing_plane_state(state,
2355 intel_plane);
2356 if (!ps)
2357 continue;
86c8bbbe
MR		 2358
2359 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2360 pristate = ps;
86c8bbbe 2361 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2362 sprstate = ps;
86c8bbbe 2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2364 curstate = ps;
43d59eda
MR		 2365 }
2366
ed4a6a7c 2367 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2368 if (sprstate) {
936e71e3
VS		 2369 pipe_wm->sprites_enabled = sprstate->base.visible;
2370 pipe_wm->sprites_scaled = sprstate->base.visible &&
2371 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2372 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2373 }
2374
d81f04c5
ML		 2375 usable_level = max_level;
2376
7b39a0b7 2377 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2378 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2379 usable_level = 1;
7b39a0b7
VS		 2380
2381 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2382 if (pipe_wm->sprites_scaled)
d81f04c5 2383 usable_level = 0;
7b39a0b7 2384
86c8bbbe 2385 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2386 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2387
2388 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2389 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2390
a42a5719 2391 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2392 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2393
ed4a6a7c 2394 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2395 return -EINVAL;
a3cb4048
VS		 2396
2397 ilk_compute_wm_reg_maximums(dev, 1, &max);
2398
2399 for (level = 1; level <= max_level; level++) {
71f0a626 2400 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2401
86c8bbbe 2402 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2403 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2404
2405 /*
2406 * Disable any watermark level that exceeds the
2407 * register maximums since such watermarks are
2408 * always invalid.
2409 */
71f0a626
ML		 2410 if (level > usable_level)
2411 continue;
2412
2413 if (ilk_validate_wm_level(level, &max, wm))
2414 pipe_wm->wm[level] = *wm;
2415 else
d81f04c5 2416 usable_level = level;
a3cb4048
VS		 2417 }
2418
86c8bbbe 2419 return 0;
0b2ae6d7
VS		 2420}
2421
ed4a6a7c
MR		 2422/*
2423 * Build a set of 'intermediate' watermark values that satisfy both the old
2424 * state and the new state. These can be programmed to the hardware
2425 * immediately.
2426 */
2427static int ilk_compute_intermediate_wm(struct drm_device *dev,
2428 struct intel_crtc *intel_crtc,
2429 struct intel_crtc_state *newstate)
2430{
e8f1f02e 2431 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2432 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2433 int level, max_level = ilk_wm_max_level(dev);
2434
2435 /*
2436 * Start with the final, target watermarks, then combine with the
2437 * currently active watermarks to get values that are safe both before
2438 * and after the vblank.
2439 */
e8f1f02e 2440 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2441 a->pipe_enabled |= b->pipe_enabled;
2442 a->sprites_enabled |= b->sprites_enabled;
2443 a->sprites_scaled |= b->sprites_scaled;
2444
2445 for (level = 0; level <= max_level; level++) {
2446 struct intel_wm_level *a_wm = &a->wm[level];
2447 const struct intel_wm_level *b_wm = &b->wm[level];
2448
2449 a_wm->enable &= b_wm->enable;
2450 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2451 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2452 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2453 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2454 }
2455
2456 /*
2457 * We need to make sure that these merged watermark values are
2458 * actually a valid configuration themselves. If they're not,
2459 * there's no safe way to transition from the old state to
2460 * the new state, so we need to fail the atomic transaction.
2461 */
2462 if (!ilk_validate_pipe_wm(dev, a))
2463 return -EINVAL;
2464
2465 /*
2466 * If our intermediate WM are identical to the final WM, then we can
2467 * omit the post-vblank programming; only update if it's different.
2468 */
e8f1f02e 2469 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2470 newstate->wm.need_postvbl_update = false;
2471
2472 return 0;
2473}
2474
0b2ae6d7
VS		 2475/*
2476 * Merge the watermarks from all active pipes for a specific level.
2477 */
2478static void ilk_merge_wm_level(struct drm_device *dev,
2479 int level,
2480 struct intel_wm_level *ret_wm)
2481{
2482 const struct intel_crtc *intel_crtc;
2483
d52fea5b
VS		 2484 ret_wm->enable = true;
2485
d3fcc808 2486 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2487 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2488 const struct intel_wm_level *wm = &active->wm[level];
2489
2490 if (!active->pipe_enabled)
2491 continue;
0b2ae6d7 2492
d52fea5b
VS		 2493 /*
2494 * The watermark values may have been used in the past,
2495 * so we must maintain them in the registers for some
2496 * time even if the level is now disabled.
2497 */
0b2ae6d7 2498 if (!wm->enable)
d52fea5b 2499 ret_wm->enable = false;
0b2ae6d7
VS		 2500
2501 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2502 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2503 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2504 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2505 }
0b2ae6d7
VS		 2506}
2507
2508/*
2509 * Merge all low power watermarks for all active pipes.
2510 */
2511static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2512 const struct intel_wm_config *config,
820c1980 2513 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2514 struct intel_pipe_wm *merged)
2515{
fac5e23e 2516 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2517 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2518 int last_enabled_level = max_level;
0b2ae6d7 2519
0ba22e26
VS		 2520 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2521 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2522 config->num_pipes_active > 1)
1204d5ba 2523 last_enabled_level = 0;
0ba22e26 2524
6c8b6c28
VS		 2525 /* ILK: FBC WM must be disabled always */
2526 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2527
2528 /* merge each WM1+ level */
2529 for (level = 1; level <= max_level; level++) {
2530 struct intel_wm_level *wm = &merged->wm[level];
2531
2532 ilk_merge_wm_level(dev, level, wm);
2533
d52fea5b
VS		 2534 if (level > last_enabled_level)
2535 wm->enable = false;
2536 else if (!ilk_validate_wm_level(level, max, wm))
2537 /* make sure all following levels get disabled */
2538 last_enabled_level = level - 1;
0b2ae6d7
VS		 2539
2540 /*
2541 * The spec says it is preferred to disable
2542 * FBC WMs instead of disabling a WM level.
2543 */
2544 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2545 if (wm->enable)
2546 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2547 wm->fbc_val = 0;
2548 }
2549 }
6c8b6c28
VS		 2550
2551 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2552 /*
2553 * FIXME this is racy. FBC might get enabled later.
2554 * What we should check here is whether FBC can be
2555 * enabled sometime later.
2556 */
7733b49b 2557 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2558 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2559 for (level = 2; level <= max_level; level++) {
2560 struct intel_wm_level *wm = &merged->wm[level];
2561
2562 wm->enable = false;
2563 }
2564 }
0b2ae6d7
VS		 2565}
2566
b380ca3c
VS		 2567static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2568{
2569 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2570 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2571}
2572
a68d68ee
VS		 2573/* The value we need to program into the WM_LPx latency field */
2574static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2575{
fac5e23e 2576 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2577
a42a5719 2578 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2579 return 2 * level;
2580 else
2581 return dev_priv->wm.pri_latency[level];
2582}
2583
820c1980 2584static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2585 const struct intel_pipe_wm *merged,
609cedef 2586 enum intel_ddb_partitioning partitioning,
820c1980 2587 struct ilk_wm_values *results)
801bcfff 2588{
0b2ae6d7
VS		 2589 struct intel_crtc *intel_crtc;
2590 int level, wm_lp;
cca32e9a 2591
0362c781 2592 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2593 results->partitioning = partitioning;
cca32e9a 2594
0b2ae6d7 2595 /* LP1+ register values */
cca32e9a 2596 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2597 const struct intel_wm_level *r;
801bcfff 2598
b380ca3c 2599 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2600
0362c781 2601 r = &merged->wm[level];
cca32e9a 2602
d52fea5b
VS		 2603 /*
2604 * Maintain the watermark values even if the level is
2605 * disabled. Doing otherwise could cause underruns.
2606 */
2607 results->wm_lp[wm_lp - 1] =
a68d68ee 2608 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2609 (r->pri_val << WM1_LP_SR_SHIFT) |
2610 r->cur_val;
2611
d52fea5b
VS		 2612 if (r->enable)
2613 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2614
416f4727
VS		 2615 if (INTEL_INFO(dev)->gen >= 8)
2616 results->wm_lp[wm_lp - 1] |=
2617 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2618 else
2619 results->wm_lp[wm_lp - 1] |=
2620 r->fbc_val << WM1_LP_FBC_SHIFT;
2621
d52fea5b
VS		 2622 /*
2623 * Always set WM1S_LP_EN when spr_val != 0, even if the
2624 * level is disabled. Doing otherwise could cause underruns.
2625 */
6cef2b8a
VS		 2626 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2627 WARN_ON(wm_lp != 1);
2628 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2629 } else
2630 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2631 }
801bcfff 2632
0b2ae6d7 2633 /* LP0 register values */
d3fcc808 2634 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2635 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2636 const struct intel_wm_level *r =
2637 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2638
2639 if (WARN_ON(!r->enable))
2640 continue;
2641
ed4a6a7c 2642 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2643
0b2ae6d7
VS		 2644 results->wm_pipe[pipe] =
2645 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2646 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2647 r->cur_val;
801bcfff
PZ		 2648 }
2649}
2650
861f3389
PZ		 2651/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2652 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2653static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2654 struct intel_pipe_wm *r1,
2655 struct intel_pipe_wm *r2)
861f3389 2656{
198a1e9b
VS		 2657 int level, max_level = ilk_wm_max_level(dev);
2658 int level1 = 0, level2 = 0;
861f3389 2659
198a1e9b
VS		 2660 for (level = 1; level <= max_level; level++) {
2661 if (r1->wm[level].enable)
2662 level1 = level;
2663 if (r2->wm[level].enable)
2664 level2 = level;
861f3389
PZ		 2665 }
2666
198a1e9b
VS		 2667 if (level1 == level2) {
2668 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2669 return r2;
2670 else
2671 return r1;
198a1e9b 2672 } else if (level1 > level2) {
861f3389
PZ		 2673 return r1;
2674 } else {
2675 return r2;
2676 }
2677}
2678
49a687c4
VS		 2679/* dirty bits used to track which watermarks need changes */
2680#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2681#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2682#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2683#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2684#define WM_DIRTY_FBC (1 << 24)
2685#define WM_DIRTY_DDB (1 << 25)
2686
055e393f 2687static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2688 const struct ilk_wm_values *old,
2689 const struct ilk_wm_values *new)
49a687c4
VS		 2690{
2691 unsigned int dirty = 0;
2692 enum pipe pipe;
2693 int wm_lp;
2694
055e393f 2695 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2696 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2697 dirty |= WM_DIRTY_LINETIME(pipe);
2698 /* Must disable LP1+ watermarks too */
2699 dirty |= WM_DIRTY_LP_ALL;
2700 }
2701
2702 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2703 dirty |= WM_DIRTY_PIPE(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707 }
2708
2709 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2710 dirty |= WM_DIRTY_FBC;
2711 /* Must disable LP1+ watermarks too */
2712 dirty |= WM_DIRTY_LP_ALL;
2713 }
2714
2715 if (old->partitioning != new->partitioning) {
2716 dirty |= WM_DIRTY_DDB;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 /* LP1+ watermarks already deemed dirty, no need to continue */
2722 if (dirty & WM_DIRTY_LP_ALL)
2723 return dirty;
2724
2725 /* Find the lowest numbered LP1+ watermark in need of an update... */
2726 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2727 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2728 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2729 break;
2730 }
2731
2732 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2733 for (; wm_lp <= 3; wm_lp++)
2734 dirty |= WM_DIRTY_LP(wm_lp);
2735
2736 return dirty;
2737}
2738
8553c18e
VS		 2739static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2740 unsigned int dirty)
801bcfff 2741{
820c1980 2742 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2743 bool changed = false;
801bcfff 2744
facd619b
VS		 2745 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2746 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2747 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2748 changed = true;
facd619b
VS		 2749 }
2750 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2751 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2752 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2753 changed = true;
facd619b
VS		 2754 }
2755 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2756 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2757 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2758 changed = true;
facd619b 2759 }
801bcfff 2760
facd619b
VS		 2761 /*
2762 * Don't touch WM1S_LP_EN here.
2763 * Doing so could cause underruns.
2764 */
6cef2b8a 2765
8553c18e
VS		 2766 return changed;
2767}
2768
2769/*
2770 * The spec says we shouldn't write when we don't need, because every write
2771 * causes WMs to be re-evaluated, expending some power.
2772 */
820c1980
ID		 2773static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2774 struct ilk_wm_values *results)
8553c18e 2775{
91c8a326 2776 struct drm_device *dev = &dev_priv->drm;
820c1980 2777 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2778 unsigned int dirty;
2779 uint32_t val;
2780
055e393f 2781 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2782 if (!dirty)
2783 return;
2784
2785 _ilk_disable_lp_wm(dev_priv, dirty);
2786
49a687c4 2787 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2788 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2789 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2790 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2791 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2792 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2793
49a687c4 2794 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2795 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2796 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2798 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2800
49a687c4 2801 if (dirty & WM_DIRTY_DDB) {
a42a5719 2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2803 val = I915_READ(WM_MISC);
2804 if (results->partitioning == INTEL_DDB_PART_1_2)
2805 val &= ~WM_MISC_DATA_PARTITION_5_6;
2806 else
2807 val |= WM_MISC_DATA_PARTITION_5_6;
2808 I915_WRITE(WM_MISC, val);
2809 } else {
2810 val = I915_READ(DISP_ARB_CTL2);
2811 if (results->partitioning == INTEL_DDB_PART_1_2)
2812 val &= ~DISP_DATA_PARTITION_5_6;
2813 else
2814 val |= DISP_DATA_PARTITION_5_6;
2815 I915_WRITE(DISP_ARB_CTL2, val);
2816 }
1011d8c4
PZ		 2817 }
2818
49a687c4 2819 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2820 val = I915_READ(DISP_ARB_CTL);
2821 if (results->enable_fbc_wm)
2822 val &= ~DISP_FBC_WM_DIS;
2823 else
2824 val |= DISP_FBC_WM_DIS;
2825 I915_WRITE(DISP_ARB_CTL, val);
2826 }
2827
954911eb
ID		 2828 if (dirty & WM_DIRTY_LP(1) &&
2829 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2830 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2831
2832 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2833 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2834 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2835 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2836 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2837 }
801bcfff 2838
facd619b 2839 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2840 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2841 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2842 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2843 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2844 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2845
2846 dev_priv->wm.hw = *results;
801bcfff
PZ		 2847}
2848
ed4a6a7c 2849bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2850{
fac5e23e 2851 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2852
2853 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2854}
2855
656d1b89 2856#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2857
024c9045
MR		 2858/*
2859 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2860 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2861 * other universal planes are in indices 1..n. Note that this may leave unused
2862 * indices between the top "sprite" plane and the cursor.
2863 */
2864static int
2865skl_wm_plane_id(const struct intel_plane *plane)
2866{
2867 switch (plane->base.type) {
2868 case DRM_PLANE_TYPE_PRIMARY:
2869 return 0;
2870 case DRM_PLANE_TYPE_CURSOR:
2871 return PLANE_CURSOR;
2872 case DRM_PLANE_TYPE_OVERLAY:
2873 return plane->plane + 1;
2874 default:
2875 MISSING_CASE(plane->base.type);
2876 return plane->plane;
2877 }
2878}
2879
56feca91
PZ		 2880static bool
2881intel_has_sagv(struct drm_i915_private *dev_priv)
2882{
2883 return IS_SKYLAKE(dev_priv) &&
2884 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
2885}
2886
656d1b89
L		 2887/*
2888 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2889 * depending on power and performance requirements. The display engine access
2890 * to system memory is blocked during the adjustment time. Because of the
2891 * blocking time, having this enabled can cause full system hangs and/or pipe
2892 * underruns if we don't meet all of the following requirements:
2893 *
2894 * - <= 1 pipe enabled
2895 * - All planes can enable watermarks for latencies >= SAGV engine block time
2896 * - We're not using an interlaced display configuration
2897 */
2898int
16dcdc4e 2899intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2900{
2901 int ret;
2902
56feca91
PZ		 2903 if (!intel_has_sagv(dev_priv))
2904 return 0;
2905
2906 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2907 return 0;
2908
2909 DRM_DEBUG_KMS("Enabling the SAGV\n");
2910 mutex_lock(&dev_priv->rps.hw_lock);
2911
2912 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2913 GEN9_SAGV_ENABLE);
2914
2915 /* We don't need to wait for the SAGV when enabling */
2916 mutex_unlock(&dev_priv->rps.hw_lock);
2917
2918 /*
2919 * Some skl systems, pre-release machines in particular,
2920 * don't actually have an SAGV.
2921 */
2922 if (ret == -ENXIO) {
2923 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2924 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2925 return 0;
2926 } else if (ret < 0) {
2927 DRM_ERROR("Failed to enable the SAGV\n");
2928 return ret;
2929 }
2930
16dcdc4e 2931 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2932 return 0;
2933}
2934
2935static int
16dcdc4e 2936intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2937{
2938 int ret;
2939 uint32_t temp = GEN9_SAGV_DISABLE;
2940
2941 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2942 &temp);
2943 if (ret)
2944 return ret;
2945 else
2946 return temp & GEN9_SAGV_IS_DISABLED;
2947}
2948
2949int
16dcdc4e 2950intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2951{
2952 int ret, result;
2953
56feca91
PZ		 2954 if (!intel_has_sagv(dev_priv))
2955 return 0;
2956
2957 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2958 return 0;
2959
2960 DRM_DEBUG_KMS("Disabling the SAGV\n");
2961 mutex_lock(&dev_priv->rps.hw_lock);
2962
2963 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2964 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2965 mutex_unlock(&dev_priv->rps.hw_lock);
2966
2967 if (ret == -ETIMEDOUT) {
2968 DRM_ERROR("Request to disable SAGV timed out\n");
2969 return -ETIMEDOUT;
2970 }
2971
2972 /*
2973 * Some skl systems, pre-release machines in particular,
2974 * don't actually have an SAGV.
2975 */
2976 if (result == -ENXIO) {
2977 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2978 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2979 return 0;
2980 } else if (result < 0) {
2981 DRM_ERROR("Failed to disable the SAGV\n");
2982 return result;
2983 }
2984
16dcdc4e 2985 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 2986 return 0;
2987}
2988
16dcdc4e 2989bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 2990{
2991 struct drm_device *dev = state->dev;
2992 struct drm_i915_private *dev_priv = to_i915(dev);
2993 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2994 struct drm_crtc *crtc;
2995 enum pipe pipe;
2996 int level, plane;
2997
56feca91
PZ		 2998 if (!intel_has_sagv(dev_priv))
2999 return false;
3000
656d1b89
L		 3001 /*
3002 * SKL workaround: bspec recommends we disable the SAGV when we have
3003 * more then one pipe enabled
3004 *
3005 * If there are no active CRTCs, no additional checks need be performed
3006 */
3007 if (hweight32(intel_state->active_crtcs) == 0)
3008 return true;
3009 else if (hweight32(intel_state->active_crtcs) > 1)
3010 return false;
3011
3012 /* Since we're now guaranteed to only have one active CRTC... */
3013 pipe = ffs(intel_state->active_crtcs) - 1;
3014 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3015
3016 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3017 return false;
3018
3019 for_each_plane(dev_priv, pipe, plane) {
3020 /* Skip this plane if it's not enabled */
3021 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3022 continue;
3023
3024 /* Find the highest enabled wm level for this plane */
3025 for (level = ilk_wm_max_level(dev);
3026 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3027 { }
3028
3029 /*
3030 * If any of the planes on this pipe don't enable wm levels
3031 * that incur memory latencies higher then 30µs we can't enable
3032 * the SAGV
3033 */
3034 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3035 return false;
3036 }
3037
3038 return true;
3039}
3040
b9cec075
DL		 3041static void
3042skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3043 const struct intel_crtc_state *cstate,
c107acfe
MR		 3044 struct skl_ddb_entry *alloc, /* out */
3045 int *num_active /* out */)
b9cec075 3046{
c107acfe
MR		 3047 struct drm_atomic_state *state = cstate->base.state;
3048 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3049 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3050 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3051 unsigned int pipe_size, ddb_size;
3052 int nth_active_pipe;
c107acfe
MR		 3053 int pipe = to_intel_crtc(for_crtc)->pipe;
3054
a6d3460e 3055 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3056 alloc->start = 0;
3057 alloc->end = 0;
a6d3460e 3058 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3059 return;
3060 }
3061
a6d3460e
MR		 3062 if (intel_state->active_pipe_changes)
3063 *num_active = hweight32(intel_state->active_crtcs);
3064 else
3065 *num_active = hweight32(dev_priv->active_crtcs);
3066
6f3fff60
D		 3067 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3068 WARN_ON(ddb_size == 0);
b9cec075
DL		 3069
3070 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3071
c107acfe 3072 /*
a6d3460e
MR		 3073 * If the state doesn't change the active CRTC's, then there's
3074 * no need to recalculate; the existing pipe allocation limits
3075 * should remain unchanged. Note that we're safe from racing
3076 * commits since any racing commit that changes the active CRTC
3077 * list would need to grab _all_ crtc locks, including the one
3078 * we currently hold.
c107acfe 3079 */
a6d3460e
MR		 3080 if (!intel_state->active_pipe_changes) {
3081 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3082 return;
c107acfe 3083 }
a6d3460e
MR		 3084
3085 nth_active_pipe = hweight32(intel_state->active_crtcs &
3086 (drm_crtc_mask(for_crtc) - 1));
3087 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3088 alloc->start = nth_active_pipe * ddb_size / *num_active;
3089 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3090}
3091
c107acfe 3092static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3093{
c107acfe 3094 if (num_active == 1)
b9cec075
DL		 3095 return 32;
3096
3097 return 8;
3098}
3099
a269c583
DL		 3100static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3101{
3102 entry->start = reg & 0x3ff;
3103 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3104 if (entry->end)
3105 entry->end += 1;
a269c583
DL		 3106}
3107
08db6652
DL		 3108void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3109 struct skl_ddb_allocation *ddb /* out */)
a269c583 3110{
a269c583
DL		 3111 enum pipe pipe;
3112 int plane;
3113 u32 val;
3114
b10f1b20
ML		 3115 memset(ddb, 0, sizeof(*ddb));
3116
a269c583 3117 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3118 enum intel_display_power_domain power_domain;
3119
3120 power_domain = POWER_DOMAIN_PIPE(pipe);
3121 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3122 continue;
3123
dd740780 3124 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3125 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3126 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3127 val);
3128 }
3129
3130 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3131 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3132 val);
4d800030
ID		 3133
3134 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3135 }
3136}
3137
9c2f7a9d
KM		 3138/*
3139 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3140 * The bspec defines downscale amount as:
3141 *
3142 * """
3143 * Horizontal down scale amount = maximum[1, Horizontal source size /
3144 * Horizontal destination size]
3145 * Vertical down scale amount = maximum[1, Vertical source size /
3146 * Vertical destination size]
3147 * Total down scale amount = Horizontal down scale amount *
3148 * Vertical down scale amount
3149 * """
3150 *
3151 * Return value is provided in 16.16 fixed point form to retain fractional part.
3152 * Caller should take care of dividing & rounding off the value.
3153 */
3154static uint32_t
3155skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3156{
3157 uint32_t downscale_h, downscale_w;
3158 uint32_t src_w, src_h, dst_w, dst_h;
3159
936e71e3 3160 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3161 return DRM_PLANE_HELPER_NO_SCALING;
3162
3163 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3164 src_w = drm_rect_width(&pstate->base.src);
3165 src_h = drm_rect_height(&pstate->base.src);
3166 dst_w = drm_rect_width(&pstate->base.dst);
3167 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3168 if (intel_rotation_90_or_270(pstate->base.rotation))
3169 swap(dst_w, dst_h);
3170
3171 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3172 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3173
3174 /* Provide result in 16.16 fixed point */
3175 return (uint64_t)downscale_w * downscale_h >> 16;
3176}
3177
b9cec075 3178static unsigned int
024c9045
MR		 3179skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3180 const struct drm_plane_state *pstate,
3181 int y)
b9cec075 3182{
a280f7dd 3183 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3184 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3185 uint32_t down_scale_amount, data_rate;
a280f7dd 3186 uint32_t width = 0, height = 0;
a1de91e5
MR		 3187 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3188
936e71e3 3189 if (!intel_pstate->base.visible)
a1de91e5
MR		 3190 return 0;
3191 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3192 return 0;
3193 if (y && format != DRM_FORMAT_NV12)
3194 return 0;
a280f7dd 3195
936e71e3
VS		 3196 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3197 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3198
3199 if (intel_rotation_90_or_270(pstate->rotation))
3200 swap(width, height);
2cd601c6
CK		 3201
3202 /* for planar format */
a1de91e5 3203 if (format == DRM_FORMAT_NV12) {
2cd601c6 3204 if (y) /* y-plane data rate */
8d19d7d9 3205 data_rate = width * height *
a1de91e5 3206 drm_format_plane_cpp(format, 0);
2cd601c6 3207 else /* uv-plane data rate */
8d19d7d9 3208 data_rate = (width / 2) * (height / 2) *
a1de91e5 3209 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3210 } else {
3211 /* for packed formats */
3212 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3213 }
3214
8d19d7d9
KM		 3215 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3216
3217 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3218}
3219
3220/*
3221 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3222 * a 8192x4096@32bpp framebuffer:
3223 * 3 * 4096 * 8192 * 4 < 2^32
3224 */
3225static unsigned int
9c74d826 3226skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3227{
9c74d826
MR		 3228 struct drm_crtc_state *cstate = &intel_cstate->base;
3229 struct drm_atomic_state *state = cstate->state;
3230 struct drm_crtc *crtc = cstate->crtc;
3231 struct drm_device *dev = crtc->dev;
3232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3233 const struct drm_plane *plane;
024c9045 3234 const struct intel_plane *intel_plane;
a6d3460e 3235 struct drm_plane_state *pstate;
a1de91e5 3236 unsigned int rate, total_data_rate = 0;
9c74d826 3237 int id;
a6d3460e
MR		 3238 int i;
3239
3240 if (WARN_ON(!state))
3241 return 0;
b9cec075 3242
a1de91e5 3243 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3244 for_each_plane_in_state(state, plane, pstate, i) {
3245 id = skl_wm_plane_id(to_intel_plane(plane));
3246 intel_plane = to_intel_plane(plane);
3247
3248 if (intel_plane->pipe != intel_crtc->pipe)
3249 continue;
3250
3251 /* packed/uv */
3252 rate = skl_plane_relative_data_rate(intel_cstate,
3253 pstate, 0);
3254 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3255
3256 /* y-plane */
3257 rate = skl_plane_relative_data_rate(intel_cstate,
3258 pstate, 1);
3259 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3260 }
024c9045 3261
a1de91e5
MR		 3262 /* Calculate CRTC's total data rate from cached values */
3263 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3264 int id = skl_wm_plane_id(intel_plane);
024c9045 3265
a1de91e5 3266 /* packed/uv */
9c74d826
MR		 3267 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3268 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3269 }
3270
3271 return total_data_rate;
3272}
3273
cbcfd14b
KM		 3274static uint16_t
3275skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3276 const int y)
3277{
3278 struct drm_framebuffer *fb = pstate->fb;
3279 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3280 uint32_t src_w, src_h;
3281 uint32_t min_scanlines = 8;
3282 uint8_t plane_bpp;
3283
3284 if (WARN_ON(!fb))
3285 return 0;
3286
3287 /* For packed formats, no y-plane, return 0 */
3288 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3289 return 0;
3290
3291 /* For Non Y-tile return 8-blocks */
3292 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3293 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3294 return 8;
3295
936e71e3
VS		 3296 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3297 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3298
3299 if (intel_rotation_90_or_270(pstate->rotation))
3300 swap(src_w, src_h);
3301
3302 /* Halve UV plane width and height for NV12 */
3303 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3304 src_w /= 2;
3305 src_h /= 2;
3306 }
3307
3308 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3309 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3310 else
3311 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3312
3313 if (intel_rotation_90_or_270(pstate->rotation)) {
3314 switch (plane_bpp) {
3315 case 1:
3316 min_scanlines = 32;
3317 break;
3318 case 2:
3319 min_scanlines = 16;
3320 break;
3321 case 4:
3322 min_scanlines = 8;
3323 break;
3324 case 8:
3325 min_scanlines = 4;
3326 break;
3327 default:
3328 WARN(1, "Unsupported pixel depth %u for rotation",
3329 plane_bpp);
3330 min_scanlines = 32;
3331 }
3332 }
3333
3334 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3335}
3336
c107acfe 3337static int
024c9045 3338skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3339 struct skl_ddb_allocation *ddb /* out */)
3340{
c107acfe 3341 struct drm_atomic_state *state = cstate->base.state;
024c9045 3342 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3343 struct drm_device *dev = crtc->dev;
3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3345 struct intel_plane *intel_plane;
c107acfe
MR		 3346 struct drm_plane *plane;
3347 struct drm_plane_state *pstate;
b9cec075 3348 enum pipe pipe = intel_crtc->pipe;
34bb56af 3349 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3350 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3351 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3352 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3353 unsigned int total_data_rate;
c107acfe
MR		 3354 int num_active;
3355 int id, i;
b9cec075 3356
a6d3460e
MR		 3357 if (WARN_ON(!state))
3358 return 0;
3359
c107acfe
MR		 3360 if (!cstate->base.active) {
3361 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3362 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3363 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3364 return 0;
3365 }
3366
a6d3460e 3367 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3368 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3369 if (alloc_size == 0) {
3370 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3371 return 0;
b9cec075
DL		 3372 }
3373
c107acfe 3374 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3375 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3376 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3377
3378 alloc_size -= cursor_blocks;
b9cec075 3379
80958155 3380 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3381 for_each_plane_in_state(state, plane, pstate, i) {
3382 intel_plane = to_intel_plane(plane);
3383 id = skl_wm_plane_id(intel_plane);
c107acfe 3384
a6d3460e
MR		 3385 if (intel_plane->pipe != pipe)
3386 continue;
c107acfe 3387
936e71e3 3388 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3389 minimum[id] = 0;
3390 y_minimum[id] = 0;
3391 continue;
3392 }
3393 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3394 minimum[id] = 0;
3395 y_minimum[id] = 0;
3396 continue;
c107acfe 3397 }
a6d3460e 3398
cbcfd14b
KM		 3399 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3400 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3401 }
80958155 3402
c107acfe
MR		 3403 for (i = 0; i < PLANE_CURSOR; i++) {
3404 alloc_size -= minimum[i];
3405 alloc_size -= y_minimum[i];
80958155
DL		 3406 }
3407
b9cec075 3408 /*
80958155
DL		 3409 * 2. Distribute the remaining space in proportion to the amount of
3410 * data each plane needs to fetch from memory.
b9cec075
DL		 3411 *
3412 * FIXME: we may not allocate every single block here.
3413 */
024c9045 3414 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3415 if (total_data_rate == 0)
c107acfe 3416 return 0;
b9cec075 3417
34bb56af 3418 start = alloc->start;
024c9045 3419 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3420 unsigned int data_rate, y_data_rate;
3421 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3422 int id = skl_wm_plane_id(intel_plane);
b9cec075 3423
a1de91e5 3424 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3425
3426 /*
2cd601c6 3427 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3428 * promote the expression to 64 bits to avoid overflowing, the
3429 * result is < available as data_rate / total_data_rate < 1
3430 */
024c9045 3431 plane_blocks = minimum[id];
80958155
DL		 3432 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3433 total_data_rate);
b9cec075 3434
c107acfe
MR		 3435 /* Leave disabled planes at (0,0) */
3436 if (data_rate) {
3437 ddb->plane[pipe][id].start = start;
3438 ddb->plane[pipe][id].end = start + plane_blocks;
3439 }
b9cec075
DL		 3440
3441 start += plane_blocks;
2cd601c6
CK		 3442
3443 /*
3444 * allocation for y_plane part of planar format:
3445 */
a1de91e5
MR		 3446 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3447
3448 y_plane_blocks = y_minimum[id];
3449 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3450 total_data_rate);
2cd601c6 3451
c107acfe
MR		 3452 if (y_data_rate) {
3453 ddb->y_plane[pipe][id].start = start;
3454 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3455 }
a1de91e5
MR		 3456
3457 start += y_plane_blocks;
b9cec075
DL		 3458 }
3459
c107acfe 3460 return 0;
b9cec075
DL		 3461}
3462
5cec258b 3463static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3464{
3465 /* TODO: Take into account the scalers once we support them */
2d112de7 3466 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3467}
3468
3469/*
3470 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3471 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3472 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3473 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3474*/
ac484963 3475static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3476{
3477 uint32_t wm_intermediate_val, ret;
3478
3479 if (latency == 0)
3480 return UINT_MAX;
3481
ac484963 3482 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3483 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3484
3485 return ret;
3486}
3487
3488static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3489 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3490 uint64_t tiling, uint32_t latency)
2d41c0b5 3491{
d4c2aa60
TU		 3492 uint32_t ret;
3493 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3494 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3495
3496 if (latency == 0)
3497 return UINT_MAX;
3498
ac484963 3499 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3500
3501 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3502 tiling == I915_FORMAT_MOD_Yf_TILED) {
3503 plane_bytes_per_line *= 4;
3504 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3505 plane_blocks_per_line /= 4;
055c3ff6
MR		 3506 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3507 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
0fda6568
TU		 3508 } else {
3509 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3510 }
3511
2d41c0b5
PB		 3512 wm_intermediate_val = latency * pixel_rate;
3513 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3514 plane_blocks_per_line;
2d41c0b5
PB		 3515
3516 return ret;
3517}
3518
9c2f7a9d
KM		 3519static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3520 struct intel_plane_state *pstate)
3521{
3522 uint64_t adjusted_pixel_rate;
3523 uint64_t downscale_amount;
3524 uint64_t pixel_rate;
3525
3526 /* Shouldn't reach here on disabled planes... */
936e71e3 3527 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3528 return 0;
3529
3530 /*
3531 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3532 * with additional adjustments for plane-specific scaling.
3533 */
3534 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3535 downscale_amount = skl_plane_downscale_amount(pstate);
3536
3537 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3538 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3539
3540 return pixel_rate;
3541}
3542
55994c2c
MR		 3543static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3544 struct intel_crtc_state *cstate,
3545 struct intel_plane_state *intel_pstate,
3546 uint16_t ddb_allocation,
3547 int level,
3548 uint16_t *out_blocks, /* out */
3549 uint8_t *out_lines, /* out */
3550 bool *enabled /* out */)
2d41c0b5 3551{
33815fa5
MR		 3552 struct drm_plane_state *pstate = &intel_pstate->base;
3553 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3554 uint32_t latency = dev_priv->wm.skl_latency[level];
3555 uint32_t method1, method2;
3556 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3557 uint32_t res_blocks, res_lines;
3558 uint32_t selected_result;
ac484963 3559 uint8_t cpp;
a280f7dd 3560 uint32_t width = 0, height = 0;
9c2f7a9d 3561 uint32_t plane_pixel_rate;
2d41c0b5 3562
936e71e3 3563 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3564 *enabled = false;
3565 return 0;
3566 }
2d41c0b5 3567
936e71e3
VS		 3568 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3569 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3570
33815fa5 3571 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3572 swap(width, height);
3573
ac484963 3574 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3575 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3576
3577 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3578 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3579 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3580 width,
3581 cpp,
3582 fb->modifier[0],
d4c2aa60 3583 latency);
2d41c0b5 3584
a280f7dd 3585 plane_bytes_per_line = width * cpp;
d4c2aa60 3586 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3587
024c9045
MR		 3588 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3589 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3590 uint32_t min_scanlines = 4;
3591 uint32_t y_tile_minimum;
33815fa5 3592 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3593 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3594 drm_format_plane_cpp(fb->pixel_format, 1) :
3595 drm_format_plane_cpp(fb->pixel_format, 0);
3596
ac484963 3597 switch (cpp) {
1fc0a8f7
TU		 3598 case 1:
3599 min_scanlines = 16;
3600 break;
3601 case 2:
3602 min_scanlines = 8;
3603 break;
3604 case 8:
3605 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3606 }
1fc0a8f7
TU		 3607 }
3608 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3609 selected_result = max(method2, y_tile_minimum);
3610 } else {
3611 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3612 selected_result = min(method1, method2);
3613 else
3614 selected_result = method1;
3615 }
2d41c0b5 3616
d4c2aa60
TU		 3617 res_blocks = selected_result + 1;
3618 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3619
0fda6568 3620 if (level >= 1 && level <= 7) {
024c9045
MR		 3621 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3622 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3623 res_lines += 4;
3624 else
3625 res_blocks++;
3626 }
e6d66171 3627
55994c2c
MR		 3628 if (res_blocks >= ddb_allocation || res_lines > 31) {
3629 *enabled = false;
6b6bada7
MR		 3630
3631 /*
3632 * If there are no valid level 0 watermarks, then we can't
3633 * support this display configuration.
3634 */
3635 if (level) {
3636 return 0;
3637 } else {
3638 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3639 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3640 to_intel_crtc(cstate->base.crtc)->pipe,
3641 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3642 res_blocks, ddb_allocation, res_lines);
3643
3644 return -EINVAL;
3645 }
55994c2c 3646 }
e6d66171
DL		 3647
3648 *out_blocks = res_blocks;
3649 *out_lines = res_lines;
55994c2c 3650 *enabled = true;
2d41c0b5 3651
55994c2c 3652 return 0;
2d41c0b5
PB		 3653}
3654
f4a96752
MR		 3655static int
3656skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3657 struct skl_ddb_allocation *ddb,
3658 struct intel_crtc_state *cstate,
3659 int level,
3660 struct skl_wm_level *result)
2d41c0b5 3661{
f4a96752 3662 struct drm_atomic_state *state = cstate->base.state;
024c9045 3663 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3664 struct drm_plane *plane;
024c9045 3665 struct intel_plane *intel_plane;
33815fa5 3666 struct intel_plane_state *intel_pstate;
2d41c0b5 3667 uint16_t ddb_blocks;
024c9045 3668 enum pipe pipe = intel_crtc->pipe;
55994c2c 3669 int ret;
024c9045 3670
f4a96752
MR		 3671 /*
3672 * We'll only calculate watermarks for planes that are actually
3673 * enabled, so make sure all other planes are set as disabled.
3674 */
3675 memset(result, 0, sizeof(*result));
3676
91c8a326
CW		 3677 for_each_intel_plane_mask(&dev_priv->drm,
3678 intel_plane,
3679 cstate->base.plane_mask) {
024c9045 3680 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3681
f4a96752
MR		 3682 plane = &intel_plane->base;
3683 intel_pstate = NULL;
3684 if (state)
3685 intel_pstate =
3686 intel_atomic_get_existing_plane_state(state,
3687 intel_plane);
3688
3689 /*
3690 * Note: If we start supporting multiple pending atomic commits
3691 * against the same planes/CRTC's in the future, plane->state
3692 * will no longer be the correct pre-state to use for the
3693 * calculations here and we'll need to change where we get the
3694 * 'unchanged' plane data from.
3695 *
3696 * For now this is fine because we only allow one queued commit
3697 * against a CRTC. Even if the plane isn't modified by this
3698 * transaction and we don't have a plane lock, we still have
3699 * the CRTC's lock, so we know that no other transactions are
3700 * racing with us to update it.
3701 */
3702 if (!intel_pstate)
3703 intel_pstate = to_intel_plane_state(plane->state);
3704
3705 WARN_ON(!intel_pstate->base.fb);
3706
2d41c0b5
PB		 3707 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3708
55994c2c
MR		 3709 ret = skl_compute_plane_wm(dev_priv,
3710 cstate,
3711 intel_pstate,
3712 ddb_blocks,
3713 level,
3714 &result->plane_res_b[i],
3715 &result->plane_res_l[i],
3716 &result->plane_en[i]);
3717 if (ret)
3718 return ret;
2d41c0b5 3719 }
f4a96752
MR		 3720
3721 return 0;
2d41c0b5
PB		 3722}
3723
407b50f3 3724static uint32_t
024c9045 3725skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3726{
024c9045 3727 if (!cstate->base.active)
407b50f3
DL		 3728 return 0;
3729
024c9045 3730 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3731 return 0;
407b50f3 3732
024c9045
MR		 3733 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3734 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3735}
3736
024c9045 3737static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3738 struct skl_wm_level *trans_wm /* out */)
407b50f3 3739{
024c9045 3740 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3742 struct intel_plane *intel_plane;
9414f563 3743
024c9045 3744 if (!cstate->base.active)
407b50f3 3745 return;
9414f563
DL		 3746
3747 /* Until we know more, just disable transition WMs */
024c9045
MR		 3748 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3749 int i = skl_wm_plane_id(intel_plane);
3750
9414f563 3751 trans_wm->plane_en[i] = false;
024c9045 3752 }
407b50f3
DL		 3753}
3754
55994c2c
MR		 3755static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3756 struct skl_ddb_allocation *ddb,
3757 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3758{
024c9045 3759 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3760 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3761 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3762 int ret;
2d41c0b5
PB		 3763
3764 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3765 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3766 level, &pipe_wm->wm[level]);
3767 if (ret)
3768 return ret;
2d41c0b5 3769 }
024c9045 3770 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3771
024c9045 3772 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3773
3774 return 0;
2d41c0b5
PB		 3775}
3776
3777static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3778 struct skl_pipe_wm *p_wm,
3779 struct skl_wm_values *r,
3780 struct intel_crtc *intel_crtc)
3781{
3782 int level, max_level = ilk_wm_max_level(dev);
3783 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3784 uint32_t temp;
3785 int i;
2d41c0b5
PB		 3786
3787 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3788 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3789 temp = 0;
2d41c0b5
PB		 3790
3791 temp |= p_wm->wm[level].plane_res_l[i] <<
3792 PLANE_WM_LINES_SHIFT;
3793 temp |= p_wm->wm[level].plane_res_b[i];
3794 if (p_wm->wm[level].plane_en[i])
3795 temp |= PLANE_WM_EN;
3796
3797 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3798 }
3799
3800 temp = 0;
2d41c0b5 3801
4969d33e
MR		 3802 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3803 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3804
4969d33e 3805 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3806 temp |= PLANE_WM_EN;
3807
4969d33e 3808 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3809
3810 }
3811
9414f563
DL		 3812 /* transition WMs */
3813 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3814 temp = 0;
3815 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3816 temp |= p_wm->trans_wm.plane_res_b[i];
3817 if (p_wm->trans_wm.plane_en[i])
3818 temp |= PLANE_WM_EN;
3819
3820 r->plane_trans[pipe][i] = temp;
3821 }
3822
3823 temp = 0;
4969d33e
MR		 3824 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3825 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3826 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3827 temp |= PLANE_WM_EN;
3828
4969d33e 3829 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3830
2d41c0b5
PB		 3831 r->wm_linetime[pipe] = p_wm->linetime;
3832}
3833
f0f59a00
VS		 3834static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3835 i915_reg_t reg,
16160e3d
DL		 3836 const struct skl_ddb_entry *entry)
3837{
3838 if (entry->end)
3839 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3840 else
3841 I915_WRITE(reg, 0);
3842}
3843
62e0fb88
L		 3844void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3845 const struct skl_wm_values *wm,
3846 int plane)
3847{
3848 struct drm_crtc *crtc = &intel_crtc->base;
3849 struct drm_device *dev = crtc->dev;
3850 struct drm_i915_private *dev_priv = to_i915(dev);
3851 int level, max_level = ilk_wm_max_level(dev);
3852 enum pipe pipe = intel_crtc->pipe;
3853
3854 for (level = 0; level <= max_level; level++) {
3855 I915_WRITE(PLANE_WM(pipe, plane, level),
3856 wm->plane[pipe][plane][level]);
3857 }
3858 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
27082493
L		 3859
3860 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3861 &wm->ddb.plane[pipe][plane]);
3862 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3863 &wm->ddb.y_plane[pipe][plane]);
62e0fb88
L		 3864}
3865
3866void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3867 const struct skl_wm_values *wm)
3868{
3869 struct drm_crtc *crtc = &intel_crtc->base;
3870 struct drm_device *dev = crtc->dev;
3871 struct drm_i915_private *dev_priv = to_i915(dev);
3872 int level, max_level = ilk_wm_max_level(dev);
3873 enum pipe pipe = intel_crtc->pipe;
3874
3875 for (level = 0; level <= max_level; level++) {
3876 I915_WRITE(CUR_WM(pipe, level),
3877 wm->plane[pipe][PLANE_CURSOR][level]);
3878 }
3879 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3880
27082493
L		 3881 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3882 &wm->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3883}
3884
27082493
L		 3885bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3886 const struct skl_ddb_allocation *new,
3887 enum pipe pipe)
0e8fb7ba 3888{
27082493
L		 3889 return new->pipe[pipe].start == old->pipe[pipe].start &&
3890 new->pipe[pipe].end == old->pipe[pipe].end;
0e8fb7ba
DL		 3891}
3892
27082493
L		 3893static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3894 const struct skl_ddb_entry *b)
0e8fb7ba 3895{
27082493 3896 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3897}
3898
27082493
L		 3899bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3900 const struct skl_ddb_allocation *old,
3901 const struct skl_ddb_allocation *new,
3902 enum pipe pipe)
0e8fb7ba 3903{
27082493
L		 3904 struct drm_device *dev = state->dev;
3905 struct intel_crtc *intel_crtc;
3906 enum pipe otherp;
0e8fb7ba 3907
27082493
L		 3908 for_each_intel_crtc(dev, intel_crtc) {
3909 otherp = intel_crtc->pipe;
0e8fb7ba 3910
27082493 3911 if (otherp == pipe)
0e8fb7ba
DL		 3912 continue;
3913
27082493
L		 3914 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3915 &old->pipe[otherp]))
3916 return true;
0e8fb7ba
DL		 3917 }
3918
27082493 3919 return false;
0e8fb7ba
DL		 3920}
3921
55994c2c
MR		 3922static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3923 struct skl_ddb_allocation *ddb, /* out */
3924 struct skl_pipe_wm *pipe_wm, /* out */
3925 bool *changed /* out */)
2d41c0b5 3926{
f4a96752
MR		 3927 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3928 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3929 int ret;
2d41c0b5 3930
55994c2c
MR		 3931 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3932 if (ret)
3933 return ret;
2d41c0b5 3934
4e0963c7 3935 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3936 *changed = false;
3937 else
3938 *changed = true;
2d41c0b5 3939
55994c2c 3940 return 0;
2d41c0b5
PB		 3941}
3942
9b613022
MR		 3943static uint32_t
3944pipes_modified(struct drm_atomic_state *state)
3945{
3946 struct drm_crtc *crtc;
3947 struct drm_crtc_state *cstate;
3948 uint32_t i, ret = 0;
3949
3950 for_each_crtc_in_state(state, crtc, cstate, i)
3951 ret |= drm_crtc_mask(crtc);
3952
3953 return ret;
3954}
3955
98d39494
MR		 3956static int
3957skl_compute_ddb(struct drm_atomic_state *state)
3958{
3959 struct drm_device *dev = state->dev;
3960 struct drm_i915_private *dev_priv = to_i915(dev);
3961 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3962 struct intel_crtc *intel_crtc;
734fa01f 3963 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3964 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3965 int ret;
3966
3967 /*
3968 * If this is our first atomic update following hardware readout,
3969 * we can't trust the DDB that the BIOS programmed for us. Let's
3970 * pretend that all pipes switched active status so that we'll
3971 * ensure a full DDB recompute.
3972 */
1b54a880
MR		 3973 if (dev_priv->wm.distrust_bios_wm) {
3974 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3975 state->acquire_ctx);
3976 if (ret)
3977 return ret;
3978
98d39494
MR		 3979 intel_state->active_pipe_changes = ~0;
3980
1b54a880
MR		 3981 /*
3982 * We usually only initialize intel_state->active_crtcs if we
3983 * we're doing a modeset; make sure this field is always
3984 * initialized during the sanitization process that happens
3985 * on the first commit too.
3986 */
3987 if (!intel_state->modeset)
3988 intel_state->active_crtcs = dev_priv->active_crtcs;
3989 }
3990
98d39494
MR		 3991 /*
3992 * If the modeset changes which CRTC's are active, we need to
3993 * recompute the DDB allocation for *all* active pipes, even
3994 * those that weren't otherwise being modified in any way by this
3995 * atomic commit. Due to the shrinking of the per-pipe allocations
3996 * when new active CRTC's are added, it's possible for a pipe that
3997 * we were already using and aren't changing at all here to suddenly
3998 * become invalid if its DDB needs exceeds its new allocation.
3999 *
4000 * Note that if we wind up doing a full DDB recompute, we can't let
4001 * any other display updates race with this transaction, so we need
4002 * to grab the lock on *all* CRTC's.
4003 */
734fa01f 4004 if (intel_state->active_pipe_changes) {
98d39494 4005 realloc_pipes = ~0;
734fa01f
MR		 4006 intel_state->wm_results.dirty_pipes = ~0;
4007 }
98d39494
MR		 4008
4009 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4010 struct intel_crtc_state *cstate;
4011
4012 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4013 if (IS_ERR(cstate))
4014 return PTR_ERR(cstate);
4015
734fa01f 4016 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4017 if (ret)
4018 return ret;
05a76d3d
L		 4019
4020 ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
4021 if (ret)
4022 return ret;
98d39494
MR		 4023 }
4024
4025 return 0;
4026}
4027
2722efb9
MR		 4028static void
4029skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4030 struct skl_wm_values *src,
4031 enum pipe pipe)
4032{
4033 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4034 memcpy(dst->plane[pipe], src->plane[pipe],
4035 sizeof(dst->plane[pipe]));
4036 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4037 sizeof(dst->plane_trans[pipe]));
4038
4039 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4040 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4041 sizeof(dst->ddb.y_plane[pipe]));
4042 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4043 sizeof(dst->ddb.plane[pipe]));
4044}
4045
98d39494
MR		 4046static int
4047skl_compute_wm(struct drm_atomic_state *state)
4048{
4049 struct drm_crtc *crtc;
4050 struct drm_crtc_state *cstate;
734fa01f
MR		 4051 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4052 struct skl_wm_values *results = &intel_state->wm_results;
4053 struct skl_pipe_wm *pipe_wm;
98d39494 4054 bool changed = false;
734fa01f 4055 int ret, i;
98d39494
MR		 4056
4057 /*
4058 * If this transaction isn't actually touching any CRTC's, don't
4059 * bother with watermark calculation. Note that if we pass this
4060 * test, we're guaranteed to hold at least one CRTC state mutex,
4061 * which means we can safely use values like dev_priv->active_crtcs
4062 * since any racing commits that want to update them would need to
4063 * hold _all_ CRTC state mutexes.
4064 */
4065 for_each_crtc_in_state(state, crtc, cstate, i)
4066 changed = true;
4067 if (!changed)
4068 return 0;
4069
734fa01f
MR		 4070 /* Clear all dirty flags */
4071 results->dirty_pipes = 0;
4072
98d39494
MR		 4073 ret = skl_compute_ddb(state);
4074 if (ret)
4075 return ret;
4076
734fa01f
MR		 4077 /*
4078 * Calculate WM's for all pipes that are part of this transaction.
4079 * Note that the DDB allocation above may have added more CRTC's that
4080 * weren't otherwise being modified (and set bits in dirty_pipes) if
4081 * pipe allocations had to change.
4082 *
4083 * FIXME: Now that we're doing this in the atomic check phase, we
4084 * should allow skl_update_pipe_wm() to return failure in cases where
4085 * no suitable watermark values can be found.
4086 */
4087 for_each_crtc_in_state(state, crtc, cstate, i) {
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 struct intel_crtc_state *intel_cstate =
4090 to_intel_crtc_state(cstate);
4091
4092 pipe_wm = &intel_cstate->wm.skl.optimal;
4093 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4094 &changed);
4095 if (ret)
4096 return ret;
4097
4098 if (changed)
4099 results->dirty_pipes |= drm_crtc_mask(crtc);
4100
4101 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4102 /* This pipe's WM's did not change */
4103 continue;
4104
4105 intel_cstate->update_wm_pre = true;
4106 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4107 }
4108
98d39494
MR		 4109 return 0;
4110}
4111
2d41c0b5
PB		 4112static void skl_update_wm(struct drm_crtc *crtc)
4113{
4114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4115 struct drm_device *dev = crtc->dev;
fac5e23e 4116 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4117 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4118 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4119 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4120 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4121 enum pipe pipe = intel_crtc->pipe;
adda50b8 4122
734fa01f 4123 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4124 return;
4125
734fa01f
MR		 4126 intel_crtc->wm.active.skl = *pipe_wm;
4127
4128 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4129
2722efb9 4130 /*
27082493
L		 4131 * If this pipe isn't active already, we're going to be enabling it
4132 * very soon. Since it's safe to update a pipe's ddb allocation while
4133 * the pipe's shut off, just do so here. Already active pipes will have
4134 * their watermarks updated once we update their planes.
2722efb9 4135 */
27082493
L		 4136 if (crtc->state->active_changed) {
4137 int plane;
4138
4139 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4140 skl_write_plane_wm(intel_crtc, results, plane);
4141
4142 skl_write_cursor_wm(intel_crtc, results);
4143 }
4144
4145 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4146
4147 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4148}
4149
d890565c
VS		 4150static void ilk_compute_wm_config(struct drm_device *dev,
4151 struct intel_wm_config *config)
4152{
4153 struct intel_crtc *crtc;
4154
4155 /* Compute the currently _active_ config */
4156 for_each_intel_crtc(dev, crtc) {
4157 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4158
4159 if (!wm->pipe_enabled)
4160 continue;
4161
4162 config->sprites_enabled |= wm->sprites_enabled;
4163 config->sprites_scaled |= wm->sprites_scaled;
4164 config->num_pipes_active++;
4165 }
4166}
4167
ed4a6a7c 4168static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4169{
91c8a326 4170 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4171 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4172 struct ilk_wm_maximums max;
d890565c 4173 struct intel_wm_config config = {};
820c1980 4174 struct ilk_wm_values results = {};
77c122bc 4175 enum intel_ddb_partitioning partitioning;
261a27d1 4176
d890565c
VS		 4177 ilk_compute_wm_config(dev, &config);
4178
4179 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4180 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4181
4182 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4183 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4184 config.num_pipes_active == 1 && config.sprites_enabled) {
4185 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4186 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4187
820c1980 4188 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4189 } else {
198a1e9b 4190 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4191 }
4192
198a1e9b 4193 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4194 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4195
820c1980 4196 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4197
820c1980 4198 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4199}
4200
ed4a6a7c 4201static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4202{
ed4a6a7c
MR		 4203 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4204 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4205
ed4a6a7c 4206 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4207 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4208 ilk_program_watermarks(dev_priv);
4209 mutex_unlock(&dev_priv->wm.wm_mutex);
4210}
bf220452 4211
ed4a6a7c
MR		 4212static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4213{
4214 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4215 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4216
ed4a6a7c
MR		 4217 mutex_lock(&dev_priv->wm.wm_mutex);
4218 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4219 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4220 ilk_program_watermarks(dev_priv);
4221 }
4222 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4223}
4224
3078999f
PB		 4225static void skl_pipe_wm_active_state(uint32_t val,
4226 struct skl_pipe_wm *active,
4227 bool is_transwm,
4228 bool is_cursor,
4229 int i,
4230 int level)
4231{
4232 bool is_enabled = (val & PLANE_WM_EN) != 0;
4233
4234 if (!is_transwm) {
4235 if (!is_cursor) {
4236 active->wm[level].plane_en[i] = is_enabled;
4237 active->wm[level].plane_res_b[i] =
4238 val & PLANE_WM_BLOCKS_MASK;
4239 active->wm[level].plane_res_l[i] =
4240 (val >> PLANE_WM_LINES_SHIFT) &
4241 PLANE_WM_LINES_MASK;
4242 } else {
4969d33e
MR		 4243 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4244 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4245 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4246 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4247 (val >> PLANE_WM_LINES_SHIFT) &
4248 PLANE_WM_LINES_MASK;
4249 }
4250 } else {
4251 if (!is_cursor) {
4252 active->trans_wm.plane_en[i] = is_enabled;
4253 active->trans_wm.plane_res_b[i] =
4254 val & PLANE_WM_BLOCKS_MASK;
4255 active->trans_wm.plane_res_l[i] =
4256 (val >> PLANE_WM_LINES_SHIFT) &
4257 PLANE_WM_LINES_MASK;
4258 } else {
4969d33e
MR		 4259 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4260 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4261 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4262 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4263 (val >> PLANE_WM_LINES_SHIFT) &
4264 PLANE_WM_LINES_MASK;
4265 }
4266 }
4267}
4268
4269static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4270{
4271 struct drm_device *dev = crtc->dev;
fac5e23e 4272 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4273 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4275 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4276 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4277 enum pipe pipe = intel_crtc->pipe;
4278 int level, i, max_level;
4279 uint32_t temp;
4280
4281 max_level = ilk_wm_max_level(dev);
4282
4283 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4284
4285 for (level = 0; level <= max_level; level++) {
4286 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4287 hw->plane[pipe][i][level] =
4288 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4289 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4290 }
4291
4292 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4293 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4294 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4295
3ef00284 4296 if (!intel_crtc->active)
3078999f
PB		 4297 return;
4298
2b4b9f35 4299 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4300
4301 active->linetime = hw->wm_linetime[pipe];
4302
4303 for (level = 0; level <= max_level; level++) {
4304 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4305 temp = hw->plane[pipe][i][level];
4306 skl_pipe_wm_active_state(temp, active, false,
4307 false, i, level);
4308 }
4969d33e 4309 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4310 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4311 }
4312
4313 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4314 temp = hw->plane_trans[pipe][i];
4315 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4316 }
4317
4969d33e 4318 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4319 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4320
4321 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4322}
4323
4324void skl_wm_get_hw_state(struct drm_device *dev)
4325{
fac5e23e 4326 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4327 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4328 struct drm_crtc *crtc;
4329
a269c583 4330 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4331 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4332 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4333
279e99d7
MR		 4334 if (dev_priv->active_crtcs) {
4335 /* Fully recompute DDB on first atomic commit */
4336 dev_priv->wm.distrust_bios_wm = true;
4337 } else {
4338 /* Easy/common case; just sanitize DDB now if everything off */
4339 memset(ddb, 0, sizeof(*ddb));
4340 }
3078999f
PB		 4341}
4342
243e6a44
VS		 4343static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4344{
4345 struct drm_device *dev = crtc->dev;
fac5e23e 4346 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4347 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4349 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4350 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4351 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4352 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4353 [PIPE_A] = WM0_PIPEA_ILK,
4354 [PIPE_B] = WM0_PIPEB_ILK,
4355 [PIPE_C] = WM0_PIPEC_IVB,
4356 };
4357
4358 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4359 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4360 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4361
15606534
VS		 4362 memset(active, 0, sizeof(*active));
4363
3ef00284 4364 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4365
4366 if (active->pipe_enabled) {
243e6a44
VS		 4367 u32 tmp = hw->wm_pipe[pipe];
4368
4369 /*
4370 * For active pipes LP0 watermark is marked as
4371 * enabled, and LP1+ watermaks as disabled since
4372 * we can't really reverse compute them in case
4373 * multiple pipes are active.
4374 */
4375 active->wm[0].enable = true;
4376 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4377 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4378 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4379 active->linetime = hw->wm_linetime[pipe];
4380 } else {
4381 int level, max_level = ilk_wm_max_level(dev);
4382
4383 /*
4384 * For inactive pipes, all watermark levels
4385 * should be marked as enabled but zeroed,
4386 * which is what we'd compute them to.
4387 */
4388 for (level = 0; level <= max_level; level++)
4389 active->wm[level].enable = true;
4390 }
4e0963c7
MR		 4391
4392 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4393}
4394
6eb1a681
VS		 4395#define _FW_WM(value, plane) \
4396 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4397#define _FW_WM_VLV(value, plane) \
4398 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4399
4400static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4401 struct vlv_wm_values *wm)
4402{
4403 enum pipe pipe;
4404 uint32_t tmp;
4405
4406 for_each_pipe(dev_priv, pipe) {
4407 tmp = I915_READ(VLV_DDL(pipe));
4408
4409 wm->ddl[pipe].primary =
4410 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4411 wm->ddl[pipe].cursor =
4412 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4413 wm->ddl[pipe].sprite[0] =
4414 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4415 wm->ddl[pipe].sprite[1] =
4416 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4417 }
4418
4419 tmp = I915_READ(DSPFW1);
4420 wm->sr.plane = _FW_WM(tmp, SR);
4421 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4422 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4423 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4424
4425 tmp = I915_READ(DSPFW2);
4426 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4427 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4428 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4429
4430 tmp = I915_READ(DSPFW3);
4431 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4432
4433 if (IS_CHERRYVIEW(dev_priv)) {
4434 tmp = I915_READ(DSPFW7_CHV);
4435 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4436 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4437
4438 tmp = I915_READ(DSPFW8_CHV);
4439 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4440 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4441
4442 tmp = I915_READ(DSPFW9_CHV);
4443 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4444 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4445
4446 tmp = I915_READ(DSPHOWM);
4447 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4448 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4449 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4450 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4451 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4452 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4453 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4454 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4455 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4456 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4457 } else {
4458 tmp = I915_READ(DSPFW7);
4459 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4460 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4461
4462 tmp = I915_READ(DSPHOWM);
4463 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4464 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4465 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4466 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4467 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4468 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4469 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4470 }
4471}
4472
4473#undef _FW_WM
4474#undef _FW_WM_VLV
4475
4476void vlv_wm_get_hw_state(struct drm_device *dev)
4477{
4478 struct drm_i915_private *dev_priv = to_i915(dev);
4479 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4480 struct intel_plane *plane;
4481 enum pipe pipe;
4482 u32 val;
4483
4484 vlv_read_wm_values(dev_priv, wm);
4485
4486 for_each_intel_plane(dev, plane) {
4487 switch (plane->base.type) {
4488 int sprite;
4489 case DRM_PLANE_TYPE_CURSOR:
4490 plane->wm.fifo_size = 63;
4491 break;
4492 case DRM_PLANE_TYPE_PRIMARY:
4493 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4494 break;
4495 case DRM_PLANE_TYPE_OVERLAY:
4496 sprite = plane->plane;
4497 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4498 break;
4499 }
4500 }
4501
4502 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4503 wm->level = VLV_WM_LEVEL_PM2;
4504
4505 if (IS_CHERRYVIEW(dev_priv)) {
4506 mutex_lock(&dev_priv->rps.hw_lock);
4507
4508 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4509 if (val & DSP_MAXFIFO_PM5_ENABLE)
4510 wm->level = VLV_WM_LEVEL_PM5;
4511
58590c14
VS		 4512 /*
4513 * If DDR DVFS is disabled in the BIOS, Punit
4514 * will never ack the request. So if that happens
4515 * assume we don't have to enable/disable DDR DVFS
4516 * dynamically. To test that just set the REQ_ACK
4517 * bit to poke the Punit, but don't change the
4518 * HIGH/LOW bits so that we don't actually change
4519 * the current state.
4520 */
6eb1a681 4521 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4522 val |= FORCE_DDR_FREQ_REQ_ACK;
4523 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4524
4525 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4526 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4527 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4528 "assuming DDR DVFS is disabled\n");
4529 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4530 } else {
4531 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4532 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4533 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4534 }
6eb1a681
VS		 4535
4536 mutex_unlock(&dev_priv->rps.hw_lock);
4537 }
4538
4539 for_each_pipe(dev_priv, pipe)
4540 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4541 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4542 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4543
4544 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4545 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4546}
4547
243e6a44
VS		 4548void ilk_wm_get_hw_state(struct drm_device *dev)
4549{
fac5e23e 4550 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4551 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4552 struct drm_crtc *crtc;
4553
70e1e0ec 4554 for_each_crtc(dev, crtc)
243e6a44
VS		 4555 ilk_pipe_wm_get_hw_state(crtc);
4556
4557 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4558 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4559 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4560
4561 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4562 if (INTEL_INFO(dev)->gen >= 7) {
4563 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4564 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4565 }
243e6a44 4566
a42a5719 4567 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4568 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4569 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4570 else if (IS_IVYBRIDGE(dev))
4571 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4572 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4573
4574 hw->enable_fbc_wm =
4575 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4576}
4577
b445e3b0
ED		 4578/**
4579 * intel_update_watermarks - update FIFO watermark values based on current modes
4580 *
4581 * Calculate watermark values for the various WM regs based on current mode
4582 * and plane configuration.
4583 *
4584 * There are several cases to deal with here:
4585 * - normal (i.e. non-self-refresh)
4586 * - self-refresh (SR) mode
4587 * - lines are large relative to FIFO size (buffer can hold up to 2)
4588 * - lines are small relative to FIFO size (buffer can hold more than 2
4589 * lines), so need to account for TLB latency
4590 *
4591 * The normal calculation is:
4592 * watermark = dotclock * bytes per pixel * latency
4593 * where latency is platform & configuration dependent (we assume pessimal
4594 * values here).
4595 *
4596 * The SR calculation is:
4597 * watermark = (trunc(latency/line time)+1) * surface width *
4598 * bytes per pixel
4599 * where
4600 * line time = htotal / dotclock
4601 * surface width = hdisplay for normal plane and 64 for cursor
4602 * and latency is assumed to be high, as above.
4603 *
4604 * The final value programmed to the register should always be rounded up,
4605 * and include an extra 2 entries to account for clock crossings.
4606 *
4607 * We don't use the sprite, so we can ignore that. And on Crestline we have
4608 * to set the non-SR watermarks to 8.
4609 */
46ba614c 4610void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4611{
fac5e23e 4612 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4613
4614 if (dev_priv->display.update_wm)
46ba614c 4615 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4616}
4617
e2828914 4618/*
9270388e 4619 * Lock protecting IPS related data structures
9270388e
DV		 4620 */
4621DEFINE_SPINLOCK(mchdev_lock);
4622
4623/* Global for IPS driver to get at the current i915 device. Protected by
4624 * mchdev_lock. */
4625static struct drm_i915_private *i915_mch_dev;
4626
91d14251 4627bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4628{
2b4e57bd
ED		 4629 u16 rgvswctl;
4630
9270388e
DV		 4631 assert_spin_locked(&mchdev_lock);
4632
2b4e57bd
ED		 4633 rgvswctl = I915_READ16(MEMSWCTL);
4634 if (rgvswctl & MEMCTL_CMD_STS) {
4635 DRM_DEBUG("gpu busy, RCS change rejected\n");
4636 return false; /* still busy with another command */
4637 }
4638
4639 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4640 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4641 I915_WRITE16(MEMSWCTL, rgvswctl);
4642 POSTING_READ16(MEMSWCTL);
4643
4644 rgvswctl |= MEMCTL_CMD_STS;
4645 I915_WRITE16(MEMSWCTL, rgvswctl);
4646
4647 return true;
4648}
4649
91d14251 4650static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4651{
84f1b20f 4652 u32 rgvmodectl;
2b4e57bd
ED		 4653 u8 fmax, fmin, fstart, vstart;
4654
9270388e
DV		 4655 spin_lock_irq(&mchdev_lock);
4656
84f1b20f
TU		 4657 rgvmodectl = I915_READ(MEMMODECTL);
4658
2b4e57bd
ED		 4659 /* Enable temp reporting */
4660 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4661 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4662
4663 /* 100ms RC evaluation intervals */
4664 I915_WRITE(RCUPEI, 100000);
4665 I915_WRITE(RCDNEI, 100000);
4666
4667 /* Set max/min thresholds to 90ms and 80ms respectively */
4668 I915_WRITE(RCBMAXAVG, 90000);
4669 I915_WRITE(RCBMINAVG, 80000);
4670
4671 I915_WRITE(MEMIHYST, 1);
4672
4673 /* Set up min, max, and cur for interrupt handling */
4674 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4675 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4676 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4677 MEMMODE_FSTART_SHIFT;
4678
616847e7 4679 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4680 PXVFREQ_PX_SHIFT;
4681
20e4d407
DV		 4682 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4683 dev_priv->ips.fstart = fstart;
2b4e57bd 4684
20e4d407
DV		 4685 dev_priv->ips.max_delay = fstart;
4686 dev_priv->ips.min_delay = fmin;
4687 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4688
4689 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4690 fmax, fmin, fstart);
4691
4692 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4693
4694 /*
4695 * Interrupts will be enabled in ironlake_irq_postinstall
4696 */
4697
4698 I915_WRITE(VIDSTART, vstart);
4699 POSTING_READ(VIDSTART);
4700
4701 rgvmodectl |= MEMMODE_SWMODE_EN;
4702 I915_WRITE(MEMMODECTL, rgvmodectl);
4703
9270388e 4704 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4705 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4706 mdelay(1);
2b4e57bd 4707
91d14251 4708 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4709
7d81c3e0
VS		 4710 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4711 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4712 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4713 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4714 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4715
4716 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4717}
4718
91d14251 4719static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4720{
9270388e
DV		 4721 u16 rgvswctl;
4722
4723 spin_lock_irq(&mchdev_lock);
4724
4725 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4726
4727 /* Ack interrupts, disable EFC interrupt */
4728 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4729 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4730 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4731 I915_WRITE(DEIIR, DE_PCU_EVENT);
4732 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4733
4734 /* Go back to the starting frequency */
91d14251 4735 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4736 mdelay(1);
2b4e57bd
ED		 4737 rgvswctl |= MEMCTL_CMD_STS;
4738 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4739 mdelay(1);
2b4e57bd 4740
9270388e 4741 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4742}
4743
acbe9475
DV		 4744/* There's a funny hw issue where the hw returns all 0 when reading from
4745 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4746 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4747 * all limits and the gpu stuck at whatever frequency it is at atm).
4748 */
74ef1173 4749static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4750{
7b9e0ae6 4751 u32 limits;
2b4e57bd 4752
20b46e59
DV		 4753 /* Only set the down limit when we've reached the lowest level to avoid
4754 * getting more interrupts, otherwise leave this clear. This prevents a
4755 * race in the hw when coming out of rc6: There's a tiny window where
4756 * the hw runs at the minimal clock before selecting the desired
4757 * frequency, if the down threshold expires in that window we will not
4758 * receive a down interrupt. */
2d1fe073 4759 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4760 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4761 if (val <= dev_priv->rps.min_freq_softlimit)
4762 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4763 } else {
4764 limits = dev_priv->rps.max_freq_softlimit << 24;
4765 if (val <= dev_priv->rps.min_freq_softlimit)
4766 limits |= dev_priv->rps.min_freq_softlimit << 16;
4767 }
20b46e59
DV		 4768
4769 return limits;
4770}
4771
dd75fdc8
CW		 4772static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4773{
4774 int new_power;
8a586437
AG		 4775 u32 threshold_up = 0, threshold_down = 0; /* in % */
4776 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4777
4778 new_power = dev_priv->rps.power;
4779 switch (dev_priv->rps.power) {
4780 case LOW_POWER:
a72b5623
CW		 4781 if (val > dev_priv->rps.efficient_freq + 1 &&
4782 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4783 new_power = BETWEEN;
4784 break;
4785
4786 case BETWEEN:
a72b5623
CW		 4787 if (val <= dev_priv->rps.efficient_freq &&
4788 val < dev_priv->rps.cur_freq)
dd75fdc8 4789 new_power = LOW_POWER;
a72b5623
CW		 4790 else if (val >= dev_priv->rps.rp0_freq &&
4791 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4792 new_power = HIGH_POWER;
4793 break;
4794
4795 case HIGH_POWER:
a72b5623
CW		 4796 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4797 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4798 new_power = BETWEEN;
4799 break;
4800 }
4801 /* Max/min bins are special */
aed242ff 4802 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4803 new_power = LOW_POWER;
aed242ff 4804 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4805 new_power = HIGH_POWER;
4806 if (new_power == dev_priv->rps.power)
4807 return;
4808
4809 /* Note the units here are not exactly 1us, but 1280ns. */
4810 switch (new_power) {
4811 case LOW_POWER:
4812 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4813 ei_up = 16000;
4814 threshold_up = 95;
dd75fdc8
CW		 4815
4816 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4817 ei_down = 32000;
4818 threshold_down = 85;
dd75fdc8
CW		 4819 break;
4820
4821 case BETWEEN:
4822 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4823 ei_up = 13000;
4824 threshold_up = 90;
dd75fdc8
CW		 4825
4826 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4827 ei_down = 32000;
4828 threshold_down = 75;
dd75fdc8
CW		 4829 break;
4830
4831 case HIGH_POWER:
4832 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4833 ei_up = 10000;
4834 threshold_up = 85;
dd75fdc8
CW		 4835
4836 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4837 ei_down = 32000;
4838 threshold_down = 60;
dd75fdc8
CW		 4839 break;
4840 }
4841
8a586437 4842 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4843 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4844 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4845 GT_INTERVAL_FROM_US(dev_priv,
4846 ei_up * threshold_up / 100));
8a586437
AG		 4847
4848 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4849 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4850 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4851 GT_INTERVAL_FROM_US(dev_priv,
4852 ei_down * threshold_down / 100));
4853
4854 I915_WRITE(GEN6_RP_CONTROL,
4855 GEN6_RP_MEDIA_TURBO |
4856 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4857 GEN6_RP_MEDIA_IS_GFX |
4858 GEN6_RP_ENABLE |
4859 GEN6_RP_UP_BUSY_AVG |
4860 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4861
dd75fdc8 4862 dev_priv->rps.power = new_power;
8fb55197
CW		 4863 dev_priv->rps.up_threshold = threshold_up;
4864 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4865 dev_priv->rps.last_adj = 0;
4866}
4867
2876ce73
CW		 4868static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4869{
4870 u32 mask = 0;
4871
4872 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4873 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4874 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4875 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4876
7b3c29f6
CW		 4877 mask &= dev_priv->pm_rps_events;
4878
59d02a1f 4879 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4880}
4881
b8a5ff8d
JM		 4882/* gen6_set_rps is called to update the frequency request, but should also be
4883 * called when the range (min_delay and max_delay) is modified so that we can
4884 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4885static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4886{
23eafea6 4887 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4888 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4889 return;
4890
4fc688ce 4891 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4892 WARN_ON(val > dev_priv->rps.max_freq);
4893 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4894
eb64cad1
CW		 4895 /* min/max delay may still have been modified so be sure to
4896 * write the limits value.
4897 */
4898 if (val != dev_priv->rps.cur_freq) {
4899 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4900
dc97997a 4901 if (IS_GEN9(dev_priv))
5704195c
AG		 4902 I915_WRITE(GEN6_RPNSWREQ,
4903 GEN9_FREQUENCY(val));
dc97997a 4904 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4905 I915_WRITE(GEN6_RPNSWREQ,
4906 HSW_FREQUENCY(val));
4907 else
4908 I915_WRITE(GEN6_RPNSWREQ,
4909 GEN6_FREQUENCY(val) |
4910 GEN6_OFFSET(0) |
4911 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4912 }
7b9e0ae6 4913
7b9e0ae6
CW		 4914 /* Make sure we continue to get interrupts
4915 * until we hit the minimum or maximum frequencies.
4916 */
74ef1173 4917 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4918 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4919
d5570a72
BW		 4920 POSTING_READ(GEN6_RPNSWREQ);
4921
b39fb297 4922 dev_priv->rps.cur_freq = val;
0f94592e 4923 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4924}
4925
dc97997a 4926static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4927{
ffe02b40 4928 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4929 WARN_ON(val > dev_priv->rps.max_freq);
4930 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4931
dc97997a 4932 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4933 "Odd GPU freq value\n"))
4934 val &= ~1;
4935
cd25dd5b
D		 4936 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4937
8fb55197 4938 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4939 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4940 if (!IS_CHERRYVIEW(dev_priv))
4941 gen6_set_rps_thresholds(dev_priv, val);
4942 }
ffe02b40 4943
ffe02b40
VS		 4944 dev_priv->rps.cur_freq = val;
4945 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4946}
4947
a7f6e231 4948/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4949 *
4950 * * If Gfx is Idle, then
a7f6e231
D		 4951 * 1. Forcewake Media well.
4952 * 2. Request idle freq.
4953 * 3. Release Forcewake of Media well.
76c3552f
D		 4954*/
4955static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4956{
aed242ff 4957 u32 val = dev_priv->rps.idle_freq;
5549d25f 4958
aed242ff 4959 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4960 return;
4961
a7f6e231
D		 4962 /* Wake up the media well, as that takes a lot less
4963 * power than the Render well. */
4964 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4965 valleyview_set_rps(dev_priv, val);
a7f6e231 4966 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4967}
4968
43cf3bf0
CW		 4969void gen6_rps_busy(struct drm_i915_private *dev_priv)
4970{
4971 mutex_lock(&dev_priv->rps.hw_lock);
4972 if (dev_priv->rps.enabled) {
4973 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4974 gen6_rps_reset_ei(dev_priv);
4975 I915_WRITE(GEN6_PMINTRMSK,
4976 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 4977
c33d247d
CW		 4978 gen6_enable_rps_interrupts(dev_priv);
4979
2b83c4c4
MW		 4980 /* Ensure we start at the user's desired frequency */
4981 intel_set_rps(dev_priv,
4982 clamp(dev_priv->rps.cur_freq,
4983 dev_priv->rps.min_freq_softlimit,
4984 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 4985 }
4986 mutex_unlock(&dev_priv->rps.hw_lock);
4987}
4988
b29c19b6
CW		 4989void gen6_rps_idle(struct drm_i915_private *dev_priv)
4990{
c33d247d
CW		 4991 /* Flush our bottom-half so that it does not race with us
4992 * setting the idle frequency and so that it is bounded by
4993 * our rpm wakeref. And then disable the interrupts to stop any
4994 * futher RPS reclocking whilst we are asleep.
4995 */
4996 gen6_disable_rps_interrupts(dev_priv);
4997
b29c19b6 4998 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4999 if (dev_priv->rps.enabled) {
dc97997a 5000 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5001 vlv_set_rps_idle(dev_priv);
7526ed79 5002 else
dc97997a 5003 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5004 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5005 I915_WRITE(GEN6_PMINTRMSK,
5006 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5007 }
8d3afd7d 5008 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5009
8d3afd7d 5010 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5011 while (!list_empty(&dev_priv->rps.clients))
5012 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5013 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5014}
5015
1854d5ca 5016void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5017 struct intel_rps_client *rps,
5018 unsigned long submitted)
b29c19b6 5019{
8d3afd7d
CW		 5020 /* This is intentionally racy! We peek at the state here, then
5021 * validate inside the RPS worker.
5022 */
67d97da3 5023 if (!(dev_priv->gt.awake &&
8d3afd7d 5024 dev_priv->rps.enabled &&
29ecd78d 5025 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5026 return;
43cf3bf0 5027
e61b9958
CW		 5028 /* Force a RPS boost (and don't count it against the client) if
5029 * the GPU is severely congested.
5030 */
d0bc54f2 5031 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5032 rps = NULL;
5033
8d3afd7d
CW		 5034 spin_lock(&dev_priv->rps.client_lock);
5035 if (rps == NULL || list_empty(&rps->link)) {
5036 spin_lock_irq(&dev_priv->irq_lock);
5037 if (dev_priv->rps.interrupts_enabled) {
5038 dev_priv->rps.client_boost = true;
c33d247d 5039 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5040 }
5041 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5042
2e1b8730
CW		 5043 if (rps != NULL) {
5044 list_add(&rps->link, &dev_priv->rps.clients);
5045 rps->boosts++;
1854d5ca
CW		 5046 } else
5047 dev_priv->rps.boosts++;
c0951f0c 5048 }
8d3afd7d 5049 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5050}
5051
dc97997a 5052void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5053{
dc97997a
CW		 5054 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5055 valleyview_set_rps(dev_priv, val);
ffe02b40 5056 else
dc97997a 5057 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5058}
5059
dc97997a 5060static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5061{
20e49366 5062 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5063 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5064}
5065
dc97997a 5066static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5067{
2030d684
AG		 5068 I915_WRITE(GEN6_RP_CONTROL, 0);
5069}
5070
dc97997a 5071static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5072{
d20d4f0c 5073 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5074 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5075 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5076}
5077
dc97997a 5078static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5079{
38807746
D		 5080 I915_WRITE(GEN6_RC_CONTROL, 0);
5081}
5082
dc97997a 5083static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5084{
98a2e5f9
D		 5085 /* we're doing forcewake before Disabling RC6,
5086 * This what the BIOS expects when going into suspend */
59bad947 5087 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5088
44fc7d5c 5089 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5090
59bad947 5091 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5092}
5093
dc97997a 5094static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5095{
dc97997a 5096 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5097 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5098 mode = GEN6_RC_CTL_RC6_ENABLE;
5099 else
5100 mode = 0;
5101 }
dc97997a 5102 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5103 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5104 "RC6 %s RC6p %s RC6pp %s\n",
5105 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5106 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5107 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5108
5109 else
b99d49cc
ID		 5110 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5111 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5112}
5113
dc97997a 5114static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5115{
72e96d64 5116 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5117 bool enable_rc6 = true;
5118 unsigned long rc6_ctx_base;
fc619841
ID		 5119 u32 rc_ctl;
5120 int rc_sw_target;
5121
5122 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5123 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5124 RC_SW_TARGET_STATE_SHIFT;
5125 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5126 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5127 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5128 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5129 rc_sw_target);
274008e8
SAK		 5130
5131 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5132 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5133 enable_rc6 = false;
5134 }
5135
5136 /*
5137 * The exact context size is not known for BXT, so assume a page size
5138 * for this check.
5139 */
5140 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5141 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5142 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5143 ggtt->stolen_reserved_size))) {
b99d49cc 5144 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5145 enable_rc6 = false;
5146 }
5147
5148 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5149 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5150 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5151 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5152 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5153 enable_rc6 = false;
5154 }
5155
fc619841
ID		 5156 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5157 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5158 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5159 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5160 enable_rc6 = false;
5161 }
5162
5163 if (!I915_READ(GEN6_GFXPAUSE)) {
5164 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5165 enable_rc6 = false;
5166 }
5167
5168 if (!I915_READ(GEN8_MISC_CTRL0)) {
5169 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5170 enable_rc6 = false;
5171 }
5172
5173 return enable_rc6;
5174}
5175
dc97997a 5176int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5177{
e7d66d89 5178 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5179 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5180 return 0;
5181
274008e8
SAK		 5182 if (!enable_rc6)
5183 return 0;
5184
dc97997a 5185 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5186 DRM_INFO("RC6 disabled by BIOS\n");
5187 return 0;
5188 }
5189
456470eb 5190 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5191 if (enable_rc6 >= 0) {
5192 int mask;
5193
dc97997a 5194 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5195 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5196 INTEL_RC6pp_ENABLE;
5197 else
5198 mask = INTEL_RC6_ENABLE;
5199
5200 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5201 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5202 "(requested %d, valid %d)\n",
5203 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5204
5205 return enable_rc6 & mask;
5206 }
2b4e57bd 5207
dc97997a 5208 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5209 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5210
5211 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5212}
5213
dc97997a 5214static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5215{
5216 /* All of these values are in units of 50MHz */
773ea9a8 5217
93ee2920 5218 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5219 if (IS_BROXTON(dev_priv)) {
773ea9a8 5220 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5221 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5222 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5223 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5224 } else {
773ea9a8 5225 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5226 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5227 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5228 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5229 }
3280e8b0 5230 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5231 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5232
93ee2920 5233 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5234 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5235 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5236 u32 ddcc_status = 0;
5237
5238 if (sandybridge_pcode_read(dev_priv,
5239 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5240 &ddcc_status) == 0)
93ee2920 5241 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5242 clamp_t(u8,
5243 ((ddcc_status >> 8) & 0xff),
5244 dev_priv->rps.min_freq,
5245 dev_priv->rps.max_freq);
93ee2920
TR		 5246 }
5247
dc97997a 5248 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5249 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5250 * the natural hardware unit for SKL
5251 */
c5e0688c
AG		 5252 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5253 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5254 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5255 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5256 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5257 }
3280e8b0
BW		 5258}
5259
3a45b05c
CW		 5260static void reset_rps(struct drm_i915_private *dev_priv,
5261 void (*set)(struct drm_i915_private *, u8))
5262{
5263 u8 freq = dev_priv->rps.cur_freq;
5264
5265 /* force a reset */
5266 dev_priv->rps.power = -1;
5267 dev_priv->rps.cur_freq = -1;
5268
5269 set(dev_priv, freq);
5270}
5271
b6fef0ef 5272/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5273static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5274{
b6fef0ef
JB		 5275 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5276
23eafea6 5277 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5278 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5279 /*
5280 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5281 * clear out the Control register just to avoid inconsitency
5282 * with debugfs interface, which will show Turbo as enabled
5283 * only and that is not expected by the User after adding the
5284 * WaGsvDisableTurbo. Apart from this there is no problem even
5285 * if the Turbo is left enabled in the Control register, as the
5286 * Up/Down interrupts would remain masked.
5287 */
dc97997a 5288 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5289 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5290 return;
5291 }
5292
0beb059a
AG		 5293 /* Program defaults and thresholds for RPS*/
5294 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5295 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5296
5297 /* 1 second timeout*/
5298 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5299 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5300
b6fef0ef 5301 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5302
0beb059a
AG		 5303 /* Leaning on the below call to gen6_set_rps to program/setup the
5304 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5305 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5306 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5307
5308 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5309}
5310
dc97997a 5311static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5312{
e2f80391 5313 struct intel_engine_cs *engine;
20e49366 5314 uint32_t rc6_mask = 0;
20e49366
ZW		 5315
5316 /* 1a: Software RC state - RC0 */
5317 I915_WRITE(GEN6_RC_STATE, 0);
5318
5319 /* 1b: Get forcewake during program sequence. Although the driver
5320 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5321 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5322
5323 /* 2a: Disable RC states. */
5324 I915_WRITE(GEN6_RC_CONTROL, 0);
5325
5326 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5327
5328 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5329 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5330 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5331 else
5332 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5333 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5334 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5335 for_each_engine(engine, dev_priv)
e2f80391 5336 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5337
1a3d1898 5338 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5339 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5340
20e49366 5341 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5342
38c23527
ZW		 5343 /* 2c: Program Coarse Power Gating Policies. */
5344 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5345 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5346
20e49366 5347 /* 3a: Enable RC6 */
dc97997a 5348 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5349 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5350 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5351 /* WaRsUseTimeoutMode */
9fc736e8 5352 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5353 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5354 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5355 GEN7_RC_CTL_TO_MODE |
5356 rc6_mask);
3e7732a0
SAK		 5357 } else {
5358 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5359 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5360 GEN6_RC_CTL_EI_MODE(1) |
5361 rc6_mask);
3e7732a0 5362 }
20e49366 5363
cb07bae0
SK		 5364 /*
5365 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5366 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5367 */
dc97997a 5368 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5369 I915_WRITE(GEN9_PG_ENABLE, 0);
5370 else
5371 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5372 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5373
59bad947 5374 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5375}
5376
dc97997a 5377static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5378{
e2f80391 5379 struct intel_engine_cs *engine;
93ee2920 5380 uint32_t rc6_mask = 0;
6edee7f3
BW		 5381
5382 /* 1a: Software RC state - RC0 */
5383 I915_WRITE(GEN6_RC_STATE, 0);
5384
5385 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5386 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5387 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5388
5389 /* 2a: Disable RC states. */
5390 I915_WRITE(GEN6_RC_CONTROL, 0);
5391
6edee7f3
BW		 5392 /* 2b: Program RC6 thresholds.*/
5393 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5394 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5395 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5396 for_each_engine(engine, dev_priv)
e2f80391 5397 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5398 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5399 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5400 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5401 else
5402 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5403
5404 /* 3: Enable RC6 */
dc97997a 5405 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5406 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5407 intel_print_rc6_info(dev_priv, rc6_mask);
5408 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5409 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5410 GEN7_RC_CTL_TO_MODE |
5411 rc6_mask);
5412 else
5413 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5414 GEN6_RC_CTL_EI_MODE(1) |
5415 rc6_mask);
6edee7f3
BW		 5416
5417 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5418 I915_WRITE(GEN6_RPNSWREQ,
5419 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5420 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5421 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5422 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5423 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5424
5425 /* Docs recommend 900MHz, and 300 MHz respectively */
5426 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5427 dev_priv->rps.max_freq_softlimit << 24 |
5428 dev_priv->rps.min_freq_softlimit << 16);
5429
5430 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5431 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5432 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5433 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5434
5435 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5436
5437 /* 5: Enable RPS */
7526ed79
DV		 5438 I915_WRITE(GEN6_RP_CONTROL,
5439 GEN6_RP_MEDIA_TURBO |
5440 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5441 GEN6_RP_MEDIA_IS_GFX |
5442 GEN6_RP_ENABLE |
5443 GEN6_RP_UP_BUSY_AVG |
5444 GEN6_RP_DOWN_IDLE_AVG);
5445
5446 /* 6: Ring frequency + overclocking (our driver does this later */
5447
3a45b05c 5448 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5449
59bad947 5450 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5451}
5452
dc97997a 5453static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5454{
e2f80391 5455 struct intel_engine_cs *engine;
99ac9612 5456 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5457 u32 gtfifodbg;
2b4e57bd 5458 int rc6_mode;
b4ac5afc 5459 int ret;
2b4e57bd 5460
4fc688ce 5461 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5462
2b4e57bd
ED		 5463 /* Here begins a magic sequence of register writes to enable
5464 * auto-downclocking.
5465 *
5466 * Perhaps there might be some value in exposing these to
5467 * userspace...
5468 */
5469 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5470
5471 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5472 gtfifodbg = I915_READ(GTFIFODBG);
5473 if (gtfifodbg) {
2b4e57bd
ED		 5474 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5475 I915_WRITE(GTFIFODBG, gtfifodbg);
5476 }
5477
59bad947 5478 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5479
5480 /* disable the counters and set deterministic thresholds */
5481 I915_WRITE(GEN6_RC_CONTROL, 0);
5482
5483 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5484 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5485 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5486 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5487 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5488
b4ac5afc 5489 for_each_engine(engine, dev_priv)
e2f80391 5490 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5491
5492 I915_WRITE(GEN6_RC_SLEEP, 0);
5493 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5494 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5495 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5496 else
5497 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5498 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5499 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5500
5a7dc92a 5501 /* Check if we are enabling RC6 */
dc97997a 5502 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5503 if (rc6_mode & INTEL_RC6_ENABLE)
5504 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5505
5a7dc92a 5506 /* We don't use those on Haswell */
dc97997a 5507 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5508 if (rc6_mode & INTEL_RC6p_ENABLE)
5509 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5510
5a7dc92a
ED		 5511 if (rc6_mode & INTEL_RC6pp_ENABLE)
5512 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5513 }
2b4e57bd 5514
dc97997a 5515 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5516
5517 I915_WRITE(GEN6_RC_CONTROL,
5518 rc6_mask |
5519 GEN6_RC_CTL_EI_MODE(1) |
5520 GEN6_RC_CTL_HW_ENABLE);
5521
dd75fdc8
CW		 5522 /* Power down if completely idle for over 50ms */
5523 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5524 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5525
42c0526c 5526 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5527 if (ret)
42c0526c 5528 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5529
3a45b05c 5530 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5531
31643d54
BW		 5532 rc6vids = 0;
5533 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5534 if (IS_GEN6(dev_priv) && ret) {
31643d54 5535 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5536 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5537 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5538 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5539 rc6vids &= 0xffff00;
5540 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5541 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5542 if (ret)
5543 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5544 }
5545
59bad947 5546 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5547}
5548
fb7404e8 5549static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5550{
5551 int min_freq = 15;
3ebecd07
CW		 5552 unsigned int gpu_freq;
5553 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5554 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5555 int scaling_factor = 180;
eda79642 5556 struct cpufreq_policy *policy;
2b4e57bd 5557
4fc688ce 5558 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5559
eda79642
BW		 5560 policy = cpufreq_cpu_get(0);
5561 if (policy) {
5562 max_ia_freq = policy->cpuinfo.max_freq;
5563 cpufreq_cpu_put(policy);
5564 } else {
5565 /*
5566 * Default to measured freq if none found, PCU will ensure we
5567 * don't go over
5568 */
2b4e57bd 5569 max_ia_freq = tsc_khz;
eda79642 5570 }
2b4e57bd
ED		 5571
5572 /* Convert from kHz to MHz */
5573 max_ia_freq /= 1000;
5574
153b4b95 5575 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5576 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5577 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5578
dc97997a 5579 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5580 /* Convert GT frequency to 50 HZ units */
5581 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5582 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5583 } else {
5584 min_gpu_freq = dev_priv->rps.min_freq;
5585 max_gpu_freq = dev_priv->rps.max_freq;
5586 }
5587
2b4e57bd
ED		 5588 /*
5589 * For each potential GPU frequency, load a ring frequency we'd like
5590 * to use for memory access. We do this by specifying the IA frequency
5591 * the PCU should use as a reference to determine the ring frequency.
5592 */
4c8c7743
AG		 5593 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5594 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5595 unsigned int ia_freq = 0, ring_freq = 0;
5596
dc97997a 5597 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5598 /*
5599 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5600 * No floor required for ring frequency on SKL.
5601 */
5602 ring_freq = gpu_freq;
dc97997a 5603 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5604 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5605 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5606 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5607 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5608 ring_freq = max(min_ring_freq, ring_freq);
5609 /* leave ia_freq as the default, chosen by cpufreq */
5610 } else {
5611 /* On older processors, there is no separate ring
5612 * clock domain, so in order to boost the bandwidth
5613 * of the ring, we need to upclock the CPU (ia_freq).
5614 *
5615 * For GPU frequencies less than 750MHz,
5616 * just use the lowest ring freq.
5617 */
5618 if (gpu_freq < min_freq)
5619 ia_freq = 800;
5620 else
5621 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5622 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5623 }
2b4e57bd 5624
42c0526c
BW		 5625 sandybridge_pcode_write(dev_priv,
5626 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5627 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5628 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5629 gpu_freq);
2b4e57bd 5630 }
2b4e57bd
ED		 5631}
5632
03af2045 5633static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5634{
5635 u32 val, rp0;
5636
5b5929cb 5637 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5638
43b67998 5639 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5640 case 8:
5641 /* (2 * 4) config */
5642 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5643 break;
5644 case 12:
5645 /* (2 * 6) config */
5646 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5647 break;
5648 case 16:
5649 /* (2 * 8) config */
5650 default:
5651 /* Setting (2 * 8) Min RP0 for any other combination */
5652 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5653 break;
095acd5f 5654 }
5b5929cb
JN		 5655
5656 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5657
2b6b3a09
D		 5658 return rp0;
5659}
5660
5661static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5662{
5663 u32 val, rpe;
5664
5665 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5666 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5667
5668 return rpe;
5669}
5670
7707df4a
D		 5671static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5672{
5673 u32 val, rp1;
5674
5b5929cb
JN		 5675 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5676 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5677
7707df4a
D		 5678 return rp1;
5679}
5680
f8f2b001
D		 5681static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5682{
5683 u32 val, rp1;
5684
5685 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5686
5687 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5688
5689 return rp1;
5690}
5691
03af2045 5692static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5693{
5694 u32 val, rp0;
5695
64936258 5696 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5697
5698 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5699 /* Clamp to max */
5700 rp0 = min_t(u32, rp0, 0xea);
5701
5702 return rp0;
5703}
5704
5705static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5706{
5707 u32 val, rpe;
5708
64936258 5709 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5710 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5711 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5712 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5713
5714 return rpe;
5715}
5716
03af2045 5717static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5718{
36146035
ID		 5719 u32 val;
5720
5721 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5722 /*
5723 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5724 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5725 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5726 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5727 * to make sure it matches what Punit accepts.
5728 */
5729 return max_t(u32, val, 0xc0);
0a073b84
JB		 5730}
5731
ae48434c
ID		 5732/* Check that the pctx buffer wasn't move under us. */
5733static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5734{
5735 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5736
5737 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5738 dev_priv->vlv_pctx->stolen->start);
5739}
5740
38807746
D		 5741
5742/* Check that the pcbr address is not empty. */
5743static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5744{
5745 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5746
5747 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5748}
5749
dc97997a 5750static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5751{
62106b4f 5752 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5753 unsigned long pctx_paddr, paddr;
38807746
D		 5754 u32 pcbr;
5755 int pctx_size = 32*1024;
5756
38807746
D		 5757 pcbr = I915_READ(VLV_PCBR);
5758 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5759 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5760 paddr = (dev_priv->mm.stolen_base +
62106b4f 5761 (ggtt->stolen_size - pctx_size));
38807746
D		 5762
5763 pctx_paddr = (paddr & (~4095));
5764 I915_WRITE(VLV_PCBR, pctx_paddr);
5765 }
ce611ef8
VS		 5766
5767 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5768}
5769
dc97997a 5770static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5771{
c9cddffc
JB		 5772 struct drm_i915_gem_object *pctx;
5773 unsigned long pctx_paddr;
5774 u32 pcbr;
5775 int pctx_size = 24*1024;
5776
5777 pcbr = I915_READ(VLV_PCBR);
5778 if (pcbr) {
5779 /* BIOS set it up already, grab the pre-alloc'd space */
5780 int pcbr_offset;
5781
5782 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5783 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5784 pcbr_offset,
190d6cd5 5785 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5786 pctx_size);
5787 goto out;
5788 }
5789
ce611ef8
VS		 5790 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5791
c9cddffc
JB		 5792 /*
5793 * From the Gunit register HAS:
5794 * The Gfx driver is expected to program this register and ensure
5795 * proper allocation within Gfx stolen memory. For example, this
5796 * register should be programmed such than the PCBR range does not
5797 * overlap with other ranges, such as the frame buffer, protected
5798 * memory, or any other relevant ranges.
5799 */
91c8a326 5800 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5801 if (!pctx) {
5802 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5803 goto out;
c9cddffc
JB		 5804 }
5805
5806 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5807 I915_WRITE(VLV_PCBR, pctx_paddr);
5808
5809out:
ce611ef8 5810 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5811 dev_priv->vlv_pctx = pctx;
5812}
5813
dc97997a 5814static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5815{
ae48434c
ID		 5816 if (WARN_ON(!dev_priv->vlv_pctx))
5817 return;
5818
34911fd3 5819 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5820 dev_priv->vlv_pctx = NULL;
5821}
5822
c30fec65
VS		 5823static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5824{
5825 dev_priv->rps.gpll_ref_freq =
5826 vlv_get_cck_clock(dev_priv, "GPLL ref",
5827 CCK_GPLL_CLOCK_CONTROL,
5828 dev_priv->czclk_freq);
5829
5830 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5831 dev_priv->rps.gpll_ref_freq);
5832}
5833
dc97997a 5834static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5835{
2bb25c17 5836 u32 val;
4e80519e 5837
dc97997a 5838 valleyview_setup_pctx(dev_priv);
4e80519e 5839
c30fec65
VS		 5840 vlv_init_gpll_ref_freq(dev_priv);
5841
2bb25c17
VS		 5842 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5843 switch ((val >> 6) & 3) {
5844 case 0:
5845 case 1:
5846 dev_priv->mem_freq = 800;
5847 break;
5848 case 2:
5849 dev_priv->mem_freq = 1066;
5850 break;
5851 case 3:
5852 dev_priv->mem_freq = 1333;
5853 break;
5854 }
80b83b62 5855 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5856
4e80519e
ID		 5857 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5858 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5859 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5860 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5861 dev_priv->rps.max_freq);
5862
5863 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5864 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5865 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5866 dev_priv->rps.efficient_freq);
5867
f8f2b001
D		 5868 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5869 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5870 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5871 dev_priv->rps.rp1_freq);
5872
4e80519e
ID		 5873 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5874 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5875 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5876 dev_priv->rps.min_freq);
4e80519e
ID		 5877}
5878
dc97997a 5879static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5880{
2bb25c17 5881 u32 val;
2b6b3a09 5882
dc97997a 5883 cherryview_setup_pctx(dev_priv);
2b6b3a09 5884
c30fec65
VS		 5885 vlv_init_gpll_ref_freq(dev_priv);
5886
a580516d 5887 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5888 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5889 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5890
2bb25c17 5891 switch ((val >> 2) & 0x7) {
2bb25c17 5892 case 3:
2bb25c17
VS		 5893 dev_priv->mem_freq = 2000;
5894 break;
bfa7df01 5895 default:
2bb25c17
VS		 5896 dev_priv->mem_freq = 1600;
5897 break;
5898 }
80b83b62 5899 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5900
2b6b3a09
D		 5901 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5902 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5903 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5904 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5905 dev_priv->rps.max_freq);
5906
5907 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5908 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5909 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5910 dev_priv->rps.efficient_freq);
5911
7707df4a
D		 5912 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5913 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5914 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5915 dev_priv->rps.rp1_freq);
5916
5b7c91b7
D		 5917 /* PUnit validated range is only [RPe, RP0] */
5918 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5919 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5920 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5921 dev_priv->rps.min_freq);
5922
1c14762d
VS		 5923 WARN_ONCE((dev_priv->rps.max_freq |
5924 dev_priv->rps.efficient_freq |
5925 dev_priv->rps.rp1_freq |
5926 dev_priv->rps.min_freq) & 1,
5927 "Odd GPU freq values\n");
38807746
D		 5928}
5929
dc97997a 5930static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5931{
dc97997a 5932 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5933}
5934
dc97997a 5935static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5936{
e2f80391 5937 struct intel_engine_cs *engine;
2b6b3a09 5938 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5939
5940 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5941
297b32ec
VS		 5942 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5943 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5944 if (gtfifodbg) {
5945 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5946 gtfifodbg);
5947 I915_WRITE(GTFIFODBG, gtfifodbg);
5948 }
5949
5950 cherryview_check_pctx(dev_priv);
5951
5952 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5953 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5954 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5955
160614a2
VS		 5956 /* Disable RC states. */
5957 I915_WRITE(GEN6_RC_CONTROL, 0);
5958
38807746
D		 5959 /* 2a: Program RC6 thresholds.*/
5960 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5961 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5962 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5963
b4ac5afc 5964 for_each_engine(engine, dev_priv)
e2f80391 5965 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5966 I915_WRITE(GEN6_RC_SLEEP, 0);
5967
f4f71c7d
D		 5968 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5969 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5970
5971 /* allows RC6 residency counter to work */
5972 I915_WRITE(VLV_COUNTER_CONTROL,
5973 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5974 VLV_MEDIA_RC6_COUNT_EN |
5975 VLV_RENDER_RC6_COUNT_EN));
5976
5977 /* For now we assume BIOS is allocating and populating the PCBR */
5978 pcbr = I915_READ(VLV_PCBR);
5979
38807746 5980 /* 3: Enable RC6 */
dc97997a
CW		 5981 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5982 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5983 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5984
5985 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5986
2b6b3a09 5987 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5988 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5989 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5990 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5991 I915_WRITE(GEN6_RP_UP_EI, 66000);
5992 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5993
5994 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5995
5996 /* 5: Enable RPS */
5997 I915_WRITE(GEN6_RP_CONTROL,
5998 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5999 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6000 GEN6_RP_ENABLE |
6001 GEN6_RP_UP_BUSY_AVG |
6002 GEN6_RP_DOWN_IDLE_AVG);
6003
3ef62342
D		 6004 /* Setting Fixed Bias */
6005 val = VLV_OVERRIDE_EN |
6006 VLV_SOC_TDP_EN |
6007 CHV_BIAS_CPU_50_SOC_50;
6008 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6009
2b6b3a09
D		 6010 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6011
8d40c3ae
VS		 6012 /* RPS code assumes GPLL is used */
6013 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6014
742f491d 6015 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6016 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6017
3a45b05c 6018 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6019
59bad947 6020 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6021}
6022
dc97997a 6023static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6024{
e2f80391 6025 struct intel_engine_cs *engine;
2a5913a8 6026 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6027
6028 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6029
ae48434c
ID		 6030 valleyview_check_pctx(dev_priv);
6031
297b32ec
VS		 6032 gtfifodbg = I915_READ(GTFIFODBG);
6033 if (gtfifodbg) {
f7d85c1e
JB		 6034 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6035 gtfifodbg);
0a073b84
JB		 6036 I915_WRITE(GTFIFODBG, gtfifodbg);
6037 }
6038
c8d9a590 6039 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6040 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6041
160614a2
VS		 6042 /* Disable RC states. */
6043 I915_WRITE(GEN6_RC_CONTROL, 0);
6044
cad725fe 6045 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6046 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6047 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6048 I915_WRITE(GEN6_RP_UP_EI, 66000);
6049 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6050
6051 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6052
6053 I915_WRITE(GEN6_RP_CONTROL,
6054 GEN6_RP_MEDIA_TURBO |
6055 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6056 GEN6_RP_MEDIA_IS_GFX |
6057 GEN6_RP_ENABLE |
6058 GEN6_RP_UP_BUSY_AVG |
6059 GEN6_RP_DOWN_IDLE_CONT);
6060
6061 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6062 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6063 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6064
b4ac5afc 6065 for_each_engine(engine, dev_priv)
e2f80391 6066 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6067
2f0aa304 6068 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6069
6070 /* allows RC6 residency counter to work */
49798eb2 6071 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6072 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6073 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6074 VLV_MEDIA_RC6_COUNT_EN |
6075 VLV_RENDER_RC6_COUNT_EN));
31685c25 6076
dc97997a 6077 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6078 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6079
dc97997a 6080 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6081
a2b23fe0 6082 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6083
3ef62342
D		 6084 /* Setting Fixed Bias */
6085 val = VLV_OVERRIDE_EN |
6086 VLV_SOC_TDP_EN |
6087 VLV_BIAS_CPU_125_SOC_875;
6088 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6089
64936258 6090 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6091
8d40c3ae
VS		 6092 /* RPS code assumes GPLL is used */
6093 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6094
742f491d 6095 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6096 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6097
3a45b05c 6098 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6099
59bad947 6100 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6101}
6102
dde18883
ED		 6103static unsigned long intel_pxfreq(u32 vidfreq)
6104{
6105 unsigned long freq;
6106 int div = (vidfreq & 0x3f0000) >> 16;
6107 int post = (vidfreq & 0x3000) >> 12;
6108 int pre = (vidfreq & 0x7);
6109
6110 if (!pre)
6111 return 0;
6112
6113 freq = ((div * 133333) / ((1<<post) * pre));
6114
6115 return freq;
6116}
6117
eb48eb00
DV		 6118static const struct cparams {
6119 u16 i;
6120 u16 t;
6121 u16 m;
6122 u16 c;
6123} cparams[] = {
6124 { 1, 1333, 301, 28664 },
6125 { 1, 1066, 294, 24460 },
6126 { 1, 800, 294, 25192 },
6127 { 0, 1333, 276, 27605 },
6128 { 0, 1066, 276, 27605 },
6129 { 0, 800, 231, 23784 },
6130};
6131
f531dcb2 6132static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6133{
6134 u64 total_count, diff, ret;
6135 u32 count1, count2, count3, m = 0, c = 0;
6136 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6137 int i;
6138
02d71956
DV		 6139 assert_spin_locked(&mchdev_lock);
6140
20e4d407 6141 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6142
6143 /* Prevent division-by-zero if we are asking too fast.
6144 * Also, we don't get interesting results if we are polling
6145 * faster than once in 10ms, so just return the saved value
6146 * in such cases.
6147 */
6148 if (diff1 <= 10)
20e4d407 6149 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6150
6151 count1 = I915_READ(DMIEC);
6152 count2 = I915_READ(DDREC);
6153 count3 = I915_READ(CSIEC);
6154
6155 total_count = count1 + count2 + count3;
6156
6157 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6158 if (total_count < dev_priv->ips.last_count1) {
6159 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6160 diff += total_count;
6161 } else {
20e4d407 6162 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6163 }
6164
6165 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6166 if (cparams[i].i == dev_priv->ips.c_m &&
6167 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6168 m = cparams[i].m;
6169 c = cparams[i].c;
6170 break;
6171 }
6172 }
6173
6174 diff = div_u64(diff, diff1);
6175 ret = ((m * diff) + c);
6176 ret = div_u64(ret, 10);
6177
20e4d407
DV		 6178 dev_priv->ips.last_count1 = total_count;
6179 dev_priv->ips.last_time1 = now;
eb48eb00 6180
20e4d407 6181 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6182
6183 return ret;
6184}
6185
f531dcb2
CW		 6186unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6187{
6188 unsigned long val;
6189
dc97997a 6190 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6191 return 0;
6192
6193 spin_lock_irq(&mchdev_lock);
6194
6195 val = __i915_chipset_val(dev_priv);
6196
6197 spin_unlock_irq(&mchdev_lock);
6198
6199 return val;
6200}
6201
eb48eb00
DV		 6202unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6203{
6204 unsigned long m, x, b;
6205 u32 tsfs;
6206
6207 tsfs = I915_READ(TSFS);
6208
6209 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6210 x = I915_READ8(TR1);
6211
6212 b = tsfs & TSFS_INTR_MASK;
6213
6214 return ((m * x) / 127) - b;
6215}
6216
d972d6ee
MK		 6217static int _pxvid_to_vd(u8 pxvid)
6218{
6219 if (pxvid == 0)
6220 return 0;
6221
6222 if (pxvid >= 8 && pxvid < 31)
6223 pxvid = 31;
6224
6225 return (pxvid + 2) * 125;
6226}
6227
6228static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6229{
d972d6ee
MK		 6230 const int vd = _pxvid_to_vd(pxvid);
6231 const int vm = vd - 1125;
6232
dc97997a 6233 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6234 return vm > 0 ? vm : 0;
6235
6236 return vd;
eb48eb00
DV		 6237}
6238
02d71956 6239static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6240{
5ed0bdf2 6241 u64 now, diff, diffms;
eb48eb00
DV		 6242 u32 count;
6243
02d71956 6244 assert_spin_locked(&mchdev_lock);
eb48eb00 6245
5ed0bdf2
TG		 6246 now = ktime_get_raw_ns();
6247 diffms = now - dev_priv->ips.last_time2;
6248 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6249
6250 /* Don't divide by 0 */
eb48eb00
DV		 6251 if (!diffms)
6252 return;
6253
6254 count = I915_READ(GFXEC);
6255
20e4d407
DV		 6256 if (count < dev_priv->ips.last_count2) {
6257 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6258 diff += count;
6259 } else {
20e4d407 6260 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6261 }
6262
20e4d407
DV		 6263 dev_priv->ips.last_count2 = count;
6264 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6265
6266 /* More magic constants... */
6267 diff = diff * 1181;
6268 diff = div_u64(diff, diffms * 10);
20e4d407 6269 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6270}
6271
02d71956
DV		 6272void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6273{
dc97997a 6274 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6275 return;
6276
9270388e 6277 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6278
6279 __i915_update_gfx_val(dev_priv);
6280
9270388e 6281 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6282}
6283
f531dcb2 6284static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6285{
6286 unsigned long t, corr, state1, corr2, state2;
6287 u32 pxvid, ext_v;
6288
02d71956
DV		 6289 assert_spin_locked(&mchdev_lock);
6290
616847e7 6291 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6292 pxvid = (pxvid >> 24) & 0x7f;
6293 ext_v = pvid_to_extvid(dev_priv, pxvid);
6294
6295 state1 = ext_v;
6296
6297 t = i915_mch_val(dev_priv);
6298
6299 /* Revel in the empirically derived constants */
6300
6301 /* Correction factor in 1/100000 units */
6302 if (t > 80)
6303 corr = ((t * 2349) + 135940);
6304 else if (t >= 50)
6305 corr = ((t * 964) + 29317);
6306 else /* < 50 */
6307 corr = ((t * 301) + 1004);
6308
6309 corr = corr * ((150142 * state1) / 10000 - 78642);
6310 corr /= 100000;
20e4d407 6311 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6312
6313 state2 = (corr2 * state1) / 10000;
6314 state2 /= 100; /* convert to mW */
6315
02d71956 6316 __i915_update_gfx_val(dev_priv);
eb48eb00 6317
20e4d407 6318 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6319}
6320
f531dcb2
CW		 6321unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6322{
6323 unsigned long val;
6324
dc97997a 6325 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6326 return 0;
6327
6328 spin_lock_irq(&mchdev_lock);
6329
6330 val = __i915_gfx_val(dev_priv);
6331
6332 spin_unlock_irq(&mchdev_lock);
6333
6334 return val;
6335}
6336
eb48eb00
DV		 6337/**
6338 * i915_read_mch_val - return value for IPS use
6339 *
6340 * Calculate and return a value for the IPS driver to use when deciding whether
6341 * we have thermal and power headroom to increase CPU or GPU power budget.
6342 */
6343unsigned long i915_read_mch_val(void)
6344{
6345 struct drm_i915_private *dev_priv;
6346 unsigned long chipset_val, graphics_val, ret = 0;
6347
9270388e 6348 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6349 if (!i915_mch_dev)
6350 goto out_unlock;
6351 dev_priv = i915_mch_dev;
6352
f531dcb2
CW		 6353 chipset_val = __i915_chipset_val(dev_priv);
6354 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6355
6356 ret = chipset_val + graphics_val;
6357
6358out_unlock:
9270388e 6359 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6360
6361 return ret;
6362}
6363EXPORT_SYMBOL_GPL(i915_read_mch_val);
6364
6365/**
6366 * i915_gpu_raise - raise GPU frequency limit
6367 *
6368 * Raise the limit; IPS indicates we have thermal headroom.
6369 */
6370bool i915_gpu_raise(void)
6371{
6372 struct drm_i915_private *dev_priv;
6373 bool ret = true;
6374
9270388e 6375 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6376 if (!i915_mch_dev) {
6377 ret = false;
6378 goto out_unlock;
6379 }
6380 dev_priv = i915_mch_dev;
6381
20e4d407
DV		 6382 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6383 dev_priv->ips.max_delay--;
eb48eb00
DV		 6384
6385out_unlock:
9270388e 6386 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6387
6388 return ret;
6389}
6390EXPORT_SYMBOL_GPL(i915_gpu_raise);
6391
6392/**
6393 * i915_gpu_lower - lower GPU frequency limit
6394 *
6395 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6396 * frequency maximum.
6397 */
6398bool i915_gpu_lower(void)
6399{
6400 struct drm_i915_private *dev_priv;
6401 bool ret = true;
6402
9270388e 6403 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6404 if (!i915_mch_dev) {
6405 ret = false;
6406 goto out_unlock;
6407 }
6408 dev_priv = i915_mch_dev;
6409
20e4d407
DV		 6410 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6411 dev_priv->ips.max_delay++;
eb48eb00
DV		 6412
6413out_unlock:
9270388e 6414 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6415
6416 return ret;
6417}
6418EXPORT_SYMBOL_GPL(i915_gpu_lower);
6419
6420/**
6421 * i915_gpu_busy - indicate GPU business to IPS
6422 *
6423 * Tell the IPS driver whether or not the GPU is busy.
6424 */
6425bool i915_gpu_busy(void)
6426{
eb48eb00
DV		 6427 bool ret = false;
6428
9270388e 6429 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6430 if (i915_mch_dev)
6431 ret = i915_mch_dev->gt.awake;
9270388e 6432 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6433
6434 return ret;
6435}
6436EXPORT_SYMBOL_GPL(i915_gpu_busy);
6437
6438/**
6439 * i915_gpu_turbo_disable - disable graphics turbo
6440 *
6441 * Disable graphics turbo by resetting the max frequency and setting the
6442 * current frequency to the default.
6443 */
6444bool i915_gpu_turbo_disable(void)
6445{
6446 struct drm_i915_private *dev_priv;
6447 bool ret = true;
6448
9270388e 6449 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6450 if (!i915_mch_dev) {
6451 ret = false;
6452 goto out_unlock;
6453 }
6454 dev_priv = i915_mch_dev;
6455
20e4d407 6456 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6457
91d14251 6458 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6459 ret = false;
6460
6461out_unlock:
9270388e 6462 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6463
6464 return ret;
6465}
6466EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6467
6468/**
6469 * Tells the intel_ips driver that the i915 driver is now loaded, if
6470 * IPS got loaded first.
6471 *
6472 * This awkward dance is so that neither module has to depend on the
6473 * other in order for IPS to do the appropriate communication of
6474 * GPU turbo limits to i915.
6475 */
6476static void
6477ips_ping_for_i915_load(void)
6478{
6479 void (*link)(void);
6480
6481 link = symbol_get(ips_link_to_i915_driver);
6482 if (link) {
6483 link();
6484 symbol_put(ips_link_to_i915_driver);
6485 }
6486}
6487
6488void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6489{
02d71956
DV		 6490 /* We only register the i915 ips part with intel-ips once everything is
6491 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6492 spin_lock_irq(&mchdev_lock);
eb48eb00 6493 i915_mch_dev = dev_priv;
9270388e 6494 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6495
6496 ips_ping_for_i915_load();
6497}
6498
6499void intel_gpu_ips_teardown(void)
6500{
9270388e 6501 spin_lock_irq(&mchdev_lock);
eb48eb00 6502 i915_mch_dev = NULL;
9270388e 6503 spin_unlock_irq(&mchdev_lock);
eb48eb00 6504}
76c3552f 6505
dc97997a 6506static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6507{
dde18883
ED		 6508 u32 lcfuse;
6509 u8 pxw[16];
6510 int i;
6511
6512 /* Disable to program */
6513 I915_WRITE(ECR, 0);
6514 POSTING_READ(ECR);
6515
6516 /* Program energy weights for various events */
6517 I915_WRITE(SDEW, 0x15040d00);
6518 I915_WRITE(CSIEW0, 0x007f0000);
6519 I915_WRITE(CSIEW1, 0x1e220004);
6520 I915_WRITE(CSIEW2, 0x04000004);
6521
6522 for (i = 0; i < 5; i++)
616847e7 6523 I915_WRITE(PEW(i), 0);
dde18883 6524 for (i = 0; i < 3; i++)
616847e7 6525 I915_WRITE(DEW(i), 0);
dde18883
ED		 6526
6527 /* Program P-state weights to account for frequency power adjustment */
6528 for (i = 0; i < 16; i++) {
616847e7 6529 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6530 unsigned long freq = intel_pxfreq(pxvidfreq);
6531 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6532 PXVFREQ_PX_SHIFT;
6533 unsigned long val;
6534
6535 val = vid * vid;
6536 val *= (freq / 1000);
6537 val *= 255;
6538 val /= (127*127*900);
6539 if (val > 0xff)
6540 DRM_ERROR("bad pxval: %ld\n", val);
6541 pxw[i] = val;
6542 }
6543 /* Render standby states get 0 weight */
6544 pxw[14] = 0;
6545 pxw[15] = 0;
6546
6547 for (i = 0; i < 4; i++) {
6548 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6549 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6550 I915_WRITE(PXW(i), val);
dde18883
ED		 6551 }
6552
6553 /* Adjust magic regs to magic values (more experimental results) */
6554 I915_WRITE(OGW0, 0);
6555 I915_WRITE(OGW1, 0);
6556 I915_WRITE(EG0, 0x00007f00);
6557 I915_WRITE(EG1, 0x0000000e);
6558 I915_WRITE(EG2, 0x000e0000);
6559 I915_WRITE(EG3, 0x68000300);
6560 I915_WRITE(EG4, 0x42000000);
6561 I915_WRITE(EG5, 0x00140031);
6562 I915_WRITE(EG6, 0);
6563 I915_WRITE(EG7, 0);
6564
6565 for (i = 0; i < 8; i++)
616847e7 6566 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6567
6568 /* Enable PMON + select events */
6569 I915_WRITE(ECR, 0x80000019);
6570
6571 lcfuse = I915_READ(LCFUSE02);
6572
20e4d407 6573 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6574}
6575
dc97997a 6576void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6577{
b268c699
ID		 6578 /*
6579 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6580 * requirement.
6581 */
6582 if (!i915.enable_rc6) {
6583 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6584 intel_runtime_pm_get(dev_priv);
6585 }
e6069ca8 6586
b5163dbb 6587 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6588 mutex_lock(&dev_priv->rps.hw_lock);
6589
6590 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6591 if (IS_CHERRYVIEW(dev_priv))
6592 cherryview_init_gt_powersave(dev_priv);
6593 else if (IS_VALLEYVIEW(dev_priv))
6594 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6595 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6596 gen6_init_rps_frequencies(dev_priv);
6597
6598 /* Derive initial user preferences/limits from the hardware limits */
6599 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6600 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6601
6602 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6603 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6604
6605 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6606 dev_priv->rps.min_freq_softlimit =
6607 max_t(int,
6608 dev_priv->rps.efficient_freq,
6609 intel_freq_opcode(dev_priv, 450));
6610
99ac9612
CW		 6611 /* After setting max-softlimit, find the overclock max freq */
6612 if (IS_GEN6(dev_priv) ||
6613 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6614 u32 params = 0;
6615
6616 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6617 if (params & BIT(31)) { /* OC supported */
6618 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6619 (dev_priv->rps.max_freq & 0xff) * 50,
6620 (params & 0xff) * 50);
6621 dev_priv->rps.max_freq = params & 0xff;
6622 }
6623 }
6624
29ecd78d
CW		 6625 /* Finally allow us to boost to max by default */
6626 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6627
773ea9a8 6628 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6629 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6630
6631 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6632}
6633
dc97997a 6634void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6635{
8dac1e1f 6636 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6637 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6638
6639 if (!i915.enable_rc6)
6640 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6641}
6642
54b4f68f
CW		 6643/**
6644 * intel_suspend_gt_powersave - suspend PM work and helper threads
6645 * @dev_priv: i915 device
6646 *
6647 * We don't want to disable RC6 or other features here, we just want
6648 * to make sure any work we've queued has finished and won't bother
6649 * us while we're suspended.
6650 */
6651void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6652{
6653 if (INTEL_GEN(dev_priv) < 6)
6654 return;
6655
6656 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6657 intel_runtime_pm_put(dev_priv);
6658
6659 /* gen6_rps_idle() will be called later to disable interrupts */
6660}
6661
b7137e0c
CW		 6662void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6663{
6664 dev_priv->rps.enabled = true; /* force disabling */
6665 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6666
6667 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6668}
6669
dc97997a 6670void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6671{
b7137e0c
CW		 6672 if (!READ_ONCE(dev_priv->rps.enabled))
6673 return;
e494837a 6674
b7137e0c 6675 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6676
b7137e0c
CW		 6677 if (INTEL_GEN(dev_priv) >= 9) {
6678 gen9_disable_rc6(dev_priv);
6679 gen9_disable_rps(dev_priv);
6680 } else if (IS_CHERRYVIEW(dev_priv)) {
6681 cherryview_disable_rps(dev_priv);
6682 } else if (IS_VALLEYVIEW(dev_priv)) {
6683 valleyview_disable_rps(dev_priv);
6684 } else if (INTEL_GEN(dev_priv) >= 6) {
6685 gen6_disable_rps(dev_priv);
6686 } else if (IS_IRONLAKE_M(dev_priv)) {
6687 ironlake_disable_drps(dev_priv);
930ebb46 6688 }
b7137e0c
CW		 6689
6690 dev_priv->rps.enabled = false;
6691 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6692}
6693
b7137e0c 6694void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6695{
54b4f68f
CW		 6696 /* We shouldn't be disabling as we submit, so this should be less
6697 * racy than it appears!
6698 */
b7137e0c
CW		 6699 if (READ_ONCE(dev_priv->rps.enabled))
6700 return;
1a01ab3b 6701
b7137e0c
CW		 6702 /* Powersaving is controlled by the host when inside a VM */
6703 if (intel_vgpu_active(dev_priv))
6704 return;
0a073b84 6705
b7137e0c 6706 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6707
6708 if (IS_CHERRYVIEW(dev_priv)) {
6709 cherryview_enable_rps(dev_priv);
6710 } else if (IS_VALLEYVIEW(dev_priv)) {
6711 valleyview_enable_rps(dev_priv);
b7137e0c 6712 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6713 gen9_enable_rc6(dev_priv);
6714 gen9_enable_rps(dev_priv);
6715 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6716 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6717 } else if (IS_BROADWELL(dev_priv)) {
6718 gen8_enable_rps(dev_priv);
fb7404e8 6719 gen6_update_ring_freq(dev_priv);
b7137e0c 6720 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6721 gen6_enable_rps(dev_priv);
fb7404e8 6722 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6723 } else if (IS_IRONLAKE_M(dev_priv)) {
6724 ironlake_enable_drps(dev_priv);
6725 intel_init_emon(dev_priv);
0a073b84 6726 }
aed242ff
CW		 6727
6728 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6729 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6730
6731 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6732 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6733
54b4f68f 6734 dev_priv->rps.enabled = true;
b7137e0c
CW		 6735 mutex_unlock(&dev_priv->rps.hw_lock);
6736}
3cc134e3 6737
54b4f68f
CW		 6738static void __intel_autoenable_gt_powersave(struct work_struct *work)
6739{
6740 struct drm_i915_private *dev_priv =
6741 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6742 struct intel_engine_cs *rcs;
6743 struct drm_i915_gem_request *req;
6744
6745 if (READ_ONCE(dev_priv->rps.enabled))
6746 goto out;
6747
6748 rcs = &dev_priv->engine[RCS];
6749 if (rcs->last_context)
6750 goto out;
6751
6752 if (!rcs->init_context)
6753 goto out;
6754
6755 mutex_lock(&dev_priv->drm.struct_mutex);
6756
6757 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6758 if (IS_ERR(req))
6759 goto unlock;
6760
6761 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6762 rcs->init_context(req);
6763
6764 /* Mark the device busy, calling intel_enable_gt_powersave() */
6765 i915_add_request_no_flush(req);
6766
6767unlock:
6768 mutex_unlock(&dev_priv->drm.struct_mutex);
6769out:
6770 intel_runtime_pm_put(dev_priv);
6771}
6772
6773void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6774{
6775 if (READ_ONCE(dev_priv->rps.enabled))
6776 return;
6777
6778 if (IS_IRONLAKE_M(dev_priv)) {
6779 ironlake_enable_drps(dev_priv);
54b4f68f 6780 intel_init_emon(dev_priv);
54b4f68f
CW		 6781 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6782 /*
6783 * PCU communication is slow and this doesn't need to be
6784 * done at any specific time, so do this out of our fast path
6785 * to make resume and init faster.
6786 *
6787 * We depend on the HW RC6 power context save/restore
6788 * mechanism when entering D3 through runtime PM suspend. So
6789 * disable RPM until RPS/RC6 is properly setup. We can only
6790 * get here via the driver load/system resume/runtime resume
6791 * paths, so the _noresume version is enough (and in case of
6792 * runtime resume it's necessary).
6793 */
6794 if (queue_delayed_work(dev_priv->wq,
6795 &dev_priv->rps.autoenable_work,
6796 round_jiffies_up_relative(HZ)))
6797 intel_runtime_pm_get_noresume(dev_priv);
6798 }
6799}
6800
3107bd48
DV		 6801static void ibx_init_clock_gating(struct drm_device *dev)
6802{
fac5e23e 6803 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6804
6805 /*
6806 * On Ibex Peak and Cougar Point, we need to disable clock
6807 * gating for the panel power sequencer or it will fail to
6808 * start up when no ports are active.
6809 */
6810 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6811}
6812
0e088b8f
VS		 6813static void g4x_disable_trickle_feed(struct drm_device *dev)
6814{
fac5e23e 6815 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6816 enum pipe pipe;
0e088b8f 6817
055e393f 6818 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6819 I915_WRITE(DSPCNTR(pipe),
6820 I915_READ(DSPCNTR(pipe)) |
6821 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6822
6823 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6824 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6825 }
6826}
6827
017636cc
VS		 6828static void ilk_init_lp_watermarks(struct drm_device *dev)
6829{
fac5e23e 6830 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6831
6832 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6833 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6834 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6835
6836 /*
6837 * Don't touch WM1S_LP_EN here.
6838 * Doing so could cause underruns.
6839 */
6840}
6841
1fa61106 6842static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6843{
fac5e23e 6844 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6845 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6846
f1e8fa56
DL		 6847 /*
6848 * Required for FBC
6849 * WaFbcDisableDpfcClockGating:ilk
6850 */
4d47e4f5
DL		 6851 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6852 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6853 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6854
6855 I915_WRITE(PCH_3DCGDIS0,
6856 MARIUNIT_CLOCK_GATE_DISABLE |
6857 SVSMUNIT_CLOCK_GATE_DISABLE);
6858 I915_WRITE(PCH_3DCGDIS1,
6859 VFMUNIT_CLOCK_GATE_DISABLE);
6860
6f1d69b0
ED		 6861 /*
6862 * According to the spec the following bits should be set in
6863 * order to enable memory self-refresh
6864 * The bit 22/21 of 0x42004
6865 * The bit 5 of 0x42020
6866 * The bit 15 of 0x45000
6867 */
6868 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6869 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6870 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6871 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6872 I915_WRITE(DISP_ARB_CTL,
6873 (I915_READ(DISP_ARB_CTL) |
6874 DISP_FBC_WM_DIS));
017636cc
VS		 6875
6876 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6877
6878 /*
6879 * Based on the document from hardware guys the following bits
6880 * should be set unconditionally in order to enable FBC.
6881 * The bit 22 of 0x42000
6882 * The bit 22 of 0x42004
6883 * The bit 7,8,9 of 0x42020.
6884 */
6885 if (IS_IRONLAKE_M(dev)) {
4bb35334 6886 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6887 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6888 I915_READ(ILK_DISPLAY_CHICKEN1) |
6889 ILK_FBCQ_DIS);
6890 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6891 I915_READ(ILK_DISPLAY_CHICKEN2) |
6892 ILK_DPARB_GATE);
6f1d69b0
ED		 6893 }
6894
4d47e4f5
DL		 6895 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6896
6f1d69b0
ED		 6897 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6898 I915_READ(ILK_DISPLAY_CHICKEN2) |
6899 ILK_ELPIN_409_SELECT);
6900 I915_WRITE(_3D_CHICKEN2,
6901 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6902 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6903
ecdb4eb7 6904 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6905 I915_WRITE(CACHE_MODE_0,
6906 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6907
4e04632e
AG		 6908 /* WaDisable_RenderCache_OperationalFlush:ilk */
6909 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6910
0e088b8f 6911 g4x_disable_trickle_feed(dev);
bdad2b2f 6912
3107bd48
DV		 6913 ibx_init_clock_gating(dev);
6914}
6915
6916static void cpt_init_clock_gating(struct drm_device *dev)
6917{
fac5e23e 6918 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6919 int pipe;
3f704fa2 6920 uint32_t val;
3107bd48
DV		 6921
6922 /*
6923 * On Ibex Peak and Cougar Point, we need to disable clock
6924 * gating for the panel power sequencer or it will fail to
6925 * start up when no ports are active.
6926 */
cd664078
JB		 6927 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6928 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6929 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6930 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6931 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6932 /* The below fixes the weird display corruption, a few pixels shifted
6933 * downward, on (only) LVDS of some HP laptops with IVY.
6934 */
055e393f 6935 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6936 val = I915_READ(TRANS_CHICKEN2(pipe));
6937 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6938 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6939 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6940 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6941 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6942 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6943 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6944 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6945 }
3107bd48 6946 /* WADP0ClockGatingDisable */
055e393f 6947 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6948 I915_WRITE(TRANS_CHICKEN1(pipe),
6949 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6950 }
6f1d69b0
ED		 6951}
6952
1d7aaa0c
DV		 6953static void gen6_check_mch_setup(struct drm_device *dev)
6954{
fac5e23e 6955 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 6956 uint32_t tmp;
6957
6958 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6959 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6960 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6961 tmp);
1d7aaa0c
DV		 6962}
6963
1fa61106 6964static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 6965{
fac5e23e 6966 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6967 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6968
231e54f6 6969 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6970
6971 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6972 I915_READ(ILK_DISPLAY_CHICKEN2) |
6973 ILK_ELPIN_409_SELECT);
6974
ecdb4eb7 6975 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6976 I915_WRITE(_3D_CHICKEN,
6977 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6978
4e04632e
AG		 6979 /* WaDisable_RenderCache_OperationalFlush:snb */
6980 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6981
8d85d272
VS		 6982 /*
6983 * BSpec recoomends 8x4 when MSAA is used,
6984 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6985 *
6986 * Note that PS/WM thread counts depend on the WIZ hashing
6987 * disable bit, which we don't touch here, but it's good
6988 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6989 */
6990 I915_WRITE(GEN6_GT_MODE,
98533251 6991 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6992
017636cc 6993 ilk_init_lp_watermarks(dev);
6f1d69b0 6994
6f1d69b0 6995 I915_WRITE(CACHE_MODE_0,
50743298 6996 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6997
6998 I915_WRITE(GEN6_UCGCTL1,
6999 I915_READ(GEN6_UCGCTL1) |
7000 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7001 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7002
7003 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7004 * gating disable must be set. Failure to set it results in
7005 * flickering pixels due to Z write ordering failures after
7006 * some amount of runtime in the Mesa "fire" demo, and Unigine
7007 * Sanctuary and Tropics, and apparently anything else with
7008 * alpha test or pixel discard.
7009 *
7010 * According to the spec, bit 11 (RCCUNIT) must also be set,
7011 * but we didn't debug actual testcases to find it out.
0f846f81 7012 *
ef59318c
VS		 7013 * WaDisableRCCUnitClockGating:snb
7014 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7015 */
7016 I915_WRITE(GEN6_UCGCTL2,
7017 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7018 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7019
5eb146dd 7020 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7021 I915_WRITE(_3D_CHICKEN3,
7022 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7023
e927ecde
VS		 7024 /*
7025 * Bspec says:
7026 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7027 * 3DSTATE_SF number of SF output attributes is more than 16."
7028 */
7029 I915_WRITE(_3D_CHICKEN3,
7030 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7031
6f1d69b0
ED		 7032 /*
7033 * According to the spec the following bits should be
7034 * set in order to enable memory self-refresh and fbc:
7035 * The bit21 and bit22 of 0x42000
7036 * The bit21 and bit22 of 0x42004
7037 * The bit5 and bit7 of 0x42020
7038 * The bit14 of 0x70180
7039 * The bit14 of 0x71180
4bb35334
DL		 7040 *
7041 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7042 */
7043 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7044 I915_READ(ILK_DISPLAY_CHICKEN1) |
7045 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7046 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7047 I915_READ(ILK_DISPLAY_CHICKEN2) |
7048 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7049 I915_WRITE(ILK_DSPCLK_GATE_D,
7050 I915_READ(ILK_DSPCLK_GATE_D) |
7051 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7052 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7053
0e088b8f 7054 g4x_disable_trickle_feed(dev);
f8f2ac9a 7055
3107bd48 7056 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7057
7058 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7059}
7060
7061static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7062{
7063 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7064
3aad9059 7065 /*
46680e0a 7066 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7067 *
7068 * This actually overrides the dispatch
7069 * mode for all thread types.
7070 */
6f1d69b0
ED		 7071 reg &= ~GEN7_FF_SCHED_MASK;
7072 reg |= GEN7_FF_TS_SCHED_HW;
7073 reg |= GEN7_FF_VS_SCHED_HW;
7074 reg |= GEN7_FF_DS_SCHED_HW;
7075
7076 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7077}
7078
17a303ec
PZ		 7079static void lpt_init_clock_gating(struct drm_device *dev)
7080{
fac5e23e 7081 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7082
7083 /*
7084 * TODO: this bit should only be enabled when really needed, then
7085 * disabled when not needed anymore in order to save power.
7086 */
c2699524 7087 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 7088 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7089 I915_READ(SOUTH_DSPCLK_GATE_D) |
7090 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7091
7092 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7093 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7094 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7095 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7096}
7097
7d708ee4
ID		 7098static void lpt_suspend_hw(struct drm_device *dev)
7099{
fac5e23e 7100 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7101
c2699524 7102 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 7103 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7104
7105 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7106 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7107 }
7108}
7109
450174fe
ID		 7110static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7111 int general_prio_credits,
7112 int high_prio_credits)
7113{
7114 u32 misccpctl;
7115
7116 /* WaTempDisableDOPClkGating:bdw */
7117 misccpctl = I915_READ(GEN7_MISCCPCTL);
7118 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7119
7120 I915_WRITE(GEN8_L3SQCREG1,
7121 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7122 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7123
7124 /*
7125 * Wait at least 100 clocks before re-enabling clock gating.
7126 * See the definition of L3SQCREG1 in BSpec.
7127 */
7128 POSTING_READ(GEN8_L3SQCREG1);
7129 udelay(1);
7130 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7131}
7132
9498dba7
MK		 7133static void kabylake_init_clock_gating(struct drm_device *dev)
7134{
9146f308 7135 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7136
b033bb6d 7137 gen9_init_clock_gating(dev);
9498dba7
MK		 7138
7139 /* WaDisableSDEUnitClockGating:kbl */
7140 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7141 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7142 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7143
7144 /* WaDisableGamClockGating:kbl */
7145 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7146 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7147 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7148
7149 /* WaFbcNukeOnHostModify:kbl */
7150 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7151 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7152}
7153
dc00b6a0
DV		 7154static void skylake_init_clock_gating(struct drm_device *dev)
7155{
c584e2d3 7156 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7157
b033bb6d 7158 gen9_init_clock_gating(dev);
44fff99f
MK		 7159
7160 /* WAC6entrylatency:skl */
7161 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7162 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7163
7164 /* WaFbcNukeOnHostModify:skl */
7165 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7166 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7167}
7168
47c2bd97 7169static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7170{
fac5e23e 7171 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7172 enum pipe pipe;
1020a5c2 7173
7ad0dbab 7174 ilk_init_lp_watermarks(dev);
50ed5fbd 7175
ab57fff1 7176 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7177 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7178
ab57fff1 7179 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7180 I915_WRITE(CHICKEN_PAR1_1,
7181 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7182
ab57fff1 7183 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7184 for_each_pipe(dev_priv, pipe) {
07d27e20 7185 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7186 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7187 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7188 }
63801f21 7189
ab57fff1
BW		 7190 /* WaVSRefCountFullforceMissDisable:bdw */
7191 /* WaDSRefCountFullforceMissDisable:bdw */
7192 I915_WRITE(GEN7_FF_THREAD_MODE,
7193 I915_READ(GEN7_FF_THREAD_MODE) &
7194 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7195
295e8bb7
VS		 7196 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7197 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7198
7199 /* WaDisableSDEUnitClockGating:bdw */
7200 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7201 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7202
450174fe
ID		 7203 /* WaProgramL3SqcReg1Default:bdw */
7204 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7205
6d50b065
VS		 7206 /*
7207 * WaGttCachingOffByDefault:bdw
7208 * GTT cache may not work with big pages, so if those
7209 * are ever enabled GTT cache may need to be disabled.
7210 */
7211 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7212
17e0adf0
MK		 7213 /* WaKVMNotificationOnConfigChange:bdw */
7214 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7215 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7216
89d6b2b8 7217 lpt_init_clock_gating(dev);
1020a5c2
BW		 7218}
7219
cad2a2d7
ED		 7220static void haswell_init_clock_gating(struct drm_device *dev)
7221{
fac5e23e 7222 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7223
017636cc 7224 ilk_init_lp_watermarks(dev);
cad2a2d7 7225
f3fc4884
FJ		 7226 /* L3 caching of data atomics doesn't work -- disable it. */
7227 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7228 I915_WRITE(HSW_ROW_CHICKEN3,
7229 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7230
ecdb4eb7 7231 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7232 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7233 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7234 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7235
e36ea7ff
VS		 7236 /* WaVSRefCountFullforceMissDisable:hsw */
7237 I915_WRITE(GEN7_FF_THREAD_MODE,
7238 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7239
4e04632e
AG		 7240 /* WaDisable_RenderCache_OperationalFlush:hsw */
7241 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7242
fe27c606
CW		 7243 /* enable HiZ Raw Stall Optimization */
7244 I915_WRITE(CACHE_MODE_0_GEN7,
7245 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7246
ecdb4eb7 7247 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7248 I915_WRITE(CACHE_MODE_1,
7249 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7250
a12c4967
VS		 7251 /*
7252 * BSpec recommends 8x4 when MSAA is used,
7253 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7254 *
7255 * Note that PS/WM thread counts depend on the WIZ hashing
7256 * disable bit, which we don't touch here, but it's good
7257 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7258 */
7259 I915_WRITE(GEN7_GT_MODE,
98533251 7260 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7261
94411593
KG		 7262 /* WaSampleCChickenBitEnable:hsw */
7263 I915_WRITE(HALF_SLICE_CHICKEN3,
7264 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7265
ecdb4eb7 7266 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7267 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7268
90a88643
PZ		 7269 /* WaRsPkgCStateDisplayPMReq:hsw */
7270 I915_WRITE(CHICKEN_PAR1_1,
7271 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7272
17a303ec 7273 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7274}
7275
1fa61106 7276static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7277{
fac5e23e 7278 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7279 uint32_t snpcr;
6f1d69b0 7280
017636cc 7281 ilk_init_lp_watermarks(dev);
6f1d69b0 7282
231e54f6 7283 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7284
ecdb4eb7 7285 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7286 I915_WRITE(_3D_CHICKEN3,
7287 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7288
ecdb4eb7 7289 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7290 I915_WRITE(IVB_CHICKEN3,
7291 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7292 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7293
ecdb4eb7 7294 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7295 if (IS_IVB_GT1(dev))
7296 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7297 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7298
4e04632e
AG		 7299 /* WaDisable_RenderCache_OperationalFlush:ivb */
7300 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7301
ecdb4eb7 7302 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7303 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7304 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7305
ecdb4eb7 7306 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7307 I915_WRITE(GEN7_L3CNTLREG1,
7308 GEN7_WA_FOR_GEN7_L3_CONTROL);
7309 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7310 GEN7_WA_L3_CHICKEN_MODE);
7311 if (IS_IVB_GT1(dev))
7312 I915_WRITE(GEN7_ROW_CHICKEN2,
7313 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7314 else {
7315 /* must write both registers */
7316 I915_WRITE(GEN7_ROW_CHICKEN2,
7317 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7318 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7319 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7320 }
6f1d69b0 7321
ecdb4eb7 7322 /* WaForceL3Serialization:ivb */
61939d97
JB		 7323 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7324 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7325
1b80a19a 7326 /*
0f846f81 7327 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7328 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7329 */
7330 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7331 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7332
ecdb4eb7 7333 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7334 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7335 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7336 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7337
0e088b8f 7338 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7339
7340 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7341
22721343
CW		 7342 if (0) { /* causes HiZ corruption on ivb:gt1 */
7343 /* enable HiZ Raw Stall Optimization */
7344 I915_WRITE(CACHE_MODE_0_GEN7,
7345 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7346 }
116f2b6d 7347
ecdb4eb7 7348 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7349 I915_WRITE(CACHE_MODE_1,
7350 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7351
a607c1a4
VS		 7352 /*
7353 * BSpec recommends 8x4 when MSAA is used,
7354 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7355 *
7356 * Note that PS/WM thread counts depend on the WIZ hashing
7357 * disable bit, which we don't touch here, but it's good
7358 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7359 */
7360 I915_WRITE(GEN7_GT_MODE,
98533251 7361 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7362
20848223
BW		 7363 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7364 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7365 snpcr |= GEN6_MBC_SNPCR_MED;
7366 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7367
ab5c608b
BW		 7368 if (!HAS_PCH_NOP(dev))
7369 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7370
7371 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7372}
7373
1fa61106 7374static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7375{
fac5e23e 7376 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7377
ecdb4eb7 7378 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7379 I915_WRITE(_3D_CHICKEN3,
7380 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7381
ecdb4eb7 7382 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7383 I915_WRITE(IVB_CHICKEN3,
7384 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7385 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7386
fad7d36e 7387 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7388 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7389 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7390 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7391 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7392
4e04632e
AG		 7393 /* WaDisable_RenderCache_OperationalFlush:vlv */
7394 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7395
ecdb4eb7 7396 /* WaForceL3Serialization:vlv */
61939d97
JB		 7397 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7398 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7399
ecdb4eb7 7400 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7401 I915_WRITE(GEN7_ROW_CHICKEN2,
7402 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7403
ecdb4eb7 7404 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7405 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7406 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7407 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7408
46680e0a
VS		 7409 gen7_setup_fixed_func_scheduler(dev_priv);
7410
3c0edaeb 7411 /*
0f846f81 7412 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7413 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7414 */
7415 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7416 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7417
c98f5062
AG		 7418 /* WaDisableL3Bank2xClockGate:vlv
7419 * Disabling L3 clock gating- MMIO 940c[25] = 1
7420 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7421 I915_WRITE(GEN7_UCGCTL4,
7422 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7423
afd58e79
VS		 7424 /*
7425 * BSpec says this must be set, even though
7426 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7427 */
6b26c86d
DV		 7428 I915_WRITE(CACHE_MODE_1,
7429 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7430
da2518f9
VS		 7431 /*
7432 * BSpec recommends 8x4 when MSAA is used,
7433 * however in practice 16x4 seems fastest.
7434 *
7435 * Note that PS/WM thread counts depend on the WIZ hashing
7436 * disable bit, which we don't touch here, but it's good
7437 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7438 */
7439 I915_WRITE(GEN7_GT_MODE,
7440 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7441
031994ee
VS		 7442 /*
7443 * WaIncreaseL3CreditsForVLVB0:vlv
7444 * This is the hardware default actually.
7445 */
7446 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7447
2d809570 7448 /*
ecdb4eb7 7449 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7450 * Disable clock gating on th GCFG unit to prevent a delay
7451 * in the reporting of vblank events.
7452 */
7a0d1eed 7453 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7454}
7455
a4565da8
VS		 7456static void cherryview_init_clock_gating(struct drm_device *dev)
7457{
fac5e23e 7458 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7459
232ce337
VS		 7460 /* WaVSRefCountFullforceMissDisable:chv */
7461 /* WaDSRefCountFullforceMissDisable:chv */
7462 I915_WRITE(GEN7_FF_THREAD_MODE,
7463 I915_READ(GEN7_FF_THREAD_MODE) &
7464 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7465
7466 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7467 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7468 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7469
7470 /* WaDisableCSUnitClockGating:chv */
7471 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7472 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7473
7474 /* WaDisableSDEUnitClockGating:chv */
7475 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7476 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7477
450174fe
ID		 7478 /*
7479 * WaProgramL3SqcReg1Default:chv
7480 * See gfxspecs/Related Documents/Performance Guide/
7481 * LSQC Setting Recommendations.
7482 */
7483 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7484
6d50b065
VS		 7485 /*
7486 * GTT cache may not work with big pages, so if those
7487 * are ever enabled GTT cache may need to be disabled.
7488 */
7489 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7490}
7491
1fa61106 7492static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7493{
fac5e23e 7494 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7495 uint32_t dspclk_gate;
7496
7497 I915_WRITE(RENCLK_GATE_D1, 0);
7498 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7499 GS_UNIT_CLOCK_GATE_DISABLE |
7500 CL_UNIT_CLOCK_GATE_DISABLE);
7501 I915_WRITE(RAMCLK_GATE_D, 0);
7502 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7503 OVRUNIT_CLOCK_GATE_DISABLE |
7504 OVCUNIT_CLOCK_GATE_DISABLE;
7505 if (IS_GM45(dev))
7506 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7507 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7508
7509 /* WaDisableRenderCachePipelinedFlush */
7510 I915_WRITE(CACHE_MODE_0,
7511 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7512
4e04632e
AG		 7513 /* WaDisable_RenderCache_OperationalFlush:g4x */
7514 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7515
0e088b8f 7516 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7517}
7518
1fa61106 7519static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7520{
fac5e23e 7521 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7522
7523 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7524 I915_WRITE(RENCLK_GATE_D2, 0);
7525 I915_WRITE(DSPCLK_GATE_D, 0);
7526 I915_WRITE(RAMCLK_GATE_D, 0);
7527 I915_WRITE16(DEUC, 0);
20f94967
VS		 7528 I915_WRITE(MI_ARB_STATE,
7529 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7530
7531 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7532 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7533}
7534
1fa61106 7535static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7536{
fac5e23e 7537 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7538
7539 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7540 I965_RCC_CLOCK_GATE_DISABLE |
7541 I965_RCPB_CLOCK_GATE_DISABLE |
7542 I965_ISC_CLOCK_GATE_DISABLE |
7543 I965_FBC_CLOCK_GATE_DISABLE);
7544 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7545 I915_WRITE(MI_ARB_STATE,
7546 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7547
7548 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7549 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7550}
7551
1fa61106 7552static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7553{
fac5e23e 7554 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7555 u32 dstate = I915_READ(D_STATE);
7556
7557 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7558 DSTATE_DOT_CLOCK_GATING;
7559 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7560
7561 if (IS_PINEVIEW(dev))
7562 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7563
7564 /* IIR "flip pending" means done if this bit is set */
7565 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7566
7567 /* interrupts should cause a wake up from C3 */
3299254f 7568 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7569
7570 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7571 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7572
7573 I915_WRITE(MI_ARB_STATE,
7574 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7575}
7576
1fa61106 7577static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7578{
fac5e23e 7579 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7580
7581 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7582
7583 /* interrupts should cause a wake up from C3 */
7584 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7585 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7586
7587 I915_WRITE(MEM_MODE,
7588 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7589}
7590
1fa61106 7591static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7592{
fac5e23e 7593 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7594
7595 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7596
7597 I915_WRITE(MEM_MODE,
7598 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7599 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7600}
7601
6f1d69b0
ED		 7602void intel_init_clock_gating(struct drm_device *dev)
7603{
fac5e23e 7604 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7605
bb400da9 7606 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7607}
7608
7d708ee4
ID		 7609void intel_suspend_hw(struct drm_device *dev)
7610{
7611 if (HAS_PCH_LPT(dev))
7612 lpt_suspend_hw(dev);
7613}
7614
bb400da9
ID		 7615static void nop_init_clock_gating(struct drm_device *dev)
7616{
7617 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7618}
7619
7620/**
7621 * intel_init_clock_gating_hooks - setup the clock gating hooks
7622 * @dev_priv: device private
7623 *
7624 * Setup the hooks that configure which clocks of a given platform can be
7625 * gated and also apply various GT and display specific workarounds for these
7626 * platforms. Note that some GT specific workarounds are applied separately
7627 * when GPU contexts or batchbuffers start their execution.
7628 */
7629void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7630{
7631 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7632 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7633 else if (IS_KABYLAKE(dev_priv))
9498dba7 7634 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7635 else if (IS_BROXTON(dev_priv))
7636 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7637 else if (IS_BROADWELL(dev_priv))
7638 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7639 else if (IS_CHERRYVIEW(dev_priv))
7640 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7641 else if (IS_HASWELL(dev_priv))
7642 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7643 else if (IS_IVYBRIDGE(dev_priv))
7644 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7645 else if (IS_VALLEYVIEW(dev_priv))
7646 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7647 else if (IS_GEN6(dev_priv))
7648 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7649 else if (IS_GEN5(dev_priv))
7650 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7651 else if (IS_G4X(dev_priv))
7652 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7653 else if (IS_CRESTLINE(dev_priv))
7654 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7655 else if (IS_BROADWATER(dev_priv))
7656 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7657 else if (IS_GEN3(dev_priv))
7658 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7659 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7660 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7661 else if (IS_GEN2(dev_priv))
7662 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7663 else {
7664 MISSING_CASE(INTEL_DEVID(dev_priv));
7665 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7666 }
7667}
7668
1fa61106
ED		 7669/* Set up chip specific power management-related functions */
7670void intel_init_pm(struct drm_device *dev)
7671{
fac5e23e 7672 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7673
7ff0ebcc 7674 intel_fbc_init(dev_priv);
1fa61106 7675
c921aba8
DV		 7676 /* For cxsr */
7677 if (IS_PINEVIEW(dev))
7678 i915_pineview_get_mem_freq(dev);
7679 else if (IS_GEN5(dev))
7680 i915_ironlake_get_mem_freq(dev);
7681
1fa61106 7682 /* For FIFO watermark updates */
f5ed50cb 7683 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7684 skl_setup_wm_latency(dev);
2d41c0b5 7685 dev_priv->display.update_wm = skl_update_wm;
98d39494 7686 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7687 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7688 ilk_setup_wm_latency(dev);
53615a5e 7689
bd602544
VS		 7690 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7691 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7692 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7693 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7694 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7695 dev_priv->display.compute_intermediate_wm =
7696 ilk_compute_intermediate_wm;
7697 dev_priv->display.initial_watermarks =
7698 ilk_initial_watermarks;
7699 dev_priv->display.optimize_watermarks =
7700 ilk_optimize_watermarks;
bd602544
VS		 7701 } else {
7702 DRM_DEBUG_KMS("Failed to read display plane latency. "
7703 "Disable CxSR\n");
7704 }
a4565da8 7705 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7706 vlv_setup_wm_latency(dev);
262cd2e1 7707 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7708 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7709 vlv_setup_wm_latency(dev);
26e1fe4f 7710 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7711 } else if (IS_PINEVIEW(dev)) {
7712 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7713 dev_priv->is_ddr3,
7714 dev_priv->fsb_freq,
7715 dev_priv->mem_freq)) {
7716 DRM_INFO("failed to find known CxSR latency "
7717 "(found ddr%s fsb freq %d, mem freq %d), "
7718 "disabling CxSR\n",
7719 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7720 dev_priv->fsb_freq, dev_priv->mem_freq);
7721 /* Disable CxSR and never update its watermark again */
5209b1f4 7722 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7723 dev_priv->display.update_wm = NULL;
7724 } else
7725 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7726 } else if (IS_G4X(dev)) {
7727 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7728 } else if (IS_GEN4(dev)) {
7729 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7730 } else if (IS_GEN3(dev)) {
7731 dev_priv->display.update_wm = i9xx_update_wm;
7732 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7733 } else if (IS_GEN2(dev)) {
7734 if (INTEL_INFO(dev)->num_pipes == 1) {
7735 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7736 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7737 } else {
7738 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7739 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7740 }
feb56b93
DV		 7741 } else {
7742 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7743 }
7744}
7745
87660502
L		 7746static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7747{
7748 uint32_t flags =
7749 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7750
7751 switch (flags) {
7752 case GEN6_PCODE_SUCCESS:
7753 return 0;
7754 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7755 case GEN6_PCODE_ILLEGAL_CMD:
7756 return -ENXIO;
7757 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7758 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7759 return -EOVERFLOW;
7760 case GEN6_PCODE_TIMEOUT:
7761 return -ETIMEDOUT;
7762 default:
7763 MISSING_CASE(flags)
7764 return 0;
7765 }
7766}
7767
7768static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7769{
7770 uint32_t flags =
7771 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7772
7773 switch (flags) {
7774 case GEN6_PCODE_SUCCESS:
7775 return 0;
7776 case GEN6_PCODE_ILLEGAL_CMD:
7777 return -ENXIO;
7778 case GEN7_PCODE_TIMEOUT:
7779 return -ETIMEDOUT;
7780 case GEN7_PCODE_ILLEGAL_DATA:
7781 return -EINVAL;
7782 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7783 return -EOVERFLOW;
7784 default:
7785 MISSING_CASE(flags);
7786 return 0;
7787 }
7788}
7789
151a49d0 7790int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7791{
87660502
L		 7792 int status;
7793
4fc688ce 7794 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7795
3f5582dd
CW		 7796 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7797 * use te fw I915_READ variants to reduce the amount of work
7798 * required when reading/writing.
7799 */
7800
7801 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7802 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7803 return -EAGAIN;
7804 }
7805
3f5582dd
CW		 7806 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7807 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7808 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7809
3f5582dd
CW		 7810 if (intel_wait_for_register_fw(dev_priv,
7811 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7812 500)) {
42c0526c
BW		 7813 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7814 return -ETIMEDOUT;
7815 }
7816
3f5582dd
CW		 7817 *val = I915_READ_FW(GEN6_PCODE_DATA);
7818 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7819
87660502
L		 7820 if (INTEL_GEN(dev_priv) > 6)
7821 status = gen7_check_mailbox_status(dev_priv);
7822 else
7823 status = gen6_check_mailbox_status(dev_priv);
7824
7825 if (status) {
7826 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7827 status);
7828 return status;
7829 }
7830
42c0526c
BW		 7831 return 0;
7832}
7833
3f5582dd 7834int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7835 u32 mbox, u32 val)
42c0526c 7836{
87660502
L		 7837 int status;
7838
4fc688ce 7839 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7840
3f5582dd
CW		 7841 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7842 * use te fw I915_READ variants to reduce the amount of work
7843 * required when reading/writing.
7844 */
7845
7846 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7847 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7848 return -EAGAIN;
7849 }
7850
3f5582dd
CW		 7851 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7852 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7853
3f5582dd
CW		 7854 if (intel_wait_for_register_fw(dev_priv,
7855 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7856 500)) {
42c0526c
BW		 7857 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7858 return -ETIMEDOUT;
7859 }
7860
3f5582dd 7861 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7862
87660502
L		 7863 if (INTEL_GEN(dev_priv) > 6)
7864 status = gen7_check_mailbox_status(dev_priv);
7865 else
7866 status = gen6_check_mailbox_status(dev_priv);
7867
7868 if (status) {
7869 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7870 status);
7871 return status;
7872 }
7873
42c0526c
BW		 7874 return 0;
7875}
a0e4e199 7876
dd06f88c
VS		 7877static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7878{
c30fec65
VS		 7879 /*
7880 * N = val - 0xb7
7881 * Slow = Fast = GPLL ref * N
7882 */
7883 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7884}
7885
b55dd647 7886static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7887{
c30fec65 7888 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7889}
7890
b55dd647 7891static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7892{
c30fec65
VS		 7893 /*
7894 * N = val / 2
7895 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7896 */
7897 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7898}
7899
b55dd647 7900static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7901{
1c14762d 7902 /* CHV needs even values */
c30fec65 7903 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7904}
7905
616bc820 7906int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7907{
2d1fe073 7908 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7909 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7910 GEN9_FREQ_SCALER);
2d1fe073 7911 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7912 return chv_gpu_freq(dev_priv, val);
2d1fe073 7913 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7914 return byt_gpu_freq(dev_priv, val);
7915 else
7916 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7917}
7918
616bc820
VS		 7919int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7920{
2d1fe073 7921 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7922 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7923 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7924 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7925 return chv_freq_opcode(dev_priv, val);
2d1fe073 7926 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7927 return byt_freq_opcode(dev_priv, val);
7928 else
500a3d2e 7929 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7930}
22b1b2f8 7931
6ad790c0
CW		 7932struct request_boost {
7933 struct work_struct work;
eed29a5b 7934 struct drm_i915_gem_request *req;
6ad790c0
CW		 7935};
7936
7937static void __intel_rps_boost_work(struct work_struct *work)
7938{
7939 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7940 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7941
f69a02c9 7942 if (!i915_gem_request_completed(req))
c033666a 7943 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7944
e8a261ea 7945 i915_gem_request_put(req);
6ad790c0
CW		 7946 kfree(boost);
7947}
7948
91d14251 7949void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7950{
7951 struct request_boost *boost;
7952
91d14251 7953 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7954 return;
7955
f69a02c9 7956 if (i915_gem_request_completed(req))
e61b9958
CW		 7957 return;
7958
6ad790c0
CW		 7959 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7960 if (boost == NULL)
7961 return;
7962
e8a261ea 7963 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7964
7965 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7966 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7967}
7968
f742a552 7969void intel_pm_setup(struct drm_device *dev)
907b28c5 7970{
fac5e23e 7971 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 7972
f742a552 7973 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7974 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7975
54b4f68f
CW		 7976 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7977 __intel_autoenable_gt_powersave);
1854d5ca 7978 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 7979
33688d95 7980 dev_priv->pm.suspended = false;
1f814dac 7981 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7982 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7983}
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