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drm/i915/gen9: Add WaEnableChickenDCPR
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
b033bb6d
MK		 72}
73
74static void bxt_init_clock_gating(struct drm_device *dev)
75{
76 struct drm_i915_private *dev_priv = dev->dev_private;
77
78 gen9_init_clock_gating(dev);
79
a7546159
NH		 80 /* WaDisableSDEUnitClockGating:bxt */
81 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
82 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
83
32608ca2
ID		 84 /*
85 * FIXME:
868434c5 86 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 87 */
32608ca2 88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 89 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 90
91 /*
92 * Wa: Backlight PWM may stop in the asserted state, causing backlight
93 * to stay fully on.
94 */
95 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
96 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
97 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 98}
99
c921aba8
DV		 100static void i915_pineview_get_mem_freq(struct drm_device *dev)
101{
50227e1c 102 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 103 u32 tmp;
104
105 tmp = I915_READ(CLKCFG);
106
107 switch (tmp & CLKCFG_FSB_MASK) {
108 case CLKCFG_FSB_533:
109 dev_priv->fsb_freq = 533; /* 133*4 */
110 break;
111 case CLKCFG_FSB_800:
112 dev_priv->fsb_freq = 800; /* 200*4 */
113 break;
114 case CLKCFG_FSB_667:
115 dev_priv->fsb_freq = 667; /* 167*4 */
116 break;
117 case CLKCFG_FSB_400:
118 dev_priv->fsb_freq = 400; /* 100*4 */
119 break;
120 }
121
122 switch (tmp & CLKCFG_MEM_MASK) {
123 case CLKCFG_MEM_533:
124 dev_priv->mem_freq = 533;
125 break;
126 case CLKCFG_MEM_667:
127 dev_priv->mem_freq = 667;
128 break;
129 case CLKCFG_MEM_800:
130 dev_priv->mem_freq = 800;
131 break;
132 }
133
134 /* detect pineview DDR3 setting */
135 tmp = I915_READ(CSHRDDR3CTL);
136 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
137}
138
139static void i915_ironlake_get_mem_freq(struct drm_device *dev)
140{
50227e1c 141 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 142 u16 ddrpll, csipll;
143
144 ddrpll = I915_READ16(DDRMPLL1);
145 csipll = I915_READ16(CSIPLL0);
146
147 switch (ddrpll & 0xff) {
148 case 0xc:
149 dev_priv->mem_freq = 800;
150 break;
151 case 0x10:
152 dev_priv->mem_freq = 1066;
153 break;
154 case 0x14:
155 dev_priv->mem_freq = 1333;
156 break;
157 case 0x18:
158 dev_priv->mem_freq = 1600;
159 break;
160 default:
161 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
162 ddrpll & 0xff);
163 dev_priv->mem_freq = 0;
164 break;
165 }
166
20e4d407 167 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 168
169 switch (csipll & 0x3ff) {
170 case 0x00c:
171 dev_priv->fsb_freq = 3200;
172 break;
173 case 0x00e:
174 dev_priv->fsb_freq = 3733;
175 break;
176 case 0x010:
177 dev_priv->fsb_freq = 4266;
178 break;
179 case 0x012:
180 dev_priv->fsb_freq = 4800;
181 break;
182 case 0x014:
183 dev_priv->fsb_freq = 5333;
184 break;
185 case 0x016:
186 dev_priv->fsb_freq = 5866;
187 break;
188 case 0x018:
189 dev_priv->fsb_freq = 6400;
190 break;
191 default:
192 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
193 csipll & 0x3ff);
194 dev_priv->fsb_freq = 0;
195 break;
196 }
197
198 if (dev_priv->fsb_freq == 3200) {
20e4d407 199 dev_priv->ips.c_m = 0;
c921aba8 200 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 201 dev_priv->ips.c_m = 1;
c921aba8 202 } else {
20e4d407 203 dev_priv->ips.c_m = 2;
c921aba8
DV		 204 }
205}
206
b445e3b0
ED		 207static const struct cxsr_latency cxsr_latency_table[] = {
208 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
209 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
210 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
211 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
212 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
213
214 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
215 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
216 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
217 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
218 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
219
220 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
221 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
222 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
223 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
224 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
225
226 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
227 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
228 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
229 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
230 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
231
232 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
233 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
234 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
235 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
236 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
237
238 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
239 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
240 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
241 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
242 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
243};
244
63c62275 245static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 246 int is_ddr3,
247 int fsb,
248 int mem)
249{
250 const struct cxsr_latency *latency;
251 int i;
252
253 if (fsb == 0 || mem == 0)
254 return NULL;
255
256 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
257 latency = &cxsr_latency_table[i];
258 if (is_desktop == latency->is_desktop &&
259 is_ddr3 == latency->is_ddr3 &&
260 fsb == latency->fsb_freq && mem == latency->mem_freq)
261 return latency;
262 }
263
264 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
265
266 return NULL;
267}
268
fc1ac8de
VS		 269static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
270{
271 u32 val;
272
273 mutex_lock(&dev_priv->rps.hw_lock);
274
275 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
276 if (enable)
277 val &= ~FORCE_DDR_HIGH_FREQ;
278 else
279 val |= FORCE_DDR_HIGH_FREQ;
280 val &= ~FORCE_DDR_LOW_FREQ;
281 val |= FORCE_DDR_FREQ_REQ_ACK;
282 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
283
284 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
285 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
286 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
287
288 mutex_unlock(&dev_priv->rps.hw_lock);
289}
290
cfb41411
VS		 291static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
292{
293 u32 val;
294
295 mutex_lock(&dev_priv->rps.hw_lock);
296
297 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
298 if (enable)
299 val |= DSP_MAXFIFO_PM5_ENABLE;
300 else
301 val &= ~DSP_MAXFIFO_PM5_ENABLE;
302 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
303
304 mutex_unlock(&dev_priv->rps.hw_lock);
305}
306
f4998963
VS		 307#define FW_WM(value, plane) \
308 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
309
5209b1f4 310void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 311{
5209b1f4
ID		 312 struct drm_device *dev = dev_priv->dev;
313 u32 val;
b445e3b0 314
666a4537 315 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 316 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 317 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 318 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 319 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
320 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 321 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 322 } else if (IS_PINEVIEW(dev)) {
323 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
324 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
325 I915_WRITE(DSPFW3, val);
a7a6c498 326 POSTING_READ(DSPFW3);
5209b1f4
ID		 327 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
328 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
329 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
330 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_I915GM(dev)) {
333 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
334 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
335 I915_WRITE(INSTPM, val);
a7a6c498 336 POSTING_READ(INSTPM);
5209b1f4
ID		 337 } else {
338 return;
339 }
b445e3b0 340
5209b1f4
ID		 341 DRM_DEBUG_KMS("memory self-refresh is %s\n",
342 enable ? "enabled" : "disabled");
b445e3b0
ED		 343}
344
fc1ac8de 345
b445e3b0
ED		 346/*
347 * Latency for FIFO fetches is dependent on several factors:
348 * - memory configuration (speed, channels)
349 * - chipset
350 * - current MCH state
351 * It can be fairly high in some situations, so here we assume a fairly
352 * pessimal value. It's a tradeoff between extra memory fetches (if we
353 * set this value too high, the FIFO will fetch frequently to stay full)
354 * and power consumption (set it too low to save power and we might see
355 * FIFO underruns and display "flicker").
356 *
357 * A value of 5us seems to be a good balance; safe for very low end
358 * platforms but not overly aggressive on lower latency configs.
359 */
5aef6003 360static const int pessimal_latency_ns = 5000;
b445e3b0 361
b5004720
VS		 362#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
363 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
364
365static int vlv_get_fifo_size(struct drm_device *dev,
366 enum pipe pipe, int plane)
367{
368 struct drm_i915_private *dev_priv = dev->dev_private;
369 int sprite0_start, sprite1_start, size;
370
371 switch (pipe) {
372 uint32_t dsparb, dsparb2, dsparb3;
373 case PIPE_A:
374 dsparb = I915_READ(DSPARB);
375 dsparb2 = I915_READ(DSPARB2);
376 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
377 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
378 break;
379 case PIPE_B:
380 dsparb = I915_READ(DSPARB);
381 dsparb2 = I915_READ(DSPARB2);
382 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
383 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
384 break;
385 case PIPE_C:
386 dsparb2 = I915_READ(DSPARB2);
387 dsparb3 = I915_READ(DSPARB3);
388 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
389 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
390 break;
391 default:
392 return 0;
393 }
394
395 switch (plane) {
396 case 0:
397 size = sprite0_start;
398 break;
399 case 1:
400 size = sprite1_start - sprite0_start;
401 break;
402 case 2:
403 size = 512 - 1 - sprite1_start;
404 break;
405 default:
406 return 0;
407 }
408
409 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
410 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
411 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
412 size);
413
414 return size;
415}
416
1fa61106 417static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 418{
419 struct drm_i915_private *dev_priv = dev->dev_private;
420 uint32_t dsparb = I915_READ(DSPARB);
421 int size;
422
423 size = dsparb & 0x7f;
424 if (plane)
425 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
426
427 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
428 plane ? "B" : "A", size);
429
430 return size;
431}
432
feb56b93 433static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 434{
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 uint32_t dsparb = I915_READ(DSPARB);
437 int size;
438
439 size = dsparb & 0x1ff;
440 if (plane)
441 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
442 size >>= 1; /* Convert to cachelines */
443
444 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
445 plane ? "B" : "A", size);
446
447 return size;
448}
449
1fa61106 450static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 451{
452 struct drm_i915_private *dev_priv = dev->dev_private;
453 uint32_t dsparb = I915_READ(DSPARB);
454 int size;
455
456 size = dsparb & 0x7f;
457 size >>= 2; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A",
461 size);
462
463 return size;
464}
465
b445e3b0
ED		 466/* Pineview has different values for various configs */
467static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 468 .fifo_size = PINEVIEW_DISPLAY_FIFO,
469 .max_wm = PINEVIEW_MAX_WM,
470 .default_wm = PINEVIEW_DFT_WM,
471 .guard_size = PINEVIEW_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 473};
474static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 475 .fifo_size = PINEVIEW_DISPLAY_FIFO,
476 .max_wm = PINEVIEW_MAX_WM,
477 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
478 .guard_size = PINEVIEW_GUARD_WM,
479 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 480};
481static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 482 .fifo_size = PINEVIEW_CURSOR_FIFO,
483 .max_wm = PINEVIEW_CURSOR_MAX_WM,
484 .default_wm = PINEVIEW_CURSOR_DFT_WM,
485 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
486 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 487};
488static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 489 .fifo_size = PINEVIEW_CURSOR_FIFO,
490 .max_wm = PINEVIEW_CURSOR_MAX_WM,
491 .default_wm = PINEVIEW_CURSOR_DFT_WM,
492 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
493 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 494};
495static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 496 .fifo_size = G4X_FIFO_SIZE,
497 .max_wm = G4X_MAX_WM,
498 .default_wm = G4X_MAX_WM,
499 .guard_size = 2,
500 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 503 .fifo_size = I965_CURSOR_FIFO,
504 .max_wm = I965_CURSOR_MAX_WM,
505 .default_wm = I965_CURSOR_DFT_WM,
506 .guard_size = 2,
507 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 508};
b445e3b0 509static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 510 .fifo_size = I965_CURSOR_FIFO,
511 .max_wm = I965_CURSOR_MAX_WM,
512 .default_wm = I965_CURSOR_DFT_WM,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 517 .fifo_size = I945_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 522};
523static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 524 .fifo_size = I915_FIFO_SIZE,
525 .max_wm = I915_MAX_WM,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 529};
9d539105 530static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 531 .fifo_size = I855GM_FIFO_SIZE,
532 .max_wm = I915_MAX_WM,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 536};
9d539105
VS		 537static const struct intel_watermark_params i830_bc_wm_info = {
538 .fifo_size = I855GM_FIFO_SIZE,
539 .max_wm = I915_MAX_WM/2,
540 .default_wm = 1,
541 .guard_size = 2,
542 .cacheline_size = I830_FIFO_LINE_SIZE,
543};
feb56b93 544static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 545 .fifo_size = I830_FIFO_SIZE,
546 .max_wm = I915_MAX_WM,
547 .default_wm = 1,
548 .guard_size = 2,
549 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 550};
551
b445e3b0
ED		 552/**
553 * intel_calculate_wm - calculate watermark level
554 * @clock_in_khz: pixel clock
555 * @wm: chip FIFO params
ac484963 556 * @cpp: bytes per pixel
b445e3b0
ED		 557 * @latency_ns: memory latency for the platform
558 *
559 * Calculate the watermark level (the level at which the display plane will
560 * start fetching from memory again). Each chip has a different display
561 * FIFO size and allocation, so the caller needs to figure that out and pass
562 * in the correct intel_watermark_params structure.
563 *
564 * As the pixel clock runs, the FIFO will be drained at a rate that depends
565 * on the pixel size. When it reaches the watermark level, it'll start
566 * fetching FIFO line sized based chunks from memory until the FIFO fills
567 * past the watermark point. If the FIFO drains completely, a FIFO underrun
568 * will occur, and a display engine hang could result.
569 */
570static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
571 const struct intel_watermark_params *wm,
ac484963 572 int fifo_size, int cpp,
b445e3b0
ED		 573 unsigned long latency_ns)
574{
575 long entries_required, wm_size;
576
577 /*
578 * Note: we need to make sure we don't overflow for various clock &
579 * latency values.
580 * clocks go from a few thousand to several hundred thousand.
581 * latency is usually a few thousand
582 */
ac484963 583 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 584 1000;
585 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
586
587 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
588
589 wm_size = fifo_size - (entries_required + wm->guard_size);
590
591 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
592
593 /* Don't promote wm_size to unsigned... */
594 if (wm_size > (long)wm->max_wm)
595 wm_size = wm->max_wm;
596 if (wm_size <= 0)
597 wm_size = wm->default_wm;
d6feb196
VS		 598
599 /*
600 * Bspec seems to indicate that the value shouldn't be lower than
601 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
602 * Lets go for 8 which is the burst size since certain platforms
603 * already use a hardcoded 8 (which is what the spec says should be
604 * done).
605 */
606 if (wm_size <= 8)
607 wm_size = 8;
608
b445e3b0
ED		 609 return wm_size;
610}
611
612static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
613{
614 struct drm_crtc *crtc, *enabled = NULL;
615
70e1e0ec 616 for_each_crtc(dev, crtc) {
3490ea5d 617 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 618 if (enabled)
619 return NULL;
620 enabled = crtc;
621 }
622 }
623
624 return enabled;
625}
626
46ba614c 627static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 628{
46ba614c 629 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 630 struct drm_i915_private *dev_priv = dev->dev_private;
631 struct drm_crtc *crtc;
632 const struct cxsr_latency *latency;
633 u32 reg;
634 unsigned long wm;
635
636 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
637 dev_priv->fsb_freq, dev_priv->mem_freq);
638 if (!latency) {
639 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 640 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 641 return;
642 }
643
644 crtc = single_enabled_crtc(dev);
645 if (crtc) {
7c5f93b0 646 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 647 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 648 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 649
650 /* Display SR */
651 wm = intel_calculate_wm(clock, &pineview_display_wm,
652 pineview_display_wm.fifo_size,
ac484963 653 cpp, latency->display_sr);
b445e3b0
ED		 654 reg = I915_READ(DSPFW1);
655 reg &= ~DSPFW_SR_MASK;
f4998963 656 reg |= FW_WM(wm, SR);
b445e3b0
ED		 657 I915_WRITE(DSPFW1, reg);
658 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
659
660 /* cursor SR */
661 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
662 pineview_display_wm.fifo_size,
ac484963 663 cpp, latency->cursor_sr);
b445e3b0
ED		 664 reg = I915_READ(DSPFW3);
665 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 666 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 667 I915_WRITE(DSPFW3, reg);
668
669 /* Display HPLL off SR */
670 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
671 pineview_display_hplloff_wm.fifo_size,
ac484963 672 cpp, latency->display_hpll_disable);
b445e3b0
ED		 673 reg = I915_READ(DSPFW3);
674 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 675 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 676 I915_WRITE(DSPFW3, reg);
677
678 /* cursor HPLL off SR */
679 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
680 pineview_display_hplloff_wm.fifo_size,
ac484963 681 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 682 reg = I915_READ(DSPFW3);
683 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 684 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 685 I915_WRITE(DSPFW3, reg);
686 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
687
5209b1f4 688 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 689 } else {
5209b1f4 690 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 691 }
692}
693
694static bool g4x_compute_wm0(struct drm_device *dev,
695 int plane,
696 const struct intel_watermark_params *display,
697 int display_latency_ns,
698 const struct intel_watermark_params *cursor,
699 int cursor_latency_ns,
700 int *plane_wm,
701 int *cursor_wm)
702{
703 struct drm_crtc *crtc;
4fe8590a 704 const struct drm_display_mode *adjusted_mode;
ac484963 705 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 706 int line_time_us, line_count;
707 int entries, tlb_miss;
708
709 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 710 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 711 *cursor_wm = cursor->guard_size;
712 *plane_wm = display->guard_size;
713 return false;
714 }
715
6e3c9717 716 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 717 clock = adjusted_mode->crtc_clock;
fec8cba3 718 htotal = adjusted_mode->crtc_htotal;
6e3c9717 719 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 720 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 721
722 /* Use the small buffer method to calculate plane watermark */
ac484963 723 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 724 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
725 if (tlb_miss > 0)
726 entries += tlb_miss;
727 entries = DIV_ROUND_UP(entries, display->cacheline_size);
728 *plane_wm = entries + display->guard_size;
729 if (*plane_wm > (int)display->max_wm)
730 *plane_wm = display->max_wm;
731
732 /* Use the large buffer method to calculate cursor watermark */
922044c9 733 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 734 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 735 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 736 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
737 if (tlb_miss > 0)
738 entries += tlb_miss;
739 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
740 *cursor_wm = entries + cursor->guard_size;
741 if (*cursor_wm > (int)cursor->max_wm)
742 *cursor_wm = (int)cursor->max_wm;
743
744 return true;
745}
746
747/*
748 * Check the wm result.
749 *
750 * If any calculated watermark values is larger than the maximum value that
751 * can be programmed into the associated watermark register, that watermark
752 * must be disabled.
753 */
754static bool g4x_check_srwm(struct drm_device *dev,
755 int display_wm, int cursor_wm,
756 const struct intel_watermark_params *display,
757 const struct intel_watermark_params *cursor)
758{
759 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
760 display_wm, cursor_wm);
761
762 if (display_wm > display->max_wm) {
763 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
764 display_wm, display->max_wm);
765 return false;
766 }
767
768 if (cursor_wm > cursor->max_wm) {
769 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
770 cursor_wm, cursor->max_wm);
771 return false;
772 }
773
774 if (!(display_wm || cursor_wm)) {
775 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
776 return false;
777 }
778
779 return true;
780}
781
782static bool g4x_compute_srwm(struct drm_device *dev,
783 int plane,
784 int latency_ns,
785 const struct intel_watermark_params *display,
786 const struct intel_watermark_params *cursor,
787 int *display_wm, int *cursor_wm)
788{
789 struct drm_crtc *crtc;
4fe8590a 790 const struct drm_display_mode *adjusted_mode;
ac484963 791 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 792 unsigned long line_time_us;
793 int line_count, line_size;
794 int small, large;
795 int entries;
796
797 if (!latency_ns) {
798 *display_wm = *cursor_wm = 0;
799 return false;
800 }
801
802 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 803 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 804 clock = adjusted_mode->crtc_clock;
fec8cba3 805 htotal = adjusted_mode->crtc_htotal;
6e3c9717 806 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 807 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 808
922044c9 809 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 810 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 811 line_size = hdisplay * cpp;
b445e3b0
ED		 812
813 /* Use the minimum of the small and large buffer method for primary */
ac484963 814 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 815 large = line_count * line_size;
816
817 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
818 *display_wm = entries + display->guard_size;
819
820 /* calculate the self-refresh watermark for display cursor */
ac484963 821 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 822 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
823 *cursor_wm = entries + cursor->guard_size;
824
825 return g4x_check_srwm(dev,
826 *display_wm, *cursor_wm,
827 display, cursor);
828}
829
15665979
VS		 830#define FW_WM_VLV(value, plane) \
831 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
832
0018fda1
VS		 833static void vlv_write_wm_values(struct intel_crtc *crtc,
834 const struct vlv_wm_values *wm)
835{
836 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
837 enum pipe pipe = crtc->pipe;
838
839 I915_WRITE(VLV_DDL(pipe),
840 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
841 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
842 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
843 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
844
ae80152d 845 I915_WRITE(DSPFW1,
15665979
VS		 846 FW_WM(wm->sr.plane, SR) |
847 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
848 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
849 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 850 I915_WRITE(DSPFW2,
15665979
VS		 851 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
852 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
853 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 854 I915_WRITE(DSPFW3,
15665979 855 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 856
857 if (IS_CHERRYVIEW(dev_priv)) {
858 I915_WRITE(DSPFW7_CHV,
15665979
VS		 859 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
860 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 861 I915_WRITE(DSPFW8_CHV,
15665979
VS		 862 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
863 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 864 I915_WRITE(DSPFW9_CHV,
15665979
VS		 865 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
866 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 867 I915_WRITE(DSPHOWM,
15665979
VS		 868 FW_WM(wm->sr.plane >> 9, SR_HI) |
869 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
870 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
871 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
872 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
873 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
874 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
875 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
876 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
877 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 878 } else {
879 I915_WRITE(DSPFW7,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
881 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
885 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
886 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
887 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
888 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
889 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 890 }
891
2cb389b7
VS		 892 /* zero (unused) WM1 watermarks */
893 I915_WRITE(DSPFW4, 0);
894 I915_WRITE(DSPFW5, 0);
895 I915_WRITE(DSPFW6, 0);
896 I915_WRITE(DSPHOWM1, 0);
897
ae80152d 898 POSTING_READ(DSPFW1);
0018fda1
VS		 899}
900
15665979
VS		 901#undef FW_WM_VLV
902
6eb1a681
VS		 903enum vlv_wm_level {
904 VLV_WM_LEVEL_PM2,
905 VLV_WM_LEVEL_PM5,
906 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 907};
908
262cd2e1
VS		 909/* latency must be in 0.1us units. */
910static unsigned int vlv_wm_method2(unsigned int pixel_rate,
911 unsigned int pipe_htotal,
912 unsigned int horiz_pixels,
ac484963 913 unsigned int cpp,
262cd2e1
VS		 914 unsigned int latency)
915{
916 unsigned int ret;
917
918 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 919 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 920 ret = DIV_ROUND_UP(ret, 64);
921
922 return ret;
923}
924
925static void vlv_setup_wm_latency(struct drm_device *dev)
926{
927 struct drm_i915_private *dev_priv = dev->dev_private;
928
929 /* all latencies in usec */
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
931
58590c14
VS		 932 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
933
262cd2e1
VS		 934 if (IS_CHERRYVIEW(dev_priv)) {
935 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
936 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 937
938 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 939 }
940}
941
942static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
943 struct intel_crtc *crtc,
944 const struct intel_plane_state *state,
945 int level)
946{
947 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 948 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 949
950 if (dev_priv->wm.pri_latency[level] == 0)
951 return USHRT_MAX;
952
953 if (!state->visible)
954 return 0;
955
ac484963 956 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 957 clock = crtc->config->base.adjusted_mode.crtc_clock;
958 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
959 width = crtc->config->pipe_src_w;
960 if (WARN_ON(htotal == 0))
961 htotal = 1;
962
963 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
964 /*
965 * FIXME the formula gives values that are
966 * too big for the cursor FIFO, and hence we
967 * would never be able to use cursors. For
968 * now just hardcode the watermark.
969 */
970 wm = 63;
971 } else {
ac484963 972 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 973 dev_priv->wm.pri_latency[level] * 10);
974 }
975
976 return min_t(int, wm, USHRT_MAX);
977}
978
54f1b6e1
VS		 979static void vlv_compute_fifo(struct intel_crtc *crtc)
980{
981 struct drm_device *dev = crtc->base.dev;
982 struct vlv_wm_state *wm_state = &crtc->wm_state;
983 struct intel_plane *plane;
984 unsigned int total_rate = 0;
985 const int fifo_size = 512 - 1;
986 int fifo_extra, fifo_left = fifo_size;
987
988 for_each_intel_plane_on_crtc(dev, crtc, plane) {
989 struct intel_plane_state *state =
990 to_intel_plane_state(plane->base.state);
991
992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
993 continue;
994
995 if (state->visible) {
996 wm_state->num_active_planes++;
997 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 }
999 }
1000
1001 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1002 struct intel_plane_state *state =
1003 to_intel_plane_state(plane->base.state);
1004 unsigned int rate;
1005
1006 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007 plane->wm.fifo_size = 63;
1008 continue;
1009 }
1010
1011 if (!state->visible) {
1012 plane->wm.fifo_size = 0;
1013 continue;
1014 }
1015
1016 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1017 plane->wm.fifo_size = fifo_size * rate / total_rate;
1018 fifo_left -= plane->wm.fifo_size;
1019 }
1020
1021 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1022
1023 /* spread the remainder evenly */
1024 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1025 int plane_extra;
1026
1027 if (fifo_left == 0)
1028 break;
1029
1030 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1031 continue;
1032
1033 /* give it all to the first plane if none are active */
1034 if (plane->wm.fifo_size == 0 &&
1035 wm_state->num_active_planes)
1036 continue;
1037
1038 plane_extra = min(fifo_extra, fifo_left);
1039 plane->wm.fifo_size += plane_extra;
1040 fifo_left -= plane_extra;
1041 }
1042
1043 WARN_ON(fifo_left != 0);
1044}
1045
262cd2e1
VS		 1046static void vlv_invert_wms(struct intel_crtc *crtc)
1047{
1048 struct vlv_wm_state *wm_state = &crtc->wm_state;
1049 int level;
1050
1051 for (level = 0; level < wm_state->num_levels; level++) {
1052 struct drm_device *dev = crtc->base.dev;
1053 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1054 struct intel_plane *plane;
1055
1056 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1057 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1058
1059 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1060 switch (plane->base.type) {
1061 int sprite;
1062 case DRM_PLANE_TYPE_CURSOR:
1063 wm_state->wm[level].cursor = plane->wm.fifo_size -
1064 wm_state->wm[level].cursor;
1065 break;
1066 case DRM_PLANE_TYPE_PRIMARY:
1067 wm_state->wm[level].primary = plane->wm.fifo_size -
1068 wm_state->wm[level].primary;
1069 break;
1070 case DRM_PLANE_TYPE_OVERLAY:
1071 sprite = plane->plane;
1072 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1073 wm_state->wm[level].sprite[sprite];
1074 break;
1075 }
1076 }
1077 }
1078}
1079
26e1fe4f 1080static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1081{
1082 struct drm_device *dev = crtc->base.dev;
1083 struct vlv_wm_state *wm_state = &crtc->wm_state;
1084 struct intel_plane *plane;
1085 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1086 int level;
1087
1088 memset(wm_state, 0, sizeof(*wm_state));
1089
852eb00d 1090 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1091 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1092
1093 wm_state->num_active_planes = 0;
262cd2e1 1094
54f1b6e1 1095 vlv_compute_fifo(crtc);
262cd2e1
VS		 1096
1097 if (wm_state->num_active_planes != 1)
1098 wm_state->cxsr = false;
1099
1100 if (wm_state->cxsr) {
1101 for (level = 0; level < wm_state->num_levels; level++) {
1102 wm_state->sr[level].plane = sr_fifo_size;
1103 wm_state->sr[level].cursor = 63;
1104 }
1105 }
1106
1107 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1108 struct intel_plane_state *state =
1109 to_intel_plane_state(plane->base.state);
1110
1111 if (!state->visible)
1112 continue;
1113
1114 /* normal watermarks */
1115 for (level = 0; level < wm_state->num_levels; level++) {
1116 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1117 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1118
1119 /* hack */
1120 if (WARN_ON(level == 0 && wm > max_wm))
1121 wm = max_wm;
1122
1123 if (wm > plane->wm.fifo_size)
1124 break;
1125
1126 switch (plane->base.type) {
1127 int sprite;
1128 case DRM_PLANE_TYPE_CURSOR:
1129 wm_state->wm[level].cursor = wm;
1130 break;
1131 case DRM_PLANE_TYPE_PRIMARY:
1132 wm_state->wm[level].primary = wm;
1133 break;
1134 case DRM_PLANE_TYPE_OVERLAY:
1135 sprite = plane->plane;
1136 wm_state->wm[level].sprite[sprite] = wm;
1137 break;
1138 }
1139 }
1140
1141 wm_state->num_levels = level;
1142
1143 if (!wm_state->cxsr)
1144 continue;
1145
1146 /* maxfifo watermarks */
1147 switch (plane->base.type) {
1148 int sprite, level;
1149 case DRM_PLANE_TYPE_CURSOR:
1150 for (level = 0; level < wm_state->num_levels; level++)
1151 wm_state->sr[level].cursor =
5a37ed0a 1152 wm_state->wm[level].cursor;
262cd2e1
VS		 1153 break;
1154 case DRM_PLANE_TYPE_PRIMARY:
1155 for (level = 0; level < wm_state->num_levels; level++)
1156 wm_state->sr[level].plane =
1157 min(wm_state->sr[level].plane,
1158 wm_state->wm[level].primary);
1159 break;
1160 case DRM_PLANE_TYPE_OVERLAY:
1161 sprite = plane->plane;
1162 for (level = 0; level < wm_state->num_levels; level++)
1163 wm_state->sr[level].plane =
1164 min(wm_state->sr[level].plane,
1165 wm_state->wm[level].sprite[sprite]);
1166 break;
1167 }
1168 }
1169
1170 /* clear any (partially) filled invalid levels */
58590c14 1171 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1172 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1173 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1174 }
1175
1176 vlv_invert_wms(crtc);
1177}
1178
54f1b6e1
VS		 1179#define VLV_FIFO(plane, value) \
1180 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1181
1182static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1183{
1184 struct drm_device *dev = crtc->base.dev;
1185 struct drm_i915_private *dev_priv = to_i915(dev);
1186 struct intel_plane *plane;
1187 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1188
1189 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1190 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1191 WARN_ON(plane->wm.fifo_size != 63);
1192 continue;
1193 }
1194
1195 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1196 sprite0_start = plane->wm.fifo_size;
1197 else if (plane->plane == 0)
1198 sprite1_start = sprite0_start + plane->wm.fifo_size;
1199 else
1200 fifo_size = sprite1_start + plane->wm.fifo_size;
1201 }
1202
1203 WARN_ON(fifo_size != 512 - 1);
1204
1205 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1206 pipe_name(crtc->pipe), sprite0_start,
1207 sprite1_start, fifo_size);
1208
1209 switch (crtc->pipe) {
1210 uint32_t dsparb, dsparb2, dsparb3;
1211 case PIPE_A:
1212 dsparb = I915_READ(DSPARB);
1213 dsparb2 = I915_READ(DSPARB2);
1214
1215 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1216 VLV_FIFO(SPRITEB, 0xff));
1217 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1218 VLV_FIFO(SPRITEB, sprite1_start));
1219
1220 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1221 VLV_FIFO(SPRITEB_HI, 0x1));
1222 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1223 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1224
1225 I915_WRITE(DSPARB, dsparb);
1226 I915_WRITE(DSPARB2, dsparb2);
1227 break;
1228 case PIPE_B:
1229 dsparb = I915_READ(DSPARB);
1230 dsparb2 = I915_READ(DSPARB2);
1231
1232 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1233 VLV_FIFO(SPRITED, 0xff));
1234 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1235 VLV_FIFO(SPRITED, sprite1_start));
1236
1237 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1238 VLV_FIFO(SPRITED_HI, 0xff));
1239 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1240 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1241
1242 I915_WRITE(DSPARB, dsparb);
1243 I915_WRITE(DSPARB2, dsparb2);
1244 break;
1245 case PIPE_C:
1246 dsparb3 = I915_READ(DSPARB3);
1247 dsparb2 = I915_READ(DSPARB2);
1248
1249 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1250 VLV_FIFO(SPRITEF, 0xff));
1251 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1252 VLV_FIFO(SPRITEF, sprite1_start));
1253
1254 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1255 VLV_FIFO(SPRITEF_HI, 0xff));
1256 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1257 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1258
1259 I915_WRITE(DSPARB3, dsparb3);
1260 I915_WRITE(DSPARB2, dsparb2);
1261 break;
1262 default:
1263 break;
1264 }
1265}
1266
1267#undef VLV_FIFO
1268
262cd2e1
VS		 1269static void vlv_merge_wm(struct drm_device *dev,
1270 struct vlv_wm_values *wm)
1271{
1272 struct intel_crtc *crtc;
1273 int num_active_crtcs = 0;
1274
58590c14 1275 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1276 wm->cxsr = true;
1277
1278 for_each_intel_crtc(dev, crtc) {
1279 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1280
1281 if (!crtc->active)
1282 continue;
1283
1284 if (!wm_state->cxsr)
1285 wm->cxsr = false;
1286
1287 num_active_crtcs++;
1288 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1289 }
1290
1291 if (num_active_crtcs != 1)
1292 wm->cxsr = false;
1293
6f9c784b
VS		 1294 if (num_active_crtcs > 1)
1295 wm->level = VLV_WM_LEVEL_PM2;
1296
262cd2e1
VS		 1297 for_each_intel_crtc(dev, crtc) {
1298 struct vlv_wm_state *wm_state = &crtc->wm_state;
1299 enum pipe pipe = crtc->pipe;
1300
1301 if (!crtc->active)
1302 continue;
1303
1304 wm->pipe[pipe] = wm_state->wm[wm->level];
1305 if (wm->cxsr)
1306 wm->sr = wm_state->sr[wm->level];
1307
1308 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1309 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1310 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1311 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1312 }
1313}
1314
1315static void vlv_update_wm(struct drm_crtc *crtc)
1316{
1317 struct drm_device *dev = crtc->dev;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1320 enum pipe pipe = intel_crtc->pipe;
1321 struct vlv_wm_values wm = {};
1322
26e1fe4f 1323 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1324 vlv_merge_wm(dev, &wm);
1325
54f1b6e1
VS		 1326 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1327 /* FIXME should be part of crtc atomic commit */
1328 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1329 return;
54f1b6e1 1330 }
262cd2e1
VS		 1331
1332 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1333 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1334 chv_set_memory_dvfs(dev_priv, false);
1335
1336 if (wm.level < VLV_WM_LEVEL_PM5 &&
1337 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1338 chv_set_memory_pm5(dev_priv, false);
1339
852eb00d 1340 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1341 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1342
54f1b6e1
VS		 1343 /* FIXME should be part of crtc atomic commit */
1344 vlv_pipe_set_fifo_size(intel_crtc);
1345
262cd2e1
VS		 1346 vlv_write_wm_values(intel_crtc, &wm);
1347
1348 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1349 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1350 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1351 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1352 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1353
852eb00d 1354 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1355 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1356
1357 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1358 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1359 chv_set_memory_pm5(dev_priv, true);
1360
1361 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1362 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1363 chv_set_memory_dvfs(dev_priv, true);
1364
1365 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1366}
1367
ae80152d
VS		 1368#define single_plane_enabled(mask) is_power_of_2(mask)
1369
46ba614c 1370static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1371{
46ba614c 1372 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1373 static const int sr_latency_ns = 12000;
1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1376 int plane_sr, cursor_sr;
1377 unsigned int enabled = 0;
9858425c 1378 bool cxsr_enabled;
b445e3b0 1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1381 &g4x_wm_info, pessimal_latency_ns,
1382 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1383 &planea_wm, &cursora_wm))
51cea1f4 1384 enabled |= 1 << PIPE_A;
b445e3b0 1385
51cea1f4 1386 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1387 &g4x_wm_info, pessimal_latency_ns,
1388 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1389 &planeb_wm, &cursorb_wm))
51cea1f4 1390 enabled |= 1 << PIPE_B;
b445e3b0 1391
b445e3b0
ED		 1392 if (single_plane_enabled(enabled) &&
1393 g4x_compute_srwm(dev, ffs(enabled) - 1,
1394 sr_latency_ns,
1395 &g4x_wm_info,
1396 &g4x_cursor_wm_info,
52bd02d8 1397 &plane_sr, &cursor_sr)) {
9858425c 1398 cxsr_enabled = true;
52bd02d8 1399 } else {
9858425c 1400 cxsr_enabled = false;
5209b1f4 1401 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1402 plane_sr = cursor_sr = 0;
1403 }
b445e3b0 1404
a5043453
VS		 1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1406 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1407 planea_wm, cursora_wm,
1408 planeb_wm, cursorb_wm,
1409 plane_sr, cursor_sr);
1410
1411 I915_WRITE(DSPFW1,
f4998963
VS		 1412 FW_WM(plane_sr, SR) |
1413 FW_WM(cursorb_wm, CURSORB) |
1414 FW_WM(planeb_wm, PLANEB) |
1415 FW_WM(planea_wm, PLANEA));
b445e3b0 1416 I915_WRITE(DSPFW2,
8c919b28 1417 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1418 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1419 /* HPLL off in SR has some issues on G4x... disable it */
1420 I915_WRITE(DSPFW3,
8c919b28 1421 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1422 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1423
1424 if (cxsr_enabled)
1425 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1426}
1427
46ba614c 1428static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1429{
46ba614c 1430 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 struct drm_crtc *crtc;
1433 int srwm = 1;
1434 int cursor_sr = 16;
9858425c 1435 bool cxsr_enabled;
b445e3b0
ED		 1436
1437 /* Calc sr entries for one plane configs */
1438 crtc = single_enabled_crtc(dev);
1439 if (crtc) {
1440 /* self-refresh has much higher latency */
1441 static const int sr_latency_ns = 12000;
124abe07 1442 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1443 int clock = adjusted_mode->crtc_clock;
fec8cba3 1444 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1445 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1446 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1447 unsigned long line_time_us;
1448 int entries;
1449
922044c9 1450 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1451
1452 /* Use ns/us then divide to preserve precision */
1453 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1454 cpp * hdisplay;
b445e3b0
ED		 1455 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1456 srwm = I965_FIFO_SIZE - entries;
1457 if (srwm < 0)
1458 srwm = 1;
1459 srwm &= 0x1ff;
1460 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1461 entries, srwm);
1462
1463 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1464 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1465 entries = DIV_ROUND_UP(entries,
1466 i965_cursor_wm_info.cacheline_size);
1467 cursor_sr = i965_cursor_wm_info.fifo_size -
1468 (entries + i965_cursor_wm_info.guard_size);
1469
1470 if (cursor_sr > i965_cursor_wm_info.max_wm)
1471 cursor_sr = i965_cursor_wm_info.max_wm;
1472
1473 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1474 "cursor %d\n", srwm, cursor_sr);
1475
9858425c 1476 cxsr_enabled = true;
b445e3b0 1477 } else {
9858425c 1478 cxsr_enabled = false;
b445e3b0 1479 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1480 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1481 }
1482
1483 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1484 srwm);
1485
1486 /* 965 has limitations... */
f4998963
VS		 1487 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1488 FW_WM(8, CURSORB) |
1489 FW_WM(8, PLANEB) |
1490 FW_WM(8, PLANEA));
1491 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1492 FW_WM(8, PLANEC_OLD));
b445e3b0 1493 /* update cursor SR watermark */
f4998963 1494 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1495
1496 if (cxsr_enabled)
1497 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1498}
1499
f4998963
VS		 1500#undef FW_WM
1501
46ba614c 1502static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1503{
46ba614c 1504 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506 const struct intel_watermark_params *wm_info;
1507 uint32_t fwater_lo;
1508 uint32_t fwater_hi;
1509 int cwm, srwm = 1;
1510 int fifo_size;
1511 int planea_wm, planeb_wm;
1512 struct drm_crtc *crtc, *enabled = NULL;
1513
1514 if (IS_I945GM(dev))
1515 wm_info = &i945_wm_info;
1516 else if (!IS_GEN2(dev))
1517 wm_info = &i915_wm_info;
1518 else
9d539105 1519 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1520
1521 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1522 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1523 if (intel_crtc_active(crtc)) {
241bfc38 1524 const struct drm_display_mode *adjusted_mode;
ac484963 1525 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1526 if (IS_GEN2(dev))
1527 cpp = 4;
1528
6e3c9717 1529 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1530 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1531 wm_info, fifo_size, cpp,
5aef6003 1532 pessimal_latency_ns);
b445e3b0 1533 enabled = crtc;
9d539105 1534 } else {
b445e3b0 1535 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1536 if (planea_wm > (long)wm_info->max_wm)
1537 planea_wm = wm_info->max_wm;
1538 }
1539
1540 if (IS_GEN2(dev))
1541 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1542
1543 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1544 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1545 if (intel_crtc_active(crtc)) {
241bfc38 1546 const struct drm_display_mode *adjusted_mode;
ac484963 1547 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1548 if (IS_GEN2(dev))
1549 cpp = 4;
1550
6e3c9717 1551 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1552 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1553 wm_info, fifo_size, cpp,
5aef6003 1554 pessimal_latency_ns);
b445e3b0
ED		 1555 if (enabled == NULL)
1556 enabled = crtc;
1557 else
1558 enabled = NULL;
9d539105 1559 } else {
b445e3b0 1560 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1561 if (planeb_wm > (long)wm_info->max_wm)
1562 planeb_wm = wm_info->max_wm;
1563 }
b445e3b0
ED		 1564
1565 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1566
2ab1bc9d 1567 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1568 struct drm_i915_gem_object *obj;
2ab1bc9d 1569
59bea882 1570 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1571
1572 /* self-refresh seems busted with untiled */
2ff8fde1 1573 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1574 enabled = NULL;
1575 }
1576
b445e3b0
ED		 1577 /*
1578 * Overlay gets an aggressive default since video jitter is bad.
1579 */
1580 cwm = 2;
1581
1582 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1583 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1584
1585 /* Calc sr entries for one plane configs */
1586 if (HAS_FW_BLC(dev) && enabled) {
1587 /* self-refresh has much higher latency */
1588 static const int sr_latency_ns = 6000;
124abe07 1589 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1590 int clock = adjusted_mode->crtc_clock;
fec8cba3 1591 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1592 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1593 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1594 unsigned long line_time_us;
1595 int entries;
1596
922044c9 1597 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1598
1599 /* Use ns/us then divide to preserve precision */
1600 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1601 cpp * hdisplay;
b445e3b0
ED		 1602 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1603 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1604 srwm = wm_info->fifo_size - entries;
1605 if (srwm < 0)
1606 srwm = 1;
1607
1608 if (IS_I945G(dev) || IS_I945GM(dev))
1609 I915_WRITE(FW_BLC_SELF,
1610 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1611 else if (IS_I915GM(dev))
1612 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1613 }
1614
1615 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1616 planea_wm, planeb_wm, cwm, srwm);
1617
1618 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1619 fwater_hi = (cwm & 0x1f);
1620
1621 /* Set request length to 8 cachelines per fetch */
1622 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1623 fwater_hi = fwater_hi | (1 << 8);
1624
1625 I915_WRITE(FW_BLC, fwater_lo);
1626 I915_WRITE(FW_BLC2, fwater_hi);
1627
5209b1f4
ID		 1628 if (enabled)
1629 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1630}
1631
feb56b93 1632static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1633{
46ba614c 1634 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636 struct drm_crtc *crtc;
241bfc38 1637 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1638 uint32_t fwater_lo;
1639 int planea_wm;
1640
1641 crtc = single_enabled_crtc(dev);
1642 if (crtc == NULL)
1643 return;
1644
6e3c9717 1645 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1646 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1647 &i845_wm_info,
b445e3b0 1648 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1649 4, pessimal_latency_ns);
b445e3b0
ED		 1650 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1651 fwater_lo |= (3<<8) | planea_wm;
1652
1653 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1654
1655 I915_WRITE(FW_BLC, fwater_lo);
1656}
1657
8cfb3407 1658uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1659{
fd4daa9c 1660 uint32_t pixel_rate;
801bcfff 1661
8cfb3407 1662 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1663
1664 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1665 * adjust the pixel_rate here. */
1666
8cfb3407 1667 if (pipe_config->pch_pfit.enabled) {
801bcfff 1668 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1669 uint32_t pfit_size = pipe_config->pch_pfit.size;
1670
1671 pipe_w = pipe_config->pipe_src_w;
1672 pipe_h = pipe_config->pipe_src_h;
801bcfff 1673
801bcfff
PZ		 1674 pfit_w = (pfit_size >> 16) & 0xFFFF;
1675 pfit_h = pfit_size & 0xFFFF;
1676 if (pipe_w < pfit_w)
1677 pipe_w = pfit_w;
1678 if (pipe_h < pfit_h)
1679 pipe_h = pfit_h;
1680
15126882
MR		 1681 if (WARN_ON(!pfit_w || !pfit_h))
1682 return pixel_rate;
1683
801bcfff
PZ		 1684 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1685 pfit_w * pfit_h);
1686 }
1687
1688 return pixel_rate;
1689}
1690
37126462 1691/* latency must be in 0.1us units. */
ac484963 1692static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1693{
1694 uint64_t ret;
1695
3312ba65
VS		 1696 if (WARN(latency == 0, "Latency value missing\n"))
1697 return UINT_MAX;
1698
ac484963 1699 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1700 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1701
1702 return ret;
1703}
1704
37126462 1705/* latency must be in 0.1us units. */
23297044 1706static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1707 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1708 uint32_t latency)
1709{
1710 uint32_t ret;
1711
3312ba65
VS		 1712 if (WARN(latency == 0, "Latency value missing\n"))
1713 return UINT_MAX;
15126882
MR		 1714 if (WARN_ON(!pipe_htotal))
1715 return UINT_MAX;
3312ba65 1716
801bcfff 1717 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1718 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1719 ret = DIV_ROUND_UP(ret, 64) + 2;
1720 return ret;
1721}
1722
23297044 1723static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1724 uint8_t cpp)
cca32e9a 1725{
15126882
MR		 1726 /*
1727 * Neither of these should be possible since this function shouldn't be
1728 * called if the CRTC is off or the plane is invisible. But let's be
1729 * extra paranoid to avoid a potential divide-by-zero if we screw up
1730 * elsewhere in the driver.
1731 */
ac484963 1732 if (WARN_ON(!cpp))
15126882
MR		 1733 return 0;
1734 if (WARN_ON(!horiz_pixels))
1735 return 0;
1736
ac484963 1737 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1738}
1739
820c1980 1740struct ilk_wm_maximums {
cca32e9a
PZ		 1741 uint16_t pri;
1742 uint16_t spr;
1743 uint16_t cur;
1744 uint16_t fbc;
1745};
1746
37126462
VS		 1747/*
1748 * For both WM_PIPE and WM_LP.
1749 * mem_value must be in 0.1us units.
1750 */
7221fc33 1751static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1752 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1753 uint32_t mem_value,
1754 bool is_lp)
801bcfff 1755{
ac484963
VS		 1756 int cpp = pstate->base.fb ?
1757 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1758 uint32_t method1, method2;
1759
7221fc33 1760 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1761 return 0;
1762
ac484963 1763 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1764
1765 if (!is_lp)
1766 return method1;
1767
7221fc33
MR		 1768 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1769 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1770 drm_rect_width(&pstate->dst),
ac484963 1771 cpp, mem_value);
cca32e9a
PZ		 1772
1773 return min(method1, method2);
801bcfff
PZ		 1774}
1775
37126462
VS		 1776/*
1777 * For both WM_PIPE and WM_LP.
1778 * mem_value must be in 0.1us units.
1779 */
7221fc33 1780static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1781 const struct intel_plane_state *pstate,
801bcfff
PZ		 1782 uint32_t mem_value)
1783{
ac484963
VS		 1784 int cpp = pstate->base.fb ?
1785 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1786 uint32_t method1, method2;
1787
7221fc33 1788 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1789 return 0;
1790
ac484963 1791 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1792 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1793 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1794 drm_rect_width(&pstate->dst),
ac484963 1795 cpp, mem_value);
801bcfff
PZ		 1796 return min(method1, method2);
1797}
1798
37126462
VS		 1799/*
1800 * For both WM_PIPE and WM_LP.
1801 * mem_value must be in 0.1us units.
1802 */
7221fc33 1803static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1804 const struct intel_plane_state *pstate,
801bcfff
PZ		 1805 uint32_t mem_value)
1806{
b2435692
MR		 1807 /*
1808 * We treat the cursor plane as always-on for the purposes of watermark
1809 * calculation. Until we have two-stage watermark programming merged,
1810 * this is necessary to avoid flickering.
1811 */
1812 int cpp = 4;
1813 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1814
b2435692 1815 if (!cstate->base.active)
801bcfff
PZ		 1816 return 0;
1817
7221fc33
MR		 1818 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1819 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1820 width, cpp, mem_value);
801bcfff
PZ		 1821}
1822
cca32e9a 1823/* Only for WM_LP. */
7221fc33 1824static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1825 const struct intel_plane_state *pstate,
1fda9882 1826 uint32_t pri_val)
cca32e9a 1827{
ac484963
VS		 1828 int cpp = pstate->base.fb ?
1829 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1830
7221fc33 1831 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1832 return 0;
1833
ac484963 1834 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1835}
1836
158ae64f
VS		 1837static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1838{
416f4727
VS		 1839 if (INTEL_INFO(dev)->gen >= 8)
1840 return 3072;
1841 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1842 return 768;
1843 else
1844 return 512;
1845}
1846
4e975081
VS		 1847static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1848 int level, bool is_sprite)
1849{
1850 if (INTEL_INFO(dev)->gen >= 8)
1851 /* BDW primary/sprite plane watermarks */
1852 return level == 0 ? 255 : 2047;
1853 else if (INTEL_INFO(dev)->gen >= 7)
1854 /* IVB/HSW primary/sprite plane watermarks */
1855 return level == 0 ? 127 : 1023;
1856 else if (!is_sprite)
1857 /* ILK/SNB primary plane watermarks */
1858 return level == 0 ? 127 : 511;
1859 else
1860 /* ILK/SNB sprite plane watermarks */
1861 return level == 0 ? 63 : 255;
1862}
1863
1864static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1865 int level)
1866{
1867 if (INTEL_INFO(dev)->gen >= 7)
1868 return level == 0 ? 63 : 255;
1869 else
1870 return level == 0 ? 31 : 63;
1871}
1872
1873static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1874{
1875 if (INTEL_INFO(dev)->gen >= 8)
1876 return 31;
1877 else
1878 return 15;
1879}
1880
158ae64f
VS		 1881/* Calculate the maximum primary/sprite plane watermark */
1882static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1883 int level,
240264f4 1884 const struct intel_wm_config *config,
158ae64f
VS		 1885 enum intel_ddb_partitioning ddb_partitioning,
1886 bool is_sprite)
1887{
1888 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1889
1890 /* if sprites aren't enabled, sprites get nothing */
240264f4 1891 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1892 return 0;
1893
1894 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1895 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1896 fifo_size /= INTEL_INFO(dev)->num_pipes;
1897
1898 /*
1899 * For some reason the non self refresh
1900 * FIFO size is only half of the self
1901 * refresh FIFO size on ILK/SNB.
1902 */
1903 if (INTEL_INFO(dev)->gen <= 6)
1904 fifo_size /= 2;
1905 }
1906
240264f4 1907 if (config->sprites_enabled) {
158ae64f
VS		 1908 /* level 0 is always calculated with 1:1 split */
1909 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1910 if (is_sprite)
1911 fifo_size *= 5;
1912 fifo_size /= 6;
1913 } else {
1914 fifo_size /= 2;
1915 }
1916 }
1917
1918 /* clamp to max that the registers can hold */
4e975081 1919 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1920}
1921
1922/* Calculate the maximum cursor plane watermark */
1923static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1924 int level,
1925 const struct intel_wm_config *config)
158ae64f
VS		 1926{
1927 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1928 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1929 return 64;
1930
1931 /* otherwise just report max that registers can hold */
4e975081 1932 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1933}
1934
d34ff9c6 1935static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1936 int level,
1937 const struct intel_wm_config *config,
1938 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1939 struct ilk_wm_maximums *max)
158ae64f 1940{
240264f4
VS		 1941 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1942 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1943 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1944 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1945}
1946
a3cb4048
VS		 1947static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1948 int level,
1949 struct ilk_wm_maximums *max)
1950{
1951 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1952 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1953 max->cur = ilk_cursor_wm_reg_max(dev, level);
1954 max->fbc = ilk_fbc_wm_reg_max(dev);
1955}
1956
d9395655 1957static bool ilk_validate_wm_level(int level,
820c1980 1958 const struct ilk_wm_maximums *max,
d9395655 1959 struct intel_wm_level *result)
a9786a11
VS		 1960{
1961 bool ret;
1962
1963 /* already determined to be invalid? */
1964 if (!result->enable)
1965 return false;
1966
1967 result->enable = result->pri_val <= max->pri &&
1968 result->spr_val <= max->spr &&
1969 result->cur_val <= max->cur;
1970
1971 ret = result->enable;
1972
1973 /*
1974 * HACK until we can pre-compute everything,
1975 * and thus fail gracefully if LP0 watermarks
1976 * are exceeded...
1977 */
1978 if (level == 0 && !result->enable) {
1979 if (result->pri_val > max->pri)
1980 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1981 level, result->pri_val, max->pri);
1982 if (result->spr_val > max->spr)
1983 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1984 level, result->spr_val, max->spr);
1985 if (result->cur_val > max->cur)
1986 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1987 level, result->cur_val, max->cur);
1988
1989 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1990 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1991 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1992 result->enable = true;
1993 }
1994
a9786a11
VS		 1995 return ret;
1996}
1997
d34ff9c6 1998static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1999 const struct intel_crtc *intel_crtc,
6f5ddd17 2000 int level,
7221fc33 2001 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2002 struct intel_plane_state *pristate,
2003 struct intel_plane_state *sprstate,
2004 struct intel_plane_state *curstate,
1fd527cc 2005 struct intel_wm_level *result)
6f5ddd17
VS		 2006{
2007 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2008 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2009 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2010
2011 /* WM1+ latency values stored in 0.5us units */
2012 if (level > 0) {
2013 pri_latency *= 5;
2014 spr_latency *= 5;
2015 cur_latency *= 5;
2016 }
2017
e3bddded
ML		 2018 if (pristate) {
2019 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2020 pri_latency, level);
2021 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2022 }
2023
2024 if (sprstate)
2025 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2026
2027 if (curstate)
2028 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2029
6f5ddd17
VS		 2030 result->enable = true;
2031}
2032
801bcfff 2033static uint32_t
532f7a7f 2034hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2035{
532f7a7f
VS		 2036 const struct intel_atomic_state *intel_state =
2037 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2038 const struct drm_display_mode *adjusted_mode =
2039 &cstate->base.adjusted_mode;
85a02deb 2040 u32 linetime, ips_linetime;
1f8eeabf 2041
ee91a159
MR		 2042 if (!cstate->base.active)
2043 return 0;
2044 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2045 return 0;
532f7a7f 2046 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2047 return 0;
1011d8c4 2048
1f8eeabf
ED		 2049 /* The WM are computed with base on how long it takes to fill a single
2050 * row at the given clock rate, multiplied by 8.
2051 * */
124abe07
VS		 2052 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2053 adjusted_mode->crtc_clock);
2054 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2055 intel_state->cdclk);
1f8eeabf 2056
801bcfff
PZ		 2057 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2058 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2059}
2060
2af30a5c 2061static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2062{
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064
2af30a5c
PB		 2065 if (IS_GEN9(dev)) {
2066 uint32_t val;
4f947386 2067 int ret, i;
367294be 2068 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2069
2070 /* read the first set of memory latencies[0:3] */
2071 val = 0; /* data0 to be programmed to 0 for first set */
2072 mutex_lock(&dev_priv->rps.hw_lock);
2073 ret = sandybridge_pcode_read(dev_priv,
2074 GEN9_PCODE_READ_MEM_LATENCY,
2075 &val);
2076 mutex_unlock(&dev_priv->rps.hw_lock);
2077
2078 if (ret) {
2079 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2080 return;
2081 }
2082
2083 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2084 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2085 GEN9_MEM_LATENCY_LEVEL_MASK;
2086 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2087 GEN9_MEM_LATENCY_LEVEL_MASK;
2088 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2089 GEN9_MEM_LATENCY_LEVEL_MASK;
2090
2091 /* read the second set of memory latencies[4:7] */
2092 val = 1; /* data0 to be programmed to 1 for second set */
2093 mutex_lock(&dev_priv->rps.hw_lock);
2094 ret = sandybridge_pcode_read(dev_priv,
2095 GEN9_PCODE_READ_MEM_LATENCY,
2096 &val);
2097 mutex_unlock(&dev_priv->rps.hw_lock);
2098 if (ret) {
2099 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2100 return;
2101 }
2102
2103 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2109 GEN9_MEM_LATENCY_LEVEL_MASK;
2110
367294be 2111 /*
6f97235b
DL		 2112 * WaWmMemoryReadLatency:skl
2113 *
367294be
VK		 2114 * punit doesn't take into account the read latency so we need
2115 * to add 2us to the various latency levels we retrieve from
2116 * the punit.
2117 * - W0 is a bit special in that it's the only level that
2118 * can't be disabled if we want to have display working, so
2119 * we always add 2us there.
2120 * - For levels >=1, punit returns 0us latency when they are
2121 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2122 *
2123 * Additionally, if a level n (n > 1) has a 0us latency, all
2124 * levels m (m >= n) need to be disabled. We make sure to
2125 * sanitize the values out of the punit to satisfy this
2126 * requirement.
367294be
VK		 2127 */
2128 wm[0] += 2;
2129 for (level = 1; level <= max_level; level++)
2130 if (wm[level] != 0)
2131 wm[level] += 2;
4f947386
VK		 2132 else {
2133 for (i = level + 1; i <= max_level; i++)
2134 wm[i] = 0;
367294be 2135
4f947386
VK		 2136 break;
2137 }
2af30a5c 2138 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2139 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2140
2141 wm[0] = (sskpd >> 56) & 0xFF;
2142 if (wm[0] == 0)
2143 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2144 wm[1] = (sskpd >> 4) & 0xFF;
2145 wm[2] = (sskpd >> 12) & 0xFF;
2146 wm[3] = (sskpd >> 20) & 0x1FF;
2147 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2148 } else if (INTEL_INFO(dev)->gen >= 6) {
2149 uint32_t sskpd = I915_READ(MCH_SSKPD);
2150
2151 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2152 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2153 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2154 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2155 } else if (INTEL_INFO(dev)->gen >= 5) {
2156 uint32_t mltr = I915_READ(MLTR_ILK);
2157
2158 /* ILK primary LP0 latency is 700 ns */
2159 wm[0] = 7;
2160 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2161 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2162 }
2163}
2164
53615a5e
VS		 2165static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2166{
2167 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2168 if (IS_GEN5(dev))
53615a5e
VS		 2169 wm[0] = 13;
2170}
2171
2172static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2173{
2174 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2175 if (IS_GEN5(dev))
53615a5e
VS		 2176 wm[0] = 13;
2177
2178 /* WaDoubleCursorLP3Latency:ivb */
2179 if (IS_IVYBRIDGE(dev))
2180 wm[3] *= 2;
2181}
2182
546c81fd 2183int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2184{
26ec971e 2185 /* how many WM levels are we expecting */
b6e742f6 2186 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2187 return 7;
2188 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2189 return 4;
26ec971e 2190 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2191 return 3;
26ec971e 2192 else
ad0d6dc4
VS		 2193 return 2;
2194}
7526ed79 2195
ad0d6dc4
VS		 2196static void intel_print_wm_latency(struct drm_device *dev,
2197 const char *name,
2af30a5c 2198 const uint16_t wm[8])
ad0d6dc4
VS		 2199{
2200 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2201
2202 for (level = 0; level <= max_level; level++) {
2203 unsigned int latency = wm[level];
2204
2205 if (latency == 0) {
2206 DRM_ERROR("%s WM%d latency not provided\n",
2207 name, level);
2208 continue;
2209 }
2210
2af30a5c
PB		 2211 /*
2212 * - latencies are in us on gen9.
2213 * - before then, WM1+ latency values are in 0.5us units
2214 */
2215 if (IS_GEN9(dev))
2216 latency *= 10;
2217 else if (level > 0)
26ec971e
VS		 2218 latency *= 5;
2219
2220 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2221 name, level, wm[level],
2222 latency / 10, latency % 10);
2223 }
2224}
2225
e95a2f75
VS		 2226static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2227 uint16_t wm[5], uint16_t min)
2228{
2229 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2230
2231 if (wm[0] >= min)
2232 return false;
2233
2234 wm[0] = max(wm[0], min);
2235 for (level = 1; level <= max_level; level++)
2236 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2237
2238 return true;
2239}
2240
2241static void snb_wm_latency_quirk(struct drm_device *dev)
2242{
2243 struct drm_i915_private *dev_priv = dev->dev_private;
2244 bool changed;
2245
2246 /*
2247 * The BIOS provided WM memory latency values are often
2248 * inadequate for high resolution displays. Adjust them.
2249 */
2250 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2251 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2252 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2253
2254 if (!changed)
2255 return;
2256
2257 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2258 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2261}
2262
fa50ad61 2263static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2264{
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266
2267 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2268
2269 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2270 sizeof(dev_priv->wm.pri_latency));
2271 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2272 sizeof(dev_priv->wm.pri_latency));
2273
2274 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2275 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2276
2277 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2278 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2279 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2280
2281 if (IS_GEN6(dev))
2282 snb_wm_latency_quirk(dev);
53615a5e
VS		 2283}
2284
2af30a5c
PB		 2285static void skl_setup_wm_latency(struct drm_device *dev)
2286{
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288
2289 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2290 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2291}
2292
ed4a6a7c
MR		 2293static bool ilk_validate_pipe_wm(struct drm_device *dev,
2294 struct intel_pipe_wm *pipe_wm)
2295{
2296 /* LP0 watermark maximums depend on this pipe alone */
2297 const struct intel_wm_config config = {
2298 .num_pipes_active = 1,
2299 .sprites_enabled = pipe_wm->sprites_enabled,
2300 .sprites_scaled = pipe_wm->sprites_scaled,
2301 };
2302 struct ilk_wm_maximums max;
2303
2304 /* LP0 watermarks always use 1/2 DDB partitioning */
2305 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2306
2307 /* At least LP0 must be valid */
2308 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2309 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2310 return false;
2311 }
2312
2313 return true;
2314}
2315
0b2ae6d7 2316/* Compute new watermarks for the pipe */
e3bddded 2317static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2318{
e3bddded
ML		 2319 struct drm_atomic_state *state = cstate->base.state;
2320 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2321 struct intel_pipe_wm *pipe_wm;
e3bddded 2322 struct drm_device *dev = state->dev;
d34ff9c6 2323 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2324 struct intel_plane *intel_plane;
86c8bbbe 2325 struct intel_plane_state *pristate = NULL;
43d59eda 2326 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2327 struct intel_plane_state *curstate = NULL;
d81f04c5 2328 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2329 struct ilk_wm_maximums max;
0b2ae6d7 2330
e8f1f02e 2331 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2332
43d59eda 2333 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2334 struct intel_plane_state *ps;
2335
2336 ps = intel_atomic_get_existing_plane_state(state,
2337 intel_plane);
2338 if (!ps)
2339 continue;
86c8bbbe
MR		 2340
2341 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2342 pristate = ps;
86c8bbbe 2343 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2344 sprstate = ps;
86c8bbbe 2345 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2346 curstate = ps;
43d59eda
MR		 2347 }
2348
ed4a6a7c 2349 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2350 if (sprstate) {
2351 pipe_wm->sprites_enabled = sprstate->visible;
2352 pipe_wm->sprites_scaled = sprstate->visible &&
2353 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2354 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2355 }
2356
d81f04c5
ML		 2357 usable_level = max_level;
2358
7b39a0b7 2359 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2360 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2361 usable_level = 1;
7b39a0b7
VS		 2362
2363 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2364 if (pipe_wm->sprites_scaled)
d81f04c5 2365 usable_level = 0;
7b39a0b7 2366
86c8bbbe 2367 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2368 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2369
2370 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2371 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2372
a42a5719 2373 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2374 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2375
ed4a6a7c 2376 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2377 return -EINVAL;
a3cb4048
VS		 2378
2379 ilk_compute_wm_reg_maximums(dev, 1, &max);
2380
2381 for (level = 1; level <= max_level; level++) {
71f0a626 2382 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2383
86c8bbbe 2384 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2385 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2386
2387 /*
2388 * Disable any watermark level that exceeds the
2389 * register maximums since such watermarks are
2390 * always invalid.
2391 */
71f0a626
ML		 2392 if (level > usable_level)
2393 continue;
2394
2395 if (ilk_validate_wm_level(level, &max, wm))
2396 pipe_wm->wm[level] = *wm;
2397 else
d81f04c5 2398 usable_level = level;
a3cb4048
VS		 2399 }
2400
86c8bbbe 2401 return 0;
0b2ae6d7
VS		 2402}
2403
ed4a6a7c
MR		 2404/*
2405 * Build a set of 'intermediate' watermark values that satisfy both the old
2406 * state and the new state. These can be programmed to the hardware
2407 * immediately.
2408 */
2409static int ilk_compute_intermediate_wm(struct drm_device *dev,
2410 struct intel_crtc *intel_crtc,
2411 struct intel_crtc_state *newstate)
2412{
e8f1f02e 2413 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2414 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2415 int level, max_level = ilk_wm_max_level(dev);
2416
2417 /*
2418 * Start with the final, target watermarks, then combine with the
2419 * currently active watermarks to get values that are safe both before
2420 * and after the vblank.
2421 */
e8f1f02e 2422 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2423 a->pipe_enabled |= b->pipe_enabled;
2424 a->sprites_enabled |= b->sprites_enabled;
2425 a->sprites_scaled |= b->sprites_scaled;
2426
2427 for (level = 0; level <= max_level; level++) {
2428 struct intel_wm_level *a_wm = &a->wm[level];
2429 const struct intel_wm_level *b_wm = &b->wm[level];
2430
2431 a_wm->enable &= b_wm->enable;
2432 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2433 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2434 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2435 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2436 }
2437
2438 /*
2439 * We need to make sure that these merged watermark values are
2440 * actually a valid configuration themselves. If they're not,
2441 * there's no safe way to transition from the old state to
2442 * the new state, so we need to fail the atomic transaction.
2443 */
2444 if (!ilk_validate_pipe_wm(dev, a))
2445 return -EINVAL;
2446
2447 /*
2448 * If our intermediate WM are identical to the final WM, then we can
2449 * omit the post-vblank programming; only update if it's different.
2450 */
e8f1f02e 2451 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2452 newstate->wm.need_postvbl_update = false;
2453
2454 return 0;
2455}
2456
0b2ae6d7
VS		 2457/*
2458 * Merge the watermarks from all active pipes for a specific level.
2459 */
2460static void ilk_merge_wm_level(struct drm_device *dev,
2461 int level,
2462 struct intel_wm_level *ret_wm)
2463{
2464 const struct intel_crtc *intel_crtc;
2465
d52fea5b
VS		 2466 ret_wm->enable = true;
2467
d3fcc808 2468 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2469 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2470 const struct intel_wm_level *wm = &active->wm[level];
2471
2472 if (!active->pipe_enabled)
2473 continue;
0b2ae6d7 2474
d52fea5b
VS		 2475 /*
2476 * The watermark values may have been used in the past,
2477 * so we must maintain them in the registers for some
2478 * time even if the level is now disabled.
2479 */
0b2ae6d7 2480 if (!wm->enable)
d52fea5b 2481 ret_wm->enable = false;
0b2ae6d7
VS		 2482
2483 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2484 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2485 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2486 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2487 }
0b2ae6d7
VS		 2488}
2489
2490/*
2491 * Merge all low power watermarks for all active pipes.
2492 */
2493static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2494 const struct intel_wm_config *config,
820c1980 2495 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2496 struct intel_pipe_wm *merged)
2497{
7733b49b 2498 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2499 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2500 int last_enabled_level = max_level;
0b2ae6d7 2501
0ba22e26
VS		 2502 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2503 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2504 config->num_pipes_active > 1)
1204d5ba 2505 last_enabled_level = 0;
0ba22e26 2506
6c8b6c28
VS		 2507 /* ILK: FBC WM must be disabled always */
2508 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2509
2510 /* merge each WM1+ level */
2511 for (level = 1; level <= max_level; level++) {
2512 struct intel_wm_level *wm = &merged->wm[level];
2513
2514 ilk_merge_wm_level(dev, level, wm);
2515
d52fea5b
VS		 2516 if (level > last_enabled_level)
2517 wm->enable = false;
2518 else if (!ilk_validate_wm_level(level, max, wm))
2519 /* make sure all following levels get disabled */
2520 last_enabled_level = level - 1;
0b2ae6d7
VS		 2521
2522 /*
2523 * The spec says it is preferred to disable
2524 * FBC WMs instead of disabling a WM level.
2525 */
2526 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2527 if (wm->enable)
2528 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2529 wm->fbc_val = 0;
2530 }
2531 }
6c8b6c28
VS		 2532
2533 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2534 /*
2535 * FIXME this is racy. FBC might get enabled later.
2536 * What we should check here is whether FBC can be
2537 * enabled sometime later.
2538 */
7733b49b 2539 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2540 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2541 for (level = 2; level <= max_level; level++) {
2542 struct intel_wm_level *wm = &merged->wm[level];
2543
2544 wm->enable = false;
2545 }
2546 }
0b2ae6d7
VS		 2547}
2548
b380ca3c
VS		 2549static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2550{
2551 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2552 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2553}
2554
a68d68ee
VS		 2555/* The value we need to program into the WM_LPx latency field */
2556static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2557{
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559
a42a5719 2560 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2561 return 2 * level;
2562 else
2563 return dev_priv->wm.pri_latency[level];
2564}
2565
820c1980 2566static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2567 const struct intel_pipe_wm *merged,
609cedef 2568 enum intel_ddb_partitioning partitioning,
820c1980 2569 struct ilk_wm_values *results)
801bcfff 2570{
0b2ae6d7
VS		 2571 struct intel_crtc *intel_crtc;
2572 int level, wm_lp;
cca32e9a 2573
0362c781 2574 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2575 results->partitioning = partitioning;
cca32e9a 2576
0b2ae6d7 2577 /* LP1+ register values */
cca32e9a 2578 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2579 const struct intel_wm_level *r;
801bcfff 2580
b380ca3c 2581 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2582
0362c781 2583 r = &merged->wm[level];
cca32e9a 2584
d52fea5b
VS		 2585 /*
2586 * Maintain the watermark values even if the level is
2587 * disabled. Doing otherwise could cause underruns.
2588 */
2589 results->wm_lp[wm_lp - 1] =
a68d68ee 2590 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2591 (r->pri_val << WM1_LP_SR_SHIFT) |
2592 r->cur_val;
2593
d52fea5b
VS		 2594 if (r->enable)
2595 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2596
416f4727
VS		 2597 if (INTEL_INFO(dev)->gen >= 8)
2598 results->wm_lp[wm_lp - 1] |=
2599 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2600 else
2601 results->wm_lp[wm_lp - 1] |=
2602 r->fbc_val << WM1_LP_FBC_SHIFT;
2603
d52fea5b
VS		 2604 /*
2605 * Always set WM1S_LP_EN when spr_val != 0, even if the
2606 * level is disabled. Doing otherwise could cause underruns.
2607 */
6cef2b8a
VS		 2608 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2609 WARN_ON(wm_lp != 1);
2610 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2611 } else
2612 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2613 }
801bcfff 2614
0b2ae6d7 2615 /* LP0 register values */
d3fcc808 2616 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2617 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2618 const struct intel_wm_level *r =
2619 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2620
2621 if (WARN_ON(!r->enable))
2622 continue;
2623
ed4a6a7c 2624 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2625
0b2ae6d7
VS		 2626 results->wm_pipe[pipe] =
2627 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2628 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2629 r->cur_val;
801bcfff
PZ		 2630 }
2631}
2632
861f3389
PZ		 2633/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2634 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2635static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2636 struct intel_pipe_wm *r1,
2637 struct intel_pipe_wm *r2)
861f3389 2638{
198a1e9b
VS		 2639 int level, max_level = ilk_wm_max_level(dev);
2640 int level1 = 0, level2 = 0;
861f3389 2641
198a1e9b
VS		 2642 for (level = 1; level <= max_level; level++) {
2643 if (r1->wm[level].enable)
2644 level1 = level;
2645 if (r2->wm[level].enable)
2646 level2 = level;
861f3389
PZ		 2647 }
2648
198a1e9b
VS		 2649 if (level1 == level2) {
2650 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2651 return r2;
2652 else
2653 return r1;
198a1e9b 2654 } else if (level1 > level2) {
861f3389
PZ		 2655 return r1;
2656 } else {
2657 return r2;
2658 }
2659}
2660
49a687c4
VS		 2661/* dirty bits used to track which watermarks need changes */
2662#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2663#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2664#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2665#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2666#define WM_DIRTY_FBC (1 << 24)
2667#define WM_DIRTY_DDB (1 << 25)
2668
055e393f 2669static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2670 const struct ilk_wm_values *old,
2671 const struct ilk_wm_values *new)
49a687c4
VS		 2672{
2673 unsigned int dirty = 0;
2674 enum pipe pipe;
2675 int wm_lp;
2676
055e393f 2677 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2678 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2679 dirty |= WM_DIRTY_LINETIME(pipe);
2680 /* Must disable LP1+ watermarks too */
2681 dirty |= WM_DIRTY_LP_ALL;
2682 }
2683
2684 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2685 dirty |= WM_DIRTY_PIPE(pipe);
2686 /* Must disable LP1+ watermarks too */
2687 dirty |= WM_DIRTY_LP_ALL;
2688 }
2689 }
2690
2691 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2692 dirty |= WM_DIRTY_FBC;
2693 /* Must disable LP1+ watermarks too */
2694 dirty |= WM_DIRTY_LP_ALL;
2695 }
2696
2697 if (old->partitioning != new->partitioning) {
2698 dirty |= WM_DIRTY_DDB;
2699 /* Must disable LP1+ watermarks too */
2700 dirty |= WM_DIRTY_LP_ALL;
2701 }
2702
2703 /* LP1+ watermarks already deemed dirty, no need to continue */
2704 if (dirty & WM_DIRTY_LP_ALL)
2705 return dirty;
2706
2707 /* Find the lowest numbered LP1+ watermark in need of an update... */
2708 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2709 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2710 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2711 break;
2712 }
2713
2714 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2715 for (; wm_lp <= 3; wm_lp++)
2716 dirty |= WM_DIRTY_LP(wm_lp);
2717
2718 return dirty;
2719}
2720
8553c18e
VS		 2721static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2722 unsigned int dirty)
801bcfff 2723{
820c1980 2724 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2725 bool changed = false;
801bcfff 2726
facd619b
VS		 2727 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2728 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2729 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2730 changed = true;
facd619b
VS		 2731 }
2732 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2733 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2734 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2735 changed = true;
facd619b
VS		 2736 }
2737 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2738 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2739 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2740 changed = true;
facd619b 2741 }
801bcfff 2742
facd619b
VS		 2743 /*
2744 * Don't touch WM1S_LP_EN here.
2745 * Doing so could cause underruns.
2746 */
6cef2b8a 2747
8553c18e
VS		 2748 return changed;
2749}
2750
2751/*
2752 * The spec says we shouldn't write when we don't need, because every write
2753 * causes WMs to be re-evaluated, expending some power.
2754 */
820c1980
ID		 2755static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2756 struct ilk_wm_values *results)
8553c18e
VS		 2757{
2758 struct drm_device *dev = dev_priv->dev;
820c1980 2759 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2760 unsigned int dirty;
2761 uint32_t val;
2762
055e393f 2763 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2764 if (!dirty)
2765 return;
2766
2767 _ilk_disable_lp_wm(dev_priv, dirty);
2768
49a687c4 2769 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2770 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2771 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2772 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2773 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2774 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2775
49a687c4 2776 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2777 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2778 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2779 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2780 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2781 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2782
49a687c4 2783 if (dirty & WM_DIRTY_DDB) {
a42a5719 2784 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2785 val = I915_READ(WM_MISC);
2786 if (results->partitioning == INTEL_DDB_PART_1_2)
2787 val &= ~WM_MISC_DATA_PARTITION_5_6;
2788 else
2789 val |= WM_MISC_DATA_PARTITION_5_6;
2790 I915_WRITE(WM_MISC, val);
2791 } else {
2792 val = I915_READ(DISP_ARB_CTL2);
2793 if (results->partitioning == INTEL_DDB_PART_1_2)
2794 val &= ~DISP_DATA_PARTITION_5_6;
2795 else
2796 val |= DISP_DATA_PARTITION_5_6;
2797 I915_WRITE(DISP_ARB_CTL2, val);
2798 }
1011d8c4
PZ		 2799 }
2800
49a687c4 2801 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2802 val = I915_READ(DISP_ARB_CTL);
2803 if (results->enable_fbc_wm)
2804 val &= ~DISP_FBC_WM_DIS;
2805 else
2806 val |= DISP_FBC_WM_DIS;
2807 I915_WRITE(DISP_ARB_CTL, val);
2808 }
2809
954911eb
ID		 2810 if (dirty & WM_DIRTY_LP(1) &&
2811 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2812 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2813
2814 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2815 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2816 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2817 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2818 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2819 }
801bcfff 2820
facd619b 2821 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2822 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2823 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2824 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2825 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2826 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2827
2828 dev_priv->wm.hw = *results;
801bcfff
PZ		 2829}
2830
ed4a6a7c 2831bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2832{
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834
2835 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2836}
2837
b9cec075
DL		 2838/*
2839 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2840 * different active planes.
2841 */
2842
2843#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2844#define BXT_DDB_SIZE 512
b9cec075 2845
024c9045
MR		 2846/*
2847 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2848 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2849 * other universal planes are in indices 1..n. Note that this may leave unused
2850 * indices between the top "sprite" plane and the cursor.
2851 */
2852static int
2853skl_wm_plane_id(const struct intel_plane *plane)
2854{
2855 switch (plane->base.type) {
2856 case DRM_PLANE_TYPE_PRIMARY:
2857 return 0;
2858 case DRM_PLANE_TYPE_CURSOR:
2859 return PLANE_CURSOR;
2860 case DRM_PLANE_TYPE_OVERLAY:
2861 return plane->plane + 1;
2862 default:
2863 MISSING_CASE(plane->base.type);
2864 return plane->plane;
2865 }
2866}
2867
b9cec075
DL		 2868static void
2869skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2870 const struct intel_crtc_state *cstate,
c107acfe
MR		 2871 struct skl_ddb_entry *alloc, /* out */
2872 int *num_active /* out */)
b9cec075 2873{
c107acfe
MR		 2874 struct drm_atomic_state *state = cstate->base.state;
2875 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2876 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 2877 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2878 unsigned int pipe_size, ddb_size;
2879 int nth_active_pipe;
c107acfe
MR		 2880 int pipe = to_intel_crtc(for_crtc)->pipe;
2881
a6d3460e 2882 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 2883 alloc->start = 0;
2884 alloc->end = 0;
a6d3460e 2885 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 2886 return;
2887 }
2888
a6d3460e
MR		 2889 if (intel_state->active_pipe_changes)
2890 *num_active = hweight32(intel_state->active_crtcs);
2891 else
2892 *num_active = hweight32(dev_priv->active_crtcs);
2893
43d735a6
DL		 2894 if (IS_BROXTON(dev))
2895 ddb_size = BXT_DDB_SIZE;
2896 else
2897 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2898
2899 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2900
c107acfe 2901 /*
a6d3460e
MR		 2902 * If the state doesn't change the active CRTC's, then there's
2903 * no need to recalculate; the existing pipe allocation limits
2904 * should remain unchanged. Note that we're safe from racing
2905 * commits since any racing commit that changes the active CRTC
2906 * list would need to grab _all_ crtc locks, including the one
2907 * we currently hold.
c107acfe 2908 */
a6d3460e
MR		 2909 if (!intel_state->active_pipe_changes) {
2910 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2911 return;
c107acfe 2912 }
a6d3460e
MR		 2913
2914 nth_active_pipe = hweight32(intel_state->active_crtcs &
2915 (drm_crtc_mask(for_crtc) - 1));
2916 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2917 alloc->start = nth_active_pipe * ddb_size / *num_active;
2918 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2919}
2920
c107acfe 2921static unsigned int skl_cursor_allocation(int num_active)
b9cec075 2922{
c107acfe 2923 if (num_active == 1)
b9cec075
DL		 2924 return 32;
2925
2926 return 8;
2927}
2928
a269c583
DL		 2929static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2930{
2931 entry->start = reg & 0x3ff;
2932 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2933 if (entry->end)
2934 entry->end += 1;
a269c583
DL		 2935}
2936
08db6652
DL		 2937void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2938 struct skl_ddb_allocation *ddb /* out */)
a269c583 2939{
a269c583
DL		 2940 enum pipe pipe;
2941 int plane;
2942 u32 val;
2943
b10f1b20
ML		 2944 memset(ddb, 0, sizeof(*ddb));
2945
a269c583 2946 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2947 enum intel_display_power_domain power_domain;
2948
2949 power_domain = POWER_DOMAIN_PIPE(pipe);
2950 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2951 continue;
2952
dd740780 2953 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2954 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2955 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2956 val);
2957 }
2958
2959 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2960 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2961 val);
4d800030
ID		 2962
2963 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2964 }
2965}
2966
9c2f7a9d
KM		 2967/*
2968 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2969 * The bspec defines downscale amount as:
2970 *
2971 * """
2972 * Horizontal down scale amount = maximum[1, Horizontal source size /
2973 * Horizontal destination size]
2974 * Vertical down scale amount = maximum[1, Vertical source size /
2975 * Vertical destination size]
2976 * Total down scale amount = Horizontal down scale amount *
2977 * Vertical down scale amount
2978 * """
2979 *
2980 * Return value is provided in 16.16 fixed point form to retain fractional part.
2981 * Caller should take care of dividing & rounding off the value.
2982 */
2983static uint32_t
2984skl_plane_downscale_amount(const struct intel_plane_state *pstate)
2985{
2986 uint32_t downscale_h, downscale_w;
2987 uint32_t src_w, src_h, dst_w, dst_h;
2988
2989 if (WARN_ON(!pstate->visible))
2990 return DRM_PLANE_HELPER_NO_SCALING;
2991
2992 /* n.b., src is 16.16 fixed point, dst is whole integer */
2993 src_w = drm_rect_width(&pstate->src);
2994 src_h = drm_rect_height(&pstate->src);
2995 dst_w = drm_rect_width(&pstate->dst);
2996 dst_h = drm_rect_height(&pstate->dst);
2997 if (intel_rotation_90_or_270(pstate->base.rotation))
2998 swap(dst_w, dst_h);
2999
3000 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3001 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3002
3003 /* Provide result in 16.16 fixed point */
3004 return (uint64_t)downscale_w * downscale_h >> 16;
3005}
3006
b9cec075 3007static unsigned int
024c9045
MR		 3008skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3009 const struct drm_plane_state *pstate,
3010 int y)
b9cec075 3011{
a280f7dd 3012 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3013 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3014 uint32_t down_scale_amount, data_rate;
a280f7dd 3015 uint32_t width = 0, height = 0;
a1de91e5
MR		 3016 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3017
3018 if (!intel_pstate->visible)
3019 return 0;
3020 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3021 return 0;
3022 if (y && format != DRM_FORMAT_NV12)
3023 return 0;
a280f7dd
KM		 3024
3025 width = drm_rect_width(&intel_pstate->src) >> 16;
3026 height = drm_rect_height(&intel_pstate->src) >> 16;
3027
3028 if (intel_rotation_90_or_270(pstate->rotation))
3029 swap(width, height);
2cd601c6
CK		 3030
3031 /* for planar format */
a1de91e5 3032 if (format == DRM_FORMAT_NV12) {
2cd601c6 3033 if (y) /* y-plane data rate */
8d19d7d9 3034 data_rate = width * height *
a1de91e5 3035 drm_format_plane_cpp(format, 0);
2cd601c6 3036 else /* uv-plane data rate */
8d19d7d9 3037 data_rate = (width / 2) * (height / 2) *
a1de91e5 3038 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3039 } else {
3040 /* for packed formats */
3041 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3042 }
3043
8d19d7d9
KM		 3044 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3045
3046 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3047}
3048
3049/*
3050 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3051 * a 8192x4096@32bpp framebuffer:
3052 * 3 * 4096 * 8192 * 4 < 2^32
3053 */
3054static unsigned int
9c74d826 3055skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3056{
9c74d826
MR		 3057 struct drm_crtc_state *cstate = &intel_cstate->base;
3058 struct drm_atomic_state *state = cstate->state;
3059 struct drm_crtc *crtc = cstate->crtc;
3060 struct drm_device *dev = crtc->dev;
3061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3062 const struct drm_plane *plane;
024c9045 3063 const struct intel_plane *intel_plane;
a6d3460e 3064 struct drm_plane_state *pstate;
a1de91e5 3065 unsigned int rate, total_data_rate = 0;
9c74d826 3066 int id;
a6d3460e
MR		 3067 int i;
3068
3069 if (WARN_ON(!state))
3070 return 0;
b9cec075 3071
a1de91e5 3072 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3073 for_each_plane_in_state(state, plane, pstate, i) {
3074 id = skl_wm_plane_id(to_intel_plane(plane));
3075 intel_plane = to_intel_plane(plane);
3076
3077 if (intel_plane->pipe != intel_crtc->pipe)
3078 continue;
3079
3080 /* packed/uv */
3081 rate = skl_plane_relative_data_rate(intel_cstate,
3082 pstate, 0);
3083 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3084
3085 /* y-plane */
3086 rate = skl_plane_relative_data_rate(intel_cstate,
3087 pstate, 1);
3088 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3089 }
024c9045 3090
a1de91e5
MR		 3091 /* Calculate CRTC's total data rate from cached values */
3092 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3093 int id = skl_wm_plane_id(intel_plane);
024c9045 3094
a1de91e5 3095 /* packed/uv */
9c74d826
MR		 3096 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3097 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3098 }
3099
9c74d826
MR		 3100 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3101
b9cec075
DL		 3102 return total_data_rate;
3103}
3104
cbcfd14b
KM		 3105static uint16_t
3106skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3107 const int y)
3108{
3109 struct drm_framebuffer *fb = pstate->fb;
3110 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3111 uint32_t src_w, src_h;
3112 uint32_t min_scanlines = 8;
3113 uint8_t plane_bpp;
3114
3115 if (WARN_ON(!fb))
3116 return 0;
3117
3118 /* For packed formats, no y-plane, return 0 */
3119 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3120 return 0;
3121
3122 /* For Non Y-tile return 8-blocks */
3123 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3124 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3125 return 8;
3126
3127 src_w = drm_rect_width(&intel_pstate->src) >> 16;
3128 src_h = drm_rect_height(&intel_pstate->src) >> 16;
3129
3130 if (intel_rotation_90_or_270(pstate->rotation))
3131 swap(src_w, src_h);
3132
3133 /* Halve UV plane width and height for NV12 */
3134 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3135 src_w /= 2;
3136 src_h /= 2;
3137 }
3138
3139 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3140 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3141 else
3142 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3143
3144 if (intel_rotation_90_or_270(pstate->rotation)) {
3145 switch (plane_bpp) {
3146 case 1:
3147 min_scanlines = 32;
3148 break;
3149 case 2:
3150 min_scanlines = 16;
3151 break;
3152 case 4:
3153 min_scanlines = 8;
3154 break;
3155 case 8:
3156 min_scanlines = 4;
3157 break;
3158 default:
3159 WARN(1, "Unsupported pixel depth %u for rotation",
3160 plane_bpp);
3161 min_scanlines = 32;
3162 }
3163 }
3164
3165 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3166}
3167
c107acfe 3168static int
024c9045 3169skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3170 struct skl_ddb_allocation *ddb /* out */)
3171{
c107acfe 3172 struct drm_atomic_state *state = cstate->base.state;
024c9045 3173 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3174 struct drm_device *dev = crtc->dev;
3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3176 struct intel_plane *intel_plane;
c107acfe
MR		 3177 struct drm_plane *plane;
3178 struct drm_plane_state *pstate;
b9cec075 3179 enum pipe pipe = intel_crtc->pipe;
34bb56af 3180 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3181 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3182 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3183 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3184 unsigned int total_data_rate;
c107acfe
MR		 3185 int num_active;
3186 int id, i;
b9cec075 3187
a6d3460e
MR		 3188 if (WARN_ON(!state))
3189 return 0;
3190
c107acfe
MR		 3191 if (!cstate->base.active) {
3192 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3193 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3194 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3195 return 0;
3196 }
3197
a6d3460e 3198 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3199 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3200 if (alloc_size == 0) {
3201 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3202 return 0;
b9cec075
DL		 3203 }
3204
c107acfe 3205 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3206 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3207 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3208
3209 alloc_size -= cursor_blocks;
b9cec075 3210
80958155 3211 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3212 for_each_plane_in_state(state, plane, pstate, i) {
3213 intel_plane = to_intel_plane(plane);
3214 id = skl_wm_plane_id(intel_plane);
c107acfe 3215
a6d3460e
MR		 3216 if (intel_plane->pipe != pipe)
3217 continue;
c107acfe 3218
a6d3460e
MR		 3219 if (!to_intel_plane_state(pstate)->visible) {
3220 minimum[id] = 0;
3221 y_minimum[id] = 0;
3222 continue;
3223 }
3224 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3225 minimum[id] = 0;
3226 y_minimum[id] = 0;
3227 continue;
c107acfe 3228 }
a6d3460e 3229
cbcfd14b
KM		 3230 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3231 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3232 }
80958155 3233
c107acfe
MR		 3234 for (i = 0; i < PLANE_CURSOR; i++) {
3235 alloc_size -= minimum[i];
3236 alloc_size -= y_minimum[i];
80958155
DL		 3237 }
3238
b9cec075 3239 /*
80958155
DL		 3240 * 2. Distribute the remaining space in proportion to the amount of
3241 * data each plane needs to fetch from memory.
b9cec075
DL		 3242 *
3243 * FIXME: we may not allocate every single block here.
3244 */
024c9045 3245 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3246 if (total_data_rate == 0)
c107acfe 3247 return 0;
b9cec075 3248
34bb56af 3249 start = alloc->start;
024c9045 3250 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3251 unsigned int data_rate, y_data_rate;
3252 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3253 int id = skl_wm_plane_id(intel_plane);
b9cec075 3254
a1de91e5 3255 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3256
3257 /*
2cd601c6 3258 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3259 * promote the expression to 64 bits to avoid overflowing, the
3260 * result is < available as data_rate / total_data_rate < 1
3261 */
024c9045 3262 plane_blocks = minimum[id];
80958155
DL		 3263 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3264 total_data_rate);
b9cec075 3265
c107acfe
MR		 3266 /* Leave disabled planes at (0,0) */
3267 if (data_rate) {
3268 ddb->plane[pipe][id].start = start;
3269 ddb->plane[pipe][id].end = start + plane_blocks;
3270 }
b9cec075
DL		 3271
3272 start += plane_blocks;
2cd601c6
CK		 3273
3274 /*
3275 * allocation for y_plane part of planar format:
3276 */
a1de91e5
MR		 3277 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3278
3279 y_plane_blocks = y_minimum[id];
3280 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3281 total_data_rate);
2cd601c6 3282
c107acfe
MR		 3283 if (y_data_rate) {
3284 ddb->y_plane[pipe][id].start = start;
3285 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3286 }
a1de91e5
MR		 3287
3288 start += y_plane_blocks;
b9cec075
DL		 3289 }
3290
c107acfe 3291 return 0;
b9cec075
DL		 3292}
3293
5cec258b 3294static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3295{
3296 /* TODO: Take into account the scalers once we support them */
2d112de7 3297 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3298}
3299
3300/*
3301 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3302 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3303 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3304 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3305*/
ac484963 3306static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3307{
3308 uint32_t wm_intermediate_val, ret;
3309
3310 if (latency == 0)
3311 return UINT_MAX;
3312
ac484963 3313 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3314 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3315
3316 return ret;
3317}
3318
3319static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3320 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3321 uint64_t tiling, uint32_t latency)
2d41c0b5 3322{
d4c2aa60
TU		 3323 uint32_t ret;
3324 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3325 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3326
3327 if (latency == 0)
3328 return UINT_MAX;
3329
ac484963 3330 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3331
3332 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3333 tiling == I915_FORMAT_MOD_Yf_TILED) {
3334 plane_bytes_per_line *= 4;
3335 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3336 plane_blocks_per_line /= 4;
3337 } else {
3338 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3339 }
3340
2d41c0b5
PB		 3341 wm_intermediate_val = latency * pixel_rate;
3342 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3343 plane_blocks_per_line;
2d41c0b5
PB		 3344
3345 return ret;
3346}
3347
9c2f7a9d
KM		 3348static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3349 struct intel_plane_state *pstate)
3350{
3351 uint64_t adjusted_pixel_rate;
3352 uint64_t downscale_amount;
3353 uint64_t pixel_rate;
3354
3355 /* Shouldn't reach here on disabled planes... */
3356 if (WARN_ON(!pstate->visible))
3357 return 0;
3358
3359 /*
3360 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3361 * with additional adjustments for plane-specific scaling.
3362 */
3363 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3364 downscale_amount = skl_plane_downscale_amount(pstate);
3365
3366 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3367 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3368
3369 return pixel_rate;
3370}
3371
55994c2c
MR		 3372static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3373 struct intel_crtc_state *cstate,
3374 struct intel_plane_state *intel_pstate,
3375 uint16_t ddb_allocation,
3376 int level,
3377 uint16_t *out_blocks, /* out */
3378 uint8_t *out_lines, /* out */
3379 bool *enabled /* out */)
2d41c0b5 3380{
33815fa5
MR		 3381 struct drm_plane_state *pstate = &intel_pstate->base;
3382 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3383 uint32_t latency = dev_priv->wm.skl_latency[level];
3384 uint32_t method1, method2;
3385 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3386 uint32_t res_blocks, res_lines;
3387 uint32_t selected_result;
ac484963 3388 uint8_t cpp;
a280f7dd 3389 uint32_t width = 0, height = 0;
9c2f7a9d 3390 uint32_t plane_pixel_rate;
2d41c0b5 3391
55994c2c
MR		 3392 if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3393 *enabled = false;
3394 return 0;
3395 }
2d41c0b5 3396
a280f7dd
KM		 3397 width = drm_rect_width(&intel_pstate->src) >> 16;
3398 height = drm_rect_height(&intel_pstate->src) >> 16;
3399
33815fa5 3400 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3401 swap(width, height);
3402
ac484963 3403 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3404 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3405
3406 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3407 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3408 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3409 width,
3410 cpp,
3411 fb->modifier[0],
d4c2aa60 3412 latency);
2d41c0b5 3413
a280f7dd 3414 plane_bytes_per_line = width * cpp;
d4c2aa60 3415 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3416
024c9045
MR		 3417 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3418 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3419 uint32_t min_scanlines = 4;
3420 uint32_t y_tile_minimum;
33815fa5 3421 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3422 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3423 drm_format_plane_cpp(fb->pixel_format, 1) :
3424 drm_format_plane_cpp(fb->pixel_format, 0);
3425
ac484963 3426 switch (cpp) {
1fc0a8f7
TU		 3427 case 1:
3428 min_scanlines = 16;
3429 break;
3430 case 2:
3431 min_scanlines = 8;
3432 break;
3433 case 8:
3434 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3435 }
1fc0a8f7
TU		 3436 }
3437 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3438 selected_result = max(method2, y_tile_minimum);
3439 } else {
3440 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3441 selected_result = min(method1, method2);
3442 else
3443 selected_result = method1;
3444 }
2d41c0b5 3445
d4c2aa60
TU		 3446 res_blocks = selected_result + 1;
3447 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3448
0fda6568 3449 if (level >= 1 && level <= 7) {
024c9045
MR		 3450 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3451 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3452 res_lines += 4;
3453 else
3454 res_blocks++;
3455 }
e6d66171 3456
55994c2c
MR		 3457 if (res_blocks >= ddb_allocation || res_lines > 31) {
3458 *enabled = false;
6b6bada7
MR		 3459
3460 /*
3461 * If there are no valid level 0 watermarks, then we can't
3462 * support this display configuration.
3463 */
3464 if (level) {
3465 return 0;
3466 } else {
3467 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3468 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3469 to_intel_crtc(cstate->base.crtc)->pipe,
3470 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3471 res_blocks, ddb_allocation, res_lines);
3472
3473 return -EINVAL;
3474 }
55994c2c 3475 }
e6d66171
DL		 3476
3477 *out_blocks = res_blocks;
3478 *out_lines = res_lines;
55994c2c 3479 *enabled = true;
2d41c0b5 3480
55994c2c 3481 return 0;
2d41c0b5
PB		 3482}
3483
f4a96752
MR		 3484static int
3485skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3486 struct skl_ddb_allocation *ddb,
3487 struct intel_crtc_state *cstate,
3488 int level,
3489 struct skl_wm_level *result)
2d41c0b5 3490{
024c9045 3491 struct drm_device *dev = dev_priv->dev;
f4a96752 3492 struct drm_atomic_state *state = cstate->base.state;
024c9045 3493 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3494 struct drm_plane *plane;
024c9045 3495 struct intel_plane *intel_plane;
33815fa5 3496 struct intel_plane_state *intel_pstate;
2d41c0b5 3497 uint16_t ddb_blocks;
024c9045 3498 enum pipe pipe = intel_crtc->pipe;
55994c2c 3499 int ret;
024c9045 3500
f4a96752
MR		 3501 /*
3502 * We'll only calculate watermarks for planes that are actually
3503 * enabled, so make sure all other planes are set as disabled.
3504 */
3505 memset(result, 0, sizeof(*result));
3506
3507 for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
024c9045 3508 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3509
f4a96752
MR		 3510 plane = &intel_plane->base;
3511 intel_pstate = NULL;
3512 if (state)
3513 intel_pstate =
3514 intel_atomic_get_existing_plane_state(state,
3515 intel_plane);
3516
3517 /*
3518 * Note: If we start supporting multiple pending atomic commits
3519 * against the same planes/CRTC's in the future, plane->state
3520 * will no longer be the correct pre-state to use for the
3521 * calculations here and we'll need to change where we get the
3522 * 'unchanged' plane data from.
3523 *
3524 * For now this is fine because we only allow one queued commit
3525 * against a CRTC. Even if the plane isn't modified by this
3526 * transaction and we don't have a plane lock, we still have
3527 * the CRTC's lock, so we know that no other transactions are
3528 * racing with us to update it.
3529 */
3530 if (!intel_pstate)
3531 intel_pstate = to_intel_plane_state(plane->state);
3532
3533 WARN_ON(!intel_pstate->base.fb);
3534
2d41c0b5
PB		 3535 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3536
55994c2c
MR		 3537 ret = skl_compute_plane_wm(dev_priv,
3538 cstate,
3539 intel_pstate,
3540 ddb_blocks,
3541 level,
3542 &result->plane_res_b[i],
3543 &result->plane_res_l[i],
3544 &result->plane_en[i]);
3545 if (ret)
3546 return ret;
2d41c0b5 3547 }
f4a96752
MR		 3548
3549 return 0;
2d41c0b5
PB		 3550}
3551
407b50f3 3552static uint32_t
024c9045 3553skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3554{
024c9045 3555 if (!cstate->base.active)
407b50f3
DL		 3556 return 0;
3557
024c9045 3558 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3559 return 0;
407b50f3 3560
024c9045
MR		 3561 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3562 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3563}
3564
024c9045 3565static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3566 struct skl_wm_level *trans_wm /* out */)
407b50f3 3567{
024c9045 3568 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3570 struct intel_plane *intel_plane;
9414f563 3571
024c9045 3572 if (!cstate->base.active)
407b50f3 3573 return;
9414f563
DL		 3574
3575 /* Until we know more, just disable transition WMs */
024c9045
MR		 3576 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3577 int i = skl_wm_plane_id(intel_plane);
3578
9414f563 3579 trans_wm->plane_en[i] = false;
024c9045 3580 }
407b50f3
DL		 3581}
3582
55994c2c
MR		 3583static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3584 struct skl_ddb_allocation *ddb,
3585 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3586{
024c9045 3587 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3588 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3589 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3590 int ret;
2d41c0b5
PB		 3591
3592 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3593 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3594 level, &pipe_wm->wm[level]);
3595 if (ret)
3596 return ret;
2d41c0b5 3597 }
024c9045 3598 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3599
024c9045 3600 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3601
3602 return 0;
2d41c0b5
PB		 3603}
3604
3605static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3606 struct skl_pipe_wm *p_wm,
3607 struct skl_wm_values *r,
3608 struct intel_crtc *intel_crtc)
3609{
3610 int level, max_level = ilk_wm_max_level(dev);
3611 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3612 uint32_t temp;
3613 int i;
2d41c0b5
PB		 3614
3615 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3616 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3617 temp = 0;
2d41c0b5
PB		 3618
3619 temp |= p_wm->wm[level].plane_res_l[i] <<
3620 PLANE_WM_LINES_SHIFT;
3621 temp |= p_wm->wm[level].plane_res_b[i];
3622 if (p_wm->wm[level].plane_en[i])
3623 temp |= PLANE_WM_EN;
3624
3625 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3626 }
3627
3628 temp = 0;
2d41c0b5 3629
4969d33e
MR		 3630 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3631 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3632
4969d33e 3633 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3634 temp |= PLANE_WM_EN;
3635
4969d33e 3636 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3637
3638 }
3639
9414f563
DL		 3640 /* transition WMs */
3641 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3642 temp = 0;
3643 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3644 temp |= p_wm->trans_wm.plane_res_b[i];
3645 if (p_wm->trans_wm.plane_en[i])
3646 temp |= PLANE_WM_EN;
3647
3648 r->plane_trans[pipe][i] = temp;
3649 }
3650
3651 temp = 0;
4969d33e
MR		 3652 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3653 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3654 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3655 temp |= PLANE_WM_EN;
3656
4969d33e 3657 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3658
2d41c0b5
PB		 3659 r->wm_linetime[pipe] = p_wm->linetime;
3660}
3661
f0f59a00
VS		 3662static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3663 i915_reg_t reg,
16160e3d
DL		 3664 const struct skl_ddb_entry *entry)
3665{
3666 if (entry->end)
3667 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3668 else
3669 I915_WRITE(reg, 0);
3670}
3671
2d41c0b5
PB		 3672static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3673 const struct skl_wm_values *new)
3674{
3675 struct drm_device *dev = dev_priv->dev;
3676 struct intel_crtc *crtc;
3677
19c8054c 3678 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3679 int i, level, max_level = ilk_wm_max_level(dev);
3680 enum pipe pipe = crtc->pipe;
3681
2b4b9f35 3682 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
5d374d96 3683 continue;
734fa01f
MR		 3684 if (!crtc->active)
3685 continue;
8211bd5b 3686
5d374d96 3687 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3688
5d374d96
DL		 3689 for (level = 0; level <= max_level; level++) {
3690 for (i = 0; i < intel_num_planes(crtc); i++)
3691 I915_WRITE(PLANE_WM(pipe, i, level),
3692 new->plane[pipe][i][level]);
3693 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3694 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3695 }
5d374d96
DL		 3696 for (i = 0; i < intel_num_planes(crtc); i++)
3697 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3698 new->plane_trans[pipe][i]);
4969d33e
MR		 3699 I915_WRITE(CUR_WM_TRANS(pipe),
3700 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3701
2cd601c6 3702 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3703 skl_ddb_entry_write(dev_priv,
3704 PLANE_BUF_CFG(pipe, i),
3705 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3706 skl_ddb_entry_write(dev_priv,
3707 PLANE_NV12_BUF_CFG(pipe, i),
3708 &new->ddb.y_plane[pipe][i]);
3709 }
5d374d96
DL		 3710
3711 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3712 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3713 }
2d41c0b5
PB		 3714}
3715
0e8fb7ba
DL		 3716/*
3717 * When setting up a new DDB allocation arrangement, we need to correctly
3718 * sequence the times at which the new allocations for the pipes are taken into
3719 * account or we'll have pipes fetching from space previously allocated to
3720 * another pipe.
3721 *
3722 * Roughly the sequence looks like:
3723 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3724 * overlapping with a previous light-up pipe (another way to put it is:
3725 * pipes with their new allocation strickly included into their old ones).
3726 * 2. re-allocate the other pipes that get their allocation reduced
3727 * 3. allocate the pipes having their allocation increased
3728 *
3729 * Steps 1. and 2. are here to take care of the following case:
3730 * - Initially DDB looks like this:
3731 * | B | C |
3732 * - enable pipe A.
3733 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3734 * allocation
3735 * | A | B | C |
3736 *
3737 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3738 */
3739
d21b795c
DL		 3740static void
3741skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3742{
0e8fb7ba
DL		 3743 int plane;
3744
d21b795c
DL		 3745 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3746
dd740780 3747 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3748 I915_WRITE(PLANE_SURF(pipe, plane),
3749 I915_READ(PLANE_SURF(pipe, plane)));
3750 }
3751 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3752}
3753
3754static bool
3755skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3756 const struct skl_ddb_allocation *new,
3757 enum pipe pipe)
3758{
3759 uint16_t old_size, new_size;
3760
3761 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3762 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3763
3764 return old_size != new_size &&
3765 new->pipe[pipe].start >= old->pipe[pipe].start &&
3766 new->pipe[pipe].end <= old->pipe[pipe].end;
3767}
3768
3769static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3770 struct skl_wm_values *new_values)
3771{
3772 struct drm_device *dev = dev_priv->dev;
3773 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3774 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3775 struct intel_crtc *crtc;
3776 enum pipe pipe;
3777
3778 new_ddb = &new_values->ddb;
3779 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3780
3781 /*
3782 * First pass: flush the pipes with the new allocation contained into
3783 * the old space.
3784 *
3785 * We'll wait for the vblank on those pipes to ensure we can safely
3786 * re-allocate the freed space without this pipe fetching from it.
3787 */
3788 for_each_intel_crtc(dev, crtc) {
3789 if (!crtc->active)
3790 continue;
3791
3792 pipe = crtc->pipe;
3793
3794 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3795 continue;
3796
d21b795c 3797 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3798 intel_wait_for_vblank(dev, pipe);
3799
3800 reallocated[pipe] = true;
3801 }
3802
3803
3804 /*
3805 * Second pass: flush the pipes that are having their allocation
3806 * reduced, but overlapping with a previous allocation.
3807 *
3808 * Here as well we need to wait for the vblank to make sure the freed
3809 * space is not used anymore.
3810 */
3811 for_each_intel_crtc(dev, crtc) {
3812 if (!crtc->active)
3813 continue;
3814
3815 pipe = crtc->pipe;
3816
3817 if (reallocated[pipe])
3818 continue;
3819
3820 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3821 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3822 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3823 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3824 reallocated[pipe] = true;
0e8fb7ba 3825 }
0e8fb7ba
DL		 3826 }
3827
3828 /*
3829 * Third pass: flush the pipes that got more space allocated.
3830 *
3831 * We don't need to actively wait for the update here, next vblank
3832 * will just get more DDB space with the correct WM values.
3833 */
3834 for_each_intel_crtc(dev, crtc) {
3835 if (!crtc->active)
3836 continue;
3837
3838 pipe = crtc->pipe;
3839
3840 /*
3841 * At this point, only the pipes more space than before are
3842 * left to re-allocate.
3843 */
3844 if (reallocated[pipe])
3845 continue;
3846
d21b795c 3847 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3848 }
3849}
3850
55994c2c
MR		 3851static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3852 struct skl_ddb_allocation *ddb, /* out */
3853 struct skl_pipe_wm *pipe_wm, /* out */
3854 bool *changed /* out */)
2d41c0b5 3855{
f4a96752
MR		 3856 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3857 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3858 int ret;
2d41c0b5 3859
55994c2c
MR		 3860 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3861 if (ret)
3862 return ret;
2d41c0b5 3863
4e0963c7 3864 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3865 *changed = false;
3866 else
3867 *changed = true;
2d41c0b5 3868
55994c2c 3869 return 0;
2d41c0b5
PB		 3870}
3871
98d39494
MR		 3872static int
3873skl_compute_ddb(struct drm_atomic_state *state)
3874{
3875 struct drm_device *dev = state->dev;
3876 struct drm_i915_private *dev_priv = to_i915(dev);
3877 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3878 struct intel_crtc *intel_crtc;
734fa01f 3879 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
98d39494
MR		 3880 unsigned realloc_pipes = dev_priv->active_crtcs;
3881 int ret;
3882
3883 /*
3884 * If this is our first atomic update following hardware readout,
3885 * we can't trust the DDB that the BIOS programmed for us. Let's
3886 * pretend that all pipes switched active status so that we'll
3887 * ensure a full DDB recompute.
3888 */
3889 if (dev_priv->wm.distrust_bios_wm)
3890 intel_state->active_pipe_changes = ~0;
3891
3892 /*
3893 * If the modeset changes which CRTC's are active, we need to
3894 * recompute the DDB allocation for *all* active pipes, even
3895 * those that weren't otherwise being modified in any way by this
3896 * atomic commit. Due to the shrinking of the per-pipe allocations
3897 * when new active CRTC's are added, it's possible for a pipe that
3898 * we were already using and aren't changing at all here to suddenly
3899 * become invalid if its DDB needs exceeds its new allocation.
3900 *
3901 * Note that if we wind up doing a full DDB recompute, we can't let
3902 * any other display updates race with this transaction, so we need
3903 * to grab the lock on *all* CRTC's.
3904 */
734fa01f 3905 if (intel_state->active_pipe_changes) {
98d39494 3906 realloc_pipes = ~0;
734fa01f
MR		 3907 intel_state->wm_results.dirty_pipes = ~0;
3908 }
98d39494
MR		 3909
3910 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3911 struct intel_crtc_state *cstate;
3912
3913 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3914 if (IS_ERR(cstate))
3915 return PTR_ERR(cstate);
3916
734fa01f 3917 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 3918 if (ret)
3919 return ret;
3920 }
3921
3922 return 0;
3923}
3924
3925static int
3926skl_compute_wm(struct drm_atomic_state *state)
3927{
3928 struct drm_crtc *crtc;
3929 struct drm_crtc_state *cstate;
734fa01f
MR		 3930 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3931 struct skl_wm_values *results = &intel_state->wm_results;
3932 struct skl_pipe_wm *pipe_wm;
98d39494 3933 bool changed = false;
734fa01f 3934 int ret, i;
98d39494
MR		 3935
3936 /*
3937 * If this transaction isn't actually touching any CRTC's, don't
3938 * bother with watermark calculation. Note that if we pass this
3939 * test, we're guaranteed to hold at least one CRTC state mutex,
3940 * which means we can safely use values like dev_priv->active_crtcs
3941 * since any racing commits that want to update them would need to
3942 * hold _all_ CRTC state mutexes.
3943 */
3944 for_each_crtc_in_state(state, crtc, cstate, i)
3945 changed = true;
3946 if (!changed)
3947 return 0;
3948
734fa01f
MR		 3949 /* Clear all dirty flags */
3950 results->dirty_pipes = 0;
3951
98d39494
MR		 3952 ret = skl_compute_ddb(state);
3953 if (ret)
3954 return ret;
3955
734fa01f
MR		 3956 /*
3957 * Calculate WM's for all pipes that are part of this transaction.
3958 * Note that the DDB allocation above may have added more CRTC's that
3959 * weren't otherwise being modified (and set bits in dirty_pipes) if
3960 * pipe allocations had to change.
3961 *
3962 * FIXME: Now that we're doing this in the atomic check phase, we
3963 * should allow skl_update_pipe_wm() to return failure in cases where
3964 * no suitable watermark values can be found.
3965 */
3966 for_each_crtc_in_state(state, crtc, cstate, i) {
3967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3968 struct intel_crtc_state *intel_cstate =
3969 to_intel_crtc_state(cstate);
3970
3971 pipe_wm = &intel_cstate->wm.skl.optimal;
3972 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
3973 &changed);
3974 if (ret)
3975 return ret;
3976
3977 if (changed)
3978 results->dirty_pipes |= drm_crtc_mask(crtc);
3979
3980 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3981 /* This pipe's WM's did not change */
3982 continue;
3983
3984 intel_cstate->update_wm_pre = true;
3985 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
3986 }
3987
98d39494
MR		 3988 return 0;
3989}
3990
2d41c0b5
PB		 3991static void skl_update_wm(struct drm_crtc *crtc)
3992{
3993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3994 struct drm_device *dev = crtc->dev;
3995 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3996 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7 3997 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 3998 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
adda50b8 3999
734fa01f 4000 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4001 return;
4002
734fa01f
MR		 4003 intel_crtc->wm.active.skl = *pipe_wm;
4004
4005 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4006
2d41c0b5 4007 skl_write_wm_values(dev_priv, results);
0e8fb7ba 4008 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 4009
4010 /* store the new configuration */
4011 dev_priv->wm.skl_hw = *results;
734fa01f
MR		 4012
4013 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4014}
4015
d890565c
VS		 4016static void ilk_compute_wm_config(struct drm_device *dev,
4017 struct intel_wm_config *config)
4018{
4019 struct intel_crtc *crtc;
4020
4021 /* Compute the currently _active_ config */
4022 for_each_intel_crtc(dev, crtc) {
4023 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4024
4025 if (!wm->pipe_enabled)
4026 continue;
4027
4028 config->sprites_enabled |= wm->sprites_enabled;
4029 config->sprites_scaled |= wm->sprites_scaled;
4030 config->num_pipes_active++;
4031 }
4032}
4033
ed4a6a7c 4034static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4035{
ed4a6a7c 4036 struct drm_device *dev = dev_priv->dev;
b9d5c839 4037 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4038 struct ilk_wm_maximums max;
d890565c 4039 struct intel_wm_config config = {};
820c1980 4040 struct ilk_wm_values results = {};
77c122bc 4041 enum intel_ddb_partitioning partitioning;
261a27d1 4042
d890565c
VS		 4043 ilk_compute_wm_config(dev, &config);
4044
4045 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4046 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4047
4048 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4049 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4050 config.num_pipes_active == 1 && config.sprites_enabled) {
4051 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4052 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4053
820c1980 4054 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4055 } else {
198a1e9b 4056 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4057 }
4058
198a1e9b 4059 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4060 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4061
820c1980 4062 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4063
820c1980 4064 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4065}
4066
ed4a6a7c 4067static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4068{
ed4a6a7c
MR		 4069 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4070 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4071
ed4a6a7c 4072 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4073 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4074 ilk_program_watermarks(dev_priv);
4075 mutex_unlock(&dev_priv->wm.wm_mutex);
4076}
bf220452 4077
ed4a6a7c
MR		 4078static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4079{
4080 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4081 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4082
ed4a6a7c
MR		 4083 mutex_lock(&dev_priv->wm.wm_mutex);
4084 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4085 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4086 ilk_program_watermarks(dev_priv);
4087 }
4088 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4089}
4090
3078999f
PB		 4091static void skl_pipe_wm_active_state(uint32_t val,
4092 struct skl_pipe_wm *active,
4093 bool is_transwm,
4094 bool is_cursor,
4095 int i,
4096 int level)
4097{
4098 bool is_enabled = (val & PLANE_WM_EN) != 0;
4099
4100 if (!is_transwm) {
4101 if (!is_cursor) {
4102 active->wm[level].plane_en[i] = is_enabled;
4103 active->wm[level].plane_res_b[i] =
4104 val & PLANE_WM_BLOCKS_MASK;
4105 active->wm[level].plane_res_l[i] =
4106 (val >> PLANE_WM_LINES_SHIFT) &
4107 PLANE_WM_LINES_MASK;
4108 } else {
4969d33e
MR		 4109 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4110 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4111 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4112 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4113 (val >> PLANE_WM_LINES_SHIFT) &
4114 PLANE_WM_LINES_MASK;
4115 }
4116 } else {
4117 if (!is_cursor) {
4118 active->trans_wm.plane_en[i] = is_enabled;
4119 active->trans_wm.plane_res_b[i] =
4120 val & PLANE_WM_BLOCKS_MASK;
4121 active->trans_wm.plane_res_l[i] =
4122 (val >> PLANE_WM_LINES_SHIFT) &
4123 PLANE_WM_LINES_MASK;
4124 } else {
4969d33e
MR		 4125 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4126 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4127 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4128 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4129 (val >> PLANE_WM_LINES_SHIFT) &
4130 PLANE_WM_LINES_MASK;
4131 }
4132 }
4133}
4134
4135static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4136{
4137 struct drm_device *dev = crtc->dev;
4138 struct drm_i915_private *dev_priv = dev->dev_private;
4139 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4141 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4142 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4143 enum pipe pipe = intel_crtc->pipe;
4144 int level, i, max_level;
4145 uint32_t temp;
4146
4147 max_level = ilk_wm_max_level(dev);
4148
4149 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4150
4151 for (level = 0; level <= max_level; level++) {
4152 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4153 hw->plane[pipe][i][level] =
4154 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4155 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4156 }
4157
4158 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4159 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4160 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4161
3ef00284 4162 if (!intel_crtc->active)
3078999f
PB		 4163 return;
4164
2b4b9f35 4165 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4166
4167 active->linetime = hw->wm_linetime[pipe];
4168
4169 for (level = 0; level <= max_level; level++) {
4170 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4171 temp = hw->plane[pipe][i][level];
4172 skl_pipe_wm_active_state(temp, active, false,
4173 false, i, level);
4174 }
4969d33e 4175 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4176 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4177 }
4178
4179 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4180 temp = hw->plane_trans[pipe][i];
4181 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4182 }
4183
4969d33e 4184 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4185 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4186
4187 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4188}
4189
4190void skl_wm_get_hw_state(struct drm_device *dev)
4191{
a269c583
DL		 4192 struct drm_i915_private *dev_priv = dev->dev_private;
4193 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4194 struct drm_crtc *crtc;
4195
a269c583 4196 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4198 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4199
279e99d7
MR		 4200 if (dev_priv->active_crtcs) {
4201 /* Fully recompute DDB on first atomic commit */
4202 dev_priv->wm.distrust_bios_wm = true;
4203 } else {
4204 /* Easy/common case; just sanitize DDB now if everything off */
4205 memset(ddb, 0, sizeof(*ddb));
4206 }
3078999f
PB		 4207}
4208
243e6a44
VS		 4209static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4210{
4211 struct drm_device *dev = crtc->dev;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4213 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4215 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4216 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4217 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4218 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4219 [PIPE_A] = WM0_PIPEA_ILK,
4220 [PIPE_B] = WM0_PIPEB_ILK,
4221 [PIPE_C] = WM0_PIPEC_IVB,
4222 };
4223
4224 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4225 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4226 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4227
15606534
VS		 4228 memset(active, 0, sizeof(*active));
4229
3ef00284 4230 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4231
4232 if (active->pipe_enabled) {
243e6a44
VS		 4233 u32 tmp = hw->wm_pipe[pipe];
4234
4235 /*
4236 * For active pipes LP0 watermark is marked as
4237 * enabled, and LP1+ watermaks as disabled since
4238 * we can't really reverse compute them in case
4239 * multiple pipes are active.
4240 */
4241 active->wm[0].enable = true;
4242 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4243 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4244 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4245 active->linetime = hw->wm_linetime[pipe];
4246 } else {
4247 int level, max_level = ilk_wm_max_level(dev);
4248
4249 /*
4250 * For inactive pipes, all watermark levels
4251 * should be marked as enabled but zeroed,
4252 * which is what we'd compute them to.
4253 */
4254 for (level = 0; level <= max_level; level++)
4255 active->wm[level].enable = true;
4256 }
4e0963c7
MR		 4257
4258 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4259}
4260
6eb1a681
VS		 4261#define _FW_WM(value, plane) \
4262 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4263#define _FW_WM_VLV(value, plane) \
4264 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4265
4266static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4267 struct vlv_wm_values *wm)
4268{
4269 enum pipe pipe;
4270 uint32_t tmp;
4271
4272 for_each_pipe(dev_priv, pipe) {
4273 tmp = I915_READ(VLV_DDL(pipe));
4274
4275 wm->ddl[pipe].primary =
4276 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4277 wm->ddl[pipe].cursor =
4278 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4279 wm->ddl[pipe].sprite[0] =
4280 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4281 wm->ddl[pipe].sprite[1] =
4282 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4283 }
4284
4285 tmp = I915_READ(DSPFW1);
4286 wm->sr.plane = _FW_WM(tmp, SR);
4287 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4288 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4289 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4290
4291 tmp = I915_READ(DSPFW2);
4292 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4293 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4294 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4295
4296 tmp = I915_READ(DSPFW3);
4297 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4298
4299 if (IS_CHERRYVIEW(dev_priv)) {
4300 tmp = I915_READ(DSPFW7_CHV);
4301 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4302 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4303
4304 tmp = I915_READ(DSPFW8_CHV);
4305 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4306 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4307
4308 tmp = I915_READ(DSPFW9_CHV);
4309 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4310 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4311
4312 tmp = I915_READ(DSPHOWM);
4313 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4314 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4315 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4316 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4317 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4318 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4319 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4320 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4321 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4322 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4323 } else {
4324 tmp = I915_READ(DSPFW7);
4325 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4326 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4327
4328 tmp = I915_READ(DSPHOWM);
4329 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4330 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4331 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4332 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4333 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4334 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4335 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4336 }
4337}
4338
4339#undef _FW_WM
4340#undef _FW_WM_VLV
4341
4342void vlv_wm_get_hw_state(struct drm_device *dev)
4343{
4344 struct drm_i915_private *dev_priv = to_i915(dev);
4345 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4346 struct intel_plane *plane;
4347 enum pipe pipe;
4348 u32 val;
4349
4350 vlv_read_wm_values(dev_priv, wm);
4351
4352 for_each_intel_plane(dev, plane) {
4353 switch (plane->base.type) {
4354 int sprite;
4355 case DRM_PLANE_TYPE_CURSOR:
4356 plane->wm.fifo_size = 63;
4357 break;
4358 case DRM_PLANE_TYPE_PRIMARY:
4359 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4360 break;
4361 case DRM_PLANE_TYPE_OVERLAY:
4362 sprite = plane->plane;
4363 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4364 break;
4365 }
4366 }
4367
4368 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4369 wm->level = VLV_WM_LEVEL_PM2;
4370
4371 if (IS_CHERRYVIEW(dev_priv)) {
4372 mutex_lock(&dev_priv->rps.hw_lock);
4373
4374 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4375 if (val & DSP_MAXFIFO_PM5_ENABLE)
4376 wm->level = VLV_WM_LEVEL_PM5;
4377
58590c14
VS		 4378 /*
4379 * If DDR DVFS is disabled in the BIOS, Punit
4380 * will never ack the request. So if that happens
4381 * assume we don't have to enable/disable DDR DVFS
4382 * dynamically. To test that just set the REQ_ACK
4383 * bit to poke the Punit, but don't change the
4384 * HIGH/LOW bits so that we don't actually change
4385 * the current state.
4386 */
6eb1a681 4387 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4388 val |= FORCE_DDR_FREQ_REQ_ACK;
4389 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4390
4391 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4392 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4393 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4394 "assuming DDR DVFS is disabled\n");
4395 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4396 } else {
4397 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4398 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4399 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4400 }
6eb1a681
VS		 4401
4402 mutex_unlock(&dev_priv->rps.hw_lock);
4403 }
4404
4405 for_each_pipe(dev_priv, pipe)
4406 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4407 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4408 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4409
4410 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4411 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4412}
4413
243e6a44
VS		 4414void ilk_wm_get_hw_state(struct drm_device *dev)
4415{
4416 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4417 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4418 struct drm_crtc *crtc;
4419
70e1e0ec 4420 for_each_crtc(dev, crtc)
243e6a44
VS		 4421 ilk_pipe_wm_get_hw_state(crtc);
4422
4423 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4424 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4425 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4426
4427 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4428 if (INTEL_INFO(dev)->gen >= 7) {
4429 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4430 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4431 }
243e6a44 4432
a42a5719 4433 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4434 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4435 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4436 else if (IS_IVYBRIDGE(dev))
4437 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4438 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4439
4440 hw->enable_fbc_wm =
4441 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4442}
4443
b445e3b0
ED		 4444/**
4445 * intel_update_watermarks - update FIFO watermark values based on current modes
4446 *
4447 * Calculate watermark values for the various WM regs based on current mode
4448 * and plane configuration.
4449 *
4450 * There are several cases to deal with here:
4451 * - normal (i.e. non-self-refresh)
4452 * - self-refresh (SR) mode
4453 * - lines are large relative to FIFO size (buffer can hold up to 2)
4454 * - lines are small relative to FIFO size (buffer can hold more than 2
4455 * lines), so need to account for TLB latency
4456 *
4457 * The normal calculation is:
4458 * watermark = dotclock * bytes per pixel * latency
4459 * where latency is platform & configuration dependent (we assume pessimal
4460 * values here).
4461 *
4462 * The SR calculation is:
4463 * watermark = (trunc(latency/line time)+1) * surface width *
4464 * bytes per pixel
4465 * where
4466 * line time = htotal / dotclock
4467 * surface width = hdisplay for normal plane and 64 for cursor
4468 * and latency is assumed to be high, as above.
4469 *
4470 * The final value programmed to the register should always be rounded up,
4471 * and include an extra 2 entries to account for clock crossings.
4472 *
4473 * We don't use the sprite, so we can ignore that. And on Crestline we have
4474 * to set the non-SR watermarks to 8.
4475 */
46ba614c 4476void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4477{
46ba614c 4478 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4479
4480 if (dev_priv->display.update_wm)
46ba614c 4481 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4482}
4483
e2828914 4484/*
9270388e 4485 * Lock protecting IPS related data structures
9270388e
DV		 4486 */
4487DEFINE_SPINLOCK(mchdev_lock);
4488
4489/* Global for IPS driver to get at the current i915 device. Protected by
4490 * mchdev_lock. */
4491static struct drm_i915_private *i915_mch_dev;
4492
91d14251 4493bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4494{
2b4e57bd
ED		 4495 u16 rgvswctl;
4496
9270388e
DV		 4497 assert_spin_locked(&mchdev_lock);
4498
2b4e57bd
ED		 4499 rgvswctl = I915_READ16(MEMSWCTL);
4500 if (rgvswctl & MEMCTL_CMD_STS) {
4501 DRM_DEBUG("gpu busy, RCS change rejected\n");
4502 return false; /* still busy with another command */
4503 }
4504
4505 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4506 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4507 I915_WRITE16(MEMSWCTL, rgvswctl);
4508 POSTING_READ16(MEMSWCTL);
4509
4510 rgvswctl |= MEMCTL_CMD_STS;
4511 I915_WRITE16(MEMSWCTL, rgvswctl);
4512
4513 return true;
4514}
4515
91d14251 4516static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4517{
84f1b20f 4518 u32 rgvmodectl;
2b4e57bd
ED		 4519 u8 fmax, fmin, fstart, vstart;
4520
9270388e
DV		 4521 spin_lock_irq(&mchdev_lock);
4522
84f1b20f
TU		 4523 rgvmodectl = I915_READ(MEMMODECTL);
4524
2b4e57bd
ED		 4525 /* Enable temp reporting */
4526 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4527 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4528
4529 /* 100ms RC evaluation intervals */
4530 I915_WRITE(RCUPEI, 100000);
4531 I915_WRITE(RCDNEI, 100000);
4532
4533 /* Set max/min thresholds to 90ms and 80ms respectively */
4534 I915_WRITE(RCBMAXAVG, 90000);
4535 I915_WRITE(RCBMINAVG, 80000);
4536
4537 I915_WRITE(MEMIHYST, 1);
4538
4539 /* Set up min, max, and cur for interrupt handling */
4540 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4541 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4542 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4543 MEMMODE_FSTART_SHIFT;
4544
616847e7 4545 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4546 PXVFREQ_PX_SHIFT;
4547
20e4d407
DV		 4548 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4549 dev_priv->ips.fstart = fstart;
2b4e57bd 4550
20e4d407
DV		 4551 dev_priv->ips.max_delay = fstart;
4552 dev_priv->ips.min_delay = fmin;
4553 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4554
4555 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4556 fmax, fmin, fstart);
4557
4558 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4559
4560 /*
4561 * Interrupts will be enabled in ironlake_irq_postinstall
4562 */
4563
4564 I915_WRITE(VIDSTART, vstart);
4565 POSTING_READ(VIDSTART);
4566
4567 rgvmodectl |= MEMMODE_SWMODE_EN;
4568 I915_WRITE(MEMMODECTL, rgvmodectl);
4569
9270388e 4570 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4571 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4572 mdelay(1);
2b4e57bd 4573
91d14251 4574 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4575
7d81c3e0
VS		 4576 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4577 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4578 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4579 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4580 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4581
4582 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4583}
4584
91d14251 4585static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4586{
9270388e
DV		 4587 u16 rgvswctl;
4588
4589 spin_lock_irq(&mchdev_lock);
4590
4591 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4592
4593 /* Ack interrupts, disable EFC interrupt */
4594 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4595 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4596 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4597 I915_WRITE(DEIIR, DE_PCU_EVENT);
4598 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4599
4600 /* Go back to the starting frequency */
91d14251 4601 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4602 mdelay(1);
2b4e57bd
ED		 4603 rgvswctl |= MEMCTL_CMD_STS;
4604 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4605 mdelay(1);
2b4e57bd 4606
9270388e 4607 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4608}
4609
acbe9475
DV		 4610/* There's a funny hw issue where the hw returns all 0 when reading from
4611 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4612 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4613 * all limits and the gpu stuck at whatever frequency it is at atm).
4614 */
74ef1173 4615static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4616{
7b9e0ae6 4617 u32 limits;
2b4e57bd 4618
20b46e59
DV		 4619 /* Only set the down limit when we've reached the lowest level to avoid
4620 * getting more interrupts, otherwise leave this clear. This prevents a
4621 * race in the hw when coming out of rc6: There's a tiny window where
4622 * the hw runs at the minimal clock before selecting the desired
4623 * frequency, if the down threshold expires in that window we will not
4624 * receive a down interrupt. */
2d1fe073 4625 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4626 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4627 if (val <= dev_priv->rps.min_freq_softlimit)
4628 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4629 } else {
4630 limits = dev_priv->rps.max_freq_softlimit << 24;
4631 if (val <= dev_priv->rps.min_freq_softlimit)
4632 limits |= dev_priv->rps.min_freq_softlimit << 16;
4633 }
20b46e59
DV		 4634
4635 return limits;
4636}
4637
dd75fdc8
CW		 4638static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4639{
4640 int new_power;
8a586437
AG		 4641 u32 threshold_up = 0, threshold_down = 0; /* in % */
4642 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4643
4644 new_power = dev_priv->rps.power;
4645 switch (dev_priv->rps.power) {
4646 case LOW_POWER:
b39fb297 4647 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4648 new_power = BETWEEN;
4649 break;
4650
4651 case BETWEEN:
b39fb297 4652 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4653 new_power = LOW_POWER;
b39fb297 4654 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4655 new_power = HIGH_POWER;
4656 break;
4657
4658 case HIGH_POWER:
b39fb297 4659 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4660 new_power = BETWEEN;
4661 break;
4662 }
4663 /* Max/min bins are special */
aed242ff 4664 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4665 new_power = LOW_POWER;
aed242ff 4666 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4667 new_power = HIGH_POWER;
4668 if (new_power == dev_priv->rps.power)
4669 return;
4670
4671 /* Note the units here are not exactly 1us, but 1280ns. */
4672 switch (new_power) {
4673 case LOW_POWER:
4674 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4675 ei_up = 16000;
4676 threshold_up = 95;
dd75fdc8
CW		 4677
4678 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4679 ei_down = 32000;
4680 threshold_down = 85;
dd75fdc8
CW		 4681 break;
4682
4683 case BETWEEN:
4684 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4685 ei_up = 13000;
4686 threshold_up = 90;
dd75fdc8
CW		 4687
4688 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4689 ei_down = 32000;
4690 threshold_down = 75;
dd75fdc8
CW		 4691 break;
4692
4693 case HIGH_POWER:
4694 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4695 ei_up = 10000;
4696 threshold_up = 85;
dd75fdc8
CW		 4697
4698 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4699 ei_down = 32000;
4700 threshold_down = 60;
dd75fdc8
CW		 4701 break;
4702 }
4703
8a586437
AG		 4704 I915_WRITE(GEN6_RP_UP_EI,
4705 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4706 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4707 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4708
4709 I915_WRITE(GEN6_RP_DOWN_EI,
4710 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4711 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4712 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4713
4714 I915_WRITE(GEN6_RP_CONTROL,
4715 GEN6_RP_MEDIA_TURBO |
4716 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4717 GEN6_RP_MEDIA_IS_GFX |
4718 GEN6_RP_ENABLE |
4719 GEN6_RP_UP_BUSY_AVG |
4720 GEN6_RP_DOWN_IDLE_AVG);
4721
dd75fdc8 4722 dev_priv->rps.power = new_power;
8fb55197
CW		 4723 dev_priv->rps.up_threshold = threshold_up;
4724 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4725 dev_priv->rps.last_adj = 0;
4726}
4727
2876ce73
CW		 4728static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4729{
4730 u32 mask = 0;
4731
4732 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4733 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4734 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4735 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4736
7b3c29f6
CW		 4737 mask &= dev_priv->pm_rps_events;
4738
59d02a1f 4739 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4740}
4741
b8a5ff8d
JM		 4742/* gen6_set_rps is called to update the frequency request, but should also be
4743 * called when the range (min_delay and max_delay) is modified so that we can
4744 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4745static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4746{
23eafea6 4747 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4748 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4749 return;
4750
4fc688ce 4751 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4752 WARN_ON(val > dev_priv->rps.max_freq);
4753 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4754
eb64cad1
CW		 4755 /* min/max delay may still have been modified so be sure to
4756 * write the limits value.
4757 */
4758 if (val != dev_priv->rps.cur_freq) {
4759 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4760
dc97997a 4761 if (IS_GEN9(dev_priv))
5704195c
AG		 4762 I915_WRITE(GEN6_RPNSWREQ,
4763 GEN9_FREQUENCY(val));
dc97997a 4764 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4765 I915_WRITE(GEN6_RPNSWREQ,
4766 HSW_FREQUENCY(val));
4767 else
4768 I915_WRITE(GEN6_RPNSWREQ,
4769 GEN6_FREQUENCY(val) |
4770 GEN6_OFFSET(0) |
4771 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4772 }
7b9e0ae6 4773
7b9e0ae6
CW		 4774 /* Make sure we continue to get interrupts
4775 * until we hit the minimum or maximum frequencies.
4776 */
74ef1173 4777 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4778 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4779
d5570a72
BW		 4780 POSTING_READ(GEN6_RPNSWREQ);
4781
b39fb297 4782 dev_priv->rps.cur_freq = val;
0f94592e 4783 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4784}
4785
dc97997a 4786static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4787{
ffe02b40 4788 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4789 WARN_ON(val > dev_priv->rps.max_freq);
4790 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4791
dc97997a 4792 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4793 "Odd GPU freq value\n"))
4794 val &= ~1;
4795
cd25dd5b
D		 4796 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4797
8fb55197 4798 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4799 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4800 if (!IS_CHERRYVIEW(dev_priv))
4801 gen6_set_rps_thresholds(dev_priv, val);
4802 }
ffe02b40 4803
ffe02b40
VS		 4804 dev_priv->rps.cur_freq = val;
4805 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4806}
4807
a7f6e231 4808/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4809 *
4810 * * If Gfx is Idle, then
a7f6e231
D		 4811 * 1. Forcewake Media well.
4812 * 2. Request idle freq.
4813 * 3. Release Forcewake of Media well.
76c3552f
D		 4814*/
4815static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4816{
aed242ff 4817 u32 val = dev_priv->rps.idle_freq;
5549d25f 4818
aed242ff 4819 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4820 return;
4821
a7f6e231
D		 4822 /* Wake up the media well, as that takes a lot less
4823 * power than the Render well. */
4824 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4825 valleyview_set_rps(dev_priv, val);
a7f6e231 4826 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4827}
4828
43cf3bf0
CW		 4829void gen6_rps_busy(struct drm_i915_private *dev_priv)
4830{
4831 mutex_lock(&dev_priv->rps.hw_lock);
4832 if (dev_priv->rps.enabled) {
4833 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4834 gen6_rps_reset_ei(dev_priv);
4835 I915_WRITE(GEN6_PMINTRMSK,
4836 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4837 }
4838 mutex_unlock(&dev_priv->rps.hw_lock);
4839}
4840
b29c19b6
CW		 4841void gen6_rps_idle(struct drm_i915_private *dev_priv)
4842{
4843 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4844 if (dev_priv->rps.enabled) {
dc97997a 4845 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 4846 vlv_set_rps_idle(dev_priv);
7526ed79 4847 else
dc97997a 4848 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 4849 dev_priv->rps.last_adj = 0;
43cf3bf0 4850 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4851 }
8d3afd7d 4852 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4853
8d3afd7d 4854 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4855 while (!list_empty(&dev_priv->rps.clients))
4856 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4857 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4858}
4859
1854d5ca 4860void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4861 struct intel_rps_client *rps,
4862 unsigned long submitted)
b29c19b6 4863{
8d3afd7d
CW		 4864 /* This is intentionally racy! We peek at the state here, then
4865 * validate inside the RPS worker.
4866 */
4867 if (!(dev_priv->mm.busy &&
4868 dev_priv->rps.enabled &&
4869 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4870 return;
43cf3bf0 4871
e61b9958
CW		 4872 /* Force a RPS boost (and don't count it against the client) if
4873 * the GPU is severely congested.
4874 */
d0bc54f2 4875 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4876 rps = NULL;
4877
8d3afd7d
CW		 4878 spin_lock(&dev_priv->rps.client_lock);
4879 if (rps == NULL || list_empty(&rps->link)) {
4880 spin_lock_irq(&dev_priv->irq_lock);
4881 if (dev_priv->rps.interrupts_enabled) {
4882 dev_priv->rps.client_boost = true;
4883 queue_work(dev_priv->wq, &dev_priv->rps.work);
4884 }
4885 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4886
2e1b8730
CW		 4887 if (rps != NULL) {
4888 list_add(&rps->link, &dev_priv->rps.clients);
4889 rps->boosts++;
1854d5ca
CW		 4890 } else
4891 dev_priv->rps.boosts++;
c0951f0c 4892 }
8d3afd7d 4893 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4894}
4895
dc97997a 4896void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 4897{
dc97997a
CW		 4898 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4899 valleyview_set_rps(dev_priv, val);
ffe02b40 4900 else
dc97997a 4901 gen6_set_rps(dev_priv, val);
0a073b84
JB		 4902}
4903
dc97997a 4904static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 4905{
20e49366 4906 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4907 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4908}
4909
dc97997a 4910static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 4911{
2030d684
AG		 4912 I915_WRITE(GEN6_RP_CONTROL, 0);
4913}
4914
dc97997a 4915static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 4916{
d20d4f0c 4917 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4918 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4919 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4920}
4921
dc97997a 4922static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 4923{
38807746
D		 4924 I915_WRITE(GEN6_RC_CONTROL, 0);
4925}
4926
dc97997a 4927static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 4928{
98a2e5f9
D		 4929 /* we're doing forcewake before Disabling RC6,
4930 * This what the BIOS expects when going into suspend */
59bad947 4931 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4932
44fc7d5c 4933 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4934
59bad947 4935 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4936}
4937
dc97997a 4938static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 4939{
dc97997a 4940 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 4941 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4942 mode = GEN6_RC_CTL_RC6_ENABLE;
4943 else
4944 mode = 0;
4945 }
dc97997a 4946 if (HAS_RC6p(dev_priv))
58abf1da 4947 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4948 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4949 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4950 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4951
4952 else
4953 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4954 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4955}
4956
dc97997a 4957static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 4958{
72e96d64 4959 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 4960 bool enable_rc6 = true;
4961 unsigned long rc6_ctx_base;
4962
4963 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4964 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4965 enable_rc6 = false;
4966 }
4967
4968 /*
4969 * The exact context size is not known for BXT, so assume a page size
4970 * for this check.
4971 */
4972 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 4973 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4974 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4975 ggtt->stolen_reserved_size))) {
274008e8
SAK		 4976 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4977 enable_rc6 = false;
4978 }
4979
4980 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4981 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4982 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4983 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4984 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4985 enable_rc6 = false;
4986 }
4987
4988 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4989 GEN6_RC_CTL_HW_ENABLE)) &&
4990 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4991 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4992 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4993 enable_rc6 = false;
4994 }
4995
4996 return enable_rc6;
4997}
4998
dc97997a 4999int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5000{
e7d66d89 5001 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5002 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5003 return 0;
5004
274008e8
SAK		 5005 if (!enable_rc6)
5006 return 0;
5007
dc97997a 5008 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5009 DRM_INFO("RC6 disabled by BIOS\n");
5010 return 0;
5011 }
5012
456470eb 5013 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5014 if (enable_rc6 >= 0) {
5015 int mask;
5016
dc97997a 5017 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5018 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5019 INTEL_RC6pp_ENABLE;
5020 else
5021 mask = INTEL_RC6_ENABLE;
5022
5023 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 5024 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
5025 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5026
5027 return enable_rc6 & mask;
5028 }
2b4e57bd 5029
dc97997a 5030 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5031 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5032
5033 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5034}
5035
dc97997a 5036static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0 5037{
93ee2920
TR		 5038 uint32_t rp_state_cap;
5039 u32 ddcc_status = 0;
5040 int ret;
5041
3280e8b0
BW		 5042 /* All of these values are in units of 50MHz */
5043 dev_priv->rps.cur_freq = 0;
93ee2920 5044 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5045 if (IS_BROXTON(dev_priv)) {
35040562
BP		 5046 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5047 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5048 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5049 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5050 } else {
5051 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5052 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5053 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5054 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5055 }
5056
3280e8b0
BW		 5057 /* hw_max = RP0 until we check for overclocking */
5058 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5059
93ee2920 5060 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5061 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5062 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
93ee2920
TR		 5063 ret = sandybridge_pcode_read(dev_priv,
5064 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5065 &ddcc_status);
5066 if (0 == ret)
5067 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5068 clamp_t(u8,
5069 ((ddcc_status >> 8) & 0xff),
5070 dev_priv->rps.min_freq,
5071 dev_priv->rps.max_freq);
93ee2920
TR		 5072 }
5073
dc97997a 5074 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c
AG		 5075 /* Store the frequency values in 16.66 MHZ units, which is
5076 the natural hardware unit for SKL */
5077 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5078 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5079 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5080 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5081 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5082 }
5083
aed242ff
CW		 5084 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5085
3280e8b0
BW		 5086 /* Preserve min/max settings in case of re-init */
5087 if (dev_priv->rps.max_freq_softlimit == 0)
5088 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5089
93ee2920 5090 if (dev_priv->rps.min_freq_softlimit == 0) {
dc97997a 5091 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
93ee2920 5092 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 5093 max_t(int, dev_priv->rps.efficient_freq,
5094 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 5095 else
5096 dev_priv->rps.min_freq_softlimit =
5097 dev_priv->rps.min_freq;
5098 }
3280e8b0
BW		 5099}
5100
b6fef0ef 5101/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5102static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5103{
b6fef0ef
JB		 5104 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5105
dc97997a 5106 gen6_init_rps_frequencies(dev_priv);
ba1c554c 5107
23eafea6 5108 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5109 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5110 /*
5111 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5112 * clear out the Control register just to avoid inconsitency
5113 * with debugfs interface, which will show Turbo as enabled
5114 * only and that is not expected by the User after adding the
5115 * WaGsvDisableTurbo. Apart from this there is no problem even
5116 * if the Turbo is left enabled in the Control register, as the
5117 * Up/Down interrupts would remain masked.
5118 */
dc97997a 5119 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5120 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5121 return;
5122 }
5123
0beb059a
AG		 5124 /* Program defaults and thresholds for RPS*/
5125 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5126 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5127
5128 /* 1 second timeout*/
5129 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5130 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5131
b6fef0ef 5132 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5133
0beb059a
AG		 5134 /* Leaning on the below call to gen6_set_rps to program/setup the
5135 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5136 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5137 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5138 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
b6fef0ef
JB		 5139
5140 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5141}
5142
dc97997a 5143static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5144{
e2f80391 5145 struct intel_engine_cs *engine;
20e49366 5146 uint32_t rc6_mask = 0;
20e49366
ZW		 5147
5148 /* 1a: Software RC state - RC0 */
5149 I915_WRITE(GEN6_RC_STATE, 0);
5150
5151 /* 1b: Get forcewake during program sequence. Although the driver
5152 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5153 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5154
5155 /* 2a: Disable RC states. */
5156 I915_WRITE(GEN6_RC_CONTROL, 0);
5157
5158 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5159
5160 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5161 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5162 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5163 else
5164 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5165 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5166 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5167 for_each_engine(engine, dev_priv)
e2f80391 5168 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5169
1a3d1898 5170 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5171 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5172
20e49366 5173 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5174
38c23527
ZW		 5175 /* 2c: Program Coarse Power Gating Policies. */
5176 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5177 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5178
20e49366 5179 /* 3a: Enable RC6 */
dc97997a 5180 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5181 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5182 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5183 /* WaRsUseTimeoutMode */
dc97997a
CW		 5184 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5185 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5186 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5187 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5188 GEN7_RC_CTL_TO_MODE |
5189 rc6_mask);
3e7732a0
SAK		 5190 } else {
5191 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5192 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5193 GEN6_RC_CTL_EI_MODE(1) |
5194 rc6_mask);
3e7732a0 5195 }
20e49366 5196
cb07bae0
SK		 5197 /*
5198 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5199 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5200 */
dc97997a 5201 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5202 I915_WRITE(GEN9_PG_ENABLE, 0);
5203 else
5204 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5205 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5206
59bad947 5207 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5208}
5209
dc97997a 5210static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5211{
e2f80391 5212 struct intel_engine_cs *engine;
93ee2920 5213 uint32_t rc6_mask = 0;
6edee7f3
BW		 5214
5215 /* 1a: Software RC state - RC0 */
5216 I915_WRITE(GEN6_RC_STATE, 0);
5217
5218 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5219 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5220 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5221
5222 /* 2a: Disable RC states. */
5223 I915_WRITE(GEN6_RC_CONTROL, 0);
5224
93ee2920 5225 /* Initialize rps frequencies */
dc97997a 5226 gen6_init_rps_frequencies(dev_priv);
6edee7f3
BW		 5227
5228 /* 2b: Program RC6 thresholds.*/
5229 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5230 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5231 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5232 for_each_engine(engine, dev_priv)
e2f80391 5233 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5234 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5235 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5236 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5237 else
5238 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5239
5240 /* 3: Enable RC6 */
dc97997a 5241 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5242 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5243 intel_print_rc6_info(dev_priv, rc6_mask);
5244 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5245 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5246 GEN7_RC_CTL_TO_MODE |
5247 rc6_mask);
5248 else
5249 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5250 GEN6_RC_CTL_EI_MODE(1) |
5251 rc6_mask);
6edee7f3
BW		 5252
5253 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5254 I915_WRITE(GEN6_RPNSWREQ,
5255 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5256 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5257 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5258 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5259 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5260
5261 /* Docs recommend 900MHz, and 300 MHz respectively */
5262 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5263 dev_priv->rps.max_freq_softlimit << 24 |
5264 dev_priv->rps.min_freq_softlimit << 16);
5265
5266 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5267 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5268 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5269 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5270
5271 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5272
5273 /* 5: Enable RPS */
7526ed79
DV		 5274 I915_WRITE(GEN6_RP_CONTROL,
5275 GEN6_RP_MEDIA_TURBO |
5276 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5277 GEN6_RP_MEDIA_IS_GFX |
5278 GEN6_RP_ENABLE |
5279 GEN6_RP_UP_BUSY_AVG |
5280 GEN6_RP_DOWN_IDLE_AVG);
5281
5282 /* 6: Ring frequency + overclocking (our driver does this later */
5283
c7f3153a 5284 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5285 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
7526ed79 5286
59bad947 5287 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5288}
5289
dc97997a 5290static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5291{
e2f80391 5292 struct intel_engine_cs *engine;
d060c169 5293 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5294 u32 gtfifodbg;
2b4e57bd 5295 int rc6_mode;
b4ac5afc 5296 int ret;
2b4e57bd 5297
4fc688ce 5298 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5299
2b4e57bd
ED		 5300 /* Here begins a magic sequence of register writes to enable
5301 * auto-downclocking.
5302 *
5303 * Perhaps there might be some value in exposing these to
5304 * userspace...
5305 */
5306 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5307
5308 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5309 gtfifodbg = I915_READ(GTFIFODBG);
5310 if (gtfifodbg) {
2b4e57bd
ED		 5311 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5312 I915_WRITE(GTFIFODBG, gtfifodbg);
5313 }
5314
59bad947 5315 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5316
93ee2920 5317 /* Initialize rps frequencies */
dc97997a 5318 gen6_init_rps_frequencies(dev_priv);
dd0a1aa1 5319
2b4e57bd
ED		 5320 /* disable the counters and set deterministic thresholds */
5321 I915_WRITE(GEN6_RC_CONTROL, 0);
5322
5323 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5324 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5325 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5326 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5327 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5328
b4ac5afc 5329 for_each_engine(engine, dev_priv)
e2f80391 5330 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5331
5332 I915_WRITE(GEN6_RC_SLEEP, 0);
5333 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5334 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5335 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5336 else
5337 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5338 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5339 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5340
5a7dc92a 5341 /* Check if we are enabling RC6 */
dc97997a 5342 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5343 if (rc6_mode & INTEL_RC6_ENABLE)
5344 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5345
5a7dc92a 5346 /* We don't use those on Haswell */
dc97997a 5347 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5348 if (rc6_mode & INTEL_RC6p_ENABLE)
5349 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5350
5a7dc92a
ED		 5351 if (rc6_mode & INTEL_RC6pp_ENABLE)
5352 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5353 }
2b4e57bd 5354
dc97997a 5355 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5356
5357 I915_WRITE(GEN6_RC_CONTROL,
5358 rc6_mask |
5359 GEN6_RC_CTL_EI_MODE(1) |
5360 GEN6_RC_CTL_HW_ENABLE);
5361
dd75fdc8
CW		 5362 /* Power down if completely idle for over 50ms */
5363 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5364 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5365
42c0526c 5366 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5367 if (ret)
42c0526c 5368 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5369
5370 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5371 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5372 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5373 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5374 (pcu_mbox & 0xff) * 50);
b39fb297 5375 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5376 }
5377
dd75fdc8 5378 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5379 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b4e57bd 5380
31643d54
BW		 5381 rc6vids = 0;
5382 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5383 if (IS_GEN6(dev_priv) && ret) {
31643d54 5384 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5385 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5386 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5387 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5388 rc6vids &= 0xffff00;
5389 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5390 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5391 if (ret)
5392 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5393 }
5394
59bad947 5395 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5396}
5397
dc97997a 5398static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5399{
5400 int min_freq = 15;
3ebecd07
CW		 5401 unsigned int gpu_freq;
5402 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5403 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5404 int scaling_factor = 180;
eda79642 5405 struct cpufreq_policy *policy;
2b4e57bd 5406
4fc688ce 5407 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5408
eda79642
BW		 5409 policy = cpufreq_cpu_get(0);
5410 if (policy) {
5411 max_ia_freq = policy->cpuinfo.max_freq;
5412 cpufreq_cpu_put(policy);
5413 } else {
5414 /*
5415 * Default to measured freq if none found, PCU will ensure we
5416 * don't go over
5417 */
2b4e57bd 5418 max_ia_freq = tsc_khz;
eda79642 5419 }
2b4e57bd
ED		 5420
5421 /* Convert from kHz to MHz */
5422 max_ia_freq /= 1000;
5423
153b4b95 5424 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5425 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5426 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5427
dc97997a 5428 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5429 /* Convert GT frequency to 50 HZ units */
5430 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5431 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5432 } else {
5433 min_gpu_freq = dev_priv->rps.min_freq;
5434 max_gpu_freq = dev_priv->rps.max_freq;
5435 }
5436
2b4e57bd
ED		 5437 /*
5438 * For each potential GPU frequency, load a ring frequency we'd like
5439 * to use for memory access. We do this by specifying the IA frequency
5440 * the PCU should use as a reference to determine the ring frequency.
5441 */
4c8c7743
AG		 5442 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5443 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5444 unsigned int ia_freq = 0, ring_freq = 0;
5445
dc97997a 5446 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5447 /*
5448 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5449 * No floor required for ring frequency on SKL.
5450 */
5451 ring_freq = gpu_freq;
dc97997a 5452 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5453 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5454 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5455 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5456 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5457 ring_freq = max(min_ring_freq, ring_freq);
5458 /* leave ia_freq as the default, chosen by cpufreq */
5459 } else {
5460 /* On older processors, there is no separate ring
5461 * clock domain, so in order to boost the bandwidth
5462 * of the ring, we need to upclock the CPU (ia_freq).
5463 *
5464 * For GPU frequencies less than 750MHz,
5465 * just use the lowest ring freq.
5466 */
5467 if (gpu_freq < min_freq)
5468 ia_freq = 800;
5469 else
5470 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5471 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5472 }
2b4e57bd 5473
42c0526c
BW		 5474 sandybridge_pcode_write(dev_priv,
5475 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5476 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5477 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5478 gpu_freq);
2b4e57bd 5479 }
2b4e57bd
ED		 5480}
5481
dc97997a 5482void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
c2bc2fc5 5483{
dc97997a 5484 if (!HAS_CORE_RING_FREQ(dev_priv))
c2bc2fc5
ID		 5485 return;
5486
5487 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a 5488 __gen6_update_ring_freq(dev_priv);
c2bc2fc5
ID		 5489 mutex_unlock(&dev_priv->rps.hw_lock);
5490}
5491
03af2045 5492static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5493{
5494 u32 val, rp0;
5495
5b5929cb 5496 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5497
dc97997a 5498 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5499 case 8:
5500 /* (2 * 4) config */
5501 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5502 break;
5503 case 12:
5504 /* (2 * 6) config */
5505 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5506 break;
5507 case 16:
5508 /* (2 * 8) config */
5509 default:
5510 /* Setting (2 * 8) Min RP0 for any other combination */
5511 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5512 break;
095acd5f 5513 }
5b5929cb
JN		 5514
5515 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5516
2b6b3a09
D		 5517 return rp0;
5518}
5519
5520static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5521{
5522 u32 val, rpe;
5523
5524 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5525 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5526
5527 return rpe;
5528}
5529
7707df4a
D		 5530static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5531{
5532 u32 val, rp1;
5533
5b5929cb
JN		 5534 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5535 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5536
7707df4a
D		 5537 return rp1;
5538}
5539
f8f2b001
D		 5540static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5541{
5542 u32 val, rp1;
5543
5544 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5545
5546 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5547
5548 return rp1;
5549}
5550
03af2045 5551static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5552{
5553 u32 val, rp0;
5554
64936258 5555 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5556
5557 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5558 /* Clamp to max */
5559 rp0 = min_t(u32, rp0, 0xea);
5560
5561 return rp0;
5562}
5563
5564static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5565{
5566 u32 val, rpe;
5567
64936258 5568 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5569 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5570 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5571 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5572
5573 return rpe;
5574}
5575
03af2045 5576static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5577{
36146035
ID		 5578 u32 val;
5579
5580 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5581 /*
5582 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5583 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5584 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5585 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5586 * to make sure it matches what Punit accepts.
5587 */
5588 return max_t(u32, val, 0xc0);
0a073b84
JB		 5589}
5590
ae48434c
ID		 5591/* Check that the pctx buffer wasn't move under us. */
5592static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5593{
5594 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5595
5596 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5597 dev_priv->vlv_pctx->stolen->start);
5598}
5599
38807746
D		 5600
5601/* Check that the pcbr address is not empty. */
5602static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5603{
5604 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5605
5606 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5607}
5608
dc97997a 5609static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5610{
62106b4f 5611 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5612 unsigned long pctx_paddr, paddr;
38807746
D		 5613 u32 pcbr;
5614 int pctx_size = 32*1024;
5615
38807746
D		 5616 pcbr = I915_READ(VLV_PCBR);
5617 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5618 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5619 paddr = (dev_priv->mm.stolen_base +
62106b4f 5620 (ggtt->stolen_size - pctx_size));
38807746
D		 5621
5622 pctx_paddr = (paddr & (~4095));
5623 I915_WRITE(VLV_PCBR, pctx_paddr);
5624 }
ce611ef8
VS		 5625
5626 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5627}
5628
dc97997a 5629static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5630{
c9cddffc
JB		 5631 struct drm_i915_gem_object *pctx;
5632 unsigned long pctx_paddr;
5633 u32 pcbr;
5634 int pctx_size = 24*1024;
5635
dc97997a 5636 mutex_lock(&dev_priv->dev->struct_mutex);
17b0c1f7 5637
c9cddffc
JB		 5638 pcbr = I915_READ(VLV_PCBR);
5639 if (pcbr) {
5640 /* BIOS set it up already, grab the pre-alloc'd space */
5641 int pcbr_offset;
5642
5643 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5644 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5645 pcbr_offset,
190d6cd5 5646 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5647 pctx_size);
5648 goto out;
5649 }
5650
ce611ef8
VS		 5651 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5652
c9cddffc
JB		 5653 /*
5654 * From the Gunit register HAS:
5655 * The Gfx driver is expected to program this register and ensure
5656 * proper allocation within Gfx stolen memory. For example, this
5657 * register should be programmed such than the PCBR range does not
5658 * overlap with other ranges, such as the frame buffer, protected
5659 * memory, or any other relevant ranges.
5660 */
dc97997a 5661 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
c9cddffc
JB		 5662 if (!pctx) {
5663 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5664 goto out;
c9cddffc
JB		 5665 }
5666
5667 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5668 I915_WRITE(VLV_PCBR, pctx_paddr);
5669
5670out:
ce611ef8 5671 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5672 dev_priv->vlv_pctx = pctx;
dc97997a 5673 mutex_unlock(&dev_priv->dev->struct_mutex);
c9cddffc
JB		 5674}
5675
dc97997a 5676static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5677{
ae48434c
ID		 5678 if (WARN_ON(!dev_priv->vlv_pctx))
5679 return;
5680
ee504898 5681 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5682 dev_priv->vlv_pctx = NULL;
5683}
5684
c30fec65
VS		 5685static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5686{
5687 dev_priv->rps.gpll_ref_freq =
5688 vlv_get_cck_clock(dev_priv, "GPLL ref",
5689 CCK_GPLL_CLOCK_CONTROL,
5690 dev_priv->czclk_freq);
5691
5692 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5693 dev_priv->rps.gpll_ref_freq);
5694}
5695
dc97997a 5696static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5697{
2bb25c17 5698 u32 val;
4e80519e 5699
dc97997a 5700 valleyview_setup_pctx(dev_priv);
4e80519e 5701
c30fec65
VS		 5702 vlv_init_gpll_ref_freq(dev_priv);
5703
4e80519e
ID		 5704 mutex_lock(&dev_priv->rps.hw_lock);
5705
2bb25c17
VS		 5706 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5707 switch ((val >> 6) & 3) {
5708 case 0:
5709 case 1:
5710 dev_priv->mem_freq = 800;
5711 break;
5712 case 2:
5713 dev_priv->mem_freq = 1066;
5714 break;
5715 case 3:
5716 dev_priv->mem_freq = 1333;
5717 break;
5718 }
80b83b62 5719 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5720
4e80519e
ID		 5721 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5722 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5723 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5724 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5725 dev_priv->rps.max_freq);
5726
5727 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5728 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5729 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5730 dev_priv->rps.efficient_freq);
5731
f8f2b001
D		 5732 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5733 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5734 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5735 dev_priv->rps.rp1_freq);
5736
4e80519e
ID		 5737 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5738 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5739 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5740 dev_priv->rps.min_freq);
5741
aed242ff
CW		 5742 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5743
4e80519e
ID		 5744 /* Preserve min/max settings in case of re-init */
5745 if (dev_priv->rps.max_freq_softlimit == 0)
5746 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5747
5748 if (dev_priv->rps.min_freq_softlimit == 0)
5749 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5750
5751 mutex_unlock(&dev_priv->rps.hw_lock);
5752}
5753
dc97997a 5754static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5755{
2bb25c17 5756 u32 val;
2b6b3a09 5757
dc97997a 5758 cherryview_setup_pctx(dev_priv);
2b6b3a09 5759
c30fec65
VS		 5760 vlv_init_gpll_ref_freq(dev_priv);
5761
2b6b3a09
D		 5762 mutex_lock(&dev_priv->rps.hw_lock);
5763
a580516d 5764 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5765 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5766 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5767
2bb25c17 5768 switch ((val >> 2) & 0x7) {
2bb25c17 5769 case 3:
2bb25c17
VS		 5770 dev_priv->mem_freq = 2000;
5771 break;
bfa7df01 5772 default:
2bb25c17
VS		 5773 dev_priv->mem_freq = 1600;
5774 break;
5775 }
80b83b62 5776 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5777
2b6b3a09
D		 5778 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5779 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5780 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5781 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5782 dev_priv->rps.max_freq);
5783
5784 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5785 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5786 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5787 dev_priv->rps.efficient_freq);
5788
7707df4a
D		 5789 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5790 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5791 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5792 dev_priv->rps.rp1_freq);
5793
5b7c91b7
D		 5794 /* PUnit validated range is only [RPe, RP0] */
5795 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5796 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5797 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5798 dev_priv->rps.min_freq);
5799
1c14762d
VS		 5800 WARN_ONCE((dev_priv->rps.max_freq |
5801 dev_priv->rps.efficient_freq |
5802 dev_priv->rps.rp1_freq |
5803 dev_priv->rps.min_freq) & 1,
5804 "Odd GPU freq values\n");
5805
aed242ff
CW		 5806 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5807
2b6b3a09
D		 5808 /* Preserve min/max settings in case of re-init */
5809 if (dev_priv->rps.max_freq_softlimit == 0)
5810 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5811
5812 if (dev_priv->rps.min_freq_softlimit == 0)
5813 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5814
5815 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5816}
5817
dc97997a 5818static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5819{
dc97997a 5820 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5821}
5822
dc97997a 5823static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5824{
e2f80391 5825 struct intel_engine_cs *engine;
2b6b3a09 5826 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5827
5828 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5829
297b32ec
VS		 5830 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5831 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5832 if (gtfifodbg) {
5833 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5834 gtfifodbg);
5835 I915_WRITE(GTFIFODBG, gtfifodbg);
5836 }
5837
5838 cherryview_check_pctx(dev_priv);
5839
5840 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5841 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5842 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5843
160614a2
VS		 5844 /* Disable RC states. */
5845 I915_WRITE(GEN6_RC_CONTROL, 0);
5846
38807746
D		 5847 /* 2a: Program RC6 thresholds.*/
5848 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5849 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5850 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5851
b4ac5afc 5852 for_each_engine(engine, dev_priv)
e2f80391 5853 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5854 I915_WRITE(GEN6_RC_SLEEP, 0);
5855
f4f71c7d
D		 5856 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5857 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5858
5859 /* allows RC6 residency counter to work */
5860 I915_WRITE(VLV_COUNTER_CONTROL,
5861 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5862 VLV_MEDIA_RC6_COUNT_EN |
5863 VLV_RENDER_RC6_COUNT_EN));
5864
5865 /* For now we assume BIOS is allocating and populating the PCBR */
5866 pcbr = I915_READ(VLV_PCBR);
5867
38807746 5868 /* 3: Enable RC6 */
dc97997a
CW		 5869 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5870 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5871 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5872
5873 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5874
2b6b3a09 5875 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5876 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5877 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5878 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5879 I915_WRITE(GEN6_RP_UP_EI, 66000);
5880 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5881
5882 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5883
5884 /* 5: Enable RPS */
5885 I915_WRITE(GEN6_RP_CONTROL,
5886 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5887 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5888 GEN6_RP_ENABLE |
5889 GEN6_RP_UP_BUSY_AVG |
5890 GEN6_RP_DOWN_IDLE_AVG);
5891
3ef62342
D		 5892 /* Setting Fixed Bias */
5893 val = VLV_OVERRIDE_EN |
5894 VLV_SOC_TDP_EN |
5895 CHV_BIAS_CPU_50_SOC_50;
5896 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5897
2b6b3a09
D		 5898 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5899
8d40c3ae
VS		 5900 /* RPS code assumes GPLL is used */
5901 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5902
742f491d 5903 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5904 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5905
5906 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5907 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5908 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5909 dev_priv->rps.cur_freq);
5910
5911 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5912 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5913 dev_priv->rps.idle_freq);
2b6b3a09 5914
dc97997a 5915 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b6b3a09 5916
59bad947 5917 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5918}
5919
dc97997a 5920static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 5921{
e2f80391 5922 struct intel_engine_cs *engine;
2a5913a8 5923 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5924
5925 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5926
ae48434c
ID		 5927 valleyview_check_pctx(dev_priv);
5928
297b32ec
VS		 5929 gtfifodbg = I915_READ(GTFIFODBG);
5930 if (gtfifodbg) {
f7d85c1e
JB		 5931 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5932 gtfifodbg);
0a073b84
JB		 5933 I915_WRITE(GTFIFODBG, gtfifodbg);
5934 }
5935
c8d9a590 5936 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5937 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5938
160614a2
VS		 5939 /* Disable RC states. */
5940 I915_WRITE(GEN6_RC_CONTROL, 0);
5941
cad725fe 5942 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5943 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5944 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5945 I915_WRITE(GEN6_RP_UP_EI, 66000);
5946 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5947
5948 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5949
5950 I915_WRITE(GEN6_RP_CONTROL,
5951 GEN6_RP_MEDIA_TURBO |
5952 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5953 GEN6_RP_MEDIA_IS_GFX |
5954 GEN6_RP_ENABLE |
5955 GEN6_RP_UP_BUSY_AVG |
5956 GEN6_RP_DOWN_IDLE_CONT);
5957
5958 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5959 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5960 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5961
b4ac5afc 5962 for_each_engine(engine, dev_priv)
e2f80391 5963 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5964
2f0aa304 5965 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5966
5967 /* allows RC6 residency counter to work */
49798eb2 5968 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5969 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5970 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5971 VLV_MEDIA_RC6_COUNT_EN |
5972 VLV_RENDER_RC6_COUNT_EN));
31685c25 5973
dc97997a 5974 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 5975 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 5976
dc97997a 5977 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 5978
a2b23fe0 5979 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5980
3ef62342
D		 5981 /* Setting Fixed Bias */
5982 val = VLV_OVERRIDE_EN |
5983 VLV_SOC_TDP_EN |
5984 VLV_BIAS_CPU_125_SOC_875;
5985 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5986
64936258 5987 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5988
8d40c3ae
VS		 5989 /* RPS code assumes GPLL is used */
5990 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5991
742f491d 5992 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5993 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5994
b39fb297 5995 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5996 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5997 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5998 dev_priv->rps.cur_freq);
0a073b84 5999
73008b98 6000 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 6001 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
6002 dev_priv->rps.idle_freq);
0a073b84 6003
dc97997a 6004 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
0a073b84 6005
59bad947 6006 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6007}
6008
dde18883
ED		 6009static unsigned long intel_pxfreq(u32 vidfreq)
6010{
6011 unsigned long freq;
6012 int div = (vidfreq & 0x3f0000) >> 16;
6013 int post = (vidfreq & 0x3000) >> 12;
6014 int pre = (vidfreq & 0x7);
6015
6016 if (!pre)
6017 return 0;
6018
6019 freq = ((div * 133333) / ((1<<post) * pre));
6020
6021 return freq;
6022}
6023
eb48eb00
DV		 6024static const struct cparams {
6025 u16 i;
6026 u16 t;
6027 u16 m;
6028 u16 c;
6029} cparams[] = {
6030 { 1, 1333, 301, 28664 },
6031 { 1, 1066, 294, 24460 },
6032 { 1, 800, 294, 25192 },
6033 { 0, 1333, 276, 27605 },
6034 { 0, 1066, 276, 27605 },
6035 { 0, 800, 231, 23784 },
6036};
6037
f531dcb2 6038static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6039{
6040 u64 total_count, diff, ret;
6041 u32 count1, count2, count3, m = 0, c = 0;
6042 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6043 int i;
6044
02d71956
DV		 6045 assert_spin_locked(&mchdev_lock);
6046
20e4d407 6047 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6048
6049 /* Prevent division-by-zero if we are asking too fast.
6050 * Also, we don't get interesting results if we are polling
6051 * faster than once in 10ms, so just return the saved value
6052 * in such cases.
6053 */
6054 if (diff1 <= 10)
20e4d407 6055 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6056
6057 count1 = I915_READ(DMIEC);
6058 count2 = I915_READ(DDREC);
6059 count3 = I915_READ(CSIEC);
6060
6061 total_count = count1 + count2 + count3;
6062
6063 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6064 if (total_count < dev_priv->ips.last_count1) {
6065 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6066 diff += total_count;
6067 } else {
20e4d407 6068 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6069 }
6070
6071 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6072 if (cparams[i].i == dev_priv->ips.c_m &&
6073 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6074 m = cparams[i].m;
6075 c = cparams[i].c;
6076 break;
6077 }
6078 }
6079
6080 diff = div_u64(diff, diff1);
6081 ret = ((m * diff) + c);
6082 ret = div_u64(ret, 10);
6083
20e4d407
DV		 6084 dev_priv->ips.last_count1 = total_count;
6085 dev_priv->ips.last_time1 = now;
eb48eb00 6086
20e4d407 6087 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6088
6089 return ret;
6090}
6091
f531dcb2
CW		 6092unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6093{
6094 unsigned long val;
6095
dc97997a 6096 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6097 return 0;
6098
6099 spin_lock_irq(&mchdev_lock);
6100
6101 val = __i915_chipset_val(dev_priv);
6102
6103 spin_unlock_irq(&mchdev_lock);
6104
6105 return val;
6106}
6107
eb48eb00
DV		 6108unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6109{
6110 unsigned long m, x, b;
6111 u32 tsfs;
6112
6113 tsfs = I915_READ(TSFS);
6114
6115 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6116 x = I915_READ8(TR1);
6117
6118 b = tsfs & TSFS_INTR_MASK;
6119
6120 return ((m * x) / 127) - b;
6121}
6122
d972d6ee
MK		 6123static int _pxvid_to_vd(u8 pxvid)
6124{
6125 if (pxvid == 0)
6126 return 0;
6127
6128 if (pxvid >= 8 && pxvid < 31)
6129 pxvid = 31;
6130
6131 return (pxvid + 2) * 125;
6132}
6133
6134static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6135{
d972d6ee
MK		 6136 const int vd = _pxvid_to_vd(pxvid);
6137 const int vm = vd - 1125;
6138
dc97997a 6139 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6140 return vm > 0 ? vm : 0;
6141
6142 return vd;
eb48eb00
DV		 6143}
6144
02d71956 6145static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6146{
5ed0bdf2 6147 u64 now, diff, diffms;
eb48eb00
DV		 6148 u32 count;
6149
02d71956 6150 assert_spin_locked(&mchdev_lock);
eb48eb00 6151
5ed0bdf2
TG		 6152 now = ktime_get_raw_ns();
6153 diffms = now - dev_priv->ips.last_time2;
6154 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6155
6156 /* Don't divide by 0 */
eb48eb00
DV		 6157 if (!diffms)
6158 return;
6159
6160 count = I915_READ(GFXEC);
6161
20e4d407
DV		 6162 if (count < dev_priv->ips.last_count2) {
6163 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6164 diff += count;
6165 } else {
20e4d407 6166 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6167 }
6168
20e4d407
DV		 6169 dev_priv->ips.last_count2 = count;
6170 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6171
6172 /* More magic constants... */
6173 diff = diff * 1181;
6174 diff = div_u64(diff, diffms * 10);
20e4d407 6175 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6176}
6177
02d71956
DV		 6178void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6179{
dc97997a 6180 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6181 return;
6182
9270388e 6183 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6184
6185 __i915_update_gfx_val(dev_priv);
6186
9270388e 6187 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6188}
6189
f531dcb2 6190static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6191{
6192 unsigned long t, corr, state1, corr2, state2;
6193 u32 pxvid, ext_v;
6194
02d71956
DV		 6195 assert_spin_locked(&mchdev_lock);
6196
616847e7 6197 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6198 pxvid = (pxvid >> 24) & 0x7f;
6199 ext_v = pvid_to_extvid(dev_priv, pxvid);
6200
6201 state1 = ext_v;
6202
6203 t = i915_mch_val(dev_priv);
6204
6205 /* Revel in the empirically derived constants */
6206
6207 /* Correction factor in 1/100000 units */
6208 if (t > 80)
6209 corr = ((t * 2349) + 135940);
6210 else if (t >= 50)
6211 corr = ((t * 964) + 29317);
6212 else /* < 50 */
6213 corr = ((t * 301) + 1004);
6214
6215 corr = corr * ((150142 * state1) / 10000 - 78642);
6216 corr /= 100000;
20e4d407 6217 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6218
6219 state2 = (corr2 * state1) / 10000;
6220 state2 /= 100; /* convert to mW */
6221
02d71956 6222 __i915_update_gfx_val(dev_priv);
eb48eb00 6223
20e4d407 6224 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6225}
6226
f531dcb2
CW		 6227unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6228{
6229 unsigned long val;
6230
dc97997a 6231 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6232 return 0;
6233
6234 spin_lock_irq(&mchdev_lock);
6235
6236 val = __i915_gfx_val(dev_priv);
6237
6238 spin_unlock_irq(&mchdev_lock);
6239
6240 return val;
6241}
6242
eb48eb00
DV		 6243/**
6244 * i915_read_mch_val - return value for IPS use
6245 *
6246 * Calculate and return a value for the IPS driver to use when deciding whether
6247 * we have thermal and power headroom to increase CPU or GPU power budget.
6248 */
6249unsigned long i915_read_mch_val(void)
6250{
6251 struct drm_i915_private *dev_priv;
6252 unsigned long chipset_val, graphics_val, ret = 0;
6253
9270388e 6254 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6255 if (!i915_mch_dev)
6256 goto out_unlock;
6257 dev_priv = i915_mch_dev;
6258
f531dcb2
CW		 6259 chipset_val = __i915_chipset_val(dev_priv);
6260 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6261
6262 ret = chipset_val + graphics_val;
6263
6264out_unlock:
9270388e 6265 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6266
6267 return ret;
6268}
6269EXPORT_SYMBOL_GPL(i915_read_mch_val);
6270
6271/**
6272 * i915_gpu_raise - raise GPU frequency limit
6273 *
6274 * Raise the limit; IPS indicates we have thermal headroom.
6275 */
6276bool i915_gpu_raise(void)
6277{
6278 struct drm_i915_private *dev_priv;
6279 bool ret = true;
6280
9270388e 6281 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6282 if (!i915_mch_dev) {
6283 ret = false;
6284 goto out_unlock;
6285 }
6286 dev_priv = i915_mch_dev;
6287
20e4d407
DV		 6288 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6289 dev_priv->ips.max_delay--;
eb48eb00
DV		 6290
6291out_unlock:
9270388e 6292 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6293
6294 return ret;
6295}
6296EXPORT_SYMBOL_GPL(i915_gpu_raise);
6297
6298/**
6299 * i915_gpu_lower - lower GPU frequency limit
6300 *
6301 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6302 * frequency maximum.
6303 */
6304bool i915_gpu_lower(void)
6305{
6306 struct drm_i915_private *dev_priv;
6307 bool ret = true;
6308
9270388e 6309 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6310 if (!i915_mch_dev) {
6311 ret = false;
6312 goto out_unlock;
6313 }
6314 dev_priv = i915_mch_dev;
6315
20e4d407
DV		 6316 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6317 dev_priv->ips.max_delay++;
eb48eb00
DV		 6318
6319out_unlock:
9270388e 6320 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6321
6322 return ret;
6323}
6324EXPORT_SYMBOL_GPL(i915_gpu_lower);
6325
6326/**
6327 * i915_gpu_busy - indicate GPU business to IPS
6328 *
6329 * Tell the IPS driver whether or not the GPU is busy.
6330 */
6331bool i915_gpu_busy(void)
6332{
6333 struct drm_i915_private *dev_priv;
e2f80391 6334 struct intel_engine_cs *engine;
eb48eb00
DV		 6335 bool ret = false;
6336
9270388e 6337 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6338 if (!i915_mch_dev)
6339 goto out_unlock;
6340 dev_priv = i915_mch_dev;
6341
b4ac5afc 6342 for_each_engine(engine, dev_priv)
e2f80391 6343 ret |= !list_empty(&engine->request_list);
eb48eb00
DV		 6344
6345out_unlock:
9270388e 6346 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6347
6348 return ret;
6349}
6350EXPORT_SYMBOL_GPL(i915_gpu_busy);
6351
6352/**
6353 * i915_gpu_turbo_disable - disable graphics turbo
6354 *
6355 * Disable graphics turbo by resetting the max frequency and setting the
6356 * current frequency to the default.
6357 */
6358bool i915_gpu_turbo_disable(void)
6359{
6360 struct drm_i915_private *dev_priv;
6361 bool ret = true;
6362
9270388e 6363 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6364 if (!i915_mch_dev) {
6365 ret = false;
6366 goto out_unlock;
6367 }
6368 dev_priv = i915_mch_dev;
6369
20e4d407 6370 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6371
91d14251 6372 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6373 ret = false;
6374
6375out_unlock:
9270388e 6376 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6377
6378 return ret;
6379}
6380EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6381
6382/**
6383 * Tells the intel_ips driver that the i915 driver is now loaded, if
6384 * IPS got loaded first.
6385 *
6386 * This awkward dance is so that neither module has to depend on the
6387 * other in order for IPS to do the appropriate communication of
6388 * GPU turbo limits to i915.
6389 */
6390static void
6391ips_ping_for_i915_load(void)
6392{
6393 void (*link)(void);
6394
6395 link = symbol_get(ips_link_to_i915_driver);
6396 if (link) {
6397 link();
6398 symbol_put(ips_link_to_i915_driver);
6399 }
6400}
6401
6402void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6403{
02d71956
DV		 6404 /* We only register the i915 ips part with intel-ips once everything is
6405 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6406 spin_lock_irq(&mchdev_lock);
eb48eb00 6407 i915_mch_dev = dev_priv;
9270388e 6408 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6409
6410 ips_ping_for_i915_load();
6411}
6412
6413void intel_gpu_ips_teardown(void)
6414{
9270388e 6415 spin_lock_irq(&mchdev_lock);
eb48eb00 6416 i915_mch_dev = NULL;
9270388e 6417 spin_unlock_irq(&mchdev_lock);
eb48eb00 6418}
76c3552f 6419
dc97997a 6420static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6421{
dde18883
ED		 6422 u32 lcfuse;
6423 u8 pxw[16];
6424 int i;
6425
6426 /* Disable to program */
6427 I915_WRITE(ECR, 0);
6428 POSTING_READ(ECR);
6429
6430 /* Program energy weights for various events */
6431 I915_WRITE(SDEW, 0x15040d00);
6432 I915_WRITE(CSIEW0, 0x007f0000);
6433 I915_WRITE(CSIEW1, 0x1e220004);
6434 I915_WRITE(CSIEW2, 0x04000004);
6435
6436 for (i = 0; i < 5; i++)
616847e7 6437 I915_WRITE(PEW(i), 0);
dde18883 6438 for (i = 0; i < 3; i++)
616847e7 6439 I915_WRITE(DEW(i), 0);
dde18883
ED		 6440
6441 /* Program P-state weights to account for frequency power adjustment */
6442 for (i = 0; i < 16; i++) {
616847e7 6443 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6444 unsigned long freq = intel_pxfreq(pxvidfreq);
6445 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6446 PXVFREQ_PX_SHIFT;
6447 unsigned long val;
6448
6449 val = vid * vid;
6450 val *= (freq / 1000);
6451 val *= 255;
6452 val /= (127*127*900);
6453 if (val > 0xff)
6454 DRM_ERROR("bad pxval: %ld\n", val);
6455 pxw[i] = val;
6456 }
6457 /* Render standby states get 0 weight */
6458 pxw[14] = 0;
6459 pxw[15] = 0;
6460
6461 for (i = 0; i < 4; i++) {
6462 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6463 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6464 I915_WRITE(PXW(i), val);
dde18883
ED		 6465 }
6466
6467 /* Adjust magic regs to magic values (more experimental results) */
6468 I915_WRITE(OGW0, 0);
6469 I915_WRITE(OGW1, 0);
6470 I915_WRITE(EG0, 0x00007f00);
6471 I915_WRITE(EG1, 0x0000000e);
6472 I915_WRITE(EG2, 0x000e0000);
6473 I915_WRITE(EG3, 0x68000300);
6474 I915_WRITE(EG4, 0x42000000);
6475 I915_WRITE(EG5, 0x00140031);
6476 I915_WRITE(EG6, 0);
6477 I915_WRITE(EG7, 0);
6478
6479 for (i = 0; i < 8; i++)
616847e7 6480 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6481
6482 /* Enable PMON + select events */
6483 I915_WRITE(ECR, 0x80000019);
6484
6485 lcfuse = I915_READ(LCFUSE02);
6486
20e4d407 6487 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6488}
6489
dc97997a 6490void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6491{
b268c699
ID		 6492 /*
6493 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6494 * requirement.
6495 */
6496 if (!i915.enable_rc6) {
6497 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6498 intel_runtime_pm_get(dev_priv);
6499 }
e6069ca8 6500
dc97997a
CW		 6501 if (IS_CHERRYVIEW(dev_priv))
6502 cherryview_init_gt_powersave(dev_priv);
6503 else if (IS_VALLEYVIEW(dev_priv))
6504 valleyview_init_gt_powersave(dev_priv);
ae48434c
ID		 6505}
6506
dc97997a 6507void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6508{
dc97997a 6509 if (IS_CHERRYVIEW(dev_priv))
38807746 6510 return;
dc97997a
CW		 6511 else if (IS_VALLEYVIEW(dev_priv))
6512 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6513
6514 if (!i915.enable_rc6)
6515 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6516}
6517
91d14251 6518static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
dbea3cea 6519{
dbea3cea
ID		 6520 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6521
91d14251 6522 gen6_disable_rps_interrupts(dev_priv);
dbea3cea
ID		 6523}
6524
156c7ca0
JB		 6525/**
6526 * intel_suspend_gt_powersave - suspend PM work and helper threads
dc97997a 6527 * @dev_priv: i915 device
156c7ca0
JB		 6528 *
6529 * We don't want to disable RC6 or other features here, we just want
6530 * to make sure any work we've queued has finished and won't bother
6531 * us while we're suspended.
6532 */
dc97997a 6533void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
156c7ca0 6534{
91d14251 6535 if (INTEL_GEN(dev_priv) < 6)
d4d70aa5
ID		 6536 return;
6537
91d14251 6538 gen6_suspend_rps(dev_priv);
b47adc17
D		 6539
6540 /* Force GPU to min freq during suspend */
6541 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6542}
6543
dc97997a 6544void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6545{
dc97997a 6546 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6547 ironlake_disable_drps(dev_priv);
dc97997a
CW		 6548 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6549 intel_suspend_gt_powersave(dev_priv);
e494837a 6550
4fc688ce 6551 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6552 if (INTEL_INFO(dev_priv)->gen >= 9) {
6553 gen9_disable_rc6(dev_priv);
6554 gen9_disable_rps(dev_priv);
6555 } else if (IS_CHERRYVIEW(dev_priv))
6556 cherryview_disable_rps(dev_priv);
6557 else if (IS_VALLEYVIEW(dev_priv))
6558 valleyview_disable_rps(dev_priv);
d20d4f0c 6559 else
dc97997a 6560 gen6_disable_rps(dev_priv);
e534770a 6561
c0951f0c 6562 dev_priv->rps.enabled = false;
4fc688ce 6563 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6564 }
8090c6b9
DV		 6565}
6566
1a01ab3b
JB		 6567static void intel_gen6_powersave_work(struct work_struct *work)
6568{
6569 struct drm_i915_private *dev_priv =
6570 container_of(work, struct drm_i915_private,
6571 rps.delayed_resume_work.work);
1a01ab3b 6572
4fc688ce 6573 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6574
dc97997a
CW		 6575 gen6_reset_rps_interrupts(dev_priv);
6576
6577 if (IS_CHERRYVIEW(dev_priv)) {
6578 cherryview_enable_rps(dev_priv);
6579 } else if (IS_VALLEYVIEW(dev_priv)) {
6580 valleyview_enable_rps(dev_priv);
6581 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6582 gen9_enable_rc6(dev_priv);
6583 gen9_enable_rps(dev_priv);
6584 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6585 __gen6_update_ring_freq(dev_priv);
6586 } else if (IS_BROADWELL(dev_priv)) {
6587 gen8_enable_rps(dev_priv);
6588 __gen6_update_ring_freq(dev_priv);
0a073b84 6589 } else {
dc97997a
CW		 6590 gen6_enable_rps(dev_priv);
6591 __gen6_update_ring_freq(dev_priv);
0a073b84 6592 }
aed242ff
CW		 6593
6594 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6595 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6596
6597 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6598 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6599
c0951f0c 6600 dev_priv->rps.enabled = true;
3cc134e3 6601
91d14251 6602 gen6_enable_rps_interrupts(dev_priv);
3cc134e3 6603
4fc688ce 6604 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6605
6606 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6607}
6608
dc97997a 6609void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6610{
f61018b1 6611 /* Powersaving is controlled by the host when inside a VM */
c033666a 6612 if (intel_vgpu_active(dev_priv))
f61018b1
YZ		 6613 return;
6614
dc97997a 6615 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6616 ironlake_enable_drps(dev_priv);
dc97997a
CW		 6617 mutex_lock(&dev_priv->dev->struct_mutex);
6618 intel_init_emon(dev_priv);
6619 mutex_unlock(&dev_priv->dev->struct_mutex);
6620 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
1a01ab3b
JB		 6621 /*
6622 * PCU communication is slow and this doesn't need to be
6623 * done at any specific time, so do this out of our fast path
6624 * to make resume and init faster.
c6df39b5
ID		 6625 *
6626 * We depend on the HW RC6 power context save/restore
6627 * mechanism when entering D3 through runtime PM suspend. So
6628 * disable RPM until RPS/RC6 is properly setup. We can only
6629 * get here via the driver load/system resume/runtime resume
6630 * paths, so the _noresume version is enough (and in case of
6631 * runtime resume it's necessary).
1a01ab3b 6632 */
c6df39b5
ID		 6633 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6634 round_jiffies_up_relative(HZ)))
6635 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6636 }
6637}
6638
dc97997a 6639void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
c6df39b5 6640{
dc97997a 6641 if (INTEL_INFO(dev_priv)->gen < 6)
dbea3cea
ID		 6642 return;
6643
91d14251 6644 gen6_suspend_rps(dev_priv);
c6df39b5 6645 dev_priv->rps.enabled = false;
c6df39b5
ID		 6646}
6647
3107bd48
DV		 6648static void ibx_init_clock_gating(struct drm_device *dev)
6649{
6650 struct drm_i915_private *dev_priv = dev->dev_private;
6651
6652 /*
6653 * On Ibex Peak and Cougar Point, we need to disable clock
6654 * gating for the panel power sequencer or it will fail to
6655 * start up when no ports are active.
6656 */
6657 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6658}
6659
0e088b8f
VS		 6660static void g4x_disable_trickle_feed(struct drm_device *dev)
6661{
6662 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6663 enum pipe pipe;
0e088b8f 6664
055e393f 6665 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6666 I915_WRITE(DSPCNTR(pipe),
6667 I915_READ(DSPCNTR(pipe)) |
6668 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6669
6670 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6671 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6672 }
6673}
6674
017636cc
VS		 6675static void ilk_init_lp_watermarks(struct drm_device *dev)
6676{
6677 struct drm_i915_private *dev_priv = dev->dev_private;
6678
6679 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6680 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6681 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6682
6683 /*
6684 * Don't touch WM1S_LP_EN here.
6685 * Doing so could cause underruns.
6686 */
6687}
6688
1fa61106 6689static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6690{
6691 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6692 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6693
f1e8fa56
DL		 6694 /*
6695 * Required for FBC
6696 * WaFbcDisableDpfcClockGating:ilk
6697 */
4d47e4f5
DL		 6698 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6699 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6700 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6701
6702 I915_WRITE(PCH_3DCGDIS0,
6703 MARIUNIT_CLOCK_GATE_DISABLE |
6704 SVSMUNIT_CLOCK_GATE_DISABLE);
6705 I915_WRITE(PCH_3DCGDIS1,
6706 VFMUNIT_CLOCK_GATE_DISABLE);
6707
6f1d69b0
ED		 6708 /*
6709 * According to the spec the following bits should be set in
6710 * order to enable memory self-refresh
6711 * The bit 22/21 of 0x42004
6712 * The bit 5 of 0x42020
6713 * The bit 15 of 0x45000
6714 */
6715 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6716 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6717 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6718 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6719 I915_WRITE(DISP_ARB_CTL,
6720 (I915_READ(DISP_ARB_CTL) |
6721 DISP_FBC_WM_DIS));
017636cc
VS		 6722
6723 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6724
6725 /*
6726 * Based on the document from hardware guys the following bits
6727 * should be set unconditionally in order to enable FBC.
6728 * The bit 22 of 0x42000
6729 * The bit 22 of 0x42004
6730 * The bit 7,8,9 of 0x42020.
6731 */
6732 if (IS_IRONLAKE_M(dev)) {
4bb35334 6733 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6734 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6735 I915_READ(ILK_DISPLAY_CHICKEN1) |
6736 ILK_FBCQ_DIS);
6737 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6738 I915_READ(ILK_DISPLAY_CHICKEN2) |
6739 ILK_DPARB_GATE);
6f1d69b0
ED		 6740 }
6741
4d47e4f5
DL		 6742 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6743
6f1d69b0
ED		 6744 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6745 I915_READ(ILK_DISPLAY_CHICKEN2) |
6746 ILK_ELPIN_409_SELECT);
6747 I915_WRITE(_3D_CHICKEN2,
6748 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6749 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6750
ecdb4eb7 6751 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6752 I915_WRITE(CACHE_MODE_0,
6753 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6754
4e04632e
AG		 6755 /* WaDisable_RenderCache_OperationalFlush:ilk */
6756 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6757
0e088b8f 6758 g4x_disable_trickle_feed(dev);
bdad2b2f 6759
3107bd48
DV		 6760 ibx_init_clock_gating(dev);
6761}
6762
6763static void cpt_init_clock_gating(struct drm_device *dev)
6764{
6765 struct drm_i915_private *dev_priv = dev->dev_private;
6766 int pipe;
3f704fa2 6767 uint32_t val;
3107bd48
DV		 6768
6769 /*
6770 * On Ibex Peak and Cougar Point, we need to disable clock
6771 * gating for the panel power sequencer or it will fail to
6772 * start up when no ports are active.
6773 */
cd664078
JB		 6774 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6775 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6776 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6777 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6778 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6779 /* The below fixes the weird display corruption, a few pixels shifted
6780 * downward, on (only) LVDS of some HP laptops with IVY.
6781 */
055e393f 6782 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6783 val = I915_READ(TRANS_CHICKEN2(pipe));
6784 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6785 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6786 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6787 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6788 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6789 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6790 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6791 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6792 }
3107bd48 6793 /* WADP0ClockGatingDisable */
055e393f 6794 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6795 I915_WRITE(TRANS_CHICKEN1(pipe),
6796 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6797 }
6f1d69b0
ED		 6798}
6799
1d7aaa0c
DV		 6800static void gen6_check_mch_setup(struct drm_device *dev)
6801{
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 uint32_t tmp;
6804
6805 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6806 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6807 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6808 tmp);
1d7aaa0c
DV		 6809}
6810
1fa61106 6811static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6812{
6813 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6814 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6815
231e54f6 6816 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6817
6818 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6819 I915_READ(ILK_DISPLAY_CHICKEN2) |
6820 ILK_ELPIN_409_SELECT);
6821
ecdb4eb7 6822 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6823 I915_WRITE(_3D_CHICKEN,
6824 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6825
4e04632e
AG		 6826 /* WaDisable_RenderCache_OperationalFlush:snb */
6827 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6828
8d85d272
VS		 6829 /*
6830 * BSpec recoomends 8x4 when MSAA is used,
6831 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6832 *
6833 * Note that PS/WM thread counts depend on the WIZ hashing
6834 * disable bit, which we don't touch here, but it's good
6835 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6836 */
6837 I915_WRITE(GEN6_GT_MODE,
98533251 6838 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6839
017636cc 6840 ilk_init_lp_watermarks(dev);
6f1d69b0 6841
6f1d69b0 6842 I915_WRITE(CACHE_MODE_0,
50743298 6843 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6844
6845 I915_WRITE(GEN6_UCGCTL1,
6846 I915_READ(GEN6_UCGCTL1) |
6847 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6848 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6849
6850 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6851 * gating disable must be set. Failure to set it results in
6852 * flickering pixels due to Z write ordering failures after
6853 * some amount of runtime in the Mesa "fire" demo, and Unigine
6854 * Sanctuary and Tropics, and apparently anything else with
6855 * alpha test or pixel discard.
6856 *
6857 * According to the spec, bit 11 (RCCUNIT) must also be set,
6858 * but we didn't debug actual testcases to find it out.
0f846f81 6859 *
ef59318c
VS		 6860 * WaDisableRCCUnitClockGating:snb
6861 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6862 */
6863 I915_WRITE(GEN6_UCGCTL2,
6864 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6865 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6866
5eb146dd 6867 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6868 I915_WRITE(_3D_CHICKEN3,
6869 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6870
e927ecde
VS		 6871 /*
6872 * Bspec says:
6873 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6874 * 3DSTATE_SF number of SF output attributes is more than 16."
6875 */
6876 I915_WRITE(_3D_CHICKEN3,
6877 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6878
6f1d69b0
ED		 6879 /*
6880 * According to the spec the following bits should be
6881 * set in order to enable memory self-refresh and fbc:
6882 * The bit21 and bit22 of 0x42000
6883 * The bit21 and bit22 of 0x42004
6884 * The bit5 and bit7 of 0x42020
6885 * The bit14 of 0x70180
6886 * The bit14 of 0x71180
4bb35334
DL		 6887 *
6888 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6889 */
6890 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6891 I915_READ(ILK_DISPLAY_CHICKEN1) |
6892 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6893 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6894 I915_READ(ILK_DISPLAY_CHICKEN2) |
6895 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6896 I915_WRITE(ILK_DSPCLK_GATE_D,
6897 I915_READ(ILK_DSPCLK_GATE_D) |
6898 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6899 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6900
0e088b8f 6901 g4x_disable_trickle_feed(dev);
f8f2ac9a 6902
3107bd48 6903 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6904
6905 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6906}
6907
6908static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6909{
6910 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6911
3aad9059 6912 /*
46680e0a 6913 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6914 *
6915 * This actually overrides the dispatch
6916 * mode for all thread types.
6917 */
6f1d69b0
ED		 6918 reg &= ~GEN7_FF_SCHED_MASK;
6919 reg |= GEN7_FF_TS_SCHED_HW;
6920 reg |= GEN7_FF_VS_SCHED_HW;
6921 reg |= GEN7_FF_DS_SCHED_HW;
6922
6923 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6924}
6925
17a303ec
PZ		 6926static void lpt_init_clock_gating(struct drm_device *dev)
6927{
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6929
6930 /*
6931 * TODO: this bit should only be enabled when really needed, then
6932 * disabled when not needed anymore in order to save power.
6933 */
c2699524 6934 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6935 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6936 I915_READ(SOUTH_DSPCLK_GATE_D) |
6937 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6938
6939 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6940 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6941 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6942 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6943}
6944
7d708ee4
ID		 6945static void lpt_suspend_hw(struct drm_device *dev)
6946{
6947 struct drm_i915_private *dev_priv = dev->dev_private;
6948
c2699524 6949 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6950 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6951
6952 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6953 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6954 }
6955}
6956
450174fe
ID		 6957static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6958 int general_prio_credits,
6959 int high_prio_credits)
6960{
6961 u32 misccpctl;
6962
6963 /* WaTempDisableDOPClkGating:bdw */
6964 misccpctl = I915_READ(GEN7_MISCCPCTL);
6965 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6966
6967 I915_WRITE(GEN8_L3SQCREG1,
6968 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6969 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6970
6971 /*
6972 * Wait at least 100 clocks before re-enabling clock gating.
6973 * See the definition of L3SQCREG1 in BSpec.
6974 */
6975 POSTING_READ(GEN8_L3SQCREG1);
6976 udelay(1);
6977 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6978}
6979
9498dba7
MK		 6980static void kabylake_init_clock_gating(struct drm_device *dev)
6981{
6982 struct drm_i915_private *dev_priv = dev->dev_private;
6983
b033bb6d 6984 gen9_init_clock_gating(dev);
9498dba7
MK		 6985
6986 /* WaDisableSDEUnitClockGating:kbl */
6987 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6988 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6989 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 6990
6991 /* WaDisableGamClockGating:kbl */
6992 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6993 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6994 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
9498dba7
MK		 6995}
6996
dc00b6a0
DV		 6997static void skylake_init_clock_gating(struct drm_device *dev)
6998{
44fff99f
MK		 6999 struct drm_i915_private *dev_priv = dev->dev_private;
7000
b033bb6d 7001 gen9_init_clock_gating(dev);
44fff99f
MK		 7002
7003 /* WAC6entrylatency:skl */
7004 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7005 FBC_LLC_FULLY_OPEN);
dc00b6a0
DV		 7006}
7007
47c2bd97 7008static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 7009{
7010 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 7011 enum pipe pipe;
1020a5c2 7012
7ad0dbab 7013 ilk_init_lp_watermarks(dev);
50ed5fbd 7014
ab57fff1 7015 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7016 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7017
ab57fff1 7018 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7019 I915_WRITE(CHICKEN_PAR1_1,
7020 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7021
ab57fff1 7022 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7023 for_each_pipe(dev_priv, pipe) {
07d27e20 7024 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7025 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7026 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7027 }
63801f21 7028
ab57fff1
BW		 7029 /* WaVSRefCountFullforceMissDisable:bdw */
7030 /* WaDSRefCountFullforceMissDisable:bdw */
7031 I915_WRITE(GEN7_FF_THREAD_MODE,
7032 I915_READ(GEN7_FF_THREAD_MODE) &
7033 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7034
295e8bb7
VS		 7035 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7036 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7037
7038 /* WaDisableSDEUnitClockGating:bdw */
7039 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7040 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7041
450174fe
ID		 7042 /* WaProgramL3SqcReg1Default:bdw */
7043 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7044
6d50b065
VS		 7045 /*
7046 * WaGttCachingOffByDefault:bdw
7047 * GTT cache may not work with big pages, so if those
7048 * are ever enabled GTT cache may need to be disabled.
7049 */
7050 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7051
17e0adf0
MK		 7052 /* WaKVMNotificationOnConfigChange:bdw */
7053 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7054 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7055
89d6b2b8 7056 lpt_init_clock_gating(dev);
1020a5c2
BW		 7057}
7058
cad2a2d7
ED		 7059static void haswell_init_clock_gating(struct drm_device *dev)
7060{
7061 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 7062
017636cc 7063 ilk_init_lp_watermarks(dev);
cad2a2d7 7064
f3fc4884
FJ		 7065 /* L3 caching of data atomics doesn't work -- disable it. */
7066 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7067 I915_WRITE(HSW_ROW_CHICKEN3,
7068 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7069
ecdb4eb7 7070 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7071 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7072 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7073 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7074
e36ea7ff
VS		 7075 /* WaVSRefCountFullforceMissDisable:hsw */
7076 I915_WRITE(GEN7_FF_THREAD_MODE,
7077 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7078
4e04632e
AG		 7079 /* WaDisable_RenderCache_OperationalFlush:hsw */
7080 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7081
fe27c606
CW		 7082 /* enable HiZ Raw Stall Optimization */
7083 I915_WRITE(CACHE_MODE_0_GEN7,
7084 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7085
ecdb4eb7 7086 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7087 I915_WRITE(CACHE_MODE_1,
7088 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7089
a12c4967
VS		 7090 /*
7091 * BSpec recommends 8x4 when MSAA is used,
7092 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7093 *
7094 * Note that PS/WM thread counts depend on the WIZ hashing
7095 * disable bit, which we don't touch here, but it's good
7096 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7097 */
7098 I915_WRITE(GEN7_GT_MODE,
98533251 7099 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7100
94411593
KG		 7101 /* WaSampleCChickenBitEnable:hsw */
7102 I915_WRITE(HALF_SLICE_CHICKEN3,
7103 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7104
ecdb4eb7 7105 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7106 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7107
90a88643
PZ		 7108 /* WaRsPkgCStateDisplayPMReq:hsw */
7109 I915_WRITE(CHICKEN_PAR1_1,
7110 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7111
17a303ec 7112 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7113}
7114
1fa61106 7115static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7116{
7117 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 7118 uint32_t snpcr;
6f1d69b0 7119
017636cc 7120 ilk_init_lp_watermarks(dev);
6f1d69b0 7121
231e54f6 7122 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7123
ecdb4eb7 7124 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7125 I915_WRITE(_3D_CHICKEN3,
7126 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7127
ecdb4eb7 7128 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7129 I915_WRITE(IVB_CHICKEN3,
7130 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7131 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7132
ecdb4eb7 7133 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7134 if (IS_IVB_GT1(dev))
7135 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7136 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7137
4e04632e
AG		 7138 /* WaDisable_RenderCache_OperationalFlush:ivb */
7139 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7140
ecdb4eb7 7141 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7142 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7143 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7144
ecdb4eb7 7145 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7146 I915_WRITE(GEN7_L3CNTLREG1,
7147 GEN7_WA_FOR_GEN7_L3_CONTROL);
7148 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7149 GEN7_WA_L3_CHICKEN_MODE);
7150 if (IS_IVB_GT1(dev))
7151 I915_WRITE(GEN7_ROW_CHICKEN2,
7152 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7153 else {
7154 /* must write both registers */
7155 I915_WRITE(GEN7_ROW_CHICKEN2,
7156 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7157 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7158 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7159 }
6f1d69b0 7160
ecdb4eb7 7161 /* WaForceL3Serialization:ivb */
61939d97
JB		 7162 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7163 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7164
1b80a19a 7165 /*
0f846f81 7166 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7167 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7168 */
7169 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7170 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7171
ecdb4eb7 7172 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7173 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7174 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7175 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7176
0e088b8f 7177 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7178
7179 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7180
22721343
CW		 7181 if (0) { /* causes HiZ corruption on ivb:gt1 */
7182 /* enable HiZ Raw Stall Optimization */
7183 I915_WRITE(CACHE_MODE_0_GEN7,
7184 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7185 }
116f2b6d 7186
ecdb4eb7 7187 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7188 I915_WRITE(CACHE_MODE_1,
7189 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7190
a607c1a4
VS		 7191 /*
7192 * BSpec recommends 8x4 when MSAA is used,
7193 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7194 *
7195 * Note that PS/WM thread counts depend on the WIZ hashing
7196 * disable bit, which we don't touch here, but it's good
7197 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7198 */
7199 I915_WRITE(GEN7_GT_MODE,
98533251 7200 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7201
20848223
BW		 7202 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7203 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7204 snpcr |= GEN6_MBC_SNPCR_MED;
7205 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7206
ab5c608b
BW		 7207 if (!HAS_PCH_NOP(dev))
7208 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7209
7210 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7211}
7212
1fa61106 7213static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7214{
7215 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 7216
ecdb4eb7 7217 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7218 I915_WRITE(_3D_CHICKEN3,
7219 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7220
ecdb4eb7 7221 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7222 I915_WRITE(IVB_CHICKEN3,
7223 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7224 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7225
fad7d36e 7226 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7227 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7228 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7229 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7230 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7231
4e04632e
AG		 7232 /* WaDisable_RenderCache_OperationalFlush:vlv */
7233 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7234
ecdb4eb7 7235 /* WaForceL3Serialization:vlv */
61939d97
JB		 7236 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7237 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7238
ecdb4eb7 7239 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7240 I915_WRITE(GEN7_ROW_CHICKEN2,
7241 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7242
ecdb4eb7 7243 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7244 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7245 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7246 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7247
46680e0a
VS		 7248 gen7_setup_fixed_func_scheduler(dev_priv);
7249
3c0edaeb 7250 /*
0f846f81 7251 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7252 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7253 */
7254 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7255 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7256
c98f5062
AG		 7257 /* WaDisableL3Bank2xClockGate:vlv
7258 * Disabling L3 clock gating- MMIO 940c[25] = 1
7259 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7260 I915_WRITE(GEN7_UCGCTL4,
7261 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7262
afd58e79
VS		 7263 /*
7264 * BSpec says this must be set, even though
7265 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7266 */
6b26c86d
DV		 7267 I915_WRITE(CACHE_MODE_1,
7268 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7269
da2518f9
VS		 7270 /*
7271 * BSpec recommends 8x4 when MSAA is used,
7272 * however in practice 16x4 seems fastest.
7273 *
7274 * Note that PS/WM thread counts depend on the WIZ hashing
7275 * disable bit, which we don't touch here, but it's good
7276 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7277 */
7278 I915_WRITE(GEN7_GT_MODE,
7279 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7280
031994ee
VS		 7281 /*
7282 * WaIncreaseL3CreditsForVLVB0:vlv
7283 * This is the hardware default actually.
7284 */
7285 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7286
2d809570 7287 /*
ecdb4eb7 7288 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7289 * Disable clock gating on th GCFG unit to prevent a delay
7290 * in the reporting of vblank events.
7291 */
7a0d1eed 7292 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7293}
7294
a4565da8
VS		 7295static void cherryview_init_clock_gating(struct drm_device *dev)
7296{
7297 struct drm_i915_private *dev_priv = dev->dev_private;
7298
232ce337
VS		 7299 /* WaVSRefCountFullforceMissDisable:chv */
7300 /* WaDSRefCountFullforceMissDisable:chv */
7301 I915_WRITE(GEN7_FF_THREAD_MODE,
7302 I915_READ(GEN7_FF_THREAD_MODE) &
7303 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7304
7305 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7306 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7307 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7308
7309 /* WaDisableCSUnitClockGating:chv */
7310 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7311 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7312
7313 /* WaDisableSDEUnitClockGating:chv */
7314 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7315 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7316
450174fe
ID		 7317 /*
7318 * WaProgramL3SqcReg1Default:chv
7319 * See gfxspecs/Related Documents/Performance Guide/
7320 * LSQC Setting Recommendations.
7321 */
7322 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7323
6d50b065
VS		 7324 /*
7325 * GTT cache may not work with big pages, so if those
7326 * are ever enabled GTT cache may need to be disabled.
7327 */
7328 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7329}
7330
1fa61106 7331static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7332{
7333 struct drm_i915_private *dev_priv = dev->dev_private;
7334 uint32_t dspclk_gate;
7335
7336 I915_WRITE(RENCLK_GATE_D1, 0);
7337 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7338 GS_UNIT_CLOCK_GATE_DISABLE |
7339 CL_UNIT_CLOCK_GATE_DISABLE);
7340 I915_WRITE(RAMCLK_GATE_D, 0);
7341 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7342 OVRUNIT_CLOCK_GATE_DISABLE |
7343 OVCUNIT_CLOCK_GATE_DISABLE;
7344 if (IS_GM45(dev))
7345 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7346 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7347
7348 /* WaDisableRenderCachePipelinedFlush */
7349 I915_WRITE(CACHE_MODE_0,
7350 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7351
4e04632e
AG		 7352 /* WaDisable_RenderCache_OperationalFlush:g4x */
7353 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7354
0e088b8f 7355 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7356}
7357
1fa61106 7358static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7359{
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361
7362 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7363 I915_WRITE(RENCLK_GATE_D2, 0);
7364 I915_WRITE(DSPCLK_GATE_D, 0);
7365 I915_WRITE(RAMCLK_GATE_D, 0);
7366 I915_WRITE16(DEUC, 0);
20f94967
VS		 7367 I915_WRITE(MI_ARB_STATE,
7368 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7369
7370 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7371 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7372}
7373
1fa61106 7374static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7375{
7376 struct drm_i915_private *dev_priv = dev->dev_private;
7377
7378 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7379 I965_RCC_CLOCK_GATE_DISABLE |
7380 I965_RCPB_CLOCK_GATE_DISABLE |
7381 I965_ISC_CLOCK_GATE_DISABLE |
7382 I965_FBC_CLOCK_GATE_DISABLE);
7383 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7384 I915_WRITE(MI_ARB_STATE,
7385 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7386
7387 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7388 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7389}
7390
1fa61106 7391static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7392{
7393 struct drm_i915_private *dev_priv = dev->dev_private;
7394 u32 dstate = I915_READ(D_STATE);
7395
7396 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7397 DSTATE_DOT_CLOCK_GATING;
7398 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7399
7400 if (IS_PINEVIEW(dev))
7401 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7402
7403 /* IIR "flip pending" means done if this bit is set */
7404 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7405
7406 /* interrupts should cause a wake up from C3 */
3299254f 7407 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7408
7409 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7410 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7411
7412 I915_WRITE(MI_ARB_STATE,
7413 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7414}
7415
1fa61106 7416static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7417{
7418 struct drm_i915_private *dev_priv = dev->dev_private;
7419
7420 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7421
7422 /* interrupts should cause a wake up from C3 */
7423 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7424 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7425
7426 I915_WRITE(MEM_MODE,
7427 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7428}
7429
1fa61106 7430static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7431{
7432 struct drm_i915_private *dev_priv = dev->dev_private;
7433
7434 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7435
7436 I915_WRITE(MEM_MODE,
7437 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7438 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7439}
7440
6f1d69b0
ED		 7441void intel_init_clock_gating(struct drm_device *dev)
7442{
7443 struct drm_i915_private *dev_priv = dev->dev_private;
7444
bb400da9 7445 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7446}
7447
7d708ee4
ID		 7448void intel_suspend_hw(struct drm_device *dev)
7449{
7450 if (HAS_PCH_LPT(dev))
7451 lpt_suspend_hw(dev);
7452}
7453
bb400da9
ID		 7454static void nop_init_clock_gating(struct drm_device *dev)
7455{
7456 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7457}
7458
7459/**
7460 * intel_init_clock_gating_hooks - setup the clock gating hooks
7461 * @dev_priv: device private
7462 *
7463 * Setup the hooks that configure which clocks of a given platform can be
7464 * gated and also apply various GT and display specific workarounds for these
7465 * platforms. Note that some GT specific workarounds are applied separately
7466 * when GPU contexts or batchbuffers start their execution.
7467 */
7468void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7469{
7470 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7471 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7472 else if (IS_KABYLAKE(dev_priv))
9498dba7 7473 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7474 else if (IS_BROXTON(dev_priv))
7475 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7476 else if (IS_BROADWELL(dev_priv))
7477 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7478 else if (IS_CHERRYVIEW(dev_priv))
7479 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7480 else if (IS_HASWELL(dev_priv))
7481 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7482 else if (IS_IVYBRIDGE(dev_priv))
7483 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7484 else if (IS_VALLEYVIEW(dev_priv))
7485 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7486 else if (IS_GEN6(dev_priv))
7487 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7488 else if (IS_GEN5(dev_priv))
7489 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7490 else if (IS_G4X(dev_priv))
7491 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7492 else if (IS_CRESTLINE(dev_priv))
7493 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7494 else if (IS_BROADWATER(dev_priv))
7495 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7496 else if (IS_GEN3(dev_priv))
7497 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7498 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7499 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7500 else if (IS_GEN2(dev_priv))
7501 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7502 else {
7503 MISSING_CASE(INTEL_DEVID(dev_priv));
7504 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7505 }
7506}
7507
1fa61106
ED		 7508/* Set up chip specific power management-related functions */
7509void intel_init_pm(struct drm_device *dev)
7510{
7511 struct drm_i915_private *dev_priv = dev->dev_private;
7512
7ff0ebcc 7513 intel_fbc_init(dev_priv);
1fa61106 7514
c921aba8
DV		 7515 /* For cxsr */
7516 if (IS_PINEVIEW(dev))
7517 i915_pineview_get_mem_freq(dev);
7518 else if (IS_GEN5(dev))
7519 i915_ironlake_get_mem_freq(dev);
7520
1fa61106 7521 /* For FIFO watermark updates */
f5ed50cb 7522 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7523 skl_setup_wm_latency(dev);
2d41c0b5 7524 dev_priv->display.update_wm = skl_update_wm;
98d39494 7525 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7526 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7527 ilk_setup_wm_latency(dev);
53615a5e 7528
bd602544
VS		 7529 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7530 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7531 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7532 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7533 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7534 dev_priv->display.compute_intermediate_wm =
7535 ilk_compute_intermediate_wm;
7536 dev_priv->display.initial_watermarks =
7537 ilk_initial_watermarks;
7538 dev_priv->display.optimize_watermarks =
7539 ilk_optimize_watermarks;
bd602544
VS		 7540 } else {
7541 DRM_DEBUG_KMS("Failed to read display plane latency. "
7542 "Disable CxSR\n");
7543 }
a4565da8 7544 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7545 vlv_setup_wm_latency(dev);
262cd2e1 7546 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7547 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7548 vlv_setup_wm_latency(dev);
26e1fe4f 7549 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7550 } else if (IS_PINEVIEW(dev)) {
7551 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7552 dev_priv->is_ddr3,
7553 dev_priv->fsb_freq,
7554 dev_priv->mem_freq)) {
7555 DRM_INFO("failed to find known CxSR latency "
7556 "(found ddr%s fsb freq %d, mem freq %d), "
7557 "disabling CxSR\n",
7558 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7559 dev_priv->fsb_freq, dev_priv->mem_freq);
7560 /* Disable CxSR and never update its watermark again */
5209b1f4 7561 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7562 dev_priv->display.update_wm = NULL;
7563 } else
7564 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7565 } else if (IS_G4X(dev)) {
7566 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7567 } else if (IS_GEN4(dev)) {
7568 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7569 } else if (IS_GEN3(dev)) {
7570 dev_priv->display.update_wm = i9xx_update_wm;
7571 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7572 } else if (IS_GEN2(dev)) {
7573 if (INTEL_INFO(dev)->num_pipes == 1) {
7574 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7575 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7576 } else {
7577 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7578 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7579 }
feb56b93
DV		 7580 } else {
7581 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7582 }
7583}
7584
151a49d0 7585int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7586{
4fc688ce 7587 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7588
7589 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7590 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7591 return -EAGAIN;
7592 }
7593
7594 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7595 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7596 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7597
7598 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7599 500)) {
7600 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7601 return -ETIMEDOUT;
7602 }
7603
7604 *val = I915_READ(GEN6_PCODE_DATA);
7605 I915_WRITE(GEN6_PCODE_DATA, 0);
7606
7607 return 0;
7608}
7609
151a49d0 7610int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7611{
4fc688ce 7612 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7613
7614 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7615 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7616 return -EAGAIN;
7617 }
7618
7619 I915_WRITE(GEN6_PCODE_DATA, val);
7620 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7621
7622 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7623 500)) {
7624 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7625 return -ETIMEDOUT;
7626 }
7627
7628 I915_WRITE(GEN6_PCODE_DATA, 0);
7629
7630 return 0;
7631}
a0e4e199 7632
dd06f88c
VS		 7633static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7634{
c30fec65
VS		 7635 /*
7636 * N = val - 0xb7
7637 * Slow = Fast = GPLL ref * N
7638 */
7639 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7640}
7641
b55dd647 7642static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7643{
c30fec65 7644 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7645}
7646
b55dd647 7647static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7648{
c30fec65
VS		 7649 /*
7650 * N = val / 2
7651 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7652 */
7653 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7654}
7655
b55dd647 7656static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7657{
1c14762d 7658 /* CHV needs even values */
c30fec65 7659 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7660}
7661
616bc820 7662int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7663{
2d1fe073 7664 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7665 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7666 GEN9_FREQ_SCALER);
2d1fe073 7667 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7668 return chv_gpu_freq(dev_priv, val);
2d1fe073 7669 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7670 return byt_gpu_freq(dev_priv, val);
7671 else
7672 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7673}
7674
616bc820
VS		 7675int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7676{
2d1fe073 7677 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7678 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7679 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7680 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7681 return chv_freq_opcode(dev_priv, val);
2d1fe073 7682 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7683 return byt_freq_opcode(dev_priv, val);
7684 else
500a3d2e 7685 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7686}
22b1b2f8 7687
6ad790c0
CW		 7688struct request_boost {
7689 struct work_struct work;
eed29a5b 7690 struct drm_i915_gem_request *req;
6ad790c0
CW		 7691};
7692
7693static void __intel_rps_boost_work(struct work_struct *work)
7694{
7695 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7696 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7697
e61b9958 7698 if (!i915_gem_request_completed(req, true))
c033666a 7699 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7700
73db04cf 7701 i915_gem_request_unreference(req);
6ad790c0
CW		 7702 kfree(boost);
7703}
7704
91d14251 7705void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7706{
7707 struct request_boost *boost;
7708
91d14251 7709 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7710 return;
7711
e61b9958
CW		 7712 if (i915_gem_request_completed(req, true))
7713 return;
7714
6ad790c0
CW		 7715 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7716 if (boost == NULL)
7717 return;
7718
eed29a5b
DV		 7719 i915_gem_request_reference(req);
7720 boost->req = req;
6ad790c0
CW		 7721
7722 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7723 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7724}
7725
f742a552 7726void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7727{
7728 struct drm_i915_private *dev_priv = dev->dev_private;
7729
f742a552 7730 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7731 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7732
907b28c5
CW		 7733 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7734 intel_gen6_powersave_work);
1854d5ca 7735 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7736 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7737 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7738
33688d95 7739 dev_priv->pm.suspended = false;
1f814dac 7740 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7741 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7742}
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