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drm/i915: Rename struct intel_crtc_config to intel_crtc_state
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
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29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV
31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
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34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL
55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
59 /*
60 * WaDisableSDEUnitClockGating:skl
61 * This seems to be a pre-production w/a.
62 */
63 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
64 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
91e41d16 65
3ca5da43
DL
66 /*
67 * WaDisableDgMirrorFixInHalfSliceChicken5:skl
68 * This is a pre-production w/a.
69 */
70 I915_WRITE(GEN9_HALF_SLICE_CHICKEN5,
71 I915_READ(GEN9_HALF_SLICE_CHICKEN5) &
72 ~GEN9_DG_MIRROR_FIX_ENABLE);
73
91e41d16
DL
74 /* Wa4x4STCOptimizationDisable:skl */
75 I915_WRITE(CACHE_MODE_1,
76 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
da2078cd
DL
77}
78
85208be0 79
c921aba8
DV
80static void i915_pineview_get_mem_freq(struct drm_device *dev)
81{
50227e1c 82 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV
83 u32 tmp;
84
85 tmp = I915_READ(CLKCFG);
86
87 switch (tmp & CLKCFG_FSB_MASK) {
88 case CLKCFG_FSB_533:
89 dev_priv->fsb_freq = 533; /* 133*4 */
90 break;
91 case CLKCFG_FSB_800:
92 dev_priv->fsb_freq = 800; /* 200*4 */
93 break;
94 case CLKCFG_FSB_667:
95 dev_priv->fsb_freq = 667; /* 167*4 */
96 break;
97 case CLKCFG_FSB_400:
98 dev_priv->fsb_freq = 400; /* 100*4 */
99 break;
100 }
101
102 switch (tmp & CLKCFG_MEM_MASK) {
103 case CLKCFG_MEM_533:
104 dev_priv->mem_freq = 533;
105 break;
106 case CLKCFG_MEM_667:
107 dev_priv->mem_freq = 667;
108 break;
109 case CLKCFG_MEM_800:
110 dev_priv->mem_freq = 800;
111 break;
112 }
113
114 /* detect pineview DDR3 setting */
115 tmp = I915_READ(CSHRDDR3CTL);
116 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
117}
118
119static void i915_ironlake_get_mem_freq(struct drm_device *dev)
120{
50227e1c 121 struct drm_i915_private *dev_priv = dev->dev_private;
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DV
122 u16 ddrpll, csipll;
123
124 ddrpll = I915_READ16(DDRMPLL1);
125 csipll = I915_READ16(CSIPLL0);
126
127 switch (ddrpll & 0xff) {
128 case 0xc:
129 dev_priv->mem_freq = 800;
130 break;
131 case 0x10:
132 dev_priv->mem_freq = 1066;
133 break;
134 case 0x14:
135 dev_priv->mem_freq = 1333;
136 break;
137 case 0x18:
138 dev_priv->mem_freq = 1600;
139 break;
140 default:
141 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
142 ddrpll & 0xff);
143 dev_priv->mem_freq = 0;
144 break;
145 }
146
20e4d407 147 dev_priv->ips.r_t = dev_priv->mem_freq;
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DV
148
149 switch (csipll & 0x3ff) {
150 case 0x00c:
151 dev_priv->fsb_freq = 3200;
152 break;
153 case 0x00e:
154 dev_priv->fsb_freq = 3733;
155 break;
156 case 0x010:
157 dev_priv->fsb_freq = 4266;
158 break;
159 case 0x012:
160 dev_priv->fsb_freq = 4800;
161 break;
162 case 0x014:
163 dev_priv->fsb_freq = 5333;
164 break;
165 case 0x016:
166 dev_priv->fsb_freq = 5866;
167 break;
168 case 0x018:
169 dev_priv->fsb_freq = 6400;
170 break;
171 default:
172 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
173 csipll & 0x3ff);
174 dev_priv->fsb_freq = 0;
175 break;
176 }
177
178 if (dev_priv->fsb_freq == 3200) {
20e4d407 179 dev_priv->ips.c_m = 0;
c921aba8 180 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 181 dev_priv->ips.c_m = 1;
c921aba8 182 } else {
20e4d407 183 dev_priv->ips.c_m = 2;
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DV
184 }
185}
186
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187static const struct cxsr_latency cxsr_latency_table[] = {
188 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
189 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
190 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
191 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
192 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
193
194 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
195 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
196 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
197 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
198 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
199
200 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
201 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
202 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
203 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
204 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
205
206 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
207 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
208 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
209 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
210 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
211
212 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
213 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
214 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
215 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
216 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
217
218 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
219 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
220 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
221 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
222 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
223};
224
63c62275 225static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
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226 int is_ddr3,
227 int fsb,
228 int mem)
229{
230 const struct cxsr_latency *latency;
231 int i;
232
233 if (fsb == 0 || mem == 0)
234 return NULL;
235
236 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
237 latency = &cxsr_latency_table[i];
238 if (is_desktop == latency->is_desktop &&
239 is_ddr3 == latency->is_ddr3 &&
240 fsb == latency->fsb_freq && mem == latency->mem_freq)
241 return latency;
242 }
243
244 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
245
246 return NULL;
247}
248
5209b1f4 249void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 250{
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ID
251 struct drm_device *dev = dev_priv->dev;
252 u32 val;
b445e3b0 253
5209b1f4
ID
254 if (IS_VALLEYVIEW(dev)) {
255 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
256 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
257 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
258 } else if (IS_PINEVIEW(dev)) {
259 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
260 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
261 I915_WRITE(DSPFW3, val);
262 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
263 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
264 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
265 I915_WRITE(FW_BLC_SELF, val);
266 } else if (IS_I915GM(dev)) {
267 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
268 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
269 I915_WRITE(INSTPM, val);
270 } else {
271 return;
272 }
b445e3b0 273
5209b1f4
ID
274 DRM_DEBUG_KMS("memory self-refresh is %s\n",
275 enable ? "enabled" : "disabled");
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276}
277
278/*
279 * Latency for FIFO fetches is dependent on several factors:
280 * - memory configuration (speed, channels)
281 * - chipset
282 * - current MCH state
283 * It can be fairly high in some situations, so here we assume a fairly
284 * pessimal value. It's a tradeoff between extra memory fetches (if we
285 * set this value too high, the FIFO will fetch frequently to stay full)
286 * and power consumption (set it too low to save power and we might see
287 * FIFO underruns and display "flicker").
288 *
289 * A value of 5us seems to be a good balance; safe for very low end
290 * platforms but not overly aggressive on lower latency configs.
291 */
5aef6003 292static const int pessimal_latency_ns = 5000;
b445e3b0 293
1fa61106 294static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
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ED
295{
296 struct drm_i915_private *dev_priv = dev->dev_private;
297 uint32_t dsparb = I915_READ(DSPARB);
298 int size;
299
300 size = dsparb & 0x7f;
301 if (plane)
302 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
303
304 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
305 plane ? "B" : "A", size);
306
307 return size;
308}
309
feb56b93 310static int i830_get_fifo_size(struct drm_device *dev, int plane)
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ED
311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313 uint32_t dsparb = I915_READ(DSPARB);
314 int size;
315
316 size = dsparb & 0x1ff;
317 if (plane)
318 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
319 size >>= 1; /* Convert to cachelines */
320
321 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
322 plane ? "B" : "A", size);
323
324 return size;
325}
326
1fa61106 327static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED
328{
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 uint32_t dsparb = I915_READ(DSPARB);
331 int size;
332
333 size = dsparb & 0x7f;
334 size >>= 2; /* Convert to cachelines */
335
336 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
337 plane ? "B" : "A",
338 size);
339
340 return size;
341}
342
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343/* Pineview has different values for various configs */
344static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS
345 .fifo_size = PINEVIEW_DISPLAY_FIFO,
346 .max_wm = PINEVIEW_MAX_WM,
347 .default_wm = PINEVIEW_DFT_WM,
348 .guard_size = PINEVIEW_GUARD_WM,
349 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
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ED
350};
351static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS
352 .fifo_size = PINEVIEW_DISPLAY_FIFO,
353 .max_wm = PINEVIEW_MAX_WM,
354 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
355 .guard_size = PINEVIEW_GUARD_WM,
356 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
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357};
358static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS
359 .fifo_size = PINEVIEW_CURSOR_FIFO,
360 .max_wm = PINEVIEW_CURSOR_MAX_WM,
361 .default_wm = PINEVIEW_CURSOR_DFT_WM,
362 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
363 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED
364};
365static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS
366 .fifo_size = PINEVIEW_CURSOR_FIFO,
367 .max_wm = PINEVIEW_CURSOR_MAX_WM,
368 .default_wm = PINEVIEW_CURSOR_DFT_WM,
369 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
370 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED
371};
372static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS
373 .fifo_size = G4X_FIFO_SIZE,
374 .max_wm = G4X_MAX_WM,
375 .default_wm = G4X_MAX_WM,
376 .guard_size = 2,
377 .cacheline_size = G4X_FIFO_LINE_SIZE,
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378};
379static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS
380 .fifo_size = I965_CURSOR_FIFO,
381 .max_wm = I965_CURSOR_MAX_WM,
382 .default_wm = I965_CURSOR_DFT_WM,
383 .guard_size = 2,
384 .cacheline_size = G4X_FIFO_LINE_SIZE,
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385};
386static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS
387 .fifo_size = VALLEYVIEW_FIFO_SIZE,
388 .max_wm = VALLEYVIEW_MAX_WM,
389 .default_wm = VALLEYVIEW_MAX_WM,
390 .guard_size = 2,
391 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
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392};
393static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS
394 .fifo_size = I965_CURSOR_FIFO,
395 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
396 .default_wm = I965_CURSOR_DFT_WM,
397 .guard_size = 2,
398 .cacheline_size = G4X_FIFO_LINE_SIZE,
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ED
399};
400static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS
401 .fifo_size = I965_CURSOR_FIFO,
402 .max_wm = I965_CURSOR_MAX_WM,
403 .default_wm = I965_CURSOR_DFT_WM,
404 .guard_size = 2,
405 .cacheline_size = I915_FIFO_LINE_SIZE,
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406};
407static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS
408 .fifo_size = I945_FIFO_SIZE,
409 .max_wm = I915_MAX_WM,
410 .default_wm = 1,
411 .guard_size = 2,
412 .cacheline_size = I915_FIFO_LINE_SIZE,
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ED
413};
414static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS
415 .fifo_size = I915_FIFO_SIZE,
416 .max_wm = I915_MAX_WM,
417 .default_wm = 1,
418 .guard_size = 2,
419 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 420};
9d539105 421static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS
422 .fifo_size = I855GM_FIFO_SIZE,
423 .max_wm = I915_MAX_WM,
424 .default_wm = 1,
425 .guard_size = 2,
426 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 427};
9d539105
VS
428static const struct intel_watermark_params i830_bc_wm_info = {
429 .fifo_size = I855GM_FIFO_SIZE,
430 .max_wm = I915_MAX_WM/2,
431 .default_wm = 1,
432 .guard_size = 2,
433 .cacheline_size = I830_FIFO_LINE_SIZE,
434};
feb56b93 435static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS
436 .fifo_size = I830_FIFO_SIZE,
437 .max_wm = I915_MAX_WM,
438 .default_wm = 1,
439 .guard_size = 2,
440 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
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441};
442
b445e3b0
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443/**
444 * intel_calculate_wm - calculate watermark level
445 * @clock_in_khz: pixel clock
446 * @wm: chip FIFO params
447 * @pixel_size: display pixel size
448 * @latency_ns: memory latency for the platform
449 *
450 * Calculate the watermark level (the level at which the display plane will
451 * start fetching from memory again). Each chip has a different display
452 * FIFO size and allocation, so the caller needs to figure that out and pass
453 * in the correct intel_watermark_params structure.
454 *
455 * As the pixel clock runs, the FIFO will be drained at a rate that depends
456 * on the pixel size. When it reaches the watermark level, it'll start
457 * fetching FIFO line sized based chunks from memory until the FIFO fills
458 * past the watermark point. If the FIFO drains completely, a FIFO underrun
459 * will occur, and a display engine hang could result.
460 */
461static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
462 const struct intel_watermark_params *wm,
463 int fifo_size,
464 int pixel_size,
465 unsigned long latency_ns)
466{
467 long entries_required, wm_size;
468
469 /*
470 * Note: we need to make sure we don't overflow for various clock &
471 * latency values.
472 * clocks go from a few thousand to several hundred thousand.
473 * latency is usually a few thousand
474 */
475 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
476 1000;
477 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
478
479 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
480
481 wm_size = fifo_size - (entries_required + wm->guard_size);
482
483 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
484
485 /* Don't promote wm_size to unsigned... */
486 if (wm_size > (long)wm->max_wm)
487 wm_size = wm->max_wm;
488 if (wm_size <= 0)
489 wm_size = wm->default_wm;
d6feb196
VS
490
491 /*
492 * Bspec seems to indicate that the value shouldn't be lower than
493 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
494 * Lets go for 8 which is the burst size since certain platforms
495 * already use a hardcoded 8 (which is what the spec says should be
496 * done).
497 */
498 if (wm_size <= 8)
499 wm_size = 8;
500
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ED
501 return wm_size;
502}
503
504static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
505{
506 struct drm_crtc *crtc, *enabled = NULL;
507
70e1e0ec 508 for_each_crtc(dev, crtc) {
3490ea5d 509 if (intel_crtc_active(crtc)) {
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ED
510 if (enabled)
511 return NULL;
512 enabled = crtc;
513 }
514 }
515
516 return enabled;
517}
518
46ba614c 519static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 520{
46ba614c 521 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 struct drm_crtc *crtc;
524 const struct cxsr_latency *latency;
525 u32 reg;
526 unsigned long wm;
527
528 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
529 dev_priv->fsb_freq, dev_priv->mem_freq);
530 if (!latency) {
531 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 532 intel_set_memory_cxsr(dev_priv, false);
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ED
533 return;
534 }
535
536 crtc = single_enabled_crtc(dev);
537 if (crtc) {
241bfc38 538 const struct drm_display_mode *adjusted_mode;
f4510a27 539 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL
540 int clock;
541
542 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
543 clock = adjusted_mode->crtc_clock;
b445e3b0
ED
544
545 /* Display SR */
546 wm = intel_calculate_wm(clock, &pineview_display_wm,
547 pineview_display_wm.fifo_size,
548 pixel_size, latency->display_sr);
549 reg = I915_READ(DSPFW1);
550 reg &= ~DSPFW_SR_MASK;
551 reg |= wm << DSPFW_SR_SHIFT;
552 I915_WRITE(DSPFW1, reg);
553 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
554
555 /* cursor SR */
556 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
557 pineview_display_wm.fifo_size,
558 pixel_size, latency->cursor_sr);
559 reg = I915_READ(DSPFW3);
560 reg &= ~DSPFW_CURSOR_SR_MASK;
561 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
562 I915_WRITE(DSPFW3, reg);
563
564 /* Display HPLL off SR */
565 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
566 pineview_display_hplloff_wm.fifo_size,
567 pixel_size, latency->display_hpll_disable);
568 reg = I915_READ(DSPFW3);
569 reg &= ~DSPFW_HPLL_SR_MASK;
570 reg |= wm & DSPFW_HPLL_SR_MASK;
571 I915_WRITE(DSPFW3, reg);
572
573 /* cursor HPLL off SR */
574 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
575 pineview_display_hplloff_wm.fifo_size,
576 pixel_size, latency->cursor_hpll_disable);
577 reg = I915_READ(DSPFW3);
578 reg &= ~DSPFW_HPLL_CURSOR_MASK;
579 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
580 I915_WRITE(DSPFW3, reg);
581 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
582
5209b1f4 583 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 584 } else {
5209b1f4 585 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED
586 }
587}
588
589static bool g4x_compute_wm0(struct drm_device *dev,
590 int plane,
591 const struct intel_watermark_params *display,
592 int display_latency_ns,
593 const struct intel_watermark_params *cursor,
594 int cursor_latency_ns,
595 int *plane_wm,
596 int *cursor_wm)
597{
598 struct drm_crtc *crtc;
4fe8590a 599 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED
600 int htotal, hdisplay, clock, pixel_size;
601 int line_time_us, line_count;
602 int entries, tlb_miss;
603
604 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 605 if (!intel_crtc_active(crtc)) {
b445e3b0
ED
606 *cursor_wm = cursor->guard_size;
607 *plane_wm = display->guard_size;
608 return false;
609 }
610
4fe8590a 611 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 612 clock = adjusted_mode->crtc_clock;
fec8cba3 613 htotal = adjusted_mode->crtc_htotal;
37327abd 614 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 615 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED
616
617 /* Use the small buffer method to calculate plane watermark */
618 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
619 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
620 if (tlb_miss > 0)
621 entries += tlb_miss;
622 entries = DIV_ROUND_UP(entries, display->cacheline_size);
623 *plane_wm = entries + display->guard_size;
624 if (*plane_wm > (int)display->max_wm)
625 *plane_wm = display->max_wm;
626
627 /* Use the large buffer method to calculate cursor watermark */
922044c9 628 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 629 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 630 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED
631 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
632 if (tlb_miss > 0)
633 entries += tlb_miss;
634 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
635 *cursor_wm = entries + cursor->guard_size;
636 if (*cursor_wm > (int)cursor->max_wm)
637 *cursor_wm = (int)cursor->max_wm;
638
639 return true;
640}
641
642/*
643 * Check the wm result.
644 *
645 * If any calculated watermark values is larger than the maximum value that
646 * can be programmed into the associated watermark register, that watermark
647 * must be disabled.
648 */
649static bool g4x_check_srwm(struct drm_device *dev,
650 int display_wm, int cursor_wm,
651 const struct intel_watermark_params *display,
652 const struct intel_watermark_params *cursor)
653{
654 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
655 display_wm, cursor_wm);
656
657 if (display_wm > display->max_wm) {
658 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
659 display_wm, display->max_wm);
660 return false;
661 }
662
663 if (cursor_wm > cursor->max_wm) {
664 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
665 cursor_wm, cursor->max_wm);
666 return false;
667 }
668
669 if (!(display_wm || cursor_wm)) {
670 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
671 return false;
672 }
673
674 return true;
675}
676
677static bool g4x_compute_srwm(struct drm_device *dev,
678 int plane,
679 int latency_ns,
680 const struct intel_watermark_params *display,
681 const struct intel_watermark_params *cursor,
682 int *display_wm, int *cursor_wm)
683{
684 struct drm_crtc *crtc;
4fe8590a 685 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED
686 int hdisplay, htotal, pixel_size, clock;
687 unsigned long line_time_us;
688 int line_count, line_size;
689 int small, large;
690 int entries;
691
692 if (!latency_ns) {
693 *display_wm = *cursor_wm = 0;
694 return false;
695 }
696
697 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 698 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 699 clock = adjusted_mode->crtc_clock;
fec8cba3 700 htotal = adjusted_mode->crtc_htotal;
37327abd 701 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 702 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 703
922044c9 704 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED
705 line_count = (latency_ns / line_time_us + 1000) / 1000;
706 line_size = hdisplay * pixel_size;
707
708 /* Use the minimum of the small and large buffer method for primary */
709 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
710 large = line_count * line_size;
711
712 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
713 *display_wm = entries + display->guard_size;
714
715 /* calculate the self-refresh watermark for display cursor */
7bb836dd 716 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED
717 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
718 *cursor_wm = entries + cursor->guard_size;
719
720 return g4x_check_srwm(dev,
721 *display_wm, *cursor_wm,
722 display, cursor);
723}
724
0948c265
GB
725static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
726 int pixel_size,
727 int *prec_mult,
728 int *drain_latency)
b445e3b0 729{
5e56ba45 730 struct drm_device *dev = crtc->dev;
b445e3b0 731 int entries;
0948c265 732 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0 733
0948c265 734 if (WARN(clock == 0, "Pixel clock is zero!\n"))
b445e3b0
ED
735 return false;
736
0948c265
GB
737 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
738 return false;
b445e3b0 739
a398e9c7 740 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
5e56ba45
RV
741 if (IS_CHERRYVIEW(dev))
742 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 :
743 DRAIN_LATENCY_PRECISION_16;
744 else
745 *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 :
746 DRAIN_LATENCY_PRECISION_32;
0948c265 747 *drain_latency = (64 * (*prec_mult) * 4) / entries;
b445e3b0 748
a398e9c7
GB
749 if (*drain_latency > DRAIN_LATENCY_MASK)
750 *drain_latency = DRAIN_LATENCY_MASK;
b445e3b0
ED
751
752 return true;
753}
754
755/*
756 * Update drain latency registers of memory arbiter
757 *
758 * Valleyview SoC has a new memory arbiter and needs drain latency registers
759 * to be programmed. Each plane has a drain latency multiplier and a drain
760 * latency value.
761 */
762
41aad816 763static void vlv_update_drain_latency(struct drm_crtc *crtc)
b445e3b0 764{
5e56ba45
RV
765 struct drm_device *dev = crtc->dev;
766 struct drm_i915_private *dev_priv = dev->dev_private;
0948c265
GB
767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
768 int pixel_size;
769 int drain_latency;
770 enum pipe pipe = intel_crtc->pipe;
771 int plane_prec, prec_mult, plane_dl;
5e56ba45
RV
772 const int high_precision = IS_CHERRYVIEW(dev) ?
773 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
b445e3b0 774
5e56ba45
RV
775 plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH |
776 DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH |
0948c265
GB
777 (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT));
778
779 if (!intel_crtc_active(crtc)) {
780 I915_WRITE(VLV_DDL(pipe), plane_dl);
781 return;
782 }
b445e3b0 783
0948c265
GB
784 /* Primary plane Drain Latency */
785 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
786 if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
5e56ba45
RV
787 plane_prec = (prec_mult == high_precision) ?
788 DDL_PLANE_PRECISION_HIGH :
789 DDL_PLANE_PRECISION_LOW;
0948c265 790 plane_dl |= plane_prec | drain_latency;
b445e3b0
ED
791 }
792
0948c265
GB
793 /* Cursor Drain Latency
794 * BPP is always 4 for cursor
795 */
796 pixel_size = 4;
b445e3b0 797
0948c265
GB
798 /* Program cursor DL only if it is enabled */
799 if (intel_crtc->cursor_base &&
800 vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) {
5e56ba45
RV
801 plane_prec = (prec_mult == high_precision) ?
802 DDL_CURSOR_PRECISION_HIGH :
803 DDL_CURSOR_PRECISION_LOW;
0948c265 804 plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT);
b445e3b0 805 }
0948c265
GB
806
807 I915_WRITE(VLV_DDL(pipe), plane_dl);
b445e3b0
ED
808}
809
810#define single_plane_enabled(mask) is_power_of_2(mask)
811
46ba614c 812static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 813{
46ba614c 814 struct drm_device *dev = crtc->dev;
b445e3b0
ED
815 static const int sr_latency_ns = 12000;
816 struct drm_i915_private *dev_priv = dev->dev_private;
817 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
818 int plane_sr, cursor_sr;
af6c4575 819 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0 820 unsigned int enabled = 0;
9858425c 821 bool cxsr_enabled;
b445e3b0 822
41aad816 823 vlv_update_drain_latency(crtc);
b445e3b0 824
51cea1f4 825 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW
826 &valleyview_wm_info, pessimal_latency_ns,
827 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 828 &planea_wm, &cursora_wm))
51cea1f4 829 enabled |= 1 << PIPE_A;
b445e3b0 830
51cea1f4 831 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW
832 &valleyview_wm_info, pessimal_latency_ns,
833 &valleyview_cursor_wm_info, pessimal_latency_ns,
b445e3b0 834 &planeb_wm, &cursorb_wm))
51cea1f4 835 enabled |= 1 << PIPE_B;
b445e3b0 836
b445e3b0
ED
837 if (single_plane_enabled(enabled) &&
838 g4x_compute_srwm(dev, ffs(enabled) - 1,
839 sr_latency_ns,
840 &valleyview_wm_info,
841 &valleyview_cursor_wm_info,
af6c4575
CW
842 &plane_sr, &ignore_cursor_sr) &&
843 g4x_compute_srwm(dev, ffs(enabled) - 1,
844 2*sr_latency_ns,
845 &valleyview_wm_info,
846 &valleyview_cursor_wm_info,
52bd02d8 847 &ignore_plane_sr, &cursor_sr)) {
9858425c 848 cxsr_enabled = true;
52bd02d8 849 } else {
9858425c 850 cxsr_enabled = false;
5209b1f4 851 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW
852 plane_sr = cursor_sr = 0;
853 }
b445e3b0 854
a5043453
VS
855 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
856 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED
857 planea_wm, cursora_wm,
858 planeb_wm, cursorb_wm,
859 plane_sr, cursor_sr);
860
861 I915_WRITE(DSPFW1,
862 (plane_sr << DSPFW_SR_SHIFT) |
863 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
864 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 865 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 866 I915_WRITE(DSPFW2,
8c919b28 867 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED
868 (cursora_wm << DSPFW_CURSORA_SHIFT));
869 I915_WRITE(DSPFW3,
8c919b28
CW
870 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
871 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID
872
873 if (cxsr_enabled)
874 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED
875}
876
3c2777fd
VS
877static void cherryview_update_wm(struct drm_crtc *crtc)
878{
879 struct drm_device *dev = crtc->dev;
880 static const int sr_latency_ns = 12000;
881 struct drm_i915_private *dev_priv = dev->dev_private;
882 int planea_wm, planeb_wm, planec_wm;
883 int cursora_wm, cursorb_wm, cursorc_wm;
884 int plane_sr, cursor_sr;
885 int ignore_plane_sr, ignore_cursor_sr;
886 unsigned int enabled = 0;
887 bool cxsr_enabled;
888
889 vlv_update_drain_latency(crtc);
890
891 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW
892 &valleyview_wm_info, pessimal_latency_ns,
893 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS
894 &planea_wm, &cursora_wm))
895 enabled |= 1 << PIPE_A;
896
897 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW
898 &valleyview_wm_info, pessimal_latency_ns,
899 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS
900 &planeb_wm, &cursorb_wm))
901 enabled |= 1 << PIPE_B;
902
903 if (g4x_compute_wm0(dev, PIPE_C,
5aef6003
CW
904 &valleyview_wm_info, pessimal_latency_ns,
905 &valleyview_cursor_wm_info, pessimal_latency_ns,
3c2777fd
VS
906 &planec_wm, &cursorc_wm))
907 enabled |= 1 << PIPE_C;
908
909 if (single_plane_enabled(enabled) &&
910 g4x_compute_srwm(dev, ffs(enabled) - 1,
911 sr_latency_ns,
912 &valleyview_wm_info,
913 &valleyview_cursor_wm_info,
914 &plane_sr, &ignore_cursor_sr) &&
915 g4x_compute_srwm(dev, ffs(enabled) - 1,
916 2*sr_latency_ns,
917 &valleyview_wm_info,
918 &valleyview_cursor_wm_info,
919 &ignore_plane_sr, &cursor_sr)) {
920 cxsr_enabled = true;
921 } else {
922 cxsr_enabled = false;
923 intel_set_memory_cxsr(dev_priv, false);
924 plane_sr = cursor_sr = 0;
925 }
926
927 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
928 "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, "
929 "SR: plane=%d, cursor=%d\n",
930 planea_wm, cursora_wm,
931 planeb_wm, cursorb_wm,
932 planec_wm, cursorc_wm,
933 plane_sr, cursor_sr);
934
935 I915_WRITE(DSPFW1,
936 (plane_sr << DSPFW_SR_SHIFT) |
937 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
938 (planeb_wm << DSPFW_PLANEB_SHIFT) |
939 (planea_wm << DSPFW_PLANEA_SHIFT));
940 I915_WRITE(DSPFW2,
941 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
942 (cursora_wm << DSPFW_CURSORA_SHIFT));
943 I915_WRITE(DSPFW3,
944 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
945 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
946 I915_WRITE(DSPFW9_CHV,
947 (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK |
948 DSPFW_CURSORC_MASK)) |
949 (planec_wm << DSPFW_PLANEC_SHIFT) |
950 (cursorc_wm << DSPFW_CURSORC_SHIFT));
951
952 if (cxsr_enabled)
953 intel_set_memory_cxsr(dev_priv, true);
954}
955
01e184cc
GB
956static void valleyview_update_sprite_wm(struct drm_plane *plane,
957 struct drm_crtc *crtc,
958 uint32_t sprite_width,
959 uint32_t sprite_height,
960 int pixel_size,
961 bool enabled, bool scaled)
962{
963 struct drm_device *dev = crtc->dev;
964 struct drm_i915_private *dev_priv = dev->dev_private;
965 int pipe = to_intel_plane(plane)->pipe;
966 int sprite = to_intel_plane(plane)->plane;
967 int drain_latency;
968 int plane_prec;
969 int sprite_dl;
970 int prec_mult;
5e56ba45
RV
971 const int high_precision = IS_CHERRYVIEW(dev) ?
972 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64;
01e184cc 973
5e56ba45 974 sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) |
01e184cc
GB
975 (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite)));
976
977 if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult,
978 &drain_latency)) {
5e56ba45
RV
979 plane_prec = (prec_mult == high_precision) ?
980 DDL_SPRITE_PRECISION_HIGH(sprite) :
981 DDL_SPRITE_PRECISION_LOW(sprite);
01e184cc
GB
982 sprite_dl |= plane_prec |
983 (drain_latency << DDL_SPRITE_SHIFT(sprite));
984 }
985
986 I915_WRITE(VLV_DDL(pipe), sprite_dl);
987}
988
46ba614c 989static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 990{
46ba614c 991 struct drm_device *dev = crtc->dev;
b445e3b0
ED
992 static const int sr_latency_ns = 12000;
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
995 int plane_sr, cursor_sr;
996 unsigned int enabled = 0;
9858425c 997 bool cxsr_enabled;
b445e3b0 998
51cea1f4 999 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW
1000 &g4x_wm_info, pessimal_latency_ns,
1001 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1002 &planea_wm, &cursora_wm))
51cea1f4 1003 enabled |= 1 << PIPE_A;
b445e3b0 1004
51cea1f4 1005 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW
1006 &g4x_wm_info, pessimal_latency_ns,
1007 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1008 &planeb_wm, &cursorb_wm))
51cea1f4 1009 enabled |= 1 << PIPE_B;
b445e3b0 1010
b445e3b0
ED
1011 if (single_plane_enabled(enabled) &&
1012 g4x_compute_srwm(dev, ffs(enabled) - 1,
1013 sr_latency_ns,
1014 &g4x_wm_info,
1015 &g4x_cursor_wm_info,
52bd02d8 1016 &plane_sr, &cursor_sr)) {
9858425c 1017 cxsr_enabled = true;
52bd02d8 1018 } else {
9858425c 1019 cxsr_enabled = false;
5209b1f4 1020 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW
1021 plane_sr = cursor_sr = 0;
1022 }
b445e3b0 1023
a5043453
VS
1024 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1025 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED
1026 planea_wm, cursora_wm,
1027 planeb_wm, cursorb_wm,
1028 plane_sr, cursor_sr);
1029
1030 I915_WRITE(DSPFW1,
1031 (plane_sr << DSPFW_SR_SHIFT) |
1032 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1033 (planeb_wm << DSPFW_PLANEB_SHIFT) |
0a560674 1034 (planea_wm << DSPFW_PLANEA_SHIFT));
b445e3b0 1035 I915_WRITE(DSPFW2,
8c919b28 1036 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED
1037 (cursora_wm << DSPFW_CURSORA_SHIFT));
1038 /* HPLL off in SR has some issues on G4x... disable it */
1039 I915_WRITE(DSPFW3,
8c919b28 1040 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0 1041 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID
1042
1043 if (cxsr_enabled)
1044 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED
1045}
1046
46ba614c 1047static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1048{
46ba614c 1049 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
1050 struct drm_i915_private *dev_priv = dev->dev_private;
1051 struct drm_crtc *crtc;
1052 int srwm = 1;
1053 int cursor_sr = 16;
9858425c 1054 bool cxsr_enabled;
b445e3b0
ED
1055
1056 /* Calc sr entries for one plane configs */
1057 crtc = single_enabled_crtc(dev);
1058 if (crtc) {
1059 /* self-refresh has much higher latency */
1060 static const int sr_latency_ns = 12000;
4fe8590a
VS
1061 const struct drm_display_mode *adjusted_mode =
1062 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1063 int clock = adjusted_mode->crtc_clock;
fec8cba3 1064 int htotal = adjusted_mode->crtc_htotal;
37327abd 1065 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1066 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED
1067 unsigned long line_time_us;
1068 int entries;
1069
922044c9 1070 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED
1071
1072 /* Use ns/us then divide to preserve precision */
1073 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1074 pixel_size * hdisplay;
1075 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1076 srwm = I965_FIFO_SIZE - entries;
1077 if (srwm < 0)
1078 srwm = 1;
1079 srwm &= 0x1ff;
1080 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1081 entries, srwm);
1082
1083 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1084 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED
1085 entries = DIV_ROUND_UP(entries,
1086 i965_cursor_wm_info.cacheline_size);
1087 cursor_sr = i965_cursor_wm_info.fifo_size -
1088 (entries + i965_cursor_wm_info.guard_size);
1089
1090 if (cursor_sr > i965_cursor_wm_info.max_wm)
1091 cursor_sr = i965_cursor_wm_info.max_wm;
1092
1093 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1094 "cursor %d\n", srwm, cursor_sr);
1095
9858425c 1096 cxsr_enabled = true;
b445e3b0 1097 } else {
9858425c 1098 cxsr_enabled = false;
b445e3b0 1099 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1100 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED
1101 }
1102
1103 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1104 srwm);
1105
1106 /* 965 has limitations... */
1107 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
0a560674
VS
1108 (8 << DSPFW_CURSORB_SHIFT) |
1109 (8 << DSPFW_PLANEB_SHIFT) |
1110 (8 << DSPFW_PLANEA_SHIFT));
1111 I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
1112 (8 << DSPFW_PLANEC_SHIFT_OLD));
b445e3b0
ED
1113 /* update cursor SR watermark */
1114 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
9858425c
ID
1115
1116 if (cxsr_enabled)
1117 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED
1118}
1119
46ba614c 1120static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1121{
46ba614c 1122 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
1123 struct drm_i915_private *dev_priv = dev->dev_private;
1124 const struct intel_watermark_params *wm_info;
1125 uint32_t fwater_lo;
1126 uint32_t fwater_hi;
1127 int cwm, srwm = 1;
1128 int fifo_size;
1129 int planea_wm, planeb_wm;
1130 struct drm_crtc *crtc, *enabled = NULL;
1131
1132 if (IS_I945GM(dev))
1133 wm_info = &i945_wm_info;
1134 else if (!IS_GEN2(dev))
1135 wm_info = &i915_wm_info;
1136 else
9d539105 1137 wm_info = &i830_a_wm_info;
b445e3b0
ED
1138
1139 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1140 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1141 if (intel_crtc_active(crtc)) {
241bfc38 1142 const struct drm_display_mode *adjusted_mode;
f4510a27 1143 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW
1144 if (IS_GEN2(dev))
1145 cpp = 4;
1146
241bfc38
DL
1147 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1148 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1149 wm_info, fifo_size, cpp,
5aef6003 1150 pessimal_latency_ns);
b445e3b0 1151 enabled = crtc;
9d539105 1152 } else {
b445e3b0 1153 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS
1154 if (planea_wm > (long)wm_info->max_wm)
1155 planea_wm = wm_info->max_wm;
1156 }
1157
1158 if (IS_GEN2(dev))
1159 wm_info = &i830_bc_wm_info;
b445e3b0
ED
1160
1161 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1162 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1163 if (intel_crtc_active(crtc)) {
241bfc38 1164 const struct drm_display_mode *adjusted_mode;
f4510a27 1165 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW
1166 if (IS_GEN2(dev))
1167 cpp = 4;
1168
241bfc38
DL
1169 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1170 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1171 wm_info, fifo_size, cpp,
5aef6003 1172 pessimal_latency_ns);
b445e3b0
ED
1173 if (enabled == NULL)
1174 enabled = crtc;
1175 else
1176 enabled = NULL;
9d539105 1177 } else {
b445e3b0 1178 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS
1179 if (planeb_wm > (long)wm_info->max_wm)
1180 planeb_wm = wm_info->max_wm;
1181 }
b445e3b0
ED
1182
1183 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1184
2ab1bc9d 1185 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1186 struct drm_i915_gem_object *obj;
2ab1bc9d 1187
2ff8fde1 1188 obj = intel_fb_obj(enabled->primary->fb);
2ab1bc9d
DV
1189
1190 /* self-refresh seems busted with untiled */
2ff8fde1 1191 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV
1192 enabled = NULL;
1193 }
1194
b445e3b0
ED
1195 /*
1196 * Overlay gets an aggressive default since video jitter is bad.
1197 */
1198 cwm = 2;
1199
1200 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1201 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED
1202
1203 /* Calc sr entries for one plane configs */
1204 if (HAS_FW_BLC(dev) && enabled) {
1205 /* self-refresh has much higher latency */
1206 static const int sr_latency_ns = 6000;
4fe8590a
VS
1207 const struct drm_display_mode *adjusted_mode =
1208 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1209 int clock = adjusted_mode->crtc_clock;
fec8cba3 1210 int htotal = adjusted_mode->crtc_htotal;
f727b490 1211 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1212 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED
1213 unsigned long line_time_us;
1214 int entries;
1215
922044c9 1216 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED
1217
1218 /* Use ns/us then divide to preserve precision */
1219 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1220 pixel_size * hdisplay;
1221 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1222 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1223 srwm = wm_info->fifo_size - entries;
1224 if (srwm < 0)
1225 srwm = 1;
1226
1227 if (IS_I945G(dev) || IS_I945GM(dev))
1228 I915_WRITE(FW_BLC_SELF,
1229 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1230 else if (IS_I915GM(dev))
1231 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1232 }
1233
1234 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1235 planea_wm, planeb_wm, cwm, srwm);
1236
1237 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1238 fwater_hi = (cwm & 0x1f);
1239
1240 /* Set request length to 8 cachelines per fetch */
1241 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1242 fwater_hi = fwater_hi | (1 << 8);
1243
1244 I915_WRITE(FW_BLC, fwater_lo);
1245 I915_WRITE(FW_BLC2, fwater_hi);
1246
5209b1f4
ID
1247 if (enabled)
1248 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED
1249}
1250
feb56b93 1251static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1252{
46ba614c 1253 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
1254 struct drm_i915_private *dev_priv = dev->dev_private;
1255 struct drm_crtc *crtc;
241bfc38 1256 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED
1257 uint32_t fwater_lo;
1258 int planea_wm;
1259
1260 crtc = single_enabled_crtc(dev);
1261 if (crtc == NULL)
1262 return;
1263
241bfc38
DL
1264 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1265 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1266 &i845_wm_info,
b445e3b0 1267 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1268 4, pessimal_latency_ns);
b445e3b0
ED
1269 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1270 fwater_lo |= (3<<8) | planea_wm;
1271
1272 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1273
1274 I915_WRITE(FW_BLC, fwater_lo);
1275}
1276
3658729a
VS
1277static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1278 struct drm_crtc *crtc)
801bcfff
PZ
1279{
1280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1281 uint32_t pixel_rate;
801bcfff 1282
241bfc38 1283 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ
1284
1285 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1286 * adjust the pixel_rate here. */
1287
fd4daa9c 1288 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1289 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1290 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1291
37327abd
VS
1292 pipe_w = intel_crtc->config.pipe_src_w;
1293 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ
1294 pfit_w = (pfit_size >> 16) & 0xFFFF;
1295 pfit_h = pfit_size & 0xFFFF;
1296 if (pipe_w < pfit_w)
1297 pipe_w = pfit_w;
1298 if (pipe_h < pfit_h)
1299 pipe_h = pfit_h;
1300
1301 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1302 pfit_w * pfit_h);
1303 }
1304
1305 return pixel_rate;
1306}
1307
37126462 1308/* latency must be in 0.1us units. */
23297044 1309static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ
1310 uint32_t latency)
1311{
1312 uint64_t ret;
1313
3312ba65
VS
1314 if (WARN(latency == 0, "Latency value missing\n"))
1315 return UINT_MAX;
1316
801bcfff
PZ
1317 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1318 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1319
1320 return ret;
1321}
1322
37126462 1323/* latency must be in 0.1us units. */
23297044 1324static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ
1325 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1326 uint32_t latency)
1327{
1328 uint32_t ret;
1329
3312ba65
VS
1330 if (WARN(latency == 0, "Latency value missing\n"))
1331 return UINT_MAX;
1332
801bcfff
PZ
1333 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1334 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1335 ret = DIV_ROUND_UP(ret, 64) + 2;
1336 return ret;
1337}
1338
23297044 1339static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ
1340 uint8_t bytes_per_pixel)
1341{
1342 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1343}
1344
2ac96d2a
PB
1345struct skl_pipe_wm_parameters {
1346 bool active;
1347 uint32_t pipe_htotal;
1348 uint32_t pixel_rate; /* in KHz */
1349 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1350 struct intel_plane_wm_parameters cursor;
1351};
1352
820c1980 1353struct ilk_pipe_wm_parameters {
801bcfff 1354 bool active;
801bcfff
PZ
1355 uint32_t pipe_htotal;
1356 uint32_t pixel_rate;
c35426d2
VS
1357 struct intel_plane_wm_parameters pri;
1358 struct intel_plane_wm_parameters spr;
1359 struct intel_plane_wm_parameters cur;
801bcfff
PZ
1360};
1361
820c1980 1362struct ilk_wm_maximums {
cca32e9a
PZ
1363 uint16_t pri;
1364 uint16_t spr;
1365 uint16_t cur;
1366 uint16_t fbc;
1367};
1368
240264f4
VS
1369/* used in computing the new watermarks state */
1370struct intel_wm_config {
1371 unsigned int num_pipes_active;
1372 bool sprites_enabled;
1373 bool sprites_scaled;
240264f4
VS
1374};
1375
37126462
VS
1376/*
1377 * For both WM_PIPE and WM_LP.
1378 * mem_value must be in 0.1us units.
1379 */
820c1980 1380static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ
1381 uint32_t mem_value,
1382 bool is_lp)
801bcfff 1383{
cca32e9a
PZ
1384 uint32_t method1, method2;
1385
c35426d2 1386 if (!params->active || !params->pri.enabled)
801bcfff
PZ
1387 return 0;
1388
23297044 1389 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1390 params->pri.bytes_per_pixel,
cca32e9a
PZ
1391 mem_value);
1392
1393 if (!is_lp)
1394 return method1;
1395
23297044 1396 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1397 params->pipe_htotal,
c35426d2
VS
1398 params->pri.horiz_pixels,
1399 params->pri.bytes_per_pixel,
cca32e9a
PZ
1400 mem_value);
1401
1402 return min(method1, method2);
801bcfff
PZ
1403}
1404
37126462
VS
1405/*
1406 * For both WM_PIPE and WM_LP.
1407 * mem_value must be in 0.1us units.
1408 */
820c1980 1409static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ
1410 uint32_t mem_value)
1411{
1412 uint32_t method1, method2;
1413
c35426d2 1414 if (!params->active || !params->spr.enabled)
801bcfff
PZ
1415 return 0;
1416
23297044 1417 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1418 params->spr.bytes_per_pixel,
801bcfff 1419 mem_value);
23297044 1420 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1421 params->pipe_htotal,
c35426d2
VS
1422 params->spr.horiz_pixels,
1423 params->spr.bytes_per_pixel,
801bcfff
PZ
1424 mem_value);
1425 return min(method1, method2);
1426}
1427
37126462
VS
1428/*
1429 * For both WM_PIPE and WM_LP.
1430 * mem_value must be in 0.1us units.
1431 */
820c1980 1432static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ
1433 uint32_t mem_value)
1434{
c35426d2 1435 if (!params->active || !params->cur.enabled)
801bcfff
PZ
1436 return 0;
1437
23297044 1438 return ilk_wm_method2(params->pixel_rate,
801bcfff 1439 params->pipe_htotal,
c35426d2
VS
1440 params->cur.horiz_pixels,
1441 params->cur.bytes_per_pixel,
801bcfff
PZ
1442 mem_value);
1443}
1444
cca32e9a 1445/* Only for WM_LP. */
820c1980 1446static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1447 uint32_t pri_val)
cca32e9a 1448{
c35426d2 1449 if (!params->active || !params->pri.enabled)
cca32e9a
PZ
1450 return 0;
1451
23297044 1452 return ilk_wm_fbc(pri_val,
c35426d2
VS
1453 params->pri.horiz_pixels,
1454 params->pri.bytes_per_pixel);
cca32e9a
PZ
1455}
1456
158ae64f
VS
1457static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1458{
416f4727
VS
1459 if (INTEL_INFO(dev)->gen >= 8)
1460 return 3072;
1461 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS
1462 return 768;
1463 else
1464 return 512;
1465}
1466
4e975081
VS
1467static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1468 int level, bool is_sprite)
1469{
1470 if (INTEL_INFO(dev)->gen >= 8)
1471 /* BDW primary/sprite plane watermarks */
1472 return level == 0 ? 255 : 2047;
1473 else if (INTEL_INFO(dev)->gen >= 7)
1474 /* IVB/HSW primary/sprite plane watermarks */
1475 return level == 0 ? 127 : 1023;
1476 else if (!is_sprite)
1477 /* ILK/SNB primary plane watermarks */
1478 return level == 0 ? 127 : 511;
1479 else
1480 /* ILK/SNB sprite plane watermarks */
1481 return level == 0 ? 63 : 255;
1482}
1483
1484static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1485 int level)
1486{
1487 if (INTEL_INFO(dev)->gen >= 7)
1488 return level == 0 ? 63 : 255;
1489 else
1490 return level == 0 ? 31 : 63;
1491}
1492
1493static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1494{
1495 if (INTEL_INFO(dev)->gen >= 8)
1496 return 31;
1497 else
1498 return 15;
1499}
1500
158ae64f
VS
1501/* Calculate the maximum primary/sprite plane watermark */
1502static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1503 int level,
240264f4 1504 const struct intel_wm_config *config,
158ae64f
VS
1505 enum intel_ddb_partitioning ddb_partitioning,
1506 bool is_sprite)
1507{
1508 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS
1509
1510 /* if sprites aren't enabled, sprites get nothing */
240264f4 1511 if (is_sprite && !config->sprites_enabled)
158ae64f
VS
1512 return 0;
1513
1514 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1515 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS
1516 fifo_size /= INTEL_INFO(dev)->num_pipes;
1517
1518 /*
1519 * For some reason the non self refresh
1520 * FIFO size is only half of the self
1521 * refresh FIFO size on ILK/SNB.
1522 */
1523 if (INTEL_INFO(dev)->gen <= 6)
1524 fifo_size /= 2;
1525 }
1526
240264f4 1527 if (config->sprites_enabled) {
158ae64f
VS
1528 /* level 0 is always calculated with 1:1 split */
1529 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1530 if (is_sprite)
1531 fifo_size *= 5;
1532 fifo_size /= 6;
1533 } else {
1534 fifo_size /= 2;
1535 }
1536 }
1537
1538 /* clamp to max that the registers can hold */
4e975081 1539 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS
1540}
1541
1542/* Calculate the maximum cursor plane watermark */
1543static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS
1544 int level,
1545 const struct intel_wm_config *config)
158ae64f
VS
1546{
1547 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1548 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS
1549 return 64;
1550
1551 /* otherwise just report max that registers can hold */
4e975081 1552 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS
1553}
1554
d34ff9c6 1555static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS
1556 int level,
1557 const struct intel_wm_config *config,
1558 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1559 struct ilk_wm_maximums *max)
158ae64f 1560{
240264f4
VS
1561 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1562 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1563 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1564 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS
1565}
1566
a3cb4048
VS
1567static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1568 int level,
1569 struct ilk_wm_maximums *max)
1570{
1571 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1572 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1573 max->cur = ilk_cursor_wm_reg_max(dev, level);
1574 max->fbc = ilk_fbc_wm_reg_max(dev);
1575}
1576
d9395655 1577static bool ilk_validate_wm_level(int level,
820c1980 1578 const struct ilk_wm_maximums *max,
d9395655 1579 struct intel_wm_level *result)
a9786a11
VS
1580{
1581 bool ret;
1582
1583 /* already determined to be invalid? */
1584 if (!result->enable)
1585 return false;
1586
1587 result->enable = result->pri_val <= max->pri &&
1588 result->spr_val <= max->spr &&
1589 result->cur_val <= max->cur;
1590
1591 ret = result->enable;
1592
1593 /*
1594 * HACK until we can pre-compute everything,
1595 * and thus fail gracefully if LP0 watermarks
1596 * are exceeded...
1597 */
1598 if (level == 0 && !result->enable) {
1599 if (result->pri_val > max->pri)
1600 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1601 level, result->pri_val, max->pri);
1602 if (result->spr_val > max->spr)
1603 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1604 level, result->spr_val, max->spr);
1605 if (result->cur_val > max->cur)
1606 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1607 level, result->cur_val, max->cur);
1608
1609 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1610 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1611 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1612 result->enable = true;
1613 }
1614
a9786a11
VS
1615 return ret;
1616}
1617
d34ff9c6 1618static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1619 int level,
820c1980 1620 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1621 struct intel_wm_level *result)
6f5ddd17
VS
1622{
1623 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1624 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1625 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1626
1627 /* WM1+ latency values stored in 0.5us units */
1628 if (level > 0) {
1629 pri_latency *= 5;
1630 spr_latency *= 5;
1631 cur_latency *= 5;
1632 }
1633
1634 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1635 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1636 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1637 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1638 result->enable = true;
1639}
1640
801bcfff
PZ
1641static uint32_t
1642hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED
1643{
1644 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 1646 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 1647 u32 linetime, ips_linetime;
1f8eeabf 1648
801bcfff
PZ
1649 if (!intel_crtc_active(crtc))
1650 return 0;
1011d8c4 1651
1f8eeabf
ED
1652 /* The WM are computed with base on how long it takes to fill a single
1653 * row at the given clock rate, multiplied by 8.
1654 * */
fec8cba3
JB
1655 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1656 mode->crtc_clock);
1657 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 1658 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 1659
801bcfff
PZ
1660 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1661 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED
1662}
1663
2af30a5c 1664static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS
1665{
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667
2af30a5c
PB
1668 if (IS_GEN9(dev)) {
1669 uint32_t val;
4f947386 1670 int ret, i;
367294be 1671 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB
1672
1673 /* read the first set of memory latencies[0:3] */
1674 val = 0; /* data0 to be programmed to 0 for first set */
1675 mutex_lock(&dev_priv->rps.hw_lock);
1676 ret = sandybridge_pcode_read(dev_priv,
1677 GEN9_PCODE_READ_MEM_LATENCY,
1678 &val);
1679 mutex_unlock(&dev_priv->rps.hw_lock);
1680
1681 if (ret) {
1682 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1683 return;
1684 }
1685
1686 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1687 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1688 GEN9_MEM_LATENCY_LEVEL_MASK;
1689 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1690 GEN9_MEM_LATENCY_LEVEL_MASK;
1691 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1692 GEN9_MEM_LATENCY_LEVEL_MASK;
1693
1694 /* read the second set of memory latencies[4:7] */
1695 val = 1; /* data0 to be programmed to 1 for second set */
1696 mutex_lock(&dev_priv->rps.hw_lock);
1697 ret = sandybridge_pcode_read(dev_priv,
1698 GEN9_PCODE_READ_MEM_LATENCY,
1699 &val);
1700 mutex_unlock(&dev_priv->rps.hw_lock);
1701 if (ret) {
1702 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1703 return;
1704 }
1705
1706 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1707 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1708 GEN9_MEM_LATENCY_LEVEL_MASK;
1709 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1710 GEN9_MEM_LATENCY_LEVEL_MASK;
1711 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1712 GEN9_MEM_LATENCY_LEVEL_MASK;
1713
367294be
VK
1714 /*
1715 * punit doesn't take into account the read latency so we need
1716 * to add 2us to the various latency levels we retrieve from
1717 * the punit.
1718 * - W0 is a bit special in that it's the only level that
1719 * can't be disabled if we want to have display working, so
1720 * we always add 2us there.
1721 * - For levels >=1, punit returns 0us latency when they are
1722 * disabled, so we respect that and don't add 2us then
4f947386
VK
1723 *
1724 * Additionally, if a level n (n > 1) has a 0us latency, all
1725 * levels m (m >= n) need to be disabled. We make sure to
1726 * sanitize the values out of the punit to satisfy this
1727 * requirement.
367294be
VK
1728 */
1729 wm[0] += 2;
1730 for (level = 1; level <= max_level; level++)
1731 if (wm[level] != 0)
1732 wm[level] += 2;
4f947386
VK
1733 else {
1734 for (i = level + 1; i <= max_level; i++)
1735 wm[i] = 0;
367294be 1736
4f947386
VK
1737 break;
1738 }
2af30a5c 1739 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS
1740 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1741
1742 wm[0] = (sskpd >> 56) & 0xFF;
1743 if (wm[0] == 0)
1744 wm[0] = sskpd & 0xF;
e5d5019e
VS
1745 wm[1] = (sskpd >> 4) & 0xFF;
1746 wm[2] = (sskpd >> 12) & 0xFF;
1747 wm[3] = (sskpd >> 20) & 0x1FF;
1748 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS
1749 } else if (INTEL_INFO(dev)->gen >= 6) {
1750 uint32_t sskpd = I915_READ(MCH_SSKPD);
1751
1752 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1753 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1754 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1755 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS
1756 } else if (INTEL_INFO(dev)->gen >= 5) {
1757 uint32_t mltr = I915_READ(MLTR_ILK);
1758
1759 /* ILK primary LP0 latency is 700 ns */
1760 wm[0] = 7;
1761 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1762 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS
1763 }
1764}
1765
53615a5e
VS
1766static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1767{
1768 /* ILK sprite LP0 latency is 1300 ns */
1769 if (INTEL_INFO(dev)->gen == 5)
1770 wm[0] = 13;
1771}
1772
1773static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1774{
1775 /* ILK cursor LP0 latency is 1300 ns */
1776 if (INTEL_INFO(dev)->gen == 5)
1777 wm[0] = 13;
1778
1779 /* WaDoubleCursorLP3Latency:ivb */
1780 if (IS_IVYBRIDGE(dev))
1781 wm[3] *= 2;
1782}
1783
546c81fd 1784int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1785{
26ec971e 1786 /* how many WM levels are we expecting */
2af30a5c
PB
1787 if (IS_GEN9(dev))
1788 return 7;
1789 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1790 return 4;
26ec971e 1791 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1792 return 3;
26ec971e 1793 else
ad0d6dc4
VS
1794 return 2;
1795}
7526ed79 1796
ad0d6dc4
VS
1797static void intel_print_wm_latency(struct drm_device *dev,
1798 const char *name,
2af30a5c 1799 const uint16_t wm[8])
ad0d6dc4
VS
1800{
1801 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS
1802
1803 for (level = 0; level <= max_level; level++) {
1804 unsigned int latency = wm[level];
1805
1806 if (latency == 0) {
1807 DRM_ERROR("%s WM%d latency not provided\n",
1808 name, level);
1809 continue;
1810 }
1811
2af30a5c
PB
1812 /*
1813 * - latencies are in us on gen9.
1814 * - before then, WM1+ latency values are in 0.5us units
1815 */
1816 if (IS_GEN9(dev))
1817 latency *= 10;
1818 else if (level > 0)
26ec971e
VS
1819 latency *= 5;
1820
1821 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1822 name, level, wm[level],
1823 latency / 10, latency % 10);
1824 }
1825}
1826
e95a2f75
VS
1827static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1828 uint16_t wm[5], uint16_t min)
1829{
1830 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1831
1832 if (wm[0] >= min)
1833 return false;
1834
1835 wm[0] = max(wm[0], min);
1836 for (level = 1; level <= max_level; level++)
1837 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1838
1839 return true;
1840}
1841
1842static void snb_wm_latency_quirk(struct drm_device *dev)
1843{
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 bool changed;
1846
1847 /*
1848 * The BIOS provided WM memory latency values are often
1849 * inadequate for high resolution displays. Adjust them.
1850 */
1851 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1852 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1853 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1854
1855 if (!changed)
1856 return;
1857
1858 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
1859 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1860 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
1861 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
1862}
1863
fa50ad61 1864static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS
1865{
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867
1868 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
1869
1870 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
1871 sizeof(dev_priv->wm.pri_latency));
1872 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
1873 sizeof(dev_priv->wm.pri_latency));
1874
1875 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
1876 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS
1877
1878 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1879 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
1880 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS
1881
1882 if (IS_GEN6(dev))
1883 snb_wm_latency_quirk(dev);
53615a5e
VS
1884}
1885
2af30a5c
PB
1886static void skl_setup_wm_latency(struct drm_device *dev)
1887{
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889
1890 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
1891 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
1892}
1893
820c1980 1894static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 1895 struct ilk_pipe_wm_parameters *p)
1011d8c4 1896{
7c4a395f
VS
1897 struct drm_device *dev = crtc->dev;
1898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1899 enum pipe pipe = intel_crtc->pipe;
7c4a395f 1900 struct drm_plane *plane;
1011d8c4 1901
2a44b76b
VS
1902 if (!intel_crtc_active(crtc))
1903 return;
801bcfff 1904
2a44b76b
VS
1905 p->active = true;
1906 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
1907 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
1908 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
1909 p->cur.bytes_per_pixel = 4;
1910 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
1911 p->cur.horiz_pixels = intel_crtc->cursor_width;
1912 /* TODO: for now, assume primary and cursor planes are always enabled. */
1913 p->pri.enabled = true;
1914 p->cur.enabled = true;
7c4a395f 1915
af2b653b 1916 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 1917 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 1918
2a44b76b 1919 if (intel_plane->pipe == pipe) {
7c4a395f 1920 p->spr = intel_plane->wm;
2a44b76b
VS
1921 break;
1922 }
1923 }
1924}
1925
1926static void ilk_compute_wm_config(struct drm_device *dev,
1927 struct intel_wm_config *config)
1928{
1929 struct intel_crtc *intel_crtc;
1930
1931 /* Compute the currently _active_ config */
d3fcc808 1932 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 1933 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 1934
2a44b76b
VS
1935 if (!wm->pipe_enabled)
1936 continue;
cca32e9a 1937
2a44b76b
VS
1938 config->sprites_enabled |= wm->sprites_enabled;
1939 config->sprites_scaled |= wm->sprites_scaled;
1940 config->num_pipes_active++;
cca32e9a 1941 }
801bcfff
PZ
1942}
1943
0b2ae6d7
VS
1944/* Compute new watermarks for the pipe */
1945static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 1946 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS
1947 struct intel_pipe_wm *pipe_wm)
1948{
1949 struct drm_device *dev = crtc->dev;
d34ff9c6 1950 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS
1951 int level, max_level = ilk_wm_max_level(dev);
1952 /* LP0 watermark maximums depend on this pipe alone */
1953 struct intel_wm_config config = {
1954 .num_pipes_active = 1,
1955 .sprites_enabled = params->spr.enabled,
1956 .sprites_scaled = params->spr.scaled,
1957 };
820c1980 1958 struct ilk_wm_maximums max;
0b2ae6d7 1959
2a44b76b
VS
1960 pipe_wm->pipe_enabled = params->active;
1961 pipe_wm->sprites_enabled = params->spr.enabled;
1962 pipe_wm->sprites_scaled = params->spr.scaled;
1963
7b39a0b7
VS
1964 /* ILK/SNB: LP2+ watermarks only w/o sprites */
1965 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
1966 max_level = 1;
1967
1968 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
1969 if (params->spr.scaled)
1970 max_level = 0;
1971
a3cb4048 1972 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 1973
a42a5719 1974 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 1975 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 1976
a3cb4048
VS
1977 /* LP0 watermarks always use 1/2 DDB partitioning */
1978 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
1979
0b2ae6d7 1980 /* At least LP0 must be valid */
a3cb4048
VS
1981 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
1982 return false;
1983
1984 ilk_compute_wm_reg_maximums(dev, 1, &max);
1985
1986 for (level = 1; level <= max_level; level++) {
1987 struct intel_wm_level wm = {};
1988
1989 ilk_compute_wm_level(dev_priv, level, params, &wm);
1990
1991 /*
1992 * Disable any watermark level that exceeds the
1993 * register maximums since such watermarks are
1994 * always invalid.
1995 */
1996 if (!ilk_validate_wm_level(level, &max, &wm))
1997 break;
1998
1999 pipe_wm->wm[level] = wm;
2000 }
2001
2002 return true;
0b2ae6d7
VS
2003}
2004
2005/*
2006 * Merge the watermarks from all active pipes for a specific level.
2007 */
2008static void ilk_merge_wm_level(struct drm_device *dev,
2009 int level,
2010 struct intel_wm_level *ret_wm)
2011{
2012 const struct intel_crtc *intel_crtc;
2013
d52fea5b
VS
2014 ret_wm->enable = true;
2015
d3fcc808 2016 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS
2017 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2018 const struct intel_wm_level *wm = &active->wm[level];
2019
2020 if (!active->pipe_enabled)
2021 continue;
0b2ae6d7 2022
d52fea5b
VS
2023 /*
2024 * The watermark values may have been used in the past,
2025 * so we must maintain them in the registers for some
2026 * time even if the level is now disabled.
2027 */
0b2ae6d7 2028 if (!wm->enable)
d52fea5b 2029 ret_wm->enable = false;
0b2ae6d7
VS
2030
2031 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2032 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2033 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2034 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2035 }
0b2ae6d7
VS
2036}
2037
2038/*
2039 * Merge all low power watermarks for all active pipes.
2040 */
2041static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2042 const struct intel_wm_config *config,
820c1980 2043 const struct ilk_wm_maximums *max,
0b2ae6d7
VS
2044 struct intel_pipe_wm *merged)
2045{
2046 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2047 int last_enabled_level = max_level;
0b2ae6d7 2048
0ba22e26
VS
2049 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2050 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2051 config->num_pipes_active > 1)
2052 return;
2053
6c8b6c28
VS
2054 /* ILK: FBC WM must be disabled always */
2055 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS
2056
2057 /* merge each WM1+ level */
2058 for (level = 1; level <= max_level; level++) {
2059 struct intel_wm_level *wm = &merged->wm[level];
2060
2061 ilk_merge_wm_level(dev, level, wm);
2062
d52fea5b
VS
2063 if (level > last_enabled_level)
2064 wm->enable = false;
2065 else if (!ilk_validate_wm_level(level, max, wm))
2066 /* make sure all following levels get disabled */
2067 last_enabled_level = level - 1;
0b2ae6d7
VS
2068
2069 /*
2070 * The spec says it is preferred to disable
2071 * FBC WMs instead of disabling a WM level.
2072 */
2073 if (wm->fbc_val > max->fbc) {
d52fea5b
VS
2074 if (wm->enable)
2075 merged->fbc_wm_enabled = false;
0b2ae6d7
VS
2076 wm->fbc_val = 0;
2077 }
2078 }
6c8b6c28
VS
2079
2080 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2081 /*
2082 * FIXME this is racy. FBC might get enabled later.
2083 * What we should check here is whether FBC can be
2084 * enabled sometime later.
2085 */
2086 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2087 for (level = 2; level <= max_level; level++) {
2088 struct intel_wm_level *wm = &merged->wm[level];
2089
2090 wm->enable = false;
2091 }
2092 }
0b2ae6d7
VS
2093}
2094
b380ca3c
VS
2095static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2096{
2097 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2098 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2099}
2100
a68d68ee
VS
2101/* The value we need to program into the WM_LPx latency field */
2102static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2103{
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105
a42a5719 2106 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS
2107 return 2 * level;
2108 else
2109 return dev_priv->wm.pri_latency[level];
2110}
2111
820c1980 2112static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2113 const struct intel_pipe_wm *merged,
609cedef 2114 enum intel_ddb_partitioning partitioning,
820c1980 2115 struct ilk_wm_values *results)
801bcfff 2116{
0b2ae6d7
VS
2117 struct intel_crtc *intel_crtc;
2118 int level, wm_lp;
cca32e9a 2119
0362c781 2120 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2121 results->partitioning = partitioning;
cca32e9a 2122
0b2ae6d7 2123 /* LP1+ register values */
cca32e9a 2124 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2125 const struct intel_wm_level *r;
801bcfff 2126
b380ca3c 2127 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2128
0362c781 2129 r = &merged->wm[level];
cca32e9a 2130
d52fea5b
VS
2131 /*
2132 * Maintain the watermark values even if the level is
2133 * disabled. Doing otherwise could cause underruns.
2134 */
2135 results->wm_lp[wm_lp - 1] =
a68d68ee 2136 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS
2137 (r->pri_val << WM1_LP_SR_SHIFT) |
2138 r->cur_val;
2139
d52fea5b
VS
2140 if (r->enable)
2141 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2142
416f4727
VS
2143 if (INTEL_INFO(dev)->gen >= 8)
2144 results->wm_lp[wm_lp - 1] |=
2145 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2146 else
2147 results->wm_lp[wm_lp - 1] |=
2148 r->fbc_val << WM1_LP_FBC_SHIFT;
2149
d52fea5b
VS
2150 /*
2151 * Always set WM1S_LP_EN when spr_val != 0, even if the
2152 * level is disabled. Doing otherwise could cause underruns.
2153 */
6cef2b8a
VS
2154 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2155 WARN_ON(wm_lp != 1);
2156 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2157 } else
2158 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2159 }
801bcfff 2160
0b2ae6d7 2161 /* LP0 register values */
d3fcc808 2162 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS
2163 enum pipe pipe = intel_crtc->pipe;
2164 const struct intel_wm_level *r =
2165 &intel_crtc->wm.active.wm[0];
2166
2167 if (WARN_ON(!r->enable))
2168 continue;
2169
2170 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2171
0b2ae6d7
VS
2172 results->wm_pipe[pipe] =
2173 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2174 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2175 r->cur_val;
801bcfff
PZ
2176 }
2177}
2178
861f3389
PZ
2179/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2180 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2181static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS
2182 struct intel_pipe_wm *r1,
2183 struct intel_pipe_wm *r2)
861f3389 2184{
198a1e9b
VS
2185 int level, max_level = ilk_wm_max_level(dev);
2186 int level1 = 0, level2 = 0;
861f3389 2187
198a1e9b
VS
2188 for (level = 1; level <= max_level; level++) {
2189 if (r1->wm[level].enable)
2190 level1 = level;
2191 if (r2->wm[level].enable)
2192 level2 = level;
861f3389
PZ
2193 }
2194
198a1e9b
VS
2195 if (level1 == level2) {
2196 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ
2197 return r2;
2198 else
2199 return r1;
198a1e9b 2200 } else if (level1 > level2) {
861f3389
PZ
2201 return r1;
2202 } else {
2203 return r2;
2204 }
2205}
2206
49a687c4
VS
2207/* dirty bits used to track which watermarks need changes */
2208#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2209#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2210#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2211#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2212#define WM_DIRTY_FBC (1 << 24)
2213#define WM_DIRTY_DDB (1 << 25)
2214
055e393f 2215static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID
2216 const struct ilk_wm_values *old,
2217 const struct ilk_wm_values *new)
49a687c4
VS
2218{
2219 unsigned int dirty = 0;
2220 enum pipe pipe;
2221 int wm_lp;
2222
055e393f 2223 for_each_pipe(dev_priv, pipe) {
49a687c4
VS
2224 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2225 dirty |= WM_DIRTY_LINETIME(pipe);
2226 /* Must disable LP1+ watermarks too */
2227 dirty |= WM_DIRTY_LP_ALL;
2228 }
2229
2230 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2231 dirty |= WM_DIRTY_PIPE(pipe);
2232 /* Must disable LP1+ watermarks too */
2233 dirty |= WM_DIRTY_LP_ALL;
2234 }
2235 }
2236
2237 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2238 dirty |= WM_DIRTY_FBC;
2239 /* Must disable LP1+ watermarks too */
2240 dirty |= WM_DIRTY_LP_ALL;
2241 }
2242
2243 if (old->partitioning != new->partitioning) {
2244 dirty |= WM_DIRTY_DDB;
2245 /* Must disable LP1+ watermarks too */
2246 dirty |= WM_DIRTY_LP_ALL;
2247 }
2248
2249 /* LP1+ watermarks already deemed dirty, no need to continue */
2250 if (dirty & WM_DIRTY_LP_ALL)
2251 return dirty;
2252
2253 /* Find the lowest numbered LP1+ watermark in need of an update... */
2254 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2255 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2256 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2257 break;
2258 }
2259
2260 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2261 for (; wm_lp <= 3; wm_lp++)
2262 dirty |= WM_DIRTY_LP(wm_lp);
2263
2264 return dirty;
2265}
2266
8553c18e
VS
2267static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2268 unsigned int dirty)
801bcfff 2269{
820c1980 2270 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2271 bool changed = false;
801bcfff 2272
facd619b
VS
2273 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2274 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2275 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2276 changed = true;
facd619b
VS
2277 }
2278 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2279 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2280 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2281 changed = true;
facd619b
VS
2282 }
2283 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2284 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2285 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2286 changed = true;
facd619b 2287 }
801bcfff 2288
facd619b
VS
2289 /*
2290 * Don't touch WM1S_LP_EN here.
2291 * Doing so could cause underruns.
2292 */
6cef2b8a 2293
8553c18e
VS
2294 return changed;
2295}
2296
2297/*
2298 * The spec says we shouldn't write when we don't need, because every write
2299 * causes WMs to be re-evaluated, expending some power.
2300 */
820c1980
ID
2301static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2302 struct ilk_wm_values *results)
8553c18e
VS
2303{
2304 struct drm_device *dev = dev_priv->dev;
820c1980 2305 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS
2306 unsigned int dirty;
2307 uint32_t val;
2308
055e393f 2309 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS
2310 if (!dirty)
2311 return;
2312
2313 _ilk_disable_lp_wm(dev_priv, dirty);
2314
49a687c4 2315 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2316 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2317 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2318 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2319 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ
2320 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2321
49a687c4 2322 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2323 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2324 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2325 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2326 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ
2327 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2328
49a687c4 2329 if (dirty & WM_DIRTY_DDB) {
a42a5719 2330 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS
2331 val = I915_READ(WM_MISC);
2332 if (results->partitioning == INTEL_DDB_PART_1_2)
2333 val &= ~WM_MISC_DATA_PARTITION_5_6;
2334 else
2335 val |= WM_MISC_DATA_PARTITION_5_6;
2336 I915_WRITE(WM_MISC, val);
2337 } else {
2338 val = I915_READ(DISP_ARB_CTL2);
2339 if (results->partitioning == INTEL_DDB_PART_1_2)
2340 val &= ~DISP_DATA_PARTITION_5_6;
2341 else
2342 val |= DISP_DATA_PARTITION_5_6;
2343 I915_WRITE(DISP_ARB_CTL2, val);
2344 }
1011d8c4
PZ
2345 }
2346
49a687c4 2347 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ
2348 val = I915_READ(DISP_ARB_CTL);
2349 if (results->enable_fbc_wm)
2350 val &= ~DISP_FBC_WM_DIS;
2351 else
2352 val |= DISP_FBC_WM_DIS;
2353 I915_WRITE(DISP_ARB_CTL, val);
2354 }
2355
954911eb
ID
2356 if (dirty & WM_DIRTY_LP(1) &&
2357 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2358 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2359
2360 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS
2361 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2362 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2363 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2364 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2365 }
801bcfff 2366
facd619b 2367 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2368 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2369 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2370 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2371 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2372 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS
2373
2374 dev_priv->wm.hw = *results;
801bcfff
PZ
2375}
2376
8553c18e
VS
2377static bool ilk_disable_lp_wm(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380
2381 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2382}
2383
b9cec075
DL
2384/*
2385 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2386 * different active planes.
2387 */
2388
2389#define SKL_DDB_SIZE 896 /* in blocks */
2390
2391static void
2392skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2393 struct drm_crtc *for_crtc,
2394 const struct intel_wm_config *config,
2395 const struct skl_pipe_wm_parameters *params,
2396 struct skl_ddb_entry *alloc /* out */)
2397{
2398 struct drm_crtc *crtc;
2399 unsigned int pipe_size, ddb_size;
2400 int nth_active_pipe;
2401
2402 if (!params->active) {
2403 alloc->start = 0;
2404 alloc->end = 0;
2405 return;
2406 }
2407
2408 ddb_size = SKL_DDB_SIZE;
2409
2410 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2411
2412 nth_active_pipe = 0;
2413 for_each_crtc(dev, crtc) {
2414 if (!intel_crtc_active(crtc))
2415 continue;
2416
2417 if (crtc == for_crtc)
2418 break;
2419
2420 nth_active_pipe++;
2421 }
2422
2423 pipe_size = ddb_size / config->num_pipes_active;
2424 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2425 alloc->end = alloc->start + pipe_size;
b9cec075
DL
2426}
2427
2428static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2429{
2430 if (config->num_pipes_active == 1)
2431 return 32;
2432
2433 return 8;
2434}
2435
a269c583
DL
2436static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2437{
2438 entry->start = reg & 0x3ff;
2439 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL
2440 if (entry->end)
2441 entry->end += 1;
a269c583
DL
2442}
2443
08db6652
DL
2444void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2445 struct skl_ddb_allocation *ddb /* out */)
a269c583
DL
2446{
2447 struct drm_device *dev = dev_priv->dev;
2448 enum pipe pipe;
2449 int plane;
2450 u32 val;
2451
2452 for_each_pipe(dev_priv, pipe) {
2453 for_each_plane(pipe, plane) {
2454 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2455 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2456 val);
2457 }
2458
2459 val = I915_READ(CUR_BUF_CFG(pipe));
2460 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2461 }
2462}
2463
b9cec075
DL
2464static unsigned int
2465skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2466{
2467 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2468}
2469
2470/*
2471 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2472 * a 8192x4096@32bpp framebuffer:
2473 * 3 * 4096 * 8192 * 4 < 2^32
2474 */
2475static unsigned int
2476skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2477 const struct skl_pipe_wm_parameters *params)
2478{
2479 unsigned int total_data_rate = 0;
2480 int plane;
2481
2482 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2483 const struct intel_plane_wm_parameters *p;
2484
2485 p = &params->plane[plane];
2486 if (!p->enabled)
2487 continue;
2488
2489 total_data_rate += skl_plane_relative_data_rate(p);
2490 }
2491
2492 return total_data_rate;
2493}
2494
2495static void
2496skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2497 const struct intel_wm_config *config,
2498 const struct skl_pipe_wm_parameters *params,
2499 struct skl_ddb_allocation *ddb /* out */)
2500{
2501 struct drm_device *dev = crtc->dev;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 enum pipe pipe = intel_crtc->pipe;
34bb56af 2504 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075
DL
2505 uint16_t alloc_size, start, cursor_blocks;
2506 unsigned int total_data_rate;
2507 int plane;
2508
34bb56af
DL
2509 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2510 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL
2511 if (alloc_size == 0) {
2512 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2513 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2514 return;
2515 }
2516
2517 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL
2518 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2519 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL
2520
2521 alloc_size -= cursor_blocks;
34bb56af 2522 alloc->end -= cursor_blocks;
b9cec075
DL
2523
2524 /*
2525 * Each active plane get a portion of the remaining space, in
2526 * proportion to the amount of data they need to fetch from memory.
2527 *
2528 * FIXME: we may not allocate every single block here.
2529 */
2530 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2531
34bb56af 2532 start = alloc->start;
b9cec075
DL
2533 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2534 const struct intel_plane_wm_parameters *p;
2535 unsigned int data_rate;
2536 uint16_t plane_blocks;
2537
2538 p = &params->plane[plane];
2539 if (!p->enabled)
2540 continue;
2541
2542 data_rate = skl_plane_relative_data_rate(p);
2543
2544 /*
2545 * promote the expression to 64 bits to avoid overflowing, the
2546 * result is < available as data_rate / total_data_rate < 1
2547 */
2548 plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
2549 total_data_rate);
2550
2551 ddb->plane[pipe][plane].start = start;
16160e3d 2552 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL
2553
2554 start += plane_blocks;
2555 }
2556
2557}
2558
5cec258b 2559static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB
2560{
2561 /* TODO: Take into account the scalers once we support them */
2562 return config->adjusted_mode.crtc_clock;
2563}
2564
2565/*
2566 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2567 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2568 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2569 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2570*/
2571static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2572 uint32_t latency)
2573{
2574 uint32_t wm_intermediate_val, ret;
2575
2576 if (latency == 0)
2577 return UINT_MAX;
2578
2579 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel;
2580 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2581
2582 return ret;
2583}
2584
2585static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2586 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2587 uint32_t latency)
2588{
2589 uint32_t ret, plane_bytes_per_line, wm_intermediate_val;
2590
2591 if (latency == 0)
2592 return UINT_MAX;
2593
2594 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
2595 wm_intermediate_val = latency * pixel_rate;
2596 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
2597 plane_bytes_per_line;
2598
2599 return ret;
2600}
2601
2d41c0b5
PB
2602static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2603 const struct intel_crtc *intel_crtc)
2604{
2605 struct drm_device *dev = intel_crtc->base.dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2608 enum pipe pipe = intel_crtc->pipe;
2609
2610 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2611 sizeof(new_ddb->plane[pipe])))
2612 return true;
2613
2614 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2615 sizeof(new_ddb->cursor[pipe])))
2616 return true;
2617
2618 return false;
2619}
2620
2621static void skl_compute_wm_global_parameters(struct drm_device *dev,
2622 struct intel_wm_config *config)
2623{
2624 struct drm_crtc *crtc;
2625 struct drm_plane *plane;
2626
2627 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2628 config->num_pipes_active += intel_crtc_active(crtc);
2629
2630 /* FIXME: I don't think we need those two global parameters on SKL */
2631 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2632 struct intel_plane *intel_plane = to_intel_plane(plane);
2633
2634 config->sprites_enabled |= intel_plane->wm.enabled;
2635 config->sprites_scaled |= intel_plane->wm.scaled;
2636 }
2637}
2638
2639static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2640 struct skl_pipe_wm_parameters *p)
2641{
2642 struct drm_device *dev = crtc->dev;
2643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2644 enum pipe pipe = intel_crtc->pipe;
2645 struct drm_plane *plane;
2646 int i = 1; /* Index for sprite planes start */
2647
2648 p->active = intel_crtc_active(crtc);
2649 if (p->active) {
2650 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2651 p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config);
2652
2653 /*
2654 * For now, assume primary and cursor planes are always enabled.
2655 */
2656 p->plane[0].enabled = true;
2657 p->plane[0].bytes_per_pixel =
2658 crtc->primary->fb->bits_per_pixel / 8;
2659 p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w;
2660 p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h;
2661
2662 p->cursor.enabled = true;
2663 p->cursor.bytes_per_pixel = 4;
2664 p->cursor.horiz_pixels = intel_crtc->cursor_width ?
2665 intel_crtc->cursor_width : 64;
2666 }
2667
2668 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2669 struct intel_plane *intel_plane = to_intel_plane(plane);
2670
a712f8eb
SJ
2671 if (intel_plane->pipe == pipe &&
2672 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB
2673 p->plane[i++] = intel_plane->wm;
2674 }
2675}
2676
2677static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p,
afb024aa
DL
2678 struct intel_plane_wm_parameters *p_params,
2679 uint16_t ddb_allocation,
2680 uint32_t mem_value,
2681 uint16_t *out_blocks, /* out */
2682 uint8_t *out_lines /* out */)
2d41c0b5 2683{
e6d66171 2684 uint32_t method1, method2, plane_bytes_per_line, res_blocks, res_lines;
2d41c0b5
PB
2685 uint32_t result_bytes;
2686
4f947386 2687 if (mem_value == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB
2688 return false;
2689
2690 method1 = skl_wm_method1(p->pixel_rate,
2691 p_params->bytes_per_pixel,
2692 mem_value);
2693 method2 = skl_wm_method2(p->pixel_rate,
2694 p->pipe_htotal,
2695 p_params->horiz_pixels,
2696 p_params->bytes_per_pixel,
2697 mem_value);
2698
2699 plane_bytes_per_line = p_params->horiz_pixels *
2700 p_params->bytes_per_pixel;
2701
2702 /* For now xtile and linear */
21fca258 2703 if (((ddb_allocation * 512) / plane_bytes_per_line) >= 1)
2d41c0b5
PB
2704 result_bytes = min(method1, method2);
2705 else
2706 result_bytes = method1;
2707
e6d66171
DL
2708 res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1;
2709 res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line);
2710
2711 if (res_blocks > ddb_allocation || res_lines > 31)
2712 return false;
2713
2714 *out_blocks = res_blocks;
2715 *out_lines = res_lines;
2d41c0b5
PB
2716
2717 return true;
2718}
2719
2720static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2721 struct skl_ddb_allocation *ddb,
2722 struct skl_pipe_wm_parameters *p,
2723 enum pipe pipe,
2724 int level,
2725 int num_planes,
2726 struct skl_wm_level *result)
2727{
2728 uint16_t latency = dev_priv->wm.skl_latency[level];
2729 uint16_t ddb_blocks;
2730 int i;
2731
2732 for (i = 0; i < num_planes; i++) {
2733 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2734
2735 result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i],
2736 ddb_blocks,
2737 latency,
2738 &result->plane_res_b[i],
2739 &result->plane_res_l[i]);
2740 }
2741
2742 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
2743 result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks,
2744 latency, &result->cursor_res_b,
2745 &result->cursor_res_l);
2746}
2747
407b50f3
DL
2748static uint32_t
2749skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2750{
2751 if (!intel_crtc_active(crtc))
2752 return 0;
2753
2754 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2755
2756}
2757
2758static void skl_compute_transition_wm(struct drm_crtc *crtc,
2759 struct skl_pipe_wm_parameters *params,
9414f563 2760 struct skl_wm_level *trans_wm /* out */)
407b50f3 2761{
9414f563
DL
2762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763 int i;
2764
407b50f3
DL
2765 if (!params->active)
2766 return;
9414f563
DL
2767
2768 /* Until we know more, just disable transition WMs */
2769 for (i = 0; i < intel_num_planes(intel_crtc); i++)
2770 trans_wm->plane_en[i] = false;
2771 trans_wm->cursor_en = false;
407b50f3
DL
2772}
2773
2d41c0b5
PB
2774static void skl_compute_pipe_wm(struct drm_crtc *crtc,
2775 struct skl_ddb_allocation *ddb,
2776 struct skl_pipe_wm_parameters *params,
2777 struct skl_pipe_wm *pipe_wm)
2778{
2779 struct drm_device *dev = crtc->dev;
2780 const struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 int level, max_level = ilk_wm_max_level(dev);
2783
2784 for (level = 0; level <= max_level; level++) {
2785 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
2786 level, intel_num_planes(intel_crtc),
2787 &pipe_wm->wm[level]);
2788 }
2789 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
2790
9414f563 2791 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB
2792}
2793
2794static void skl_compute_wm_results(struct drm_device *dev,
2795 struct skl_pipe_wm_parameters *p,
2796 struct skl_pipe_wm *p_wm,
2797 struct skl_wm_values *r,
2798 struct intel_crtc *intel_crtc)
2799{
2800 int level, max_level = ilk_wm_max_level(dev);
2801 enum pipe pipe = intel_crtc->pipe;
9414f563
DL
2802 uint32_t temp;
2803 int i;
2d41c0b5
PB
2804
2805 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB
2806 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
2807 temp = 0;
2d41c0b5
PB
2808
2809 temp |= p_wm->wm[level].plane_res_l[i] <<
2810 PLANE_WM_LINES_SHIFT;
2811 temp |= p_wm->wm[level].plane_res_b[i];
2812 if (p_wm->wm[level].plane_en[i])
2813 temp |= PLANE_WM_EN;
2814
2815 r->plane[pipe][i][level] = temp;
2d41c0b5
PB
2816 }
2817
2818 temp = 0;
2d41c0b5
PB
2819
2820 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
2821 temp |= p_wm->wm[level].cursor_res_b;
2822
2823 if (p_wm->wm[level].cursor_en)
2824 temp |= PLANE_WM_EN;
2825
2826 r->cursor[pipe][level] = temp;
2d41c0b5
PB
2827
2828 }
2829
9414f563
DL
2830 /* transition WMs */
2831 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
2832 temp = 0;
2833 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
2834 temp |= p_wm->trans_wm.plane_res_b[i];
2835 if (p_wm->trans_wm.plane_en[i])
2836 temp |= PLANE_WM_EN;
2837
2838 r->plane_trans[pipe][i] = temp;
2839 }
2840
2841 temp = 0;
2842 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
2843 temp |= p_wm->trans_wm.cursor_res_b;
2844 if (p_wm->trans_wm.cursor_en)
2845 temp |= PLANE_WM_EN;
2846
2847 r->cursor_trans[pipe] = temp;
2848
2d41c0b5
PB
2849 r->wm_linetime[pipe] = p_wm->linetime;
2850}
2851
16160e3d
DL
2852static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
2853 const struct skl_ddb_entry *entry)
2854{
2855 if (entry->end)
2856 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
2857 else
2858 I915_WRITE(reg, 0);
2859}
2860
2d41c0b5
PB
2861static void skl_write_wm_values(struct drm_i915_private *dev_priv,
2862 const struct skl_wm_values *new)
2863{
2864 struct drm_device *dev = dev_priv->dev;
2865 struct intel_crtc *crtc;
2866
2867 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
2868 int i, level, max_level = ilk_wm_max_level(dev);
2869 enum pipe pipe = crtc->pipe;
2870
5d374d96
DL
2871 if (!new->dirty[pipe])
2872 continue;
8211bd5b 2873
5d374d96 2874 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 2875
5d374d96
DL
2876 for (level = 0; level <= max_level; level++) {
2877 for (i = 0; i < intel_num_planes(crtc); i++)
2878 I915_WRITE(PLANE_WM(pipe, i, level),
2879 new->plane[pipe][i][level]);
2880 I915_WRITE(CUR_WM(pipe, level),
2881 new->cursor[pipe][level]);
2d41c0b5 2882 }
5d374d96
DL
2883 for (i = 0; i < intel_num_planes(crtc); i++)
2884 I915_WRITE(PLANE_WM_TRANS(pipe, i),
2885 new->plane_trans[pipe][i]);
2886 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
2887
2888 for (i = 0; i < intel_num_planes(crtc); i++)
2889 skl_ddb_entry_write(dev_priv,
2890 PLANE_BUF_CFG(pipe, i),
2891 &new->ddb.plane[pipe][i]);
2892
2893 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
2894 &new->ddb.cursor[pipe]);
2d41c0b5 2895 }
2d41c0b5
PB
2896}
2897
0e8fb7ba
DL
2898/*
2899 * When setting up a new DDB allocation arrangement, we need to correctly
2900 * sequence the times at which the new allocations for the pipes are taken into
2901 * account or we'll have pipes fetching from space previously allocated to
2902 * another pipe.
2903 *
2904 * Roughly the sequence looks like:
2905 * 1. re-allocate the pipe(s) with the allocation being reduced and not
2906 * overlapping with a previous light-up pipe (another way to put it is:
2907 * pipes with their new allocation strickly included into their old ones).
2908 * 2. re-allocate the other pipes that get their allocation reduced
2909 * 3. allocate the pipes having their allocation increased
2910 *
2911 * Steps 1. and 2. are here to take care of the following case:
2912 * - Initially DDB looks like this:
2913 * | B | C |
2914 * - enable pipe A.
2915 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
2916 * allocation
2917 * | A | B | C |
2918 *
2919 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
2920 */
2921
d21b795c
DL
2922static void
2923skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba
DL
2924{
2925 struct drm_device *dev = dev_priv->dev;
2926 int plane;
2927
d21b795c
DL
2928 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
2929
0e8fb7ba
DL
2930 for_each_plane(pipe, plane) {
2931 I915_WRITE(PLANE_SURF(pipe, plane),
2932 I915_READ(PLANE_SURF(pipe, plane)));
2933 }
2934 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
2935}
2936
2937static bool
2938skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
2939 const struct skl_ddb_allocation *new,
2940 enum pipe pipe)
2941{
2942 uint16_t old_size, new_size;
2943
2944 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
2945 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
2946
2947 return old_size != new_size &&
2948 new->pipe[pipe].start >= old->pipe[pipe].start &&
2949 new->pipe[pipe].end <= old->pipe[pipe].end;
2950}
2951
2952static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
2953 struct skl_wm_values *new_values)
2954{
2955 struct drm_device *dev = dev_priv->dev;
2956 struct skl_ddb_allocation *cur_ddb, *new_ddb;
2957 bool reallocated[I915_MAX_PIPES] = {false, false, false};
2958 struct intel_crtc *crtc;
2959 enum pipe pipe;
2960
2961 new_ddb = &new_values->ddb;
2962 cur_ddb = &dev_priv->wm.skl_hw.ddb;
2963
2964 /*
2965 * First pass: flush the pipes with the new allocation contained into
2966 * the old space.
2967 *
2968 * We'll wait for the vblank on those pipes to ensure we can safely
2969 * re-allocate the freed space without this pipe fetching from it.
2970 */
2971 for_each_intel_crtc(dev, crtc) {
2972 if (!crtc->active)
2973 continue;
2974
2975 pipe = crtc->pipe;
2976
2977 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
2978 continue;
2979
d21b795c 2980 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL
2981 intel_wait_for_vblank(dev, pipe);
2982
2983 reallocated[pipe] = true;
2984 }
2985
2986
2987 /*
2988 * Second pass: flush the pipes that are having their allocation
2989 * reduced, but overlapping with a previous allocation.
2990 *
2991 * Here as well we need to wait for the vblank to make sure the freed
2992 * space is not used anymore.
2993 */
2994 for_each_intel_crtc(dev, crtc) {
2995 if (!crtc->active)
2996 continue;
2997
2998 pipe = crtc->pipe;
2999
3000 if (reallocated[pipe])
3001 continue;
3002
3003 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3004 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3005 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3006 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3007 reallocated[pipe] = true;
0e8fb7ba 3008 }
0e8fb7ba
DL
3009 }
3010
3011 /*
3012 * Third pass: flush the pipes that got more space allocated.
3013 *
3014 * We don't need to actively wait for the update here, next vblank
3015 * will just get more DDB space with the correct WM values.
3016 */
3017 for_each_intel_crtc(dev, crtc) {
3018 if (!crtc->active)
3019 continue;
3020
3021 pipe = crtc->pipe;
3022
3023 /*
3024 * At this point, only the pipes more space than before are
3025 * left to re-allocate.
3026 */
3027 if (reallocated[pipe])
3028 continue;
3029
d21b795c 3030 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL
3031 }
3032}
3033
2d41c0b5
PB
3034static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3035 struct skl_pipe_wm_parameters *params,
3036 struct intel_wm_config *config,
3037 struct skl_ddb_allocation *ddb, /* out */
3038 struct skl_pipe_wm *pipe_wm /* out */)
3039{
3040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3041
3042 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3043 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB
3044 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3045
3046 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3047 return false;
3048
3049 intel_crtc->wm.skl_active = *pipe_wm;
3050 return true;
3051}
3052
3053static void skl_update_other_pipe_wm(struct drm_device *dev,
3054 struct drm_crtc *crtc,
3055 struct intel_wm_config *config,
3056 struct skl_wm_values *r)
3057{
3058 struct intel_crtc *intel_crtc;
3059 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3060
3061 /*
3062 * If the WM update hasn't changed the allocation for this_crtc (the
3063 * crtc we are currently computing the new WM values for), other
3064 * enabled crtcs will keep the same allocation and we don't need to
3065 * recompute anything for them.
3066 */
3067 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3068 return;
3069
3070 /*
3071 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3072 * other active pipes need new DDB allocation and WM values.
3073 */
3074 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3075 base.head) {
3076 struct skl_pipe_wm_parameters params = {};
3077 struct skl_pipe_wm pipe_wm = {};
3078 bool wm_changed;
3079
3080 if (this_crtc->pipe == intel_crtc->pipe)
3081 continue;
3082
3083 if (!intel_crtc->active)
3084 continue;
3085
3086 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3087 &params, config,
3088 &r->ddb, &pipe_wm);
3089
3090 /*
3091 * If we end up re-computing the other pipe WM values, it's
3092 * because it was really needed, so we expect the WM values to
3093 * be different.
3094 */
3095 WARN_ON(!wm_changed);
3096
3097 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3098 r->dirty[intel_crtc->pipe] = true;
3099 }
3100}
3101
3102static void skl_update_wm(struct drm_crtc *crtc)
3103{
3104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct skl_pipe_wm_parameters params = {};
3108 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3109 struct skl_pipe_wm pipe_wm = {};
3110 struct intel_wm_config config = {};
3111
3112 memset(results, 0, sizeof(*results));
3113
3114 skl_compute_wm_global_parameters(dev, &config);
3115
3116 if (!skl_update_pipe_wm(crtc, &params, &config,
3117 &results->ddb, &pipe_wm))
3118 return;
3119
3120 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3121 results->dirty[intel_crtc->pipe] = true;
3122
3123 skl_update_other_pipe_wm(dev, crtc, &config, results);
3124 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3125 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL
3126
3127 /* store the new configuration */
3128 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB
3129}
3130
3131static void
3132skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3133 uint32_t sprite_width, uint32_t sprite_height,
3134 int pixel_size, bool enabled, bool scaled)
3135{
3136 struct intel_plane *intel_plane = to_intel_plane(plane);
3137
3138 intel_plane->wm.enabled = enabled;
3139 intel_plane->wm.scaled = scaled;
3140 intel_plane->wm.horiz_pixels = sprite_width;
3141 intel_plane->wm.vert_pixels = sprite_height;
3142 intel_plane->wm.bytes_per_pixel = pixel_size;
3143
3144 skl_update_wm(crtc);
3145}
3146
820c1980 3147static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3148{
7c4a395f 3149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3150 struct drm_device *dev = crtc->dev;
801bcfff 3151 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID
3152 struct ilk_wm_maximums max;
3153 struct ilk_pipe_wm_parameters params = {};
3154 struct ilk_wm_values results = {};
77c122bc 3155 enum intel_ddb_partitioning partitioning;
7c4a395f 3156 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3157 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3158 struct intel_wm_config config = {};
7c4a395f 3159
2a44b76b 3160 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS
3161
3162 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3163
3164 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3165 return;
861f3389 3166
7c4a395f 3167 intel_crtc->wm.active = pipe_wm;
861f3389 3168
2a44b76b
VS
3169 ilk_compute_wm_config(dev, &config);
3170
34982fe1 3171 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3172 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS
3173
3174 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS
3175 if (INTEL_INFO(dev)->gen >= 7 &&
3176 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3177 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3178 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3179
820c1980 3180 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3181 } else {
198a1e9b 3182 best_lp_wm = &lp_wm_1_2;
861f3389
PZ
3183 }
3184
198a1e9b 3185 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3186 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3187
820c1980 3188 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3189
820c1980 3190 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ
3191}
3192
ed57cb8a
DL
3193static void
3194ilk_update_sprite_wm(struct drm_plane *plane,
3195 struct drm_crtc *crtc,
3196 uint32_t sprite_width, uint32_t sprite_height,
3197 int pixel_size, bool enabled, bool scaled)
526682e9 3198{
8553c18e 3199 struct drm_device *dev = plane->dev;
adf3d35e 3200 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3201
adf3d35e
VS
3202 intel_plane->wm.enabled = enabled;
3203 intel_plane->wm.scaled = scaled;
3204 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3205 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3206 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3207
8553c18e
VS
3208 /*
3209 * IVB workaround: must disable low power watermarks for at least
3210 * one frame before enabling scaling. LP watermarks can be re-enabled
3211 * when scaling is disabled.
3212 *
3213 * WaCxSRDisabledForSpriteScaling:ivb
3214 */
3215 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3216 intel_wait_for_vblank(dev, intel_plane->pipe);
3217
820c1980 3218 ilk_update_wm(crtc);
526682e9
PZ
3219}
3220
3078999f
PB
3221static void skl_pipe_wm_active_state(uint32_t val,
3222 struct skl_pipe_wm *active,
3223 bool is_transwm,
3224 bool is_cursor,
3225 int i,
3226 int level)
3227{
3228 bool is_enabled = (val & PLANE_WM_EN) != 0;
3229
3230 if (!is_transwm) {
3231 if (!is_cursor) {
3232 active->wm[level].plane_en[i] = is_enabled;
3233 active->wm[level].plane_res_b[i] =
3234 val & PLANE_WM_BLOCKS_MASK;
3235 active->wm[level].plane_res_l[i] =
3236 (val >> PLANE_WM_LINES_SHIFT) &
3237 PLANE_WM_LINES_MASK;
3238 } else {
3239 active->wm[level].cursor_en = is_enabled;
3240 active->wm[level].cursor_res_b =
3241 val & PLANE_WM_BLOCKS_MASK;
3242 active->wm[level].cursor_res_l =
3243 (val >> PLANE_WM_LINES_SHIFT) &
3244 PLANE_WM_LINES_MASK;
3245 }
3246 } else {
3247 if (!is_cursor) {
3248 active->trans_wm.plane_en[i] = is_enabled;
3249 active->trans_wm.plane_res_b[i] =
3250 val & PLANE_WM_BLOCKS_MASK;
3251 active->trans_wm.plane_res_l[i] =
3252 (val >> PLANE_WM_LINES_SHIFT) &
3253 PLANE_WM_LINES_MASK;
3254 } else {
3255 active->trans_wm.cursor_en = is_enabled;
3256 active->trans_wm.cursor_res_b =
3257 val & PLANE_WM_BLOCKS_MASK;
3258 active->trans_wm.cursor_res_l =
3259 (val >> PLANE_WM_LINES_SHIFT) &
3260 PLANE_WM_LINES_MASK;
3261 }
3262 }
3263}
3264
3265static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3266{
3267 struct drm_device *dev = crtc->dev;
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3272 enum pipe pipe = intel_crtc->pipe;
3273 int level, i, max_level;
3274 uint32_t temp;
3275
3276 max_level = ilk_wm_max_level(dev);
3277
3278 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3279
3280 for (level = 0; level <= max_level; level++) {
3281 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3282 hw->plane[pipe][i][level] =
3283 I915_READ(PLANE_WM(pipe, i, level));
3284 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3285 }
3286
3287 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3288 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3289 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3290
3291 if (!intel_crtc_active(crtc))
3292 return;
3293
3294 hw->dirty[pipe] = true;
3295
3296 active->linetime = hw->wm_linetime[pipe];
3297
3298 for (level = 0; level <= max_level; level++) {
3299 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3300 temp = hw->plane[pipe][i][level];
3301 skl_pipe_wm_active_state(temp, active, false,
3302 false, i, level);
3303 }
3304 temp = hw->cursor[pipe][level];
3305 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3306 }
3307
3308 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3309 temp = hw->plane_trans[pipe][i];
3310 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3311 }
3312
3313 temp = hw->cursor_trans[pipe];
3314 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3315}
3316
3317void skl_wm_get_hw_state(struct drm_device *dev)
3318{
a269c583
DL
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB
3321 struct drm_crtc *crtc;
3322
a269c583 3323 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB
3324 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3325 skl_pipe_wm_get_hw_state(crtc);
3326}
3327
243e6a44
VS
3328static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3329{
3330 struct drm_device *dev = crtc->dev;
3331 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3332 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS
3333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3334 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3335 enum pipe pipe = intel_crtc->pipe;
3336 static const unsigned int wm0_pipe_reg[] = {
3337 [PIPE_A] = WM0_PIPEA_ILK,
3338 [PIPE_B] = WM0_PIPEB_ILK,
3339 [PIPE_C] = WM0_PIPEC_IVB,
3340 };
3341
3342 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3343 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3344 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3345
2a44b76b
VS
3346 active->pipe_enabled = intel_crtc_active(crtc);
3347
3348 if (active->pipe_enabled) {
243e6a44
VS
3349 u32 tmp = hw->wm_pipe[pipe];
3350
3351 /*
3352 * For active pipes LP0 watermark is marked as
3353 * enabled, and LP1+ watermaks as disabled since
3354 * we can't really reverse compute them in case
3355 * multiple pipes are active.
3356 */
3357 active->wm[0].enable = true;
3358 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3359 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3360 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3361 active->linetime = hw->wm_linetime[pipe];
3362 } else {
3363 int level, max_level = ilk_wm_max_level(dev);
3364
3365 /*
3366 * For inactive pipes, all watermark levels
3367 * should be marked as enabled but zeroed,
3368 * which is what we'd compute them to.
3369 */
3370 for (level = 0; level <= max_level; level++)
3371 active->wm[level].enable = true;
3372 }
3373}
3374
3375void ilk_wm_get_hw_state(struct drm_device *dev)
3376{
3377 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3378 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS
3379 struct drm_crtc *crtc;
3380
70e1e0ec 3381 for_each_crtc(dev, crtc)
243e6a44
VS
3382 ilk_pipe_wm_get_hw_state(crtc);
3383
3384 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3385 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3386 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3387
3388 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS
3389 if (INTEL_INFO(dev)->gen >= 7) {
3390 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3391 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3392 }
243e6a44 3393
a42a5719 3394 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS
3395 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3396 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3397 else if (IS_IVYBRIDGE(dev))
3398 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3399 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS
3400
3401 hw->enable_fbc_wm =
3402 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3403}
3404
b445e3b0
ED
3405/**
3406 * intel_update_watermarks - update FIFO watermark values based on current modes
3407 *
3408 * Calculate watermark values for the various WM regs based on current mode
3409 * and plane configuration.
3410 *
3411 * There are several cases to deal with here:
3412 * - normal (i.e. non-self-refresh)
3413 * - self-refresh (SR) mode
3414 * - lines are large relative to FIFO size (buffer can hold up to 2)
3415 * - lines are small relative to FIFO size (buffer can hold more than 2
3416 * lines), so need to account for TLB latency
3417 *
3418 * The normal calculation is:
3419 * watermark = dotclock * bytes per pixel * latency
3420 * where latency is platform & configuration dependent (we assume pessimal
3421 * values here).
3422 *
3423 * The SR calculation is:
3424 * watermark = (trunc(latency/line time)+1) * surface width *
3425 * bytes per pixel
3426 * where
3427 * line time = htotal / dotclock
3428 * surface width = hdisplay for normal plane and 64 for cursor
3429 * and latency is assumed to be high, as above.
3430 *
3431 * The final value programmed to the register should always be rounded up,
3432 * and include an extra 2 entries to account for clock crossings.
3433 *
3434 * We don't use the sprite, so we can ignore that. And on Crestline we have
3435 * to set the non-SR watermarks to 8.
3436 */
46ba614c 3437void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3438{
46ba614c 3439 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED
3440
3441 if (dev_priv->display.update_wm)
46ba614c 3442 dev_priv->display.update_wm(crtc);
b445e3b0
ED
3443}
3444
adf3d35e
VS
3445void intel_update_sprite_watermarks(struct drm_plane *plane,
3446 struct drm_crtc *crtc,
ed57cb8a
DL
3447 uint32_t sprite_width,
3448 uint32_t sprite_height,
3449 int pixel_size,
39db4a4d 3450 bool enabled, bool scaled)
b445e3b0 3451{
adf3d35e 3452 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED
3453
3454 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL
3455 dev_priv->display.update_sprite_wm(plane, crtc,
3456 sprite_width, sprite_height,
39db4a4d 3457 pixel_size, enabled, scaled);
b445e3b0
ED
3458}
3459
2b4e57bd
ED
3460static struct drm_i915_gem_object *
3461intel_alloc_context_page(struct drm_device *dev)
3462{
3463 struct drm_i915_gem_object *ctx;
3464 int ret;
3465
3466 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3467
3468 ctx = i915_gem_alloc_object(dev, 4096);
3469 if (!ctx) {
3470 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3471 return NULL;
3472 }
3473
c69766f2 3474 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED
3475 if (ret) {
3476 DRM_ERROR("failed to pin power context: %d\n", ret);
3477 goto err_unref;
3478 }
3479
3480 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3481 if (ret) {
3482 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3483 goto err_unpin;
3484 }
3485
3486 return ctx;
3487
3488err_unpin:
d7f46fc4 3489 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED
3490err_unref:
3491 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED
3492 return NULL;
3493}
3494
9270388e
DV
3495/**
3496 * Lock protecting IPS related data structures
9270388e
DV
3497 */
3498DEFINE_SPINLOCK(mchdev_lock);
3499
3500/* Global for IPS driver to get at the current i915 device. Protected by
3501 * mchdev_lock. */
3502static struct drm_i915_private *i915_mch_dev;
3503
2b4e57bd
ED
3504bool ironlake_set_drps(struct drm_device *dev, u8 val)
3505{
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 u16 rgvswctl;
3508
9270388e
DV
3509 assert_spin_locked(&mchdev_lock);
3510
2b4e57bd
ED
3511 rgvswctl = I915_READ16(MEMSWCTL);
3512 if (rgvswctl & MEMCTL_CMD_STS) {
3513 DRM_DEBUG("gpu busy, RCS change rejected\n");
3514 return false; /* still busy with another command */
3515 }
3516
3517 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3518 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3519 I915_WRITE16(MEMSWCTL, rgvswctl);
3520 POSTING_READ16(MEMSWCTL);
3521
3522 rgvswctl |= MEMCTL_CMD_STS;
3523 I915_WRITE16(MEMSWCTL, rgvswctl);
3524
3525 return true;
3526}
3527
8090c6b9 3528static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED
3529{
3530 struct drm_i915_private *dev_priv = dev->dev_private;
3531 u32 rgvmodectl = I915_READ(MEMMODECTL);
3532 u8 fmax, fmin, fstart, vstart;
3533
9270388e
DV
3534 spin_lock_irq(&mchdev_lock);
3535
2b4e57bd
ED
3536 /* Enable temp reporting */
3537 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3538 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3539
3540 /* 100ms RC evaluation intervals */
3541 I915_WRITE(RCUPEI, 100000);
3542 I915_WRITE(RCDNEI, 100000);
3543
3544 /* Set max/min thresholds to 90ms and 80ms respectively */
3545 I915_WRITE(RCBMAXAVG, 90000);
3546 I915_WRITE(RCBMINAVG, 80000);
3547
3548 I915_WRITE(MEMIHYST, 1);
3549
3550 /* Set up min, max, and cur for interrupt handling */
3551 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3552 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3553 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3554 MEMMODE_FSTART_SHIFT;
3555
3556 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3557 PXVFREQ_PX_SHIFT;
3558
20e4d407
DV
3559 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3560 dev_priv->ips.fstart = fstart;
2b4e57bd 3561
20e4d407
DV
3562 dev_priv->ips.max_delay = fstart;
3563 dev_priv->ips.min_delay = fmin;
3564 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED
3565
3566 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3567 fmax, fmin, fstart);
3568
3569 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3570
3571 /*
3572 * Interrupts will be enabled in ironlake_irq_postinstall
3573 */
3574
3575 I915_WRITE(VIDSTART, vstart);
3576 POSTING_READ(VIDSTART);
3577
3578 rgvmodectl |= MEMMODE_SWMODE_EN;
3579 I915_WRITE(MEMMODECTL, rgvmodectl);
3580
9270388e 3581 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3582 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3583 mdelay(1);
2b4e57bd
ED
3584
3585 ironlake_set_drps(dev, fstart);
3586
20e4d407 3587 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3588 I915_READ(0x112e0);
20e4d407
DV
3589 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3590 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3591 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV
3592
3593 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED
3594}
3595
8090c6b9 3596static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED
3597{
3598 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV
3599 u16 rgvswctl;
3600
3601 spin_lock_irq(&mchdev_lock);
3602
3603 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED
3604
3605 /* Ack interrupts, disable EFC interrupt */
3606 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3607 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3608 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3609 I915_WRITE(DEIIR, DE_PCU_EVENT);
3610 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3611
3612 /* Go back to the starting frequency */
20e4d407 3613 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3614 mdelay(1);
2b4e57bd
ED
3615 rgvswctl |= MEMCTL_CMD_STS;
3616 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3617 mdelay(1);
2b4e57bd 3618
9270388e 3619 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED
3620}
3621
acbe9475
DV
3622/* There's a funny hw issue where the hw returns all 0 when reading from
3623 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3624 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3625 * all limits and the gpu stuck at whatever frequency it is at atm).
3626 */
6917c7b9 3627static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3628{
7b9e0ae6 3629 u32 limits;
2b4e57bd 3630
20b46e59
DV
3631 /* Only set the down limit when we've reached the lowest level to avoid
3632 * getting more interrupts, otherwise leave this clear. This prevents a
3633 * race in the hw when coming out of rc6: There's a tiny window where
3634 * the hw runs at the minimal clock before selecting the desired
3635 * frequency, if the down threshold expires in that window we will not
3636 * receive a down interrupt. */
b39fb297
BW
3637 limits = dev_priv->rps.max_freq_softlimit << 24;
3638 if (val <= dev_priv->rps.min_freq_softlimit)
3639 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV
3640
3641 return limits;
3642}
3643
dd75fdc8
CW
3644static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3645{
3646 int new_power;
3647
3648 new_power = dev_priv->rps.power;
3649 switch (dev_priv->rps.power) {
3650 case LOW_POWER:
b39fb297 3651 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW
3652 new_power = BETWEEN;
3653 break;
3654
3655 case BETWEEN:
b39fb297 3656 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3657 new_power = LOW_POWER;
b39fb297 3658 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW
3659 new_power = HIGH_POWER;
3660 break;
3661
3662 case HIGH_POWER:
b39fb297 3663 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW
3664 new_power = BETWEEN;
3665 break;
3666 }
3667 /* Max/min bins are special */
b39fb297 3668 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3669 new_power = LOW_POWER;
b39fb297 3670 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW
3671 new_power = HIGH_POWER;
3672 if (new_power == dev_priv->rps.power)
3673 return;
3674
3675 /* Note the units here are not exactly 1us, but 1280ns. */
3676 switch (new_power) {
3677 case LOW_POWER:
3678 /* Upclock if more than 95% busy over 16ms */
3679 I915_WRITE(GEN6_RP_UP_EI, 12500);
3680 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3681
3682 /* Downclock if less than 85% busy over 32ms */
3683 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3684 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3685
3686 I915_WRITE(GEN6_RP_CONTROL,
3687 GEN6_RP_MEDIA_TURBO |
3688 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3689 GEN6_RP_MEDIA_IS_GFX |
3690 GEN6_RP_ENABLE |
3691 GEN6_RP_UP_BUSY_AVG |
3692 GEN6_RP_DOWN_IDLE_AVG);
3693 break;
3694
3695 case BETWEEN:
3696 /* Upclock if more than 90% busy over 13ms */
3697 I915_WRITE(GEN6_RP_UP_EI, 10250);
3698 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3699
3700 /* Downclock if less than 75% busy over 32ms */
3701 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3702 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3703
3704 I915_WRITE(GEN6_RP_CONTROL,
3705 GEN6_RP_MEDIA_TURBO |
3706 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3707 GEN6_RP_MEDIA_IS_GFX |
3708 GEN6_RP_ENABLE |
3709 GEN6_RP_UP_BUSY_AVG |
3710 GEN6_RP_DOWN_IDLE_AVG);
3711 break;
3712
3713 case HIGH_POWER:
3714 /* Upclock if more than 85% busy over 10ms */
3715 I915_WRITE(GEN6_RP_UP_EI, 8000);
3716 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3717
3718 /* Downclock if less than 60% busy over 32ms */
3719 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3720 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3721
3722 I915_WRITE(GEN6_RP_CONTROL,
3723 GEN6_RP_MEDIA_TURBO |
3724 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3725 GEN6_RP_MEDIA_IS_GFX |
3726 GEN6_RP_ENABLE |
3727 GEN6_RP_UP_BUSY_AVG |
3728 GEN6_RP_DOWN_IDLE_AVG);
3729 break;
3730 }
3731
3732 dev_priv->rps.power = new_power;
3733 dev_priv->rps.last_adj = 0;
3734}
3735
2876ce73
CW
3736static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3737{
3738 u32 mask = 0;
3739
3740 if (val > dev_priv->rps.min_freq_softlimit)
3741 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3742 if (val < dev_priv->rps.max_freq_softlimit)
3743 mask |= GEN6_PM_RP_UP_THRESHOLD;
3744
7b3c29f6
CW
3745 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3746 mask &= dev_priv->pm_rps_events;
3747
59d02a1f 3748 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW
3749}
3750
b8a5ff8d
JM
3751/* gen6_set_rps is called to update the frequency request, but should also be
3752 * called when the range (min_delay and max_delay) is modified so that we can
3753 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV
3754void gen6_set_rps(struct drm_device *dev, u8 val)
3755{
3756 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3757
4fc688ce 3758 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW
3759 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3760 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3761
eb64cad1
CW
3762 /* min/max delay may still have been modified so be sure to
3763 * write the limits value.
3764 */
3765 if (val != dev_priv->rps.cur_freq) {
3766 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3767
50e6a2a7 3768 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW
3769 I915_WRITE(GEN6_RPNSWREQ,
3770 HSW_FREQUENCY(val));
3771 else
3772 I915_WRITE(GEN6_RPNSWREQ,
3773 GEN6_FREQUENCY(val) |
3774 GEN6_OFFSET(0) |
3775 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3776 }
7b9e0ae6 3777
7b9e0ae6
CW
3778 /* Make sure we continue to get interrupts
3779 * until we hit the minimum or maximum frequencies.
3780 */
eb64cad1 3781 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3782 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3783
d5570a72
BW
3784 POSTING_READ(GEN6_RPNSWREQ);
3785
b39fb297 3786 dev_priv->rps.cur_freq = val;
be2cde9a 3787 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED
3788}
3789
76c3552f
D
3790/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3791 *
3792 * * If Gfx is Idle, then
3793 * 1. Mask Turbo interrupts
3794 * 2. Bring up Gfx clock
3795 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3796 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3797 * 5. Unmask Turbo interrupts
3798*/
3799static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3800{
5549d25f
D
3801 struct drm_device *dev = dev_priv->dev;
3802
3803 /* Latest VLV doesn't need to force the gfx clock */
3804 if (dev->pdev->revision >= 0xd) {
3805 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3806 return;
3807 }
3808
76c3552f
D
3809 /*
3810 * When we are idle. Drop to min voltage state.
3811 */
3812
b39fb297 3813 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D
3814 return;
3815
3816 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID
3817 I915_WRITE(GEN6_PMINTRMSK,
3818 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 3819
650ad970 3820 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3821
b39fb297 3822 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D
3823
3824 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3825 dev_priv->rps.min_freq_softlimit);
76c3552f
D
3826
3827 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 3828 & GENFREQSTATUS) == 0, 100))
76c3552f
D
3829 DRM_ERROR("timed out waiting for Punit\n");
3830
650ad970 3831 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3832
2876ce73
CW
3833 I915_WRITE(GEN6_PMINTRMSK,
3834 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D
3835}
3836
b29c19b6
CW
3837void gen6_rps_idle(struct drm_i915_private *dev_priv)
3838{
691bb717
DL
3839 struct drm_device *dev = dev_priv->dev;
3840
b29c19b6 3841 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3842 if (dev_priv->rps.enabled) {
34638118
D
3843 if (IS_CHERRYVIEW(dev))
3844 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3845 else if (IS_VALLEYVIEW(dev))
76c3552f 3846 vlv_set_rps_idle(dev_priv);
7526ed79 3847 else
b39fb297 3848 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW
3849 dev_priv->rps.last_adj = 0;
3850 }
b29c19b6
CW
3851 mutex_unlock(&dev_priv->rps.hw_lock);
3852}
3853
3854void gen6_rps_boost(struct drm_i915_private *dev_priv)
3855{
691bb717
DL
3856 struct drm_device *dev = dev_priv->dev;
3857
b29c19b6 3858 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3859 if (dev_priv->rps.enabled) {
691bb717 3860 if (IS_VALLEYVIEW(dev))
b39fb297 3861 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
7526ed79 3862 else
b39fb297 3863 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW
3864 dev_priv->rps.last_adj = 0;
3865 }
b29c19b6
CW
3866 mutex_unlock(&dev_priv->rps.hw_lock);
3867}
3868
0a073b84
JB
3869void valleyview_set_rps(struct drm_device *dev, u8 val)
3870{
3871 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3872
0a073b84 3873 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW
3874 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3875 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3876
1c14762d
VS
3877 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3878 "Odd GPU freq value\n"))
3879 val &= ~1;
3880
9a3b9c7a 3881 if (val != dev_priv->rps.cur_freq)
2876ce73 3882 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3883
09c87db8 3884 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3885
b39fb297 3886 dev_priv->rps.cur_freq = val;
2ec3815f 3887 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB
3888}
3889
20e49366
ZW
3890static void gen9_disable_rps(struct drm_device *dev)
3891{
3892 struct drm_i915_private *dev_priv = dev->dev_private;
3893
3894 I915_WRITE(GEN6_RC_CONTROL, 0);
3895}
3896
44fc7d5c 3897static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB
3898{
3899 struct drm_i915_private *dev_priv = dev->dev_private;
3900
3901 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3902 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV
3903}
3904
38807746
D
3905static void cherryview_disable_rps(struct drm_device *dev)
3906{
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909 I915_WRITE(GEN6_RC_CONTROL, 0);
3910}
3911
44fc7d5c
DV
3912static void valleyview_disable_rps(struct drm_device *dev)
3913{
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915
98a2e5f9
D
3916 /* we're doing forcewake before Disabling RC6,
3917 * This what the BIOS expects when going into suspend */
3918 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3919
44fc7d5c 3920 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3921
98a2e5f9 3922 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB
3923}
3924
dc39fff7
BW
3925static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3926{
91ca689a
ID
3927 if (IS_VALLEYVIEW(dev)) {
3928 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3929 mode = GEN6_RC_CTL_RC6_ENABLE;
3930 else
3931 mode = 0;
3932 }
58abf1da
RV
3933 if (HAS_RC6p(dev))
3934 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
3935 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3936 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3937 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3938
3939 else
3940 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
3941 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW
3942}
3943
e6069ca8 3944static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3945{
eb4926e4
DL
3946 /* No RC6 before Ironlake */
3947 if (INTEL_INFO(dev)->gen < 5)
3948 return 0;
3949
e6069ca8
ID
3950 /* RC6 is only on Ironlake mobile not on desktop */
3951 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3952 return 0;
3953
456470eb 3954 /* Respect the kernel parameter if it is set */
e6069ca8
ID
3955 if (enable_rc6 >= 0) {
3956 int mask;
3957
58abf1da 3958 if (HAS_RC6p(dev))
e6069ca8
ID
3959 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3960 INTEL_RC6pp_ENABLE;
3961 else
3962 mask = INTEL_RC6_ENABLE;
3963
3964 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV
3965 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3966 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID
3967
3968 return enable_rc6 & mask;
3969 }
2b4e57bd 3970
6567d748
CW
3971 /* Disable RC6 on Ironlake */
3972 if (INTEL_INFO(dev)->gen == 5)
3973 return 0;
2b4e57bd 3974
8bade1ad 3975 if (IS_IVYBRIDGE(dev))
cca84a1f 3976 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW
3977
3978 return INTEL_RC6_ENABLE;
2b4e57bd
ED
3979}
3980
e6069ca8
ID
3981int intel_enable_rc6(const struct drm_device *dev)
3982{
3983 return i915.enable_rc6;
3984}
3985
93ee2920 3986static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 3987{
93ee2920
TR
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989 uint32_t rp_state_cap;
3990 u32 ddcc_status = 0;
3991 int ret;
3992
3993 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW
3994 /* All of these values are in units of 50MHz */
3995 dev_priv->rps.cur_freq = 0;
93ee2920 3996 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 3997 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 3998 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 3999 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3280e8b0
BW
4000 /* hw_max = RP0 until we check for overclocking */
4001 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4002
93ee2920
TR
4003 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4004 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4005 ret = sandybridge_pcode_read(dev_priv,
4006 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4007 &ddcc_status);
4008 if (0 == ret)
4009 dev_priv->rps.efficient_freq =
4010 (ddcc_status >> 8) & 0xff;
4011 }
4012
3280e8b0
BW
4013 /* Preserve min/max settings in case of re-init */
4014 if (dev_priv->rps.max_freq_softlimit == 0)
4015 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4016
93ee2920
TR
4017 if (dev_priv->rps.min_freq_softlimit == 0) {
4018 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4019 dev_priv->rps.min_freq_softlimit =
f4ab408c
TR
4020 /* max(RPe, 450 MHz) */
4021 max(dev_priv->rps.efficient_freq, (u8) 9);
93ee2920
TR
4022 else
4023 dev_priv->rps.min_freq_softlimit =
4024 dev_priv->rps.min_freq;
4025 }
3280e8b0
BW
4026}
4027
20e49366
ZW
4028static void gen9_enable_rps(struct drm_device *dev)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_engine_cs *ring;
4032 uint32_t rc6_mask = 0;
4033 int unused;
4034
4035 /* 1a: Software RC state - RC0 */
4036 I915_WRITE(GEN6_RC_STATE, 0);
4037
4038 /* 1b: Get forcewake during program sequence. Although the driver
4039 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4040 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4041
4042 /* 2a: Disable RC states. */
4043 I915_WRITE(GEN6_RC_CONTROL, 0);
4044
4045 /* 2b: Program RC6 thresholds.*/
4046 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4047 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4048 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4049 for_each_ring(ring, dev_priv, unused)
4050 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4051 I915_WRITE(GEN6_RC_SLEEP, 0);
4052 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4053
4054 /* 3a: Enable RC6 */
4055 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4056 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4057 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4058 "on" : "off");
4059 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4060 GEN6_RC_CTL_EI_MODE(1) |
4061 rc6_mask);
4062
4063 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4064
4065}
4066
6edee7f3
BW
4067static void gen8_enable_rps(struct drm_device *dev)
4068{
4069 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4070 struct intel_engine_cs *ring;
93ee2920 4071 uint32_t rc6_mask = 0;
6edee7f3
BW
4072 int unused;
4073
4074 /* 1a: Software RC state - RC0 */
4075 I915_WRITE(GEN6_RC_STATE, 0);
4076
4077 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4078 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 4079 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW
4080
4081 /* 2a: Disable RC states. */
4082 I915_WRITE(GEN6_RC_CONTROL, 0);
4083
93ee2920
TR
4084 /* Initialize rps frequencies */
4085 gen6_init_rps_frequencies(dev);
6edee7f3
BW
4086
4087 /* 2b: Program RC6 thresholds.*/
4088 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4089 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4090 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4091 for_each_ring(ring, dev_priv, unused)
4092 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4093 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR
4094 if (IS_BROADWELL(dev))
4095 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4096 else
4097 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW
4098
4099 /* 3: Enable RC6 */
4100 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4101 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4102 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR
4103 if (IS_BROADWELL(dev))
4104 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4105 GEN7_RC_CTL_TO_MODE |
4106 rc6_mask);
4107 else
4108 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4109 GEN6_RC_CTL_EI_MODE(1) |
4110 rc6_mask);
6edee7f3
BW
4111
4112 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW
4113 I915_WRITE(GEN6_RPNSWREQ,
4114 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4115 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4116 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV
4117 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4118 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4119
4120 /* Docs recommend 900MHz, and 300 MHz respectively */
4121 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4122 dev_priv->rps.max_freq_softlimit << 24 |
4123 dev_priv->rps.min_freq_softlimit << 16);
4124
4125 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4126 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4127 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4128 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4129
4130 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW
4131
4132 /* 5: Enable RPS */
7526ed79
DV
4133 I915_WRITE(GEN6_RP_CONTROL,
4134 GEN6_RP_MEDIA_TURBO |
4135 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4136 GEN6_RP_MEDIA_IS_GFX |
4137 GEN6_RP_ENABLE |
4138 GEN6_RP_UP_BUSY_AVG |
4139 GEN6_RP_DOWN_IDLE_AVG);
4140
4141 /* 6: Ring frequency + overclocking (our driver does this later */
4142
c7f3153a
TR
4143 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4144 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
7526ed79 4145
c8d9a590 4146 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW
4147}
4148
79f5b2c7 4149static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4150{
79f5b2c7 4151 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4152 struct intel_engine_cs *ring;
d060c169 4153 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4154 u32 gtfifodbg;
2b4e57bd 4155 int rc6_mode;
42c0526c 4156 int i, ret;
2b4e57bd 4157
4fc688ce 4158 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4159
2b4e57bd
ED
4160 /* Here begins a magic sequence of register writes to enable
4161 * auto-downclocking.
4162 *
4163 * Perhaps there might be some value in exposing these to
4164 * userspace...
4165 */
4166 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED
4167
4168 /* Clear the DBG now so we don't confuse earlier errors */
4169 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4170 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4171 I915_WRITE(GTFIFODBG, gtfifodbg);
4172 }
4173
c8d9a590 4174 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4175
93ee2920
TR
4176 /* Initialize rps frequencies */
4177 gen6_init_rps_frequencies(dev);
dd0a1aa1 4178
2b4e57bd
ED
4179 /* disable the counters and set deterministic thresholds */
4180 I915_WRITE(GEN6_RC_CONTROL, 0);
4181
4182 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4183 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4184 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4185 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4186 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4187
b4519513
CW
4188 for_each_ring(ring, dev_priv, i)
4189 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED
4190
4191 I915_WRITE(GEN6_RC_SLEEP, 0);
4192 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4193 if (IS_IVYBRIDGE(dev))
351aa566
SM
4194 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4195 else
4196 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4197 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED
4198 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4199
5a7dc92a 4200 /* Check if we are enabling RC6 */
2b4e57bd
ED
4201 rc6_mode = intel_enable_rc6(dev_priv->dev);
4202 if (rc6_mode & INTEL_RC6_ENABLE)
4203 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4204
5a7dc92a
ED
4205 /* We don't use those on Haswell */
4206 if (!IS_HASWELL(dev)) {
4207 if (rc6_mode & INTEL_RC6p_ENABLE)
4208 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4209
5a7dc92a
ED
4210 if (rc6_mode & INTEL_RC6pp_ENABLE)
4211 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4212 }
2b4e57bd 4213
dc39fff7 4214 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED
4215
4216 I915_WRITE(GEN6_RC_CONTROL,
4217 rc6_mask |
4218 GEN6_RC_CTL_EI_MODE(1) |
4219 GEN6_RC_CTL_HW_ENABLE);
4220
dd75fdc8
CW
4221 /* Power down if completely idle for over 50ms */
4222 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4223 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4224
42c0526c 4225 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4226 if (ret)
42c0526c 4227 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW
4228
4229 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4230 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4231 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4232 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4233 (pcu_mbox & 0xff) * 50);
b39fb297 4234 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED
4235 }
4236
dd75fdc8 4237 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 4238 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 4239
31643d54
BW
4240 rc6vids = 0;
4241 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4242 if (IS_GEN6(dev) && ret) {
4243 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4244 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4245 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4246 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4247 rc6vids &= 0xffff00;
4248 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4249 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4250 if (ret)
4251 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4252 }
4253
c8d9a590 4254 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED
4255}
4256
c2bc2fc5 4257static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4258{
79f5b2c7 4259 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4260 int min_freq = 15;
3ebecd07
CW
4261 unsigned int gpu_freq;
4262 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4263 int scaling_factor = 180;
eda79642 4264 struct cpufreq_policy *policy;
2b4e57bd 4265
4fc688ce 4266 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4267
eda79642
BW
4268 policy = cpufreq_cpu_get(0);
4269 if (policy) {
4270 max_ia_freq = policy->cpuinfo.max_freq;
4271 cpufreq_cpu_put(policy);
4272 } else {
4273 /*
4274 * Default to measured freq if none found, PCU will ensure we
4275 * don't go over
4276 */
2b4e57bd 4277 max_ia_freq = tsc_khz;
eda79642 4278 }
2b4e57bd
ED
4279
4280 /* Convert from kHz to MHz */
4281 max_ia_freq /= 1000;
4282
153b4b95 4283 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW
4284 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4285 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4286
2b4e57bd
ED
4287 /*
4288 * For each potential GPU frequency, load a ring frequency we'd like
4289 * to use for memory access. We do this by specifying the IA frequency
4290 * the PCU should use as a reference to determine the ring frequency.
4291 */
6985b352 4292 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4293 gpu_freq--) {
6985b352 4294 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW
4295 unsigned int ia_freq = 0, ring_freq = 0;
4296
46c764d4
BW
4297 if (INTEL_INFO(dev)->gen >= 8) {
4298 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4299 ring_freq = max(min_ring_freq, gpu_freq);
4300 } else if (IS_HASWELL(dev)) {
f6aca45c 4301 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW
4302 ring_freq = max(min_ring_freq, ring_freq);
4303 /* leave ia_freq as the default, chosen by cpufreq */
4304 } else {
4305 /* On older processors, there is no separate ring
4306 * clock domain, so in order to boost the bandwidth
4307 * of the ring, we need to upclock the CPU (ia_freq).
4308 *
4309 * For GPU frequencies less than 750MHz,
4310 * just use the lowest ring freq.
4311 */
4312 if (gpu_freq < min_freq)
4313 ia_freq = 800;
4314 else
4315 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4316 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4317 }
2b4e57bd 4318
42c0526c
BW
4319 sandybridge_pcode_write(dev_priv,
4320 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW
4321 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4322 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4323 gpu_freq);
2b4e57bd 4324 }
2b4e57bd
ED
4325}
4326
c2bc2fc5
ID
4327void gen6_update_ring_freq(struct drm_device *dev)
4328{
4329 struct drm_i915_private *dev_priv = dev->dev_private;
4330
4331 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4332 return;
4333
4334 mutex_lock(&dev_priv->rps.hw_lock);
4335 __gen6_update_ring_freq(dev);
4336 mutex_unlock(&dev_priv->rps.hw_lock);
4337}
4338
03af2045 4339static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4340{
095acd5f 4341 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D
4342 u32 val, rp0;
4343
095acd5f
D
4344 if (dev->pdev->revision >= 0x20) {
4345 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4346
095acd5f
D
4347 switch (INTEL_INFO(dev)->eu_total) {
4348 case 8:
4349 /* (2 * 4) config */
4350 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4351 break;
4352 case 12:
4353 /* (2 * 6) config */
4354 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4355 break;
4356 case 16:
4357 /* (2 * 8) config */
4358 default:
4359 /* Setting (2 * 8) Min RP0 for any other combination */
4360 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4361 break;
4362 }
4363 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4364 } else {
4365 /* For pre-production hardware */
4366 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4367 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4368 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4369 }
2b6b3a09
D
4370 return rp0;
4371}
4372
4373static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4374{
4375 u32 val, rpe;
4376
4377 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4378 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4379
4380 return rpe;
4381}
4382
7707df4a
D
4383static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4384{
095acd5f 4385 struct drm_device *dev = dev_priv->dev;
7707df4a
D
4386 u32 val, rp1;
4387
095acd5f
D
4388 if (dev->pdev->revision >= 0x20) {
4389 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4390 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4391 } else {
4392 /* For pre-production hardware */
4393 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4394 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4395 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4396 }
7707df4a
D
4397 return rp1;
4398}
4399
03af2045 4400static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4401{
095acd5f 4402 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D
4403 u32 val, rpn;
4404
095acd5f
D
4405 if (dev->pdev->revision >= 0x20) {
4406 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4407 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4408 FB_GFX_FREQ_FUSE_MASK);
4409 } else { /* For pre-production hardware */
4410 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4411 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4412 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4413 }
4414
2b6b3a09
D
4415 return rpn;
4416}
4417
f8f2b001
D
4418static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4419{
4420 u32 val, rp1;
4421
4422 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4423
4424 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4425
4426 return rp1;
4427}
4428
03af2045 4429static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB
4430{
4431 u32 val, rp0;
4432
64936258 4433 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB
4434
4435 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4436 /* Clamp to max */
4437 rp0 = min_t(u32, rp0, 0xea);
4438
4439 return rp0;
4440}
4441
4442static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4443{
4444 u32 val, rpe;
4445
64936258 4446 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4447 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4448 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB
4449 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4450
4451 return rpe;
4452}
4453
03af2045 4454static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4455{
64936258 4456 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB
4457}
4458
ae48434c
ID
4459/* Check that the pctx buffer wasn't move under us. */
4460static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4461{
4462 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4463
4464 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4465 dev_priv->vlv_pctx->stolen->start);
4466}
4467
38807746
D
4468
4469/* Check that the pcbr address is not empty. */
4470static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4471{
4472 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4473
4474 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4475}
4476
4477static void cherryview_setup_pctx(struct drm_device *dev)
4478{
4479 struct drm_i915_private *dev_priv = dev->dev_private;
4480 unsigned long pctx_paddr, paddr;
4481 struct i915_gtt *gtt = &dev_priv->gtt;
4482 u32 pcbr;
4483 int pctx_size = 32*1024;
4484
4485 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4486
4487 pcbr = I915_READ(VLV_PCBR);
4488 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4489 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D
4490 paddr = (dev_priv->mm.stolen_base +
4491 (gtt->stolen_size - pctx_size));
4492
4493 pctx_paddr = (paddr & (~4095));
4494 I915_WRITE(VLV_PCBR, pctx_paddr);
4495 }
ce611ef8
VS
4496
4497 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D
4498}
4499
c9cddffc
JB
4500static void valleyview_setup_pctx(struct drm_device *dev)
4501{
4502 struct drm_i915_private *dev_priv = dev->dev_private;
4503 struct drm_i915_gem_object *pctx;
4504 unsigned long pctx_paddr;
4505 u32 pcbr;
4506 int pctx_size = 24*1024;
4507
17b0c1f7
ID
4508 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4509
c9cddffc
JB
4510 pcbr = I915_READ(VLV_PCBR);
4511 if (pcbr) {
4512 /* BIOS set it up already, grab the pre-alloc'd space */
4513 int pcbr_offset;
4514
4515 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4516 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4517 pcbr_offset,
190d6cd5 4518 I915_GTT_OFFSET_NONE,
c9cddffc
JB
4519 pctx_size);
4520 goto out;
4521 }
4522
ce611ef8
VS
4523 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4524
c9cddffc
JB
4525 /*
4526 * From the Gunit register HAS:
4527 * The Gfx driver is expected to program this register and ensure
4528 * proper allocation within Gfx stolen memory. For example, this
4529 * register should be programmed such than the PCBR range does not
4530 * overlap with other ranges, such as the frame buffer, protected
4531 * memory, or any other relevant ranges.
4532 */
4533 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4534 if (!pctx) {
4535 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4536 return;
4537 }
4538
4539 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4540 I915_WRITE(VLV_PCBR, pctx_paddr);
4541
4542out:
ce611ef8 4543 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB
4544 dev_priv->vlv_pctx = pctx;
4545}
4546
ae48434c
ID
4547static void valleyview_cleanup_pctx(struct drm_device *dev)
4548{
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550
4551 if (WARN_ON(!dev_priv->vlv_pctx))
4552 return;
4553
4554 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4555 dev_priv->vlv_pctx = NULL;
4556}
4557
4e80519e
ID
4558static void valleyview_init_gt_powersave(struct drm_device *dev)
4559{
4560 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4561 u32 val;
4e80519e
ID
4562
4563 valleyview_setup_pctx(dev);
4564
4565 mutex_lock(&dev_priv->rps.hw_lock);
4566
2bb25c17
VS
4567 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4568 switch ((val >> 6) & 3) {
4569 case 0:
4570 case 1:
4571 dev_priv->mem_freq = 800;
4572 break;
4573 case 2:
4574 dev_priv->mem_freq = 1066;
4575 break;
4576 case 3:
4577 dev_priv->mem_freq = 1333;
4578 break;
4579 }
80b83b62 4580 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4581
4e80519e
ID
4582 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4583 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4584 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4585 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4586 dev_priv->rps.max_freq);
4587
4588 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4589 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4590 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4591 dev_priv->rps.efficient_freq);
4592
f8f2b001
D
4593 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4594 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4595 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4596 dev_priv->rps.rp1_freq);
4597
4e80519e
ID
4598 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4599 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4600 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4601 dev_priv->rps.min_freq);
4602
4603 /* Preserve min/max settings in case of re-init */
4604 if (dev_priv->rps.max_freq_softlimit == 0)
4605 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4606
4607 if (dev_priv->rps.min_freq_softlimit == 0)
4608 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4609
4610 mutex_unlock(&dev_priv->rps.hw_lock);
4611}
4612
38807746
D
4613static void cherryview_init_gt_powersave(struct drm_device *dev)
4614{
2b6b3a09 4615 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4616 u32 val;
2b6b3a09 4617
38807746 4618 cherryview_setup_pctx(dev);
2b6b3a09
D
4619
4620 mutex_lock(&dev_priv->rps.hw_lock);
4621
c6e8f39d
VS
4622 mutex_lock(&dev_priv->dpio_lock);
4623 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4624 mutex_unlock(&dev_priv->dpio_lock);
4625
2bb25c17
VS
4626 switch ((val >> 2) & 0x7) {
4627 case 0:
4628 case 1:
4629 dev_priv->rps.cz_freq = 200;
4630 dev_priv->mem_freq = 1600;
4631 break;
4632 case 2:
4633 dev_priv->rps.cz_freq = 267;
4634 dev_priv->mem_freq = 1600;
4635 break;
4636 case 3:
4637 dev_priv->rps.cz_freq = 333;
4638 dev_priv->mem_freq = 2000;
4639 break;
4640 case 4:
4641 dev_priv->rps.cz_freq = 320;
4642 dev_priv->mem_freq = 1600;
4643 break;
4644 case 5:
4645 dev_priv->rps.cz_freq = 400;
4646 dev_priv->mem_freq = 1600;
4647 break;
4648 }
80b83b62 4649 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4650
2b6b3a09
D
4651 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4652 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4653 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4654 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4655 dev_priv->rps.max_freq);
4656
4657 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4658 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4659 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4660 dev_priv->rps.efficient_freq);
4661
7707df4a
D
4662 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4663 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4664 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4665 dev_priv->rps.rp1_freq);
4666
2b6b3a09
D
4667 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4668 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4669 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4670 dev_priv->rps.min_freq);
4671
1c14762d
VS
4672 WARN_ONCE((dev_priv->rps.max_freq |
4673 dev_priv->rps.efficient_freq |
4674 dev_priv->rps.rp1_freq |
4675 dev_priv->rps.min_freq) & 1,
4676 "Odd GPU freq values\n");
4677
2b6b3a09
D
4678 /* Preserve min/max settings in case of re-init */
4679 if (dev_priv->rps.max_freq_softlimit == 0)
4680 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4681
4682 if (dev_priv->rps.min_freq_softlimit == 0)
4683 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4684
4685 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D
4686}
4687
4e80519e
ID
4688static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4689{
4690 valleyview_cleanup_pctx(dev);
4691}
4692
38807746
D
4693static void cherryview_enable_rps(struct drm_device *dev)
4694{
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 struct intel_engine_cs *ring;
2b6b3a09 4697 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D
4698 int i;
4699
4700 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4701
4702 gtfifodbg = I915_READ(GTFIFODBG);
4703 if (gtfifodbg) {
4704 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4705 gtfifodbg);
4706 I915_WRITE(GTFIFODBG, gtfifodbg);
4707 }
4708
4709 cherryview_check_pctx(dev_priv);
4710
4711 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4712 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4713 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4714
160614a2
VS
4715 /* Disable RC states. */
4716 I915_WRITE(GEN6_RC_CONTROL, 0);
4717
38807746
D
4718 /* 2a: Program RC6 thresholds.*/
4719 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4720 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4721 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4722
4723 for_each_ring(ring, dev_priv, i)
4724 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4725 I915_WRITE(GEN6_RC_SLEEP, 0);
4726
af5a75a3
VS
4727 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4728 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
38807746
D
4729
4730 /* allows RC6 residency counter to work */
4731 I915_WRITE(VLV_COUNTER_CONTROL,
4732 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4733 VLV_MEDIA_RC6_COUNT_EN |
4734 VLV_RENDER_RC6_COUNT_EN));
4735
4736 /* For now we assume BIOS is allocating and populating the PCBR */
4737 pcbr = I915_READ(VLV_PCBR);
4738
38807746
D
4739 /* 3: Enable RC6 */
4740 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4741 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 4742 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D
4743
4744 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4745
2b6b3a09 4746 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 4747 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D
4748 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4749 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4750 I915_WRITE(GEN6_RP_UP_EI, 66000);
4751 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4752
4753 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4754
7405f42c
TR
4755 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4756 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4757 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4758
2b6b3a09
D
4759 /* 5: Enable RPS */
4760 I915_WRITE(GEN6_RP_CONTROL,
4761 GEN6_RP_MEDIA_HW_NORMAL_MODE |
7405f42c 4762 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
2b6b3a09
D
4763 GEN6_RP_ENABLE |
4764 GEN6_RP_UP_BUSY_AVG |
4765 GEN6_RP_DOWN_IDLE_AVG);
4766
4767 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4768
8d40c3ae
VS
4769 /* RPS code assumes GPLL is used */
4770 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
4771
c8e9627d 4772 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D
4773 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4774
4775 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4776 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4777 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4778 dev_priv->rps.cur_freq);
4779
4780 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4781 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4782 dev_priv->rps.efficient_freq);
4783
4784 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4785
38807746
D
4786 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4787}
4788
0a073b84
JB
4789static void valleyview_enable_rps(struct drm_device *dev)
4790{
4791 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4792 struct intel_engine_cs *ring;
2a5913a8 4793 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB
4794 int i;
4795
4796 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4797
ae48434c
ID
4798 valleyview_check_pctx(dev_priv);
4799
0a073b84 4800 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB
4801 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4802 gtfifodbg);
0a073b84
JB
4803 I915_WRITE(GTFIFODBG, gtfifodbg);
4804 }
4805
c8d9a590
D
4806 /* If VLV, Forcewake all wells, else re-direct to regular path */
4807 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 4808
160614a2
VS
4809 /* Disable RC states. */
4810 I915_WRITE(GEN6_RC_CONTROL, 0);
4811
cad725fe 4812 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB
4813 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4814 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4815 I915_WRITE(GEN6_RP_UP_EI, 66000);
4816 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4817
4818 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4819
4820 I915_WRITE(GEN6_RP_CONTROL,
4821 GEN6_RP_MEDIA_TURBO |
4822 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4823 GEN6_RP_MEDIA_IS_GFX |
4824 GEN6_RP_ENABLE |
4825 GEN6_RP_UP_BUSY_AVG |
4826 GEN6_RP_DOWN_IDLE_CONT);
4827
4828 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4829 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4830 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4831
4832 for_each_ring(ring, dev_priv, i)
4833 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4834
2f0aa304 4835 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB
4836
4837 /* allows RC6 residency counter to work */
49798eb2 4838 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D
4839 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
4840 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB
4841 VLV_MEDIA_RC6_COUNT_EN |
4842 VLV_RENDER_RC6_COUNT_EN));
31685c25 4843
a2b23fe0 4844 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4845 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW
4846
4847 intel_print_rc6_info(dev, rc6_mode);
4848
a2b23fe0 4849 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4850
64936258 4851 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 4852
8d40c3ae
VS
4853 /* RPS code assumes GPLL is used */
4854 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
4855
c8e9627d 4856 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB
4857 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4858
b39fb297 4859 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 4860 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW
4861 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4862 dev_priv->rps.cur_freq);
0a073b84 4863
73008b98 4864 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW
4865 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4866 dev_priv->rps.efficient_freq);
0a073b84 4867
b39fb297 4868 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 4869
c8d9a590 4870 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB
4871}
4872
930ebb46 4873void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED
4874{
4875 struct drm_i915_private *dev_priv = dev->dev_private;
4876
3e373948 4877 if (dev_priv->ips.renderctx) {
d7f46fc4 4878 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV
4879 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4880 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED
4881 }
4882
3e373948 4883 if (dev_priv->ips.pwrctx) {
d7f46fc4 4884 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV
4885 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4886 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED
4887 }
4888}
4889
930ebb46 4890static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED
4891{
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893
4894 if (I915_READ(PWRCTXA)) {
4895 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4896 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4897 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4898 50);
4899
4900 I915_WRITE(PWRCTXA, 0);
4901 POSTING_READ(PWRCTXA);
4902
4903 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4904 POSTING_READ(RSTDBYCTL);
4905 }
2b4e57bd
ED
4906}
4907
4908static int ironlake_setup_rc6(struct drm_device *dev)
4909{
4910 struct drm_i915_private *dev_priv = dev->dev_private;
4911
3e373948
DV
4912 if (dev_priv->ips.renderctx == NULL)
4913 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4914 if (!dev_priv->ips.renderctx)
2b4e57bd
ED
4915 return -ENOMEM;
4916
3e373948
DV
4917 if (dev_priv->ips.pwrctx == NULL)
4918 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4919 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED
4920 ironlake_teardown_rc6(dev);
4921 return -ENOMEM;
4922 }
4923
4924 return 0;
4925}
4926
930ebb46 4927static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED
4928{
4929 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4930 struct intel_engine_cs *ring = &dev_priv->ring[RCS];
3e960501 4931 bool was_interruptible;
2b4e57bd
ED
4932 int ret;
4933
4934 /* rc6 disabled by default due to repeated reports of hanging during
4935 * boot and resume.
4936 */
4937 if (!intel_enable_rc6(dev))
4938 return;
4939
79f5b2c7
DV
4940 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4941
2b4e57bd 4942 ret = ironlake_setup_rc6(dev);
79f5b2c7 4943 if (ret)
2b4e57bd 4944 return;
2b4e57bd 4945
3e960501
CW
4946 was_interruptible = dev_priv->mm.interruptible;
4947 dev_priv->mm.interruptible = false;
4948
2b4e57bd
ED
4949 /*
4950 * GPU can automatically power down the render unit if given a page
4951 * to save state.
4952 */
6d90c952 4953 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED
4954 if (ret) {
4955 ironlake_teardown_rc6(dev);
3e960501 4956 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED
4957 return;
4958 }
4959
6d90c952
DV
4960 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4961 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4962 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV
4963 MI_MM_SPACE_GTT |
4964 MI_SAVE_EXT_STATE_EN |
4965 MI_RESTORE_EXT_STATE_EN |
4966 MI_RESTORE_INHIBIT);
4967 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4968 intel_ring_emit(ring, MI_NOOP);
4969 intel_ring_emit(ring, MI_FLUSH);
4970 intel_ring_advance(ring);
2b4e57bd
ED
4971
4972 /*
4973 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4974 * does an implicit flush, combined with MI_FLUSH above, it should be
4975 * safe to assume that renderctx is valid
4976 */
3e960501
CW
4977 ret = intel_ring_idle(ring);
4978 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4979 if (ret) {
def27a58 4980 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4981 ironlake_teardown_rc6(dev);
2b4e57bd
ED
4982 return;
4983 }
4984
f343c5f6 4985 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4986 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4987
91ca689a 4988 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED
4989}
4990
dde18883
ED
4991static unsigned long intel_pxfreq(u32 vidfreq)
4992{
4993 unsigned long freq;
4994 int div = (vidfreq & 0x3f0000) >> 16;
4995 int post = (vidfreq & 0x3000) >> 12;
4996 int pre = (vidfreq & 0x7);
4997
4998 if (!pre)
4999 return 0;
5000
5001 freq = ((div * 133333) / ((1<<post) * pre));
5002
5003 return freq;
5004}
5005
eb48eb00
DV
5006static const struct cparams {
5007 u16 i;
5008 u16 t;
5009 u16 m;
5010 u16 c;
5011} cparams[] = {
5012 { 1, 1333, 301, 28664 },
5013 { 1, 1066, 294, 24460 },
5014 { 1, 800, 294, 25192 },
5015 { 0, 1333, 276, 27605 },
5016 { 0, 1066, 276, 27605 },
5017 { 0, 800, 231, 23784 },
5018};
5019
f531dcb2 5020static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV
5021{
5022 u64 total_count, diff, ret;
5023 u32 count1, count2, count3, m = 0, c = 0;
5024 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5025 int i;
5026
02d71956
DV
5027 assert_spin_locked(&mchdev_lock);
5028
20e4d407 5029 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV
5030
5031 /* Prevent division-by-zero if we are asking too fast.
5032 * Also, we don't get interesting results if we are polling
5033 * faster than once in 10ms, so just return the saved value
5034 * in such cases.
5035 */
5036 if (diff1 <= 10)
20e4d407 5037 return dev_priv->ips.chipset_power;
eb48eb00
DV
5038
5039 count1 = I915_READ(DMIEC);
5040 count2 = I915_READ(DDREC);
5041 count3 = I915_READ(CSIEC);
5042
5043 total_count = count1 + count2 + count3;
5044
5045 /* FIXME: handle per-counter overflow */
20e4d407
DV
5046 if (total_count < dev_priv->ips.last_count1) {
5047 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV
5048 diff += total_count;
5049 } else {
20e4d407 5050 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV
5051 }
5052
5053 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV
5054 if (cparams[i].i == dev_priv->ips.c_m &&
5055 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV
5056 m = cparams[i].m;
5057 c = cparams[i].c;
5058 break;
5059 }
5060 }
5061
5062 diff = div_u64(diff, diff1);
5063 ret = ((m * diff) + c);
5064 ret = div_u64(ret, 10);
5065
20e4d407
DV
5066 dev_priv->ips.last_count1 = total_count;
5067 dev_priv->ips.last_time1 = now;
eb48eb00 5068
20e4d407 5069 dev_priv->ips.chipset_power = ret;
eb48eb00
DV
5070
5071 return ret;
5072}
5073
f531dcb2
CW
5074unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5075{
3d13ef2e 5076 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW
5077 unsigned long val;
5078
3d13ef2e 5079 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW
5080 return 0;
5081
5082 spin_lock_irq(&mchdev_lock);
5083
5084 val = __i915_chipset_val(dev_priv);
5085
5086 spin_unlock_irq(&mchdev_lock);
5087
5088 return val;
5089}
5090
eb48eb00
DV
5091unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5092{
5093 unsigned long m, x, b;
5094 u32 tsfs;
5095
5096 tsfs = I915_READ(TSFS);
5097
5098 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5099 x = I915_READ8(TR1);
5100
5101 b = tsfs & TSFS_INTR_MASK;
5102
5103 return ((m * x) / 127) - b;
5104}
5105
d972d6ee
MK
5106static int _pxvid_to_vd(u8 pxvid)
5107{
5108 if (pxvid == 0)
5109 return 0;
5110
5111 if (pxvid >= 8 && pxvid < 31)
5112 pxvid = 31;
5113
5114 return (pxvid + 2) * 125;
5115}
5116
5117static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5118{
3d13ef2e 5119 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK
5120 const int vd = _pxvid_to_vd(pxvid);
5121 const int vm = vd - 1125;
5122
3d13ef2e 5123 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK
5124 return vm > 0 ? vm : 0;
5125
5126 return vd;
eb48eb00
DV
5127}
5128
02d71956 5129static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5130{
5ed0bdf2 5131 u64 now, diff, diffms;
eb48eb00
DV
5132 u32 count;
5133
02d71956 5134 assert_spin_locked(&mchdev_lock);
eb48eb00 5135
5ed0bdf2
TG
5136 now = ktime_get_raw_ns();
5137 diffms = now - dev_priv->ips.last_time2;
5138 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV
5139
5140 /* Don't divide by 0 */
eb48eb00
DV
5141 if (!diffms)
5142 return;
5143
5144 count = I915_READ(GFXEC);
5145
20e4d407
DV
5146 if (count < dev_priv->ips.last_count2) {
5147 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV
5148 diff += count;
5149 } else {
20e4d407 5150 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV
5151 }
5152
20e4d407
DV
5153 dev_priv->ips.last_count2 = count;
5154 dev_priv->ips.last_time2 = now;
eb48eb00
DV
5155
5156 /* More magic constants... */
5157 diff = diff * 1181;
5158 diff = div_u64(diff, diffms * 10);
20e4d407 5159 dev_priv->ips.gfx_power = diff;
eb48eb00
DV
5160}
5161
02d71956
DV
5162void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5163{
3d13ef2e
DL
5164 struct drm_device *dev = dev_priv->dev;
5165
5166 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV
5167 return;
5168
9270388e 5169 spin_lock_irq(&mchdev_lock);
02d71956
DV
5170
5171 __i915_update_gfx_val(dev_priv);
5172
9270388e 5173 spin_unlock_irq(&mchdev_lock);
02d71956
DV
5174}
5175
f531dcb2 5176static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV
5177{
5178 unsigned long t, corr, state1, corr2, state2;
5179 u32 pxvid, ext_v;
5180
02d71956
DV
5181 assert_spin_locked(&mchdev_lock);
5182
b39fb297 5183 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV
5184 pxvid = (pxvid >> 24) & 0x7f;
5185 ext_v = pvid_to_extvid(dev_priv, pxvid);
5186
5187 state1 = ext_v;
5188
5189 t = i915_mch_val(dev_priv);
5190
5191 /* Revel in the empirically derived constants */
5192
5193 /* Correction factor in 1/100000 units */
5194 if (t > 80)
5195 corr = ((t * 2349) + 135940);
5196 else if (t >= 50)
5197 corr = ((t * 964) + 29317);
5198 else /* < 50 */
5199 corr = ((t * 301) + 1004);
5200
5201 corr = corr * ((150142 * state1) / 10000 - 78642);
5202 corr /= 100000;
20e4d407 5203 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV
5204
5205 state2 = (corr2 * state1) / 10000;
5206 state2 /= 100; /* convert to mW */
5207
02d71956 5208 __i915_update_gfx_val(dev_priv);
eb48eb00 5209
20e4d407 5210 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV
5211}
5212
f531dcb2
CW
5213unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5214{
3d13ef2e 5215 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW
5216 unsigned long val;
5217
3d13ef2e 5218 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW
5219 return 0;
5220
5221 spin_lock_irq(&mchdev_lock);
5222
5223 val = __i915_gfx_val(dev_priv);
5224
5225 spin_unlock_irq(&mchdev_lock);
5226
5227 return val;
5228}
5229
eb48eb00
DV
5230/**
5231 * i915_read_mch_val - return value for IPS use
5232 *
5233 * Calculate and return a value for the IPS driver to use when deciding whether
5234 * we have thermal and power headroom to increase CPU or GPU power budget.
5235 */
5236unsigned long i915_read_mch_val(void)
5237{
5238 struct drm_i915_private *dev_priv;
5239 unsigned long chipset_val, graphics_val, ret = 0;
5240
9270388e 5241 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5242 if (!i915_mch_dev)
5243 goto out_unlock;
5244 dev_priv = i915_mch_dev;
5245
f531dcb2
CW
5246 chipset_val = __i915_chipset_val(dev_priv);
5247 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV
5248
5249 ret = chipset_val + graphics_val;
5250
5251out_unlock:
9270388e 5252 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5253
5254 return ret;
5255}
5256EXPORT_SYMBOL_GPL(i915_read_mch_val);
5257
5258/**
5259 * i915_gpu_raise - raise GPU frequency limit
5260 *
5261 * Raise the limit; IPS indicates we have thermal headroom.
5262 */
5263bool i915_gpu_raise(void)
5264{
5265 struct drm_i915_private *dev_priv;
5266 bool ret = true;
5267
9270388e 5268 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5269 if (!i915_mch_dev) {
5270 ret = false;
5271 goto out_unlock;
5272 }
5273 dev_priv = i915_mch_dev;
5274
20e4d407
DV
5275 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5276 dev_priv->ips.max_delay--;
eb48eb00
DV
5277
5278out_unlock:
9270388e 5279 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5280
5281 return ret;
5282}
5283EXPORT_SYMBOL_GPL(i915_gpu_raise);
5284
5285/**
5286 * i915_gpu_lower - lower GPU frequency limit
5287 *
5288 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5289 * frequency maximum.
5290 */
5291bool i915_gpu_lower(void)
5292{
5293 struct drm_i915_private *dev_priv;
5294 bool ret = true;
5295
9270388e 5296 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5297 if (!i915_mch_dev) {
5298 ret = false;
5299 goto out_unlock;
5300 }
5301 dev_priv = i915_mch_dev;
5302
20e4d407
DV
5303 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5304 dev_priv->ips.max_delay++;
eb48eb00
DV
5305
5306out_unlock:
9270388e 5307 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5308
5309 return ret;
5310}
5311EXPORT_SYMBOL_GPL(i915_gpu_lower);
5312
5313/**
5314 * i915_gpu_busy - indicate GPU business to IPS
5315 *
5316 * Tell the IPS driver whether or not the GPU is busy.
5317 */
5318bool i915_gpu_busy(void)
5319{
5320 struct drm_i915_private *dev_priv;
a4872ba6 5321 struct intel_engine_cs *ring;
eb48eb00 5322 bool ret = false;
f047e395 5323 int i;
eb48eb00 5324
9270388e 5325 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5326 if (!i915_mch_dev)
5327 goto out_unlock;
5328 dev_priv = i915_mch_dev;
5329
f047e395
CW
5330 for_each_ring(ring, dev_priv, i)
5331 ret |= !list_empty(&ring->request_list);
eb48eb00
DV
5332
5333out_unlock:
9270388e 5334 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5335
5336 return ret;
5337}
5338EXPORT_SYMBOL_GPL(i915_gpu_busy);
5339
5340/**
5341 * i915_gpu_turbo_disable - disable graphics turbo
5342 *
5343 * Disable graphics turbo by resetting the max frequency and setting the
5344 * current frequency to the default.
5345 */
5346bool i915_gpu_turbo_disable(void)
5347{
5348 struct drm_i915_private *dev_priv;
5349 bool ret = true;
5350
9270388e 5351 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5352 if (!i915_mch_dev) {
5353 ret = false;
5354 goto out_unlock;
5355 }
5356 dev_priv = i915_mch_dev;
5357
20e4d407 5358 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5359
20e4d407 5360 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV
5361 ret = false;
5362
5363out_unlock:
9270388e 5364 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5365
5366 return ret;
5367}
5368EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5369
5370/**
5371 * Tells the intel_ips driver that the i915 driver is now loaded, if
5372 * IPS got loaded first.
5373 *
5374 * This awkward dance is so that neither module has to depend on the
5375 * other in order for IPS to do the appropriate communication of
5376 * GPU turbo limits to i915.
5377 */
5378static void
5379ips_ping_for_i915_load(void)
5380{
5381 void (*link)(void);
5382
5383 link = symbol_get(ips_link_to_i915_driver);
5384 if (link) {
5385 link();
5386 symbol_put(ips_link_to_i915_driver);
5387 }
5388}
5389
5390void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5391{
02d71956
DV
5392 /* We only register the i915 ips part with intel-ips once everything is
5393 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5394 spin_lock_irq(&mchdev_lock);
eb48eb00 5395 i915_mch_dev = dev_priv;
9270388e 5396 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5397
5398 ips_ping_for_i915_load();
5399}
5400
5401void intel_gpu_ips_teardown(void)
5402{
9270388e 5403 spin_lock_irq(&mchdev_lock);
eb48eb00 5404 i915_mch_dev = NULL;
9270388e 5405 spin_unlock_irq(&mchdev_lock);
eb48eb00 5406}
76c3552f 5407
8090c6b9 5408static void intel_init_emon(struct drm_device *dev)
dde18883
ED
5409{
5410 struct drm_i915_private *dev_priv = dev->dev_private;
5411 u32 lcfuse;
5412 u8 pxw[16];
5413 int i;
5414
5415 /* Disable to program */
5416 I915_WRITE(ECR, 0);
5417 POSTING_READ(ECR);
5418
5419 /* Program energy weights for various events */
5420 I915_WRITE(SDEW, 0x15040d00);
5421 I915_WRITE(CSIEW0, 0x007f0000);
5422 I915_WRITE(CSIEW1, 0x1e220004);
5423 I915_WRITE(CSIEW2, 0x04000004);
5424
5425 for (i = 0; i < 5; i++)
5426 I915_WRITE(PEW + (i * 4), 0);
5427 for (i = 0; i < 3; i++)
5428 I915_WRITE(DEW + (i * 4), 0);
5429
5430 /* Program P-state weights to account for frequency power adjustment */
5431 for (i = 0; i < 16; i++) {
5432 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5433 unsigned long freq = intel_pxfreq(pxvidfreq);
5434 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5435 PXVFREQ_PX_SHIFT;
5436 unsigned long val;
5437
5438 val = vid * vid;
5439 val *= (freq / 1000);
5440 val *= 255;
5441 val /= (127*127*900);
5442 if (val > 0xff)
5443 DRM_ERROR("bad pxval: %ld\n", val);
5444 pxw[i] = val;
5445 }
5446 /* Render standby states get 0 weight */
5447 pxw[14] = 0;
5448 pxw[15] = 0;
5449
5450 for (i = 0; i < 4; i++) {
5451 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5452 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5453 I915_WRITE(PXW + (i * 4), val);
5454 }
5455
5456 /* Adjust magic regs to magic values (more experimental results) */
5457 I915_WRITE(OGW0, 0);
5458 I915_WRITE(OGW1, 0);
5459 I915_WRITE(EG0, 0x00007f00);
5460 I915_WRITE(EG1, 0x0000000e);
5461 I915_WRITE(EG2, 0x000e0000);
5462 I915_WRITE(EG3, 0x68000300);
5463 I915_WRITE(EG4, 0x42000000);
5464 I915_WRITE(EG5, 0x00140031);
5465 I915_WRITE(EG6, 0);
5466 I915_WRITE(EG7, 0);
5467
5468 for (i = 0; i < 8; i++)
5469 I915_WRITE(PXWL + (i * 4), 0);
5470
5471 /* Enable PMON + select events */
5472 I915_WRITE(ECR, 0x80000019);
5473
5474 lcfuse = I915_READ(LCFUSE02);
5475
20e4d407 5476 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED
5477}
5478
ae48434c
ID
5479void intel_init_gt_powersave(struct drm_device *dev)
5480{
e6069ca8
ID
5481 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5482
38807746
D
5483 if (IS_CHERRYVIEW(dev))
5484 cherryview_init_gt_powersave(dev);
5485 else if (IS_VALLEYVIEW(dev))
4e80519e 5486 valleyview_init_gt_powersave(dev);
ae48434c
ID
5487}
5488
5489void intel_cleanup_gt_powersave(struct drm_device *dev)
5490{
38807746
D
5491 if (IS_CHERRYVIEW(dev))
5492 return;
5493 else if (IS_VALLEYVIEW(dev))
4e80519e 5494 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID
5495}
5496
dbea3cea
ID
5497static void gen6_suspend_rps(struct drm_device *dev)
5498{
5499 struct drm_i915_private *dev_priv = dev->dev_private;
5500
5501 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5502
5503 /*
5504 * TODO: disable RPS interrupts on GEN9+ too once RPS support
5505 * is added for it.
5506 */
5507 if (INTEL_INFO(dev)->gen < 9)
5508 gen6_disable_rps_interrupts(dev);
5509}
5510
156c7ca0
JB
5511/**
5512 * intel_suspend_gt_powersave - suspend PM work and helper threads
5513 * @dev: drm device
5514 *
5515 * We don't want to disable RC6 or other features here, we just want
5516 * to make sure any work we've queued has finished and won't bother
5517 * us while we're suspended.
5518 */
5519void intel_suspend_gt_powersave(struct drm_device *dev)
5520{
5521 struct drm_i915_private *dev_priv = dev->dev_private;
5522
d4d70aa5
ID
5523 if (INTEL_INFO(dev)->gen < 6)
5524 return;
5525
dbea3cea 5526 gen6_suspend_rps(dev);
b47adc17
D
5527
5528 /* Force GPU to min freq during suspend */
5529 gen6_rps_idle(dev_priv);
156c7ca0
JB
5530}
5531
8090c6b9
DV
5532void intel_disable_gt_powersave(struct drm_device *dev)
5533{
1a01ab3b
JB
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535
930ebb46 5536 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5537 ironlake_disable_drps(dev);
930ebb46 5538 ironlake_disable_rc6(dev);
38807746 5539 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5540 intel_suspend_gt_powersave(dev);
e494837a 5541
4fc688ce 5542 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW
5543 if (INTEL_INFO(dev)->gen >= 9)
5544 gen9_disable_rps(dev);
5545 else if (IS_CHERRYVIEW(dev))
38807746
D
5546 cherryview_disable_rps(dev);
5547 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB
5548 valleyview_disable_rps(dev);
5549 else
5550 gen6_disable_rps(dev);
e534770a 5551
c0951f0c 5552 dev_priv->rps.enabled = false;
4fc688ce 5553 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5554 }
8090c6b9
DV
5555}
5556
1a01ab3b
JB
5557static void intel_gen6_powersave_work(struct work_struct *work)
5558{
5559 struct drm_i915_private *dev_priv =
5560 container_of(work, struct drm_i915_private,
5561 rps.delayed_resume_work.work);
5562 struct drm_device *dev = dev_priv->dev;
5563
4fc688ce 5564 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5565
3cc134e3
ID
5566 /*
5567 * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is
5568 * added for it.
5569 */
5570 if (INTEL_INFO(dev)->gen < 9)
5571 gen6_reset_rps_interrupts(dev);
5572
38807746
D
5573 if (IS_CHERRYVIEW(dev)) {
5574 cherryview_enable_rps(dev);
5575 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5576 valleyview_enable_rps(dev);
20e49366
ZW
5577 } else if (INTEL_INFO(dev)->gen >= 9) {
5578 gen9_enable_rps(dev);
6edee7f3
BW
5579 } else if (IS_BROADWELL(dev)) {
5580 gen8_enable_rps(dev);
c2bc2fc5 5581 __gen6_update_ring_freq(dev);
0a073b84
JB
5582 } else {
5583 gen6_enable_rps(dev);
c2bc2fc5 5584 __gen6_update_ring_freq(dev);
0a073b84 5585 }
c0951f0c 5586 dev_priv->rps.enabled = true;
3cc134e3
ID
5587
5588 if (INTEL_INFO(dev)->gen < 9)
5589 gen6_enable_rps_interrupts(dev);
5590
4fc688ce 5591 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID
5592
5593 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB
5594}
5595
8090c6b9
DV
5596void intel_enable_gt_powersave(struct drm_device *dev)
5597{
1a01ab3b
JB
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599
8090c6b9 5600 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5601 mutex_lock(&dev->struct_mutex);
8090c6b9
DV
5602 ironlake_enable_drps(dev);
5603 ironlake_enable_rc6(dev);
5604 intel_init_emon(dev);
dc1d0136 5605 mutex_unlock(&dev->struct_mutex);
38807746 5606 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB
5607 /*
5608 * PCU communication is slow and this doesn't need to be
5609 * done at any specific time, so do this out of our fast path
5610 * to make resume and init faster.
c6df39b5
ID
5611 *
5612 * We depend on the HW RC6 power context save/restore
5613 * mechanism when entering D3 through runtime PM suspend. So
5614 * disable RPM until RPS/RC6 is properly setup. We can only
5615 * get here via the driver load/system resume/runtime resume
5616 * paths, so the _noresume version is enough (and in case of
5617 * runtime resume it's necessary).
1a01ab3b 5618 */
c6df39b5
ID
5619 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5620 round_jiffies_up_relative(HZ)))
5621 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV
5622 }
5623}
5624
c6df39b5
ID
5625void intel_reset_gt_powersave(struct drm_device *dev)
5626{
5627 struct drm_i915_private *dev_priv = dev->dev_private;
5628
dbea3cea
ID
5629 if (INTEL_INFO(dev)->gen < 6)
5630 return;
5631
5632 gen6_suspend_rps(dev);
c6df39b5 5633 dev_priv->rps.enabled = false;
c6df39b5
ID
5634}
5635
3107bd48
DV
5636static void ibx_init_clock_gating(struct drm_device *dev)
5637{
5638 struct drm_i915_private *dev_priv = dev->dev_private;
5639
5640 /*
5641 * On Ibex Peak and Cougar Point, we need to disable clock
5642 * gating for the panel power sequencer or it will fail to
5643 * start up when no ports are active.
5644 */
5645 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5646}
5647
0e088b8f
VS
5648static void g4x_disable_trickle_feed(struct drm_device *dev)
5649{
5650 struct drm_i915_private *dev_priv = dev->dev_private;
5651 int pipe;
5652
055e393f 5653 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS
5654 I915_WRITE(DSPCNTR(pipe),
5655 I915_READ(DSPCNTR(pipe)) |
5656 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5657 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS
5658 }
5659}
5660
017636cc
VS
5661static void ilk_init_lp_watermarks(struct drm_device *dev)
5662{
5663 struct drm_i915_private *dev_priv = dev->dev_private;
5664
5665 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5666 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5667 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5668
5669 /*
5670 * Don't touch WM1S_LP_EN here.
5671 * Doing so could cause underruns.
5672 */
5673}
5674
1fa61106 5675static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
5676{
5677 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5678 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5679
f1e8fa56
DL
5680 /*
5681 * Required for FBC
5682 * WaFbcDisableDpfcClockGating:ilk
5683 */
4d47e4f5
DL
5684 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5685 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5686 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED
5687
5688 I915_WRITE(PCH_3DCGDIS0,
5689 MARIUNIT_CLOCK_GATE_DISABLE |
5690 SVSMUNIT_CLOCK_GATE_DISABLE);
5691 I915_WRITE(PCH_3DCGDIS1,
5692 VFMUNIT_CLOCK_GATE_DISABLE);
5693
6f1d69b0
ED
5694 /*
5695 * According to the spec the following bits should be set in
5696 * order to enable memory self-refresh
5697 * The bit 22/21 of 0x42004
5698 * The bit 5 of 0x42020
5699 * The bit 15 of 0x45000
5700 */
5701 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5702 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5703 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5704 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED
5705 I915_WRITE(DISP_ARB_CTL,
5706 (I915_READ(DISP_ARB_CTL) |
5707 DISP_FBC_WM_DIS));
017636cc
VS
5708
5709 ilk_init_lp_watermarks(dev);
6f1d69b0
ED
5710
5711 /*
5712 * Based on the document from hardware guys the following bits
5713 * should be set unconditionally in order to enable FBC.
5714 * The bit 22 of 0x42000
5715 * The bit 22 of 0x42004
5716 * The bit 7,8,9 of 0x42020.
5717 */
5718 if (IS_IRONLAKE_M(dev)) {
4bb35334 5719 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED
5720 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5721 I915_READ(ILK_DISPLAY_CHICKEN1) |
5722 ILK_FBCQ_DIS);
5723 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5724 I915_READ(ILK_DISPLAY_CHICKEN2) |
5725 ILK_DPARB_GATE);
6f1d69b0
ED
5726 }
5727
4d47e4f5
DL
5728 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5729
6f1d69b0
ED
5730 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5731 I915_READ(ILK_DISPLAY_CHICKEN2) |
5732 ILK_ELPIN_409_SELECT);
5733 I915_WRITE(_3D_CHICKEN2,
5734 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5735 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5736
ecdb4eb7 5737 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV
5738 I915_WRITE(CACHE_MODE_0,
5739 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5740
4e04632e
AG
5741 /* WaDisable_RenderCache_OperationalFlush:ilk */
5742 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5743
0e088b8f 5744 g4x_disable_trickle_feed(dev);
bdad2b2f 5745
3107bd48
DV
5746 ibx_init_clock_gating(dev);
5747}
5748
5749static void cpt_init_clock_gating(struct drm_device *dev)
5750{
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 int pipe;
3f704fa2 5753 uint32_t val;
3107bd48
DV
5754
5755 /*
5756 * On Ibex Peak and Cougar Point, we need to disable clock
5757 * gating for the panel power sequencer or it will fail to
5758 * start up when no ports are active.
5759 */
cd664078
JB
5760 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5761 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5762 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV
5763 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5764 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI
5765 /* The below fixes the weird display corruption, a few pixels shifted
5766 * downward, on (only) LVDS of some HP laptops with IVY.
5767 */
055e393f 5768 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ
5769 val = I915_READ(TRANS_CHICKEN2(pipe));
5770 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5771 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5772 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5773 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ
5774 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5775 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5776 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ
5777 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5778 }
3107bd48 5779 /* WADP0ClockGatingDisable */
055e393f 5780 for_each_pipe(dev_priv, pipe) {
3107bd48
DV
5781 I915_WRITE(TRANS_CHICKEN1(pipe),
5782 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5783 }
6f1d69b0
ED
5784}
5785
1d7aaa0c
DV
5786static void gen6_check_mch_setup(struct drm_device *dev)
5787{
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 uint32_t tmp;
5790
5791 tmp = I915_READ(MCH_SSKPD);
df662a28
DV
5792 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5793 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5794 tmp);
1d7aaa0c
DV
5795}
5796
1fa61106 5797static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
5798{
5799 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5800 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5801
231e54f6 5802 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED
5803
5804 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5805 I915_READ(ILK_DISPLAY_CHICKEN2) |
5806 ILK_ELPIN_409_SELECT);
5807
ecdb4eb7 5808 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV
5809 I915_WRITE(_3D_CHICKEN,
5810 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5811
4e04632e
AG
5812 /* WaDisable_RenderCache_OperationalFlush:snb */
5813 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5814
8d85d272
VS
5815 /*
5816 * BSpec recoomends 8x4 when MSAA is used,
5817 * however in practice 16x4 seems fastest.
c5c98a58
VS
5818 *
5819 * Note that PS/WM thread counts depend on the WIZ hashing
5820 * disable bit, which we don't touch here, but it's good
5821 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS
5822 */
5823 I915_WRITE(GEN6_GT_MODE,
98533251 5824 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 5825
017636cc 5826 ilk_init_lp_watermarks(dev);
6f1d69b0 5827
6f1d69b0 5828 I915_WRITE(CACHE_MODE_0,
50743298 5829 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED
5830
5831 I915_WRITE(GEN6_UCGCTL1,
5832 I915_READ(GEN6_UCGCTL1) |
5833 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5834 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5835
5836 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5837 * gating disable must be set. Failure to set it results in
5838 * flickering pixels due to Z write ordering failures after
5839 * some amount of runtime in the Mesa "fire" demo, and Unigine
5840 * Sanctuary and Tropics, and apparently anything else with
5841 * alpha test or pixel discard.
5842 *
5843 * According to the spec, bit 11 (RCCUNIT) must also be set,
5844 * but we didn't debug actual testcases to find it out.
0f846f81 5845 *
ef59318c
VS
5846 * WaDisableRCCUnitClockGating:snb
5847 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED
5848 */
5849 I915_WRITE(GEN6_UCGCTL2,
5850 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5851 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5852
5eb146dd 5853 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS
5854 I915_WRITE(_3D_CHICKEN3,
5855 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5856
e927ecde
VS
5857 /*
5858 * Bspec says:
5859 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5860 * 3DSTATE_SF number of SF output attributes is more than 16."
5861 */
5862 I915_WRITE(_3D_CHICKEN3,
5863 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5864
6f1d69b0
ED
5865 /*
5866 * According to the spec the following bits should be
5867 * set in order to enable memory self-refresh and fbc:
5868 * The bit21 and bit22 of 0x42000
5869 * The bit21 and bit22 of 0x42004
5870 * The bit5 and bit7 of 0x42020
5871 * The bit14 of 0x70180
5872 * The bit14 of 0x71180
4bb35334
DL
5873 *
5874 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED
5875 */
5876 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5877 I915_READ(ILK_DISPLAY_CHICKEN1) |
5878 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5879 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5880 I915_READ(ILK_DISPLAY_CHICKEN2) |
5881 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL
5882 I915_WRITE(ILK_DSPCLK_GATE_D,
5883 I915_READ(ILK_DSPCLK_GATE_D) |
5884 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5885 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5886
0e088b8f 5887 g4x_disable_trickle_feed(dev);
f8f2ac9a 5888
3107bd48 5889 cpt_init_clock_gating(dev);
1d7aaa0c
DV
5890
5891 gen6_check_mch_setup(dev);
6f1d69b0
ED
5892}
5893
5894static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5895{
5896 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5897
3aad9059 5898 /*
46680e0a 5899 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS
5900 *
5901 * This actually overrides the dispatch
5902 * mode for all thread types.
5903 */
6f1d69b0
ED
5904 reg &= ~GEN7_FF_SCHED_MASK;
5905 reg |= GEN7_FF_TS_SCHED_HW;
5906 reg |= GEN7_FF_VS_SCHED_HW;
5907 reg |= GEN7_FF_DS_SCHED_HW;
5908
5909 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5910}
5911
17a303ec
PZ
5912static void lpt_init_clock_gating(struct drm_device *dev)
5913{
5914 struct drm_i915_private *dev_priv = dev->dev_private;
5915
5916 /*
5917 * TODO: this bit should only be enabled when really needed, then
5918 * disabled when not needed anymore in order to save power.
5919 */
5920 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5921 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5922 I915_READ(SOUTH_DSPCLK_GATE_D) |
5923 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ
5924
5925 /* WADPOClockGatingDisable:hsw */
5926 I915_WRITE(_TRANSA_CHICKEN1,
5927 I915_READ(_TRANSA_CHICKEN1) |
5928 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ
5929}
5930
7d708ee4
ID
5931static void lpt_suspend_hw(struct drm_device *dev)
5932{
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934
5935 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5936 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5937
5938 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5939 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5940 }
5941}
5942
47c2bd97 5943static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW
5944{
5945 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5946 enum pipe pipe;
1020a5c2
BW
5947
5948 I915_WRITE(WM3_LP_ILK, 0);
5949 I915_WRITE(WM2_LP_ILK, 0);
5950 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 5951
ab57fff1 5952 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5953 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5954
ab57fff1 5955 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW
5956 I915_WRITE(CHICKEN_PAR1_1,
5957 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5958
ab57fff1 5959 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 5960 for_each_pipe(dev_priv, pipe) {
07d27e20 5961 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5962 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5963 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5964 }
63801f21 5965
ab57fff1
BW
5966 /* WaVSRefCountFullforceMissDisable:bdw */
5967 /* WaDSRefCountFullforceMissDisable:bdw */
5968 I915_WRITE(GEN7_FF_THREAD_MODE,
5969 I915_READ(GEN7_FF_THREAD_MODE) &
5970 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 5971
295e8bb7
VS
5972 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5973 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS
5974
5975 /* WaDisableSDEUnitClockGating:bdw */
5976 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5977 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 5978
89d6b2b8 5979 lpt_init_clock_gating(dev);
1020a5c2
BW
5980}
5981
cad2a2d7
ED
5982static void haswell_init_clock_gating(struct drm_device *dev)
5983{
5984 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5985
017636cc 5986 ilk_init_lp_watermarks(dev);
cad2a2d7 5987
f3fc4884
FJ
5988 /* L3 caching of data atomics doesn't work -- disable it. */
5989 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5990 I915_WRITE(HSW_ROW_CHICKEN3,
5991 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5992
ecdb4eb7 5993 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED
5994 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5995 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5996 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5997
e36ea7ff
VS
5998 /* WaVSRefCountFullforceMissDisable:hsw */
5999 I915_WRITE(GEN7_FF_THREAD_MODE,
6000 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6001
4e04632e
AG
6002 /* WaDisable_RenderCache_OperationalFlush:hsw */
6003 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6004
fe27c606
CW
6005 /* enable HiZ Raw Stall Optimization */
6006 I915_WRITE(CACHE_MODE_0_GEN7,
6007 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6008
ecdb4eb7 6009 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED
6010 I915_WRITE(CACHE_MODE_1,
6011 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6012
a12c4967
VS
6013 /*
6014 * BSpec recommends 8x4 when MSAA is used,
6015 * however in practice 16x4 seems fastest.
c5c98a58
VS
6016 *
6017 * Note that PS/WM thread counts depend on the WIZ hashing
6018 * disable bit, which we don't touch here, but it's good
6019 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS
6020 */
6021 I915_WRITE(GEN7_GT_MODE,
98533251 6022 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6023
94411593
KG
6024 /* WaSampleCChickenBitEnable:hsw */
6025 I915_WRITE(HALF_SLICE_CHICKEN3,
6026 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6027
ecdb4eb7 6028 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW
6029 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6030
90a88643
PZ
6031 /* WaRsPkgCStateDisplayPMReq:hsw */
6032 I915_WRITE(CHICKEN_PAR1_1,
6033 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6034
17a303ec 6035 lpt_init_clock_gating(dev);
cad2a2d7
ED
6036}
6037
1fa61106 6038static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6039{
6040 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6041 uint32_t snpcr;
6f1d69b0 6042
017636cc 6043 ilk_init_lp_watermarks(dev);
6f1d69b0 6044
231e54f6 6045 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6046
ecdb4eb7 6047 /* WaDisableEarlyCull:ivb */
87f8020e
JB
6048 I915_WRITE(_3D_CHICKEN3,
6049 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6050
ecdb4eb7 6051 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED
6052 I915_WRITE(IVB_CHICKEN3,
6053 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6054 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6055
ecdb4eb7 6056 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB
6057 if (IS_IVB_GT1(dev))
6058 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6059 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6060
4e04632e
AG
6061 /* WaDisable_RenderCache_OperationalFlush:ivb */
6062 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6063
ecdb4eb7 6064 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED
6065 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6066 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6067
ecdb4eb7 6068 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED
6069 I915_WRITE(GEN7_L3CNTLREG1,
6070 GEN7_WA_FOR_GEN7_L3_CONTROL);
6071 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB
6072 GEN7_WA_L3_CHICKEN_MODE);
6073 if (IS_IVB_GT1(dev))
6074 I915_WRITE(GEN7_ROW_CHICKEN2,
6075 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS
6076 else {
6077 /* must write both registers */
6078 I915_WRITE(GEN7_ROW_CHICKEN2,
6079 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB
6080 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6081 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6082 }
6f1d69b0 6083
ecdb4eb7 6084 /* WaForceL3Serialization:ivb */
61939d97
JB
6085 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6086 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6087
1b80a19a 6088 /*
0f846f81 6089 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6090 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB
6091 */
6092 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6093 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6094
ecdb4eb7 6095 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED
6096 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6097 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6098 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6099
0e088b8f 6100 g4x_disable_trickle_feed(dev);
6f1d69b0
ED
6101
6102 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6103
22721343
CW
6104 if (0) { /* causes HiZ corruption on ivb:gt1 */
6105 /* enable HiZ Raw Stall Optimization */
6106 I915_WRITE(CACHE_MODE_0_GEN7,
6107 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6108 }
116f2b6d 6109
ecdb4eb7 6110 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV
6111 I915_WRITE(CACHE_MODE_1,
6112 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6113
a607c1a4
VS
6114 /*
6115 * BSpec recommends 8x4 when MSAA is used,
6116 * however in practice 16x4 seems fastest.
c5c98a58
VS
6117 *
6118 * Note that PS/WM thread counts depend on the WIZ hashing
6119 * disable bit, which we don't touch here, but it's good
6120 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS
6121 */
6122 I915_WRITE(GEN7_GT_MODE,
98533251 6123 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6124
20848223
BW
6125 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6126 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6127 snpcr |= GEN6_MBC_SNPCR_MED;
6128 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6129
ab5c608b
BW
6130 if (!HAS_PCH_NOP(dev))
6131 cpt_init_clock_gating(dev);
1d7aaa0c
DV
6132
6133 gen6_check_mch_setup(dev);
6f1d69b0
ED
6134}
6135
1fa61106 6136static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6137{
6138 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6139
d7fe0cc0 6140 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6141
ecdb4eb7 6142 /* WaDisableEarlyCull:vlv */
87f8020e
JB
6143 I915_WRITE(_3D_CHICKEN3,
6144 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6145
ecdb4eb7 6146 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED
6147 I915_WRITE(IVB_CHICKEN3,
6148 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6149 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6150
fad7d36e 6151 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6152 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6153 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB
6154 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6155 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6156
4e04632e
AG
6157 /* WaDisable_RenderCache_OperationalFlush:vlv */
6158 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6159
ecdb4eb7 6160 /* WaForceL3Serialization:vlv */
61939d97
JB
6161 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6162 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6163
ecdb4eb7 6164 /* WaDisableDopClockGating:vlv */
8ab43976
JB
6165 I915_WRITE(GEN7_ROW_CHICKEN2,
6166 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6167
ecdb4eb7 6168 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED
6169 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6170 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6171 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6172
46680e0a
VS
6173 gen7_setup_fixed_func_scheduler(dev_priv);
6174
3c0edaeb 6175 /*
0f846f81 6176 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6177 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB
6178 */
6179 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6180 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6181
c98f5062
AG
6182 /* WaDisableL3Bank2xClockGate:vlv
6183 * Disabling L3 clock gating- MMIO 940c[25] = 1
6184 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6185 I915_WRITE(GEN7_UCGCTL4,
6186 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6187
e0d8d59b 6188 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 6189
afd58e79
VS
6190 /*
6191 * BSpec says this must be set, even though
6192 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6193 */
6b26c86d
DV
6194 I915_WRITE(CACHE_MODE_1,
6195 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6196
031994ee
VS
6197 /*
6198 * WaIncreaseL3CreditsForVLVB0:vlv
6199 * This is the hardware default actually.
6200 */
6201 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6202
2d809570 6203 /*
ecdb4eb7 6204 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB
6205 * Disable clock gating on th GCFG unit to prevent a delay
6206 * in the reporting of vblank events.
6207 */
7a0d1eed 6208 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED
6209}
6210
a4565da8
VS
6211static void cherryview_init_clock_gating(struct drm_device *dev)
6212{
6213 struct drm_i915_private *dev_priv = dev->dev_private;
6214
6215 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6216
6217 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70 6218
232ce337
VS
6219 /* WaVSRefCountFullforceMissDisable:chv */
6220 /* WaDSRefCountFullforceMissDisable:chv */
6221 I915_WRITE(GEN7_FF_THREAD_MODE,
6222 I915_READ(GEN7_FF_THREAD_MODE) &
6223 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS
6224
6225 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6226 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6227 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS
6228
6229 /* WaDisableCSUnitClockGating:chv */
6230 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6231 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS
6232
6233 /* WaDisableSDEUnitClockGating:chv */
6234 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6235 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS
6236}
6237
1fa61106 6238static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6239{
6240 struct drm_i915_private *dev_priv = dev->dev_private;
6241 uint32_t dspclk_gate;
6242
6243 I915_WRITE(RENCLK_GATE_D1, 0);
6244 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6245 GS_UNIT_CLOCK_GATE_DISABLE |
6246 CL_UNIT_CLOCK_GATE_DISABLE);
6247 I915_WRITE(RAMCLK_GATE_D, 0);
6248 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6249 OVRUNIT_CLOCK_GATE_DISABLE |
6250 OVCUNIT_CLOCK_GATE_DISABLE;
6251 if (IS_GM45(dev))
6252 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6253 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV
6254
6255 /* WaDisableRenderCachePipelinedFlush */
6256 I915_WRITE(CACHE_MODE_0,
6257 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6258
4e04632e
AG
6259 /* WaDisable_RenderCache_OperationalFlush:g4x */
6260 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6261
0e088b8f 6262 g4x_disable_trickle_feed(dev);
6f1d69b0
ED
6263}
6264
1fa61106 6265static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6266{
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268
6269 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6270 I915_WRITE(RENCLK_GATE_D2, 0);
6271 I915_WRITE(DSPCLK_GATE_D, 0);
6272 I915_WRITE(RAMCLK_GATE_D, 0);
6273 I915_WRITE16(DEUC, 0);
20f94967
VS
6274 I915_WRITE(MI_ARB_STATE,
6275 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG
6276
6277 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6278 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED
6279}
6280
1fa61106 6281static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6282{
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284
6285 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6286 I965_RCC_CLOCK_GATE_DISABLE |
6287 I965_RCPB_CLOCK_GATE_DISABLE |
6288 I965_ISC_CLOCK_GATE_DISABLE |
6289 I965_FBC_CLOCK_GATE_DISABLE);
6290 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS
6291 I915_WRITE(MI_ARB_STATE,
6292 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG
6293
6294 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6295 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED
6296}
6297
1fa61106 6298static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6299{
6300 struct drm_i915_private *dev_priv = dev->dev_private;
6301 u32 dstate = I915_READ(D_STATE);
6302
6303 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6304 DSTATE_DOT_CLOCK_GATING;
6305 I915_WRITE(D_STATE, dstate);
13a86b85
CW
6306
6307 if (IS_PINEVIEW(dev))
6308 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV
6309
6310 /* IIR "flip pending" means done if this bit is set */
6311 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS
6312
6313 /* interrupts should cause a wake up from C3 */
3299254f 6314 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS
6315
6316 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6317 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS
6318
6319 I915_WRITE(MI_ARB_STATE,
6320 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED
6321}
6322
1fa61106 6323static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6324{
6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326
6327 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS
6328
6329 /* interrupts should cause a wake up from C3 */
6330 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6331 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS
6332
6333 I915_WRITE(MEM_MODE,
6334 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED
6335}
6336
1fa61106 6337static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6338{
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340
6341 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS
6342
6343 I915_WRITE(MEM_MODE,
6344 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6345 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED
6346}
6347
6f1d69b0
ED
6348void intel_init_clock_gating(struct drm_device *dev)
6349{
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351
6352 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED
6353}
6354
7d708ee4
ID
6355void intel_suspend_hw(struct drm_device *dev)
6356{
6357 if (HAS_PCH_LPT(dev))
6358 lpt_suspend_hw(dev);
6359}
6360
1fa61106
ED
6361/* Set up chip specific power management-related functions */
6362void intel_init_pm(struct drm_device *dev)
6363{
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365
7ff0ebcc 6366 intel_fbc_init(dev_priv);
1fa61106 6367
c921aba8
DV
6368 /* For cxsr */
6369 if (IS_PINEVIEW(dev))
6370 i915_pineview_get_mem_freq(dev);
6371 else if (IS_GEN5(dev))
6372 i915_ironlake_get_mem_freq(dev);
6373
1fa61106 6374 /* For FIFO watermark updates */
f5ed50cb 6375 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB
6376 skl_setup_wm_latency(dev);
6377
c83155a6 6378 dev_priv->display.init_clock_gating = gen9_init_clock_gating;
2d41c0b5
PB
6379 dev_priv->display.update_wm = skl_update_wm;
6380 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6381 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6382 ilk_setup_wm_latency(dev);
53615a5e 6383
bd602544
VS
6384 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6385 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6386 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6387 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6388 dev_priv->display.update_wm = ilk_update_wm;
6389 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6390 } else {
6391 DRM_DEBUG_KMS("Failed to read display plane latency. "
6392 "Disable CxSR\n");
6393 }
6394
6395 if (IS_GEN5(dev))
1fa61106 6396 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6397 else if (IS_GEN6(dev))
1fa61106 6398 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6399 else if (IS_IVYBRIDGE(dev))
1fa61106 6400 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6401 else if (IS_HASWELL(dev))
cad2a2d7 6402 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6403 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6404 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6405 } else if (IS_CHERRYVIEW(dev)) {
3c2777fd 6406 dev_priv->display.update_wm = cherryview_update_wm;
01e184cc 6407 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS
6408 dev_priv->display.init_clock_gating =
6409 cherryview_init_clock_gating;
1fa61106
ED
6410 } else if (IS_VALLEYVIEW(dev)) {
6411 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6412 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED
6413 dev_priv->display.init_clock_gating =
6414 valleyview_init_clock_gating;
1fa61106
ED
6415 } else if (IS_PINEVIEW(dev)) {
6416 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6417 dev_priv->is_ddr3,
6418 dev_priv->fsb_freq,
6419 dev_priv->mem_freq)) {
6420 DRM_INFO("failed to find known CxSR latency "
6421 "(found ddr%s fsb freq %d, mem freq %d), "
6422 "disabling CxSR\n",
6423 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6424 dev_priv->fsb_freq, dev_priv->mem_freq);
6425 /* Disable CxSR and never update its watermark again */
5209b1f4 6426 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED
6427 dev_priv->display.update_wm = NULL;
6428 } else
6429 dev_priv->display.update_wm = pineview_update_wm;
6430 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6431 } else if (IS_G4X(dev)) {
6432 dev_priv->display.update_wm = g4x_update_wm;
6433 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6434 } else if (IS_GEN4(dev)) {
6435 dev_priv->display.update_wm = i965_update_wm;
6436 if (IS_CRESTLINE(dev))
6437 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6438 else if (IS_BROADWATER(dev))
6439 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6440 } else if (IS_GEN3(dev)) {
6441 dev_priv->display.update_wm = i9xx_update_wm;
6442 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6443 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV
6444 } else if (IS_GEN2(dev)) {
6445 if (INTEL_INFO(dev)->num_pipes == 1) {
6446 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6447 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV
6448 } else {
6449 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6450 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV
6451 }
6452
6453 if (IS_I85X(dev) || IS_I865G(dev))
6454 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6455 else
6456 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6457 } else {
6458 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED
6459 }
6460}
6461
151a49d0 6462int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6463{
4fc688ce 6464 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW
6465
6466 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6467 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6468 return -EAGAIN;
6469 }
6470
6471 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6472 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW
6473 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6474
6475 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6476 500)) {
6477 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6478 return -ETIMEDOUT;
6479 }
6480
6481 *val = I915_READ(GEN6_PCODE_DATA);
6482 I915_WRITE(GEN6_PCODE_DATA, 0);
6483
6484 return 0;
6485}
6486
151a49d0 6487int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6488{
4fc688ce 6489 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW
6490
6491 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6492 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6493 return -EAGAIN;
6494 }
6495
6496 I915_WRITE(GEN6_PCODE_DATA, val);
6497 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6498
6499 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6500 500)) {
6501 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6502 return -ETIMEDOUT;
6503 }
6504
6505 I915_WRITE(GEN6_PCODE_DATA, 0);
6506
6507 return 0;
6508}
a0e4e199 6509
dd06f88c 6510static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6511{
dd06f88c
VS
6512 switch (czclk_freq) {
6513 case 200:
6514 return 10;
6515 case 267:
6516 return 12;
6517 case 320:
6518 case 333:
dd06f88c 6519 return 16;
ab3fb157
VS
6520 case 400:
6521 return 20;
855ba3be
JB
6522 default:
6523 return -1;
6524 }
dd06f88c 6525}
855ba3be 6526
dd06f88c
VS
6527static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6528{
6529 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6530
6531 div = vlv_gpu_freq_div(czclk_freq);
6532 if (div < 0)
6533 return div;
6534
6535 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB
6536}
6537
b55dd647 6538static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6539{
dd06f88c 6540 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6541
dd06f88c
VS
6542 mul = vlv_gpu_freq_div(czclk_freq);
6543 if (mul < 0)
6544 return mul;
855ba3be 6545
dd06f88c 6546 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB
6547}
6548
b55dd647 6549static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6550{
dd06f88c 6551 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6552
dd06f88c
VS
6553 div = vlv_gpu_freq_div(czclk_freq) / 2;
6554 if (div < 0)
6555 return div;
22b1b2f8 6556
dd06f88c 6557 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D
6558}
6559
b55dd647 6560static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6561{
dd06f88c 6562 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6563
dd06f88c
VS
6564 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6565 if (mul < 0)
6566 return mul;
22b1b2f8 6567
1c14762d 6568 /* CHV needs even values */
dd06f88c 6569 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D
6570}
6571
6572int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6573{
6574 int ret = -1;
6575
6576 if (IS_CHERRYVIEW(dev_priv->dev))
6577 ret = chv_gpu_freq(dev_priv, val);
6578 else if (IS_VALLEYVIEW(dev_priv->dev))
6579 ret = byt_gpu_freq(dev_priv, val);
6580
6581 return ret;
6582}
6583
6584int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6585{
6586 int ret = -1;
6587
6588 if (IS_CHERRYVIEW(dev_priv->dev))
6589 ret = chv_freq_opcode(dev_priv, val);
6590 else if (IS_VALLEYVIEW(dev_priv->dev))
6591 ret = byt_freq_opcode(dev_priv, val);
6592
6593 return ret;
6594}
6595
f742a552 6596void intel_pm_setup(struct drm_device *dev)
907b28c5
CW
6597{
6598 struct drm_i915_private *dev_priv = dev->dev_private;
6599
f742a552
DV
6600 mutex_init(&dev_priv->rps.hw_lock);
6601
907b28c5
CW
6602 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6603 intel_gen6_powersave_work);
5d584b2e 6604
33688d95 6605 dev_priv->pm.suspended = false;
907b28c5 6606}