]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/gen9: Merge two WA as they part of same register
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
6381b550
NH		 62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
77719d28 66}
91e41d16 67
45db2194 68static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 69{
acd5c346 70 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 71
77719d28
DL		 72 gen9_init_clock_gating(dev);
73
669506e7 74 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 75 /*
76 * WaDisableSDEUnitClockGating:skl
9253c2e5 77 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 78 */
79 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 80 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 81 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 82
83 /* WaDisableVFUnitClockGating:skl */
84 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
85 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 86 }
8bc0ccf6 87
2caa3b26 88 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 89 /* WaDisableHDCInvalidation:skl */
90 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
91 BDW_DISABLE_HDC_INVALIDATION);
92
2caa3b26
DL		 93 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
94 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 95 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 96 }
81e231af 97
a4106a78
AS		 98 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
99 * involving this register should also be added to WA batch as required.
100 */
8bc0ccf6
DL		 101 if (INTEL_REVID(dev) <= SKL_REVID_E0)
102 /* WaDisableLSQCROPERFforOCL:skl */
103 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
104 GEN8_LQSC_RO_PERF_DIS);
245d9667
AS		 105
106 /* WaEnableGapsTsvCreditFix:skl */
107 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
108 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
109 GEN9_GAPS_TSV_CREDIT_DISABLE));
110 }
da2078cd
DL		 111}
112
a82abe43
ID		 113static void bxt_init_clock_gating(struct drm_device *dev)
114{
32608ca2
ID		 115 struct drm_i915_private *dev_priv = dev->dev_private;
116
a82abe43 117 gen9_init_clock_gating(dev);
32608ca2 118
a7546159
NH		 119 /* WaDisableSDEUnitClockGating:bxt */
120 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
121 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
122
32608ca2
ID		 123 /*
124 * FIXME:
868434c5 125 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 126 */
32608ca2 127 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 128 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 129
a7546159
NH		 130 if (INTEL_REVID(dev) == BXT_REVID_A0) {
131 /*
132 * Hardware specification requires this bit to be
133 * set to 1 for A0
134 */
135 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
136 }
5b88abac
AS		 137
138 /* WaSetClckGatingDisableMedia:bxt */
139 if (INTEL_REVID(dev) == BXT_REVID_A0) {
140 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
141 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
142 }
a82abe43
ID		 143}
144
c921aba8
DV		 145static void i915_pineview_get_mem_freq(struct drm_device *dev)
146{
50227e1c 147 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 148 u32 tmp;
149
150 tmp = I915_READ(CLKCFG);
151
152 switch (tmp & CLKCFG_FSB_MASK) {
153 case CLKCFG_FSB_533:
154 dev_priv->fsb_freq = 533; /* 133*4 */
155 break;
156 case CLKCFG_FSB_800:
157 dev_priv->fsb_freq = 800; /* 200*4 */
158 break;
159 case CLKCFG_FSB_667:
160 dev_priv->fsb_freq = 667; /* 167*4 */
161 break;
162 case CLKCFG_FSB_400:
163 dev_priv->fsb_freq = 400; /* 100*4 */
164 break;
165 }
166
167 switch (tmp & CLKCFG_MEM_MASK) {
168 case CLKCFG_MEM_533:
169 dev_priv->mem_freq = 533;
170 break;
171 case CLKCFG_MEM_667:
172 dev_priv->mem_freq = 667;
173 break;
174 case CLKCFG_MEM_800:
175 dev_priv->mem_freq = 800;
176 break;
177 }
178
179 /* detect pineview DDR3 setting */
180 tmp = I915_READ(CSHRDDR3CTL);
181 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
182}
183
184static void i915_ironlake_get_mem_freq(struct drm_device *dev)
185{
50227e1c 186 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 187 u16 ddrpll, csipll;
188
189 ddrpll = I915_READ16(DDRMPLL1);
190 csipll = I915_READ16(CSIPLL0);
191
192 switch (ddrpll & 0xff) {
193 case 0xc:
194 dev_priv->mem_freq = 800;
195 break;
196 case 0x10:
197 dev_priv->mem_freq = 1066;
198 break;
199 case 0x14:
200 dev_priv->mem_freq = 1333;
201 break;
202 case 0x18:
203 dev_priv->mem_freq = 1600;
204 break;
205 default:
206 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
207 ddrpll & 0xff);
208 dev_priv->mem_freq = 0;
209 break;
210 }
211
20e4d407 212 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 213
214 switch (csipll & 0x3ff) {
215 case 0x00c:
216 dev_priv->fsb_freq = 3200;
217 break;
218 case 0x00e:
219 dev_priv->fsb_freq = 3733;
220 break;
221 case 0x010:
222 dev_priv->fsb_freq = 4266;
223 break;
224 case 0x012:
225 dev_priv->fsb_freq = 4800;
226 break;
227 case 0x014:
228 dev_priv->fsb_freq = 5333;
229 break;
230 case 0x016:
231 dev_priv->fsb_freq = 5866;
232 break;
233 case 0x018:
234 dev_priv->fsb_freq = 6400;
235 break;
236 default:
237 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
238 csipll & 0x3ff);
239 dev_priv->fsb_freq = 0;
240 break;
241 }
242
243 if (dev_priv->fsb_freq == 3200) {
20e4d407 244 dev_priv->ips.c_m = 0;
c921aba8 245 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 246 dev_priv->ips.c_m = 1;
c921aba8 247 } else {
20e4d407 248 dev_priv->ips.c_m = 2;
c921aba8
DV		 249 }
250}
251
b445e3b0
ED		 252static const struct cxsr_latency cxsr_latency_table[] = {
253 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
254 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
255 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
256 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
257 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
258
259 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
260 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
261 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
262 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
263 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
264
265 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
266 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
267 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
268 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
269 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
270
271 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
272 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
273 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
274 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
275 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
276
277 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
278 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
279 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
280 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
281 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
282
283 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
284 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
285 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
286 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
287 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
288};
289
63c62275 290static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 291 int is_ddr3,
292 int fsb,
293 int mem)
294{
295 const struct cxsr_latency *latency;
296 int i;
297
298 if (fsb == 0 || mem == 0)
299 return NULL;
300
301 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
302 latency = &cxsr_latency_table[i];
303 if (is_desktop == latency->is_desktop &&
304 is_ddr3 == latency->is_ddr3 &&
305 fsb == latency->fsb_freq && mem == latency->mem_freq)
306 return latency;
307 }
308
309 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
310
311 return NULL;
312}
313
fc1ac8de
VS		 314static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
315{
316 u32 val;
317
318 mutex_lock(&dev_priv->rps.hw_lock);
319
320 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
321 if (enable)
322 val &= ~FORCE_DDR_HIGH_FREQ;
323 else
324 val |= FORCE_DDR_HIGH_FREQ;
325 val &= ~FORCE_DDR_LOW_FREQ;
326 val |= FORCE_DDR_FREQ_REQ_ACK;
327 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
328
329 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
330 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
331 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
332
333 mutex_unlock(&dev_priv->rps.hw_lock);
334}
335
cfb41411
VS		 336static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
337{
338 u32 val;
339
340 mutex_lock(&dev_priv->rps.hw_lock);
341
342 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
343 if (enable)
344 val |= DSP_MAXFIFO_PM5_ENABLE;
345 else
346 val &= ~DSP_MAXFIFO_PM5_ENABLE;
347 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
348
349 mutex_unlock(&dev_priv->rps.hw_lock);
350}
351
f4998963
VS		 352#define FW_WM(value, plane) \
353 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
354
5209b1f4 355void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 356{
5209b1f4
ID		 357 struct drm_device *dev = dev_priv->dev;
358 u32 val;
b445e3b0 359
5209b1f4
ID		 360 if (IS_VALLEYVIEW(dev)) {
361 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 362 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 363 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 364 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
365 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 366 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 367 } else if (IS_PINEVIEW(dev)) {
368 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
369 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
370 I915_WRITE(DSPFW3, val);
a7a6c498 371 POSTING_READ(DSPFW3);
5209b1f4
ID		 372 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
373 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
374 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
375 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 376 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 377 } else if (IS_I915GM(dev)) {
378 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
379 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
380 I915_WRITE(INSTPM, val);
a7a6c498 381 POSTING_READ(INSTPM);
5209b1f4
ID		 382 } else {
383 return;
384 }
b445e3b0 385
5209b1f4
ID		 386 DRM_DEBUG_KMS("memory self-refresh is %s\n",
387 enable ? "enabled" : "disabled");
b445e3b0
ED		 388}
389
fc1ac8de 390
b445e3b0
ED		 391/*
392 * Latency for FIFO fetches is dependent on several factors:
393 * - memory configuration (speed, channels)
394 * - chipset
395 * - current MCH state
396 * It can be fairly high in some situations, so here we assume a fairly
397 * pessimal value. It's a tradeoff between extra memory fetches (if we
398 * set this value too high, the FIFO will fetch frequently to stay full)
399 * and power consumption (set it too low to save power and we might see
400 * FIFO underruns and display "flicker").
401 *
402 * A value of 5us seems to be a good balance; safe for very low end
403 * platforms but not overly aggressive on lower latency configs.
404 */
5aef6003 405static const int pessimal_latency_ns = 5000;
b445e3b0 406
b5004720
VS		 407#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
408 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
409
410static int vlv_get_fifo_size(struct drm_device *dev,
411 enum pipe pipe, int plane)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414 int sprite0_start, sprite1_start, size;
415
416 switch (pipe) {
417 uint32_t dsparb, dsparb2, dsparb3;
418 case PIPE_A:
419 dsparb = I915_READ(DSPARB);
420 dsparb2 = I915_READ(DSPARB2);
421 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
422 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
423 break;
424 case PIPE_B:
425 dsparb = I915_READ(DSPARB);
426 dsparb2 = I915_READ(DSPARB2);
427 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
428 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
429 break;
430 case PIPE_C:
431 dsparb2 = I915_READ(DSPARB2);
432 dsparb3 = I915_READ(DSPARB3);
433 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
434 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
435 break;
436 default:
437 return 0;
438 }
439
440 switch (plane) {
441 case 0:
442 size = sprite0_start;
443 break;
444 case 1:
445 size = sprite1_start - sprite0_start;
446 break;
447 case 2:
448 size = 512 - 1 - sprite1_start;
449 break;
450 default:
451 return 0;
452 }
453
454 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
455 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
456 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
457 size);
458
459 return size;
460}
461
1fa61106 462static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 463{
464 struct drm_i915_private *dev_priv = dev->dev_private;
465 uint32_t dsparb = I915_READ(DSPARB);
466 int size;
467
468 size = dsparb & 0x7f;
469 if (plane)
470 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476}
477
feb56b93 478static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 479{
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 uint32_t dsparb = I915_READ(DSPARB);
482 int size;
483
484 size = dsparb & 0x1ff;
485 if (plane)
486 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
487 size >>= 1; /* Convert to cachelines */
488
489 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
490 plane ? "B" : "A", size);
491
492 return size;
493}
494
1fa61106 495static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 496{
497 struct drm_i915_private *dev_priv = dev->dev_private;
498 uint32_t dsparb = I915_READ(DSPARB);
499 int size;
500
501 size = dsparb & 0x7f;
502 size >>= 2; /* Convert to cachelines */
503
504 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
505 plane ? "B" : "A",
506 size);
507
508 return size;
509}
510
b445e3b0
ED		 511/* Pineview has different values for various configs */
512static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 513 .fifo_size = PINEVIEW_DISPLAY_FIFO,
514 .max_wm = PINEVIEW_MAX_WM,
515 .default_wm = PINEVIEW_DFT_WM,
516 .guard_size = PINEVIEW_GUARD_WM,
517 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 518};
519static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 520 .fifo_size = PINEVIEW_DISPLAY_FIFO,
521 .max_wm = PINEVIEW_MAX_WM,
522 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
523 .guard_size = PINEVIEW_GUARD_WM,
524 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 525};
526static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 527 .fifo_size = PINEVIEW_CURSOR_FIFO,
528 .max_wm = PINEVIEW_CURSOR_MAX_WM,
529 .default_wm = PINEVIEW_CURSOR_DFT_WM,
530 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
531 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 532};
533static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 534 .fifo_size = PINEVIEW_CURSOR_FIFO,
535 .max_wm = PINEVIEW_CURSOR_MAX_WM,
536 .default_wm = PINEVIEW_CURSOR_DFT_WM,
537 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
538 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 539};
540static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 541 .fifo_size = G4X_FIFO_SIZE,
542 .max_wm = G4X_MAX_WM,
543 .default_wm = G4X_MAX_WM,
544 .guard_size = 2,
545 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 546};
547static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 548 .fifo_size = I965_CURSOR_FIFO,
549 .max_wm = I965_CURSOR_MAX_WM,
550 .default_wm = I965_CURSOR_DFT_WM,
551 .guard_size = 2,
552 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 553};
554static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 555 .fifo_size = VALLEYVIEW_FIFO_SIZE,
556 .max_wm = VALLEYVIEW_MAX_WM,
557 .default_wm = VALLEYVIEW_MAX_WM,
558 .guard_size = 2,
559 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 560};
561static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 562 .fifo_size = I965_CURSOR_FIFO,
563 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
564 .default_wm = I965_CURSOR_DFT_WM,
565 .guard_size = 2,
566 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 567};
568static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 569 .fifo_size = I965_CURSOR_FIFO,
570 .max_wm = I965_CURSOR_MAX_WM,
571 .default_wm = I965_CURSOR_DFT_WM,
572 .guard_size = 2,
573 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 574};
575static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 576 .fifo_size = I945_FIFO_SIZE,
577 .max_wm = I915_MAX_WM,
578 .default_wm = 1,
579 .guard_size = 2,
580 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 581};
582static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 583 .fifo_size = I915_FIFO_SIZE,
584 .max_wm = I915_MAX_WM,
585 .default_wm = 1,
586 .guard_size = 2,
587 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 588};
9d539105 589static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 590 .fifo_size = I855GM_FIFO_SIZE,
591 .max_wm = I915_MAX_WM,
592 .default_wm = 1,
593 .guard_size = 2,
594 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 595};
9d539105
VS		 596static const struct intel_watermark_params i830_bc_wm_info = {
597 .fifo_size = I855GM_FIFO_SIZE,
598 .max_wm = I915_MAX_WM/2,
599 .default_wm = 1,
600 .guard_size = 2,
601 .cacheline_size = I830_FIFO_LINE_SIZE,
602};
feb56b93 603static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 604 .fifo_size = I830_FIFO_SIZE,
605 .max_wm = I915_MAX_WM,
606 .default_wm = 1,
607 .guard_size = 2,
608 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 609};
610
b445e3b0
ED		 611/**
612 * intel_calculate_wm - calculate watermark level
613 * @clock_in_khz: pixel clock
614 * @wm: chip FIFO params
615 * @pixel_size: display pixel size
616 * @latency_ns: memory latency for the platform
617 *
618 * Calculate the watermark level (the level at which the display plane will
619 * start fetching from memory again). Each chip has a different display
620 * FIFO size and allocation, so the caller needs to figure that out and pass
621 * in the correct intel_watermark_params structure.
622 *
623 * As the pixel clock runs, the FIFO will be drained at a rate that depends
624 * on the pixel size. When it reaches the watermark level, it'll start
625 * fetching FIFO line sized based chunks from memory until the FIFO fills
626 * past the watermark point. If the FIFO drains completely, a FIFO underrun
627 * will occur, and a display engine hang could result.
628 */
629static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
630 const struct intel_watermark_params *wm,
631 int fifo_size,
632 int pixel_size,
633 unsigned long latency_ns)
634{
635 long entries_required, wm_size;
636
637 /*
638 * Note: we need to make sure we don't overflow for various clock &
639 * latency values.
640 * clocks go from a few thousand to several hundred thousand.
641 * latency is usually a few thousand
642 */
643 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
644 1000;
645 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
646
647 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
648
649 wm_size = fifo_size - (entries_required + wm->guard_size);
650
651 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
652
653 /* Don't promote wm_size to unsigned... */
654 if (wm_size > (long)wm->max_wm)
655 wm_size = wm->max_wm;
656 if (wm_size <= 0)
657 wm_size = wm->default_wm;
d6feb196
VS		 658
659 /*
660 * Bspec seems to indicate that the value shouldn't be lower than
661 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
662 * Lets go for 8 which is the burst size since certain platforms
663 * already use a hardcoded 8 (which is what the spec says should be
664 * done).
665 */
666 if (wm_size <= 8)
667 wm_size = 8;
668
b445e3b0
ED		 669 return wm_size;
670}
671
672static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
673{
674 struct drm_crtc *crtc, *enabled = NULL;
675
70e1e0ec 676 for_each_crtc(dev, crtc) {
3490ea5d 677 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 678 if (enabled)
679 return NULL;
680 enabled = crtc;
681 }
682 }
683
684 return enabled;
685}
686
46ba614c 687static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 688{
46ba614c 689 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 690 struct drm_i915_private *dev_priv = dev->dev_private;
691 struct drm_crtc *crtc;
692 const struct cxsr_latency *latency;
693 u32 reg;
694 unsigned long wm;
695
696 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
697 dev_priv->fsb_freq, dev_priv->mem_freq);
698 if (!latency) {
699 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 700 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 701 return;
702 }
703
704 crtc = single_enabled_crtc(dev);
705 if (crtc) {
7c5f93b0 706 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 707 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 708 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 709
710 /* Display SR */
711 wm = intel_calculate_wm(clock, &pineview_display_wm,
712 pineview_display_wm.fifo_size,
713 pixel_size, latency->display_sr);
714 reg = I915_READ(DSPFW1);
715 reg &= ~DSPFW_SR_MASK;
f4998963 716 reg |= FW_WM(wm, SR);
b445e3b0
ED		 717 I915_WRITE(DSPFW1, reg);
718 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
719
720 /* cursor SR */
721 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
722 pineview_display_wm.fifo_size,
723 pixel_size, latency->cursor_sr);
724 reg = I915_READ(DSPFW3);
725 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 726 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 727 I915_WRITE(DSPFW3, reg);
728
729 /* Display HPLL off SR */
730 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
731 pineview_display_hplloff_wm.fifo_size,
732 pixel_size, latency->display_hpll_disable);
733 reg = I915_READ(DSPFW3);
734 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 735 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 736 I915_WRITE(DSPFW3, reg);
737
738 /* cursor HPLL off SR */
739 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
740 pineview_display_hplloff_wm.fifo_size,
741 pixel_size, latency->cursor_hpll_disable);
742 reg = I915_READ(DSPFW3);
743 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 744 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 745 I915_WRITE(DSPFW3, reg);
746 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
747
5209b1f4 748 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 749 } else {
5209b1f4 750 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 751 }
752}
753
754static bool g4x_compute_wm0(struct drm_device *dev,
755 int plane,
756 const struct intel_watermark_params *display,
757 int display_latency_ns,
758 const struct intel_watermark_params *cursor,
759 int cursor_latency_ns,
760 int *plane_wm,
761 int *cursor_wm)
762{
763 struct drm_crtc *crtc;
4fe8590a 764 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 765 int htotal, hdisplay, clock, pixel_size;
766 int line_time_us, line_count;
767 int entries, tlb_miss;
768
769 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 770 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 771 *cursor_wm = cursor->guard_size;
772 *plane_wm = display->guard_size;
773 return false;
774 }
775
6e3c9717 776 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 777 clock = adjusted_mode->crtc_clock;
fec8cba3 778 htotal = adjusted_mode->crtc_htotal;
6e3c9717 779 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 780 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 781
782 /* Use the small buffer method to calculate plane watermark */
783 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
784 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
785 if (tlb_miss > 0)
786 entries += tlb_miss;
787 entries = DIV_ROUND_UP(entries, display->cacheline_size);
788 *plane_wm = entries + display->guard_size;
789 if (*plane_wm > (int)display->max_wm)
790 *plane_wm = display->max_wm;
791
792 /* Use the large buffer method to calculate cursor watermark */
922044c9 793 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 794 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 795 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 796 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
797 if (tlb_miss > 0)
798 entries += tlb_miss;
799 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
800 *cursor_wm = entries + cursor->guard_size;
801 if (*cursor_wm > (int)cursor->max_wm)
802 *cursor_wm = (int)cursor->max_wm;
803
804 return true;
805}
806
807/*
808 * Check the wm result.
809 *
810 * If any calculated watermark values is larger than the maximum value that
811 * can be programmed into the associated watermark register, that watermark
812 * must be disabled.
813 */
814static bool g4x_check_srwm(struct drm_device *dev,
815 int display_wm, int cursor_wm,
816 const struct intel_watermark_params *display,
817 const struct intel_watermark_params *cursor)
818{
819 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
820 display_wm, cursor_wm);
821
822 if (display_wm > display->max_wm) {
823 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
824 display_wm, display->max_wm);
825 return false;
826 }
827
828 if (cursor_wm > cursor->max_wm) {
829 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
830 cursor_wm, cursor->max_wm);
831 return false;
832 }
833
834 if (!(display_wm || cursor_wm)) {
835 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
836 return false;
837 }
838
839 return true;
840}
841
842static bool g4x_compute_srwm(struct drm_device *dev,
843 int plane,
844 int latency_ns,
845 const struct intel_watermark_params *display,
846 const struct intel_watermark_params *cursor,
847 int *display_wm, int *cursor_wm)
848{
849 struct drm_crtc *crtc;
4fe8590a 850 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 851 int hdisplay, htotal, pixel_size, clock;
852 unsigned long line_time_us;
853 int line_count, line_size;
854 int small, large;
855 int entries;
856
857 if (!latency_ns) {
858 *display_wm = *cursor_wm = 0;
859 return false;
860 }
861
862 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 863 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 864 clock = adjusted_mode->crtc_clock;
fec8cba3 865 htotal = adjusted_mode->crtc_htotal;
6e3c9717 866 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 867 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 868
922044c9 869 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 870 line_count = (latency_ns / line_time_us + 1000) / 1000;
871 line_size = hdisplay * pixel_size;
872
873 /* Use the minimum of the small and large buffer method for primary */
874 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
875 large = line_count * line_size;
876
877 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
878 *display_wm = entries + display->guard_size;
879
880 /* calculate the self-refresh watermark for display cursor */
3dd512fb 881 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 882 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
883 *cursor_wm = entries + cursor->guard_size;
884
885 return g4x_check_srwm(dev,
886 *display_wm, *cursor_wm,
887 display, cursor);
888}
889
15665979
VS		 890#define FW_WM_VLV(value, plane) \
891 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
892
0018fda1
VS		 893static void vlv_write_wm_values(struct intel_crtc *crtc,
894 const struct vlv_wm_values *wm)
895{
896 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
897 enum pipe pipe = crtc->pipe;
898
899 I915_WRITE(VLV_DDL(pipe),
900 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
901 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
902 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
903 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
904
ae80152d 905 I915_WRITE(DSPFW1,
15665979
VS		 906 FW_WM(wm->sr.plane, SR) |
907 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
908 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
909 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 910 I915_WRITE(DSPFW2,
15665979
VS		 911 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
912 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
913 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 914 I915_WRITE(DSPFW3,
15665979 915 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 916
917 if (IS_CHERRYVIEW(dev_priv)) {
918 I915_WRITE(DSPFW7_CHV,
15665979
VS		 919 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
920 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 921 I915_WRITE(DSPFW8_CHV,
15665979
VS		 922 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
923 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 924 I915_WRITE(DSPFW9_CHV,
15665979
VS		 925 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
926 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 927 I915_WRITE(DSPHOWM,
15665979
VS		 928 FW_WM(wm->sr.plane >> 9, SR_HI) |
929 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
930 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
931 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
932 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
933 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
934 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
935 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
936 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
937 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 938 } else {
939 I915_WRITE(DSPFW7,
15665979
VS		 940 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
941 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 942 I915_WRITE(DSPHOWM,
15665979
VS		 943 FW_WM(wm->sr.plane >> 9, SR_HI) |
944 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
945 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
946 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
947 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
948 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
949 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 950 }
951
2cb389b7
VS		 952 /* zero (unused) WM1 watermarks */
953 I915_WRITE(DSPFW4, 0);
954 I915_WRITE(DSPFW5, 0);
955 I915_WRITE(DSPFW6, 0);
956 I915_WRITE(DSPHOWM1, 0);
957
ae80152d 958 POSTING_READ(DSPFW1);
0018fda1
VS		 959}
960
15665979
VS		 961#undef FW_WM_VLV
962
6eb1a681
VS		 963enum vlv_wm_level {
964 VLV_WM_LEVEL_PM2,
965 VLV_WM_LEVEL_PM5,
966 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 967};
968
262cd2e1
VS		 969/* latency must be in 0.1us units. */
970static unsigned int vlv_wm_method2(unsigned int pixel_rate,
971 unsigned int pipe_htotal,
972 unsigned int horiz_pixels,
973 unsigned int bytes_per_pixel,
974 unsigned int latency)
975{
976 unsigned int ret;
977
978 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
979 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
980 ret = DIV_ROUND_UP(ret, 64);
981
982 return ret;
983}
984
985static void vlv_setup_wm_latency(struct drm_device *dev)
986{
987 struct drm_i915_private *dev_priv = dev->dev_private;
988
989 /* all latencies in usec */
990 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
991
58590c14
VS		 992 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
993
262cd2e1
VS		 994 if (IS_CHERRYVIEW(dev_priv)) {
995 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
996 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 997
998 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 999 }
1000}
1001
1002static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
1003 struct intel_crtc *crtc,
1004 const struct intel_plane_state *state,
1005 int level)
1006{
1007 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1008 int clock, htotal, pixel_size, width, wm;
1009
1010 if (dev_priv->wm.pri_latency[level] == 0)
1011 return USHRT_MAX;
1012
1013 if (!state->visible)
1014 return 0;
1015
1016 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1017 clock = crtc->config->base.adjusted_mode.crtc_clock;
1018 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1019 width = crtc->config->pipe_src_w;
1020 if (WARN_ON(htotal == 0))
1021 htotal = 1;
1022
1023 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1024 /*
1025 * FIXME the formula gives values that are
1026 * too big for the cursor FIFO, and hence we
1027 * would never be able to use cursors. For
1028 * now just hardcode the watermark.
1029 */
1030 wm = 63;
1031 } else {
1032 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1033 dev_priv->wm.pri_latency[level] * 10);
1034 }
1035
1036 return min_t(int, wm, USHRT_MAX);
1037}
1038
54f1b6e1
VS		 1039static void vlv_compute_fifo(struct intel_crtc *crtc)
1040{
1041 struct drm_device *dev = crtc->base.dev;
1042 struct vlv_wm_state *wm_state = &crtc->wm_state;
1043 struct intel_plane *plane;
1044 unsigned int total_rate = 0;
1045 const int fifo_size = 512 - 1;
1046 int fifo_extra, fifo_left = fifo_size;
1047
1048 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1049 struct intel_plane_state *state =
1050 to_intel_plane_state(plane->base.state);
1051
1052 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1053 continue;
1054
1055 if (state->visible) {
1056 wm_state->num_active_planes++;
1057 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1058 }
1059 }
1060
1061 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1062 struct intel_plane_state *state =
1063 to_intel_plane_state(plane->base.state);
1064 unsigned int rate;
1065
1066 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1067 plane->wm.fifo_size = 63;
1068 continue;
1069 }
1070
1071 if (!state->visible) {
1072 plane->wm.fifo_size = 0;
1073 continue;
1074 }
1075
1076 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1077 plane->wm.fifo_size = fifo_size * rate / total_rate;
1078 fifo_left -= plane->wm.fifo_size;
1079 }
1080
1081 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1082
1083 /* spread the remainder evenly */
1084 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1085 int plane_extra;
1086
1087 if (fifo_left == 0)
1088 break;
1089
1090 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1091 continue;
1092
1093 /* give it all to the first plane if none are active */
1094 if (plane->wm.fifo_size == 0 &&
1095 wm_state->num_active_planes)
1096 continue;
1097
1098 plane_extra = min(fifo_extra, fifo_left);
1099 plane->wm.fifo_size += plane_extra;
1100 fifo_left -= plane_extra;
1101 }
1102
1103 WARN_ON(fifo_left != 0);
1104}
1105
262cd2e1
VS		 1106static void vlv_invert_wms(struct intel_crtc *crtc)
1107{
1108 struct vlv_wm_state *wm_state = &crtc->wm_state;
1109 int level;
1110
1111 for (level = 0; level < wm_state->num_levels; level++) {
1112 struct drm_device *dev = crtc->base.dev;
1113 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1114 struct intel_plane *plane;
1115
1116 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1117 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1118
1119 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1120 switch (plane->base.type) {
1121 int sprite;
1122 case DRM_PLANE_TYPE_CURSOR:
1123 wm_state->wm[level].cursor = plane->wm.fifo_size -
1124 wm_state->wm[level].cursor;
1125 break;
1126 case DRM_PLANE_TYPE_PRIMARY:
1127 wm_state->wm[level].primary = plane->wm.fifo_size -
1128 wm_state->wm[level].primary;
1129 break;
1130 case DRM_PLANE_TYPE_OVERLAY:
1131 sprite = plane->plane;
1132 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1133 wm_state->wm[level].sprite[sprite];
1134 break;
1135 }
1136 }
1137 }
1138}
1139
26e1fe4f 1140static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1141{
1142 struct drm_device *dev = crtc->base.dev;
1143 struct vlv_wm_state *wm_state = &crtc->wm_state;
1144 struct intel_plane *plane;
1145 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1146 int level;
1147
1148 memset(wm_state, 0, sizeof(*wm_state));
1149
852eb00d 1150 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1151 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1152
1153 wm_state->num_active_planes = 0;
262cd2e1 1154
54f1b6e1 1155 vlv_compute_fifo(crtc);
262cd2e1
VS		 1156
1157 if (wm_state->num_active_planes != 1)
1158 wm_state->cxsr = false;
1159
1160 if (wm_state->cxsr) {
1161 for (level = 0; level < wm_state->num_levels; level++) {
1162 wm_state->sr[level].plane = sr_fifo_size;
1163 wm_state->sr[level].cursor = 63;
1164 }
1165 }
1166
1167 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1168 struct intel_plane_state *state =
1169 to_intel_plane_state(plane->base.state);
1170
1171 if (!state->visible)
1172 continue;
1173
1174 /* normal watermarks */
1175 for (level = 0; level < wm_state->num_levels; level++) {
1176 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1177 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1178
1179 /* hack */
1180 if (WARN_ON(level == 0 && wm > max_wm))
1181 wm = max_wm;
1182
1183 if (wm > plane->wm.fifo_size)
1184 break;
1185
1186 switch (plane->base.type) {
1187 int sprite;
1188 case DRM_PLANE_TYPE_CURSOR:
1189 wm_state->wm[level].cursor = wm;
1190 break;
1191 case DRM_PLANE_TYPE_PRIMARY:
1192 wm_state->wm[level].primary = wm;
1193 break;
1194 case DRM_PLANE_TYPE_OVERLAY:
1195 sprite = plane->plane;
1196 wm_state->wm[level].sprite[sprite] = wm;
1197 break;
1198 }
1199 }
1200
1201 wm_state->num_levels = level;
1202
1203 if (!wm_state->cxsr)
1204 continue;
1205
1206 /* maxfifo watermarks */
1207 switch (plane->base.type) {
1208 int sprite, level;
1209 case DRM_PLANE_TYPE_CURSOR:
1210 for (level = 0; level < wm_state->num_levels; level++)
1211 wm_state->sr[level].cursor =
1212 wm_state->sr[level].cursor;
1213 break;
1214 case DRM_PLANE_TYPE_PRIMARY:
1215 for (level = 0; level < wm_state->num_levels; level++)
1216 wm_state->sr[level].plane =
1217 min(wm_state->sr[level].plane,
1218 wm_state->wm[level].primary);
1219 break;
1220 case DRM_PLANE_TYPE_OVERLAY:
1221 sprite = plane->plane;
1222 for (level = 0; level < wm_state->num_levels; level++)
1223 wm_state->sr[level].plane =
1224 min(wm_state->sr[level].plane,
1225 wm_state->wm[level].sprite[sprite]);
1226 break;
1227 }
1228 }
1229
1230 /* clear any (partially) filled invalid levels */
58590c14 1231 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1232 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1233 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1234 }
1235
1236 vlv_invert_wms(crtc);
1237}
1238
54f1b6e1
VS		 1239#define VLV_FIFO(plane, value) \
1240 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1241
1242static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1243{
1244 struct drm_device *dev = crtc->base.dev;
1245 struct drm_i915_private *dev_priv = to_i915(dev);
1246 struct intel_plane *plane;
1247 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1248
1249 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1250 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1251 WARN_ON(plane->wm.fifo_size != 63);
1252 continue;
1253 }
1254
1255 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1256 sprite0_start = plane->wm.fifo_size;
1257 else if (plane->plane == 0)
1258 sprite1_start = sprite0_start + plane->wm.fifo_size;
1259 else
1260 fifo_size = sprite1_start + plane->wm.fifo_size;
1261 }
1262
1263 WARN_ON(fifo_size != 512 - 1);
1264
1265 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1266 pipe_name(crtc->pipe), sprite0_start,
1267 sprite1_start, fifo_size);
1268
1269 switch (crtc->pipe) {
1270 uint32_t dsparb, dsparb2, dsparb3;
1271 case PIPE_A:
1272 dsparb = I915_READ(DSPARB);
1273 dsparb2 = I915_READ(DSPARB2);
1274
1275 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1276 VLV_FIFO(SPRITEB, 0xff));
1277 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1278 VLV_FIFO(SPRITEB, sprite1_start));
1279
1280 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1281 VLV_FIFO(SPRITEB_HI, 0x1));
1282 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1283 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1284
1285 I915_WRITE(DSPARB, dsparb);
1286 I915_WRITE(DSPARB2, dsparb2);
1287 break;
1288 case PIPE_B:
1289 dsparb = I915_READ(DSPARB);
1290 dsparb2 = I915_READ(DSPARB2);
1291
1292 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1293 VLV_FIFO(SPRITED, 0xff));
1294 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1295 VLV_FIFO(SPRITED, sprite1_start));
1296
1297 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1298 VLV_FIFO(SPRITED_HI, 0xff));
1299 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1300 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1301
1302 I915_WRITE(DSPARB, dsparb);
1303 I915_WRITE(DSPARB2, dsparb2);
1304 break;
1305 case PIPE_C:
1306 dsparb3 = I915_READ(DSPARB3);
1307 dsparb2 = I915_READ(DSPARB2);
1308
1309 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1310 VLV_FIFO(SPRITEF, 0xff));
1311 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1312 VLV_FIFO(SPRITEF, sprite1_start));
1313
1314 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1315 VLV_FIFO(SPRITEF_HI, 0xff));
1316 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1317 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1318
1319 I915_WRITE(DSPARB3, dsparb3);
1320 I915_WRITE(DSPARB2, dsparb2);
1321 break;
1322 default:
1323 break;
1324 }
1325}
1326
1327#undef VLV_FIFO
1328
262cd2e1
VS		 1329static void vlv_merge_wm(struct drm_device *dev,
1330 struct vlv_wm_values *wm)
1331{
1332 struct intel_crtc *crtc;
1333 int num_active_crtcs = 0;
1334
58590c14 1335 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1336 wm->cxsr = true;
1337
1338 for_each_intel_crtc(dev, crtc) {
1339 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1340
1341 if (!crtc->active)
1342 continue;
1343
1344 if (!wm_state->cxsr)
1345 wm->cxsr = false;
1346
1347 num_active_crtcs++;
1348 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1349 }
1350
1351 if (num_active_crtcs != 1)
1352 wm->cxsr = false;
1353
6f9c784b
VS		 1354 if (num_active_crtcs > 1)
1355 wm->level = VLV_WM_LEVEL_PM2;
1356
262cd2e1
VS		 1357 for_each_intel_crtc(dev, crtc) {
1358 struct vlv_wm_state *wm_state = &crtc->wm_state;
1359 enum pipe pipe = crtc->pipe;
1360
1361 if (!crtc->active)
1362 continue;
1363
1364 wm->pipe[pipe] = wm_state->wm[wm->level];
1365 if (wm->cxsr)
1366 wm->sr = wm_state->sr[wm->level];
1367
1368 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1369 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1370 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1371 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1372 }
1373}
1374
1375static void vlv_update_wm(struct drm_crtc *crtc)
1376{
1377 struct drm_device *dev = crtc->dev;
1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1380 enum pipe pipe = intel_crtc->pipe;
1381 struct vlv_wm_values wm = {};
1382
26e1fe4f 1383 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1384 vlv_merge_wm(dev, &wm);
1385
54f1b6e1
VS		 1386 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1387 /* FIXME should be part of crtc atomic commit */
1388 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1389 return;
54f1b6e1 1390 }
262cd2e1
VS		 1391
1392 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1393 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1394 chv_set_memory_dvfs(dev_priv, false);
1395
1396 if (wm.level < VLV_WM_LEVEL_PM5 &&
1397 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1398 chv_set_memory_pm5(dev_priv, false);
1399
852eb00d 1400 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1401 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1402
54f1b6e1
VS		 1403 /* FIXME should be part of crtc atomic commit */
1404 vlv_pipe_set_fifo_size(intel_crtc);
1405
262cd2e1
VS		 1406 vlv_write_wm_values(intel_crtc, &wm);
1407
1408 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1409 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1410 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1411 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1412 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1413
852eb00d 1414 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1415 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1416
1417 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1418 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1419 chv_set_memory_pm5(dev_priv, true);
1420
1421 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1422 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1423 chv_set_memory_dvfs(dev_priv, true);
1424
1425 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1426}
1427
ae80152d
VS		 1428#define single_plane_enabled(mask) is_power_of_2(mask)
1429
46ba614c 1430static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1431{
46ba614c 1432 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1433 static const int sr_latency_ns = 12000;
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1435 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1436 int plane_sr, cursor_sr;
1437 unsigned int enabled = 0;
9858425c 1438 bool cxsr_enabled;
b445e3b0 1439
51cea1f4 1440 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1441 &g4x_wm_info, pessimal_latency_ns,
1442 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1443 &planea_wm, &cursora_wm))
51cea1f4 1444 enabled |= 1 << PIPE_A;
b445e3b0 1445
51cea1f4 1446 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1447 &g4x_wm_info, pessimal_latency_ns,
1448 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1449 &planeb_wm, &cursorb_wm))
51cea1f4 1450 enabled |= 1 << PIPE_B;
b445e3b0 1451
b445e3b0
ED		 1452 if (single_plane_enabled(enabled) &&
1453 g4x_compute_srwm(dev, ffs(enabled) - 1,
1454 sr_latency_ns,
1455 &g4x_wm_info,
1456 &g4x_cursor_wm_info,
52bd02d8 1457 &plane_sr, &cursor_sr)) {
9858425c 1458 cxsr_enabled = true;
52bd02d8 1459 } else {
9858425c 1460 cxsr_enabled = false;
5209b1f4 1461 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1462 plane_sr = cursor_sr = 0;
1463 }
b445e3b0 1464
a5043453
VS		 1465 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1466 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1467 planea_wm, cursora_wm,
1468 planeb_wm, cursorb_wm,
1469 plane_sr, cursor_sr);
1470
1471 I915_WRITE(DSPFW1,
f4998963
VS		 1472 FW_WM(plane_sr, SR) |
1473 FW_WM(cursorb_wm, CURSORB) |
1474 FW_WM(planeb_wm, PLANEB) |
1475 FW_WM(planea_wm, PLANEA));
b445e3b0 1476 I915_WRITE(DSPFW2,
8c919b28 1477 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1478 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1479 /* HPLL off in SR has some issues on G4x... disable it */
1480 I915_WRITE(DSPFW3,
8c919b28 1481 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1482 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1483
1484 if (cxsr_enabled)
1485 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1486}
1487
46ba614c 1488static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1489{
46ba614c 1490 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 struct drm_crtc *crtc;
1493 int srwm = 1;
1494 int cursor_sr = 16;
9858425c 1495 bool cxsr_enabled;
b445e3b0
ED		 1496
1497 /* Calc sr entries for one plane configs */
1498 crtc = single_enabled_crtc(dev);
1499 if (crtc) {
1500 /* self-refresh has much higher latency */
1501 static const int sr_latency_ns = 12000;
124abe07 1502 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1503 int clock = adjusted_mode->crtc_clock;
fec8cba3 1504 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1505 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1506 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1507 unsigned long line_time_us;
1508 int entries;
1509
922044c9 1510 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1511
1512 /* Use ns/us then divide to preserve precision */
1513 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1514 pixel_size * hdisplay;
1515 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1516 srwm = I965_FIFO_SIZE - entries;
1517 if (srwm < 0)
1518 srwm = 1;
1519 srwm &= 0x1ff;
1520 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1521 entries, srwm);
1522
1523 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1524 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1525 entries = DIV_ROUND_UP(entries,
1526 i965_cursor_wm_info.cacheline_size);
1527 cursor_sr = i965_cursor_wm_info.fifo_size -
1528 (entries + i965_cursor_wm_info.guard_size);
1529
1530 if (cursor_sr > i965_cursor_wm_info.max_wm)
1531 cursor_sr = i965_cursor_wm_info.max_wm;
1532
1533 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1534 "cursor %d\n", srwm, cursor_sr);
1535
9858425c 1536 cxsr_enabled = true;
b445e3b0 1537 } else {
9858425c 1538 cxsr_enabled = false;
b445e3b0 1539 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1540 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1541 }
1542
1543 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1544 srwm);
1545
1546 /* 965 has limitations... */
f4998963
VS		 1547 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1548 FW_WM(8, CURSORB) |
1549 FW_WM(8, PLANEB) |
1550 FW_WM(8, PLANEA));
1551 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1552 FW_WM(8, PLANEC_OLD));
b445e3b0 1553 /* update cursor SR watermark */
f4998963 1554 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1555
1556 if (cxsr_enabled)
1557 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1558}
1559
f4998963
VS		 1560#undef FW_WM
1561
46ba614c 1562static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1563{
46ba614c 1564 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566 const struct intel_watermark_params *wm_info;
1567 uint32_t fwater_lo;
1568 uint32_t fwater_hi;
1569 int cwm, srwm = 1;
1570 int fifo_size;
1571 int planea_wm, planeb_wm;
1572 struct drm_crtc *crtc, *enabled = NULL;
1573
1574 if (IS_I945GM(dev))
1575 wm_info = &i945_wm_info;
1576 else if (!IS_GEN2(dev))
1577 wm_info = &i915_wm_info;
1578 else
9d539105 1579 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1580
1581 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1582 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1583 if (intel_crtc_active(crtc)) {
241bfc38 1584 const struct drm_display_mode *adjusted_mode;
59bea882 1585 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1586 if (IS_GEN2(dev))
1587 cpp = 4;
1588
6e3c9717 1589 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1590 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1591 wm_info, fifo_size, cpp,
5aef6003 1592 pessimal_latency_ns);
b445e3b0 1593 enabled = crtc;
9d539105 1594 } else {
b445e3b0 1595 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1596 if (planea_wm > (long)wm_info->max_wm)
1597 planea_wm = wm_info->max_wm;
1598 }
1599
1600 if (IS_GEN2(dev))
1601 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1602
1603 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1604 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1605 if (intel_crtc_active(crtc)) {
241bfc38 1606 const struct drm_display_mode *adjusted_mode;
59bea882 1607 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1608 if (IS_GEN2(dev))
1609 cpp = 4;
1610
6e3c9717 1611 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1612 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1613 wm_info, fifo_size, cpp,
5aef6003 1614 pessimal_latency_ns);
b445e3b0
ED		 1615 if (enabled == NULL)
1616 enabled = crtc;
1617 else
1618 enabled = NULL;
9d539105 1619 } else {
b445e3b0 1620 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1621 if (planeb_wm > (long)wm_info->max_wm)
1622 planeb_wm = wm_info->max_wm;
1623 }
b445e3b0
ED		 1624
1625 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1626
2ab1bc9d 1627 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1628 struct drm_i915_gem_object *obj;
2ab1bc9d 1629
59bea882 1630 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1631
1632 /* self-refresh seems busted with untiled */
2ff8fde1 1633 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1634 enabled = NULL;
1635 }
1636
b445e3b0
ED		 1637 /*
1638 * Overlay gets an aggressive default since video jitter is bad.
1639 */
1640 cwm = 2;
1641
1642 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1643 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1644
1645 /* Calc sr entries for one plane configs */
1646 if (HAS_FW_BLC(dev) && enabled) {
1647 /* self-refresh has much higher latency */
1648 static const int sr_latency_ns = 6000;
124abe07 1649 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1650 int clock = adjusted_mode->crtc_clock;
fec8cba3 1651 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1652 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1653 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1654 unsigned long line_time_us;
1655 int entries;
1656
922044c9 1657 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1658
1659 /* Use ns/us then divide to preserve precision */
1660 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1661 pixel_size * hdisplay;
1662 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1663 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1664 srwm = wm_info->fifo_size - entries;
1665 if (srwm < 0)
1666 srwm = 1;
1667
1668 if (IS_I945G(dev) || IS_I945GM(dev))
1669 I915_WRITE(FW_BLC_SELF,
1670 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1671 else if (IS_I915GM(dev))
1672 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1673 }
1674
1675 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1676 planea_wm, planeb_wm, cwm, srwm);
1677
1678 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1679 fwater_hi = (cwm & 0x1f);
1680
1681 /* Set request length to 8 cachelines per fetch */
1682 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1683 fwater_hi = fwater_hi | (1 << 8);
1684
1685 I915_WRITE(FW_BLC, fwater_lo);
1686 I915_WRITE(FW_BLC2, fwater_hi);
1687
5209b1f4
ID		 1688 if (enabled)
1689 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1690}
1691
feb56b93 1692static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1693{
46ba614c 1694 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 struct drm_crtc *crtc;
241bfc38 1697 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1698 uint32_t fwater_lo;
1699 int planea_wm;
1700
1701 crtc = single_enabled_crtc(dev);
1702 if (crtc == NULL)
1703 return;
1704
6e3c9717 1705 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1706 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1707 &i845_wm_info,
b445e3b0 1708 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1709 4, pessimal_latency_ns);
b445e3b0
ED		 1710 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1711 fwater_lo |= (3<<8) | planea_wm;
1712
1713 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1714
1715 I915_WRITE(FW_BLC, fwater_lo);
1716}
1717
8cfb3407 1718uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1719{
fd4daa9c 1720 uint32_t pixel_rate;
801bcfff 1721
8cfb3407 1722 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1723
1724 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1725 * adjust the pixel_rate here. */
1726
8cfb3407 1727 if (pipe_config->pch_pfit.enabled) {
801bcfff 1728 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1729 uint32_t pfit_size = pipe_config->pch_pfit.size;
1730
1731 pipe_w = pipe_config->pipe_src_w;
1732 pipe_h = pipe_config->pipe_src_h;
801bcfff 1733
801bcfff
PZ		 1734 pfit_w = (pfit_size >> 16) & 0xFFFF;
1735 pfit_h = pfit_size & 0xFFFF;
1736 if (pipe_w < pfit_w)
1737 pipe_w = pfit_w;
1738 if (pipe_h < pfit_h)
1739 pipe_h = pfit_h;
1740
1741 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1742 pfit_w * pfit_h);
1743 }
1744
1745 return pixel_rate;
1746}
1747
37126462 1748/* latency must be in 0.1us units. */
23297044 1749static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1750 uint32_t latency)
1751{
1752 uint64_t ret;
1753
3312ba65
VS		 1754 if (WARN(latency == 0, "Latency value missing\n"))
1755 return UINT_MAX;
1756
801bcfff
PZ		 1757 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1758 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1759
1760 return ret;
1761}
1762
37126462 1763/* latency must be in 0.1us units. */
23297044 1764static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1765 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1766 uint32_t latency)
1767{
1768 uint32_t ret;
1769
3312ba65
VS		 1770 if (WARN(latency == 0, "Latency value missing\n"))
1771 return UINT_MAX;
1772
801bcfff
PZ		 1773 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1774 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1775 ret = DIV_ROUND_UP(ret, 64) + 2;
1776 return ret;
1777}
1778
23297044 1779static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1780 uint8_t bytes_per_pixel)
1781{
1782 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1783}
1784
2ac96d2a
PB		 1785struct skl_pipe_wm_parameters {
1786 bool active;
1787 uint32_t pipe_htotal;
1788 uint32_t pixel_rate; /* in KHz */
1789 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1790 struct intel_plane_wm_parameters cursor;
1791};
1792
820c1980 1793struct ilk_pipe_wm_parameters {
801bcfff 1794 bool active;
801bcfff
PZ		 1795 uint32_t pipe_htotal;
1796 uint32_t pixel_rate;
c35426d2
VS		 1797 struct intel_plane_wm_parameters pri;
1798 struct intel_plane_wm_parameters spr;
1799 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1800};
1801
820c1980 1802struct ilk_wm_maximums {
cca32e9a
PZ		 1803 uint16_t pri;
1804 uint16_t spr;
1805 uint16_t cur;
1806 uint16_t fbc;
1807};
1808
240264f4
VS		 1809/* used in computing the new watermarks state */
1810struct intel_wm_config {
1811 unsigned int num_pipes_active;
1812 bool sprites_enabled;
1813 bool sprites_scaled;
240264f4
VS		 1814};
1815
37126462
VS		 1816/*
1817 * For both WM_PIPE and WM_LP.
1818 * mem_value must be in 0.1us units.
1819 */
820c1980 1820static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1821 uint32_t mem_value,
1822 bool is_lp)
801bcfff 1823{
cca32e9a
PZ		 1824 uint32_t method1, method2;
1825
c35426d2 1826 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1827 return 0;
1828
23297044 1829 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1830 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1831 mem_value);
1832
1833 if (!is_lp)
1834 return method1;
1835
23297044 1836 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1837 params->pipe_htotal,
c35426d2
VS		 1838 params->pri.horiz_pixels,
1839 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1840 mem_value);
1841
1842 return min(method1, method2);
801bcfff
PZ		 1843}
1844
37126462
VS		 1845/*
1846 * For both WM_PIPE and WM_LP.
1847 * mem_value must be in 0.1us units.
1848 */
820c1980 1849static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1850 uint32_t mem_value)
1851{
1852 uint32_t method1, method2;
1853
c35426d2 1854 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1855 return 0;
1856
23297044 1857 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1858 params->spr.bytes_per_pixel,
801bcfff 1859 mem_value);
23297044 1860 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1861 params->pipe_htotal,
c35426d2
VS		 1862 params->spr.horiz_pixels,
1863 params->spr.bytes_per_pixel,
801bcfff
PZ		 1864 mem_value);
1865 return min(method1, method2);
1866}
1867
37126462
VS		 1868/*
1869 * For both WM_PIPE and WM_LP.
1870 * mem_value must be in 0.1us units.
1871 */
820c1980 1872static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1873 uint32_t mem_value)
1874{
c35426d2 1875 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1876 return 0;
1877
23297044 1878 return ilk_wm_method2(params->pixel_rate,
801bcfff 1879 params->pipe_htotal,
c35426d2
VS		 1880 params->cur.horiz_pixels,
1881 params->cur.bytes_per_pixel,
801bcfff
PZ		 1882 mem_value);
1883}
1884
cca32e9a 1885/* Only for WM_LP. */
820c1980 1886static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1887 uint32_t pri_val)
cca32e9a 1888{
c35426d2 1889 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1890 return 0;
1891
23297044 1892 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1893 params->pri.horiz_pixels,
1894 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1895}
1896
158ae64f
VS		 1897static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1898{
416f4727
VS		 1899 if (INTEL_INFO(dev)->gen >= 8)
1900 return 3072;
1901 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1902 return 768;
1903 else
1904 return 512;
1905}
1906
4e975081
VS		 1907static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1908 int level, bool is_sprite)
1909{
1910 if (INTEL_INFO(dev)->gen >= 8)
1911 /* BDW primary/sprite plane watermarks */
1912 return level == 0 ? 255 : 2047;
1913 else if (INTEL_INFO(dev)->gen >= 7)
1914 /* IVB/HSW primary/sprite plane watermarks */
1915 return level == 0 ? 127 : 1023;
1916 else if (!is_sprite)
1917 /* ILK/SNB primary plane watermarks */
1918 return level == 0 ? 127 : 511;
1919 else
1920 /* ILK/SNB sprite plane watermarks */
1921 return level == 0 ? 63 : 255;
1922}
1923
1924static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1925 int level)
1926{
1927 if (INTEL_INFO(dev)->gen >= 7)
1928 return level == 0 ? 63 : 255;
1929 else
1930 return level == 0 ? 31 : 63;
1931}
1932
1933static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1934{
1935 if (INTEL_INFO(dev)->gen >= 8)
1936 return 31;
1937 else
1938 return 15;
1939}
1940
158ae64f
VS		 1941/* Calculate the maximum primary/sprite plane watermark */
1942static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1943 int level,
240264f4 1944 const struct intel_wm_config *config,
158ae64f
VS		 1945 enum intel_ddb_partitioning ddb_partitioning,
1946 bool is_sprite)
1947{
1948 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1949
1950 /* if sprites aren't enabled, sprites get nothing */
240264f4 1951 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1952 return 0;
1953
1954 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1955 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1956 fifo_size /= INTEL_INFO(dev)->num_pipes;
1957
1958 /*
1959 * For some reason the non self refresh
1960 * FIFO size is only half of the self
1961 * refresh FIFO size on ILK/SNB.
1962 */
1963 if (INTEL_INFO(dev)->gen <= 6)
1964 fifo_size /= 2;
1965 }
1966
240264f4 1967 if (config->sprites_enabled) {
158ae64f
VS		 1968 /* level 0 is always calculated with 1:1 split */
1969 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1970 if (is_sprite)
1971 fifo_size *= 5;
1972 fifo_size /= 6;
1973 } else {
1974 fifo_size /= 2;
1975 }
1976 }
1977
1978 /* clamp to max that the registers can hold */
4e975081 1979 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1980}
1981
1982/* Calculate the maximum cursor plane watermark */
1983static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1984 int level,
1985 const struct intel_wm_config *config)
158ae64f
VS		 1986{
1987 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1988 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1989 return 64;
1990
1991 /* otherwise just report max that registers can hold */
4e975081 1992 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1993}
1994
d34ff9c6 1995static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1996 int level,
1997 const struct intel_wm_config *config,
1998 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1999 struct ilk_wm_maximums *max)
158ae64f 2000{
240264f4
VS		 2001 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2002 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2003 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 2004 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 2005}
2006
a3cb4048
VS		 2007static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2008 int level,
2009 struct ilk_wm_maximums *max)
2010{
2011 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2012 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2013 max->cur = ilk_cursor_wm_reg_max(dev, level);
2014 max->fbc = ilk_fbc_wm_reg_max(dev);
2015}
2016
d9395655 2017static bool ilk_validate_wm_level(int level,
820c1980 2018 const struct ilk_wm_maximums *max,
d9395655 2019 struct intel_wm_level *result)
a9786a11
VS		 2020{
2021 bool ret;
2022
2023 /* already determined to be invalid? */
2024 if (!result->enable)
2025 return false;
2026
2027 result->enable = result->pri_val <= max->pri &&
2028 result->spr_val <= max->spr &&
2029 result->cur_val <= max->cur;
2030
2031 ret = result->enable;
2032
2033 /*
2034 * HACK until we can pre-compute everything,
2035 * and thus fail gracefully if LP0 watermarks
2036 * are exceeded...
2037 */
2038 if (level == 0 && !result->enable) {
2039 if (result->pri_val > max->pri)
2040 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2041 level, result->pri_val, max->pri);
2042 if (result->spr_val > max->spr)
2043 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2044 level, result->spr_val, max->spr);
2045 if (result->cur_val > max->cur)
2046 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2047 level, result->cur_val, max->cur);
2048
2049 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2050 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2051 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2052 result->enable = true;
2053 }
2054
a9786a11
VS		 2055 return ret;
2056}
2057
d34ff9c6 2058static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2059 int level,
820c1980 2060 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2061 struct intel_wm_level *result)
6f5ddd17
VS		 2062{
2063 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2064 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2065 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2066
2067 /* WM1+ latency values stored in 0.5us units */
2068 if (level > 0) {
2069 pri_latency *= 5;
2070 spr_latency *= 5;
2071 cur_latency *= 5;
2072 }
2073
2074 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2075 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2076 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2077 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2078 result->enable = true;
2079}
2080
801bcfff
PZ		 2081static uint32_t
2082hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2083{
2084 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7c5f93b0 2086 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2087 u32 linetime, ips_linetime;
1f8eeabf 2088
3ef00284 2089 if (!intel_crtc->active)
801bcfff 2090 return 0;
1011d8c4 2091
1f8eeabf
ED		 2092 /* The WM are computed with base on how long it takes to fill a single
2093 * row at the given clock rate, multiplied by 8.
2094 * */
124abe07
VS		 2095 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2096 adjusted_mode->crtc_clock);
2097 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2098 dev_priv->cdclk_freq);
1f8eeabf 2099
801bcfff
PZ		 2100 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2101 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2102}
2103
2af30a5c 2104static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2105{
2106 struct drm_i915_private *dev_priv = dev->dev_private;
2107
2af30a5c
PB		 2108 if (IS_GEN9(dev)) {
2109 uint32_t val;
4f947386 2110 int ret, i;
367294be 2111 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2112
2113 /* read the first set of memory latencies[0:3] */
2114 val = 0; /* data0 to be programmed to 0 for first set */
2115 mutex_lock(&dev_priv->rps.hw_lock);
2116 ret = sandybridge_pcode_read(dev_priv,
2117 GEN9_PCODE_READ_MEM_LATENCY,
2118 &val);
2119 mutex_unlock(&dev_priv->rps.hw_lock);
2120
2121 if (ret) {
2122 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2123 return;
2124 }
2125
2126 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2127 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2128 GEN9_MEM_LATENCY_LEVEL_MASK;
2129 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2130 GEN9_MEM_LATENCY_LEVEL_MASK;
2131 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2132 GEN9_MEM_LATENCY_LEVEL_MASK;
2133
2134 /* read the second set of memory latencies[4:7] */
2135 val = 1; /* data0 to be programmed to 1 for second set */
2136 mutex_lock(&dev_priv->rps.hw_lock);
2137 ret = sandybridge_pcode_read(dev_priv,
2138 GEN9_PCODE_READ_MEM_LATENCY,
2139 &val);
2140 mutex_unlock(&dev_priv->rps.hw_lock);
2141 if (ret) {
2142 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2143 return;
2144 }
2145
2146 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2147 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2148 GEN9_MEM_LATENCY_LEVEL_MASK;
2149 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2150 GEN9_MEM_LATENCY_LEVEL_MASK;
2151 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2152 GEN9_MEM_LATENCY_LEVEL_MASK;
2153
367294be 2154 /*
6f97235b
DL		 2155 * WaWmMemoryReadLatency:skl
2156 *
367294be
VK		 2157 * punit doesn't take into account the read latency so we need
2158 * to add 2us to the various latency levels we retrieve from
2159 * the punit.
2160 * - W0 is a bit special in that it's the only level that
2161 * can't be disabled if we want to have display working, so
2162 * we always add 2us there.
2163 * - For levels >=1, punit returns 0us latency when they are
2164 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2165 *
2166 * Additionally, if a level n (n > 1) has a 0us latency, all
2167 * levels m (m >= n) need to be disabled. We make sure to
2168 * sanitize the values out of the punit to satisfy this
2169 * requirement.
367294be
VK		 2170 */
2171 wm[0] += 2;
2172 for (level = 1; level <= max_level; level++)
2173 if (wm[level] != 0)
2174 wm[level] += 2;
4f947386
VK		 2175 else {
2176 for (i = level + 1; i <= max_level; i++)
2177 wm[i] = 0;
367294be 2178
4f947386
VK		 2179 break;
2180 }
2af30a5c 2181 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2182 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2183
2184 wm[0] = (sskpd >> 56) & 0xFF;
2185 if (wm[0] == 0)
2186 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2187 wm[1] = (sskpd >> 4) & 0xFF;
2188 wm[2] = (sskpd >> 12) & 0xFF;
2189 wm[3] = (sskpd >> 20) & 0x1FF;
2190 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2191 } else if (INTEL_INFO(dev)->gen >= 6) {
2192 uint32_t sskpd = I915_READ(MCH_SSKPD);
2193
2194 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2195 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2196 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2197 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2198 } else if (INTEL_INFO(dev)->gen >= 5) {
2199 uint32_t mltr = I915_READ(MLTR_ILK);
2200
2201 /* ILK primary LP0 latency is 700 ns */
2202 wm[0] = 7;
2203 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2204 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2205 }
2206}
2207
53615a5e
VS		 2208static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2209{
2210 /* ILK sprite LP0 latency is 1300 ns */
2211 if (INTEL_INFO(dev)->gen == 5)
2212 wm[0] = 13;
2213}
2214
2215static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2216{
2217 /* ILK cursor LP0 latency is 1300 ns */
2218 if (INTEL_INFO(dev)->gen == 5)
2219 wm[0] = 13;
2220
2221 /* WaDoubleCursorLP3Latency:ivb */
2222 if (IS_IVYBRIDGE(dev))
2223 wm[3] *= 2;
2224}
2225
546c81fd 2226int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2227{
26ec971e 2228 /* how many WM levels are we expecting */
b6e742f6 2229 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2230 return 7;
2231 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2232 return 4;
26ec971e 2233 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2234 return 3;
26ec971e 2235 else
ad0d6dc4
VS		 2236 return 2;
2237}
7526ed79 2238
ad0d6dc4
VS		 2239static void intel_print_wm_latency(struct drm_device *dev,
2240 const char *name,
2af30a5c 2241 const uint16_t wm[8])
ad0d6dc4
VS		 2242{
2243 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2244
2245 for (level = 0; level <= max_level; level++) {
2246 unsigned int latency = wm[level];
2247
2248 if (latency == 0) {
2249 DRM_ERROR("%s WM%d latency not provided\n",
2250 name, level);
2251 continue;
2252 }
2253
2af30a5c
PB		 2254 /*
2255 * - latencies are in us on gen9.
2256 * - before then, WM1+ latency values are in 0.5us units
2257 */
2258 if (IS_GEN9(dev))
2259 latency *= 10;
2260 else if (level > 0)
26ec971e
VS		 2261 latency *= 5;
2262
2263 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2264 name, level, wm[level],
2265 latency / 10, latency % 10);
2266 }
2267}
2268
e95a2f75
VS		 2269static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2270 uint16_t wm[5], uint16_t min)
2271{
2272 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2273
2274 if (wm[0] >= min)
2275 return false;
2276
2277 wm[0] = max(wm[0], min);
2278 for (level = 1; level <= max_level; level++)
2279 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2280
2281 return true;
2282}
2283
2284static void snb_wm_latency_quirk(struct drm_device *dev)
2285{
2286 struct drm_i915_private *dev_priv = dev->dev_private;
2287 bool changed;
2288
2289 /*
2290 * The BIOS provided WM memory latency values are often
2291 * inadequate for high resolution displays. Adjust them.
2292 */
2293 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2294 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2295 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2296
2297 if (!changed)
2298 return;
2299
2300 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2301 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2302 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2303 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2304}
2305
fa50ad61 2306static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2307{
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309
2310 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2311
2312 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2313 sizeof(dev_priv->wm.pri_latency));
2314 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2315 sizeof(dev_priv->wm.pri_latency));
2316
2317 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2318 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2319
2320 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2321 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2322 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2323
2324 if (IS_GEN6(dev))
2325 snb_wm_latency_quirk(dev);
53615a5e
VS		 2326}
2327
2af30a5c
PB		 2328static void skl_setup_wm_latency(struct drm_device *dev)
2329{
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331
2332 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2333 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2334}
2335
820c1980 2336static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2337 struct ilk_pipe_wm_parameters *p)
1011d8c4 2338{
7c4a395f
VS		 2339 struct drm_device *dev = crtc->dev;
2340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2341 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2342 struct drm_plane *plane;
1011d8c4 2343
3ef00284 2344 if (!intel_crtc->active)
2a44b76b 2345 return;
801bcfff 2346
2a44b76b 2347 p->active = true;
6e3c9717 2348 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2349 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2350
54da691d 2351 if (crtc->primary->state->fb)
c9f038a1
MR		 2352 p->pri.bytes_per_pixel =
2353 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG		 2354 else
2355 p->pri.bytes_per_pixel = 4;
2356
2357 p->cur.bytes_per_pixel = 4;
2358 /*
2359 * TODO: for now, assume primary and cursor planes are always enabled.
2360 * Setting them to false makes the screen flicker.
2361 */
2362 p->pri.enabled = true;
2363 p->cur.enabled = true;
c9f038a1 2364
6e3c9717 2365 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2366 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2367
4ea50e99 2368 drm_for_each_legacy_plane(plane, dev) {
801bcfff 2369 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2370
2a44b76b 2371 if (intel_plane->pipe == pipe) {
7c4a395f 2372 p->spr = intel_plane->wm;
2a44b76b
VS		 2373 break;
2374 }
2375 }
2376}
2377
2378static void ilk_compute_wm_config(struct drm_device *dev,
2379 struct intel_wm_config *config)
2380{
2381 struct intel_crtc *intel_crtc;
2382
2383 /* Compute the currently _active_ config */
d3fcc808 2384 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2385 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2386
2a44b76b
VS		 2387 if (!wm->pipe_enabled)
2388 continue;
cca32e9a 2389
2a44b76b
VS		 2390 config->sprites_enabled |= wm->sprites_enabled;
2391 config->sprites_scaled |= wm->sprites_scaled;
2392 config->num_pipes_active++;
cca32e9a 2393 }
801bcfff
PZ		 2394}
2395
0b2ae6d7
VS		 2396/* Compute new watermarks for the pipe */
2397static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2398 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2399 struct intel_pipe_wm *pipe_wm)
2400{
2401 struct drm_device *dev = crtc->dev;
d34ff9c6 2402 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2403 int level, max_level = ilk_wm_max_level(dev);
2404 /* LP0 watermark maximums depend on this pipe alone */
2405 struct intel_wm_config config = {
2406 .num_pipes_active = 1,
2407 .sprites_enabled = params->spr.enabled,
2408 .sprites_scaled = params->spr.scaled,
2409 };
820c1980 2410 struct ilk_wm_maximums max;
0b2ae6d7 2411
2a44b76b
VS		 2412 pipe_wm->pipe_enabled = params->active;
2413 pipe_wm->sprites_enabled = params->spr.enabled;
2414 pipe_wm->sprites_scaled = params->spr.scaled;
2415
7b39a0b7
VS		 2416 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2417 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2418 max_level = 1;
2419
2420 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2421 if (params->spr.scaled)
2422 max_level = 0;
2423
a3cb4048 2424 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2425
a42a5719 2426 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2427 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2428
a3cb4048
VS		 2429 /* LP0 watermarks always use 1/2 DDB partitioning */
2430 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2431
0b2ae6d7 2432 /* At least LP0 must be valid */
a3cb4048
VS		 2433 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2434 return false;
2435
2436 ilk_compute_wm_reg_maximums(dev, 1, &max);
2437
2438 for (level = 1; level <= max_level; level++) {
2439 struct intel_wm_level wm = {};
2440
2441 ilk_compute_wm_level(dev_priv, level, params, &wm);
2442
2443 /*
2444 * Disable any watermark level that exceeds the
2445 * register maximums since such watermarks are
2446 * always invalid.
2447 */
2448 if (!ilk_validate_wm_level(level, &max, &wm))
2449 break;
2450
2451 pipe_wm->wm[level] = wm;
2452 }
2453
2454 return true;
0b2ae6d7
VS		 2455}
2456
2457/*
2458 * Merge the watermarks from all active pipes for a specific level.
2459 */
2460static void ilk_merge_wm_level(struct drm_device *dev,
2461 int level,
2462 struct intel_wm_level *ret_wm)
2463{
2464 const struct intel_crtc *intel_crtc;
2465
d52fea5b
VS		 2466 ret_wm->enable = true;
2467
d3fcc808 2468 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2469 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2470 const struct intel_wm_level *wm = &active->wm[level];
2471
2472 if (!active->pipe_enabled)
2473 continue;
0b2ae6d7 2474
d52fea5b
VS		 2475 /*
2476 * The watermark values may have been used in the past,
2477 * so we must maintain them in the registers for some
2478 * time even if the level is now disabled.
2479 */
0b2ae6d7 2480 if (!wm->enable)
d52fea5b 2481 ret_wm->enable = false;
0b2ae6d7
VS		 2482
2483 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2484 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2485 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2486 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2487 }
0b2ae6d7
VS		 2488}
2489
2490/*
2491 * Merge all low power watermarks for all active pipes.
2492 */
2493static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2494 const struct intel_wm_config *config,
820c1980 2495 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2496 struct intel_pipe_wm *merged)
2497{
7733b49b 2498 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2499 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2500 int last_enabled_level = max_level;
0b2ae6d7 2501
0ba22e26
VS		 2502 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2503 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2504 config->num_pipes_active > 1)
2505 return;
2506
6c8b6c28
VS		 2507 /* ILK: FBC WM must be disabled always */
2508 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2509
2510 /* merge each WM1+ level */
2511 for (level = 1; level <= max_level; level++) {
2512 struct intel_wm_level *wm = &merged->wm[level];
2513
2514 ilk_merge_wm_level(dev, level, wm);
2515
d52fea5b
VS		 2516 if (level > last_enabled_level)
2517 wm->enable = false;
2518 else if (!ilk_validate_wm_level(level, max, wm))
2519 /* make sure all following levels get disabled */
2520 last_enabled_level = level - 1;
0b2ae6d7
VS		 2521
2522 /*
2523 * The spec says it is preferred to disable
2524 * FBC WMs instead of disabling a WM level.
2525 */
2526 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2527 if (wm->enable)
2528 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2529 wm->fbc_val = 0;
2530 }
2531 }
6c8b6c28
VS		 2532
2533 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2534 /*
2535 * FIXME this is racy. FBC might get enabled later.
2536 * What we should check here is whether FBC can be
2537 * enabled sometime later.
2538 */
7733b49b
PZ		 2539 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2540 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2541 for (level = 2; level <= max_level; level++) {
2542 struct intel_wm_level *wm = &merged->wm[level];
2543
2544 wm->enable = false;
2545 }
2546 }
0b2ae6d7
VS		 2547}
2548
b380ca3c
VS		 2549static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2550{
2551 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2552 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2553}
2554
a68d68ee
VS		 2555/* The value we need to program into the WM_LPx latency field */
2556static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2557{
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559
a42a5719 2560 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2561 return 2 * level;
2562 else
2563 return dev_priv->wm.pri_latency[level];
2564}
2565
820c1980 2566static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2567 const struct intel_pipe_wm *merged,
609cedef 2568 enum intel_ddb_partitioning partitioning,
820c1980 2569 struct ilk_wm_values *results)
801bcfff 2570{
0b2ae6d7
VS		 2571 struct intel_crtc *intel_crtc;
2572 int level, wm_lp;
cca32e9a 2573
0362c781 2574 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2575 results->partitioning = partitioning;
cca32e9a 2576
0b2ae6d7 2577 /* LP1+ register values */
cca32e9a 2578 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2579 const struct intel_wm_level *r;
801bcfff 2580
b380ca3c 2581 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2582
0362c781 2583 r = &merged->wm[level];
cca32e9a 2584
d52fea5b
VS		 2585 /*
2586 * Maintain the watermark values even if the level is
2587 * disabled. Doing otherwise could cause underruns.
2588 */
2589 results->wm_lp[wm_lp - 1] =
a68d68ee 2590 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2591 (r->pri_val << WM1_LP_SR_SHIFT) |
2592 r->cur_val;
2593
d52fea5b
VS		 2594 if (r->enable)
2595 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2596
416f4727
VS		 2597 if (INTEL_INFO(dev)->gen >= 8)
2598 results->wm_lp[wm_lp - 1] |=
2599 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2600 else
2601 results->wm_lp[wm_lp - 1] |=
2602 r->fbc_val << WM1_LP_FBC_SHIFT;
2603
d52fea5b
VS		 2604 /*
2605 * Always set WM1S_LP_EN when spr_val != 0, even if the
2606 * level is disabled. Doing otherwise could cause underruns.
2607 */
6cef2b8a
VS		 2608 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2609 WARN_ON(wm_lp != 1);
2610 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2611 } else
2612 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2613 }
801bcfff 2614
0b2ae6d7 2615 /* LP0 register values */
d3fcc808 2616 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2617 enum pipe pipe = intel_crtc->pipe;
2618 const struct intel_wm_level *r =
2619 &intel_crtc->wm.active.wm[0];
2620
2621 if (WARN_ON(!r->enable))
2622 continue;
2623
2624 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2625
0b2ae6d7
VS		 2626 results->wm_pipe[pipe] =
2627 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2628 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2629 r->cur_val;
801bcfff
PZ		 2630 }
2631}
2632
861f3389
PZ		 2633/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2634 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2635static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2636 struct intel_pipe_wm *r1,
2637 struct intel_pipe_wm *r2)
861f3389 2638{
198a1e9b
VS		 2639 int level, max_level = ilk_wm_max_level(dev);
2640 int level1 = 0, level2 = 0;
861f3389 2641
198a1e9b
VS		 2642 for (level = 1; level <= max_level; level++) {
2643 if (r1->wm[level].enable)
2644 level1 = level;
2645 if (r2->wm[level].enable)
2646 level2 = level;
861f3389
PZ		 2647 }
2648
198a1e9b
VS		 2649 if (level1 == level2) {
2650 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2651 return r2;
2652 else
2653 return r1;
198a1e9b 2654 } else if (level1 > level2) {
861f3389
PZ		 2655 return r1;
2656 } else {
2657 return r2;
2658 }
2659}
2660
49a687c4
VS		 2661/* dirty bits used to track which watermarks need changes */
2662#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2663#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2664#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2665#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2666#define WM_DIRTY_FBC (1 << 24)
2667#define WM_DIRTY_DDB (1 << 25)
2668
055e393f 2669static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2670 const struct ilk_wm_values *old,
2671 const struct ilk_wm_values *new)
49a687c4
VS		 2672{
2673 unsigned int dirty = 0;
2674 enum pipe pipe;
2675 int wm_lp;
2676
055e393f 2677 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2678 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2679 dirty |= WM_DIRTY_LINETIME(pipe);
2680 /* Must disable LP1+ watermarks too */
2681 dirty |= WM_DIRTY_LP_ALL;
2682 }
2683
2684 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2685 dirty |= WM_DIRTY_PIPE(pipe);
2686 /* Must disable LP1+ watermarks too */
2687 dirty |= WM_DIRTY_LP_ALL;
2688 }
2689 }
2690
2691 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2692 dirty |= WM_DIRTY_FBC;
2693 /* Must disable LP1+ watermarks too */
2694 dirty |= WM_DIRTY_LP_ALL;
2695 }
2696
2697 if (old->partitioning != new->partitioning) {
2698 dirty |= WM_DIRTY_DDB;
2699 /* Must disable LP1+ watermarks too */
2700 dirty |= WM_DIRTY_LP_ALL;
2701 }
2702
2703 /* LP1+ watermarks already deemed dirty, no need to continue */
2704 if (dirty & WM_DIRTY_LP_ALL)
2705 return dirty;
2706
2707 /* Find the lowest numbered LP1+ watermark in need of an update... */
2708 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2709 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2710 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2711 break;
2712 }
2713
2714 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2715 for (; wm_lp <= 3; wm_lp++)
2716 dirty |= WM_DIRTY_LP(wm_lp);
2717
2718 return dirty;
2719}
2720
8553c18e
VS		 2721static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2722 unsigned int dirty)
801bcfff 2723{
820c1980 2724 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2725 bool changed = false;
801bcfff 2726
facd619b
VS		 2727 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2728 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2729 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2730 changed = true;
facd619b
VS		 2731 }
2732 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2733 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2734 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2735 changed = true;
facd619b
VS		 2736 }
2737 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2738 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2739 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2740 changed = true;
facd619b 2741 }
801bcfff 2742
facd619b
VS		 2743 /*
2744 * Don't touch WM1S_LP_EN here.
2745 * Doing so could cause underruns.
2746 */
6cef2b8a 2747
8553c18e
VS		 2748 return changed;
2749}
2750
2751/*
2752 * The spec says we shouldn't write when we don't need, because every write
2753 * causes WMs to be re-evaluated, expending some power.
2754 */
820c1980
ID		 2755static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2756 struct ilk_wm_values *results)
8553c18e
VS		 2757{
2758 struct drm_device *dev = dev_priv->dev;
820c1980 2759 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2760 unsigned int dirty;
2761 uint32_t val;
2762
055e393f 2763 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2764 if (!dirty)
2765 return;
2766
2767 _ilk_disable_lp_wm(dev_priv, dirty);
2768
49a687c4 2769 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2770 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2771 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2772 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2773 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2774 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2775
49a687c4 2776 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2777 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2778 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2779 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2780 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2781 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2782
49a687c4 2783 if (dirty & WM_DIRTY_DDB) {
a42a5719 2784 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2785 val = I915_READ(WM_MISC);
2786 if (results->partitioning == INTEL_DDB_PART_1_2)
2787 val &= ~WM_MISC_DATA_PARTITION_5_6;
2788 else
2789 val |= WM_MISC_DATA_PARTITION_5_6;
2790 I915_WRITE(WM_MISC, val);
2791 } else {
2792 val = I915_READ(DISP_ARB_CTL2);
2793 if (results->partitioning == INTEL_DDB_PART_1_2)
2794 val &= ~DISP_DATA_PARTITION_5_6;
2795 else
2796 val |= DISP_DATA_PARTITION_5_6;
2797 I915_WRITE(DISP_ARB_CTL2, val);
2798 }
1011d8c4
PZ		 2799 }
2800
49a687c4 2801 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2802 val = I915_READ(DISP_ARB_CTL);
2803 if (results->enable_fbc_wm)
2804 val &= ~DISP_FBC_WM_DIS;
2805 else
2806 val |= DISP_FBC_WM_DIS;
2807 I915_WRITE(DISP_ARB_CTL, val);
2808 }
2809
954911eb
ID		 2810 if (dirty & WM_DIRTY_LP(1) &&
2811 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2812 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2813
2814 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2815 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2816 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2817 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2818 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2819 }
801bcfff 2820
facd619b 2821 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2822 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2823 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2824 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2825 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2826 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2827
2828 dev_priv->wm.hw = *results;
801bcfff
PZ		 2829}
2830
8553c18e
VS		 2831static bool ilk_disable_lp_wm(struct drm_device *dev)
2832{
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834
2835 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2836}
2837
b9cec075
DL		 2838/*
2839 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2840 * different active planes.
2841 */
2842
2843#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2844#define BXT_DDB_SIZE 512
b9cec075
DL		 2845
2846static void
2847skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2848 struct drm_crtc *for_crtc,
2849 const struct intel_wm_config *config,
2850 const struct skl_pipe_wm_parameters *params,
2851 struct skl_ddb_entry *alloc /* out */)
2852{
2853 struct drm_crtc *crtc;
2854 unsigned int pipe_size, ddb_size;
2855 int nth_active_pipe;
2856
2857 if (!params->active) {
2858 alloc->start = 0;
2859 alloc->end = 0;
2860 return;
2861 }
2862
43d735a6
DL		 2863 if (IS_BROXTON(dev))
2864 ddb_size = BXT_DDB_SIZE;
2865 else
2866 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2867
2868 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2869
2870 nth_active_pipe = 0;
2871 for_each_crtc(dev, crtc) {
3ef00284 2872 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2873 continue;
2874
2875 if (crtc == for_crtc)
2876 break;
2877
2878 nth_active_pipe++;
2879 }
2880
2881 pipe_size = ddb_size / config->num_pipes_active;
2882 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2883 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2884}
2885
2886static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2887{
2888 if (config->num_pipes_active == 1)
2889 return 32;
2890
2891 return 8;
2892}
2893
a269c583
DL		 2894static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2895{
2896 entry->start = reg & 0x3ff;
2897 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2898 if (entry->end)
2899 entry->end += 1;
a269c583
DL		 2900}
2901
08db6652
DL		 2902void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2903 struct skl_ddb_allocation *ddb /* out */)
a269c583 2904{
a269c583
DL		 2905 enum pipe pipe;
2906 int plane;
2907 u32 val;
2908
2909 for_each_pipe(dev_priv, pipe) {
dd740780 2910 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2911 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2912 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2913 val);
2914 }
2915
2916 val = I915_READ(CUR_BUF_CFG(pipe));
2917 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2918 }
2919}
2920
b9cec075 2921static unsigned int
2cd601c6 2922skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2923{
2cd601c6
CK		 2924
2925 /* for planar format */
2926 if (p->y_bytes_per_pixel) {
2927 if (y) /* y-plane data rate */
2928 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2929 else /* uv-plane data rate */
2930 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2931 }
2932
2933 /* for packed formats */
b9cec075
DL		 2934 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2935}
2936
2937/*
2938 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2939 * a 8192x4096@32bpp framebuffer:
2940 * 3 * 4096 * 8192 * 4 < 2^32
2941 */
2942static unsigned int
2943skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2944 const struct skl_pipe_wm_parameters *params)
2945{
2946 unsigned int total_data_rate = 0;
2947 int plane;
2948
2949 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2950 const struct intel_plane_wm_parameters *p;
2951
2952 p = &params->plane[plane];
2953 if (!p->enabled)
2954 continue;
2955
2cd601c6
CK		 2956 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2957 if (p->y_bytes_per_pixel) {
2958 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2959 }
b9cec075
DL		 2960 }
2961
2962 return total_data_rate;
2963}
2964
2965static void
2966skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2967 const struct intel_wm_config *config,
2968 const struct skl_pipe_wm_parameters *params,
2969 struct skl_ddb_allocation *ddb /* out */)
2970{
2971 struct drm_device *dev = crtc->dev;
dd740780 2972 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2974 enum pipe pipe = intel_crtc->pipe;
34bb56af 2975 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2976 uint16_t alloc_size, start, cursor_blocks;
80958155 2977 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2978 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2979 unsigned int total_data_rate;
2980 int plane;
2981
34bb56af
DL		 2982 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2983 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2984 if (alloc_size == 0) {
2985 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2986 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2987 return;
2988 }
2989
2990 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2991 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2992 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2993
2994 alloc_size -= cursor_blocks;
34bb56af 2995 alloc->end -= cursor_blocks;
b9cec075 2996
80958155 2997 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2998 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2999 const struct intel_plane_wm_parameters *p;
3000
3001 p = &params->plane[plane];
3002 if (!p->enabled)
3003 continue;
3004
3005 minimum[plane] = 8;
3006 alloc_size -= minimum[plane];
2cd601c6
CK		 3007 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
3008 alloc_size -= y_minimum[plane];
80958155
DL		 3009 }
3010
b9cec075 3011 /*
80958155
DL		 3012 * 2. Distribute the remaining space in proportion to the amount of
3013 * data each plane needs to fetch from memory.
b9cec075
DL		 3014 *
3015 * FIXME: we may not allocate every single block here.
3016 */
3017 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3018
34bb56af 3019 start = alloc->start;
b9cec075
DL		 3020 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3021 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 3022 unsigned int data_rate, y_data_rate;
3023 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 3024
3025 p = &params->plane[plane];
3026 if (!p->enabled)
3027 continue;
3028
2cd601c6 3029 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 3030
3031 /*
2cd601c6 3032 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3033 * promote the expression to 64 bits to avoid overflowing, the
3034 * result is < available as data_rate / total_data_rate < 1
3035 */
80958155
DL		 3036 plane_blocks = minimum[plane];
3037 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3038 total_data_rate);
b9cec075
DL		 3039
3040 ddb->plane[pipe][plane].start = start;
16160e3d 3041 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3042
3043 start += plane_blocks;
2cd601c6
CK		 3044
3045 /*
3046 * allocation for y_plane part of planar format:
3047 */
3048 if (p->y_bytes_per_pixel) {
3049 y_data_rate = skl_plane_relative_data_rate(p, 1);
3050 y_plane_blocks = y_minimum[plane];
3051 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3052 total_data_rate);
3053
3054 ddb->y_plane[pipe][plane].start = start;
3055 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3056
3057 start += y_plane_blocks;
3058 }
3059
b9cec075
DL		 3060 }
3061
3062}
3063
5cec258b 3064static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3065{
3066 /* TODO: Take into account the scalers once we support them */
2d112de7 3067 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3068}
3069
3070/*
3071 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3072 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3073 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3074 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3075*/
3076static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3077 uint32_t latency)
3078{
3079 uint32_t wm_intermediate_val, ret;
3080
3081 if (latency == 0)
3082 return UINT_MAX;
3083
d4c2aa60 3084 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3085 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3086
3087 return ret;
3088}
3089
3090static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3091 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3092 uint64_t tiling, uint32_t latency)
2d41c0b5 3093{
d4c2aa60
TU		 3094 uint32_t ret;
3095 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3096 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3097
3098 if (latency == 0)
3099 return UINT_MAX;
3100
3101 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3102
3103 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3104 tiling == I915_FORMAT_MOD_Yf_TILED) {
3105 plane_bytes_per_line *= 4;
3106 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3107 plane_blocks_per_line /= 4;
3108 } else {
3109 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3110 }
3111
2d41c0b5
PB		 3112 wm_intermediate_val = latency * pixel_rate;
3113 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3114 plane_blocks_per_line;
2d41c0b5
PB		 3115
3116 return ret;
3117}
3118
2d41c0b5
PB		 3119static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3120 const struct intel_crtc *intel_crtc)
3121{
3122 struct drm_device *dev = intel_crtc->base.dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3125 enum pipe pipe = intel_crtc->pipe;
3126
3127 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3128 sizeof(new_ddb->plane[pipe])))
3129 return true;
3130
3131 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3132 sizeof(new_ddb->cursor[pipe])))
3133 return true;
3134
3135 return false;
3136}
3137
3138static void skl_compute_wm_global_parameters(struct drm_device *dev,
3139 struct intel_wm_config *config)
3140{
3141 struct drm_crtc *crtc;
3142 struct drm_plane *plane;
3143
3144 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 3145 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 3146
3147 /* FIXME: I don't think we need those two global parameters on SKL */
3148 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3149 struct intel_plane *intel_plane = to_intel_plane(plane);
3150
3151 config->sprites_enabled |= intel_plane->wm.enabled;
3152 config->sprites_scaled |= intel_plane->wm.scaled;
3153 }
3154}
3155
3156static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3157 struct skl_pipe_wm_parameters *p)
3158{
3159 struct drm_device *dev = crtc->dev;
3160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3161 enum pipe pipe = intel_crtc->pipe;
3162 struct drm_plane *plane;
0fda6568 3163 struct drm_framebuffer *fb;
2d41c0b5
PB		 3164 int i = 1; /* Index for sprite planes start */
3165
3ef00284 3166 p->active = intel_crtc->active;
2d41c0b5 3167 if (p->active) {
6e3c9717
ACO		 3168 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3169 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 3170
0fda6568 3171 fb = crtc->primary->state->fb;
2cd601c6 3172 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 3173 if (fb) {
3174 p->plane[0].enabled = true;
2cd601c6 3175 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
395ab754
KM		 3176 drm_format_plane_cpp(fb->pixel_format, 1) :
3177 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6
CK		 3178 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3179 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 3180 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 3181 } else {
3182 p->plane[0].enabled = false;
3183 p->plane[0].bytes_per_pixel = 0;
2cd601c6 3184 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 3185 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3186 }
3187 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3188 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 3189 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 3190
c9f038a1 3191 fb = crtc->cursor->state->fb;
2cd601c6 3192 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 3193 if (fb) {
3194 p->cursor.enabled = true;
3195 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3196 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3197 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3198 } else {
3199 p->cursor.enabled = false;
3200 p->cursor.bytes_per_pixel = 0;
3201 p->cursor.horiz_pixels = 64;
3202 p->cursor.vert_pixels = 64;
3203 }
2d41c0b5
PB		 3204 }
3205
3206 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3207 struct intel_plane *intel_plane = to_intel_plane(plane);
3208
a712f8eb
SJ		 3209 if (intel_plane->pipe == pipe &&
3210 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 3211 p->plane[i++] = intel_plane->wm;
3212 }
3213}
3214
d4c2aa60
TU		 3215static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3216 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 3217 struct intel_plane_wm_parameters *p_params,
3218 uint16_t ddb_allocation,
d4c2aa60 3219 int level,
afb024aa
DL		 3220 uint16_t *out_blocks, /* out */
3221 uint8_t *out_lines /* out */)
2d41c0b5 3222{
d4c2aa60
TU		 3223 uint32_t latency = dev_priv->wm.skl_latency[level];
3224 uint32_t method1, method2;
3225 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3226 uint32_t res_blocks, res_lines;
3227 uint32_t selected_result;
2cd601c6 3228 uint8_t bytes_per_pixel;
2d41c0b5 3229
d4c2aa60 3230 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3231 return false;
3232
2cd601c6
CK		 3233 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3234 p_params->y_bytes_per_pixel :
3235 p_params->bytes_per_pixel;
2d41c0b5 3236 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 3237 bytes_per_pixel,
d4c2aa60 3238 latency);
2d41c0b5
PB		 3239 method2 = skl_wm_method2(p->pixel_rate,
3240 p->pipe_htotal,
3241 p_params->horiz_pixels,
2cd601c6 3242 bytes_per_pixel,
0fda6568 3243 p_params->tiling,
d4c2aa60 3244 latency);
2d41c0b5 3245
2cd601c6 3246 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 3247 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3248
0fda6568
TU		 3249 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3250 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3251 uint32_t min_scanlines = 4;
3252 uint32_t y_tile_minimum;
3253 if (intel_rotation_90_or_270(p_params->rotation)) {
3254 switch (p_params->bytes_per_pixel) {
3255 case 1:
3256 min_scanlines = 16;
3257 break;
3258 case 2:
3259 min_scanlines = 8;
3260 break;
3261 case 8:
3262 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3263 }
1fc0a8f7
TU		 3264 }
3265 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3266 selected_result = max(method2, y_tile_minimum);
3267 } else {
3268 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3269 selected_result = min(method1, method2);
3270 else
3271 selected_result = method1;
3272 }
2d41c0b5 3273
d4c2aa60
TU		 3274 res_blocks = selected_result + 1;
3275 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3276
0fda6568
TU		 3277 if (level >= 1 && level <= 7) {
3278 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3279 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3280 res_lines += 4;
3281 else
3282 res_blocks++;
3283 }
e6d66171 3284
d4c2aa60 3285 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3286 return false;
3287
3288 *out_blocks = res_blocks;
3289 *out_lines = res_lines;
2d41c0b5
PB		 3290
3291 return true;
3292}
3293
3294static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3295 struct skl_ddb_allocation *ddb,
3296 struct skl_pipe_wm_parameters *p,
3297 enum pipe pipe,
3298 int level,
3299 int num_planes,
3300 struct skl_wm_level *result)
3301{
2d41c0b5
PB		 3302 uint16_t ddb_blocks;
3303 int i;
3304
3305 for (i = 0; i < num_planes; i++) {
3306 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3307
d4c2aa60
TU		 3308 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3309 p, &p->plane[i],
2d41c0b5 3310 ddb_blocks,
d4c2aa60 3311 level,
2d41c0b5
PB		 3312 &result->plane_res_b[i],
3313 &result->plane_res_l[i]);
3314 }
3315
3316 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3317 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3318 ddb_blocks, level,
3319 &result->cursor_res_b,
2d41c0b5
PB		 3320 &result->cursor_res_l);
3321}
3322
407b50f3
DL		 3323static uint32_t
3324skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3325{
3ef00284 3326 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3327 return 0;
3328
661abfc0
MK		 3329 if (WARN_ON(p->pixel_rate == 0))
3330 return 0;
407b50f3 3331
661abfc0 3332 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
407b50f3
DL		 3333}
3334
3335static void skl_compute_transition_wm(struct drm_crtc *crtc,
3336 struct skl_pipe_wm_parameters *params,
9414f563 3337 struct skl_wm_level *trans_wm /* out */)
407b50f3 3338{
9414f563
DL		 3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 int i;
3341
407b50f3
DL		 3342 if (!params->active)
3343 return;
9414f563
DL		 3344
3345 /* Until we know more, just disable transition WMs */
3346 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3347 trans_wm->plane_en[i] = false;
3348 trans_wm->cursor_en = false;
407b50f3
DL		 3349}
3350
2d41c0b5
PB		 3351static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3352 struct skl_ddb_allocation *ddb,
3353 struct skl_pipe_wm_parameters *params,
3354 struct skl_pipe_wm *pipe_wm)
3355{
3356 struct drm_device *dev = crtc->dev;
3357 const struct drm_i915_private *dev_priv = dev->dev_private;
3358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3359 int level, max_level = ilk_wm_max_level(dev);
3360
3361 for (level = 0; level <= max_level; level++) {
3362 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3363 level, intel_num_planes(intel_crtc),
3364 &pipe_wm->wm[level]);
3365 }
3366 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3367
9414f563 3368 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3369}
3370
3371static void skl_compute_wm_results(struct drm_device *dev,
3372 struct skl_pipe_wm_parameters *p,
3373 struct skl_pipe_wm *p_wm,
3374 struct skl_wm_values *r,
3375 struct intel_crtc *intel_crtc)
3376{
3377 int level, max_level = ilk_wm_max_level(dev);
3378 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3379 uint32_t temp;
3380 int i;
2d41c0b5
PB		 3381
3382 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3383 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3384 temp = 0;
2d41c0b5
PB		 3385
3386 temp |= p_wm->wm[level].plane_res_l[i] <<
3387 PLANE_WM_LINES_SHIFT;
3388 temp |= p_wm->wm[level].plane_res_b[i];
3389 if (p_wm->wm[level].plane_en[i])
3390 temp |= PLANE_WM_EN;
3391
3392 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3393 }
3394
3395 temp = 0;
2d41c0b5
PB		 3396
3397 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3398 temp |= p_wm->wm[level].cursor_res_b;
3399
3400 if (p_wm->wm[level].cursor_en)
3401 temp |= PLANE_WM_EN;
3402
3403 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3404
3405 }
3406
9414f563
DL		 3407 /* transition WMs */
3408 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3409 temp = 0;
3410 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3411 temp |= p_wm->trans_wm.plane_res_b[i];
3412 if (p_wm->trans_wm.plane_en[i])
3413 temp |= PLANE_WM_EN;
3414
3415 r->plane_trans[pipe][i] = temp;
3416 }
3417
3418 temp = 0;
3419 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3420 temp |= p_wm->trans_wm.cursor_res_b;
3421 if (p_wm->trans_wm.cursor_en)
3422 temp |= PLANE_WM_EN;
3423
3424 r->cursor_trans[pipe] = temp;
3425
2d41c0b5
PB		 3426 r->wm_linetime[pipe] = p_wm->linetime;
3427}
3428
16160e3d
DL		 3429static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3430 const struct skl_ddb_entry *entry)
3431{
3432 if (entry->end)
3433 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3434 else
3435 I915_WRITE(reg, 0);
3436}
3437
2d41c0b5
PB		 3438static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3439 const struct skl_wm_values *new)
3440{
3441 struct drm_device *dev = dev_priv->dev;
3442 struct intel_crtc *crtc;
3443
3444 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3445 int i, level, max_level = ilk_wm_max_level(dev);
3446 enum pipe pipe = crtc->pipe;
3447
5d374d96
DL		 3448 if (!new->dirty[pipe])
3449 continue;
8211bd5b 3450
5d374d96 3451 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3452
5d374d96
DL		 3453 for (level = 0; level <= max_level; level++) {
3454 for (i = 0; i < intel_num_planes(crtc); i++)
3455 I915_WRITE(PLANE_WM(pipe, i, level),
3456 new->plane[pipe][i][level]);
3457 I915_WRITE(CUR_WM(pipe, level),
3458 new->cursor[pipe][level]);
2d41c0b5 3459 }
5d374d96
DL		 3460 for (i = 0; i < intel_num_planes(crtc); i++)
3461 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3462 new->plane_trans[pipe][i]);
3463 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3464
2cd601c6 3465 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3466 skl_ddb_entry_write(dev_priv,
3467 PLANE_BUF_CFG(pipe, i),
3468 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3469 skl_ddb_entry_write(dev_priv,
3470 PLANE_NV12_BUF_CFG(pipe, i),
3471 &new->ddb.y_plane[pipe][i]);
3472 }
5d374d96
DL		 3473
3474 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3475 &new->ddb.cursor[pipe]);
2d41c0b5 3476 }
2d41c0b5
PB		 3477}
3478
0e8fb7ba
DL		 3479/*
3480 * When setting up a new DDB allocation arrangement, we need to correctly
3481 * sequence the times at which the new allocations for the pipes are taken into
3482 * account or we'll have pipes fetching from space previously allocated to
3483 * another pipe.
3484 *
3485 * Roughly the sequence looks like:
3486 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3487 * overlapping with a previous light-up pipe (another way to put it is:
3488 * pipes with their new allocation strickly included into their old ones).
3489 * 2. re-allocate the other pipes that get their allocation reduced
3490 * 3. allocate the pipes having their allocation increased
3491 *
3492 * Steps 1. and 2. are here to take care of the following case:
3493 * - Initially DDB looks like this:
3494 * | B | C |
3495 * - enable pipe A.
3496 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3497 * allocation
3498 * | A | B | C |
3499 *
3500 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3501 */
3502
d21b795c
DL		 3503static void
3504skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3505{
0e8fb7ba
DL		 3506 int plane;
3507
d21b795c
DL		 3508 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3509
dd740780 3510 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3511 I915_WRITE(PLANE_SURF(pipe, plane),
3512 I915_READ(PLANE_SURF(pipe, plane)));
3513 }
3514 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3515}
3516
3517static bool
3518skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3519 const struct skl_ddb_allocation *new,
3520 enum pipe pipe)
3521{
3522 uint16_t old_size, new_size;
3523
3524 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3525 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3526
3527 return old_size != new_size &&
3528 new->pipe[pipe].start >= old->pipe[pipe].start &&
3529 new->pipe[pipe].end <= old->pipe[pipe].end;
3530}
3531
3532static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3533 struct skl_wm_values *new_values)
3534{
3535 struct drm_device *dev = dev_priv->dev;
3536 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3537 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3538 struct intel_crtc *crtc;
3539 enum pipe pipe;
3540
3541 new_ddb = &new_values->ddb;
3542 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3543
3544 /*
3545 * First pass: flush the pipes with the new allocation contained into
3546 * the old space.
3547 *
3548 * We'll wait for the vblank on those pipes to ensure we can safely
3549 * re-allocate the freed space without this pipe fetching from it.
3550 */
3551 for_each_intel_crtc(dev, crtc) {
3552 if (!crtc->active)
3553 continue;
3554
3555 pipe = crtc->pipe;
3556
3557 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3558 continue;
3559
d21b795c 3560 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3561 intel_wait_for_vblank(dev, pipe);
3562
3563 reallocated[pipe] = true;
3564 }
3565
3566
3567 /*
3568 * Second pass: flush the pipes that are having their allocation
3569 * reduced, but overlapping with a previous allocation.
3570 *
3571 * Here as well we need to wait for the vblank to make sure the freed
3572 * space is not used anymore.
3573 */
3574 for_each_intel_crtc(dev, crtc) {
3575 if (!crtc->active)
3576 continue;
3577
3578 pipe = crtc->pipe;
3579
3580 if (reallocated[pipe])
3581 continue;
3582
3583 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3584 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3585 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3586 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3587 reallocated[pipe] = true;
0e8fb7ba 3588 }
0e8fb7ba
DL		 3589 }
3590
3591 /*
3592 * Third pass: flush the pipes that got more space allocated.
3593 *
3594 * We don't need to actively wait for the update here, next vblank
3595 * will just get more DDB space with the correct WM values.
3596 */
3597 for_each_intel_crtc(dev, crtc) {
3598 if (!crtc->active)
3599 continue;
3600
3601 pipe = crtc->pipe;
3602
3603 /*
3604 * At this point, only the pipes more space than before are
3605 * left to re-allocate.
3606 */
3607 if (reallocated[pipe])
3608 continue;
3609
d21b795c 3610 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3611 }
3612}
3613
2d41c0b5
PB		 3614static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3615 struct skl_pipe_wm_parameters *params,
3616 struct intel_wm_config *config,
3617 struct skl_ddb_allocation *ddb, /* out */
3618 struct skl_pipe_wm *pipe_wm /* out */)
3619{
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621
3622 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3623 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3624 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3625
3626 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3627 return false;
3628
3629 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3630
2d41c0b5
PB		 3631 return true;
3632}
3633
3634static void skl_update_other_pipe_wm(struct drm_device *dev,
3635 struct drm_crtc *crtc,
3636 struct intel_wm_config *config,
3637 struct skl_wm_values *r)
3638{
3639 struct intel_crtc *intel_crtc;
3640 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3641
3642 /*
3643 * If the WM update hasn't changed the allocation for this_crtc (the
3644 * crtc we are currently computing the new WM values for), other
3645 * enabled crtcs will keep the same allocation and we don't need to
3646 * recompute anything for them.
3647 */
3648 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3649 return;
3650
3651 /*
3652 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3653 * other active pipes need new DDB allocation and WM values.
3654 */
3655 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3656 base.head) {
3657 struct skl_pipe_wm_parameters params = {};
3658 struct skl_pipe_wm pipe_wm = {};
3659 bool wm_changed;
3660
3661 if (this_crtc->pipe == intel_crtc->pipe)
3662 continue;
3663
3664 if (!intel_crtc->active)
3665 continue;
3666
3667 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3668 &params, config,
3669 &r->ddb, &pipe_wm);
3670
3671 /*
3672 * If we end up re-computing the other pipe WM values, it's
3673 * because it was really needed, so we expect the WM values to
3674 * be different.
3675 */
3676 WARN_ON(!wm_changed);
3677
3678 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3679 r->dirty[intel_crtc->pipe] = true;
3680 }
3681}
3682
adda50b8
BP		 3683static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3684{
3685 watermarks->wm_linetime[pipe] = 0;
3686 memset(watermarks->plane[pipe], 0,
3687 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3688 memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
3689 memset(watermarks->plane_trans[pipe],
3690 0, sizeof(uint32_t) * I915_MAX_PLANES);
3691 watermarks->cursor_trans[pipe] = 0;
3692
3693 /* Clear ddb entries for pipe */
3694 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3695 memset(&watermarks->ddb.plane[pipe], 0,
3696 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3697 memset(&watermarks->ddb.y_plane[pipe], 0,
3698 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3699 memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
3700
3701}
3702
2d41c0b5
PB		 3703static void skl_update_wm(struct drm_crtc *crtc)
3704{
3705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3706 struct drm_device *dev = crtc->dev;
3707 struct drm_i915_private *dev_priv = dev->dev_private;
3708 struct skl_pipe_wm_parameters params = {};
3709 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3710 struct skl_pipe_wm pipe_wm = {};
3711 struct intel_wm_config config = {};
3712
adda50b8
BP		 3713
3714 /* Clear all dirty flags */
3715 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3716
3717 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5
PB		 3718
3719 skl_compute_wm_global_parameters(dev, &config);
3720
3721 if (!skl_update_pipe_wm(crtc, &params, &config,
3722 &results->ddb, &pipe_wm))
3723 return;
3724
3725 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3726 results->dirty[intel_crtc->pipe] = true;
3727
3728 skl_update_other_pipe_wm(dev, crtc, &config, results);
3729 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3730 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3731
3732 /* store the new configuration */
3733 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3734}
3735
3736static void
3737skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3738 uint32_t sprite_width, uint32_t sprite_height,
3739 int pixel_size, bool enabled, bool scaled)
3740{
3741 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3742 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3743
3744 intel_plane->wm.enabled = enabled;
3745 intel_plane->wm.scaled = scaled;
3746 intel_plane->wm.horiz_pixels = sprite_width;
3747 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3748 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3749
3750 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3751 intel_plane->wm.bytes_per_pixel =
3752 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3753 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3754 intel_plane->wm.y_bytes_per_pixel =
3755 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3756 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3757
0fda6568
TU		 3758 /*
3759 * Framebuffer can be NULL on plane disable, but it does not
3760 * matter for watermarks if we assume no tiling in that case.
3761 */
3762 if (fb)
3763 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3764 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3765
3766 skl_update_wm(crtc);
3767}
3768
820c1980 3769static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3770{
7c4a395f 3771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3772 struct drm_device *dev = crtc->dev;
801bcfff 3773 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3774 struct ilk_wm_maximums max;
3775 struct ilk_pipe_wm_parameters params = {};
3776 struct ilk_wm_values results = {};
77c122bc 3777 enum intel_ddb_partitioning partitioning;
7c4a395f 3778 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3779 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3780 struct intel_wm_config config = {};
7c4a395f 3781
2a44b76b 3782 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3783
3784 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3785
3786 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3787 return;
861f3389 3788
7c4a395f 3789 intel_crtc->wm.active = pipe_wm;
861f3389 3790
2a44b76b
VS		 3791 ilk_compute_wm_config(dev, &config);
3792
34982fe1 3793 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3794 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3795
3796 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3797 if (INTEL_INFO(dev)->gen >= 7 &&
3798 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3799 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3800 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3801
820c1980 3802 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3803 } else {
198a1e9b 3804 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3805 }
3806
198a1e9b 3807 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3808 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3809
820c1980 3810 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3811
820c1980 3812 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3813}
3814
ed57cb8a
DL		 3815static void
3816ilk_update_sprite_wm(struct drm_plane *plane,
3817 struct drm_crtc *crtc,
3818 uint32_t sprite_width, uint32_t sprite_height,
3819 int pixel_size, bool enabled, bool scaled)
526682e9 3820{
8553c18e 3821 struct drm_device *dev = plane->dev;
adf3d35e 3822 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3823
adf3d35e
VS		 3824 intel_plane->wm.enabled = enabled;
3825 intel_plane->wm.scaled = scaled;
3826 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3827 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3828 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3829
8553c18e
VS		 3830 /*
3831 * IVB workaround: must disable low power watermarks for at least
3832 * one frame before enabling scaling. LP watermarks can be re-enabled
3833 * when scaling is disabled.
3834 *
3835 * WaCxSRDisabledForSpriteScaling:ivb
3836 */
3837 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3838 intel_wait_for_vblank(dev, intel_plane->pipe);
3839
820c1980 3840 ilk_update_wm(crtc);
526682e9
PZ		 3841}
3842
3078999f
PB		 3843static void skl_pipe_wm_active_state(uint32_t val,
3844 struct skl_pipe_wm *active,
3845 bool is_transwm,
3846 bool is_cursor,
3847 int i,
3848 int level)
3849{
3850 bool is_enabled = (val & PLANE_WM_EN) != 0;
3851
3852 if (!is_transwm) {
3853 if (!is_cursor) {
3854 active->wm[level].plane_en[i] = is_enabled;
3855 active->wm[level].plane_res_b[i] =
3856 val & PLANE_WM_BLOCKS_MASK;
3857 active->wm[level].plane_res_l[i] =
3858 (val >> PLANE_WM_LINES_SHIFT) &
3859 PLANE_WM_LINES_MASK;
3860 } else {
3861 active->wm[level].cursor_en = is_enabled;
3862 active->wm[level].cursor_res_b =
3863 val & PLANE_WM_BLOCKS_MASK;
3864 active->wm[level].cursor_res_l =
3865 (val >> PLANE_WM_LINES_SHIFT) &
3866 PLANE_WM_LINES_MASK;
3867 }
3868 } else {
3869 if (!is_cursor) {
3870 active->trans_wm.plane_en[i] = is_enabled;
3871 active->trans_wm.plane_res_b[i] =
3872 val & PLANE_WM_BLOCKS_MASK;
3873 active->trans_wm.plane_res_l[i] =
3874 (val >> PLANE_WM_LINES_SHIFT) &
3875 PLANE_WM_LINES_MASK;
3876 } else {
3877 active->trans_wm.cursor_en = is_enabled;
3878 active->trans_wm.cursor_res_b =
3879 val & PLANE_WM_BLOCKS_MASK;
3880 active->trans_wm.cursor_res_l =
3881 (val >> PLANE_WM_LINES_SHIFT) &
3882 PLANE_WM_LINES_MASK;
3883 }
3884 }
3885}
3886
3887static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3888{
3889 struct drm_device *dev = crtc->dev;
3890 struct drm_i915_private *dev_priv = dev->dev_private;
3891 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3894 enum pipe pipe = intel_crtc->pipe;
3895 int level, i, max_level;
3896 uint32_t temp;
3897
3898 max_level = ilk_wm_max_level(dev);
3899
3900 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3901
3902 for (level = 0; level <= max_level; level++) {
3903 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3904 hw->plane[pipe][i][level] =
3905 I915_READ(PLANE_WM(pipe, i, level));
3906 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3907 }
3908
3909 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3910 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3911 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3912
3ef00284 3913 if (!intel_crtc->active)
3078999f
PB		 3914 return;
3915
3916 hw->dirty[pipe] = true;
3917
3918 active->linetime = hw->wm_linetime[pipe];
3919
3920 for (level = 0; level <= max_level; level++) {
3921 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3922 temp = hw->plane[pipe][i][level];
3923 skl_pipe_wm_active_state(temp, active, false,
3924 false, i, level);
3925 }
3926 temp = hw->cursor[pipe][level];
3927 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3928 }
3929
3930 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3931 temp = hw->plane_trans[pipe][i];
3932 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3933 }
3934
3935 temp = hw->cursor_trans[pipe];
3936 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3937}
3938
3939void skl_wm_get_hw_state(struct drm_device *dev)
3940{
a269c583
DL		 3941 struct drm_i915_private *dev_priv = dev->dev_private;
3942 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3943 struct drm_crtc *crtc;
3944
a269c583 3945 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3946 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3947 skl_pipe_wm_get_hw_state(crtc);
3948}
3949
243e6a44
VS		 3950static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3951{
3952 struct drm_device *dev = crtc->dev;
3953 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3954 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3956 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3957 enum pipe pipe = intel_crtc->pipe;
3958 static const unsigned int wm0_pipe_reg[] = {
3959 [PIPE_A] = WM0_PIPEA_ILK,
3960 [PIPE_B] = WM0_PIPEB_ILK,
3961 [PIPE_C] = WM0_PIPEC_IVB,
3962 };
3963
3964 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3965 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3966 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3967
3ef00284 3968 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3969
3970 if (active->pipe_enabled) {
243e6a44
VS		 3971 u32 tmp = hw->wm_pipe[pipe];
3972
3973 /*
3974 * For active pipes LP0 watermark is marked as
3975 * enabled, and LP1+ watermaks as disabled since
3976 * we can't really reverse compute them in case
3977 * multiple pipes are active.
3978 */
3979 active->wm[0].enable = true;
3980 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3981 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3982 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3983 active->linetime = hw->wm_linetime[pipe];
3984 } else {
3985 int level, max_level = ilk_wm_max_level(dev);
3986
3987 /*
3988 * For inactive pipes, all watermark levels
3989 * should be marked as enabled but zeroed,
3990 * which is what we'd compute them to.
3991 */
3992 for (level = 0; level <= max_level; level++)
3993 active->wm[level].enable = true;
3994 }
3995}
3996
6eb1a681
VS		 3997#define _FW_WM(value, plane) \
3998 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3999#define _FW_WM_VLV(value, plane) \
4000 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4001
4002static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4003 struct vlv_wm_values *wm)
4004{
4005 enum pipe pipe;
4006 uint32_t tmp;
4007
4008 for_each_pipe(dev_priv, pipe) {
4009 tmp = I915_READ(VLV_DDL(pipe));
4010
4011 wm->ddl[pipe].primary =
4012 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4013 wm->ddl[pipe].cursor =
4014 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4015 wm->ddl[pipe].sprite[0] =
4016 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4017 wm->ddl[pipe].sprite[1] =
4018 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4019 }
4020
4021 tmp = I915_READ(DSPFW1);
4022 wm->sr.plane = _FW_WM(tmp, SR);
4023 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4024 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4025 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4026
4027 tmp = I915_READ(DSPFW2);
4028 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4029 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4030 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4031
4032 tmp = I915_READ(DSPFW3);
4033 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4034
4035 if (IS_CHERRYVIEW(dev_priv)) {
4036 tmp = I915_READ(DSPFW7_CHV);
4037 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4038 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4039
4040 tmp = I915_READ(DSPFW8_CHV);
4041 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4042 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4043
4044 tmp = I915_READ(DSPFW9_CHV);
4045 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4046 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4047
4048 tmp = I915_READ(DSPHOWM);
4049 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4050 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4051 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4052 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4053 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4054 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4055 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4056 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4057 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4058 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4059 } else {
4060 tmp = I915_READ(DSPFW7);
4061 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4062 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4063
4064 tmp = I915_READ(DSPHOWM);
4065 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4066 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4067 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4068 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4069 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4070 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4071 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4072 }
4073}
4074
4075#undef _FW_WM
4076#undef _FW_WM_VLV
4077
4078void vlv_wm_get_hw_state(struct drm_device *dev)
4079{
4080 struct drm_i915_private *dev_priv = to_i915(dev);
4081 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4082 struct intel_plane *plane;
4083 enum pipe pipe;
4084 u32 val;
4085
4086 vlv_read_wm_values(dev_priv, wm);
4087
4088 for_each_intel_plane(dev, plane) {
4089 switch (plane->base.type) {
4090 int sprite;
4091 case DRM_PLANE_TYPE_CURSOR:
4092 plane->wm.fifo_size = 63;
4093 break;
4094 case DRM_PLANE_TYPE_PRIMARY:
4095 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4096 break;
4097 case DRM_PLANE_TYPE_OVERLAY:
4098 sprite = plane->plane;
4099 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4100 break;
4101 }
4102 }
4103
4104 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4105 wm->level = VLV_WM_LEVEL_PM2;
4106
4107 if (IS_CHERRYVIEW(dev_priv)) {
4108 mutex_lock(&dev_priv->rps.hw_lock);
4109
4110 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4111 if (val & DSP_MAXFIFO_PM5_ENABLE)
4112 wm->level = VLV_WM_LEVEL_PM5;
4113
58590c14
VS		 4114 /*
4115 * If DDR DVFS is disabled in the BIOS, Punit
4116 * will never ack the request. So if that happens
4117 * assume we don't have to enable/disable DDR DVFS
4118 * dynamically. To test that just set the REQ_ACK
4119 * bit to poke the Punit, but don't change the
4120 * HIGH/LOW bits so that we don't actually change
4121 * the current state.
4122 */
6eb1a681 4123 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4124 val |= FORCE_DDR_FREQ_REQ_ACK;
4125 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4126
4127 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4128 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4129 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4130 "assuming DDR DVFS is disabled\n");
4131 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4132 } else {
4133 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4134 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4135 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4136 }
6eb1a681
VS		 4137
4138 mutex_unlock(&dev_priv->rps.hw_lock);
4139 }
4140
4141 for_each_pipe(dev_priv, pipe)
4142 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4143 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4144 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4145
4146 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4147 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4148}
4149
243e6a44
VS		 4150void ilk_wm_get_hw_state(struct drm_device *dev)
4151{
4152 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4153 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4154 struct drm_crtc *crtc;
4155
70e1e0ec 4156 for_each_crtc(dev, crtc)
243e6a44
VS		 4157 ilk_pipe_wm_get_hw_state(crtc);
4158
4159 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4160 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4161 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4162
4163 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4164 if (INTEL_INFO(dev)->gen >= 7) {
4165 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4166 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4167 }
243e6a44 4168
a42a5719 4169 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4170 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4171 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4172 else if (IS_IVYBRIDGE(dev))
4173 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4174 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4175
4176 hw->enable_fbc_wm =
4177 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4178}
4179
b445e3b0
ED		 4180/**
4181 * intel_update_watermarks - update FIFO watermark values based on current modes
4182 *
4183 * Calculate watermark values for the various WM regs based on current mode
4184 * and plane configuration.
4185 *
4186 * There are several cases to deal with here:
4187 * - normal (i.e. non-self-refresh)
4188 * - self-refresh (SR) mode
4189 * - lines are large relative to FIFO size (buffer can hold up to 2)
4190 * - lines are small relative to FIFO size (buffer can hold more than 2
4191 * lines), so need to account for TLB latency
4192 *
4193 * The normal calculation is:
4194 * watermark = dotclock * bytes per pixel * latency
4195 * where latency is platform & configuration dependent (we assume pessimal
4196 * values here).
4197 *
4198 * The SR calculation is:
4199 * watermark = (trunc(latency/line time)+1) * surface width *
4200 * bytes per pixel
4201 * where
4202 * line time = htotal / dotclock
4203 * surface width = hdisplay for normal plane and 64 for cursor
4204 * and latency is assumed to be high, as above.
4205 *
4206 * The final value programmed to the register should always be rounded up,
4207 * and include an extra 2 entries to account for clock crossings.
4208 *
4209 * We don't use the sprite, so we can ignore that. And on Crestline we have
4210 * to set the non-SR watermarks to 8.
4211 */
46ba614c 4212void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4213{
46ba614c 4214 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4215
4216 if (dev_priv->display.update_wm)
46ba614c 4217 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4218}
4219
adf3d35e
VS		 4220void intel_update_sprite_watermarks(struct drm_plane *plane,
4221 struct drm_crtc *crtc,
ed57cb8a
DL		 4222 uint32_t sprite_width,
4223 uint32_t sprite_height,
4224 int pixel_size,
39db4a4d 4225 bool enabled, bool scaled)
b445e3b0 4226{
adf3d35e 4227 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 4228
4229 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 4230 dev_priv->display.update_sprite_wm(plane, crtc,
4231 sprite_width, sprite_height,
39db4a4d 4232 pixel_size, enabled, scaled);
b445e3b0
ED		 4233}
4234
9270388e
DV		 4235/**
4236 * Lock protecting IPS related data structures
9270388e
DV		 4237 */
4238DEFINE_SPINLOCK(mchdev_lock);
4239
4240/* Global for IPS driver to get at the current i915 device. Protected by
4241 * mchdev_lock. */
4242static struct drm_i915_private *i915_mch_dev;
4243
2b4e57bd
ED		 4244bool ironlake_set_drps(struct drm_device *dev, u8 val)
4245{
4246 struct drm_i915_private *dev_priv = dev->dev_private;
4247 u16 rgvswctl;
4248
9270388e
DV		 4249 assert_spin_locked(&mchdev_lock);
4250
2b4e57bd
ED		 4251 rgvswctl = I915_READ16(MEMSWCTL);
4252 if (rgvswctl & MEMCTL_CMD_STS) {
4253 DRM_DEBUG("gpu busy, RCS change rejected\n");
4254 return false; /* still busy with another command */
4255 }
4256
4257 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4258 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4259 I915_WRITE16(MEMSWCTL, rgvswctl);
4260 POSTING_READ16(MEMSWCTL);
4261
4262 rgvswctl |= MEMCTL_CMD_STS;
4263 I915_WRITE16(MEMSWCTL, rgvswctl);
4264
4265 return true;
4266}
4267
8090c6b9 4268static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4269{
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 u32 rgvmodectl = I915_READ(MEMMODECTL);
4272 u8 fmax, fmin, fstart, vstart;
4273
9270388e
DV		 4274 spin_lock_irq(&mchdev_lock);
4275
2b4e57bd
ED		 4276 /* Enable temp reporting */
4277 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4278 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4279
4280 /* 100ms RC evaluation intervals */
4281 I915_WRITE(RCUPEI, 100000);
4282 I915_WRITE(RCDNEI, 100000);
4283
4284 /* Set max/min thresholds to 90ms and 80ms respectively */
4285 I915_WRITE(RCBMAXAVG, 90000);
4286 I915_WRITE(RCBMINAVG, 80000);
4287
4288 I915_WRITE(MEMIHYST, 1);
4289
4290 /* Set up min, max, and cur for interrupt handling */
4291 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4292 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4293 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4294 MEMMODE_FSTART_SHIFT;
4295
616847e7 4296 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4297 PXVFREQ_PX_SHIFT;
4298
20e4d407
DV		 4299 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4300 dev_priv->ips.fstart = fstart;
2b4e57bd 4301
20e4d407
DV		 4302 dev_priv->ips.max_delay = fstart;
4303 dev_priv->ips.min_delay = fmin;
4304 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4305
4306 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4307 fmax, fmin, fstart);
4308
4309 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4310
4311 /*
4312 * Interrupts will be enabled in ironlake_irq_postinstall
4313 */
4314
4315 I915_WRITE(VIDSTART, vstart);
4316 POSTING_READ(VIDSTART);
4317
4318 rgvmodectl |= MEMMODE_SWMODE_EN;
4319 I915_WRITE(MEMMODECTL, rgvmodectl);
4320
9270388e 4321 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4322 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4323 mdelay(1);
2b4e57bd
ED		 4324
4325 ironlake_set_drps(dev, fstart);
4326
7d81c3e0
VS		 4327 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4328 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4329 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4330 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4331 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4332
4333 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4334}
4335
8090c6b9 4336static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4337{
4338 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4339 u16 rgvswctl;
4340
4341 spin_lock_irq(&mchdev_lock);
4342
4343 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4344
4345 /* Ack interrupts, disable EFC interrupt */
4346 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4347 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4348 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4349 I915_WRITE(DEIIR, DE_PCU_EVENT);
4350 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4351
4352 /* Go back to the starting frequency */
20e4d407 4353 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4354 mdelay(1);
2b4e57bd
ED		 4355 rgvswctl |= MEMCTL_CMD_STS;
4356 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4357 mdelay(1);
2b4e57bd 4358
9270388e 4359 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4360}
4361
acbe9475
DV		 4362/* There's a funny hw issue where the hw returns all 0 when reading from
4363 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4364 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4365 * all limits and the gpu stuck at whatever frequency it is at atm).
4366 */
74ef1173 4367static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4368{
7b9e0ae6 4369 u32 limits;
2b4e57bd 4370
20b46e59
DV		 4371 /* Only set the down limit when we've reached the lowest level to avoid
4372 * getting more interrupts, otherwise leave this clear. This prevents a
4373 * race in the hw when coming out of rc6: There's a tiny window where
4374 * the hw runs at the minimal clock before selecting the desired
4375 * frequency, if the down threshold expires in that window we will not
4376 * receive a down interrupt. */
74ef1173
AG		 4377 if (IS_GEN9(dev_priv->dev)) {
4378 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4379 if (val <= dev_priv->rps.min_freq_softlimit)
4380 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4381 } else {
4382 limits = dev_priv->rps.max_freq_softlimit << 24;
4383 if (val <= dev_priv->rps.min_freq_softlimit)
4384 limits |= dev_priv->rps.min_freq_softlimit << 16;
4385 }
20b46e59
DV		 4386
4387 return limits;
4388}
4389
dd75fdc8
CW		 4390static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4391{
4392 int new_power;
8a586437
AG		 4393 u32 threshold_up = 0, threshold_down = 0; /* in % */
4394 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4395
4396 new_power = dev_priv->rps.power;
4397 switch (dev_priv->rps.power) {
4398 case LOW_POWER:
b39fb297 4399 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4400 new_power = BETWEEN;
4401 break;
4402
4403 case BETWEEN:
b39fb297 4404 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4405 new_power = LOW_POWER;
b39fb297 4406 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4407 new_power = HIGH_POWER;
4408 break;
4409
4410 case HIGH_POWER:
b39fb297 4411 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4412 new_power = BETWEEN;
4413 break;
4414 }
4415 /* Max/min bins are special */
aed242ff 4416 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4417 new_power = LOW_POWER;
aed242ff 4418 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4419 new_power = HIGH_POWER;
4420 if (new_power == dev_priv->rps.power)
4421 return;
4422
4423 /* Note the units here are not exactly 1us, but 1280ns. */
4424 switch (new_power) {
4425 case LOW_POWER:
4426 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4427 ei_up = 16000;
4428 threshold_up = 95;
dd75fdc8
CW		 4429
4430 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4431 ei_down = 32000;
4432 threshold_down = 85;
dd75fdc8
CW		 4433 break;
4434
4435 case BETWEEN:
4436 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4437 ei_up = 13000;
4438 threshold_up = 90;
dd75fdc8
CW		 4439
4440 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4441 ei_down = 32000;
4442 threshold_down = 75;
dd75fdc8
CW		 4443 break;
4444
4445 case HIGH_POWER:
4446 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4447 ei_up = 10000;
4448 threshold_up = 85;
dd75fdc8
CW		 4449
4450 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4451 ei_down = 32000;
4452 threshold_down = 60;
dd75fdc8
CW		 4453 break;
4454 }
4455
8a586437
AG		 4456 I915_WRITE(GEN6_RP_UP_EI,
4457 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4458 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4459 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4460
4461 I915_WRITE(GEN6_RP_DOWN_EI,
4462 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4463 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4464 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4465
4466 I915_WRITE(GEN6_RP_CONTROL,
4467 GEN6_RP_MEDIA_TURBO |
4468 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4469 GEN6_RP_MEDIA_IS_GFX |
4470 GEN6_RP_ENABLE |
4471 GEN6_RP_UP_BUSY_AVG |
4472 GEN6_RP_DOWN_IDLE_AVG);
4473
dd75fdc8 4474 dev_priv->rps.power = new_power;
8fb55197
CW		 4475 dev_priv->rps.up_threshold = threshold_up;
4476 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4477 dev_priv->rps.last_adj = 0;
4478}
4479
2876ce73
CW		 4480static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4481{
4482 u32 mask = 0;
4483
4484 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4485 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4486 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4487 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4488
7b3c29f6
CW		 4489 mask &= dev_priv->pm_rps_events;
4490
59d02a1f 4491 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4492}
4493
b8a5ff8d
JM		 4494/* gen6_set_rps is called to update the frequency request, but should also be
4495 * called when the range (min_delay and max_delay) is modified so that we can
4496 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4497static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4498{
4499 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4500
23eafea6
SAK		 4501 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4502 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4503 return;
4504
4fc688ce 4505 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4506 WARN_ON(val > dev_priv->rps.max_freq);
4507 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4508
eb64cad1
CW		 4509 /* min/max delay may still have been modified so be sure to
4510 * write the limits value.
4511 */
4512 if (val != dev_priv->rps.cur_freq) {
4513 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4514
5704195c
AG		 4515 if (IS_GEN9(dev))
4516 I915_WRITE(GEN6_RPNSWREQ,
4517 GEN9_FREQUENCY(val));
4518 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4519 I915_WRITE(GEN6_RPNSWREQ,
4520 HSW_FREQUENCY(val));
4521 else
4522 I915_WRITE(GEN6_RPNSWREQ,
4523 GEN6_FREQUENCY(val) |
4524 GEN6_OFFSET(0) |
4525 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4526 }
7b9e0ae6 4527
7b9e0ae6
CW		 4528 /* Make sure we continue to get interrupts
4529 * until we hit the minimum or maximum frequencies.
4530 */
74ef1173 4531 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4532 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4533
d5570a72
BW		 4534 POSTING_READ(GEN6_RPNSWREQ);
4535
b39fb297 4536 dev_priv->rps.cur_freq = val;
be2cde9a 4537 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4538}
4539
ffe02b40
VS		 4540static void valleyview_set_rps(struct drm_device *dev, u8 val)
4541{
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543
4544 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4545 WARN_ON(val > dev_priv->rps.max_freq);
4546 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4547
4548 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4549 "Odd GPU freq value\n"))
4550 val &= ~1;
4551
cd25dd5b
D		 4552 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4553
8fb55197 4554 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4555 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4556 if (!IS_CHERRYVIEW(dev_priv))
4557 gen6_set_rps_thresholds(dev_priv, val);
4558 }
ffe02b40 4559
ffe02b40
VS		 4560 dev_priv->rps.cur_freq = val;
4561 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4562}
4563
a7f6e231 4564/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4565 *
4566 * * If Gfx is Idle, then
a7f6e231
D		 4567 * 1. Forcewake Media well.
4568 * 2. Request idle freq.
4569 * 3. Release Forcewake of Media well.
76c3552f
D		 4570*/
4571static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4572{
aed242ff 4573 u32 val = dev_priv->rps.idle_freq;
5549d25f 4574
aed242ff 4575 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4576 return;
4577
a7f6e231
D		 4578 /* Wake up the media well, as that takes a lot less
4579 * power than the Render well. */
4580 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4581 valleyview_set_rps(dev_priv->dev, val);
4582 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4583}
4584
43cf3bf0
CW		 4585void gen6_rps_busy(struct drm_i915_private *dev_priv)
4586{
4587 mutex_lock(&dev_priv->rps.hw_lock);
4588 if (dev_priv->rps.enabled) {
4589 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4590 gen6_rps_reset_ei(dev_priv);
4591 I915_WRITE(GEN6_PMINTRMSK,
4592 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4593 }
4594 mutex_unlock(&dev_priv->rps.hw_lock);
4595}
4596
b29c19b6
CW		 4597void gen6_rps_idle(struct drm_i915_private *dev_priv)
4598{
691bb717
DL		 4599 struct drm_device *dev = dev_priv->dev;
4600
b29c19b6 4601 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4602 if (dev_priv->rps.enabled) {
21a11fff 4603 if (IS_VALLEYVIEW(dev))
76c3552f 4604 vlv_set_rps_idle(dev_priv);
7526ed79 4605 else
aed242ff 4606 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4607 dev_priv->rps.last_adj = 0;
43cf3bf0 4608 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4609 }
8d3afd7d 4610 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4611
8d3afd7d 4612 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4613 while (!list_empty(&dev_priv->rps.clients))
4614 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4615 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4616}
4617
1854d5ca 4618void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4619 struct intel_rps_client *rps,
4620 unsigned long submitted)
b29c19b6 4621{
8d3afd7d
CW		 4622 /* This is intentionally racy! We peek at the state here, then
4623 * validate inside the RPS worker.
4624 */
4625 if (!(dev_priv->mm.busy &&
4626 dev_priv->rps.enabled &&
4627 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4628 return;
43cf3bf0 4629
e61b9958
CW		 4630 /* Force a RPS boost (and don't count it against the client) if
4631 * the GPU is severely congested.
4632 */
d0bc54f2 4633 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4634 rps = NULL;
4635
8d3afd7d
CW		 4636 spin_lock(&dev_priv->rps.client_lock);
4637 if (rps == NULL || list_empty(&rps->link)) {
4638 spin_lock_irq(&dev_priv->irq_lock);
4639 if (dev_priv->rps.interrupts_enabled) {
4640 dev_priv->rps.client_boost = true;
4641 queue_work(dev_priv->wq, &dev_priv->rps.work);
4642 }
4643 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4644
2e1b8730
CW		 4645 if (rps != NULL) {
4646 list_add(&rps->link, &dev_priv->rps.clients);
4647 rps->boosts++;
1854d5ca
CW		 4648 } else
4649 dev_priv->rps.boosts++;
c0951f0c 4650 }
8d3afd7d 4651 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4652}
4653
ffe02b40 4654void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4655{
ffe02b40
VS		 4656 if (IS_VALLEYVIEW(dev))
4657 valleyview_set_rps(dev, val);
4658 else
4659 gen6_set_rps(dev, val);
0a073b84
JB		 4660}
4661
20e49366
ZW		 4662static void gen9_disable_rps(struct drm_device *dev)
4663{
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4667 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4668}
4669
44fc7d5c 4670static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4671{
4672 struct drm_i915_private *dev_priv = dev->dev_private;
4673
4674 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4675 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4676}
4677
38807746
D		 4678static void cherryview_disable_rps(struct drm_device *dev)
4679{
4680 struct drm_i915_private *dev_priv = dev->dev_private;
4681
4682 I915_WRITE(GEN6_RC_CONTROL, 0);
4683}
4684
44fc7d5c
DV		 4685static void valleyview_disable_rps(struct drm_device *dev)
4686{
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688
98a2e5f9
D		 4689 /* we're doing forcewake before Disabling RC6,
4690 * This what the BIOS expects when going into suspend */
59bad947 4691 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4692
44fc7d5c 4693 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4694
59bad947 4695 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4696}
4697
dc39fff7
BW		 4698static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4699{
91ca689a
ID		 4700 if (IS_VALLEYVIEW(dev)) {
4701 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4702 mode = GEN6_RC_CTL_RC6_ENABLE;
4703 else
4704 mode = 0;
4705 }
58abf1da
RV		 4706 if (HAS_RC6p(dev))
4707 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4708 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4709 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4710 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4711
4712 else
4713 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4714 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4715}
4716
e6069ca8 4717static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4718{
e7d66d89
DV		 4719 /* No RC6 before Ironlake and code is gone for ilk. */
4720 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4721 return 0;
4722
456470eb 4723 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4724 if (enable_rc6 >= 0) {
4725 int mask;
4726
58abf1da 4727 if (HAS_RC6p(dev))
e6069ca8
ID		 4728 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4729 INTEL_RC6pp_ENABLE;
4730 else
4731 mask = INTEL_RC6_ENABLE;
4732
4733 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4734 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4735 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4736
4737 return enable_rc6 & mask;
4738 }
2b4e57bd 4739
8bade1ad 4740 if (IS_IVYBRIDGE(dev))
cca84a1f 4741 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4742
4743 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4744}
4745
e6069ca8
ID		 4746int intel_enable_rc6(const struct drm_device *dev)
4747{
4748 return i915.enable_rc6;
4749}
4750
93ee2920 4751static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4752{
93ee2920
TR		 4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 uint32_t rp_state_cap;
4755 u32 ddcc_status = 0;
4756 int ret;
4757
3280e8b0
BW		 4758 /* All of these values are in units of 50MHz */
4759 dev_priv->rps.cur_freq = 0;
93ee2920 4760 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4761 if (IS_BROXTON(dev)) {
4762 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4763 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4764 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4765 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4766 } else {
4767 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4768 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4769 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4770 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4771 }
4772
3280e8b0
BW		 4773 /* hw_max = RP0 until we check for overclocking */
4774 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4775
93ee2920 4776 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4777 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4778 ret = sandybridge_pcode_read(dev_priv,
4779 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4780 &ddcc_status);
4781 if (0 == ret)
4782 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4783 clamp_t(u8,
4784 ((ddcc_status >> 8) & 0xff),
4785 dev_priv->rps.min_freq,
4786 dev_priv->rps.max_freq);
93ee2920
TR		 4787 }
4788
c5e0688c
AG		 4789 if (IS_SKYLAKE(dev)) {
4790 /* Store the frequency values in 16.66 MHZ units, which is
4791 the natural hardware unit for SKL */
4792 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4793 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4794 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4795 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4796 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4797 }
4798
aed242ff
CW		 4799 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4800
3280e8b0
BW		 4801 /* Preserve min/max settings in case of re-init */
4802 if (dev_priv->rps.max_freq_softlimit == 0)
4803 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4804
93ee2920
TR		 4805 if (dev_priv->rps.min_freq_softlimit == 0) {
4806 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4807 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4808 max_t(int, dev_priv->rps.efficient_freq,
4809 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4810 else
4811 dev_priv->rps.min_freq_softlimit =
4812 dev_priv->rps.min_freq;
4813 }
3280e8b0
BW		 4814}
4815
b6fef0ef 4816/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4817static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4818{
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820
4821 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4822
ba1c554c
DL		 4823 gen6_init_rps_frequencies(dev);
4824
23eafea6
SAK		 4825 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4826 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4827 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4828 return;
4829 }
4830
0beb059a
AG		 4831 /* Program defaults and thresholds for RPS*/
4832 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4833 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4834
4835 /* 1 second timeout*/
4836 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4837 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4838
b6fef0ef 4839 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4840
0beb059a
AG		 4841 /* Leaning on the below call to gen6_set_rps to program/setup the
4842 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4843 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4844 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4845 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4846
4847 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4848}
4849
4850static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4851{
4852 struct drm_i915_private *dev_priv = dev->dev_private;
4853 struct intel_engine_cs *ring;
4854 uint32_t rc6_mask = 0;
4855 int unused;
4856
4857 /* 1a: Software RC state - RC0 */
4858 I915_WRITE(GEN6_RC_STATE, 0);
4859
4860 /* 1b: Get forcewake during program sequence. Although the driver
4861 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4862 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4863
4864 /* 2a: Disable RC states. */
4865 I915_WRITE(GEN6_RC_CONTROL, 0);
4866
4867 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4868
4869 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4870 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4871 (INTEL_REVID(dev) <= SKL_REVID_E0)))
4872 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4873 else
4874 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4875 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4876 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4877 for_each_ring(ring, dev_priv, unused)
4878 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4879
4880 if (HAS_GUC_UCODE(dev))
4881 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4882
20e49366
ZW		 4883 I915_WRITE(GEN6_RC_SLEEP, 0);
4884 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4885
38c23527
ZW		 4886 /* 2c: Program Coarse Power Gating Policies. */
4887 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4888 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4889
20e49366
ZW		 4890 /* 3a: Enable RC6 */
4891 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4892 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4893 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4894 "on" : "off");
e3429cd2
SAK		 4895
4896 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4897 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
4898 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4899 GEN7_RC_CTL_TO_MODE |
4900 rc6_mask);
4901 else
4902 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4903 GEN6_RC_CTL_EI_MODE(1) |
4904 rc6_mask);
20e49366 4905
cb07bae0
SK		 4906 /*
4907 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4908 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4909 */
f2d2fe95
SAK		 4910 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4911 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4912 I915_WRITE(GEN9_PG_ENABLE, 0);
4913 else
4914 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4915 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4916
59bad947 4917 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4918
4919}
4920
6edee7f3
BW		 4921static void gen8_enable_rps(struct drm_device *dev)
4922{
4923 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4924 struct intel_engine_cs *ring;
93ee2920 4925 uint32_t rc6_mask = 0;
6edee7f3
BW		 4926 int unused;
4927
4928 /* 1a: Software RC state - RC0 */
4929 I915_WRITE(GEN6_RC_STATE, 0);
4930
4931 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4932 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4933 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4934
4935 /* 2a: Disable RC states. */
4936 I915_WRITE(GEN6_RC_CONTROL, 0);
4937
93ee2920
TR		 4938 /* Initialize rps frequencies */
4939 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4940
4941 /* 2b: Program RC6 thresholds.*/
4942 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4943 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4944 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4945 for_each_ring(ring, dev_priv, unused)
4946 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4947 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4948 if (IS_BROADWELL(dev))
4949 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4950 else
4951 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4952
4953 /* 3: Enable RC6 */
4954 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4955 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4956 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4957 if (IS_BROADWELL(dev))
4958 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4959 GEN7_RC_CTL_TO_MODE |
4960 rc6_mask);
4961 else
4962 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4963 GEN6_RC_CTL_EI_MODE(1) |
4964 rc6_mask);
6edee7f3
BW		 4965
4966 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4967 I915_WRITE(GEN6_RPNSWREQ,
4968 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4969 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4970 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4971 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4972 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4973
4974 /* Docs recommend 900MHz, and 300 MHz respectively */
4975 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4976 dev_priv->rps.max_freq_softlimit << 24 |
4977 dev_priv->rps.min_freq_softlimit << 16);
4978
4979 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4980 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4981 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4982 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4983
4984 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4985
4986 /* 5: Enable RPS */
7526ed79
DV		 4987 I915_WRITE(GEN6_RP_CONTROL,
4988 GEN6_RP_MEDIA_TURBO |
4989 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4990 GEN6_RP_MEDIA_IS_GFX |
4991 GEN6_RP_ENABLE |
4992 GEN6_RP_UP_BUSY_AVG |
4993 GEN6_RP_DOWN_IDLE_AVG);
4994
4995 /* 6: Ring frequency + overclocking (our driver does this later */
4996
c7f3153a 4997 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4998 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4999
59bad947 5000 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5001}
5002
79f5b2c7 5003static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 5004{
79f5b2c7 5005 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5006 struct intel_engine_cs *ring;
d060c169 5007 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5008 u32 gtfifodbg;
2b4e57bd 5009 int rc6_mode;
42c0526c 5010 int i, ret;
2b4e57bd 5011
4fc688ce 5012 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5013
2b4e57bd
ED		 5014 /* Here begins a magic sequence of register writes to enable
5015 * auto-downclocking.
5016 *
5017 * Perhaps there might be some value in exposing these to
5018 * userspace...
5019 */
5020 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5021
5022 /* Clear the DBG now so we don't confuse earlier errors */
5023 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5024 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5025 I915_WRITE(GTFIFODBG, gtfifodbg);
5026 }
5027
59bad947 5028 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5029
93ee2920
TR		 5030 /* Initialize rps frequencies */
5031 gen6_init_rps_frequencies(dev);
dd0a1aa1 5032
2b4e57bd
ED		 5033 /* disable the counters and set deterministic thresholds */
5034 I915_WRITE(GEN6_RC_CONTROL, 0);
5035
5036 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5037 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5038 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5039 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5040 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5041
b4519513
CW		 5042 for_each_ring(ring, dev_priv, i)
5043 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 5044
5045 I915_WRITE(GEN6_RC_SLEEP, 0);
5046 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 5047 if (IS_IVYBRIDGE(dev))
351aa566
SM		 5048 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5049 else
5050 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5051 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5052 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5053
5a7dc92a 5054 /* Check if we are enabling RC6 */
2b4e57bd
ED		 5055 rc6_mode = intel_enable_rc6(dev_priv->dev);
5056 if (rc6_mode & INTEL_RC6_ENABLE)
5057 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5058
5a7dc92a
ED		 5059 /* We don't use those on Haswell */
5060 if (!IS_HASWELL(dev)) {
5061 if (rc6_mode & INTEL_RC6p_ENABLE)
5062 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5063
5a7dc92a
ED		 5064 if (rc6_mode & INTEL_RC6pp_ENABLE)
5065 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5066 }
2b4e57bd 5067
dc39fff7 5068 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 5069
5070 I915_WRITE(GEN6_RC_CONTROL,
5071 rc6_mask |
5072 GEN6_RC_CTL_EI_MODE(1) |
5073 GEN6_RC_CTL_HW_ENABLE);
5074
dd75fdc8
CW		 5075 /* Power down if completely idle for over 50ms */
5076 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5077 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5078
42c0526c 5079 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5080 if (ret)
42c0526c 5081 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5082
5083 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5084 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5085 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5086 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5087 (pcu_mbox & 0xff) * 50);
b39fb297 5088 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5089 }
5090
dd75fdc8 5091 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5092 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5093
31643d54
BW		 5094 rc6vids = 0;
5095 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5096 if (IS_GEN6(dev) && ret) {
5097 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5098 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5099 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5100 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5101 rc6vids &= 0xffff00;
5102 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5103 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5104 if (ret)
5105 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5106 }
5107
59bad947 5108 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5109}
5110
c2bc2fc5 5111static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5112{
79f5b2c7 5113 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5114 int min_freq = 15;
3ebecd07
CW		 5115 unsigned int gpu_freq;
5116 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5117 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5118 int scaling_factor = 180;
eda79642 5119 struct cpufreq_policy *policy;
2b4e57bd 5120
4fc688ce 5121 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5122
eda79642
BW		 5123 policy = cpufreq_cpu_get(0);
5124 if (policy) {
5125 max_ia_freq = policy->cpuinfo.max_freq;
5126 cpufreq_cpu_put(policy);
5127 } else {
5128 /*
5129 * Default to measured freq if none found, PCU will ensure we
5130 * don't go over
5131 */
2b4e57bd 5132 max_ia_freq = tsc_khz;
eda79642 5133 }
2b4e57bd
ED		 5134
5135 /* Convert from kHz to MHz */
5136 max_ia_freq /= 1000;
5137
153b4b95 5138 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5139 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5140 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5141
4c8c7743
AG		 5142 if (IS_SKYLAKE(dev)) {
5143 /* Convert GT frequency to 50 HZ units */
5144 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5145 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5146 } else {
5147 min_gpu_freq = dev_priv->rps.min_freq;
5148 max_gpu_freq = dev_priv->rps.max_freq;
5149 }
5150
2b4e57bd
ED		 5151 /*
5152 * For each potential GPU frequency, load a ring frequency we'd like
5153 * to use for memory access. We do this by specifying the IA frequency
5154 * the PCU should use as a reference to determine the ring frequency.
5155 */
4c8c7743
AG		 5156 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5157 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5158 unsigned int ia_freq = 0, ring_freq = 0;
5159
4c8c7743
AG		 5160 if (IS_SKYLAKE(dev)) {
5161 /*
5162 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5163 * No floor required for ring frequency on SKL.
5164 */
5165 ring_freq = gpu_freq;
5166 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5167 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5168 ring_freq = max(min_ring_freq, gpu_freq);
5169 } else if (IS_HASWELL(dev)) {
f6aca45c 5170 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5171 ring_freq = max(min_ring_freq, ring_freq);
5172 /* leave ia_freq as the default, chosen by cpufreq */
5173 } else {
5174 /* On older processors, there is no separate ring
5175 * clock domain, so in order to boost the bandwidth
5176 * of the ring, we need to upclock the CPU (ia_freq).
5177 *
5178 * For GPU frequencies less than 750MHz,
5179 * just use the lowest ring freq.
5180 */
5181 if (gpu_freq < min_freq)
5182 ia_freq = 800;
5183 else
5184 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5185 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5186 }
2b4e57bd 5187
42c0526c
BW		 5188 sandybridge_pcode_write(dev_priv,
5189 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5190 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5191 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5192 gpu_freq);
2b4e57bd 5193 }
2b4e57bd
ED		 5194}
5195
c2bc2fc5
ID		 5196void gen6_update_ring_freq(struct drm_device *dev)
5197{
5198 struct drm_i915_private *dev_priv = dev->dev_private;
5199
97d3308a 5200 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5201 return;
5202
5203 mutex_lock(&dev_priv->rps.hw_lock);
5204 __gen6_update_ring_freq(dev);
5205 mutex_unlock(&dev_priv->rps.hw_lock);
5206}
5207
03af2045 5208static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5209{
095acd5f 5210 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5211 u32 val, rp0;
5212
095acd5f
D		 5213 if (dev->pdev->revision >= 0x20) {
5214 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5215
095acd5f
D		 5216 switch (INTEL_INFO(dev)->eu_total) {
5217 case 8:
5218 /* (2 * 4) config */
5219 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5220 break;
5221 case 12:
5222 /* (2 * 6) config */
5223 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5224 break;
5225 case 16:
5226 /* (2 * 8) config */
5227 default:
5228 /* Setting (2 * 8) Min RP0 for any other combination */
5229 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5230 break;
5231 }
5232 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5233 } else {
5234 /* For pre-production hardware */
5235 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5236 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5237 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5238 }
2b6b3a09
D		 5239 return rp0;
5240}
5241
5242static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5243{
5244 u32 val, rpe;
5245
5246 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5247 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5248
5249 return rpe;
5250}
5251
7707df4a
D		 5252static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5253{
095acd5f 5254 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5255 u32 val, rp1;
5256
095acd5f
D		 5257 if (dev->pdev->revision >= 0x20) {
5258 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5259 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5260 } else {
5261 /* For pre-production hardware */
5262 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5263 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5264 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5265 }
7707df4a
D		 5266 return rp1;
5267}
5268
f8f2b001
D		 5269static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5270{
5271 u32 val, rp1;
5272
5273 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5274
5275 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5276
5277 return rp1;
5278}
5279
03af2045 5280static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5281{
5282 u32 val, rp0;
5283
64936258 5284 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5285
5286 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5287 /* Clamp to max */
5288 rp0 = min_t(u32, rp0, 0xea);
5289
5290 return rp0;
5291}
5292
5293static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5294{
5295 u32 val, rpe;
5296
64936258 5297 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5298 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5299 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5300 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5301
5302 return rpe;
5303}
5304
03af2045 5305static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5306{
64936258 5307 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5308}
5309
ae48434c
ID		 5310/* Check that the pctx buffer wasn't move under us. */
5311static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5312{
5313 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5314
5315 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5316 dev_priv->vlv_pctx->stolen->start);
5317}
5318
38807746
D		 5319
5320/* Check that the pcbr address is not empty. */
5321static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5322{
5323 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5324
5325 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5326}
5327
5328static void cherryview_setup_pctx(struct drm_device *dev)
5329{
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 unsigned long pctx_paddr, paddr;
5332 struct i915_gtt *gtt = &dev_priv->gtt;
5333 u32 pcbr;
5334 int pctx_size = 32*1024;
5335
5336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5337
5338 pcbr = I915_READ(VLV_PCBR);
5339 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5340 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5341 paddr = (dev_priv->mm.stolen_base +
5342 (gtt->stolen_size - pctx_size));
5343
5344 pctx_paddr = (paddr & (~4095));
5345 I915_WRITE(VLV_PCBR, pctx_paddr);
5346 }
ce611ef8
VS		 5347
5348 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5349}
5350
c9cddffc
JB		 5351static void valleyview_setup_pctx(struct drm_device *dev)
5352{
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 struct drm_i915_gem_object *pctx;
5355 unsigned long pctx_paddr;
5356 u32 pcbr;
5357 int pctx_size = 24*1024;
5358
17b0c1f7
ID		 5359 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5360
c9cddffc
JB		 5361 pcbr = I915_READ(VLV_PCBR);
5362 if (pcbr) {
5363 /* BIOS set it up already, grab the pre-alloc'd space */
5364 int pcbr_offset;
5365
5366 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5367 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5368 pcbr_offset,
190d6cd5 5369 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5370 pctx_size);
5371 goto out;
5372 }
5373
ce611ef8
VS		 5374 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5375
c9cddffc
JB		 5376 /*
5377 * From the Gunit register HAS:
5378 * The Gfx driver is expected to program this register and ensure
5379 * proper allocation within Gfx stolen memory. For example, this
5380 * register should be programmed such than the PCBR range does not
5381 * overlap with other ranges, such as the frame buffer, protected
5382 * memory, or any other relevant ranges.
5383 */
5384 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5385 if (!pctx) {
5386 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5387 return;
5388 }
5389
5390 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5391 I915_WRITE(VLV_PCBR, pctx_paddr);
5392
5393out:
ce611ef8 5394 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5395 dev_priv->vlv_pctx = pctx;
5396}
5397
ae48434c
ID		 5398static void valleyview_cleanup_pctx(struct drm_device *dev)
5399{
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401
5402 if (WARN_ON(!dev_priv->vlv_pctx))
5403 return;
5404
5405 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5406 dev_priv->vlv_pctx = NULL;
5407}
5408
4e80519e
ID		 5409static void valleyview_init_gt_powersave(struct drm_device *dev)
5410{
5411 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5412 u32 val;
4e80519e
ID		 5413
5414 valleyview_setup_pctx(dev);
5415
5416 mutex_lock(&dev_priv->rps.hw_lock);
5417
2bb25c17
VS		 5418 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5419 switch ((val >> 6) & 3) {
5420 case 0:
5421 case 1:
5422 dev_priv->mem_freq = 800;
5423 break;
5424 case 2:
5425 dev_priv->mem_freq = 1066;
5426 break;
5427 case 3:
5428 dev_priv->mem_freq = 1333;
5429 break;
5430 }
80b83b62 5431 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5432
4e80519e
ID		 5433 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5434 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5435 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5436 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5437 dev_priv->rps.max_freq);
5438
5439 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5440 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5441 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5442 dev_priv->rps.efficient_freq);
5443
f8f2b001
D		 5444 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5445 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5446 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5447 dev_priv->rps.rp1_freq);
5448
4e80519e
ID		 5449 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5450 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5451 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5452 dev_priv->rps.min_freq);
5453
aed242ff
CW		 5454 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5455
4e80519e
ID		 5456 /* Preserve min/max settings in case of re-init */
5457 if (dev_priv->rps.max_freq_softlimit == 0)
5458 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5459
5460 if (dev_priv->rps.min_freq_softlimit == 0)
5461 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5462
5463 mutex_unlock(&dev_priv->rps.hw_lock);
5464}
5465
38807746
D		 5466static void cherryview_init_gt_powersave(struct drm_device *dev)
5467{
2b6b3a09 5468 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5469 u32 val;
2b6b3a09 5470
38807746 5471 cherryview_setup_pctx(dev);
2b6b3a09
D		 5472
5473 mutex_lock(&dev_priv->rps.hw_lock);
5474
a580516d 5475 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5476 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5477 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5478
2bb25c17
VS		 5479 switch ((val >> 2) & 0x7) {
5480 case 0:
5481 case 1:
5482 dev_priv->rps.cz_freq = 200;
5483 dev_priv->mem_freq = 1600;
5484 break;
5485 case 2:
5486 dev_priv->rps.cz_freq = 267;
5487 dev_priv->mem_freq = 1600;
5488 break;
5489 case 3:
5490 dev_priv->rps.cz_freq = 333;
5491 dev_priv->mem_freq = 2000;
5492 break;
5493 case 4:
5494 dev_priv->rps.cz_freq = 320;
5495 dev_priv->mem_freq = 1600;
5496 break;
5497 case 5:
5498 dev_priv->rps.cz_freq = 400;
5499 dev_priv->mem_freq = 1600;
5500 break;
5501 }
80b83b62 5502 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5503
2b6b3a09
D		 5504 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5505 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5506 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5507 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5508 dev_priv->rps.max_freq);
5509
5510 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5511 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5512 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5513 dev_priv->rps.efficient_freq);
5514
7707df4a
D		 5515 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5516 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5517 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5518 dev_priv->rps.rp1_freq);
5519
5b7c91b7
D		 5520 /* PUnit validated range is only [RPe, RP0] */
5521 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5522 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5523 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5524 dev_priv->rps.min_freq);
5525
1c14762d
VS		 5526 WARN_ONCE((dev_priv->rps.max_freq |
5527 dev_priv->rps.efficient_freq |
5528 dev_priv->rps.rp1_freq |
5529 dev_priv->rps.min_freq) & 1,
5530 "Odd GPU freq values\n");
5531
aed242ff
CW		 5532 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5533
2b6b3a09
D		 5534 /* Preserve min/max settings in case of re-init */
5535 if (dev_priv->rps.max_freq_softlimit == 0)
5536 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5537
5538 if (dev_priv->rps.min_freq_softlimit == 0)
5539 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5540
5541 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5542}
5543
4e80519e
ID		 5544static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5545{
5546 valleyview_cleanup_pctx(dev);
5547}
5548
38807746
D		 5549static void cherryview_enable_rps(struct drm_device *dev)
5550{
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552 struct intel_engine_cs *ring;
2b6b3a09 5553 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5554 int i;
5555
5556 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5557
5558 gtfifodbg = I915_READ(GTFIFODBG);
5559 if (gtfifodbg) {
5560 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5561 gtfifodbg);
5562 I915_WRITE(GTFIFODBG, gtfifodbg);
5563 }
5564
5565 cherryview_check_pctx(dev_priv);
5566
5567 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5568 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5569 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5570
160614a2
VS		 5571 /* Disable RC states. */
5572 I915_WRITE(GEN6_RC_CONTROL, 0);
5573
38807746
D		 5574 /* 2a: Program RC6 thresholds.*/
5575 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5576 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5577 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5578
5579 for_each_ring(ring, dev_priv, i)
5580 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5581 I915_WRITE(GEN6_RC_SLEEP, 0);
5582
f4f71c7d
D		 5583 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5584 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5585
5586 /* allows RC6 residency counter to work */
5587 I915_WRITE(VLV_COUNTER_CONTROL,
5588 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5589 VLV_MEDIA_RC6_COUNT_EN |
5590 VLV_RENDER_RC6_COUNT_EN));
5591
5592 /* For now we assume BIOS is allocating and populating the PCBR */
5593 pcbr = I915_READ(VLV_PCBR);
5594
38807746
D		 5595 /* 3: Enable RC6 */
5596 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5597 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5598 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5599
5600 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5601
2b6b3a09 5602 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5603 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5604 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5605 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5606 I915_WRITE(GEN6_RP_UP_EI, 66000);
5607 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5608
5609 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5610
5611 /* 5: Enable RPS */
5612 I915_WRITE(GEN6_RP_CONTROL,
5613 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5614 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5615 GEN6_RP_ENABLE |
5616 GEN6_RP_UP_BUSY_AVG |
5617 GEN6_RP_DOWN_IDLE_AVG);
5618
3ef62342
D		 5619 /* Setting Fixed Bias */
5620 val = VLV_OVERRIDE_EN |
5621 VLV_SOC_TDP_EN |
5622 CHV_BIAS_CPU_50_SOC_50;
5623 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5624
2b6b3a09
D		 5625 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5626
8d40c3ae
VS		 5627 /* RPS code assumes GPLL is used */
5628 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5629
742f491d 5630 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5631 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5632
5633 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5634 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5635 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5636 dev_priv->rps.cur_freq);
5637
5638 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5639 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5640 dev_priv->rps.efficient_freq);
5641
5642 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5643
59bad947 5644 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5645}
5646
0a073b84
JB		 5647static void valleyview_enable_rps(struct drm_device *dev)
5648{
5649 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5650 struct intel_engine_cs *ring;
2a5913a8 5651 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5652 int i;
5653
5654 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5655
ae48434c
ID		 5656 valleyview_check_pctx(dev_priv);
5657
0a073b84 5658 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5659 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5660 gtfifodbg);
0a073b84
JB		 5661 I915_WRITE(GTFIFODBG, gtfifodbg);
5662 }
5663
c8d9a590 5664 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5665 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5666
160614a2
VS		 5667 /* Disable RC states. */
5668 I915_WRITE(GEN6_RC_CONTROL, 0);
5669
cad725fe 5670 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5671 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5672 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5673 I915_WRITE(GEN6_RP_UP_EI, 66000);
5674 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5675
5676 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5677
5678 I915_WRITE(GEN6_RP_CONTROL,
5679 GEN6_RP_MEDIA_TURBO |
5680 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5681 GEN6_RP_MEDIA_IS_GFX |
5682 GEN6_RP_ENABLE |
5683 GEN6_RP_UP_BUSY_AVG |
5684 GEN6_RP_DOWN_IDLE_CONT);
5685
5686 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5687 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5688 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5689
5690 for_each_ring(ring, dev_priv, i)
5691 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5692
2f0aa304 5693 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5694
5695 /* allows RC6 residency counter to work */
49798eb2 5696 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5697 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5698 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5699 VLV_MEDIA_RC6_COUNT_EN |
5700 VLV_RENDER_RC6_COUNT_EN));
31685c25 5701
a2b23fe0 5702 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5703 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5704
5705 intel_print_rc6_info(dev, rc6_mode);
5706
a2b23fe0 5707 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5708
3ef62342
D		 5709 /* Setting Fixed Bias */
5710 val = VLV_OVERRIDE_EN |
5711 VLV_SOC_TDP_EN |
5712 VLV_BIAS_CPU_125_SOC_875;
5713 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5714
64936258 5715 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5716
8d40c3ae
VS		 5717 /* RPS code assumes GPLL is used */
5718 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5719
742f491d 5720 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5721 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5722
b39fb297 5723 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5724 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5725 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5726 dev_priv->rps.cur_freq);
0a073b84 5727
73008b98 5728 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5729 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5730 dev_priv->rps.efficient_freq);
0a073b84 5731
b39fb297 5732 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5733
59bad947 5734 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5735}
5736
dde18883
ED		 5737static unsigned long intel_pxfreq(u32 vidfreq)
5738{
5739 unsigned long freq;
5740 int div = (vidfreq & 0x3f0000) >> 16;
5741 int post = (vidfreq & 0x3000) >> 12;
5742 int pre = (vidfreq & 0x7);
5743
5744 if (!pre)
5745 return 0;
5746
5747 freq = ((div * 133333) / ((1<<post) * pre));
5748
5749 return freq;
5750}
5751
eb48eb00
DV		 5752static const struct cparams {
5753 u16 i;
5754 u16 t;
5755 u16 m;
5756 u16 c;
5757} cparams[] = {
5758 { 1, 1333, 301, 28664 },
5759 { 1, 1066, 294, 24460 },
5760 { 1, 800, 294, 25192 },
5761 { 0, 1333, 276, 27605 },
5762 { 0, 1066, 276, 27605 },
5763 { 0, 800, 231, 23784 },
5764};
5765
f531dcb2 5766static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5767{
5768 u64 total_count, diff, ret;
5769 u32 count1, count2, count3, m = 0, c = 0;
5770 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5771 int i;
5772
02d71956
DV		 5773 assert_spin_locked(&mchdev_lock);
5774
20e4d407 5775 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5776
5777 /* Prevent division-by-zero if we are asking too fast.
5778 * Also, we don't get interesting results if we are polling
5779 * faster than once in 10ms, so just return the saved value
5780 * in such cases.
5781 */
5782 if (diff1 <= 10)
20e4d407 5783 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5784
5785 count1 = I915_READ(DMIEC);
5786 count2 = I915_READ(DDREC);
5787 count3 = I915_READ(CSIEC);
5788
5789 total_count = count1 + count2 + count3;
5790
5791 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5792 if (total_count < dev_priv->ips.last_count1) {
5793 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5794 diff += total_count;
5795 } else {
20e4d407 5796 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5797 }
5798
5799 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5800 if (cparams[i].i == dev_priv->ips.c_m &&
5801 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5802 m = cparams[i].m;
5803 c = cparams[i].c;
5804 break;
5805 }
5806 }
5807
5808 diff = div_u64(diff, diff1);
5809 ret = ((m * diff) + c);
5810 ret = div_u64(ret, 10);
5811
20e4d407
DV		 5812 dev_priv->ips.last_count1 = total_count;
5813 dev_priv->ips.last_time1 = now;
eb48eb00 5814
20e4d407 5815 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5816
5817 return ret;
5818}
5819
f531dcb2
CW		 5820unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5821{
3d13ef2e 5822 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5823 unsigned long val;
5824
3d13ef2e 5825 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5826 return 0;
5827
5828 spin_lock_irq(&mchdev_lock);
5829
5830 val = __i915_chipset_val(dev_priv);
5831
5832 spin_unlock_irq(&mchdev_lock);
5833
5834 return val;
5835}
5836
eb48eb00
DV		 5837unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5838{
5839 unsigned long m, x, b;
5840 u32 tsfs;
5841
5842 tsfs = I915_READ(TSFS);
5843
5844 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5845 x = I915_READ8(TR1);
5846
5847 b = tsfs & TSFS_INTR_MASK;
5848
5849 return ((m * x) / 127) - b;
5850}
5851
d972d6ee
MK		 5852static int _pxvid_to_vd(u8 pxvid)
5853{
5854 if (pxvid == 0)
5855 return 0;
5856
5857 if (pxvid >= 8 && pxvid < 31)
5858 pxvid = 31;
5859
5860 return (pxvid + 2) * 125;
5861}
5862
5863static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5864{
3d13ef2e 5865 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5866 const int vd = _pxvid_to_vd(pxvid);
5867 const int vm = vd - 1125;
5868
3d13ef2e 5869 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5870 return vm > 0 ? vm : 0;
5871
5872 return vd;
eb48eb00
DV		 5873}
5874
02d71956 5875static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5876{
5ed0bdf2 5877 u64 now, diff, diffms;
eb48eb00
DV		 5878 u32 count;
5879
02d71956 5880 assert_spin_locked(&mchdev_lock);
eb48eb00 5881
5ed0bdf2
TG		 5882 now = ktime_get_raw_ns();
5883 diffms = now - dev_priv->ips.last_time2;
5884 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5885
5886 /* Don't divide by 0 */
eb48eb00
DV		 5887 if (!diffms)
5888 return;
5889
5890 count = I915_READ(GFXEC);
5891
20e4d407
DV		 5892 if (count < dev_priv->ips.last_count2) {
5893 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5894 diff += count;
5895 } else {
20e4d407 5896 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5897 }
5898
20e4d407
DV		 5899 dev_priv->ips.last_count2 = count;
5900 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5901
5902 /* More magic constants... */
5903 diff = diff * 1181;
5904 diff = div_u64(diff, diffms * 10);
20e4d407 5905 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5906}
5907
02d71956
DV		 5908void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5909{
3d13ef2e
DL		 5910 struct drm_device *dev = dev_priv->dev;
5911
5912 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5913 return;
5914
9270388e 5915 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5916
5917 __i915_update_gfx_val(dev_priv);
5918
9270388e 5919 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5920}
5921
f531dcb2 5922static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5923{
5924 unsigned long t, corr, state1, corr2, state2;
5925 u32 pxvid, ext_v;
5926
02d71956
DV		 5927 assert_spin_locked(&mchdev_lock);
5928
616847e7 5929 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5930 pxvid = (pxvid >> 24) & 0x7f;
5931 ext_v = pvid_to_extvid(dev_priv, pxvid);
5932
5933 state1 = ext_v;
5934
5935 t = i915_mch_val(dev_priv);
5936
5937 /* Revel in the empirically derived constants */
5938
5939 /* Correction factor in 1/100000 units */
5940 if (t > 80)
5941 corr = ((t * 2349) + 135940);
5942 else if (t >= 50)
5943 corr = ((t * 964) + 29317);
5944 else /* < 50 */
5945 corr = ((t * 301) + 1004);
5946
5947 corr = corr * ((150142 * state1) / 10000 - 78642);
5948 corr /= 100000;
20e4d407 5949 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5950
5951 state2 = (corr2 * state1) / 10000;
5952 state2 /= 100; /* convert to mW */
5953
02d71956 5954 __i915_update_gfx_val(dev_priv);
eb48eb00 5955
20e4d407 5956 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5957}
5958
f531dcb2
CW		 5959unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5960{
3d13ef2e 5961 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5962 unsigned long val;
5963
3d13ef2e 5964 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5965 return 0;
5966
5967 spin_lock_irq(&mchdev_lock);
5968
5969 val = __i915_gfx_val(dev_priv);
5970
5971 spin_unlock_irq(&mchdev_lock);
5972
5973 return val;
5974}
5975
eb48eb00
DV		 5976/**
5977 * i915_read_mch_val - return value for IPS use
5978 *
5979 * Calculate and return a value for the IPS driver to use when deciding whether
5980 * we have thermal and power headroom to increase CPU or GPU power budget.
5981 */
5982unsigned long i915_read_mch_val(void)
5983{
5984 struct drm_i915_private *dev_priv;
5985 unsigned long chipset_val, graphics_val, ret = 0;
5986
9270388e 5987 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5988 if (!i915_mch_dev)
5989 goto out_unlock;
5990 dev_priv = i915_mch_dev;
5991
f531dcb2
CW		 5992 chipset_val = __i915_chipset_val(dev_priv);
5993 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5994
5995 ret = chipset_val + graphics_val;
5996
5997out_unlock:
9270388e 5998 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5999
6000 return ret;
6001}
6002EXPORT_SYMBOL_GPL(i915_read_mch_val);
6003
6004/**
6005 * i915_gpu_raise - raise GPU frequency limit
6006 *
6007 * Raise the limit; IPS indicates we have thermal headroom.
6008 */
6009bool i915_gpu_raise(void)
6010{
6011 struct drm_i915_private *dev_priv;
6012 bool ret = true;
6013
9270388e 6014 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6015 if (!i915_mch_dev) {
6016 ret = false;
6017 goto out_unlock;
6018 }
6019 dev_priv = i915_mch_dev;
6020
20e4d407
DV		 6021 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6022 dev_priv->ips.max_delay--;
eb48eb00
DV		 6023
6024out_unlock:
9270388e 6025 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6026
6027 return ret;
6028}
6029EXPORT_SYMBOL_GPL(i915_gpu_raise);
6030
6031/**
6032 * i915_gpu_lower - lower GPU frequency limit
6033 *
6034 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6035 * frequency maximum.
6036 */
6037bool i915_gpu_lower(void)
6038{
6039 struct drm_i915_private *dev_priv;
6040 bool ret = true;
6041
9270388e 6042 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6043 if (!i915_mch_dev) {
6044 ret = false;
6045 goto out_unlock;
6046 }
6047 dev_priv = i915_mch_dev;
6048
20e4d407
DV		 6049 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6050 dev_priv->ips.max_delay++;
eb48eb00
DV		 6051
6052out_unlock:
9270388e 6053 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6054
6055 return ret;
6056}
6057EXPORT_SYMBOL_GPL(i915_gpu_lower);
6058
6059/**
6060 * i915_gpu_busy - indicate GPU business to IPS
6061 *
6062 * Tell the IPS driver whether or not the GPU is busy.
6063 */
6064bool i915_gpu_busy(void)
6065{
6066 struct drm_i915_private *dev_priv;
a4872ba6 6067 struct intel_engine_cs *ring;
eb48eb00 6068 bool ret = false;
f047e395 6069 int i;
eb48eb00 6070
9270388e 6071 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6072 if (!i915_mch_dev)
6073 goto out_unlock;
6074 dev_priv = i915_mch_dev;
6075
f047e395
CW		 6076 for_each_ring(ring, dev_priv, i)
6077 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 6078
6079out_unlock:
9270388e 6080 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6081
6082 return ret;
6083}
6084EXPORT_SYMBOL_GPL(i915_gpu_busy);
6085
6086/**
6087 * i915_gpu_turbo_disable - disable graphics turbo
6088 *
6089 * Disable graphics turbo by resetting the max frequency and setting the
6090 * current frequency to the default.
6091 */
6092bool i915_gpu_turbo_disable(void)
6093{
6094 struct drm_i915_private *dev_priv;
6095 bool ret = true;
6096
9270388e 6097 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6098 if (!i915_mch_dev) {
6099 ret = false;
6100 goto out_unlock;
6101 }
6102 dev_priv = i915_mch_dev;
6103
20e4d407 6104 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6105
20e4d407 6106 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6107 ret = false;
6108
6109out_unlock:
9270388e 6110 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6111
6112 return ret;
6113}
6114EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6115
6116/**
6117 * Tells the intel_ips driver that the i915 driver is now loaded, if
6118 * IPS got loaded first.
6119 *
6120 * This awkward dance is so that neither module has to depend on the
6121 * other in order for IPS to do the appropriate communication of
6122 * GPU turbo limits to i915.
6123 */
6124static void
6125ips_ping_for_i915_load(void)
6126{
6127 void (*link)(void);
6128
6129 link = symbol_get(ips_link_to_i915_driver);
6130 if (link) {
6131 link();
6132 symbol_put(ips_link_to_i915_driver);
6133 }
6134}
6135
6136void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6137{
02d71956
DV		 6138 /* We only register the i915 ips part with intel-ips once everything is
6139 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6140 spin_lock_irq(&mchdev_lock);
eb48eb00 6141 i915_mch_dev = dev_priv;
9270388e 6142 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6143
6144 ips_ping_for_i915_load();
6145}
6146
6147void intel_gpu_ips_teardown(void)
6148{
9270388e 6149 spin_lock_irq(&mchdev_lock);
eb48eb00 6150 i915_mch_dev = NULL;
9270388e 6151 spin_unlock_irq(&mchdev_lock);
eb48eb00 6152}
76c3552f 6153
8090c6b9 6154static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6155{
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157 u32 lcfuse;
6158 u8 pxw[16];
6159 int i;
6160
6161 /* Disable to program */
6162 I915_WRITE(ECR, 0);
6163 POSTING_READ(ECR);
6164
6165 /* Program energy weights for various events */
6166 I915_WRITE(SDEW, 0x15040d00);
6167 I915_WRITE(CSIEW0, 0x007f0000);
6168 I915_WRITE(CSIEW1, 0x1e220004);
6169 I915_WRITE(CSIEW2, 0x04000004);
6170
6171 for (i = 0; i < 5; i++)
616847e7 6172 I915_WRITE(PEW(i), 0);
dde18883 6173 for (i = 0; i < 3; i++)
616847e7 6174 I915_WRITE(DEW(i), 0);
dde18883
ED		 6175
6176 /* Program P-state weights to account for frequency power adjustment */
6177 for (i = 0; i < 16; i++) {
616847e7 6178 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6179 unsigned long freq = intel_pxfreq(pxvidfreq);
6180 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6181 PXVFREQ_PX_SHIFT;
6182 unsigned long val;
6183
6184 val = vid * vid;
6185 val *= (freq / 1000);
6186 val *= 255;
6187 val /= (127*127*900);
6188 if (val > 0xff)
6189 DRM_ERROR("bad pxval: %ld\n", val);
6190 pxw[i] = val;
6191 }
6192 /* Render standby states get 0 weight */
6193 pxw[14] = 0;
6194 pxw[15] = 0;
6195
6196 for (i = 0; i < 4; i++) {
6197 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6198 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6199 I915_WRITE(PXW(i), val);
dde18883
ED		 6200 }
6201
6202 /* Adjust magic regs to magic values (more experimental results) */
6203 I915_WRITE(OGW0, 0);
6204 I915_WRITE(OGW1, 0);
6205 I915_WRITE(EG0, 0x00007f00);
6206 I915_WRITE(EG1, 0x0000000e);
6207 I915_WRITE(EG2, 0x000e0000);
6208 I915_WRITE(EG3, 0x68000300);
6209 I915_WRITE(EG4, 0x42000000);
6210 I915_WRITE(EG5, 0x00140031);
6211 I915_WRITE(EG6, 0);
6212 I915_WRITE(EG7, 0);
6213
6214 for (i = 0; i < 8; i++)
616847e7 6215 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6216
6217 /* Enable PMON + select events */
6218 I915_WRITE(ECR, 0x80000019);
6219
6220 lcfuse = I915_READ(LCFUSE02);
6221
20e4d407 6222 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6223}
6224
ae48434c
ID		 6225void intel_init_gt_powersave(struct drm_device *dev)
6226{
e6069ca8
ID		 6227 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6228
38807746
D		 6229 if (IS_CHERRYVIEW(dev))
6230 cherryview_init_gt_powersave(dev);
6231 else if (IS_VALLEYVIEW(dev))
4e80519e 6232 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6233}
6234
6235void intel_cleanup_gt_powersave(struct drm_device *dev)
6236{
38807746
D		 6237 if (IS_CHERRYVIEW(dev))
6238 return;
6239 else if (IS_VALLEYVIEW(dev))
4e80519e 6240 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6241}
6242
dbea3cea
ID		 6243static void gen6_suspend_rps(struct drm_device *dev)
6244{
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246
6247 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6248
4c2a8897 6249 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6250}
6251
156c7ca0
JB		 6252/**
6253 * intel_suspend_gt_powersave - suspend PM work and helper threads
6254 * @dev: drm device
6255 *
6256 * We don't want to disable RC6 or other features here, we just want
6257 * to make sure any work we've queued has finished and won't bother
6258 * us while we're suspended.
6259 */
6260void intel_suspend_gt_powersave(struct drm_device *dev)
6261{
6262 struct drm_i915_private *dev_priv = dev->dev_private;
6263
d4d70aa5
ID		 6264 if (INTEL_INFO(dev)->gen < 6)
6265 return;
6266
dbea3cea 6267 gen6_suspend_rps(dev);
b47adc17
D		 6268
6269 /* Force GPU to min freq during suspend */
6270 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6271}
6272
8090c6b9
DV		 6273void intel_disable_gt_powersave(struct drm_device *dev)
6274{
1a01ab3b
JB		 6275 struct drm_i915_private *dev_priv = dev->dev_private;
6276
930ebb46 6277 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6278 ironlake_disable_drps(dev);
38807746 6279 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6280 intel_suspend_gt_powersave(dev);
e494837a 6281
4fc688ce 6282 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6283 if (INTEL_INFO(dev)->gen >= 9)
6284 gen9_disable_rps(dev);
6285 else if (IS_CHERRYVIEW(dev))
38807746
D		 6286 cherryview_disable_rps(dev);
6287 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6288 valleyview_disable_rps(dev);
6289 else
6290 gen6_disable_rps(dev);
e534770a 6291
c0951f0c 6292 dev_priv->rps.enabled = false;
4fc688ce 6293 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6294 }
8090c6b9
DV		 6295}
6296
1a01ab3b
JB		 6297static void intel_gen6_powersave_work(struct work_struct *work)
6298{
6299 struct drm_i915_private *dev_priv =
6300 container_of(work, struct drm_i915_private,
6301 rps.delayed_resume_work.work);
6302 struct drm_device *dev = dev_priv->dev;
6303
4fc688ce 6304 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6305
4c2a8897 6306 gen6_reset_rps_interrupts(dev);
3cc134e3 6307
38807746
D		 6308 if (IS_CHERRYVIEW(dev)) {
6309 cherryview_enable_rps(dev);
6310 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6311 valleyview_enable_rps(dev);
20e49366 6312 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6313 gen9_enable_rc6(dev);
20e49366 6314 gen9_enable_rps(dev);
cc017fb4
AG		 6315 if (IS_SKYLAKE(dev))
6316 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6317 } else if (IS_BROADWELL(dev)) {
6318 gen8_enable_rps(dev);
c2bc2fc5 6319 __gen6_update_ring_freq(dev);
0a073b84
JB		 6320 } else {
6321 gen6_enable_rps(dev);
c2bc2fc5 6322 __gen6_update_ring_freq(dev);
0a073b84 6323 }
aed242ff
CW		 6324
6325 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6326 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6327
6328 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6329 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6330
c0951f0c 6331 dev_priv->rps.enabled = true;
3cc134e3 6332
4c2a8897 6333 gen6_enable_rps_interrupts(dev);
3cc134e3 6334
4fc688ce 6335 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6336
6337 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6338}
6339
8090c6b9
DV		 6340void intel_enable_gt_powersave(struct drm_device *dev)
6341{
1a01ab3b
JB		 6342 struct drm_i915_private *dev_priv = dev->dev_private;
6343
f61018b1
YZ		 6344 /* Powersaving is controlled by the host when inside a VM */
6345 if (intel_vgpu_active(dev))
6346 return;
6347
8090c6b9 6348 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6349 mutex_lock(&dev->struct_mutex);
8090c6b9 6350 ironlake_enable_drps(dev);
8090c6b9 6351 intel_init_emon(dev);
dc1d0136 6352 mutex_unlock(&dev->struct_mutex);
38807746 6353 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6354 /*
6355 * PCU communication is slow and this doesn't need to be
6356 * done at any specific time, so do this out of our fast path
6357 * to make resume and init faster.
c6df39b5
ID		 6358 *
6359 * We depend on the HW RC6 power context save/restore
6360 * mechanism when entering D3 through runtime PM suspend. So
6361 * disable RPM until RPS/RC6 is properly setup. We can only
6362 * get here via the driver load/system resume/runtime resume
6363 * paths, so the _noresume version is enough (and in case of
6364 * runtime resume it's necessary).
1a01ab3b 6365 */
c6df39b5
ID		 6366 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6367 round_jiffies_up_relative(HZ)))
6368 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6369 }
6370}
6371
c6df39b5
ID		 6372void intel_reset_gt_powersave(struct drm_device *dev)
6373{
6374 struct drm_i915_private *dev_priv = dev->dev_private;
6375
dbea3cea
ID		 6376 if (INTEL_INFO(dev)->gen < 6)
6377 return;
6378
6379 gen6_suspend_rps(dev);
c6df39b5 6380 dev_priv->rps.enabled = false;
c6df39b5
ID		 6381}
6382
3107bd48
DV		 6383static void ibx_init_clock_gating(struct drm_device *dev)
6384{
6385 struct drm_i915_private *dev_priv = dev->dev_private;
6386
6387 /*
6388 * On Ibex Peak and Cougar Point, we need to disable clock
6389 * gating for the panel power sequencer or it will fail to
6390 * start up when no ports are active.
6391 */
6392 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6393}
6394
0e088b8f
VS		 6395static void g4x_disable_trickle_feed(struct drm_device *dev)
6396{
6397 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6398 enum pipe pipe;
0e088b8f 6399
055e393f 6400 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6401 I915_WRITE(DSPCNTR(pipe),
6402 I915_READ(DSPCNTR(pipe)) |
6403 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6404
6405 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6406 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6407 }
6408}
6409
017636cc
VS		 6410static void ilk_init_lp_watermarks(struct drm_device *dev)
6411{
6412 struct drm_i915_private *dev_priv = dev->dev_private;
6413
6414 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6415 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6416 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6417
6418 /*
6419 * Don't touch WM1S_LP_EN here.
6420 * Doing so could cause underruns.
6421 */
6422}
6423
1fa61106 6424static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6425{
6426 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6427 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6428
f1e8fa56
DL		 6429 /*
6430 * Required for FBC
6431 * WaFbcDisableDpfcClockGating:ilk
6432 */
4d47e4f5
DL		 6433 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6434 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6435 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6436
6437 I915_WRITE(PCH_3DCGDIS0,
6438 MARIUNIT_CLOCK_GATE_DISABLE |
6439 SVSMUNIT_CLOCK_GATE_DISABLE);
6440 I915_WRITE(PCH_3DCGDIS1,
6441 VFMUNIT_CLOCK_GATE_DISABLE);
6442
6f1d69b0
ED		 6443 /*
6444 * According to the spec the following bits should be set in
6445 * order to enable memory self-refresh
6446 * The bit 22/21 of 0x42004
6447 * The bit 5 of 0x42020
6448 * The bit 15 of 0x45000
6449 */
6450 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6451 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6452 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6453 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6454 I915_WRITE(DISP_ARB_CTL,
6455 (I915_READ(DISP_ARB_CTL) |
6456 DISP_FBC_WM_DIS));
017636cc
VS		 6457
6458 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6459
6460 /*
6461 * Based on the document from hardware guys the following bits
6462 * should be set unconditionally in order to enable FBC.
6463 * The bit 22 of 0x42000
6464 * The bit 22 of 0x42004
6465 * The bit 7,8,9 of 0x42020.
6466 */
6467 if (IS_IRONLAKE_M(dev)) {
4bb35334 6468 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6469 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6470 I915_READ(ILK_DISPLAY_CHICKEN1) |
6471 ILK_FBCQ_DIS);
6472 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6473 I915_READ(ILK_DISPLAY_CHICKEN2) |
6474 ILK_DPARB_GATE);
6f1d69b0
ED		 6475 }
6476
4d47e4f5
DL		 6477 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6478
6f1d69b0
ED		 6479 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6480 I915_READ(ILK_DISPLAY_CHICKEN2) |
6481 ILK_ELPIN_409_SELECT);
6482 I915_WRITE(_3D_CHICKEN2,
6483 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6484 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6485
ecdb4eb7 6486 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6487 I915_WRITE(CACHE_MODE_0,
6488 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6489
4e04632e
AG		 6490 /* WaDisable_RenderCache_OperationalFlush:ilk */
6491 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6492
0e088b8f 6493 g4x_disable_trickle_feed(dev);
bdad2b2f 6494
3107bd48
DV		 6495 ibx_init_clock_gating(dev);
6496}
6497
6498static void cpt_init_clock_gating(struct drm_device *dev)
6499{
6500 struct drm_i915_private *dev_priv = dev->dev_private;
6501 int pipe;
3f704fa2 6502 uint32_t val;
3107bd48
DV		 6503
6504 /*
6505 * On Ibex Peak and Cougar Point, we need to disable clock
6506 * gating for the panel power sequencer or it will fail to
6507 * start up when no ports are active.
6508 */
cd664078
JB		 6509 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6510 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6511 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6512 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6513 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6514 /* The below fixes the weird display corruption, a few pixels shifted
6515 * downward, on (only) LVDS of some HP laptops with IVY.
6516 */
055e393f 6517 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6518 val = I915_READ(TRANS_CHICKEN2(pipe));
6519 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6520 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6521 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6522 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6523 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6524 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6525 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6526 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6527 }
3107bd48 6528 /* WADP0ClockGatingDisable */
055e393f 6529 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6530 I915_WRITE(TRANS_CHICKEN1(pipe),
6531 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6532 }
6f1d69b0
ED		 6533}
6534
1d7aaa0c
DV		 6535static void gen6_check_mch_setup(struct drm_device *dev)
6536{
6537 struct drm_i915_private *dev_priv = dev->dev_private;
6538 uint32_t tmp;
6539
6540 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6541 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6542 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6543 tmp);
1d7aaa0c
DV		 6544}
6545
1fa61106 6546static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6547{
6548 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6549 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6550
231e54f6 6551 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6552
6553 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6554 I915_READ(ILK_DISPLAY_CHICKEN2) |
6555 ILK_ELPIN_409_SELECT);
6556
ecdb4eb7 6557 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6558 I915_WRITE(_3D_CHICKEN,
6559 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6560
4e04632e
AG		 6561 /* WaDisable_RenderCache_OperationalFlush:snb */
6562 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6563
8d85d272
VS		 6564 /*
6565 * BSpec recoomends 8x4 when MSAA is used,
6566 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6567 *
6568 * Note that PS/WM thread counts depend on the WIZ hashing
6569 * disable bit, which we don't touch here, but it's good
6570 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6571 */
6572 I915_WRITE(GEN6_GT_MODE,
98533251 6573 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6574
017636cc 6575 ilk_init_lp_watermarks(dev);
6f1d69b0 6576
6f1d69b0 6577 I915_WRITE(CACHE_MODE_0,
50743298 6578 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6579
6580 I915_WRITE(GEN6_UCGCTL1,
6581 I915_READ(GEN6_UCGCTL1) |
6582 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6583 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6584
6585 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6586 * gating disable must be set. Failure to set it results in
6587 * flickering pixels due to Z write ordering failures after
6588 * some amount of runtime in the Mesa "fire" demo, and Unigine
6589 * Sanctuary and Tropics, and apparently anything else with
6590 * alpha test or pixel discard.
6591 *
6592 * According to the spec, bit 11 (RCCUNIT) must also be set,
6593 * but we didn't debug actual testcases to find it out.
0f846f81 6594 *
ef59318c
VS		 6595 * WaDisableRCCUnitClockGating:snb
6596 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6597 */
6598 I915_WRITE(GEN6_UCGCTL2,
6599 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6600 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6601
5eb146dd 6602 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6603 I915_WRITE(_3D_CHICKEN3,
6604 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6605
e927ecde
VS		 6606 /*
6607 * Bspec says:
6608 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6609 * 3DSTATE_SF number of SF output attributes is more than 16."
6610 */
6611 I915_WRITE(_3D_CHICKEN3,
6612 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6613
6f1d69b0
ED		 6614 /*
6615 * According to the spec the following bits should be
6616 * set in order to enable memory self-refresh and fbc:
6617 * The bit21 and bit22 of 0x42000
6618 * The bit21 and bit22 of 0x42004
6619 * The bit5 and bit7 of 0x42020
6620 * The bit14 of 0x70180
6621 * The bit14 of 0x71180
4bb35334
DL		 6622 *
6623 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6624 */
6625 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6626 I915_READ(ILK_DISPLAY_CHICKEN1) |
6627 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6628 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6629 I915_READ(ILK_DISPLAY_CHICKEN2) |
6630 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6631 I915_WRITE(ILK_DSPCLK_GATE_D,
6632 I915_READ(ILK_DSPCLK_GATE_D) |
6633 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6634 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6635
0e088b8f 6636 g4x_disable_trickle_feed(dev);
f8f2ac9a 6637
3107bd48 6638 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6639
6640 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6641}
6642
6643static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6644{
6645 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6646
3aad9059 6647 /*
46680e0a 6648 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6649 *
6650 * This actually overrides the dispatch
6651 * mode for all thread types.
6652 */
6f1d69b0
ED		 6653 reg &= ~GEN7_FF_SCHED_MASK;
6654 reg |= GEN7_FF_TS_SCHED_HW;
6655 reg |= GEN7_FF_VS_SCHED_HW;
6656 reg |= GEN7_FF_DS_SCHED_HW;
6657
6658 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6659}
6660
17a303ec
PZ		 6661static void lpt_init_clock_gating(struct drm_device *dev)
6662{
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664
6665 /*
6666 * TODO: this bit should only be enabled when really needed, then
6667 * disabled when not needed anymore in order to save power.
6668 */
c2699524 6669 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6670 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6671 I915_READ(SOUTH_DSPCLK_GATE_D) |
6672 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6673
6674 /* WADPOClockGatingDisable:hsw */
6675 I915_WRITE(_TRANSA_CHICKEN1,
6676 I915_READ(_TRANSA_CHICKEN1) |
6677 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6678}
6679
7d708ee4
ID		 6680static void lpt_suspend_hw(struct drm_device *dev)
6681{
6682 struct drm_i915_private *dev_priv = dev->dev_private;
6683
c2699524 6684 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6685 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6686
6687 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6688 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6689 }
6690}
6691
47c2bd97 6692static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6693{
6694 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6695 enum pipe pipe;
4d487cff 6696 uint32_t misccpctl;
1020a5c2 6697
7ad0dbab 6698 ilk_init_lp_watermarks(dev);
50ed5fbd 6699
ab57fff1 6700 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6701 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6702
ab57fff1 6703 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6704 I915_WRITE(CHICKEN_PAR1_1,
6705 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6706
ab57fff1 6707 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6708 for_each_pipe(dev_priv, pipe) {
07d27e20 6709 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6710 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6711 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6712 }
63801f21 6713
ab57fff1
BW		 6714 /* WaVSRefCountFullforceMissDisable:bdw */
6715 /* WaDSRefCountFullforceMissDisable:bdw */
6716 I915_WRITE(GEN7_FF_THREAD_MODE,
6717 I915_READ(GEN7_FF_THREAD_MODE) &
6718 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6719
295e8bb7
VS		 6720 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6721 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6722
6723 /* WaDisableSDEUnitClockGating:bdw */
6724 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6725 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6726
4d487cff
VS		 6727 /*
6728 * WaProgramL3SqcReg1Default:bdw
6729 * WaTempDisableDOPClkGating:bdw
6730 */
6731 misccpctl = I915_READ(GEN7_MISCCPCTL);
6732 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6733 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6734 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6735
6d50b065
VS		 6736 /*
6737 * WaGttCachingOffByDefault:bdw
6738 * GTT cache may not work with big pages, so if those
6739 * are ever enabled GTT cache may need to be disabled.
6740 */
6741 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6742
89d6b2b8 6743 lpt_init_clock_gating(dev);
1020a5c2
BW		 6744}
6745
cad2a2d7
ED		 6746static void haswell_init_clock_gating(struct drm_device *dev)
6747{
6748 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6749
017636cc 6750 ilk_init_lp_watermarks(dev);
cad2a2d7 6751
f3fc4884
FJ		 6752 /* L3 caching of data atomics doesn't work -- disable it. */
6753 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6754 I915_WRITE(HSW_ROW_CHICKEN3,
6755 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6756
ecdb4eb7 6757 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6758 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6759 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6760 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6761
e36ea7ff
VS		 6762 /* WaVSRefCountFullforceMissDisable:hsw */
6763 I915_WRITE(GEN7_FF_THREAD_MODE,
6764 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6765
4e04632e
AG		 6766 /* WaDisable_RenderCache_OperationalFlush:hsw */
6767 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6768
fe27c606
CW		 6769 /* enable HiZ Raw Stall Optimization */
6770 I915_WRITE(CACHE_MODE_0_GEN7,
6771 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6772
ecdb4eb7 6773 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6774 I915_WRITE(CACHE_MODE_1,
6775 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6776
a12c4967
VS		 6777 /*
6778 * BSpec recommends 8x4 when MSAA is used,
6779 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6780 *
6781 * Note that PS/WM thread counts depend on the WIZ hashing
6782 * disable bit, which we don't touch here, but it's good
6783 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6784 */
6785 I915_WRITE(GEN7_GT_MODE,
98533251 6786 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6787
94411593
KG		 6788 /* WaSampleCChickenBitEnable:hsw */
6789 I915_WRITE(HALF_SLICE_CHICKEN3,
6790 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6791
ecdb4eb7 6792 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6793 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6794
90a88643
PZ		 6795 /* WaRsPkgCStateDisplayPMReq:hsw */
6796 I915_WRITE(CHICKEN_PAR1_1,
6797 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6798
17a303ec 6799 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6800}
6801
1fa61106 6802static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6803{
6804 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6805 uint32_t snpcr;
6f1d69b0 6806
017636cc 6807 ilk_init_lp_watermarks(dev);
6f1d69b0 6808
231e54f6 6809 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6810
ecdb4eb7 6811 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6812 I915_WRITE(_3D_CHICKEN3,
6813 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6814
ecdb4eb7 6815 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6816 I915_WRITE(IVB_CHICKEN3,
6817 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6818 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6819
ecdb4eb7 6820 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6821 if (IS_IVB_GT1(dev))
6822 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6823 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6824
4e04632e
AG		 6825 /* WaDisable_RenderCache_OperationalFlush:ivb */
6826 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6827
ecdb4eb7 6828 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6829 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6830 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6831
ecdb4eb7 6832 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6833 I915_WRITE(GEN7_L3CNTLREG1,
6834 GEN7_WA_FOR_GEN7_L3_CONTROL);
6835 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6836 GEN7_WA_L3_CHICKEN_MODE);
6837 if (IS_IVB_GT1(dev))
6838 I915_WRITE(GEN7_ROW_CHICKEN2,
6839 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6840 else {
6841 /* must write both registers */
6842 I915_WRITE(GEN7_ROW_CHICKEN2,
6843 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6844 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6845 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6846 }
6f1d69b0 6847
ecdb4eb7 6848 /* WaForceL3Serialization:ivb */
61939d97
JB		 6849 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6850 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6851
1b80a19a 6852 /*
0f846f81 6853 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6854 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6855 */
6856 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6857 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6858
ecdb4eb7 6859 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6860 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6861 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6862 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6863
0e088b8f 6864 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6865
6866 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6867
22721343
CW		 6868 if (0) { /* causes HiZ corruption on ivb:gt1 */
6869 /* enable HiZ Raw Stall Optimization */
6870 I915_WRITE(CACHE_MODE_0_GEN7,
6871 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6872 }
116f2b6d 6873
ecdb4eb7 6874 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6875 I915_WRITE(CACHE_MODE_1,
6876 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6877
a607c1a4
VS		 6878 /*
6879 * BSpec recommends 8x4 when MSAA is used,
6880 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6881 *
6882 * Note that PS/WM thread counts depend on the WIZ hashing
6883 * disable bit, which we don't touch here, but it's good
6884 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6885 */
6886 I915_WRITE(GEN7_GT_MODE,
98533251 6887 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6888
20848223
BW		 6889 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6890 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6891 snpcr |= GEN6_MBC_SNPCR_MED;
6892 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6893
ab5c608b
BW		 6894 if (!HAS_PCH_NOP(dev))
6895 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6896
6897 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6898}
6899
c6beb13e
VS		 6900static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6901{
6902 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6903
6904 /*
6905 * Disable trickle feed and enable pnd deadline calculation
6906 */
6907 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6908 I915_WRITE(CBR1_VLV, 0);
6909}
6910
1fa61106 6911static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6912{
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6914
c6beb13e 6915 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6916
ecdb4eb7 6917 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6918 I915_WRITE(_3D_CHICKEN3,
6919 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6920
ecdb4eb7 6921 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6922 I915_WRITE(IVB_CHICKEN3,
6923 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6924 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6925
fad7d36e 6926 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6927 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6928 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6929 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6930 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6931
4e04632e
AG		 6932 /* WaDisable_RenderCache_OperationalFlush:vlv */
6933 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6934
ecdb4eb7 6935 /* WaForceL3Serialization:vlv */
61939d97
JB		 6936 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6937 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6938
ecdb4eb7 6939 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6940 I915_WRITE(GEN7_ROW_CHICKEN2,
6941 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6942
ecdb4eb7 6943 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6944 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6945 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6946 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6947
46680e0a
VS		 6948 gen7_setup_fixed_func_scheduler(dev_priv);
6949
3c0edaeb 6950 /*
0f846f81 6951 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6952 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6953 */
6954 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6955 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6956
c98f5062
AG		 6957 /* WaDisableL3Bank2xClockGate:vlv
6958 * Disabling L3 clock gating- MMIO 940c[25] = 1
6959 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6960 I915_WRITE(GEN7_UCGCTL4,
6961 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6962
afd58e79
VS		 6963 /*
6964 * BSpec says this must be set, even though
6965 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6966 */
6b26c86d
DV		 6967 I915_WRITE(CACHE_MODE_1,
6968 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6969
da2518f9
VS		 6970 /*
6971 * BSpec recommends 8x4 when MSAA is used,
6972 * however in practice 16x4 seems fastest.
6973 *
6974 * Note that PS/WM thread counts depend on the WIZ hashing
6975 * disable bit, which we don't touch here, but it's good
6976 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6977 */
6978 I915_WRITE(GEN7_GT_MODE,
6979 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6980
031994ee
VS		 6981 /*
6982 * WaIncreaseL3CreditsForVLVB0:vlv
6983 * This is the hardware default actually.
6984 */
6985 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6986
2d809570 6987 /*
ecdb4eb7 6988 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6989 * Disable clock gating on th GCFG unit to prevent a delay
6990 * in the reporting of vblank events.
6991 */
7a0d1eed 6992 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6993}
6994
a4565da8
VS		 6995static void cherryview_init_clock_gating(struct drm_device *dev)
6996{
6997 struct drm_i915_private *dev_priv = dev->dev_private;
6998
c6beb13e 6999 vlv_init_display_clock_gating(dev_priv);
dd811e70 7000
232ce337
VS		 7001 /* WaVSRefCountFullforceMissDisable:chv */
7002 /* WaDSRefCountFullforceMissDisable:chv */
7003 I915_WRITE(GEN7_FF_THREAD_MODE,
7004 I915_READ(GEN7_FF_THREAD_MODE) &
7005 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7006
7007 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7008 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7009 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7010
7011 /* WaDisableCSUnitClockGating:chv */
7012 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7013 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7014
7015 /* WaDisableSDEUnitClockGating:chv */
7016 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7017 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 7018
7019 /*
7020 * GTT cache may not work with big pages, so if those
7021 * are ever enabled GTT cache may need to be disabled.
7022 */
7023 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7024}
7025
1fa61106 7026static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7027{
7028 struct drm_i915_private *dev_priv = dev->dev_private;
7029 uint32_t dspclk_gate;
7030
7031 I915_WRITE(RENCLK_GATE_D1, 0);
7032 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7033 GS_UNIT_CLOCK_GATE_DISABLE |
7034 CL_UNIT_CLOCK_GATE_DISABLE);
7035 I915_WRITE(RAMCLK_GATE_D, 0);
7036 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7037 OVRUNIT_CLOCK_GATE_DISABLE |
7038 OVCUNIT_CLOCK_GATE_DISABLE;
7039 if (IS_GM45(dev))
7040 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7041 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7042
7043 /* WaDisableRenderCachePipelinedFlush */
7044 I915_WRITE(CACHE_MODE_0,
7045 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7046
4e04632e
AG		 7047 /* WaDisable_RenderCache_OperationalFlush:g4x */
7048 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7049
0e088b8f 7050 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7051}
7052
1fa61106 7053static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7054{
7055 struct drm_i915_private *dev_priv = dev->dev_private;
7056
7057 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7058 I915_WRITE(RENCLK_GATE_D2, 0);
7059 I915_WRITE(DSPCLK_GATE_D, 0);
7060 I915_WRITE(RAMCLK_GATE_D, 0);
7061 I915_WRITE16(DEUC, 0);
20f94967
VS		 7062 I915_WRITE(MI_ARB_STATE,
7063 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7064
7065 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7066 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7067}
7068
1fa61106 7069static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7070{
7071 struct drm_i915_private *dev_priv = dev->dev_private;
7072
7073 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7074 I965_RCC_CLOCK_GATE_DISABLE |
7075 I965_RCPB_CLOCK_GATE_DISABLE |
7076 I965_ISC_CLOCK_GATE_DISABLE |
7077 I965_FBC_CLOCK_GATE_DISABLE);
7078 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7079 I915_WRITE(MI_ARB_STATE,
7080 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7081
7082 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7083 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7084}
7085
1fa61106 7086static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7087{
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089 u32 dstate = I915_READ(D_STATE);
7090
7091 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7092 DSTATE_DOT_CLOCK_GATING;
7093 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7094
7095 if (IS_PINEVIEW(dev))
7096 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7097
7098 /* IIR "flip pending" means done if this bit is set */
7099 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7100
7101 /* interrupts should cause a wake up from C3 */
3299254f 7102 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7103
7104 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7105 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7106
7107 I915_WRITE(MI_ARB_STATE,
7108 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7109}
7110
1fa61106 7111static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7112{
7113 struct drm_i915_private *dev_priv = dev->dev_private;
7114
7115 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7116
7117 /* interrupts should cause a wake up from C3 */
7118 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7119 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7120
7121 I915_WRITE(MEM_MODE,
7122 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7123}
7124
1fa61106 7125static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7126{
7127 struct drm_i915_private *dev_priv = dev->dev_private;
7128
7129 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7130
7131 I915_WRITE(MEM_MODE,
7132 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7133 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7134}
7135
6f1d69b0
ED		 7136void intel_init_clock_gating(struct drm_device *dev)
7137{
7138 struct drm_i915_private *dev_priv = dev->dev_private;
7139
c57e3551
DL		 7140 if (dev_priv->display.init_clock_gating)
7141 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7142}
7143
7d708ee4
ID		 7144void intel_suspend_hw(struct drm_device *dev)
7145{
7146 if (HAS_PCH_LPT(dev))
7147 lpt_suspend_hw(dev);
7148}
7149
1fa61106
ED		 7150/* Set up chip specific power management-related functions */
7151void intel_init_pm(struct drm_device *dev)
7152{
7153 struct drm_i915_private *dev_priv = dev->dev_private;
7154
7ff0ebcc 7155 intel_fbc_init(dev_priv);
1fa61106 7156
c921aba8
DV		 7157 /* For cxsr */
7158 if (IS_PINEVIEW(dev))
7159 i915_pineview_get_mem_freq(dev);
7160 else if (IS_GEN5(dev))
7161 i915_ironlake_get_mem_freq(dev);
7162
1fa61106 7163 /* For FIFO watermark updates */
f5ed50cb 7164 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7165 skl_setup_wm_latency(dev);
7166
a82abe43
ID		 7167 if (IS_BROXTON(dev))
7168 dev_priv->display.init_clock_gating =
7169 bxt_init_clock_gating;
7170 else if (IS_SKYLAKE(dev))
7171 dev_priv->display.init_clock_gating =
7172 skl_init_clock_gating;
2d41c0b5
PB		 7173 dev_priv->display.update_wm = skl_update_wm;
7174 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 7175 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7176 ilk_setup_wm_latency(dev);
53615a5e 7177
bd602544
VS		 7178 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7179 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7180 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7181 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7182 dev_priv->display.update_wm = ilk_update_wm;
7183 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7184 } else {
7185 DRM_DEBUG_KMS("Failed to read display plane latency. "
7186 "Disable CxSR\n");
7187 }
7188
7189 if (IS_GEN5(dev))
1fa61106 7190 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7191 else if (IS_GEN6(dev))
1fa61106 7192 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7193 else if (IS_IVYBRIDGE(dev))
1fa61106 7194 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7195 else if (IS_HASWELL(dev))
cad2a2d7 7196 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7197 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7198 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7199 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7200 vlv_setup_wm_latency(dev);
7201
7202 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7203 dev_priv->display.init_clock_gating =
7204 cherryview_init_clock_gating;
1fa61106 7205 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7206 vlv_setup_wm_latency(dev);
7207
7208 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7209 dev_priv->display.init_clock_gating =
7210 valleyview_init_clock_gating;
1fa61106
ED		 7211 } else if (IS_PINEVIEW(dev)) {
7212 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7213 dev_priv->is_ddr3,
7214 dev_priv->fsb_freq,
7215 dev_priv->mem_freq)) {
7216 DRM_INFO("failed to find known CxSR latency "
7217 "(found ddr%s fsb freq %d, mem freq %d), "
7218 "disabling CxSR\n",
7219 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7220 dev_priv->fsb_freq, dev_priv->mem_freq);
7221 /* Disable CxSR and never update its watermark again */
5209b1f4 7222 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7223 dev_priv->display.update_wm = NULL;
7224 } else
7225 dev_priv->display.update_wm = pineview_update_wm;
7226 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7227 } else if (IS_G4X(dev)) {
7228 dev_priv->display.update_wm = g4x_update_wm;
7229 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7230 } else if (IS_GEN4(dev)) {
7231 dev_priv->display.update_wm = i965_update_wm;
7232 if (IS_CRESTLINE(dev))
7233 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7234 else if (IS_BROADWATER(dev))
7235 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7236 } else if (IS_GEN3(dev)) {
7237 dev_priv->display.update_wm = i9xx_update_wm;
7238 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7239 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7240 } else if (IS_GEN2(dev)) {
7241 if (INTEL_INFO(dev)->num_pipes == 1) {
7242 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7243 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7244 } else {
7245 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7246 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7247 }
7248
7249 if (IS_I85X(dev) || IS_I865G(dev))
7250 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7251 else
7252 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7253 } else {
7254 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7255 }
7256}
7257
151a49d0 7258int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7259{
4fc688ce 7260 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7261
7262 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7263 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7264 return -EAGAIN;
7265 }
7266
7267 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7268 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7269 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7270
7271 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7272 500)) {
7273 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7274 return -ETIMEDOUT;
7275 }
7276
7277 *val = I915_READ(GEN6_PCODE_DATA);
7278 I915_WRITE(GEN6_PCODE_DATA, 0);
7279
7280 return 0;
7281}
7282
151a49d0 7283int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7284{
4fc688ce 7285 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7286
7287 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7288 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7289 return -EAGAIN;
7290 }
7291
7292 I915_WRITE(GEN6_PCODE_DATA, val);
7293 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7294
7295 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7296 500)) {
7297 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7298 return -ETIMEDOUT;
7299 }
7300
7301 I915_WRITE(GEN6_PCODE_DATA, 0);
7302
7303 return 0;
7304}
a0e4e199 7305
dd06f88c 7306static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7307{
dd06f88c
VS		 7308 switch (czclk_freq) {
7309 case 200:
7310 return 10;
7311 case 267:
7312 return 12;
7313 case 320:
7314 case 333:
dd06f88c 7315 return 16;
ab3fb157
VS		 7316 case 400:
7317 return 20;
855ba3be
JB		 7318 default:
7319 return -1;
7320 }
dd06f88c 7321}
855ba3be 7322
dd06f88c
VS		 7323static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7324{
7325 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7326
7327 div = vlv_gpu_freq_div(czclk_freq);
7328 if (div < 0)
7329 return div;
7330
7331 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7332}
7333
b55dd647 7334static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7335{
dd06f88c 7336 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 7337
dd06f88c
VS		 7338 mul = vlv_gpu_freq_div(czclk_freq);
7339 if (mul < 0)
7340 return mul;
855ba3be 7341
dd06f88c 7342 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7343}
7344
b55dd647 7345static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7346{
dd06f88c 7347 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7348
dd06f88c
VS		 7349 div = vlv_gpu_freq_div(czclk_freq) / 2;
7350 if (div < 0)
7351 return div;
22b1b2f8 7352
dd06f88c 7353 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7354}
7355
b55dd647 7356static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7357{
dd06f88c 7358 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7359
dd06f88c
VS		 7360 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7361 if (mul < 0)
7362 return mul;
22b1b2f8 7363
1c14762d 7364 /* CHV needs even values */
dd06f88c 7365 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7366}
7367
616bc820 7368int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7369{
80b6dda4
AG		 7370 if (IS_GEN9(dev_priv->dev))
7371 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7372 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7373 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7374 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7375 return byt_gpu_freq(dev_priv, val);
7376 else
7377 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7378}
7379
616bc820
VS		 7380int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7381{
80b6dda4
AG		 7382 if (IS_GEN9(dev_priv->dev))
7383 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7384 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7385 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7386 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7387 return byt_freq_opcode(dev_priv, val);
7388 else
7389 return val / GT_FREQUENCY_MULTIPLIER;
7390}
22b1b2f8 7391
6ad790c0
CW		 7392struct request_boost {
7393 struct work_struct work;
eed29a5b 7394 struct drm_i915_gem_request *req;
6ad790c0
CW		 7395};
7396
7397static void __intel_rps_boost_work(struct work_struct *work)
7398{
7399 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7400 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7401
e61b9958
CW		 7402 if (!i915_gem_request_completed(req, true))
7403 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7404 req->emitted_jiffies);
6ad790c0 7405
e61b9958 7406 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7407 kfree(boost);
7408}
7409
7410void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7411 struct drm_i915_gem_request *req)
6ad790c0
CW		 7412{
7413 struct request_boost *boost;
7414
eed29a5b 7415 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7416 return;
7417
e61b9958
CW		 7418 if (i915_gem_request_completed(req, true))
7419 return;
7420
6ad790c0
CW		 7421 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7422 if (boost == NULL)
7423 return;
7424
eed29a5b
DV		 7425 i915_gem_request_reference(req);
7426 boost->req = req;
6ad790c0
CW		 7427
7428 INIT_WORK(&boost->work, __intel_rps_boost_work);
7429 queue_work(to_i915(dev)->wq, &boost->work);
7430}
7431
f742a552 7432void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7433{
7434 struct drm_i915_private *dev_priv = dev->dev_private;
7435
f742a552 7436 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7437 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7438
907b28c5
CW		 7439 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7440 intel_gen6_powersave_work);
1854d5ca 7441 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7442 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7443 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7444
33688d95 7445 dev_priv->pm.suspended = false;
907b28c5 7446}
ubuntu-bionic-kernel mirror