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drm/i915: Refactor intel_surf_alignment()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
a82abe43
ID		 55static void bxt_init_clock_gating(struct drm_device *dev)
56{
32608ca2
ID		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
a7546159
NH		 59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
32608ca2
ID		 63 /*
64 * FIXME:
868434c5 65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 66 */
32608ca2 67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 69
70 /*
71 * Wa: Backlight PWM may stop in the asserted state, causing backlight
72 * to stay fully on.
73 */
74 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
75 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
76 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 77}
78
c921aba8
DV		 79static void i915_pineview_get_mem_freq(struct drm_device *dev)
80{
50227e1c 81 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 82 u32 tmp;
83
84 tmp = I915_READ(CLKCFG);
85
86 switch (tmp & CLKCFG_FSB_MASK) {
87 case CLKCFG_FSB_533:
88 dev_priv->fsb_freq = 533; /* 133*4 */
89 break;
90 case CLKCFG_FSB_800:
91 dev_priv->fsb_freq = 800; /* 200*4 */
92 break;
93 case CLKCFG_FSB_667:
94 dev_priv->fsb_freq = 667; /* 167*4 */
95 break;
96 case CLKCFG_FSB_400:
97 dev_priv->fsb_freq = 400; /* 100*4 */
98 break;
99 }
100
101 switch (tmp & CLKCFG_MEM_MASK) {
102 case CLKCFG_MEM_533:
103 dev_priv->mem_freq = 533;
104 break;
105 case CLKCFG_MEM_667:
106 dev_priv->mem_freq = 667;
107 break;
108 case CLKCFG_MEM_800:
109 dev_priv->mem_freq = 800;
110 break;
111 }
112
113 /* detect pineview DDR3 setting */
114 tmp = I915_READ(CSHRDDR3CTL);
115 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
116}
117
118static void i915_ironlake_get_mem_freq(struct drm_device *dev)
119{
50227e1c 120 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 121 u16 ddrpll, csipll;
122
123 ddrpll = I915_READ16(DDRMPLL1);
124 csipll = I915_READ16(CSIPLL0);
125
126 switch (ddrpll & 0xff) {
127 case 0xc:
128 dev_priv->mem_freq = 800;
129 break;
130 case 0x10:
131 dev_priv->mem_freq = 1066;
132 break;
133 case 0x14:
134 dev_priv->mem_freq = 1333;
135 break;
136 case 0x18:
137 dev_priv->mem_freq = 1600;
138 break;
139 default:
140 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
141 ddrpll & 0xff);
142 dev_priv->mem_freq = 0;
143 break;
144 }
145
20e4d407 146 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 147
148 switch (csipll & 0x3ff) {
149 case 0x00c:
150 dev_priv->fsb_freq = 3200;
151 break;
152 case 0x00e:
153 dev_priv->fsb_freq = 3733;
154 break;
155 case 0x010:
156 dev_priv->fsb_freq = 4266;
157 break;
158 case 0x012:
159 dev_priv->fsb_freq = 4800;
160 break;
161 case 0x014:
162 dev_priv->fsb_freq = 5333;
163 break;
164 case 0x016:
165 dev_priv->fsb_freq = 5866;
166 break;
167 case 0x018:
168 dev_priv->fsb_freq = 6400;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
172 csipll & 0x3ff);
173 dev_priv->fsb_freq = 0;
174 break;
175 }
176
177 if (dev_priv->fsb_freq == 3200) {
20e4d407 178 dev_priv->ips.c_m = 0;
c921aba8 179 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 180 dev_priv->ips.c_m = 1;
c921aba8 181 } else {
20e4d407 182 dev_priv->ips.c_m = 2;
c921aba8
DV		 183 }
184}
185
b445e3b0
ED		 186static const struct cxsr_latency cxsr_latency_table[] = {
187 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
188 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
189 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
190 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
191 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
192
193 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
194 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
195 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
196 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
197 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
198
199 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
200 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
201 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
202 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
203 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
204
205 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
206 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
207 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
208 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
209 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
210
211 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
212 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
213 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
214 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
215 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
216
217 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
218 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
219 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
220 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
221 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
222};
223
63c62275 224static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 225 int is_ddr3,
226 int fsb,
227 int mem)
228{
229 const struct cxsr_latency *latency;
230 int i;
231
232 if (fsb == 0 || mem == 0)
233 return NULL;
234
235 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
236 latency = &cxsr_latency_table[i];
237 if (is_desktop == latency->is_desktop &&
238 is_ddr3 == latency->is_ddr3 &&
239 fsb == latency->fsb_freq && mem == latency->mem_freq)
240 return latency;
241 }
242
243 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
244
245 return NULL;
246}
247
fc1ac8de
VS		 248static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
249{
250 u32 val;
251
252 mutex_lock(&dev_priv->rps.hw_lock);
253
254 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
255 if (enable)
256 val &= ~FORCE_DDR_HIGH_FREQ;
257 else
258 val |= FORCE_DDR_HIGH_FREQ;
259 val &= ~FORCE_DDR_LOW_FREQ;
260 val |= FORCE_DDR_FREQ_REQ_ACK;
261 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
262
263 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
264 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
265 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
266
267 mutex_unlock(&dev_priv->rps.hw_lock);
268}
269
cfb41411
VS		 270static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
271{
272 u32 val;
273
274 mutex_lock(&dev_priv->rps.hw_lock);
275
276 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
277 if (enable)
278 val |= DSP_MAXFIFO_PM5_ENABLE;
279 else
280 val &= ~DSP_MAXFIFO_PM5_ENABLE;
281 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
282
283 mutex_unlock(&dev_priv->rps.hw_lock);
284}
285
f4998963
VS		 286#define FW_WM(value, plane) \
287 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
288
5209b1f4 289void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 290{
5209b1f4
ID		 291 struct drm_device *dev = dev_priv->dev;
292 u32 val;
b445e3b0 293
666a4537 294 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 295 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 296 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 297 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 298 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
299 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 300 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 301 } else if (IS_PINEVIEW(dev)) {
302 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
303 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
304 I915_WRITE(DSPFW3, val);
a7a6c498 305 POSTING_READ(DSPFW3);
5209b1f4
ID		 306 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
307 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
308 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
309 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 310 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 311 } else if (IS_I915GM(dev)) {
312 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
313 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
314 I915_WRITE(INSTPM, val);
a7a6c498 315 POSTING_READ(INSTPM);
5209b1f4
ID		 316 } else {
317 return;
318 }
b445e3b0 319
5209b1f4
ID		 320 DRM_DEBUG_KMS("memory self-refresh is %s\n",
321 enable ? "enabled" : "disabled");
b445e3b0
ED		 322}
323
fc1ac8de 324
b445e3b0
ED		 325/*
326 * Latency for FIFO fetches is dependent on several factors:
327 * - memory configuration (speed, channels)
328 * - chipset
329 * - current MCH state
330 * It can be fairly high in some situations, so here we assume a fairly
331 * pessimal value. It's a tradeoff between extra memory fetches (if we
332 * set this value too high, the FIFO will fetch frequently to stay full)
333 * and power consumption (set it too low to save power and we might see
334 * FIFO underruns and display "flicker").
335 *
336 * A value of 5us seems to be a good balance; safe for very low end
337 * platforms but not overly aggressive on lower latency configs.
338 */
5aef6003 339static const int pessimal_latency_ns = 5000;
b445e3b0 340
b5004720
VS		 341#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
342 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
343
344static int vlv_get_fifo_size(struct drm_device *dev,
345 enum pipe pipe, int plane)
346{
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 int sprite0_start, sprite1_start, size;
349
350 switch (pipe) {
351 uint32_t dsparb, dsparb2, dsparb3;
352 case PIPE_A:
353 dsparb = I915_READ(DSPARB);
354 dsparb2 = I915_READ(DSPARB2);
355 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
356 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
357 break;
358 case PIPE_B:
359 dsparb = I915_READ(DSPARB);
360 dsparb2 = I915_READ(DSPARB2);
361 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
362 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
363 break;
364 case PIPE_C:
365 dsparb2 = I915_READ(DSPARB2);
366 dsparb3 = I915_READ(DSPARB3);
367 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
368 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
369 break;
370 default:
371 return 0;
372 }
373
374 switch (plane) {
375 case 0:
376 size = sprite0_start;
377 break;
378 case 1:
379 size = sprite1_start - sprite0_start;
380 break;
381 case 2:
382 size = 512 - 1 - sprite1_start;
383 break;
384 default:
385 return 0;
386 }
387
388 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
389 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
390 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
391 size);
392
393 return size;
394}
395
1fa61106 396static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 397{
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 uint32_t dsparb = I915_READ(DSPARB);
400 int size;
401
402 size = dsparb & 0x7f;
403 if (plane)
404 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
405
406 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
407 plane ? "B" : "A", size);
408
409 return size;
410}
411
feb56b93 412static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 413{
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 uint32_t dsparb = I915_READ(DSPARB);
416 int size;
417
418 size = dsparb & 0x1ff;
419 if (plane)
420 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
421 size >>= 1; /* Convert to cachelines */
422
423 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
424 plane ? "B" : "A", size);
425
426 return size;
427}
428
1fa61106 429static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 430{
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 uint32_t dsparb = I915_READ(DSPARB);
433 int size;
434
435 size = dsparb & 0x7f;
436 size >>= 2; /* Convert to cachelines */
437
438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
439 plane ? "B" : "A",
440 size);
441
442 return size;
443}
444
b445e3b0
ED		 445/* Pineview has different values for various configs */
446static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 447 .fifo_size = PINEVIEW_DISPLAY_FIFO,
448 .max_wm = PINEVIEW_MAX_WM,
449 .default_wm = PINEVIEW_DFT_WM,
450 .guard_size = PINEVIEW_GUARD_WM,
451 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 452};
453static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 454 .fifo_size = PINEVIEW_DISPLAY_FIFO,
455 .max_wm = PINEVIEW_MAX_WM,
456 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
457 .guard_size = PINEVIEW_GUARD_WM,
458 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 459};
460static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 461 .fifo_size = PINEVIEW_CURSOR_FIFO,
462 .max_wm = PINEVIEW_CURSOR_MAX_WM,
463 .default_wm = PINEVIEW_CURSOR_DFT_WM,
464 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 466};
467static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 468 .fifo_size = PINEVIEW_CURSOR_FIFO,
469 .max_wm = PINEVIEW_CURSOR_MAX_WM,
470 .default_wm = PINEVIEW_CURSOR_DFT_WM,
471 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 473};
474static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 475 .fifo_size = G4X_FIFO_SIZE,
476 .max_wm = G4X_MAX_WM,
477 .default_wm = G4X_MAX_WM,
478 .guard_size = 2,
479 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 480};
481static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 482 .fifo_size = I965_CURSOR_FIFO,
483 .max_wm = I965_CURSOR_MAX_WM,
484 .default_wm = I965_CURSOR_DFT_WM,
485 .guard_size = 2,
486 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 487};
488static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 489 .fifo_size = VALLEYVIEW_FIFO_SIZE,
490 .max_wm = VALLEYVIEW_MAX_WM,
491 .default_wm = VALLEYVIEW_MAX_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 494};
495static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 503 .fifo_size = I965_CURSOR_FIFO,
504 .max_wm = I965_CURSOR_MAX_WM,
505 .default_wm = I965_CURSOR_DFT_WM,
506 .guard_size = 2,
507 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 510 .fifo_size = I945_FIFO_SIZE,
511 .max_wm = I915_MAX_WM,
512 .default_wm = 1,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 517 .fifo_size = I915_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 522};
9d539105 523static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 524 .fifo_size = I855GM_FIFO_SIZE,
525 .max_wm = I915_MAX_WM,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 529};
9d539105
VS		 530static const struct intel_watermark_params i830_bc_wm_info = {
531 .fifo_size = I855GM_FIFO_SIZE,
532 .max_wm = I915_MAX_WM/2,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
536};
feb56b93 537static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 538 .fifo_size = I830_FIFO_SIZE,
539 .max_wm = I915_MAX_WM,
540 .default_wm = 1,
541 .guard_size = 2,
542 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 543};
544
b445e3b0
ED		 545/**
546 * intel_calculate_wm - calculate watermark level
547 * @clock_in_khz: pixel clock
548 * @wm: chip FIFO params
549 * @pixel_size: display pixel size
550 * @latency_ns: memory latency for the platform
551 *
552 * Calculate the watermark level (the level at which the display plane will
553 * start fetching from memory again). Each chip has a different display
554 * FIFO size and allocation, so the caller needs to figure that out and pass
555 * in the correct intel_watermark_params structure.
556 *
557 * As the pixel clock runs, the FIFO will be drained at a rate that depends
558 * on the pixel size. When it reaches the watermark level, it'll start
559 * fetching FIFO line sized based chunks from memory until the FIFO fills
560 * past the watermark point. If the FIFO drains completely, a FIFO underrun
561 * will occur, and a display engine hang could result.
562 */
563static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
564 const struct intel_watermark_params *wm,
565 int fifo_size,
566 int pixel_size,
567 unsigned long latency_ns)
568{
569 long entries_required, wm_size;
570
571 /*
572 * Note: we need to make sure we don't overflow for various clock &
573 * latency values.
574 * clocks go from a few thousand to several hundred thousand.
575 * latency is usually a few thousand
576 */
577 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
578 1000;
579 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
580
581 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
582
583 wm_size = fifo_size - (entries_required + wm->guard_size);
584
585 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
586
587 /* Don't promote wm_size to unsigned... */
588 if (wm_size > (long)wm->max_wm)
589 wm_size = wm->max_wm;
590 if (wm_size <= 0)
591 wm_size = wm->default_wm;
d6feb196
VS		 592
593 /*
594 * Bspec seems to indicate that the value shouldn't be lower than
595 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
596 * Lets go for 8 which is the burst size since certain platforms
597 * already use a hardcoded 8 (which is what the spec says should be
598 * done).
599 */
600 if (wm_size <= 8)
601 wm_size = 8;
602
b445e3b0
ED		 603 return wm_size;
604}
605
606static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
607{
608 struct drm_crtc *crtc, *enabled = NULL;
609
70e1e0ec 610 for_each_crtc(dev, crtc) {
3490ea5d 611 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 612 if (enabled)
613 return NULL;
614 enabled = crtc;
615 }
616 }
617
618 return enabled;
619}
620
46ba614c 621static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 622{
46ba614c 623 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 624 struct drm_i915_private *dev_priv = dev->dev_private;
625 struct drm_crtc *crtc;
626 const struct cxsr_latency *latency;
627 u32 reg;
628 unsigned long wm;
629
630 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
631 dev_priv->fsb_freq, dev_priv->mem_freq);
632 if (!latency) {
633 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 634 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 635 return;
636 }
637
638 crtc = single_enabled_crtc(dev);
639 if (crtc) {
7c5f93b0 640 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 641 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 642 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 643
644 /* Display SR */
645 wm = intel_calculate_wm(clock, &pineview_display_wm,
646 pineview_display_wm.fifo_size,
647 pixel_size, latency->display_sr);
648 reg = I915_READ(DSPFW1);
649 reg &= ~DSPFW_SR_MASK;
f4998963 650 reg |= FW_WM(wm, SR);
b445e3b0
ED		 651 I915_WRITE(DSPFW1, reg);
652 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
653
654 /* cursor SR */
655 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
656 pineview_display_wm.fifo_size,
657 pixel_size, latency->cursor_sr);
658 reg = I915_READ(DSPFW3);
659 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 660 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 661 I915_WRITE(DSPFW3, reg);
662
663 /* Display HPLL off SR */
664 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
665 pineview_display_hplloff_wm.fifo_size,
666 pixel_size, latency->display_hpll_disable);
667 reg = I915_READ(DSPFW3);
668 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 669 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 670 I915_WRITE(DSPFW3, reg);
671
672 /* cursor HPLL off SR */
673 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
674 pineview_display_hplloff_wm.fifo_size,
675 pixel_size, latency->cursor_hpll_disable);
676 reg = I915_READ(DSPFW3);
677 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 678 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 679 I915_WRITE(DSPFW3, reg);
680 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
681
5209b1f4 682 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 683 } else {
5209b1f4 684 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 685 }
686}
687
688static bool g4x_compute_wm0(struct drm_device *dev,
689 int plane,
690 const struct intel_watermark_params *display,
691 int display_latency_ns,
692 const struct intel_watermark_params *cursor,
693 int cursor_latency_ns,
694 int *plane_wm,
695 int *cursor_wm)
696{
697 struct drm_crtc *crtc;
4fe8590a 698 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 699 int htotal, hdisplay, clock, pixel_size;
700 int line_time_us, line_count;
701 int entries, tlb_miss;
702
703 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 704 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 705 *cursor_wm = cursor->guard_size;
706 *plane_wm = display->guard_size;
707 return false;
708 }
709
6e3c9717 710 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 711 clock = adjusted_mode->crtc_clock;
fec8cba3 712 htotal = adjusted_mode->crtc_htotal;
6e3c9717 713 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 714 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 715
716 /* Use the small buffer method to calculate plane watermark */
717 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
718 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
719 if (tlb_miss > 0)
720 entries += tlb_miss;
721 entries = DIV_ROUND_UP(entries, display->cacheline_size);
722 *plane_wm = entries + display->guard_size;
723 if (*plane_wm > (int)display->max_wm)
724 *plane_wm = display->max_wm;
725
726 /* Use the large buffer method to calculate cursor watermark */
922044c9 727 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 728 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 729 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 730 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
731 if (tlb_miss > 0)
732 entries += tlb_miss;
733 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
734 *cursor_wm = entries + cursor->guard_size;
735 if (*cursor_wm > (int)cursor->max_wm)
736 *cursor_wm = (int)cursor->max_wm;
737
738 return true;
739}
740
741/*
742 * Check the wm result.
743 *
744 * If any calculated watermark values is larger than the maximum value that
745 * can be programmed into the associated watermark register, that watermark
746 * must be disabled.
747 */
748static bool g4x_check_srwm(struct drm_device *dev,
749 int display_wm, int cursor_wm,
750 const struct intel_watermark_params *display,
751 const struct intel_watermark_params *cursor)
752{
753 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
754 display_wm, cursor_wm);
755
756 if (display_wm > display->max_wm) {
757 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
758 display_wm, display->max_wm);
759 return false;
760 }
761
762 if (cursor_wm > cursor->max_wm) {
763 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
764 cursor_wm, cursor->max_wm);
765 return false;
766 }
767
768 if (!(display_wm || cursor_wm)) {
769 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
770 return false;
771 }
772
773 return true;
774}
775
776static bool g4x_compute_srwm(struct drm_device *dev,
777 int plane,
778 int latency_ns,
779 const struct intel_watermark_params *display,
780 const struct intel_watermark_params *cursor,
781 int *display_wm, int *cursor_wm)
782{
783 struct drm_crtc *crtc;
4fe8590a 784 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 785 int hdisplay, htotal, pixel_size, clock;
786 unsigned long line_time_us;
787 int line_count, line_size;
788 int small, large;
789 int entries;
790
791 if (!latency_ns) {
792 *display_wm = *cursor_wm = 0;
793 return false;
794 }
795
796 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 797 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 798 clock = adjusted_mode->crtc_clock;
fec8cba3 799 htotal = adjusted_mode->crtc_htotal;
6e3c9717 800 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 801 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 802
922044c9 803 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 804 line_count = (latency_ns / line_time_us + 1000) / 1000;
805 line_size = hdisplay * pixel_size;
806
807 /* Use the minimum of the small and large buffer method for primary */
808 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
809 large = line_count * line_size;
810
811 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
812 *display_wm = entries + display->guard_size;
813
814 /* calculate the self-refresh watermark for display cursor */
3dd512fb 815 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 816 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
817 *cursor_wm = entries + cursor->guard_size;
818
819 return g4x_check_srwm(dev,
820 *display_wm, *cursor_wm,
821 display, cursor);
822}
823
15665979
VS		 824#define FW_WM_VLV(value, plane) \
825 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
826
0018fda1
VS		 827static void vlv_write_wm_values(struct intel_crtc *crtc,
828 const struct vlv_wm_values *wm)
829{
830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
831 enum pipe pipe = crtc->pipe;
832
833 I915_WRITE(VLV_DDL(pipe),
834 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
835 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
836 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
837 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
838
ae80152d 839 I915_WRITE(DSPFW1,
15665979
VS		 840 FW_WM(wm->sr.plane, SR) |
841 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
842 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
843 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 844 I915_WRITE(DSPFW2,
15665979
VS		 845 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
846 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
847 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 848 I915_WRITE(DSPFW3,
15665979 849 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 850
851 if (IS_CHERRYVIEW(dev_priv)) {
852 I915_WRITE(DSPFW7_CHV,
15665979
VS		 853 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 855 I915_WRITE(DSPFW8_CHV,
15665979
VS		 856 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 858 I915_WRITE(DSPFW9_CHV,
15665979
VS		 859 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
860 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 861 I915_WRITE(DSPHOWM,
15665979
VS		 862 FW_WM(wm->sr.plane >> 9, SR_HI) |
863 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
865 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
868 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
871 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 872 } else {
873 I915_WRITE(DSPFW7,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPHOWM,
15665979
VS		 877 FW_WM(wm->sr.plane >> 9, SR_HI) |
878 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
880 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
881 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
883 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 884 }
885
2cb389b7
VS		 886 /* zero (unused) WM1 watermarks */
887 I915_WRITE(DSPFW4, 0);
888 I915_WRITE(DSPFW5, 0);
889 I915_WRITE(DSPFW6, 0);
890 I915_WRITE(DSPHOWM1, 0);
891
ae80152d 892 POSTING_READ(DSPFW1);
0018fda1
VS		 893}
894
15665979
VS		 895#undef FW_WM_VLV
896
6eb1a681
VS		 897enum vlv_wm_level {
898 VLV_WM_LEVEL_PM2,
899 VLV_WM_LEVEL_PM5,
900 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 901};
902
262cd2e1
VS		 903/* latency must be in 0.1us units. */
904static unsigned int vlv_wm_method2(unsigned int pixel_rate,
905 unsigned int pipe_htotal,
906 unsigned int horiz_pixels,
907 unsigned int bytes_per_pixel,
908 unsigned int latency)
909{
910 unsigned int ret;
911
912 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
913 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
914 ret = DIV_ROUND_UP(ret, 64);
915
916 return ret;
917}
918
919static void vlv_setup_wm_latency(struct drm_device *dev)
920{
921 struct drm_i915_private *dev_priv = dev->dev_private;
922
923 /* all latencies in usec */
924 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
925
58590c14
VS		 926 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
927
262cd2e1
VS		 928 if (IS_CHERRYVIEW(dev_priv)) {
929 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 931
932 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 933 }
934}
935
936static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
937 struct intel_crtc *crtc,
938 const struct intel_plane_state *state,
939 int level)
940{
941 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
942 int clock, htotal, pixel_size, width, wm;
943
944 if (dev_priv->wm.pri_latency[level] == 0)
945 return USHRT_MAX;
946
947 if (!state->visible)
948 return 0;
949
950 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
951 clock = crtc->config->base.adjusted_mode.crtc_clock;
952 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
953 width = crtc->config->pipe_src_w;
954 if (WARN_ON(htotal == 0))
955 htotal = 1;
956
957 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
958 /*
959 * FIXME the formula gives values that are
960 * too big for the cursor FIFO, and hence we
961 * would never be able to use cursors. For
962 * now just hardcode the watermark.
963 */
964 wm = 63;
965 } else {
966 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
967 dev_priv->wm.pri_latency[level] * 10);
968 }
969
970 return min_t(int, wm, USHRT_MAX);
971}
972
54f1b6e1
VS		 973static void vlv_compute_fifo(struct intel_crtc *crtc)
974{
975 struct drm_device *dev = crtc->base.dev;
976 struct vlv_wm_state *wm_state = &crtc->wm_state;
977 struct intel_plane *plane;
978 unsigned int total_rate = 0;
979 const int fifo_size = 512 - 1;
980 int fifo_extra, fifo_left = fifo_size;
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985
986 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
987 continue;
988
989 if (state->visible) {
990 wm_state->num_active_planes++;
991 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
992 }
993 }
994
995 for_each_intel_plane_on_crtc(dev, crtc, plane) {
996 struct intel_plane_state *state =
997 to_intel_plane_state(plane->base.state);
998 unsigned int rate;
999
1000 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1001 plane->wm.fifo_size = 63;
1002 continue;
1003 }
1004
1005 if (!state->visible) {
1006 plane->wm.fifo_size = 0;
1007 continue;
1008 }
1009
1010 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1011 plane->wm.fifo_size = fifo_size * rate / total_rate;
1012 fifo_left -= plane->wm.fifo_size;
1013 }
1014
1015 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1016
1017 /* spread the remainder evenly */
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 int plane_extra;
1020
1021 if (fifo_left == 0)
1022 break;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1025 continue;
1026
1027 /* give it all to the first plane if none are active */
1028 if (plane->wm.fifo_size == 0 &&
1029 wm_state->num_active_planes)
1030 continue;
1031
1032 plane_extra = min(fifo_extra, fifo_left);
1033 plane->wm.fifo_size += plane_extra;
1034 fifo_left -= plane_extra;
1035 }
1036
1037 WARN_ON(fifo_left != 0);
1038}
1039
262cd2e1
VS		 1040static void vlv_invert_wms(struct intel_crtc *crtc)
1041{
1042 struct vlv_wm_state *wm_state = &crtc->wm_state;
1043 int level;
1044
1045 for (level = 0; level < wm_state->num_levels; level++) {
1046 struct drm_device *dev = crtc->base.dev;
1047 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1048 struct intel_plane *plane;
1049
1050 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1051 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1052
1053 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1054 switch (plane->base.type) {
1055 int sprite;
1056 case DRM_PLANE_TYPE_CURSOR:
1057 wm_state->wm[level].cursor = plane->wm.fifo_size -
1058 wm_state->wm[level].cursor;
1059 break;
1060 case DRM_PLANE_TYPE_PRIMARY:
1061 wm_state->wm[level].primary = plane->wm.fifo_size -
1062 wm_state->wm[level].primary;
1063 break;
1064 case DRM_PLANE_TYPE_OVERLAY:
1065 sprite = plane->plane;
1066 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1067 wm_state->wm[level].sprite[sprite];
1068 break;
1069 }
1070 }
1071 }
1072}
1073
26e1fe4f 1074static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1075{
1076 struct drm_device *dev = crtc->base.dev;
1077 struct vlv_wm_state *wm_state = &crtc->wm_state;
1078 struct intel_plane *plane;
1079 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1080 int level;
1081
1082 memset(wm_state, 0, sizeof(*wm_state));
1083
852eb00d 1084 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1085 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1086
1087 wm_state->num_active_planes = 0;
262cd2e1 1088
54f1b6e1 1089 vlv_compute_fifo(crtc);
262cd2e1
VS		 1090
1091 if (wm_state->num_active_planes != 1)
1092 wm_state->cxsr = false;
1093
1094 if (wm_state->cxsr) {
1095 for (level = 0; level < wm_state->num_levels; level++) {
1096 wm_state->sr[level].plane = sr_fifo_size;
1097 wm_state->sr[level].cursor = 63;
1098 }
1099 }
1100
1101 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1102 struct intel_plane_state *state =
1103 to_intel_plane_state(plane->base.state);
1104
1105 if (!state->visible)
1106 continue;
1107
1108 /* normal watermarks */
1109 for (level = 0; level < wm_state->num_levels; level++) {
1110 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1111 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1112
1113 /* hack */
1114 if (WARN_ON(level == 0 && wm > max_wm))
1115 wm = max_wm;
1116
1117 if (wm > plane->wm.fifo_size)
1118 break;
1119
1120 switch (plane->base.type) {
1121 int sprite;
1122 case DRM_PLANE_TYPE_CURSOR:
1123 wm_state->wm[level].cursor = wm;
1124 break;
1125 case DRM_PLANE_TYPE_PRIMARY:
1126 wm_state->wm[level].primary = wm;
1127 break;
1128 case DRM_PLANE_TYPE_OVERLAY:
1129 sprite = plane->plane;
1130 wm_state->wm[level].sprite[sprite] = wm;
1131 break;
1132 }
1133 }
1134
1135 wm_state->num_levels = level;
1136
1137 if (!wm_state->cxsr)
1138 continue;
1139
1140 /* maxfifo watermarks */
1141 switch (plane->base.type) {
1142 int sprite, level;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 for (level = 0; level < wm_state->num_levels; level++)
1145 wm_state->sr[level].cursor =
5a37ed0a 1146 wm_state->wm[level].cursor;
262cd2e1
VS		 1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 for (level = 0; level < wm_state->num_levels; level++)
1150 wm_state->sr[level].plane =
1151 min(wm_state->sr[level].plane,
1152 wm_state->wm[level].primary);
1153 break;
1154 case DRM_PLANE_TYPE_OVERLAY:
1155 sprite = plane->plane;
1156 for (level = 0; level < wm_state->num_levels; level++)
1157 wm_state->sr[level].plane =
1158 min(wm_state->sr[level].plane,
1159 wm_state->wm[level].sprite[sprite]);
1160 break;
1161 }
1162 }
1163
1164 /* clear any (partially) filled invalid levels */
58590c14 1165 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1166 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1167 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1168 }
1169
1170 vlv_invert_wms(crtc);
1171}
1172
54f1b6e1
VS		 1173#define VLV_FIFO(plane, value) \
1174 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1175
1176static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1177{
1178 struct drm_device *dev = crtc->base.dev;
1179 struct drm_i915_private *dev_priv = to_i915(dev);
1180 struct intel_plane *plane;
1181 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1182
1183 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1184 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1185 WARN_ON(plane->wm.fifo_size != 63);
1186 continue;
1187 }
1188
1189 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1190 sprite0_start = plane->wm.fifo_size;
1191 else if (plane->plane == 0)
1192 sprite1_start = sprite0_start + plane->wm.fifo_size;
1193 else
1194 fifo_size = sprite1_start + plane->wm.fifo_size;
1195 }
1196
1197 WARN_ON(fifo_size != 512 - 1);
1198
1199 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1200 pipe_name(crtc->pipe), sprite0_start,
1201 sprite1_start, fifo_size);
1202
1203 switch (crtc->pipe) {
1204 uint32_t dsparb, dsparb2, dsparb3;
1205 case PIPE_A:
1206 dsparb = I915_READ(DSPARB);
1207 dsparb2 = I915_READ(DSPARB2);
1208
1209 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1210 VLV_FIFO(SPRITEB, 0xff));
1211 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1212 VLV_FIFO(SPRITEB, sprite1_start));
1213
1214 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1215 VLV_FIFO(SPRITEB_HI, 0x1));
1216 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1217 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1218
1219 I915_WRITE(DSPARB, dsparb);
1220 I915_WRITE(DSPARB2, dsparb2);
1221 break;
1222 case PIPE_B:
1223 dsparb = I915_READ(DSPARB);
1224 dsparb2 = I915_READ(DSPARB2);
1225
1226 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1227 VLV_FIFO(SPRITED, 0xff));
1228 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1229 VLV_FIFO(SPRITED, sprite1_start));
1230
1231 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1232 VLV_FIFO(SPRITED_HI, 0xff));
1233 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1234 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1235
1236 I915_WRITE(DSPARB, dsparb);
1237 I915_WRITE(DSPARB2, dsparb2);
1238 break;
1239 case PIPE_C:
1240 dsparb3 = I915_READ(DSPARB3);
1241 dsparb2 = I915_READ(DSPARB2);
1242
1243 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1244 VLV_FIFO(SPRITEF, 0xff));
1245 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1246 VLV_FIFO(SPRITEF, sprite1_start));
1247
1248 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1249 VLV_FIFO(SPRITEF_HI, 0xff));
1250 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1251 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1252
1253 I915_WRITE(DSPARB3, dsparb3);
1254 I915_WRITE(DSPARB2, dsparb2);
1255 break;
1256 default:
1257 break;
1258 }
1259}
1260
1261#undef VLV_FIFO
1262
262cd2e1
VS		 1263static void vlv_merge_wm(struct drm_device *dev,
1264 struct vlv_wm_values *wm)
1265{
1266 struct intel_crtc *crtc;
1267 int num_active_crtcs = 0;
1268
58590c14 1269 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1270 wm->cxsr = true;
1271
1272 for_each_intel_crtc(dev, crtc) {
1273 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1274
1275 if (!crtc->active)
1276 continue;
1277
1278 if (!wm_state->cxsr)
1279 wm->cxsr = false;
1280
1281 num_active_crtcs++;
1282 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1283 }
1284
1285 if (num_active_crtcs != 1)
1286 wm->cxsr = false;
1287
6f9c784b
VS		 1288 if (num_active_crtcs > 1)
1289 wm->level = VLV_WM_LEVEL_PM2;
1290
262cd2e1
VS		 1291 for_each_intel_crtc(dev, crtc) {
1292 struct vlv_wm_state *wm_state = &crtc->wm_state;
1293 enum pipe pipe = crtc->pipe;
1294
1295 if (!crtc->active)
1296 continue;
1297
1298 wm->pipe[pipe] = wm_state->wm[wm->level];
1299 if (wm->cxsr)
1300 wm->sr = wm_state->sr[wm->level];
1301
1302 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1303 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1306 }
1307}
1308
1309static void vlv_update_wm(struct drm_crtc *crtc)
1310{
1311 struct drm_device *dev = crtc->dev;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314 enum pipe pipe = intel_crtc->pipe;
1315 struct vlv_wm_values wm = {};
1316
26e1fe4f 1317 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1318 vlv_merge_wm(dev, &wm);
1319
54f1b6e1
VS		 1320 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1321 /* FIXME should be part of crtc atomic commit */
1322 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1323 return;
54f1b6e1 1324 }
262cd2e1
VS		 1325
1326 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1327 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1328 chv_set_memory_dvfs(dev_priv, false);
1329
1330 if (wm.level < VLV_WM_LEVEL_PM5 &&
1331 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1332 chv_set_memory_pm5(dev_priv, false);
1333
852eb00d 1334 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1335 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1336
54f1b6e1
VS		 1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc);
1339
262cd2e1
VS		 1340 vlv_write_wm_values(intel_crtc, &wm);
1341
1342 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1343 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1344 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1345 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1346 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1347
852eb00d 1348 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1349 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1350
1351 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, true);
1354
1355 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1356 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1357 chv_set_memory_dvfs(dev_priv, true);
1358
1359 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1360}
1361
ae80152d
VS		 1362#define single_plane_enabled(mask) is_power_of_2(mask)
1363
46ba614c 1364static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1365{
46ba614c 1366 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1367 static const int sr_latency_ns = 12000;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1370 int plane_sr, cursor_sr;
1371 unsigned int enabled = 0;
9858425c 1372 bool cxsr_enabled;
b445e3b0 1373
51cea1f4 1374 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1375 &g4x_wm_info, pessimal_latency_ns,
1376 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1377 &planea_wm, &cursora_wm))
51cea1f4 1378 enabled |= 1 << PIPE_A;
b445e3b0 1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1381 &g4x_wm_info, pessimal_latency_ns,
1382 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1383 &planeb_wm, &cursorb_wm))
51cea1f4 1384 enabled |= 1 << PIPE_B;
b445e3b0 1385
b445e3b0
ED		 1386 if (single_plane_enabled(enabled) &&
1387 g4x_compute_srwm(dev, ffs(enabled) - 1,
1388 sr_latency_ns,
1389 &g4x_wm_info,
1390 &g4x_cursor_wm_info,
52bd02d8 1391 &plane_sr, &cursor_sr)) {
9858425c 1392 cxsr_enabled = true;
52bd02d8 1393 } else {
9858425c 1394 cxsr_enabled = false;
5209b1f4 1395 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1396 plane_sr = cursor_sr = 0;
1397 }
b445e3b0 1398
a5043453
VS		 1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1400 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1401 planea_wm, cursora_wm,
1402 planeb_wm, cursorb_wm,
1403 plane_sr, cursor_sr);
1404
1405 I915_WRITE(DSPFW1,
f4998963
VS		 1406 FW_WM(plane_sr, SR) |
1407 FW_WM(cursorb_wm, CURSORB) |
1408 FW_WM(planeb_wm, PLANEB) |
1409 FW_WM(planea_wm, PLANEA));
b445e3b0 1410 I915_WRITE(DSPFW2,
8c919b28 1411 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1412 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1413 /* HPLL off in SR has some issues on G4x... disable it */
1414 I915_WRITE(DSPFW3,
8c919b28 1415 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1416 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1417
1418 if (cxsr_enabled)
1419 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1420}
1421
46ba614c 1422static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1423{
46ba614c 1424 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 struct drm_crtc *crtc;
1427 int srwm = 1;
1428 int cursor_sr = 16;
9858425c 1429 bool cxsr_enabled;
b445e3b0
ED		 1430
1431 /* Calc sr entries for one plane configs */
1432 crtc = single_enabled_crtc(dev);
1433 if (crtc) {
1434 /* self-refresh has much higher latency */
1435 static const int sr_latency_ns = 12000;
124abe07 1436 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1437 int clock = adjusted_mode->crtc_clock;
fec8cba3 1438 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1439 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1440 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1441 unsigned long line_time_us;
1442 int entries;
1443
922044c9 1444 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1445
1446 /* Use ns/us then divide to preserve precision */
1447 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1448 pixel_size * hdisplay;
1449 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1450 srwm = I965_FIFO_SIZE - entries;
1451 if (srwm < 0)
1452 srwm = 1;
1453 srwm &= 0x1ff;
1454 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1455 entries, srwm);
1456
1457 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1458 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1459 entries = DIV_ROUND_UP(entries,
1460 i965_cursor_wm_info.cacheline_size);
1461 cursor_sr = i965_cursor_wm_info.fifo_size -
1462 (entries + i965_cursor_wm_info.guard_size);
1463
1464 if (cursor_sr > i965_cursor_wm_info.max_wm)
1465 cursor_sr = i965_cursor_wm_info.max_wm;
1466
1467 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1468 "cursor %d\n", srwm, cursor_sr);
1469
9858425c 1470 cxsr_enabled = true;
b445e3b0 1471 } else {
9858425c 1472 cxsr_enabled = false;
b445e3b0 1473 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1474 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1475 }
1476
1477 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1478 srwm);
1479
1480 /* 965 has limitations... */
f4998963
VS		 1481 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1482 FW_WM(8, CURSORB) |
1483 FW_WM(8, PLANEB) |
1484 FW_WM(8, PLANEA));
1485 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1486 FW_WM(8, PLANEC_OLD));
b445e3b0 1487 /* update cursor SR watermark */
f4998963 1488 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1489
1490 if (cxsr_enabled)
1491 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1492}
1493
f4998963
VS		 1494#undef FW_WM
1495
46ba614c 1496static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1497{
46ba614c 1498 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 const struct intel_watermark_params *wm_info;
1501 uint32_t fwater_lo;
1502 uint32_t fwater_hi;
1503 int cwm, srwm = 1;
1504 int fifo_size;
1505 int planea_wm, planeb_wm;
1506 struct drm_crtc *crtc, *enabled = NULL;
1507
1508 if (IS_I945GM(dev))
1509 wm_info = &i945_wm_info;
1510 else if (!IS_GEN2(dev))
1511 wm_info = &i915_wm_info;
1512 else
9d539105 1513 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1514
1515 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1516 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1517 if (intel_crtc_active(crtc)) {
241bfc38 1518 const struct drm_display_mode *adjusted_mode;
59bea882 1519 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1520 if (IS_GEN2(dev))
1521 cpp = 4;
1522
6e3c9717 1523 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1524 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1525 wm_info, fifo_size, cpp,
5aef6003 1526 pessimal_latency_ns);
b445e3b0 1527 enabled = crtc;
9d539105 1528 } else {
b445e3b0 1529 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1530 if (planea_wm > (long)wm_info->max_wm)
1531 planea_wm = wm_info->max_wm;
1532 }
1533
1534 if (IS_GEN2(dev))
1535 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1536
1537 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1538 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1539 if (intel_crtc_active(crtc)) {
241bfc38 1540 const struct drm_display_mode *adjusted_mode;
59bea882 1541 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1542 if (IS_GEN2(dev))
1543 cpp = 4;
1544
6e3c9717 1545 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1546 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
5aef6003 1548 pessimal_latency_ns);
b445e3b0
ED		 1549 if (enabled == NULL)
1550 enabled = crtc;
1551 else
1552 enabled = NULL;
9d539105 1553 } else {
b445e3b0 1554 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1555 if (planeb_wm > (long)wm_info->max_wm)
1556 planeb_wm = wm_info->max_wm;
1557 }
b445e3b0
ED		 1558
1559 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1560
2ab1bc9d 1561 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1562 struct drm_i915_gem_object *obj;
2ab1bc9d 1563
59bea882 1564 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1565
1566 /* self-refresh seems busted with untiled */
2ff8fde1 1567 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1568 enabled = NULL;
1569 }
1570
b445e3b0
ED		 1571 /*
1572 * Overlay gets an aggressive default since video jitter is bad.
1573 */
1574 cwm = 2;
1575
1576 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1577 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1578
1579 /* Calc sr entries for one plane configs */
1580 if (HAS_FW_BLC(dev) && enabled) {
1581 /* self-refresh has much higher latency */
1582 static const int sr_latency_ns = 6000;
124abe07 1583 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1584 int clock = adjusted_mode->crtc_clock;
fec8cba3 1585 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1586 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1587 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1588 unsigned long line_time_us;
1589 int entries;
1590
922044c9 1591 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1592
1593 /* Use ns/us then divide to preserve precision */
1594 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1595 pixel_size * hdisplay;
1596 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1597 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1598 srwm = wm_info->fifo_size - entries;
1599 if (srwm < 0)
1600 srwm = 1;
1601
1602 if (IS_I945G(dev) || IS_I945GM(dev))
1603 I915_WRITE(FW_BLC_SELF,
1604 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1605 else if (IS_I915GM(dev))
1606 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1607 }
1608
1609 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1610 planea_wm, planeb_wm, cwm, srwm);
1611
1612 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1613 fwater_hi = (cwm & 0x1f);
1614
1615 /* Set request length to 8 cachelines per fetch */
1616 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1617 fwater_hi = fwater_hi | (1 << 8);
1618
1619 I915_WRITE(FW_BLC, fwater_lo);
1620 I915_WRITE(FW_BLC2, fwater_hi);
1621
5209b1f4
ID		 1622 if (enabled)
1623 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
6e3c9717 1639 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1643 4, pessimal_latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
8cfb3407 1652uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1653{
fd4daa9c 1654 uint32_t pixel_rate;
801bcfff 1655
8cfb3407 1656 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1657
1658 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1659 * adjust the pixel_rate here. */
1660
8cfb3407 1661 if (pipe_config->pch_pfit.enabled) {
801bcfff 1662 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1663 uint32_t pfit_size = pipe_config->pch_pfit.size;
1664
1665 pipe_w = pipe_config->pipe_src_w;
1666 pipe_h = pipe_config->pipe_src_h;
801bcfff 1667
801bcfff
PZ		 1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1671 pipe_w = pfit_w;
1672 if (pipe_h < pfit_h)
1673 pipe_h = pfit_h;
1674
15126882
MR		 1675 if (WARN_ON(!pfit_w || !pfit_h))
1676 return pixel_rate;
1677
801bcfff
PZ		 1678 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1679 pfit_w * pfit_h);
1680 }
1681
1682 return pixel_rate;
1683}
1684
37126462 1685/* latency must be in 0.1us units. */
23297044 1686static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1687 uint32_t latency)
1688{
1689 uint64_t ret;
1690
3312ba65
VS		 1691 if (WARN(latency == 0, "Latency value missing\n"))
1692 return UINT_MAX;
1693
801bcfff
PZ		 1694 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1695 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697 return ret;
1698}
1699
37126462 1700/* latency must be in 0.1us units. */
23297044 1701static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1702 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1703 uint32_t latency)
1704{
1705 uint32_t ret;
1706
3312ba65
VS		 1707 if (WARN(latency == 0, "Latency value missing\n"))
1708 return UINT_MAX;
15126882
MR		 1709 if (WARN_ON(!pipe_htotal))
1710 return UINT_MAX;
3312ba65 1711
801bcfff
PZ		 1712 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1713 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1714 ret = DIV_ROUND_UP(ret, 64) + 2;
1715 return ret;
1716}
1717
23297044 1718static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1719 uint8_t bytes_per_pixel)
1720{
15126882
MR		 1721 /*
1722 * Neither of these should be possible since this function shouldn't be
1723 * called if the CRTC is off or the plane is invisible. But let's be
1724 * extra paranoid to avoid a potential divide-by-zero if we screw up
1725 * elsewhere in the driver.
1726 */
1727 if (WARN_ON(!bytes_per_pixel))
1728 return 0;
1729 if (WARN_ON(!horiz_pixels))
1730 return 0;
1731
cca32e9a
PZ		 1732 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1733}
1734
820c1980 1735struct ilk_wm_maximums {
cca32e9a
PZ		 1736 uint16_t pri;
1737 uint16_t spr;
1738 uint16_t cur;
1739 uint16_t fbc;
1740};
1741
37126462
VS		 1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
7221fc33 1746static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1747 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
43d59eda 1751 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
cca32e9a
PZ		 1752 uint32_t method1, method2;
1753
7221fc33 1754 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1755 return 0;
1756
7221fc33 1757 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
cca32e9a
PZ		 1758
1759 if (!is_lp)
1760 return method1;
1761
7221fc33
MR		 1762 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1763 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1764 drm_rect_width(&pstate->dst),
1765 bpp,
cca32e9a
PZ		 1766 mem_value);
1767
1768 return min(method1, method2);
801bcfff
PZ		 1769}
1770
37126462
VS		 1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
7221fc33 1775static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1776 const struct intel_plane_state *pstate,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
43d59eda 1779 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
801bcfff
PZ		 1780 uint32_t method1, method2;
1781
7221fc33 1782 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1783 return 0;
1784
7221fc33
MR		 1785 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1788 drm_rect_width(&pstate->dst),
1789 bpp,
801bcfff
PZ		 1790 mem_value);
1791 return min(method1, method2);
1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
43d59eda
MR		 1802 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1803
7221fc33 1804 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1805 return 0;
1806
7221fc33
MR		 1807 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1808 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1809 drm_rect_width(&pstate->dst),
1810 bpp,
801bcfff
PZ		 1811 mem_value);
1812}
1813
cca32e9a 1814/* Only for WM_LP. */
7221fc33 1815static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1816 const struct intel_plane_state *pstate,
1fda9882 1817 uint32_t pri_val)
cca32e9a 1818{
43d59eda
MR		 1819 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1820
7221fc33 1821 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1822 return 0;
1823
43d59eda 1824 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
cca32e9a
PZ		 1825}
1826
158ae64f
VS		 1827static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1828{
416f4727
VS		 1829 if (INTEL_INFO(dev)->gen >= 8)
1830 return 3072;
1831 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1832 return 768;
1833 else
1834 return 512;
1835}
1836
4e975081
VS		 1837static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1838 int level, bool is_sprite)
1839{
1840 if (INTEL_INFO(dev)->gen >= 8)
1841 /* BDW primary/sprite plane watermarks */
1842 return level == 0 ? 255 : 2047;
1843 else if (INTEL_INFO(dev)->gen >= 7)
1844 /* IVB/HSW primary/sprite plane watermarks */
1845 return level == 0 ? 127 : 1023;
1846 else if (!is_sprite)
1847 /* ILK/SNB primary plane watermarks */
1848 return level == 0 ? 127 : 511;
1849 else
1850 /* ILK/SNB sprite plane watermarks */
1851 return level == 0 ? 63 : 255;
1852}
1853
1854static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1855 int level)
1856{
1857 if (INTEL_INFO(dev)->gen >= 7)
1858 return level == 0 ? 63 : 255;
1859 else
1860 return level == 0 ? 31 : 63;
1861}
1862
1863static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1864{
1865 if (INTEL_INFO(dev)->gen >= 8)
1866 return 31;
1867 else
1868 return 15;
1869}
1870
158ae64f
VS		 1871/* Calculate the maximum primary/sprite plane watermark */
1872static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1873 int level,
240264f4 1874 const struct intel_wm_config *config,
158ae64f
VS		 1875 enum intel_ddb_partitioning ddb_partitioning,
1876 bool is_sprite)
1877{
1878 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1879
1880 /* if sprites aren't enabled, sprites get nothing */
240264f4 1881 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1882 return 0;
1883
1884 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1885 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1886 fifo_size /= INTEL_INFO(dev)->num_pipes;
1887
1888 /*
1889 * For some reason the non self refresh
1890 * FIFO size is only half of the self
1891 * refresh FIFO size on ILK/SNB.
1892 */
1893 if (INTEL_INFO(dev)->gen <= 6)
1894 fifo_size /= 2;
1895 }
1896
240264f4 1897 if (config->sprites_enabled) {
158ae64f
VS		 1898 /* level 0 is always calculated with 1:1 split */
1899 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1900 if (is_sprite)
1901 fifo_size *= 5;
1902 fifo_size /= 6;
1903 } else {
1904 fifo_size /= 2;
1905 }
1906 }
1907
1908 /* clamp to max that the registers can hold */
4e975081 1909 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1910}
1911
1912/* Calculate the maximum cursor plane watermark */
1913static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1914 int level,
1915 const struct intel_wm_config *config)
158ae64f
VS		 1916{
1917 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1918 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1919 return 64;
1920
1921 /* otherwise just report max that registers can hold */
4e975081 1922 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1923}
1924
d34ff9c6 1925static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1926 int level,
1927 const struct intel_wm_config *config,
1928 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1929 struct ilk_wm_maximums *max)
158ae64f 1930{
240264f4
VS		 1931 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1932 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1933 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1934 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1935}
1936
a3cb4048
VS		 1937static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1938 int level,
1939 struct ilk_wm_maximums *max)
1940{
1941 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1942 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1943 max->cur = ilk_cursor_wm_reg_max(dev, level);
1944 max->fbc = ilk_fbc_wm_reg_max(dev);
1945}
1946
d9395655 1947static bool ilk_validate_wm_level(int level,
820c1980 1948 const struct ilk_wm_maximums *max,
d9395655 1949 struct intel_wm_level *result)
a9786a11
VS		 1950{
1951 bool ret;
1952
1953 /* already determined to be invalid? */
1954 if (!result->enable)
1955 return false;
1956
1957 result->enable = result->pri_val <= max->pri &&
1958 result->spr_val <= max->spr &&
1959 result->cur_val <= max->cur;
1960
1961 ret = result->enable;
1962
1963 /*
1964 * HACK until we can pre-compute everything,
1965 * and thus fail gracefully if LP0 watermarks
1966 * are exceeded...
1967 */
1968 if (level == 0 && !result->enable) {
1969 if (result->pri_val > max->pri)
1970 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1971 level, result->pri_val, max->pri);
1972 if (result->spr_val > max->spr)
1973 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1974 level, result->spr_val, max->spr);
1975 if (result->cur_val > max->cur)
1976 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1977 level, result->cur_val, max->cur);
1978
1979 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1980 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1981 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1982 result->enable = true;
1983 }
1984
a9786a11
VS		 1985 return ret;
1986}
1987
d34ff9c6 1988static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1989 const struct intel_crtc *intel_crtc,
6f5ddd17 1990 int level,
7221fc33 1991 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1992 struct intel_plane_state *pristate,
1993 struct intel_plane_state *sprstate,
1994 struct intel_plane_state *curstate,
1fd527cc 1995 struct intel_wm_level *result)
6f5ddd17
VS		 1996{
1997 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1998 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1999 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2000
2001 /* WM1+ latency values stored in 0.5us units */
2002 if (level > 0) {
2003 pri_latency *= 5;
2004 spr_latency *= 5;
2005 cur_latency *= 5;
2006 }
2007
86c8bbbe
MR		 2008 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2009 pri_latency, level);
2010 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2011 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2012 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 2013 result->enable = true;
2014}
2015
801bcfff 2016static uint32_t
ee91a159
MR		 2017hsw_compute_linetime_wm(struct drm_device *dev,
2018 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2019{
2020 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2021 const struct drm_display_mode *adjusted_mode =
2022 &cstate->base.adjusted_mode;
85a02deb 2023 u32 linetime, ips_linetime;
1f8eeabf 2024
ee91a159
MR		 2025 if (!cstate->base.active)
2026 return 0;
2027 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2028 return 0;
2029 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2030 return 0;
1011d8c4 2031
1f8eeabf
ED		 2032 /* The WM are computed with base on how long it takes to fill a single
2033 * row at the given clock rate, multiplied by 8.
2034 * */
124abe07
VS		 2035 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2036 adjusted_mode->crtc_clock);
2037 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2038 dev_priv->cdclk_freq);
1f8eeabf 2039
801bcfff
PZ		 2040 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2041 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2042}
2043
2af30a5c 2044static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2045{
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047
2af30a5c
PB		 2048 if (IS_GEN9(dev)) {
2049 uint32_t val;
4f947386 2050 int ret, i;
367294be 2051 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2052
2053 /* read the first set of memory latencies[0:3] */
2054 val = 0; /* data0 to be programmed to 0 for first set */
2055 mutex_lock(&dev_priv->rps.hw_lock);
2056 ret = sandybridge_pcode_read(dev_priv,
2057 GEN9_PCODE_READ_MEM_LATENCY,
2058 &val);
2059 mutex_unlock(&dev_priv->rps.hw_lock);
2060
2061 if (ret) {
2062 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2063 return;
2064 }
2065
2066 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2072 GEN9_MEM_LATENCY_LEVEL_MASK;
2073
2074 /* read the second set of memory latencies[4:7] */
2075 val = 1; /* data0 to be programmed to 1 for second set */
2076 mutex_lock(&dev_priv->rps.hw_lock);
2077 ret = sandybridge_pcode_read(dev_priv,
2078 GEN9_PCODE_READ_MEM_LATENCY,
2079 &val);
2080 mutex_unlock(&dev_priv->rps.hw_lock);
2081 if (ret) {
2082 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2083 return;
2084 }
2085
2086 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2092 GEN9_MEM_LATENCY_LEVEL_MASK;
2093
367294be 2094 /*
6f97235b
DL		 2095 * WaWmMemoryReadLatency:skl
2096 *
367294be
VK		 2097 * punit doesn't take into account the read latency so we need
2098 * to add 2us to the various latency levels we retrieve from
2099 * the punit.
2100 * - W0 is a bit special in that it's the only level that
2101 * can't be disabled if we want to have display working, so
2102 * we always add 2us there.
2103 * - For levels >=1, punit returns 0us latency when they are
2104 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2105 *
2106 * Additionally, if a level n (n > 1) has a 0us latency, all
2107 * levels m (m >= n) need to be disabled. We make sure to
2108 * sanitize the values out of the punit to satisfy this
2109 * requirement.
367294be
VK		 2110 */
2111 wm[0] += 2;
2112 for (level = 1; level <= max_level; level++)
2113 if (wm[level] != 0)
2114 wm[level] += 2;
4f947386
VK		 2115 else {
2116 for (i = level + 1; i <= max_level; i++)
2117 wm[i] = 0;
367294be 2118
4f947386
VK		 2119 break;
2120 }
2af30a5c 2121 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2122 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2123
2124 wm[0] = (sskpd >> 56) & 0xFF;
2125 if (wm[0] == 0)
2126 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2127 wm[1] = (sskpd >> 4) & 0xFF;
2128 wm[2] = (sskpd >> 12) & 0xFF;
2129 wm[3] = (sskpd >> 20) & 0x1FF;
2130 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2131 } else if (INTEL_INFO(dev)->gen >= 6) {
2132 uint32_t sskpd = I915_READ(MCH_SSKPD);
2133
2134 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2135 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2136 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2137 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2138 } else if (INTEL_INFO(dev)->gen >= 5) {
2139 uint32_t mltr = I915_READ(MLTR_ILK);
2140
2141 /* ILK primary LP0 latency is 700 ns */
2142 wm[0] = 7;
2143 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2144 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2145 }
2146}
2147
53615a5e
VS		 2148static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2149{
2150 /* ILK sprite LP0 latency is 1300 ns */
2151 if (INTEL_INFO(dev)->gen == 5)
2152 wm[0] = 13;
2153}
2154
2155static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2156{
2157 /* ILK cursor LP0 latency is 1300 ns */
2158 if (INTEL_INFO(dev)->gen == 5)
2159 wm[0] = 13;
2160
2161 /* WaDoubleCursorLP3Latency:ivb */
2162 if (IS_IVYBRIDGE(dev))
2163 wm[3] *= 2;
2164}
2165
546c81fd 2166int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2167{
26ec971e 2168 /* how many WM levels are we expecting */
b6e742f6 2169 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2170 return 7;
2171 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2172 return 4;
26ec971e 2173 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2174 return 3;
26ec971e 2175 else
ad0d6dc4
VS		 2176 return 2;
2177}
7526ed79 2178
ad0d6dc4
VS		 2179static void intel_print_wm_latency(struct drm_device *dev,
2180 const char *name,
2af30a5c 2181 const uint16_t wm[8])
ad0d6dc4
VS		 2182{
2183 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2184
2185 for (level = 0; level <= max_level; level++) {
2186 unsigned int latency = wm[level];
2187
2188 if (latency == 0) {
2189 DRM_ERROR("%s WM%d latency not provided\n",
2190 name, level);
2191 continue;
2192 }
2193
2af30a5c
PB		 2194 /*
2195 * - latencies are in us on gen9.
2196 * - before then, WM1+ latency values are in 0.5us units
2197 */
2198 if (IS_GEN9(dev))
2199 latency *= 10;
2200 else if (level > 0)
26ec971e
VS		 2201 latency *= 5;
2202
2203 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2204 name, level, wm[level],
2205 latency / 10, latency % 10);
2206 }
2207}
2208
e95a2f75
VS		 2209static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2210 uint16_t wm[5], uint16_t min)
2211{
2212 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2213
2214 if (wm[0] >= min)
2215 return false;
2216
2217 wm[0] = max(wm[0], min);
2218 for (level = 1; level <= max_level; level++)
2219 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2220
2221 return true;
2222}
2223
2224static void snb_wm_latency_quirk(struct drm_device *dev)
2225{
2226 struct drm_i915_private *dev_priv = dev->dev_private;
2227 bool changed;
2228
2229 /*
2230 * The BIOS provided WM memory latency values are often
2231 * inadequate for high resolution displays. Adjust them.
2232 */
2233 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2234 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2235 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2236
2237 if (!changed)
2238 return;
2239
2240 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2241 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2242 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2243 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2244}
2245
fa50ad61 2246static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2247{
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249
2250 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2251
2252 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2255 sizeof(dev_priv->wm.pri_latency));
2256
2257 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2258 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2259
2260 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2261 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2262 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2263
2264 if (IS_GEN6(dev))
2265 snb_wm_latency_quirk(dev);
53615a5e
VS		 2266}
2267
2af30a5c
PB		 2268static void skl_setup_wm_latency(struct drm_device *dev)
2269{
2270 struct drm_i915_private *dev_priv = dev->dev_private;
2271
2272 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2273 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2274}
2275
396e33ae
MR		 2276static bool ilk_validate_pipe_wm(struct drm_device *dev,
2277 struct intel_pipe_wm *pipe_wm)
2278{
2279 /* LP0 watermark maximums depend on this pipe alone */
2280 const struct intel_wm_config config = {
2281 .num_pipes_active = 1,
2282 .sprites_enabled = pipe_wm->sprites_enabled,
2283 .sprites_scaled = pipe_wm->sprites_scaled,
2284 };
2285 struct ilk_wm_maximums max;
2286
2287 /* LP0 watermarks always use 1/2 DDB partitioning */
2288 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2289
2290 /* At least LP0 must be valid */
2291 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2292 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2293 return false;
2294 }
2295
2296 return true;
2297}
2298
0b2ae6d7 2299/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2300static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2301 struct drm_atomic_state *state)
0b2ae6d7 2302{
86c8bbbe
MR		 2303 struct intel_pipe_wm *pipe_wm;
2304 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2305 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2306 struct intel_crtc_state *cstate = NULL;
43d59eda 2307 struct intel_plane *intel_plane;
86c8bbbe
MR		 2308 struct drm_plane_state *ps;
2309 struct intel_plane_state *pristate = NULL;
43d59eda 2310 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2311 struct intel_plane_state *curstate = NULL;
0b2ae6d7 2312 int level, max_level = ilk_wm_max_level(dev);
820c1980 2313 struct ilk_wm_maximums max;
0b2ae6d7 2314
86c8bbbe
MR		 2315 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2316 if (IS_ERR(cstate))
2317 return PTR_ERR(cstate);
2318
2319 pipe_wm = &cstate->wm.optimal.ilk;
2320
43d59eda 2321 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2322 ps = drm_atomic_get_plane_state(state,
2323 &intel_plane->base);
2324 if (IS_ERR(ps))
2325 return PTR_ERR(ps);
2326
2327 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2328 pristate = to_intel_plane_state(ps);
2329 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2330 sprstate = to_intel_plane_state(ps);
2331 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2332 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2333 }
2334
396e33ae
MR		 2335 pipe_wm->pipe_enabled = cstate->base.active;
2336 pipe_wm->sprites_enabled = sprstate->visible;
2337 pipe_wm->sprites_scaled = sprstate->visible &&
43d59eda
MR		 2338 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2339 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2340
7b39a0b7 2341 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2342 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2343 max_level = 1;
2344
2345 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
396e33ae 2346 if (pipe_wm->sprites_scaled)
7b39a0b7
VS		 2347 max_level = 0;
2348
86c8bbbe
MR		 2349 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2350 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2351
a42a5719 2352 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2353 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2354
396e33ae
MR		 2355 if (!ilk_validate_pipe_wm(dev, pipe_wm))
2356 return false;
a3cb4048
VS		 2357
2358 ilk_compute_wm_reg_maximums(dev, 1, &max);
2359
2360 for (level = 1; level <= max_level; level++) {
2361 struct intel_wm_level wm = {};
2362
86c8bbbe
MR		 2363 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2364 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2365
2366 /*
2367 * Disable any watermark level that exceeds the
2368 * register maximums since such watermarks are
2369 * always invalid.
2370 */
2371 if (!ilk_validate_wm_level(level, &max, &wm))
2372 break;
2373
2374 pipe_wm->wm[level] = wm;
2375 }
2376
86c8bbbe 2377 return 0;
0b2ae6d7
VS		 2378}
2379
396e33ae
MR		 2380/*
2381 * Build a set of 'intermediate' watermark values that satisfy both the old
2382 * state and the new state. These can be programmed to the hardware
2383 * immediately.
2384 */
2385static int ilk_compute_intermediate_wm(struct drm_device *dev,
2386 struct intel_crtc *intel_crtc,
2387 struct intel_crtc_state *newstate)
2388{
2389 struct intel_pipe_wm *a = &newstate->wm.intermediate;
2390 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2391 int level, max_level = ilk_wm_max_level(dev);
2392
2393 /*
2394 * Start with the final, target watermarks, then combine with the
2395 * currently active watermarks to get values that are safe both before
2396 * and after the vblank.
2397 */
2398 *a = newstate->wm.optimal.ilk;
2399 a->pipe_enabled |= b->pipe_enabled;
2400 a->sprites_enabled |= b->sprites_enabled;
2401 a->sprites_scaled |= b->sprites_scaled;
2402
2403 for (level = 0; level <= max_level; level++) {
2404 struct intel_wm_level *a_wm = &a->wm[level];
2405 const struct intel_wm_level *b_wm = &b->wm[level];
2406
2407 a_wm->enable &= b_wm->enable;
2408 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2409 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2410 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2411 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2412 }
2413
2414 /*
2415 * We need to make sure that these merged watermark values are
2416 * actually a valid configuration themselves. If they're not,
2417 * there's no safe way to transition from the old state to
2418 * the new state, so we need to fail the atomic transaction.
2419 */
2420 if (!ilk_validate_pipe_wm(dev, a))
2421 return -EINVAL;
2422
2423 /*
2424 * If our intermediate WM are identical to the final WM, then we can
2425 * omit the post-vblank programming; only update if it's different.
2426 */
2427 if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) != 0)
2428 newstate->wm.need_postvbl_update = false;
2429
2430 return 0;
2431}
2432
0b2ae6d7
VS		 2433/*
2434 * Merge the watermarks from all active pipes for a specific level.
2435 */
2436static void ilk_merge_wm_level(struct drm_device *dev,
2437 int level,
2438 struct intel_wm_level *ret_wm)
2439{
2440 const struct intel_crtc *intel_crtc;
2441
d52fea5b
VS		 2442 ret_wm->enable = true;
2443
d3fcc808 2444 for_each_intel_crtc(dev, intel_crtc) {
396e33ae 2445 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2446 const struct intel_wm_level *wm = &active->wm[level];
2447
2448 if (!active->pipe_enabled)
2449 continue;
0b2ae6d7 2450
d52fea5b
VS		 2451 /*
2452 * The watermark values may have been used in the past,
2453 * so we must maintain them in the registers for some
2454 * time even if the level is now disabled.
2455 */
0b2ae6d7 2456 if (!wm->enable)
d52fea5b 2457 ret_wm->enable = false;
0b2ae6d7
VS		 2458
2459 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2460 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2461 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2462 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2463 }
0b2ae6d7
VS		 2464}
2465
2466/*
2467 * Merge all low power watermarks for all active pipes.
2468 */
2469static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2470 const struct intel_wm_config *config,
820c1980 2471 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2472 struct intel_pipe_wm *merged)
2473{
7733b49b 2474 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2475 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2476 int last_enabled_level = max_level;
0b2ae6d7 2477
0ba22e26
VS		 2478 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2479 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2480 config->num_pipes_active > 1)
2481 return;
2482
6c8b6c28
VS		 2483 /* ILK: FBC WM must be disabled always */
2484 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2485
2486 /* merge each WM1+ level */
2487 for (level = 1; level <= max_level; level++) {
2488 struct intel_wm_level *wm = &merged->wm[level];
2489
2490 ilk_merge_wm_level(dev, level, wm);
2491
d52fea5b
VS		 2492 if (level > last_enabled_level)
2493 wm->enable = false;
2494 else if (!ilk_validate_wm_level(level, max, wm))
2495 /* make sure all following levels get disabled */
2496 last_enabled_level = level - 1;
0b2ae6d7
VS		 2497
2498 /*
2499 * The spec says it is preferred to disable
2500 * FBC WMs instead of disabling a WM level.
2501 */
2502 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2503 if (wm->enable)
2504 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2505 wm->fbc_val = 0;
2506 }
2507 }
6c8b6c28
VS		 2508
2509 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2510 /*
2511 * FIXME this is racy. FBC might get enabled later.
2512 * What we should check here is whether FBC can be
2513 * enabled sometime later.
2514 */
7733b49b 2515 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2516 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2517 for (level = 2; level <= max_level; level++) {
2518 struct intel_wm_level *wm = &merged->wm[level];
2519
2520 wm->enable = false;
2521 }
2522 }
0b2ae6d7
VS		 2523}
2524
b380ca3c
VS		 2525static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2526{
2527 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2528 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2529}
2530
a68d68ee
VS		 2531/* The value we need to program into the WM_LPx latency field */
2532static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2533{
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535
a42a5719 2536 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2537 return 2 * level;
2538 else
2539 return dev_priv->wm.pri_latency[level];
2540}
2541
820c1980 2542static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2543 const struct intel_pipe_wm *merged,
609cedef 2544 enum intel_ddb_partitioning partitioning,
820c1980 2545 struct ilk_wm_values *results)
801bcfff 2546{
0b2ae6d7
VS		 2547 struct intel_crtc *intel_crtc;
2548 int level, wm_lp;
cca32e9a 2549
0362c781 2550 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2551 results->partitioning = partitioning;
cca32e9a 2552
0b2ae6d7 2553 /* LP1+ register values */
cca32e9a 2554 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2555 const struct intel_wm_level *r;
801bcfff 2556
b380ca3c 2557 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2558
0362c781 2559 r = &merged->wm[level];
cca32e9a 2560
d52fea5b
VS		 2561 /*
2562 * Maintain the watermark values even if the level is
2563 * disabled. Doing otherwise could cause underruns.
2564 */
2565 results->wm_lp[wm_lp - 1] =
a68d68ee 2566 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2567 (r->pri_val << WM1_LP_SR_SHIFT) |
2568 r->cur_val;
2569
d52fea5b
VS		 2570 if (r->enable)
2571 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2572
416f4727
VS		 2573 if (INTEL_INFO(dev)->gen >= 8)
2574 results->wm_lp[wm_lp - 1] |=
2575 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2576 else
2577 results->wm_lp[wm_lp - 1] |=
2578 r->fbc_val << WM1_LP_FBC_SHIFT;
2579
d52fea5b
VS		 2580 /*
2581 * Always set WM1S_LP_EN when spr_val != 0, even if the
2582 * level is disabled. Doing otherwise could cause underruns.
2583 */
6cef2b8a
VS		 2584 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2585 WARN_ON(wm_lp != 1);
2586 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2587 } else
2588 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2589 }
801bcfff 2590
0b2ae6d7 2591 /* LP0 register values */
d3fcc808 2592 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2593 enum pipe pipe = intel_crtc->pipe;
396e33ae
MR		 2594 const struct intel_wm_level *r =
2595 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2596
2597 if (WARN_ON(!r->enable))
2598 continue;
2599
396e33ae 2600 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2601
0b2ae6d7
VS		 2602 results->wm_pipe[pipe] =
2603 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2604 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2605 r->cur_val;
801bcfff
PZ		 2606 }
2607}
2608
861f3389
PZ		 2609/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2610 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2611static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2612 struct intel_pipe_wm *r1,
2613 struct intel_pipe_wm *r2)
861f3389 2614{
198a1e9b
VS		 2615 int level, max_level = ilk_wm_max_level(dev);
2616 int level1 = 0, level2 = 0;
861f3389 2617
198a1e9b
VS		 2618 for (level = 1; level <= max_level; level++) {
2619 if (r1->wm[level].enable)
2620 level1 = level;
2621 if (r2->wm[level].enable)
2622 level2 = level;
861f3389
PZ		 2623 }
2624
198a1e9b
VS		 2625 if (level1 == level2) {
2626 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2627 return r2;
2628 else
2629 return r1;
198a1e9b 2630 } else if (level1 > level2) {
861f3389
PZ		 2631 return r1;
2632 } else {
2633 return r2;
2634 }
2635}
2636
49a687c4
VS		 2637/* dirty bits used to track which watermarks need changes */
2638#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2639#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2640#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2641#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2642#define WM_DIRTY_FBC (1 << 24)
2643#define WM_DIRTY_DDB (1 << 25)
2644
055e393f 2645static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2646 const struct ilk_wm_values *old,
2647 const struct ilk_wm_values *new)
49a687c4
VS		 2648{
2649 unsigned int dirty = 0;
2650 enum pipe pipe;
2651 int wm_lp;
2652
055e393f 2653 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2654 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2655 dirty |= WM_DIRTY_LINETIME(pipe);
2656 /* Must disable LP1+ watermarks too */
2657 dirty |= WM_DIRTY_LP_ALL;
2658 }
2659
2660 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2661 dirty |= WM_DIRTY_PIPE(pipe);
2662 /* Must disable LP1+ watermarks too */
2663 dirty |= WM_DIRTY_LP_ALL;
2664 }
2665 }
2666
2667 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2668 dirty |= WM_DIRTY_FBC;
2669 /* Must disable LP1+ watermarks too */
2670 dirty |= WM_DIRTY_LP_ALL;
2671 }
2672
2673 if (old->partitioning != new->partitioning) {
2674 dirty |= WM_DIRTY_DDB;
2675 /* Must disable LP1+ watermarks too */
2676 dirty |= WM_DIRTY_LP_ALL;
2677 }
2678
2679 /* LP1+ watermarks already deemed dirty, no need to continue */
2680 if (dirty & WM_DIRTY_LP_ALL)
2681 return dirty;
2682
2683 /* Find the lowest numbered LP1+ watermark in need of an update... */
2684 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2685 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2686 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2687 break;
2688 }
2689
2690 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2691 for (; wm_lp <= 3; wm_lp++)
2692 dirty |= WM_DIRTY_LP(wm_lp);
2693
2694 return dirty;
2695}
2696
8553c18e
VS		 2697static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2698 unsigned int dirty)
801bcfff 2699{
820c1980 2700 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2701 bool changed = false;
801bcfff 2702
facd619b
VS		 2703 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2704 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2705 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2706 changed = true;
facd619b
VS		 2707 }
2708 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2709 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2710 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2711 changed = true;
facd619b
VS		 2712 }
2713 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2714 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2716 changed = true;
facd619b 2717 }
801bcfff 2718
facd619b
VS		 2719 /*
2720 * Don't touch WM1S_LP_EN here.
2721 * Doing so could cause underruns.
2722 */
6cef2b8a 2723
8553c18e
VS		 2724 return changed;
2725}
2726
2727/*
2728 * The spec says we shouldn't write when we don't need, because every write
2729 * causes WMs to be re-evaluated, expending some power.
2730 */
820c1980
ID		 2731static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2732 struct ilk_wm_values *results)
8553c18e
VS		 2733{
2734 struct drm_device *dev = dev_priv->dev;
820c1980 2735 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2736 unsigned int dirty;
2737 uint32_t val;
2738
055e393f 2739 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2740 if (!dirty)
2741 return;
2742
2743 _ilk_disable_lp_wm(dev_priv, dirty);
2744
49a687c4 2745 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2746 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2747 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2748 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2749 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2750 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2751
49a687c4 2752 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2753 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2754 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2755 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2756 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2757 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2758
49a687c4 2759 if (dirty & WM_DIRTY_DDB) {
a42a5719 2760 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2761 val = I915_READ(WM_MISC);
2762 if (results->partitioning == INTEL_DDB_PART_1_2)
2763 val &= ~WM_MISC_DATA_PARTITION_5_6;
2764 else
2765 val |= WM_MISC_DATA_PARTITION_5_6;
2766 I915_WRITE(WM_MISC, val);
2767 } else {
2768 val = I915_READ(DISP_ARB_CTL2);
2769 if (results->partitioning == INTEL_DDB_PART_1_2)
2770 val &= ~DISP_DATA_PARTITION_5_6;
2771 else
2772 val |= DISP_DATA_PARTITION_5_6;
2773 I915_WRITE(DISP_ARB_CTL2, val);
2774 }
1011d8c4
PZ		 2775 }
2776
49a687c4 2777 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2778 val = I915_READ(DISP_ARB_CTL);
2779 if (results->enable_fbc_wm)
2780 val &= ~DISP_FBC_WM_DIS;
2781 else
2782 val |= DISP_FBC_WM_DIS;
2783 I915_WRITE(DISP_ARB_CTL, val);
2784 }
2785
954911eb
ID		 2786 if (dirty & WM_DIRTY_LP(1) &&
2787 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2788 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2789
2790 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2791 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2792 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2793 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2794 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2795 }
801bcfff 2796
facd619b 2797 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2798 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2799 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2800 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2801 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2802 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2803
2804 dev_priv->wm.hw = *results;
801bcfff
PZ		 2805}
2806
396e33ae 2807bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2808{
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810
2811 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2812}
2813
b9cec075
DL		 2814/*
2815 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2816 * different active planes.
2817 */
2818
2819#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2820#define BXT_DDB_SIZE 512
b9cec075 2821
024c9045
MR		 2822/*
2823 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2824 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2825 * other universal planes are in indices 1..n. Note that this may leave unused
2826 * indices between the top "sprite" plane and the cursor.
2827 */
2828static int
2829skl_wm_plane_id(const struct intel_plane *plane)
2830{
2831 switch (plane->base.type) {
2832 case DRM_PLANE_TYPE_PRIMARY:
2833 return 0;
2834 case DRM_PLANE_TYPE_CURSOR:
2835 return PLANE_CURSOR;
2836 case DRM_PLANE_TYPE_OVERLAY:
2837 return plane->plane + 1;
2838 default:
2839 MISSING_CASE(plane->base.type);
2840 return plane->plane;
2841 }
2842}
2843
b9cec075
DL		 2844static void
2845skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2846 const struct intel_crtc_state *cstate,
b9cec075 2847 const struct intel_wm_config *config,
b9cec075
DL		 2848 struct skl_ddb_entry *alloc /* out */)
2849{
024c9045 2850 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2851 struct drm_crtc *crtc;
2852 unsigned int pipe_size, ddb_size;
2853 int nth_active_pipe;
2854
024c9045 2855 if (!cstate->base.active) {
b9cec075
DL		 2856 alloc->start = 0;
2857 alloc->end = 0;
2858 return;
2859 }
2860
43d735a6
DL		 2861 if (IS_BROXTON(dev))
2862 ddb_size = BXT_DDB_SIZE;
2863 else
2864 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2865
2866 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2867
2868 nth_active_pipe = 0;
2869 for_each_crtc(dev, crtc) {
3ef00284 2870 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2871 continue;
2872
2873 if (crtc == for_crtc)
2874 break;
2875
2876 nth_active_pipe++;
2877 }
2878
2879 pipe_size = ddb_size / config->num_pipes_active;
2880 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2881 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2882}
2883
2884static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2885{
2886 if (config->num_pipes_active == 1)
2887 return 32;
2888
2889 return 8;
2890}
2891
a269c583
DL		 2892static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2893{
2894 entry->start = reg & 0x3ff;
2895 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2896 if (entry->end)
2897 entry->end += 1;
a269c583
DL		 2898}
2899
08db6652
DL		 2900void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2901 struct skl_ddb_allocation *ddb /* out */)
a269c583 2902{
a269c583
DL		 2903 enum pipe pipe;
2904 int plane;
2905 u32 val;
2906
b10f1b20
ML		 2907 memset(ddb, 0, sizeof(*ddb));
2908
a269c583 2909 for_each_pipe(dev_priv, pipe) {
b10f1b20
ML		 2910 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2911 continue;
2912
dd740780 2913 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2914 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2915 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2916 val);
2917 }
2918
2919 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2920 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2921 val);
a269c583
DL		 2922 }
2923}
2924
b9cec075 2925static unsigned int
024c9045
MR		 2926skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2927 const struct drm_plane_state *pstate,
2928 int y)
b9cec075 2929{
024c9045
MR		 2930 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2931 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2932
2933 /* for planar format */
024c9045 2934 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2935 if (y) /* y-plane data rate */
024c9045
MR		 2936 return intel_crtc->config->pipe_src_w *
2937 intel_crtc->config->pipe_src_h *
2938 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2939 else /* uv-plane data rate */
024c9045
MR		 2940 return (intel_crtc->config->pipe_src_w/2) *
2941 (intel_crtc->config->pipe_src_h/2) *
2942 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2943 }
2944
2945 /* for packed formats */
024c9045
MR		 2946 return intel_crtc->config->pipe_src_w *
2947 intel_crtc->config->pipe_src_h *
2948 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2949}
2950
2951/*
2952 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2953 * a 8192x4096@32bpp framebuffer:
2954 * 3 * 4096 * 8192 * 4 < 2^32
2955 */
2956static unsigned int
024c9045 2957skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2958{
024c9045
MR		 2959 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2960 struct drm_device *dev = intel_crtc->base.dev;
2961 const struct intel_plane *intel_plane;
b9cec075 2962 unsigned int total_data_rate = 0;
b9cec075 2963
024c9045
MR		 2964 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2965 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2966
024c9045 2967 if (pstate->fb == NULL)
b9cec075
DL		 2968 continue;
2969
024c9045
MR		 2970 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2971 continue;
2972
2973 /* packed/uv */
2974 total_data_rate += skl_plane_relative_data_rate(cstate,
2975 pstate,
2976 0);
2977
2978 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2979 /* y-plane */
2980 total_data_rate += skl_plane_relative_data_rate(cstate,
2981 pstate,
2982 1);
b9cec075
DL		 2983 }
2984
2985 return total_data_rate;
2986}
2987
2988static void
024c9045 2989skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2990 struct skl_ddb_allocation *ddb /* out */)
2991{
024c9045 2992 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2993 struct drm_device *dev = crtc->dev;
aa363136
MR		 2994 struct drm_i915_private *dev_priv = to_i915(dev);
2995 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2997 struct intel_plane *intel_plane;
b9cec075 2998 enum pipe pipe = intel_crtc->pipe;
34bb56af 2999 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3000 uint16_t alloc_size, start, cursor_blocks;
80958155 3001 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 3002 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 3003 unsigned int total_data_rate;
b9cec075 3004
024c9045 3005 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 3006 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3007 if (alloc_size == 0) {
3008 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 3009 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3010 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 3011 return;
3012 }
3013
3014 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 3015 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3016 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3017
3018 alloc_size -= cursor_blocks;
34bb56af 3019 alloc->end -= cursor_blocks;
b9cec075 3020
80958155 3021 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 3022 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3023 struct drm_plane *plane = &intel_plane->base;
3024 struct drm_framebuffer *fb = plane->state->fb;
3025 int id = skl_wm_plane_id(intel_plane);
80958155 3026
024c9045
MR		 3027 if (fb == NULL)
3028 continue;
3029 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 3030 continue;
3031
024c9045
MR		 3032 minimum[id] = 8;
3033 alloc_size -= minimum[id];
3034 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3035 alloc_size -= y_minimum[id];
80958155
DL		 3036 }
3037
b9cec075 3038 /*
80958155
DL		 3039 * 2. Distribute the remaining space in proportion to the amount of
3040 * data each plane needs to fetch from memory.
b9cec075
DL		 3041 *
3042 * FIXME: we may not allocate every single block here.
3043 */
024c9045 3044 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 3045
34bb56af 3046 start = alloc->start;
024c9045
MR		 3047 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3048 struct drm_plane *plane = &intel_plane->base;
3049 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 3050 unsigned int data_rate, y_data_rate;
3051 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3052 int id = skl_wm_plane_id(intel_plane);
b9cec075 3053
024c9045
MR		 3054 if (pstate->fb == NULL)
3055 continue;
3056 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 3057 continue;
3058
024c9045 3059 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3060
3061 /*
2cd601c6 3062 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3063 * promote the expression to 64 bits to avoid overflowing, the
3064 * result is < available as data_rate / total_data_rate < 1
3065 */
024c9045 3066 plane_blocks = minimum[id];
80958155
DL		 3067 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3068 total_data_rate);
b9cec075 3069
024c9045
MR		 3070 ddb->plane[pipe][id].start = start;
3071 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3072
3073 start += plane_blocks;
2cd601c6
CK		 3074
3075 /*
3076 * allocation for y_plane part of planar format:
3077 */
024c9045
MR		 3078 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3079 y_data_rate = skl_plane_relative_data_rate(cstate,
3080 pstate,
3081 1);
3082 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3083 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3084 total_data_rate);
3085
024c9045
MR		 3086 ddb->y_plane[pipe][id].start = start;
3087 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3088
3089 start += y_plane_blocks;
3090 }
3091
b9cec075
DL		 3092 }
3093
3094}
3095
5cec258b 3096static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3097{
3098 /* TODO: Take into account the scalers once we support them */
2d112de7 3099 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3100}
3101
3102/*
3103 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3104 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3105 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3106 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3107*/
3108static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3109 uint32_t latency)
3110{
3111 uint32_t wm_intermediate_val, ret;
3112
3113 if (latency == 0)
3114 return UINT_MAX;
3115
d4c2aa60 3116 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3117 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3118
3119 return ret;
3120}
3121
3122static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3123 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3124 uint64_t tiling, uint32_t latency)
2d41c0b5 3125{
d4c2aa60
TU		 3126 uint32_t ret;
3127 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3128 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3129
3130 if (latency == 0)
3131 return UINT_MAX;
3132
3133 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3134
3135 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3136 tiling == I915_FORMAT_MOD_Yf_TILED) {
3137 plane_bytes_per_line *= 4;
3138 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3139 plane_blocks_per_line /= 4;
3140 } else {
3141 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3142 }
3143
2d41c0b5
PB		 3144 wm_intermediate_val = latency * pixel_rate;
3145 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3146 plane_blocks_per_line;
2d41c0b5
PB		 3147
3148 return ret;
3149}
3150
2d41c0b5
PB		 3151static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3152 const struct intel_crtc *intel_crtc)
3153{
3154 struct drm_device *dev = intel_crtc->base.dev;
3155 struct drm_i915_private *dev_priv = dev->dev_private;
3156 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3157
e6d90023
KM		 3158 /*
3159 * If ddb allocation of pipes changed, it may require recalculation of
3160 * watermarks
3161 */
3162 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3163 return true;
3164
3165 return false;
3166}
3167
d4c2aa60 3168static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3169 struct intel_crtc_state *cstate,
3170 struct intel_plane *intel_plane,
afb024aa 3171 uint16_t ddb_allocation,
d4c2aa60 3172 int level,
afb024aa
DL		 3173 uint16_t *out_blocks, /* out */
3174 uint8_t *out_lines /* out */)
2d41c0b5 3175{
024c9045
MR		 3176 struct drm_plane *plane = &intel_plane->base;
3177 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3178 uint32_t latency = dev_priv->wm.skl_latency[level];
3179 uint32_t method1, method2;
3180 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3181 uint32_t res_blocks, res_lines;
3182 uint32_t selected_result;
2cd601c6 3183 uint8_t bytes_per_pixel;
2d41c0b5 3184
024c9045 3185 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3186 return false;
3187
024c9045
MR		 3188 bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3189 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
2cd601c6 3190 bytes_per_pixel,
d4c2aa60 3191 latency);
024c9045
MR		 3192 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3193 cstate->base.adjusted_mode.crtc_htotal,
3194 cstate->pipe_src_w,
2cd601c6 3195 bytes_per_pixel,
024c9045 3196 fb->modifier[0],
d4c2aa60 3197 latency);
2d41c0b5 3198
024c9045 3199 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
d4c2aa60 3200 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3201
024c9045
MR		 3202 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3203 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3204 uint32_t min_scanlines = 4;
3205 uint32_t y_tile_minimum;
024c9045
MR		 3206 if (intel_rotation_90_or_270(plane->state->rotation)) {
3207 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3208 drm_format_plane_cpp(fb->pixel_format, 1) :
3209 drm_format_plane_cpp(fb->pixel_format, 0);
3210
3211 switch (bpp) {
1fc0a8f7
TU		 3212 case 1:
3213 min_scanlines = 16;
3214 break;
3215 case 2:
3216 min_scanlines = 8;
3217 break;
3218 case 8:
3219 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3220 }
1fc0a8f7
TU		 3221 }
3222 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3223 selected_result = max(method2, y_tile_minimum);
3224 } else {
3225 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3226 selected_result = min(method1, method2);
3227 else
3228 selected_result = method1;
3229 }
2d41c0b5 3230
d4c2aa60
TU		 3231 res_blocks = selected_result + 1;
3232 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3233
0fda6568 3234 if (level >= 1 && level <= 7) {
024c9045
MR		 3235 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3236 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3237 res_lines += 4;
3238 else
3239 res_blocks++;
3240 }
e6d66171 3241
d4c2aa60 3242 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3243 return false;
3244
3245 *out_blocks = res_blocks;
3246 *out_lines = res_lines;
2d41c0b5
PB		 3247
3248 return true;
3249}
3250
3251static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3252 struct skl_ddb_allocation *ddb,
024c9045 3253 struct intel_crtc_state *cstate,
2d41c0b5 3254 int level,
2d41c0b5
PB		 3255 struct skl_wm_level *result)
3256{
024c9045
MR		 3257 struct drm_device *dev = dev_priv->dev;
3258 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3259 struct intel_plane *intel_plane;
2d41c0b5 3260 uint16_t ddb_blocks;
024c9045
MR		 3261 enum pipe pipe = intel_crtc->pipe;
3262
3263 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3264 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3265
2d41c0b5
PB		 3266 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3267
d4c2aa60 3268 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3269 cstate,
3270 intel_plane,
2d41c0b5 3271 ddb_blocks,
d4c2aa60 3272 level,
2d41c0b5
PB		 3273 &result->plane_res_b[i],
3274 &result->plane_res_l[i]);
3275 }
2d41c0b5
PB		 3276}
3277
407b50f3 3278static uint32_t
024c9045 3279skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3280{
024c9045 3281 if (!cstate->base.active)
407b50f3
DL		 3282 return 0;
3283
024c9045 3284 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3285 return 0;
407b50f3 3286
024c9045
MR		 3287 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3288 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3289}
3290
024c9045 3291static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3292 struct skl_wm_level *trans_wm /* out */)
407b50f3 3293{
024c9045 3294 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3296 struct intel_plane *intel_plane;
9414f563 3297
024c9045 3298 if (!cstate->base.active)
407b50f3 3299 return;
9414f563
DL		 3300
3301 /* Until we know more, just disable transition WMs */
024c9045
MR		 3302 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3303 int i = skl_wm_plane_id(intel_plane);
3304
9414f563 3305 trans_wm->plane_en[i] = false;
024c9045 3306 }
407b50f3
DL		 3307}
3308
024c9045 3309static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3310 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3311 struct skl_pipe_wm *pipe_wm)
3312{
024c9045 3313 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3314 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3315 int level, max_level = ilk_wm_max_level(dev);
3316
3317 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3318 skl_compute_wm_level(dev_priv, ddb, cstate,
3319 level, &pipe_wm->wm[level]);
2d41c0b5 3320 }
024c9045 3321 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3322
024c9045 3323 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3324}
3325
3326static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3327 struct skl_pipe_wm *p_wm,
3328 struct skl_wm_values *r,
3329 struct intel_crtc *intel_crtc)
3330{
3331 int level, max_level = ilk_wm_max_level(dev);
3332 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3333 uint32_t temp;
3334 int i;
2d41c0b5
PB		 3335
3336 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3337 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3338 temp = 0;
2d41c0b5
PB		 3339
3340 temp |= p_wm->wm[level].plane_res_l[i] <<
3341 PLANE_WM_LINES_SHIFT;
3342 temp |= p_wm->wm[level].plane_res_b[i];
3343 if (p_wm->wm[level].plane_en[i])
3344 temp |= PLANE_WM_EN;
3345
3346 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3347 }
3348
3349 temp = 0;
2d41c0b5 3350
4969d33e
MR		 3351 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3352 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3353
4969d33e 3354 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3355 temp |= PLANE_WM_EN;
3356
4969d33e 3357 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3358
3359 }
3360
9414f563
DL		 3361 /* transition WMs */
3362 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3363 temp = 0;
3364 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3365 temp |= p_wm->trans_wm.plane_res_b[i];
3366 if (p_wm->trans_wm.plane_en[i])
3367 temp |= PLANE_WM_EN;
3368
3369 r->plane_trans[pipe][i] = temp;
3370 }
3371
3372 temp = 0;
4969d33e
MR		 3373 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3374 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3375 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3376 temp |= PLANE_WM_EN;
3377
4969d33e 3378 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3379
2d41c0b5
PB		 3380 r->wm_linetime[pipe] = p_wm->linetime;
3381}
3382
f0f59a00
VS		 3383static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3384 i915_reg_t reg,
16160e3d
DL		 3385 const struct skl_ddb_entry *entry)
3386{
3387 if (entry->end)
3388 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3389 else
3390 I915_WRITE(reg, 0);
3391}
3392
2d41c0b5
PB		 3393static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3394 const struct skl_wm_values *new)
3395{
3396 struct drm_device *dev = dev_priv->dev;
3397 struct intel_crtc *crtc;
3398
19c8054c 3399 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3400 int i, level, max_level = ilk_wm_max_level(dev);
3401 enum pipe pipe = crtc->pipe;
3402
5d374d96
DL		 3403 if (!new->dirty[pipe])
3404 continue;
8211bd5b 3405
5d374d96 3406 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3407
5d374d96
DL		 3408 for (level = 0; level <= max_level; level++) {
3409 for (i = 0; i < intel_num_planes(crtc); i++)
3410 I915_WRITE(PLANE_WM(pipe, i, level),
3411 new->plane[pipe][i][level]);
3412 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3413 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3414 }
5d374d96
DL		 3415 for (i = 0; i < intel_num_planes(crtc); i++)
3416 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3417 new->plane_trans[pipe][i]);
4969d33e
MR		 3418 I915_WRITE(CUR_WM_TRANS(pipe),
3419 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3420
2cd601c6 3421 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3422 skl_ddb_entry_write(dev_priv,
3423 PLANE_BUF_CFG(pipe, i),
3424 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3425 skl_ddb_entry_write(dev_priv,
3426 PLANE_NV12_BUF_CFG(pipe, i),
3427 &new->ddb.y_plane[pipe][i]);
3428 }
5d374d96
DL		 3429
3430 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3431 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3432 }
2d41c0b5
PB		 3433}
3434
0e8fb7ba
DL		 3435/*
3436 * When setting up a new DDB allocation arrangement, we need to correctly
3437 * sequence the times at which the new allocations for the pipes are taken into
3438 * account or we'll have pipes fetching from space previously allocated to
3439 * another pipe.
3440 *
3441 * Roughly the sequence looks like:
3442 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3443 * overlapping with a previous light-up pipe (another way to put it is:
3444 * pipes with their new allocation strickly included into their old ones).
3445 * 2. re-allocate the other pipes that get their allocation reduced
3446 * 3. allocate the pipes having their allocation increased
3447 *
3448 * Steps 1. and 2. are here to take care of the following case:
3449 * - Initially DDB looks like this:
3450 * | B | C |
3451 * - enable pipe A.
3452 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3453 * allocation
3454 * | A | B | C |
3455 *
3456 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3457 */
3458
d21b795c
DL		 3459static void
3460skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3461{
0e8fb7ba
DL		 3462 int plane;
3463
d21b795c
DL		 3464 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3465
dd740780 3466 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3467 I915_WRITE(PLANE_SURF(pipe, plane),
3468 I915_READ(PLANE_SURF(pipe, plane)));
3469 }
3470 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3471}
3472
3473static bool
3474skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3475 const struct skl_ddb_allocation *new,
3476 enum pipe pipe)
3477{
3478 uint16_t old_size, new_size;
3479
3480 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3481 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3482
3483 return old_size != new_size &&
3484 new->pipe[pipe].start >= old->pipe[pipe].start &&
3485 new->pipe[pipe].end <= old->pipe[pipe].end;
3486}
3487
3488static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3489 struct skl_wm_values *new_values)
3490{
3491 struct drm_device *dev = dev_priv->dev;
3492 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3493 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3494 struct intel_crtc *crtc;
3495 enum pipe pipe;
3496
3497 new_ddb = &new_values->ddb;
3498 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3499
3500 /*
3501 * First pass: flush the pipes with the new allocation contained into
3502 * the old space.
3503 *
3504 * We'll wait for the vblank on those pipes to ensure we can safely
3505 * re-allocate the freed space without this pipe fetching from it.
3506 */
3507 for_each_intel_crtc(dev, crtc) {
3508 if (!crtc->active)
3509 continue;
3510
3511 pipe = crtc->pipe;
3512
3513 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3514 continue;
3515
d21b795c 3516 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3517 intel_wait_for_vblank(dev, pipe);
3518
3519 reallocated[pipe] = true;
3520 }
3521
3522
3523 /*
3524 * Second pass: flush the pipes that are having their allocation
3525 * reduced, but overlapping with a previous allocation.
3526 *
3527 * Here as well we need to wait for the vblank to make sure the freed
3528 * space is not used anymore.
3529 */
3530 for_each_intel_crtc(dev, crtc) {
3531 if (!crtc->active)
3532 continue;
3533
3534 pipe = crtc->pipe;
3535
3536 if (reallocated[pipe])
3537 continue;
3538
3539 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3540 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3541 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3542 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3543 reallocated[pipe] = true;
0e8fb7ba 3544 }
0e8fb7ba
DL		 3545 }
3546
3547 /*
3548 * Third pass: flush the pipes that got more space allocated.
3549 *
3550 * We don't need to actively wait for the update here, next vblank
3551 * will just get more DDB space with the correct WM values.
3552 */
3553 for_each_intel_crtc(dev, crtc) {
3554 if (!crtc->active)
3555 continue;
3556
3557 pipe = crtc->pipe;
3558
3559 /*
3560 * At this point, only the pipes more space than before are
3561 * left to re-allocate.
3562 */
3563 if (reallocated[pipe])
3564 continue;
3565
d21b795c 3566 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3567 }
3568}
3569
2d41c0b5 3570static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3571 struct skl_ddb_allocation *ddb, /* out */
3572 struct skl_pipe_wm *pipe_wm /* out */)
3573{
3574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3575 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3576
aa363136 3577 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3578 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3579
4e0963c7 3580 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3581 return false;
3582
4e0963c7 3583 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3584
2d41c0b5
PB		 3585 return true;
3586}
3587
3588static void skl_update_other_pipe_wm(struct drm_device *dev,
3589 struct drm_crtc *crtc,
2d41c0b5
PB		 3590 struct skl_wm_values *r)
3591{
3592 struct intel_crtc *intel_crtc;
3593 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3594
3595 /*
3596 * If the WM update hasn't changed the allocation for this_crtc (the
3597 * crtc we are currently computing the new WM values for), other
3598 * enabled crtcs will keep the same allocation and we don't need to
3599 * recompute anything for them.
3600 */
3601 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3602 return;
3603
3604 /*
3605 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3606 * other active pipes need new DDB allocation and WM values.
3607 */
19c8054c 3608 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3609 struct skl_pipe_wm pipe_wm = {};
3610 bool wm_changed;
3611
3612 if (this_crtc->pipe == intel_crtc->pipe)
3613 continue;
3614
3615 if (!intel_crtc->active)
3616 continue;
3617
aa363136 3618 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3619 &r->ddb, &pipe_wm);
3620
3621 /*
3622 * If we end up re-computing the other pipe WM values, it's
3623 * because it was really needed, so we expect the WM values to
3624 * be different.
3625 */
3626 WARN_ON(!wm_changed);
3627
024c9045 3628 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3629 r->dirty[intel_crtc->pipe] = true;
3630 }
3631}
3632
adda50b8
BP		 3633static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3634{
3635 watermarks->wm_linetime[pipe] = 0;
3636 memset(watermarks->plane[pipe], 0,
3637 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3638 memset(watermarks->plane_trans[pipe],
3639 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3640 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3641
3642 /* Clear ddb entries for pipe */
3643 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3644 memset(&watermarks->ddb.plane[pipe], 0,
3645 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3646 memset(&watermarks->ddb.y_plane[pipe], 0,
3647 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3648 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3649 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3650
3651}
3652
2d41c0b5
PB		 3653static void skl_update_wm(struct drm_crtc *crtc)
3654{
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 struct drm_device *dev = crtc->dev;
3657 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3658 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3659 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3660 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3661
adda50b8
BP		 3662
3663 /* Clear all dirty flags */
3664 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3665
3666 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3667
aa363136 3668 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3669 return;
3670
4e0963c7 3671 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3672 results->dirty[intel_crtc->pipe] = true;
3673
aa363136 3674 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3675 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3676 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3677
3678 /* store the new configuration */
3679 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3680}
3681
396e33ae 3682static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3683{
396e33ae 3684 struct drm_device *dev = dev_priv->dev;
b9d5c839 3685 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3686 struct ilk_wm_maximums max;
aa363136 3687 struct intel_wm_config *config = &dev_priv->wm.config;
820c1980 3688 struct ilk_wm_values results = {};
77c122bc 3689 enum intel_ddb_partitioning partitioning;
261a27d1 3690
aa363136
MR		 3691 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3692 ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
a485bfb8
VS		 3693
3694 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3695 if (INTEL_INFO(dev)->gen >= 7 &&
aa363136
MR		 3696 config->num_pipes_active == 1 && config->sprites_enabled) {
3697 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3698 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
0362c781 3699
820c1980 3700 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3701 } else {
198a1e9b 3702 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3703 }
3704
198a1e9b 3705 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3706 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3707
820c1980 3708 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3709
820c1980 3710 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3711}
3712
396e33ae 3713static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 3714{
396e33ae
MR		 3715 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3716 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3717
396e33ae
MR		 3718 mutex_lock(&dev_priv->wm.wm_mutex);
3719 intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3720 ilk_program_watermarks(dev_priv);
3721 mutex_unlock(&dev_priv->wm.wm_mutex);
3722}
b9d5c839 3723
396e33ae
MR		 3724static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3725{
3726 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3727 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3728
396e33ae
MR		 3729 mutex_lock(&dev_priv->wm.wm_mutex);
3730 if (cstate->wm.need_postvbl_update) {
3731 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3732 ilk_program_watermarks(dev_priv);
3733 }
3734 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 3735}
3736
3078999f
PB		 3737static void skl_pipe_wm_active_state(uint32_t val,
3738 struct skl_pipe_wm *active,
3739 bool is_transwm,
3740 bool is_cursor,
3741 int i,
3742 int level)
3743{
3744 bool is_enabled = (val & PLANE_WM_EN) != 0;
3745
3746 if (!is_transwm) {
3747 if (!is_cursor) {
3748 active->wm[level].plane_en[i] = is_enabled;
3749 active->wm[level].plane_res_b[i] =
3750 val & PLANE_WM_BLOCKS_MASK;
3751 active->wm[level].plane_res_l[i] =
3752 (val >> PLANE_WM_LINES_SHIFT) &
3753 PLANE_WM_LINES_MASK;
3754 } else {
4969d33e
MR		 3755 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3756 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3757 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3758 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3759 (val >> PLANE_WM_LINES_SHIFT) &
3760 PLANE_WM_LINES_MASK;
3761 }
3762 } else {
3763 if (!is_cursor) {
3764 active->trans_wm.plane_en[i] = is_enabled;
3765 active->trans_wm.plane_res_b[i] =
3766 val & PLANE_WM_BLOCKS_MASK;
3767 active->trans_wm.plane_res_l[i] =
3768 (val >> PLANE_WM_LINES_SHIFT) &
3769 PLANE_WM_LINES_MASK;
3770 } else {
4969d33e
MR		 3771 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3772 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3773 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3774 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3775 (val >> PLANE_WM_LINES_SHIFT) &
3776 PLANE_WM_LINES_MASK;
3777 }
3778 }
3779}
3780
3781static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3782{
3783 struct drm_device *dev = crtc->dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3787 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3788 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3789 enum pipe pipe = intel_crtc->pipe;
3790 int level, i, max_level;
3791 uint32_t temp;
3792
3793 max_level = ilk_wm_max_level(dev);
3794
3795 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3796
3797 for (level = 0; level <= max_level; level++) {
3798 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3799 hw->plane[pipe][i][level] =
3800 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3801 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3802 }
3803
3804 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3805 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3806 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3807
3ef00284 3808 if (!intel_crtc->active)
3078999f
PB		 3809 return;
3810
3811 hw->dirty[pipe] = true;
3812
3813 active->linetime = hw->wm_linetime[pipe];
3814
3815 for (level = 0; level <= max_level; level++) {
3816 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3817 temp = hw->plane[pipe][i][level];
3818 skl_pipe_wm_active_state(temp, active, false,
3819 false, i, level);
3820 }
4969d33e 3821 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3822 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3823 }
3824
3825 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3826 temp = hw->plane_trans[pipe][i];
3827 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3828 }
3829
4969d33e 3830 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3831 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3832
3833 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3834}
3835
3836void skl_wm_get_hw_state(struct drm_device *dev)
3837{
a269c583
DL		 3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3840 struct drm_crtc *crtc;
3841
a269c583 3842 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3843 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3844 skl_pipe_wm_get_hw_state(crtc);
3845}
3846
243e6a44
VS		 3847static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3848{
3849 struct drm_device *dev = crtc->dev;
3850 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3851 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3853 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3854 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3855 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3856 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3857 [PIPE_A] = WM0_PIPEA_ILK,
3858 [PIPE_B] = WM0_PIPEB_ILK,
3859 [PIPE_C] = WM0_PIPEC_IVB,
3860 };
3861
3862 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3863 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3864 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3865
3ef00284 3866 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3867
3868 if (active->pipe_enabled) {
243e6a44
VS		 3869 u32 tmp = hw->wm_pipe[pipe];
3870
3871 /*
3872 * For active pipes LP0 watermark is marked as
3873 * enabled, and LP1+ watermaks as disabled since
3874 * we can't really reverse compute them in case
3875 * multiple pipes are active.
3876 */
3877 active->wm[0].enable = true;
3878 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3879 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3880 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3881 active->linetime = hw->wm_linetime[pipe];
3882 } else {
3883 int level, max_level = ilk_wm_max_level(dev);
3884
3885 /*
3886 * For inactive pipes, all watermark levels
3887 * should be marked as enabled but zeroed,
3888 * which is what we'd compute them to.
3889 */
3890 for (level = 0; level <= max_level; level++)
3891 active->wm[level].enable = true;
3892 }
4e0963c7
MR		 3893
3894 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3895}
3896
6eb1a681
VS		 3897#define _FW_WM(value, plane) \
3898 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3899#define _FW_WM_VLV(value, plane) \
3900 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3901
3902static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3903 struct vlv_wm_values *wm)
3904{
3905 enum pipe pipe;
3906 uint32_t tmp;
3907
3908 for_each_pipe(dev_priv, pipe) {
3909 tmp = I915_READ(VLV_DDL(pipe));
3910
3911 wm->ddl[pipe].primary =
3912 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3913 wm->ddl[pipe].cursor =
3914 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3915 wm->ddl[pipe].sprite[0] =
3916 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3917 wm->ddl[pipe].sprite[1] =
3918 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3919 }
3920
3921 tmp = I915_READ(DSPFW1);
3922 wm->sr.plane = _FW_WM(tmp, SR);
3923 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3924 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3925 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3926
3927 tmp = I915_READ(DSPFW2);
3928 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3929 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3930 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3931
3932 tmp = I915_READ(DSPFW3);
3933 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3934
3935 if (IS_CHERRYVIEW(dev_priv)) {
3936 tmp = I915_READ(DSPFW7_CHV);
3937 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3938 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3939
3940 tmp = I915_READ(DSPFW8_CHV);
3941 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3942 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3943
3944 tmp = I915_READ(DSPFW9_CHV);
3945 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3946 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3947
3948 tmp = I915_READ(DSPHOWM);
3949 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3950 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3951 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3952 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3953 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3954 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3955 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3956 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3957 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3958 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3959 } else {
3960 tmp = I915_READ(DSPFW7);
3961 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3962 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3963
3964 tmp = I915_READ(DSPHOWM);
3965 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3966 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3967 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3968 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3969 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3970 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3971 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3972 }
3973}
3974
3975#undef _FW_WM
3976#undef _FW_WM_VLV
3977
3978void vlv_wm_get_hw_state(struct drm_device *dev)
3979{
3980 struct drm_i915_private *dev_priv = to_i915(dev);
3981 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3982 struct intel_plane *plane;
3983 enum pipe pipe;
3984 u32 val;
3985
3986 vlv_read_wm_values(dev_priv, wm);
3987
3988 for_each_intel_plane(dev, plane) {
3989 switch (plane->base.type) {
3990 int sprite;
3991 case DRM_PLANE_TYPE_CURSOR:
3992 plane->wm.fifo_size = 63;
3993 break;
3994 case DRM_PLANE_TYPE_PRIMARY:
3995 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3996 break;
3997 case DRM_PLANE_TYPE_OVERLAY:
3998 sprite = plane->plane;
3999 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4000 break;
4001 }
4002 }
4003
4004 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4005 wm->level = VLV_WM_LEVEL_PM2;
4006
4007 if (IS_CHERRYVIEW(dev_priv)) {
4008 mutex_lock(&dev_priv->rps.hw_lock);
4009
4010 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4011 if (val & DSP_MAXFIFO_PM5_ENABLE)
4012 wm->level = VLV_WM_LEVEL_PM5;
4013
58590c14
VS		 4014 /*
4015 * If DDR DVFS is disabled in the BIOS, Punit
4016 * will never ack the request. So if that happens
4017 * assume we don't have to enable/disable DDR DVFS
4018 * dynamically. To test that just set the REQ_ACK
4019 * bit to poke the Punit, but don't change the
4020 * HIGH/LOW bits so that we don't actually change
4021 * the current state.
4022 */
6eb1a681 4023 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4024 val |= FORCE_DDR_FREQ_REQ_ACK;
4025 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4026
4027 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4028 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4029 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4030 "assuming DDR DVFS is disabled\n");
4031 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4032 } else {
4033 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4034 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4035 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4036 }
6eb1a681
VS		 4037
4038 mutex_unlock(&dev_priv->rps.hw_lock);
4039 }
4040
4041 for_each_pipe(dev_priv, pipe)
4042 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4043 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4044 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4045
4046 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4047 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4048}
4049
243e6a44
VS		 4050void ilk_wm_get_hw_state(struct drm_device *dev)
4051{
4052 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4053 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4054 struct drm_crtc *crtc;
4055
70e1e0ec 4056 for_each_crtc(dev, crtc)
243e6a44
VS		 4057 ilk_pipe_wm_get_hw_state(crtc);
4058
4059 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4060 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4061 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4062
4063 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4064 if (INTEL_INFO(dev)->gen >= 7) {
4065 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4066 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4067 }
243e6a44 4068
a42a5719 4069 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4070 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4071 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4072 else if (IS_IVYBRIDGE(dev))
4073 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4074 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4075
4076 hw->enable_fbc_wm =
4077 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4078}
4079
b445e3b0
ED		 4080/**
4081 * intel_update_watermarks - update FIFO watermark values based on current modes
4082 *
4083 * Calculate watermark values for the various WM regs based on current mode
4084 * and plane configuration.
4085 *
4086 * There are several cases to deal with here:
4087 * - normal (i.e. non-self-refresh)
4088 * - self-refresh (SR) mode
4089 * - lines are large relative to FIFO size (buffer can hold up to 2)
4090 * - lines are small relative to FIFO size (buffer can hold more than 2
4091 * lines), so need to account for TLB latency
4092 *
4093 * The normal calculation is:
4094 * watermark = dotclock * bytes per pixel * latency
4095 * where latency is platform & configuration dependent (we assume pessimal
4096 * values here).
4097 *
4098 * The SR calculation is:
4099 * watermark = (trunc(latency/line time)+1) * surface width *
4100 * bytes per pixel
4101 * where
4102 * line time = htotal / dotclock
4103 * surface width = hdisplay for normal plane and 64 for cursor
4104 * and latency is assumed to be high, as above.
4105 *
4106 * The final value programmed to the register should always be rounded up,
4107 * and include an extra 2 entries to account for clock crossings.
4108 *
4109 * We don't use the sprite, so we can ignore that. And on Crestline we have
4110 * to set the non-SR watermarks to 8.
4111 */
46ba614c 4112void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4113{
46ba614c 4114 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4115
4116 if (dev_priv->display.update_wm)
46ba614c 4117 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4118}
4119
9270388e
DV		 4120/**
4121 * Lock protecting IPS related data structures
9270388e
DV		 4122 */
4123DEFINE_SPINLOCK(mchdev_lock);
4124
4125/* Global for IPS driver to get at the current i915 device. Protected by
4126 * mchdev_lock. */
4127static struct drm_i915_private *i915_mch_dev;
4128
2b4e57bd
ED		 4129bool ironlake_set_drps(struct drm_device *dev, u8 val)
4130{
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 u16 rgvswctl;
4133
9270388e
DV		 4134 assert_spin_locked(&mchdev_lock);
4135
2b4e57bd
ED		 4136 rgvswctl = I915_READ16(MEMSWCTL);
4137 if (rgvswctl & MEMCTL_CMD_STS) {
4138 DRM_DEBUG("gpu busy, RCS change rejected\n");
4139 return false; /* still busy with another command */
4140 }
4141
4142 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4143 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4144 I915_WRITE16(MEMSWCTL, rgvswctl);
4145 POSTING_READ16(MEMSWCTL);
4146
4147 rgvswctl |= MEMCTL_CMD_STS;
4148 I915_WRITE16(MEMSWCTL, rgvswctl);
4149
4150 return true;
4151}
4152
8090c6b9 4153static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4154{
4155 struct drm_i915_private *dev_priv = dev->dev_private;
4156 u32 rgvmodectl = I915_READ(MEMMODECTL);
4157 u8 fmax, fmin, fstart, vstart;
4158
9270388e
DV		 4159 spin_lock_irq(&mchdev_lock);
4160
2b4e57bd
ED		 4161 /* Enable temp reporting */
4162 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4163 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4164
4165 /* 100ms RC evaluation intervals */
4166 I915_WRITE(RCUPEI, 100000);
4167 I915_WRITE(RCDNEI, 100000);
4168
4169 /* Set max/min thresholds to 90ms and 80ms respectively */
4170 I915_WRITE(RCBMAXAVG, 90000);
4171 I915_WRITE(RCBMINAVG, 80000);
4172
4173 I915_WRITE(MEMIHYST, 1);
4174
4175 /* Set up min, max, and cur for interrupt handling */
4176 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4177 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4178 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4179 MEMMODE_FSTART_SHIFT;
4180
616847e7 4181 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4182 PXVFREQ_PX_SHIFT;
4183
20e4d407
DV		 4184 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4185 dev_priv->ips.fstart = fstart;
2b4e57bd 4186
20e4d407
DV		 4187 dev_priv->ips.max_delay = fstart;
4188 dev_priv->ips.min_delay = fmin;
4189 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4190
4191 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4192 fmax, fmin, fstart);
4193
4194 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4195
4196 /*
4197 * Interrupts will be enabled in ironlake_irq_postinstall
4198 */
4199
4200 I915_WRITE(VIDSTART, vstart);
4201 POSTING_READ(VIDSTART);
4202
4203 rgvmodectl |= MEMMODE_SWMODE_EN;
4204 I915_WRITE(MEMMODECTL, rgvmodectl);
4205
9270388e 4206 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4207 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4208 mdelay(1);
2b4e57bd
ED		 4209
4210 ironlake_set_drps(dev, fstart);
4211
7d81c3e0
VS		 4212 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4213 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4214 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4215 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4216 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4217
4218 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4219}
4220
8090c6b9 4221static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4222{
4223 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4224 u16 rgvswctl;
4225
4226 spin_lock_irq(&mchdev_lock);
4227
4228 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4229
4230 /* Ack interrupts, disable EFC interrupt */
4231 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4232 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4233 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4234 I915_WRITE(DEIIR, DE_PCU_EVENT);
4235 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4236
4237 /* Go back to the starting frequency */
20e4d407 4238 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4239 mdelay(1);
2b4e57bd
ED		 4240 rgvswctl |= MEMCTL_CMD_STS;
4241 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4242 mdelay(1);
2b4e57bd 4243
9270388e 4244 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4245}
4246
acbe9475
DV		 4247/* There's a funny hw issue where the hw returns all 0 when reading from
4248 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4249 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4250 * all limits and the gpu stuck at whatever frequency it is at atm).
4251 */
74ef1173 4252static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4253{
7b9e0ae6 4254 u32 limits;
2b4e57bd 4255
20b46e59
DV		 4256 /* Only set the down limit when we've reached the lowest level to avoid
4257 * getting more interrupts, otherwise leave this clear. This prevents a
4258 * race in the hw when coming out of rc6: There's a tiny window where
4259 * the hw runs at the minimal clock before selecting the desired
4260 * frequency, if the down threshold expires in that window we will not
4261 * receive a down interrupt. */
74ef1173
AG		 4262 if (IS_GEN9(dev_priv->dev)) {
4263 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4264 if (val <= dev_priv->rps.min_freq_softlimit)
4265 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4266 } else {
4267 limits = dev_priv->rps.max_freq_softlimit << 24;
4268 if (val <= dev_priv->rps.min_freq_softlimit)
4269 limits |= dev_priv->rps.min_freq_softlimit << 16;
4270 }
20b46e59
DV		 4271
4272 return limits;
4273}
4274
dd75fdc8
CW		 4275static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4276{
4277 int new_power;
8a586437
AG		 4278 u32 threshold_up = 0, threshold_down = 0; /* in % */
4279 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4280
4281 new_power = dev_priv->rps.power;
4282 switch (dev_priv->rps.power) {
4283 case LOW_POWER:
b39fb297 4284 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4285 new_power = BETWEEN;
4286 break;
4287
4288 case BETWEEN:
b39fb297 4289 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4290 new_power = LOW_POWER;
b39fb297 4291 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4292 new_power = HIGH_POWER;
4293 break;
4294
4295 case HIGH_POWER:
b39fb297 4296 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4297 new_power = BETWEEN;
4298 break;
4299 }
4300 /* Max/min bins are special */
aed242ff 4301 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4302 new_power = LOW_POWER;
aed242ff 4303 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4304 new_power = HIGH_POWER;
4305 if (new_power == dev_priv->rps.power)
4306 return;
4307
4308 /* Note the units here are not exactly 1us, but 1280ns. */
4309 switch (new_power) {
4310 case LOW_POWER:
4311 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4312 ei_up = 16000;
4313 threshold_up = 95;
dd75fdc8
CW		 4314
4315 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4316 ei_down = 32000;
4317 threshold_down = 85;
dd75fdc8
CW		 4318 break;
4319
4320 case BETWEEN:
4321 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4322 ei_up = 13000;
4323 threshold_up = 90;
dd75fdc8
CW		 4324
4325 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4326 ei_down = 32000;
4327 threshold_down = 75;
dd75fdc8
CW		 4328 break;
4329
4330 case HIGH_POWER:
4331 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4332 ei_up = 10000;
4333 threshold_up = 85;
dd75fdc8
CW		 4334
4335 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4336 ei_down = 32000;
4337 threshold_down = 60;
dd75fdc8
CW		 4338 break;
4339 }
4340
8a586437
AG		 4341 I915_WRITE(GEN6_RP_UP_EI,
4342 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4343 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4344 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4345
4346 I915_WRITE(GEN6_RP_DOWN_EI,
4347 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4348 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4349 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4350
4351 I915_WRITE(GEN6_RP_CONTROL,
4352 GEN6_RP_MEDIA_TURBO |
4353 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4354 GEN6_RP_MEDIA_IS_GFX |
4355 GEN6_RP_ENABLE |
4356 GEN6_RP_UP_BUSY_AVG |
4357 GEN6_RP_DOWN_IDLE_AVG);
4358
dd75fdc8 4359 dev_priv->rps.power = new_power;
8fb55197
CW		 4360 dev_priv->rps.up_threshold = threshold_up;
4361 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4362 dev_priv->rps.last_adj = 0;
4363}
4364
2876ce73
CW		 4365static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4366{
4367 u32 mask = 0;
4368
4369 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4370 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4371 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4372 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4373
7b3c29f6
CW		 4374 mask &= dev_priv->pm_rps_events;
4375
59d02a1f 4376 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4377}
4378
b8a5ff8d
JM		 4379/* gen6_set_rps is called to update the frequency request, but should also be
4380 * called when the range (min_delay and max_delay) is modified so that we can
4381 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4382static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4383{
4384 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4385
23eafea6 4386 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4387 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4388 return;
4389
4fc688ce 4390 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4391 WARN_ON(val > dev_priv->rps.max_freq);
4392 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4393
eb64cad1
CW		 4394 /* min/max delay may still have been modified so be sure to
4395 * write the limits value.
4396 */
4397 if (val != dev_priv->rps.cur_freq) {
4398 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4399
5704195c
AG		 4400 if (IS_GEN9(dev))
4401 I915_WRITE(GEN6_RPNSWREQ,
4402 GEN9_FREQUENCY(val));
4403 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4404 I915_WRITE(GEN6_RPNSWREQ,
4405 HSW_FREQUENCY(val));
4406 else
4407 I915_WRITE(GEN6_RPNSWREQ,
4408 GEN6_FREQUENCY(val) |
4409 GEN6_OFFSET(0) |
4410 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4411 }
7b9e0ae6 4412
7b9e0ae6
CW		 4413 /* Make sure we continue to get interrupts
4414 * until we hit the minimum or maximum frequencies.
4415 */
74ef1173 4416 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4417 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4418
d5570a72
BW		 4419 POSTING_READ(GEN6_RPNSWREQ);
4420
b39fb297 4421 dev_priv->rps.cur_freq = val;
0f94592e 4422 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4423}
4424
ffe02b40
VS		 4425static void valleyview_set_rps(struct drm_device *dev, u8 val)
4426{
4427 struct drm_i915_private *dev_priv = dev->dev_private;
4428
4429 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4430 WARN_ON(val > dev_priv->rps.max_freq);
4431 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4432
4433 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4434 "Odd GPU freq value\n"))
4435 val &= ~1;
4436
cd25dd5b
D		 4437 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4438
8fb55197 4439 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4440 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4441 if (!IS_CHERRYVIEW(dev_priv))
4442 gen6_set_rps_thresholds(dev_priv, val);
4443 }
ffe02b40 4444
ffe02b40
VS		 4445 dev_priv->rps.cur_freq = val;
4446 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4447}
4448
a7f6e231 4449/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4450 *
4451 * * If Gfx is Idle, then
a7f6e231
D		 4452 * 1. Forcewake Media well.
4453 * 2. Request idle freq.
4454 * 3. Release Forcewake of Media well.
76c3552f
D		 4455*/
4456static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4457{
aed242ff 4458 u32 val = dev_priv->rps.idle_freq;
5549d25f 4459
aed242ff 4460 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4461 return;
4462
a7f6e231
D		 4463 /* Wake up the media well, as that takes a lot less
4464 * power than the Render well. */
4465 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4466 valleyview_set_rps(dev_priv->dev, val);
4467 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4468}
4469
43cf3bf0
CW		 4470void gen6_rps_busy(struct drm_i915_private *dev_priv)
4471{
4472 mutex_lock(&dev_priv->rps.hw_lock);
4473 if (dev_priv->rps.enabled) {
4474 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4475 gen6_rps_reset_ei(dev_priv);
4476 I915_WRITE(GEN6_PMINTRMSK,
4477 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4478 }
4479 mutex_unlock(&dev_priv->rps.hw_lock);
4480}
4481
b29c19b6
CW		 4482void gen6_rps_idle(struct drm_i915_private *dev_priv)
4483{
691bb717
DL		 4484 struct drm_device *dev = dev_priv->dev;
4485
b29c19b6 4486 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4487 if (dev_priv->rps.enabled) {
666a4537 4488 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4489 vlv_set_rps_idle(dev_priv);
7526ed79 4490 else
aed242ff 4491 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4492 dev_priv->rps.last_adj = 0;
43cf3bf0 4493 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4494 }
8d3afd7d 4495 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4496
8d3afd7d 4497 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4498 while (!list_empty(&dev_priv->rps.clients))
4499 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4500 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4501}
4502
1854d5ca 4503void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4504 struct intel_rps_client *rps,
4505 unsigned long submitted)
b29c19b6 4506{
8d3afd7d
CW		 4507 /* This is intentionally racy! We peek at the state here, then
4508 * validate inside the RPS worker.
4509 */
4510 if (!(dev_priv->mm.busy &&
4511 dev_priv->rps.enabled &&
4512 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4513 return;
43cf3bf0 4514
e61b9958
CW		 4515 /* Force a RPS boost (and don't count it against the client) if
4516 * the GPU is severely congested.
4517 */
d0bc54f2 4518 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4519 rps = NULL;
4520
8d3afd7d
CW		 4521 spin_lock(&dev_priv->rps.client_lock);
4522 if (rps == NULL || list_empty(&rps->link)) {
4523 spin_lock_irq(&dev_priv->irq_lock);
4524 if (dev_priv->rps.interrupts_enabled) {
4525 dev_priv->rps.client_boost = true;
4526 queue_work(dev_priv->wq, &dev_priv->rps.work);
4527 }
4528 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4529
2e1b8730
CW		 4530 if (rps != NULL) {
4531 list_add(&rps->link, &dev_priv->rps.clients);
4532 rps->boosts++;
1854d5ca
CW		 4533 } else
4534 dev_priv->rps.boosts++;
c0951f0c 4535 }
8d3afd7d 4536 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4537}
4538
ffe02b40 4539void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4540{
666a4537 4541 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4542 valleyview_set_rps(dev, val);
4543 else
4544 gen6_set_rps(dev, val);
0a073b84
JB		 4545}
4546
20e49366
ZW		 4547static void gen9_disable_rps(struct drm_device *dev)
4548{
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550
4551 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4552 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4553}
4554
44fc7d5c 4555static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4556{
4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558
4559 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4560 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4561}
4562
38807746
D		 4563static void cherryview_disable_rps(struct drm_device *dev)
4564{
4565 struct drm_i915_private *dev_priv = dev->dev_private;
4566
4567 I915_WRITE(GEN6_RC_CONTROL, 0);
4568}
4569
44fc7d5c
DV		 4570static void valleyview_disable_rps(struct drm_device *dev)
4571{
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573
98a2e5f9
D		 4574 /* we're doing forcewake before Disabling RC6,
4575 * This what the BIOS expects when going into suspend */
59bad947 4576 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4577
44fc7d5c 4578 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4579
59bad947 4580 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4581}
4582
dc39fff7
BW		 4583static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4584{
666a4537 4585 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4586 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4587 mode = GEN6_RC_CTL_RC6_ENABLE;
4588 else
4589 mode = 0;
4590 }
58abf1da
RV		 4591 if (HAS_RC6p(dev))
4592 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4593 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4594 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4595 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4596
4597 else
4598 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4599 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4600}
4601
e6069ca8 4602static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4603{
e7d66d89
DV		 4604 /* No RC6 before Ironlake and code is gone for ilk. */
4605 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4606 return 0;
4607
456470eb 4608 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4609 if (enable_rc6 >= 0) {
4610 int mask;
4611
58abf1da 4612 if (HAS_RC6p(dev))
e6069ca8
ID		 4613 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4614 INTEL_RC6pp_ENABLE;
4615 else
4616 mask = INTEL_RC6_ENABLE;
4617
4618 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4619 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4620 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4621
4622 return enable_rc6 & mask;
4623 }
2b4e57bd 4624
8bade1ad 4625 if (IS_IVYBRIDGE(dev))
cca84a1f 4626 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4627
4628 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4629}
4630
e6069ca8
ID		 4631int intel_enable_rc6(const struct drm_device *dev)
4632{
4633 return i915.enable_rc6;
4634}
4635
93ee2920 4636static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4637{
93ee2920
TR		 4638 struct drm_i915_private *dev_priv = dev->dev_private;
4639 uint32_t rp_state_cap;
4640 u32 ddcc_status = 0;
4641 int ret;
4642
3280e8b0
BW		 4643 /* All of these values are in units of 50MHz */
4644 dev_priv->rps.cur_freq = 0;
93ee2920 4645 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4646 if (IS_BROXTON(dev)) {
4647 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4648 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4649 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4650 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4651 } else {
4652 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4653 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4654 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4655 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4656 }
4657
3280e8b0
BW		 4658 /* hw_max = RP0 until we check for overclocking */
4659 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4660
93ee2920 4661 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4662 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4663 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4664 ret = sandybridge_pcode_read(dev_priv,
4665 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4666 &ddcc_status);
4667 if (0 == ret)
4668 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4669 clamp_t(u8,
4670 ((ddcc_status >> 8) & 0xff),
4671 dev_priv->rps.min_freq,
4672 dev_priv->rps.max_freq);
93ee2920
TR		 4673 }
4674
ef11bdb3 4675 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4676 /* Store the frequency values in 16.66 MHZ units, which is
4677 the natural hardware unit for SKL */
4678 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4679 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4680 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4681 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4682 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4683 }
4684
aed242ff
CW		 4685 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4686
3280e8b0
BW		 4687 /* Preserve min/max settings in case of re-init */
4688 if (dev_priv->rps.max_freq_softlimit == 0)
4689 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4690
93ee2920
TR		 4691 if (dev_priv->rps.min_freq_softlimit == 0) {
4692 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4693 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4694 max_t(int, dev_priv->rps.efficient_freq,
4695 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4696 else
4697 dev_priv->rps.min_freq_softlimit =
4698 dev_priv->rps.min_freq;
4699 }
3280e8b0
BW		 4700}
4701
b6fef0ef 4702/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4703static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4704{
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706
4707 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4708
ba1c554c
DL		 4709 gen6_init_rps_frequencies(dev);
4710
23eafea6 4711 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4712 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4713 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4714 return;
4715 }
4716
0beb059a
AG		 4717 /* Program defaults and thresholds for RPS*/
4718 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4719 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4720
4721 /* 1 second timeout*/
4722 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4723 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4724
b6fef0ef 4725 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4726
0beb059a
AG		 4727 /* Leaning on the below call to gen6_set_rps to program/setup the
4728 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4729 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4730 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4731 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4732
4733 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4734}
4735
4736static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4737{
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739 struct intel_engine_cs *ring;
4740 uint32_t rc6_mask = 0;
4741 int unused;
4742
4743 /* 1a: Software RC state - RC0 */
4744 I915_WRITE(GEN6_RC_STATE, 0);
4745
4746 /* 1b: Get forcewake during program sequence. Although the driver
4747 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4748 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4749
4750 /* 2a: Disable RC states. */
4751 I915_WRITE(GEN6_RC_CONTROL, 0);
4752
4753 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4754
4755 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4756 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4757 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4758 else
4759 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4760 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4761 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4762 for_each_ring(ring, dev_priv, unused)
4763 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4764
4765 if (HAS_GUC_UCODE(dev))
4766 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4767
20e49366 4768 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4769
38c23527
ZW		 4770 /* 2c: Program Coarse Power Gating Policies. */
4771 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4772 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4773
20e49366
ZW		 4774 /* 3a: Enable RC6 */
4775 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4776 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4777 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4778 "on" : "off");
3e7732a0 4779 /* WaRsUseTimeoutMode */
e87a005d 4780 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4781 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4782 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4783 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4784 GEN7_RC_CTL_TO_MODE |
4785 rc6_mask);
3e7732a0
SAK		 4786 } else {
4787 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4788 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4789 GEN6_RC_CTL_EI_MODE(1) |
4790 rc6_mask);
3e7732a0 4791 }
20e49366 4792
cb07bae0
SK		 4793 /*
4794 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4795 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4796 */
06e668ac 4797 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4798 I915_WRITE(GEN9_PG_ENABLE, 0);
4799 else
4800 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4801 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4802
59bad947 4803 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4804
4805}
4806
6edee7f3
BW		 4807static void gen8_enable_rps(struct drm_device *dev)
4808{
4809 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4810 struct intel_engine_cs *ring;
93ee2920 4811 uint32_t rc6_mask = 0;
6edee7f3
BW		 4812 int unused;
4813
4814 /* 1a: Software RC state - RC0 */
4815 I915_WRITE(GEN6_RC_STATE, 0);
4816
4817 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4818 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4819 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4820
4821 /* 2a: Disable RC states. */
4822 I915_WRITE(GEN6_RC_CONTROL, 0);
4823
93ee2920
TR		 4824 /* Initialize rps frequencies */
4825 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4826
4827 /* 2b: Program RC6 thresholds.*/
4828 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4829 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4830 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4831 for_each_ring(ring, dev_priv, unused)
4832 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4833 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4834 if (IS_BROADWELL(dev))
4835 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4836 else
4837 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4838
4839 /* 3: Enable RC6 */
4840 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4841 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4842 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4843 if (IS_BROADWELL(dev))
4844 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4845 GEN7_RC_CTL_TO_MODE |
4846 rc6_mask);
4847 else
4848 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4849 GEN6_RC_CTL_EI_MODE(1) |
4850 rc6_mask);
6edee7f3
BW		 4851
4852 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4853 I915_WRITE(GEN6_RPNSWREQ,
4854 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4855 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4856 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4857 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4858 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4859
4860 /* Docs recommend 900MHz, and 300 MHz respectively */
4861 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4862 dev_priv->rps.max_freq_softlimit << 24 |
4863 dev_priv->rps.min_freq_softlimit << 16);
4864
4865 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4866 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4867 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4868 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4869
4870 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4871
4872 /* 5: Enable RPS */
7526ed79
DV		 4873 I915_WRITE(GEN6_RP_CONTROL,
4874 GEN6_RP_MEDIA_TURBO |
4875 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4876 GEN6_RP_MEDIA_IS_GFX |
4877 GEN6_RP_ENABLE |
4878 GEN6_RP_UP_BUSY_AVG |
4879 GEN6_RP_DOWN_IDLE_AVG);
4880
4881 /* 6: Ring frequency + overclocking (our driver does this later */
4882
c7f3153a 4883 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4884 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4885
59bad947 4886 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4887}
4888
79f5b2c7 4889static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4890{
79f5b2c7 4891 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4892 struct intel_engine_cs *ring;
d060c169 4893 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4894 u32 gtfifodbg;
2b4e57bd 4895 int rc6_mode;
42c0526c 4896 int i, ret;
2b4e57bd 4897
4fc688ce 4898 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4899
2b4e57bd
ED		 4900 /* Here begins a magic sequence of register writes to enable
4901 * auto-downclocking.
4902 *
4903 * Perhaps there might be some value in exposing these to
4904 * userspace...
4905 */
4906 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4907
4908 /* Clear the DBG now so we don't confuse earlier errors */
4909 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4910 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4911 I915_WRITE(GTFIFODBG, gtfifodbg);
4912 }
4913
59bad947 4914 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4915
93ee2920
TR		 4916 /* Initialize rps frequencies */
4917 gen6_init_rps_frequencies(dev);
dd0a1aa1 4918
2b4e57bd
ED		 4919 /* disable the counters and set deterministic thresholds */
4920 I915_WRITE(GEN6_RC_CONTROL, 0);
4921
4922 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4923 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4924 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4925 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4926 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4927
b4519513
CW		 4928 for_each_ring(ring, dev_priv, i)
4929 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4930
4931 I915_WRITE(GEN6_RC_SLEEP, 0);
4932 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4933 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4934 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4935 else
4936 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4937 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4938 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4939
5a7dc92a 4940 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4941 rc6_mode = intel_enable_rc6(dev_priv->dev);
4942 if (rc6_mode & INTEL_RC6_ENABLE)
4943 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4944
5a7dc92a
ED		 4945 /* We don't use those on Haswell */
4946 if (!IS_HASWELL(dev)) {
4947 if (rc6_mode & INTEL_RC6p_ENABLE)
4948 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4949
5a7dc92a
ED		 4950 if (rc6_mode & INTEL_RC6pp_ENABLE)
4951 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4952 }
2b4e57bd 4953
dc39fff7 4954 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4955
4956 I915_WRITE(GEN6_RC_CONTROL,
4957 rc6_mask |
4958 GEN6_RC_CTL_EI_MODE(1) |
4959 GEN6_RC_CTL_HW_ENABLE);
4960
dd75fdc8
CW		 4961 /* Power down if completely idle for over 50ms */
4962 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4963 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4964
42c0526c 4965 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4966 if (ret)
42c0526c 4967 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4968
4969 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4970 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4971 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4972 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4973 (pcu_mbox & 0xff) * 50);
b39fb297 4974 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4975 }
4976
dd75fdc8 4977 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4978 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4979
31643d54
BW		 4980 rc6vids = 0;
4981 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4982 if (IS_GEN6(dev) && ret) {
4983 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4984 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4985 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4986 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4987 rc6vids &= 0xffff00;
4988 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4989 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4990 if (ret)
4991 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4992 }
4993
59bad947 4994 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4995}
4996
c2bc2fc5 4997static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4998{
79f5b2c7 4999 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5000 int min_freq = 15;
3ebecd07
CW		 5001 unsigned int gpu_freq;
5002 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5003 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5004 int scaling_factor = 180;
eda79642 5005 struct cpufreq_policy *policy;
2b4e57bd 5006
4fc688ce 5007 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5008
eda79642
BW		 5009 policy = cpufreq_cpu_get(0);
5010 if (policy) {
5011 max_ia_freq = policy->cpuinfo.max_freq;
5012 cpufreq_cpu_put(policy);
5013 } else {
5014 /*
5015 * Default to measured freq if none found, PCU will ensure we
5016 * don't go over
5017 */
2b4e57bd 5018 max_ia_freq = tsc_khz;
eda79642 5019 }
2b4e57bd
ED		 5020
5021 /* Convert from kHz to MHz */
5022 max_ia_freq /= 1000;
5023
153b4b95 5024 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5025 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5026 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5027
ef11bdb3 5028 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5029 /* Convert GT frequency to 50 HZ units */
5030 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5031 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5032 } else {
5033 min_gpu_freq = dev_priv->rps.min_freq;
5034 max_gpu_freq = dev_priv->rps.max_freq;
5035 }
5036
2b4e57bd
ED		 5037 /*
5038 * For each potential GPU frequency, load a ring frequency we'd like
5039 * to use for memory access. We do this by specifying the IA frequency
5040 * the PCU should use as a reference to determine the ring frequency.
5041 */
4c8c7743
AG		 5042 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5043 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5044 unsigned int ia_freq = 0, ring_freq = 0;
5045
ef11bdb3 5046 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5047 /*
5048 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5049 * No floor required for ring frequency on SKL.
5050 */
5051 ring_freq = gpu_freq;
5052 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5053 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5054 ring_freq = max(min_ring_freq, gpu_freq);
5055 } else if (IS_HASWELL(dev)) {
f6aca45c 5056 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5057 ring_freq = max(min_ring_freq, ring_freq);
5058 /* leave ia_freq as the default, chosen by cpufreq */
5059 } else {
5060 /* On older processors, there is no separate ring
5061 * clock domain, so in order to boost the bandwidth
5062 * of the ring, we need to upclock the CPU (ia_freq).
5063 *
5064 * For GPU frequencies less than 750MHz,
5065 * just use the lowest ring freq.
5066 */
5067 if (gpu_freq < min_freq)
5068 ia_freq = 800;
5069 else
5070 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5071 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5072 }
2b4e57bd 5073
42c0526c
BW		 5074 sandybridge_pcode_write(dev_priv,
5075 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5076 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5077 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5078 gpu_freq);
2b4e57bd 5079 }
2b4e57bd
ED		 5080}
5081
c2bc2fc5
ID		 5082void gen6_update_ring_freq(struct drm_device *dev)
5083{
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085
97d3308a 5086 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5087 return;
5088
5089 mutex_lock(&dev_priv->rps.hw_lock);
5090 __gen6_update_ring_freq(dev);
5091 mutex_unlock(&dev_priv->rps.hw_lock);
5092}
5093
03af2045 5094static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5095{
095acd5f 5096 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5097 u32 val, rp0;
5098
5b5929cb 5099 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5100
5b5929cb
JN		 5101 switch (INTEL_INFO(dev)->eu_total) {
5102 case 8:
5103 /* (2 * 4) config */
5104 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5105 break;
5106 case 12:
5107 /* (2 * 6) config */
5108 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5109 break;
5110 case 16:
5111 /* (2 * 8) config */
5112 default:
5113 /* Setting (2 * 8) Min RP0 for any other combination */
5114 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5115 break;
095acd5f 5116 }
5b5929cb
JN		 5117
5118 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5119
2b6b3a09
D		 5120 return rp0;
5121}
5122
5123static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5124{
5125 u32 val, rpe;
5126
5127 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5128 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5129
5130 return rpe;
5131}
5132
7707df4a
D		 5133static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5134{
5135 u32 val, rp1;
5136
5b5929cb
JN		 5137 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5138 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5139
7707df4a
D		 5140 return rp1;
5141}
5142
f8f2b001
D		 5143static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5144{
5145 u32 val, rp1;
5146
5147 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5148
5149 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5150
5151 return rp1;
5152}
5153
03af2045 5154static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5155{
5156 u32 val, rp0;
5157
64936258 5158 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5159
5160 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5161 /* Clamp to max */
5162 rp0 = min_t(u32, rp0, 0xea);
5163
5164 return rp0;
5165}
5166
5167static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5168{
5169 u32 val, rpe;
5170
64936258 5171 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5172 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5173 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5174 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5175
5176 return rpe;
5177}
5178
03af2045 5179static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5180{
36146035
ID		 5181 u32 val;
5182
5183 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5184 /*
5185 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5186 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5187 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5188 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5189 * to make sure it matches what Punit accepts.
5190 */
5191 return max_t(u32, val, 0xc0);
0a073b84
JB		 5192}
5193
ae48434c
ID		 5194/* Check that the pctx buffer wasn't move under us. */
5195static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5196{
5197 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5198
5199 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5200 dev_priv->vlv_pctx->stolen->start);
5201}
5202
38807746
D		 5203
5204/* Check that the pcbr address is not empty. */
5205static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5206{
5207 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5208
5209 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5210}
5211
5212static void cherryview_setup_pctx(struct drm_device *dev)
5213{
5214 struct drm_i915_private *dev_priv = dev->dev_private;
5215 unsigned long pctx_paddr, paddr;
5216 struct i915_gtt *gtt = &dev_priv->gtt;
5217 u32 pcbr;
5218 int pctx_size = 32*1024;
5219
5220 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5221
5222 pcbr = I915_READ(VLV_PCBR);
5223 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5224 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5225 paddr = (dev_priv->mm.stolen_base +
5226 (gtt->stolen_size - pctx_size));
5227
5228 pctx_paddr = (paddr & (~4095));
5229 I915_WRITE(VLV_PCBR, pctx_paddr);
5230 }
ce611ef8
VS		 5231
5232 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5233}
5234
c9cddffc
JB		 5235static void valleyview_setup_pctx(struct drm_device *dev)
5236{
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct drm_i915_gem_object *pctx;
5239 unsigned long pctx_paddr;
5240 u32 pcbr;
5241 int pctx_size = 24*1024;
5242
17b0c1f7
ID		 5243 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5244
c9cddffc
JB		 5245 pcbr = I915_READ(VLV_PCBR);
5246 if (pcbr) {
5247 /* BIOS set it up already, grab the pre-alloc'd space */
5248 int pcbr_offset;
5249
5250 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5251 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5252 pcbr_offset,
190d6cd5 5253 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5254 pctx_size);
5255 goto out;
5256 }
5257
ce611ef8
VS		 5258 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5259
c9cddffc
JB		 5260 /*
5261 * From the Gunit register HAS:
5262 * The Gfx driver is expected to program this register and ensure
5263 * proper allocation within Gfx stolen memory. For example, this
5264 * register should be programmed such than the PCBR range does not
5265 * overlap with other ranges, such as the frame buffer, protected
5266 * memory, or any other relevant ranges.
5267 */
5268 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5269 if (!pctx) {
5270 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5271 return;
5272 }
5273
5274 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5275 I915_WRITE(VLV_PCBR, pctx_paddr);
5276
5277out:
ce611ef8 5278 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5279 dev_priv->vlv_pctx = pctx;
5280}
5281
ae48434c
ID		 5282static void valleyview_cleanup_pctx(struct drm_device *dev)
5283{
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285
5286 if (WARN_ON(!dev_priv->vlv_pctx))
5287 return;
5288
5289 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5290 dev_priv->vlv_pctx = NULL;
5291}
5292
4e80519e
ID		 5293static void valleyview_init_gt_powersave(struct drm_device *dev)
5294{
5295 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5296 u32 val;
4e80519e
ID		 5297
5298 valleyview_setup_pctx(dev);
5299
5300 mutex_lock(&dev_priv->rps.hw_lock);
5301
2bb25c17
VS		 5302 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5303 switch ((val >> 6) & 3) {
5304 case 0:
5305 case 1:
5306 dev_priv->mem_freq = 800;
5307 break;
5308 case 2:
5309 dev_priv->mem_freq = 1066;
5310 break;
5311 case 3:
5312 dev_priv->mem_freq = 1333;
5313 break;
5314 }
80b83b62 5315 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5316
4e80519e
ID		 5317 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5318 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5319 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5320 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5321 dev_priv->rps.max_freq);
5322
5323 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5324 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5325 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5326 dev_priv->rps.efficient_freq);
5327
f8f2b001
D		 5328 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5329 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5330 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5331 dev_priv->rps.rp1_freq);
5332
4e80519e
ID		 5333 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5334 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5335 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5336 dev_priv->rps.min_freq);
5337
aed242ff
CW		 5338 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5339
4e80519e
ID		 5340 /* Preserve min/max settings in case of re-init */
5341 if (dev_priv->rps.max_freq_softlimit == 0)
5342 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5343
5344 if (dev_priv->rps.min_freq_softlimit == 0)
5345 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5346
5347 mutex_unlock(&dev_priv->rps.hw_lock);
5348}
5349
38807746
D		 5350static void cherryview_init_gt_powersave(struct drm_device *dev)
5351{
2b6b3a09 5352 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5353 u32 val;
2b6b3a09 5354
38807746 5355 cherryview_setup_pctx(dev);
2b6b3a09
D		 5356
5357 mutex_lock(&dev_priv->rps.hw_lock);
5358
a580516d 5359 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5360 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5361 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5362
2bb25c17 5363 switch ((val >> 2) & 0x7) {
2bb25c17 5364 case 3:
2bb25c17
VS		 5365 dev_priv->mem_freq = 2000;
5366 break;
bfa7df01 5367 default:
2bb25c17
VS		 5368 dev_priv->mem_freq = 1600;
5369 break;
5370 }
80b83b62 5371 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5372
2b6b3a09
D		 5373 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5374 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5375 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5376 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5377 dev_priv->rps.max_freq);
5378
5379 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5380 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5381 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5382 dev_priv->rps.efficient_freq);
5383
7707df4a
D		 5384 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5385 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5386 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5387 dev_priv->rps.rp1_freq);
5388
5b7c91b7
D		 5389 /* PUnit validated range is only [RPe, RP0] */
5390 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5391 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5392 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5393 dev_priv->rps.min_freq);
5394
1c14762d
VS		 5395 WARN_ONCE((dev_priv->rps.max_freq |
5396 dev_priv->rps.efficient_freq |
5397 dev_priv->rps.rp1_freq |
5398 dev_priv->rps.min_freq) & 1,
5399 "Odd GPU freq values\n");
5400
aed242ff
CW		 5401 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5402
2b6b3a09
D		 5403 /* Preserve min/max settings in case of re-init */
5404 if (dev_priv->rps.max_freq_softlimit == 0)
5405 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5406
5407 if (dev_priv->rps.min_freq_softlimit == 0)
5408 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5409
5410 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5411}
5412
4e80519e
ID		 5413static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5414{
5415 valleyview_cleanup_pctx(dev);
5416}
5417
38807746
D		 5418static void cherryview_enable_rps(struct drm_device *dev)
5419{
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 struct intel_engine_cs *ring;
2b6b3a09 5422 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5423 int i;
5424
5425 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5426
5427 gtfifodbg = I915_READ(GTFIFODBG);
5428 if (gtfifodbg) {
5429 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5430 gtfifodbg);
5431 I915_WRITE(GTFIFODBG, gtfifodbg);
5432 }
5433
5434 cherryview_check_pctx(dev_priv);
5435
5436 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5437 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5438 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5439
160614a2
VS		 5440 /* Disable RC states. */
5441 I915_WRITE(GEN6_RC_CONTROL, 0);
5442
38807746
D		 5443 /* 2a: Program RC6 thresholds.*/
5444 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5445 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5446 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5447
5448 for_each_ring(ring, dev_priv, i)
5449 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5450 I915_WRITE(GEN6_RC_SLEEP, 0);
5451
f4f71c7d
D		 5452 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5453 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5454
5455 /* allows RC6 residency counter to work */
5456 I915_WRITE(VLV_COUNTER_CONTROL,
5457 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5458 VLV_MEDIA_RC6_COUNT_EN |
5459 VLV_RENDER_RC6_COUNT_EN));
5460
5461 /* For now we assume BIOS is allocating and populating the PCBR */
5462 pcbr = I915_READ(VLV_PCBR);
5463
38807746
D		 5464 /* 3: Enable RC6 */
5465 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5466 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5467 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5468
5469 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5470
2b6b3a09 5471 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5472 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5473 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5474 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5475 I915_WRITE(GEN6_RP_UP_EI, 66000);
5476 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5477
5478 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5479
5480 /* 5: Enable RPS */
5481 I915_WRITE(GEN6_RP_CONTROL,
5482 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5483 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5484 GEN6_RP_ENABLE |
5485 GEN6_RP_UP_BUSY_AVG |
5486 GEN6_RP_DOWN_IDLE_AVG);
5487
3ef62342
D		 5488 /* Setting Fixed Bias */
5489 val = VLV_OVERRIDE_EN |
5490 VLV_SOC_TDP_EN |
5491 CHV_BIAS_CPU_50_SOC_50;
5492 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5493
2b6b3a09
D		 5494 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5495
8d40c3ae
VS		 5496 /* RPS code assumes GPLL is used */
5497 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5498
742f491d 5499 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5500 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5501
5502 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5503 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5504 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5505 dev_priv->rps.cur_freq);
5506
5507 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5508 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5509 dev_priv->rps.efficient_freq);
5510
5511 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5512
59bad947 5513 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5514}
5515
0a073b84
JB		 5516static void valleyview_enable_rps(struct drm_device *dev)
5517{
5518 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5519 struct intel_engine_cs *ring;
2a5913a8 5520 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5521 int i;
5522
5523 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5524
ae48434c
ID		 5525 valleyview_check_pctx(dev_priv);
5526
0a073b84 5527 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5528 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5529 gtfifodbg);
0a073b84
JB		 5530 I915_WRITE(GTFIFODBG, gtfifodbg);
5531 }
5532
c8d9a590 5533 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5534 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5535
160614a2
VS		 5536 /* Disable RC states. */
5537 I915_WRITE(GEN6_RC_CONTROL, 0);
5538
cad725fe 5539 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5540 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5541 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5542 I915_WRITE(GEN6_RP_UP_EI, 66000);
5543 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5544
5545 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5546
5547 I915_WRITE(GEN6_RP_CONTROL,
5548 GEN6_RP_MEDIA_TURBO |
5549 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5550 GEN6_RP_MEDIA_IS_GFX |
5551 GEN6_RP_ENABLE |
5552 GEN6_RP_UP_BUSY_AVG |
5553 GEN6_RP_DOWN_IDLE_CONT);
5554
5555 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5556 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5557 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5558
5559 for_each_ring(ring, dev_priv, i)
5560 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5561
2f0aa304 5562 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5563
5564 /* allows RC6 residency counter to work */
49798eb2 5565 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5566 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5567 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5568 VLV_MEDIA_RC6_COUNT_EN |
5569 VLV_RENDER_RC6_COUNT_EN));
31685c25 5570
a2b23fe0 5571 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5572 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5573
5574 intel_print_rc6_info(dev, rc6_mode);
5575
a2b23fe0 5576 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5577
3ef62342
D		 5578 /* Setting Fixed Bias */
5579 val = VLV_OVERRIDE_EN |
5580 VLV_SOC_TDP_EN |
5581 VLV_BIAS_CPU_125_SOC_875;
5582 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5583
64936258 5584 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5585
8d40c3ae
VS		 5586 /* RPS code assumes GPLL is used */
5587 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5588
742f491d 5589 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5590 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5591
b39fb297 5592 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5593 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5594 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5595 dev_priv->rps.cur_freq);
0a073b84 5596
73008b98 5597 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5598 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5599 dev_priv->rps.efficient_freq);
0a073b84 5600
b39fb297 5601 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5602
59bad947 5603 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5604}
5605
dde18883
ED		 5606static unsigned long intel_pxfreq(u32 vidfreq)
5607{
5608 unsigned long freq;
5609 int div = (vidfreq & 0x3f0000) >> 16;
5610 int post = (vidfreq & 0x3000) >> 12;
5611 int pre = (vidfreq & 0x7);
5612
5613 if (!pre)
5614 return 0;
5615
5616 freq = ((div * 133333) / ((1<<post) * pre));
5617
5618 return freq;
5619}
5620
eb48eb00
DV		 5621static const struct cparams {
5622 u16 i;
5623 u16 t;
5624 u16 m;
5625 u16 c;
5626} cparams[] = {
5627 { 1, 1333, 301, 28664 },
5628 { 1, 1066, 294, 24460 },
5629 { 1, 800, 294, 25192 },
5630 { 0, 1333, 276, 27605 },
5631 { 0, 1066, 276, 27605 },
5632 { 0, 800, 231, 23784 },
5633};
5634
f531dcb2 5635static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5636{
5637 u64 total_count, diff, ret;
5638 u32 count1, count2, count3, m = 0, c = 0;
5639 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5640 int i;
5641
02d71956
DV		 5642 assert_spin_locked(&mchdev_lock);
5643
20e4d407 5644 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5645
5646 /* Prevent division-by-zero if we are asking too fast.
5647 * Also, we don't get interesting results if we are polling
5648 * faster than once in 10ms, so just return the saved value
5649 * in such cases.
5650 */
5651 if (diff1 <= 10)
20e4d407 5652 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5653
5654 count1 = I915_READ(DMIEC);
5655 count2 = I915_READ(DDREC);
5656 count3 = I915_READ(CSIEC);
5657
5658 total_count = count1 + count2 + count3;
5659
5660 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5661 if (total_count < dev_priv->ips.last_count1) {
5662 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5663 diff += total_count;
5664 } else {
20e4d407 5665 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5666 }
5667
5668 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5669 if (cparams[i].i == dev_priv->ips.c_m &&
5670 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5671 m = cparams[i].m;
5672 c = cparams[i].c;
5673 break;
5674 }
5675 }
5676
5677 diff = div_u64(diff, diff1);
5678 ret = ((m * diff) + c);
5679 ret = div_u64(ret, 10);
5680
20e4d407
DV		 5681 dev_priv->ips.last_count1 = total_count;
5682 dev_priv->ips.last_time1 = now;
eb48eb00 5683
20e4d407 5684 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5685
5686 return ret;
5687}
5688
f531dcb2
CW		 5689unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5690{
3d13ef2e 5691 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5692 unsigned long val;
5693
3d13ef2e 5694 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5695 return 0;
5696
5697 spin_lock_irq(&mchdev_lock);
5698
5699 val = __i915_chipset_val(dev_priv);
5700
5701 spin_unlock_irq(&mchdev_lock);
5702
5703 return val;
5704}
5705
eb48eb00
DV		 5706unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5707{
5708 unsigned long m, x, b;
5709 u32 tsfs;
5710
5711 tsfs = I915_READ(TSFS);
5712
5713 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5714 x = I915_READ8(TR1);
5715
5716 b = tsfs & TSFS_INTR_MASK;
5717
5718 return ((m * x) / 127) - b;
5719}
5720
d972d6ee
MK		 5721static int _pxvid_to_vd(u8 pxvid)
5722{
5723 if (pxvid == 0)
5724 return 0;
5725
5726 if (pxvid >= 8 && pxvid < 31)
5727 pxvid = 31;
5728
5729 return (pxvid + 2) * 125;
5730}
5731
5732static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5733{
3d13ef2e 5734 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5735 const int vd = _pxvid_to_vd(pxvid);
5736 const int vm = vd - 1125;
5737
3d13ef2e 5738 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5739 return vm > 0 ? vm : 0;
5740
5741 return vd;
eb48eb00
DV		 5742}
5743
02d71956 5744static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5745{
5ed0bdf2 5746 u64 now, diff, diffms;
eb48eb00
DV		 5747 u32 count;
5748
02d71956 5749 assert_spin_locked(&mchdev_lock);
eb48eb00 5750
5ed0bdf2
TG		 5751 now = ktime_get_raw_ns();
5752 diffms = now - dev_priv->ips.last_time2;
5753 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5754
5755 /* Don't divide by 0 */
eb48eb00
DV		 5756 if (!diffms)
5757 return;
5758
5759 count = I915_READ(GFXEC);
5760
20e4d407
DV		 5761 if (count < dev_priv->ips.last_count2) {
5762 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5763 diff += count;
5764 } else {
20e4d407 5765 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5766 }
5767
20e4d407
DV		 5768 dev_priv->ips.last_count2 = count;
5769 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5770
5771 /* More magic constants... */
5772 diff = diff * 1181;
5773 diff = div_u64(diff, diffms * 10);
20e4d407 5774 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5775}
5776
02d71956
DV		 5777void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5778{
3d13ef2e
DL		 5779 struct drm_device *dev = dev_priv->dev;
5780
5781 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5782 return;
5783
9270388e 5784 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5785
5786 __i915_update_gfx_val(dev_priv);
5787
9270388e 5788 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5789}
5790
f531dcb2 5791static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5792{
5793 unsigned long t, corr, state1, corr2, state2;
5794 u32 pxvid, ext_v;
5795
02d71956
DV		 5796 assert_spin_locked(&mchdev_lock);
5797
616847e7 5798 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5799 pxvid = (pxvid >> 24) & 0x7f;
5800 ext_v = pvid_to_extvid(dev_priv, pxvid);
5801
5802 state1 = ext_v;
5803
5804 t = i915_mch_val(dev_priv);
5805
5806 /* Revel in the empirically derived constants */
5807
5808 /* Correction factor in 1/100000 units */
5809 if (t > 80)
5810 corr = ((t * 2349) + 135940);
5811 else if (t >= 50)
5812 corr = ((t * 964) + 29317);
5813 else /* < 50 */
5814 corr = ((t * 301) + 1004);
5815
5816 corr = corr * ((150142 * state1) / 10000 - 78642);
5817 corr /= 100000;
20e4d407 5818 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5819
5820 state2 = (corr2 * state1) / 10000;
5821 state2 /= 100; /* convert to mW */
5822
02d71956 5823 __i915_update_gfx_val(dev_priv);
eb48eb00 5824
20e4d407 5825 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5826}
5827
f531dcb2
CW		 5828unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5829{
3d13ef2e 5830 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5831 unsigned long val;
5832
3d13ef2e 5833 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5834 return 0;
5835
5836 spin_lock_irq(&mchdev_lock);
5837
5838 val = __i915_gfx_val(dev_priv);
5839
5840 spin_unlock_irq(&mchdev_lock);
5841
5842 return val;
5843}
5844
eb48eb00
DV		 5845/**
5846 * i915_read_mch_val - return value for IPS use
5847 *
5848 * Calculate and return a value for the IPS driver to use when deciding whether
5849 * we have thermal and power headroom to increase CPU or GPU power budget.
5850 */
5851unsigned long i915_read_mch_val(void)
5852{
5853 struct drm_i915_private *dev_priv;
5854 unsigned long chipset_val, graphics_val, ret = 0;
5855
9270388e 5856 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5857 if (!i915_mch_dev)
5858 goto out_unlock;
5859 dev_priv = i915_mch_dev;
5860
f531dcb2
CW		 5861 chipset_val = __i915_chipset_val(dev_priv);
5862 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5863
5864 ret = chipset_val + graphics_val;
5865
5866out_unlock:
9270388e 5867 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5868
5869 return ret;
5870}
5871EXPORT_SYMBOL_GPL(i915_read_mch_val);
5872
5873/**
5874 * i915_gpu_raise - raise GPU frequency limit
5875 *
5876 * Raise the limit; IPS indicates we have thermal headroom.
5877 */
5878bool i915_gpu_raise(void)
5879{
5880 struct drm_i915_private *dev_priv;
5881 bool ret = true;
5882
9270388e 5883 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5884 if (!i915_mch_dev) {
5885 ret = false;
5886 goto out_unlock;
5887 }
5888 dev_priv = i915_mch_dev;
5889
20e4d407
DV		 5890 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5891 dev_priv->ips.max_delay--;
eb48eb00
DV		 5892
5893out_unlock:
9270388e 5894 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5895
5896 return ret;
5897}
5898EXPORT_SYMBOL_GPL(i915_gpu_raise);
5899
5900/**
5901 * i915_gpu_lower - lower GPU frequency limit
5902 *
5903 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5904 * frequency maximum.
5905 */
5906bool i915_gpu_lower(void)
5907{
5908 struct drm_i915_private *dev_priv;
5909 bool ret = true;
5910
9270388e 5911 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5912 if (!i915_mch_dev) {
5913 ret = false;
5914 goto out_unlock;
5915 }
5916 dev_priv = i915_mch_dev;
5917
20e4d407
DV		 5918 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5919 dev_priv->ips.max_delay++;
eb48eb00
DV		 5920
5921out_unlock:
9270388e 5922 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5923
5924 return ret;
5925}
5926EXPORT_SYMBOL_GPL(i915_gpu_lower);
5927
5928/**
5929 * i915_gpu_busy - indicate GPU business to IPS
5930 *
5931 * Tell the IPS driver whether or not the GPU is busy.
5932 */
5933bool i915_gpu_busy(void)
5934{
5935 struct drm_i915_private *dev_priv;
a4872ba6 5936 struct intel_engine_cs *ring;
eb48eb00 5937 bool ret = false;
f047e395 5938 int i;
eb48eb00 5939
9270388e 5940 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5941 if (!i915_mch_dev)
5942 goto out_unlock;
5943 dev_priv = i915_mch_dev;
5944
f047e395
CW		 5945 for_each_ring(ring, dev_priv, i)
5946 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5947
5948out_unlock:
9270388e 5949 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5950
5951 return ret;
5952}
5953EXPORT_SYMBOL_GPL(i915_gpu_busy);
5954
5955/**
5956 * i915_gpu_turbo_disable - disable graphics turbo
5957 *
5958 * Disable graphics turbo by resetting the max frequency and setting the
5959 * current frequency to the default.
5960 */
5961bool i915_gpu_turbo_disable(void)
5962{
5963 struct drm_i915_private *dev_priv;
5964 bool ret = true;
5965
9270388e 5966 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5967 if (!i915_mch_dev) {
5968 ret = false;
5969 goto out_unlock;
5970 }
5971 dev_priv = i915_mch_dev;
5972
20e4d407 5973 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5974
20e4d407 5975 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5976 ret = false;
5977
5978out_unlock:
9270388e 5979 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5980
5981 return ret;
5982}
5983EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5984
5985/**
5986 * Tells the intel_ips driver that the i915 driver is now loaded, if
5987 * IPS got loaded first.
5988 *
5989 * This awkward dance is so that neither module has to depend on the
5990 * other in order for IPS to do the appropriate communication of
5991 * GPU turbo limits to i915.
5992 */
5993static void
5994ips_ping_for_i915_load(void)
5995{
5996 void (*link)(void);
5997
5998 link = symbol_get(ips_link_to_i915_driver);
5999 if (link) {
6000 link();
6001 symbol_put(ips_link_to_i915_driver);
6002 }
6003}
6004
6005void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6006{
02d71956
DV		 6007 /* We only register the i915 ips part with intel-ips once everything is
6008 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6009 spin_lock_irq(&mchdev_lock);
eb48eb00 6010 i915_mch_dev = dev_priv;
9270388e 6011 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6012
6013 ips_ping_for_i915_load();
6014}
6015
6016void intel_gpu_ips_teardown(void)
6017{
9270388e 6018 spin_lock_irq(&mchdev_lock);
eb48eb00 6019 i915_mch_dev = NULL;
9270388e 6020 spin_unlock_irq(&mchdev_lock);
eb48eb00 6021}
76c3552f 6022
8090c6b9 6023static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6024{
6025 struct drm_i915_private *dev_priv = dev->dev_private;
6026 u32 lcfuse;
6027 u8 pxw[16];
6028 int i;
6029
6030 /* Disable to program */
6031 I915_WRITE(ECR, 0);
6032 POSTING_READ(ECR);
6033
6034 /* Program energy weights for various events */
6035 I915_WRITE(SDEW, 0x15040d00);
6036 I915_WRITE(CSIEW0, 0x007f0000);
6037 I915_WRITE(CSIEW1, 0x1e220004);
6038 I915_WRITE(CSIEW2, 0x04000004);
6039
6040 for (i = 0; i < 5; i++)
616847e7 6041 I915_WRITE(PEW(i), 0);
dde18883 6042 for (i = 0; i < 3; i++)
616847e7 6043 I915_WRITE(DEW(i), 0);
dde18883
ED		 6044
6045 /* Program P-state weights to account for frequency power adjustment */
6046 for (i = 0; i < 16; i++) {
616847e7 6047 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6048 unsigned long freq = intel_pxfreq(pxvidfreq);
6049 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6050 PXVFREQ_PX_SHIFT;
6051 unsigned long val;
6052
6053 val = vid * vid;
6054 val *= (freq / 1000);
6055 val *= 255;
6056 val /= (127*127*900);
6057 if (val > 0xff)
6058 DRM_ERROR("bad pxval: %ld\n", val);
6059 pxw[i] = val;
6060 }
6061 /* Render standby states get 0 weight */
6062 pxw[14] = 0;
6063 pxw[15] = 0;
6064
6065 for (i = 0; i < 4; i++) {
6066 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6067 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6068 I915_WRITE(PXW(i), val);
dde18883
ED		 6069 }
6070
6071 /* Adjust magic regs to magic values (more experimental results) */
6072 I915_WRITE(OGW0, 0);
6073 I915_WRITE(OGW1, 0);
6074 I915_WRITE(EG0, 0x00007f00);
6075 I915_WRITE(EG1, 0x0000000e);
6076 I915_WRITE(EG2, 0x000e0000);
6077 I915_WRITE(EG3, 0x68000300);
6078 I915_WRITE(EG4, 0x42000000);
6079 I915_WRITE(EG5, 0x00140031);
6080 I915_WRITE(EG6, 0);
6081 I915_WRITE(EG7, 0);
6082
6083 for (i = 0; i < 8; i++)
616847e7 6084 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6085
6086 /* Enable PMON + select events */
6087 I915_WRITE(ECR, 0x80000019);
6088
6089 lcfuse = I915_READ(LCFUSE02);
6090
20e4d407 6091 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6092}
6093
ae48434c
ID		 6094void intel_init_gt_powersave(struct drm_device *dev)
6095{
b268c699
ID		 6096 struct drm_i915_private *dev_priv = dev->dev_private;
6097
e6069ca8 6098 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
b268c699
ID		 6099 /*
6100 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6101 * requirement.
6102 */
6103 if (!i915.enable_rc6) {
6104 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6105 intel_runtime_pm_get(dev_priv);
6106 }
e6069ca8 6107
38807746
D		 6108 if (IS_CHERRYVIEW(dev))
6109 cherryview_init_gt_powersave(dev);
6110 else if (IS_VALLEYVIEW(dev))
4e80519e 6111 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6112}
6113
6114void intel_cleanup_gt_powersave(struct drm_device *dev)
6115{
b268c699
ID		 6116 struct drm_i915_private *dev_priv = dev->dev_private;
6117
38807746
D		 6118 if (IS_CHERRYVIEW(dev))
6119 return;
6120 else if (IS_VALLEYVIEW(dev))
4e80519e 6121 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6122
6123 if (!i915.enable_rc6)
6124 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6125}
6126
dbea3cea
ID		 6127static void gen6_suspend_rps(struct drm_device *dev)
6128{
6129 struct drm_i915_private *dev_priv = dev->dev_private;
6130
6131 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6132
4c2a8897 6133 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6134}
6135
156c7ca0
JB		 6136/**
6137 * intel_suspend_gt_powersave - suspend PM work and helper threads
6138 * @dev: drm device
6139 *
6140 * We don't want to disable RC6 or other features here, we just want
6141 * to make sure any work we've queued has finished and won't bother
6142 * us while we're suspended.
6143 */
6144void intel_suspend_gt_powersave(struct drm_device *dev)
6145{
6146 struct drm_i915_private *dev_priv = dev->dev_private;
6147
d4d70aa5
ID		 6148 if (INTEL_INFO(dev)->gen < 6)
6149 return;
6150
dbea3cea 6151 gen6_suspend_rps(dev);
b47adc17
D		 6152
6153 /* Force GPU to min freq during suspend */
6154 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6155}
6156
8090c6b9
DV		 6157void intel_disable_gt_powersave(struct drm_device *dev)
6158{
1a01ab3b
JB		 6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160
930ebb46 6161 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6162 ironlake_disable_drps(dev);
38807746 6163 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6164 intel_suspend_gt_powersave(dev);
e494837a 6165
4fc688ce 6166 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6167 if (INTEL_INFO(dev)->gen >= 9)
6168 gen9_disable_rps(dev);
6169 else if (IS_CHERRYVIEW(dev))
38807746
D		 6170 cherryview_disable_rps(dev);
6171 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6172 valleyview_disable_rps(dev);
6173 else
6174 gen6_disable_rps(dev);
e534770a 6175
c0951f0c 6176 dev_priv->rps.enabled = false;
4fc688ce 6177 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6178 }
8090c6b9
DV		 6179}
6180
1a01ab3b
JB		 6181static void intel_gen6_powersave_work(struct work_struct *work)
6182{
6183 struct drm_i915_private *dev_priv =
6184 container_of(work, struct drm_i915_private,
6185 rps.delayed_resume_work.work);
6186 struct drm_device *dev = dev_priv->dev;
6187
4fc688ce 6188 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6189
4c2a8897 6190 gen6_reset_rps_interrupts(dev);
3cc134e3 6191
38807746
D		 6192 if (IS_CHERRYVIEW(dev)) {
6193 cherryview_enable_rps(dev);
6194 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6195 valleyview_enable_rps(dev);
20e49366 6196 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6197 gen9_enable_rc6(dev);
20e49366 6198 gen9_enable_rps(dev);
ef11bdb3 6199 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6200 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6201 } else if (IS_BROADWELL(dev)) {
6202 gen8_enable_rps(dev);
c2bc2fc5 6203 __gen6_update_ring_freq(dev);
0a073b84
JB		 6204 } else {
6205 gen6_enable_rps(dev);
c2bc2fc5 6206 __gen6_update_ring_freq(dev);
0a073b84 6207 }
aed242ff
CW		 6208
6209 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6210 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6211
6212 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6213 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6214
c0951f0c 6215 dev_priv->rps.enabled = true;
3cc134e3 6216
4c2a8897 6217 gen6_enable_rps_interrupts(dev);
3cc134e3 6218
4fc688ce 6219 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6220
6221 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6222}
6223
8090c6b9
DV		 6224void intel_enable_gt_powersave(struct drm_device *dev)
6225{
1a01ab3b
JB		 6226 struct drm_i915_private *dev_priv = dev->dev_private;
6227
f61018b1
YZ		 6228 /* Powersaving is controlled by the host when inside a VM */
6229 if (intel_vgpu_active(dev))
6230 return;
6231
8090c6b9 6232 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6233 mutex_lock(&dev->struct_mutex);
8090c6b9 6234 ironlake_enable_drps(dev);
8090c6b9 6235 intel_init_emon(dev);
dc1d0136 6236 mutex_unlock(&dev->struct_mutex);
38807746 6237 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6238 /*
6239 * PCU communication is slow and this doesn't need to be
6240 * done at any specific time, so do this out of our fast path
6241 * to make resume and init faster.
c6df39b5
ID		 6242 *
6243 * We depend on the HW RC6 power context save/restore
6244 * mechanism when entering D3 through runtime PM suspend. So
6245 * disable RPM until RPS/RC6 is properly setup. We can only
6246 * get here via the driver load/system resume/runtime resume
6247 * paths, so the _noresume version is enough (and in case of
6248 * runtime resume it's necessary).
1a01ab3b 6249 */
c6df39b5
ID		 6250 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6251 round_jiffies_up_relative(HZ)))
6252 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6253 }
6254}
6255
c6df39b5
ID		 6256void intel_reset_gt_powersave(struct drm_device *dev)
6257{
6258 struct drm_i915_private *dev_priv = dev->dev_private;
6259
dbea3cea
ID		 6260 if (INTEL_INFO(dev)->gen < 6)
6261 return;
6262
6263 gen6_suspend_rps(dev);
c6df39b5 6264 dev_priv->rps.enabled = false;
c6df39b5
ID		 6265}
6266
3107bd48
DV		 6267static void ibx_init_clock_gating(struct drm_device *dev)
6268{
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6270
6271 /*
6272 * On Ibex Peak and Cougar Point, we need to disable clock
6273 * gating for the panel power sequencer or it will fail to
6274 * start up when no ports are active.
6275 */
6276 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6277}
6278
0e088b8f
VS		 6279static void g4x_disable_trickle_feed(struct drm_device *dev)
6280{
6281 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6282 enum pipe pipe;
0e088b8f 6283
055e393f 6284 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6285 I915_WRITE(DSPCNTR(pipe),
6286 I915_READ(DSPCNTR(pipe)) |
6287 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6288
6289 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6290 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6291 }
6292}
6293
017636cc
VS		 6294static void ilk_init_lp_watermarks(struct drm_device *dev)
6295{
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297
6298 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6299 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6300 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6301
6302 /*
6303 * Don't touch WM1S_LP_EN here.
6304 * Doing so could cause underruns.
6305 */
6306}
6307
1fa61106 6308static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6309{
6310 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6311 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6312
f1e8fa56
DL		 6313 /*
6314 * Required for FBC
6315 * WaFbcDisableDpfcClockGating:ilk
6316 */
4d47e4f5
DL		 6317 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6318 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6319 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6320
6321 I915_WRITE(PCH_3DCGDIS0,
6322 MARIUNIT_CLOCK_GATE_DISABLE |
6323 SVSMUNIT_CLOCK_GATE_DISABLE);
6324 I915_WRITE(PCH_3DCGDIS1,
6325 VFMUNIT_CLOCK_GATE_DISABLE);
6326
6f1d69b0
ED		 6327 /*
6328 * According to the spec the following bits should be set in
6329 * order to enable memory self-refresh
6330 * The bit 22/21 of 0x42004
6331 * The bit 5 of 0x42020
6332 * The bit 15 of 0x45000
6333 */
6334 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6335 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6336 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6337 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6338 I915_WRITE(DISP_ARB_CTL,
6339 (I915_READ(DISP_ARB_CTL) |
6340 DISP_FBC_WM_DIS));
017636cc
VS		 6341
6342 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6343
6344 /*
6345 * Based on the document from hardware guys the following bits
6346 * should be set unconditionally in order to enable FBC.
6347 * The bit 22 of 0x42000
6348 * The bit 22 of 0x42004
6349 * The bit 7,8,9 of 0x42020.
6350 */
6351 if (IS_IRONLAKE_M(dev)) {
4bb35334 6352 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6353 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6354 I915_READ(ILK_DISPLAY_CHICKEN1) |
6355 ILK_FBCQ_DIS);
6356 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6357 I915_READ(ILK_DISPLAY_CHICKEN2) |
6358 ILK_DPARB_GATE);
6f1d69b0
ED		 6359 }
6360
4d47e4f5
DL		 6361 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6362
6f1d69b0
ED		 6363 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6364 I915_READ(ILK_DISPLAY_CHICKEN2) |
6365 ILK_ELPIN_409_SELECT);
6366 I915_WRITE(_3D_CHICKEN2,
6367 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6368 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6369
ecdb4eb7 6370 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6371 I915_WRITE(CACHE_MODE_0,
6372 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6373
4e04632e
AG		 6374 /* WaDisable_RenderCache_OperationalFlush:ilk */
6375 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6376
0e088b8f 6377 g4x_disable_trickle_feed(dev);
bdad2b2f 6378
3107bd48
DV		 6379 ibx_init_clock_gating(dev);
6380}
6381
6382static void cpt_init_clock_gating(struct drm_device *dev)
6383{
6384 struct drm_i915_private *dev_priv = dev->dev_private;
6385 int pipe;
3f704fa2 6386 uint32_t val;
3107bd48
DV		 6387
6388 /*
6389 * On Ibex Peak and Cougar Point, we need to disable clock
6390 * gating for the panel power sequencer or it will fail to
6391 * start up when no ports are active.
6392 */
cd664078
JB		 6393 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6394 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6395 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6396 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6397 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6398 /* The below fixes the weird display corruption, a few pixels shifted
6399 * downward, on (only) LVDS of some HP laptops with IVY.
6400 */
055e393f 6401 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6402 val = I915_READ(TRANS_CHICKEN2(pipe));
6403 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6404 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6405 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6406 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6407 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6408 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6409 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6410 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6411 }
3107bd48 6412 /* WADP0ClockGatingDisable */
055e393f 6413 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6414 I915_WRITE(TRANS_CHICKEN1(pipe),
6415 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6416 }
6f1d69b0
ED		 6417}
6418
1d7aaa0c
DV		 6419static void gen6_check_mch_setup(struct drm_device *dev)
6420{
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 uint32_t tmp;
6423
6424 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6425 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6426 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6427 tmp);
1d7aaa0c
DV		 6428}
6429
1fa61106 6430static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6431{
6432 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6433 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6434
231e54f6 6435 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6436
6437 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6438 I915_READ(ILK_DISPLAY_CHICKEN2) |
6439 ILK_ELPIN_409_SELECT);
6440
ecdb4eb7 6441 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6442 I915_WRITE(_3D_CHICKEN,
6443 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6444
4e04632e
AG		 6445 /* WaDisable_RenderCache_OperationalFlush:snb */
6446 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6447
8d85d272
VS		 6448 /*
6449 * BSpec recoomends 8x4 when MSAA is used,
6450 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6451 *
6452 * Note that PS/WM thread counts depend on the WIZ hashing
6453 * disable bit, which we don't touch here, but it's good
6454 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6455 */
6456 I915_WRITE(GEN6_GT_MODE,
98533251 6457 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6458
017636cc 6459 ilk_init_lp_watermarks(dev);
6f1d69b0 6460
6f1d69b0 6461 I915_WRITE(CACHE_MODE_0,
50743298 6462 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6463
6464 I915_WRITE(GEN6_UCGCTL1,
6465 I915_READ(GEN6_UCGCTL1) |
6466 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6467 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6468
6469 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6470 * gating disable must be set. Failure to set it results in
6471 * flickering pixels due to Z write ordering failures after
6472 * some amount of runtime in the Mesa "fire" demo, and Unigine
6473 * Sanctuary and Tropics, and apparently anything else with
6474 * alpha test or pixel discard.
6475 *
6476 * According to the spec, bit 11 (RCCUNIT) must also be set,
6477 * but we didn't debug actual testcases to find it out.
0f846f81 6478 *
ef59318c
VS		 6479 * WaDisableRCCUnitClockGating:snb
6480 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6481 */
6482 I915_WRITE(GEN6_UCGCTL2,
6483 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6484 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6485
5eb146dd 6486 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6487 I915_WRITE(_3D_CHICKEN3,
6488 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6489
e927ecde
VS		 6490 /*
6491 * Bspec says:
6492 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6493 * 3DSTATE_SF number of SF output attributes is more than 16."
6494 */
6495 I915_WRITE(_3D_CHICKEN3,
6496 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6497
6f1d69b0
ED		 6498 /*
6499 * According to the spec the following bits should be
6500 * set in order to enable memory self-refresh and fbc:
6501 * The bit21 and bit22 of 0x42000
6502 * The bit21 and bit22 of 0x42004
6503 * The bit5 and bit7 of 0x42020
6504 * The bit14 of 0x70180
6505 * The bit14 of 0x71180
4bb35334
DL		 6506 *
6507 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6508 */
6509 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6510 I915_READ(ILK_DISPLAY_CHICKEN1) |
6511 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6512 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6513 I915_READ(ILK_DISPLAY_CHICKEN2) |
6514 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6515 I915_WRITE(ILK_DSPCLK_GATE_D,
6516 I915_READ(ILK_DSPCLK_GATE_D) |
6517 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6518 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6519
0e088b8f 6520 g4x_disable_trickle_feed(dev);
f8f2ac9a 6521
3107bd48 6522 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6523
6524 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6525}
6526
6527static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6528{
6529 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6530
3aad9059 6531 /*
46680e0a 6532 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6533 *
6534 * This actually overrides the dispatch
6535 * mode for all thread types.
6536 */
6f1d69b0
ED		 6537 reg &= ~GEN7_FF_SCHED_MASK;
6538 reg |= GEN7_FF_TS_SCHED_HW;
6539 reg |= GEN7_FF_VS_SCHED_HW;
6540 reg |= GEN7_FF_DS_SCHED_HW;
6541
6542 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6543}
6544
17a303ec
PZ		 6545static void lpt_init_clock_gating(struct drm_device *dev)
6546{
6547 struct drm_i915_private *dev_priv = dev->dev_private;
6548
6549 /*
6550 * TODO: this bit should only be enabled when really needed, then
6551 * disabled when not needed anymore in order to save power.
6552 */
c2699524 6553 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6554 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6555 I915_READ(SOUTH_DSPCLK_GATE_D) |
6556 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6557
6558 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6559 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6560 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6561 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6562}
6563
7d708ee4
ID		 6564static void lpt_suspend_hw(struct drm_device *dev)
6565{
6566 struct drm_i915_private *dev_priv = dev->dev_private;
6567
c2699524 6568 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6569 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6570
6571 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6572 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6573 }
6574}
6575
47c2bd97 6576static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6577{
6578 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6579 enum pipe pipe;
4d487cff 6580 uint32_t misccpctl;
1020a5c2 6581
7ad0dbab 6582 ilk_init_lp_watermarks(dev);
50ed5fbd 6583
ab57fff1 6584 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6585 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6586
ab57fff1 6587 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6588 I915_WRITE(CHICKEN_PAR1_1,
6589 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6590
ab57fff1 6591 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6592 for_each_pipe(dev_priv, pipe) {
07d27e20 6593 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6594 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6595 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6596 }
63801f21 6597
ab57fff1
BW		 6598 /* WaVSRefCountFullforceMissDisable:bdw */
6599 /* WaDSRefCountFullforceMissDisable:bdw */
6600 I915_WRITE(GEN7_FF_THREAD_MODE,
6601 I915_READ(GEN7_FF_THREAD_MODE) &
6602 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6603
295e8bb7
VS		 6604 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6605 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6606
6607 /* WaDisableSDEUnitClockGating:bdw */
6608 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6609 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6610
4d487cff
VS		 6611 /*
6612 * WaProgramL3SqcReg1Default:bdw
6613 * WaTempDisableDOPClkGating:bdw
6614 */
6615 misccpctl = I915_READ(GEN7_MISCCPCTL);
6616 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6617 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6618 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6619
6d50b065
VS		 6620 /*
6621 * WaGttCachingOffByDefault:bdw
6622 * GTT cache may not work with big pages, so if those
6623 * are ever enabled GTT cache may need to be disabled.
6624 */
6625 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6626
89d6b2b8 6627 lpt_init_clock_gating(dev);
1020a5c2
BW		 6628}
6629
cad2a2d7
ED		 6630static void haswell_init_clock_gating(struct drm_device *dev)
6631{
6632 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6633
017636cc 6634 ilk_init_lp_watermarks(dev);
cad2a2d7 6635
f3fc4884
FJ		 6636 /* L3 caching of data atomics doesn't work -- disable it. */
6637 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6638 I915_WRITE(HSW_ROW_CHICKEN3,
6639 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6640
ecdb4eb7 6641 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6642 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6643 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6644 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6645
e36ea7ff
VS		 6646 /* WaVSRefCountFullforceMissDisable:hsw */
6647 I915_WRITE(GEN7_FF_THREAD_MODE,
6648 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6649
4e04632e
AG		 6650 /* WaDisable_RenderCache_OperationalFlush:hsw */
6651 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6652
fe27c606
CW		 6653 /* enable HiZ Raw Stall Optimization */
6654 I915_WRITE(CACHE_MODE_0_GEN7,
6655 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6656
ecdb4eb7 6657 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6658 I915_WRITE(CACHE_MODE_1,
6659 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6660
a12c4967
VS		 6661 /*
6662 * BSpec recommends 8x4 when MSAA is used,
6663 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6664 *
6665 * Note that PS/WM thread counts depend on the WIZ hashing
6666 * disable bit, which we don't touch here, but it's good
6667 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6668 */
6669 I915_WRITE(GEN7_GT_MODE,
98533251 6670 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6671
94411593
KG		 6672 /* WaSampleCChickenBitEnable:hsw */
6673 I915_WRITE(HALF_SLICE_CHICKEN3,
6674 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6675
ecdb4eb7 6676 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6677 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6678
90a88643
PZ		 6679 /* WaRsPkgCStateDisplayPMReq:hsw */
6680 I915_WRITE(CHICKEN_PAR1_1,
6681 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6682
17a303ec 6683 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6684}
6685
1fa61106 6686static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6687{
6688 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6689 uint32_t snpcr;
6f1d69b0 6690
017636cc 6691 ilk_init_lp_watermarks(dev);
6f1d69b0 6692
231e54f6 6693 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6694
ecdb4eb7 6695 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6696 I915_WRITE(_3D_CHICKEN3,
6697 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6698
ecdb4eb7 6699 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6700 I915_WRITE(IVB_CHICKEN3,
6701 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6702 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6703
ecdb4eb7 6704 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6705 if (IS_IVB_GT1(dev))
6706 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6707 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6708
4e04632e
AG		 6709 /* WaDisable_RenderCache_OperationalFlush:ivb */
6710 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6711
ecdb4eb7 6712 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6713 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6714 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6715
ecdb4eb7 6716 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6717 I915_WRITE(GEN7_L3CNTLREG1,
6718 GEN7_WA_FOR_GEN7_L3_CONTROL);
6719 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6720 GEN7_WA_L3_CHICKEN_MODE);
6721 if (IS_IVB_GT1(dev))
6722 I915_WRITE(GEN7_ROW_CHICKEN2,
6723 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6724 else {
6725 /* must write both registers */
6726 I915_WRITE(GEN7_ROW_CHICKEN2,
6727 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6728 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6729 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6730 }
6f1d69b0 6731
ecdb4eb7 6732 /* WaForceL3Serialization:ivb */
61939d97
JB		 6733 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6734 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6735
1b80a19a 6736 /*
0f846f81 6737 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6738 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6739 */
6740 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6741 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6742
ecdb4eb7 6743 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6744 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6745 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6746 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6747
0e088b8f 6748 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6749
6750 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6751
22721343
CW		 6752 if (0) { /* causes HiZ corruption on ivb:gt1 */
6753 /* enable HiZ Raw Stall Optimization */
6754 I915_WRITE(CACHE_MODE_0_GEN7,
6755 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6756 }
116f2b6d 6757
ecdb4eb7 6758 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6759 I915_WRITE(CACHE_MODE_1,
6760 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6761
a607c1a4
VS		 6762 /*
6763 * BSpec recommends 8x4 when MSAA is used,
6764 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6765 *
6766 * Note that PS/WM thread counts depend on the WIZ hashing
6767 * disable bit, which we don't touch here, but it's good
6768 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6769 */
6770 I915_WRITE(GEN7_GT_MODE,
98533251 6771 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6772
20848223
BW		 6773 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6774 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6775 snpcr |= GEN6_MBC_SNPCR_MED;
6776 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6777
ab5c608b
BW		 6778 if (!HAS_PCH_NOP(dev))
6779 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6780
6781 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6782}
6783
c6beb13e
VS		 6784static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6785{
6786 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6787
6788 /*
6789 * Disable trickle feed and enable pnd deadline calculation
6790 */
6791 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6792 I915_WRITE(CBR1_VLV, 0);
6793}
6794
1fa61106 6795static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6796{
6797 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6798
c6beb13e 6799 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6800
ecdb4eb7 6801 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6802 I915_WRITE(_3D_CHICKEN3,
6803 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6804
ecdb4eb7 6805 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6806 I915_WRITE(IVB_CHICKEN3,
6807 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6808 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6809
fad7d36e 6810 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6811 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6812 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6813 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6814 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6815
4e04632e
AG		 6816 /* WaDisable_RenderCache_OperationalFlush:vlv */
6817 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6818
ecdb4eb7 6819 /* WaForceL3Serialization:vlv */
61939d97
JB		 6820 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6821 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6822
ecdb4eb7 6823 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6824 I915_WRITE(GEN7_ROW_CHICKEN2,
6825 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6826
ecdb4eb7 6827 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6828 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6829 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6830 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6831
46680e0a
VS		 6832 gen7_setup_fixed_func_scheduler(dev_priv);
6833
3c0edaeb 6834 /*
0f846f81 6835 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6836 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6837 */
6838 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6839 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6840
c98f5062
AG		 6841 /* WaDisableL3Bank2xClockGate:vlv
6842 * Disabling L3 clock gating- MMIO 940c[25] = 1
6843 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6844 I915_WRITE(GEN7_UCGCTL4,
6845 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6846
afd58e79
VS		 6847 /*
6848 * BSpec says this must be set, even though
6849 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6850 */
6b26c86d
DV		 6851 I915_WRITE(CACHE_MODE_1,
6852 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6853
da2518f9
VS		 6854 /*
6855 * BSpec recommends 8x4 when MSAA is used,
6856 * however in practice 16x4 seems fastest.
6857 *
6858 * Note that PS/WM thread counts depend on the WIZ hashing
6859 * disable bit, which we don't touch here, but it's good
6860 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6861 */
6862 I915_WRITE(GEN7_GT_MODE,
6863 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6864
031994ee
VS		 6865 /*
6866 * WaIncreaseL3CreditsForVLVB0:vlv
6867 * This is the hardware default actually.
6868 */
6869 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6870
2d809570 6871 /*
ecdb4eb7 6872 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6873 * Disable clock gating on th GCFG unit to prevent a delay
6874 * in the reporting of vblank events.
6875 */
7a0d1eed 6876 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6877}
6878
a4565da8
VS		 6879static void cherryview_init_clock_gating(struct drm_device *dev)
6880{
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6882
c6beb13e 6883 vlv_init_display_clock_gating(dev_priv);
dd811e70 6884
232ce337
VS		 6885 /* WaVSRefCountFullforceMissDisable:chv */
6886 /* WaDSRefCountFullforceMissDisable:chv */
6887 I915_WRITE(GEN7_FF_THREAD_MODE,
6888 I915_READ(GEN7_FF_THREAD_MODE) &
6889 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6890
6891 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6892 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6893 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6894
6895 /* WaDisableCSUnitClockGating:chv */
6896 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6897 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6898
6899 /* WaDisableSDEUnitClockGating:chv */
6900 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6901 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6902
6903 /*
6904 * GTT cache may not work with big pages, so if those
6905 * are ever enabled GTT cache may need to be disabled.
6906 */
6907 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6908}
6909
1fa61106 6910static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6911{
6912 struct drm_i915_private *dev_priv = dev->dev_private;
6913 uint32_t dspclk_gate;
6914
6915 I915_WRITE(RENCLK_GATE_D1, 0);
6916 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6917 GS_UNIT_CLOCK_GATE_DISABLE |
6918 CL_UNIT_CLOCK_GATE_DISABLE);
6919 I915_WRITE(RAMCLK_GATE_D, 0);
6920 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6921 OVRUNIT_CLOCK_GATE_DISABLE |
6922 OVCUNIT_CLOCK_GATE_DISABLE;
6923 if (IS_GM45(dev))
6924 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6925 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6926
6927 /* WaDisableRenderCachePipelinedFlush */
6928 I915_WRITE(CACHE_MODE_0,
6929 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6930
4e04632e
AG		 6931 /* WaDisable_RenderCache_OperationalFlush:g4x */
6932 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6933
0e088b8f 6934 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6935}
6936
1fa61106 6937static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6938{
6939 struct drm_i915_private *dev_priv = dev->dev_private;
6940
6941 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6942 I915_WRITE(RENCLK_GATE_D2, 0);
6943 I915_WRITE(DSPCLK_GATE_D, 0);
6944 I915_WRITE(RAMCLK_GATE_D, 0);
6945 I915_WRITE16(DEUC, 0);
20f94967
VS		 6946 I915_WRITE(MI_ARB_STATE,
6947 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6948
6949 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6950 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6951}
6952
1fa61106 6953static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6954{
6955 struct drm_i915_private *dev_priv = dev->dev_private;
6956
6957 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6958 I965_RCC_CLOCK_GATE_DISABLE |
6959 I965_RCPB_CLOCK_GATE_DISABLE |
6960 I965_ISC_CLOCK_GATE_DISABLE |
6961 I965_FBC_CLOCK_GATE_DISABLE);
6962 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6963 I915_WRITE(MI_ARB_STATE,
6964 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6965
6966 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6967 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6968}
6969
1fa61106 6970static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6971{
6972 struct drm_i915_private *dev_priv = dev->dev_private;
6973 u32 dstate = I915_READ(D_STATE);
6974
6975 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6976 DSTATE_DOT_CLOCK_GATING;
6977 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6978
6979 if (IS_PINEVIEW(dev))
6980 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6981
6982 /* IIR "flip pending" means done if this bit is set */
6983 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6984
6985 /* interrupts should cause a wake up from C3 */
3299254f 6986 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6987
6988 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6989 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6990
6991 I915_WRITE(MI_ARB_STATE,
6992 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6993}
6994
1fa61106 6995static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6996{
6997 struct drm_i915_private *dev_priv = dev->dev_private;
6998
6999 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7000
7001 /* interrupts should cause a wake up from C3 */
7002 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7003 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7004
7005 I915_WRITE(MEM_MODE,
7006 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7007}
7008
1fa61106 7009static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7010{
7011 struct drm_i915_private *dev_priv = dev->dev_private;
7012
7013 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7014
7015 I915_WRITE(MEM_MODE,
7016 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7017 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7018}
7019
6f1d69b0
ED		 7020void intel_init_clock_gating(struct drm_device *dev)
7021{
7022 struct drm_i915_private *dev_priv = dev->dev_private;
7023
c57e3551
DL		 7024 if (dev_priv->display.init_clock_gating)
7025 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7026}
7027
7d708ee4
ID		 7028void intel_suspend_hw(struct drm_device *dev)
7029{
7030 if (HAS_PCH_LPT(dev))
7031 lpt_suspend_hw(dev);
7032}
7033
1fa61106
ED		 7034/* Set up chip specific power management-related functions */
7035void intel_init_pm(struct drm_device *dev)
7036{
7037 struct drm_i915_private *dev_priv = dev->dev_private;
7038
7ff0ebcc 7039 intel_fbc_init(dev_priv);
1fa61106 7040
c921aba8
DV		 7041 /* For cxsr */
7042 if (IS_PINEVIEW(dev))
7043 i915_pineview_get_mem_freq(dev);
7044 else if (IS_GEN5(dev))
7045 i915_ironlake_get_mem_freq(dev);
7046
1fa61106 7047 /* For FIFO watermark updates */
f5ed50cb 7048 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7049 skl_setup_wm_latency(dev);
7050
a82abe43
ID		 7051 if (IS_BROXTON(dev))
7052 dev_priv->display.init_clock_gating =
7053 bxt_init_clock_gating;
2d41c0b5 7054 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7055 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7056 ilk_setup_wm_latency(dev);
53615a5e 7057
bd602544
VS		 7058 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7059 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7060 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7061 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7062 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
396e33ae
MR		 7063 dev_priv->display.compute_intermediate_wm =
7064 ilk_compute_intermediate_wm;
7065 dev_priv->display.initial_watermarks =
7066 ilk_initial_watermarks;
7067 dev_priv->display.optimize_watermarks =
7068 ilk_optimize_watermarks;
bd602544
VS		 7069 } else {
7070 DRM_DEBUG_KMS("Failed to read display plane latency. "
7071 "Disable CxSR\n");
7072 }
7073
7074 if (IS_GEN5(dev))
1fa61106 7075 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7076 else if (IS_GEN6(dev))
1fa61106 7077 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7078 else if (IS_IVYBRIDGE(dev))
1fa61106 7079 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7080 else if (IS_HASWELL(dev))
cad2a2d7 7081 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7082 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7083 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7084 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7085 vlv_setup_wm_latency(dev);
7086
7087 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7088 dev_priv->display.init_clock_gating =
7089 cherryview_init_clock_gating;
1fa61106 7090 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7091 vlv_setup_wm_latency(dev);
7092
7093 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7094 dev_priv->display.init_clock_gating =
7095 valleyview_init_clock_gating;
1fa61106
ED		 7096 } else if (IS_PINEVIEW(dev)) {
7097 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7098 dev_priv->is_ddr3,
7099 dev_priv->fsb_freq,
7100 dev_priv->mem_freq)) {
7101 DRM_INFO("failed to find known CxSR latency "
7102 "(found ddr%s fsb freq %d, mem freq %d), "
7103 "disabling CxSR\n",
7104 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7105 dev_priv->fsb_freq, dev_priv->mem_freq);
7106 /* Disable CxSR and never update its watermark again */
5209b1f4 7107 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7108 dev_priv->display.update_wm = NULL;
7109 } else
7110 dev_priv->display.update_wm = pineview_update_wm;
7111 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7112 } else if (IS_G4X(dev)) {
7113 dev_priv->display.update_wm = g4x_update_wm;
7114 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7115 } else if (IS_GEN4(dev)) {
7116 dev_priv->display.update_wm = i965_update_wm;
7117 if (IS_CRESTLINE(dev))
7118 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7119 else if (IS_BROADWATER(dev))
7120 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7121 } else if (IS_GEN3(dev)) {
7122 dev_priv->display.update_wm = i9xx_update_wm;
7123 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7124 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7125 } else if (IS_GEN2(dev)) {
7126 if (INTEL_INFO(dev)->num_pipes == 1) {
7127 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7128 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7129 } else {
7130 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7131 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7132 }
7133
7134 if (IS_I85X(dev) || IS_I865G(dev))
7135 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7136 else
7137 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7138 } else {
7139 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7140 }
7141}
7142
151a49d0 7143int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7144{
4fc688ce 7145 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7146
7147 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7148 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7149 return -EAGAIN;
7150 }
7151
7152 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7153 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7154 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7155
7156 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7157 500)) {
7158 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7159 return -ETIMEDOUT;
7160 }
7161
7162 *val = I915_READ(GEN6_PCODE_DATA);
7163 I915_WRITE(GEN6_PCODE_DATA, 0);
7164
7165 return 0;
7166}
7167
151a49d0 7168int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7169{
4fc688ce 7170 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7171
7172 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7173 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7174 return -EAGAIN;
7175 }
7176
7177 I915_WRITE(GEN6_PCODE_DATA, val);
7178 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7179
7180 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7181 500)) {
7182 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7183 return -ETIMEDOUT;
7184 }
7185
7186 I915_WRITE(GEN6_PCODE_DATA, 0);
7187
7188 return 0;
7189}
a0e4e199 7190
dd06f88c 7191static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7192{
dd06f88c
VS		 7193 switch (czclk_freq) {
7194 case 200:
7195 return 10;
7196 case 267:
7197 return 12;
7198 case 320:
7199 case 333:
dd06f88c 7200 return 16;
ab3fb157
VS		 7201 case 400:
7202 return 20;
855ba3be
JB		 7203 default:
7204 return -1;
7205 }
dd06f88c 7206}
855ba3be 7207
dd06f88c
VS		 7208static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7209{
bfa7df01 7210 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7211
7212 div = vlv_gpu_freq_div(czclk_freq);
7213 if (div < 0)
7214 return div;
7215
7216 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7217}
7218
b55dd647 7219static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7220{
bfa7df01 7221 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7222
dd06f88c
VS		 7223 mul = vlv_gpu_freq_div(czclk_freq);
7224 if (mul < 0)
7225 return mul;
855ba3be 7226
dd06f88c 7227 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7228}
7229
b55dd647 7230static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7231{
bfa7df01 7232 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7233
dd06f88c
VS		 7234 div = vlv_gpu_freq_div(czclk_freq) / 2;
7235 if (div < 0)
7236 return div;
22b1b2f8 7237
dd06f88c 7238 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7239}
7240
b55dd647 7241static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7242{
bfa7df01 7243 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7244
dd06f88c
VS		 7245 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7246 if (mul < 0)
7247 return mul;
22b1b2f8 7248
1c14762d 7249 /* CHV needs even values */
dd06f88c 7250 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7251}
7252
616bc820 7253int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7254{
80b6dda4 7255 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7256 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7257 GEN9_FREQ_SCALER);
80b6dda4 7258 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7259 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7260 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7261 return byt_gpu_freq(dev_priv, val);
7262 else
7263 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7264}
7265
616bc820
VS		 7266int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7267{
80b6dda4 7268 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7269 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7270 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7271 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7272 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7273 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7274 return byt_freq_opcode(dev_priv, val);
7275 else
500a3d2e 7276 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7277}
22b1b2f8 7278
6ad790c0
CW		 7279struct request_boost {
7280 struct work_struct work;
eed29a5b 7281 struct drm_i915_gem_request *req;
6ad790c0
CW		 7282};
7283
7284static void __intel_rps_boost_work(struct work_struct *work)
7285{
7286 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7287 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7288
e61b9958
CW		 7289 if (!i915_gem_request_completed(req, true))
7290 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7291 req->emitted_jiffies);
6ad790c0 7292
e61b9958 7293 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7294 kfree(boost);
7295}
7296
7297void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7298 struct drm_i915_gem_request *req)
6ad790c0
CW		 7299{
7300 struct request_boost *boost;
7301
eed29a5b 7302 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7303 return;
7304
e61b9958
CW		 7305 if (i915_gem_request_completed(req, true))
7306 return;
7307
6ad790c0
CW		 7308 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7309 if (boost == NULL)
7310 return;
7311
eed29a5b
DV		 7312 i915_gem_request_reference(req);
7313 boost->req = req;
6ad790c0
CW		 7314
7315 INIT_WORK(&boost->work, __intel_rps_boost_work);
7316 queue_work(to_i915(dev)->wq, &boost->work);
7317}
7318
f742a552 7319void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7320{
7321 struct drm_i915_private *dev_priv = dev->dev_private;
7322
f742a552 7323 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7324 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7325
907b28c5
CW		 7326 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7327 intel_gen6_powersave_work);
1854d5ca 7328 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7329 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7330 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7331
33688d95 7332 dev_priv->pm.suspended = false;
1f814dac 7333 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7334 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7335}
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