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drm/i915: Fix cmdparser STORE/LOAD command descriptors
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
6381b550
NH		 62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
77719d28 66}
91e41d16 67
45db2194 68static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 69{
acd5c346 70 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 71
77719d28
DL		 72 gen9_init_clock_gating(dev);
73
669506e7 74 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 75 /*
76 * WaDisableSDEUnitClockGating:skl
9253c2e5 77 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 78 */
79 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 80 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 81 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 82
83 /* WaDisableVFUnitClockGating:skl */
84 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
85 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 86 }
8bc0ccf6 87
2caa3b26 88 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 89 /* WaDisableHDCInvalidation:skl */
90 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
91 BDW_DISABLE_HDC_INVALIDATION);
92
2caa3b26
DL		 93 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
94 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 95 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 96 }
81e231af 97
a4106a78
AS		 98 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
99 * involving this register should also be added to WA batch as required.
100 */
8bc0ccf6
DL		 101 if (INTEL_REVID(dev) <= SKL_REVID_E0)
102 /* WaDisableLSQCROPERFforOCL:skl */
103 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
104 GEN8_LQSC_RO_PERF_DIS);
245d9667
AS		 105
106 /* WaEnableGapsTsvCreditFix:skl */
107 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
108 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
109 GEN9_GAPS_TSV_CREDIT_DISABLE));
110 }
da2078cd
DL		 111}
112
a82abe43
ID		 113static void bxt_init_clock_gating(struct drm_device *dev)
114{
32608ca2
ID		 115 struct drm_i915_private *dev_priv = dev->dev_private;
116
a82abe43 117 gen9_init_clock_gating(dev);
32608ca2
ID		 118
119 /*
120 * FIXME:
121 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 122 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID		 123 */
124 /* WaDisableSDEUnitClockGating:bxt */
125 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW		 126 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
127 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 128
e3a29055
RB		 129 /* FIXME: apply on A0 only */
130 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
a82abe43
ID		 131}
132
c921aba8
DV		 133static void i915_pineview_get_mem_freq(struct drm_device *dev)
134{
50227e1c 135 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 136 u32 tmp;
137
138 tmp = I915_READ(CLKCFG);
139
140 switch (tmp & CLKCFG_FSB_MASK) {
141 case CLKCFG_FSB_533:
142 dev_priv->fsb_freq = 533; /* 133*4 */
143 break;
144 case CLKCFG_FSB_800:
145 dev_priv->fsb_freq = 800; /* 200*4 */
146 break;
147 case CLKCFG_FSB_667:
148 dev_priv->fsb_freq = 667; /* 167*4 */
149 break;
150 case CLKCFG_FSB_400:
151 dev_priv->fsb_freq = 400; /* 100*4 */
152 break;
153 }
154
155 switch (tmp & CLKCFG_MEM_MASK) {
156 case CLKCFG_MEM_533:
157 dev_priv->mem_freq = 533;
158 break;
159 case CLKCFG_MEM_667:
160 dev_priv->mem_freq = 667;
161 break;
162 case CLKCFG_MEM_800:
163 dev_priv->mem_freq = 800;
164 break;
165 }
166
167 /* detect pineview DDR3 setting */
168 tmp = I915_READ(CSHRDDR3CTL);
169 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
170}
171
172static void i915_ironlake_get_mem_freq(struct drm_device *dev)
173{
50227e1c 174 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 175 u16 ddrpll, csipll;
176
177 ddrpll = I915_READ16(DDRMPLL1);
178 csipll = I915_READ16(CSIPLL0);
179
180 switch (ddrpll & 0xff) {
181 case 0xc:
182 dev_priv->mem_freq = 800;
183 break;
184 case 0x10:
185 dev_priv->mem_freq = 1066;
186 break;
187 case 0x14:
188 dev_priv->mem_freq = 1333;
189 break;
190 case 0x18:
191 dev_priv->mem_freq = 1600;
192 break;
193 default:
194 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
195 ddrpll & 0xff);
196 dev_priv->mem_freq = 0;
197 break;
198 }
199
20e4d407 200 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 201
202 switch (csipll & 0x3ff) {
203 case 0x00c:
204 dev_priv->fsb_freq = 3200;
205 break;
206 case 0x00e:
207 dev_priv->fsb_freq = 3733;
208 break;
209 case 0x010:
210 dev_priv->fsb_freq = 4266;
211 break;
212 case 0x012:
213 dev_priv->fsb_freq = 4800;
214 break;
215 case 0x014:
216 dev_priv->fsb_freq = 5333;
217 break;
218 case 0x016:
219 dev_priv->fsb_freq = 5866;
220 break;
221 case 0x018:
222 dev_priv->fsb_freq = 6400;
223 break;
224 default:
225 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
226 csipll & 0x3ff);
227 dev_priv->fsb_freq = 0;
228 break;
229 }
230
231 if (dev_priv->fsb_freq == 3200) {
20e4d407 232 dev_priv->ips.c_m = 0;
c921aba8 233 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 234 dev_priv->ips.c_m = 1;
c921aba8 235 } else {
20e4d407 236 dev_priv->ips.c_m = 2;
c921aba8
DV		 237 }
238}
239
b445e3b0
ED		 240static const struct cxsr_latency cxsr_latency_table[] = {
241 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
242 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
243 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
244 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
245 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
246
247 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
248 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
249 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
250 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
251 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
252
253 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
254 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
255 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
256 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
257 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
258
259 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
260 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
261 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
262 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
263 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
264
265 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
266 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
267 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
268 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
269 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
270
271 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
272 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
273 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
274 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
275 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
276};
277
63c62275 278static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 279 int is_ddr3,
280 int fsb,
281 int mem)
282{
283 const struct cxsr_latency *latency;
284 int i;
285
286 if (fsb == 0 || mem == 0)
287 return NULL;
288
289 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
290 latency = &cxsr_latency_table[i];
291 if (is_desktop == latency->is_desktop &&
292 is_ddr3 == latency->is_ddr3 &&
293 fsb == latency->fsb_freq && mem == latency->mem_freq)
294 return latency;
295 }
296
297 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
298
299 return NULL;
300}
301
fc1ac8de
VS		 302static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
303{
304 u32 val;
305
306 mutex_lock(&dev_priv->rps.hw_lock);
307
308 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
309 if (enable)
310 val &= ~FORCE_DDR_HIGH_FREQ;
311 else
312 val |= FORCE_DDR_HIGH_FREQ;
313 val &= ~FORCE_DDR_LOW_FREQ;
314 val |= FORCE_DDR_FREQ_REQ_ACK;
315 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
316
317 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
318 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
319 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
320
321 mutex_unlock(&dev_priv->rps.hw_lock);
322}
323
cfb41411
VS		 324static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
325{
326 u32 val;
327
328 mutex_lock(&dev_priv->rps.hw_lock);
329
330 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
331 if (enable)
332 val |= DSP_MAXFIFO_PM5_ENABLE;
333 else
334 val &= ~DSP_MAXFIFO_PM5_ENABLE;
335 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
336
337 mutex_unlock(&dev_priv->rps.hw_lock);
338}
339
f4998963
VS		 340#define FW_WM(value, plane) \
341 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
342
5209b1f4 343void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 344{
5209b1f4
ID		 345 struct drm_device *dev = dev_priv->dev;
346 u32 val;
b445e3b0 347
5209b1f4
ID		 348 if (IS_VALLEYVIEW(dev)) {
349 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 350 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 351 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 352 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
353 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 354 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 355 } else if (IS_PINEVIEW(dev)) {
356 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
357 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
358 I915_WRITE(DSPFW3, val);
a7a6c498 359 POSTING_READ(DSPFW3);
5209b1f4
ID		 360 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
361 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
362 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
363 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 364 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 365 } else if (IS_I915GM(dev)) {
366 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
367 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
368 I915_WRITE(INSTPM, val);
a7a6c498 369 POSTING_READ(INSTPM);
5209b1f4
ID		 370 } else {
371 return;
372 }
b445e3b0 373
5209b1f4
ID		 374 DRM_DEBUG_KMS("memory self-refresh is %s\n",
375 enable ? "enabled" : "disabled");
b445e3b0
ED		 376}
377
fc1ac8de 378
b445e3b0
ED		 379/*
380 * Latency for FIFO fetches is dependent on several factors:
381 * - memory configuration (speed, channels)
382 * - chipset
383 * - current MCH state
384 * It can be fairly high in some situations, so here we assume a fairly
385 * pessimal value. It's a tradeoff between extra memory fetches (if we
386 * set this value too high, the FIFO will fetch frequently to stay full)
387 * and power consumption (set it too low to save power and we might see
388 * FIFO underruns and display "flicker").
389 *
390 * A value of 5us seems to be a good balance; safe for very low end
391 * platforms but not overly aggressive on lower latency configs.
392 */
5aef6003 393static const int pessimal_latency_ns = 5000;
b445e3b0 394
b5004720
VS		 395#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
396 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
397
398static int vlv_get_fifo_size(struct drm_device *dev,
399 enum pipe pipe, int plane)
400{
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 int sprite0_start, sprite1_start, size;
403
404 switch (pipe) {
405 uint32_t dsparb, dsparb2, dsparb3;
406 case PIPE_A:
407 dsparb = I915_READ(DSPARB);
408 dsparb2 = I915_READ(DSPARB2);
409 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
410 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
411 break;
412 case PIPE_B:
413 dsparb = I915_READ(DSPARB);
414 dsparb2 = I915_READ(DSPARB2);
415 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
416 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
417 break;
418 case PIPE_C:
419 dsparb2 = I915_READ(DSPARB2);
420 dsparb3 = I915_READ(DSPARB3);
421 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
422 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
423 break;
424 default:
425 return 0;
426 }
427
428 switch (plane) {
429 case 0:
430 size = sprite0_start;
431 break;
432 case 1:
433 size = sprite1_start - sprite0_start;
434 break;
435 case 2:
436 size = 512 - 1 - sprite1_start;
437 break;
438 default:
439 return 0;
440 }
441
442 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
443 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
444 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
445 size);
446
447 return size;
448}
449
1fa61106 450static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 451{
452 struct drm_i915_private *dev_priv = dev->dev_private;
453 uint32_t dsparb = I915_READ(DSPARB);
454 int size;
455
456 size = dsparb & 0x7f;
457 if (plane)
458 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
459
460 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
461 plane ? "B" : "A", size);
462
463 return size;
464}
465
feb56b93 466static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469 uint32_t dsparb = I915_READ(DSPARB);
470 int size;
471
472 size = dsparb & 0x1ff;
473 if (plane)
474 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
475 size >>= 1; /* Convert to cachelines */
476
477 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
478 plane ? "B" : "A", size);
479
480 return size;
481}
482
1fa61106 483static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 484{
485 struct drm_i915_private *dev_priv = dev->dev_private;
486 uint32_t dsparb = I915_READ(DSPARB);
487 int size;
488
489 size = dsparb & 0x7f;
490 size >>= 2; /* Convert to cachelines */
491
492 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
493 plane ? "B" : "A",
494 size);
495
496 return size;
497}
498
b445e3b0
ED		 499/* Pineview has different values for various configs */
500static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 501 .fifo_size = PINEVIEW_DISPLAY_FIFO,
502 .max_wm = PINEVIEW_MAX_WM,
503 .default_wm = PINEVIEW_DFT_WM,
504 .guard_size = PINEVIEW_GUARD_WM,
505 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 506};
507static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 508 .fifo_size = PINEVIEW_DISPLAY_FIFO,
509 .max_wm = PINEVIEW_MAX_WM,
510 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
511 .guard_size = PINEVIEW_GUARD_WM,
512 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 513};
514static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 515 .fifo_size = PINEVIEW_CURSOR_FIFO,
516 .max_wm = PINEVIEW_CURSOR_MAX_WM,
517 .default_wm = PINEVIEW_CURSOR_DFT_WM,
518 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
519 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 520};
521static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 522 .fifo_size = PINEVIEW_CURSOR_FIFO,
523 .max_wm = PINEVIEW_CURSOR_MAX_WM,
524 .default_wm = PINEVIEW_CURSOR_DFT_WM,
525 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
526 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 527};
528static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 529 .fifo_size = G4X_FIFO_SIZE,
530 .max_wm = G4X_MAX_WM,
531 .default_wm = G4X_MAX_WM,
532 .guard_size = 2,
533 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 534};
535static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 536 .fifo_size = I965_CURSOR_FIFO,
537 .max_wm = I965_CURSOR_MAX_WM,
538 .default_wm = I965_CURSOR_DFT_WM,
539 .guard_size = 2,
540 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 541};
542static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 543 .fifo_size = VALLEYVIEW_FIFO_SIZE,
544 .max_wm = VALLEYVIEW_MAX_WM,
545 .default_wm = VALLEYVIEW_MAX_WM,
546 .guard_size = 2,
547 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 548};
549static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 550 .fifo_size = I965_CURSOR_FIFO,
551 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
552 .default_wm = I965_CURSOR_DFT_WM,
553 .guard_size = 2,
554 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 555};
556static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 557 .fifo_size = I965_CURSOR_FIFO,
558 .max_wm = I965_CURSOR_MAX_WM,
559 .default_wm = I965_CURSOR_DFT_WM,
560 .guard_size = 2,
561 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 562};
563static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 564 .fifo_size = I945_FIFO_SIZE,
565 .max_wm = I915_MAX_WM,
566 .default_wm = 1,
567 .guard_size = 2,
568 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 569};
570static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 571 .fifo_size = I915_FIFO_SIZE,
572 .max_wm = I915_MAX_WM,
573 .default_wm = 1,
574 .guard_size = 2,
575 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 576};
9d539105 577static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 578 .fifo_size = I855GM_FIFO_SIZE,
579 .max_wm = I915_MAX_WM,
580 .default_wm = 1,
581 .guard_size = 2,
582 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 583};
9d539105
VS		 584static const struct intel_watermark_params i830_bc_wm_info = {
585 .fifo_size = I855GM_FIFO_SIZE,
586 .max_wm = I915_MAX_WM/2,
587 .default_wm = 1,
588 .guard_size = 2,
589 .cacheline_size = I830_FIFO_LINE_SIZE,
590};
feb56b93 591static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 592 .fifo_size = I830_FIFO_SIZE,
593 .max_wm = I915_MAX_WM,
594 .default_wm = 1,
595 .guard_size = 2,
596 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 597};
598
b445e3b0
ED		 599/**
600 * intel_calculate_wm - calculate watermark level
601 * @clock_in_khz: pixel clock
602 * @wm: chip FIFO params
603 * @pixel_size: display pixel size
604 * @latency_ns: memory latency for the platform
605 *
606 * Calculate the watermark level (the level at which the display plane will
607 * start fetching from memory again). Each chip has a different display
608 * FIFO size and allocation, so the caller needs to figure that out and pass
609 * in the correct intel_watermark_params structure.
610 *
611 * As the pixel clock runs, the FIFO will be drained at a rate that depends
612 * on the pixel size. When it reaches the watermark level, it'll start
613 * fetching FIFO line sized based chunks from memory until the FIFO fills
614 * past the watermark point. If the FIFO drains completely, a FIFO underrun
615 * will occur, and a display engine hang could result.
616 */
617static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
618 const struct intel_watermark_params *wm,
619 int fifo_size,
620 int pixel_size,
621 unsigned long latency_ns)
622{
623 long entries_required, wm_size;
624
625 /*
626 * Note: we need to make sure we don't overflow for various clock &
627 * latency values.
628 * clocks go from a few thousand to several hundred thousand.
629 * latency is usually a few thousand
630 */
631 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
632 1000;
633 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
634
635 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
636
637 wm_size = fifo_size - (entries_required + wm->guard_size);
638
639 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
640
641 /* Don't promote wm_size to unsigned... */
642 if (wm_size > (long)wm->max_wm)
643 wm_size = wm->max_wm;
644 if (wm_size <= 0)
645 wm_size = wm->default_wm;
d6feb196
VS		 646
647 /*
648 * Bspec seems to indicate that the value shouldn't be lower than
649 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
650 * Lets go for 8 which is the burst size since certain platforms
651 * already use a hardcoded 8 (which is what the spec says should be
652 * done).
653 */
654 if (wm_size <= 8)
655 wm_size = 8;
656
b445e3b0
ED		 657 return wm_size;
658}
659
660static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
661{
662 struct drm_crtc *crtc, *enabled = NULL;
663
70e1e0ec 664 for_each_crtc(dev, crtc) {
3490ea5d 665 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 666 if (enabled)
667 return NULL;
668 enabled = crtc;
669 }
670 }
671
672 return enabled;
673}
674
46ba614c 675static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 676{
46ba614c 677 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 678 struct drm_i915_private *dev_priv = dev->dev_private;
679 struct drm_crtc *crtc;
680 const struct cxsr_latency *latency;
681 u32 reg;
682 unsigned long wm;
683
684 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
685 dev_priv->fsb_freq, dev_priv->mem_freq);
686 if (!latency) {
687 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 688 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 689 return;
690 }
691
692 crtc = single_enabled_crtc(dev);
693 if (crtc) {
241bfc38 694 const struct drm_display_mode *adjusted_mode;
59bea882 695 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 696 int clock;
697
6e3c9717 698 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 699 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 700
701 /* Display SR */
702 wm = intel_calculate_wm(clock, &pineview_display_wm,
703 pineview_display_wm.fifo_size,
704 pixel_size, latency->display_sr);
705 reg = I915_READ(DSPFW1);
706 reg &= ~DSPFW_SR_MASK;
f4998963 707 reg |= FW_WM(wm, SR);
b445e3b0
ED		 708 I915_WRITE(DSPFW1, reg);
709 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
710
711 /* cursor SR */
712 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
713 pineview_display_wm.fifo_size,
714 pixel_size, latency->cursor_sr);
715 reg = I915_READ(DSPFW3);
716 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 717 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 718 I915_WRITE(DSPFW3, reg);
719
720 /* Display HPLL off SR */
721 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
722 pineview_display_hplloff_wm.fifo_size,
723 pixel_size, latency->display_hpll_disable);
724 reg = I915_READ(DSPFW3);
725 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 726 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 727 I915_WRITE(DSPFW3, reg);
728
729 /* cursor HPLL off SR */
730 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
731 pineview_display_hplloff_wm.fifo_size,
732 pixel_size, latency->cursor_hpll_disable);
733 reg = I915_READ(DSPFW3);
734 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 735 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 736 I915_WRITE(DSPFW3, reg);
737 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
738
5209b1f4 739 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 740 } else {
5209b1f4 741 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 742 }
743}
744
745static bool g4x_compute_wm0(struct drm_device *dev,
746 int plane,
747 const struct intel_watermark_params *display,
748 int display_latency_ns,
749 const struct intel_watermark_params *cursor,
750 int cursor_latency_ns,
751 int *plane_wm,
752 int *cursor_wm)
753{
754 struct drm_crtc *crtc;
4fe8590a 755 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 756 int htotal, hdisplay, clock, pixel_size;
757 int line_time_us, line_count;
758 int entries, tlb_miss;
759
760 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 761 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 762 *cursor_wm = cursor->guard_size;
763 *plane_wm = display->guard_size;
764 return false;
765 }
766
6e3c9717 767 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 768 clock = adjusted_mode->crtc_clock;
fec8cba3 769 htotal = adjusted_mode->crtc_htotal;
6e3c9717 770 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 771 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 772
773 /* Use the small buffer method to calculate plane watermark */
774 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
775 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
776 if (tlb_miss > 0)
777 entries += tlb_miss;
778 entries = DIV_ROUND_UP(entries, display->cacheline_size);
779 *plane_wm = entries + display->guard_size;
780 if (*plane_wm > (int)display->max_wm)
781 *plane_wm = display->max_wm;
782
783 /* Use the large buffer method to calculate cursor watermark */
922044c9 784 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 785 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 786 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 787 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
788 if (tlb_miss > 0)
789 entries += tlb_miss;
790 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
791 *cursor_wm = entries + cursor->guard_size;
792 if (*cursor_wm > (int)cursor->max_wm)
793 *cursor_wm = (int)cursor->max_wm;
794
795 return true;
796}
797
798/*
799 * Check the wm result.
800 *
801 * If any calculated watermark values is larger than the maximum value that
802 * can be programmed into the associated watermark register, that watermark
803 * must be disabled.
804 */
805static bool g4x_check_srwm(struct drm_device *dev,
806 int display_wm, int cursor_wm,
807 const struct intel_watermark_params *display,
808 const struct intel_watermark_params *cursor)
809{
810 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
811 display_wm, cursor_wm);
812
813 if (display_wm > display->max_wm) {
814 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
815 display_wm, display->max_wm);
816 return false;
817 }
818
819 if (cursor_wm > cursor->max_wm) {
820 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
821 cursor_wm, cursor->max_wm);
822 return false;
823 }
824
825 if (!(display_wm || cursor_wm)) {
826 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
827 return false;
828 }
829
830 return true;
831}
832
833static bool g4x_compute_srwm(struct drm_device *dev,
834 int plane,
835 int latency_ns,
836 const struct intel_watermark_params *display,
837 const struct intel_watermark_params *cursor,
838 int *display_wm, int *cursor_wm)
839{
840 struct drm_crtc *crtc;
4fe8590a 841 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 842 int hdisplay, htotal, pixel_size, clock;
843 unsigned long line_time_us;
844 int line_count, line_size;
845 int small, large;
846 int entries;
847
848 if (!latency_ns) {
849 *display_wm = *cursor_wm = 0;
850 return false;
851 }
852
853 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 854 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 855 clock = adjusted_mode->crtc_clock;
fec8cba3 856 htotal = adjusted_mode->crtc_htotal;
6e3c9717 857 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 858 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 859
922044c9 860 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 861 line_count = (latency_ns / line_time_us + 1000) / 1000;
862 line_size = hdisplay * pixel_size;
863
864 /* Use the minimum of the small and large buffer method for primary */
865 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
866 large = line_count * line_size;
867
868 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
869 *display_wm = entries + display->guard_size;
870
871 /* calculate the self-refresh watermark for display cursor */
3dd512fb 872 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 873 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
874 *cursor_wm = entries + cursor->guard_size;
875
876 return g4x_check_srwm(dev,
877 *display_wm, *cursor_wm,
878 display, cursor);
879}
880
15665979
VS		 881#define FW_WM_VLV(value, plane) \
882 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
883
0018fda1
VS		 884static void vlv_write_wm_values(struct intel_crtc *crtc,
885 const struct vlv_wm_values *wm)
886{
887 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
888 enum pipe pipe = crtc->pipe;
889
890 I915_WRITE(VLV_DDL(pipe),
891 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
892 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
893 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
894 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
895
ae80152d 896 I915_WRITE(DSPFW1,
15665979
VS		 897 FW_WM(wm->sr.plane, SR) |
898 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
899 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
900 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 901 I915_WRITE(DSPFW2,
15665979
VS		 902 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
903 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
904 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 905 I915_WRITE(DSPFW3,
15665979 906 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 907
908 if (IS_CHERRYVIEW(dev_priv)) {
909 I915_WRITE(DSPFW7_CHV,
15665979
VS		 910 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
911 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 912 I915_WRITE(DSPFW8_CHV,
15665979
VS		 913 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
914 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 915 I915_WRITE(DSPFW9_CHV,
15665979
VS		 916 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
917 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 918 I915_WRITE(DSPHOWM,
15665979
VS		 919 FW_WM(wm->sr.plane >> 9, SR_HI) |
920 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
921 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
922 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
923 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
924 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
925 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
926 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
927 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
928 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 929 } else {
930 I915_WRITE(DSPFW7,
15665979
VS		 931 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
932 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 933 I915_WRITE(DSPHOWM,
15665979
VS		 934 FW_WM(wm->sr.plane >> 9, SR_HI) |
935 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
936 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
937 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
938 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
939 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
940 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 941 }
942
2cb389b7
VS		 943 /* zero (unused) WM1 watermarks */
944 I915_WRITE(DSPFW4, 0);
945 I915_WRITE(DSPFW5, 0);
946 I915_WRITE(DSPFW6, 0);
947 I915_WRITE(DSPHOWM1, 0);
948
ae80152d 949 POSTING_READ(DSPFW1);
0018fda1
VS		 950}
951
15665979
VS		 952#undef FW_WM_VLV
953
6eb1a681
VS		 954enum vlv_wm_level {
955 VLV_WM_LEVEL_PM2,
956 VLV_WM_LEVEL_PM5,
957 VLV_WM_LEVEL_DDR_DVFS,
958 CHV_WM_NUM_LEVELS,
959 VLV_WM_NUM_LEVELS = 1,
960};
961
262cd2e1
VS		 962/* latency must be in 0.1us units. */
963static unsigned int vlv_wm_method2(unsigned int pixel_rate,
964 unsigned int pipe_htotal,
965 unsigned int horiz_pixels,
966 unsigned int bytes_per_pixel,
967 unsigned int latency)
968{
969 unsigned int ret;
970
971 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
972 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
973 ret = DIV_ROUND_UP(ret, 64);
974
975 return ret;
976}
977
978static void vlv_setup_wm_latency(struct drm_device *dev)
979{
980 struct drm_i915_private *dev_priv = dev->dev_private;
981
982 /* all latencies in usec */
983 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
984
985 if (IS_CHERRYVIEW(dev_priv)) {
986 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
987 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
988 }
989}
990
991static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
992 struct intel_crtc *crtc,
993 const struct intel_plane_state *state,
994 int level)
995{
996 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
997 int clock, htotal, pixel_size, width, wm;
998
999 if (dev_priv->wm.pri_latency[level] == 0)
1000 return USHRT_MAX;
1001
1002 if (!state->visible)
1003 return 0;
1004
1005 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1006 clock = crtc->config->base.adjusted_mode.crtc_clock;
1007 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1008 width = crtc->config->pipe_src_w;
1009 if (WARN_ON(htotal == 0))
1010 htotal = 1;
1011
1012 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1013 /*
1014 * FIXME the formula gives values that are
1015 * too big for the cursor FIFO, and hence we
1016 * would never be able to use cursors. For
1017 * now just hardcode the watermark.
1018 */
1019 wm = 63;
1020 } else {
1021 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1022 dev_priv->wm.pri_latency[level] * 10);
1023 }
1024
1025 return min_t(int, wm, USHRT_MAX);
1026}
1027
54f1b6e1
VS		 1028static void vlv_compute_fifo(struct intel_crtc *crtc)
1029{
1030 struct drm_device *dev = crtc->base.dev;
1031 struct vlv_wm_state *wm_state = &crtc->wm_state;
1032 struct intel_plane *plane;
1033 unsigned int total_rate = 0;
1034 const int fifo_size = 512 - 1;
1035 int fifo_extra, fifo_left = fifo_size;
1036
1037 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1038 struct intel_plane_state *state =
1039 to_intel_plane_state(plane->base.state);
1040
1041 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1042 continue;
1043
1044 if (state->visible) {
1045 wm_state->num_active_planes++;
1046 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1047 }
1048 }
1049
1050 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1051 struct intel_plane_state *state =
1052 to_intel_plane_state(plane->base.state);
1053 unsigned int rate;
1054
1055 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1056 plane->wm.fifo_size = 63;
1057 continue;
1058 }
1059
1060 if (!state->visible) {
1061 plane->wm.fifo_size = 0;
1062 continue;
1063 }
1064
1065 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1066 plane->wm.fifo_size = fifo_size * rate / total_rate;
1067 fifo_left -= plane->wm.fifo_size;
1068 }
1069
1070 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1071
1072 /* spread the remainder evenly */
1073 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1074 int plane_extra;
1075
1076 if (fifo_left == 0)
1077 break;
1078
1079 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1080 continue;
1081
1082 /* give it all to the first plane if none are active */
1083 if (plane->wm.fifo_size == 0 &&
1084 wm_state->num_active_planes)
1085 continue;
1086
1087 plane_extra = min(fifo_extra, fifo_left);
1088 plane->wm.fifo_size += plane_extra;
1089 fifo_left -= plane_extra;
1090 }
1091
1092 WARN_ON(fifo_left != 0);
1093}
1094
262cd2e1
VS		 1095static void vlv_invert_wms(struct intel_crtc *crtc)
1096{
1097 struct vlv_wm_state *wm_state = &crtc->wm_state;
1098 int level;
1099
1100 for (level = 0; level < wm_state->num_levels; level++) {
1101 struct drm_device *dev = crtc->base.dev;
1102 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1103 struct intel_plane *plane;
1104
1105 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1106 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1107
1108 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1109 switch (plane->base.type) {
1110 int sprite;
1111 case DRM_PLANE_TYPE_CURSOR:
1112 wm_state->wm[level].cursor = plane->wm.fifo_size -
1113 wm_state->wm[level].cursor;
1114 break;
1115 case DRM_PLANE_TYPE_PRIMARY:
1116 wm_state->wm[level].primary = plane->wm.fifo_size -
1117 wm_state->wm[level].primary;
1118 break;
1119 case DRM_PLANE_TYPE_OVERLAY:
1120 sprite = plane->plane;
1121 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1122 wm_state->wm[level].sprite[sprite];
1123 break;
1124 }
1125 }
1126 }
1127}
1128
26e1fe4f 1129static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1130{
1131 struct drm_device *dev = crtc->base.dev;
1132 struct vlv_wm_state *wm_state = &crtc->wm_state;
1133 struct intel_plane *plane;
1134 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1135 int level;
1136
1137 memset(wm_state, 0, sizeof(*wm_state));
1138
852eb00d 1139 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
262cd2e1
VS		 1140 if (IS_CHERRYVIEW(dev))
1141 wm_state->num_levels = CHV_WM_NUM_LEVELS;
1142 else
1143 wm_state->num_levels = VLV_WM_NUM_LEVELS;
1144
1145 wm_state->num_active_planes = 0;
262cd2e1 1146
54f1b6e1 1147 vlv_compute_fifo(crtc);
262cd2e1
VS		 1148
1149 if (wm_state->num_active_planes != 1)
1150 wm_state->cxsr = false;
1151
1152 if (wm_state->cxsr) {
1153 for (level = 0; level < wm_state->num_levels; level++) {
1154 wm_state->sr[level].plane = sr_fifo_size;
1155 wm_state->sr[level].cursor = 63;
1156 }
1157 }
1158
1159 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1160 struct intel_plane_state *state =
1161 to_intel_plane_state(plane->base.state);
1162
1163 if (!state->visible)
1164 continue;
1165
1166 /* normal watermarks */
1167 for (level = 0; level < wm_state->num_levels; level++) {
1168 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1169 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1170
1171 /* hack */
1172 if (WARN_ON(level == 0 && wm > max_wm))
1173 wm = max_wm;
1174
1175 if (wm > plane->wm.fifo_size)
1176 break;
1177
1178 switch (plane->base.type) {
1179 int sprite;
1180 case DRM_PLANE_TYPE_CURSOR:
1181 wm_state->wm[level].cursor = wm;
1182 break;
1183 case DRM_PLANE_TYPE_PRIMARY:
1184 wm_state->wm[level].primary = wm;
1185 break;
1186 case DRM_PLANE_TYPE_OVERLAY:
1187 sprite = plane->plane;
1188 wm_state->wm[level].sprite[sprite] = wm;
1189 break;
1190 }
1191 }
1192
1193 wm_state->num_levels = level;
1194
1195 if (!wm_state->cxsr)
1196 continue;
1197
1198 /* maxfifo watermarks */
1199 switch (plane->base.type) {
1200 int sprite, level;
1201 case DRM_PLANE_TYPE_CURSOR:
1202 for (level = 0; level < wm_state->num_levels; level++)
1203 wm_state->sr[level].cursor =
1204 wm_state->sr[level].cursor;
1205 break;
1206 case DRM_PLANE_TYPE_PRIMARY:
1207 for (level = 0; level < wm_state->num_levels; level++)
1208 wm_state->sr[level].plane =
1209 min(wm_state->sr[level].plane,
1210 wm_state->wm[level].primary);
1211 break;
1212 case DRM_PLANE_TYPE_OVERLAY:
1213 sprite = plane->plane;
1214 for (level = 0; level < wm_state->num_levels; level++)
1215 wm_state->sr[level].plane =
1216 min(wm_state->sr[level].plane,
1217 wm_state->wm[level].sprite[sprite]);
1218 break;
1219 }
1220 }
1221
1222 /* clear any (partially) filled invalid levels */
1223 for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
1224 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1225 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1226 }
1227
1228 vlv_invert_wms(crtc);
1229}
1230
54f1b6e1
VS		 1231#define VLV_FIFO(plane, value) \
1232 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1233
1234static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1235{
1236 struct drm_device *dev = crtc->base.dev;
1237 struct drm_i915_private *dev_priv = to_i915(dev);
1238 struct intel_plane *plane;
1239 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1240
1241 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1242 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1243 WARN_ON(plane->wm.fifo_size != 63);
1244 continue;
1245 }
1246
1247 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1248 sprite0_start = plane->wm.fifo_size;
1249 else if (plane->plane == 0)
1250 sprite1_start = sprite0_start + plane->wm.fifo_size;
1251 else
1252 fifo_size = sprite1_start + plane->wm.fifo_size;
1253 }
1254
1255 WARN_ON(fifo_size != 512 - 1);
1256
1257 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1258 pipe_name(crtc->pipe), sprite0_start,
1259 sprite1_start, fifo_size);
1260
1261 switch (crtc->pipe) {
1262 uint32_t dsparb, dsparb2, dsparb3;
1263 case PIPE_A:
1264 dsparb = I915_READ(DSPARB);
1265 dsparb2 = I915_READ(DSPARB2);
1266
1267 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1268 VLV_FIFO(SPRITEB, 0xff));
1269 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1270 VLV_FIFO(SPRITEB, sprite1_start));
1271
1272 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1273 VLV_FIFO(SPRITEB_HI, 0x1));
1274 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1275 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1276
1277 I915_WRITE(DSPARB, dsparb);
1278 I915_WRITE(DSPARB2, dsparb2);
1279 break;
1280 case PIPE_B:
1281 dsparb = I915_READ(DSPARB);
1282 dsparb2 = I915_READ(DSPARB2);
1283
1284 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1285 VLV_FIFO(SPRITED, 0xff));
1286 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1287 VLV_FIFO(SPRITED, sprite1_start));
1288
1289 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1290 VLV_FIFO(SPRITED_HI, 0xff));
1291 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1292 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1293
1294 I915_WRITE(DSPARB, dsparb);
1295 I915_WRITE(DSPARB2, dsparb2);
1296 break;
1297 case PIPE_C:
1298 dsparb3 = I915_READ(DSPARB3);
1299 dsparb2 = I915_READ(DSPARB2);
1300
1301 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1302 VLV_FIFO(SPRITEF, 0xff));
1303 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1304 VLV_FIFO(SPRITEF, sprite1_start));
1305
1306 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1307 VLV_FIFO(SPRITEF_HI, 0xff));
1308 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1309 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1310
1311 I915_WRITE(DSPARB3, dsparb3);
1312 I915_WRITE(DSPARB2, dsparb2);
1313 break;
1314 default:
1315 break;
1316 }
1317}
1318
1319#undef VLV_FIFO
1320
262cd2e1
VS		 1321static void vlv_merge_wm(struct drm_device *dev,
1322 struct vlv_wm_values *wm)
1323{
1324 struct intel_crtc *crtc;
1325 int num_active_crtcs = 0;
1326
1327 if (IS_CHERRYVIEW(dev))
1328 wm->level = VLV_WM_LEVEL_DDR_DVFS;
1329 else
1330 wm->level = VLV_WM_LEVEL_PM2;
1331 wm->cxsr = true;
1332
1333 for_each_intel_crtc(dev, crtc) {
1334 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1335
1336 if (!crtc->active)
1337 continue;
1338
1339 if (!wm_state->cxsr)
1340 wm->cxsr = false;
1341
1342 num_active_crtcs++;
1343 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1344 }
1345
1346 if (num_active_crtcs != 1)
1347 wm->cxsr = false;
1348
6f9c784b
VS		 1349 if (num_active_crtcs > 1)
1350 wm->level = VLV_WM_LEVEL_PM2;
1351
262cd2e1
VS		 1352 for_each_intel_crtc(dev, crtc) {
1353 struct vlv_wm_state *wm_state = &crtc->wm_state;
1354 enum pipe pipe = crtc->pipe;
1355
1356 if (!crtc->active)
1357 continue;
1358
1359 wm->pipe[pipe] = wm_state->wm[wm->level];
1360 if (wm->cxsr)
1361 wm->sr = wm_state->sr[wm->level];
1362
1363 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1364 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1365 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1366 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1367 }
1368}
1369
1370static void vlv_update_wm(struct drm_crtc *crtc)
1371{
1372 struct drm_device *dev = crtc->dev;
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1375 enum pipe pipe = intel_crtc->pipe;
1376 struct vlv_wm_values wm = {};
1377
26e1fe4f 1378 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1379 vlv_merge_wm(dev, &wm);
1380
54f1b6e1
VS		 1381 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1382 /* FIXME should be part of crtc atomic commit */
1383 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1384 return;
54f1b6e1 1385 }
262cd2e1
VS		 1386
1387 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1388 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1389 chv_set_memory_dvfs(dev_priv, false);
1390
1391 if (wm.level < VLV_WM_LEVEL_PM5 &&
1392 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1393 chv_set_memory_pm5(dev_priv, false);
1394
852eb00d 1395 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1396 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1397
54f1b6e1
VS		 1398 /* FIXME should be part of crtc atomic commit */
1399 vlv_pipe_set_fifo_size(intel_crtc);
1400
262cd2e1
VS		 1401 vlv_write_wm_values(intel_crtc, &wm);
1402
1403 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1404 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1405 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1406 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1407 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1408
852eb00d 1409 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1410 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1411
1412 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1413 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1414 chv_set_memory_pm5(dev_priv, true);
1415
1416 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1417 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1418 chv_set_memory_dvfs(dev_priv, true);
1419
1420 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1421}
1422
ae80152d
VS		 1423#define single_plane_enabled(mask) is_power_of_2(mask)
1424
46ba614c 1425static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1426{
46ba614c 1427 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1428 static const int sr_latency_ns = 12000;
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1431 int plane_sr, cursor_sr;
1432 unsigned int enabled = 0;
9858425c 1433 bool cxsr_enabled;
b445e3b0 1434
51cea1f4 1435 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1436 &g4x_wm_info, pessimal_latency_ns,
1437 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1438 &planea_wm, &cursora_wm))
51cea1f4 1439 enabled |= 1 << PIPE_A;
b445e3b0 1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1442 &g4x_wm_info, pessimal_latency_ns,
1443 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1444 &planeb_wm, &cursorb_wm))
51cea1f4 1445 enabled |= 1 << PIPE_B;
b445e3b0 1446
b445e3b0
ED		 1447 if (single_plane_enabled(enabled) &&
1448 g4x_compute_srwm(dev, ffs(enabled) - 1,
1449 sr_latency_ns,
1450 &g4x_wm_info,
1451 &g4x_cursor_wm_info,
52bd02d8 1452 &plane_sr, &cursor_sr)) {
9858425c 1453 cxsr_enabled = true;
52bd02d8 1454 } else {
9858425c 1455 cxsr_enabled = false;
5209b1f4 1456 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1457 plane_sr = cursor_sr = 0;
1458 }
b445e3b0 1459
a5043453
VS		 1460 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1461 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1462 planea_wm, cursora_wm,
1463 planeb_wm, cursorb_wm,
1464 plane_sr, cursor_sr);
1465
1466 I915_WRITE(DSPFW1,
f4998963
VS		 1467 FW_WM(plane_sr, SR) |
1468 FW_WM(cursorb_wm, CURSORB) |
1469 FW_WM(planeb_wm, PLANEB) |
1470 FW_WM(planea_wm, PLANEA));
b445e3b0 1471 I915_WRITE(DSPFW2,
8c919b28 1472 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1473 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1474 /* HPLL off in SR has some issues on G4x... disable it */
1475 I915_WRITE(DSPFW3,
8c919b28 1476 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1477 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1478
1479 if (cxsr_enabled)
1480 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1481}
1482
46ba614c 1483static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1484{
46ba614c 1485 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 struct drm_crtc *crtc;
1488 int srwm = 1;
1489 int cursor_sr = 16;
9858425c 1490 bool cxsr_enabled;
b445e3b0
ED		 1491
1492 /* Calc sr entries for one plane configs */
1493 crtc = single_enabled_crtc(dev);
1494 if (crtc) {
1495 /* self-refresh has much higher latency */
1496 static const int sr_latency_ns = 12000;
4fe8590a 1497 const struct drm_display_mode *adjusted_mode =
6e3c9717 1498 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1499 int clock = adjusted_mode->crtc_clock;
fec8cba3 1500 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1501 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1502 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1503 unsigned long line_time_us;
1504 int entries;
1505
922044c9 1506 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1507
1508 /* Use ns/us then divide to preserve precision */
1509 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510 pixel_size * hdisplay;
1511 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512 srwm = I965_FIFO_SIZE - entries;
1513 if (srwm < 0)
1514 srwm = 1;
1515 srwm &= 0x1ff;
1516 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1517 entries, srwm);
1518
1519 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1520 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1521 entries = DIV_ROUND_UP(entries,
1522 i965_cursor_wm_info.cacheline_size);
1523 cursor_sr = i965_cursor_wm_info.fifo_size -
1524 (entries + i965_cursor_wm_info.guard_size);
1525
1526 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527 cursor_sr = i965_cursor_wm_info.max_wm;
1528
1529 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530 "cursor %d\n", srwm, cursor_sr);
1531
9858425c 1532 cxsr_enabled = true;
b445e3b0 1533 } else {
9858425c 1534 cxsr_enabled = false;
b445e3b0 1535 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1536 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1537 }
1538
1539 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1540 srwm);
1541
1542 /* 965 has limitations... */
f4998963
VS		 1543 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1544 FW_WM(8, CURSORB) |
1545 FW_WM(8, PLANEB) |
1546 FW_WM(8, PLANEA));
1547 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1548 FW_WM(8, PLANEC_OLD));
b445e3b0 1549 /* update cursor SR watermark */
f4998963 1550 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1551
1552 if (cxsr_enabled)
1553 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1554}
1555
f4998963
VS		 1556#undef FW_WM
1557
46ba614c 1558static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1559{
46ba614c 1560 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1561 struct drm_i915_private *dev_priv = dev->dev_private;
1562 const struct intel_watermark_params *wm_info;
1563 uint32_t fwater_lo;
1564 uint32_t fwater_hi;
1565 int cwm, srwm = 1;
1566 int fifo_size;
1567 int planea_wm, planeb_wm;
1568 struct drm_crtc *crtc, *enabled = NULL;
1569
1570 if (IS_I945GM(dev))
1571 wm_info = &i945_wm_info;
1572 else if (!IS_GEN2(dev))
1573 wm_info = &i915_wm_info;
1574 else
9d539105 1575 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1576
1577 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1578 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1579 if (intel_crtc_active(crtc)) {
241bfc38 1580 const struct drm_display_mode *adjusted_mode;
59bea882 1581 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1582 if (IS_GEN2(dev))
1583 cpp = 4;
1584
6e3c9717 1585 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1586 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1587 wm_info, fifo_size, cpp,
5aef6003 1588 pessimal_latency_ns);
b445e3b0 1589 enabled = crtc;
9d539105 1590 } else {
b445e3b0 1591 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1592 if (planea_wm > (long)wm_info->max_wm)
1593 planea_wm = wm_info->max_wm;
1594 }
1595
1596 if (IS_GEN2(dev))
1597 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1598
1599 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1600 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1601 if (intel_crtc_active(crtc)) {
241bfc38 1602 const struct drm_display_mode *adjusted_mode;
59bea882 1603 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1604 if (IS_GEN2(dev))
1605 cpp = 4;
1606
6e3c9717 1607 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1608 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1609 wm_info, fifo_size, cpp,
5aef6003 1610 pessimal_latency_ns);
b445e3b0
ED		 1611 if (enabled == NULL)
1612 enabled = crtc;
1613 else
1614 enabled = NULL;
9d539105 1615 } else {
b445e3b0 1616 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1617 if (planeb_wm > (long)wm_info->max_wm)
1618 planeb_wm = wm_info->max_wm;
1619 }
b445e3b0
ED		 1620
1621 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1622
2ab1bc9d 1623 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1624 struct drm_i915_gem_object *obj;
2ab1bc9d 1625
59bea882 1626 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1627
1628 /* self-refresh seems busted with untiled */
2ff8fde1 1629 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1630 enabled = NULL;
1631 }
1632
b445e3b0
ED		 1633 /*
1634 * Overlay gets an aggressive default since video jitter is bad.
1635 */
1636 cwm = 2;
1637
1638 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1639 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1640
1641 /* Calc sr entries for one plane configs */
1642 if (HAS_FW_BLC(dev) && enabled) {
1643 /* self-refresh has much higher latency */
1644 static const int sr_latency_ns = 6000;
4fe8590a 1645 const struct drm_display_mode *adjusted_mode =
6e3c9717 1646 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1647 int clock = adjusted_mode->crtc_clock;
fec8cba3 1648 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1649 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1650 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1651 unsigned long line_time_us;
1652 int entries;
1653
922044c9 1654 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1655
1656 /* Use ns/us then divide to preserve precision */
1657 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1658 pixel_size * hdisplay;
1659 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1660 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1661 srwm = wm_info->fifo_size - entries;
1662 if (srwm < 0)
1663 srwm = 1;
1664
1665 if (IS_I945G(dev) || IS_I945GM(dev))
1666 I915_WRITE(FW_BLC_SELF,
1667 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1668 else if (IS_I915GM(dev))
1669 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1670 }
1671
1672 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1673 planea_wm, planeb_wm, cwm, srwm);
1674
1675 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1676 fwater_hi = (cwm & 0x1f);
1677
1678 /* Set request length to 8 cachelines per fetch */
1679 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1680 fwater_hi = fwater_hi | (1 << 8);
1681
1682 I915_WRITE(FW_BLC, fwater_lo);
1683 I915_WRITE(FW_BLC2, fwater_hi);
1684
5209b1f4
ID		 1685 if (enabled)
1686 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1687}
1688
feb56b93 1689static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1690{
46ba614c 1691 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 struct drm_crtc *crtc;
241bfc38 1694 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1695 uint32_t fwater_lo;
1696 int planea_wm;
1697
1698 crtc = single_enabled_crtc(dev);
1699 if (crtc == NULL)
1700 return;
1701
6e3c9717 1702 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1703 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1704 &i845_wm_info,
b445e3b0 1705 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1706 4, pessimal_latency_ns);
b445e3b0
ED		 1707 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1708 fwater_lo |= (3<<8) | planea_wm;
1709
1710 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1711
1712 I915_WRITE(FW_BLC, fwater_lo);
1713}
1714
8cfb3407 1715uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1716{
fd4daa9c 1717 uint32_t pixel_rate;
801bcfff 1718
8cfb3407 1719 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1720
1721 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1722 * adjust the pixel_rate here. */
1723
8cfb3407 1724 if (pipe_config->pch_pfit.enabled) {
801bcfff 1725 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1726 uint32_t pfit_size = pipe_config->pch_pfit.size;
1727
1728 pipe_w = pipe_config->pipe_src_w;
1729 pipe_h = pipe_config->pipe_src_h;
801bcfff 1730
801bcfff
PZ		 1731 pfit_w = (pfit_size >> 16) & 0xFFFF;
1732 pfit_h = pfit_size & 0xFFFF;
1733 if (pipe_w < pfit_w)
1734 pipe_w = pfit_w;
1735 if (pipe_h < pfit_h)
1736 pipe_h = pfit_h;
1737
1738 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1739 pfit_w * pfit_h);
1740 }
1741
1742 return pixel_rate;
1743}
1744
37126462 1745/* latency must be in 0.1us units. */
23297044 1746static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1747 uint32_t latency)
1748{
1749 uint64_t ret;
1750
3312ba65
VS		 1751 if (WARN(latency == 0, "Latency value missing\n"))
1752 return UINT_MAX;
1753
801bcfff
PZ		 1754 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1755 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1756
1757 return ret;
1758}
1759
37126462 1760/* latency must be in 0.1us units. */
23297044 1761static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1762 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1763 uint32_t latency)
1764{
1765 uint32_t ret;
1766
3312ba65
VS		 1767 if (WARN(latency == 0, "Latency value missing\n"))
1768 return UINT_MAX;
1769
801bcfff
PZ		 1770 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1771 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1772 ret = DIV_ROUND_UP(ret, 64) + 2;
1773 return ret;
1774}
1775
23297044 1776static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1777 uint8_t bytes_per_pixel)
1778{
1779 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1780}
1781
2ac96d2a
PB		 1782struct skl_pipe_wm_parameters {
1783 bool active;
1784 uint32_t pipe_htotal;
1785 uint32_t pixel_rate; /* in KHz */
1786 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1787 struct intel_plane_wm_parameters cursor;
1788};
1789
820c1980 1790struct ilk_pipe_wm_parameters {
801bcfff 1791 bool active;
801bcfff
PZ		 1792 uint32_t pipe_htotal;
1793 uint32_t pixel_rate;
c35426d2
VS		 1794 struct intel_plane_wm_parameters pri;
1795 struct intel_plane_wm_parameters spr;
1796 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1797};
1798
820c1980 1799struct ilk_wm_maximums {
cca32e9a
PZ		 1800 uint16_t pri;
1801 uint16_t spr;
1802 uint16_t cur;
1803 uint16_t fbc;
1804};
1805
240264f4
VS		 1806/* used in computing the new watermarks state */
1807struct intel_wm_config {
1808 unsigned int num_pipes_active;
1809 bool sprites_enabled;
1810 bool sprites_scaled;
240264f4
VS		 1811};
1812
37126462
VS		 1813/*
1814 * For both WM_PIPE and WM_LP.
1815 * mem_value must be in 0.1us units.
1816 */
820c1980 1817static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1818 uint32_t mem_value,
1819 bool is_lp)
801bcfff 1820{
cca32e9a
PZ		 1821 uint32_t method1, method2;
1822
c35426d2 1823 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1824 return 0;
1825
23297044 1826 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1827 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1828 mem_value);
1829
1830 if (!is_lp)
1831 return method1;
1832
23297044 1833 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1834 params->pipe_htotal,
c35426d2
VS		 1835 params->pri.horiz_pixels,
1836 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1837 mem_value);
1838
1839 return min(method1, method2);
801bcfff
PZ		 1840}
1841
37126462
VS		 1842/*
1843 * For both WM_PIPE and WM_LP.
1844 * mem_value must be in 0.1us units.
1845 */
820c1980 1846static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1847 uint32_t mem_value)
1848{
1849 uint32_t method1, method2;
1850
c35426d2 1851 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1852 return 0;
1853
23297044 1854 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1855 params->spr.bytes_per_pixel,
801bcfff 1856 mem_value);
23297044 1857 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1858 params->pipe_htotal,
c35426d2
VS		 1859 params->spr.horiz_pixels,
1860 params->spr.bytes_per_pixel,
801bcfff
PZ		 1861 mem_value);
1862 return min(method1, method2);
1863}
1864
37126462
VS		 1865/*
1866 * For both WM_PIPE and WM_LP.
1867 * mem_value must be in 0.1us units.
1868 */
820c1980 1869static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1870 uint32_t mem_value)
1871{
c35426d2 1872 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1873 return 0;
1874
23297044 1875 return ilk_wm_method2(params->pixel_rate,
801bcfff 1876 params->pipe_htotal,
c35426d2
VS		 1877 params->cur.horiz_pixels,
1878 params->cur.bytes_per_pixel,
801bcfff
PZ		 1879 mem_value);
1880}
1881
cca32e9a 1882/* Only for WM_LP. */
820c1980 1883static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1884 uint32_t pri_val)
cca32e9a 1885{
c35426d2 1886 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1887 return 0;
1888
23297044 1889 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1890 params->pri.horiz_pixels,
1891 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1892}
1893
158ae64f
VS		 1894static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1895{
416f4727
VS		 1896 if (INTEL_INFO(dev)->gen >= 8)
1897 return 3072;
1898 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1899 return 768;
1900 else
1901 return 512;
1902}
1903
4e975081
VS		 1904static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1905 int level, bool is_sprite)
1906{
1907 if (INTEL_INFO(dev)->gen >= 8)
1908 /* BDW primary/sprite plane watermarks */
1909 return level == 0 ? 255 : 2047;
1910 else if (INTEL_INFO(dev)->gen >= 7)
1911 /* IVB/HSW primary/sprite plane watermarks */
1912 return level == 0 ? 127 : 1023;
1913 else if (!is_sprite)
1914 /* ILK/SNB primary plane watermarks */
1915 return level == 0 ? 127 : 511;
1916 else
1917 /* ILK/SNB sprite plane watermarks */
1918 return level == 0 ? 63 : 255;
1919}
1920
1921static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1922 int level)
1923{
1924 if (INTEL_INFO(dev)->gen >= 7)
1925 return level == 0 ? 63 : 255;
1926 else
1927 return level == 0 ? 31 : 63;
1928}
1929
1930static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1931{
1932 if (INTEL_INFO(dev)->gen >= 8)
1933 return 31;
1934 else
1935 return 15;
1936}
1937
158ae64f
VS		 1938/* Calculate the maximum primary/sprite plane watermark */
1939static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1940 int level,
240264f4 1941 const struct intel_wm_config *config,
158ae64f
VS		 1942 enum intel_ddb_partitioning ddb_partitioning,
1943 bool is_sprite)
1944{
1945 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1946
1947 /* if sprites aren't enabled, sprites get nothing */
240264f4 1948 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1949 return 0;
1950
1951 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1952 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1953 fifo_size /= INTEL_INFO(dev)->num_pipes;
1954
1955 /*
1956 * For some reason the non self refresh
1957 * FIFO size is only half of the self
1958 * refresh FIFO size on ILK/SNB.
1959 */
1960 if (INTEL_INFO(dev)->gen <= 6)
1961 fifo_size /= 2;
1962 }
1963
240264f4 1964 if (config->sprites_enabled) {
158ae64f
VS		 1965 /* level 0 is always calculated with 1:1 split */
1966 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1967 if (is_sprite)
1968 fifo_size *= 5;
1969 fifo_size /= 6;
1970 } else {
1971 fifo_size /= 2;
1972 }
1973 }
1974
1975 /* clamp to max that the registers can hold */
4e975081 1976 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1977}
1978
1979/* Calculate the maximum cursor plane watermark */
1980static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1981 int level,
1982 const struct intel_wm_config *config)
158ae64f
VS		 1983{
1984 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1985 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1986 return 64;
1987
1988 /* otherwise just report max that registers can hold */
4e975081 1989 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1990}
1991
d34ff9c6 1992static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1993 int level,
1994 const struct intel_wm_config *config,
1995 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1996 struct ilk_wm_maximums *max)
158ae64f 1997{
240264f4
VS		 1998 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1999 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2000 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 2001 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 2002}
2003
a3cb4048
VS		 2004static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
2005 int level,
2006 struct ilk_wm_maximums *max)
2007{
2008 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2009 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2010 max->cur = ilk_cursor_wm_reg_max(dev, level);
2011 max->fbc = ilk_fbc_wm_reg_max(dev);
2012}
2013
d9395655 2014static bool ilk_validate_wm_level(int level,
820c1980 2015 const struct ilk_wm_maximums *max,
d9395655 2016 struct intel_wm_level *result)
a9786a11
VS		 2017{
2018 bool ret;
2019
2020 /* already determined to be invalid? */
2021 if (!result->enable)
2022 return false;
2023
2024 result->enable = result->pri_val <= max->pri &&
2025 result->spr_val <= max->spr &&
2026 result->cur_val <= max->cur;
2027
2028 ret = result->enable;
2029
2030 /*
2031 * HACK until we can pre-compute everything,
2032 * and thus fail gracefully if LP0 watermarks
2033 * are exceeded...
2034 */
2035 if (level == 0 && !result->enable) {
2036 if (result->pri_val > max->pri)
2037 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2038 level, result->pri_val, max->pri);
2039 if (result->spr_val > max->spr)
2040 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2041 level, result->spr_val, max->spr);
2042 if (result->cur_val > max->cur)
2043 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2044 level, result->cur_val, max->cur);
2045
2046 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2047 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2048 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2049 result->enable = true;
2050 }
2051
a9786a11
VS		 2052 return ret;
2053}
2054
d34ff9c6 2055static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2056 int level,
820c1980 2057 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2058 struct intel_wm_level *result)
6f5ddd17
VS		 2059{
2060 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2061 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2062 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2063
2064 /* WM1+ latency values stored in 0.5us units */
2065 if (level > 0) {
2066 pri_latency *= 5;
2067 spr_latency *= 5;
2068 cur_latency *= 5;
2069 }
2070
2071 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2072 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2073 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2074 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2075 result->enable = true;
2076}
2077
801bcfff
PZ		 2078static uint32_t
2079hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2080{
2081 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 2083 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2084 u32 linetime, ips_linetime;
1f8eeabf 2085
3ef00284 2086 if (!intel_crtc->active)
801bcfff 2087 return 0;
1011d8c4 2088
1f8eeabf
ED		 2089 /* The WM are computed with base on how long it takes to fill a single
2090 * row at the given clock rate, multiplied by 8.
2091 * */
fec8cba3
JB		 2092 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2093 mode->crtc_clock);
2094 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
05024da3 2095 dev_priv->cdclk_freq);
1f8eeabf 2096
801bcfff
PZ		 2097 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2098 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2099}
2100
2af30a5c 2101static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2102{
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104
2af30a5c
PB		 2105 if (IS_GEN9(dev)) {
2106 uint32_t val;
4f947386 2107 int ret, i;
367294be 2108 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2109
2110 /* read the first set of memory latencies[0:3] */
2111 val = 0; /* data0 to be programmed to 0 for first set */
2112 mutex_lock(&dev_priv->rps.hw_lock);
2113 ret = sandybridge_pcode_read(dev_priv,
2114 GEN9_PCODE_READ_MEM_LATENCY,
2115 &val);
2116 mutex_unlock(&dev_priv->rps.hw_lock);
2117
2118 if (ret) {
2119 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120 return;
2121 }
2122
2123 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
2131 /* read the second set of memory latencies[4:7] */
2132 val = 1; /* data0 to be programmed to 1 for second set */
2133 mutex_lock(&dev_priv->rps.hw_lock);
2134 ret = sandybridge_pcode_read(dev_priv,
2135 GEN9_PCODE_READ_MEM_LATENCY,
2136 &val);
2137 mutex_unlock(&dev_priv->rps.hw_lock);
2138 if (ret) {
2139 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2140 return;
2141 }
2142
2143 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2144 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2145 GEN9_MEM_LATENCY_LEVEL_MASK;
2146 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2147 GEN9_MEM_LATENCY_LEVEL_MASK;
2148 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2149 GEN9_MEM_LATENCY_LEVEL_MASK;
2150
367294be 2151 /*
6f97235b
DL		 2152 * WaWmMemoryReadLatency:skl
2153 *
367294be
VK		 2154 * punit doesn't take into account the read latency so we need
2155 * to add 2us to the various latency levels we retrieve from
2156 * the punit.
2157 * - W0 is a bit special in that it's the only level that
2158 * can't be disabled if we want to have display working, so
2159 * we always add 2us there.
2160 * - For levels >=1, punit returns 0us latency when they are
2161 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2162 *
2163 * Additionally, if a level n (n > 1) has a 0us latency, all
2164 * levels m (m >= n) need to be disabled. We make sure to
2165 * sanitize the values out of the punit to satisfy this
2166 * requirement.
367294be
VK		 2167 */
2168 wm[0] += 2;
2169 for (level = 1; level <= max_level; level++)
2170 if (wm[level] != 0)
2171 wm[level] += 2;
4f947386
VK		 2172 else {
2173 for (i = level + 1; i <= max_level; i++)
2174 wm[i] = 0;
367294be 2175
4f947386
VK		 2176 break;
2177 }
2af30a5c 2178 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2179 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2180
2181 wm[0] = (sskpd >> 56) & 0xFF;
2182 if (wm[0] == 0)
2183 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2184 wm[1] = (sskpd >> 4) & 0xFF;
2185 wm[2] = (sskpd >> 12) & 0xFF;
2186 wm[3] = (sskpd >> 20) & 0x1FF;
2187 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2188 } else if (INTEL_INFO(dev)->gen >= 6) {
2189 uint32_t sskpd = I915_READ(MCH_SSKPD);
2190
2191 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2192 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2193 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2194 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2195 } else if (INTEL_INFO(dev)->gen >= 5) {
2196 uint32_t mltr = I915_READ(MLTR_ILK);
2197
2198 /* ILK primary LP0 latency is 700 ns */
2199 wm[0] = 7;
2200 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2201 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2202 }
2203}
2204
53615a5e
VS		 2205static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2206{
2207 /* ILK sprite LP0 latency is 1300 ns */
2208 if (INTEL_INFO(dev)->gen == 5)
2209 wm[0] = 13;
2210}
2211
2212static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2213{
2214 /* ILK cursor LP0 latency is 1300 ns */
2215 if (INTEL_INFO(dev)->gen == 5)
2216 wm[0] = 13;
2217
2218 /* WaDoubleCursorLP3Latency:ivb */
2219 if (IS_IVYBRIDGE(dev))
2220 wm[3] *= 2;
2221}
2222
546c81fd 2223int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2224{
26ec971e 2225 /* how many WM levels are we expecting */
b6e742f6 2226 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2227 return 7;
2228 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2229 return 4;
26ec971e 2230 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2231 return 3;
26ec971e 2232 else
ad0d6dc4
VS		 2233 return 2;
2234}
7526ed79 2235
ad0d6dc4
VS		 2236static void intel_print_wm_latency(struct drm_device *dev,
2237 const char *name,
2af30a5c 2238 const uint16_t wm[8])
ad0d6dc4
VS		 2239{
2240 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2241
2242 for (level = 0; level <= max_level; level++) {
2243 unsigned int latency = wm[level];
2244
2245 if (latency == 0) {
2246 DRM_ERROR("%s WM%d latency not provided\n",
2247 name, level);
2248 continue;
2249 }
2250
2af30a5c
PB		 2251 /*
2252 * - latencies are in us on gen9.
2253 * - before then, WM1+ latency values are in 0.5us units
2254 */
2255 if (IS_GEN9(dev))
2256 latency *= 10;
2257 else if (level > 0)
26ec971e
VS		 2258 latency *= 5;
2259
2260 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2261 name, level, wm[level],
2262 latency / 10, latency % 10);
2263 }
2264}
2265
e95a2f75
VS		 2266static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2267 uint16_t wm[5], uint16_t min)
2268{
2269 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2270
2271 if (wm[0] >= min)
2272 return false;
2273
2274 wm[0] = max(wm[0], min);
2275 for (level = 1; level <= max_level; level++)
2276 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2277
2278 return true;
2279}
2280
2281static void snb_wm_latency_quirk(struct drm_device *dev)
2282{
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284 bool changed;
2285
2286 /*
2287 * The BIOS provided WM memory latency values are often
2288 * inadequate for high resolution displays. Adjust them.
2289 */
2290 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2291 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2292 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2293
2294 if (!changed)
2295 return;
2296
2297 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2298 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2299 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2300 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2301}
2302
fa50ad61 2303static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2304{
2305 struct drm_i915_private *dev_priv = dev->dev_private;
2306
2307 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2308
2309 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2310 sizeof(dev_priv->wm.pri_latency));
2311 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2312 sizeof(dev_priv->wm.pri_latency));
2313
2314 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2315 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2316
2317 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2318 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2319 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2320
2321 if (IS_GEN6(dev))
2322 snb_wm_latency_quirk(dev);
53615a5e
VS		 2323}
2324
2af30a5c
PB		 2325static void skl_setup_wm_latency(struct drm_device *dev)
2326{
2327 struct drm_i915_private *dev_priv = dev->dev_private;
2328
2329 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2330 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2331}
2332
820c1980 2333static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2334 struct ilk_pipe_wm_parameters *p)
1011d8c4 2335{
7c4a395f
VS		 2336 struct drm_device *dev = crtc->dev;
2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2339 struct drm_plane *plane;
1011d8c4 2340
3ef00284 2341 if (!intel_crtc->active)
2a44b76b 2342 return;
801bcfff 2343
2a44b76b 2344 p->active = true;
6e3c9717 2345 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2346 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2347
54da691d 2348 if (crtc->primary->state->fb)
c9f038a1
MR		 2349 p->pri.bytes_per_pixel =
2350 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG		 2351 else
2352 p->pri.bytes_per_pixel = 4;
2353
2354 p->cur.bytes_per_pixel = 4;
2355 /*
2356 * TODO: for now, assume primary and cursor planes are always enabled.
2357 * Setting them to false makes the screen flicker.
2358 */
2359 p->pri.enabled = true;
2360 p->cur.enabled = true;
c9f038a1 2361
6e3c9717 2362 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2363 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2364
4ea50e99 2365 drm_for_each_legacy_plane(plane, dev) {
801bcfff 2366 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2367
2a44b76b 2368 if (intel_plane->pipe == pipe) {
7c4a395f 2369 p->spr = intel_plane->wm;
2a44b76b
VS		 2370 break;
2371 }
2372 }
2373}
2374
2375static void ilk_compute_wm_config(struct drm_device *dev,
2376 struct intel_wm_config *config)
2377{
2378 struct intel_crtc *intel_crtc;
2379
2380 /* Compute the currently _active_ config */
d3fcc808 2381 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2382 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2383
2a44b76b
VS		 2384 if (!wm->pipe_enabled)
2385 continue;
cca32e9a 2386
2a44b76b
VS		 2387 config->sprites_enabled |= wm->sprites_enabled;
2388 config->sprites_scaled |= wm->sprites_scaled;
2389 config->num_pipes_active++;
cca32e9a 2390 }
801bcfff
PZ		 2391}
2392
0b2ae6d7
VS		 2393/* Compute new watermarks for the pipe */
2394static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2395 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2396 struct intel_pipe_wm *pipe_wm)
2397{
2398 struct drm_device *dev = crtc->dev;
d34ff9c6 2399 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2400 int level, max_level = ilk_wm_max_level(dev);
2401 /* LP0 watermark maximums depend on this pipe alone */
2402 struct intel_wm_config config = {
2403 .num_pipes_active = 1,
2404 .sprites_enabled = params->spr.enabled,
2405 .sprites_scaled = params->spr.scaled,
2406 };
820c1980 2407 struct ilk_wm_maximums max;
0b2ae6d7 2408
2a44b76b
VS		 2409 pipe_wm->pipe_enabled = params->active;
2410 pipe_wm->sprites_enabled = params->spr.enabled;
2411 pipe_wm->sprites_scaled = params->spr.scaled;
2412
7b39a0b7
VS		 2413 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2414 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2415 max_level = 1;
2416
2417 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2418 if (params->spr.scaled)
2419 max_level = 0;
2420
a3cb4048 2421 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2422
a42a5719 2423 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2424 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2425
a3cb4048
VS		 2426 /* LP0 watermarks always use 1/2 DDB partitioning */
2427 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2428
0b2ae6d7 2429 /* At least LP0 must be valid */
a3cb4048
VS		 2430 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2431 return false;
2432
2433 ilk_compute_wm_reg_maximums(dev, 1, &max);
2434
2435 for (level = 1; level <= max_level; level++) {
2436 struct intel_wm_level wm = {};
2437
2438 ilk_compute_wm_level(dev_priv, level, params, &wm);
2439
2440 /*
2441 * Disable any watermark level that exceeds the
2442 * register maximums since such watermarks are
2443 * always invalid.
2444 */
2445 if (!ilk_validate_wm_level(level, &max, &wm))
2446 break;
2447
2448 pipe_wm->wm[level] = wm;
2449 }
2450
2451 return true;
0b2ae6d7
VS		 2452}
2453
2454/*
2455 * Merge the watermarks from all active pipes for a specific level.
2456 */
2457static void ilk_merge_wm_level(struct drm_device *dev,
2458 int level,
2459 struct intel_wm_level *ret_wm)
2460{
2461 const struct intel_crtc *intel_crtc;
2462
d52fea5b
VS		 2463 ret_wm->enable = true;
2464
d3fcc808 2465 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2466 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2467 const struct intel_wm_level *wm = &active->wm[level];
2468
2469 if (!active->pipe_enabled)
2470 continue;
0b2ae6d7 2471
d52fea5b
VS		 2472 /*
2473 * The watermark values may have been used in the past,
2474 * so we must maintain them in the registers for some
2475 * time even if the level is now disabled.
2476 */
0b2ae6d7 2477 if (!wm->enable)
d52fea5b 2478 ret_wm->enable = false;
0b2ae6d7
VS		 2479
2480 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2481 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2482 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2483 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2484 }
0b2ae6d7
VS		 2485}
2486
2487/*
2488 * Merge all low power watermarks for all active pipes.
2489 */
2490static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2491 const struct intel_wm_config *config,
820c1980 2492 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2493 struct intel_pipe_wm *merged)
2494{
7733b49b 2495 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2496 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2497 int last_enabled_level = max_level;
0b2ae6d7 2498
0ba22e26
VS		 2499 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2500 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2501 config->num_pipes_active > 1)
2502 return;
2503
6c8b6c28
VS		 2504 /* ILK: FBC WM must be disabled always */
2505 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2506
2507 /* merge each WM1+ level */
2508 for (level = 1; level <= max_level; level++) {
2509 struct intel_wm_level *wm = &merged->wm[level];
2510
2511 ilk_merge_wm_level(dev, level, wm);
2512
d52fea5b
VS		 2513 if (level > last_enabled_level)
2514 wm->enable = false;
2515 else if (!ilk_validate_wm_level(level, max, wm))
2516 /* make sure all following levels get disabled */
2517 last_enabled_level = level - 1;
0b2ae6d7
VS		 2518
2519 /*
2520 * The spec says it is preferred to disable
2521 * FBC WMs instead of disabling a WM level.
2522 */
2523 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2524 if (wm->enable)
2525 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2526 wm->fbc_val = 0;
2527 }
2528 }
6c8b6c28
VS		 2529
2530 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2531 /*
2532 * FIXME this is racy. FBC might get enabled later.
2533 * What we should check here is whether FBC can be
2534 * enabled sometime later.
2535 */
7733b49b
PZ		 2536 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2537 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2538 for (level = 2; level <= max_level; level++) {
2539 struct intel_wm_level *wm = &merged->wm[level];
2540
2541 wm->enable = false;
2542 }
2543 }
0b2ae6d7
VS		 2544}
2545
b380ca3c
VS		 2546static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2547{
2548 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2549 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2550}
2551
a68d68ee
VS		 2552/* The value we need to program into the WM_LPx latency field */
2553static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2554{
2555 struct drm_i915_private *dev_priv = dev->dev_private;
2556
a42a5719 2557 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2558 return 2 * level;
2559 else
2560 return dev_priv->wm.pri_latency[level];
2561}
2562
820c1980 2563static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2564 const struct intel_pipe_wm *merged,
609cedef 2565 enum intel_ddb_partitioning partitioning,
820c1980 2566 struct ilk_wm_values *results)
801bcfff 2567{
0b2ae6d7
VS		 2568 struct intel_crtc *intel_crtc;
2569 int level, wm_lp;
cca32e9a 2570
0362c781 2571 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2572 results->partitioning = partitioning;
cca32e9a 2573
0b2ae6d7 2574 /* LP1+ register values */
cca32e9a 2575 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2576 const struct intel_wm_level *r;
801bcfff 2577
b380ca3c 2578 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2579
0362c781 2580 r = &merged->wm[level];
cca32e9a 2581
d52fea5b
VS		 2582 /*
2583 * Maintain the watermark values even if the level is
2584 * disabled. Doing otherwise could cause underruns.
2585 */
2586 results->wm_lp[wm_lp - 1] =
a68d68ee 2587 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2588 (r->pri_val << WM1_LP_SR_SHIFT) |
2589 r->cur_val;
2590
d52fea5b
VS		 2591 if (r->enable)
2592 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2593
416f4727
VS		 2594 if (INTEL_INFO(dev)->gen >= 8)
2595 results->wm_lp[wm_lp - 1] |=
2596 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2597 else
2598 results->wm_lp[wm_lp - 1] |=
2599 r->fbc_val << WM1_LP_FBC_SHIFT;
2600
d52fea5b
VS		 2601 /*
2602 * Always set WM1S_LP_EN when spr_val != 0, even if the
2603 * level is disabled. Doing otherwise could cause underruns.
2604 */
6cef2b8a
VS		 2605 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2606 WARN_ON(wm_lp != 1);
2607 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2608 } else
2609 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2610 }
801bcfff 2611
0b2ae6d7 2612 /* LP0 register values */
d3fcc808 2613 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2614 enum pipe pipe = intel_crtc->pipe;
2615 const struct intel_wm_level *r =
2616 &intel_crtc->wm.active.wm[0];
2617
2618 if (WARN_ON(!r->enable))
2619 continue;
2620
2621 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2622
0b2ae6d7
VS		 2623 results->wm_pipe[pipe] =
2624 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2625 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2626 r->cur_val;
801bcfff
PZ		 2627 }
2628}
2629
861f3389
PZ		 2630/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2631 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2632static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2633 struct intel_pipe_wm *r1,
2634 struct intel_pipe_wm *r2)
861f3389 2635{
198a1e9b
VS		 2636 int level, max_level = ilk_wm_max_level(dev);
2637 int level1 = 0, level2 = 0;
861f3389 2638
198a1e9b
VS		 2639 for (level = 1; level <= max_level; level++) {
2640 if (r1->wm[level].enable)
2641 level1 = level;
2642 if (r2->wm[level].enable)
2643 level2 = level;
861f3389
PZ		 2644 }
2645
198a1e9b
VS		 2646 if (level1 == level2) {
2647 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2648 return r2;
2649 else
2650 return r1;
198a1e9b 2651 } else if (level1 > level2) {
861f3389
PZ		 2652 return r1;
2653 } else {
2654 return r2;
2655 }
2656}
2657
49a687c4
VS		 2658/* dirty bits used to track which watermarks need changes */
2659#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2660#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2661#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2662#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2663#define WM_DIRTY_FBC (1 << 24)
2664#define WM_DIRTY_DDB (1 << 25)
2665
055e393f 2666static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2667 const struct ilk_wm_values *old,
2668 const struct ilk_wm_values *new)
49a687c4
VS		 2669{
2670 unsigned int dirty = 0;
2671 enum pipe pipe;
2672 int wm_lp;
2673
055e393f 2674 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2675 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2676 dirty |= WM_DIRTY_LINETIME(pipe);
2677 /* Must disable LP1+ watermarks too */
2678 dirty |= WM_DIRTY_LP_ALL;
2679 }
2680
2681 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2682 dirty |= WM_DIRTY_PIPE(pipe);
2683 /* Must disable LP1+ watermarks too */
2684 dirty |= WM_DIRTY_LP_ALL;
2685 }
2686 }
2687
2688 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2689 dirty |= WM_DIRTY_FBC;
2690 /* Must disable LP1+ watermarks too */
2691 dirty |= WM_DIRTY_LP_ALL;
2692 }
2693
2694 if (old->partitioning != new->partitioning) {
2695 dirty |= WM_DIRTY_DDB;
2696 /* Must disable LP1+ watermarks too */
2697 dirty |= WM_DIRTY_LP_ALL;
2698 }
2699
2700 /* LP1+ watermarks already deemed dirty, no need to continue */
2701 if (dirty & WM_DIRTY_LP_ALL)
2702 return dirty;
2703
2704 /* Find the lowest numbered LP1+ watermark in need of an update... */
2705 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2706 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2707 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2708 break;
2709 }
2710
2711 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2712 for (; wm_lp <= 3; wm_lp++)
2713 dirty |= WM_DIRTY_LP(wm_lp);
2714
2715 return dirty;
2716}
2717
8553c18e
VS		 2718static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2719 unsigned int dirty)
801bcfff 2720{
820c1980 2721 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2722 bool changed = false;
801bcfff 2723
facd619b
VS		 2724 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2725 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2726 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2727 changed = true;
facd619b
VS		 2728 }
2729 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2730 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2731 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2732 changed = true;
facd619b
VS		 2733 }
2734 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2735 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2736 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2737 changed = true;
facd619b 2738 }
801bcfff 2739
facd619b
VS		 2740 /*
2741 * Don't touch WM1S_LP_EN here.
2742 * Doing so could cause underruns.
2743 */
6cef2b8a 2744
8553c18e
VS		 2745 return changed;
2746}
2747
2748/*
2749 * The spec says we shouldn't write when we don't need, because every write
2750 * causes WMs to be re-evaluated, expending some power.
2751 */
820c1980
ID		 2752static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2753 struct ilk_wm_values *results)
8553c18e
VS		 2754{
2755 struct drm_device *dev = dev_priv->dev;
820c1980 2756 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2757 unsigned int dirty;
2758 uint32_t val;
2759
055e393f 2760 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2761 if (!dirty)
2762 return;
2763
2764 _ilk_disable_lp_wm(dev_priv, dirty);
2765
49a687c4 2766 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2767 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2768 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2769 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2770 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2771 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2772
49a687c4 2773 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2774 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2775 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2776 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2777 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2778 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2779
49a687c4 2780 if (dirty & WM_DIRTY_DDB) {
a42a5719 2781 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2782 val = I915_READ(WM_MISC);
2783 if (results->partitioning == INTEL_DDB_PART_1_2)
2784 val &= ~WM_MISC_DATA_PARTITION_5_6;
2785 else
2786 val |= WM_MISC_DATA_PARTITION_5_6;
2787 I915_WRITE(WM_MISC, val);
2788 } else {
2789 val = I915_READ(DISP_ARB_CTL2);
2790 if (results->partitioning == INTEL_DDB_PART_1_2)
2791 val &= ~DISP_DATA_PARTITION_5_6;
2792 else
2793 val |= DISP_DATA_PARTITION_5_6;
2794 I915_WRITE(DISP_ARB_CTL2, val);
2795 }
1011d8c4
PZ		 2796 }
2797
49a687c4 2798 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2799 val = I915_READ(DISP_ARB_CTL);
2800 if (results->enable_fbc_wm)
2801 val &= ~DISP_FBC_WM_DIS;
2802 else
2803 val |= DISP_FBC_WM_DIS;
2804 I915_WRITE(DISP_ARB_CTL, val);
2805 }
2806
954911eb
ID		 2807 if (dirty & WM_DIRTY_LP(1) &&
2808 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2809 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2810
2811 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2812 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2813 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2814 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2815 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2816 }
801bcfff 2817
facd619b 2818 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2819 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2820 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2821 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2822 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2823 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2824
2825 dev_priv->wm.hw = *results;
801bcfff
PZ		 2826}
2827
8553c18e
VS		 2828static bool ilk_disable_lp_wm(struct drm_device *dev)
2829{
2830 struct drm_i915_private *dev_priv = dev->dev_private;
2831
2832 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2833}
2834
b9cec075
DL		 2835/*
2836 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2837 * different active planes.
2838 */
2839
2840#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2841#define BXT_DDB_SIZE 512
b9cec075
DL		 2842
2843static void
2844skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2845 struct drm_crtc *for_crtc,
2846 const struct intel_wm_config *config,
2847 const struct skl_pipe_wm_parameters *params,
2848 struct skl_ddb_entry *alloc /* out */)
2849{
2850 struct drm_crtc *crtc;
2851 unsigned int pipe_size, ddb_size;
2852 int nth_active_pipe;
2853
2854 if (!params->active) {
2855 alloc->start = 0;
2856 alloc->end = 0;
2857 return;
2858 }
2859
43d735a6
DL		 2860 if (IS_BROXTON(dev))
2861 ddb_size = BXT_DDB_SIZE;
2862 else
2863 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2864
2865 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2866
2867 nth_active_pipe = 0;
2868 for_each_crtc(dev, crtc) {
3ef00284 2869 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2870 continue;
2871
2872 if (crtc == for_crtc)
2873 break;
2874
2875 nth_active_pipe++;
2876 }
2877
2878 pipe_size = ddb_size / config->num_pipes_active;
2879 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2880 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2881}
2882
2883static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2884{
2885 if (config->num_pipes_active == 1)
2886 return 32;
2887
2888 return 8;
2889}
2890
a269c583
DL		 2891static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2892{
2893 entry->start = reg & 0x3ff;
2894 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2895 if (entry->end)
2896 entry->end += 1;
a269c583
DL		 2897}
2898
08db6652
DL		 2899void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2900 struct skl_ddb_allocation *ddb /* out */)
a269c583 2901{
a269c583
DL		 2902 enum pipe pipe;
2903 int plane;
2904 u32 val;
2905
2906 for_each_pipe(dev_priv, pipe) {
dd740780 2907 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2908 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2909 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2910 val);
2911 }
2912
2913 val = I915_READ(CUR_BUF_CFG(pipe));
2914 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2915 }
2916}
2917
b9cec075 2918static unsigned int
2cd601c6 2919skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2920{
2cd601c6
CK		 2921
2922 /* for planar format */
2923 if (p->y_bytes_per_pixel) {
2924 if (y) /* y-plane data rate */
2925 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2926 else /* uv-plane data rate */
2927 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2928 }
2929
2930 /* for packed formats */
b9cec075
DL		 2931 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2932}
2933
2934/*
2935 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2936 * a 8192x4096@32bpp framebuffer:
2937 * 3 * 4096 * 8192 * 4 < 2^32
2938 */
2939static unsigned int
2940skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2941 const struct skl_pipe_wm_parameters *params)
2942{
2943 unsigned int total_data_rate = 0;
2944 int plane;
2945
2946 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2947 const struct intel_plane_wm_parameters *p;
2948
2949 p = &params->plane[plane];
2950 if (!p->enabled)
2951 continue;
2952
2cd601c6
CK		 2953 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2954 if (p->y_bytes_per_pixel) {
2955 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2956 }
b9cec075
DL		 2957 }
2958
2959 return total_data_rate;
2960}
2961
2962static void
2963skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2964 const struct intel_wm_config *config,
2965 const struct skl_pipe_wm_parameters *params,
2966 struct skl_ddb_allocation *ddb /* out */)
2967{
2968 struct drm_device *dev = crtc->dev;
dd740780 2969 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2971 enum pipe pipe = intel_crtc->pipe;
34bb56af 2972 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2973 uint16_t alloc_size, start, cursor_blocks;
80958155 2974 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2975 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2976 unsigned int total_data_rate;
2977 int plane;
2978
34bb56af
DL		 2979 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2980 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2981 if (alloc_size == 0) {
2982 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2983 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2984 return;
2985 }
2986
2987 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2988 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2989 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2990
2991 alloc_size -= cursor_blocks;
34bb56af 2992 alloc->end -= cursor_blocks;
b9cec075 2993
80958155 2994 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2995 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2996 const struct intel_plane_wm_parameters *p;
2997
2998 p = &params->plane[plane];
2999 if (!p->enabled)
3000 continue;
3001
3002 minimum[plane] = 8;
3003 alloc_size -= minimum[plane];
2cd601c6
CK		 3004 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
3005 alloc_size -= y_minimum[plane];
80958155
DL		 3006 }
3007
b9cec075 3008 /*
80958155
DL		 3009 * 2. Distribute the remaining space in proportion to the amount of
3010 * data each plane needs to fetch from memory.
b9cec075
DL		 3011 *
3012 * FIXME: we may not allocate every single block here.
3013 */
3014 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3015
34bb56af 3016 start = alloc->start;
b9cec075
DL		 3017 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3018 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 3019 unsigned int data_rate, y_data_rate;
3020 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 3021
3022 p = &params->plane[plane];
3023 if (!p->enabled)
3024 continue;
3025
2cd601c6 3026 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 3027
3028 /*
2cd601c6 3029 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3030 * promote the expression to 64 bits to avoid overflowing, the
3031 * result is < available as data_rate / total_data_rate < 1
3032 */
80958155
DL		 3033 plane_blocks = minimum[plane];
3034 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3035 total_data_rate);
b9cec075
DL		 3036
3037 ddb->plane[pipe][plane].start = start;
16160e3d 3038 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3039
3040 start += plane_blocks;
2cd601c6
CK		 3041
3042 /*
3043 * allocation for y_plane part of planar format:
3044 */
3045 if (p->y_bytes_per_pixel) {
3046 y_data_rate = skl_plane_relative_data_rate(p, 1);
3047 y_plane_blocks = y_minimum[plane];
3048 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3049 total_data_rate);
3050
3051 ddb->y_plane[pipe][plane].start = start;
3052 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3053
3054 start += y_plane_blocks;
3055 }
3056
b9cec075
DL		 3057 }
3058
3059}
3060
5cec258b 3061static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3062{
3063 /* TODO: Take into account the scalers once we support them */
2d112de7 3064 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3065}
3066
3067/*
3068 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3069 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3070 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3071 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3072*/
3073static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3074 uint32_t latency)
3075{
3076 uint32_t wm_intermediate_val, ret;
3077
3078 if (latency == 0)
3079 return UINT_MAX;
3080
d4c2aa60 3081 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3082 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3083
3084 return ret;
3085}
3086
3087static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3088 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3089 uint64_t tiling, uint32_t latency)
2d41c0b5 3090{
d4c2aa60
TU		 3091 uint32_t ret;
3092 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3093 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3094
3095 if (latency == 0)
3096 return UINT_MAX;
3097
3098 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3099
3100 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3101 tiling == I915_FORMAT_MOD_Yf_TILED) {
3102 plane_bytes_per_line *= 4;
3103 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3104 plane_blocks_per_line /= 4;
3105 } else {
3106 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3107 }
3108
2d41c0b5
PB		 3109 wm_intermediate_val = latency * pixel_rate;
3110 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3111 plane_blocks_per_line;
2d41c0b5
PB		 3112
3113 return ret;
3114}
3115
2d41c0b5
PB		 3116static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3117 const struct intel_crtc *intel_crtc)
3118{
3119 struct drm_device *dev = intel_crtc->base.dev;
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3122 enum pipe pipe = intel_crtc->pipe;
3123
3124 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3125 sizeof(new_ddb->plane[pipe])))
3126 return true;
3127
3128 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3129 sizeof(new_ddb->cursor[pipe])))
3130 return true;
3131
3132 return false;
3133}
3134
3135static void skl_compute_wm_global_parameters(struct drm_device *dev,
3136 struct intel_wm_config *config)
3137{
3138 struct drm_crtc *crtc;
3139 struct drm_plane *plane;
3140
3141 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 3142 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 3143
3144 /* FIXME: I don't think we need those two global parameters on SKL */
3145 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3146 struct intel_plane *intel_plane = to_intel_plane(plane);
3147
3148 config->sprites_enabled |= intel_plane->wm.enabled;
3149 config->sprites_scaled |= intel_plane->wm.scaled;
3150 }
3151}
3152
3153static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3154 struct skl_pipe_wm_parameters *p)
3155{
3156 struct drm_device *dev = crtc->dev;
3157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3158 enum pipe pipe = intel_crtc->pipe;
3159 struct drm_plane *plane;
0fda6568 3160 struct drm_framebuffer *fb;
2d41c0b5
PB		 3161 int i = 1; /* Index for sprite planes start */
3162
3ef00284 3163 p->active = intel_crtc->active;
2d41c0b5 3164 if (p->active) {
6e3c9717
ACO		 3165 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3166 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 3167
0fda6568 3168 fb = crtc->primary->state->fb;
2cd601c6 3169 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 3170 if (fb) {
3171 p->plane[0].enabled = true;
2cd601c6 3172 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
395ab754
KM		 3173 drm_format_plane_cpp(fb->pixel_format, 1) :
3174 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6
CK		 3175 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3176 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 3177 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 3178 } else {
3179 p->plane[0].enabled = false;
3180 p->plane[0].bytes_per_pixel = 0;
2cd601c6 3181 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 3182 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3183 }
3184 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3185 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 3186 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 3187
c9f038a1 3188 fb = crtc->cursor->state->fb;
2cd601c6 3189 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 3190 if (fb) {
3191 p->cursor.enabled = true;
3192 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3193 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3194 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3195 } else {
3196 p->cursor.enabled = false;
3197 p->cursor.bytes_per_pixel = 0;
3198 p->cursor.horiz_pixels = 64;
3199 p->cursor.vert_pixels = 64;
3200 }
2d41c0b5
PB		 3201 }
3202
3203 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3204 struct intel_plane *intel_plane = to_intel_plane(plane);
3205
a712f8eb
SJ		 3206 if (intel_plane->pipe == pipe &&
3207 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 3208 p->plane[i++] = intel_plane->wm;
3209 }
3210}
3211
d4c2aa60
TU		 3212static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3213 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 3214 struct intel_plane_wm_parameters *p_params,
3215 uint16_t ddb_allocation,
d4c2aa60 3216 int level,
afb024aa
DL		 3217 uint16_t *out_blocks, /* out */
3218 uint8_t *out_lines /* out */)
2d41c0b5 3219{
d4c2aa60
TU		 3220 uint32_t latency = dev_priv->wm.skl_latency[level];
3221 uint32_t method1, method2;
3222 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3223 uint32_t res_blocks, res_lines;
3224 uint32_t selected_result;
2cd601c6 3225 uint8_t bytes_per_pixel;
2d41c0b5 3226
d4c2aa60 3227 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3228 return false;
3229
2cd601c6
CK		 3230 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3231 p_params->y_bytes_per_pixel :
3232 p_params->bytes_per_pixel;
2d41c0b5 3233 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 3234 bytes_per_pixel,
d4c2aa60 3235 latency);
2d41c0b5
PB		 3236 method2 = skl_wm_method2(p->pixel_rate,
3237 p->pipe_htotal,
3238 p_params->horiz_pixels,
2cd601c6 3239 bytes_per_pixel,
0fda6568 3240 p_params->tiling,
d4c2aa60 3241 latency);
2d41c0b5 3242
2cd601c6 3243 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 3244 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3245
0fda6568
TU		 3246 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3247 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3248 uint32_t min_scanlines = 4;
3249 uint32_t y_tile_minimum;
3250 if (intel_rotation_90_or_270(p_params->rotation)) {
3251 switch (p_params->bytes_per_pixel) {
3252 case 1:
3253 min_scanlines = 16;
3254 break;
3255 case 2:
3256 min_scanlines = 8;
3257 break;
3258 case 8:
3259 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3260 }
1fc0a8f7
TU		 3261 }
3262 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3263 selected_result = max(method2, y_tile_minimum);
3264 } else {
3265 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3266 selected_result = min(method1, method2);
3267 else
3268 selected_result = method1;
3269 }
2d41c0b5 3270
d4c2aa60
TU		 3271 res_blocks = selected_result + 1;
3272 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3273
0fda6568
TU		 3274 if (level >= 1 && level <= 7) {
3275 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3276 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3277 res_lines += 4;
3278 else
3279 res_blocks++;
3280 }
e6d66171 3281
d4c2aa60 3282 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3283 return false;
3284
3285 *out_blocks = res_blocks;
3286 *out_lines = res_lines;
2d41c0b5
PB		 3287
3288 return true;
3289}
3290
3291static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3292 struct skl_ddb_allocation *ddb,
3293 struct skl_pipe_wm_parameters *p,
3294 enum pipe pipe,
3295 int level,
3296 int num_planes,
3297 struct skl_wm_level *result)
3298{
2d41c0b5
PB		 3299 uint16_t ddb_blocks;
3300 int i;
3301
3302 for (i = 0; i < num_planes; i++) {
3303 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3304
d4c2aa60
TU		 3305 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3306 p, &p->plane[i],
2d41c0b5 3307 ddb_blocks,
d4c2aa60 3308 level,
2d41c0b5
PB		 3309 &result->plane_res_b[i],
3310 &result->plane_res_l[i]);
3311 }
3312
3313 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3314 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3315 ddb_blocks, level,
3316 &result->cursor_res_b,
2d41c0b5
PB		 3317 &result->cursor_res_l);
3318}
3319
407b50f3
DL		 3320static uint32_t
3321skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3322{
3ef00284 3323 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3324 return 0;
3325
661abfc0
MK		 3326 if (WARN_ON(p->pixel_rate == 0))
3327 return 0;
407b50f3 3328
661abfc0 3329 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
407b50f3
DL		 3330}
3331
3332static void skl_compute_transition_wm(struct drm_crtc *crtc,
3333 struct skl_pipe_wm_parameters *params,
9414f563 3334 struct skl_wm_level *trans_wm /* out */)
407b50f3 3335{
9414f563
DL		 3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 int i;
3338
407b50f3
DL		 3339 if (!params->active)
3340 return;
9414f563
DL		 3341
3342 /* Until we know more, just disable transition WMs */
3343 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3344 trans_wm->plane_en[i] = false;
3345 trans_wm->cursor_en = false;
407b50f3
DL		 3346}
3347
2d41c0b5
PB		 3348static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3349 struct skl_ddb_allocation *ddb,
3350 struct skl_pipe_wm_parameters *params,
3351 struct skl_pipe_wm *pipe_wm)
3352{
3353 struct drm_device *dev = crtc->dev;
3354 const struct drm_i915_private *dev_priv = dev->dev_private;
3355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356 int level, max_level = ilk_wm_max_level(dev);
3357
3358 for (level = 0; level <= max_level; level++) {
3359 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3360 level, intel_num_planes(intel_crtc),
3361 &pipe_wm->wm[level]);
3362 }
3363 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3364
9414f563 3365 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3366}
3367
3368static void skl_compute_wm_results(struct drm_device *dev,
3369 struct skl_pipe_wm_parameters *p,
3370 struct skl_pipe_wm *p_wm,
3371 struct skl_wm_values *r,
3372 struct intel_crtc *intel_crtc)
3373{
3374 int level, max_level = ilk_wm_max_level(dev);
3375 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3376 uint32_t temp;
3377 int i;
2d41c0b5
PB		 3378
3379 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3380 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3381 temp = 0;
2d41c0b5
PB		 3382
3383 temp |= p_wm->wm[level].plane_res_l[i] <<
3384 PLANE_WM_LINES_SHIFT;
3385 temp |= p_wm->wm[level].plane_res_b[i];
3386 if (p_wm->wm[level].plane_en[i])
3387 temp |= PLANE_WM_EN;
3388
3389 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3390 }
3391
3392 temp = 0;
2d41c0b5
PB		 3393
3394 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3395 temp |= p_wm->wm[level].cursor_res_b;
3396
3397 if (p_wm->wm[level].cursor_en)
3398 temp |= PLANE_WM_EN;
3399
3400 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3401
3402 }
3403
9414f563
DL		 3404 /* transition WMs */
3405 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3406 temp = 0;
3407 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3408 temp |= p_wm->trans_wm.plane_res_b[i];
3409 if (p_wm->trans_wm.plane_en[i])
3410 temp |= PLANE_WM_EN;
3411
3412 r->plane_trans[pipe][i] = temp;
3413 }
3414
3415 temp = 0;
3416 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3417 temp |= p_wm->trans_wm.cursor_res_b;
3418 if (p_wm->trans_wm.cursor_en)
3419 temp |= PLANE_WM_EN;
3420
3421 r->cursor_trans[pipe] = temp;
3422
2d41c0b5
PB		 3423 r->wm_linetime[pipe] = p_wm->linetime;
3424}
3425
16160e3d
DL		 3426static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3427 const struct skl_ddb_entry *entry)
3428{
3429 if (entry->end)
3430 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3431 else
3432 I915_WRITE(reg, 0);
3433}
3434
2d41c0b5
PB		 3435static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3436 const struct skl_wm_values *new)
3437{
3438 struct drm_device *dev = dev_priv->dev;
3439 struct intel_crtc *crtc;
3440
3441 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3442 int i, level, max_level = ilk_wm_max_level(dev);
3443 enum pipe pipe = crtc->pipe;
3444
5d374d96
DL		 3445 if (!new->dirty[pipe])
3446 continue;
8211bd5b 3447
5d374d96 3448 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3449
5d374d96
DL		 3450 for (level = 0; level <= max_level; level++) {
3451 for (i = 0; i < intel_num_planes(crtc); i++)
3452 I915_WRITE(PLANE_WM(pipe, i, level),
3453 new->plane[pipe][i][level]);
3454 I915_WRITE(CUR_WM(pipe, level),
3455 new->cursor[pipe][level]);
2d41c0b5 3456 }
5d374d96
DL		 3457 for (i = 0; i < intel_num_planes(crtc); i++)
3458 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3459 new->plane_trans[pipe][i]);
3460 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3461
2cd601c6 3462 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3463 skl_ddb_entry_write(dev_priv,
3464 PLANE_BUF_CFG(pipe, i),
3465 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3466 skl_ddb_entry_write(dev_priv,
3467 PLANE_NV12_BUF_CFG(pipe, i),
3468 &new->ddb.y_plane[pipe][i]);
3469 }
5d374d96
DL		 3470
3471 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3472 &new->ddb.cursor[pipe]);
2d41c0b5 3473 }
2d41c0b5
PB		 3474}
3475
0e8fb7ba
DL		 3476/*
3477 * When setting up a new DDB allocation arrangement, we need to correctly
3478 * sequence the times at which the new allocations for the pipes are taken into
3479 * account or we'll have pipes fetching from space previously allocated to
3480 * another pipe.
3481 *
3482 * Roughly the sequence looks like:
3483 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3484 * overlapping with a previous light-up pipe (another way to put it is:
3485 * pipes with their new allocation strickly included into their old ones).
3486 * 2. re-allocate the other pipes that get their allocation reduced
3487 * 3. allocate the pipes having their allocation increased
3488 *
3489 * Steps 1. and 2. are here to take care of the following case:
3490 * - Initially DDB looks like this:
3491 * | B | C |
3492 * - enable pipe A.
3493 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3494 * allocation
3495 * | A | B | C |
3496 *
3497 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3498 */
3499
d21b795c
DL		 3500static void
3501skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3502{
0e8fb7ba
DL		 3503 int plane;
3504
d21b795c
DL		 3505 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3506
dd740780 3507 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3508 I915_WRITE(PLANE_SURF(pipe, plane),
3509 I915_READ(PLANE_SURF(pipe, plane)));
3510 }
3511 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3512}
3513
3514static bool
3515skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3516 const struct skl_ddb_allocation *new,
3517 enum pipe pipe)
3518{
3519 uint16_t old_size, new_size;
3520
3521 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3522 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3523
3524 return old_size != new_size &&
3525 new->pipe[pipe].start >= old->pipe[pipe].start &&
3526 new->pipe[pipe].end <= old->pipe[pipe].end;
3527}
3528
3529static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3530 struct skl_wm_values *new_values)
3531{
3532 struct drm_device *dev = dev_priv->dev;
3533 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3534 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3535 struct intel_crtc *crtc;
3536 enum pipe pipe;
3537
3538 new_ddb = &new_values->ddb;
3539 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3540
3541 /*
3542 * First pass: flush the pipes with the new allocation contained into
3543 * the old space.
3544 *
3545 * We'll wait for the vblank on those pipes to ensure we can safely
3546 * re-allocate the freed space without this pipe fetching from it.
3547 */
3548 for_each_intel_crtc(dev, crtc) {
3549 if (!crtc->active)
3550 continue;
3551
3552 pipe = crtc->pipe;
3553
3554 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3555 continue;
3556
d21b795c 3557 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3558 intel_wait_for_vblank(dev, pipe);
3559
3560 reallocated[pipe] = true;
3561 }
3562
3563
3564 /*
3565 * Second pass: flush the pipes that are having their allocation
3566 * reduced, but overlapping with a previous allocation.
3567 *
3568 * Here as well we need to wait for the vblank to make sure the freed
3569 * space is not used anymore.
3570 */
3571 for_each_intel_crtc(dev, crtc) {
3572 if (!crtc->active)
3573 continue;
3574
3575 pipe = crtc->pipe;
3576
3577 if (reallocated[pipe])
3578 continue;
3579
3580 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3581 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3582 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3583 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3584 reallocated[pipe] = true;
0e8fb7ba 3585 }
0e8fb7ba
DL		 3586 }
3587
3588 /*
3589 * Third pass: flush the pipes that got more space allocated.
3590 *
3591 * We don't need to actively wait for the update here, next vblank
3592 * will just get more DDB space with the correct WM values.
3593 */
3594 for_each_intel_crtc(dev, crtc) {
3595 if (!crtc->active)
3596 continue;
3597
3598 pipe = crtc->pipe;
3599
3600 /*
3601 * At this point, only the pipes more space than before are
3602 * left to re-allocate.
3603 */
3604 if (reallocated[pipe])
3605 continue;
3606
d21b795c 3607 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3608 }
3609}
3610
2d41c0b5
PB		 3611static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3612 struct skl_pipe_wm_parameters *params,
3613 struct intel_wm_config *config,
3614 struct skl_ddb_allocation *ddb, /* out */
3615 struct skl_pipe_wm *pipe_wm /* out */)
3616{
3617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3618
3619 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3620 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3621 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3622
3623 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3624 return false;
3625
3626 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3627
2d41c0b5
PB		 3628 return true;
3629}
3630
3631static void skl_update_other_pipe_wm(struct drm_device *dev,
3632 struct drm_crtc *crtc,
3633 struct intel_wm_config *config,
3634 struct skl_wm_values *r)
3635{
3636 struct intel_crtc *intel_crtc;
3637 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3638
3639 /*
3640 * If the WM update hasn't changed the allocation for this_crtc (the
3641 * crtc we are currently computing the new WM values for), other
3642 * enabled crtcs will keep the same allocation and we don't need to
3643 * recompute anything for them.
3644 */
3645 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3646 return;
3647
3648 /*
3649 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3650 * other active pipes need new DDB allocation and WM values.
3651 */
3652 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3653 base.head) {
3654 struct skl_pipe_wm_parameters params = {};
3655 struct skl_pipe_wm pipe_wm = {};
3656 bool wm_changed;
3657
3658 if (this_crtc->pipe == intel_crtc->pipe)
3659 continue;
3660
3661 if (!intel_crtc->active)
3662 continue;
3663
3664 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3665 &params, config,
3666 &r->ddb, &pipe_wm);
3667
3668 /*
3669 * If we end up re-computing the other pipe WM values, it's
3670 * because it was really needed, so we expect the WM values to
3671 * be different.
3672 */
3673 WARN_ON(!wm_changed);
3674
3675 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3676 r->dirty[intel_crtc->pipe] = true;
3677 }
3678}
3679
3680static void skl_update_wm(struct drm_crtc *crtc)
3681{
3682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct skl_pipe_wm_parameters params = {};
3686 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3687 struct skl_pipe_wm pipe_wm = {};
3688 struct intel_wm_config config = {};
3689
3690 memset(results, 0, sizeof(*results));
3691
3692 skl_compute_wm_global_parameters(dev, &config);
3693
3694 if (!skl_update_pipe_wm(crtc, &params, &config,
3695 &results->ddb, &pipe_wm))
3696 return;
3697
3698 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3699 results->dirty[intel_crtc->pipe] = true;
3700
3701 skl_update_other_pipe_wm(dev, crtc, &config, results);
3702 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3703 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3704
3705 /* store the new configuration */
3706 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3707}
3708
3709static void
3710skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3711 uint32_t sprite_width, uint32_t sprite_height,
3712 int pixel_size, bool enabled, bool scaled)
3713{
3714 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3715 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3716
3717 intel_plane->wm.enabled = enabled;
3718 intel_plane->wm.scaled = scaled;
3719 intel_plane->wm.horiz_pixels = sprite_width;
3720 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3721 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3722
3723 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3724 intel_plane->wm.bytes_per_pixel =
3725 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3726 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3727 intel_plane->wm.y_bytes_per_pixel =
3728 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3729 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3730
0fda6568
TU		 3731 /*
3732 * Framebuffer can be NULL on plane disable, but it does not
3733 * matter for watermarks if we assume no tiling in that case.
3734 */
3735 if (fb)
3736 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3737 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3738
3739 skl_update_wm(crtc);
3740}
3741
820c1980 3742static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3743{
7c4a395f 3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3745 struct drm_device *dev = crtc->dev;
801bcfff 3746 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3747 struct ilk_wm_maximums max;
3748 struct ilk_pipe_wm_parameters params = {};
3749 struct ilk_wm_values results = {};
77c122bc 3750 enum intel_ddb_partitioning partitioning;
7c4a395f 3751 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3752 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3753 struct intel_wm_config config = {};
7c4a395f 3754
2a44b76b 3755 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3756
3757 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3758
3759 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3760 return;
861f3389 3761
7c4a395f 3762 intel_crtc->wm.active = pipe_wm;
861f3389 3763
2a44b76b
VS		 3764 ilk_compute_wm_config(dev, &config);
3765
34982fe1 3766 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3767 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3768
3769 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3770 if (INTEL_INFO(dev)->gen >= 7 &&
3771 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3772 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3773 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3774
820c1980 3775 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3776 } else {
198a1e9b 3777 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3778 }
3779
198a1e9b 3780 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3781 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3782
820c1980 3783 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3784
820c1980 3785 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3786}
3787
ed57cb8a
DL		 3788static void
3789ilk_update_sprite_wm(struct drm_plane *plane,
3790 struct drm_crtc *crtc,
3791 uint32_t sprite_width, uint32_t sprite_height,
3792 int pixel_size, bool enabled, bool scaled)
526682e9 3793{
8553c18e 3794 struct drm_device *dev = plane->dev;
adf3d35e 3795 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3796
adf3d35e
VS		 3797 intel_plane->wm.enabled = enabled;
3798 intel_plane->wm.scaled = scaled;
3799 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3800 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3801 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3802
8553c18e
VS		 3803 /*
3804 * IVB workaround: must disable low power watermarks for at least
3805 * one frame before enabling scaling. LP watermarks can be re-enabled
3806 * when scaling is disabled.
3807 *
3808 * WaCxSRDisabledForSpriteScaling:ivb
3809 */
3810 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3811 intel_wait_for_vblank(dev, intel_plane->pipe);
3812
820c1980 3813 ilk_update_wm(crtc);
526682e9
PZ		 3814}
3815
3078999f
PB		 3816static void skl_pipe_wm_active_state(uint32_t val,
3817 struct skl_pipe_wm *active,
3818 bool is_transwm,
3819 bool is_cursor,
3820 int i,
3821 int level)
3822{
3823 bool is_enabled = (val & PLANE_WM_EN) != 0;
3824
3825 if (!is_transwm) {
3826 if (!is_cursor) {
3827 active->wm[level].plane_en[i] = is_enabled;
3828 active->wm[level].plane_res_b[i] =
3829 val & PLANE_WM_BLOCKS_MASK;
3830 active->wm[level].plane_res_l[i] =
3831 (val >> PLANE_WM_LINES_SHIFT) &
3832 PLANE_WM_LINES_MASK;
3833 } else {
3834 active->wm[level].cursor_en = is_enabled;
3835 active->wm[level].cursor_res_b =
3836 val & PLANE_WM_BLOCKS_MASK;
3837 active->wm[level].cursor_res_l =
3838 (val >> PLANE_WM_LINES_SHIFT) &
3839 PLANE_WM_LINES_MASK;
3840 }
3841 } else {
3842 if (!is_cursor) {
3843 active->trans_wm.plane_en[i] = is_enabled;
3844 active->trans_wm.plane_res_b[i] =
3845 val & PLANE_WM_BLOCKS_MASK;
3846 active->trans_wm.plane_res_l[i] =
3847 (val >> PLANE_WM_LINES_SHIFT) &
3848 PLANE_WM_LINES_MASK;
3849 } else {
3850 active->trans_wm.cursor_en = is_enabled;
3851 active->trans_wm.cursor_res_b =
3852 val & PLANE_WM_BLOCKS_MASK;
3853 active->trans_wm.cursor_res_l =
3854 (val >> PLANE_WM_LINES_SHIFT) &
3855 PLANE_WM_LINES_MASK;
3856 }
3857 }
3858}
3859
3860static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3861{
3862 struct drm_device *dev = crtc->dev;
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3866 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3867 enum pipe pipe = intel_crtc->pipe;
3868 int level, i, max_level;
3869 uint32_t temp;
3870
3871 max_level = ilk_wm_max_level(dev);
3872
3873 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3874
3875 for (level = 0; level <= max_level; level++) {
3876 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3877 hw->plane[pipe][i][level] =
3878 I915_READ(PLANE_WM(pipe, i, level));
3879 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3880 }
3881
3882 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3883 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3884 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3885
3ef00284 3886 if (!intel_crtc->active)
3078999f
PB		 3887 return;
3888
3889 hw->dirty[pipe] = true;
3890
3891 active->linetime = hw->wm_linetime[pipe];
3892
3893 for (level = 0; level <= max_level; level++) {
3894 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3895 temp = hw->plane[pipe][i][level];
3896 skl_pipe_wm_active_state(temp, active, false,
3897 false, i, level);
3898 }
3899 temp = hw->cursor[pipe][level];
3900 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3901 }
3902
3903 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3904 temp = hw->plane_trans[pipe][i];
3905 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3906 }
3907
3908 temp = hw->cursor_trans[pipe];
3909 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3910}
3911
3912void skl_wm_get_hw_state(struct drm_device *dev)
3913{
a269c583
DL		 3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3916 struct drm_crtc *crtc;
3917
a269c583 3918 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3919 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3920 skl_pipe_wm_get_hw_state(crtc);
3921}
3922
243e6a44
VS		 3923static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3924{
3925 struct drm_device *dev = crtc->dev;
3926 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3927 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3930 enum pipe pipe = intel_crtc->pipe;
3931 static const unsigned int wm0_pipe_reg[] = {
3932 [PIPE_A] = WM0_PIPEA_ILK,
3933 [PIPE_B] = WM0_PIPEB_ILK,
3934 [PIPE_C] = WM0_PIPEC_IVB,
3935 };
3936
3937 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3938 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3939 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3940
3ef00284 3941 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3942
3943 if (active->pipe_enabled) {
243e6a44
VS		 3944 u32 tmp = hw->wm_pipe[pipe];
3945
3946 /*
3947 * For active pipes LP0 watermark is marked as
3948 * enabled, and LP1+ watermaks as disabled since
3949 * we can't really reverse compute them in case
3950 * multiple pipes are active.
3951 */
3952 active->wm[0].enable = true;
3953 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3954 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3955 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3956 active->linetime = hw->wm_linetime[pipe];
3957 } else {
3958 int level, max_level = ilk_wm_max_level(dev);
3959
3960 /*
3961 * For inactive pipes, all watermark levels
3962 * should be marked as enabled but zeroed,
3963 * which is what we'd compute them to.
3964 */
3965 for (level = 0; level <= max_level; level++)
3966 active->wm[level].enable = true;
3967 }
3968}
3969
6eb1a681
VS		 3970#define _FW_WM(value, plane) \
3971 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3972#define _FW_WM_VLV(value, plane) \
3973 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3974
3975static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3976 struct vlv_wm_values *wm)
3977{
3978 enum pipe pipe;
3979 uint32_t tmp;
3980
3981 for_each_pipe(dev_priv, pipe) {
3982 tmp = I915_READ(VLV_DDL(pipe));
3983
3984 wm->ddl[pipe].primary =
3985 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3986 wm->ddl[pipe].cursor =
3987 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3988 wm->ddl[pipe].sprite[0] =
3989 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3990 wm->ddl[pipe].sprite[1] =
3991 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3992 }
3993
3994 tmp = I915_READ(DSPFW1);
3995 wm->sr.plane = _FW_WM(tmp, SR);
3996 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3997 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3998 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3999
4000 tmp = I915_READ(DSPFW2);
4001 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4002 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4003 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4004
4005 tmp = I915_READ(DSPFW3);
4006 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4007
4008 if (IS_CHERRYVIEW(dev_priv)) {
4009 tmp = I915_READ(DSPFW7_CHV);
4010 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4011 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4012
4013 tmp = I915_READ(DSPFW8_CHV);
4014 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4015 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4016
4017 tmp = I915_READ(DSPFW9_CHV);
4018 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4019 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4020
4021 tmp = I915_READ(DSPHOWM);
4022 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4023 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4024 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4025 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4026 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4027 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4028 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4029 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4030 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4031 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4032 } else {
4033 tmp = I915_READ(DSPFW7);
4034 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4035 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4036
4037 tmp = I915_READ(DSPHOWM);
4038 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4039 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4040 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4041 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4042 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4043 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4044 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4045 }
4046}
4047
4048#undef _FW_WM
4049#undef _FW_WM_VLV
4050
4051void vlv_wm_get_hw_state(struct drm_device *dev)
4052{
4053 struct drm_i915_private *dev_priv = to_i915(dev);
4054 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4055 struct intel_plane *plane;
4056 enum pipe pipe;
4057 u32 val;
4058
4059 vlv_read_wm_values(dev_priv, wm);
4060
4061 for_each_intel_plane(dev, plane) {
4062 switch (plane->base.type) {
4063 int sprite;
4064 case DRM_PLANE_TYPE_CURSOR:
4065 plane->wm.fifo_size = 63;
4066 break;
4067 case DRM_PLANE_TYPE_PRIMARY:
4068 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4069 break;
4070 case DRM_PLANE_TYPE_OVERLAY:
4071 sprite = plane->plane;
4072 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4073 break;
4074 }
4075 }
4076
4077 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4078 wm->level = VLV_WM_LEVEL_PM2;
4079
4080 if (IS_CHERRYVIEW(dev_priv)) {
4081 mutex_lock(&dev_priv->rps.hw_lock);
4082
4083 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4084 if (val & DSP_MAXFIFO_PM5_ENABLE)
4085 wm->level = VLV_WM_LEVEL_PM5;
4086
4087 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4088 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4089 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4090
4091 mutex_unlock(&dev_priv->rps.hw_lock);
4092 }
4093
4094 for_each_pipe(dev_priv, pipe)
4095 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4096 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4097 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4098
4099 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4100 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4101}
4102
243e6a44
VS		 4103void ilk_wm_get_hw_state(struct drm_device *dev)
4104{
4105 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4106 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4107 struct drm_crtc *crtc;
4108
70e1e0ec 4109 for_each_crtc(dev, crtc)
243e6a44
VS		 4110 ilk_pipe_wm_get_hw_state(crtc);
4111
4112 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4113 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4114 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4115
4116 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4117 if (INTEL_INFO(dev)->gen >= 7) {
4118 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4119 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4120 }
243e6a44 4121
a42a5719 4122 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4123 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4124 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4125 else if (IS_IVYBRIDGE(dev))
4126 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4127 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4128
4129 hw->enable_fbc_wm =
4130 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4131}
4132
b445e3b0
ED		 4133/**
4134 * intel_update_watermarks - update FIFO watermark values based on current modes
4135 *
4136 * Calculate watermark values for the various WM regs based on current mode
4137 * and plane configuration.
4138 *
4139 * There are several cases to deal with here:
4140 * - normal (i.e. non-self-refresh)
4141 * - self-refresh (SR) mode
4142 * - lines are large relative to FIFO size (buffer can hold up to 2)
4143 * - lines are small relative to FIFO size (buffer can hold more than 2
4144 * lines), so need to account for TLB latency
4145 *
4146 * The normal calculation is:
4147 * watermark = dotclock * bytes per pixel * latency
4148 * where latency is platform & configuration dependent (we assume pessimal
4149 * values here).
4150 *
4151 * The SR calculation is:
4152 * watermark = (trunc(latency/line time)+1) * surface width *
4153 * bytes per pixel
4154 * where
4155 * line time = htotal / dotclock
4156 * surface width = hdisplay for normal plane and 64 for cursor
4157 * and latency is assumed to be high, as above.
4158 *
4159 * The final value programmed to the register should always be rounded up,
4160 * and include an extra 2 entries to account for clock crossings.
4161 *
4162 * We don't use the sprite, so we can ignore that. And on Crestline we have
4163 * to set the non-SR watermarks to 8.
4164 */
46ba614c 4165void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4166{
46ba614c 4167 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4168
4169 if (dev_priv->display.update_wm)
46ba614c 4170 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4171}
4172
adf3d35e
VS		 4173void intel_update_sprite_watermarks(struct drm_plane *plane,
4174 struct drm_crtc *crtc,
ed57cb8a
DL		 4175 uint32_t sprite_width,
4176 uint32_t sprite_height,
4177 int pixel_size,
39db4a4d 4178 bool enabled, bool scaled)
b445e3b0 4179{
adf3d35e 4180 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 4181
4182 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 4183 dev_priv->display.update_sprite_wm(plane, crtc,
4184 sprite_width, sprite_height,
39db4a4d 4185 pixel_size, enabled, scaled);
b445e3b0
ED		 4186}
4187
9270388e
DV		 4188/**
4189 * Lock protecting IPS related data structures
9270388e
DV		 4190 */
4191DEFINE_SPINLOCK(mchdev_lock);
4192
4193/* Global for IPS driver to get at the current i915 device. Protected by
4194 * mchdev_lock. */
4195static struct drm_i915_private *i915_mch_dev;
4196
2b4e57bd
ED		 4197bool ironlake_set_drps(struct drm_device *dev, u8 val)
4198{
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 u16 rgvswctl;
4201
9270388e
DV		 4202 assert_spin_locked(&mchdev_lock);
4203
2b4e57bd
ED		 4204 rgvswctl = I915_READ16(MEMSWCTL);
4205 if (rgvswctl & MEMCTL_CMD_STS) {
4206 DRM_DEBUG("gpu busy, RCS change rejected\n");
4207 return false; /* still busy with another command */
4208 }
4209
4210 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4211 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4212 I915_WRITE16(MEMSWCTL, rgvswctl);
4213 POSTING_READ16(MEMSWCTL);
4214
4215 rgvswctl |= MEMCTL_CMD_STS;
4216 I915_WRITE16(MEMSWCTL, rgvswctl);
4217
4218 return true;
4219}
4220
8090c6b9 4221static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4222{
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 u32 rgvmodectl = I915_READ(MEMMODECTL);
4225 u8 fmax, fmin, fstart, vstart;
4226
9270388e
DV		 4227 spin_lock_irq(&mchdev_lock);
4228
2b4e57bd
ED		 4229 /* Enable temp reporting */
4230 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4231 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4232
4233 /* 100ms RC evaluation intervals */
4234 I915_WRITE(RCUPEI, 100000);
4235 I915_WRITE(RCDNEI, 100000);
4236
4237 /* Set max/min thresholds to 90ms and 80ms respectively */
4238 I915_WRITE(RCBMAXAVG, 90000);
4239 I915_WRITE(RCBMINAVG, 80000);
4240
4241 I915_WRITE(MEMIHYST, 1);
4242
4243 /* Set up min, max, and cur for interrupt handling */
4244 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4245 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4246 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4247 MEMMODE_FSTART_SHIFT;
4248
4249 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4250 PXVFREQ_PX_SHIFT;
4251
20e4d407
DV		 4252 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4253 dev_priv->ips.fstart = fstart;
2b4e57bd 4254
20e4d407
DV		 4255 dev_priv->ips.max_delay = fstart;
4256 dev_priv->ips.min_delay = fmin;
4257 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4258
4259 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4260 fmax, fmin, fstart);
4261
4262 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4263
4264 /*
4265 * Interrupts will be enabled in ironlake_irq_postinstall
4266 */
4267
4268 I915_WRITE(VIDSTART, vstart);
4269 POSTING_READ(VIDSTART);
4270
4271 rgvmodectl |= MEMMODE_SWMODE_EN;
4272 I915_WRITE(MEMMODECTL, rgvmodectl);
4273
9270388e 4274 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4275 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4276 mdelay(1);
2b4e57bd
ED		 4277
4278 ironlake_set_drps(dev, fstart);
4279
20e4d407 4280 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 4281 I915_READ(0x112e0);
20e4d407
DV		 4282 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4283 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 4284 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4285
4286 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4287}
4288
8090c6b9 4289static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4290{
4291 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4292 u16 rgvswctl;
4293
4294 spin_lock_irq(&mchdev_lock);
4295
4296 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4297
4298 /* Ack interrupts, disable EFC interrupt */
4299 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4300 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4301 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4302 I915_WRITE(DEIIR, DE_PCU_EVENT);
4303 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4304
4305 /* Go back to the starting frequency */
20e4d407 4306 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4307 mdelay(1);
2b4e57bd
ED		 4308 rgvswctl |= MEMCTL_CMD_STS;
4309 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4310 mdelay(1);
2b4e57bd 4311
9270388e 4312 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4313}
4314
acbe9475
DV		 4315/* There's a funny hw issue where the hw returns all 0 when reading from
4316 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4317 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4318 * all limits and the gpu stuck at whatever frequency it is at atm).
4319 */
74ef1173 4320static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4321{
7b9e0ae6 4322 u32 limits;
2b4e57bd 4323
20b46e59
DV		 4324 /* Only set the down limit when we've reached the lowest level to avoid
4325 * getting more interrupts, otherwise leave this clear. This prevents a
4326 * race in the hw when coming out of rc6: There's a tiny window where
4327 * the hw runs at the minimal clock before selecting the desired
4328 * frequency, if the down threshold expires in that window we will not
4329 * receive a down interrupt. */
74ef1173
AG		 4330 if (IS_GEN9(dev_priv->dev)) {
4331 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4332 if (val <= dev_priv->rps.min_freq_softlimit)
4333 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4334 } else {
4335 limits = dev_priv->rps.max_freq_softlimit << 24;
4336 if (val <= dev_priv->rps.min_freq_softlimit)
4337 limits |= dev_priv->rps.min_freq_softlimit << 16;
4338 }
20b46e59
DV		 4339
4340 return limits;
4341}
4342
dd75fdc8
CW		 4343static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4344{
4345 int new_power;
8a586437
AG		 4346 u32 threshold_up = 0, threshold_down = 0; /* in % */
4347 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4348
4349 new_power = dev_priv->rps.power;
4350 switch (dev_priv->rps.power) {
4351 case LOW_POWER:
b39fb297 4352 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4353 new_power = BETWEEN;
4354 break;
4355
4356 case BETWEEN:
b39fb297 4357 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4358 new_power = LOW_POWER;
b39fb297 4359 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4360 new_power = HIGH_POWER;
4361 break;
4362
4363 case HIGH_POWER:
b39fb297 4364 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4365 new_power = BETWEEN;
4366 break;
4367 }
4368 /* Max/min bins are special */
aed242ff 4369 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4370 new_power = LOW_POWER;
aed242ff 4371 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4372 new_power = HIGH_POWER;
4373 if (new_power == dev_priv->rps.power)
4374 return;
4375
4376 /* Note the units here are not exactly 1us, but 1280ns. */
4377 switch (new_power) {
4378 case LOW_POWER:
4379 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4380 ei_up = 16000;
4381 threshold_up = 95;
dd75fdc8
CW		 4382
4383 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4384 ei_down = 32000;
4385 threshold_down = 85;
dd75fdc8
CW		 4386 break;
4387
4388 case BETWEEN:
4389 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4390 ei_up = 13000;
4391 threshold_up = 90;
dd75fdc8
CW		 4392
4393 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4394 ei_down = 32000;
4395 threshold_down = 75;
dd75fdc8
CW		 4396 break;
4397
4398 case HIGH_POWER:
4399 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4400 ei_up = 10000;
4401 threshold_up = 85;
dd75fdc8
CW		 4402
4403 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4404 ei_down = 32000;
4405 threshold_down = 60;
dd75fdc8
CW		 4406 break;
4407 }
4408
8a586437
AG		 4409 I915_WRITE(GEN6_RP_UP_EI,
4410 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4411 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4412 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4413
4414 I915_WRITE(GEN6_RP_DOWN_EI,
4415 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4416 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4417 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4418
4419 I915_WRITE(GEN6_RP_CONTROL,
4420 GEN6_RP_MEDIA_TURBO |
4421 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4422 GEN6_RP_MEDIA_IS_GFX |
4423 GEN6_RP_ENABLE |
4424 GEN6_RP_UP_BUSY_AVG |
4425 GEN6_RP_DOWN_IDLE_AVG);
4426
dd75fdc8 4427 dev_priv->rps.power = new_power;
8fb55197
CW		 4428 dev_priv->rps.up_threshold = threshold_up;
4429 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4430 dev_priv->rps.last_adj = 0;
4431}
4432
2876ce73
CW		 4433static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4434{
4435 u32 mask = 0;
4436
4437 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4438 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4439 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4440 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4441
7b3c29f6
CW		 4442 mask &= dev_priv->pm_rps_events;
4443
59d02a1f 4444 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4445}
4446
b8a5ff8d
JM		 4447/* gen6_set_rps is called to update the frequency request, but should also be
4448 * called when the range (min_delay and max_delay) is modified so that we can
4449 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4450static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4451{
4452 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4453
4fc688ce 4454 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4455 WARN_ON(val > dev_priv->rps.max_freq);
4456 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4457
eb64cad1
CW		 4458 /* min/max delay may still have been modified so be sure to
4459 * write the limits value.
4460 */
4461 if (val != dev_priv->rps.cur_freq) {
4462 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4463
5704195c
AG		 4464 if (IS_GEN9(dev))
4465 I915_WRITE(GEN6_RPNSWREQ,
4466 GEN9_FREQUENCY(val));
4467 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4468 I915_WRITE(GEN6_RPNSWREQ,
4469 HSW_FREQUENCY(val));
4470 else
4471 I915_WRITE(GEN6_RPNSWREQ,
4472 GEN6_FREQUENCY(val) |
4473 GEN6_OFFSET(0) |
4474 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4475 }
7b9e0ae6 4476
7b9e0ae6
CW		 4477 /* Make sure we continue to get interrupts
4478 * until we hit the minimum or maximum frequencies.
4479 */
74ef1173 4480 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4481 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4482
d5570a72
BW		 4483 POSTING_READ(GEN6_RPNSWREQ);
4484
b39fb297 4485 dev_priv->rps.cur_freq = val;
be2cde9a 4486 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4487}
4488
ffe02b40
VS		 4489static void valleyview_set_rps(struct drm_device *dev, u8 val)
4490{
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4492
4493 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4494 WARN_ON(val > dev_priv->rps.max_freq);
4495 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4496
4497 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4498 "Odd GPU freq value\n"))
4499 val &= ~1;
4500
cd25dd5b
D		 4501 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4502
8fb55197 4503 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4504 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4505 if (!IS_CHERRYVIEW(dev_priv))
4506 gen6_set_rps_thresholds(dev_priv, val);
4507 }
ffe02b40 4508
ffe02b40
VS		 4509 dev_priv->rps.cur_freq = val;
4510 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4511}
4512
a7f6e231 4513/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4514 *
4515 * * If Gfx is Idle, then
a7f6e231
D		 4516 * 1. Forcewake Media well.
4517 * 2. Request idle freq.
4518 * 3. Release Forcewake of Media well.
76c3552f
D		 4519*/
4520static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4521{
aed242ff 4522 u32 val = dev_priv->rps.idle_freq;
5549d25f 4523
aed242ff 4524 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4525 return;
4526
a7f6e231
D		 4527 /* Wake up the media well, as that takes a lot less
4528 * power than the Render well. */
4529 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4530 valleyview_set_rps(dev_priv->dev, val);
4531 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4532}
4533
43cf3bf0
CW		 4534void gen6_rps_busy(struct drm_i915_private *dev_priv)
4535{
4536 mutex_lock(&dev_priv->rps.hw_lock);
4537 if (dev_priv->rps.enabled) {
4538 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4539 gen6_rps_reset_ei(dev_priv);
4540 I915_WRITE(GEN6_PMINTRMSK,
4541 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4542 }
4543 mutex_unlock(&dev_priv->rps.hw_lock);
4544}
4545
b29c19b6
CW		 4546void gen6_rps_idle(struct drm_i915_private *dev_priv)
4547{
691bb717
DL		 4548 struct drm_device *dev = dev_priv->dev;
4549
b29c19b6 4550 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4551 if (dev_priv->rps.enabled) {
21a11fff 4552 if (IS_VALLEYVIEW(dev))
76c3552f 4553 vlv_set_rps_idle(dev_priv);
7526ed79 4554 else
aed242ff 4555 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4556 dev_priv->rps.last_adj = 0;
43cf3bf0 4557 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4558 }
8d3afd7d 4559 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4560
8d3afd7d 4561 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4562 while (!list_empty(&dev_priv->rps.clients))
4563 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4564 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4565}
4566
1854d5ca 4567void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4568 struct intel_rps_client *rps,
4569 unsigned long submitted)
b29c19b6 4570{
8d3afd7d
CW		 4571 /* This is intentionally racy! We peek at the state here, then
4572 * validate inside the RPS worker.
4573 */
4574 if (!(dev_priv->mm.busy &&
4575 dev_priv->rps.enabled &&
4576 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4577 return;
43cf3bf0 4578
e61b9958
CW		 4579 /* Force a RPS boost (and don't count it against the client) if
4580 * the GPU is severely congested.
4581 */
d0bc54f2 4582 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4583 rps = NULL;
4584
8d3afd7d
CW		 4585 spin_lock(&dev_priv->rps.client_lock);
4586 if (rps == NULL || list_empty(&rps->link)) {
4587 spin_lock_irq(&dev_priv->irq_lock);
4588 if (dev_priv->rps.interrupts_enabled) {
4589 dev_priv->rps.client_boost = true;
4590 queue_work(dev_priv->wq, &dev_priv->rps.work);
4591 }
4592 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4593
2e1b8730
CW		 4594 if (rps != NULL) {
4595 list_add(&rps->link, &dev_priv->rps.clients);
4596 rps->boosts++;
1854d5ca
CW		 4597 } else
4598 dev_priv->rps.boosts++;
c0951f0c 4599 }
8d3afd7d 4600 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4601}
4602
ffe02b40 4603void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4604{
ffe02b40
VS		 4605 if (IS_VALLEYVIEW(dev))
4606 valleyview_set_rps(dev, val);
4607 else
4608 gen6_set_rps(dev, val);
0a073b84
JB		 4609}
4610
20e49366
ZW		 4611static void gen9_disable_rps(struct drm_device *dev)
4612{
4613 struct drm_i915_private *dev_priv = dev->dev_private;
4614
4615 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4616 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4617}
4618
44fc7d5c 4619static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4620{
4621 struct drm_i915_private *dev_priv = dev->dev_private;
4622
4623 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4624 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4625}
4626
38807746
D		 4627static void cherryview_disable_rps(struct drm_device *dev)
4628{
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630
4631 I915_WRITE(GEN6_RC_CONTROL, 0);
4632}
4633
44fc7d5c
DV		 4634static void valleyview_disable_rps(struct drm_device *dev)
4635{
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
98a2e5f9
D		 4638 /* we're doing forcewake before Disabling RC6,
4639 * This what the BIOS expects when going into suspend */
59bad947 4640 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4641
44fc7d5c 4642 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4643
59bad947 4644 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4645}
4646
dc39fff7
BW		 4647static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4648{
91ca689a
ID		 4649 if (IS_VALLEYVIEW(dev)) {
4650 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4651 mode = GEN6_RC_CTL_RC6_ENABLE;
4652 else
4653 mode = 0;
4654 }
58abf1da
RV		 4655 if (HAS_RC6p(dev))
4656 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4657 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4658 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4659 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4660
4661 else
4662 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4663 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4664}
4665
e6069ca8 4666static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4667{
e7d66d89
DV		 4668 /* No RC6 before Ironlake and code is gone for ilk. */
4669 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4670 return 0;
4671
456470eb 4672 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4673 if (enable_rc6 >= 0) {
4674 int mask;
4675
58abf1da 4676 if (HAS_RC6p(dev))
e6069ca8
ID		 4677 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4678 INTEL_RC6pp_ENABLE;
4679 else
4680 mask = INTEL_RC6_ENABLE;
4681
4682 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4683 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4684 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4685
4686 return enable_rc6 & mask;
4687 }
2b4e57bd 4688
8bade1ad 4689 if (IS_IVYBRIDGE(dev))
cca84a1f 4690 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4691
4692 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4693}
4694
e6069ca8
ID		 4695int intel_enable_rc6(const struct drm_device *dev)
4696{
4697 return i915.enable_rc6;
4698}
4699
93ee2920 4700static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4701{
93ee2920
TR		 4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 uint32_t rp_state_cap;
4704 u32 ddcc_status = 0;
4705 int ret;
4706
3280e8b0
BW		 4707 /* All of these values are in units of 50MHz */
4708 dev_priv->rps.cur_freq = 0;
93ee2920 4709 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4710 if (IS_BROXTON(dev)) {
4711 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4712 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4713 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4714 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4715 } else {
4716 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4717 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4718 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4719 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4720 }
4721
3280e8b0
BW		 4722 /* hw_max = RP0 until we check for overclocking */
4723 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4724
93ee2920 4725 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4726 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4727 ret = sandybridge_pcode_read(dev_priv,
4728 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4729 &ddcc_status);
4730 if (0 == ret)
4731 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4732 clamp_t(u8,
4733 ((ddcc_status >> 8) & 0xff),
4734 dev_priv->rps.min_freq,
4735 dev_priv->rps.max_freq);
93ee2920
TR		 4736 }
4737
c5e0688c
AG		 4738 if (IS_SKYLAKE(dev)) {
4739 /* Store the frequency values in 16.66 MHZ units, which is
4740 the natural hardware unit for SKL */
4741 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4742 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4743 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4744 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4745 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4746 }
4747
aed242ff
CW		 4748 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4749
3280e8b0
BW		 4750 /* Preserve min/max settings in case of re-init */
4751 if (dev_priv->rps.max_freq_softlimit == 0)
4752 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4753
93ee2920
TR		 4754 if (dev_priv->rps.min_freq_softlimit == 0) {
4755 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4756 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4757 max_t(int, dev_priv->rps.efficient_freq,
4758 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4759 else
4760 dev_priv->rps.min_freq_softlimit =
4761 dev_priv->rps.min_freq;
4762 }
3280e8b0
BW		 4763}
4764
b6fef0ef 4765/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4766static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4767{
4768 struct drm_i915_private *dev_priv = dev->dev_private;
4769
4770 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4771
ba1c554c
DL		 4772 gen6_init_rps_frequencies(dev);
4773
0beb059a
AG		 4774 /* Program defaults and thresholds for RPS*/
4775 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4776 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4777
4778 /* 1 second timeout*/
4779 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4780 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4781
b6fef0ef 4782 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4783
0beb059a
AG		 4784 /* Leaning on the below call to gen6_set_rps to program/setup the
4785 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4786 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4787 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4788 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4789
4790 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4791}
4792
4793static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4794{
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 struct intel_engine_cs *ring;
4797 uint32_t rc6_mask = 0;
4798 int unused;
4799
4800 /* 1a: Software RC state - RC0 */
4801 I915_WRITE(GEN6_RC_STATE, 0);
4802
4803 /* 1b: Get forcewake during program sequence. Although the driver
4804 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4805 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4806
4807 /* 2a: Disable RC states. */
4808 I915_WRITE(GEN6_RC_CONTROL, 0);
4809
4810 /* 2b: Program RC6 thresholds.*/
4811 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4812 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4813 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4814 for_each_ring(ring, dev_priv, unused)
4815 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4816 I915_WRITE(GEN6_RC_SLEEP, 0);
4817 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4818
38c23527
ZW		 4819 /* 2c: Program Coarse Power Gating Policies. */
4820 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4821 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4822
20e49366
ZW		 4823 /* 3a: Enable RC6 */
4824 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4825 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4826 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4827 "on" : "off");
4828 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4829 GEN6_RC_CTL_EI_MODE(1) |
4830 rc6_mask);
4831
cb07bae0
SK		 4832 /*
4833 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4834 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4835 */
a4104c55 4836 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
cb07bae0 4837 GEN9_MEDIA_PG_ENABLE : 0);
a4104c55 4838
38c23527 4839
59bad947 4840 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4841
4842}
4843
6edee7f3
BW		 4844static void gen8_enable_rps(struct drm_device *dev)
4845{
4846 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4847 struct intel_engine_cs *ring;
93ee2920 4848 uint32_t rc6_mask = 0;
6edee7f3
BW		 4849 int unused;
4850
4851 /* 1a: Software RC state - RC0 */
4852 I915_WRITE(GEN6_RC_STATE, 0);
4853
4854 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4855 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4856 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4857
4858 /* 2a: Disable RC states. */
4859 I915_WRITE(GEN6_RC_CONTROL, 0);
4860
93ee2920
TR		 4861 /* Initialize rps frequencies */
4862 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4863
4864 /* 2b: Program RC6 thresholds.*/
4865 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4866 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4867 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4868 for_each_ring(ring, dev_priv, unused)
4869 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4870 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4871 if (IS_BROADWELL(dev))
4872 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4873 else
4874 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4875
4876 /* 3: Enable RC6 */
4877 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4878 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4879 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4880 if (IS_BROADWELL(dev))
4881 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4882 GEN7_RC_CTL_TO_MODE |
4883 rc6_mask);
4884 else
4885 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4886 GEN6_RC_CTL_EI_MODE(1) |
4887 rc6_mask);
6edee7f3
BW		 4888
4889 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4890 I915_WRITE(GEN6_RPNSWREQ,
4891 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4892 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4893 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4894 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4895 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4896
4897 /* Docs recommend 900MHz, and 300 MHz respectively */
4898 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4899 dev_priv->rps.max_freq_softlimit << 24 |
4900 dev_priv->rps.min_freq_softlimit << 16);
4901
4902 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4903 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4904 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4905 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4906
4907 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4908
4909 /* 5: Enable RPS */
7526ed79
DV		 4910 I915_WRITE(GEN6_RP_CONTROL,
4911 GEN6_RP_MEDIA_TURBO |
4912 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4913 GEN6_RP_MEDIA_IS_GFX |
4914 GEN6_RP_ENABLE |
4915 GEN6_RP_UP_BUSY_AVG |
4916 GEN6_RP_DOWN_IDLE_AVG);
4917
4918 /* 6: Ring frequency + overclocking (our driver does this later */
4919
c7f3153a 4920 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4921 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4922
59bad947 4923 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4924}
4925
79f5b2c7 4926static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4927{
79f5b2c7 4928 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4929 struct intel_engine_cs *ring;
d060c169 4930 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4931 u32 gtfifodbg;
2b4e57bd 4932 int rc6_mode;
42c0526c 4933 int i, ret;
2b4e57bd 4934
4fc688ce 4935 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4936
2b4e57bd
ED		 4937 /* Here begins a magic sequence of register writes to enable
4938 * auto-downclocking.
4939 *
4940 * Perhaps there might be some value in exposing these to
4941 * userspace...
4942 */
4943 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4944
4945 /* Clear the DBG now so we don't confuse earlier errors */
4946 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4947 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4948 I915_WRITE(GTFIFODBG, gtfifodbg);
4949 }
4950
59bad947 4951 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4952
93ee2920
TR		 4953 /* Initialize rps frequencies */
4954 gen6_init_rps_frequencies(dev);
dd0a1aa1 4955
2b4e57bd
ED		 4956 /* disable the counters and set deterministic thresholds */
4957 I915_WRITE(GEN6_RC_CONTROL, 0);
4958
4959 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4960 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4961 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4962 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4963 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4964
b4519513
CW		 4965 for_each_ring(ring, dev_priv, i)
4966 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4967
4968 I915_WRITE(GEN6_RC_SLEEP, 0);
4969 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4970 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4971 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4972 else
4973 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4974 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4975 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4976
5a7dc92a 4977 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4978 rc6_mode = intel_enable_rc6(dev_priv->dev);
4979 if (rc6_mode & INTEL_RC6_ENABLE)
4980 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4981
5a7dc92a
ED		 4982 /* We don't use those on Haswell */
4983 if (!IS_HASWELL(dev)) {
4984 if (rc6_mode & INTEL_RC6p_ENABLE)
4985 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4986
5a7dc92a
ED		 4987 if (rc6_mode & INTEL_RC6pp_ENABLE)
4988 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4989 }
2b4e57bd 4990
dc39fff7 4991 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4992
4993 I915_WRITE(GEN6_RC_CONTROL,
4994 rc6_mask |
4995 GEN6_RC_CTL_EI_MODE(1) |
4996 GEN6_RC_CTL_HW_ENABLE);
4997
dd75fdc8
CW		 4998 /* Power down if completely idle for over 50ms */
4999 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5000 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5001
42c0526c 5002 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5003 if (ret)
42c0526c 5004 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5005
5006 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5007 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5008 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5009 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5010 (pcu_mbox & 0xff) * 50);
b39fb297 5011 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5012 }
5013
dd75fdc8 5014 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5015 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5016
31643d54
BW		 5017 rc6vids = 0;
5018 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5019 if (IS_GEN6(dev) && ret) {
5020 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5021 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5022 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5023 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5024 rc6vids &= 0xffff00;
5025 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5026 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5027 if (ret)
5028 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5029 }
5030
59bad947 5031 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5032}
5033
c2bc2fc5 5034static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5035{
79f5b2c7 5036 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5037 int min_freq = 15;
3ebecd07
CW		 5038 unsigned int gpu_freq;
5039 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5040 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5041 int scaling_factor = 180;
eda79642 5042 struct cpufreq_policy *policy;
2b4e57bd 5043
4fc688ce 5044 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5045
eda79642
BW		 5046 policy = cpufreq_cpu_get(0);
5047 if (policy) {
5048 max_ia_freq = policy->cpuinfo.max_freq;
5049 cpufreq_cpu_put(policy);
5050 } else {
5051 /*
5052 * Default to measured freq if none found, PCU will ensure we
5053 * don't go over
5054 */
2b4e57bd 5055 max_ia_freq = tsc_khz;
eda79642 5056 }
2b4e57bd
ED		 5057
5058 /* Convert from kHz to MHz */
5059 max_ia_freq /= 1000;
5060
153b4b95 5061 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5062 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5063 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5064
4c8c7743
AG		 5065 if (IS_SKYLAKE(dev)) {
5066 /* Convert GT frequency to 50 HZ units */
5067 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5068 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5069 } else {
5070 min_gpu_freq = dev_priv->rps.min_freq;
5071 max_gpu_freq = dev_priv->rps.max_freq;
5072 }
5073
2b4e57bd
ED		 5074 /*
5075 * For each potential GPU frequency, load a ring frequency we'd like
5076 * to use for memory access. We do this by specifying the IA frequency
5077 * the PCU should use as a reference to determine the ring frequency.
5078 */
4c8c7743
AG		 5079 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5080 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5081 unsigned int ia_freq = 0, ring_freq = 0;
5082
4c8c7743
AG		 5083 if (IS_SKYLAKE(dev)) {
5084 /*
5085 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5086 * No floor required for ring frequency on SKL.
5087 */
5088 ring_freq = gpu_freq;
5089 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5090 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5091 ring_freq = max(min_ring_freq, gpu_freq);
5092 } else if (IS_HASWELL(dev)) {
f6aca45c 5093 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5094 ring_freq = max(min_ring_freq, ring_freq);
5095 /* leave ia_freq as the default, chosen by cpufreq */
5096 } else {
5097 /* On older processors, there is no separate ring
5098 * clock domain, so in order to boost the bandwidth
5099 * of the ring, we need to upclock the CPU (ia_freq).
5100 *
5101 * For GPU frequencies less than 750MHz,
5102 * just use the lowest ring freq.
5103 */
5104 if (gpu_freq < min_freq)
5105 ia_freq = 800;
5106 else
5107 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5108 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5109 }
2b4e57bd 5110
42c0526c
BW		 5111 sandybridge_pcode_write(dev_priv,
5112 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5113 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5114 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5115 gpu_freq);
2b4e57bd 5116 }
2b4e57bd
ED		 5117}
5118
c2bc2fc5
ID		 5119void gen6_update_ring_freq(struct drm_device *dev)
5120{
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122
97d3308a 5123 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5124 return;
5125
5126 mutex_lock(&dev_priv->rps.hw_lock);
5127 __gen6_update_ring_freq(dev);
5128 mutex_unlock(&dev_priv->rps.hw_lock);
5129}
5130
03af2045 5131static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5132{
095acd5f 5133 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5134 u32 val, rp0;
5135
095acd5f
D		 5136 if (dev->pdev->revision >= 0x20) {
5137 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5138
095acd5f
D		 5139 switch (INTEL_INFO(dev)->eu_total) {
5140 case 8:
5141 /* (2 * 4) config */
5142 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5143 break;
5144 case 12:
5145 /* (2 * 6) config */
5146 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5147 break;
5148 case 16:
5149 /* (2 * 8) config */
5150 default:
5151 /* Setting (2 * 8) Min RP0 for any other combination */
5152 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5153 break;
5154 }
5155 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5156 } else {
5157 /* For pre-production hardware */
5158 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5159 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5160 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5161 }
2b6b3a09
D		 5162 return rp0;
5163}
5164
5165static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5166{
5167 u32 val, rpe;
5168
5169 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5170 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5171
5172 return rpe;
5173}
5174
7707df4a
D		 5175static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5176{
095acd5f 5177 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5178 u32 val, rp1;
5179
095acd5f
D		 5180 if (dev->pdev->revision >= 0x20) {
5181 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5182 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5183 } else {
5184 /* For pre-production hardware */
5185 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5186 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5187 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5188 }
7707df4a
D		 5189 return rp1;
5190}
5191
f8f2b001
D		 5192static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5193{
5194 u32 val, rp1;
5195
5196 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5197
5198 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5199
5200 return rp1;
5201}
5202
03af2045 5203static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5204{
5205 u32 val, rp0;
5206
64936258 5207 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5208
5209 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5210 /* Clamp to max */
5211 rp0 = min_t(u32, rp0, 0xea);
5212
5213 return rp0;
5214}
5215
5216static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5217{
5218 u32 val, rpe;
5219
64936258 5220 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5221 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5222 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5223 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5224
5225 return rpe;
5226}
5227
03af2045 5228static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5229{
64936258 5230 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5231}
5232
ae48434c
ID		 5233/* Check that the pctx buffer wasn't move under us. */
5234static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5235{
5236 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5237
5238 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5239 dev_priv->vlv_pctx->stolen->start);
5240}
5241
38807746
D		 5242
5243/* Check that the pcbr address is not empty. */
5244static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5245{
5246 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5247
5248 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5249}
5250
5251static void cherryview_setup_pctx(struct drm_device *dev)
5252{
5253 struct drm_i915_private *dev_priv = dev->dev_private;
5254 unsigned long pctx_paddr, paddr;
5255 struct i915_gtt *gtt = &dev_priv->gtt;
5256 u32 pcbr;
5257 int pctx_size = 32*1024;
5258
5259 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5260
5261 pcbr = I915_READ(VLV_PCBR);
5262 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5263 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5264 paddr = (dev_priv->mm.stolen_base +
5265 (gtt->stolen_size - pctx_size));
5266
5267 pctx_paddr = (paddr & (~4095));
5268 I915_WRITE(VLV_PCBR, pctx_paddr);
5269 }
ce611ef8
VS		 5270
5271 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5272}
5273
c9cddffc
JB		 5274static void valleyview_setup_pctx(struct drm_device *dev)
5275{
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277 struct drm_i915_gem_object *pctx;
5278 unsigned long pctx_paddr;
5279 u32 pcbr;
5280 int pctx_size = 24*1024;
5281
17b0c1f7
ID		 5282 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5283
c9cddffc
JB		 5284 pcbr = I915_READ(VLV_PCBR);
5285 if (pcbr) {
5286 /* BIOS set it up already, grab the pre-alloc'd space */
5287 int pcbr_offset;
5288
5289 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5290 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5291 pcbr_offset,
190d6cd5 5292 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5293 pctx_size);
5294 goto out;
5295 }
5296
ce611ef8
VS		 5297 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5298
c9cddffc
JB		 5299 /*
5300 * From the Gunit register HAS:
5301 * The Gfx driver is expected to program this register and ensure
5302 * proper allocation within Gfx stolen memory. For example, this
5303 * register should be programmed such than the PCBR range does not
5304 * overlap with other ranges, such as the frame buffer, protected
5305 * memory, or any other relevant ranges.
5306 */
5307 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5308 if (!pctx) {
5309 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5310 return;
5311 }
5312
5313 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5314 I915_WRITE(VLV_PCBR, pctx_paddr);
5315
5316out:
ce611ef8 5317 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5318 dev_priv->vlv_pctx = pctx;
5319}
5320
ae48434c
ID		 5321static void valleyview_cleanup_pctx(struct drm_device *dev)
5322{
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324
5325 if (WARN_ON(!dev_priv->vlv_pctx))
5326 return;
5327
5328 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5329 dev_priv->vlv_pctx = NULL;
5330}
5331
4e80519e
ID		 5332static void valleyview_init_gt_powersave(struct drm_device *dev)
5333{
5334 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5335 u32 val;
4e80519e
ID		 5336
5337 valleyview_setup_pctx(dev);
5338
5339 mutex_lock(&dev_priv->rps.hw_lock);
5340
2bb25c17
VS		 5341 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5342 switch ((val >> 6) & 3) {
5343 case 0:
5344 case 1:
5345 dev_priv->mem_freq = 800;
5346 break;
5347 case 2:
5348 dev_priv->mem_freq = 1066;
5349 break;
5350 case 3:
5351 dev_priv->mem_freq = 1333;
5352 break;
5353 }
80b83b62 5354 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5355
4e80519e
ID		 5356 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5357 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5358 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5359 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5360 dev_priv->rps.max_freq);
5361
5362 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5363 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5364 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5365 dev_priv->rps.efficient_freq);
5366
f8f2b001
D		 5367 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5368 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5369 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5370 dev_priv->rps.rp1_freq);
5371
4e80519e
ID		 5372 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5373 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5374 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5375 dev_priv->rps.min_freq);
5376
aed242ff
CW		 5377 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5378
4e80519e
ID		 5379 /* Preserve min/max settings in case of re-init */
5380 if (dev_priv->rps.max_freq_softlimit == 0)
5381 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5382
5383 if (dev_priv->rps.min_freq_softlimit == 0)
5384 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5385
5386 mutex_unlock(&dev_priv->rps.hw_lock);
5387}
5388
38807746
D		 5389static void cherryview_init_gt_powersave(struct drm_device *dev)
5390{
2b6b3a09 5391 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5392 u32 val;
2b6b3a09 5393
38807746 5394 cherryview_setup_pctx(dev);
2b6b3a09
D		 5395
5396 mutex_lock(&dev_priv->rps.hw_lock);
5397
a580516d 5398 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5399 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5400 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5401
2bb25c17
VS		 5402 switch ((val >> 2) & 0x7) {
5403 case 0:
5404 case 1:
5405 dev_priv->rps.cz_freq = 200;
5406 dev_priv->mem_freq = 1600;
5407 break;
5408 case 2:
5409 dev_priv->rps.cz_freq = 267;
5410 dev_priv->mem_freq = 1600;
5411 break;
5412 case 3:
5413 dev_priv->rps.cz_freq = 333;
5414 dev_priv->mem_freq = 2000;
5415 break;
5416 case 4:
5417 dev_priv->rps.cz_freq = 320;
5418 dev_priv->mem_freq = 1600;
5419 break;
5420 case 5:
5421 dev_priv->rps.cz_freq = 400;
5422 dev_priv->mem_freq = 1600;
5423 break;
5424 }
80b83b62 5425 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5426
2b6b3a09
D		 5427 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5428 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5429 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5430 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5431 dev_priv->rps.max_freq);
5432
5433 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5434 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5435 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5436 dev_priv->rps.efficient_freq);
5437
7707df4a
D		 5438 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5439 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5440 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5441 dev_priv->rps.rp1_freq);
5442
5b7c91b7
D		 5443 /* PUnit validated range is only [RPe, RP0] */
5444 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5445 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5446 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5447 dev_priv->rps.min_freq);
5448
1c14762d
VS		 5449 WARN_ONCE((dev_priv->rps.max_freq |
5450 dev_priv->rps.efficient_freq |
5451 dev_priv->rps.rp1_freq |
5452 dev_priv->rps.min_freq) & 1,
5453 "Odd GPU freq values\n");
5454
aed242ff
CW		 5455 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5456
2b6b3a09
D		 5457 /* Preserve min/max settings in case of re-init */
5458 if (dev_priv->rps.max_freq_softlimit == 0)
5459 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5460
5461 if (dev_priv->rps.min_freq_softlimit == 0)
5462 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5463
5464 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5465}
5466
4e80519e
ID		 5467static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5468{
5469 valleyview_cleanup_pctx(dev);
5470}
5471
38807746
D		 5472static void cherryview_enable_rps(struct drm_device *dev)
5473{
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475 struct intel_engine_cs *ring;
2b6b3a09 5476 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5477 int i;
5478
5479 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5480
5481 gtfifodbg = I915_READ(GTFIFODBG);
5482 if (gtfifodbg) {
5483 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5484 gtfifodbg);
5485 I915_WRITE(GTFIFODBG, gtfifodbg);
5486 }
5487
5488 cherryview_check_pctx(dev_priv);
5489
5490 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5491 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5492 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5493
160614a2
VS		 5494 /* Disable RC states. */
5495 I915_WRITE(GEN6_RC_CONTROL, 0);
5496
38807746
D		 5497 /* 2a: Program RC6 thresholds.*/
5498 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5499 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5500 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5501
5502 for_each_ring(ring, dev_priv, i)
5503 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5504 I915_WRITE(GEN6_RC_SLEEP, 0);
5505
f4f71c7d
D		 5506 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5507 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5508
5509 /* allows RC6 residency counter to work */
5510 I915_WRITE(VLV_COUNTER_CONTROL,
5511 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5512 VLV_MEDIA_RC6_COUNT_EN |
5513 VLV_RENDER_RC6_COUNT_EN));
5514
5515 /* For now we assume BIOS is allocating and populating the PCBR */
5516 pcbr = I915_READ(VLV_PCBR);
5517
38807746
D		 5518 /* 3: Enable RC6 */
5519 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5520 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5521 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5522
5523 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5524
2b6b3a09 5525 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5526 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5527 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5528 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5529 I915_WRITE(GEN6_RP_UP_EI, 66000);
5530 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5531
5532 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5533
5534 /* 5: Enable RPS */
5535 I915_WRITE(GEN6_RP_CONTROL,
5536 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5537 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5538 GEN6_RP_ENABLE |
5539 GEN6_RP_UP_BUSY_AVG |
5540 GEN6_RP_DOWN_IDLE_AVG);
5541
3ef62342
D		 5542 /* Setting Fixed Bias */
5543 val = VLV_OVERRIDE_EN |
5544 VLV_SOC_TDP_EN |
5545 CHV_BIAS_CPU_50_SOC_50;
5546 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5547
2b6b3a09
D		 5548 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5549
8d40c3ae
VS		 5550 /* RPS code assumes GPLL is used */
5551 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5552
742f491d 5553 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5554 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5555
5556 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5557 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5558 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5559 dev_priv->rps.cur_freq);
5560
5561 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5562 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5563 dev_priv->rps.efficient_freq);
5564
5565 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5566
59bad947 5567 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5568}
5569
0a073b84
JB		 5570static void valleyview_enable_rps(struct drm_device *dev)
5571{
5572 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5573 struct intel_engine_cs *ring;
2a5913a8 5574 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5575 int i;
5576
5577 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5578
ae48434c
ID		 5579 valleyview_check_pctx(dev_priv);
5580
0a073b84 5581 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5582 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5583 gtfifodbg);
0a073b84
JB		 5584 I915_WRITE(GTFIFODBG, gtfifodbg);
5585 }
5586
c8d9a590 5587 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5588 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5589
160614a2
VS		 5590 /* Disable RC states. */
5591 I915_WRITE(GEN6_RC_CONTROL, 0);
5592
cad725fe 5593 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5594 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5595 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5596 I915_WRITE(GEN6_RP_UP_EI, 66000);
5597 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5598
5599 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5600
5601 I915_WRITE(GEN6_RP_CONTROL,
5602 GEN6_RP_MEDIA_TURBO |
5603 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5604 GEN6_RP_MEDIA_IS_GFX |
5605 GEN6_RP_ENABLE |
5606 GEN6_RP_UP_BUSY_AVG |
5607 GEN6_RP_DOWN_IDLE_CONT);
5608
5609 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5610 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5611 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5612
5613 for_each_ring(ring, dev_priv, i)
5614 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5615
2f0aa304 5616 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5617
5618 /* allows RC6 residency counter to work */
49798eb2 5619 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5620 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5621 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5622 VLV_MEDIA_RC6_COUNT_EN |
5623 VLV_RENDER_RC6_COUNT_EN));
31685c25 5624
a2b23fe0 5625 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5626 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5627
5628 intel_print_rc6_info(dev, rc6_mode);
5629
a2b23fe0 5630 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5631
3ef62342
D		 5632 /* Setting Fixed Bias */
5633 val = VLV_OVERRIDE_EN |
5634 VLV_SOC_TDP_EN |
5635 VLV_BIAS_CPU_125_SOC_875;
5636 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5637
64936258 5638 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5639
8d40c3ae
VS		 5640 /* RPS code assumes GPLL is used */
5641 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5642
742f491d 5643 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5644 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5645
b39fb297 5646 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5647 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5648 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5649 dev_priv->rps.cur_freq);
0a073b84 5650
73008b98 5651 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5652 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5653 dev_priv->rps.efficient_freq);
0a073b84 5654
b39fb297 5655 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5656
59bad947 5657 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5658}
5659
dde18883
ED		 5660static unsigned long intel_pxfreq(u32 vidfreq)
5661{
5662 unsigned long freq;
5663 int div = (vidfreq & 0x3f0000) >> 16;
5664 int post = (vidfreq & 0x3000) >> 12;
5665 int pre = (vidfreq & 0x7);
5666
5667 if (!pre)
5668 return 0;
5669
5670 freq = ((div * 133333) / ((1<<post) * pre));
5671
5672 return freq;
5673}
5674
eb48eb00
DV		 5675static const struct cparams {
5676 u16 i;
5677 u16 t;
5678 u16 m;
5679 u16 c;
5680} cparams[] = {
5681 { 1, 1333, 301, 28664 },
5682 { 1, 1066, 294, 24460 },
5683 { 1, 800, 294, 25192 },
5684 { 0, 1333, 276, 27605 },
5685 { 0, 1066, 276, 27605 },
5686 { 0, 800, 231, 23784 },
5687};
5688
f531dcb2 5689static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5690{
5691 u64 total_count, diff, ret;
5692 u32 count1, count2, count3, m = 0, c = 0;
5693 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5694 int i;
5695
02d71956
DV		 5696 assert_spin_locked(&mchdev_lock);
5697
20e4d407 5698 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5699
5700 /* Prevent division-by-zero if we are asking too fast.
5701 * Also, we don't get interesting results if we are polling
5702 * faster than once in 10ms, so just return the saved value
5703 * in such cases.
5704 */
5705 if (diff1 <= 10)
20e4d407 5706 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5707
5708 count1 = I915_READ(DMIEC);
5709 count2 = I915_READ(DDREC);
5710 count3 = I915_READ(CSIEC);
5711
5712 total_count = count1 + count2 + count3;
5713
5714 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5715 if (total_count < dev_priv->ips.last_count1) {
5716 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5717 diff += total_count;
5718 } else {
20e4d407 5719 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5720 }
5721
5722 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5723 if (cparams[i].i == dev_priv->ips.c_m &&
5724 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5725 m = cparams[i].m;
5726 c = cparams[i].c;
5727 break;
5728 }
5729 }
5730
5731 diff = div_u64(diff, diff1);
5732 ret = ((m * diff) + c);
5733 ret = div_u64(ret, 10);
5734
20e4d407
DV		 5735 dev_priv->ips.last_count1 = total_count;
5736 dev_priv->ips.last_time1 = now;
eb48eb00 5737
20e4d407 5738 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5739
5740 return ret;
5741}
5742
f531dcb2
CW		 5743unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5744{
3d13ef2e 5745 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5746 unsigned long val;
5747
3d13ef2e 5748 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5749 return 0;
5750
5751 spin_lock_irq(&mchdev_lock);
5752
5753 val = __i915_chipset_val(dev_priv);
5754
5755 spin_unlock_irq(&mchdev_lock);
5756
5757 return val;
5758}
5759
eb48eb00
DV		 5760unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5761{
5762 unsigned long m, x, b;
5763 u32 tsfs;
5764
5765 tsfs = I915_READ(TSFS);
5766
5767 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5768 x = I915_READ8(TR1);
5769
5770 b = tsfs & TSFS_INTR_MASK;
5771
5772 return ((m * x) / 127) - b;
5773}
5774
d972d6ee
MK		 5775static int _pxvid_to_vd(u8 pxvid)
5776{
5777 if (pxvid == 0)
5778 return 0;
5779
5780 if (pxvid >= 8 && pxvid < 31)
5781 pxvid = 31;
5782
5783 return (pxvid + 2) * 125;
5784}
5785
5786static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5787{
3d13ef2e 5788 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5789 const int vd = _pxvid_to_vd(pxvid);
5790 const int vm = vd - 1125;
5791
3d13ef2e 5792 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5793 return vm > 0 ? vm : 0;
5794
5795 return vd;
eb48eb00
DV		 5796}
5797
02d71956 5798static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5799{
5ed0bdf2 5800 u64 now, diff, diffms;
eb48eb00
DV		 5801 u32 count;
5802
02d71956 5803 assert_spin_locked(&mchdev_lock);
eb48eb00 5804
5ed0bdf2
TG		 5805 now = ktime_get_raw_ns();
5806 diffms = now - dev_priv->ips.last_time2;
5807 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5808
5809 /* Don't divide by 0 */
eb48eb00
DV		 5810 if (!diffms)
5811 return;
5812
5813 count = I915_READ(GFXEC);
5814
20e4d407
DV		 5815 if (count < dev_priv->ips.last_count2) {
5816 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5817 diff += count;
5818 } else {
20e4d407 5819 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5820 }
5821
20e4d407
DV		 5822 dev_priv->ips.last_count2 = count;
5823 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5824
5825 /* More magic constants... */
5826 diff = diff * 1181;
5827 diff = div_u64(diff, diffms * 10);
20e4d407 5828 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5829}
5830
02d71956
DV		 5831void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5832{
3d13ef2e
DL		 5833 struct drm_device *dev = dev_priv->dev;
5834
5835 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5836 return;
5837
9270388e 5838 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5839
5840 __i915_update_gfx_val(dev_priv);
5841
9270388e 5842 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5843}
5844
f531dcb2 5845static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5846{
5847 unsigned long t, corr, state1, corr2, state2;
5848 u32 pxvid, ext_v;
5849
02d71956
DV		 5850 assert_spin_locked(&mchdev_lock);
5851
b39fb297 5852 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5853 pxvid = (pxvid >> 24) & 0x7f;
5854 ext_v = pvid_to_extvid(dev_priv, pxvid);
5855
5856 state1 = ext_v;
5857
5858 t = i915_mch_val(dev_priv);
5859
5860 /* Revel in the empirically derived constants */
5861
5862 /* Correction factor in 1/100000 units */
5863 if (t > 80)
5864 corr = ((t * 2349) + 135940);
5865 else if (t >= 50)
5866 corr = ((t * 964) + 29317);
5867 else /* < 50 */
5868 corr = ((t * 301) + 1004);
5869
5870 corr = corr * ((150142 * state1) / 10000 - 78642);
5871 corr /= 100000;
20e4d407 5872 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5873
5874 state2 = (corr2 * state1) / 10000;
5875 state2 /= 100; /* convert to mW */
5876
02d71956 5877 __i915_update_gfx_val(dev_priv);
eb48eb00 5878
20e4d407 5879 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5880}
5881
f531dcb2
CW		 5882unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5883{
3d13ef2e 5884 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5885 unsigned long val;
5886
3d13ef2e 5887 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5888 return 0;
5889
5890 spin_lock_irq(&mchdev_lock);
5891
5892 val = __i915_gfx_val(dev_priv);
5893
5894 spin_unlock_irq(&mchdev_lock);
5895
5896 return val;
5897}
5898
eb48eb00
DV		 5899/**
5900 * i915_read_mch_val - return value for IPS use
5901 *
5902 * Calculate and return a value for the IPS driver to use when deciding whether
5903 * we have thermal and power headroom to increase CPU or GPU power budget.
5904 */
5905unsigned long i915_read_mch_val(void)
5906{
5907 struct drm_i915_private *dev_priv;
5908 unsigned long chipset_val, graphics_val, ret = 0;
5909
9270388e 5910 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5911 if (!i915_mch_dev)
5912 goto out_unlock;
5913 dev_priv = i915_mch_dev;
5914
f531dcb2
CW		 5915 chipset_val = __i915_chipset_val(dev_priv);
5916 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5917
5918 ret = chipset_val + graphics_val;
5919
5920out_unlock:
9270388e 5921 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5922
5923 return ret;
5924}
5925EXPORT_SYMBOL_GPL(i915_read_mch_val);
5926
5927/**
5928 * i915_gpu_raise - raise GPU frequency limit
5929 *
5930 * Raise the limit; IPS indicates we have thermal headroom.
5931 */
5932bool i915_gpu_raise(void)
5933{
5934 struct drm_i915_private *dev_priv;
5935 bool ret = true;
5936
9270388e 5937 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5938 if (!i915_mch_dev) {
5939 ret = false;
5940 goto out_unlock;
5941 }
5942 dev_priv = i915_mch_dev;
5943
20e4d407
DV		 5944 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5945 dev_priv->ips.max_delay--;
eb48eb00
DV		 5946
5947out_unlock:
9270388e 5948 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5949
5950 return ret;
5951}
5952EXPORT_SYMBOL_GPL(i915_gpu_raise);
5953
5954/**
5955 * i915_gpu_lower - lower GPU frequency limit
5956 *
5957 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5958 * frequency maximum.
5959 */
5960bool i915_gpu_lower(void)
5961{
5962 struct drm_i915_private *dev_priv;
5963 bool ret = true;
5964
9270388e 5965 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5966 if (!i915_mch_dev) {
5967 ret = false;
5968 goto out_unlock;
5969 }
5970 dev_priv = i915_mch_dev;
5971
20e4d407
DV		 5972 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5973 dev_priv->ips.max_delay++;
eb48eb00
DV		 5974
5975out_unlock:
9270388e 5976 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5977
5978 return ret;
5979}
5980EXPORT_SYMBOL_GPL(i915_gpu_lower);
5981
5982/**
5983 * i915_gpu_busy - indicate GPU business to IPS
5984 *
5985 * Tell the IPS driver whether or not the GPU is busy.
5986 */
5987bool i915_gpu_busy(void)
5988{
5989 struct drm_i915_private *dev_priv;
a4872ba6 5990 struct intel_engine_cs *ring;
eb48eb00 5991 bool ret = false;
f047e395 5992 int i;
eb48eb00 5993
9270388e 5994 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5995 if (!i915_mch_dev)
5996 goto out_unlock;
5997 dev_priv = i915_mch_dev;
5998
f047e395
CW		 5999 for_each_ring(ring, dev_priv, i)
6000 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 6001
6002out_unlock:
9270388e 6003 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6004
6005 return ret;
6006}
6007EXPORT_SYMBOL_GPL(i915_gpu_busy);
6008
6009/**
6010 * i915_gpu_turbo_disable - disable graphics turbo
6011 *
6012 * Disable graphics turbo by resetting the max frequency and setting the
6013 * current frequency to the default.
6014 */
6015bool i915_gpu_turbo_disable(void)
6016{
6017 struct drm_i915_private *dev_priv;
6018 bool ret = true;
6019
9270388e 6020 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6021 if (!i915_mch_dev) {
6022 ret = false;
6023 goto out_unlock;
6024 }
6025 dev_priv = i915_mch_dev;
6026
20e4d407 6027 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6028
20e4d407 6029 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6030 ret = false;
6031
6032out_unlock:
9270388e 6033 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6034
6035 return ret;
6036}
6037EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6038
6039/**
6040 * Tells the intel_ips driver that the i915 driver is now loaded, if
6041 * IPS got loaded first.
6042 *
6043 * This awkward dance is so that neither module has to depend on the
6044 * other in order for IPS to do the appropriate communication of
6045 * GPU turbo limits to i915.
6046 */
6047static void
6048ips_ping_for_i915_load(void)
6049{
6050 void (*link)(void);
6051
6052 link = symbol_get(ips_link_to_i915_driver);
6053 if (link) {
6054 link();
6055 symbol_put(ips_link_to_i915_driver);
6056 }
6057}
6058
6059void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6060{
02d71956
DV		 6061 /* We only register the i915 ips part with intel-ips once everything is
6062 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6063 spin_lock_irq(&mchdev_lock);
eb48eb00 6064 i915_mch_dev = dev_priv;
9270388e 6065 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6066
6067 ips_ping_for_i915_load();
6068}
6069
6070void intel_gpu_ips_teardown(void)
6071{
9270388e 6072 spin_lock_irq(&mchdev_lock);
eb48eb00 6073 i915_mch_dev = NULL;
9270388e 6074 spin_unlock_irq(&mchdev_lock);
eb48eb00 6075}
76c3552f 6076
8090c6b9 6077static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6078{
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080 u32 lcfuse;
6081 u8 pxw[16];
6082 int i;
6083
6084 /* Disable to program */
6085 I915_WRITE(ECR, 0);
6086 POSTING_READ(ECR);
6087
6088 /* Program energy weights for various events */
6089 I915_WRITE(SDEW, 0x15040d00);
6090 I915_WRITE(CSIEW0, 0x007f0000);
6091 I915_WRITE(CSIEW1, 0x1e220004);
6092 I915_WRITE(CSIEW2, 0x04000004);
6093
6094 for (i = 0; i < 5; i++)
6095 I915_WRITE(PEW + (i * 4), 0);
6096 for (i = 0; i < 3; i++)
6097 I915_WRITE(DEW + (i * 4), 0);
6098
6099 /* Program P-state weights to account for frequency power adjustment */
6100 for (i = 0; i < 16; i++) {
6101 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6102 unsigned long freq = intel_pxfreq(pxvidfreq);
6103 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6104 PXVFREQ_PX_SHIFT;
6105 unsigned long val;
6106
6107 val = vid * vid;
6108 val *= (freq / 1000);
6109 val *= 255;
6110 val /= (127*127*900);
6111 if (val > 0xff)
6112 DRM_ERROR("bad pxval: %ld\n", val);
6113 pxw[i] = val;
6114 }
6115 /* Render standby states get 0 weight */
6116 pxw[14] = 0;
6117 pxw[15] = 0;
6118
6119 for (i = 0; i < 4; i++) {
6120 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6121 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6122 I915_WRITE(PXW + (i * 4), val);
6123 }
6124
6125 /* Adjust magic regs to magic values (more experimental results) */
6126 I915_WRITE(OGW0, 0);
6127 I915_WRITE(OGW1, 0);
6128 I915_WRITE(EG0, 0x00007f00);
6129 I915_WRITE(EG1, 0x0000000e);
6130 I915_WRITE(EG2, 0x000e0000);
6131 I915_WRITE(EG3, 0x68000300);
6132 I915_WRITE(EG4, 0x42000000);
6133 I915_WRITE(EG5, 0x00140031);
6134 I915_WRITE(EG6, 0);
6135 I915_WRITE(EG7, 0);
6136
6137 for (i = 0; i < 8; i++)
6138 I915_WRITE(PXWL + (i * 4), 0);
6139
6140 /* Enable PMON + select events */
6141 I915_WRITE(ECR, 0x80000019);
6142
6143 lcfuse = I915_READ(LCFUSE02);
6144
20e4d407 6145 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6146}
6147
ae48434c
ID		 6148void intel_init_gt_powersave(struct drm_device *dev)
6149{
e6069ca8
ID		 6150 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6151
38807746
D		 6152 if (IS_CHERRYVIEW(dev))
6153 cherryview_init_gt_powersave(dev);
6154 else if (IS_VALLEYVIEW(dev))
4e80519e 6155 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6156}
6157
6158void intel_cleanup_gt_powersave(struct drm_device *dev)
6159{
38807746
D		 6160 if (IS_CHERRYVIEW(dev))
6161 return;
6162 else if (IS_VALLEYVIEW(dev))
4e80519e 6163 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6164}
6165
dbea3cea
ID		 6166static void gen6_suspend_rps(struct drm_device *dev)
6167{
6168 struct drm_i915_private *dev_priv = dev->dev_private;
6169
6170 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6171
4c2a8897 6172 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6173}
6174
156c7ca0
JB		 6175/**
6176 * intel_suspend_gt_powersave - suspend PM work and helper threads
6177 * @dev: drm device
6178 *
6179 * We don't want to disable RC6 or other features here, we just want
6180 * to make sure any work we've queued has finished and won't bother
6181 * us while we're suspended.
6182 */
6183void intel_suspend_gt_powersave(struct drm_device *dev)
6184{
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186
d4d70aa5
ID		 6187 if (INTEL_INFO(dev)->gen < 6)
6188 return;
6189
dbea3cea 6190 gen6_suspend_rps(dev);
b47adc17
D		 6191
6192 /* Force GPU to min freq during suspend */
6193 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6194}
6195
8090c6b9
DV		 6196void intel_disable_gt_powersave(struct drm_device *dev)
6197{
1a01ab3b
JB		 6198 struct drm_i915_private *dev_priv = dev->dev_private;
6199
930ebb46 6200 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6201 ironlake_disable_drps(dev);
38807746 6202 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6203 intel_suspend_gt_powersave(dev);
e494837a 6204
4fc688ce 6205 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6206 if (INTEL_INFO(dev)->gen >= 9)
6207 gen9_disable_rps(dev);
6208 else if (IS_CHERRYVIEW(dev))
38807746
D		 6209 cherryview_disable_rps(dev);
6210 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6211 valleyview_disable_rps(dev);
6212 else
6213 gen6_disable_rps(dev);
e534770a 6214
c0951f0c 6215 dev_priv->rps.enabled = false;
4fc688ce 6216 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6217 }
8090c6b9
DV		 6218}
6219
1a01ab3b
JB		 6220static void intel_gen6_powersave_work(struct work_struct *work)
6221{
6222 struct drm_i915_private *dev_priv =
6223 container_of(work, struct drm_i915_private,
6224 rps.delayed_resume_work.work);
6225 struct drm_device *dev = dev_priv->dev;
6226
4fc688ce 6227 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6228
4c2a8897 6229 gen6_reset_rps_interrupts(dev);
3cc134e3 6230
38807746
D		 6231 if (IS_CHERRYVIEW(dev)) {
6232 cherryview_enable_rps(dev);
6233 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6234 valleyview_enable_rps(dev);
20e49366 6235 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6236 gen9_enable_rc6(dev);
20e49366 6237 gen9_enable_rps(dev);
cc017fb4
AG		 6238 if (IS_SKYLAKE(dev))
6239 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6240 } else if (IS_BROADWELL(dev)) {
6241 gen8_enable_rps(dev);
c2bc2fc5 6242 __gen6_update_ring_freq(dev);
0a073b84
JB		 6243 } else {
6244 gen6_enable_rps(dev);
c2bc2fc5 6245 __gen6_update_ring_freq(dev);
0a073b84 6246 }
aed242ff
CW		 6247
6248 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6249 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6250
6251 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6252 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6253
c0951f0c 6254 dev_priv->rps.enabled = true;
3cc134e3 6255
4c2a8897 6256 gen6_enable_rps_interrupts(dev);
3cc134e3 6257
4fc688ce 6258 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6259
6260 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6261}
6262
8090c6b9
DV		 6263void intel_enable_gt_powersave(struct drm_device *dev)
6264{
1a01ab3b
JB		 6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266
f61018b1
YZ		 6267 /* Powersaving is controlled by the host when inside a VM */
6268 if (intel_vgpu_active(dev))
6269 return;
6270
8090c6b9 6271 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6272 mutex_lock(&dev->struct_mutex);
8090c6b9 6273 ironlake_enable_drps(dev);
8090c6b9 6274 intel_init_emon(dev);
dc1d0136 6275 mutex_unlock(&dev->struct_mutex);
38807746 6276 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6277 /*
6278 * PCU communication is slow and this doesn't need to be
6279 * done at any specific time, so do this out of our fast path
6280 * to make resume and init faster.
c6df39b5
ID		 6281 *
6282 * We depend on the HW RC6 power context save/restore
6283 * mechanism when entering D3 through runtime PM suspend. So
6284 * disable RPM until RPS/RC6 is properly setup. We can only
6285 * get here via the driver load/system resume/runtime resume
6286 * paths, so the _noresume version is enough (and in case of
6287 * runtime resume it's necessary).
1a01ab3b 6288 */
c6df39b5
ID		 6289 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6290 round_jiffies_up_relative(HZ)))
6291 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6292 }
6293}
6294
c6df39b5
ID		 6295void intel_reset_gt_powersave(struct drm_device *dev)
6296{
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298
dbea3cea
ID		 6299 if (INTEL_INFO(dev)->gen < 6)
6300 return;
6301
6302 gen6_suspend_rps(dev);
c6df39b5 6303 dev_priv->rps.enabled = false;
c6df39b5
ID		 6304}
6305
3107bd48
DV		 6306static void ibx_init_clock_gating(struct drm_device *dev)
6307{
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6309
6310 /*
6311 * On Ibex Peak and Cougar Point, we need to disable clock
6312 * gating for the panel power sequencer or it will fail to
6313 * start up when no ports are active.
6314 */
6315 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6316}
6317
0e088b8f
VS		 6318static void g4x_disable_trickle_feed(struct drm_device *dev)
6319{
6320 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6321 enum pipe pipe;
0e088b8f 6322
055e393f 6323 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6324 I915_WRITE(DSPCNTR(pipe),
6325 I915_READ(DSPCNTR(pipe)) |
6326 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6327
6328 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6329 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6330 }
6331}
6332
017636cc
VS		 6333static void ilk_init_lp_watermarks(struct drm_device *dev)
6334{
6335 struct drm_i915_private *dev_priv = dev->dev_private;
6336
6337 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6338 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6339 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6340
6341 /*
6342 * Don't touch WM1S_LP_EN here.
6343 * Doing so could cause underruns.
6344 */
6345}
6346
1fa61106 6347static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6348{
6349 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6350 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6351
f1e8fa56
DL		 6352 /*
6353 * Required for FBC
6354 * WaFbcDisableDpfcClockGating:ilk
6355 */
4d47e4f5
DL		 6356 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6357 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6358 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6359
6360 I915_WRITE(PCH_3DCGDIS0,
6361 MARIUNIT_CLOCK_GATE_DISABLE |
6362 SVSMUNIT_CLOCK_GATE_DISABLE);
6363 I915_WRITE(PCH_3DCGDIS1,
6364 VFMUNIT_CLOCK_GATE_DISABLE);
6365
6f1d69b0
ED		 6366 /*
6367 * According to the spec the following bits should be set in
6368 * order to enable memory self-refresh
6369 * The bit 22/21 of 0x42004
6370 * The bit 5 of 0x42020
6371 * The bit 15 of 0x45000
6372 */
6373 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6374 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6375 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6376 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6377 I915_WRITE(DISP_ARB_CTL,
6378 (I915_READ(DISP_ARB_CTL) |
6379 DISP_FBC_WM_DIS));
017636cc
VS		 6380
6381 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6382
6383 /*
6384 * Based on the document from hardware guys the following bits
6385 * should be set unconditionally in order to enable FBC.
6386 * The bit 22 of 0x42000
6387 * The bit 22 of 0x42004
6388 * The bit 7,8,9 of 0x42020.
6389 */
6390 if (IS_IRONLAKE_M(dev)) {
4bb35334 6391 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6392 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6393 I915_READ(ILK_DISPLAY_CHICKEN1) |
6394 ILK_FBCQ_DIS);
6395 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6396 I915_READ(ILK_DISPLAY_CHICKEN2) |
6397 ILK_DPARB_GATE);
6f1d69b0
ED		 6398 }
6399
4d47e4f5
DL		 6400 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6401
6f1d69b0
ED		 6402 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6403 I915_READ(ILK_DISPLAY_CHICKEN2) |
6404 ILK_ELPIN_409_SELECT);
6405 I915_WRITE(_3D_CHICKEN2,
6406 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6407 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6408
ecdb4eb7 6409 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6410 I915_WRITE(CACHE_MODE_0,
6411 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6412
4e04632e
AG		 6413 /* WaDisable_RenderCache_OperationalFlush:ilk */
6414 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6415
0e088b8f 6416 g4x_disable_trickle_feed(dev);
bdad2b2f 6417
3107bd48
DV		 6418 ibx_init_clock_gating(dev);
6419}
6420
6421static void cpt_init_clock_gating(struct drm_device *dev)
6422{
6423 struct drm_i915_private *dev_priv = dev->dev_private;
6424 int pipe;
3f704fa2 6425 uint32_t val;
3107bd48
DV		 6426
6427 /*
6428 * On Ibex Peak and Cougar Point, we need to disable clock
6429 * gating for the panel power sequencer or it will fail to
6430 * start up when no ports are active.
6431 */
cd664078
JB		 6432 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6433 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6434 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6435 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6436 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6437 /* The below fixes the weird display corruption, a few pixels shifted
6438 * downward, on (only) LVDS of some HP laptops with IVY.
6439 */
055e393f 6440 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6441 val = I915_READ(TRANS_CHICKEN2(pipe));
6442 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6443 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6444 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6445 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6446 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6447 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6448 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6449 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6450 }
3107bd48 6451 /* WADP0ClockGatingDisable */
055e393f 6452 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6453 I915_WRITE(TRANS_CHICKEN1(pipe),
6454 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6455 }
6f1d69b0
ED		 6456}
6457
1d7aaa0c
DV		 6458static void gen6_check_mch_setup(struct drm_device *dev)
6459{
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 uint32_t tmp;
6462
6463 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6464 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6465 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6466 tmp);
1d7aaa0c
DV		 6467}
6468
1fa61106 6469static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6470{
6471 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6472 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6473
231e54f6 6474 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6475
6476 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6477 I915_READ(ILK_DISPLAY_CHICKEN2) |
6478 ILK_ELPIN_409_SELECT);
6479
ecdb4eb7 6480 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6481 I915_WRITE(_3D_CHICKEN,
6482 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6483
4e04632e
AG		 6484 /* WaDisable_RenderCache_OperationalFlush:snb */
6485 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6486
8d85d272
VS		 6487 /*
6488 * BSpec recoomends 8x4 when MSAA is used,
6489 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6490 *
6491 * Note that PS/WM thread counts depend on the WIZ hashing
6492 * disable bit, which we don't touch here, but it's good
6493 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6494 */
6495 I915_WRITE(GEN6_GT_MODE,
98533251 6496 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6497
017636cc 6498 ilk_init_lp_watermarks(dev);
6f1d69b0 6499
6f1d69b0 6500 I915_WRITE(CACHE_MODE_0,
50743298 6501 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6502
6503 I915_WRITE(GEN6_UCGCTL1,
6504 I915_READ(GEN6_UCGCTL1) |
6505 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6506 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6507
6508 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6509 * gating disable must be set. Failure to set it results in
6510 * flickering pixels due to Z write ordering failures after
6511 * some amount of runtime in the Mesa "fire" demo, and Unigine
6512 * Sanctuary and Tropics, and apparently anything else with
6513 * alpha test or pixel discard.
6514 *
6515 * According to the spec, bit 11 (RCCUNIT) must also be set,
6516 * but we didn't debug actual testcases to find it out.
0f846f81 6517 *
ef59318c
VS		 6518 * WaDisableRCCUnitClockGating:snb
6519 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6520 */
6521 I915_WRITE(GEN6_UCGCTL2,
6522 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6523 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6524
5eb146dd 6525 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6526 I915_WRITE(_3D_CHICKEN3,
6527 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6528
e927ecde
VS		 6529 /*
6530 * Bspec says:
6531 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6532 * 3DSTATE_SF number of SF output attributes is more than 16."
6533 */
6534 I915_WRITE(_3D_CHICKEN3,
6535 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6536
6f1d69b0
ED		 6537 /*
6538 * According to the spec the following bits should be
6539 * set in order to enable memory self-refresh and fbc:
6540 * The bit21 and bit22 of 0x42000
6541 * The bit21 and bit22 of 0x42004
6542 * The bit5 and bit7 of 0x42020
6543 * The bit14 of 0x70180
6544 * The bit14 of 0x71180
4bb35334
DL		 6545 *
6546 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6547 */
6548 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6549 I915_READ(ILK_DISPLAY_CHICKEN1) |
6550 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6551 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6552 I915_READ(ILK_DISPLAY_CHICKEN2) |
6553 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6554 I915_WRITE(ILK_DSPCLK_GATE_D,
6555 I915_READ(ILK_DSPCLK_GATE_D) |
6556 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6557 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6558
0e088b8f 6559 g4x_disable_trickle_feed(dev);
f8f2ac9a 6560
3107bd48 6561 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6562
6563 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6564}
6565
6566static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6567{
6568 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6569
3aad9059 6570 /*
46680e0a 6571 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6572 *
6573 * This actually overrides the dispatch
6574 * mode for all thread types.
6575 */
6f1d69b0
ED		 6576 reg &= ~GEN7_FF_SCHED_MASK;
6577 reg |= GEN7_FF_TS_SCHED_HW;
6578 reg |= GEN7_FF_VS_SCHED_HW;
6579 reg |= GEN7_FF_DS_SCHED_HW;
6580
6581 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6582}
6583
17a303ec
PZ		 6584static void lpt_init_clock_gating(struct drm_device *dev)
6585{
6586 struct drm_i915_private *dev_priv = dev->dev_private;
6587
6588 /*
6589 * TODO: this bit should only be enabled when really needed, then
6590 * disabled when not needed anymore in order to save power.
6591 */
c2699524 6592 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6593 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6594 I915_READ(SOUTH_DSPCLK_GATE_D) |
6595 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6596
6597 /* WADPOClockGatingDisable:hsw */
6598 I915_WRITE(_TRANSA_CHICKEN1,
6599 I915_READ(_TRANSA_CHICKEN1) |
6600 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6601}
6602
7d708ee4
ID		 6603static void lpt_suspend_hw(struct drm_device *dev)
6604{
6605 struct drm_i915_private *dev_priv = dev->dev_private;
6606
c2699524 6607 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6608 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6609
6610 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6611 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6612 }
6613}
6614
47c2bd97 6615static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6616{
6617 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6618 enum pipe pipe;
4d487cff 6619 uint32_t misccpctl;
1020a5c2 6620
7ad0dbab 6621 ilk_init_lp_watermarks(dev);
50ed5fbd 6622
ab57fff1 6623 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6624 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6625
ab57fff1 6626 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6627 I915_WRITE(CHICKEN_PAR1_1,
6628 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6629
ab57fff1 6630 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6631 for_each_pipe(dev_priv, pipe) {
07d27e20 6632 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6633 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6634 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6635 }
63801f21 6636
ab57fff1
BW		 6637 /* WaVSRefCountFullforceMissDisable:bdw */
6638 /* WaDSRefCountFullforceMissDisable:bdw */
6639 I915_WRITE(GEN7_FF_THREAD_MODE,
6640 I915_READ(GEN7_FF_THREAD_MODE) &
6641 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6642
295e8bb7
VS		 6643 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6644 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6645
6646 /* WaDisableSDEUnitClockGating:bdw */
6647 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6648 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6649
4d487cff
VS		 6650 /*
6651 * WaProgramL3SqcReg1Default:bdw
6652 * WaTempDisableDOPClkGating:bdw
6653 */
6654 misccpctl = I915_READ(GEN7_MISCCPCTL);
6655 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6656 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6657 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6658
6d50b065
VS		 6659 /*
6660 * WaGttCachingOffByDefault:bdw
6661 * GTT cache may not work with big pages, so if those
6662 * are ever enabled GTT cache may need to be disabled.
6663 */
6664 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6665
89d6b2b8 6666 lpt_init_clock_gating(dev);
1020a5c2
BW		 6667}
6668
cad2a2d7
ED		 6669static void haswell_init_clock_gating(struct drm_device *dev)
6670{
6671 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6672
017636cc 6673 ilk_init_lp_watermarks(dev);
cad2a2d7 6674
f3fc4884
FJ		 6675 /* L3 caching of data atomics doesn't work -- disable it. */
6676 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6677 I915_WRITE(HSW_ROW_CHICKEN3,
6678 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6679
ecdb4eb7 6680 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6681 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6682 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6683 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6684
e36ea7ff
VS		 6685 /* WaVSRefCountFullforceMissDisable:hsw */
6686 I915_WRITE(GEN7_FF_THREAD_MODE,
6687 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6688
4e04632e
AG		 6689 /* WaDisable_RenderCache_OperationalFlush:hsw */
6690 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6691
fe27c606
CW		 6692 /* enable HiZ Raw Stall Optimization */
6693 I915_WRITE(CACHE_MODE_0_GEN7,
6694 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6695
ecdb4eb7 6696 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6697 I915_WRITE(CACHE_MODE_1,
6698 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6699
a12c4967
VS		 6700 /*
6701 * BSpec recommends 8x4 when MSAA is used,
6702 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6703 *
6704 * Note that PS/WM thread counts depend on the WIZ hashing
6705 * disable bit, which we don't touch here, but it's good
6706 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6707 */
6708 I915_WRITE(GEN7_GT_MODE,
98533251 6709 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6710
94411593
KG		 6711 /* WaSampleCChickenBitEnable:hsw */
6712 I915_WRITE(HALF_SLICE_CHICKEN3,
6713 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6714
ecdb4eb7 6715 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6716 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6717
90a88643
PZ		 6718 /* WaRsPkgCStateDisplayPMReq:hsw */
6719 I915_WRITE(CHICKEN_PAR1_1,
6720 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6721
17a303ec 6722 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6723}
6724
1fa61106 6725static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6726{
6727 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6728 uint32_t snpcr;
6f1d69b0 6729
017636cc 6730 ilk_init_lp_watermarks(dev);
6f1d69b0 6731
231e54f6 6732 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6733
ecdb4eb7 6734 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6735 I915_WRITE(_3D_CHICKEN3,
6736 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6737
ecdb4eb7 6738 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6739 I915_WRITE(IVB_CHICKEN3,
6740 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6741 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6742
ecdb4eb7 6743 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6744 if (IS_IVB_GT1(dev))
6745 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6746 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6747
4e04632e
AG		 6748 /* WaDisable_RenderCache_OperationalFlush:ivb */
6749 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6750
ecdb4eb7 6751 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6752 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6753 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6754
ecdb4eb7 6755 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6756 I915_WRITE(GEN7_L3CNTLREG1,
6757 GEN7_WA_FOR_GEN7_L3_CONTROL);
6758 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6759 GEN7_WA_L3_CHICKEN_MODE);
6760 if (IS_IVB_GT1(dev))
6761 I915_WRITE(GEN7_ROW_CHICKEN2,
6762 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6763 else {
6764 /* must write both registers */
6765 I915_WRITE(GEN7_ROW_CHICKEN2,
6766 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6767 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6768 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6769 }
6f1d69b0 6770
ecdb4eb7 6771 /* WaForceL3Serialization:ivb */
61939d97
JB		 6772 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6773 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6774
1b80a19a 6775 /*
0f846f81 6776 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6777 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6778 */
6779 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6780 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6781
ecdb4eb7 6782 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6783 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6784 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6785 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6786
0e088b8f 6787 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6788
6789 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6790
22721343
CW		 6791 if (0) { /* causes HiZ corruption on ivb:gt1 */
6792 /* enable HiZ Raw Stall Optimization */
6793 I915_WRITE(CACHE_MODE_0_GEN7,
6794 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6795 }
116f2b6d 6796
ecdb4eb7 6797 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6798 I915_WRITE(CACHE_MODE_1,
6799 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6800
a607c1a4
VS		 6801 /*
6802 * BSpec recommends 8x4 when MSAA is used,
6803 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6804 *
6805 * Note that PS/WM thread counts depend on the WIZ hashing
6806 * disable bit, which we don't touch here, but it's good
6807 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6808 */
6809 I915_WRITE(GEN7_GT_MODE,
98533251 6810 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6811
20848223
BW		 6812 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6813 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6814 snpcr |= GEN6_MBC_SNPCR_MED;
6815 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6816
ab5c608b
BW		 6817 if (!HAS_PCH_NOP(dev))
6818 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6819
6820 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6821}
6822
c6beb13e
VS		 6823static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6824{
6825 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6826
6827 /*
6828 * Disable trickle feed and enable pnd deadline calculation
6829 */
6830 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6831 I915_WRITE(CBR1_VLV, 0);
6832}
6833
1fa61106 6834static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6835{
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6837
c6beb13e 6838 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6839
ecdb4eb7 6840 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6841 I915_WRITE(_3D_CHICKEN3,
6842 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6843
ecdb4eb7 6844 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6845 I915_WRITE(IVB_CHICKEN3,
6846 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6847 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6848
fad7d36e 6849 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6850 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6851 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6852 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6853 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6854
4e04632e
AG		 6855 /* WaDisable_RenderCache_OperationalFlush:vlv */
6856 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6857
ecdb4eb7 6858 /* WaForceL3Serialization:vlv */
61939d97
JB		 6859 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6860 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6861
ecdb4eb7 6862 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6863 I915_WRITE(GEN7_ROW_CHICKEN2,
6864 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6865
ecdb4eb7 6866 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6867 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6868 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6869 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6870
46680e0a
VS		 6871 gen7_setup_fixed_func_scheduler(dev_priv);
6872
3c0edaeb 6873 /*
0f846f81 6874 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6875 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6876 */
6877 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6878 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6879
c98f5062
AG		 6880 /* WaDisableL3Bank2xClockGate:vlv
6881 * Disabling L3 clock gating- MMIO 940c[25] = 1
6882 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6883 I915_WRITE(GEN7_UCGCTL4,
6884 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6885
afd58e79
VS		 6886 /*
6887 * BSpec says this must be set, even though
6888 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6889 */
6b26c86d
DV		 6890 I915_WRITE(CACHE_MODE_1,
6891 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6892
da2518f9
VS		 6893 /*
6894 * BSpec recommends 8x4 when MSAA is used,
6895 * however in practice 16x4 seems fastest.
6896 *
6897 * Note that PS/WM thread counts depend on the WIZ hashing
6898 * disable bit, which we don't touch here, but it's good
6899 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6900 */
6901 I915_WRITE(GEN7_GT_MODE,
6902 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6903
031994ee
VS		 6904 /*
6905 * WaIncreaseL3CreditsForVLVB0:vlv
6906 * This is the hardware default actually.
6907 */
6908 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6909
2d809570 6910 /*
ecdb4eb7 6911 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6912 * Disable clock gating on th GCFG unit to prevent a delay
6913 * in the reporting of vblank events.
6914 */
7a0d1eed 6915 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6916}
6917
a4565da8
VS		 6918static void cherryview_init_clock_gating(struct drm_device *dev)
6919{
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921
c6beb13e 6922 vlv_init_display_clock_gating(dev_priv);
dd811e70 6923
232ce337
VS		 6924 /* WaVSRefCountFullforceMissDisable:chv */
6925 /* WaDSRefCountFullforceMissDisable:chv */
6926 I915_WRITE(GEN7_FF_THREAD_MODE,
6927 I915_READ(GEN7_FF_THREAD_MODE) &
6928 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6929
6930 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6931 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6932 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6933
6934 /* WaDisableCSUnitClockGating:chv */
6935 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6936 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6937
6938 /* WaDisableSDEUnitClockGating:chv */
6939 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6940 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6941
6942 /*
6943 * GTT cache may not work with big pages, so if those
6944 * are ever enabled GTT cache may need to be disabled.
6945 */
6946 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6947}
6948
1fa61106 6949static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6950{
6951 struct drm_i915_private *dev_priv = dev->dev_private;
6952 uint32_t dspclk_gate;
6953
6954 I915_WRITE(RENCLK_GATE_D1, 0);
6955 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6956 GS_UNIT_CLOCK_GATE_DISABLE |
6957 CL_UNIT_CLOCK_GATE_DISABLE);
6958 I915_WRITE(RAMCLK_GATE_D, 0);
6959 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6960 OVRUNIT_CLOCK_GATE_DISABLE |
6961 OVCUNIT_CLOCK_GATE_DISABLE;
6962 if (IS_GM45(dev))
6963 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6964 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6965
6966 /* WaDisableRenderCachePipelinedFlush */
6967 I915_WRITE(CACHE_MODE_0,
6968 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6969
4e04632e
AG		 6970 /* WaDisable_RenderCache_OperationalFlush:g4x */
6971 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6972
0e088b8f 6973 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6974}
6975
1fa61106 6976static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6977{
6978 struct drm_i915_private *dev_priv = dev->dev_private;
6979
6980 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6981 I915_WRITE(RENCLK_GATE_D2, 0);
6982 I915_WRITE(DSPCLK_GATE_D, 0);
6983 I915_WRITE(RAMCLK_GATE_D, 0);
6984 I915_WRITE16(DEUC, 0);
20f94967
VS		 6985 I915_WRITE(MI_ARB_STATE,
6986 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6987
6988 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6989 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6990}
6991
1fa61106 6992static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6993{
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995
6996 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6997 I965_RCC_CLOCK_GATE_DISABLE |
6998 I965_RCPB_CLOCK_GATE_DISABLE |
6999 I965_ISC_CLOCK_GATE_DISABLE |
7000 I965_FBC_CLOCK_GATE_DISABLE);
7001 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7002 I915_WRITE(MI_ARB_STATE,
7003 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7004
7005 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7006 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7007}
7008
1fa61106 7009static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7010{
7011 struct drm_i915_private *dev_priv = dev->dev_private;
7012 u32 dstate = I915_READ(D_STATE);
7013
7014 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7015 DSTATE_DOT_CLOCK_GATING;
7016 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7017
7018 if (IS_PINEVIEW(dev))
7019 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7020
7021 /* IIR "flip pending" means done if this bit is set */
7022 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7023
7024 /* interrupts should cause a wake up from C3 */
3299254f 7025 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7026
7027 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7028 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7029
7030 I915_WRITE(MI_ARB_STATE,
7031 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7032}
7033
1fa61106 7034static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7035{
7036 struct drm_i915_private *dev_priv = dev->dev_private;
7037
7038 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7039
7040 /* interrupts should cause a wake up from C3 */
7041 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7042 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7043
7044 I915_WRITE(MEM_MODE,
7045 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7046}
7047
1fa61106 7048static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7049{
7050 struct drm_i915_private *dev_priv = dev->dev_private;
7051
7052 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7053
7054 I915_WRITE(MEM_MODE,
7055 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7056 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7057}
7058
6f1d69b0
ED		 7059void intel_init_clock_gating(struct drm_device *dev)
7060{
7061 struct drm_i915_private *dev_priv = dev->dev_private;
7062
c57e3551
DL		 7063 if (dev_priv->display.init_clock_gating)
7064 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7065}
7066
7d708ee4
ID		 7067void intel_suspend_hw(struct drm_device *dev)
7068{
7069 if (HAS_PCH_LPT(dev))
7070 lpt_suspend_hw(dev);
7071}
7072
1fa61106
ED		 7073/* Set up chip specific power management-related functions */
7074void intel_init_pm(struct drm_device *dev)
7075{
7076 struct drm_i915_private *dev_priv = dev->dev_private;
7077
7ff0ebcc 7078 intel_fbc_init(dev_priv);
1fa61106 7079
c921aba8
DV		 7080 /* For cxsr */
7081 if (IS_PINEVIEW(dev))
7082 i915_pineview_get_mem_freq(dev);
7083 else if (IS_GEN5(dev))
7084 i915_ironlake_get_mem_freq(dev);
7085
1fa61106 7086 /* For FIFO watermark updates */
f5ed50cb 7087 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7088 skl_setup_wm_latency(dev);
7089
a82abe43
ID		 7090 if (IS_BROXTON(dev))
7091 dev_priv->display.init_clock_gating =
7092 bxt_init_clock_gating;
7093 else if (IS_SKYLAKE(dev))
7094 dev_priv->display.init_clock_gating =
7095 skl_init_clock_gating;
2d41c0b5
PB		 7096 dev_priv->display.update_wm = skl_update_wm;
7097 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 7098 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7099 ilk_setup_wm_latency(dev);
53615a5e 7100
bd602544
VS		 7101 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7102 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7103 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7104 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7105 dev_priv->display.update_wm = ilk_update_wm;
7106 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7107 } else {
7108 DRM_DEBUG_KMS("Failed to read display plane latency. "
7109 "Disable CxSR\n");
7110 }
7111
7112 if (IS_GEN5(dev))
1fa61106 7113 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7114 else if (IS_GEN6(dev))
1fa61106 7115 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7116 else if (IS_IVYBRIDGE(dev))
1fa61106 7117 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7118 else if (IS_HASWELL(dev))
cad2a2d7 7119 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7120 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7121 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7122 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7123 vlv_setup_wm_latency(dev);
7124
7125 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7126 dev_priv->display.init_clock_gating =
7127 cherryview_init_clock_gating;
1fa61106 7128 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7129 vlv_setup_wm_latency(dev);
7130
7131 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7132 dev_priv->display.init_clock_gating =
7133 valleyview_init_clock_gating;
1fa61106
ED		 7134 } else if (IS_PINEVIEW(dev)) {
7135 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7136 dev_priv->is_ddr3,
7137 dev_priv->fsb_freq,
7138 dev_priv->mem_freq)) {
7139 DRM_INFO("failed to find known CxSR latency "
7140 "(found ddr%s fsb freq %d, mem freq %d), "
7141 "disabling CxSR\n",
7142 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7143 dev_priv->fsb_freq, dev_priv->mem_freq);
7144 /* Disable CxSR and never update its watermark again */
5209b1f4 7145 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7146 dev_priv->display.update_wm = NULL;
7147 } else
7148 dev_priv->display.update_wm = pineview_update_wm;
7149 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7150 } else if (IS_G4X(dev)) {
7151 dev_priv->display.update_wm = g4x_update_wm;
7152 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7153 } else if (IS_GEN4(dev)) {
7154 dev_priv->display.update_wm = i965_update_wm;
7155 if (IS_CRESTLINE(dev))
7156 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7157 else if (IS_BROADWATER(dev))
7158 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7159 } else if (IS_GEN3(dev)) {
7160 dev_priv->display.update_wm = i9xx_update_wm;
7161 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7162 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7163 } else if (IS_GEN2(dev)) {
7164 if (INTEL_INFO(dev)->num_pipes == 1) {
7165 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7166 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7167 } else {
7168 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7169 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7170 }
7171
7172 if (IS_I85X(dev) || IS_I865G(dev))
7173 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7174 else
7175 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7176 } else {
7177 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7178 }
7179}
7180
151a49d0 7181int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7182{
4fc688ce 7183 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7184
7185 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7186 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7187 return -EAGAIN;
7188 }
7189
7190 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7191 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7192 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7193
7194 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7195 500)) {
7196 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7197 return -ETIMEDOUT;
7198 }
7199
7200 *val = I915_READ(GEN6_PCODE_DATA);
7201 I915_WRITE(GEN6_PCODE_DATA, 0);
7202
7203 return 0;
7204}
7205
151a49d0 7206int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7207{
4fc688ce 7208 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7209
7210 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7211 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7212 return -EAGAIN;
7213 }
7214
7215 I915_WRITE(GEN6_PCODE_DATA, val);
7216 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7217
7218 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7219 500)) {
7220 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7221 return -ETIMEDOUT;
7222 }
7223
7224 I915_WRITE(GEN6_PCODE_DATA, 0);
7225
7226 return 0;
7227}
a0e4e199 7228
dd06f88c 7229static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7230{
dd06f88c
VS		 7231 switch (czclk_freq) {
7232 case 200:
7233 return 10;
7234 case 267:
7235 return 12;
7236 case 320:
7237 case 333:
dd06f88c 7238 return 16;
ab3fb157
VS		 7239 case 400:
7240 return 20;
855ba3be
JB		 7241 default:
7242 return -1;
7243 }
dd06f88c 7244}
855ba3be 7245
dd06f88c
VS		 7246static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7247{
7248 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7249
7250 div = vlv_gpu_freq_div(czclk_freq);
7251 if (div < 0)
7252 return div;
7253
7254 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7255}
7256
b55dd647 7257static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7258{
dd06f88c 7259 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 7260
dd06f88c
VS		 7261 mul = vlv_gpu_freq_div(czclk_freq);
7262 if (mul < 0)
7263 return mul;
855ba3be 7264
dd06f88c 7265 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7266}
7267
b55dd647 7268static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7269{
dd06f88c 7270 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7271
dd06f88c
VS		 7272 div = vlv_gpu_freq_div(czclk_freq) / 2;
7273 if (div < 0)
7274 return div;
22b1b2f8 7275
dd06f88c 7276 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7277}
7278
b55dd647 7279static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7280{
dd06f88c 7281 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7282
dd06f88c
VS		 7283 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7284 if (mul < 0)
7285 return mul;
22b1b2f8 7286
1c14762d 7287 /* CHV needs even values */
dd06f88c 7288 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7289}
7290
616bc820 7291int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7292{
80b6dda4
AG		 7293 if (IS_GEN9(dev_priv->dev))
7294 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7295 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7296 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7297 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7298 return byt_gpu_freq(dev_priv, val);
7299 else
7300 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7301}
7302
616bc820
VS		 7303int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7304{
80b6dda4
AG		 7305 if (IS_GEN9(dev_priv->dev))
7306 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7307 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7308 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7309 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7310 return byt_freq_opcode(dev_priv, val);
7311 else
7312 return val / GT_FREQUENCY_MULTIPLIER;
7313}
22b1b2f8 7314
6ad790c0
CW		 7315struct request_boost {
7316 struct work_struct work;
eed29a5b 7317 struct drm_i915_gem_request *req;
6ad790c0
CW		 7318};
7319
7320static void __intel_rps_boost_work(struct work_struct *work)
7321{
7322 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7323 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7324
e61b9958
CW		 7325 if (!i915_gem_request_completed(req, true))
7326 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7327 req->emitted_jiffies);
6ad790c0 7328
e61b9958 7329 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7330 kfree(boost);
7331}
7332
7333void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7334 struct drm_i915_gem_request *req)
6ad790c0
CW		 7335{
7336 struct request_boost *boost;
7337
eed29a5b 7338 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7339 return;
7340
e61b9958
CW		 7341 if (i915_gem_request_completed(req, true))
7342 return;
7343
6ad790c0
CW		 7344 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7345 if (boost == NULL)
7346 return;
7347
eed29a5b
DV		 7348 i915_gem_request_reference(req);
7349 boost->req = req;
6ad790c0
CW		 7350
7351 INIT_WORK(&boost->work, __intel_rps_boost_work);
7352 queue_work(to_i915(dev)->wq, &boost->work);
7353}
7354
f742a552 7355void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7356{
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358
f742a552 7359 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7360 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7361
907b28c5
CW		 7362 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7363 intel_gen6_powersave_work);
1854d5ca 7364 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7365 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7366 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7367
33688d95 7368 dev_priv->pm.suspended = false;
907b28c5 7369}
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