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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
85208be0 | 33 | |
dc39fff7 BW |
34 | /** |
35 | * RC6 is a special power stage which allows the GPU to enter an very | |
36 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
37 | * stage is entered automatically when the GPU is idle when RC6 support is | |
38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
39 | * | |
40 | * There are different RC6 modes available in Intel GPU, which differentiate | |
41 | * among each other with the latency required to enter and leave RC6 and | |
42 | * voltage consumed by the GPU in different states. | |
43 | * | |
44 | * The combination of the following flags define which states GPU is allowed | |
45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
46 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
48 | * which brings the most power savings; deeper states save more power, but | |
49 | * require higher latency to switch to and wake up. | |
50 | */ | |
51 | #define INTEL_RC6_ENABLE (1<<0) | |
52 | #define INTEL_RC6p_ENABLE (1<<1) | |
53 | #define INTEL_RC6pp_ENABLE (1<<2) | |
54 | ||
a82abe43 ID |
55 | static void bxt_init_clock_gating(struct drm_device *dev) |
56 | { | |
32608ca2 ID |
57 | struct drm_i915_private *dev_priv = dev->dev_private; |
58 | ||
a7546159 NH |
59 | /* WaDisableSDEUnitClockGating:bxt */ |
60 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
61 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
62 | ||
32608ca2 ID |
63 | /* |
64 | * FIXME: | |
868434c5 | 65 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
32608ca2 | 66 | */ |
32608ca2 | 67 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
868434c5 | 68 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
a82abe43 ID |
69 | } |
70 | ||
c921aba8 DV |
71 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
72 | { | |
50227e1c | 73 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
74 | u32 tmp; |
75 | ||
76 | tmp = I915_READ(CLKCFG); | |
77 | ||
78 | switch (tmp & CLKCFG_FSB_MASK) { | |
79 | case CLKCFG_FSB_533: | |
80 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
81 | break; | |
82 | case CLKCFG_FSB_800: | |
83 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
84 | break; | |
85 | case CLKCFG_FSB_667: | |
86 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
87 | break; | |
88 | case CLKCFG_FSB_400: | |
89 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
90 | break; | |
91 | } | |
92 | ||
93 | switch (tmp & CLKCFG_MEM_MASK) { | |
94 | case CLKCFG_MEM_533: | |
95 | dev_priv->mem_freq = 533; | |
96 | break; | |
97 | case CLKCFG_MEM_667: | |
98 | dev_priv->mem_freq = 667; | |
99 | break; | |
100 | case CLKCFG_MEM_800: | |
101 | dev_priv->mem_freq = 800; | |
102 | break; | |
103 | } | |
104 | ||
105 | /* detect pineview DDR3 setting */ | |
106 | tmp = I915_READ(CSHRDDR3CTL); | |
107 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
108 | } | |
109 | ||
110 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
111 | { | |
50227e1c | 112 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
113 | u16 ddrpll, csipll; |
114 | ||
115 | ddrpll = I915_READ16(DDRMPLL1); | |
116 | csipll = I915_READ16(CSIPLL0); | |
117 | ||
118 | switch (ddrpll & 0xff) { | |
119 | case 0xc: | |
120 | dev_priv->mem_freq = 800; | |
121 | break; | |
122 | case 0x10: | |
123 | dev_priv->mem_freq = 1066; | |
124 | break; | |
125 | case 0x14: | |
126 | dev_priv->mem_freq = 1333; | |
127 | break; | |
128 | case 0x18: | |
129 | dev_priv->mem_freq = 1600; | |
130 | break; | |
131 | default: | |
132 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
133 | ddrpll & 0xff); | |
134 | dev_priv->mem_freq = 0; | |
135 | break; | |
136 | } | |
137 | ||
20e4d407 | 138 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
139 | |
140 | switch (csipll & 0x3ff) { | |
141 | case 0x00c: | |
142 | dev_priv->fsb_freq = 3200; | |
143 | break; | |
144 | case 0x00e: | |
145 | dev_priv->fsb_freq = 3733; | |
146 | break; | |
147 | case 0x010: | |
148 | dev_priv->fsb_freq = 4266; | |
149 | break; | |
150 | case 0x012: | |
151 | dev_priv->fsb_freq = 4800; | |
152 | break; | |
153 | case 0x014: | |
154 | dev_priv->fsb_freq = 5333; | |
155 | break; | |
156 | case 0x016: | |
157 | dev_priv->fsb_freq = 5866; | |
158 | break; | |
159 | case 0x018: | |
160 | dev_priv->fsb_freq = 6400; | |
161 | break; | |
162 | default: | |
163 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
164 | csipll & 0x3ff); | |
165 | dev_priv->fsb_freq = 0; | |
166 | break; | |
167 | } | |
168 | ||
169 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 170 | dev_priv->ips.c_m = 0; |
c921aba8 | 171 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 172 | dev_priv->ips.c_m = 1; |
c921aba8 | 173 | } else { |
20e4d407 | 174 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
175 | } |
176 | } | |
177 | ||
b445e3b0 ED |
178 | static const struct cxsr_latency cxsr_latency_table[] = { |
179 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
180 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
181 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
182 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
183 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
184 | ||
185 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
186 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
187 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
188 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
189 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
190 | ||
191 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
192 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
193 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
194 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
195 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
196 | ||
197 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
198 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
199 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
200 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
201 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
202 | ||
203 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
204 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
205 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
206 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
207 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
208 | ||
209 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
210 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
211 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
212 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
213 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
214 | }; | |
215 | ||
63c62275 | 216 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
217 | int is_ddr3, |
218 | int fsb, | |
219 | int mem) | |
220 | { | |
221 | const struct cxsr_latency *latency; | |
222 | int i; | |
223 | ||
224 | if (fsb == 0 || mem == 0) | |
225 | return NULL; | |
226 | ||
227 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
228 | latency = &cxsr_latency_table[i]; | |
229 | if (is_desktop == latency->is_desktop && | |
230 | is_ddr3 == latency->is_ddr3 && | |
231 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
232 | return latency; | |
233 | } | |
234 | ||
235 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
236 | ||
237 | return NULL; | |
238 | } | |
239 | ||
fc1ac8de VS |
240 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
241 | { | |
242 | u32 val; | |
243 | ||
244 | mutex_lock(&dev_priv->rps.hw_lock); | |
245 | ||
246 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
247 | if (enable) | |
248 | val &= ~FORCE_DDR_HIGH_FREQ; | |
249 | else | |
250 | val |= FORCE_DDR_HIGH_FREQ; | |
251 | val &= ~FORCE_DDR_LOW_FREQ; | |
252 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
253 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
254 | ||
255 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
256 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
257 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
258 | ||
259 | mutex_unlock(&dev_priv->rps.hw_lock); | |
260 | } | |
261 | ||
cfb41411 VS |
262 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
263 | { | |
264 | u32 val; | |
265 | ||
266 | mutex_lock(&dev_priv->rps.hw_lock); | |
267 | ||
268 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
269 | if (enable) | |
270 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
271 | else | |
272 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
273 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
274 | ||
275 | mutex_unlock(&dev_priv->rps.hw_lock); | |
276 | } | |
277 | ||
f4998963 VS |
278 | #define FW_WM(value, plane) \ |
279 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
280 | ||
5209b1f4 | 281 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 282 | { |
5209b1f4 ID |
283 | struct drm_device *dev = dev_priv->dev; |
284 | u32 val; | |
b445e3b0 | 285 | |
5209b1f4 ID |
286 | if (IS_VALLEYVIEW(dev)) { |
287 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
a7a6c498 | 288 | POSTING_READ(FW_BLC_SELF_VLV); |
852eb00d | 289 | dev_priv->wm.vlv.cxsr = enable; |
5209b1f4 ID |
290 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
291 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
a7a6c498 | 292 | POSTING_READ(FW_BLC_SELF); |
5209b1f4 ID |
293 | } else if (IS_PINEVIEW(dev)) { |
294 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
295 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
296 | I915_WRITE(DSPFW3, val); | |
a7a6c498 | 297 | POSTING_READ(DSPFW3); |
5209b1f4 ID |
298 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
299 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
300 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
301 | I915_WRITE(FW_BLC_SELF, val); | |
a7a6c498 | 302 | POSTING_READ(FW_BLC_SELF); |
5209b1f4 ID |
303 | } else if (IS_I915GM(dev)) { |
304 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
305 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
306 | I915_WRITE(INSTPM, val); | |
a7a6c498 | 307 | POSTING_READ(INSTPM); |
5209b1f4 ID |
308 | } else { |
309 | return; | |
310 | } | |
b445e3b0 | 311 | |
5209b1f4 ID |
312 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
313 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
314 | } |
315 | ||
fc1ac8de | 316 | |
b445e3b0 ED |
317 | /* |
318 | * Latency for FIFO fetches is dependent on several factors: | |
319 | * - memory configuration (speed, channels) | |
320 | * - chipset | |
321 | * - current MCH state | |
322 | * It can be fairly high in some situations, so here we assume a fairly | |
323 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
324 | * set this value too high, the FIFO will fetch frequently to stay full) | |
325 | * and power consumption (set it too low to save power and we might see | |
326 | * FIFO underruns and display "flicker"). | |
327 | * | |
328 | * A value of 5us seems to be a good balance; safe for very low end | |
329 | * platforms but not overly aggressive on lower latency configs. | |
330 | */ | |
5aef6003 | 331 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 332 | |
b5004720 VS |
333 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
334 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
335 | ||
336 | static int vlv_get_fifo_size(struct drm_device *dev, | |
337 | enum pipe pipe, int plane) | |
338 | { | |
339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
340 | int sprite0_start, sprite1_start, size; | |
341 | ||
342 | switch (pipe) { | |
343 | uint32_t dsparb, dsparb2, dsparb3; | |
344 | case PIPE_A: | |
345 | dsparb = I915_READ(DSPARB); | |
346 | dsparb2 = I915_READ(DSPARB2); | |
347 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
348 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
349 | break; | |
350 | case PIPE_B: | |
351 | dsparb = I915_READ(DSPARB); | |
352 | dsparb2 = I915_READ(DSPARB2); | |
353 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
354 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
355 | break; | |
356 | case PIPE_C: | |
357 | dsparb2 = I915_READ(DSPARB2); | |
358 | dsparb3 = I915_READ(DSPARB3); | |
359 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
360 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
361 | break; | |
362 | default: | |
363 | return 0; | |
364 | } | |
365 | ||
366 | switch (plane) { | |
367 | case 0: | |
368 | size = sprite0_start; | |
369 | break; | |
370 | case 1: | |
371 | size = sprite1_start - sprite0_start; | |
372 | break; | |
373 | case 2: | |
374 | size = 512 - 1 - sprite1_start; | |
375 | break; | |
376 | default: | |
377 | return 0; | |
378 | } | |
379 | ||
380 | DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", | |
381 | pipe_name(pipe), plane == 0 ? "primary" : "sprite", | |
382 | plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), | |
383 | size); | |
384 | ||
385 | return size; | |
386 | } | |
387 | ||
1fa61106 | 388 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
389 | { |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
391 | uint32_t dsparb = I915_READ(DSPARB); | |
392 | int size; | |
393 | ||
394 | size = dsparb & 0x7f; | |
395 | if (plane) | |
396 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
397 | ||
398 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
399 | plane ? "B" : "A", size); | |
400 | ||
401 | return size; | |
402 | } | |
403 | ||
feb56b93 | 404 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
405 | { |
406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
407 | uint32_t dsparb = I915_READ(DSPARB); | |
408 | int size; | |
409 | ||
410 | size = dsparb & 0x1ff; | |
411 | if (plane) | |
412 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
413 | size >>= 1; /* Convert to cachelines */ | |
414 | ||
415 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
416 | plane ? "B" : "A", size); | |
417 | ||
418 | return size; | |
419 | } | |
420 | ||
1fa61106 | 421 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
422 | { |
423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
424 | uint32_t dsparb = I915_READ(DSPARB); | |
425 | int size; | |
426 | ||
427 | size = dsparb & 0x7f; | |
428 | size >>= 2; /* Convert to cachelines */ | |
429 | ||
430 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
431 | plane ? "B" : "A", | |
432 | size); | |
433 | ||
434 | return size; | |
435 | } | |
436 | ||
b445e3b0 ED |
437 | /* Pineview has different values for various configs */ |
438 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
439 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
440 | .max_wm = PINEVIEW_MAX_WM, | |
441 | .default_wm = PINEVIEW_DFT_WM, | |
442 | .guard_size = PINEVIEW_GUARD_WM, | |
443 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
444 | }; |
445 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
446 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
447 | .max_wm = PINEVIEW_MAX_WM, | |
448 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
449 | .guard_size = PINEVIEW_GUARD_WM, | |
450 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
451 | }; |
452 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
453 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
454 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
455 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
456 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
457 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
458 | }; |
459 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
460 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
461 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
462 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
463 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
464 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
465 | }; |
466 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
467 | .fifo_size = G4X_FIFO_SIZE, |
468 | .max_wm = G4X_MAX_WM, | |
469 | .default_wm = G4X_MAX_WM, | |
470 | .guard_size = 2, | |
471 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
472 | }; |
473 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
474 | .fifo_size = I965_CURSOR_FIFO, |
475 | .max_wm = I965_CURSOR_MAX_WM, | |
476 | .default_wm = I965_CURSOR_DFT_WM, | |
477 | .guard_size = 2, | |
478 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
479 | }; |
480 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
481 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
482 | .max_wm = VALLEYVIEW_MAX_WM, | |
483 | .default_wm = VALLEYVIEW_MAX_WM, | |
484 | .guard_size = 2, | |
485 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
486 | }; |
487 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
488 | .fifo_size = I965_CURSOR_FIFO, |
489 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
490 | .default_wm = I965_CURSOR_DFT_WM, | |
491 | .guard_size = 2, | |
492 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
493 | }; |
494 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
495 | .fifo_size = I965_CURSOR_FIFO, |
496 | .max_wm = I965_CURSOR_MAX_WM, | |
497 | .default_wm = I965_CURSOR_DFT_WM, | |
498 | .guard_size = 2, | |
499 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
500 | }; |
501 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
502 | .fifo_size = I945_FIFO_SIZE, |
503 | .max_wm = I915_MAX_WM, | |
504 | .default_wm = 1, | |
505 | .guard_size = 2, | |
506 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
507 | }; |
508 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
509 | .fifo_size = I915_FIFO_SIZE, |
510 | .max_wm = I915_MAX_WM, | |
511 | .default_wm = 1, | |
512 | .guard_size = 2, | |
513 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 514 | }; |
9d539105 | 515 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
516 | .fifo_size = I855GM_FIFO_SIZE, |
517 | .max_wm = I915_MAX_WM, | |
518 | .default_wm = 1, | |
519 | .guard_size = 2, | |
520 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 521 | }; |
9d539105 VS |
522 | static const struct intel_watermark_params i830_bc_wm_info = { |
523 | .fifo_size = I855GM_FIFO_SIZE, | |
524 | .max_wm = I915_MAX_WM/2, | |
525 | .default_wm = 1, | |
526 | .guard_size = 2, | |
527 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
528 | }; | |
feb56b93 | 529 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
530 | .fifo_size = I830_FIFO_SIZE, |
531 | .max_wm = I915_MAX_WM, | |
532 | .default_wm = 1, | |
533 | .guard_size = 2, | |
534 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
535 | }; |
536 | ||
b445e3b0 ED |
537 | /** |
538 | * intel_calculate_wm - calculate watermark level | |
539 | * @clock_in_khz: pixel clock | |
540 | * @wm: chip FIFO params | |
541 | * @pixel_size: display pixel size | |
542 | * @latency_ns: memory latency for the platform | |
543 | * | |
544 | * Calculate the watermark level (the level at which the display plane will | |
545 | * start fetching from memory again). Each chip has a different display | |
546 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
547 | * in the correct intel_watermark_params structure. | |
548 | * | |
549 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
550 | * on the pixel size. When it reaches the watermark level, it'll start | |
551 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
552 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
553 | * will occur, and a display engine hang could result. | |
554 | */ | |
555 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
556 | const struct intel_watermark_params *wm, | |
557 | int fifo_size, | |
558 | int pixel_size, | |
559 | unsigned long latency_ns) | |
560 | { | |
561 | long entries_required, wm_size; | |
562 | ||
563 | /* | |
564 | * Note: we need to make sure we don't overflow for various clock & | |
565 | * latency values. | |
566 | * clocks go from a few thousand to several hundred thousand. | |
567 | * latency is usually a few thousand | |
568 | */ | |
569 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
570 | 1000; | |
571 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
572 | ||
573 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
574 | ||
575 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
576 | ||
577 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
578 | ||
579 | /* Don't promote wm_size to unsigned... */ | |
580 | if (wm_size > (long)wm->max_wm) | |
581 | wm_size = wm->max_wm; | |
582 | if (wm_size <= 0) | |
583 | wm_size = wm->default_wm; | |
d6feb196 VS |
584 | |
585 | /* | |
586 | * Bspec seems to indicate that the value shouldn't be lower than | |
587 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
588 | * Lets go for 8 which is the burst size since certain platforms | |
589 | * already use a hardcoded 8 (which is what the spec says should be | |
590 | * done). | |
591 | */ | |
592 | if (wm_size <= 8) | |
593 | wm_size = 8; | |
594 | ||
b445e3b0 ED |
595 | return wm_size; |
596 | } | |
597 | ||
598 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
599 | { | |
600 | struct drm_crtc *crtc, *enabled = NULL; | |
601 | ||
70e1e0ec | 602 | for_each_crtc(dev, crtc) { |
3490ea5d | 603 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
604 | if (enabled) |
605 | return NULL; | |
606 | enabled = crtc; | |
607 | } | |
608 | } | |
609 | ||
610 | return enabled; | |
611 | } | |
612 | ||
46ba614c | 613 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 614 | { |
46ba614c | 615 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
616 | struct drm_i915_private *dev_priv = dev->dev_private; |
617 | struct drm_crtc *crtc; | |
618 | const struct cxsr_latency *latency; | |
619 | u32 reg; | |
620 | unsigned long wm; | |
621 | ||
622 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
623 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
624 | if (!latency) { | |
625 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 626 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
627 | return; |
628 | } | |
629 | ||
630 | crtc = single_enabled_crtc(dev); | |
631 | if (crtc) { | |
7c5f93b0 | 632 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
59bea882 | 633 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
7c5f93b0 | 634 | int clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
635 | |
636 | /* Display SR */ | |
637 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
638 | pineview_display_wm.fifo_size, | |
639 | pixel_size, latency->display_sr); | |
640 | reg = I915_READ(DSPFW1); | |
641 | reg &= ~DSPFW_SR_MASK; | |
f4998963 | 642 | reg |= FW_WM(wm, SR); |
b445e3b0 ED |
643 | I915_WRITE(DSPFW1, reg); |
644 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
645 | ||
646 | /* cursor SR */ | |
647 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
648 | pineview_display_wm.fifo_size, | |
649 | pixel_size, latency->cursor_sr); | |
650 | reg = I915_READ(DSPFW3); | |
651 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
f4998963 | 652 | reg |= FW_WM(wm, CURSOR_SR); |
b445e3b0 ED |
653 | I915_WRITE(DSPFW3, reg); |
654 | ||
655 | /* Display HPLL off SR */ | |
656 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
657 | pineview_display_hplloff_wm.fifo_size, | |
658 | pixel_size, latency->display_hpll_disable); | |
659 | reg = I915_READ(DSPFW3); | |
660 | reg &= ~DSPFW_HPLL_SR_MASK; | |
f4998963 | 661 | reg |= FW_WM(wm, HPLL_SR); |
b445e3b0 ED |
662 | I915_WRITE(DSPFW3, reg); |
663 | ||
664 | /* cursor HPLL off SR */ | |
665 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
666 | pineview_display_hplloff_wm.fifo_size, | |
667 | pixel_size, latency->cursor_hpll_disable); | |
668 | reg = I915_READ(DSPFW3); | |
669 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
f4998963 | 670 | reg |= FW_WM(wm, HPLL_CURSOR); |
b445e3b0 ED |
671 | I915_WRITE(DSPFW3, reg); |
672 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
673 | ||
5209b1f4 | 674 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 675 | } else { |
5209b1f4 | 676 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
677 | } |
678 | } | |
679 | ||
680 | static bool g4x_compute_wm0(struct drm_device *dev, | |
681 | int plane, | |
682 | const struct intel_watermark_params *display, | |
683 | int display_latency_ns, | |
684 | const struct intel_watermark_params *cursor, | |
685 | int cursor_latency_ns, | |
686 | int *plane_wm, | |
687 | int *cursor_wm) | |
688 | { | |
689 | struct drm_crtc *crtc; | |
4fe8590a | 690 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
691 | int htotal, hdisplay, clock, pixel_size; |
692 | int line_time_us, line_count; | |
693 | int entries, tlb_miss; | |
694 | ||
695 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 696 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
697 | *cursor_wm = cursor->guard_size; |
698 | *plane_wm = display->guard_size; | |
699 | return false; | |
700 | } | |
701 | ||
6e3c9717 | 702 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 703 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 704 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 705 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 706 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
707 | |
708 | /* Use the small buffer method to calculate plane watermark */ | |
709 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
710 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
711 | if (tlb_miss > 0) | |
712 | entries += tlb_miss; | |
713 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
714 | *plane_wm = entries + display->guard_size; | |
715 | if (*plane_wm > (int)display->max_wm) | |
716 | *plane_wm = display->max_wm; | |
717 | ||
718 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 719 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 720 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
3dd512fb | 721 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
b445e3b0 ED |
722 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
723 | if (tlb_miss > 0) | |
724 | entries += tlb_miss; | |
725 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
726 | *cursor_wm = entries + cursor->guard_size; | |
727 | if (*cursor_wm > (int)cursor->max_wm) | |
728 | *cursor_wm = (int)cursor->max_wm; | |
729 | ||
730 | return true; | |
731 | } | |
732 | ||
733 | /* | |
734 | * Check the wm result. | |
735 | * | |
736 | * If any calculated watermark values is larger than the maximum value that | |
737 | * can be programmed into the associated watermark register, that watermark | |
738 | * must be disabled. | |
739 | */ | |
740 | static bool g4x_check_srwm(struct drm_device *dev, | |
741 | int display_wm, int cursor_wm, | |
742 | const struct intel_watermark_params *display, | |
743 | const struct intel_watermark_params *cursor) | |
744 | { | |
745 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
746 | display_wm, cursor_wm); | |
747 | ||
748 | if (display_wm > display->max_wm) { | |
749 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
750 | display_wm, display->max_wm); | |
751 | return false; | |
752 | } | |
753 | ||
754 | if (cursor_wm > cursor->max_wm) { | |
755 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
756 | cursor_wm, cursor->max_wm); | |
757 | return false; | |
758 | } | |
759 | ||
760 | if (!(display_wm || cursor_wm)) { | |
761 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
762 | return false; | |
763 | } | |
764 | ||
765 | return true; | |
766 | } | |
767 | ||
768 | static bool g4x_compute_srwm(struct drm_device *dev, | |
769 | int plane, | |
770 | int latency_ns, | |
771 | const struct intel_watermark_params *display, | |
772 | const struct intel_watermark_params *cursor, | |
773 | int *display_wm, int *cursor_wm) | |
774 | { | |
775 | struct drm_crtc *crtc; | |
4fe8590a | 776 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
777 | int hdisplay, htotal, pixel_size, clock; |
778 | unsigned long line_time_us; | |
779 | int line_count, line_size; | |
780 | int small, large; | |
781 | int entries; | |
782 | ||
783 | if (!latency_ns) { | |
784 | *display_wm = *cursor_wm = 0; | |
785 | return false; | |
786 | } | |
787 | ||
788 | crtc = intel_get_crtc_for_plane(dev, plane); | |
6e3c9717 | 789 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 790 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 791 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 792 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 793 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 | 794 | |
922044c9 | 795 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
796 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
797 | line_size = hdisplay * pixel_size; | |
798 | ||
799 | /* Use the minimum of the small and large buffer method for primary */ | |
800 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
801 | large = line_count * line_size; | |
802 | ||
803 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
804 | *display_wm = entries + display->guard_size; | |
805 | ||
806 | /* calculate the self-refresh watermark for display cursor */ | |
3dd512fb | 807 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
808 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
809 | *cursor_wm = entries + cursor->guard_size; | |
810 | ||
811 | return g4x_check_srwm(dev, | |
812 | *display_wm, *cursor_wm, | |
813 | display, cursor); | |
814 | } | |
815 | ||
15665979 VS |
816 | #define FW_WM_VLV(value, plane) \ |
817 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
818 | ||
0018fda1 VS |
819 | static void vlv_write_wm_values(struct intel_crtc *crtc, |
820 | const struct vlv_wm_values *wm) | |
821 | { | |
822 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
823 | enum pipe pipe = crtc->pipe; | |
824 | ||
825 | I915_WRITE(VLV_DDL(pipe), | |
826 | (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | | |
827 | (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | | |
828 | (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | | |
829 | (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); | |
830 | ||
ae80152d | 831 | I915_WRITE(DSPFW1, |
15665979 VS |
832 | FW_WM(wm->sr.plane, SR) | |
833 | FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | | |
834 | FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | | |
835 | FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); | |
ae80152d | 836 | I915_WRITE(DSPFW2, |
15665979 VS |
837 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | |
838 | FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | | |
839 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); | |
ae80152d | 840 | I915_WRITE(DSPFW3, |
15665979 | 841 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
842 | |
843 | if (IS_CHERRYVIEW(dev_priv)) { | |
844 | I915_WRITE(DSPFW7_CHV, | |
15665979 VS |
845 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
846 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 847 | I915_WRITE(DSPFW8_CHV, |
15665979 VS |
848 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | |
849 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); | |
ae80152d | 850 | I915_WRITE(DSPFW9_CHV, |
15665979 VS |
851 | FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | |
852 | FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); | |
ae80152d | 853 | I915_WRITE(DSPHOWM, |
15665979 VS |
854 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
855 | FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | | |
856 | FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | | |
857 | FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | | |
858 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
859 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
860 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
861 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
862 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
863 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
864 | } else { |
865 | I915_WRITE(DSPFW7, | |
15665979 VS |
866 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
867 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 868 | I915_WRITE(DSPHOWM, |
15665979 VS |
869 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
870 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
871 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
872 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
873 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
874 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
875 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
876 | } |
877 | ||
2cb389b7 VS |
878 | /* zero (unused) WM1 watermarks */ |
879 | I915_WRITE(DSPFW4, 0); | |
880 | I915_WRITE(DSPFW5, 0); | |
881 | I915_WRITE(DSPFW6, 0); | |
882 | I915_WRITE(DSPHOWM1, 0); | |
883 | ||
ae80152d | 884 | POSTING_READ(DSPFW1); |
0018fda1 VS |
885 | } |
886 | ||
15665979 VS |
887 | #undef FW_WM_VLV |
888 | ||
6eb1a681 VS |
889 | enum vlv_wm_level { |
890 | VLV_WM_LEVEL_PM2, | |
891 | VLV_WM_LEVEL_PM5, | |
892 | VLV_WM_LEVEL_DDR_DVFS, | |
6eb1a681 VS |
893 | }; |
894 | ||
262cd2e1 VS |
895 | /* latency must be in 0.1us units. */ |
896 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, | |
897 | unsigned int pipe_htotal, | |
898 | unsigned int horiz_pixels, | |
899 | unsigned int bytes_per_pixel, | |
900 | unsigned int latency) | |
901 | { | |
902 | unsigned int ret; | |
903 | ||
904 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); | |
905 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
906 | ret = DIV_ROUND_UP(ret, 64); | |
907 | ||
908 | return ret; | |
909 | } | |
910 | ||
911 | static void vlv_setup_wm_latency(struct drm_device *dev) | |
912 | { | |
913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
914 | ||
915 | /* all latencies in usec */ | |
916 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; | |
917 | ||
58590c14 VS |
918 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
919 | ||
262cd2e1 VS |
920 | if (IS_CHERRYVIEW(dev_priv)) { |
921 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; | |
922 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; | |
58590c14 VS |
923 | |
924 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; | |
262cd2e1 VS |
925 | } |
926 | } | |
927 | ||
928 | static uint16_t vlv_compute_wm_level(struct intel_plane *plane, | |
929 | struct intel_crtc *crtc, | |
930 | const struct intel_plane_state *state, | |
931 | int level) | |
932 | { | |
933 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
934 | int clock, htotal, pixel_size, width, wm; | |
935 | ||
936 | if (dev_priv->wm.pri_latency[level] == 0) | |
937 | return USHRT_MAX; | |
938 | ||
939 | if (!state->visible) | |
940 | return 0; | |
941 | ||
942 | pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); | |
943 | clock = crtc->config->base.adjusted_mode.crtc_clock; | |
944 | htotal = crtc->config->base.adjusted_mode.crtc_htotal; | |
945 | width = crtc->config->pipe_src_w; | |
946 | if (WARN_ON(htotal == 0)) | |
947 | htotal = 1; | |
948 | ||
949 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { | |
950 | /* | |
951 | * FIXME the formula gives values that are | |
952 | * too big for the cursor FIFO, and hence we | |
953 | * would never be able to use cursors. For | |
954 | * now just hardcode the watermark. | |
955 | */ | |
956 | wm = 63; | |
957 | } else { | |
958 | wm = vlv_wm_method2(clock, htotal, width, pixel_size, | |
959 | dev_priv->wm.pri_latency[level] * 10); | |
960 | } | |
961 | ||
962 | return min_t(int, wm, USHRT_MAX); | |
963 | } | |
964 | ||
54f1b6e1 VS |
965 | static void vlv_compute_fifo(struct intel_crtc *crtc) |
966 | { | |
967 | struct drm_device *dev = crtc->base.dev; | |
968 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
969 | struct intel_plane *plane; | |
970 | unsigned int total_rate = 0; | |
971 | const int fifo_size = 512 - 1; | |
972 | int fifo_extra, fifo_left = fifo_size; | |
973 | ||
974 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
975 | struct intel_plane_state *state = | |
976 | to_intel_plane_state(plane->base.state); | |
977 | ||
978 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) | |
979 | continue; | |
980 | ||
981 | if (state->visible) { | |
982 | wm_state->num_active_planes++; | |
983 | total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); | |
984 | } | |
985 | } | |
986 | ||
987 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
988 | struct intel_plane_state *state = | |
989 | to_intel_plane_state(plane->base.state); | |
990 | unsigned int rate; | |
991 | ||
992 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { | |
993 | plane->wm.fifo_size = 63; | |
994 | continue; | |
995 | } | |
996 | ||
997 | if (!state->visible) { | |
998 | plane->wm.fifo_size = 0; | |
999 | continue; | |
1000 | } | |
1001 | ||
1002 | rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); | |
1003 | plane->wm.fifo_size = fifo_size * rate / total_rate; | |
1004 | fifo_left -= plane->wm.fifo_size; | |
1005 | } | |
1006 | ||
1007 | fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); | |
1008 | ||
1009 | /* spread the remainder evenly */ | |
1010 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1011 | int plane_extra; | |
1012 | ||
1013 | if (fifo_left == 0) | |
1014 | break; | |
1015 | ||
1016 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) | |
1017 | continue; | |
1018 | ||
1019 | /* give it all to the first plane if none are active */ | |
1020 | if (plane->wm.fifo_size == 0 && | |
1021 | wm_state->num_active_planes) | |
1022 | continue; | |
1023 | ||
1024 | plane_extra = min(fifo_extra, fifo_left); | |
1025 | plane->wm.fifo_size += plane_extra; | |
1026 | fifo_left -= plane_extra; | |
1027 | } | |
1028 | ||
1029 | WARN_ON(fifo_left != 0); | |
1030 | } | |
1031 | ||
262cd2e1 VS |
1032 | static void vlv_invert_wms(struct intel_crtc *crtc) |
1033 | { | |
1034 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1035 | int level; | |
1036 | ||
1037 | for (level = 0; level < wm_state->num_levels; level++) { | |
1038 | struct drm_device *dev = crtc->base.dev; | |
1039 | const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; | |
1040 | struct intel_plane *plane; | |
1041 | ||
1042 | wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; | |
1043 | wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; | |
1044 | ||
1045 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1046 | switch (plane->base.type) { | |
1047 | int sprite; | |
1048 | case DRM_PLANE_TYPE_CURSOR: | |
1049 | wm_state->wm[level].cursor = plane->wm.fifo_size - | |
1050 | wm_state->wm[level].cursor; | |
1051 | break; | |
1052 | case DRM_PLANE_TYPE_PRIMARY: | |
1053 | wm_state->wm[level].primary = plane->wm.fifo_size - | |
1054 | wm_state->wm[level].primary; | |
1055 | break; | |
1056 | case DRM_PLANE_TYPE_OVERLAY: | |
1057 | sprite = plane->plane; | |
1058 | wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - | |
1059 | wm_state->wm[level].sprite[sprite]; | |
1060 | break; | |
1061 | } | |
1062 | } | |
1063 | } | |
1064 | } | |
1065 | ||
26e1fe4f | 1066 | static void vlv_compute_wm(struct intel_crtc *crtc) |
262cd2e1 VS |
1067 | { |
1068 | struct drm_device *dev = crtc->base.dev; | |
1069 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1070 | struct intel_plane *plane; | |
1071 | int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; | |
1072 | int level; | |
1073 | ||
1074 | memset(wm_state, 0, sizeof(*wm_state)); | |
1075 | ||
852eb00d | 1076 | wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; |
58590c14 | 1077 | wm_state->num_levels = to_i915(dev)->wm.max_level + 1; |
262cd2e1 VS |
1078 | |
1079 | wm_state->num_active_planes = 0; | |
262cd2e1 | 1080 | |
54f1b6e1 | 1081 | vlv_compute_fifo(crtc); |
262cd2e1 VS |
1082 | |
1083 | if (wm_state->num_active_planes != 1) | |
1084 | wm_state->cxsr = false; | |
1085 | ||
1086 | if (wm_state->cxsr) { | |
1087 | for (level = 0; level < wm_state->num_levels; level++) { | |
1088 | wm_state->sr[level].plane = sr_fifo_size; | |
1089 | wm_state->sr[level].cursor = 63; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1094 | struct intel_plane_state *state = | |
1095 | to_intel_plane_state(plane->base.state); | |
1096 | ||
1097 | if (!state->visible) | |
1098 | continue; | |
1099 | ||
1100 | /* normal watermarks */ | |
1101 | for (level = 0; level < wm_state->num_levels; level++) { | |
1102 | int wm = vlv_compute_wm_level(plane, crtc, state, level); | |
1103 | int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; | |
1104 | ||
1105 | /* hack */ | |
1106 | if (WARN_ON(level == 0 && wm > max_wm)) | |
1107 | wm = max_wm; | |
1108 | ||
1109 | if (wm > plane->wm.fifo_size) | |
1110 | break; | |
1111 | ||
1112 | switch (plane->base.type) { | |
1113 | int sprite; | |
1114 | case DRM_PLANE_TYPE_CURSOR: | |
1115 | wm_state->wm[level].cursor = wm; | |
1116 | break; | |
1117 | case DRM_PLANE_TYPE_PRIMARY: | |
1118 | wm_state->wm[level].primary = wm; | |
1119 | break; | |
1120 | case DRM_PLANE_TYPE_OVERLAY: | |
1121 | sprite = plane->plane; | |
1122 | wm_state->wm[level].sprite[sprite] = wm; | |
1123 | break; | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | wm_state->num_levels = level; | |
1128 | ||
1129 | if (!wm_state->cxsr) | |
1130 | continue; | |
1131 | ||
1132 | /* maxfifo watermarks */ | |
1133 | switch (plane->base.type) { | |
1134 | int sprite, level; | |
1135 | case DRM_PLANE_TYPE_CURSOR: | |
1136 | for (level = 0; level < wm_state->num_levels; level++) | |
1137 | wm_state->sr[level].cursor = | |
5a37ed0a | 1138 | wm_state->wm[level].cursor; |
262cd2e1 VS |
1139 | break; |
1140 | case DRM_PLANE_TYPE_PRIMARY: | |
1141 | for (level = 0; level < wm_state->num_levels; level++) | |
1142 | wm_state->sr[level].plane = | |
1143 | min(wm_state->sr[level].plane, | |
1144 | wm_state->wm[level].primary); | |
1145 | break; | |
1146 | case DRM_PLANE_TYPE_OVERLAY: | |
1147 | sprite = plane->plane; | |
1148 | for (level = 0; level < wm_state->num_levels; level++) | |
1149 | wm_state->sr[level].plane = | |
1150 | min(wm_state->sr[level].plane, | |
1151 | wm_state->wm[level].sprite[sprite]); | |
1152 | break; | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | /* clear any (partially) filled invalid levels */ | |
58590c14 | 1157 | for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { |
262cd2e1 VS |
1158 | memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); |
1159 | memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); | |
1160 | } | |
1161 | ||
1162 | vlv_invert_wms(crtc); | |
1163 | } | |
1164 | ||
54f1b6e1 VS |
1165 | #define VLV_FIFO(plane, value) \ |
1166 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) | |
1167 | ||
1168 | static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) | |
1169 | { | |
1170 | struct drm_device *dev = crtc->base.dev; | |
1171 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1172 | struct intel_plane *plane; | |
1173 | int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; | |
1174 | ||
1175 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1176 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { | |
1177 | WARN_ON(plane->wm.fifo_size != 63); | |
1178 | continue; | |
1179 | } | |
1180 | ||
1181 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
1182 | sprite0_start = plane->wm.fifo_size; | |
1183 | else if (plane->plane == 0) | |
1184 | sprite1_start = sprite0_start + plane->wm.fifo_size; | |
1185 | else | |
1186 | fifo_size = sprite1_start + plane->wm.fifo_size; | |
1187 | } | |
1188 | ||
1189 | WARN_ON(fifo_size != 512 - 1); | |
1190 | ||
1191 | DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", | |
1192 | pipe_name(crtc->pipe), sprite0_start, | |
1193 | sprite1_start, fifo_size); | |
1194 | ||
1195 | switch (crtc->pipe) { | |
1196 | uint32_t dsparb, dsparb2, dsparb3; | |
1197 | case PIPE_A: | |
1198 | dsparb = I915_READ(DSPARB); | |
1199 | dsparb2 = I915_READ(DSPARB2); | |
1200 | ||
1201 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | | |
1202 | VLV_FIFO(SPRITEB, 0xff)); | |
1203 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | | |
1204 | VLV_FIFO(SPRITEB, sprite1_start)); | |
1205 | ||
1206 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | | |
1207 | VLV_FIFO(SPRITEB_HI, 0x1)); | |
1208 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | | |
1209 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); | |
1210 | ||
1211 | I915_WRITE(DSPARB, dsparb); | |
1212 | I915_WRITE(DSPARB2, dsparb2); | |
1213 | break; | |
1214 | case PIPE_B: | |
1215 | dsparb = I915_READ(DSPARB); | |
1216 | dsparb2 = I915_READ(DSPARB2); | |
1217 | ||
1218 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | | |
1219 | VLV_FIFO(SPRITED, 0xff)); | |
1220 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | | |
1221 | VLV_FIFO(SPRITED, sprite1_start)); | |
1222 | ||
1223 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | | |
1224 | VLV_FIFO(SPRITED_HI, 0xff)); | |
1225 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | | |
1226 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); | |
1227 | ||
1228 | I915_WRITE(DSPARB, dsparb); | |
1229 | I915_WRITE(DSPARB2, dsparb2); | |
1230 | break; | |
1231 | case PIPE_C: | |
1232 | dsparb3 = I915_READ(DSPARB3); | |
1233 | dsparb2 = I915_READ(DSPARB2); | |
1234 | ||
1235 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | | |
1236 | VLV_FIFO(SPRITEF, 0xff)); | |
1237 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | | |
1238 | VLV_FIFO(SPRITEF, sprite1_start)); | |
1239 | ||
1240 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | | |
1241 | VLV_FIFO(SPRITEF_HI, 0xff)); | |
1242 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | | |
1243 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); | |
1244 | ||
1245 | I915_WRITE(DSPARB3, dsparb3); | |
1246 | I915_WRITE(DSPARB2, dsparb2); | |
1247 | break; | |
1248 | default: | |
1249 | break; | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | #undef VLV_FIFO | |
1254 | ||
262cd2e1 VS |
1255 | static void vlv_merge_wm(struct drm_device *dev, |
1256 | struct vlv_wm_values *wm) | |
1257 | { | |
1258 | struct intel_crtc *crtc; | |
1259 | int num_active_crtcs = 0; | |
1260 | ||
58590c14 | 1261 | wm->level = to_i915(dev)->wm.max_level; |
262cd2e1 VS |
1262 | wm->cxsr = true; |
1263 | ||
1264 | for_each_intel_crtc(dev, crtc) { | |
1265 | const struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1266 | ||
1267 | if (!crtc->active) | |
1268 | continue; | |
1269 | ||
1270 | if (!wm_state->cxsr) | |
1271 | wm->cxsr = false; | |
1272 | ||
1273 | num_active_crtcs++; | |
1274 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); | |
1275 | } | |
1276 | ||
1277 | if (num_active_crtcs != 1) | |
1278 | wm->cxsr = false; | |
1279 | ||
6f9c784b VS |
1280 | if (num_active_crtcs > 1) |
1281 | wm->level = VLV_WM_LEVEL_PM2; | |
1282 | ||
262cd2e1 VS |
1283 | for_each_intel_crtc(dev, crtc) { |
1284 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1285 | enum pipe pipe = crtc->pipe; | |
1286 | ||
1287 | if (!crtc->active) | |
1288 | continue; | |
1289 | ||
1290 | wm->pipe[pipe] = wm_state->wm[wm->level]; | |
1291 | if (wm->cxsr) | |
1292 | wm->sr = wm_state->sr[wm->level]; | |
1293 | ||
1294 | wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; | |
1295 | wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; | |
1296 | wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; | |
1297 | wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | static void vlv_update_wm(struct drm_crtc *crtc) | |
1302 | { | |
1303 | struct drm_device *dev = crtc->dev; | |
1304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1306 | enum pipe pipe = intel_crtc->pipe; | |
1307 | struct vlv_wm_values wm = {}; | |
1308 | ||
26e1fe4f | 1309 | vlv_compute_wm(intel_crtc); |
262cd2e1 VS |
1310 | vlv_merge_wm(dev, &wm); |
1311 | ||
54f1b6e1 VS |
1312 | if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { |
1313 | /* FIXME should be part of crtc atomic commit */ | |
1314 | vlv_pipe_set_fifo_size(intel_crtc); | |
262cd2e1 | 1315 | return; |
54f1b6e1 | 1316 | } |
262cd2e1 VS |
1317 | |
1318 | if (wm.level < VLV_WM_LEVEL_DDR_DVFS && | |
1319 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) | |
1320 | chv_set_memory_dvfs(dev_priv, false); | |
1321 | ||
1322 | if (wm.level < VLV_WM_LEVEL_PM5 && | |
1323 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) | |
1324 | chv_set_memory_pm5(dev_priv, false); | |
1325 | ||
852eb00d | 1326 | if (!wm.cxsr && dev_priv->wm.vlv.cxsr) |
262cd2e1 | 1327 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 1328 | |
54f1b6e1 VS |
1329 | /* FIXME should be part of crtc atomic commit */ |
1330 | vlv_pipe_set_fifo_size(intel_crtc); | |
1331 | ||
262cd2e1 VS |
1332 | vlv_write_wm_values(intel_crtc, &wm); |
1333 | ||
1334 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " | |
1335 | "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", | |
1336 | pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, | |
1337 | wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], | |
1338 | wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); | |
1339 | ||
852eb00d | 1340 | if (wm.cxsr && !dev_priv->wm.vlv.cxsr) |
262cd2e1 | 1341 | intel_set_memory_cxsr(dev_priv, true); |
262cd2e1 VS |
1342 | |
1343 | if (wm.level >= VLV_WM_LEVEL_PM5 && | |
1344 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) | |
1345 | chv_set_memory_pm5(dev_priv, true); | |
1346 | ||
1347 | if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && | |
1348 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) | |
1349 | chv_set_memory_dvfs(dev_priv, true); | |
1350 | ||
1351 | dev_priv->wm.vlv = wm; | |
3c2777fd VS |
1352 | } |
1353 | ||
ae80152d VS |
1354 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1355 | ||
46ba614c | 1356 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1357 | { |
46ba614c | 1358 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1359 | static const int sr_latency_ns = 12000; |
1360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1361 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1362 | int plane_sr, cursor_sr; | |
1363 | unsigned int enabled = 0; | |
9858425c | 1364 | bool cxsr_enabled; |
b445e3b0 | 1365 | |
51cea1f4 | 1366 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1367 | &g4x_wm_info, pessimal_latency_ns, |
1368 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1369 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1370 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1371 | |
51cea1f4 | 1372 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1373 | &g4x_wm_info, pessimal_latency_ns, |
1374 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1375 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1376 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1377 | |
b445e3b0 ED |
1378 | if (single_plane_enabled(enabled) && |
1379 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1380 | sr_latency_ns, | |
1381 | &g4x_wm_info, | |
1382 | &g4x_cursor_wm_info, | |
52bd02d8 | 1383 | &plane_sr, &cursor_sr)) { |
9858425c | 1384 | cxsr_enabled = true; |
52bd02d8 | 1385 | } else { |
9858425c | 1386 | cxsr_enabled = false; |
5209b1f4 | 1387 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1388 | plane_sr = cursor_sr = 0; |
1389 | } | |
b445e3b0 | 1390 | |
a5043453 VS |
1391 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1392 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1393 | planea_wm, cursora_wm, |
1394 | planeb_wm, cursorb_wm, | |
1395 | plane_sr, cursor_sr); | |
1396 | ||
1397 | I915_WRITE(DSPFW1, | |
f4998963 VS |
1398 | FW_WM(plane_sr, SR) | |
1399 | FW_WM(cursorb_wm, CURSORB) | | |
1400 | FW_WM(planeb_wm, PLANEB) | | |
1401 | FW_WM(planea_wm, PLANEA)); | |
b445e3b0 | 1402 | I915_WRITE(DSPFW2, |
8c919b28 | 1403 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
f4998963 | 1404 | FW_WM(cursora_wm, CURSORA)); |
b445e3b0 ED |
1405 | /* HPLL off in SR has some issues on G4x... disable it */ |
1406 | I915_WRITE(DSPFW3, | |
8c919b28 | 1407 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
f4998963 | 1408 | FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1409 | |
1410 | if (cxsr_enabled) | |
1411 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1412 | } |
1413 | ||
46ba614c | 1414 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1415 | { |
46ba614c | 1416 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1417 | struct drm_i915_private *dev_priv = dev->dev_private; |
1418 | struct drm_crtc *crtc; | |
1419 | int srwm = 1; | |
1420 | int cursor_sr = 16; | |
9858425c | 1421 | bool cxsr_enabled; |
b445e3b0 ED |
1422 | |
1423 | /* Calc sr entries for one plane configs */ | |
1424 | crtc = single_enabled_crtc(dev); | |
1425 | if (crtc) { | |
1426 | /* self-refresh has much higher latency */ | |
1427 | static const int sr_latency_ns = 12000; | |
124abe07 | 1428 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1429 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1430 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1431 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 1432 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1433 | unsigned long line_time_us; |
1434 | int entries; | |
1435 | ||
922044c9 | 1436 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1437 | |
1438 | /* Use ns/us then divide to preserve precision */ | |
1439 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1440 | pixel_size * hdisplay; | |
1441 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1442 | srwm = I965_FIFO_SIZE - entries; | |
1443 | if (srwm < 0) | |
1444 | srwm = 1; | |
1445 | srwm &= 0x1ff; | |
1446 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1447 | entries, srwm); | |
1448 | ||
1449 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
3dd512fb | 1450 | pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
1451 | entries = DIV_ROUND_UP(entries, |
1452 | i965_cursor_wm_info.cacheline_size); | |
1453 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1454 | (entries + i965_cursor_wm_info.guard_size); | |
1455 | ||
1456 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1457 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1458 | ||
1459 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1460 | "cursor %d\n", srwm, cursor_sr); | |
1461 | ||
9858425c | 1462 | cxsr_enabled = true; |
b445e3b0 | 1463 | } else { |
9858425c | 1464 | cxsr_enabled = false; |
b445e3b0 | 1465 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1466 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1467 | } |
1468 | ||
1469 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1470 | srwm); | |
1471 | ||
1472 | /* 965 has limitations... */ | |
f4998963 VS |
1473 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
1474 | FW_WM(8, CURSORB) | | |
1475 | FW_WM(8, PLANEB) | | |
1476 | FW_WM(8, PLANEA)); | |
1477 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | | |
1478 | FW_WM(8, PLANEC_OLD)); | |
b445e3b0 | 1479 | /* update cursor SR watermark */ |
f4998963 | 1480 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1481 | |
1482 | if (cxsr_enabled) | |
1483 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1484 | } |
1485 | ||
f4998963 VS |
1486 | #undef FW_WM |
1487 | ||
46ba614c | 1488 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1489 | { |
46ba614c | 1490 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1491 | struct drm_i915_private *dev_priv = dev->dev_private; |
1492 | const struct intel_watermark_params *wm_info; | |
1493 | uint32_t fwater_lo; | |
1494 | uint32_t fwater_hi; | |
1495 | int cwm, srwm = 1; | |
1496 | int fifo_size; | |
1497 | int planea_wm, planeb_wm; | |
1498 | struct drm_crtc *crtc, *enabled = NULL; | |
1499 | ||
1500 | if (IS_I945GM(dev)) | |
1501 | wm_info = &i945_wm_info; | |
1502 | else if (!IS_GEN2(dev)) | |
1503 | wm_info = &i915_wm_info; | |
1504 | else | |
9d539105 | 1505 | wm_info = &i830_a_wm_info; |
b445e3b0 ED |
1506 | |
1507 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1508 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1509 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1510 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1511 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1512 | if (IS_GEN2(dev)) |
1513 | cpp = 4; | |
1514 | ||
6e3c9717 | 1515 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1516 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1517 | wm_info, fifo_size, cpp, |
5aef6003 | 1518 | pessimal_latency_ns); |
b445e3b0 | 1519 | enabled = crtc; |
9d539105 | 1520 | } else { |
b445e3b0 | 1521 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1522 | if (planea_wm > (long)wm_info->max_wm) |
1523 | planea_wm = wm_info->max_wm; | |
1524 | } | |
1525 | ||
1526 | if (IS_GEN2(dev)) | |
1527 | wm_info = &i830_bc_wm_info; | |
b445e3b0 ED |
1528 | |
1529 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1530 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1531 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1532 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1533 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1534 | if (IS_GEN2(dev)) |
1535 | cpp = 4; | |
1536 | ||
6e3c9717 | 1537 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1538 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1539 | wm_info, fifo_size, cpp, |
5aef6003 | 1540 | pessimal_latency_ns); |
b445e3b0 ED |
1541 | if (enabled == NULL) |
1542 | enabled = crtc; | |
1543 | else | |
1544 | enabled = NULL; | |
9d539105 | 1545 | } else { |
b445e3b0 | 1546 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1547 | if (planeb_wm > (long)wm_info->max_wm) |
1548 | planeb_wm = wm_info->max_wm; | |
1549 | } | |
b445e3b0 ED |
1550 | |
1551 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1552 | ||
2ab1bc9d | 1553 | if (IS_I915GM(dev) && enabled) { |
2ff8fde1 | 1554 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1555 | |
59bea882 | 1556 | obj = intel_fb_obj(enabled->primary->state->fb); |
2ab1bc9d DV |
1557 | |
1558 | /* self-refresh seems busted with untiled */ | |
2ff8fde1 | 1559 | if (obj->tiling_mode == I915_TILING_NONE) |
2ab1bc9d DV |
1560 | enabled = NULL; |
1561 | } | |
1562 | ||
b445e3b0 ED |
1563 | /* |
1564 | * Overlay gets an aggressive default since video jitter is bad. | |
1565 | */ | |
1566 | cwm = 2; | |
1567 | ||
1568 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1569 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1570 | |
1571 | /* Calc sr entries for one plane configs */ | |
1572 | if (HAS_FW_BLC(dev) && enabled) { | |
1573 | /* self-refresh has much higher latency */ | |
1574 | static const int sr_latency_ns = 6000; | |
124abe07 | 1575 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; |
241bfc38 | 1576 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1577 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1578 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
59bea882 | 1579 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1580 | unsigned long line_time_us; |
1581 | int entries; | |
1582 | ||
922044c9 | 1583 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1584 | |
1585 | /* Use ns/us then divide to preserve precision */ | |
1586 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1587 | pixel_size * hdisplay; | |
1588 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1589 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1590 | srwm = wm_info->fifo_size - entries; | |
1591 | if (srwm < 0) | |
1592 | srwm = 1; | |
1593 | ||
1594 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1595 | I915_WRITE(FW_BLC_SELF, | |
1596 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1597 | else if (IS_I915GM(dev)) | |
1598 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1599 | } | |
1600 | ||
1601 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1602 | planea_wm, planeb_wm, cwm, srwm); | |
1603 | ||
1604 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1605 | fwater_hi = (cwm & 0x1f); | |
1606 | ||
1607 | /* Set request length to 8 cachelines per fetch */ | |
1608 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1609 | fwater_hi = fwater_hi | (1 << 8); | |
1610 | ||
1611 | I915_WRITE(FW_BLC, fwater_lo); | |
1612 | I915_WRITE(FW_BLC2, fwater_hi); | |
1613 | ||
5209b1f4 ID |
1614 | if (enabled) |
1615 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1616 | } |
1617 | ||
feb56b93 | 1618 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1619 | { |
46ba614c | 1620 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1621 | struct drm_i915_private *dev_priv = dev->dev_private; |
1622 | struct drm_crtc *crtc; | |
241bfc38 | 1623 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1624 | uint32_t fwater_lo; |
1625 | int planea_wm; | |
1626 | ||
1627 | crtc = single_enabled_crtc(dev); | |
1628 | if (crtc == NULL) | |
1629 | return; | |
1630 | ||
6e3c9717 | 1631 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1632 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 1633 | &i845_wm_info, |
b445e3b0 | 1634 | dev_priv->display.get_fifo_size(dev, 0), |
5aef6003 | 1635 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1636 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1637 | fwater_lo |= (3<<8) | planea_wm; | |
1638 | ||
1639 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1640 | ||
1641 | I915_WRITE(FW_BLC, fwater_lo); | |
1642 | } | |
1643 | ||
8cfb3407 | 1644 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
801bcfff | 1645 | { |
fd4daa9c | 1646 | uint32_t pixel_rate; |
801bcfff | 1647 | |
8cfb3407 | 1648 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; |
801bcfff PZ |
1649 | |
1650 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1651 | * adjust the pixel_rate here. */ | |
1652 | ||
8cfb3407 | 1653 | if (pipe_config->pch_pfit.enabled) { |
801bcfff | 1654 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
8cfb3407 VS |
1655 | uint32_t pfit_size = pipe_config->pch_pfit.size; |
1656 | ||
1657 | pipe_w = pipe_config->pipe_src_w; | |
1658 | pipe_h = pipe_config->pipe_src_h; | |
801bcfff | 1659 | |
801bcfff PZ |
1660 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1661 | pfit_h = pfit_size & 0xFFFF; | |
1662 | if (pipe_w < pfit_w) | |
1663 | pipe_w = pfit_w; | |
1664 | if (pipe_h < pfit_h) | |
1665 | pipe_h = pfit_h; | |
1666 | ||
1667 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1668 | pfit_w * pfit_h); | |
1669 | } | |
1670 | ||
1671 | return pixel_rate; | |
1672 | } | |
1673 | ||
37126462 | 1674 | /* latency must be in 0.1us units. */ |
23297044 | 1675 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1676 | uint32_t latency) |
1677 | { | |
1678 | uint64_t ret; | |
1679 | ||
3312ba65 VS |
1680 | if (WARN(latency == 0, "Latency value missing\n")) |
1681 | return UINT_MAX; | |
1682 | ||
801bcfff PZ |
1683 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1684 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1685 | ||
1686 | return ret; | |
1687 | } | |
1688 | ||
37126462 | 1689 | /* latency must be in 0.1us units. */ |
23297044 | 1690 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1691 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1692 | uint32_t latency) | |
1693 | { | |
1694 | uint32_t ret; | |
1695 | ||
3312ba65 VS |
1696 | if (WARN(latency == 0, "Latency value missing\n")) |
1697 | return UINT_MAX; | |
1698 | ||
801bcfff PZ |
1699 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1700 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1701 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1702 | return ret; | |
1703 | } | |
1704 | ||
23297044 | 1705 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1706 | uint8_t bytes_per_pixel) |
1707 | { | |
1708 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1709 | } | |
1710 | ||
2791a16c PZ |
1711 | struct skl_pipe_wm_parameters { |
1712 | bool active; | |
1713 | uint32_t pipe_htotal; | |
1714 | uint32_t pixel_rate; /* in KHz */ | |
1715 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; | |
1716 | }; | |
1717 | ||
820c1980 | 1718 | struct ilk_wm_maximums { |
cca32e9a PZ |
1719 | uint16_t pri; |
1720 | uint16_t spr; | |
1721 | uint16_t cur; | |
1722 | uint16_t fbc; | |
1723 | }; | |
1724 | ||
261a27d1 MR |
1725 | /* used in computing the new watermarks state */ |
1726 | struct intel_wm_config { | |
1727 | unsigned int num_pipes_active; | |
1728 | bool sprites_enabled; | |
1729 | bool sprites_scaled; | |
1730 | }; | |
1731 | ||
37126462 VS |
1732 | /* |
1733 | * For both WM_PIPE and WM_LP. | |
1734 | * mem_value must be in 0.1us units. | |
1735 | */ | |
7221fc33 | 1736 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1737 | const struct intel_plane_state *pstate, |
cca32e9a PZ |
1738 | uint32_t mem_value, |
1739 | bool is_lp) | |
801bcfff | 1740 | { |
43d59eda | 1741 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
cca32e9a PZ |
1742 | uint32_t method1, method2; |
1743 | ||
7221fc33 | 1744 | if (!cstate->base.active || !pstate->visible) |
801bcfff PZ |
1745 | return 0; |
1746 | ||
7221fc33 | 1747 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
cca32e9a PZ |
1748 | |
1749 | if (!is_lp) | |
1750 | return method1; | |
1751 | ||
7221fc33 MR |
1752 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1753 | cstate->base.adjusted_mode.crtc_htotal, | |
43d59eda MR |
1754 | drm_rect_width(&pstate->dst), |
1755 | bpp, | |
cca32e9a PZ |
1756 | mem_value); |
1757 | ||
1758 | return min(method1, method2); | |
801bcfff PZ |
1759 | } |
1760 | ||
37126462 VS |
1761 | /* |
1762 | * For both WM_PIPE and WM_LP. | |
1763 | * mem_value must be in 0.1us units. | |
1764 | */ | |
7221fc33 | 1765 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1766 | const struct intel_plane_state *pstate, |
801bcfff PZ |
1767 | uint32_t mem_value) |
1768 | { | |
43d59eda | 1769 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
801bcfff PZ |
1770 | uint32_t method1, method2; |
1771 | ||
7221fc33 | 1772 | if (!cstate->base.active || !pstate->visible) |
801bcfff PZ |
1773 | return 0; |
1774 | ||
7221fc33 MR |
1775 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1776 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), | |
1777 | cstate->base.adjusted_mode.crtc_htotal, | |
43d59eda MR |
1778 | drm_rect_width(&pstate->dst), |
1779 | bpp, | |
801bcfff PZ |
1780 | mem_value); |
1781 | return min(method1, method2); | |
1782 | } | |
1783 | ||
37126462 VS |
1784 | /* |
1785 | * For both WM_PIPE and WM_LP. | |
1786 | * mem_value must be in 0.1us units. | |
1787 | */ | |
7221fc33 | 1788 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1789 | const struct intel_plane_state *pstate, |
801bcfff PZ |
1790 | uint32_t mem_value) |
1791 | { | |
43d59eda MR |
1792 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1793 | ||
7221fc33 | 1794 | if (!cstate->base.active || !pstate->visible) |
801bcfff PZ |
1795 | return 0; |
1796 | ||
7221fc33 MR |
1797 | return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1798 | cstate->base.adjusted_mode.crtc_htotal, | |
43d59eda MR |
1799 | drm_rect_width(&pstate->dst), |
1800 | bpp, | |
801bcfff PZ |
1801 | mem_value); |
1802 | } | |
1803 | ||
cca32e9a | 1804 | /* Only for WM_LP. */ |
7221fc33 | 1805 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1806 | const struct intel_plane_state *pstate, |
1fda9882 | 1807 | uint32_t pri_val) |
cca32e9a | 1808 | { |
43d59eda MR |
1809 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1810 | ||
7221fc33 | 1811 | if (!cstate->base.active || !pstate->visible) |
cca32e9a PZ |
1812 | return 0; |
1813 | ||
43d59eda | 1814 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); |
cca32e9a PZ |
1815 | } |
1816 | ||
158ae64f VS |
1817 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1818 | { | |
416f4727 VS |
1819 | if (INTEL_INFO(dev)->gen >= 8) |
1820 | return 3072; | |
1821 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1822 | return 768; |
1823 | else | |
1824 | return 512; | |
1825 | } | |
1826 | ||
4e975081 VS |
1827 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1828 | int level, bool is_sprite) | |
1829 | { | |
1830 | if (INTEL_INFO(dev)->gen >= 8) | |
1831 | /* BDW primary/sprite plane watermarks */ | |
1832 | return level == 0 ? 255 : 2047; | |
1833 | else if (INTEL_INFO(dev)->gen >= 7) | |
1834 | /* IVB/HSW primary/sprite plane watermarks */ | |
1835 | return level == 0 ? 127 : 1023; | |
1836 | else if (!is_sprite) | |
1837 | /* ILK/SNB primary plane watermarks */ | |
1838 | return level == 0 ? 127 : 511; | |
1839 | else | |
1840 | /* ILK/SNB sprite plane watermarks */ | |
1841 | return level == 0 ? 63 : 255; | |
1842 | } | |
1843 | ||
1844 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
1845 | int level) | |
1846 | { | |
1847 | if (INTEL_INFO(dev)->gen >= 7) | |
1848 | return level == 0 ? 63 : 255; | |
1849 | else | |
1850 | return level == 0 ? 31 : 63; | |
1851 | } | |
1852 | ||
1853 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
1854 | { | |
1855 | if (INTEL_INFO(dev)->gen >= 8) | |
1856 | return 31; | |
1857 | else | |
1858 | return 15; | |
1859 | } | |
1860 | ||
158ae64f VS |
1861 | /* Calculate the maximum primary/sprite plane watermark */ |
1862 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1863 | int level, | |
240264f4 | 1864 | const struct intel_wm_config *config, |
158ae64f VS |
1865 | enum intel_ddb_partitioning ddb_partitioning, |
1866 | bool is_sprite) | |
1867 | { | |
1868 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
1869 | |
1870 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 1871 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
1872 | return 0; |
1873 | ||
1874 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 1875 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
1876 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1877 | ||
1878 | /* | |
1879 | * For some reason the non self refresh | |
1880 | * FIFO size is only half of the self | |
1881 | * refresh FIFO size on ILK/SNB. | |
1882 | */ | |
1883 | if (INTEL_INFO(dev)->gen <= 6) | |
1884 | fifo_size /= 2; | |
1885 | } | |
1886 | ||
240264f4 | 1887 | if (config->sprites_enabled) { |
158ae64f VS |
1888 | /* level 0 is always calculated with 1:1 split */ |
1889 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1890 | if (is_sprite) | |
1891 | fifo_size *= 5; | |
1892 | fifo_size /= 6; | |
1893 | } else { | |
1894 | fifo_size /= 2; | |
1895 | } | |
1896 | } | |
1897 | ||
1898 | /* clamp to max that the registers can hold */ | |
4e975081 | 1899 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
1900 | } |
1901 | ||
1902 | /* Calculate the maximum cursor plane watermark */ | |
1903 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
1904 | int level, |
1905 | const struct intel_wm_config *config) | |
158ae64f VS |
1906 | { |
1907 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 1908 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
1909 | return 64; |
1910 | ||
1911 | /* otherwise just report max that registers can hold */ | |
4e975081 | 1912 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
1913 | } |
1914 | ||
d34ff9c6 | 1915 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
1916 | int level, |
1917 | const struct intel_wm_config *config, | |
1918 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 1919 | struct ilk_wm_maximums *max) |
158ae64f | 1920 | { |
240264f4 VS |
1921 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1922 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1923 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 1924 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
1925 | } |
1926 | ||
a3cb4048 VS |
1927 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1928 | int level, | |
1929 | struct ilk_wm_maximums *max) | |
1930 | { | |
1931 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
1932 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
1933 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
1934 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1935 | } | |
1936 | ||
d9395655 | 1937 | static bool ilk_validate_wm_level(int level, |
820c1980 | 1938 | const struct ilk_wm_maximums *max, |
d9395655 | 1939 | struct intel_wm_level *result) |
a9786a11 VS |
1940 | { |
1941 | bool ret; | |
1942 | ||
1943 | /* already determined to be invalid? */ | |
1944 | if (!result->enable) | |
1945 | return false; | |
1946 | ||
1947 | result->enable = result->pri_val <= max->pri && | |
1948 | result->spr_val <= max->spr && | |
1949 | result->cur_val <= max->cur; | |
1950 | ||
1951 | ret = result->enable; | |
1952 | ||
1953 | /* | |
1954 | * HACK until we can pre-compute everything, | |
1955 | * and thus fail gracefully if LP0 watermarks | |
1956 | * are exceeded... | |
1957 | */ | |
1958 | if (level == 0 && !result->enable) { | |
1959 | if (result->pri_val > max->pri) | |
1960 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1961 | level, result->pri_val, max->pri); | |
1962 | if (result->spr_val > max->spr) | |
1963 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1964 | level, result->spr_val, max->spr); | |
1965 | if (result->cur_val > max->cur) | |
1966 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
1967 | level, result->cur_val, max->cur); | |
1968 | ||
1969 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
1970 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
1971 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
1972 | result->enable = true; | |
1973 | } | |
1974 | ||
a9786a11 VS |
1975 | return ret; |
1976 | } | |
1977 | ||
d34ff9c6 | 1978 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
43d59eda | 1979 | const struct intel_crtc *intel_crtc, |
6f5ddd17 | 1980 | int level, |
7221fc33 | 1981 | struct intel_crtc_state *cstate, |
1fd527cc | 1982 | struct intel_wm_level *result) |
6f5ddd17 | 1983 | { |
261a27d1 | 1984 | struct intel_plane *intel_plane; |
6f5ddd17 VS |
1985 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; |
1986 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
1987 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
1988 | ||
1989 | /* WM1+ latency values stored in 0.5us units */ | |
1990 | if (level > 0) { | |
1991 | pri_latency *= 5; | |
1992 | spr_latency *= 5; | |
1993 | cur_latency *= 5; | |
1994 | } | |
1995 | ||
261a27d1 MR |
1996 | for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { |
1997 | struct intel_plane_state *pstate = | |
1998 | to_intel_plane_state(intel_plane->base.state); | |
1999 | ||
2000 | switch (intel_plane->base.type) { | |
2001 | case DRM_PLANE_TYPE_PRIMARY: | |
2002 | result->pri_val = ilk_compute_pri_wm(cstate, pstate, | |
2003 | pri_latency, | |
2004 | level); | |
2005 | result->fbc_val = ilk_compute_fbc_wm(cstate, pstate, | |
2006 | result->pri_val); | |
2007 | break; | |
2008 | case DRM_PLANE_TYPE_OVERLAY: | |
2009 | result->spr_val = ilk_compute_spr_wm(cstate, pstate, | |
2010 | spr_latency); | |
2011 | break; | |
2012 | case DRM_PLANE_TYPE_CURSOR: | |
2013 | result->cur_val = ilk_compute_cur_wm(cstate, pstate, | |
2014 | cur_latency); | |
2015 | break; | |
2016 | } | |
2017 | } | |
2018 | ||
6f5ddd17 VS |
2019 | result->enable = true; |
2020 | } | |
2021 | ||
801bcfff PZ |
2022 | static uint32_t |
2023 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
2024 | { |
2025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 2026 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7c5f93b0 | 2027 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
85a02deb | 2028 | u32 linetime, ips_linetime; |
1f8eeabf | 2029 | |
3ef00284 | 2030 | if (!intel_crtc->active) |
801bcfff | 2031 | return 0; |
1011d8c4 | 2032 | |
1f8eeabf ED |
2033 | /* The WM are computed with base on how long it takes to fill a single |
2034 | * row at the given clock rate, multiplied by 8. | |
2035 | * */ | |
124abe07 VS |
2036 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2037 | adjusted_mode->crtc_clock); | |
2038 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, | |
05024da3 | 2039 | dev_priv->cdclk_freq); |
1f8eeabf | 2040 | |
801bcfff PZ |
2041 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2042 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2043 | } |
2044 | ||
2af30a5c | 2045 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
12b134df VS |
2046 | { |
2047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2048 | ||
2af30a5c PB |
2049 | if (IS_GEN9(dev)) { |
2050 | uint32_t val; | |
4f947386 | 2051 | int ret, i; |
367294be | 2052 | int level, max_level = ilk_wm_max_level(dev); |
2af30a5c PB |
2053 | |
2054 | /* read the first set of memory latencies[0:3] */ | |
2055 | val = 0; /* data0 to be programmed to 0 for first set */ | |
2056 | mutex_lock(&dev_priv->rps.hw_lock); | |
2057 | ret = sandybridge_pcode_read(dev_priv, | |
2058 | GEN9_PCODE_READ_MEM_LATENCY, | |
2059 | &val); | |
2060 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2061 | ||
2062 | if (ret) { | |
2063 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2064 | return; | |
2065 | } | |
2066 | ||
2067 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2068 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2069 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2070 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2071 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2072 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2073 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2074 | ||
2075 | /* read the second set of memory latencies[4:7] */ | |
2076 | val = 1; /* data0 to be programmed to 1 for second set */ | |
2077 | mutex_lock(&dev_priv->rps.hw_lock); | |
2078 | ret = sandybridge_pcode_read(dev_priv, | |
2079 | GEN9_PCODE_READ_MEM_LATENCY, | |
2080 | &val); | |
2081 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2082 | if (ret) { | |
2083 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2084 | return; | |
2085 | } | |
2086 | ||
2087 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2088 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2089 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2090 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2091 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2092 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2093 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2094 | ||
367294be | 2095 | /* |
6f97235b DL |
2096 | * WaWmMemoryReadLatency:skl |
2097 | * | |
367294be VK |
2098 | * punit doesn't take into account the read latency so we need |
2099 | * to add 2us to the various latency levels we retrieve from | |
2100 | * the punit. | |
2101 | * - W0 is a bit special in that it's the only level that | |
2102 | * can't be disabled if we want to have display working, so | |
2103 | * we always add 2us there. | |
2104 | * - For levels >=1, punit returns 0us latency when they are | |
2105 | * disabled, so we respect that and don't add 2us then | |
4f947386 VK |
2106 | * |
2107 | * Additionally, if a level n (n > 1) has a 0us latency, all | |
2108 | * levels m (m >= n) need to be disabled. We make sure to | |
2109 | * sanitize the values out of the punit to satisfy this | |
2110 | * requirement. | |
367294be VK |
2111 | */ |
2112 | wm[0] += 2; | |
2113 | for (level = 1; level <= max_level; level++) | |
2114 | if (wm[level] != 0) | |
2115 | wm[level] += 2; | |
4f947386 VK |
2116 | else { |
2117 | for (i = level + 1; i <= max_level; i++) | |
2118 | wm[i] = 0; | |
367294be | 2119 | |
4f947386 VK |
2120 | break; |
2121 | } | |
2af30a5c | 2122 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
2123 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2124 | ||
2125 | wm[0] = (sskpd >> 56) & 0xFF; | |
2126 | if (wm[0] == 0) | |
2127 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2128 | wm[1] = (sskpd >> 4) & 0xFF; |
2129 | wm[2] = (sskpd >> 12) & 0xFF; | |
2130 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2131 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
2132 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2133 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
2134 | ||
2135 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2136 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2137 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2138 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
2139 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2140 | uint32_t mltr = I915_READ(MLTR_ILK); | |
2141 | ||
2142 | /* ILK primary LP0 latency is 700 ns */ | |
2143 | wm[0] = 7; | |
2144 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2145 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2146 | } |
2147 | } | |
2148 | ||
53615a5e VS |
2149 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2150 | { | |
2151 | /* ILK sprite LP0 latency is 1300 ns */ | |
2152 | if (INTEL_INFO(dev)->gen == 5) | |
2153 | wm[0] = 13; | |
2154 | } | |
2155 | ||
2156 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
2157 | { | |
2158 | /* ILK cursor LP0 latency is 1300 ns */ | |
2159 | if (INTEL_INFO(dev)->gen == 5) | |
2160 | wm[0] = 13; | |
2161 | ||
2162 | /* WaDoubleCursorLP3Latency:ivb */ | |
2163 | if (IS_IVYBRIDGE(dev)) | |
2164 | wm[3] *= 2; | |
2165 | } | |
2166 | ||
546c81fd | 2167 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 2168 | { |
26ec971e | 2169 | /* how many WM levels are we expecting */ |
b6e742f6 | 2170 | if (INTEL_INFO(dev)->gen >= 9) |
2af30a5c PB |
2171 | return 7; |
2172 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
ad0d6dc4 | 2173 | return 4; |
26ec971e | 2174 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 2175 | return 3; |
26ec971e | 2176 | else |
ad0d6dc4 VS |
2177 | return 2; |
2178 | } | |
7526ed79 | 2179 | |
ad0d6dc4 VS |
2180 | static void intel_print_wm_latency(struct drm_device *dev, |
2181 | const char *name, | |
2af30a5c | 2182 | const uint16_t wm[8]) |
ad0d6dc4 VS |
2183 | { |
2184 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
2185 | |
2186 | for (level = 0; level <= max_level; level++) { | |
2187 | unsigned int latency = wm[level]; | |
2188 | ||
2189 | if (latency == 0) { | |
2190 | DRM_ERROR("%s WM%d latency not provided\n", | |
2191 | name, level); | |
2192 | continue; | |
2193 | } | |
2194 | ||
2af30a5c PB |
2195 | /* |
2196 | * - latencies are in us on gen9. | |
2197 | * - before then, WM1+ latency values are in 0.5us units | |
2198 | */ | |
2199 | if (IS_GEN9(dev)) | |
2200 | latency *= 10; | |
2201 | else if (level > 0) | |
26ec971e VS |
2202 | latency *= 5; |
2203 | ||
2204 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2205 | name, level, wm[level], | |
2206 | latency / 10, latency % 10); | |
2207 | } | |
2208 | } | |
2209 | ||
e95a2f75 VS |
2210 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2211 | uint16_t wm[5], uint16_t min) | |
2212 | { | |
2213 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
2214 | ||
2215 | if (wm[0] >= min) | |
2216 | return false; | |
2217 | ||
2218 | wm[0] = max(wm[0], min); | |
2219 | for (level = 1; level <= max_level; level++) | |
2220 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2221 | ||
2222 | return true; | |
2223 | } | |
2224 | ||
2225 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
2226 | { | |
2227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2228 | bool changed; | |
2229 | ||
2230 | /* | |
2231 | * The BIOS provided WM memory latency values are often | |
2232 | * inadequate for high resolution displays. Adjust them. | |
2233 | */ | |
2234 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2235 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2236 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2237 | ||
2238 | if (!changed) | |
2239 | return; | |
2240 | ||
2241 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
2242 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2243 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2244 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
2245 | } | |
2246 | ||
fa50ad61 | 2247 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2248 | { |
2249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2250 | ||
2251 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2252 | ||
2253 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2254 | sizeof(dev_priv->wm.pri_latency)); | |
2255 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2256 | sizeof(dev_priv->wm.pri_latency)); | |
2257 | ||
2258 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2259 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2260 | |
2261 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2262 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2263 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2264 | |
2265 | if (IS_GEN6(dev)) | |
2266 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
2267 | } |
2268 | ||
2af30a5c PB |
2269 | static void skl_setup_wm_latency(struct drm_device *dev) |
2270 | { | |
2271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2272 | ||
2273 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); | |
2274 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); | |
2275 | } | |
2276 | ||
261a27d1 MR |
2277 | static void ilk_compute_wm_config(struct drm_device *dev, |
2278 | struct intel_wm_config *config) | |
2279 | { | |
2280 | struct intel_crtc *intel_crtc; | |
2281 | ||
2282 | /* Compute the currently _active_ config */ | |
2283 | for_each_intel_crtc(dev, intel_crtc) { | |
2284 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; | |
2285 | ||
2286 | if (!wm->pipe_enabled) | |
2287 | continue; | |
2288 | ||
2289 | config->sprites_enabled |= wm->sprites_enabled; | |
2290 | config->sprites_scaled |= wm->sprites_scaled; | |
2291 | config->num_pipes_active++; | |
2292 | } | |
2293 | } | |
2294 | ||
0b2ae6d7 | 2295 | /* Compute new watermarks for the pipe */ |
261a27d1 MR |
2296 | static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate, |
2297 | struct intel_pipe_wm *pipe_wm) | |
0b2ae6d7 | 2298 | { |
261a27d1 MR |
2299 | struct drm_crtc *crtc = cstate->base.crtc; |
2300 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 2301 | const struct drm_i915_private *dev_priv = dev->dev_private; |
261a27d1 | 2302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
43d59eda MR |
2303 | struct intel_plane *intel_plane; |
2304 | struct intel_plane_state *sprstate = NULL; | |
0b2ae6d7 VS |
2305 | int level, max_level = ilk_wm_max_level(dev); |
2306 | /* LP0 watermark maximums depend on this pipe alone */ | |
2307 | struct intel_wm_config config = { | |
2308 | .num_pipes_active = 1, | |
0b2ae6d7 | 2309 | }; |
820c1980 | 2310 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2311 | |
43d59eda | 2312 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
261a27d1 MR |
2313 | if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) { |
2314 | sprstate = to_intel_plane_state(intel_plane->base.state); | |
2315 | break; | |
2316 | } | |
43d59eda MR |
2317 | } |
2318 | ||
2319 | config.sprites_enabled = sprstate->visible; | |
2320 | config.sprites_scaled = sprstate->visible && | |
2321 | (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || | |
2322 | drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); | |
2323 | ||
7221fc33 | 2324 | pipe_wm->pipe_enabled = cstate->base.active; |
261a27d1 | 2325 | pipe_wm->sprites_enabled = sprstate->visible; |
43d59eda | 2326 | pipe_wm->sprites_scaled = config.sprites_scaled; |
2a44b76b | 2327 | |
7b39a0b7 | 2328 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
43d59eda | 2329 | if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) |
7b39a0b7 VS |
2330 | max_level = 1; |
2331 | ||
2332 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
43d59eda | 2333 | if (config.sprites_scaled) |
7b39a0b7 VS |
2334 | max_level = 0; |
2335 | ||
261a27d1 | 2336 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]); |
0b2ae6d7 | 2337 | |
a42a5719 | 2338 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
261a27d1 | 2339 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 | 2340 | |
a3cb4048 VS |
2341 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2342 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2343 | ||
0b2ae6d7 | 2344 | /* At least LP0 must be valid */ |
a3cb4048 | 2345 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
261a27d1 | 2346 | return false; |
a3cb4048 VS |
2347 | |
2348 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2349 | ||
2350 | for (level = 1; level <= max_level; level++) { | |
2351 | struct intel_wm_level wm = {}; | |
2352 | ||
261a27d1 | 2353 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm); |
a3cb4048 VS |
2354 | |
2355 | /* | |
2356 | * Disable any watermark level that exceeds the | |
2357 | * register maximums since such watermarks are | |
2358 | * always invalid. | |
2359 | */ | |
2360 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2361 | break; | |
2362 | ||
2363 | pipe_wm->wm[level] = wm; | |
2364 | } | |
2365 | ||
261a27d1 | 2366 | return true; |
0b2ae6d7 VS |
2367 | } |
2368 | ||
2369 | /* | |
2370 | * Merge the watermarks from all active pipes for a specific level. | |
2371 | */ | |
2372 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2373 | int level, | |
2374 | struct intel_wm_level *ret_wm) | |
2375 | { | |
2376 | const struct intel_crtc *intel_crtc; | |
2377 | ||
d52fea5b VS |
2378 | ret_wm->enable = true; |
2379 | ||
d3fcc808 | 2380 | for_each_intel_crtc(dev, intel_crtc) { |
261a27d1 | 2381 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
fe392efd VS |
2382 | const struct intel_wm_level *wm = &active->wm[level]; |
2383 | ||
2384 | if (!active->pipe_enabled) | |
2385 | continue; | |
0b2ae6d7 | 2386 | |
d52fea5b VS |
2387 | /* |
2388 | * The watermark values may have been used in the past, | |
2389 | * so we must maintain them in the registers for some | |
2390 | * time even if the level is now disabled. | |
2391 | */ | |
0b2ae6d7 | 2392 | if (!wm->enable) |
d52fea5b | 2393 | ret_wm->enable = false; |
0b2ae6d7 VS |
2394 | |
2395 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2396 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2397 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2398 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2399 | } | |
0b2ae6d7 VS |
2400 | } |
2401 | ||
2402 | /* | |
2403 | * Merge all low power watermarks for all active pipes. | |
2404 | */ | |
2405 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2406 | const struct intel_wm_config *config, |
820c1980 | 2407 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2408 | struct intel_pipe_wm *merged) |
2409 | { | |
7733b49b | 2410 | struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 | 2411 | int level, max_level = ilk_wm_max_level(dev); |
d52fea5b | 2412 | int last_enabled_level = max_level; |
0b2ae6d7 | 2413 | |
0ba22e26 VS |
2414 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2415 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2416 | config->num_pipes_active > 1) | |
2417 | return; | |
2418 | ||
6c8b6c28 VS |
2419 | /* ILK: FBC WM must be disabled always */ |
2420 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2421 | |
2422 | /* merge each WM1+ level */ | |
2423 | for (level = 1; level <= max_level; level++) { | |
2424 | struct intel_wm_level *wm = &merged->wm[level]; | |
2425 | ||
2426 | ilk_merge_wm_level(dev, level, wm); | |
2427 | ||
d52fea5b VS |
2428 | if (level > last_enabled_level) |
2429 | wm->enable = false; | |
2430 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2431 | /* make sure all following levels get disabled */ | |
2432 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2433 | |
2434 | /* | |
2435 | * The spec says it is preferred to disable | |
2436 | * FBC WMs instead of disabling a WM level. | |
2437 | */ | |
2438 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2439 | if (wm->enable) |
2440 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2441 | wm->fbc_val = 0; |
2442 | } | |
2443 | } | |
6c8b6c28 VS |
2444 | |
2445 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2446 | /* | |
2447 | * FIXME this is racy. FBC might get enabled later. | |
2448 | * What we should check here is whether FBC can be | |
2449 | * enabled sometime later. | |
2450 | */ | |
7733b49b PZ |
2451 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && |
2452 | intel_fbc_enabled(dev_priv)) { | |
6c8b6c28 VS |
2453 | for (level = 2; level <= max_level; level++) { |
2454 | struct intel_wm_level *wm = &merged->wm[level]; | |
2455 | ||
2456 | wm->enable = false; | |
2457 | } | |
2458 | } | |
0b2ae6d7 VS |
2459 | } |
2460 | ||
b380ca3c VS |
2461 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2462 | { | |
2463 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2464 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2465 | } | |
2466 | ||
a68d68ee VS |
2467 | /* The value we need to program into the WM_LPx latency field */ |
2468 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2469 | { | |
2470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2471 | ||
a42a5719 | 2472 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2473 | return 2 * level; |
2474 | else | |
2475 | return dev_priv->wm.pri_latency[level]; | |
2476 | } | |
2477 | ||
820c1980 | 2478 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2479 | const struct intel_pipe_wm *merged, |
609cedef | 2480 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2481 | struct ilk_wm_values *results) |
801bcfff | 2482 | { |
0b2ae6d7 VS |
2483 | struct intel_crtc *intel_crtc; |
2484 | int level, wm_lp; | |
cca32e9a | 2485 | |
0362c781 | 2486 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2487 | results->partitioning = partitioning; |
cca32e9a | 2488 | |
0b2ae6d7 | 2489 | /* LP1+ register values */ |
cca32e9a | 2490 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2491 | const struct intel_wm_level *r; |
801bcfff | 2492 | |
b380ca3c | 2493 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2494 | |
0362c781 | 2495 | r = &merged->wm[level]; |
cca32e9a | 2496 | |
d52fea5b VS |
2497 | /* |
2498 | * Maintain the watermark values even if the level is | |
2499 | * disabled. Doing otherwise could cause underruns. | |
2500 | */ | |
2501 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2502 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2503 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2504 | r->cur_val; | |
2505 | ||
d52fea5b VS |
2506 | if (r->enable) |
2507 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2508 | ||
416f4727 VS |
2509 | if (INTEL_INFO(dev)->gen >= 8) |
2510 | results->wm_lp[wm_lp - 1] |= | |
2511 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2512 | else | |
2513 | results->wm_lp[wm_lp - 1] |= | |
2514 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2515 | ||
d52fea5b VS |
2516 | /* |
2517 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2518 | * level is disabled. Doing otherwise could cause underruns. | |
2519 | */ | |
6cef2b8a VS |
2520 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2521 | WARN_ON(wm_lp != 1); | |
2522 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2523 | } else | |
2524 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2525 | } |
801bcfff | 2526 | |
0b2ae6d7 | 2527 | /* LP0 register values */ |
d3fcc808 | 2528 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 | 2529 | enum pipe pipe = intel_crtc->pipe; |
261a27d1 MR |
2530 | const struct intel_wm_level *r = |
2531 | &intel_crtc->wm.active.wm[0]; | |
0b2ae6d7 VS |
2532 | |
2533 | if (WARN_ON(!r->enable)) | |
2534 | continue; | |
2535 | ||
261a27d1 | 2536 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; |
1011d8c4 | 2537 | |
0b2ae6d7 VS |
2538 | results->wm_pipe[pipe] = |
2539 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2540 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2541 | r->cur_val; | |
801bcfff PZ |
2542 | } |
2543 | } | |
2544 | ||
861f3389 PZ |
2545 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2546 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2547 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2548 | struct intel_pipe_wm *r1, |
2549 | struct intel_pipe_wm *r2) | |
861f3389 | 2550 | { |
198a1e9b VS |
2551 | int level, max_level = ilk_wm_max_level(dev); |
2552 | int level1 = 0, level2 = 0; | |
861f3389 | 2553 | |
198a1e9b VS |
2554 | for (level = 1; level <= max_level; level++) { |
2555 | if (r1->wm[level].enable) | |
2556 | level1 = level; | |
2557 | if (r2->wm[level].enable) | |
2558 | level2 = level; | |
861f3389 PZ |
2559 | } |
2560 | ||
198a1e9b VS |
2561 | if (level1 == level2) { |
2562 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2563 | return r2; |
2564 | else | |
2565 | return r1; | |
198a1e9b | 2566 | } else if (level1 > level2) { |
861f3389 PZ |
2567 | return r1; |
2568 | } else { | |
2569 | return r2; | |
2570 | } | |
2571 | } | |
2572 | ||
49a687c4 VS |
2573 | /* dirty bits used to track which watermarks need changes */ |
2574 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2575 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2576 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2577 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2578 | #define WM_DIRTY_FBC (1 << 24) | |
2579 | #define WM_DIRTY_DDB (1 << 25) | |
2580 | ||
055e393f | 2581 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2582 | const struct ilk_wm_values *old, |
2583 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2584 | { |
2585 | unsigned int dirty = 0; | |
2586 | enum pipe pipe; | |
2587 | int wm_lp; | |
2588 | ||
055e393f | 2589 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2590 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2591 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2592 | /* Must disable LP1+ watermarks too */ | |
2593 | dirty |= WM_DIRTY_LP_ALL; | |
2594 | } | |
2595 | ||
2596 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2597 | dirty |= WM_DIRTY_PIPE(pipe); | |
2598 | /* Must disable LP1+ watermarks too */ | |
2599 | dirty |= WM_DIRTY_LP_ALL; | |
2600 | } | |
2601 | } | |
2602 | ||
2603 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2604 | dirty |= WM_DIRTY_FBC; | |
2605 | /* Must disable LP1+ watermarks too */ | |
2606 | dirty |= WM_DIRTY_LP_ALL; | |
2607 | } | |
2608 | ||
2609 | if (old->partitioning != new->partitioning) { | |
2610 | dirty |= WM_DIRTY_DDB; | |
2611 | /* Must disable LP1+ watermarks too */ | |
2612 | dirty |= WM_DIRTY_LP_ALL; | |
2613 | } | |
2614 | ||
2615 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2616 | if (dirty & WM_DIRTY_LP_ALL) | |
2617 | return dirty; | |
2618 | ||
2619 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2620 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2621 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2622 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2623 | break; | |
2624 | } | |
2625 | ||
2626 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2627 | for (; wm_lp <= 3; wm_lp++) | |
2628 | dirty |= WM_DIRTY_LP(wm_lp); | |
2629 | ||
2630 | return dirty; | |
2631 | } | |
2632 | ||
8553c18e VS |
2633 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2634 | unsigned int dirty) | |
801bcfff | 2635 | { |
820c1980 | 2636 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2637 | bool changed = false; |
801bcfff | 2638 | |
facd619b VS |
2639 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2640 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2641 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2642 | changed = true; |
facd619b VS |
2643 | } |
2644 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2645 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2646 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2647 | changed = true; |
facd619b VS |
2648 | } |
2649 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2650 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2651 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2652 | changed = true; |
facd619b | 2653 | } |
801bcfff | 2654 | |
facd619b VS |
2655 | /* |
2656 | * Don't touch WM1S_LP_EN here. | |
2657 | * Doing so could cause underruns. | |
2658 | */ | |
6cef2b8a | 2659 | |
8553c18e VS |
2660 | return changed; |
2661 | } | |
2662 | ||
2663 | /* | |
2664 | * The spec says we shouldn't write when we don't need, because every write | |
2665 | * causes WMs to be re-evaluated, expending some power. | |
2666 | */ | |
820c1980 ID |
2667 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2668 | struct ilk_wm_values *results) | |
8553c18e VS |
2669 | { |
2670 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2671 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2672 | unsigned int dirty; |
2673 | uint32_t val; | |
2674 | ||
055e393f | 2675 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2676 | if (!dirty) |
2677 | return; | |
2678 | ||
2679 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2680 | ||
49a687c4 | 2681 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2682 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2683 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2684 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2685 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2686 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2687 | ||
49a687c4 | 2688 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2689 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2690 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2691 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2692 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2693 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2694 | ||
49a687c4 | 2695 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2696 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2697 | val = I915_READ(WM_MISC); |
2698 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2699 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2700 | else | |
2701 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2702 | I915_WRITE(WM_MISC, val); | |
2703 | } else { | |
2704 | val = I915_READ(DISP_ARB_CTL2); | |
2705 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2706 | val &= ~DISP_DATA_PARTITION_5_6; | |
2707 | else | |
2708 | val |= DISP_DATA_PARTITION_5_6; | |
2709 | I915_WRITE(DISP_ARB_CTL2, val); | |
2710 | } | |
1011d8c4 PZ |
2711 | } |
2712 | ||
49a687c4 | 2713 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2714 | val = I915_READ(DISP_ARB_CTL); |
2715 | if (results->enable_fbc_wm) | |
2716 | val &= ~DISP_FBC_WM_DIS; | |
2717 | else | |
2718 | val |= DISP_FBC_WM_DIS; | |
2719 | I915_WRITE(DISP_ARB_CTL, val); | |
2720 | } | |
2721 | ||
954911eb ID |
2722 | if (dirty & WM_DIRTY_LP(1) && |
2723 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2724 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2725 | ||
2726 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2727 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2728 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2729 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2730 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2731 | } | |
801bcfff | 2732 | |
facd619b | 2733 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2734 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2735 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2736 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2737 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2738 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2739 | |
2740 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2741 | } |
2742 | ||
8553c18e VS |
2743 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2744 | { | |
2745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2746 | ||
2747 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2748 | } | |
2749 | ||
b9cec075 DL |
2750 | /* |
2751 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the | |
2752 | * different active planes. | |
2753 | */ | |
2754 | ||
2755 | #define SKL_DDB_SIZE 896 /* in blocks */ | |
43d735a6 | 2756 | #define BXT_DDB_SIZE 512 |
b9cec075 DL |
2757 | |
2758 | static void | |
2759 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
2791a16c | 2760 | struct drm_crtc *for_crtc, |
b9cec075 | 2761 | const struct intel_wm_config *config, |
2791a16c | 2762 | const struct skl_pipe_wm_parameters *params, |
b9cec075 DL |
2763 | struct skl_ddb_entry *alloc /* out */) |
2764 | { | |
2765 | struct drm_crtc *crtc; | |
2766 | unsigned int pipe_size, ddb_size; | |
2767 | int nth_active_pipe; | |
2768 | ||
2791a16c | 2769 | if (!params->active) { |
b9cec075 DL |
2770 | alloc->start = 0; |
2771 | alloc->end = 0; | |
2772 | return; | |
2773 | } | |
2774 | ||
43d735a6 DL |
2775 | if (IS_BROXTON(dev)) |
2776 | ddb_size = BXT_DDB_SIZE; | |
2777 | else | |
2778 | ddb_size = SKL_DDB_SIZE; | |
b9cec075 DL |
2779 | |
2780 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
2781 | ||
2782 | nth_active_pipe = 0; | |
2783 | for_each_crtc(dev, crtc) { | |
3ef00284 | 2784 | if (!to_intel_crtc(crtc)->active) |
b9cec075 DL |
2785 | continue; |
2786 | ||
2787 | if (crtc == for_crtc) | |
2788 | break; | |
2789 | ||
2790 | nth_active_pipe++; | |
2791 | } | |
2792 | ||
2793 | pipe_size = ddb_size / config->num_pipes_active; | |
2794 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; | |
16160e3d | 2795 | alloc->end = alloc->start + pipe_size; |
b9cec075 DL |
2796 | } |
2797 | ||
2798 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) | |
2799 | { | |
2800 | if (config->num_pipes_active == 1) | |
2801 | return 32; | |
2802 | ||
2803 | return 8; | |
2804 | } | |
2805 | ||
a269c583 DL |
2806 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
2807 | { | |
2808 | entry->start = reg & 0x3ff; | |
2809 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
2810 | if (entry->end) |
2811 | entry->end += 1; | |
a269c583 DL |
2812 | } |
2813 | ||
08db6652 DL |
2814 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2815 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 2816 | { |
a269c583 DL |
2817 | enum pipe pipe; |
2818 | int plane; | |
2819 | u32 val; | |
2820 | ||
2821 | for_each_pipe(dev_priv, pipe) { | |
dd740780 | 2822 | for_each_plane(dev_priv, pipe, plane) { |
a269c583 DL |
2823 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
2824 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], | |
2825 | val); | |
2826 | } | |
2827 | ||
2828 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
4969d33e MR |
2829 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], |
2830 | val); | |
a269c583 DL |
2831 | } |
2832 | } | |
2833 | ||
b9cec075 | 2834 | static unsigned int |
2791a16c | 2835 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) |
b9cec075 | 2836 | { |
2cd601c6 CK |
2837 | |
2838 | /* for planar format */ | |
2791a16c | 2839 | if (p->y_bytes_per_pixel) { |
2cd601c6 | 2840 | if (y) /* y-plane data rate */ |
2791a16c | 2841 | return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; |
2cd601c6 | 2842 | else /* uv-plane data rate */ |
2791a16c | 2843 | return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; |
2cd601c6 CK |
2844 | } |
2845 | ||
2846 | /* for packed formats */ | |
2791a16c | 2847 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; |
b9cec075 DL |
2848 | } |
2849 | ||
2850 | /* | |
2851 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
2852 | * a 8192x4096@32bpp framebuffer: | |
2853 | * 3 * 4096 * 8192 * 4 < 2^32 | |
2854 | */ | |
2855 | static unsigned int | |
2791a16c PZ |
2856 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, |
2857 | const struct skl_pipe_wm_parameters *params) | |
b9cec075 DL |
2858 | { |
2859 | unsigned int total_data_rate = 0; | |
2791a16c | 2860 | int plane; |
b9cec075 | 2861 | |
2791a16c PZ |
2862 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
2863 | const struct intel_plane_wm_parameters *p; | |
b9cec075 | 2864 | |
2791a16c PZ |
2865 | p = ¶ms->plane[plane]; |
2866 | if (!p->enabled) | |
b9cec075 DL |
2867 | continue; |
2868 | ||
2791a16c PZ |
2869 | total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ |
2870 | if (p->y_bytes_per_pixel) { | |
2871 | total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ | |
2872 | } | |
b9cec075 DL |
2873 | } |
2874 | ||
2875 | return total_data_rate; | |
2876 | } | |
2877 | ||
2878 | static void | |
2791a16c | 2879 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, |
261a27d1 | 2880 | const struct intel_wm_config *config, |
2791a16c | 2881 | const struct skl_pipe_wm_parameters *params, |
b9cec075 DL |
2882 | struct skl_ddb_allocation *ddb /* out */) |
2883 | { | |
2884 | struct drm_device *dev = crtc->dev; | |
2791a16c | 2885 | struct drm_i915_private *dev_priv = dev->dev_private; |
b9cec075 DL |
2886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2887 | enum pipe pipe = intel_crtc->pipe; | |
34bb56af | 2888 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
b9cec075 | 2889 | uint16_t alloc_size, start, cursor_blocks; |
80958155 | 2890 | uint16_t minimum[I915_MAX_PLANES]; |
2cd601c6 | 2891 | uint16_t y_minimum[I915_MAX_PLANES]; |
b9cec075 | 2892 | unsigned int total_data_rate; |
2791a16c | 2893 | int plane; |
b9cec075 | 2894 | |
2791a16c | 2895 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); |
34bb56af | 2896 | alloc_size = skl_ddb_entry_size(alloc); |
b9cec075 DL |
2897 | if (alloc_size == 0) { |
2898 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
4969d33e MR |
2899 | memset(&ddb->plane[pipe][PLANE_CURSOR], 0, |
2900 | sizeof(ddb->plane[pipe][PLANE_CURSOR])); | |
b9cec075 DL |
2901 | return; |
2902 | } | |
2903 | ||
2904 | cursor_blocks = skl_cursor_allocation(config); | |
4969d33e MR |
2905 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; |
2906 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; | |
b9cec075 DL |
2907 | |
2908 | alloc_size -= cursor_blocks; | |
34bb56af | 2909 | alloc->end -= cursor_blocks; |
b9cec075 | 2910 | |
80958155 | 2911 | /* 1. Allocate the mininum required blocks for each active plane */ |
2791a16c PZ |
2912 | for_each_plane(dev_priv, pipe, plane) { |
2913 | const struct intel_plane_wm_parameters *p; | |
80958155 | 2914 | |
2791a16c PZ |
2915 | p = ¶ms->plane[plane]; |
2916 | if (!p->enabled) | |
80958155 DL |
2917 | continue; |
2918 | ||
2791a16c PZ |
2919 | minimum[plane] = 8; |
2920 | alloc_size -= minimum[plane]; | |
2921 | y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; | |
2922 | alloc_size -= y_minimum[plane]; | |
80958155 DL |
2923 | } |
2924 | ||
b9cec075 | 2925 | /* |
80958155 DL |
2926 | * 2. Distribute the remaining space in proportion to the amount of |
2927 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
2928 | * |
2929 | * FIXME: we may not allocate every single block here. | |
2930 | */ | |
2791a16c | 2931 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); |
b9cec075 | 2932 | |
34bb56af | 2933 | start = alloc->start; |
2791a16c PZ |
2934 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
2935 | const struct intel_plane_wm_parameters *p; | |
2cd601c6 CK |
2936 | unsigned int data_rate, y_data_rate; |
2937 | uint16_t plane_blocks, y_plane_blocks = 0; | |
b9cec075 | 2938 | |
2791a16c PZ |
2939 | p = ¶ms->plane[plane]; |
2940 | if (!p->enabled) | |
b9cec075 DL |
2941 | continue; |
2942 | ||
2791a16c | 2943 | data_rate = skl_plane_relative_data_rate(p, 0); |
b9cec075 DL |
2944 | |
2945 | /* | |
2cd601c6 | 2946 | * allocation for (packed formats) or (uv-plane part of planar format): |
b9cec075 DL |
2947 | * promote the expression to 64 bits to avoid overflowing, the |
2948 | * result is < available as data_rate / total_data_rate < 1 | |
2949 | */ | |
2791a16c | 2950 | plane_blocks = minimum[plane]; |
80958155 DL |
2951 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
2952 | total_data_rate); | |
b9cec075 | 2953 | |
2791a16c PZ |
2954 | ddb->plane[pipe][plane].start = start; |
2955 | ddb->plane[pipe][plane].end = start + plane_blocks; | |
b9cec075 DL |
2956 | |
2957 | start += plane_blocks; | |
2cd601c6 CK |
2958 | |
2959 | /* | |
2960 | * allocation for y_plane part of planar format: | |
2961 | */ | |
2791a16c PZ |
2962 | if (p->y_bytes_per_pixel) { |
2963 | y_data_rate = skl_plane_relative_data_rate(p, 1); | |
2964 | y_plane_blocks = y_minimum[plane]; | |
2cd601c6 CK |
2965 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
2966 | total_data_rate); | |
2967 | ||
2791a16c PZ |
2968 | ddb->y_plane[pipe][plane].start = start; |
2969 | ddb->y_plane[pipe][plane].end = start + y_plane_blocks; | |
2cd601c6 CK |
2970 | |
2971 | start += y_plane_blocks; | |
2972 | } | |
2973 | ||
b9cec075 DL |
2974 | } |
2975 | ||
2976 | } | |
2977 | ||
5cec258b | 2978 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
2d41c0b5 PB |
2979 | { |
2980 | /* TODO: Take into account the scalers once we support them */ | |
2d112de7 | 2981 | return config->base.adjusted_mode.crtc_clock; |
2d41c0b5 PB |
2982 | } |
2983 | ||
2984 | /* | |
2985 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
2986 | * for the read latency) and bytes_per_pixel should always be <= 8, so that | |
2987 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max | |
2988 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
2989 | */ | |
2990 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
2991 | uint32_t latency) | |
2992 | { | |
2993 | uint32_t wm_intermediate_val, ret; | |
2994 | ||
2995 | if (latency == 0) | |
2996 | return UINT_MAX; | |
2997 | ||
d4c2aa60 | 2998 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
2d41c0b5 PB |
2999 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
3000 | ||
3001 | return ret; | |
3002 | } | |
3003 | ||
3004 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
3005 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
0fda6568 | 3006 | uint64_t tiling, uint32_t latency) |
2d41c0b5 | 3007 | { |
d4c2aa60 TU |
3008 | uint32_t ret; |
3009 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
3010 | uint32_t wm_intermediate_val; | |
2d41c0b5 PB |
3011 | |
3012 | if (latency == 0) | |
3013 | return UINT_MAX; | |
3014 | ||
3015 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; | |
0fda6568 TU |
3016 | |
3017 | if (tiling == I915_FORMAT_MOD_Y_TILED || | |
3018 | tiling == I915_FORMAT_MOD_Yf_TILED) { | |
3019 | plane_bytes_per_line *= 4; | |
3020 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
3021 | plane_blocks_per_line /= 4; | |
3022 | } else { | |
3023 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
3024 | } | |
3025 | ||
2d41c0b5 PB |
3026 | wm_intermediate_val = latency * pixel_rate; |
3027 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * | |
d4c2aa60 | 3028 | plane_blocks_per_line; |
2d41c0b5 PB |
3029 | |
3030 | return ret; | |
3031 | } | |
3032 | ||
2d41c0b5 PB |
3033 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
3034 | const struct intel_crtc *intel_crtc) | |
3035 | { | |
3036 | struct drm_device *dev = intel_crtc->base.dev; | |
3037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3038 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3039 | enum pipe pipe = intel_crtc->pipe; | |
3040 | ||
3041 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], | |
3042 | sizeof(new_ddb->plane[pipe]))) | |
3043 | return true; | |
3044 | ||
4969d33e MR |
3045 | if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], |
3046 | sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) | |
2d41c0b5 PB |
3047 | return true; |
3048 | ||
3049 | return false; | |
3050 | } | |
3051 | ||
261a27d1 MR |
3052 | static void skl_compute_wm_global_parameters(struct drm_device *dev, |
3053 | struct intel_wm_config *config) | |
3054 | { | |
3055 | struct drm_crtc *crtc; | |
2791a16c | 3056 | struct drm_plane *plane; |
261a27d1 MR |
3057 | |
3058 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
3059 | config->num_pipes_active += to_intel_crtc(crtc)->active; | |
2791a16c PZ |
3060 | |
3061 | /* FIXME: I don't think we need those two global parameters on SKL */ | |
3062 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
3063 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3064 | ||
3065 | config->sprites_enabled |= intel_plane->wm.enabled; | |
3066 | config->sprites_scaled |= intel_plane->wm.scaled; | |
3067 | } | |
3068 | } | |
3069 | ||
3070 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, | |
3071 | struct skl_pipe_wm_parameters *p) | |
3072 | { | |
3073 | struct drm_device *dev = crtc->dev; | |
3074 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3075 | enum pipe pipe = intel_crtc->pipe; | |
3076 | struct drm_plane *plane; | |
3077 | struct drm_framebuffer *fb; | |
3078 | int i = 1; /* Index for sprite planes start */ | |
3079 | ||
3080 | p->active = intel_crtc->active; | |
3081 | if (p->active) { | |
3082 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; | |
3083 | p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); | |
3084 | ||
3085 | fb = crtc->primary->state->fb; | |
3086 | /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ | |
3087 | if (fb) { | |
3088 | p->plane[0].enabled = true; | |
3089 | p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? | |
3090 | drm_format_plane_cpp(fb->pixel_format, 1) : | |
3091 | drm_format_plane_cpp(fb->pixel_format, 0); | |
3092 | p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? | |
3093 | drm_format_plane_cpp(fb->pixel_format, 0) : 0; | |
3094 | p->plane[0].tiling = fb->modifier[0]; | |
3095 | } else { | |
3096 | p->plane[0].enabled = false; | |
3097 | p->plane[0].bytes_per_pixel = 0; | |
3098 | p->plane[0].y_bytes_per_pixel = 0; | |
3099 | p->plane[0].tiling = DRM_FORMAT_MOD_NONE; | |
3100 | } | |
3101 | p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; | |
3102 | p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; | |
3103 | p->plane[0].rotation = crtc->primary->state->rotation; | |
3104 | ||
3105 | fb = crtc->cursor->state->fb; | |
3106 | p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0; | |
3107 | if (fb) { | |
3108 | p->plane[PLANE_CURSOR].enabled = true; | |
3109 | p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8; | |
3110 | p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w; | |
3111 | p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h; | |
3112 | } else { | |
3113 | p->plane[PLANE_CURSOR].enabled = false; | |
3114 | p->plane[PLANE_CURSOR].bytes_per_pixel = 0; | |
3115 | p->plane[PLANE_CURSOR].horiz_pixels = 64; | |
3116 | p->plane[PLANE_CURSOR].vert_pixels = 64; | |
3117 | } | |
3118 | } | |
3119 | ||
3120 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
3121 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3122 | ||
3123 | if (intel_plane->pipe == pipe && | |
3124 | plane->type == DRM_PLANE_TYPE_OVERLAY) | |
3125 | p->plane[i++] = intel_plane->wm; | |
3126 | } | |
261a27d1 MR |
3127 | } |
3128 | ||
d4c2aa60 | 3129 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
2791a16c PZ |
3130 | struct skl_pipe_wm_parameters *p, |
3131 | struct intel_plane_wm_parameters *p_params, | |
afb024aa | 3132 | uint16_t ddb_allocation, |
d4c2aa60 | 3133 | int level, |
afb024aa DL |
3134 | uint16_t *out_blocks, /* out */ |
3135 | uint8_t *out_lines /* out */) | |
2d41c0b5 | 3136 | { |
d4c2aa60 TU |
3137 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
3138 | uint32_t method1, method2; | |
3139 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
3140 | uint32_t res_blocks, res_lines; | |
3141 | uint32_t selected_result; | |
2cd601c6 | 3142 | uint8_t bytes_per_pixel; |
2d41c0b5 | 3143 | |
2791a16c | 3144 | if (latency == 0 || !p->active || !p_params->enabled) |
2d41c0b5 PB |
3145 | return false; |
3146 | ||
2791a16c PZ |
3147 | bytes_per_pixel = p_params->y_bytes_per_pixel ? |
3148 | p_params->y_bytes_per_pixel : | |
3149 | p_params->bytes_per_pixel; | |
3150 | method1 = skl_wm_method1(p->pixel_rate, | |
2cd601c6 | 3151 | bytes_per_pixel, |
d4c2aa60 | 3152 | latency); |
2791a16c PZ |
3153 | method2 = skl_wm_method2(p->pixel_rate, |
3154 | p->pipe_htotal, | |
3155 | p_params->horiz_pixels, | |
2cd601c6 | 3156 | bytes_per_pixel, |
2791a16c | 3157 | p_params->tiling, |
d4c2aa60 | 3158 | latency); |
2d41c0b5 | 3159 | |
2791a16c | 3160 | plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; |
d4c2aa60 | 3161 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
2d41c0b5 | 3162 | |
2791a16c PZ |
3163 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || |
3164 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { | |
1fc0a8f7 TU |
3165 | uint32_t min_scanlines = 4; |
3166 | uint32_t y_tile_minimum; | |
2791a16c PZ |
3167 | if (intel_rotation_90_or_270(p_params->rotation)) { |
3168 | switch (p_params->bytes_per_pixel) { | |
1fc0a8f7 TU |
3169 | case 1: |
3170 | min_scanlines = 16; | |
3171 | break; | |
3172 | case 2: | |
3173 | min_scanlines = 8; | |
3174 | break; | |
3175 | case 8: | |
3176 | WARN(1, "Unsupported pixel depth for rotation"); | |
2f0b5790 | 3177 | } |
1fc0a8f7 TU |
3178 | } |
3179 | y_tile_minimum = plane_blocks_per_line * min_scanlines; | |
0fda6568 TU |
3180 | selected_result = max(method2, y_tile_minimum); |
3181 | } else { | |
3182 | if ((ddb_allocation / plane_blocks_per_line) >= 1) | |
3183 | selected_result = min(method1, method2); | |
3184 | else | |
3185 | selected_result = method1; | |
3186 | } | |
2d41c0b5 | 3187 | |
d4c2aa60 TU |
3188 | res_blocks = selected_result + 1; |
3189 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); | |
e6d66171 | 3190 | |
0fda6568 | 3191 | if (level >= 1 && level <= 7) { |
2791a16c PZ |
3192 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || |
3193 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) | |
0fda6568 TU |
3194 | res_lines += 4; |
3195 | else | |
3196 | res_blocks++; | |
3197 | } | |
e6d66171 | 3198 | |
d4c2aa60 | 3199 | if (res_blocks >= ddb_allocation || res_lines > 31) |
e6d66171 DL |
3200 | return false; |
3201 | ||
3202 | *out_blocks = res_blocks; | |
3203 | *out_lines = res_lines; | |
2d41c0b5 PB |
3204 | |
3205 | return true; | |
3206 | } | |
3207 | ||
3208 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
3209 | struct skl_ddb_allocation *ddb, | |
2791a16c PZ |
3210 | struct skl_pipe_wm_parameters *p, |
3211 | enum pipe pipe, | |
2d41c0b5 | 3212 | int level, |
2791a16c | 3213 | int num_planes, |
2d41c0b5 PB |
3214 | struct skl_wm_level *result) |
3215 | { | |
2d41c0b5 | 3216 | uint16_t ddb_blocks; |
2791a16c | 3217 | int i; |
2d41c0b5 | 3218 | |
2791a16c | 3219 | for (i = 0; i < num_planes; i++) { |
2d41c0b5 PB |
3220 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); |
3221 | ||
d4c2aa60 | 3222 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
2791a16c | 3223 | p, &p->plane[i], |
2d41c0b5 | 3224 | ddb_blocks, |
d4c2aa60 | 3225 | level, |
2d41c0b5 PB |
3226 | &result->plane_res_b[i], |
3227 | &result->plane_res_l[i]); | |
3228 | } | |
2791a16c PZ |
3229 | |
3230 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]); | |
3231 | result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p, | |
3232 | &p->plane[PLANE_CURSOR], | |
3233 | ddb_blocks, level, | |
3234 | &result->plane_res_b[PLANE_CURSOR], | |
3235 | &result->plane_res_l[PLANE_CURSOR]); | |
2d41c0b5 PB |
3236 | } |
3237 | ||
407b50f3 | 3238 | static uint32_t |
2791a16c | 3239 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) |
407b50f3 | 3240 | { |
2791a16c | 3241 | if (!to_intel_crtc(crtc)->active) |
407b50f3 DL |
3242 | return 0; |
3243 | ||
2791a16c | 3244 | if (WARN_ON(p->pixel_rate == 0)) |
661abfc0 | 3245 | return 0; |
407b50f3 | 3246 | |
2791a16c | 3247 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); |
407b50f3 DL |
3248 | } |
3249 | ||
2791a16c PZ |
3250 | static void skl_compute_transition_wm(struct drm_crtc *crtc, |
3251 | struct skl_pipe_wm_parameters *params, | |
9414f563 | 3252 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 3253 | { |
9414f563 | 3254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2791a16c | 3255 | int i; |
9414f563 | 3256 | |
2791a16c | 3257 | if (!params->active) |
407b50f3 | 3258 | return; |
9414f563 DL |
3259 | |
3260 | /* Until we know more, just disable transition WMs */ | |
2791a16c | 3261 | for (i = 0; i < intel_num_planes(intel_crtc); i++) |
9414f563 | 3262 | trans_wm->plane_en[i] = false; |
2791a16c | 3263 | trans_wm->plane_en[PLANE_CURSOR] = false; |
407b50f3 DL |
3264 | } |
3265 | ||
2791a16c | 3266 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, |
2d41c0b5 | 3267 | struct skl_ddb_allocation *ddb, |
2791a16c | 3268 | struct skl_pipe_wm_parameters *params, |
2d41c0b5 PB |
3269 | struct skl_pipe_wm *pipe_wm) |
3270 | { | |
2791a16c | 3271 | struct drm_device *dev = crtc->dev; |
2d41c0b5 | 3272 | const struct drm_i915_private *dev_priv = dev->dev_private; |
2791a16c | 3273 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2d41c0b5 PB |
3274 | int level, max_level = ilk_wm_max_level(dev); |
3275 | ||
3276 | for (level = 0; level <= max_level; level++) { | |
2791a16c PZ |
3277 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, |
3278 | level, intel_num_planes(intel_crtc), | |
3279 | &pipe_wm->wm[level]); | |
2d41c0b5 | 3280 | } |
2791a16c | 3281 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); |
2d41c0b5 | 3282 | |
2791a16c | 3283 | skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); |
2d41c0b5 PB |
3284 | } |
3285 | ||
3286 | static void skl_compute_wm_results(struct drm_device *dev, | |
2791a16c | 3287 | struct skl_pipe_wm_parameters *p, |
2d41c0b5 PB |
3288 | struct skl_pipe_wm *p_wm, |
3289 | struct skl_wm_values *r, | |
3290 | struct intel_crtc *intel_crtc) | |
3291 | { | |
3292 | int level, max_level = ilk_wm_max_level(dev); | |
3293 | enum pipe pipe = intel_crtc->pipe; | |
9414f563 DL |
3294 | uint32_t temp; |
3295 | int i; | |
2d41c0b5 PB |
3296 | |
3297 | for (level = 0; level <= max_level; level++) { | |
2d41c0b5 PB |
3298 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3299 | temp = 0; | |
2d41c0b5 PB |
3300 | |
3301 | temp |= p_wm->wm[level].plane_res_l[i] << | |
3302 | PLANE_WM_LINES_SHIFT; | |
3303 | temp |= p_wm->wm[level].plane_res_b[i]; | |
3304 | if (p_wm->wm[level].plane_en[i]) | |
3305 | temp |= PLANE_WM_EN; | |
3306 | ||
3307 | r->plane[pipe][i][level] = temp; | |
2d41c0b5 PB |
3308 | } |
3309 | ||
3310 | temp = 0; | |
2d41c0b5 | 3311 | |
4969d33e MR |
3312 | temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3313 | temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; | |
2d41c0b5 | 3314 | |
4969d33e | 3315 | if (p_wm->wm[level].plane_en[PLANE_CURSOR]) |
2d41c0b5 PB |
3316 | temp |= PLANE_WM_EN; |
3317 | ||
4969d33e | 3318 | r->plane[pipe][PLANE_CURSOR][level] = temp; |
2d41c0b5 PB |
3319 | |
3320 | } | |
3321 | ||
9414f563 DL |
3322 | /* transition WMs */ |
3323 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3324 | temp = 0; | |
3325 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; | |
3326 | temp |= p_wm->trans_wm.plane_res_b[i]; | |
3327 | if (p_wm->trans_wm.plane_en[i]) | |
3328 | temp |= PLANE_WM_EN; | |
3329 | ||
3330 | r->plane_trans[pipe][i] = temp; | |
3331 | } | |
3332 | ||
3333 | temp = 0; | |
4969d33e MR |
3334 | temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3335 | temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; | |
3336 | if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) | |
9414f563 DL |
3337 | temp |= PLANE_WM_EN; |
3338 | ||
4969d33e | 3339 | r->plane_trans[pipe][PLANE_CURSOR] = temp; |
9414f563 | 3340 | |
2d41c0b5 PB |
3341 | r->wm_linetime[pipe] = p_wm->linetime; |
3342 | } | |
3343 | ||
16160e3d DL |
3344 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
3345 | const struct skl_ddb_entry *entry) | |
3346 | { | |
3347 | if (entry->end) | |
3348 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
3349 | else | |
3350 | I915_WRITE(reg, 0); | |
3351 | } | |
3352 | ||
2d41c0b5 PB |
3353 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
3354 | const struct skl_wm_values *new) | |
3355 | { | |
3356 | struct drm_device *dev = dev_priv->dev; | |
3357 | struct intel_crtc *crtc; | |
3358 | ||
3359 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3360 | int i, level, max_level = ilk_wm_max_level(dev); | |
3361 | enum pipe pipe = crtc->pipe; | |
3362 | ||
5d374d96 DL |
3363 | if (!new->dirty[pipe]) |
3364 | continue; | |
8211bd5b | 3365 | |
5d374d96 | 3366 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
8211bd5b | 3367 | |
5d374d96 DL |
3368 | for (level = 0; level <= max_level; level++) { |
3369 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3370 | I915_WRITE(PLANE_WM(pipe, i, level), | |
3371 | new->plane[pipe][i][level]); | |
3372 | I915_WRITE(CUR_WM(pipe, level), | |
4969d33e | 3373 | new->plane[pipe][PLANE_CURSOR][level]); |
2d41c0b5 | 3374 | } |
5d374d96 DL |
3375 | for (i = 0; i < intel_num_planes(crtc); i++) |
3376 | I915_WRITE(PLANE_WM_TRANS(pipe, i), | |
3377 | new->plane_trans[pipe][i]); | |
4969d33e MR |
3378 | I915_WRITE(CUR_WM_TRANS(pipe), |
3379 | new->plane_trans[pipe][PLANE_CURSOR]); | |
5d374d96 | 3380 | |
2cd601c6 | 3381 | for (i = 0; i < intel_num_planes(crtc); i++) { |
5d374d96 DL |
3382 | skl_ddb_entry_write(dev_priv, |
3383 | PLANE_BUF_CFG(pipe, i), | |
3384 | &new->ddb.plane[pipe][i]); | |
2cd601c6 CK |
3385 | skl_ddb_entry_write(dev_priv, |
3386 | PLANE_NV12_BUF_CFG(pipe, i), | |
3387 | &new->ddb.y_plane[pipe][i]); | |
3388 | } | |
5d374d96 DL |
3389 | |
3390 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), | |
4969d33e | 3391 | &new->ddb.plane[pipe][PLANE_CURSOR]); |
2d41c0b5 | 3392 | } |
2d41c0b5 PB |
3393 | } |
3394 | ||
0e8fb7ba DL |
3395 | /* |
3396 | * When setting up a new DDB allocation arrangement, we need to correctly | |
3397 | * sequence the times at which the new allocations for the pipes are taken into | |
3398 | * account or we'll have pipes fetching from space previously allocated to | |
3399 | * another pipe. | |
3400 | * | |
3401 | * Roughly the sequence looks like: | |
3402 | * 1. re-allocate the pipe(s) with the allocation being reduced and not | |
3403 | * overlapping with a previous light-up pipe (another way to put it is: | |
3404 | * pipes with their new allocation strickly included into their old ones). | |
3405 | * 2. re-allocate the other pipes that get their allocation reduced | |
3406 | * 3. allocate the pipes having their allocation increased | |
3407 | * | |
3408 | * Steps 1. and 2. are here to take care of the following case: | |
3409 | * - Initially DDB looks like this: | |
3410 | * | B | C | | |
3411 | * - enable pipe A. | |
3412 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C | |
3413 | * allocation | |
3414 | * | A | B | C | | |
3415 | * | |
3416 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). | |
3417 | */ | |
3418 | ||
d21b795c DL |
3419 | static void |
3420 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) | |
0e8fb7ba | 3421 | { |
0e8fb7ba DL |
3422 | int plane; |
3423 | ||
d21b795c DL |
3424 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
3425 | ||
dd740780 | 3426 | for_each_plane(dev_priv, pipe, plane) { |
0e8fb7ba DL |
3427 | I915_WRITE(PLANE_SURF(pipe, plane), |
3428 | I915_READ(PLANE_SURF(pipe, plane))); | |
3429 | } | |
3430 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3431 | } | |
3432 | ||
3433 | static bool | |
3434 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, | |
3435 | const struct skl_ddb_allocation *new, | |
3436 | enum pipe pipe) | |
3437 | { | |
3438 | uint16_t old_size, new_size; | |
3439 | ||
3440 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); | |
3441 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); | |
3442 | ||
3443 | return old_size != new_size && | |
3444 | new->pipe[pipe].start >= old->pipe[pipe].start && | |
3445 | new->pipe[pipe].end <= old->pipe[pipe].end; | |
3446 | } | |
3447 | ||
3448 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, | |
3449 | struct skl_wm_values *new_values) | |
3450 | { | |
3451 | struct drm_device *dev = dev_priv->dev; | |
3452 | struct skl_ddb_allocation *cur_ddb, *new_ddb; | |
c929cb45 | 3453 | bool reallocated[I915_MAX_PIPES] = {}; |
0e8fb7ba DL |
3454 | struct intel_crtc *crtc; |
3455 | enum pipe pipe; | |
3456 | ||
3457 | new_ddb = &new_values->ddb; | |
3458 | cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3459 | ||
3460 | /* | |
3461 | * First pass: flush the pipes with the new allocation contained into | |
3462 | * the old space. | |
3463 | * | |
3464 | * We'll wait for the vblank on those pipes to ensure we can safely | |
3465 | * re-allocate the freed space without this pipe fetching from it. | |
3466 | */ | |
3467 | for_each_intel_crtc(dev, crtc) { | |
3468 | if (!crtc->active) | |
3469 | continue; | |
3470 | ||
3471 | pipe = crtc->pipe; | |
3472 | ||
3473 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) | |
3474 | continue; | |
3475 | ||
d21b795c | 3476 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
0e8fb7ba DL |
3477 | intel_wait_for_vblank(dev, pipe); |
3478 | ||
3479 | reallocated[pipe] = true; | |
3480 | } | |
3481 | ||
3482 | ||
3483 | /* | |
3484 | * Second pass: flush the pipes that are having their allocation | |
3485 | * reduced, but overlapping with a previous allocation. | |
3486 | * | |
3487 | * Here as well we need to wait for the vblank to make sure the freed | |
3488 | * space is not used anymore. | |
3489 | */ | |
3490 | for_each_intel_crtc(dev, crtc) { | |
3491 | if (!crtc->active) | |
3492 | continue; | |
3493 | ||
3494 | pipe = crtc->pipe; | |
3495 | ||
3496 | if (reallocated[pipe]) | |
3497 | continue; | |
3498 | ||
3499 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < | |
3500 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { | |
d21b795c | 3501 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
0e8fb7ba | 3502 | intel_wait_for_vblank(dev, pipe); |
d9d8e6b3 | 3503 | reallocated[pipe] = true; |
0e8fb7ba | 3504 | } |
0e8fb7ba DL |
3505 | } |
3506 | ||
3507 | /* | |
3508 | * Third pass: flush the pipes that got more space allocated. | |
3509 | * | |
3510 | * We don't need to actively wait for the update here, next vblank | |
3511 | * will just get more DDB space with the correct WM values. | |
3512 | */ | |
3513 | for_each_intel_crtc(dev, crtc) { | |
3514 | if (!crtc->active) | |
3515 | continue; | |
3516 | ||
3517 | pipe = crtc->pipe; | |
3518 | ||
3519 | /* | |
3520 | * At this point, only the pipes more space than before are | |
3521 | * left to re-allocate. | |
3522 | */ | |
3523 | if (reallocated[pipe]) | |
3524 | continue; | |
3525 | ||
d21b795c | 3526 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
0e8fb7ba DL |
3527 | } |
3528 | } | |
3529 | ||
2d41c0b5 | 3530 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
2791a16c | 3531 | struct skl_pipe_wm_parameters *params, |
261a27d1 | 3532 | struct intel_wm_config *config, |
2d41c0b5 PB |
3533 | struct skl_ddb_allocation *ddb, /* out */ |
3534 | struct skl_pipe_wm *pipe_wm /* out */) | |
3535 | { | |
3536 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3537 | ||
2791a16c PZ |
3538 | skl_compute_wm_pipe_parameters(crtc, params); |
3539 | skl_allocate_pipe_ddb(crtc, config, params, ddb); | |
3540 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); | |
2d41c0b5 | 3541 | |
261a27d1 | 3542 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) |
2d41c0b5 PB |
3543 | return false; |
3544 | ||
261a27d1 | 3545 | intel_crtc->wm.skl_active = *pipe_wm; |
2cd601c6 | 3546 | |
2d41c0b5 PB |
3547 | return true; |
3548 | } | |
3549 | ||
3550 | static void skl_update_other_pipe_wm(struct drm_device *dev, | |
3551 | struct drm_crtc *crtc, | |
261a27d1 | 3552 | struct intel_wm_config *config, |
2d41c0b5 PB |
3553 | struct skl_wm_values *r) |
3554 | { | |
3555 | struct intel_crtc *intel_crtc; | |
3556 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); | |
3557 | ||
3558 | /* | |
3559 | * If the WM update hasn't changed the allocation for this_crtc (the | |
3560 | * crtc we are currently computing the new WM values for), other | |
3561 | * enabled crtcs will keep the same allocation and we don't need to | |
3562 | * recompute anything for them. | |
3563 | */ | |
3564 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) | |
3565 | return; | |
3566 | ||
3567 | /* | |
3568 | * Otherwise, because of this_crtc being freshly enabled/disabled, the | |
3569 | * other active pipes need new DDB allocation and WM values. | |
3570 | */ | |
3571 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
3572 | base.head) { | |
2791a16c | 3573 | struct skl_pipe_wm_parameters params = {}; |
2d41c0b5 PB |
3574 | struct skl_pipe_wm pipe_wm = {}; |
3575 | bool wm_changed; | |
3576 | ||
3577 | if (this_crtc->pipe == intel_crtc->pipe) | |
3578 | continue; | |
3579 | ||
3580 | if (!intel_crtc->active) | |
3581 | continue; | |
3582 | ||
2791a16c PZ |
3583 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, |
3584 | ¶ms, config, | |
2d41c0b5 PB |
3585 | &r->ddb, &pipe_wm); |
3586 | ||
3587 | /* | |
3588 | * If we end up re-computing the other pipe WM values, it's | |
3589 | * because it was really needed, so we expect the WM values to | |
3590 | * be different. | |
3591 | */ | |
3592 | WARN_ON(!wm_changed); | |
3593 | ||
2791a16c | 3594 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); |
2d41c0b5 PB |
3595 | r->dirty[intel_crtc->pipe] = true; |
3596 | } | |
3597 | } | |
3598 | ||
adda50b8 BP |
3599 | static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) |
3600 | { | |
3601 | watermarks->wm_linetime[pipe] = 0; | |
3602 | memset(watermarks->plane[pipe], 0, | |
3603 | sizeof(uint32_t) * 8 * I915_MAX_PLANES); | |
adda50b8 BP |
3604 | memset(watermarks->plane_trans[pipe], |
3605 | 0, sizeof(uint32_t) * I915_MAX_PLANES); | |
4969d33e | 3606 | watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; |
adda50b8 BP |
3607 | |
3608 | /* Clear ddb entries for pipe */ | |
3609 | memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); | |
3610 | memset(&watermarks->ddb.plane[pipe], 0, | |
3611 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); | |
3612 | memset(&watermarks->ddb.y_plane[pipe], 0, | |
3613 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); | |
4969d33e MR |
3614 | memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, |
3615 | sizeof(struct skl_ddb_entry)); | |
adda50b8 BP |
3616 | |
3617 | } | |
3618 | ||
2d41c0b5 PB |
3619 | static void skl_update_wm(struct drm_crtc *crtc) |
3620 | { | |
3621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3622 | struct drm_device *dev = crtc->dev; | |
3623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2791a16c | 3624 | struct skl_pipe_wm_parameters params = {}; |
2d41c0b5 | 3625 | struct skl_wm_values *results = &dev_priv->wm.skl_results; |
261a27d1 MR |
3626 | struct skl_pipe_wm pipe_wm = {}; |
3627 | struct intel_wm_config config = {}; | |
2d41c0b5 | 3628 | |
adda50b8 BP |
3629 | |
3630 | /* Clear all dirty flags */ | |
3631 | memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); | |
3632 | ||
3633 | skl_clear_wm(results, intel_crtc->pipe); | |
2d41c0b5 | 3634 | |
261a27d1 MR |
3635 | skl_compute_wm_global_parameters(dev, &config); |
3636 | ||
2791a16c PZ |
3637 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, |
3638 | &results->ddb, &pipe_wm)) | |
2d41c0b5 PB |
3639 | return; |
3640 | ||
2791a16c | 3641 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); |
2d41c0b5 PB |
3642 | results->dirty[intel_crtc->pipe] = true; |
3643 | ||
261a27d1 | 3644 | skl_update_other_pipe_wm(dev, crtc, &config, results); |
2d41c0b5 | 3645 | skl_write_wm_values(dev_priv, results); |
0e8fb7ba | 3646 | skl_flush_wm_values(dev_priv, results); |
53b0deb4 DL |
3647 | |
3648 | /* store the new configuration */ | |
3649 | dev_priv->wm.skl_hw = *results; | |
2d41c0b5 PB |
3650 | } |
3651 | ||
2791a16c PZ |
3652 | static void |
3653 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, | |
3654 | uint32_t sprite_width, uint32_t sprite_height, | |
3655 | int pixel_size, bool enabled, bool scaled) | |
3656 | { | |
3657 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3658 | struct drm_framebuffer *fb = plane->state->fb; | |
3659 | ||
3660 | intel_plane->wm.enabled = enabled; | |
3661 | intel_plane->wm.scaled = scaled; | |
3662 | intel_plane->wm.horiz_pixels = sprite_width; | |
3663 | intel_plane->wm.vert_pixels = sprite_height; | |
3664 | intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; | |
3665 | ||
3666 | /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ | |
3667 | intel_plane->wm.bytes_per_pixel = | |
3668 | (fb && fb->pixel_format == DRM_FORMAT_NV12) ? | |
3669 | drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; | |
3670 | intel_plane->wm.y_bytes_per_pixel = | |
3671 | (fb && fb->pixel_format == DRM_FORMAT_NV12) ? | |
3672 | drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; | |
3673 | ||
3674 | /* | |
3675 | * Framebuffer can be NULL on plane disable, but it does not | |
3676 | * matter for watermarks if we assume no tiling in that case. | |
3677 | */ | |
3678 | if (fb) | |
3679 | intel_plane->wm.tiling = fb->modifier[0]; | |
3680 | intel_plane->wm.rotation = plane->state->rotation; | |
3681 | ||
3682 | skl_update_wm(crtc); | |
3683 | } | |
3684 | ||
261a27d1 | 3685 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 3686 | { |
261a27d1 MR |
3687 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3688 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); | |
3689 | struct drm_device *dev = crtc->dev; | |
3690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3691 | struct ilk_wm_maximums max; |
820c1980 | 3692 | struct ilk_wm_values results = {}; |
77c122bc | 3693 | enum intel_ddb_partitioning partitioning; |
261a27d1 MR |
3694 | struct intel_pipe_wm pipe_wm = {}; |
3695 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; | |
3696 | struct intel_wm_config config = {}; | |
861f3389 | 3697 | |
261a27d1 MR |
3698 | WARN_ON(cstate->base.active != intel_crtc->active); |
3699 | ||
261a27d1 MR |
3700 | intel_compute_pipe_wm(cstate, &pipe_wm); |
3701 | ||
3702 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
3703 | return; | |
3704 | ||
3705 | intel_crtc->wm.active = pipe_wm; | |
3706 | ||
3707 | ilk_compute_wm_config(dev, &config); | |
3708 | ||
3709 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); | |
3710 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); | |
a485bfb8 VS |
3711 | |
3712 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 | 3713 | if (INTEL_INFO(dev)->gen >= 7 && |
261a27d1 MR |
3714 | config.num_pipes_active == 1 && config.sprites_enabled) { |
3715 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); | |
3716 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); | |
0362c781 | 3717 | |
820c1980 | 3718 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 3719 | } else { |
198a1e9b | 3720 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
3721 | } |
3722 | ||
198a1e9b | 3723 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 3724 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 3725 | |
820c1980 | 3726 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 3727 | |
820c1980 | 3728 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
3729 | } |
3730 | ||
2791a16c PZ |
3731 | static void |
3732 | ilk_update_sprite_wm(struct drm_plane *plane, | |
3733 | struct drm_crtc *crtc, | |
3734 | uint32_t sprite_width, uint32_t sprite_height, | |
3735 | int pixel_size, bool enabled, bool scaled) | |
3736 | { | |
3737 | struct drm_device *dev = plane->dev; | |
3738 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3739 | ||
3740 | /* | |
3741 | * IVB workaround: must disable low power watermarks for at least | |
3742 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
3743 | * when scaling is disabled. | |
3744 | * | |
3745 | * WaCxSRDisabledForSpriteScaling:ivb | |
3746 | */ | |
3747 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
3748 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
3749 | ||
3750 | ilk_update_wm(crtc); | |
3751 | } | |
3752 | ||
3078999f PB |
3753 | static void skl_pipe_wm_active_state(uint32_t val, |
3754 | struct skl_pipe_wm *active, | |
3755 | bool is_transwm, | |
3756 | bool is_cursor, | |
3757 | int i, | |
3758 | int level) | |
3759 | { | |
3760 | bool is_enabled = (val & PLANE_WM_EN) != 0; | |
3761 | ||
3762 | if (!is_transwm) { | |
3763 | if (!is_cursor) { | |
3764 | active->wm[level].plane_en[i] = is_enabled; | |
3765 | active->wm[level].plane_res_b[i] = | |
3766 | val & PLANE_WM_BLOCKS_MASK; | |
3767 | active->wm[level].plane_res_l[i] = | |
3768 | (val >> PLANE_WM_LINES_SHIFT) & | |
3769 | PLANE_WM_LINES_MASK; | |
3770 | } else { | |
4969d33e MR |
3771 | active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; |
3772 | active->wm[level].plane_res_b[PLANE_CURSOR] = | |
3078999f | 3773 | val & PLANE_WM_BLOCKS_MASK; |
4969d33e | 3774 | active->wm[level].plane_res_l[PLANE_CURSOR] = |
3078999f PB |
3775 | (val >> PLANE_WM_LINES_SHIFT) & |
3776 | PLANE_WM_LINES_MASK; | |
3777 | } | |
3778 | } else { | |
3779 | if (!is_cursor) { | |
3780 | active->trans_wm.plane_en[i] = is_enabled; | |
3781 | active->trans_wm.plane_res_b[i] = | |
3782 | val & PLANE_WM_BLOCKS_MASK; | |
3783 | active->trans_wm.plane_res_l[i] = | |
3784 | (val >> PLANE_WM_LINES_SHIFT) & | |
3785 | PLANE_WM_LINES_MASK; | |
3786 | } else { | |
4969d33e MR |
3787 | active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; |
3788 | active->trans_wm.plane_res_b[PLANE_CURSOR] = | |
3078999f | 3789 | val & PLANE_WM_BLOCKS_MASK; |
4969d33e | 3790 | active->trans_wm.plane_res_l[PLANE_CURSOR] = |
3078999f PB |
3791 | (val >> PLANE_WM_LINES_SHIFT) & |
3792 | PLANE_WM_LINES_MASK; | |
3793 | } | |
3794 | } | |
3795 | } | |
3796 | ||
3797 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3798 | { | |
3799 | struct drm_device *dev = crtc->dev; | |
3800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3801 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; | |
3802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
261a27d1 | 3803 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; |
3078999f PB |
3804 | enum pipe pipe = intel_crtc->pipe; |
3805 | int level, i, max_level; | |
3806 | uint32_t temp; | |
3807 | ||
3808 | max_level = ilk_wm_max_level(dev); | |
3809 | ||
3810 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3811 | ||
3812 | for (level = 0; level <= max_level; level++) { | |
3813 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3814 | hw->plane[pipe][i][level] = | |
3815 | I915_READ(PLANE_WM(pipe, i, level)); | |
4969d33e | 3816 | hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); |
3078999f PB |
3817 | } |
3818 | ||
3819 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3820 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); | |
4969d33e | 3821 | hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); |
3078999f | 3822 | |
3ef00284 | 3823 | if (!intel_crtc->active) |
3078999f PB |
3824 | return; |
3825 | ||
3826 | hw->dirty[pipe] = true; | |
3827 | ||
3828 | active->linetime = hw->wm_linetime[pipe]; | |
3829 | ||
3830 | for (level = 0; level <= max_level; level++) { | |
3831 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3832 | temp = hw->plane[pipe][i][level]; | |
3833 | skl_pipe_wm_active_state(temp, active, false, | |
3834 | false, i, level); | |
3835 | } | |
4969d33e | 3836 | temp = hw->plane[pipe][PLANE_CURSOR][level]; |
3078999f PB |
3837 | skl_pipe_wm_active_state(temp, active, false, true, i, level); |
3838 | } | |
3839 | ||
3840 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3841 | temp = hw->plane_trans[pipe][i]; | |
3842 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); | |
3843 | } | |
3844 | ||
4969d33e | 3845 | temp = hw->plane_trans[pipe][PLANE_CURSOR]; |
3078999f PB |
3846 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); |
3847 | } | |
3848 | ||
3849 | void skl_wm_get_hw_state(struct drm_device *dev) | |
3850 | { | |
a269c583 DL |
3851 | struct drm_i915_private *dev_priv = dev->dev_private; |
3852 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; | |
3078999f PB |
3853 | struct drm_crtc *crtc; |
3854 | ||
a269c583 | 3855 | skl_ddb_get_hw_state(dev_priv, ddb); |
3078999f PB |
3856 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
3857 | skl_pipe_wm_get_hw_state(crtc); | |
3858 | } | |
3859 | ||
243e6a44 VS |
3860 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3861 | { | |
3862 | struct drm_device *dev = crtc->dev; | |
3863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3864 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 | 3865 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
261a27d1 | 3866 | struct intel_pipe_wm *active = &intel_crtc->wm.active; |
243e6a44 VS |
3867 | enum pipe pipe = intel_crtc->pipe; |
3868 | static const unsigned int wm0_pipe_reg[] = { | |
3869 | [PIPE_A] = WM0_PIPEA_ILK, | |
3870 | [PIPE_B] = WM0_PIPEB_ILK, | |
3871 | [PIPE_C] = WM0_PIPEC_IVB, | |
3872 | }; | |
3873 | ||
3874 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 3875 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 3876 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 3877 | |
3ef00284 | 3878 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
3879 | |
3880 | if (active->pipe_enabled) { | |
243e6a44 VS |
3881 | u32 tmp = hw->wm_pipe[pipe]; |
3882 | ||
3883 | /* | |
3884 | * For active pipes LP0 watermark is marked as | |
3885 | * enabled, and LP1+ watermaks as disabled since | |
3886 | * we can't really reverse compute them in case | |
3887 | * multiple pipes are active. | |
3888 | */ | |
3889 | active->wm[0].enable = true; | |
3890 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
3891 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
3892 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
3893 | active->linetime = hw->wm_linetime[pipe]; | |
3894 | } else { | |
3895 | int level, max_level = ilk_wm_max_level(dev); | |
3896 | ||
3897 | /* | |
3898 | * For inactive pipes, all watermark levels | |
3899 | * should be marked as enabled but zeroed, | |
3900 | * which is what we'd compute them to. | |
3901 | */ | |
3902 | for (level = 0; level <= max_level; level++) | |
3903 | active->wm[level].enable = true; | |
3904 | } | |
3905 | } | |
3906 | ||
6eb1a681 VS |
3907 | #define _FW_WM(value, plane) \ |
3908 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) | |
3909 | #define _FW_WM_VLV(value, plane) \ | |
3910 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) | |
3911 | ||
3912 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, | |
3913 | struct vlv_wm_values *wm) | |
3914 | { | |
3915 | enum pipe pipe; | |
3916 | uint32_t tmp; | |
3917 | ||
3918 | for_each_pipe(dev_priv, pipe) { | |
3919 | tmp = I915_READ(VLV_DDL(pipe)); | |
3920 | ||
3921 | wm->ddl[pipe].primary = | |
3922 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3923 | wm->ddl[pipe].cursor = | |
3924 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3925 | wm->ddl[pipe].sprite[0] = | |
3926 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3927 | wm->ddl[pipe].sprite[1] = | |
3928 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3929 | } | |
3930 | ||
3931 | tmp = I915_READ(DSPFW1); | |
3932 | wm->sr.plane = _FW_WM(tmp, SR); | |
3933 | wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); | |
3934 | wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); | |
3935 | wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); | |
3936 | ||
3937 | tmp = I915_READ(DSPFW2); | |
3938 | wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); | |
3939 | wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); | |
3940 | wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); | |
3941 | ||
3942 | tmp = I915_READ(DSPFW3); | |
3943 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
3944 | ||
3945 | if (IS_CHERRYVIEW(dev_priv)) { | |
3946 | tmp = I915_READ(DSPFW7_CHV); | |
3947 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); | |
3948 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); | |
3949 | ||
3950 | tmp = I915_READ(DSPFW8_CHV); | |
3951 | wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); | |
3952 | wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); | |
3953 | ||
3954 | tmp = I915_READ(DSPFW9_CHV); | |
3955 | wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); | |
3956 | wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); | |
3957 | ||
3958 | tmp = I915_READ(DSPHOWM); | |
3959 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
3960 | wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; | |
3961 | wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; | |
3962 | wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; | |
3963 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
3964 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
3965 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; | |
3966 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
3967 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
3968 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; | |
3969 | } else { | |
3970 | tmp = I915_READ(DSPFW7); | |
3971 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); | |
3972 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); | |
3973 | ||
3974 | tmp = I915_READ(DSPHOWM); | |
3975 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
3976 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
3977 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
3978 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; | |
3979 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
3980 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
3981 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; | |
3982 | } | |
3983 | } | |
3984 | ||
3985 | #undef _FW_WM | |
3986 | #undef _FW_WM_VLV | |
3987 | ||
3988 | void vlv_wm_get_hw_state(struct drm_device *dev) | |
3989 | { | |
3990 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3991 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; | |
3992 | struct intel_plane *plane; | |
3993 | enum pipe pipe; | |
3994 | u32 val; | |
3995 | ||
3996 | vlv_read_wm_values(dev_priv, wm); | |
3997 | ||
3998 | for_each_intel_plane(dev, plane) { | |
3999 | switch (plane->base.type) { | |
4000 | int sprite; | |
4001 | case DRM_PLANE_TYPE_CURSOR: | |
4002 | plane->wm.fifo_size = 63; | |
4003 | break; | |
4004 | case DRM_PLANE_TYPE_PRIMARY: | |
4005 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); | |
4006 | break; | |
4007 | case DRM_PLANE_TYPE_OVERLAY: | |
4008 | sprite = plane->plane; | |
4009 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); | |
4010 | break; | |
4011 | } | |
4012 | } | |
4013 | ||
4014 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; | |
4015 | wm->level = VLV_WM_LEVEL_PM2; | |
4016 | ||
4017 | if (IS_CHERRYVIEW(dev_priv)) { | |
4018 | mutex_lock(&dev_priv->rps.hw_lock); | |
4019 | ||
4020 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4021 | if (val & DSP_MAXFIFO_PM5_ENABLE) | |
4022 | wm->level = VLV_WM_LEVEL_PM5; | |
4023 | ||
58590c14 VS |
4024 | /* |
4025 | * If DDR DVFS is disabled in the BIOS, Punit | |
4026 | * will never ack the request. So if that happens | |
4027 | * assume we don't have to enable/disable DDR DVFS | |
4028 | * dynamically. To test that just set the REQ_ACK | |
4029 | * bit to poke the Punit, but don't change the | |
4030 | * HIGH/LOW bits so that we don't actually change | |
4031 | * the current state. | |
4032 | */ | |
6eb1a681 | 4033 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
58590c14 VS |
4034 | val |= FORCE_DDR_FREQ_REQ_ACK; |
4035 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
4036 | ||
4037 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
4038 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { | |
4039 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " | |
4040 | "assuming DDR DVFS is disabled\n"); | |
4041 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; | |
4042 | } else { | |
4043 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
4044 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) | |
4045 | wm->level = VLV_WM_LEVEL_DDR_DVFS; | |
4046 | } | |
6eb1a681 VS |
4047 | |
4048 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4049 | } | |
4050 | ||
4051 | for_each_pipe(dev_priv, pipe) | |
4052 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", | |
4053 | pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, | |
4054 | wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); | |
4055 | ||
4056 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", | |
4057 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); | |
4058 | } | |
4059 | ||
243e6a44 VS |
4060 | void ilk_wm_get_hw_state(struct drm_device *dev) |
4061 | { | |
4062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 4063 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
4064 | struct drm_crtc *crtc; |
4065 | ||
70e1e0ec | 4066 | for_each_crtc(dev, crtc) |
243e6a44 VS |
4067 | ilk_pipe_wm_get_hw_state(crtc); |
4068 | ||
4069 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
4070 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
4071 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
4072 | ||
4073 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
4074 | if (INTEL_INFO(dev)->gen >= 7) { |
4075 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
4076 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
4077 | } | |
243e6a44 | 4078 | |
a42a5719 | 4079 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
4080 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
4081 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
4082 | else if (IS_IVYBRIDGE(dev)) | |
4083 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
4084 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
4085 | |
4086 | hw->enable_fbc_wm = | |
4087 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
4088 | } | |
4089 | ||
b445e3b0 ED |
4090 | /** |
4091 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4092 | * | |
4093 | * Calculate watermark values for the various WM regs based on current mode | |
4094 | * and plane configuration. | |
4095 | * | |
4096 | * There are several cases to deal with here: | |
4097 | * - normal (i.e. non-self-refresh) | |
4098 | * - self-refresh (SR) mode | |
4099 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4100 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4101 | * lines), so need to account for TLB latency | |
4102 | * | |
4103 | * The normal calculation is: | |
4104 | * watermark = dotclock * bytes per pixel * latency | |
4105 | * where latency is platform & configuration dependent (we assume pessimal | |
4106 | * values here). | |
4107 | * | |
4108 | * The SR calculation is: | |
4109 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4110 | * bytes per pixel | |
4111 | * where | |
4112 | * line time = htotal / dotclock | |
4113 | * surface width = hdisplay for normal plane and 64 for cursor | |
4114 | * and latency is assumed to be high, as above. | |
4115 | * | |
4116 | * The final value programmed to the register should always be rounded up, | |
4117 | * and include an extra 2 entries to account for clock crossings. | |
4118 | * | |
4119 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4120 | * to set the non-SR watermarks to 8. | |
4121 | */ | |
46ba614c | 4122 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 4123 | { |
46ba614c | 4124 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
4125 | |
4126 | if (dev_priv->display.update_wm) | |
46ba614c | 4127 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
4128 | } |
4129 | ||
2791a16c PZ |
4130 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
4131 | struct drm_crtc *crtc, | |
4132 | uint32_t sprite_width, | |
4133 | uint32_t sprite_height, | |
4134 | int pixel_size, | |
4135 | bool enabled, bool scaled) | |
4136 | { | |
4137 | struct drm_i915_private *dev_priv = plane->dev->dev_private; | |
4138 | ||
4139 | if (dev_priv->display.update_sprite_wm) | |
4140 | dev_priv->display.update_sprite_wm(plane, crtc, | |
4141 | sprite_width, sprite_height, | |
4142 | pixel_size, enabled, scaled); | |
4143 | } | |
4144 | ||
9270388e DV |
4145 | /** |
4146 | * Lock protecting IPS related data structures | |
9270388e DV |
4147 | */ |
4148 | DEFINE_SPINLOCK(mchdev_lock); | |
4149 | ||
4150 | /* Global for IPS driver to get at the current i915 device. Protected by | |
4151 | * mchdev_lock. */ | |
4152 | static struct drm_i915_private *i915_mch_dev; | |
4153 | ||
2b4e57bd ED |
4154 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
4155 | { | |
4156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4157 | u16 rgvswctl; | |
4158 | ||
9270388e DV |
4159 | assert_spin_locked(&mchdev_lock); |
4160 | ||
2b4e57bd ED |
4161 | rgvswctl = I915_READ16(MEMSWCTL); |
4162 | if (rgvswctl & MEMCTL_CMD_STS) { | |
4163 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
4164 | return false; /* still busy with another command */ | |
4165 | } | |
4166 | ||
4167 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
4168 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
4169 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
4170 | POSTING_READ16(MEMSWCTL); | |
4171 | ||
4172 | rgvswctl |= MEMCTL_CMD_STS; | |
4173 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
4174 | ||
4175 | return true; | |
4176 | } | |
4177 | ||
8090c6b9 | 4178 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
4179 | { |
4180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4181 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
4182 | u8 fmax, fmin, fstart, vstart; | |
4183 | ||
9270388e DV |
4184 | spin_lock_irq(&mchdev_lock); |
4185 | ||
2b4e57bd ED |
4186 | /* Enable temp reporting */ |
4187 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
4188 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
4189 | ||
4190 | /* 100ms RC evaluation intervals */ | |
4191 | I915_WRITE(RCUPEI, 100000); | |
4192 | I915_WRITE(RCDNEI, 100000); | |
4193 | ||
4194 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
4195 | I915_WRITE(RCBMAXAVG, 90000); | |
4196 | I915_WRITE(RCBMINAVG, 80000); | |
4197 | ||
4198 | I915_WRITE(MEMIHYST, 1); | |
4199 | ||
4200 | /* Set up min, max, and cur for interrupt handling */ | |
4201 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
4202 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
4203 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
4204 | MEMMODE_FSTART_SHIFT; | |
4205 | ||
616847e7 | 4206 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
2b4e57bd ED |
4207 | PXVFREQ_PX_SHIFT; |
4208 | ||
20e4d407 DV |
4209 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
4210 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 4211 | |
20e4d407 DV |
4212 | dev_priv->ips.max_delay = fstart; |
4213 | dev_priv->ips.min_delay = fmin; | |
4214 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
4215 | |
4216 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
4217 | fmax, fmin, fstart); | |
4218 | ||
4219 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
4220 | ||
4221 | /* | |
4222 | * Interrupts will be enabled in ironlake_irq_postinstall | |
4223 | */ | |
4224 | ||
4225 | I915_WRITE(VIDSTART, vstart); | |
4226 | POSTING_READ(VIDSTART); | |
4227 | ||
4228 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
4229 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
4230 | ||
9270388e | 4231 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 4232 | DRM_ERROR("stuck trying to change perf mode\n"); |
dd92d8de | 4233 | mdelay(1); |
2b4e57bd ED |
4234 | |
4235 | ironlake_set_drps(dev, fstart); | |
4236 | ||
7d81c3e0 VS |
4237 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
4238 | I915_READ(DDREC) + I915_READ(CSIEC); | |
20e4d407 | 4239 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
7d81c3e0 | 4240 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
5ed0bdf2 | 4241 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
4242 | |
4243 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
4244 | } |
4245 | ||
8090c6b9 | 4246 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
4247 | { |
4248 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
4249 | u16 rgvswctl; |
4250 | ||
4251 | spin_lock_irq(&mchdev_lock); | |
4252 | ||
4253 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
4254 | |
4255 | /* Ack interrupts, disable EFC interrupt */ | |
4256 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
4257 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
4258 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
4259 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
4260 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
4261 | ||
4262 | /* Go back to the starting frequency */ | |
20e4d407 | 4263 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
dd92d8de | 4264 | mdelay(1); |
2b4e57bd ED |
4265 | rgvswctl |= MEMCTL_CMD_STS; |
4266 | I915_WRITE(MEMSWCTL, rgvswctl); | |
dd92d8de | 4267 | mdelay(1); |
2b4e57bd | 4268 | |
9270388e | 4269 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
4270 | } |
4271 | ||
acbe9475 DV |
4272 | /* There's a funny hw issue where the hw returns all 0 when reading from |
4273 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
4274 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
4275 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
4276 | */ | |
74ef1173 | 4277 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 4278 | { |
7b9e0ae6 | 4279 | u32 limits; |
2b4e57bd | 4280 | |
20b46e59 DV |
4281 | /* Only set the down limit when we've reached the lowest level to avoid |
4282 | * getting more interrupts, otherwise leave this clear. This prevents a | |
4283 | * race in the hw when coming out of rc6: There's a tiny window where | |
4284 | * the hw runs at the minimal clock before selecting the desired | |
4285 | * frequency, if the down threshold expires in that window we will not | |
4286 | * receive a down interrupt. */ | |
74ef1173 AG |
4287 | if (IS_GEN9(dev_priv->dev)) { |
4288 | limits = (dev_priv->rps.max_freq_softlimit) << 23; | |
4289 | if (val <= dev_priv->rps.min_freq_softlimit) | |
4290 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; | |
4291 | } else { | |
4292 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
4293 | if (val <= dev_priv->rps.min_freq_softlimit) | |
4294 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
4295 | } | |
20b46e59 DV |
4296 | |
4297 | return limits; | |
4298 | } | |
4299 | ||
dd75fdc8 CW |
4300 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
4301 | { | |
4302 | int new_power; | |
8a586437 AG |
4303 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
4304 | u32 ei_up = 0, ei_down = 0; | |
dd75fdc8 CW |
4305 | |
4306 | new_power = dev_priv->rps.power; | |
4307 | switch (dev_priv->rps.power) { | |
4308 | case LOW_POWER: | |
b39fb297 | 4309 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4310 | new_power = BETWEEN; |
4311 | break; | |
4312 | ||
4313 | case BETWEEN: | |
b39fb297 | 4314 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 4315 | new_power = LOW_POWER; |
b39fb297 | 4316 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4317 | new_power = HIGH_POWER; |
4318 | break; | |
4319 | ||
4320 | case HIGH_POWER: | |
b39fb297 | 4321 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4322 | new_power = BETWEEN; |
4323 | break; | |
4324 | } | |
4325 | /* Max/min bins are special */ | |
aed242ff | 4326 | if (val <= dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 4327 | new_power = LOW_POWER; |
aed242ff | 4328 | if (val >= dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
4329 | new_power = HIGH_POWER; |
4330 | if (new_power == dev_priv->rps.power) | |
4331 | return; | |
4332 | ||
4333 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
4334 | switch (new_power) { | |
4335 | case LOW_POWER: | |
4336 | /* Upclock if more than 95% busy over 16ms */ | |
8a586437 AG |
4337 | ei_up = 16000; |
4338 | threshold_up = 95; | |
dd75fdc8 CW |
4339 | |
4340 | /* Downclock if less than 85% busy over 32ms */ | |
8a586437 AG |
4341 | ei_down = 32000; |
4342 | threshold_down = 85; | |
dd75fdc8 CW |
4343 | break; |
4344 | ||
4345 | case BETWEEN: | |
4346 | /* Upclock if more than 90% busy over 13ms */ | |
8a586437 AG |
4347 | ei_up = 13000; |
4348 | threshold_up = 90; | |
dd75fdc8 CW |
4349 | |
4350 | /* Downclock if less than 75% busy over 32ms */ | |
8a586437 AG |
4351 | ei_down = 32000; |
4352 | threshold_down = 75; | |
dd75fdc8 CW |
4353 | break; |
4354 | ||
4355 | case HIGH_POWER: | |
4356 | /* Upclock if more than 85% busy over 10ms */ | |
8a586437 AG |
4357 | ei_up = 10000; |
4358 | threshold_up = 85; | |
dd75fdc8 CW |
4359 | |
4360 | /* Downclock if less than 60% busy over 32ms */ | |
8a586437 AG |
4361 | ei_down = 32000; |
4362 | threshold_down = 60; | |
dd75fdc8 CW |
4363 | break; |
4364 | } | |
4365 | ||
8a586437 AG |
4366 | I915_WRITE(GEN6_RP_UP_EI, |
4367 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); | |
4368 | I915_WRITE(GEN6_RP_UP_THRESHOLD, | |
4369 | GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); | |
4370 | ||
4371 | I915_WRITE(GEN6_RP_DOWN_EI, | |
4372 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); | |
4373 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, | |
4374 | GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); | |
4375 | ||
4376 | I915_WRITE(GEN6_RP_CONTROL, | |
4377 | GEN6_RP_MEDIA_TURBO | | |
4378 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4379 | GEN6_RP_MEDIA_IS_GFX | | |
4380 | GEN6_RP_ENABLE | | |
4381 | GEN6_RP_UP_BUSY_AVG | | |
4382 | GEN6_RP_DOWN_IDLE_AVG); | |
4383 | ||
dd75fdc8 | 4384 | dev_priv->rps.power = new_power; |
8fb55197 CW |
4385 | dev_priv->rps.up_threshold = threshold_up; |
4386 | dev_priv->rps.down_threshold = threshold_down; | |
dd75fdc8 CW |
4387 | dev_priv->rps.last_adj = 0; |
4388 | } | |
4389 | ||
2876ce73 CW |
4390 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
4391 | { | |
4392 | u32 mask = 0; | |
4393 | ||
4394 | if (val > dev_priv->rps.min_freq_softlimit) | |
6f4b12f8 | 4395 | mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
2876ce73 | 4396 | if (val < dev_priv->rps.max_freq_softlimit) |
6f4b12f8 | 4397 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
2876ce73 | 4398 | |
7b3c29f6 CW |
4399 | mask &= dev_priv->pm_rps_events; |
4400 | ||
59d02a1f | 4401 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
4402 | } |
4403 | ||
b8a5ff8d JM |
4404 | /* gen6_set_rps is called to update the frequency request, but should also be |
4405 | * called when the range (min_delay and max_delay) is modified so that we can | |
4406 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
ffe02b40 | 4407 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
20b46e59 DV |
4408 | { |
4409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 4410 | |
23eafea6 SAK |
4411 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
4412 | if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) | |
4413 | return; | |
4414 | ||
4fc688ce | 4415 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
aed242ff CW |
4416 | WARN_ON(val > dev_priv->rps.max_freq); |
4417 | WARN_ON(val < dev_priv->rps.min_freq); | |
004777cb | 4418 | |
eb64cad1 CW |
4419 | /* min/max delay may still have been modified so be sure to |
4420 | * write the limits value. | |
4421 | */ | |
4422 | if (val != dev_priv->rps.cur_freq) { | |
4423 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 4424 | |
5704195c AG |
4425 | if (IS_GEN9(dev)) |
4426 | I915_WRITE(GEN6_RPNSWREQ, | |
4427 | GEN9_FREQUENCY(val)); | |
4428 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
eb64cad1 CW |
4429 | I915_WRITE(GEN6_RPNSWREQ, |
4430 | HSW_FREQUENCY(val)); | |
4431 | else | |
4432 | I915_WRITE(GEN6_RPNSWREQ, | |
4433 | GEN6_FREQUENCY(val) | | |
4434 | GEN6_OFFSET(0) | | |
4435 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 4436 | } |
7b9e0ae6 | 4437 | |
7b9e0ae6 CW |
4438 | /* Make sure we continue to get interrupts |
4439 | * until we hit the minimum or maximum frequencies. | |
4440 | */ | |
74ef1173 | 4441 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
2876ce73 | 4442 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 4443 | |
d5570a72 BW |
4444 | POSTING_READ(GEN6_RPNSWREQ); |
4445 | ||
b39fb297 | 4446 | dev_priv->rps.cur_freq = val; |
be2cde9a | 4447 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
4448 | } |
4449 | ||
ffe02b40 VS |
4450 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
4451 | { | |
4452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4453 | ||
4454 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
aed242ff CW |
4455 | WARN_ON(val > dev_priv->rps.max_freq); |
4456 | WARN_ON(val < dev_priv->rps.min_freq); | |
ffe02b40 VS |
4457 | |
4458 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), | |
4459 | "Odd GPU freq value\n")) | |
4460 | val &= ~1; | |
4461 | ||
cd25dd5b D |
4462 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
4463 | ||
8fb55197 | 4464 | if (val != dev_priv->rps.cur_freq) { |
ffe02b40 | 4465 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
8fb55197 CW |
4466 | if (!IS_CHERRYVIEW(dev_priv)) |
4467 | gen6_set_rps_thresholds(dev_priv, val); | |
4468 | } | |
ffe02b40 | 4469 | |
ffe02b40 VS |
4470 | dev_priv->rps.cur_freq = val; |
4471 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
4472 | } | |
4473 | ||
a7f6e231 | 4474 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
76c3552f D |
4475 | * |
4476 | * * If Gfx is Idle, then | |
a7f6e231 D |
4477 | * 1. Forcewake Media well. |
4478 | * 2. Request idle freq. | |
4479 | * 3. Release Forcewake of Media well. | |
76c3552f D |
4480 | */ |
4481 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
4482 | { | |
aed242ff | 4483 | u32 val = dev_priv->rps.idle_freq; |
5549d25f | 4484 | |
aed242ff | 4485 | if (dev_priv->rps.cur_freq <= val) |
76c3552f D |
4486 | return; |
4487 | ||
a7f6e231 D |
4488 | /* Wake up the media well, as that takes a lot less |
4489 | * power than the Render well. */ | |
4490 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); | |
4491 | valleyview_set_rps(dev_priv->dev, val); | |
4492 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); | |
76c3552f D |
4493 | } |
4494 | ||
43cf3bf0 CW |
4495 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
4496 | { | |
4497 | mutex_lock(&dev_priv->rps.hw_lock); | |
4498 | if (dev_priv->rps.enabled) { | |
4499 | if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) | |
4500 | gen6_rps_reset_ei(dev_priv); | |
4501 | I915_WRITE(GEN6_PMINTRMSK, | |
4502 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
4503 | } | |
4504 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4505 | } | |
4506 | ||
b29c19b6 CW |
4507 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
4508 | { | |
691bb717 DL |
4509 | struct drm_device *dev = dev_priv->dev; |
4510 | ||
b29c19b6 | 4511 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 4512 | if (dev_priv->rps.enabled) { |
21a11fff | 4513 | if (IS_VALLEYVIEW(dev)) |
76c3552f | 4514 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 4515 | else |
aed242ff | 4516 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
c0951f0c | 4517 | dev_priv->rps.last_adj = 0; |
43cf3bf0 | 4518 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
c0951f0c | 4519 | } |
8d3afd7d | 4520 | mutex_unlock(&dev_priv->rps.hw_lock); |
1854d5ca | 4521 | |
8d3afd7d | 4522 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
4523 | while (!list_empty(&dev_priv->rps.clients)) |
4524 | list_del_init(dev_priv->rps.clients.next); | |
8d3afd7d | 4525 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
4526 | } |
4527 | ||
1854d5ca | 4528 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
4529 | struct intel_rps_client *rps, |
4530 | unsigned long submitted) | |
b29c19b6 | 4531 | { |
8d3afd7d CW |
4532 | /* This is intentionally racy! We peek at the state here, then |
4533 | * validate inside the RPS worker. | |
4534 | */ | |
4535 | if (!(dev_priv->mm.busy && | |
4536 | dev_priv->rps.enabled && | |
4537 | dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) | |
4538 | return; | |
43cf3bf0 | 4539 | |
e61b9958 CW |
4540 | /* Force a RPS boost (and don't count it against the client) if |
4541 | * the GPU is severely congested. | |
4542 | */ | |
d0bc54f2 | 4543 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
e61b9958 CW |
4544 | rps = NULL; |
4545 | ||
8d3afd7d CW |
4546 | spin_lock(&dev_priv->rps.client_lock); |
4547 | if (rps == NULL || list_empty(&rps->link)) { | |
4548 | spin_lock_irq(&dev_priv->irq_lock); | |
4549 | if (dev_priv->rps.interrupts_enabled) { | |
4550 | dev_priv->rps.client_boost = true; | |
4551 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
4552 | } | |
4553 | spin_unlock_irq(&dev_priv->irq_lock); | |
1854d5ca | 4554 | |
2e1b8730 CW |
4555 | if (rps != NULL) { |
4556 | list_add(&rps->link, &dev_priv->rps.clients); | |
4557 | rps->boosts++; | |
1854d5ca CW |
4558 | } else |
4559 | dev_priv->rps.boosts++; | |
c0951f0c | 4560 | } |
8d3afd7d | 4561 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
4562 | } |
4563 | ||
ffe02b40 | 4564 | void intel_set_rps(struct drm_device *dev, u8 val) |
0a073b84 | 4565 | { |
ffe02b40 VS |
4566 | if (IS_VALLEYVIEW(dev)) |
4567 | valleyview_set_rps(dev, val); | |
4568 | else | |
4569 | gen6_set_rps(dev, val); | |
0a073b84 JB |
4570 | } |
4571 | ||
20e49366 ZW |
4572 | static void gen9_disable_rps(struct drm_device *dev) |
4573 | { | |
4574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4575 | ||
4576 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
38c23527 | 4577 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
4578 | } |
4579 | ||
44fc7d5c | 4580 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
4581 | { |
4582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4583 | ||
4584 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 4585 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
44fc7d5c DV |
4586 | } |
4587 | ||
38807746 D |
4588 | static void cherryview_disable_rps(struct drm_device *dev) |
4589 | { | |
4590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4591 | ||
4592 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4593 | } | |
4594 | ||
44fc7d5c DV |
4595 | static void valleyview_disable_rps(struct drm_device *dev) |
4596 | { | |
4597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4598 | ||
98a2e5f9 D |
4599 | /* we're doing forcewake before Disabling RC6, |
4600 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 4601 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 4602 | |
44fc7d5c | 4603 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 4604 | |
59bad947 | 4605 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
4606 | } |
4607 | ||
dc39fff7 BW |
4608 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
4609 | { | |
91ca689a ID |
4610 | if (IS_VALLEYVIEW(dev)) { |
4611 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
4612 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
4613 | else | |
4614 | mode = 0; | |
4615 | } | |
58abf1da RV |
4616 | if (HAS_RC6p(dev)) |
4617 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", | |
4618 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
4619 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
4620 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
4621 | ||
4622 | else | |
4623 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", | |
4624 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
4625 | } |
4626 | ||
e6069ca8 | 4627 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 4628 | { |
e7d66d89 DV |
4629 | /* No RC6 before Ironlake and code is gone for ilk. */ |
4630 | if (INTEL_INFO(dev)->gen < 6) | |
e6069ca8 ID |
4631 | return 0; |
4632 | ||
456470eb | 4633 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
4634 | if (enable_rc6 >= 0) { |
4635 | int mask; | |
4636 | ||
58abf1da | 4637 | if (HAS_RC6p(dev)) |
e6069ca8 ID |
4638 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4639 | INTEL_RC6pp_ENABLE; | |
4640 | else | |
4641 | mask = INTEL_RC6_ENABLE; | |
4642 | ||
4643 | if ((enable_rc6 & mask) != enable_rc6) | |
8dfd1f04 DV |
4644 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4645 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
4646 | |
4647 | return enable_rc6 & mask; | |
4648 | } | |
2b4e57bd | 4649 | |
8bade1ad | 4650 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 4651 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
4652 | |
4653 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
4654 | } |
4655 | ||
e6069ca8 ID |
4656 | int intel_enable_rc6(const struct drm_device *dev) |
4657 | { | |
4658 | return i915.enable_rc6; | |
4659 | } | |
4660 | ||
93ee2920 | 4661 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
3280e8b0 | 4662 | { |
93ee2920 TR |
4663 | struct drm_i915_private *dev_priv = dev->dev_private; |
4664 | uint32_t rp_state_cap; | |
4665 | u32 ddcc_status = 0; | |
4666 | int ret; | |
4667 | ||
3280e8b0 BW |
4668 | /* All of these values are in units of 50MHz */ |
4669 | dev_priv->rps.cur_freq = 0; | |
93ee2920 | 4670 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
35040562 BP |
4671 | if (IS_BROXTON(dev)) { |
4672 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
4673 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; | |
4674 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
4675 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; | |
4676 | } else { | |
4677 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
4678 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
4679 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
4680 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
4681 | } | |
4682 | ||
3280e8b0 BW |
4683 | /* hw_max = RP0 until we check for overclocking */ |
4684 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
4685 | ||
93ee2920 | 4686 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
c5e0688c | 4687 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { |
93ee2920 TR |
4688 | ret = sandybridge_pcode_read(dev_priv, |
4689 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
4690 | &ddcc_status); | |
4691 | if (0 == ret) | |
4692 | dev_priv->rps.efficient_freq = | |
46efa4ab TR |
4693 | clamp_t(u8, |
4694 | ((ddcc_status >> 8) & 0xff), | |
4695 | dev_priv->rps.min_freq, | |
4696 | dev_priv->rps.max_freq); | |
93ee2920 TR |
4697 | } |
4698 | ||
c5e0688c AG |
4699 | if (IS_SKYLAKE(dev)) { |
4700 | /* Store the frequency values in 16.66 MHZ units, which is | |
4701 | the natural hardware unit for SKL */ | |
4702 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; | |
4703 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; | |
4704 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; | |
4705 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; | |
4706 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; | |
4707 | } | |
4708 | ||
aed242ff CW |
4709 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
4710 | ||
3280e8b0 BW |
4711 | /* Preserve min/max settings in case of re-init */ |
4712 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4713 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4714 | ||
93ee2920 TR |
4715 | if (dev_priv->rps.min_freq_softlimit == 0) { |
4716 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
4717 | dev_priv->rps.min_freq_softlimit = | |
813b5e69 VS |
4718 | max_t(int, dev_priv->rps.efficient_freq, |
4719 | intel_freq_opcode(dev_priv, 450)); | |
93ee2920 TR |
4720 | else |
4721 | dev_priv->rps.min_freq_softlimit = | |
4722 | dev_priv->rps.min_freq; | |
4723 | } | |
3280e8b0 BW |
4724 | } |
4725 | ||
b6fef0ef | 4726 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
20e49366 | 4727 | static void gen9_enable_rps(struct drm_device *dev) |
b6fef0ef JB |
4728 | { |
4729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4730 | ||
4731 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4732 | ||
ba1c554c DL |
4733 | gen6_init_rps_frequencies(dev); |
4734 | ||
23eafea6 SAK |
4735 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
4736 | if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) { | |
4737 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4738 | return; | |
4739 | } | |
4740 | ||
0beb059a AG |
4741 | /* Program defaults and thresholds for RPS*/ |
4742 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4743 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4744 | ||
4745 | /* 1 second timeout*/ | |
4746 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, | |
4747 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); | |
4748 | ||
b6fef0ef | 4749 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
b6fef0ef | 4750 | |
0beb059a AG |
4751 | /* Leaning on the below call to gen6_set_rps to program/setup the |
4752 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, | |
4753 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ | |
4754 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ | |
4755 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
b6fef0ef JB |
4756 | |
4757 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4758 | } | |
4759 | ||
4760 | static void gen9_enable_rc6(struct drm_device *dev) | |
20e49366 ZW |
4761 | { |
4762 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4763 | struct intel_engine_cs *ring; | |
4764 | uint32_t rc6_mask = 0; | |
4765 | int unused; | |
4766 | ||
4767 | /* 1a: Software RC state - RC0 */ | |
4768 | I915_WRITE(GEN6_RC_STATE, 0); | |
4769 | ||
4770 | /* 1b: Get forcewake during program sequence. Although the driver | |
4771 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4772 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4773 | |
4774 | /* 2a: Disable RC states. */ | |
4775 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4776 | ||
4777 | /* 2b: Program RC6 thresholds.*/ | |
63a4dec2 SAK |
4778 | |
4779 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ | |
4780 | if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && | |
4781 | (INTEL_REVID(dev) <= SKL_REVID_E0))) | |
4782 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); | |
4783 | else | |
4784 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
20e49366 ZW |
4785 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
4786 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4787 | for_each_ring(ring, dev_priv, unused) | |
4788 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
97c322e7 SAK |
4789 | |
4790 | if (HAS_GUC_UCODE(dev)) | |
4791 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); | |
4792 | ||
20e49366 | 4793 | I915_WRITE(GEN6_RC_SLEEP, 0); |
20e49366 | 4794 | |
38c23527 ZW |
4795 | /* 2c: Program Coarse Power Gating Policies. */ |
4796 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
4797 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
4798 | ||
20e49366 ZW |
4799 | /* 3a: Enable RC6 */ |
4800 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4801 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
4802 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4803 | "on" : "off"); | |
3e7732a0 | 4804 | /* WaRsUseTimeoutMode */ |
e3429cd2 | 4805 | if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) || |
3e7732a0 SAK |
4806 | (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) { |
4807 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ | |
e3429cd2 SAK |
4808 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4809 | GEN7_RC_CTL_TO_MODE | | |
4810 | rc6_mask); | |
3e7732a0 SAK |
4811 | } else { |
4812 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ | |
e3429cd2 SAK |
4813 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4814 | GEN6_RC_CTL_EI_MODE(1) | | |
4815 | rc6_mask); | |
3e7732a0 | 4816 | } |
20e49366 | 4817 | |
cb07bae0 SK |
4818 | /* |
4819 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. | |
f2d2fe95 | 4820 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
cb07bae0 | 4821 | */ |
f2d2fe95 SAK |
4822 | if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || |
4823 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) | |
4824 | I915_WRITE(GEN9_PG_ENABLE, 0); | |
4825 | else | |
4826 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4827 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); | |
38c23527 | 4828 | |
59bad947 | 4829 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4830 | |
4831 | } | |
4832 | ||
6edee7f3 BW |
4833 | static void gen8_enable_rps(struct drm_device *dev) |
4834 | { | |
4835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4836 | struct intel_engine_cs *ring; |
93ee2920 | 4837 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
4838 | int unused; |
4839 | ||
4840 | /* 1a: Software RC state - RC0 */ | |
4841 | I915_WRITE(GEN6_RC_STATE, 0); | |
4842 | ||
4843 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
4844 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4845 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4846 | |
4847 | /* 2a: Disable RC states. */ | |
4848 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4849 | ||
93ee2920 TR |
4850 | /* Initialize rps frequencies */ |
4851 | gen6_init_rps_frequencies(dev); | |
6edee7f3 BW |
4852 | |
4853 | /* 2b: Program RC6 thresholds.*/ | |
4854 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4855 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4856 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4857 | for_each_ring(ring, dev_priv, unused) | |
4858 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4859 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
4860 | if (IS_BROADWELL(dev)) |
4861 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
4862 | else | |
4863 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
4864 | |
4865 | /* 3: Enable RC6 */ | |
4866 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4867 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 4868 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
4869 | if (IS_BROADWELL(dev)) |
4870 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4871 | GEN7_RC_CTL_TO_MODE | | |
4872 | rc6_mask); | |
4873 | else | |
4874 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4875 | GEN6_RC_CTL_EI_MODE(1) | | |
4876 | rc6_mask); | |
6edee7f3 BW |
4877 | |
4878 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
4879 | I915_WRITE(GEN6_RPNSWREQ, |
4880 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4881 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4882 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
4883 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4884 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
4885 | ||
4886 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
4887 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
4888 | dev_priv->rps.max_freq_softlimit << 24 | | |
4889 | dev_priv->rps.min_freq_softlimit << 16); | |
4890 | ||
4891 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
4892 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
4893 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
4894 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
4895 | ||
4896 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
4897 | |
4898 | /* 5: Enable RPS */ | |
7526ed79 DV |
4899 | I915_WRITE(GEN6_RP_CONTROL, |
4900 | GEN6_RP_MEDIA_TURBO | | |
4901 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4902 | GEN6_RP_MEDIA_IS_GFX | | |
4903 | GEN6_RP_ENABLE | | |
4904 | GEN6_RP_UP_BUSY_AVG | | |
4905 | GEN6_RP_DOWN_IDLE_AVG); | |
4906 | ||
4907 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
4908 | ||
c7f3153a | 4909 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
aed242ff | 4910 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
7526ed79 | 4911 | |
59bad947 | 4912 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4913 | } |
4914 | ||
79f5b2c7 | 4915 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 4916 | { |
79f5b2c7 | 4917 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4918 | struct intel_engine_cs *ring; |
d060c169 | 4919 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 4920 | u32 gtfifodbg; |
2b4e57bd | 4921 | int rc6_mode; |
42c0526c | 4922 | int i, ret; |
2b4e57bd | 4923 | |
4fc688ce | 4924 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4925 | |
2b4e57bd ED |
4926 | /* Here begins a magic sequence of register writes to enable |
4927 | * auto-downclocking. | |
4928 | * | |
4929 | * Perhaps there might be some value in exposing these to | |
4930 | * userspace... | |
4931 | */ | |
4932 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
4933 | |
4934 | /* Clear the DBG now so we don't confuse earlier errors */ | |
4935 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4936 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
4937 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4938 | } | |
4939 | ||
59bad947 | 4940 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 4941 | |
93ee2920 TR |
4942 | /* Initialize rps frequencies */ |
4943 | gen6_init_rps_frequencies(dev); | |
dd0a1aa1 | 4944 | |
2b4e57bd ED |
4945 | /* disable the counters and set deterministic thresholds */ |
4946 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4947 | ||
4948 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
4949 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
4950 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
4951 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4952 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4953 | ||
b4519513 CW |
4954 | for_each_ring(ring, dev_priv, i) |
4955 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
4956 | |
4957 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4958 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 4959 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
4960 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4961 | else | |
4962 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 4963 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
4964 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4965 | ||
5a7dc92a | 4966 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
4967 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4968 | if (rc6_mode & INTEL_RC6_ENABLE) | |
4969 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
4970 | ||
5a7dc92a ED |
4971 | /* We don't use those on Haswell */ |
4972 | if (!IS_HASWELL(dev)) { | |
4973 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
4974 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 4975 | |
5a7dc92a ED |
4976 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
4977 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
4978 | } | |
2b4e57bd | 4979 | |
dc39fff7 | 4980 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
4981 | |
4982 | I915_WRITE(GEN6_RC_CONTROL, | |
4983 | rc6_mask | | |
4984 | GEN6_RC_CTL_EI_MODE(1) | | |
4985 | GEN6_RC_CTL_HW_ENABLE); | |
4986 | ||
dd75fdc8 CW |
4987 | /* Power down if completely idle for over 50ms */ |
4988 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 4989 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 4990 | |
42c0526c | 4991 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 4992 | if (ret) |
42c0526c | 4993 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
4994 | |
4995 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
4996 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
4997 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 4998 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 4999 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 5000 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
5001 | } |
5002 | ||
dd75fdc8 | 5003 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
aed242ff | 5004 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
2b4e57bd | 5005 | |
31643d54 BW |
5006 | rc6vids = 0; |
5007 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
5008 | if (IS_GEN6(dev) && ret) { | |
5009 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
5010 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
5011 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
5012 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
5013 | rc6vids &= 0xffff00; | |
5014 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
5015 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
5016 | if (ret) | |
5017 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
5018 | } | |
5019 | ||
59bad947 | 5020 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
5021 | } |
5022 | ||
c2bc2fc5 | 5023 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 5024 | { |
79f5b2c7 | 5025 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 5026 | int min_freq = 15; |
3ebecd07 CW |
5027 | unsigned int gpu_freq; |
5028 | unsigned int max_ia_freq, min_ring_freq; | |
4c8c7743 | 5029 | unsigned int max_gpu_freq, min_gpu_freq; |
2b4e57bd | 5030 | int scaling_factor = 180; |
eda79642 | 5031 | struct cpufreq_policy *policy; |
2b4e57bd | 5032 | |
4fc688ce | 5033 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 5034 | |
eda79642 BW |
5035 | policy = cpufreq_cpu_get(0); |
5036 | if (policy) { | |
5037 | max_ia_freq = policy->cpuinfo.max_freq; | |
5038 | cpufreq_cpu_put(policy); | |
5039 | } else { | |
5040 | /* | |
5041 | * Default to measured freq if none found, PCU will ensure we | |
5042 | * don't go over | |
5043 | */ | |
2b4e57bd | 5044 | max_ia_freq = tsc_khz; |
eda79642 | 5045 | } |
2b4e57bd ED |
5046 | |
5047 | /* Convert from kHz to MHz */ | |
5048 | max_ia_freq /= 1000; | |
5049 | ||
153b4b95 | 5050 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
5051 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
5052 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 5053 | |
4c8c7743 AG |
5054 | if (IS_SKYLAKE(dev)) { |
5055 | /* Convert GT frequency to 50 HZ units */ | |
5056 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; | |
5057 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; | |
5058 | } else { | |
5059 | min_gpu_freq = dev_priv->rps.min_freq; | |
5060 | max_gpu_freq = dev_priv->rps.max_freq; | |
5061 | } | |
5062 | ||
2b4e57bd ED |
5063 | /* |
5064 | * For each potential GPU frequency, load a ring frequency we'd like | |
5065 | * to use for memory access. We do this by specifying the IA frequency | |
5066 | * the PCU should use as a reference to determine the ring frequency. | |
5067 | */ | |
4c8c7743 AG |
5068 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
5069 | int diff = max_gpu_freq - gpu_freq; | |
3ebecd07 CW |
5070 | unsigned int ia_freq = 0, ring_freq = 0; |
5071 | ||
4c8c7743 AG |
5072 | if (IS_SKYLAKE(dev)) { |
5073 | /* | |
5074 | * ring_freq = 2 * GT. ring_freq is in 100MHz units | |
5075 | * No floor required for ring frequency on SKL. | |
5076 | */ | |
5077 | ring_freq = gpu_freq; | |
5078 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
46c764d4 BW |
5079 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
5080 | ring_freq = max(min_ring_freq, gpu_freq); | |
5081 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 5082 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
5083 | ring_freq = max(min_ring_freq, ring_freq); |
5084 | /* leave ia_freq as the default, chosen by cpufreq */ | |
5085 | } else { | |
5086 | /* On older processors, there is no separate ring | |
5087 | * clock domain, so in order to boost the bandwidth | |
5088 | * of the ring, we need to upclock the CPU (ia_freq). | |
5089 | * | |
5090 | * For GPU frequencies less than 750MHz, | |
5091 | * just use the lowest ring freq. | |
5092 | */ | |
5093 | if (gpu_freq < min_freq) | |
5094 | ia_freq = 800; | |
5095 | else | |
5096 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
5097 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
5098 | } | |
2b4e57bd | 5099 | |
42c0526c BW |
5100 | sandybridge_pcode_write(dev_priv, |
5101 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
5102 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
5103 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
5104 | gpu_freq); | |
2b4e57bd | 5105 | } |
2b4e57bd ED |
5106 | } |
5107 | ||
c2bc2fc5 ID |
5108 | void gen6_update_ring_freq(struct drm_device *dev) |
5109 | { | |
5110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5111 | ||
97d3308a | 5112 | if (!HAS_CORE_RING_FREQ(dev)) |
c2bc2fc5 ID |
5113 | return; |
5114 | ||
5115 | mutex_lock(&dev_priv->rps.hw_lock); | |
5116 | __gen6_update_ring_freq(dev); | |
5117 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5118 | } | |
5119 | ||
03af2045 | 5120 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 | 5121 | { |
095acd5f | 5122 | struct drm_device *dev = dev_priv->dev; |
2b6b3a09 D |
5123 | u32 val, rp0; |
5124 | ||
5b5929cb | 5125 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
2b6b3a09 | 5126 | |
5b5929cb JN |
5127 | switch (INTEL_INFO(dev)->eu_total) { |
5128 | case 8: | |
5129 | /* (2 * 4) config */ | |
5130 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
5131 | break; | |
5132 | case 12: | |
5133 | /* (2 * 6) config */ | |
5134 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
5135 | break; | |
5136 | case 16: | |
5137 | /* (2 * 8) config */ | |
5138 | default: | |
5139 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
5140 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
5141 | break; | |
095acd5f | 5142 | } |
5b5929cb JN |
5143 | |
5144 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
5145 | ||
2b6b3a09 D |
5146 | return rp0; |
5147 | } | |
5148 | ||
5149 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
5150 | { | |
5151 | u32 val, rpe; | |
5152 | ||
5153 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
5154 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
5155 | ||
5156 | return rpe; | |
5157 | } | |
5158 | ||
7707df4a D |
5159 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5160 | { | |
5161 | u32 val, rp1; | |
5162 | ||
5b5929cb JN |
5163 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
5164 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
5165 | ||
7707df4a D |
5166 | return rp1; |
5167 | } | |
5168 | ||
f8f2b001 D |
5169 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5170 | { | |
5171 | u32 val, rp1; | |
5172 | ||
5173 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
5174 | ||
5175 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
5176 | ||
5177 | return rp1; | |
5178 | } | |
5179 | ||
03af2045 | 5180 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
5181 | { |
5182 | u32 val, rp0; | |
5183 | ||
64936258 | 5184 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
5185 | |
5186 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
5187 | /* Clamp to max */ | |
5188 | rp0 = min_t(u32, rp0, 0xea); | |
5189 | ||
5190 | return rp0; | |
5191 | } | |
5192 | ||
5193 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
5194 | { | |
5195 | u32 val, rpe; | |
5196 | ||
64936258 | 5197 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 5198 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 5199 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
5200 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
5201 | ||
5202 | return rpe; | |
5203 | } | |
5204 | ||
03af2045 | 5205 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 5206 | { |
64936258 | 5207 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
5208 | } |
5209 | ||
ae48434c ID |
5210 | /* Check that the pctx buffer wasn't move under us. */ |
5211 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
5212 | { | |
5213 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
5214 | ||
5215 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
5216 | dev_priv->vlv_pctx->stolen->start); | |
5217 | } | |
5218 | ||
38807746 D |
5219 | |
5220 | /* Check that the pcbr address is not empty. */ | |
5221 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
5222 | { | |
5223 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
5224 | ||
5225 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
5226 | } | |
5227 | ||
5228 | static void cherryview_setup_pctx(struct drm_device *dev) | |
5229 | { | |
5230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5231 | unsigned long pctx_paddr, paddr; | |
5232 | struct i915_gtt *gtt = &dev_priv->gtt; | |
5233 | u32 pcbr; | |
5234 | int pctx_size = 32*1024; | |
5235 | ||
5236 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
5237 | ||
5238 | pcbr = I915_READ(VLV_PCBR); | |
5239 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 5240 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 D |
5241 | paddr = (dev_priv->mm.stolen_base + |
5242 | (gtt->stolen_size - pctx_size)); | |
5243 | ||
5244 | pctx_paddr = (paddr & (~4095)); | |
5245 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
5246 | } | |
ce611ef8 VS |
5247 | |
5248 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
5249 | } |
5250 | ||
c9cddffc JB |
5251 | static void valleyview_setup_pctx(struct drm_device *dev) |
5252 | { | |
5253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5254 | struct drm_i915_gem_object *pctx; | |
5255 | unsigned long pctx_paddr; | |
5256 | u32 pcbr; | |
5257 | int pctx_size = 24*1024; | |
5258 | ||
17b0c1f7 ID |
5259 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5260 | ||
c9cddffc JB |
5261 | pcbr = I915_READ(VLV_PCBR); |
5262 | if (pcbr) { | |
5263 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
5264 | int pcbr_offset; | |
5265 | ||
5266 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
5267 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
5268 | pcbr_offset, | |
190d6cd5 | 5269 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
5270 | pctx_size); |
5271 | goto out; | |
5272 | } | |
5273 | ||
ce611ef8 VS |
5274 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5275 | ||
c9cddffc JB |
5276 | /* |
5277 | * From the Gunit register HAS: | |
5278 | * The Gfx driver is expected to program this register and ensure | |
5279 | * proper allocation within Gfx stolen memory. For example, this | |
5280 | * register should be programmed such than the PCBR range does not | |
5281 | * overlap with other ranges, such as the frame buffer, protected | |
5282 | * memory, or any other relevant ranges. | |
5283 | */ | |
5284 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
5285 | if (!pctx) { | |
5286 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
5287 | return; | |
5288 | } | |
5289 | ||
5290 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
5291 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
5292 | ||
5293 | out: | |
ce611ef8 | 5294 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
5295 | dev_priv->vlv_pctx = pctx; |
5296 | } | |
5297 | ||
ae48434c ID |
5298 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
5299 | { | |
5300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5301 | ||
5302 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
5303 | return; | |
5304 | ||
5305 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
5306 | dev_priv->vlv_pctx = NULL; | |
5307 | } | |
5308 | ||
4e80519e ID |
5309 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
5310 | { | |
5311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bb25c17 | 5312 | u32 val; |
4e80519e ID |
5313 | |
5314 | valleyview_setup_pctx(dev); | |
5315 | ||
5316 | mutex_lock(&dev_priv->rps.hw_lock); | |
5317 | ||
2bb25c17 VS |
5318 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5319 | switch ((val >> 6) & 3) { | |
5320 | case 0: | |
5321 | case 1: | |
5322 | dev_priv->mem_freq = 800; | |
5323 | break; | |
5324 | case 2: | |
5325 | dev_priv->mem_freq = 1066; | |
5326 | break; | |
5327 | case 3: | |
5328 | dev_priv->mem_freq = 1333; | |
5329 | break; | |
5330 | } | |
80b83b62 | 5331 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 5332 | |
4e80519e ID |
5333 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
5334 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
5335 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5336 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
5337 | dev_priv->rps.max_freq); |
5338 | ||
5339 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
5340 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5341 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
5342 | dev_priv->rps.efficient_freq); |
5343 | ||
f8f2b001 D |
5344 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
5345 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5346 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
5347 | dev_priv->rps.rp1_freq); |
5348 | ||
4e80519e ID |
5349 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
5350 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5351 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e ID |
5352 | dev_priv->rps.min_freq); |
5353 | ||
aed242ff CW |
5354 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5355 | ||
4e80519e ID |
5356 | /* Preserve min/max settings in case of re-init */ |
5357 | if (dev_priv->rps.max_freq_softlimit == 0) | |
5358 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
5359 | ||
5360 | if (dev_priv->rps.min_freq_softlimit == 0) | |
5361 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
5362 | ||
5363 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5364 | } | |
5365 | ||
38807746 D |
5366 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
5367 | { | |
2b6b3a09 | 5368 | struct drm_i915_private *dev_priv = dev->dev_private; |
2bb25c17 | 5369 | u32 val; |
2b6b3a09 | 5370 | |
38807746 | 5371 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
5372 | |
5373 | mutex_lock(&dev_priv->rps.hw_lock); | |
5374 | ||
a580516d | 5375 | mutex_lock(&dev_priv->sb_lock); |
c6e8f39d | 5376 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
a580516d | 5377 | mutex_unlock(&dev_priv->sb_lock); |
c6e8f39d | 5378 | |
2bb25c17 | 5379 | switch ((val >> 2) & 0x7) { |
2bb25c17 | 5380 | case 3: |
2bb25c17 VS |
5381 | dev_priv->mem_freq = 2000; |
5382 | break; | |
bfa7df01 | 5383 | default: |
2bb25c17 VS |
5384 | dev_priv->mem_freq = 1600; |
5385 | break; | |
5386 | } | |
80b83b62 | 5387 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 5388 | |
2b6b3a09 D |
5389 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
5390 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
5391 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5392 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
5393 | dev_priv->rps.max_freq); |
5394 | ||
5395 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
5396 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5397 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
5398 | dev_priv->rps.efficient_freq); |
5399 | ||
7707df4a D |
5400 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
5401 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5402 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
5403 | dev_priv->rps.rp1_freq); |
5404 | ||
5b7c91b7 D |
5405 | /* PUnit validated range is only [RPe, RP0] */ |
5406 | dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; | |
2b6b3a09 | 5407 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 5408 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
5409 | dev_priv->rps.min_freq); |
5410 | ||
1c14762d VS |
5411 | WARN_ONCE((dev_priv->rps.max_freq | |
5412 | dev_priv->rps.efficient_freq | | |
5413 | dev_priv->rps.rp1_freq | | |
5414 | dev_priv->rps.min_freq) & 1, | |
5415 | "Odd GPU freq values\n"); | |
5416 | ||
aed242ff CW |
5417 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5418 | ||
2b6b3a09 D |
5419 | /* Preserve min/max settings in case of re-init */ |
5420 | if (dev_priv->rps.max_freq_softlimit == 0) | |
5421 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
5422 | ||
5423 | if (dev_priv->rps.min_freq_softlimit == 0) | |
5424 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
5425 | ||
5426 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
5427 | } |
5428 | ||
4e80519e ID |
5429 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
5430 | { | |
5431 | valleyview_cleanup_pctx(dev); | |
5432 | } | |
5433 | ||
38807746 D |
5434 | static void cherryview_enable_rps(struct drm_device *dev) |
5435 | { | |
5436 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5437 | struct intel_engine_cs *ring; | |
2b6b3a09 | 5438 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
5439 | int i; |
5440 | ||
5441 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5442 | ||
5443 | gtfifodbg = I915_READ(GTFIFODBG); | |
5444 | if (gtfifodbg) { | |
5445 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
5446 | gtfifodbg); | |
5447 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
5448 | } | |
5449 | ||
5450 | cherryview_check_pctx(dev_priv); | |
5451 | ||
5452 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
5453 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 5454 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 5455 | |
160614a2 VS |
5456 | /* Disable RC states. */ |
5457 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5458 | ||
38807746 D |
5459 | /* 2a: Program RC6 thresholds.*/ |
5460 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
5461 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
5462 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
5463 | ||
5464 | for_each_ring(ring, dev_priv, i) | |
5465 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5466 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
5467 | ||
f4f71c7d D |
5468 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
5469 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); | |
38807746 D |
5470 | |
5471 | /* allows RC6 residency counter to work */ | |
5472 | I915_WRITE(VLV_COUNTER_CONTROL, | |
5473 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
5474 | VLV_MEDIA_RC6_COUNT_EN | | |
5475 | VLV_RENDER_RC6_COUNT_EN)); | |
5476 | ||
5477 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
5478 | pcbr = I915_READ(VLV_PCBR); | |
5479 | ||
38807746 D |
5480 | /* 3: Enable RC6 */ |
5481 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
5482 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 5483 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
5484 | |
5485 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
5486 | ||
2b6b3a09 | 5487 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 5488 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
5489 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5490 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5491 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5492 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5493 | ||
5494 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5495 | ||
5496 | /* 5: Enable RPS */ | |
5497 | I915_WRITE(GEN6_RP_CONTROL, | |
5498 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 5499 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
5500 | GEN6_RP_ENABLE | |
5501 | GEN6_RP_UP_BUSY_AVG | | |
5502 | GEN6_RP_DOWN_IDLE_AVG); | |
5503 | ||
3ef62342 D |
5504 | /* Setting Fixed Bias */ |
5505 | val = VLV_OVERRIDE_EN | | |
5506 | VLV_SOC_TDP_EN | | |
5507 | CHV_BIAS_CPU_50_SOC_50; | |
5508 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
5509 | ||
2b6b3a09 D |
5510 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5511 | ||
8d40c3ae VS |
5512 | /* RPS code assumes GPLL is used */ |
5513 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
5514 | ||
742f491d | 5515 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
2b6b3a09 D |
5516 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5517 | ||
5518 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
5519 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5520 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
2b6b3a09 D |
5521 | dev_priv->rps.cur_freq); |
5522 | ||
5523 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
7c59a9c1 | 5524 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
5525 | dev_priv->rps.efficient_freq); |
5526 | ||
5527 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
5528 | ||
59bad947 | 5529 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
5530 | } |
5531 | ||
0a073b84 JB |
5532 | static void valleyview_enable_rps(struct drm_device *dev) |
5533 | { | |
5534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 5535 | struct intel_engine_cs *ring; |
2a5913a8 | 5536 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
5537 | int i; |
5538 | ||
5539 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5540 | ||
ae48434c ID |
5541 | valleyview_check_pctx(dev_priv); |
5542 | ||
0a073b84 | 5543 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
5544 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5545 | gtfifodbg); | |
0a073b84 JB |
5546 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5547 | } | |
5548 | ||
c8d9a590 | 5549 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 5550 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 5551 | |
160614a2 VS |
5552 | /* Disable RC states. */ |
5553 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5554 | ||
cad725fe | 5555 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
5556 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5557 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5558 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5559 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5560 | ||
5561 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5562 | ||
5563 | I915_WRITE(GEN6_RP_CONTROL, | |
5564 | GEN6_RP_MEDIA_TURBO | | |
5565 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5566 | GEN6_RP_MEDIA_IS_GFX | | |
5567 | GEN6_RP_ENABLE | | |
5568 | GEN6_RP_UP_BUSY_AVG | | |
5569 | GEN6_RP_DOWN_IDLE_CONT); | |
5570 | ||
5571 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
5572 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
5573 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
5574 | ||
5575 | for_each_ring(ring, dev_priv, i) | |
5576 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5577 | ||
2f0aa304 | 5578 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
5579 | |
5580 | /* allows RC6 residency counter to work */ | |
49798eb2 | 5581 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
5582 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
5583 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
5584 | VLV_MEDIA_RC6_COUNT_EN | |
5585 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 5586 | |
a2b23fe0 | 5587 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 5588 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
5589 | |
5590 | intel_print_rc6_info(dev, rc6_mode); | |
5591 | ||
a2b23fe0 | 5592 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 5593 | |
3ef62342 D |
5594 | /* Setting Fixed Bias */ |
5595 | val = VLV_OVERRIDE_EN | | |
5596 | VLV_SOC_TDP_EN | | |
5597 | VLV_BIAS_CPU_125_SOC_875; | |
5598 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
5599 | ||
64936258 | 5600 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 5601 | |
8d40c3ae VS |
5602 | /* RPS code assumes GPLL is used */ |
5603 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
5604 | ||
742f491d | 5605 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
0a073b84 JB |
5606 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5607 | ||
b39fb297 | 5608 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 5609 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 5610 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
b39fb297 | 5611 | dev_priv->rps.cur_freq); |
0a073b84 | 5612 | |
73008b98 | 5613 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
7c59a9c1 | 5614 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
b39fb297 | 5615 | dev_priv->rps.efficient_freq); |
0a073b84 | 5616 | |
b39fb297 | 5617 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 5618 | |
59bad947 | 5619 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
5620 | } |
5621 | ||
dde18883 ED |
5622 | static unsigned long intel_pxfreq(u32 vidfreq) |
5623 | { | |
5624 | unsigned long freq; | |
5625 | int div = (vidfreq & 0x3f0000) >> 16; | |
5626 | int post = (vidfreq & 0x3000) >> 12; | |
5627 | int pre = (vidfreq & 0x7); | |
5628 | ||
5629 | if (!pre) | |
5630 | return 0; | |
5631 | ||
5632 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5633 | ||
5634 | return freq; | |
5635 | } | |
5636 | ||
eb48eb00 DV |
5637 | static const struct cparams { |
5638 | u16 i; | |
5639 | u16 t; | |
5640 | u16 m; | |
5641 | u16 c; | |
5642 | } cparams[] = { | |
5643 | { 1, 1333, 301, 28664 }, | |
5644 | { 1, 1066, 294, 24460 }, | |
5645 | { 1, 800, 294, 25192 }, | |
5646 | { 0, 1333, 276, 27605 }, | |
5647 | { 0, 1066, 276, 27605 }, | |
5648 | { 0, 800, 231, 23784 }, | |
5649 | }; | |
5650 | ||
f531dcb2 | 5651 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5652 | { |
5653 | u64 total_count, diff, ret; | |
5654 | u32 count1, count2, count3, m = 0, c = 0; | |
5655 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
5656 | int i; | |
5657 | ||
02d71956 DV |
5658 | assert_spin_locked(&mchdev_lock); |
5659 | ||
20e4d407 | 5660 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
5661 | |
5662 | /* Prevent division-by-zero if we are asking too fast. | |
5663 | * Also, we don't get interesting results if we are polling | |
5664 | * faster than once in 10ms, so just return the saved value | |
5665 | * in such cases. | |
5666 | */ | |
5667 | if (diff1 <= 10) | |
20e4d407 | 5668 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
5669 | |
5670 | count1 = I915_READ(DMIEC); | |
5671 | count2 = I915_READ(DDREC); | |
5672 | count3 = I915_READ(CSIEC); | |
5673 | ||
5674 | total_count = count1 + count2 + count3; | |
5675 | ||
5676 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
5677 | if (total_count < dev_priv->ips.last_count1) { |
5678 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
5679 | diff += total_count; |
5680 | } else { | |
20e4d407 | 5681 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
5682 | } |
5683 | ||
5684 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
5685 | if (cparams[i].i == dev_priv->ips.c_m && |
5686 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
5687 | m = cparams[i].m; |
5688 | c = cparams[i].c; | |
5689 | break; | |
5690 | } | |
5691 | } | |
5692 | ||
5693 | diff = div_u64(diff, diff1); | |
5694 | ret = ((m * diff) + c); | |
5695 | ret = div_u64(ret, 10); | |
5696 | ||
20e4d407 DV |
5697 | dev_priv->ips.last_count1 = total_count; |
5698 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 5699 | |
20e4d407 | 5700 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
5701 | |
5702 | return ret; | |
5703 | } | |
5704 | ||
f531dcb2 CW |
5705 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5706 | { | |
3d13ef2e | 5707 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5708 | unsigned long val; |
5709 | ||
3d13ef2e | 5710 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5711 | return 0; |
5712 | ||
5713 | spin_lock_irq(&mchdev_lock); | |
5714 | ||
5715 | val = __i915_chipset_val(dev_priv); | |
5716 | ||
5717 | spin_unlock_irq(&mchdev_lock); | |
5718 | ||
5719 | return val; | |
5720 | } | |
5721 | ||
eb48eb00 DV |
5722 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5723 | { | |
5724 | unsigned long m, x, b; | |
5725 | u32 tsfs; | |
5726 | ||
5727 | tsfs = I915_READ(TSFS); | |
5728 | ||
5729 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
5730 | x = I915_READ8(TR1); | |
5731 | ||
5732 | b = tsfs & TSFS_INTR_MASK; | |
5733 | ||
5734 | return ((m * x) / 127) - b; | |
5735 | } | |
5736 | ||
d972d6ee MK |
5737 | static int _pxvid_to_vd(u8 pxvid) |
5738 | { | |
5739 | if (pxvid == 0) | |
5740 | return 0; | |
5741 | ||
5742 | if (pxvid >= 8 && pxvid < 31) | |
5743 | pxvid = 31; | |
5744 | ||
5745 | return (pxvid + 2) * 125; | |
5746 | } | |
5747 | ||
5748 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 5749 | { |
3d13ef2e | 5750 | struct drm_device *dev = dev_priv->dev; |
d972d6ee MK |
5751 | const int vd = _pxvid_to_vd(pxvid); |
5752 | const int vm = vd - 1125; | |
5753 | ||
3d13ef2e | 5754 | if (INTEL_INFO(dev)->is_mobile) |
d972d6ee MK |
5755 | return vm > 0 ? vm : 0; |
5756 | ||
5757 | return vd; | |
eb48eb00 DV |
5758 | } |
5759 | ||
02d71956 | 5760 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 5761 | { |
5ed0bdf2 | 5762 | u64 now, diff, diffms; |
eb48eb00 DV |
5763 | u32 count; |
5764 | ||
02d71956 | 5765 | assert_spin_locked(&mchdev_lock); |
eb48eb00 | 5766 | |
5ed0bdf2 TG |
5767 | now = ktime_get_raw_ns(); |
5768 | diffms = now - dev_priv->ips.last_time2; | |
5769 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
5770 | |
5771 | /* Don't divide by 0 */ | |
eb48eb00 DV |
5772 | if (!diffms) |
5773 | return; | |
5774 | ||
5775 | count = I915_READ(GFXEC); | |
5776 | ||
20e4d407 DV |
5777 | if (count < dev_priv->ips.last_count2) { |
5778 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
5779 | diff += count; |
5780 | } else { | |
20e4d407 | 5781 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
5782 | } |
5783 | ||
20e4d407 DV |
5784 | dev_priv->ips.last_count2 = count; |
5785 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
5786 | |
5787 | /* More magic constants... */ | |
5788 | diff = diff * 1181; | |
5789 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 5790 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
5791 | } |
5792 | ||
02d71956 DV |
5793 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5794 | { | |
3d13ef2e DL |
5795 | struct drm_device *dev = dev_priv->dev; |
5796 | ||
5797 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
5798 | return; |
5799 | ||
9270388e | 5800 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
5801 | |
5802 | __i915_update_gfx_val(dev_priv); | |
5803 | ||
9270388e | 5804 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
5805 | } |
5806 | ||
f531dcb2 | 5807 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5808 | { |
5809 | unsigned long t, corr, state1, corr2, state2; | |
5810 | u32 pxvid, ext_v; | |
5811 | ||
02d71956 DV |
5812 | assert_spin_locked(&mchdev_lock); |
5813 | ||
616847e7 | 5814 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
eb48eb00 DV |
5815 | pxvid = (pxvid >> 24) & 0x7f; |
5816 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5817 | ||
5818 | state1 = ext_v; | |
5819 | ||
5820 | t = i915_mch_val(dev_priv); | |
5821 | ||
5822 | /* Revel in the empirically derived constants */ | |
5823 | ||
5824 | /* Correction factor in 1/100000 units */ | |
5825 | if (t > 80) | |
5826 | corr = ((t * 2349) + 135940); | |
5827 | else if (t >= 50) | |
5828 | corr = ((t * 964) + 29317); | |
5829 | else /* < 50 */ | |
5830 | corr = ((t * 301) + 1004); | |
5831 | ||
5832 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5833 | corr /= 100000; | |
20e4d407 | 5834 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
5835 | |
5836 | state2 = (corr2 * state1) / 10000; | |
5837 | state2 /= 100; /* convert to mW */ | |
5838 | ||
02d71956 | 5839 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 5840 | |
20e4d407 | 5841 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
5842 | } |
5843 | ||
f531dcb2 CW |
5844 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5845 | { | |
3d13ef2e | 5846 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5847 | unsigned long val; |
5848 | ||
3d13ef2e | 5849 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5850 | return 0; |
5851 | ||
5852 | spin_lock_irq(&mchdev_lock); | |
5853 | ||
5854 | val = __i915_gfx_val(dev_priv); | |
5855 | ||
5856 | spin_unlock_irq(&mchdev_lock); | |
5857 | ||
5858 | return val; | |
5859 | } | |
5860 | ||
eb48eb00 DV |
5861 | /** |
5862 | * i915_read_mch_val - return value for IPS use | |
5863 | * | |
5864 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5865 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5866 | */ | |
5867 | unsigned long i915_read_mch_val(void) | |
5868 | { | |
5869 | struct drm_i915_private *dev_priv; | |
5870 | unsigned long chipset_val, graphics_val, ret = 0; | |
5871 | ||
9270388e | 5872 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5873 | if (!i915_mch_dev) |
5874 | goto out_unlock; | |
5875 | dev_priv = i915_mch_dev; | |
5876 | ||
f531dcb2 CW |
5877 | chipset_val = __i915_chipset_val(dev_priv); |
5878 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
5879 | |
5880 | ret = chipset_val + graphics_val; | |
5881 | ||
5882 | out_unlock: | |
9270388e | 5883 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5884 | |
5885 | return ret; | |
5886 | } | |
5887 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5888 | ||
5889 | /** | |
5890 | * i915_gpu_raise - raise GPU frequency limit | |
5891 | * | |
5892 | * Raise the limit; IPS indicates we have thermal headroom. | |
5893 | */ | |
5894 | bool i915_gpu_raise(void) | |
5895 | { | |
5896 | struct drm_i915_private *dev_priv; | |
5897 | bool ret = true; | |
5898 | ||
9270388e | 5899 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5900 | if (!i915_mch_dev) { |
5901 | ret = false; | |
5902 | goto out_unlock; | |
5903 | } | |
5904 | dev_priv = i915_mch_dev; | |
5905 | ||
20e4d407 DV |
5906 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5907 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
5908 | |
5909 | out_unlock: | |
9270388e | 5910 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5911 | |
5912 | return ret; | |
5913 | } | |
5914 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5915 | ||
5916 | /** | |
5917 | * i915_gpu_lower - lower GPU frequency limit | |
5918 | * | |
5919 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5920 | * frequency maximum. | |
5921 | */ | |
5922 | bool i915_gpu_lower(void) | |
5923 | { | |
5924 | struct drm_i915_private *dev_priv; | |
5925 | bool ret = true; | |
5926 | ||
9270388e | 5927 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5928 | if (!i915_mch_dev) { |
5929 | ret = false; | |
5930 | goto out_unlock; | |
5931 | } | |
5932 | dev_priv = i915_mch_dev; | |
5933 | ||
20e4d407 DV |
5934 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5935 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
5936 | |
5937 | out_unlock: | |
9270388e | 5938 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5939 | |
5940 | return ret; | |
5941 | } | |
5942 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5943 | ||
5944 | /** | |
5945 | * i915_gpu_busy - indicate GPU business to IPS | |
5946 | * | |
5947 | * Tell the IPS driver whether or not the GPU is busy. | |
5948 | */ | |
5949 | bool i915_gpu_busy(void) | |
5950 | { | |
5951 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 5952 | struct intel_engine_cs *ring; |
eb48eb00 | 5953 | bool ret = false; |
f047e395 | 5954 | int i; |
eb48eb00 | 5955 | |
9270388e | 5956 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5957 | if (!i915_mch_dev) |
5958 | goto out_unlock; | |
5959 | dev_priv = i915_mch_dev; | |
5960 | ||
f047e395 CW |
5961 | for_each_ring(ring, dev_priv, i) |
5962 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
5963 | |
5964 | out_unlock: | |
9270388e | 5965 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5966 | |
5967 | return ret; | |
5968 | } | |
5969 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5970 | ||
5971 | /** | |
5972 | * i915_gpu_turbo_disable - disable graphics turbo | |
5973 | * | |
5974 | * Disable graphics turbo by resetting the max frequency and setting the | |
5975 | * current frequency to the default. | |
5976 | */ | |
5977 | bool i915_gpu_turbo_disable(void) | |
5978 | { | |
5979 | struct drm_i915_private *dev_priv; | |
5980 | bool ret = true; | |
5981 | ||
9270388e | 5982 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5983 | if (!i915_mch_dev) { |
5984 | ret = false; | |
5985 | goto out_unlock; | |
5986 | } | |
5987 | dev_priv = i915_mch_dev; | |
5988 | ||
20e4d407 | 5989 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 5990 | |
20e4d407 | 5991 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
5992 | ret = false; |
5993 | ||
5994 | out_unlock: | |
9270388e | 5995 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5996 | |
5997 | return ret; | |
5998 | } | |
5999 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
6000 | ||
6001 | /** | |
6002 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
6003 | * IPS got loaded first. | |
6004 | * | |
6005 | * This awkward dance is so that neither module has to depend on the | |
6006 | * other in order for IPS to do the appropriate communication of | |
6007 | * GPU turbo limits to i915. | |
6008 | */ | |
6009 | static void | |
6010 | ips_ping_for_i915_load(void) | |
6011 | { | |
6012 | void (*link)(void); | |
6013 | ||
6014 | link = symbol_get(ips_link_to_i915_driver); | |
6015 | if (link) { | |
6016 | link(); | |
6017 | symbol_put(ips_link_to_i915_driver); | |
6018 | } | |
6019 | } | |
6020 | ||
6021 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
6022 | { | |
02d71956 DV |
6023 | /* We only register the i915 ips part with intel-ips once everything is |
6024 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 6025 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 6026 | i915_mch_dev = dev_priv; |
9270388e | 6027 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6028 | |
6029 | ips_ping_for_i915_load(); | |
6030 | } | |
6031 | ||
6032 | void intel_gpu_ips_teardown(void) | |
6033 | { | |
9270388e | 6034 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 6035 | i915_mch_dev = NULL; |
9270388e | 6036 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 6037 | } |
76c3552f | 6038 | |
8090c6b9 | 6039 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
6040 | { |
6041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6042 | u32 lcfuse; | |
6043 | u8 pxw[16]; | |
6044 | int i; | |
6045 | ||
6046 | /* Disable to program */ | |
6047 | I915_WRITE(ECR, 0); | |
6048 | POSTING_READ(ECR); | |
6049 | ||
6050 | /* Program energy weights for various events */ | |
6051 | I915_WRITE(SDEW, 0x15040d00); | |
6052 | I915_WRITE(CSIEW0, 0x007f0000); | |
6053 | I915_WRITE(CSIEW1, 0x1e220004); | |
6054 | I915_WRITE(CSIEW2, 0x04000004); | |
6055 | ||
6056 | for (i = 0; i < 5; i++) | |
616847e7 | 6057 | I915_WRITE(PEW(i), 0); |
dde18883 | 6058 | for (i = 0; i < 3; i++) |
616847e7 | 6059 | I915_WRITE(DEW(i), 0); |
dde18883 ED |
6060 | |
6061 | /* Program P-state weights to account for frequency power adjustment */ | |
6062 | for (i = 0; i < 16; i++) { | |
616847e7 | 6063 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
dde18883 ED |
6064 | unsigned long freq = intel_pxfreq(pxvidfreq); |
6065 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
6066 | PXVFREQ_PX_SHIFT; | |
6067 | unsigned long val; | |
6068 | ||
6069 | val = vid * vid; | |
6070 | val *= (freq / 1000); | |
6071 | val *= 255; | |
6072 | val /= (127*127*900); | |
6073 | if (val > 0xff) | |
6074 | DRM_ERROR("bad pxval: %ld\n", val); | |
6075 | pxw[i] = val; | |
6076 | } | |
6077 | /* Render standby states get 0 weight */ | |
6078 | pxw[14] = 0; | |
6079 | pxw[15] = 0; | |
6080 | ||
6081 | for (i = 0; i < 4; i++) { | |
6082 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
6083 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
616847e7 | 6084 | I915_WRITE(PXW(i), val); |
dde18883 ED |
6085 | } |
6086 | ||
6087 | /* Adjust magic regs to magic values (more experimental results) */ | |
6088 | I915_WRITE(OGW0, 0); | |
6089 | I915_WRITE(OGW1, 0); | |
6090 | I915_WRITE(EG0, 0x00007f00); | |
6091 | I915_WRITE(EG1, 0x0000000e); | |
6092 | I915_WRITE(EG2, 0x000e0000); | |
6093 | I915_WRITE(EG3, 0x68000300); | |
6094 | I915_WRITE(EG4, 0x42000000); | |
6095 | I915_WRITE(EG5, 0x00140031); | |
6096 | I915_WRITE(EG6, 0); | |
6097 | I915_WRITE(EG7, 0); | |
6098 | ||
6099 | for (i = 0; i < 8; i++) | |
616847e7 | 6100 | I915_WRITE(PXWL(i), 0); |
dde18883 ED |
6101 | |
6102 | /* Enable PMON + select events */ | |
6103 | I915_WRITE(ECR, 0x80000019); | |
6104 | ||
6105 | lcfuse = I915_READ(LCFUSE02); | |
6106 | ||
20e4d407 | 6107 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
6108 | } |
6109 | ||
ae48434c ID |
6110 | void intel_init_gt_powersave(struct drm_device *dev) |
6111 | { | |
e6069ca8 ID |
6112 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
6113 | ||
38807746 D |
6114 | if (IS_CHERRYVIEW(dev)) |
6115 | cherryview_init_gt_powersave(dev); | |
6116 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 6117 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
6118 | } |
6119 | ||
6120 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
6121 | { | |
38807746 D |
6122 | if (IS_CHERRYVIEW(dev)) |
6123 | return; | |
6124 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 6125 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
6126 | } |
6127 | ||
dbea3cea ID |
6128 | static void gen6_suspend_rps(struct drm_device *dev) |
6129 | { | |
6130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6131 | ||
6132 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
6133 | ||
4c2a8897 | 6134 | gen6_disable_rps_interrupts(dev); |
dbea3cea ID |
6135 | } |
6136 | ||
156c7ca0 JB |
6137 | /** |
6138 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
6139 | * @dev: drm device | |
6140 | * | |
6141 | * We don't want to disable RC6 or other features here, we just want | |
6142 | * to make sure any work we've queued has finished and won't bother | |
6143 | * us while we're suspended. | |
6144 | */ | |
6145 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
6146 | { | |
6147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6148 | ||
d4d70aa5 ID |
6149 | if (INTEL_INFO(dev)->gen < 6) |
6150 | return; | |
6151 | ||
dbea3cea | 6152 | gen6_suspend_rps(dev); |
b47adc17 D |
6153 | |
6154 | /* Force GPU to min freq during suspend */ | |
6155 | gen6_rps_idle(dev_priv); | |
156c7ca0 JB |
6156 | } |
6157 | ||
8090c6b9 DV |
6158 | void intel_disable_gt_powersave(struct drm_device *dev) |
6159 | { | |
1a01ab3b JB |
6160 | struct drm_i915_private *dev_priv = dev->dev_private; |
6161 | ||
930ebb46 | 6162 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 6163 | ironlake_disable_drps(dev); |
38807746 | 6164 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 6165 | intel_suspend_gt_powersave(dev); |
e494837a | 6166 | |
4fc688ce | 6167 | mutex_lock(&dev_priv->rps.hw_lock); |
20e49366 ZW |
6168 | if (INTEL_INFO(dev)->gen >= 9) |
6169 | gen9_disable_rps(dev); | |
6170 | else if (IS_CHERRYVIEW(dev)) | |
38807746 D |
6171 | cherryview_disable_rps(dev); |
6172 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
6173 | valleyview_disable_rps(dev); |
6174 | else | |
6175 | gen6_disable_rps(dev); | |
e534770a | 6176 | |
c0951f0c | 6177 | dev_priv->rps.enabled = false; |
4fc688ce | 6178 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 6179 | } |
8090c6b9 DV |
6180 | } |
6181 | ||
1a01ab3b JB |
6182 | static void intel_gen6_powersave_work(struct work_struct *work) |
6183 | { | |
6184 | struct drm_i915_private *dev_priv = | |
6185 | container_of(work, struct drm_i915_private, | |
6186 | rps.delayed_resume_work.work); | |
6187 | struct drm_device *dev = dev_priv->dev; | |
6188 | ||
4fc688ce | 6189 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 6190 | |
4c2a8897 | 6191 | gen6_reset_rps_interrupts(dev); |
3cc134e3 | 6192 | |
38807746 D |
6193 | if (IS_CHERRYVIEW(dev)) { |
6194 | cherryview_enable_rps(dev); | |
6195 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 6196 | valleyview_enable_rps(dev); |
20e49366 | 6197 | } else if (INTEL_INFO(dev)->gen >= 9) { |
b6fef0ef | 6198 | gen9_enable_rc6(dev); |
20e49366 | 6199 | gen9_enable_rps(dev); |
cc017fb4 AG |
6200 | if (IS_SKYLAKE(dev)) |
6201 | __gen6_update_ring_freq(dev); | |
6edee7f3 BW |
6202 | } else if (IS_BROADWELL(dev)) { |
6203 | gen8_enable_rps(dev); | |
c2bc2fc5 | 6204 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
6205 | } else { |
6206 | gen6_enable_rps(dev); | |
c2bc2fc5 | 6207 | __gen6_update_ring_freq(dev); |
0a073b84 | 6208 | } |
aed242ff CW |
6209 | |
6210 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); | |
6211 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); | |
6212 | ||
6213 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); | |
6214 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); | |
6215 | ||
c0951f0c | 6216 | dev_priv->rps.enabled = true; |
3cc134e3 | 6217 | |
4c2a8897 | 6218 | gen6_enable_rps_interrupts(dev); |
3cc134e3 | 6219 | |
4fc688ce | 6220 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
6221 | |
6222 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
6223 | } |
6224 | ||
8090c6b9 DV |
6225 | void intel_enable_gt_powersave(struct drm_device *dev) |
6226 | { | |
1a01ab3b JB |
6227 | struct drm_i915_private *dev_priv = dev->dev_private; |
6228 | ||
f61018b1 YZ |
6229 | /* Powersaving is controlled by the host when inside a VM */ |
6230 | if (intel_vgpu_active(dev)) | |
6231 | return; | |
6232 | ||
8090c6b9 | 6233 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 6234 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 6235 | ironlake_enable_drps(dev); |
8090c6b9 | 6236 | intel_init_emon(dev); |
dc1d0136 | 6237 | mutex_unlock(&dev->struct_mutex); |
38807746 | 6238 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
6239 | /* |
6240 | * PCU communication is slow and this doesn't need to be | |
6241 | * done at any specific time, so do this out of our fast path | |
6242 | * to make resume and init faster. | |
c6df39b5 ID |
6243 | * |
6244 | * We depend on the HW RC6 power context save/restore | |
6245 | * mechanism when entering D3 through runtime PM suspend. So | |
6246 | * disable RPM until RPS/RC6 is properly setup. We can only | |
6247 | * get here via the driver load/system resume/runtime resume | |
6248 | * paths, so the _noresume version is enough (and in case of | |
6249 | * runtime resume it's necessary). | |
1a01ab3b | 6250 | */ |
c6df39b5 ID |
6251 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
6252 | round_jiffies_up_relative(HZ))) | |
6253 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
6254 | } |
6255 | } | |
6256 | ||
c6df39b5 ID |
6257 | void intel_reset_gt_powersave(struct drm_device *dev) |
6258 | { | |
6259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6260 | ||
dbea3cea ID |
6261 | if (INTEL_INFO(dev)->gen < 6) |
6262 | return; | |
6263 | ||
6264 | gen6_suspend_rps(dev); | |
c6df39b5 | 6265 | dev_priv->rps.enabled = false; |
c6df39b5 ID |
6266 | } |
6267 | ||
3107bd48 DV |
6268 | static void ibx_init_clock_gating(struct drm_device *dev) |
6269 | { | |
6270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6271 | ||
6272 | /* | |
6273 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6274 | * gating for the panel power sequencer or it will fail to | |
6275 | * start up when no ports are active. | |
6276 | */ | |
6277 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
6278 | } | |
6279 | ||
0e088b8f VS |
6280 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
6281 | { | |
6282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b12ce1d8 | 6283 | enum pipe pipe; |
0e088b8f | 6284 | |
055e393f | 6285 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
6286 | I915_WRITE(DSPCNTR(pipe), |
6287 | I915_READ(DSPCNTR(pipe)) | | |
6288 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
b12ce1d8 VS |
6289 | |
6290 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); | |
6291 | POSTING_READ(DSPSURF(pipe)); | |
0e088b8f VS |
6292 | } |
6293 | } | |
6294 | ||
017636cc VS |
6295 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
6296 | { | |
6297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6298 | ||
6299 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
6300 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
6301 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
6302 | ||
6303 | /* | |
6304 | * Don't touch WM1S_LP_EN here. | |
6305 | * Doing so could cause underruns. | |
6306 | */ | |
6307 | } | |
6308 | ||
1fa61106 | 6309 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6310 | { |
6311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 6312 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 6313 | |
f1e8fa56 DL |
6314 | /* |
6315 | * Required for FBC | |
6316 | * WaFbcDisableDpfcClockGating:ilk | |
6317 | */ | |
4d47e4f5 DL |
6318 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
6319 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
6320 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
6321 | |
6322 | I915_WRITE(PCH_3DCGDIS0, | |
6323 | MARIUNIT_CLOCK_GATE_DISABLE | | |
6324 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
6325 | I915_WRITE(PCH_3DCGDIS1, | |
6326 | VFMUNIT_CLOCK_GATE_DISABLE); | |
6327 | ||
6f1d69b0 ED |
6328 | /* |
6329 | * According to the spec the following bits should be set in | |
6330 | * order to enable memory self-refresh | |
6331 | * The bit 22/21 of 0x42004 | |
6332 | * The bit 5 of 0x42020 | |
6333 | * The bit 15 of 0x45000 | |
6334 | */ | |
6335 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6336 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6337 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 6338 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
6339 | I915_WRITE(DISP_ARB_CTL, |
6340 | (I915_READ(DISP_ARB_CTL) | | |
6341 | DISP_FBC_WM_DIS)); | |
017636cc VS |
6342 | |
6343 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
6344 | |
6345 | /* | |
6346 | * Based on the document from hardware guys the following bits | |
6347 | * should be set unconditionally in order to enable FBC. | |
6348 | * The bit 22 of 0x42000 | |
6349 | * The bit 22 of 0x42004 | |
6350 | * The bit 7,8,9 of 0x42020. | |
6351 | */ | |
6352 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 6353 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
6354 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
6355 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6356 | ILK_FBCQ_DIS); | |
6357 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6358 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6359 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
6360 | } |
6361 | ||
4d47e4f5 DL |
6362 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6363 | ||
6f1d69b0 ED |
6364 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6365 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6366 | ILK_ELPIN_409_SELECT); | |
6367 | I915_WRITE(_3D_CHICKEN2, | |
6368 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
6369 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 6370 | |
ecdb4eb7 | 6371 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
6372 | I915_WRITE(CACHE_MODE_0, |
6373 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 6374 | |
4e04632e AG |
6375 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
6376 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6377 | ||
0e088b8f | 6378 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 6379 | |
3107bd48 DV |
6380 | ibx_init_clock_gating(dev); |
6381 | } | |
6382 | ||
6383 | static void cpt_init_clock_gating(struct drm_device *dev) | |
6384 | { | |
6385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6386 | int pipe; | |
3f704fa2 | 6387 | uint32_t val; |
3107bd48 DV |
6388 | |
6389 | /* | |
6390 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6391 | * gating for the panel power sequencer or it will fail to | |
6392 | * start up when no ports are active. | |
6393 | */ | |
cd664078 JB |
6394 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
6395 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
6396 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
6397 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
6398 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
6399 | /* The below fixes the weird display corruption, a few pixels shifted |
6400 | * downward, on (only) LVDS of some HP laptops with IVY. | |
6401 | */ | |
055e393f | 6402 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
6403 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
6404 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
6405 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 6406 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 6407 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
6408 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
6409 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
6410 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
6411 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
6412 | } | |
3107bd48 | 6413 | /* WADP0ClockGatingDisable */ |
055e393f | 6414 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
6415 | I915_WRITE(TRANS_CHICKEN1(pipe), |
6416 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
6417 | } | |
6f1d69b0 ED |
6418 | } |
6419 | ||
1d7aaa0c DV |
6420 | static void gen6_check_mch_setup(struct drm_device *dev) |
6421 | { | |
6422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6423 | uint32_t tmp; | |
6424 | ||
6425 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
6426 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
6427 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
6428 | tmp); | |
1d7aaa0c DV |
6429 | } |
6430 | ||
1fa61106 | 6431 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6432 | { |
6433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 6434 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 6435 | |
231e54f6 | 6436 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
6437 | |
6438 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6439 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6440 | ILK_ELPIN_409_SELECT); | |
6441 | ||
ecdb4eb7 | 6442 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
6443 | I915_WRITE(_3D_CHICKEN, |
6444 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
6445 | ||
4e04632e AG |
6446 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
6447 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6448 | ||
8d85d272 VS |
6449 | /* |
6450 | * BSpec recoomends 8x4 when MSAA is used, | |
6451 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6452 | * |
6453 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6454 | * disable bit, which we don't touch here, but it's good | |
6455 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
6456 | */ |
6457 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 6458 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 6459 | |
017636cc | 6460 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6461 | |
6f1d69b0 | 6462 | I915_WRITE(CACHE_MODE_0, |
50743298 | 6463 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
6464 | |
6465 | I915_WRITE(GEN6_UCGCTL1, | |
6466 | I915_READ(GEN6_UCGCTL1) | | |
6467 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
6468 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
6469 | ||
6470 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
6471 | * gating disable must be set. Failure to set it results in | |
6472 | * flickering pixels due to Z write ordering failures after | |
6473 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
6474 | * Sanctuary and Tropics, and apparently anything else with | |
6475 | * alpha test or pixel discard. | |
6476 | * | |
6477 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
6478 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 6479 | * |
ef59318c VS |
6480 | * WaDisableRCCUnitClockGating:snb |
6481 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
6482 | */ |
6483 | I915_WRITE(GEN6_UCGCTL2, | |
6484 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
6485 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
6486 | ||
5eb146dd | 6487 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
6488 | I915_WRITE(_3D_CHICKEN3, |
6489 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 6490 | |
e927ecde VS |
6491 | /* |
6492 | * Bspec says: | |
6493 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
6494 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
6495 | */ | |
6496 | I915_WRITE(_3D_CHICKEN3, | |
6497 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
6498 | ||
6f1d69b0 ED |
6499 | /* |
6500 | * According to the spec the following bits should be | |
6501 | * set in order to enable memory self-refresh and fbc: | |
6502 | * The bit21 and bit22 of 0x42000 | |
6503 | * The bit21 and bit22 of 0x42004 | |
6504 | * The bit5 and bit7 of 0x42020 | |
6505 | * The bit14 of 0x70180 | |
6506 | * The bit14 of 0x71180 | |
4bb35334 DL |
6507 | * |
6508 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
6509 | */ |
6510 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6511 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6512 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
6513 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6514 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6515 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
6516 | I915_WRITE(ILK_DSPCLK_GATE_D, |
6517 | I915_READ(ILK_DSPCLK_GATE_D) | | |
6518 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
6519 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 6520 | |
0e088b8f | 6521 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 6522 | |
3107bd48 | 6523 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
6524 | |
6525 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6526 | } |
6527 | ||
6528 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
6529 | { | |
6530 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
6531 | ||
3aad9059 | 6532 | /* |
46680e0a | 6533 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
6534 | * |
6535 | * This actually overrides the dispatch | |
6536 | * mode for all thread types. | |
6537 | */ | |
6f1d69b0 ED |
6538 | reg &= ~GEN7_FF_SCHED_MASK; |
6539 | reg |= GEN7_FF_TS_SCHED_HW; | |
6540 | reg |= GEN7_FF_VS_SCHED_HW; | |
6541 | reg |= GEN7_FF_DS_SCHED_HW; | |
6542 | ||
6543 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
6544 | } | |
6545 | ||
17a303ec PZ |
6546 | static void lpt_init_clock_gating(struct drm_device *dev) |
6547 | { | |
6548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6549 | ||
6550 | /* | |
6551 | * TODO: this bit should only be enabled when really needed, then | |
6552 | * disabled when not needed anymore in order to save power. | |
6553 | */ | |
c2699524 | 6554 | if (HAS_PCH_LPT_LP(dev)) |
17a303ec PZ |
6555 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
6556 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
6557 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
6558 | |
6559 | /* WADPOClockGatingDisable:hsw */ | |
36c0d0cf VS |
6560 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
6561 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | | |
0a790cdb | 6562 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
17a303ec PZ |
6563 | } |
6564 | ||
7d708ee4 ID |
6565 | static void lpt_suspend_hw(struct drm_device *dev) |
6566 | { | |
6567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6568 | ||
c2699524 | 6569 | if (HAS_PCH_LPT_LP(dev)) { |
7d708ee4 ID |
6570 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6571 | ||
6572 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6573 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6574 | } | |
6575 | } | |
6576 | ||
47c2bd97 | 6577 | static void broadwell_init_clock_gating(struct drm_device *dev) |
1020a5c2 BW |
6578 | { |
6579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 6580 | enum pipe pipe; |
4d487cff | 6581 | uint32_t misccpctl; |
1020a5c2 | 6582 | |
7ad0dbab | 6583 | ilk_init_lp_watermarks(dev); |
50ed5fbd | 6584 | |
ab57fff1 | 6585 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 6586 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 6587 | |
ab57fff1 | 6588 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
6589 | I915_WRITE(CHICKEN_PAR1_1, |
6590 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
6591 | ||
ab57fff1 | 6592 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 6593 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 6594 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 6595 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 6596 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 6597 | } |
63801f21 | 6598 | |
ab57fff1 BW |
6599 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6600 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
6601 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6602 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6603 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 6604 | |
295e8bb7 VS |
6605 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6606 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
6607 | |
6608 | /* WaDisableSDEUnitClockGating:bdw */ | |
6609 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6610 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 6611 | |
4d487cff VS |
6612 | /* |
6613 | * WaProgramL3SqcReg1Default:bdw | |
6614 | * WaTempDisableDOPClkGating:bdw | |
6615 | */ | |
6616 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
6617 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
6618 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); | |
6619 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
6620 | ||
6d50b065 VS |
6621 | /* |
6622 | * WaGttCachingOffByDefault:bdw | |
6623 | * GTT cache may not work with big pages, so if those | |
6624 | * are ever enabled GTT cache may need to be disabled. | |
6625 | */ | |
6626 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
6627 | ||
89d6b2b8 | 6628 | lpt_init_clock_gating(dev); |
1020a5c2 BW |
6629 | } |
6630 | ||
cad2a2d7 ED |
6631 | static void haswell_init_clock_gating(struct drm_device *dev) |
6632 | { | |
6633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 6634 | |
017636cc | 6635 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 6636 | |
f3fc4884 FJ |
6637 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6638 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
6639 | I915_WRITE(HSW_ROW_CHICKEN3, | |
6640 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
6641 | ||
ecdb4eb7 | 6642 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
6643 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6644 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6645 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6646 | ||
e36ea7ff VS |
6647 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6648 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6649 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 6650 | |
4e04632e AG |
6651 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6652 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6653 | ||
fe27c606 CW |
6654 | /* enable HiZ Raw Stall Optimization */ |
6655 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6656 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6657 | ||
ecdb4eb7 | 6658 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
6659 | I915_WRITE(CACHE_MODE_1, |
6660 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 6661 | |
a12c4967 VS |
6662 | /* |
6663 | * BSpec recommends 8x4 when MSAA is used, | |
6664 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6665 | * |
6666 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6667 | * disable bit, which we don't touch here, but it's good | |
6668 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
6669 | */ |
6670 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6671 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 6672 | |
94411593 KG |
6673 | /* WaSampleCChickenBitEnable:hsw */ |
6674 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
6675 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
6676 | ||
ecdb4eb7 | 6677 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
6678 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6679 | ||
90a88643 PZ |
6680 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6681 | I915_WRITE(CHICKEN_PAR1_1, | |
6682 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 6683 | |
17a303ec | 6684 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
6685 | } |
6686 | ||
1fa61106 | 6687 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6688 | { |
6689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 6690 | uint32_t snpcr; |
6f1d69b0 | 6691 | |
017636cc | 6692 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6693 | |
231e54f6 | 6694 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6695 | |
ecdb4eb7 | 6696 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
6697 | I915_WRITE(_3D_CHICKEN3, |
6698 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6699 | ||
ecdb4eb7 | 6700 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
6701 | I915_WRITE(IVB_CHICKEN3, |
6702 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6703 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6704 | ||
ecdb4eb7 | 6705 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
6706 | if (IS_IVB_GT1(dev)) |
6707 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6708 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6709 | |
4e04632e AG |
6710 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6711 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6712 | ||
ecdb4eb7 | 6713 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
6714 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6715 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
6716 | ||
ecdb4eb7 | 6717 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
6718 | I915_WRITE(GEN7_L3CNTLREG1, |
6719 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
6720 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
6721 | GEN7_WA_L3_CHICKEN_MODE); |
6722 | if (IS_IVB_GT1(dev)) | |
6723 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6724 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
6725 | else { |
6726 | /* must write both registers */ | |
6727 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6728 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
6729 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6730 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 6731 | } |
6f1d69b0 | 6732 | |
ecdb4eb7 | 6733 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
6734 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6735 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6736 | ||
1b80a19a | 6737 | /* |
0f846f81 | 6738 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6739 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
6740 | */ |
6741 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 6742 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6743 | |
ecdb4eb7 | 6744 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
6745 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6746 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6747 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6748 | ||
0e088b8f | 6749 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6750 | |
6751 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 6752 | |
22721343 CW |
6753 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6754 | /* enable HiZ Raw Stall Optimization */ | |
6755 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6756 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6757 | } | |
116f2b6d | 6758 | |
ecdb4eb7 | 6759 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
6760 | I915_WRITE(CACHE_MODE_1, |
6761 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 6762 | |
a607c1a4 VS |
6763 | /* |
6764 | * BSpec recommends 8x4 when MSAA is used, | |
6765 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6766 | * |
6767 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6768 | * disable bit, which we don't touch here, but it's good | |
6769 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
6770 | */ |
6771 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6772 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 6773 | |
20848223 BW |
6774 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6775 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
6776 | snpcr |= GEN6_MBC_SNPCR_MED; | |
6777 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 6778 | |
ab5c608b BW |
6779 | if (!HAS_PCH_NOP(dev)) |
6780 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
6781 | |
6782 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6783 | } |
6784 | ||
c6beb13e VS |
6785 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
6786 | { | |
6787 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6788 | ||
6789 | /* | |
6790 | * Disable trickle feed and enable pnd deadline calculation | |
6791 | */ | |
6792 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
6793 | I915_WRITE(CBR1_VLV, 0); | |
6794 | } | |
6795 | ||
1fa61106 | 6796 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6797 | { |
6798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6f1d69b0 | 6799 | |
c6beb13e | 6800 | vlv_init_display_clock_gating(dev_priv); |
6f1d69b0 | 6801 | |
ecdb4eb7 | 6802 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
6803 | I915_WRITE(_3D_CHICKEN3, |
6804 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6805 | ||
ecdb4eb7 | 6806 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
6807 | I915_WRITE(IVB_CHICKEN3, |
6808 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6809 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6810 | ||
fad7d36e | 6811 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 6812 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 6813 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
6814 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6815 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6816 | |
4e04632e AG |
6817 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6818 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6819 | ||
ecdb4eb7 | 6820 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
6821 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6822 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6823 | ||
ecdb4eb7 | 6824 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
6825 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6826 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6827 | ||
ecdb4eb7 | 6828 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
6829 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6830 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6831 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6832 | ||
46680e0a VS |
6833 | gen7_setup_fixed_func_scheduler(dev_priv); |
6834 | ||
3c0edaeb | 6835 | /* |
0f846f81 | 6836 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6837 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
6838 | */ |
6839 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 6840 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6841 | |
c98f5062 AG |
6842 | /* WaDisableL3Bank2xClockGate:vlv |
6843 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
6844 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6845 | I915_WRITE(GEN7_UCGCTL4, | |
6846 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 6847 | |
afd58e79 VS |
6848 | /* |
6849 | * BSpec says this must be set, even though | |
6850 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6851 | */ | |
6b26c86d DV |
6852 | I915_WRITE(CACHE_MODE_1, |
6853 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 6854 | |
da2518f9 VS |
6855 | /* |
6856 | * BSpec recommends 8x4 when MSAA is used, | |
6857 | * however in practice 16x4 seems fastest. | |
6858 | * | |
6859 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6860 | * disable bit, which we don't touch here, but it's good | |
6861 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6862 | */ | |
6863 | I915_WRITE(GEN7_GT_MODE, | |
6864 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6865 | ||
031994ee VS |
6866 | /* |
6867 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6868 | * This is the hardware default actually. | |
6869 | */ | |
6870 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6871 | ||
2d809570 | 6872 | /* |
ecdb4eb7 | 6873 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
6874 | * Disable clock gating on th GCFG unit to prevent a delay |
6875 | * in the reporting of vblank events. | |
6876 | */ | |
7a0d1eed | 6877 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
6878 | } |
6879 | ||
a4565da8 VS |
6880 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6881 | { | |
6882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6883 | ||
c6beb13e | 6884 | vlv_init_display_clock_gating(dev_priv); |
dd811e70 | 6885 | |
232ce337 VS |
6886 | /* WaVSRefCountFullforceMissDisable:chv */ |
6887 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6888 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6889 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6890 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
6891 | |
6892 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6893 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6894 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
6895 | |
6896 | /* WaDisableCSUnitClockGating:chv */ | |
6897 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6898 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
6899 | |
6900 | /* WaDisableSDEUnitClockGating:chv */ | |
6901 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6902 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6d50b065 VS |
6903 | |
6904 | /* | |
6905 | * GTT cache may not work with big pages, so if those | |
6906 | * are ever enabled GTT cache may need to be disabled. | |
6907 | */ | |
6908 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
a4565da8 VS |
6909 | } |
6910 | ||
1fa61106 | 6911 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6912 | { |
6913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6914 | uint32_t dspclk_gate; | |
6915 | ||
6916 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6917 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6918 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6919 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6920 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6921 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6922 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6923 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6924 | if (IS_GM45(dev)) | |
6925 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6926 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
6927 | |
6928 | /* WaDisableRenderCachePipelinedFlush */ | |
6929 | I915_WRITE(CACHE_MODE_0, | |
6930 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 6931 | |
4e04632e AG |
6932 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6933 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6934 | ||
0e088b8f | 6935 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6936 | } |
6937 | ||
1fa61106 | 6938 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6939 | { |
6940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6941 | ||
6942 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6943 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6944 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6945 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6946 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
6947 | I915_WRITE(MI_ARB_STATE, |
6948 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6949 | |
6950 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6951 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6952 | } |
6953 | ||
1fa61106 | 6954 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6955 | { |
6956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6957 | ||
6958 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6959 | I965_RCC_CLOCK_GATE_DISABLE | | |
6960 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6961 | I965_ISC_CLOCK_GATE_DISABLE | | |
6962 | I965_FBC_CLOCK_GATE_DISABLE); | |
6963 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
6964 | I915_WRITE(MI_ARB_STATE, |
6965 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6966 | |
6967 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6968 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6969 | } |
6970 | ||
1fa61106 | 6971 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6972 | { |
6973 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6974 | u32 dstate = I915_READ(D_STATE); | |
6975 | ||
6976 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6977 | DSTATE_DOT_CLOCK_GATING; | |
6978 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
6979 | |
6980 | if (IS_PINEVIEW(dev)) | |
6981 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
6982 | |
6983 | /* IIR "flip pending" means done if this bit is set */ | |
6984 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
6985 | |
6986 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 6987 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
6988 | |
6989 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6990 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
6991 | |
6992 | I915_WRITE(MI_ARB_STATE, | |
6993 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6994 | } |
6995 | ||
1fa61106 | 6996 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6997 | { |
6998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6999 | ||
7000 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
7001 | |
7002 | /* interrupts should cause a wake up from C3 */ | |
7003 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
7004 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
7005 | |
7006 | I915_WRITE(MEM_MODE, | |
7007 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7008 | } |
7009 | ||
1fa61106 | 7010 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
7011 | { |
7012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7013 | ||
7014 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
1038392b VS |
7015 | |
7016 | I915_WRITE(MEM_MODE, | |
7017 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
7018 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7019 | } |
7020 | ||
6f1d69b0 ED |
7021 | void intel_init_clock_gating(struct drm_device *dev) |
7022 | { | |
7023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7024 | ||
c57e3551 DL |
7025 | if (dev_priv->display.init_clock_gating) |
7026 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
7027 | } |
7028 | ||
7d708ee4 ID |
7029 | void intel_suspend_hw(struct drm_device *dev) |
7030 | { | |
7031 | if (HAS_PCH_LPT(dev)) | |
7032 | lpt_suspend_hw(dev); | |
7033 | } | |
7034 | ||
1fa61106 ED |
7035 | /* Set up chip specific power management-related functions */ |
7036 | void intel_init_pm(struct drm_device *dev) | |
7037 | { | |
7038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7039 | ||
7ff0ebcc | 7040 | intel_fbc_init(dev_priv); |
1fa61106 | 7041 | |
c921aba8 DV |
7042 | /* For cxsr */ |
7043 | if (IS_PINEVIEW(dev)) | |
7044 | i915_pineview_get_mem_freq(dev); | |
7045 | else if (IS_GEN5(dev)) | |
7046 | i915_ironlake_get_mem_freq(dev); | |
7047 | ||
1fa61106 | 7048 | /* For FIFO watermark updates */ |
f5ed50cb | 7049 | if (INTEL_INFO(dev)->gen >= 9) { |
2af30a5c PB |
7050 | skl_setup_wm_latency(dev); |
7051 | ||
a82abe43 ID |
7052 | if (IS_BROXTON(dev)) |
7053 | dev_priv->display.init_clock_gating = | |
7054 | bxt_init_clock_gating; | |
2d41c0b5 | 7055 | dev_priv->display.update_wm = skl_update_wm; |
2791a16c | 7056 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; |
c83155a6 | 7057 | } else if (HAS_PCH_SPLIT(dev)) { |
fa50ad61 | 7058 | ilk_setup_wm_latency(dev); |
53615a5e | 7059 | |
bd602544 VS |
7060 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
7061 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
7062 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
7063 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
7064 | dev_priv->display.update_wm = ilk_update_wm; | |
2791a16c | 7065 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; |
bd602544 VS |
7066 | } else { |
7067 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
7068 | "Disable CxSR\n"); | |
7069 | } | |
7070 | ||
7071 | if (IS_GEN5(dev)) | |
1fa61106 | 7072 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 7073 | else if (IS_GEN6(dev)) |
1fa61106 | 7074 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 7075 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 7076 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 7077 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 7078 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 7079 | else if (INTEL_INFO(dev)->gen == 8) |
47c2bd97 | 7080 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
a4565da8 | 7081 | } else if (IS_CHERRYVIEW(dev)) { |
262cd2e1 VS |
7082 | vlv_setup_wm_latency(dev); |
7083 | ||
7084 | dev_priv->display.update_wm = vlv_update_wm; | |
a4565da8 VS |
7085 | dev_priv->display.init_clock_gating = |
7086 | cherryview_init_clock_gating; | |
1fa61106 | 7087 | } else if (IS_VALLEYVIEW(dev)) { |
26e1fe4f VS |
7088 | vlv_setup_wm_latency(dev); |
7089 | ||
7090 | dev_priv->display.update_wm = vlv_update_wm; | |
1fa61106 ED |
7091 | dev_priv->display.init_clock_gating = |
7092 | valleyview_init_clock_gating; | |
1fa61106 ED |
7093 | } else if (IS_PINEVIEW(dev)) { |
7094 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
7095 | dev_priv->is_ddr3, | |
7096 | dev_priv->fsb_freq, | |
7097 | dev_priv->mem_freq)) { | |
7098 | DRM_INFO("failed to find known CxSR latency " | |
7099 | "(found ddr%s fsb freq %d, mem freq %d), " | |
7100 | "disabling CxSR\n", | |
7101 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
7102 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
7103 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 7104 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
7105 | dev_priv->display.update_wm = NULL; |
7106 | } else | |
7107 | dev_priv->display.update_wm = pineview_update_wm; | |
7108 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
7109 | } else if (IS_G4X(dev)) { | |
7110 | dev_priv->display.update_wm = g4x_update_wm; | |
7111 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
7112 | } else if (IS_GEN4(dev)) { | |
7113 | dev_priv->display.update_wm = i965_update_wm; | |
7114 | if (IS_CRESTLINE(dev)) | |
7115 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
7116 | else if (IS_BROADWATER(dev)) | |
7117 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
7118 | } else if (IS_GEN3(dev)) { | |
7119 | dev_priv->display.update_wm = i9xx_update_wm; | |
7120 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
7121 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
7122 | } else if (IS_GEN2(dev)) { |
7123 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
7124 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 7125 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
7126 | } else { |
7127 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 7128 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
7129 | } |
7130 | ||
7131 | if (IS_I85X(dev) || IS_I865G(dev)) | |
7132 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
7133 | else | |
7134 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
7135 | } else { | |
7136 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
7137 | } |
7138 | } | |
7139 | ||
151a49d0 | 7140 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 7141 | { |
4fc688ce | 7142 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
7143 | |
7144 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
7145 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
7146 | return -EAGAIN; | |
7147 | } | |
7148 | ||
7149 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
dddab346 | 7150 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
42c0526c BW |
7151 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
7152 | ||
7153 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7154 | 500)) { | |
7155 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
7156 | return -ETIMEDOUT; | |
7157 | } | |
7158 | ||
7159 | *val = I915_READ(GEN6_PCODE_DATA); | |
7160 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7161 | ||
7162 | return 0; | |
7163 | } | |
7164 | ||
151a49d0 | 7165 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
42c0526c | 7166 | { |
4fc688ce | 7167 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
7168 | |
7169 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
7170 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
7171 | return -EAGAIN; | |
7172 | } | |
7173 | ||
7174 | I915_WRITE(GEN6_PCODE_DATA, val); | |
7175 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
7176 | ||
7177 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7178 | 500)) { | |
7179 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
7180 | return -ETIMEDOUT; | |
7181 | } | |
7182 | ||
7183 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7184 | ||
7185 | return 0; | |
7186 | } | |
a0e4e199 | 7187 | |
dd06f88c | 7188 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
855ba3be | 7189 | { |
dd06f88c VS |
7190 | switch (czclk_freq) { |
7191 | case 200: | |
7192 | return 10; | |
7193 | case 267: | |
7194 | return 12; | |
7195 | case 320: | |
7196 | case 333: | |
dd06f88c | 7197 | return 16; |
ab3fb157 VS |
7198 | case 400: |
7199 | return 20; | |
855ba3be JB |
7200 | default: |
7201 | return -1; | |
7202 | } | |
dd06f88c | 7203 | } |
855ba3be | 7204 | |
dd06f88c VS |
7205 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7206 | { | |
bfa7df01 | 7207 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
dd06f88c VS |
7208 | |
7209 | div = vlv_gpu_freq_div(czclk_freq); | |
7210 | if (div < 0) | |
7211 | return div; | |
7212 | ||
7213 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); | |
855ba3be JB |
7214 | } |
7215 | ||
b55dd647 | 7216 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 7217 | { |
bfa7df01 | 7218 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
855ba3be | 7219 | |
dd06f88c VS |
7220 | mul = vlv_gpu_freq_div(czclk_freq); |
7221 | if (mul < 0) | |
7222 | return mul; | |
855ba3be | 7223 | |
dd06f88c | 7224 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
855ba3be JB |
7225 | } |
7226 | ||
b55dd647 | 7227 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 7228 | { |
bfa7df01 | 7229 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
22b1b2f8 | 7230 | |
dd06f88c VS |
7231 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
7232 | if (div < 0) | |
7233 | return div; | |
22b1b2f8 | 7234 | |
dd06f88c | 7235 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
22b1b2f8 D |
7236 | } |
7237 | ||
b55dd647 | 7238 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 7239 | { |
bfa7df01 | 7240 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
22b1b2f8 | 7241 | |
dd06f88c VS |
7242 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
7243 | if (mul < 0) | |
7244 | return mul; | |
22b1b2f8 | 7245 | |
1c14762d | 7246 | /* CHV needs even values */ |
dd06f88c | 7247 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
22b1b2f8 D |
7248 | } |
7249 | ||
616bc820 | 7250 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 7251 | { |
80b6dda4 AG |
7252 | if (IS_GEN9(dev_priv->dev)) |
7253 | return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER; | |
7254 | else if (IS_CHERRYVIEW(dev_priv->dev)) | |
616bc820 | 7255 | return chv_gpu_freq(dev_priv, val); |
22b1b2f8 | 7256 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
7257 | return byt_gpu_freq(dev_priv, val); |
7258 | else | |
7259 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
7260 | } |
7261 | ||
616bc820 VS |
7262 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7263 | { | |
80b6dda4 AG |
7264 | if (IS_GEN9(dev_priv->dev)) |
7265 | return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER; | |
7266 | else if (IS_CHERRYVIEW(dev_priv->dev)) | |
616bc820 | 7267 | return chv_freq_opcode(dev_priv, val); |
22b1b2f8 | 7268 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
7269 | return byt_freq_opcode(dev_priv, val); |
7270 | else | |
7271 | return val / GT_FREQUENCY_MULTIPLIER; | |
7272 | } | |
22b1b2f8 | 7273 | |
6ad790c0 CW |
7274 | struct request_boost { |
7275 | struct work_struct work; | |
eed29a5b | 7276 | struct drm_i915_gem_request *req; |
6ad790c0 CW |
7277 | }; |
7278 | ||
7279 | static void __intel_rps_boost_work(struct work_struct *work) | |
7280 | { | |
7281 | struct request_boost *boost = container_of(work, struct request_boost, work); | |
e61b9958 | 7282 | struct drm_i915_gem_request *req = boost->req; |
6ad790c0 | 7283 | |
e61b9958 CW |
7284 | if (!i915_gem_request_completed(req, true)) |
7285 | gen6_rps_boost(to_i915(req->ring->dev), NULL, | |
7286 | req->emitted_jiffies); | |
6ad790c0 | 7287 | |
e61b9958 | 7288 | i915_gem_request_unreference__unlocked(req); |
6ad790c0 CW |
7289 | kfree(boost); |
7290 | } | |
7291 | ||
7292 | void intel_queue_rps_boost_for_request(struct drm_device *dev, | |
eed29a5b | 7293 | struct drm_i915_gem_request *req) |
6ad790c0 CW |
7294 | { |
7295 | struct request_boost *boost; | |
7296 | ||
eed29a5b | 7297 | if (req == NULL || INTEL_INFO(dev)->gen < 6) |
6ad790c0 CW |
7298 | return; |
7299 | ||
e61b9958 CW |
7300 | if (i915_gem_request_completed(req, true)) |
7301 | return; | |
7302 | ||
6ad790c0 CW |
7303 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
7304 | if (boost == NULL) | |
7305 | return; | |
7306 | ||
eed29a5b DV |
7307 | i915_gem_request_reference(req); |
7308 | boost->req = req; | |
6ad790c0 CW |
7309 | |
7310 | INIT_WORK(&boost->work, __intel_rps_boost_work); | |
7311 | queue_work(to_i915(dev)->wq, &boost->work); | |
7312 | } | |
7313 | ||
f742a552 | 7314 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
7315 | { |
7316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7317 | ||
f742a552 | 7318 | mutex_init(&dev_priv->rps.hw_lock); |
8d3afd7d | 7319 | spin_lock_init(&dev_priv->rps.client_lock); |
f742a552 | 7320 | |
907b28c5 CW |
7321 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
7322 | intel_gen6_powersave_work); | |
1854d5ca | 7323 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
2e1b8730 CW |
7324 | INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); |
7325 | INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); | |
5d584b2e | 7326 | |
33688d95 | 7327 | dev_priv->pm.suspended = false; |
907b28c5 | 7328 | } |