]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: restore backlight precision when converting from ACPI
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
7f2cf220 100 int i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
159f9875
VS		 117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
85208be0
ED		 126
127 /* enable it... */
993495ae
VS		 128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
5cd5410e 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 139}
140
1fa61106 141static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146}
147
993495ae 148static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 149{
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 152 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 156 u32 dpfc_ctl;
157
3fa2e0ee
VS		 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 164
85208be0
ED		 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
fe74c1a5 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 169
84f44ce7 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 171}
172
1fa61106 173static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186}
187
1fa61106 188static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193}
194
195static void sandybridge_blit_fbc_update(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
940aece4
D		 201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 205
85208be0
ED		 206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 216
940aece4 217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 218}
219
993495ae 220static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 221{
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 224 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 228 u32 dpfc_ctl;
229
46f3dab9 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee
VS		 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0 238
85208be0 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
84f44ce7 251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 252}
253
1fa61106 254static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267}
268
1fa61106 269static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274}
275
993495ae 276static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 277{
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 280 struct drm_framebuffer *fb = crtc->primary->fb;
abe959c7
RV		 281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 284 u32 dpfc_ctl;
abe959c7 285
3fa2e0ee
VS		 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 294
891348b2 295 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
299 ILK_FBCQ_DIS);
28554164 300 } else {
2adb6db8 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
304 HSW_FBCQ_DIS);
891348b2 305 }
b74ea102 306
abe959c7
RV		 307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
310
311 sandybridge_blit_fbc_update(dev);
312
b19870ee 313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 314}
315
85208be0
ED		 316bool intel_fbc_enabled(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (!dev_priv->display.fbc_enabled)
321 return false;
322
323 return dev_priv->display.fbc_enabled(dev);
324}
325
326static void intel_fbc_work_fn(struct work_struct *__work)
327{
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333
334 mutex_lock(&dev->struct_mutex);
5c3fe8b0 335 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 336 /* Double check that we haven't switched fb without cancelling
337 * the prior work.
338 */
f4510a27 339 if (work->crtc->primary->fb == work->fb) {
993495ae 340 dev_priv->display.enable_fbc(work->crtc);
85208be0 341
5c3fe8b0 342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 344 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 345 }
346
5c3fe8b0 347 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 348 }
349 mutex_unlock(&dev->struct_mutex);
350
351 kfree(work);
352}
353
354static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
355{
5c3fe8b0 356 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 357 return;
358
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
360
361 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 363 * entirely asynchronously.
364 */
5c3fe8b0 365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 366 /* tasklet was killed before being run, clean up */
5c3fe8b0 367 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 368
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
372 * necessary to run.
373 */
5c3fe8b0 374 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 375}
376
993495ae 377static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 378{
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382
383 if (!dev_priv->display.enable_fbc)
384 return;
385
386 intel_cancel_fbc_work(dev_priv);
387
b14c5679 388 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 389 if (work == NULL) {
6cdcb5e7 390 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 391 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 392 return;
393 }
394
395 work->crtc = crtc;
f4510a27 396 work->fb = crtc->primary->fb;
85208be0
ED		 397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
398
5c3fe8b0 399 dev_priv->fbc.fbc_work = work;
85208be0 400
85208be0
ED		 401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
406 *
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
7457d617
DL		 411 *
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 413 */
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
415}
416
417void intel_disable_fbc(struct drm_device *dev)
418{
419 struct drm_i915_private *dev_priv = dev->dev_private;
420
421 intel_cancel_fbc_work(dev_priv);
422
423 if (!dev_priv->display.disable_fbc)
424 return;
425
426 dev_priv->display.disable_fbc(dev);
5c3fe8b0 427 dev_priv->fbc.plane = -1;
85208be0
ED		 428}
429
29ebf90f
CW		 430static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
432{
433 if (dev_priv->fbc.no_fbc_reason == reason)
434 return false;
435
436 dev_priv->fbc.no_fbc_reason = reason;
437 return true;
438}
439
85208be0
ED		 440/**
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
443 *
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
449 * - no dual wide
f85da868 450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 451 *
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
455 * stolen memory.
456 *
457 * We need to enable/disable FBC on a global basis.
458 */
459void intel_update_fbc(struct drm_device *dev)
460{
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
ef644fda 467 const struct drm_display_mode *adjusted_mode;
37327abd 468 unsigned int max_width, max_height;
85208be0 469
3a77c4c4 470 if (!HAS_FBC(dev)) {
29ebf90f 471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 472 return;
29ebf90f 473 }
85208be0 474
d330a953 475 if (!i915.powersave) {
29ebf90f
CW		 476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 478 return;
29ebf90f 479 }
85208be0
ED		 480
481 /*
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
489 */
490 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 491 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 492 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 493 if (crtc) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 496 goto out_disable;
497 }
498 crtc = tmp_crtc;
499 }
500 }
501
f4510a27 502 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 505 goto out_disable;
506 }
507
508 intel_crtc = to_intel_crtc(crtc);
f4510a27 509 fb = crtc->primary->fb;
85208be0
ED		 510 intel_fb = to_intel_framebuffer(fb);
511 obj = intel_fb->obj;
ef644fda 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 513
d330a953 514 if (i915.enable_fbc < 0 &&
8a5729a3 515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 518 goto out_disable;
85208be0 519 }
d330a953 520 if (!i915.enable_fbc) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 523 goto out_disable;
524 }
ef644fda
VS		 525 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
526 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 527 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
529 "disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
f85da868
PZ		 532
533 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 534 max_width = 4096;
535 max_height = 2048;
f85da868 536 } else {
37327abd
VS		 537 max_width = 2048;
538 max_height = 1536;
f85da868 539 }
37327abd
VS		 540 if (intel_crtc->config.pipe_src_w > max_width ||
541 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 544 goto out_disable;
545 }
8f94d24b 546 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 547 intel_crtc->plane != PLANE_A) {
29ebf90f 548 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 550 goto out_disable;
551 }
552
553 /* The use of a CPU fence is mandatory in order to detect writes
554 * by the CPU to the scanout and trigger updates to the FBC.
555 */
556 if (obj->tiling_mode != I915_TILING_X ||
557 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 558 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
559 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 560 goto out_disable;
561 }
562
563 /* If the kernel debugger is active, always disable compression */
564 if (in_dbg_master())
565 goto out_disable;
566
11be49eb 567 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 568 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
569 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 570 goto out_disable;
571 }
572
85208be0
ED		 573 /* If the scanout has not changed, don't modify the FBC settings.
574 * Note that we make the fundamental assumption that the fb->obj
575 * cannot be unpinned (and have its GTT offset and fence revoked)
576 * without first being decoupled from the scanout and FBC disabled.
577 */
5c3fe8b0
BW		 578 if (dev_priv->fbc.plane == intel_crtc->plane &&
579 dev_priv->fbc.fb_id == fb->base.id &&
580 dev_priv->fbc.y == crtc->y)
85208be0
ED		 581 return;
582
583 if (intel_fbc_enabled(dev)) {
584 /* We update FBC along two paths, after changing fb/crtc
585 * configuration (modeswitching) and after page-flipping
586 * finishes. For the latter, we know that not only did
587 * we disable the FBC at the start of the page-flip
588 * sequence, but also more than one vblank has passed.
589 *
590 * For the former case of modeswitching, it is possible
591 * to switch between two FBC valid configurations
592 * instantaneously so we do need to disable the FBC
593 * before we can modify its control registers. We also
594 * have to wait for the next vblank for that to take
595 * effect. However, since we delay enabling FBC we can
596 * assume that a vblank has passed since disabling and
597 * that we can safely alter the registers in the deferred
598 * callback.
599 *
600 * In the scenario that we go from a valid to invalid
601 * and then back to valid FBC configuration we have
602 * no strict enforcement that a vblank occurred since
603 * disabling the FBC. However, along all current pipe
604 * disabling paths we do need to wait for a vblank at
605 * some point. And we wait before enabling FBC anyway.
606 */
607 DRM_DEBUG_KMS("disabling active FBC for update\n");
608 intel_disable_fbc(dev);
609 }
610
993495ae 611 intel_enable_fbc(crtc);
29ebf90f 612 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 613 return;
614
615out_disable:
616 /* Multiple disables should be harmless */
617 if (intel_fbc_enabled(dev)) {
618 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
619 intel_disable_fbc(dev);
620 }
11be49eb 621 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 622}
623
c921aba8
DV		 624static void i915_pineview_get_mem_freq(struct drm_device *dev)
625{
50227e1c 626 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 627 u32 tmp;
628
629 tmp = I915_READ(CLKCFG);
630
631 switch (tmp & CLKCFG_FSB_MASK) {
632 case CLKCFG_FSB_533:
633 dev_priv->fsb_freq = 533; /* 133*4 */
634 break;
635 case CLKCFG_FSB_800:
636 dev_priv->fsb_freq = 800; /* 200*4 */
637 break;
638 case CLKCFG_FSB_667:
639 dev_priv->fsb_freq = 667; /* 167*4 */
640 break;
641 case CLKCFG_FSB_400:
642 dev_priv->fsb_freq = 400; /* 100*4 */
643 break;
644 }
645
646 switch (tmp & CLKCFG_MEM_MASK) {
647 case CLKCFG_MEM_533:
648 dev_priv->mem_freq = 533;
649 break;
650 case CLKCFG_MEM_667:
651 dev_priv->mem_freq = 667;
652 break;
653 case CLKCFG_MEM_800:
654 dev_priv->mem_freq = 800;
655 break;
656 }
657
658 /* detect pineview DDR3 setting */
659 tmp = I915_READ(CSHRDDR3CTL);
660 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
661}
662
663static void i915_ironlake_get_mem_freq(struct drm_device *dev)
664{
50227e1c 665 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 666 u16 ddrpll, csipll;
667
668 ddrpll = I915_READ16(DDRMPLL1);
669 csipll = I915_READ16(CSIPLL0);
670
671 switch (ddrpll & 0xff) {
672 case 0xc:
673 dev_priv->mem_freq = 800;
674 break;
675 case 0x10:
676 dev_priv->mem_freq = 1066;
677 break;
678 case 0x14:
679 dev_priv->mem_freq = 1333;
680 break;
681 case 0x18:
682 dev_priv->mem_freq = 1600;
683 break;
684 default:
685 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
686 ddrpll & 0xff);
687 dev_priv->mem_freq = 0;
688 break;
689 }
690
20e4d407 691 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 692
693 switch (csipll & 0x3ff) {
694 case 0x00c:
695 dev_priv->fsb_freq = 3200;
696 break;
697 case 0x00e:
698 dev_priv->fsb_freq = 3733;
699 break;
700 case 0x010:
701 dev_priv->fsb_freq = 4266;
702 break;
703 case 0x012:
704 dev_priv->fsb_freq = 4800;
705 break;
706 case 0x014:
707 dev_priv->fsb_freq = 5333;
708 break;
709 case 0x016:
710 dev_priv->fsb_freq = 5866;
711 break;
712 case 0x018:
713 dev_priv->fsb_freq = 6400;
714 break;
715 default:
716 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
717 csipll & 0x3ff);
718 dev_priv->fsb_freq = 0;
719 break;
720 }
721
722 if (dev_priv->fsb_freq == 3200) {
20e4d407 723 dev_priv->ips.c_m = 0;
c921aba8 724 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 725 dev_priv->ips.c_m = 1;
c921aba8 726 } else {
20e4d407 727 dev_priv->ips.c_m = 2;
c921aba8
DV		 728 }
729}
730
b445e3b0
ED		 731static const struct cxsr_latency cxsr_latency_table[] = {
732 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
733 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
734 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
735 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
736 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
737
738 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
739 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
740 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
741 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
742 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
743
744 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
745 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
746 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
747 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
748 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
749
750 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
751 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
752 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
753 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
754 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
755
756 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
757 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
758 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
759 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
760 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
761
762 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
763 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
764 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
765 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
766 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
767};
768
63c62275 769static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 770 int is_ddr3,
771 int fsb,
772 int mem)
773{
774 const struct cxsr_latency *latency;
775 int i;
776
777 if (fsb == 0 || mem == 0)
778 return NULL;
779
780 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
781 latency = &cxsr_latency_table[i];
782 if (is_desktop == latency->is_desktop &&
783 is_ddr3 == latency->is_ddr3 &&
784 fsb == latency->fsb_freq && mem == latency->mem_freq)
785 return latency;
786 }
787
788 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
789
790 return NULL;
791}
792
1fa61106 793static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
796
797 /* deactivate cxsr */
798 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
799}
800
801/*
802 * Latency for FIFO fetches is dependent on several factors:
803 * - memory configuration (speed, channels)
804 * - chipset
805 * - current MCH state
806 * It can be fairly high in some situations, so here we assume a fairly
807 * pessimal value. It's a tradeoff between extra memory fetches (if we
808 * set this value too high, the FIFO will fetch frequently to stay full)
809 * and power consumption (set it too low to save power and we might see
810 * FIFO underruns and display "flicker").
811 *
812 * A value of 5us seems to be a good balance; safe for very low end
813 * platforms but not overly aggressive on lower latency configs.
814 */
815static const int latency_ns = 5000;
816
1fa61106 817static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 818{
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 uint32_t dsparb = I915_READ(DSPARB);
821 int size;
822
823 size = dsparb & 0x7f;
824 if (plane)
825 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
826
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
828 plane ? "B" : "A", size);
829
830 return size;
831}
832
feb56b93 833static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 834{
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 uint32_t dsparb = I915_READ(DSPARB);
837 int size;
838
839 size = dsparb & 0x1ff;
840 if (plane)
841 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
842 size >>= 1; /* Convert to cachelines */
843
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
846
847 return size;
848}
849
1fa61106 850static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 uint32_t dsparb = I915_READ(DSPARB);
854 int size;
855
856 size = dsparb & 0x7f;
857 size >>= 2; /* Convert to cachelines */
858
859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
860 plane ? "B" : "A",
861 size);
862
863 return size;
864}
865
b445e3b0
ED		 866/* Pineview has different values for various configs */
867static const struct intel_watermark_params pineview_display_wm = {
868 PINEVIEW_DISPLAY_FIFO,
869 PINEVIEW_MAX_WM,
870 PINEVIEW_DFT_WM,
871 PINEVIEW_GUARD_WM,
872 PINEVIEW_FIFO_LINE_SIZE
873};
874static const struct intel_watermark_params pineview_display_hplloff_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_HPLLOFF_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_cursor_wm = {
882 PINEVIEW_CURSOR_FIFO,
883 PINEVIEW_CURSOR_MAX_WM,
884 PINEVIEW_CURSOR_DFT_WM,
885 PINEVIEW_CURSOR_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE,
887};
888static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params g4x_wm_info = {
896 G4X_FIFO_SIZE,
897 G4X_MAX_WM,
898 G4X_MAX_WM,
899 2,
900 G4X_FIFO_LINE_SIZE,
901};
902static const struct intel_watermark_params g4x_cursor_wm_info = {
903 I965_CURSOR_FIFO,
904 I965_CURSOR_MAX_WM,
905 I965_CURSOR_DFT_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params valleyview_wm_info = {
910 VALLEYVIEW_FIFO_SIZE,
911 VALLEYVIEW_MAX_WM,
912 VALLEYVIEW_MAX_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_cursor_wm_info = {
917 I965_CURSOR_FIFO,
918 VALLEYVIEW_CURSOR_MAX_WM,
919 I965_CURSOR_DFT_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params i965_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 I965_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 I915_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i945_wm_info = {
931 I945_FIFO_SIZE,
932 I915_MAX_WM,
933 1,
934 2,
935 I915_FIFO_LINE_SIZE
936};
937static const struct intel_watermark_params i915_wm_info = {
938 I915_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
feb56b93 944static const struct intel_watermark_params i830_wm_info = {
b445e3b0
ED		 945 I855GM_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I830_FIFO_LINE_SIZE
950};
feb56b93 951static const struct intel_watermark_params i845_wm_info = {
b445e3b0
ED		 952 I830_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958
b445e3b0
ED		 959/**
960 * intel_calculate_wm - calculate watermark level
961 * @clock_in_khz: pixel clock
962 * @wm: chip FIFO params
963 * @pixel_size: display pixel size
964 * @latency_ns: memory latency for the platform
965 *
966 * Calculate the watermark level (the level at which the display plane will
967 * start fetching from memory again). Each chip has a different display
968 * FIFO size and allocation, so the caller needs to figure that out and pass
969 * in the correct intel_watermark_params structure.
970 *
971 * As the pixel clock runs, the FIFO will be drained at a rate that depends
972 * on the pixel size. When it reaches the watermark level, it'll start
973 * fetching FIFO line sized based chunks from memory until the FIFO fills
974 * past the watermark point. If the FIFO drains completely, a FIFO underrun
975 * will occur, and a display engine hang could result.
976 */
977static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
978 const struct intel_watermark_params *wm,
979 int fifo_size,
980 int pixel_size,
981 unsigned long latency_ns)
982{
983 long entries_required, wm_size;
984
985 /*
986 * Note: we need to make sure we don't overflow for various clock &
987 * latency values.
988 * clocks go from a few thousand to several hundred thousand.
989 * latency is usually a few thousand
990 */
991 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
992 1000;
993 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
994
995 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
996
997 wm_size = fifo_size - (entries_required + wm->guard_size);
998
999 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001 /* Don't promote wm_size to unsigned... */
1002 if (wm_size > (long)wm->max_wm)
1003 wm_size = wm->max_wm;
1004 if (wm_size <= 0)
1005 wm_size = wm->default_wm;
1006 return wm_size;
1007}
1008
1009static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010{
1011 struct drm_crtc *crtc, *enabled = NULL;
1012
1013 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1014 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1015 if (enabled)
1016 return NULL;
1017 enabled = crtc;
1018 }
1019 }
1020
1021 return enabled;
1022}
1023
46ba614c 1024static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1025{
46ba614c 1026 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_crtc *crtc;
1029 const struct cxsr_latency *latency;
1030 u32 reg;
1031 unsigned long wm;
1032
1033 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034 dev_priv->fsb_freq, dev_priv->mem_freq);
1035 if (!latency) {
1036 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037 pineview_disable_cxsr(dev);
1038 return;
1039 }
1040
1041 crtc = single_enabled_crtc(dev);
1042 if (crtc) {
241bfc38 1043 const struct drm_display_mode *adjusted_mode;
f4510a27 1044 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1045 int clock;
1046
1047 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1049
1050 /* Display SR */
1051 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052 pineview_display_wm.fifo_size,
1053 pixel_size, latency->display_sr);
1054 reg = I915_READ(DSPFW1);
1055 reg &= ~DSPFW_SR_MASK;
1056 reg |= wm << DSPFW_SR_SHIFT;
1057 I915_WRITE(DSPFW1, reg);
1058 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060 /* cursor SR */
1061 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062 pineview_display_wm.fifo_size,
1063 pixel_size, latency->cursor_sr);
1064 reg = I915_READ(DSPFW3);
1065 reg &= ~DSPFW_CURSOR_SR_MASK;
1066 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067 I915_WRITE(DSPFW3, reg);
1068
1069 /* Display HPLL off SR */
1070 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071 pineview_display_hplloff_wm.fifo_size,
1072 pixel_size, latency->display_hpll_disable);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_HPLL_SR_MASK;
1075 reg |= wm & DSPFW_HPLL_SR_MASK;
1076 I915_WRITE(DSPFW3, reg);
1077
1078 /* cursor HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->cursor_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085 I915_WRITE(DSPFW3, reg);
1086 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088 /* activate cxsr */
1089 I915_WRITE(DSPFW3,
1090 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092 } else {
1093 pineview_disable_cxsr(dev);
1094 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095 }
1096}
1097
1098static bool g4x_compute_wm0(struct drm_device *dev,
1099 int plane,
1100 const struct intel_watermark_params *display,
1101 int display_latency_ns,
1102 const struct intel_watermark_params *cursor,
1103 int cursor_latency_ns,
1104 int *plane_wm,
1105 int *cursor_wm)
1106{
1107 struct drm_crtc *crtc;
4fe8590a 1108 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1109 int htotal, hdisplay, clock, pixel_size;
1110 int line_time_us, line_count;
1111 int entries, tlb_miss;
1112
1113 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1114 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1115 *cursor_wm = cursor->guard_size;
1116 *plane_wm = display->guard_size;
1117 return false;
1118 }
1119
4fe8590a 1120 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1121 clock = adjusted_mode->crtc_clock;
fec8cba3 1122 htotal = adjusted_mode->crtc_htotal;
37327abd 1123 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1124 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1125
1126 /* Use the small buffer method to calculate plane watermark */
1127 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129 if (tlb_miss > 0)
1130 entries += tlb_miss;
1131 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132 *plane_wm = entries + display->guard_size;
1133 if (*plane_wm > (int)display->max_wm)
1134 *plane_wm = display->max_wm;
1135
1136 /* Use the large buffer method to calculate cursor watermark */
922044c9 1137 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1139 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141 if (tlb_miss > 0)
1142 entries += tlb_miss;
1143 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144 *cursor_wm = entries + cursor->guard_size;
1145 if (*cursor_wm > (int)cursor->max_wm)
1146 *cursor_wm = (int)cursor->max_wm;
1147
1148 return true;
1149}
1150
1151/*
1152 * Check the wm result.
1153 *
1154 * If any calculated watermark values is larger than the maximum value that
1155 * can be programmed into the associated watermark register, that watermark
1156 * must be disabled.
1157 */
1158static bool g4x_check_srwm(struct drm_device *dev,
1159 int display_wm, int cursor_wm,
1160 const struct intel_watermark_params *display,
1161 const struct intel_watermark_params *cursor)
1162{
1163 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164 display_wm, cursor_wm);
1165
1166 if (display_wm > display->max_wm) {
1167 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168 display_wm, display->max_wm);
1169 return false;
1170 }
1171
1172 if (cursor_wm > cursor->max_wm) {
1173 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174 cursor_wm, cursor->max_wm);
1175 return false;
1176 }
1177
1178 if (!(display_wm || cursor_wm)) {
1179 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180 return false;
1181 }
1182
1183 return true;
1184}
1185
1186static bool g4x_compute_srwm(struct drm_device *dev,
1187 int plane,
1188 int latency_ns,
1189 const struct intel_watermark_params *display,
1190 const struct intel_watermark_params *cursor,
1191 int *display_wm, int *cursor_wm)
1192{
1193 struct drm_crtc *crtc;
4fe8590a 1194 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1195 int hdisplay, htotal, pixel_size, clock;
1196 unsigned long line_time_us;
1197 int line_count, line_size;
1198 int small, large;
1199 int entries;
1200
1201 if (!latency_ns) {
1202 *display_wm = *cursor_wm = 0;
1203 return false;
1204 }
1205
1206 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1207 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1208 clock = adjusted_mode->crtc_clock;
fec8cba3 1209 htotal = adjusted_mode->crtc_htotal;
37327abd 1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1211 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1212
922044c9 1213 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1215 line_size = hdisplay * pixel_size;
1216
1217 /* Use the minimum of the small and large buffer method for primary */
1218 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219 large = line_count * line_size;
1220
1221 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222 *display_wm = entries + display->guard_size;
1223
1224 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1225 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1226 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227 *cursor_wm = entries + cursor->guard_size;
1228
1229 return g4x_check_srwm(dev,
1230 *display_wm, *cursor_wm,
1231 display, cursor);
1232}
1233
1234static bool vlv_compute_drain_latency(struct drm_device *dev,
1235 int plane,
1236 int *plane_prec_mult,
1237 int *plane_dl,
1238 int *cursor_prec_mult,
1239 int *cursor_dl)
1240{
1241 struct drm_crtc *crtc;
1242 int clock, pixel_size;
1243 int entries;
1244
1245 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1246 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1247 return false;
1248
241bfc38 1249 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1250 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1251
1252 entries = (clock / 1000) * pixel_size;
1253 *plane_prec_mult = (entries > 256) ?
1254 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256 pixel_size);
1257
1258 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1259 *cursor_prec_mult = (entries > 256) ?
1260 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263 return true;
1264}
1265
1266/*
1267 * Update drain latency registers of memory arbiter
1268 *
1269 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270 * to be programmed. Each plane has a drain latency multiplier and a drain
1271 * latency value.
1272 */
1273
1274static void vlv_update_drain_latency(struct drm_device *dev)
1275{
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280 either 16 or 32 */
1281
1282 /* For plane A, Cursor A */
1283 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284 &cursor_prec_mult, &cursora_dl)) {
1285 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290 I915_WRITE(VLV_DDL1, cursora_prec |
1291 (cursora_dl << DDL_CURSORA_SHIFT) |
1292 planea_prec | planea_dl);
1293 }
1294
1295 /* For plane B, Cursor B */
1296 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297 &cursor_prec_mult, &cursorb_dl)) {
1298 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303 I915_WRITE(VLV_DDL2, cursorb_prec |
1304 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305 planeb_prec | planeb_dl);
1306 }
1307}
1308
1309#define single_plane_enabled(mask) is_power_of_2(mask)
1310
46ba614c 1311static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1312{
46ba614c 1313 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1314 static const int sr_latency_ns = 12000;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317 int plane_sr, cursor_sr;
af6c4575 1318 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1319 unsigned int enabled = 0;
1320
1321 vlv_update_drain_latency(dev);
1322
51cea1f4 1323 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1324 &valleyview_wm_info, latency_ns,
1325 &valleyview_cursor_wm_info, latency_ns,
1326 &planea_wm, &cursora_wm))
51cea1f4 1327 enabled |= 1 << PIPE_A;
b445e3b0 1328
51cea1f4 1329 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1330 &valleyview_wm_info, latency_ns,
1331 &valleyview_cursor_wm_info, latency_ns,
1332 &planeb_wm, &cursorb_wm))
51cea1f4 1333 enabled |= 1 << PIPE_B;
b445e3b0 1334
b445e3b0
ED		 1335 if (single_plane_enabled(enabled) &&
1336 g4x_compute_srwm(dev, ffs(enabled) - 1,
1337 sr_latency_ns,
1338 &valleyview_wm_info,
1339 &valleyview_cursor_wm_info,
af6c4575
CW		 1340 &plane_sr, &ignore_cursor_sr) &&
1341 g4x_compute_srwm(dev, ffs(enabled) - 1,
1342 2*sr_latency_ns,
1343 &valleyview_wm_info,
1344 &valleyview_cursor_wm_info,
52bd02d8 1345 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1346 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1347 } else {
b445e3b0
ED		 1348 I915_WRITE(FW_BLC_SELF_VLV,
1349 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1350 plane_sr = cursor_sr = 0;
1351 }
b445e3b0
ED		 1352
1353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354 planea_wm, cursora_wm,
1355 planeb_wm, cursorb_wm,
1356 plane_sr, cursor_sr);
1357
1358 I915_WRITE(DSPFW1,
1359 (plane_sr << DSPFW_SR_SHIFT) |
1360 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362 planea_wm);
1363 I915_WRITE(DSPFW2,
8c919b28 1364 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1365 (cursora_wm << DSPFW_CURSORA_SHIFT));
1366 I915_WRITE(DSPFW3,
8c919b28
CW		 1367 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1369}
1370
46ba614c 1371static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1372{
46ba614c 1373 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 unsigned int enabled = 0;
1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1381 &g4x_wm_info, latency_ns,
1382 &g4x_cursor_wm_info, latency_ns,
1383 &planea_wm, &cursora_wm))
51cea1f4 1384 enabled |= 1 << PIPE_A;
b445e3b0 1385
51cea1f4 1386 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1387 &g4x_wm_info, latency_ns,
1388 &g4x_cursor_wm_info, latency_ns,
1389 &planeb_wm, &cursorb_wm))
51cea1f4 1390 enabled |= 1 << PIPE_B;
b445e3b0 1391
b445e3b0
ED		 1392 if (single_plane_enabled(enabled) &&
1393 g4x_compute_srwm(dev, ffs(enabled) - 1,
1394 sr_latency_ns,
1395 &g4x_wm_info,
1396 &g4x_cursor_wm_info,
52bd02d8 1397 &plane_sr, &cursor_sr)) {
b445e3b0 1398 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1399 } else {
b445e3b0
ED		 1400 I915_WRITE(FW_BLC_SELF,
1401 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1402 plane_sr = cursor_sr = 0;
1403 }
b445e3b0
ED		 1404
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406 planea_wm, cursora_wm,
1407 planeb_wm, cursorb_wm,
1408 plane_sr, cursor_sr);
1409
1410 I915_WRITE(DSPFW1,
1411 (plane_sr << DSPFW_SR_SHIFT) |
1412 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414 planea_wm);
1415 I915_WRITE(DSPFW2,
8c919b28 1416 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1417 (cursora_wm << DSPFW_CURSORA_SHIFT));
1418 /* HPLL off in SR has some issues on G4x... disable it */
1419 I915_WRITE(DSPFW3,
8c919b28 1420 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1421 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422}
1423
46ba614c 1424static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1425{
46ba614c 1426 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct drm_crtc *crtc;
1429 int srwm = 1;
1430 int cursor_sr = 16;
1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1437 const struct drm_display_mode *adjusted_mode =
1438 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1439 int clock = adjusted_mode->crtc_clock;
fec8cba3 1440 int htotal = adjusted_mode->crtc_htotal;
37327abd 1441 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1442 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1443 unsigned long line_time_us;
1444 int entries;
1445
922044c9 1446 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1447
1448 /* Use ns/us then divide to preserve precision */
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 pixel_size * hdisplay;
1451 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452 srwm = I965_FIFO_SIZE - entries;
1453 if (srwm < 0)
1454 srwm = 1;
1455 srwm &= 0x1ff;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457 entries, srwm);
1458
1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1460 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1461 entries = DIV_ROUND_UP(entries,
1462 i965_cursor_wm_info.cacheline_size);
1463 cursor_sr = i965_cursor_wm_info.fifo_size -
1464 (entries + i965_cursor_wm_info.guard_size);
1465
1466 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467 cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm, cursor_sr);
1471
1472 if (IS_CRESTLINE(dev))
1473 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474 } else {
1475 /* Turn off self refresh if both pipes are enabled */
1476 if (IS_CRESTLINE(dev))
1477 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478 & ~FW_BLC_SELF_EN);
1479 }
1480
1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482 srwm);
1483
1484 /* 965 has limitations... */
1485 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486 (8 << 16) | (8 << 8) | (8 << 0));
1487 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490}
1491
46ba614c 1492static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1493{
46ba614c 1494 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 const struct intel_watermark_params *wm_info;
1497 uint32_t fwater_lo;
1498 uint32_t fwater_hi;
1499 int cwm, srwm = 1;
1500 int fifo_size;
1501 int planea_wm, planeb_wm;
1502 struct drm_crtc *crtc, *enabled = NULL;
1503
1504 if (IS_I945GM(dev))
1505 wm_info = &i945_wm_info;
1506 else if (!IS_GEN2(dev))
1507 wm_info = &i915_wm_info;
1508 else
feb56b93 1509 wm_info = &i830_wm_info;
b445e3b0
ED		 1510
1511 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1513 if (intel_crtc_active(crtc)) {
241bfc38 1514 const struct drm_display_mode *adjusted_mode;
f4510a27 1515 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1516 if (IS_GEN2(dev))
1517 cpp = 4;
1518
241bfc38
DL		 1519 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1521 wm_info, fifo_size, cpp,
b445e3b0
ED		 1522 latency_ns);
1523 enabled = crtc;
1524 } else
1525 planea_wm = fifo_size - wm_info->guard_size;
1526
1527 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1529 if (intel_crtc_active(crtc)) {
241bfc38 1530 const struct drm_display_mode *adjusted_mode;
f4510a27 1531 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1532 if (IS_GEN2(dev))
1533 cpp = 4;
1534
241bfc38
DL		 1535 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1537 wm_info, fifo_size, cpp,
b445e3b0
ED		 1538 latency_ns);
1539 if (enabled == NULL)
1540 enabled = crtc;
1541 else
1542 enabled = NULL;
1543 } else
1544 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d
DV		 1548 if (IS_I915GM(dev) && enabled) {
1549 struct intel_framebuffer *fb;
1550
1551 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553 /* self-refresh seems busted with untiled */
1554 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 if (IS_I945G(dev) || IS_I945GM(dev))
1565 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566 else if (IS_I915GM(dev))
3f2dc5ac 1567 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1568
1569 /* Calc sr entries for one plane configs */
1570 if (HAS_FW_BLC(dev) && enabled) {
1571 /* self-refresh has much higher latency */
1572 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1573 const struct drm_display_mode *adjusted_mode =
1574 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1575 int clock = adjusted_mode->crtc_clock;
fec8cba3 1576 int htotal = adjusted_mode->crtc_htotal;
f727b490 1577 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1578 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1579 unsigned long line_time_us;
1580 int entries;
1581
922044c9 1582 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1583
1584 /* Use ns/us then divide to preserve precision */
1585 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586 pixel_size * hdisplay;
1587 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589 srwm = wm_info->fifo_size - entries;
1590 if (srwm < 0)
1591 srwm = 1;
1592
1593 if (IS_I945G(dev) || IS_I945GM(dev))
1594 I915_WRITE(FW_BLC_SELF,
1595 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596 else if (IS_I915GM(dev))
1597 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598 }
1599
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601 planea_wm, planeb_wm, cwm, srwm);
1602
1603 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604 fwater_hi = (cwm & 0x1f);
1605
1606 /* Set request length to 8 cachelines per fetch */
1607 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608 fwater_hi = fwater_hi | (1 << 8);
1609
1610 I915_WRITE(FW_BLC, fwater_lo);
1611 I915_WRITE(FW_BLC2, fwater_hi);
1612
1613 if (HAS_FW_BLC(dev)) {
1614 if (enabled) {
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF,
1617 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618 else if (IS_I915GM(dev))
3f2dc5ac 1619 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1620 DRM_DEBUG_KMS("memory self refresh enabled\n");
1621 } else
1622 DRM_DEBUG_KMS("memory self refresh disabled\n");
1623 }
1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
241bfc38
DL		 1639 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1643 4, latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
3658729a
VS		 1652static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653 struct drm_crtc *crtc)
801bcfff
PZ		 1654{
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1656 uint32_t pixel_rate;
801bcfff 1657
241bfc38 1658 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1659
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1662
fd4daa9c 1663 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1664 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1665 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1666
37327abd
VS		 1667 pipe_w = intel_crtc->config.pipe_src_w;
1668 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
1676 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677 pfit_w * pfit_h);
1678 }
1679
1680 return pixel_rate;
1681}
1682
37126462 1683/* latency must be in 0.1us units. */
23297044 1684static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1685 uint32_t latency)
1686{
1687 uint64_t ret;
1688
3312ba65
VS		 1689 if (WARN(latency == 0, "Latency value missing\n"))
1690 return UINT_MAX;
1691
801bcfff
PZ		 1692 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695 return ret;
1696}
1697
37126462 1698/* latency must be in 0.1us units. */
23297044 1699static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1700 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701 uint32_t latency)
1702{
1703 uint32_t ret;
1704
3312ba65
VS		 1705 if (WARN(latency == 0, "Latency value missing\n"))
1706 return UINT_MAX;
1707
801bcfff
PZ		 1708 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710 ret = DIV_ROUND_UP(ret, 64) + 2;
1711 return ret;
1712}
1713
23297044 1714static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1715 uint8_t bytes_per_pixel)
1716{
1717 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718}
1719
820c1980 1720struct ilk_pipe_wm_parameters {
801bcfff 1721 bool active;
801bcfff
PZ		 1722 uint32_t pipe_htotal;
1723 uint32_t pixel_rate;
c35426d2
VS		 1724 struct intel_plane_wm_parameters pri;
1725 struct intel_plane_wm_parameters spr;
1726 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1727};
1728
820c1980 1729struct ilk_wm_maximums {
cca32e9a
PZ		 1730 uint16_t pri;
1731 uint16_t spr;
1732 uint16_t cur;
1733 uint16_t fbc;
1734};
1735
240264f4
VS		 1736/* used in computing the new watermarks state */
1737struct intel_wm_config {
1738 unsigned int num_pipes_active;
1739 bool sprites_enabled;
1740 bool sprites_scaled;
240264f4
VS		 1741};
1742
37126462
VS		 1743/*
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1746 */
820c1980 1747static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
cca32e9a
PZ		 1751 uint32_t method1, method2;
1752
c35426d2 1753 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1754 return 0;
1755
23297044 1756 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1757 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1758 mem_value);
1759
1760 if (!is_lp)
1761 return method1;
1762
23297044 1763 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1764 params->pipe_htotal,
c35426d2
VS		 1765 params->pri.horiz_pixels,
1766 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1767 mem_value);
1768
1769 return min(method1, method2);
801bcfff
PZ		 1770}
1771
37126462
VS		 1772/*
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1775 */
820c1980 1776static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
1779 uint32_t method1, method2;
1780
c35426d2 1781 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1782 return 0;
1783
23297044 1784 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1785 params->spr.bytes_per_pixel,
801bcfff 1786 mem_value);
23297044 1787 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1788 params->pipe_htotal,
c35426d2
VS		 1789 params->spr.horiz_pixels,
1790 params->spr.bytes_per_pixel,
801bcfff
PZ		 1791 mem_value);
1792 return min(method1, method2);
1793}
1794
37126462
VS		 1795/*
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1798 */
820c1980 1799static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
c35426d2 1802 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1803 return 0;
1804
23297044 1805 return ilk_wm_method2(params->pixel_rate,
801bcfff 1806 params->pipe_htotal,
c35426d2
VS		 1807 params->cur.horiz_pixels,
1808 params->cur.bytes_per_pixel,
801bcfff
PZ		 1809 mem_value);
1810}
1811
cca32e9a 1812/* Only for WM_LP. */
820c1980 1813static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1814 uint32_t pri_val)
cca32e9a 1815{
c35426d2 1816 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1817 return 0;
1818
23297044 1819 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1820 params->pri.horiz_pixels,
1821 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1822}
1823
158ae64f
VS		 1824static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825{
416f4727
VS		 1826 if (INTEL_INFO(dev)->gen >= 8)
1827 return 3072;
1828 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1829 return 768;
1830 else
1831 return 512;
1832}
1833
1834/* Calculate the maximum primary/sprite plane watermark */
1835static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1836 int level,
240264f4 1837 const struct intel_wm_config *config,
158ae64f
VS		 1838 enum intel_ddb_partitioning ddb_partitioning,
1839 bool is_sprite)
1840{
1841 unsigned int fifo_size = ilk_display_fifo_size(dev);
1842 unsigned int max;
1843
1844 /* if sprites aren't enabled, sprites get nothing */
240264f4 1845 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1846 return 0;
1847
1848 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1849 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1850 fifo_size /= INTEL_INFO(dev)->num_pipes;
1851
1852 /*
1853 * For some reason the non self refresh
1854 * FIFO size is only half of the self
1855 * refresh FIFO size on ILK/SNB.
1856 */
1857 if (INTEL_INFO(dev)->gen <= 6)
1858 fifo_size /= 2;
1859 }
1860
240264f4 1861 if (config->sprites_enabled) {
158ae64f
VS		 1862 /* level 0 is always calculated with 1:1 split */
1863 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1864 if (is_sprite)
1865 fifo_size *= 5;
1866 fifo_size /= 6;
1867 } else {
1868 fifo_size /= 2;
1869 }
1870 }
1871
1872 /* clamp to max that the registers can hold */
416f4727
VS		 1873 if (INTEL_INFO(dev)->gen >= 8)
1874 max = level == 0 ? 255 : 2047;
1875 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1876 /* IVB/HSW primary/sprite plane watermarks */
1877 max = level == 0 ? 127 : 1023;
1878 else if (!is_sprite)
1879 /* ILK/SNB primary plane watermarks */
1880 max = level == 0 ? 127 : 511;
1881 else
1882 /* ILK/SNB sprite plane watermarks */
1883 max = level == 0 ? 63 : 255;
1884
1885 return min(fifo_size, max);
1886}
1887
1888/* Calculate the maximum cursor plane watermark */
1889static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1890 int level,
1891 const struct intel_wm_config *config)
158ae64f
VS		 1892{
1893 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1894 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1895 return 64;
1896
1897 /* otherwise just report max that registers can hold */
1898 if (INTEL_INFO(dev)->gen >= 7)
1899 return level == 0 ? 63 : 255;
1900 else
1901 return level == 0 ? 31 : 63;
1902}
1903
1904/* Calculate the maximum FBC watermark */
d34ff9c6 1905static unsigned int ilk_fbc_wm_max(const struct drm_device *dev)
158ae64f
VS		 1906{
1907 /* max that registers can hold */
416f4727
VS		 1908 if (INTEL_INFO(dev)->gen >= 8)
1909 return 31;
1910 else
1911 return 15;
158ae64f
VS		 1912}
1913
d34ff9c6 1914static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1915 int level,
1916 const struct intel_wm_config *config,
1917 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1918 struct ilk_wm_maximums *max)
158ae64f 1919{
240264f4
VS		 1920 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1921 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1922 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 1923 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 1924}
1925
d9395655 1926static bool ilk_validate_wm_level(int level,
820c1980 1927 const struct ilk_wm_maximums *max,
d9395655 1928 struct intel_wm_level *result)
a9786a11
VS		 1929{
1930 bool ret;
1931
1932 /* already determined to be invalid? */
1933 if (!result->enable)
1934 return false;
1935
1936 result->enable = result->pri_val <= max->pri &&
1937 result->spr_val <= max->spr &&
1938 result->cur_val <= max->cur;
1939
1940 ret = result->enable;
1941
1942 /*
1943 * HACK until we can pre-compute everything,
1944 * and thus fail gracefully if LP0 watermarks
1945 * are exceeded...
1946 */
1947 if (level == 0 && !result->enable) {
1948 if (result->pri_val > max->pri)
1949 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1950 level, result->pri_val, max->pri);
1951 if (result->spr_val > max->spr)
1952 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1953 level, result->spr_val, max->spr);
1954 if (result->cur_val > max->cur)
1955 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1956 level, result->cur_val, max->cur);
1957
1958 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1959 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1960 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1961 result->enable = true;
1962 }
1963
a9786a11
VS		 1964 return ret;
1965}
1966
d34ff9c6 1967static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1968 int level,
820c1980 1969 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1970 struct intel_wm_level *result)
6f5ddd17
VS		 1971{
1972 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1973 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1974 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1975
1976 /* WM1+ latency values stored in 0.5us units */
1977 if (level > 0) {
1978 pri_latency *= 5;
1979 spr_latency *= 5;
1980 cur_latency *= 5;
1981 }
1982
1983 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1984 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1985 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1986 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1987 result->enable = true;
1988}
1989
801bcfff
PZ		 1990static uint32_t
1991hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1992{
1993 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 1995 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 1996 u32 linetime, ips_linetime;
1f8eeabf 1997
801bcfff
PZ		 1998 if (!intel_crtc_active(crtc))
1999 return 0;
1011d8c4 2000
1f8eeabf
ED		 2001 /* The WM are computed with base on how long it takes to fill a single
2002 * row at the given clock rate, multiplied by 8.
2003 * */
fec8cba3
JB		 2004 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2005 mode->crtc_clock);
2006 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2007 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2008
801bcfff
PZ		 2009 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2010 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2011}
2012
12b134df
VS		 2013static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2014{
2015 struct drm_i915_private *dev_priv = dev->dev_private;
2016
a42a5719 2017 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2018 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2019
2020 wm[0] = (sskpd >> 56) & 0xFF;
2021 if (wm[0] == 0)
2022 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2023 wm[1] = (sskpd >> 4) & 0xFF;
2024 wm[2] = (sskpd >> 12) & 0xFF;
2025 wm[3] = (sskpd >> 20) & 0x1FF;
2026 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2027 } else if (INTEL_INFO(dev)->gen >= 6) {
2028 uint32_t sskpd = I915_READ(MCH_SSKPD);
2029
2030 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2031 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2032 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2033 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2034 } else if (INTEL_INFO(dev)->gen >= 5) {
2035 uint32_t mltr = I915_READ(MLTR_ILK);
2036
2037 /* ILK primary LP0 latency is 700 ns */
2038 wm[0] = 7;
2039 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2040 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2041 }
2042}
2043
53615a5e
VS		 2044static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2045{
2046 /* ILK sprite LP0 latency is 1300 ns */
2047 if (INTEL_INFO(dev)->gen == 5)
2048 wm[0] = 13;
2049}
2050
2051static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2052{
2053 /* ILK cursor LP0 latency is 1300 ns */
2054 if (INTEL_INFO(dev)->gen == 5)
2055 wm[0] = 13;
2056
2057 /* WaDoubleCursorLP3Latency:ivb */
2058 if (IS_IVYBRIDGE(dev))
2059 wm[3] *= 2;
2060}
2061
ad0d6dc4 2062static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2063{
26ec971e 2064 /* how many WM levels are we expecting */
a42a5719 2065 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2066 return 4;
26ec971e 2067 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2068 return 3;
26ec971e 2069 else
ad0d6dc4
VS		 2070 return 2;
2071}
2072
2073static void intel_print_wm_latency(struct drm_device *dev,
2074 const char *name,
2075 const uint16_t wm[5])
2076{
2077 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2078
2079 for (level = 0; level <= max_level; level++) {
2080 unsigned int latency = wm[level];
2081
2082 if (latency == 0) {
2083 DRM_ERROR("%s WM%d latency not provided\n",
2084 name, level);
2085 continue;
2086 }
2087
2088 /* WM1+ latency values in 0.5us units */
2089 if (level > 0)
2090 latency *= 5;
2091
2092 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2093 name, level, wm[level],
2094 latency / 10, latency % 10);
2095 }
2096}
2097
fa50ad61 2098static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2099{
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101
2102 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2103
2104 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2105 sizeof(dev_priv->wm.pri_latency));
2106 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2107 sizeof(dev_priv->wm.pri_latency));
2108
2109 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2110 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2111
2112 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2113 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2114 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2115}
2116
820c1980
ID		 2117static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2118 struct ilk_pipe_wm_parameters *p,
a485bfb8 2119 struct intel_wm_config *config)
1011d8c4 2120{
7c4a395f
VS		 2121 struct drm_device *dev = crtc->dev;
2122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2123 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2124 struct drm_plane *plane;
1011d8c4 2125
7c4a395f
VS		 2126 p->active = intel_crtc_active(crtc);
2127 if (p->active) {
576b259e 2128 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
3658729a 2129 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
f4510a27 2130 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
c35426d2 2131 p->cur.bytes_per_pixel = 4;
37327abd 2132 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
7bb836dd 2133 p->cur.horiz_pixels = intel_crtc->cursor_width;
c35426d2
VS		 2134 /* TODO: for now, assume primary and cursor planes are always enabled. */
2135 p->pri.enabled = true;
2136 p->cur.enabled = true;
801bcfff
PZ		 2137 }
2138
7c4a395f 2139 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2140 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2141
af2b653b 2142 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2143 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2144
7c4a395f
VS		 2145 if (intel_plane->pipe == pipe)
2146 p->spr = intel_plane->wm;
cca32e9a 2147
a485bfb8
VS		 2148 config->sprites_enabled |= intel_plane->wm.enabled;
2149 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2150 }
801bcfff
PZ		 2151}
2152
0b2ae6d7
VS		 2153/* Compute new watermarks for the pipe */
2154static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2155 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2156 struct intel_pipe_wm *pipe_wm)
2157{
2158 struct drm_device *dev = crtc->dev;
d34ff9c6 2159 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2160 int level, max_level = ilk_wm_max_level(dev);
2161 /* LP0 watermark maximums depend on this pipe alone */
2162 struct intel_wm_config config = {
2163 .num_pipes_active = 1,
2164 .sprites_enabled = params->spr.enabled,
2165 .sprites_scaled = params->spr.scaled,
2166 };
820c1980 2167 struct ilk_wm_maximums max;
0b2ae6d7 2168
0b2ae6d7 2169 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2170 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7 2171
7b39a0b7
VS		 2172 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2173 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2174 max_level = 1;
2175
2176 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2177 if (params->spr.scaled)
2178 max_level = 0;
2179
0b2ae6d7
VS		 2180 for (level = 0; level <= max_level; level++)
2181 ilk_compute_wm_level(dev_priv, level, params,
2182 &pipe_wm->wm[level]);
2183
a42a5719 2184 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2185 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7
VS		 2186
2187 /* At least LP0 must be valid */
d9395655 2188 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2189}
2190
2191/*
2192 * Merge the watermarks from all active pipes for a specific level.
2193 */
2194static void ilk_merge_wm_level(struct drm_device *dev,
2195 int level,
2196 struct intel_wm_level *ret_wm)
2197{
2198 const struct intel_crtc *intel_crtc;
2199
2200 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2201 const struct intel_wm_level *wm =
2202 &intel_crtc->wm.active.wm[level];
2203
2204 if (!wm->enable)
2205 return;
2206
2207 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2208 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2209 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2210 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2211 }
2212
2213 ret_wm->enable = true;
2214}
2215
2216/*
2217 * Merge all low power watermarks for all active pipes.
2218 */
2219static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2220 const struct intel_wm_config *config,
820c1980 2221 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2222 struct intel_pipe_wm *merged)
2223{
2224 int level, max_level = ilk_wm_max_level(dev);
2225
0ba22e26
VS		 2226 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2227 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2228 config->num_pipes_active > 1)
2229 return;
2230
6c8b6c28
VS		 2231 /* ILK: FBC WM must be disabled always */
2232 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2233
2234 /* merge each WM1+ level */
2235 for (level = 1; level <= max_level; level++) {
2236 struct intel_wm_level *wm = &merged->wm[level];
2237
2238 ilk_merge_wm_level(dev, level, wm);
2239
d9395655 2240 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2241 break;
2242
2243 /*
2244 * The spec says it is preferred to disable
2245 * FBC WMs instead of disabling a WM level.
2246 */
2247 if (wm->fbc_val > max->fbc) {
2248 merged->fbc_wm_enabled = false;
2249 wm->fbc_val = 0;
2250 }
2251 }
6c8b6c28
VS		 2252
2253 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2254 /*
2255 * FIXME this is racy. FBC might get enabled later.
2256 * What we should check here is whether FBC can be
2257 * enabled sometime later.
2258 */
2259 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2260 for (level = 2; level <= max_level; level++) {
2261 struct intel_wm_level *wm = &merged->wm[level];
2262
2263 wm->enable = false;
2264 }
2265 }
0b2ae6d7
VS		 2266}
2267
b380ca3c
VS		 2268static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2269{
2270 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2271 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2272}
2273
a68d68ee
VS		 2274/* The value we need to program into the WM_LPx latency field */
2275static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2276{
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278
a42a5719 2279 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2280 return 2 * level;
2281 else
2282 return dev_priv->wm.pri_latency[level];
2283}
2284
820c1980 2285static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2286 const struct intel_pipe_wm *merged,
609cedef 2287 enum intel_ddb_partitioning partitioning,
820c1980 2288 struct ilk_wm_values *results)
801bcfff 2289{
0b2ae6d7
VS		 2290 struct intel_crtc *intel_crtc;
2291 int level, wm_lp;
cca32e9a 2292
0362c781 2293 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2294 results->partitioning = partitioning;
cca32e9a 2295
0b2ae6d7 2296 /* LP1+ register values */
cca32e9a 2297 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2298 const struct intel_wm_level *r;
801bcfff 2299
b380ca3c 2300 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2301
0362c781 2302 r = &merged->wm[level];
0b2ae6d7 2303 if (!r->enable)
cca32e9a
PZ		 2304 break;
2305
416f4727 2306 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
a68d68ee 2307 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2308 (r->pri_val << WM1_LP_SR_SHIFT) |
2309 r->cur_val;
2310
2311 if (INTEL_INFO(dev)->gen >= 8)
2312 results->wm_lp[wm_lp - 1] |=
2313 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2314 else
2315 results->wm_lp[wm_lp - 1] |=
2316 r->fbc_val << WM1_LP_FBC_SHIFT;
2317
6cef2b8a
VS		 2318 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2319 WARN_ON(wm_lp != 1);
2320 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2321 } else
2322 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2323 }
801bcfff 2324
0b2ae6d7
VS		 2325 /* LP0 register values */
2326 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2327 enum pipe pipe = intel_crtc->pipe;
2328 const struct intel_wm_level *r =
2329 &intel_crtc->wm.active.wm[0];
2330
2331 if (WARN_ON(!r->enable))
2332 continue;
2333
2334 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2335
0b2ae6d7
VS		 2336 results->wm_pipe[pipe] =
2337 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2338 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2339 r->cur_val;
801bcfff
PZ		 2340 }
2341}
2342
861f3389
PZ		 2343/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2344 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2345static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2346 struct intel_pipe_wm *r1,
2347 struct intel_pipe_wm *r2)
861f3389 2348{
198a1e9b
VS		 2349 int level, max_level = ilk_wm_max_level(dev);
2350 int level1 = 0, level2 = 0;
861f3389 2351
198a1e9b
VS		 2352 for (level = 1; level <= max_level; level++) {
2353 if (r1->wm[level].enable)
2354 level1 = level;
2355 if (r2->wm[level].enable)
2356 level2 = level;
861f3389
PZ		 2357 }
2358
198a1e9b
VS		 2359 if (level1 == level2) {
2360 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2361 return r2;
2362 else
2363 return r1;
198a1e9b 2364 } else if (level1 > level2) {
861f3389
PZ		 2365 return r1;
2366 } else {
2367 return r2;
2368 }
2369}
2370
49a687c4
VS		 2371/* dirty bits used to track which watermarks need changes */
2372#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2373#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2374#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2375#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2376#define WM_DIRTY_FBC (1 << 24)
2377#define WM_DIRTY_DDB (1 << 25)
2378
2379static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2380 const struct ilk_wm_values *old,
2381 const struct ilk_wm_values *new)
49a687c4
VS		 2382{
2383 unsigned int dirty = 0;
2384 enum pipe pipe;
2385 int wm_lp;
2386
2387 for_each_pipe(pipe) {
2388 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2389 dirty |= WM_DIRTY_LINETIME(pipe);
2390 /* Must disable LP1+ watermarks too */
2391 dirty |= WM_DIRTY_LP_ALL;
2392 }
2393
2394 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2395 dirty |= WM_DIRTY_PIPE(pipe);
2396 /* Must disable LP1+ watermarks too */
2397 dirty |= WM_DIRTY_LP_ALL;
2398 }
2399 }
2400
2401 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2402 dirty |= WM_DIRTY_FBC;
2403 /* Must disable LP1+ watermarks too */
2404 dirty |= WM_DIRTY_LP_ALL;
2405 }
2406
2407 if (old->partitioning != new->partitioning) {
2408 dirty |= WM_DIRTY_DDB;
2409 /* Must disable LP1+ watermarks too */
2410 dirty |= WM_DIRTY_LP_ALL;
2411 }
2412
2413 /* LP1+ watermarks already deemed dirty, no need to continue */
2414 if (dirty & WM_DIRTY_LP_ALL)
2415 return dirty;
2416
2417 /* Find the lowest numbered LP1+ watermark in need of an update... */
2418 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2419 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2420 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2421 break;
2422 }
2423
2424 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2425 for (; wm_lp <= 3; wm_lp++)
2426 dirty |= WM_DIRTY_LP(wm_lp);
2427
2428 return dirty;
2429}
2430
8553c18e
VS		 2431static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2432 unsigned int dirty)
801bcfff 2433{
820c1980 2434 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2435 bool changed = false;
801bcfff 2436
facd619b
VS		 2437 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2438 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2439 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2440 changed = true;
facd619b
VS		 2441 }
2442 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2443 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2444 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2445 changed = true;
facd619b
VS		 2446 }
2447 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2448 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2449 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2450 changed = true;
facd619b 2451 }
801bcfff 2452
facd619b
VS		 2453 /*
2454 * Don't touch WM1S_LP_EN here.
2455 * Doing so could cause underruns.
2456 */
6cef2b8a 2457
8553c18e
VS		 2458 return changed;
2459}
2460
2461/*
2462 * The spec says we shouldn't write when we don't need, because every write
2463 * causes WMs to be re-evaluated, expending some power.
2464 */
820c1980
ID		 2465static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2466 struct ilk_wm_values *results)
8553c18e
VS		 2467{
2468 struct drm_device *dev = dev_priv->dev;
820c1980 2469 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2470 unsigned int dirty;
2471 uint32_t val;
2472
2473 dirty = ilk_compute_wm_dirty(dev, previous, results);
2474 if (!dirty)
2475 return;
2476
2477 _ilk_disable_lp_wm(dev_priv, dirty);
2478
49a687c4 2479 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2480 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2481 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2482 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2483 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2484 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2485
49a687c4 2486 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2487 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2488 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2489 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2490 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2491 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2492
49a687c4 2493 if (dirty & WM_DIRTY_DDB) {
a42a5719 2494 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2495 val = I915_READ(WM_MISC);
2496 if (results->partitioning == INTEL_DDB_PART_1_2)
2497 val &= ~WM_MISC_DATA_PARTITION_5_6;
2498 else
2499 val |= WM_MISC_DATA_PARTITION_5_6;
2500 I915_WRITE(WM_MISC, val);
2501 } else {
2502 val = I915_READ(DISP_ARB_CTL2);
2503 if (results->partitioning == INTEL_DDB_PART_1_2)
2504 val &= ~DISP_DATA_PARTITION_5_6;
2505 else
2506 val |= DISP_DATA_PARTITION_5_6;
2507 I915_WRITE(DISP_ARB_CTL2, val);
2508 }
1011d8c4
PZ		 2509 }
2510
49a687c4 2511 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2512 val = I915_READ(DISP_ARB_CTL);
2513 if (results->enable_fbc_wm)
2514 val &= ~DISP_FBC_WM_DIS;
2515 else
2516 val |= DISP_FBC_WM_DIS;
2517 I915_WRITE(DISP_ARB_CTL, val);
2518 }
2519
954911eb
ID		 2520 if (dirty & WM_DIRTY_LP(1) &&
2521 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2522 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2523
2524 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2525 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2526 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2527 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2528 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2529 }
801bcfff 2530
facd619b 2531 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2532 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2533 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2534 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2535 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2536 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2537
2538 dev_priv->wm.hw = *results;
801bcfff
PZ		 2539}
2540
8553c18e
VS		 2541static bool ilk_disable_lp_wm(struct drm_device *dev)
2542{
2543 struct drm_i915_private *dev_priv = dev->dev_private;
2544
2545 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2546}
2547
820c1980 2548static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2549{
7c4a395f 2550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2551 struct drm_device *dev = crtc->dev;
801bcfff 2552 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2553 struct ilk_wm_maximums max;
2554 struct ilk_pipe_wm_parameters params = {};
2555 struct ilk_wm_values results = {};
77c122bc 2556 enum intel_ddb_partitioning partitioning;
7c4a395f 2557 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2558 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2559 struct intel_wm_config config = {};
7c4a395f 2560
820c1980 2561 ilk_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2562
2563 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2564
2565 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2566 return;
861f3389 2567
7c4a395f 2568 intel_crtc->wm.active = pipe_wm;
861f3389 2569
34982fe1 2570 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2571 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2572
2573 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2574 if (INTEL_INFO(dev)->gen >= 7 &&
2575 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2576 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2577 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2578
820c1980 2579 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2580 } else {
198a1e9b 2581 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2582 }
2583
198a1e9b 2584 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2585 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2586
820c1980 2587 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2588
820c1980 2589 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2590}
2591
820c1980 2592static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2593 struct drm_crtc *crtc,
526682e9 2594 uint32_t sprite_width, int pixel_size,
bdd57d03 2595 bool enabled, bool scaled)
526682e9 2596{
8553c18e 2597 struct drm_device *dev = plane->dev;
adf3d35e 2598 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2599
adf3d35e
VS		 2600 intel_plane->wm.enabled = enabled;
2601 intel_plane->wm.scaled = scaled;
2602 intel_plane->wm.horiz_pixels = sprite_width;
2603 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2604
8553c18e
VS		 2605 /*
2606 * IVB workaround: must disable low power watermarks for at least
2607 * one frame before enabling scaling. LP watermarks can be re-enabled
2608 * when scaling is disabled.
2609 *
2610 * WaCxSRDisabledForSpriteScaling:ivb
2611 */
2612 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2613 intel_wait_for_vblank(dev, intel_plane->pipe);
2614
820c1980 2615 ilk_update_wm(crtc);
526682e9
PZ		 2616}
2617
243e6a44
VS		 2618static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2619{
2620 struct drm_device *dev = crtc->dev;
2621 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2622 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2624 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2625 enum pipe pipe = intel_crtc->pipe;
2626 static const unsigned int wm0_pipe_reg[] = {
2627 [PIPE_A] = WM0_PIPEA_ILK,
2628 [PIPE_B] = WM0_PIPEB_ILK,
2629 [PIPE_C] = WM0_PIPEC_IVB,
2630 };
2631
2632 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2633 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2634 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44
VS		 2635
2636 if (intel_crtc_active(crtc)) {
2637 u32 tmp = hw->wm_pipe[pipe];
2638
2639 /*
2640 * For active pipes LP0 watermark is marked as
2641 * enabled, and LP1+ watermaks as disabled since
2642 * we can't really reverse compute them in case
2643 * multiple pipes are active.
2644 */
2645 active->wm[0].enable = true;
2646 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2647 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2648 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2649 active->linetime = hw->wm_linetime[pipe];
2650 } else {
2651 int level, max_level = ilk_wm_max_level(dev);
2652
2653 /*
2654 * For inactive pipes, all watermark levels
2655 * should be marked as enabled but zeroed,
2656 * which is what we'd compute them to.
2657 */
2658 for (level = 0; level <= max_level; level++)
2659 active->wm[level].enable = true;
2660 }
2661}
2662
2663void ilk_wm_get_hw_state(struct drm_device *dev)
2664{
2665 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2666 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2667 struct drm_crtc *crtc;
2668
2669 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2670 ilk_pipe_wm_get_hw_state(crtc);
2671
2672 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2673 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2674 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2675
2676 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2677 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2678 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2679
a42a5719 2680 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2681 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2682 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2683 else if (IS_IVYBRIDGE(dev))
2684 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2685 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2686
2687 hw->enable_fbc_wm =
2688 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2689}
2690
b445e3b0
ED		 2691/**
2692 * intel_update_watermarks - update FIFO watermark values based on current modes
2693 *
2694 * Calculate watermark values for the various WM regs based on current mode
2695 * and plane configuration.
2696 *
2697 * There are several cases to deal with here:
2698 * - normal (i.e. non-self-refresh)
2699 * - self-refresh (SR) mode
2700 * - lines are large relative to FIFO size (buffer can hold up to 2)
2701 * - lines are small relative to FIFO size (buffer can hold more than 2
2702 * lines), so need to account for TLB latency
2703 *
2704 * The normal calculation is:
2705 * watermark = dotclock * bytes per pixel * latency
2706 * where latency is platform & configuration dependent (we assume pessimal
2707 * values here).
2708 *
2709 * The SR calculation is:
2710 * watermark = (trunc(latency/line time)+1) * surface width *
2711 * bytes per pixel
2712 * where
2713 * line time = htotal / dotclock
2714 * surface width = hdisplay for normal plane and 64 for cursor
2715 * and latency is assumed to be high, as above.
2716 *
2717 * The final value programmed to the register should always be rounded up,
2718 * and include an extra 2 entries to account for clock crossings.
2719 *
2720 * We don't use the sprite, so we can ignore that. And on Crestline we have
2721 * to set the non-SR watermarks to 8.
2722 */
46ba614c 2723void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2724{
46ba614c 2725 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2726
2727 if (dev_priv->display.update_wm)
46ba614c 2728 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2729}
2730
adf3d35e
VS		 2731void intel_update_sprite_watermarks(struct drm_plane *plane,
2732 struct drm_crtc *crtc,
4c4ff43a 2733 uint32_t sprite_width, int pixel_size,
39db4a4d 2734 bool enabled, bool scaled)
b445e3b0 2735{
adf3d35e 2736 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2737
2738 if (dev_priv->display.update_sprite_wm)
adf3d35e 2739 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2740 pixel_size, enabled, scaled);
b445e3b0
ED		 2741}
2742
2b4e57bd
ED		 2743static struct drm_i915_gem_object *
2744intel_alloc_context_page(struct drm_device *dev)
2745{
2746 struct drm_i915_gem_object *ctx;
2747 int ret;
2748
2749 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2750
2751 ctx = i915_gem_alloc_object(dev, 4096);
2752 if (!ctx) {
2753 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2754 return NULL;
2755 }
2756
c69766f2 2757 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2758 if (ret) {
2759 DRM_ERROR("failed to pin power context: %d\n", ret);
2760 goto err_unref;
2761 }
2762
2763 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2764 if (ret) {
2765 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2766 goto err_unpin;
2767 }
2768
2769 return ctx;
2770
2771err_unpin:
d7f46fc4 2772 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2773err_unref:
2774 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2775 return NULL;
2776}
2777
9270388e
DV		 2778/**
2779 * Lock protecting IPS related data structures
9270388e
DV		 2780 */
2781DEFINE_SPINLOCK(mchdev_lock);
2782
2783/* Global for IPS driver to get at the current i915 device. Protected by
2784 * mchdev_lock. */
2785static struct drm_i915_private *i915_mch_dev;
2786
2b4e57bd
ED		 2787bool ironlake_set_drps(struct drm_device *dev, u8 val)
2788{
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 u16 rgvswctl;
2791
9270388e
DV		 2792 assert_spin_locked(&mchdev_lock);
2793
2b4e57bd
ED		 2794 rgvswctl = I915_READ16(MEMSWCTL);
2795 if (rgvswctl & MEMCTL_CMD_STS) {
2796 DRM_DEBUG("gpu busy, RCS change rejected\n");
2797 return false; /* still busy with another command */
2798 }
2799
2800 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2801 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2802 I915_WRITE16(MEMSWCTL, rgvswctl);
2803 POSTING_READ16(MEMSWCTL);
2804
2805 rgvswctl |= MEMCTL_CMD_STS;
2806 I915_WRITE16(MEMSWCTL, rgvswctl);
2807
2808 return true;
2809}
2810
8090c6b9 2811static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2812{
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 u32 rgvmodectl = I915_READ(MEMMODECTL);
2815 u8 fmax, fmin, fstart, vstart;
2816
9270388e
DV		 2817 spin_lock_irq(&mchdev_lock);
2818
2b4e57bd
ED		 2819 /* Enable temp reporting */
2820 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2821 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2822
2823 /* 100ms RC evaluation intervals */
2824 I915_WRITE(RCUPEI, 100000);
2825 I915_WRITE(RCDNEI, 100000);
2826
2827 /* Set max/min thresholds to 90ms and 80ms respectively */
2828 I915_WRITE(RCBMAXAVG, 90000);
2829 I915_WRITE(RCBMINAVG, 80000);
2830
2831 I915_WRITE(MEMIHYST, 1);
2832
2833 /* Set up min, max, and cur for interrupt handling */
2834 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2835 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2836 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2837 MEMMODE_FSTART_SHIFT;
2838
2839 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2840 PXVFREQ_PX_SHIFT;
2841
20e4d407
DV		 2842 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2843 dev_priv->ips.fstart = fstart;
2b4e57bd 2844
20e4d407
DV		 2845 dev_priv->ips.max_delay = fstart;
2846 dev_priv->ips.min_delay = fmin;
2847 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2848
2849 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2850 fmax, fmin, fstart);
2851
2852 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2853
2854 /*
2855 * Interrupts will be enabled in ironlake_irq_postinstall
2856 */
2857
2858 I915_WRITE(VIDSTART, vstart);
2859 POSTING_READ(VIDSTART);
2860
2861 rgvmodectl |= MEMMODE_SWMODE_EN;
2862 I915_WRITE(MEMMODECTL, rgvmodectl);
2863
9270388e 2864 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2865 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2866 mdelay(1);
2b4e57bd
ED		 2867
2868 ironlake_set_drps(dev, fstart);
2869
20e4d407 2870 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2871 I915_READ(0x112e0);
20e4d407
DV		 2872 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2873 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2874 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2875
2876 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2877}
2878
8090c6b9 2879static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2880{
2881 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2882 u16 rgvswctl;
2883
2884 spin_lock_irq(&mchdev_lock);
2885
2886 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2887
2888 /* Ack interrupts, disable EFC interrupt */
2889 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2890 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2891 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2892 I915_WRITE(DEIIR, DE_PCU_EVENT);
2893 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2894
2895 /* Go back to the starting frequency */
20e4d407 2896 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2897 mdelay(1);
2b4e57bd
ED		 2898 rgvswctl |= MEMCTL_CMD_STS;
2899 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2900 mdelay(1);
2b4e57bd 2901
9270388e 2902 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2903}
2904
acbe9475
DV		 2905/* There's a funny hw issue where the hw returns all 0 when reading from
2906 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2907 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2908 * all limits and the gpu stuck at whatever frequency it is at atm).
2909 */
6917c7b9 2910static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 2911{
7b9e0ae6 2912 u32 limits;
2b4e57bd 2913
20b46e59
DV		 2914 /* Only set the down limit when we've reached the lowest level to avoid
2915 * getting more interrupts, otherwise leave this clear. This prevents a
2916 * race in the hw when coming out of rc6: There's a tiny window where
2917 * the hw runs at the minimal clock before selecting the desired
2918 * frequency, if the down threshold expires in that window we will not
2919 * receive a down interrupt. */
b39fb297
BW		 2920 limits = dev_priv->rps.max_freq_softlimit << 24;
2921 if (val <= dev_priv->rps.min_freq_softlimit)
2922 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 2923
2924 return limits;
2925}
2926
dd75fdc8
CW		 2927static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2928{
2929 int new_power;
2930
2931 new_power = dev_priv->rps.power;
2932 switch (dev_priv->rps.power) {
2933 case LOW_POWER:
b39fb297 2934 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 2935 new_power = BETWEEN;
2936 break;
2937
2938 case BETWEEN:
b39fb297 2939 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 2940 new_power = LOW_POWER;
b39fb297 2941 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 2942 new_power = HIGH_POWER;
2943 break;
2944
2945 case HIGH_POWER:
b39fb297 2946 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 2947 new_power = BETWEEN;
2948 break;
2949 }
2950 /* Max/min bins are special */
b39fb297 2951 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 2952 new_power = LOW_POWER;
b39fb297 2953 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 2954 new_power = HIGH_POWER;
2955 if (new_power == dev_priv->rps.power)
2956 return;
2957
2958 /* Note the units here are not exactly 1us, but 1280ns. */
2959 switch (new_power) {
2960 case LOW_POWER:
2961 /* Upclock if more than 95% busy over 16ms */
2962 I915_WRITE(GEN6_RP_UP_EI, 12500);
2963 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2964
2965 /* Downclock if less than 85% busy over 32ms */
2966 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2967 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2968
2969 I915_WRITE(GEN6_RP_CONTROL,
2970 GEN6_RP_MEDIA_TURBO |
2971 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2972 GEN6_RP_MEDIA_IS_GFX |
2973 GEN6_RP_ENABLE |
2974 GEN6_RP_UP_BUSY_AVG |
2975 GEN6_RP_DOWN_IDLE_AVG);
2976 break;
2977
2978 case BETWEEN:
2979 /* Upclock if more than 90% busy over 13ms */
2980 I915_WRITE(GEN6_RP_UP_EI, 10250);
2981 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2982
2983 /* Downclock if less than 75% busy over 32ms */
2984 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2985 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2986
2987 I915_WRITE(GEN6_RP_CONTROL,
2988 GEN6_RP_MEDIA_TURBO |
2989 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2990 GEN6_RP_MEDIA_IS_GFX |
2991 GEN6_RP_ENABLE |
2992 GEN6_RP_UP_BUSY_AVG |
2993 GEN6_RP_DOWN_IDLE_AVG);
2994 break;
2995
2996 case HIGH_POWER:
2997 /* Upclock if more than 85% busy over 10ms */
2998 I915_WRITE(GEN6_RP_UP_EI, 8000);
2999 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3000
3001 /* Downclock if less than 60% busy over 32ms */
3002 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3003 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3004
3005 I915_WRITE(GEN6_RP_CONTROL,
3006 GEN6_RP_MEDIA_TURBO |
3007 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3008 GEN6_RP_MEDIA_IS_GFX |
3009 GEN6_RP_ENABLE |
3010 GEN6_RP_UP_BUSY_AVG |
3011 GEN6_RP_DOWN_IDLE_AVG);
3012 break;
3013 }
3014
3015 dev_priv->rps.power = new_power;
3016 dev_priv->rps.last_adj = 0;
3017}
3018
2876ce73
CW		 3019static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3020{
3021 u32 mask = 0;
3022
3023 if (val > dev_priv->rps.min_freq_softlimit)
3024 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3025 if (val < dev_priv->rps.max_freq_softlimit)
3026 mask |= GEN6_PM_RP_UP_THRESHOLD;
3027
3028 /* IVB and SNB hard hangs on looping batchbuffer
3029 * if GEN6_PM_UP_EI_EXPIRED is masked.
3030 */
3031 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3032 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3033
3034 return ~mask;
3035}
3036
b8a5ff8d
JM		 3037/* gen6_set_rps is called to update the frequency request, but should also be
3038 * called when the range (min_delay and max_delay) is modified so that we can
3039 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3040void gen6_set_rps(struct drm_device *dev, u8 val)
3041{
3042 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3043
4fc688ce 3044 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3045 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3046 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3047
eb64cad1
CW		 3048 /* min/max delay may still have been modified so be sure to
3049 * write the limits value.
3050 */
3051 if (val != dev_priv->rps.cur_freq) {
3052 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3053
eb64cad1
CW		 3054 if (IS_HASWELL(dev))
3055 I915_WRITE(GEN6_RPNSWREQ,
3056 HSW_FREQUENCY(val));
3057 else
3058 I915_WRITE(GEN6_RPNSWREQ,
3059 GEN6_FREQUENCY(val) |
3060 GEN6_OFFSET(0) |
3061 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3062 }
7b9e0ae6 3063
7b9e0ae6
CW		 3064 /* Make sure we continue to get interrupts
3065 * until we hit the minimum or maximum frequencies.
3066 */
eb64cad1 3067 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3068 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3069
d5570a72
BW		 3070 POSTING_READ(GEN6_RPNSWREQ);
3071
b39fb297 3072 dev_priv->rps.cur_freq = val;
be2cde9a 3073 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3074}
3075
76c3552f
D		 3076/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3077 *
3078 * * If Gfx is Idle, then
3079 * 1. Mask Turbo interrupts
3080 * 2. Bring up Gfx clock
3081 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3082 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3083 * 5. Unmask Turbo interrupts
3084*/
3085static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3086{
3087 /*
3088 * When we are idle. Drop to min voltage state.
3089 */
3090
b39fb297 3091 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3092 return;
3093
3094 /* Mask turbo interrupt so that they will not come in between */
3095 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3096
3097 /* Bring up the Gfx clock */
3098 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3099 I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
3100 VLV_GFX_CLK_FORCE_ON_BIT);
3101
3102 if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
3103 I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
3104 DRM_ERROR("GFX_CLK_ON request timed out\n");
3105 return;
3106 }
3107
b39fb297 3108 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3109
3110 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3111 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3112
3113 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3114 & GENFREQSTATUS) == 0, 5))
3115 DRM_ERROR("timed out waiting for Punit\n");
3116
3117 /* Release the Gfx clock */
3118 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3119 I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
3120 ~VLV_GFX_CLK_FORCE_ON_BIT);
3121
2876ce73
CW		 3122 I915_WRITE(GEN6_PMINTRMSK,
3123 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3124}
3125
b29c19b6
CW		 3126void gen6_rps_idle(struct drm_i915_private *dev_priv)
3127{
691bb717
DL		 3128 struct drm_device *dev = dev_priv->dev;
3129
b29c19b6 3130 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3131 if (dev_priv->rps.enabled) {
691bb717 3132 if (IS_VALLEYVIEW(dev))
76c3552f 3133 vlv_set_rps_idle(dev_priv);
c0951f0c 3134 else
b39fb297 3135 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3136 dev_priv->rps.last_adj = 0;
3137 }
b29c19b6
CW		 3138 mutex_unlock(&dev_priv->rps.hw_lock);
3139}
3140
3141void gen6_rps_boost(struct drm_i915_private *dev_priv)
3142{
691bb717
DL		 3143 struct drm_device *dev = dev_priv->dev;
3144
b29c19b6 3145 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3146 if (dev_priv->rps.enabled) {
691bb717 3147 if (IS_VALLEYVIEW(dev))
b39fb297 3148 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3149 else
b39fb297 3150 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3151 dev_priv->rps.last_adj = 0;
3152 }
b29c19b6
CW		 3153 mutex_unlock(&dev_priv->rps.hw_lock);
3154}
3155
0a073b84
JB		 3156void valleyview_set_rps(struct drm_device *dev, u8 val)
3157{
3158 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3159
0a073b84 3160 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3161 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3162 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3163
73008b98 3164 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3165 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3166 dev_priv->rps.cur_freq,
2ec3815f 3167 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3168
2876ce73
CW		 3169 if (val != dev_priv->rps.cur_freq)
3170 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3171
09c87db8 3172 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3173
b39fb297 3174 dev_priv->rps.cur_freq = val;
2ec3815f 3175 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3176}
3177
44fc7d5c 3178static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3179{
3180 struct drm_i915_private *dev_priv = dev->dev_private;
3181
2b4e57bd 3182 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3183 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3184 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3185 /* Complete PM interrupt masking here doesn't race with the rps work
3186 * item again unmasking PM interrupts because that is using a different
3187 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3188 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3189
59cdb63d 3190 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3191 dev_priv->rps.pm_iir = 0;
59cdb63d 3192 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3193
a6706b45 3194 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3195}
3196
44fc7d5c 3197static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3198{
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200
3201 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3202 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3203
44fc7d5c
DV		 3204 gen6_disable_rps_interrupts(dev);
3205}
3206
3207static void valleyview_disable_rps(struct drm_device *dev)
3208{
3209 struct drm_i915_private *dev_priv = dev->dev_private;
3210
3211 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3212
44fc7d5c 3213 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3214}
3215
dc39fff7
BW		 3216static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3217{
dc39fff7 3218 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1c79b42f
BW		 3219 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3220 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3221 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3222}
3223
2b4e57bd
ED		 3224int intel_enable_rc6(const struct drm_device *dev)
3225{
eb4926e4
DL		 3226 /* No RC6 before Ironlake */
3227 if (INTEL_INFO(dev)->gen < 5)
3228 return 0;
3229
456470eb 3230 /* Respect the kernel parameter if it is set */
d330a953
JN		 3231 if (i915.enable_rc6 >= 0)
3232 return i915.enable_rc6;
2b4e57bd 3233
6567d748
CW		 3234 /* Disable RC6 on Ironlake */
3235 if (INTEL_INFO(dev)->gen == 5)
3236 return 0;
2b4e57bd 3237
8bade1ad 3238 if (IS_IVYBRIDGE(dev))
cca84a1f 3239 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3240
3241 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3242}
3243
44fc7d5c
DV		 3244static void gen6_enable_rps_interrupts(struct drm_device *dev)
3245{
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247
3248 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3249 WARN_ON(dev_priv->rps.pm_iir);
a6706b45
D		 3250 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3251 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3252 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3253}
3254
6edee7f3
BW		 3255static void gen8_enable_rps(struct drm_device *dev)
3256{
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct intel_ring_buffer *ring;
3259 uint32_t rc6_mask = 0, rp_state_cap;
3260 int unused;
3261
3262 /* 1a: Software RC state - RC0 */
3263 I915_WRITE(GEN6_RC_STATE, 0);
3264
3265 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3266 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3267 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3268
3269 /* 2a: Disable RC states. */
3270 I915_WRITE(GEN6_RC_CONTROL, 0);
3271
3272 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3273
3274 /* 2b: Program RC6 thresholds.*/
3275 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3276 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3277 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3278 for_each_ring(ring, dev_priv, unused)
3279 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3280 I915_WRITE(GEN6_RC_SLEEP, 0);
3281 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3282
3283 /* 3: Enable RC6 */
3284 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3285 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3286 intel_print_rc6_info(dev, rc6_mask);
6edee7f3 3287 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
abbf9d2c
BW		 3288 GEN6_RC_CTL_EI_MODE(1) |
3289 rc6_mask);
6edee7f3
BW		 3290
3291 /* 4 Program defaults and thresholds for RPS*/
3292 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3293 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3294 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3295 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3296
3297 /* Docs recommend 900MHz, and 300 MHz respectively */
3298 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3299 dev_priv->rps.max_freq_softlimit << 24 |
3300 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3301
3302 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3303 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3304 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3305 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3306
3307 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3308
3309 /* 5: Enable RPS */
3310 I915_WRITE(GEN6_RP_CONTROL,
3311 GEN6_RP_MEDIA_TURBO |
3312 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3313 GEN6_RP_MEDIA_IS_GFX |
3314 GEN6_RP_ENABLE |
3315 GEN6_RP_UP_BUSY_AVG |
3316 GEN6_RP_DOWN_IDLE_AVG);
3317
3318 /* 6: Ring frequency + overclocking (our driver does this later */
3319
3320 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3321
3322 gen6_enable_rps_interrupts(dev);
3323
c8d9a590 3324 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3325}
3326
79f5b2c7 3327static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3328{
79f5b2c7 3329 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3330 struct intel_ring_buffer *ring;
2a5913a8 3331 u32 rp_state_cap;
7b9e0ae6 3332 u32 gt_perf_status;
d060c169 3333 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3334 u32 gtfifodbg;
2b4e57bd 3335 int rc6_mode;
42c0526c 3336 int i, ret;
2b4e57bd 3337
4fc688ce 3338 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3339
2b4e57bd
ED		 3340 /* Here begins a magic sequence of register writes to enable
3341 * auto-downclocking.
3342 *
3343 * Perhaps there might be some value in exposing these to
3344 * userspace...
3345 */
3346 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3347
3348 /* Clear the DBG now so we don't confuse earlier errors */
3349 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3350 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3351 I915_WRITE(GTFIFODBG, gtfifodbg);
3352 }
3353
c8d9a590 3354 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3355
7b9e0ae6
CW		 3356 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3357 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3358
b39fb297 3359 /* All of these values are in units of 50MHz */
2a5913a8 3360 dev_priv->rps.cur_freq = 0;
b39fb297 3361 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
2a5913a8
BW		 3362 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3363 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3364 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3365 /* XXX: only BYT has a special efficient freq */
3366 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3367 /* hw_max = RP0 until we check for overclocking */
3368 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
7b9e0ae6 3369
dd0a1aa1 3370 /* Preserve min/max settings in case of re-init */
b39fb297 3371 if (dev_priv->rps.max_freq_softlimit == 0)
2a5913a8 3372 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
dd0a1aa1 3373
b39fb297 3374 if (dev_priv->rps.min_freq_softlimit == 0)
2a5913a8 3375 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
dd0a1aa1 3376
2b4e57bd
ED		 3377 /* disable the counters and set deterministic thresholds */
3378 I915_WRITE(GEN6_RC_CONTROL, 0);
3379
3380 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3381 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3382 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3383 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3384 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3385
b4519513
CW		 3386 for_each_ring(ring, dev_priv, i)
3387 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3388
3389 I915_WRITE(GEN6_RC_SLEEP, 0);
3390 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3391 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3392 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3393 else
3394 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3395 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3396 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3397
5a7dc92a 3398 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3399 rc6_mode = intel_enable_rc6(dev_priv->dev);
3400 if (rc6_mode & INTEL_RC6_ENABLE)
3401 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3402
5a7dc92a
ED		 3403 /* We don't use those on Haswell */
3404 if (!IS_HASWELL(dev)) {
3405 if (rc6_mode & INTEL_RC6p_ENABLE)
3406 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3407
5a7dc92a
ED		 3408 if (rc6_mode & INTEL_RC6pp_ENABLE)
3409 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3410 }
2b4e57bd 3411
dc39fff7 3412 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3413
3414 I915_WRITE(GEN6_RC_CONTROL,
3415 rc6_mask |
3416 GEN6_RC_CTL_EI_MODE(1) |
3417 GEN6_RC_CTL_HW_ENABLE);
3418
dd75fdc8
CW		 3419 /* Power down if completely idle for over 50ms */
3420 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3421 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3422
42c0526c 3423 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3424 if (ret)
42c0526c 3425 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3426
3427 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3428 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3429 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3430 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3431 (pcu_mbox & 0xff) * 50);
b39fb297 3432 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3433 }
3434
dd75fdc8 3435 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3436 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3437
44fc7d5c 3438 gen6_enable_rps_interrupts(dev);
2b4e57bd 3439
31643d54
BW		 3440 rc6vids = 0;
3441 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3442 if (IS_GEN6(dev) && ret) {
3443 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3444 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3445 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3446 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3447 rc6vids &= 0xffff00;
3448 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3449 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3450 if (ret)
3451 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3452 }
3453
c8d9a590 3454 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3455}
3456
c67a470b 3457void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3458{
79f5b2c7 3459 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3460 int min_freq = 15;
3ebecd07
CW		 3461 unsigned int gpu_freq;
3462 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3463 int scaling_factor = 180;
eda79642 3464 struct cpufreq_policy *policy;
2b4e57bd 3465
4fc688ce 3466 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3467
eda79642
BW		 3468 policy = cpufreq_cpu_get(0);
3469 if (policy) {
3470 max_ia_freq = policy->cpuinfo.max_freq;
3471 cpufreq_cpu_put(policy);
3472 } else {
3473 /*
3474 * Default to measured freq if none found, PCU will ensure we
3475 * don't go over
3476 */
2b4e57bd 3477 max_ia_freq = tsc_khz;
eda79642 3478 }
2b4e57bd
ED		 3479
3480 /* Convert from kHz to MHz */
3481 max_ia_freq /= 1000;
3482
153b4b95 3483 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3484 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3485 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3486
2b4e57bd
ED		 3487 /*
3488 * For each potential GPU frequency, load a ring frequency we'd like
3489 * to use for memory access. We do this by specifying the IA frequency
3490 * the PCU should use as a reference to determine the ring frequency.
3491 */
b39fb297 3492 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3493 gpu_freq--) {
b39fb297 3494 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3495 unsigned int ia_freq = 0, ring_freq = 0;
3496
46c764d4
BW		 3497 if (INTEL_INFO(dev)->gen >= 8) {
3498 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3499 ring_freq = max(min_ring_freq, gpu_freq);
3500 } else if (IS_HASWELL(dev)) {
f6aca45c 3501 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3502 ring_freq = max(min_ring_freq, ring_freq);
3503 /* leave ia_freq as the default, chosen by cpufreq */
3504 } else {
3505 /* On older processors, there is no separate ring
3506 * clock domain, so in order to boost the bandwidth
3507 * of the ring, we need to upclock the CPU (ia_freq).
3508 *
3509 * For GPU frequencies less than 750MHz,
3510 * just use the lowest ring freq.
3511 */
3512 if (gpu_freq < min_freq)
3513 ia_freq = 800;
3514 else
3515 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3516 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3517 }
2b4e57bd 3518
42c0526c
BW		 3519 sandybridge_pcode_write(dev_priv,
3520 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3521 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3522 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3523 gpu_freq);
2b4e57bd 3524 }
2b4e57bd
ED		 3525}
3526
0a073b84
JB		 3527int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3528{
3529 u32 val, rp0;
3530
64936258 3531 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3532
3533 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3534 /* Clamp to max */
3535 rp0 = min_t(u32, rp0, 0xea);
3536
3537 return rp0;
3538}
3539
3540static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3541{
3542 u32 val, rpe;
3543
64936258 3544 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3545 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3546 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3547 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3548
3549 return rpe;
3550}
3551
3552int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3553{
64936258 3554 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3555}
3556
ae48434c
ID		 3557/* Check that the pctx buffer wasn't move under us. */
3558static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3559{
3560 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3561
3562 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3563 dev_priv->vlv_pctx->stolen->start);
3564}
3565
c9cddffc
JB		 3566static void valleyview_setup_pctx(struct drm_device *dev)
3567{
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569 struct drm_i915_gem_object *pctx;
3570 unsigned long pctx_paddr;
3571 u32 pcbr;
3572 int pctx_size = 24*1024;
3573
17b0c1f7
ID		 3574 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3575
c9cddffc
JB		 3576 pcbr = I915_READ(VLV_PCBR);
3577 if (pcbr) {
3578 /* BIOS set it up already, grab the pre-alloc'd space */
3579 int pcbr_offset;
3580
3581 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3582 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3583 pcbr_offset,
190d6cd5 3584 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3585 pctx_size);
3586 goto out;
3587 }
3588
3589 /*
3590 * From the Gunit register HAS:
3591 * The Gfx driver is expected to program this register and ensure
3592 * proper allocation within Gfx stolen memory. For example, this
3593 * register should be programmed such than the PCBR range does not
3594 * overlap with other ranges, such as the frame buffer, protected
3595 * memory, or any other relevant ranges.
3596 */
3597 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3598 if (!pctx) {
3599 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3600 return;
3601 }
3602
3603 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3604 I915_WRITE(VLV_PCBR, pctx_paddr);
3605
3606out:
3607 dev_priv->vlv_pctx = pctx;
3608}
3609
ae48434c
ID		 3610static void valleyview_cleanup_pctx(struct drm_device *dev)
3611{
3612 struct drm_i915_private *dev_priv = dev->dev_private;
3613
3614 if (WARN_ON(!dev_priv->vlv_pctx))
3615 return;
3616
3617 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3618 dev_priv->vlv_pctx = NULL;
3619}
3620
0a073b84
JB		 3621static void valleyview_enable_rps(struct drm_device *dev)
3622{
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_ring_buffer *ring;
2a5913a8 3625 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3626 int i;
3627
3628 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3629
ae48434c
ID		 3630 valleyview_check_pctx(dev_priv);
3631
0a073b84 3632 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3633 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3634 gtfifodbg);
0a073b84
JB		 3635 I915_WRITE(GTFIFODBG, gtfifodbg);
3636 }
3637
c8d9a590
D		 3638 /* If VLV, Forcewake all wells, else re-direct to regular path */
3639 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3640
3641 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3642 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3643 I915_WRITE(GEN6_RP_UP_EI, 66000);
3644 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3645
3646 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3647
3648 I915_WRITE(GEN6_RP_CONTROL,
3649 GEN6_RP_MEDIA_TURBO |
3650 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3651 GEN6_RP_MEDIA_IS_GFX |
3652 GEN6_RP_ENABLE |
3653 GEN6_RP_UP_BUSY_AVG |
3654 GEN6_RP_DOWN_IDLE_CONT);
3655
3656 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3657 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3658 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3659
3660 for_each_ring(ring, dev_priv, i)
3661 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3662
2f0aa304 3663 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 3664
3665 /* allows RC6 residency counter to work */
49798eb2
JB		 3666 I915_WRITE(VLV_COUNTER_CONTROL,
3667 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3668 VLV_MEDIA_RC6_COUNT_EN |
3669 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 3670 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 3671 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 3672
3673 intel_print_rc6_info(dev, rc6_mode);
3674
a2b23fe0 3675 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3676
64936258 3677 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3678
3679 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3680 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3681
b39fb297 3682 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 3683 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 3684 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3685 dev_priv->rps.cur_freq);
0a073b84 3686
2a5913a8
BW		 3687 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3688 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
73008b98 3689 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
2a5913a8
BW		 3690 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3691 dev_priv->rps.max_freq);
0a073b84 3692
b39fb297 3693 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
73008b98 3694 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
b39fb297
BW		 3695 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3696 dev_priv->rps.efficient_freq);
0a073b84 3697
2a5913a8 3698 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
73008b98 3699 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
2a5913a8
BW		 3700 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3701 dev_priv->rps.min_freq);
dd0a1aa1
JM		 3702
3703 /* Preserve min/max settings in case of re-init */
b39fb297 3704 if (dev_priv->rps.max_freq_softlimit == 0)
2a5913a8 3705 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
dd0a1aa1 3706
b39fb297 3707 if (dev_priv->rps.min_freq_softlimit == 0)
2a5913a8 3708 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
0a073b84 3709
73008b98 3710 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 3711 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3712 dev_priv->rps.efficient_freq);
0a073b84 3713
b39fb297 3714 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 3715
44fc7d5c 3716 gen6_enable_rps_interrupts(dev);
0a073b84 3717
c8d9a590 3718 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3719}
3720
930ebb46 3721void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3722{
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724
3e373948 3725 if (dev_priv->ips.renderctx) {
d7f46fc4 3726 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 3727 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3728 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3729 }
3730
3e373948 3731 if (dev_priv->ips.pwrctx) {
d7f46fc4 3732 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 3733 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3734 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3735 }
3736}
3737
930ebb46 3738static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3739{
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741
3742 if (I915_READ(PWRCTXA)) {
3743 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3744 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3745 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3746 50);
3747
3748 I915_WRITE(PWRCTXA, 0);
3749 POSTING_READ(PWRCTXA);
3750
3751 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3752 POSTING_READ(RSTDBYCTL);
3753 }
2b4e57bd
ED		 3754}
3755
3756static int ironlake_setup_rc6(struct drm_device *dev)
3757{
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759
3e373948
DV		 3760 if (dev_priv->ips.renderctx == NULL)
3761 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3762 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3763 return -ENOMEM;
3764
3e373948
DV		 3765 if (dev_priv->ips.pwrctx == NULL)
3766 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3767 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3768 ironlake_teardown_rc6(dev);
3769 return -ENOMEM;
3770 }
3771
3772 return 0;
3773}
3774
930ebb46 3775static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3776{
3777 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3778 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3779 bool was_interruptible;
2b4e57bd
ED		 3780 int ret;
3781
3782 /* rc6 disabled by default due to repeated reports of hanging during
3783 * boot and resume.
3784 */
3785 if (!intel_enable_rc6(dev))
3786 return;
3787
79f5b2c7
DV		 3788 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3789
2b4e57bd 3790 ret = ironlake_setup_rc6(dev);
79f5b2c7 3791 if (ret)
2b4e57bd 3792 return;
2b4e57bd 3793
3e960501
CW		 3794 was_interruptible = dev_priv->mm.interruptible;
3795 dev_priv->mm.interruptible = false;
3796
2b4e57bd
ED		 3797 /*
3798 * GPU can automatically power down the render unit if given a page
3799 * to save state.
3800 */
6d90c952 3801 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3802 if (ret) {
3803 ironlake_teardown_rc6(dev);
3e960501 3804 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3805 return;
3806 }
3807
6d90c952
DV		 3808 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3809 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3810 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3811 MI_MM_SPACE_GTT |
3812 MI_SAVE_EXT_STATE_EN |
3813 MI_RESTORE_EXT_STATE_EN |
3814 MI_RESTORE_INHIBIT);
3815 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3816 intel_ring_emit(ring, MI_NOOP);
3817 intel_ring_emit(ring, MI_FLUSH);
3818 intel_ring_advance(ring);
2b4e57bd
ED		 3819
3820 /*
3821 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3822 * does an implicit flush, combined with MI_FLUSH above, it should be
3823 * safe to assume that renderctx is valid
3824 */
3e960501
CW		 3825 ret = intel_ring_idle(ring);
3826 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3827 if (ret) {
def27a58 3828 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3829 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3830 return;
3831 }
3832
f343c5f6 3833 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3834 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 3835
3836 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 3837}
3838
dde18883
ED		 3839static unsigned long intel_pxfreq(u32 vidfreq)
3840{
3841 unsigned long freq;
3842 int div = (vidfreq & 0x3f0000) >> 16;
3843 int post = (vidfreq & 0x3000) >> 12;
3844 int pre = (vidfreq & 0x7);
3845
3846 if (!pre)
3847 return 0;
3848
3849 freq = ((div * 133333) / ((1<<post) * pre));
3850
3851 return freq;
3852}
3853
eb48eb00
DV		 3854static const struct cparams {
3855 u16 i;
3856 u16 t;
3857 u16 m;
3858 u16 c;
3859} cparams[] = {
3860 { 1, 1333, 301, 28664 },
3861 { 1, 1066, 294, 24460 },
3862 { 1, 800, 294, 25192 },
3863 { 0, 1333, 276, 27605 },
3864 { 0, 1066, 276, 27605 },
3865 { 0, 800, 231, 23784 },
3866};
3867
f531dcb2 3868static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3869{
3870 u64 total_count, diff, ret;
3871 u32 count1, count2, count3, m = 0, c = 0;
3872 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3873 int i;
3874
02d71956
DV		 3875 assert_spin_locked(&mchdev_lock);
3876
20e4d407 3877 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3878
3879 /* Prevent division-by-zero if we are asking too fast.
3880 * Also, we don't get interesting results if we are polling
3881 * faster than once in 10ms, so just return the saved value
3882 * in such cases.
3883 */
3884 if (diff1 <= 10)
20e4d407 3885 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3886
3887 count1 = I915_READ(DMIEC);
3888 count2 = I915_READ(DDREC);
3889 count3 = I915_READ(CSIEC);
3890
3891 total_count = count1 + count2 + count3;
3892
3893 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3894 if (total_count < dev_priv->ips.last_count1) {
3895 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3896 diff += total_count;
3897 } else {
20e4d407 3898 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3899 }
3900
3901 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3902 if (cparams[i].i == dev_priv->ips.c_m &&
3903 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3904 m = cparams[i].m;
3905 c = cparams[i].c;
3906 break;
3907 }
3908 }
3909
3910 diff = div_u64(diff, diff1);
3911 ret = ((m * diff) + c);
3912 ret = div_u64(ret, 10);
3913
20e4d407
DV		 3914 dev_priv->ips.last_count1 = total_count;
3915 dev_priv->ips.last_time1 = now;
eb48eb00 3916
20e4d407 3917 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3918
3919 return ret;
3920}
3921
f531dcb2
CW		 3922unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3923{
3d13ef2e 3924 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 3925 unsigned long val;
3926
3d13ef2e 3927 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 3928 return 0;
3929
3930 spin_lock_irq(&mchdev_lock);
3931
3932 val = __i915_chipset_val(dev_priv);
3933
3934 spin_unlock_irq(&mchdev_lock);
3935
3936 return val;
3937}
3938
eb48eb00
DV		 3939unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3940{
3941 unsigned long m, x, b;
3942 u32 tsfs;
3943
3944 tsfs = I915_READ(TSFS);
3945
3946 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3947 x = I915_READ8(TR1);
3948
3949 b = tsfs & TSFS_INTR_MASK;
3950
3951 return ((m * x) / 127) - b;
3952}
3953
3954static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3955{
3d13ef2e 3956 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 3957 static const struct v_table {
3958 u16 vd; /* in .1 mil */
3959 u16 vm; /* in .1 mil */
3960 } v_table[] = {
3961 { 0, 0, },
3962 { 375, 0, },
3963 { 500, 0, },
3964 { 625, 0, },
3965 { 750, 0, },
3966 { 875, 0, },
3967 { 1000, 0, },
3968 { 1125, 0, },
3969 { 4125, 3000, },
3970 { 4125, 3000, },
3971 { 4125, 3000, },
3972 { 4125, 3000, },
3973 { 4125, 3000, },
3974 { 4125, 3000, },
3975 { 4125, 3000, },
3976 { 4125, 3000, },
3977 { 4125, 3000, },
3978 { 4125, 3000, },
3979 { 4125, 3000, },
3980 { 4125, 3000, },
3981 { 4125, 3000, },
3982 { 4125, 3000, },
3983 { 4125, 3000, },
3984 { 4125, 3000, },
3985 { 4125, 3000, },
3986 { 4125, 3000, },
3987 { 4125, 3000, },
3988 { 4125, 3000, },
3989 { 4125, 3000, },
3990 { 4125, 3000, },
3991 { 4125, 3000, },
3992 { 4125, 3000, },
3993 { 4250, 3125, },
3994 { 4375, 3250, },
3995 { 4500, 3375, },
3996 { 4625, 3500, },
3997 { 4750, 3625, },
3998 { 4875, 3750, },
3999 { 5000, 3875, },
4000 { 5125, 4000, },
4001 { 5250, 4125, },
4002 { 5375, 4250, },
4003 { 5500, 4375, },
4004 { 5625, 4500, },
4005 { 5750, 4625, },
4006 { 5875, 4750, },
4007 { 6000, 4875, },
4008 { 6125, 5000, },
4009 { 6250, 5125, },
4010 { 6375, 5250, },
4011 { 6500, 5375, },
4012 { 6625, 5500, },
4013 { 6750, 5625, },
4014 { 6875, 5750, },
4015 { 7000, 5875, },
4016 { 7125, 6000, },
4017 { 7250, 6125, },
4018 { 7375, 6250, },
4019 { 7500, 6375, },
4020 { 7625, 6500, },
4021 { 7750, 6625, },
4022 { 7875, 6750, },
4023 { 8000, 6875, },
4024 { 8125, 7000, },
4025 { 8250, 7125, },
4026 { 8375, 7250, },
4027 { 8500, 7375, },
4028 { 8625, 7500, },
4029 { 8750, 7625, },
4030 { 8875, 7750, },
4031 { 9000, 7875, },
4032 { 9125, 8000, },
4033 { 9250, 8125, },
4034 { 9375, 8250, },
4035 { 9500, 8375, },
4036 { 9625, 8500, },
4037 { 9750, 8625, },
4038 { 9875, 8750, },
4039 { 10000, 8875, },
4040 { 10125, 9000, },
4041 { 10250, 9125, },
4042 { 10375, 9250, },
4043 { 10500, 9375, },
4044 { 10625, 9500, },
4045 { 10750, 9625, },
4046 { 10875, 9750, },
4047 { 11000, 9875, },
4048 { 11125, 10000, },
4049 { 11250, 10125, },
4050 { 11375, 10250, },
4051 { 11500, 10375, },
4052 { 11625, 10500, },
4053 { 11750, 10625, },
4054 { 11875, 10750, },
4055 { 12000, 10875, },
4056 { 12125, 11000, },
4057 { 12250, 11125, },
4058 { 12375, 11250, },
4059 { 12500, 11375, },
4060 { 12625, 11500, },
4061 { 12750, 11625, },
4062 { 12875, 11750, },
4063 { 13000, 11875, },
4064 { 13125, 12000, },
4065 { 13250, 12125, },
4066 { 13375, 12250, },
4067 { 13500, 12375, },
4068 { 13625, 12500, },
4069 { 13750, 12625, },
4070 { 13875, 12750, },
4071 { 14000, 12875, },
4072 { 14125, 13000, },
4073 { 14250, 13125, },
4074 { 14375, 13250, },
4075 { 14500, 13375, },
4076 { 14625, 13500, },
4077 { 14750, 13625, },
4078 { 14875, 13750, },
4079 { 15000, 13875, },
4080 { 15125, 14000, },
4081 { 15250, 14125, },
4082 { 15375, 14250, },
4083 { 15500, 14375, },
4084 { 15625, 14500, },
4085 { 15750, 14625, },
4086 { 15875, 14750, },
4087 { 16000, 14875, },
4088 { 16125, 15000, },
4089 };
3d13ef2e 4090 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4091 return v_table[pxvid].vm;
4092 else
4093 return v_table[pxvid].vd;
4094}
4095
02d71956 4096static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4097{
4098 struct timespec now, diff1;
4099 u64 diff;
4100 unsigned long diffms;
4101 u32 count;
4102
02d71956 4103 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4104
4105 getrawmonotonic(&now);
20e4d407 4106 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4107
4108 /* Don't divide by 0 */
4109 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4110 if (!diffms)
4111 return;
4112
4113 count = I915_READ(GFXEC);
4114
20e4d407
DV		 4115 if (count < dev_priv->ips.last_count2) {
4116 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4117 diff += count;
4118 } else {
20e4d407 4119 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4120 }
4121
20e4d407
DV		 4122 dev_priv->ips.last_count2 = count;
4123 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4124
4125 /* More magic constants... */
4126 diff = diff * 1181;
4127 diff = div_u64(diff, diffms * 10);
20e4d407 4128 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4129}
4130
02d71956
DV		 4131void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4132{
3d13ef2e
DL		 4133 struct drm_device *dev = dev_priv->dev;
4134
4135 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4136 return;
4137
9270388e 4138 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4139
4140 __i915_update_gfx_val(dev_priv);
4141
9270388e 4142 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4143}
4144
f531dcb2 4145static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4146{
4147 unsigned long t, corr, state1, corr2, state2;
4148 u32 pxvid, ext_v;
4149
02d71956
DV		 4150 assert_spin_locked(&mchdev_lock);
4151
b39fb297 4152 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4153 pxvid = (pxvid >> 24) & 0x7f;
4154 ext_v = pvid_to_extvid(dev_priv, pxvid);
4155
4156 state1 = ext_v;
4157
4158 t = i915_mch_val(dev_priv);
4159
4160 /* Revel in the empirically derived constants */
4161
4162 /* Correction factor in 1/100000 units */
4163 if (t > 80)
4164 corr = ((t * 2349) + 135940);
4165 else if (t >= 50)
4166 corr = ((t * 964) + 29317);
4167 else /* < 50 */
4168 corr = ((t * 301) + 1004);
4169
4170 corr = corr * ((150142 * state1) / 10000 - 78642);
4171 corr /= 100000;
20e4d407 4172 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4173
4174 state2 = (corr2 * state1) / 10000;
4175 state2 /= 100; /* convert to mW */
4176
02d71956 4177 __i915_update_gfx_val(dev_priv);
eb48eb00 4178
20e4d407 4179 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4180}
4181
f531dcb2
CW		 4182unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4183{
3d13ef2e 4184 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4185 unsigned long val;
4186
3d13ef2e 4187 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4188 return 0;
4189
4190 spin_lock_irq(&mchdev_lock);
4191
4192 val = __i915_gfx_val(dev_priv);
4193
4194 spin_unlock_irq(&mchdev_lock);
4195
4196 return val;
4197}
4198
eb48eb00
DV		 4199/**
4200 * i915_read_mch_val - return value for IPS use
4201 *
4202 * Calculate and return a value for the IPS driver to use when deciding whether
4203 * we have thermal and power headroom to increase CPU or GPU power budget.
4204 */
4205unsigned long i915_read_mch_val(void)
4206{
4207 struct drm_i915_private *dev_priv;
4208 unsigned long chipset_val, graphics_val, ret = 0;
4209
9270388e 4210 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4211 if (!i915_mch_dev)
4212 goto out_unlock;
4213 dev_priv = i915_mch_dev;
4214
f531dcb2
CW		 4215 chipset_val = __i915_chipset_val(dev_priv);
4216 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4217
4218 ret = chipset_val + graphics_val;
4219
4220out_unlock:
9270388e 4221 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4222
4223 return ret;
4224}
4225EXPORT_SYMBOL_GPL(i915_read_mch_val);
4226
4227/**
4228 * i915_gpu_raise - raise GPU frequency limit
4229 *
4230 * Raise the limit; IPS indicates we have thermal headroom.
4231 */
4232bool i915_gpu_raise(void)
4233{
4234 struct drm_i915_private *dev_priv;
4235 bool ret = true;
4236
9270388e 4237 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4238 if (!i915_mch_dev) {
4239 ret = false;
4240 goto out_unlock;
4241 }
4242 dev_priv = i915_mch_dev;
4243
20e4d407
DV		 4244 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4245 dev_priv->ips.max_delay--;
eb48eb00
DV		 4246
4247out_unlock:
9270388e 4248 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4249
4250 return ret;
4251}
4252EXPORT_SYMBOL_GPL(i915_gpu_raise);
4253
4254/**
4255 * i915_gpu_lower - lower GPU frequency limit
4256 *
4257 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4258 * frequency maximum.
4259 */
4260bool i915_gpu_lower(void)
4261{
4262 struct drm_i915_private *dev_priv;
4263 bool ret = true;
4264
9270388e 4265 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4266 if (!i915_mch_dev) {
4267 ret = false;
4268 goto out_unlock;
4269 }
4270 dev_priv = i915_mch_dev;
4271
20e4d407
DV		 4272 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4273 dev_priv->ips.max_delay++;
eb48eb00
DV		 4274
4275out_unlock:
9270388e 4276 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4277
4278 return ret;
4279}
4280EXPORT_SYMBOL_GPL(i915_gpu_lower);
4281
4282/**
4283 * i915_gpu_busy - indicate GPU business to IPS
4284 *
4285 * Tell the IPS driver whether or not the GPU is busy.
4286 */
4287bool i915_gpu_busy(void)
4288{
4289 struct drm_i915_private *dev_priv;
f047e395 4290 struct intel_ring_buffer *ring;
eb48eb00 4291 bool ret = false;
f047e395 4292 int i;
eb48eb00 4293
9270388e 4294 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4295 if (!i915_mch_dev)
4296 goto out_unlock;
4297 dev_priv = i915_mch_dev;
4298
f047e395
CW		 4299 for_each_ring(ring, dev_priv, i)
4300 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4301
4302out_unlock:
9270388e 4303 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4304
4305 return ret;
4306}
4307EXPORT_SYMBOL_GPL(i915_gpu_busy);
4308
4309/**
4310 * i915_gpu_turbo_disable - disable graphics turbo
4311 *
4312 * Disable graphics turbo by resetting the max frequency and setting the
4313 * current frequency to the default.
4314 */
4315bool i915_gpu_turbo_disable(void)
4316{
4317 struct drm_i915_private *dev_priv;
4318 bool ret = true;
4319
9270388e 4320 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4321 if (!i915_mch_dev) {
4322 ret = false;
4323 goto out_unlock;
4324 }
4325 dev_priv = i915_mch_dev;
4326
20e4d407 4327 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4328
20e4d407 4329 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4330 ret = false;
4331
4332out_unlock:
9270388e 4333 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4334
4335 return ret;
4336}
4337EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4338
4339/**
4340 * Tells the intel_ips driver that the i915 driver is now loaded, if
4341 * IPS got loaded first.
4342 *
4343 * This awkward dance is so that neither module has to depend on the
4344 * other in order for IPS to do the appropriate communication of
4345 * GPU turbo limits to i915.
4346 */
4347static void
4348ips_ping_for_i915_load(void)
4349{
4350 void (*link)(void);
4351
4352 link = symbol_get(ips_link_to_i915_driver);
4353 if (link) {
4354 link();
4355 symbol_put(ips_link_to_i915_driver);
4356 }
4357}
4358
4359void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4360{
02d71956
DV		 4361 /* We only register the i915 ips part with intel-ips once everything is
4362 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4363 spin_lock_irq(&mchdev_lock);
eb48eb00 4364 i915_mch_dev = dev_priv;
9270388e 4365 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4366
4367 ips_ping_for_i915_load();
4368}
4369
4370void intel_gpu_ips_teardown(void)
4371{
9270388e 4372 spin_lock_irq(&mchdev_lock);
eb48eb00 4373 i915_mch_dev = NULL;
9270388e 4374 spin_unlock_irq(&mchdev_lock);
eb48eb00 4375}
76c3552f 4376
8090c6b9 4377static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4378{
4379 struct drm_i915_private *dev_priv = dev->dev_private;
4380 u32 lcfuse;
4381 u8 pxw[16];
4382 int i;
4383
4384 /* Disable to program */
4385 I915_WRITE(ECR, 0);
4386 POSTING_READ(ECR);
4387
4388 /* Program energy weights for various events */
4389 I915_WRITE(SDEW, 0x15040d00);
4390 I915_WRITE(CSIEW0, 0x007f0000);
4391 I915_WRITE(CSIEW1, 0x1e220004);
4392 I915_WRITE(CSIEW2, 0x04000004);
4393
4394 for (i = 0; i < 5; i++)
4395 I915_WRITE(PEW + (i * 4), 0);
4396 for (i = 0; i < 3; i++)
4397 I915_WRITE(DEW + (i * 4), 0);
4398
4399 /* Program P-state weights to account for frequency power adjustment */
4400 for (i = 0; i < 16; i++) {
4401 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4402 unsigned long freq = intel_pxfreq(pxvidfreq);
4403 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4404 PXVFREQ_PX_SHIFT;
4405 unsigned long val;
4406
4407 val = vid * vid;
4408 val *= (freq / 1000);
4409 val *= 255;
4410 val /= (127*127*900);
4411 if (val > 0xff)
4412 DRM_ERROR("bad pxval: %ld\n", val);
4413 pxw[i] = val;
4414 }
4415 /* Render standby states get 0 weight */
4416 pxw[14] = 0;
4417 pxw[15] = 0;
4418
4419 for (i = 0; i < 4; i++) {
4420 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4421 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4422 I915_WRITE(PXW + (i * 4), val);
4423 }
4424
4425 /* Adjust magic regs to magic values (more experimental results) */
4426 I915_WRITE(OGW0, 0);
4427 I915_WRITE(OGW1, 0);
4428 I915_WRITE(EG0, 0x00007f00);
4429 I915_WRITE(EG1, 0x0000000e);
4430 I915_WRITE(EG2, 0x000e0000);
4431 I915_WRITE(EG3, 0x68000300);
4432 I915_WRITE(EG4, 0x42000000);
4433 I915_WRITE(EG5, 0x00140031);
4434 I915_WRITE(EG6, 0);
4435 I915_WRITE(EG7, 0);
4436
4437 for (i = 0; i < 8; i++)
4438 I915_WRITE(PXWL + (i * 4), 0);
4439
4440 /* Enable PMON + select events */
4441 I915_WRITE(ECR, 0x80000019);
4442
4443 lcfuse = I915_READ(LCFUSE02);
4444
20e4d407 4445 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4446}
4447
ae48434c
ID		 4448void intel_init_gt_powersave(struct drm_device *dev)
4449{
4450 if (IS_VALLEYVIEW(dev))
4451 valleyview_setup_pctx(dev);
4452}
4453
4454void intel_cleanup_gt_powersave(struct drm_device *dev)
4455{
4456 if (IS_VALLEYVIEW(dev))
4457 valleyview_cleanup_pctx(dev);
4458}
4459
8090c6b9
DV		 4460void intel_disable_gt_powersave(struct drm_device *dev)
4461{
1a01ab3b
JB		 4462 struct drm_i915_private *dev_priv = dev->dev_private;
4463
fd0c0642
DV		 4464 /* Interrupts should be disabled already to avoid re-arming. */
4465 WARN_ON(dev->irq_enabled);
4466
930ebb46 4467 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4468 ironlake_disable_drps(dev);
930ebb46 4469 ironlake_disable_rc6(dev);
0a073b84 4470 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4471 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4472 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4473 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4474 if (IS_VALLEYVIEW(dev))
4475 valleyview_disable_rps(dev);
4476 else
4477 gen6_disable_rps(dev);
c0951f0c 4478 dev_priv->rps.enabled = false;
4fc688ce 4479 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4480 }
8090c6b9
DV		 4481}
4482
1a01ab3b
JB		 4483static void intel_gen6_powersave_work(struct work_struct *work)
4484{
4485 struct drm_i915_private *dev_priv =
4486 container_of(work, struct drm_i915_private,
4487 rps.delayed_resume_work.work);
4488 struct drm_device *dev = dev_priv->dev;
4489
4fc688ce 4490 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4491
4492 if (IS_VALLEYVIEW(dev)) {
4493 valleyview_enable_rps(dev);
6edee7f3
BW		 4494 } else if (IS_BROADWELL(dev)) {
4495 gen8_enable_rps(dev);
4496 gen6_update_ring_freq(dev);
0a073b84
JB		 4497 } else {
4498 gen6_enable_rps(dev);
4499 gen6_update_ring_freq(dev);
4500 }
c0951f0c 4501 dev_priv->rps.enabled = true;
4fc688ce 4502 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4503}
4504
8090c6b9
DV		 4505void intel_enable_gt_powersave(struct drm_device *dev)
4506{
1a01ab3b
JB		 4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508
8090c6b9
DV		 4509 if (IS_IRONLAKE_M(dev)) {
4510 ironlake_enable_drps(dev);
4511 ironlake_enable_rc6(dev);
4512 intel_init_emon(dev);
0a073b84 4513 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4514 /*
4515 * PCU communication is slow and this doesn't need to be
4516 * done at any specific time, so do this out of our fast path
4517 * to make resume and init faster.
4518 */
4519 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4520 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4521 }
4522}
4523
3107bd48
DV		 4524static void ibx_init_clock_gating(struct drm_device *dev)
4525{
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527
4528 /*
4529 * On Ibex Peak and Cougar Point, we need to disable clock
4530 * gating for the panel power sequencer or it will fail to
4531 * start up when no ports are active.
4532 */
4533 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4534}
4535
0e088b8f
VS		 4536static void g4x_disable_trickle_feed(struct drm_device *dev)
4537{
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 int pipe;
4540
4541 for_each_pipe(pipe) {
4542 I915_WRITE(DSPCNTR(pipe),
4543 I915_READ(DSPCNTR(pipe)) |
4544 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4545 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4546 }
4547}
4548
017636cc
VS		 4549static void ilk_init_lp_watermarks(struct drm_device *dev)
4550{
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552
4553 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4554 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4555 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4556
4557 /*
4558 * Don't touch WM1S_LP_EN here.
4559 * Doing so could cause underruns.
4560 */
4561}
4562
1fa61106 4563static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4564{
4565 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4566 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4567
f1e8fa56
DL		 4568 /*
4569 * Required for FBC
4570 * WaFbcDisableDpfcClockGating:ilk
4571 */
4d47e4f5
DL		 4572 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4573 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4574 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4575
4576 I915_WRITE(PCH_3DCGDIS0,
4577 MARIUNIT_CLOCK_GATE_DISABLE |
4578 SVSMUNIT_CLOCK_GATE_DISABLE);
4579 I915_WRITE(PCH_3DCGDIS1,
4580 VFMUNIT_CLOCK_GATE_DISABLE);
4581
6f1d69b0
ED		 4582 /*
4583 * According to the spec the following bits should be set in
4584 * order to enable memory self-refresh
4585 * The bit 22/21 of 0x42004
4586 * The bit 5 of 0x42020
4587 * The bit 15 of 0x45000
4588 */
4589 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4590 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4591 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4592 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4593 I915_WRITE(DISP_ARB_CTL,
4594 (I915_READ(DISP_ARB_CTL) |
4595 DISP_FBC_WM_DIS));
017636cc
VS		 4596
4597 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 4598
4599 /*
4600 * Based on the document from hardware guys the following bits
4601 * should be set unconditionally in order to enable FBC.
4602 * The bit 22 of 0x42000
4603 * The bit 22 of 0x42004
4604 * The bit 7,8,9 of 0x42020.
4605 */
4606 if (IS_IRONLAKE_M(dev)) {
4bb35334 4607 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4608 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4609 I915_READ(ILK_DISPLAY_CHICKEN1) |
4610 ILK_FBCQ_DIS);
4611 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4612 I915_READ(ILK_DISPLAY_CHICKEN2) |
4613 ILK_DPARB_GATE);
6f1d69b0
ED		 4614 }
4615
4d47e4f5
DL		 4616 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4617
6f1d69b0
ED		 4618 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4619 I915_READ(ILK_DISPLAY_CHICKEN2) |
4620 ILK_ELPIN_409_SELECT);
4621 I915_WRITE(_3D_CHICKEN2,
4622 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4623 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4624
ecdb4eb7 4625 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4626 I915_WRITE(CACHE_MODE_0,
4627 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4628
0e088b8f 4629 g4x_disable_trickle_feed(dev);
bdad2b2f 4630
3107bd48
DV		 4631 ibx_init_clock_gating(dev);
4632}
4633
4634static void cpt_init_clock_gating(struct drm_device *dev)
4635{
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 int pipe;
3f704fa2 4638 uint32_t val;
3107bd48
DV		 4639
4640 /*
4641 * On Ibex Peak and Cougar Point, we need to disable clock
4642 * gating for the panel power sequencer or it will fail to
4643 * start up when no ports are active.
4644 */
cd664078
JB		 4645 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4646 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4647 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 4648 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4649 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4650 /* The below fixes the weird display corruption, a few pixels shifted
4651 * downward, on (only) LVDS of some HP laptops with IVY.
4652 */
3f704fa2 4653 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4654 val = I915_READ(TRANS_CHICKEN2(pipe));
4655 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4656 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4657 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4658 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4659 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4660 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4661 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4662 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4663 }
3107bd48
DV		 4664 /* WADP0ClockGatingDisable */
4665 for_each_pipe(pipe) {
4666 I915_WRITE(TRANS_CHICKEN1(pipe),
4667 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4668 }
6f1d69b0
ED		 4669}
4670
1d7aaa0c
DV		 4671static void gen6_check_mch_setup(struct drm_device *dev)
4672{
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674 uint32_t tmp;
4675
4676 tmp = I915_READ(MCH_SSKPD);
4677 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4678 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4679 DRM_INFO("This can cause pipe underruns and display issues.\n");
4680 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4681 }
4682}
4683
1fa61106 4684static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4685{
4686 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4687 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4688
231e54f6 4689 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4690
4691 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4692 I915_READ(ILK_DISPLAY_CHICKEN2) |
4693 ILK_ELPIN_409_SELECT);
4694
ecdb4eb7 4695 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4696 I915_WRITE(_3D_CHICKEN,
4697 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4698
ecdb4eb7 4699 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4700 if (IS_SNB_GT1(dev))
4701 I915_WRITE(GEN6_GT_MODE,
4702 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4703
8d85d272
VS		 4704 /*
4705 * BSpec recoomends 8x4 when MSAA is used,
4706 * however in practice 16x4 seems fastest.
c5c98a58
VS		 4707 *
4708 * Note that PS/WM thread counts depend on the WIZ hashing
4709 * disable bit, which we don't touch here, but it's good
4710 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 4711 */
4712 I915_WRITE(GEN6_GT_MODE,
4713 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4714
017636cc 4715 ilk_init_lp_watermarks(dev);
6f1d69b0 4716
6f1d69b0 4717 I915_WRITE(CACHE_MODE_0,
50743298 4718 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4719
4720 I915_WRITE(GEN6_UCGCTL1,
4721 I915_READ(GEN6_UCGCTL1) |
4722 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4723 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4724
4725 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4726 * gating disable must be set. Failure to set it results in
4727 * flickering pixels due to Z write ordering failures after
4728 * some amount of runtime in the Mesa "fire" demo, and Unigine
4729 * Sanctuary and Tropics, and apparently anything else with
4730 * alpha test or pixel discard.
4731 *
4732 * According to the spec, bit 11 (RCCUNIT) must also be set,
4733 * but we didn't debug actual testcases to find it out.
0f846f81 4734 *
ef59318c
VS		 4735 * WaDisableRCCUnitClockGating:snb
4736 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 4737 */
4738 I915_WRITE(GEN6_UCGCTL2,
4739 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4740 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4741
5eb146dd 4742 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 4743 I915_WRITE(_3D_CHICKEN3,
4744 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 4745
e927ecde
VS		 4746 /*
4747 * Bspec says:
4748 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4749 * 3DSTATE_SF number of SF output attributes is more than 16."
4750 */
4751 I915_WRITE(_3D_CHICKEN3,
4752 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4753
6f1d69b0
ED		 4754 /*
4755 * According to the spec the following bits should be
4756 * set in order to enable memory self-refresh and fbc:
4757 * The bit21 and bit22 of 0x42000
4758 * The bit21 and bit22 of 0x42004
4759 * The bit5 and bit7 of 0x42020
4760 * The bit14 of 0x70180
4761 * The bit14 of 0x71180
4bb35334
DL		 4762 *
4763 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4764 */
4765 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4766 I915_READ(ILK_DISPLAY_CHICKEN1) |
4767 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4768 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4769 I915_READ(ILK_DISPLAY_CHICKEN2) |
4770 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4771 I915_WRITE(ILK_DSPCLK_GATE_D,
4772 I915_READ(ILK_DSPCLK_GATE_D) |
4773 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4774 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4775
0e088b8f 4776 g4x_disable_trickle_feed(dev);
f8f2ac9a 4777
3107bd48 4778 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4779
4780 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4781}
4782
4783static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4784{
4785 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4786
3aad9059 4787 /*
46680e0a 4788 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 4789 *
4790 * This actually overrides the dispatch
4791 * mode for all thread types.
4792 */
6f1d69b0
ED		 4793 reg &= ~GEN7_FF_SCHED_MASK;
4794 reg |= GEN7_FF_TS_SCHED_HW;
4795 reg |= GEN7_FF_VS_SCHED_HW;
4796 reg |= GEN7_FF_DS_SCHED_HW;
4797
4798 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4799}
4800
17a303ec
PZ		 4801static void lpt_init_clock_gating(struct drm_device *dev)
4802{
4803 struct drm_i915_private *dev_priv = dev->dev_private;
4804
4805 /*
4806 * TODO: this bit should only be enabled when really needed, then
4807 * disabled when not needed anymore in order to save power.
4808 */
4809 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4810 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4811 I915_READ(SOUTH_DSPCLK_GATE_D) |
4812 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4813
4814 /* WADPOClockGatingDisable:hsw */
4815 I915_WRITE(_TRANSA_CHICKEN1,
4816 I915_READ(_TRANSA_CHICKEN1) |
4817 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4818}
4819
7d708ee4
ID		 4820static void lpt_suspend_hw(struct drm_device *dev)
4821{
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823
4824 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4825 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4826
4827 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4828 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4829 }
4830}
4831
1020a5c2
BW		 4832static void gen8_init_clock_gating(struct drm_device *dev)
4833{
4834 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 4835 enum pipe pipe;
1020a5c2
BW		 4836
4837 I915_WRITE(WM3_LP_ILK, 0);
4838 I915_WRITE(WM2_LP_ILK, 0);
4839 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 4840
4841 /* FIXME(BDW): Check all the w/a, some might only apply to
4842 * pre-production hw. */
4843
c8966e10
KG		 4844 /* WaDisablePartialInstShootdown:bdw */
4845 I915_WRITE(GEN8_ROW_CHICKEN,
4846 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4847
1411e6a5
KG		 4848 /* WaDisableThreadStallDopClockGating:bdw */
4849 /* FIXME: Unclear whether we really need this on production bdw. */
4850 I915_WRITE(GEN8_ROW_CHICKEN,
4851 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
4852
4167e32c
DL		 4853 /*
4854 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4855 * pre-production hardware
4856 */
fd392b60
BW		 4857 I915_WRITE(HALF_SLICE_CHICKEN3,
4858 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 4859 I915_WRITE(HALF_SLICE_CHICKEN3,
4860 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 4861 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4862
7f88da0c
BW		 4863 I915_WRITE(_3D_CHICKEN3,
4864 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4865
a75f3628
BW		 4866 I915_WRITE(COMMON_SLICE_CHICKEN2,
4867 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4868
4c2e7a5f
BW		 4869 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4870 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4871
ab57fff1 4872 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 4873 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 4874
ab57fff1 4875 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4876 I915_WRITE(CHICKEN_PAR1_1,
4877 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4878
ab57fff1 4879 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 4880 for_each_pipe(pipe) {
4881 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 4882 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 4883 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 4884 }
63801f21
BW		 4885
4886 /* Use Force Non-Coherent whenever executing a 3D context. This is a
4887 * workaround for for a possible hang in the unlikely event a TLB
4888 * invalidation occurs during a PSD flush.
4889 */
4890 I915_WRITE(HDC_CHICKEN0,
4891 I915_READ(HDC_CHICKEN0) |
4892 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 4893
4894 /* WaVSRefCountFullforceMissDisable:bdw */
4895 /* WaDSRefCountFullforceMissDisable:bdw */
4896 I915_WRITE(GEN7_FF_THREAD_MODE,
4897 I915_READ(GEN7_FF_THREAD_MODE) &
4898 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 4899
4900 /*
4901 * BSpec recommends 8x4 when MSAA is used,
4902 * however in practice 16x4 seems fastest.
c5c98a58
VS		 4903 *
4904 * Note that PS/WM thread counts depend on the WIZ hashing
4905 * disable bit, which we don't touch here, but it's good
4906 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 4907 */
4908 I915_WRITE(GEN7_GT_MODE,
4909 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 4910
4911 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
4912 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 4913
4914 /* WaDisableSDEUnitClockGating:bdw */
4915 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
4916 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 4917
4918 /* Wa4x4STCOptimizationDisable:bdw */
4919 I915_WRITE(CACHE_MODE_1,
4920 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 4921}
4922
cad2a2d7
ED		 4923static void haswell_init_clock_gating(struct drm_device *dev)
4924{
4925 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 4926
017636cc 4927 ilk_init_lp_watermarks(dev);
cad2a2d7 4928
f3fc4884
FJ		 4929 /* L3 caching of data atomics doesn't work -- disable it. */
4930 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4931 I915_WRITE(HSW_ROW_CHICKEN3,
4932 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4933
ecdb4eb7 4934 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4935 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4936 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4937 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4938
e36ea7ff
VS		 4939 /* WaVSRefCountFullforceMissDisable:hsw */
4940 I915_WRITE(GEN7_FF_THREAD_MODE,
4941 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 4942
fe27c606
CW		 4943 /* enable HiZ Raw Stall Optimization */
4944 I915_WRITE(CACHE_MODE_0_GEN7,
4945 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4946
ecdb4eb7 4947 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4948 I915_WRITE(CACHE_MODE_1,
4949 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4950
a12c4967
VS		 4951 /*
4952 * BSpec recommends 8x4 when MSAA is used,
4953 * however in practice 16x4 seems fastest.
c5c98a58
VS		 4954 *
4955 * Note that PS/WM thread counts depend on the WIZ hashing
4956 * disable bit, which we don't touch here, but it's good
4957 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 4958 */
4959 I915_WRITE(GEN7_GT_MODE,
4960 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4961
ecdb4eb7 4962 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4963 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4964
90a88643
PZ		 4965 /* WaRsPkgCStateDisplayPMReq:hsw */
4966 I915_WRITE(CHICKEN_PAR1_1,
4967 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4968
17a303ec 4969 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4970}
4971
1fa61106 4972static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4973{
4974 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4975 uint32_t snpcr;
6f1d69b0 4976
017636cc 4977 ilk_init_lp_watermarks(dev);
6f1d69b0 4978
231e54f6 4979 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4980
ecdb4eb7 4981 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4982 I915_WRITE(_3D_CHICKEN3,
4983 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4984
ecdb4eb7 4985 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4986 I915_WRITE(IVB_CHICKEN3,
4987 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4988 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4989
ecdb4eb7 4990 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4991 if (IS_IVB_GT1(dev))
4992 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4993 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4994
ecdb4eb7 4995 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4996 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4997 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4998
ecdb4eb7 4999 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5000 I915_WRITE(GEN7_L3CNTLREG1,
5001 GEN7_WA_FOR_GEN7_L3_CONTROL);
5002 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5003 GEN7_WA_L3_CHICKEN_MODE);
5004 if (IS_IVB_GT1(dev))
5005 I915_WRITE(GEN7_ROW_CHICKEN2,
5006 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5007 else {
5008 /* must write both registers */
5009 I915_WRITE(GEN7_ROW_CHICKEN2,
5010 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5011 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5012 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5013 }
6f1d69b0 5014
ecdb4eb7 5015 /* WaForceL3Serialization:ivb */
61939d97
JB		 5016 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5017 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5018
1b80a19a 5019 /*
0f846f81 5020 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5021 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5022 */
5023 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5024 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5025
ecdb4eb7 5026 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5027 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5028 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5029 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5030
0e088b8f 5031 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5032
5033 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5034
22721343
CW		 5035 if (0) { /* causes HiZ corruption on ivb:gt1 */
5036 /* enable HiZ Raw Stall Optimization */
5037 I915_WRITE(CACHE_MODE_0_GEN7,
5038 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5039 }
116f2b6d 5040
ecdb4eb7 5041 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5042 I915_WRITE(CACHE_MODE_1,
5043 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5044
a607c1a4
VS		 5045 /*
5046 * BSpec recommends 8x4 when MSAA is used,
5047 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5048 *
5049 * Note that PS/WM thread counts depend on the WIZ hashing
5050 * disable bit, which we don't touch here, but it's good
5051 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5052 */
5053 I915_WRITE(GEN7_GT_MODE,
5054 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5055
20848223
BW		 5056 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5057 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5058 snpcr |= GEN6_MBC_SNPCR_MED;
5059 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5060
ab5c608b
BW		 5061 if (!HAS_PCH_NOP(dev))
5062 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5063
5064 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5065}
5066
1fa61106 5067static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5068{
5069 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5070 u32 val;
5071
5072 mutex_lock(&dev_priv->rps.hw_lock);
5073 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5074 mutex_unlock(&dev_priv->rps.hw_lock);
5075 switch ((val >> 6) & 3) {
5076 case 0:
f64a28a7 5077 case 1:
f6d51948 5078 dev_priv->mem_freq = 800;
85b1d7b3 5079 break;
f64a28a7 5080 case 2:
f6d51948 5081 dev_priv->mem_freq = 1066;
85b1d7b3 5082 break;
f64a28a7 5083 case 3:
2325991e 5084 dev_priv->mem_freq = 1333;
f64a28a7 5085 break;
85b1d7b3
JB		 5086 }
5087 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5088
d7fe0cc0 5089 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5090
ecdb4eb7 5091 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5092 I915_WRITE(_3D_CHICKEN3,
5093 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5094
ecdb4eb7 5095 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5096 I915_WRITE(IVB_CHICKEN3,
5097 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5098 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5099
fad7d36e 5100 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5101 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5102 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5103 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5104 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5105
ecdb4eb7 5106 /* WaForceL3Serialization:vlv */
61939d97
JB		 5107 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5108 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5109
ecdb4eb7 5110 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5111 I915_WRITE(GEN7_ROW_CHICKEN2,
5112 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5113
ecdb4eb7 5114 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5115 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5116 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5117 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5118
46680e0a
VS		 5119 gen7_setup_fixed_func_scheduler(dev_priv);
5120
3c0edaeb 5121 /*
0f846f81 5122 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5123 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5124 */
5125 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5126 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5127
c5c32cda 5128 /* WaDisableL3Bank2xClockGate:vlv */
e3f33d46
JB		 5129 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5130
e0d8d59b 5131 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5132
afd58e79
VS		 5133 /*
5134 * BSpec says this must be set, even though
5135 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5136 */
6b26c86d
DV		 5137 I915_WRITE(CACHE_MODE_1,
5138 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5139
031994ee
VS		 5140 /*
5141 * WaIncreaseL3CreditsForVLVB0:vlv
5142 * This is the hardware default actually.
5143 */
5144 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5145
2d809570 5146 /*
ecdb4eb7 5147 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5148 * Disable clock gating on th GCFG unit to prevent a delay
5149 * in the reporting of vblank events.
5150 */
7a0d1eed 5151 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5152}
5153
1fa61106 5154static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5155{
5156 struct drm_i915_private *dev_priv = dev->dev_private;
5157 uint32_t dspclk_gate;
5158
5159 I915_WRITE(RENCLK_GATE_D1, 0);
5160 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5161 GS_UNIT_CLOCK_GATE_DISABLE |
5162 CL_UNIT_CLOCK_GATE_DISABLE);
5163 I915_WRITE(RAMCLK_GATE_D, 0);
5164 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5165 OVRUNIT_CLOCK_GATE_DISABLE |
5166 OVCUNIT_CLOCK_GATE_DISABLE;
5167 if (IS_GM45(dev))
5168 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5169 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5170
5171 /* WaDisableRenderCachePipelinedFlush */
5172 I915_WRITE(CACHE_MODE_0,
5173 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5174
0e088b8f 5175 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5176}
5177
1fa61106 5178static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5179{
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181
5182 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5183 I915_WRITE(RENCLK_GATE_D2, 0);
5184 I915_WRITE(DSPCLK_GATE_D, 0);
5185 I915_WRITE(RAMCLK_GATE_D, 0);
5186 I915_WRITE16(DEUC, 0);
20f94967
VS		 5187 I915_WRITE(MI_ARB_STATE,
5188 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5189}
5190
1fa61106 5191static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5192{
5193 struct drm_i915_private *dev_priv = dev->dev_private;
5194
5195 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5196 I965_RCC_CLOCK_GATE_DISABLE |
5197 I965_RCPB_CLOCK_GATE_DISABLE |
5198 I965_ISC_CLOCK_GATE_DISABLE |
5199 I965_FBC_CLOCK_GATE_DISABLE);
5200 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5201 I915_WRITE(MI_ARB_STATE,
5202 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5203}
5204
1fa61106 5205static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5206{
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208 u32 dstate = I915_READ(D_STATE);
5209
5210 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5211 DSTATE_DOT_CLOCK_GATING;
5212 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5213
5214 if (IS_PINEVIEW(dev))
5215 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5216
5217 /* IIR "flip pending" means done if this bit is set */
5218 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5219}
5220
1fa61106 5221static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5222{
5223 struct drm_i915_private *dev_priv = dev->dev_private;
5224
5225 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5226}
5227
1fa61106 5228static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5229{
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231
5232 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5233}
5234
6f1d69b0
ED		 5235void intel_init_clock_gating(struct drm_device *dev)
5236{
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238
5239 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5240}
5241
7d708ee4
ID		 5242void intel_suspend_hw(struct drm_device *dev)
5243{
5244 if (HAS_PCH_LPT(dev))
5245 lpt_suspend_hw(dev);
5246}
5247
c1ca727f
ID		 5248#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5249 for (i = 0; \
5250 i < (power_domains)->power_well_count && \
5251 ((power_well) = &(power_domains)->power_wells[i]); \
5252 i++) \
5253 if ((power_well)->domains & (domain_mask))
5254
5255#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5256 for (i = (power_domains)->power_well_count - 1; \
5257 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5258 i--) \
5259 if ((power_well)->domains & (domain_mask))
5260
15d199ea
PZ		 5261/**
5262 * We should only use the power well if we explicitly asked the hardware to
5263 * enable it, so check if it's enabled and also check if we've requested it to
5264 * be enabled.
5265 */
da7e29bd 5266static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5267 struct i915_power_well *power_well)
5268{
c1ca727f
ID		 5269 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5270 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5271}
5272
da7e29bd 5273bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536
ID		 5274 enum intel_display_power_domain domain)
5275{
ddf9c536
ID		 5276 struct i915_power_domains *power_domains;
5277
5278 power_domains = &dev_priv->power_domains;
5279
5280 return power_domains->domain_use_count[domain];
5281}
5282
da7e29bd 5283bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5284 enum intel_display_power_domain domain)
15d199ea 5285{
c1ca727f
ID		 5286 struct i915_power_domains *power_domains;
5287 struct i915_power_well *power_well;
5288 bool is_enabled;
5289 int i;
15d199ea 5290
882244a3
PZ		 5291 if (dev_priv->pm.suspended)
5292 return false;
5293
c1ca727f
ID		 5294 power_domains = &dev_priv->power_domains;
5295
5296 is_enabled = true;
5297
5298 mutex_lock(&power_domains->lock);
5299 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5300 if (power_well->always_on)
5301 continue;
5302
c6cb582e 5303 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
c1ca727f
ID		 5304 is_enabled = false;
5305 break;
5306 }
5307 }
5308 mutex_unlock(&power_domains->lock);
5309
5310 return is_enabled;
15d199ea
PZ		 5311}
5312
93c73e8c
ID		 5313/*
5314 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5315 * when not needed anymore. We have 4 registers that can request the power well
5316 * to be enabled, and it will only be disabled if none of the registers is
5317 * requesting it to be enabled.
5318 */
d5e8fdc8
PZ		 5319static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5320{
5321 struct drm_device *dev = dev_priv->dev;
5322 unsigned long irqflags;
5323
f9dcb0df
PZ		 5324 /*
5325 * After we re-enable the power well, if we touch VGA register 0x3d5
5326 * we'll get unclaimed register interrupts. This stops after we write
5327 * anything to the VGA MSR register. The vgacon module uses this
5328 * register all the time, so if we unbind our driver and, as a
5329 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5330 * console_unlock(). So make here we touch the VGA MSR register, making
5331 * sure vgacon can keep working normally without triggering interrupts
5332 * and error messages.
5333 */
5334 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5335 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5336 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5337
d5e8fdc8
PZ		 5338 if (IS_BROADWELL(dev)) {
5339 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5340 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5341 dev_priv->de_irq_mask[PIPE_B]);
5342 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5343 ~dev_priv->de_irq_mask[PIPE_B] |
5344 GEN8_PIPE_VBLANK);
5345 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5346 dev_priv->de_irq_mask[PIPE_C]);
5347 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5348 ~dev_priv->de_irq_mask[PIPE_C] |
5349 GEN8_PIPE_VBLANK);
5350 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5351 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5352 }
5353}
5354
dd7c0b66
ID		 5355static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5356{
5357 assert_spin_locked(&dev->vbl_lock);
5358
5359 dev->vblank[pipe].last = 0;
5360}
5361
d5e8fdc8
PZ		 5362static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5363{
5364 struct drm_device *dev = dev_priv->dev;
07d27e20 5365 enum pipe pipe;
d5e8fdc8
PZ		 5366 unsigned long irqflags;
5367
5368 /*
5369 * After this, the registers on the pipes that are part of the power
5370 * well will become zero, so we have to adjust our counters according to
5371 * that.
5372 *
5373 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5374 */
5375 spin_lock_irqsave(&dev->vbl_lock, irqflags);
07d27e20
DL		 5376 for_each_pipe(pipe)
5377 if (pipe != PIPE_A)
dd7c0b66 5378 reset_vblank_counter(dev, pipe);
d5e8fdc8
PZ		 5379 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5380}
5381
da7e29bd 5382static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 5383 struct i915_power_well *power_well, bool enable)
d0d3e513 5384{
fa42e23c
PZ		 5385 bool is_enabled, enable_requested;
5386 uint32_t tmp;
d0d3e513 5387
fa42e23c 5388 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5389 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5390 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5391
fa42e23c
PZ		 5392 if (enable) {
5393 if (!enable_requested)
6aedd1f5
PZ		 5394 I915_WRITE(HSW_PWR_WELL_DRIVER,
5395 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5396
fa42e23c
PZ		 5397 if (!is_enabled) {
5398 DRM_DEBUG_KMS("Enabling power well\n");
5399 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5400 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5401 DRM_ERROR("Timeout enabling power well\n");
5402 }
596cc11e 5403
d5e8fdc8 5404 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5405 } else {
5406 if (enable_requested) {
5407 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5408 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5409 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5410
d5e8fdc8 5411 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5412 }
5413 }
fa42e23c 5414}
d0d3e513 5415
c6cb582e
ID		 5416static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5417 struct i915_power_well *power_well)
5418{
5419 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5420
5421 /*
5422 * We're taking over the BIOS, so clear any requests made by it since
5423 * the driver is in charge now.
5424 */
5425 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5426 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5427}
5428
5429static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5430 struct i915_power_well *power_well)
5431{
c6cb582e
ID		 5432 hsw_set_power_well(dev_priv, power_well, true);
5433}
5434
5435static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5436 struct i915_power_well *power_well)
5437{
5438 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 5439}
5440
a45f4466
ID		 5441static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5442 struct i915_power_well *power_well)
5443{
5444}
5445
5446static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5447 struct i915_power_well *power_well)
5448{
5449 return true;
5450}
5451
77961eb9
ID		 5452static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5453 struct i915_power_well *power_well, bool enable)
5454{
5455 enum punit_power_well power_well_id = power_well->data;
5456 u32 mask;
5457 u32 state;
5458 u32 ctrl;
5459
5460 mask = PUNIT_PWRGT_MASK(power_well_id);
5461 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5462 PUNIT_PWRGT_PWR_GATE(power_well_id);
5463
5464 mutex_lock(&dev_priv->rps.hw_lock);
5465
5466#define COND \
5467 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5468
5469 if (COND)
5470 goto out;
5471
5472 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5473 ctrl &= ~mask;
5474 ctrl |= state;
5475 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5476
5477 if (wait_for(COND, 100))
5478 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5479 state,
5480 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5481
5482#undef COND
5483
5484out:
5485 mutex_unlock(&dev_priv->rps.hw_lock);
5486}
5487
5488static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5489 struct i915_power_well *power_well)
5490{
5491 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5492}
5493
5494static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5495 struct i915_power_well *power_well)
5496{
5497 vlv_set_power_well(dev_priv, power_well, true);
5498}
5499
5500static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5501 struct i915_power_well *power_well)
5502{
5503 vlv_set_power_well(dev_priv, power_well, false);
5504}
5505
5506static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5507 struct i915_power_well *power_well)
5508{
5509 int power_well_id = power_well->data;
5510 bool enabled = false;
5511 u32 mask;
5512 u32 state;
5513 u32 ctrl;
5514
5515 mask = PUNIT_PWRGT_MASK(power_well_id);
5516 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5517
5518 mutex_lock(&dev_priv->rps.hw_lock);
5519
5520 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5521 /*
5522 * We only ever set the power-on and power-gate states, anything
5523 * else is unexpected.
5524 */
5525 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5526 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5527 if (state == ctrl)
5528 enabled = true;
5529
5530 /*
5531 * A transient state at this point would mean some unexpected party
5532 * is poking at the power controls too.
5533 */
5534 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5535 WARN_ON(ctrl != state);
5536
5537 mutex_unlock(&dev_priv->rps.hw_lock);
5538
5539 return enabled;
5540}
5541
5542static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5543 struct i915_power_well *power_well)
5544{
5545 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5546
5547 vlv_set_power_well(dev_priv, power_well, true);
5548
5549 spin_lock_irq(&dev_priv->irq_lock);
5550 valleyview_enable_display_irqs(dev_priv);
5551 spin_unlock_irq(&dev_priv->irq_lock);
5552
5553 /*
5554 * During driver initialization we need to defer enabling hotplug
5555 * processing until fbdev is set up.
5556 */
5557 if (dev_priv->enable_hotplug_processing)
5558 intel_hpd_init(dev_priv->dev);
5559
5560 i915_redisable_vga_power_on(dev_priv->dev);
5561}
5562
5563static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5564 struct i915_power_well *power_well)
5565{
5566 struct drm_device *dev = dev_priv->dev;
5567 enum pipe pipe;
5568
5569 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5570
5571 spin_lock_irq(&dev_priv->irq_lock);
5572 for_each_pipe(pipe)
5573 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5574
5575 valleyview_disable_display_irqs(dev_priv);
5576 spin_unlock_irq(&dev_priv->irq_lock);
5577
5578 spin_lock_irq(&dev->vbl_lock);
5579 for_each_pipe(pipe)
5580 reset_vblank_counter(dev, pipe);
5581 spin_unlock_irq(&dev->vbl_lock);
5582
5583 vlv_set_power_well(dev_priv, power_well, false);
5584}
5585
25eaa003
ID		 5586static void check_power_well_state(struct drm_i915_private *dev_priv,
5587 struct i915_power_well *power_well)
5588{
5589 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5590
5591 if (power_well->always_on || !i915.disable_power_well) {
5592 if (!enabled)
5593 goto mismatch;
5594
5595 return;
5596 }
5597
5598 if (enabled != (power_well->count > 0))
5599 goto mismatch;
5600
5601 return;
5602
5603mismatch:
5604 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5605 power_well->name, power_well->always_on, enabled,
5606 power_well->count, i915.disable_power_well);
5607}
5608
da7e29bd 5609void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 5610 enum intel_display_power_domain domain)
5611{
83c00f55 5612 struct i915_power_domains *power_domains;
c1ca727f
ID		 5613 struct i915_power_well *power_well;
5614 int i;
6765625e 5615
9e6ea71a
PZ		 5616 intel_runtime_pm_get(dev_priv);
5617
83c00f55
ID		 5618 power_domains = &dev_priv->power_domains;
5619
5620 mutex_lock(&power_domains->lock);
1da51581 5621
25eaa003
ID		 5622 for_each_power_well(i, power_well, BIT(domain), power_domains) {
5623 if (!power_well->count++) {
5624 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 5625 power_well->ops->enable(dev_priv, power_well);
25eaa003
ID		 5626 }
5627
5628 check_power_well_state(dev_priv, power_well);
5629 }
1da51581 5630
ddf9c536
ID		 5631 power_domains->domain_use_count[domain]++;
5632
83c00f55 5633 mutex_unlock(&power_domains->lock);
6765625e
VS		 5634}
5635
da7e29bd 5636void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 5637 enum intel_display_power_domain domain)
5638{
83c00f55 5639 struct i915_power_domains *power_domains;
c1ca727f
ID		 5640 struct i915_power_well *power_well;
5641 int i;
6765625e 5642
83c00f55
ID		 5643 power_domains = &dev_priv->power_domains;
5644
5645 mutex_lock(&power_domains->lock);
1da51581 5646
1da51581
ID		 5647 WARN_ON(!power_domains->domain_use_count[domain]);
5648 power_domains->domain_use_count[domain]--;
ddf9c536 5649
70bf407c
ID		 5650 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5651 WARN_ON(!power_well->count);
5652
25eaa003
ID		 5653 if (!--power_well->count && i915.disable_power_well) {
5654 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
c6cb582e 5655 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 5656 }
5657
5658 check_power_well_state(dev_priv, power_well);
70bf407c 5659 }
1da51581 5660
83c00f55 5661 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 5662
5663 intel_runtime_pm_put(dev_priv);
6765625e
VS		 5664}
5665
83c00f55 5666static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5667
5668/* Display audio driver power well request */
5669void i915_request_power_well(void)
5670{
b4ed4484
ID		 5671 struct drm_i915_private *dev_priv;
5672
a38911a3
WX		 5673 if (WARN_ON(!hsw_pwr))
5674 return;
5675
b4ed4484
ID		 5676 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5677 power_domains);
da7e29bd 5678 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5679}
5680EXPORT_SYMBOL_GPL(i915_request_power_well);
5681
5682/* Display audio driver power well release */
5683void i915_release_power_well(void)
5684{
b4ed4484
ID		 5685 struct drm_i915_private *dev_priv;
5686
a38911a3
WX		 5687 if (WARN_ON(!hsw_pwr))
5688 return;
5689
b4ed4484
ID		 5690 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5691 power_domains);
da7e29bd 5692 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5693}
5694EXPORT_SYMBOL_GPL(i915_release_power_well);
5695
efcad917
ID		 5696#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5697
5698#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
5699 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 5700 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 5701 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
5702 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
5703 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5704 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5705 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5706 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5707 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
5708 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
5709 BIT(POWER_DOMAIN_PORT_CRT) | \
f5938f36 5710 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 5711#define HSW_DISPLAY_POWER_DOMAINS ( \
5712 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
5713 BIT(POWER_DOMAIN_INIT))
5714
5715#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
5716 HSW_ALWAYS_ON_POWER_DOMAINS | \
5717 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5718#define BDW_DISPLAY_POWER_DOMAINS ( \
5719 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
5720 BIT(POWER_DOMAIN_INIT))
5721
77961eb9
ID		 5722#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
5723#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
5724
5725#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
5726 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5727 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5728 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5729 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5730 BIT(POWER_DOMAIN_PORT_CRT) | \
5731 BIT(POWER_DOMAIN_INIT))
5732
5733#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
5734 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5735 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5736 BIT(POWER_DOMAIN_INIT))
5737
5738#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
5739 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5740 BIT(POWER_DOMAIN_INIT))
5741
5742#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
5743 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5744 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5745 BIT(POWER_DOMAIN_INIT))
5746
5747#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
5748 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5749 BIT(POWER_DOMAIN_INIT))
5750
a45f4466
ID		 5751static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5752 .sync_hw = i9xx_always_on_power_well_noop,
5753 .enable = i9xx_always_on_power_well_noop,
5754 .disable = i9xx_always_on_power_well_noop,
5755 .is_enabled = i9xx_always_on_power_well_enabled,
5756};
c6cb582e 5757
1c2256df
ID		 5758static struct i915_power_well i9xx_always_on_power_well[] = {
5759 {
5760 .name = "always-on",
5761 .always_on = 1,
5762 .domains = POWER_DOMAIN_MASK,
c6cb582e 5763 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 5764 },
5765};
5766
c6cb582e
ID		 5767static const struct i915_power_well_ops hsw_power_well_ops = {
5768 .sync_hw = hsw_power_well_sync_hw,
5769 .enable = hsw_power_well_enable,
5770 .disable = hsw_power_well_disable,
5771 .is_enabled = hsw_power_well_enabled,
5772};
5773
c1ca727f 5774static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5775 {
5776 .name = "always-on",
5777 .always_on = 1,
5778 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 5779 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 5780 },
c1ca727f
ID		 5781 {
5782 .name = "display",
efcad917 5783 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 5784 .ops = &hsw_power_well_ops,
c1ca727f
ID		 5785 },
5786};
5787
5788static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5789 {
5790 .name = "always-on",
5791 .always_on = 1,
5792 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 5793 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 5794 },
c1ca727f
ID		 5795 {
5796 .name = "display",
efcad917 5797 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 5798 .ops = &hsw_power_well_ops,
c1ca727f
ID		 5799 },
5800};
5801
77961eb9
ID		 5802static const struct i915_power_well_ops vlv_display_power_well_ops = {
5803 .sync_hw = vlv_power_well_sync_hw,
5804 .enable = vlv_display_power_well_enable,
5805 .disable = vlv_display_power_well_disable,
5806 .is_enabled = vlv_power_well_enabled,
5807};
5808
5809static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
5810 .sync_hw = vlv_power_well_sync_hw,
5811 .enable = vlv_power_well_enable,
5812 .disable = vlv_power_well_disable,
5813 .is_enabled = vlv_power_well_enabled,
5814};
5815
5816static struct i915_power_well vlv_power_wells[] = {
5817 {
5818 .name = "always-on",
5819 .always_on = 1,
5820 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
5821 .ops = &i9xx_always_on_power_well_ops,
5822 },
5823 {
5824 .name = "display",
5825 .domains = VLV_DISPLAY_POWER_DOMAINS,
5826 .data = PUNIT_POWER_WELL_DISP2D,
5827 .ops = &vlv_display_power_well_ops,
5828 },
5829 {
5830 .name = "dpio-common",
5831 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
5832 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
5833 .ops = &vlv_dpio_power_well_ops,
5834 },
5835 {
5836 .name = "dpio-tx-b-01",
5837 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5838 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5839 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5840 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5841 .ops = &vlv_dpio_power_well_ops,
5842 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
5843 },
5844 {
5845 .name = "dpio-tx-b-23",
5846 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5847 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5848 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5849 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5850 .ops = &vlv_dpio_power_well_ops,
5851 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
5852 },
5853 {
5854 .name = "dpio-tx-c-01",
5855 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5856 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5857 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5858 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5859 .ops = &vlv_dpio_power_well_ops,
5860 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
5861 },
5862 {
5863 .name = "dpio-tx-c-23",
5864 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5865 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5866 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5867 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5868 .ops = &vlv_dpio_power_well_ops,
5869 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
5870 },
5871};
5872
c1ca727f
ID		 5873#define set_power_wells(power_domains, __power_wells) ({ \
5874 (power_domains)->power_wells = (__power_wells); \
5875 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5876})
5877
da7e29bd 5878int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 5879{
83c00f55 5880 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 5881
83c00f55 5882 mutex_init(&power_domains->lock);
a38911a3 5883
c1ca727f
ID		 5884 /*
5885 * The enabling order will be from lower to higher indexed wells,
5886 * the disabling order is reversed.
5887 */
da7e29bd 5888 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 5889 set_power_wells(power_domains, hsw_power_wells);
5890 hsw_pwr = power_domains;
da7e29bd 5891 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 5892 set_power_wells(power_domains, bdw_power_wells);
5893 hsw_pwr = power_domains;
77961eb9
ID		 5894 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
5895 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 5896 } else {
1c2256df 5897 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 5898 }
a38911a3
WX		 5899
5900 return 0;
5901}
5902
da7e29bd 5903void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 5904{
5905 hsw_pwr = NULL;
5906}
5907
da7e29bd 5908static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 5909{
83c00f55
ID		 5910 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5911 struct i915_power_well *power_well;
c1ca727f 5912 int i;
9cdb826c 5913
83c00f55 5914 mutex_lock(&power_domains->lock);
a45f4466
ID		 5915 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
5916 power_well->ops->sync_hw(dev_priv, power_well);
83c00f55 5917 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5918}
5919
da7e29bd 5920void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 5921{
fa42e23c 5922 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 5923 intel_display_set_init_power(dev_priv, true);
5924 intel_power_domains_resume(dev_priv);
d0d3e513
ED		 5925}
5926
c67a470b
PZ		 5927void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5928{
d361ae26 5929 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 5930}
5931
5932void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5933{
d361ae26 5934 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 5935}
5936
8a187455
PZ		 5937void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5938{
5939 struct drm_device *dev = dev_priv->dev;
5940 struct device *device = &dev->pdev->dev;
5941
5942 if (!HAS_RUNTIME_PM(dev))
5943 return;
5944
5945 pm_runtime_get_sync(device);
5946 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5947}
5948
5949void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5950{
5951 struct drm_device *dev = dev_priv->dev;
5952 struct device *device = &dev->pdev->dev;
5953
5954 if (!HAS_RUNTIME_PM(dev))
5955 return;
5956
5957 pm_runtime_mark_last_busy(device);
5958 pm_runtime_put_autosuspend(device);
5959}
5960
5961void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5962{
5963 struct drm_device *dev = dev_priv->dev;
5964 struct device *device = &dev->pdev->dev;
5965
8a187455
PZ		 5966 if (!HAS_RUNTIME_PM(dev))
5967 return;
5968
5969 pm_runtime_set_active(device);
5970
5971 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5972 pm_runtime_mark_last_busy(device);
5973 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 5974
5975 pm_runtime_put_autosuspend(device);
8a187455
PZ		 5976}
5977
5978void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5979{
5980 struct drm_device *dev = dev_priv->dev;
5981 struct device *device = &dev->pdev->dev;
5982
5983 if (!HAS_RUNTIME_PM(dev))
5984 return;
5985
5986 /* Make sure we're not suspended first. */
5987 pm_runtime_get_sync(device);
5988 pm_runtime_disable(device);
5989}
5990
1fa61106
ED		 5991/* Set up chip specific power management-related functions */
5992void intel_init_pm(struct drm_device *dev)
5993{
5994 struct drm_i915_private *dev_priv = dev->dev_private;
5995
3a77c4c4 5996 if (HAS_FBC(dev)) {
40045465 5997 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 5998 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 5999 dev_priv->display.enable_fbc = gen7_enable_fbc;
6000 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6001 } else if (INTEL_INFO(dev)->gen >= 5) {
6002 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6003 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6004 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6005 } else if (IS_GM45(dev)) {
6006 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6007 dev_priv->display.enable_fbc = g4x_enable_fbc;
6008 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6009 } else {
1fa61106
ED		 6010 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6011 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6012 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6013
6014 /* This value was pulled out of someone's hat */
6015 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6016 }
1fa61106
ED		 6017 }
6018
c921aba8
DV		 6019 /* For cxsr */
6020 if (IS_PINEVIEW(dev))
6021 i915_pineview_get_mem_freq(dev);
6022 else if (IS_GEN5(dev))
6023 i915_ironlake_get_mem_freq(dev);
6024
1fa61106
ED		 6025 /* For FIFO watermark updates */
6026 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6027 ilk_setup_wm_latency(dev);
53615a5e 6028
bd602544
VS		 6029 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6030 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6031 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6032 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6033 dev_priv->display.update_wm = ilk_update_wm;
6034 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6035 } else {
6036 DRM_DEBUG_KMS("Failed to read display plane latency. "
6037 "Disable CxSR\n");
6038 }
6039
6040 if (IS_GEN5(dev))
1fa61106 6041 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6042 else if (IS_GEN6(dev))
1fa61106 6043 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6044 else if (IS_IVYBRIDGE(dev))
1fa61106 6045 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6046 else if (IS_HASWELL(dev))
cad2a2d7 6047 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6048 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 6049 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 6050 } else if (IS_VALLEYVIEW(dev)) {
6051 dev_priv->display.update_wm = valleyview_update_wm;
6052 dev_priv->display.init_clock_gating =
6053 valleyview_init_clock_gating;
1fa61106
ED		 6054 } else if (IS_PINEVIEW(dev)) {
6055 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6056 dev_priv->is_ddr3,
6057 dev_priv->fsb_freq,
6058 dev_priv->mem_freq)) {
6059 DRM_INFO("failed to find known CxSR latency "
6060 "(found ddr%s fsb freq %d, mem freq %d), "
6061 "disabling CxSR\n",
6062 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6063 dev_priv->fsb_freq, dev_priv->mem_freq);
6064 /* Disable CxSR and never update its watermark again */
6065 pineview_disable_cxsr(dev);
6066 dev_priv->display.update_wm = NULL;
6067 } else
6068 dev_priv->display.update_wm = pineview_update_wm;
6069 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6070 } else if (IS_G4X(dev)) {
6071 dev_priv->display.update_wm = g4x_update_wm;
6072 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6073 } else if (IS_GEN4(dev)) {
6074 dev_priv->display.update_wm = i965_update_wm;
6075 if (IS_CRESTLINE(dev))
6076 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6077 else if (IS_BROADWATER(dev))
6078 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6079 } else if (IS_GEN3(dev)) {
6080 dev_priv->display.update_wm = i9xx_update_wm;
6081 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6082 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6083 } else if (IS_GEN2(dev)) {
6084 if (INTEL_INFO(dev)->num_pipes == 1) {
6085 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6086 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6087 } else {
6088 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6089 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6090 }
6091
6092 if (IS_I85X(dev) || IS_I865G(dev))
6093 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6094 else
6095 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6096 } else {
6097 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6098 }
6099}
6100
42c0526c
BW		 6101int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6102{
4fc688ce 6103 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6104
6105 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6106 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6107 return -EAGAIN;
6108 }
6109
6110 I915_WRITE(GEN6_PCODE_DATA, *val);
6111 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6112
6113 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6114 500)) {
6115 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6116 return -ETIMEDOUT;
6117 }
6118
6119 *val = I915_READ(GEN6_PCODE_DATA);
6120 I915_WRITE(GEN6_PCODE_DATA, 0);
6121
6122 return 0;
6123}
6124
6125int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6126{
4fc688ce 6127 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6128
6129 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6130 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6131 return -EAGAIN;
6132 }
6133
6134 I915_WRITE(GEN6_PCODE_DATA, val);
6135 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6136
6137 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6138 500)) {
6139 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6140 return -ETIMEDOUT;
6141 }
6142
6143 I915_WRITE(GEN6_PCODE_DATA, 0);
6144
6145 return 0;
6146}
a0e4e199 6147
2ec3815f 6148int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6149{
07ab118b 6150 int div;
855ba3be 6151
07ab118b 6152 /* 4 x czclk */
2ec3815f 6153 switch (dev_priv->mem_freq) {
855ba3be 6154 case 800:
07ab118b 6155 div = 10;
855ba3be
JB		 6156 break;
6157 case 1066:
07ab118b 6158 div = 12;
855ba3be
JB		 6159 break;
6160 case 1333:
07ab118b 6161 div = 16;
855ba3be
JB		 6162 break;
6163 default:
6164 return -1;
6165 }
6166
2ec3815f 6167 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6168}
6169
2ec3815f 6170int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6171{
07ab118b 6172 int mul;
855ba3be 6173
07ab118b 6174 /* 4 x czclk */
2ec3815f 6175 switch (dev_priv->mem_freq) {
855ba3be 6176 case 800:
07ab118b 6177 mul = 10;
855ba3be
JB		 6178 break;
6179 case 1066:
07ab118b 6180 mul = 12;
855ba3be
JB		 6181 break;
6182 case 1333:
07ab118b 6183 mul = 16;
855ba3be
JB		 6184 break;
6185 default:
6186 return -1;
6187 }
6188
2ec3815f 6189 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6190}
6191
f742a552 6192void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6193{
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195
f742a552
DV		 6196 mutex_init(&dev_priv->rps.hw_lock);
6197
907b28c5
CW		 6198 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6199 intel_gen6_powersave_work);
5d584b2e 6200
33688d95 6201 dev_priv->pm.suspended = false;
5d584b2e 6202 dev_priv->pm.irqs_disabled = false;
907b28c5 6203}
Ubuntu Artful kernel mirror