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drm/i915/chv: Add Cherryview interrupt registers into debugfs
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
7f2cf220 100 int i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
159f9875
VS		 117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
85208be0
ED		 126
127 /* enable it... */
993495ae
VS		 128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
5cd5410e 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 139}
140
1fa61106 141static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146}
147
993495ae 148static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 149{
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 152 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 156 u32 dpfc_ctl;
157
3fa2e0ee
VS		 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 164
85208be0
ED		 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
fe74c1a5 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 169
84f44ce7 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 171}
172
1fa61106 173static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186}
187
1fa61106 188static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193}
194
195static void sandybridge_blit_fbc_update(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
940aece4
D		 201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 205
85208be0
ED		 206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 216
940aece4 217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 218}
219
993495ae 220static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 221{
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 224 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 228 u32 dpfc_ctl;
229
46f3dab9 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee
VS		 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0 238
85208be0 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
84f44ce7 251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 252}
253
1fa61106 254static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267}
268
1fa61106 269static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274}
275
993495ae 276static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 277{
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 280 struct drm_framebuffer *fb = crtc->primary->fb;
abe959c7
RV		 281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 284 u32 dpfc_ctl;
abe959c7 285
3fa2e0ee
VS		 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 294
891348b2 295 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
299 ILK_FBCQ_DIS);
28554164 300 } else {
2adb6db8 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
304 HSW_FBCQ_DIS);
891348b2 305 }
b74ea102 306
abe959c7
RV		 307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
310
311 sandybridge_blit_fbc_update(dev);
312
b19870ee 313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 314}
315
85208be0
ED		 316bool intel_fbc_enabled(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (!dev_priv->display.fbc_enabled)
321 return false;
322
323 return dev_priv->display.fbc_enabled(dev);
324}
325
326static void intel_fbc_work_fn(struct work_struct *__work)
327{
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333
334 mutex_lock(&dev->struct_mutex);
5c3fe8b0 335 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 336 /* Double check that we haven't switched fb without cancelling
337 * the prior work.
338 */
f4510a27 339 if (work->crtc->primary->fb == work->fb) {
993495ae 340 dev_priv->display.enable_fbc(work->crtc);
85208be0 341
5c3fe8b0 342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 344 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 345 }
346
5c3fe8b0 347 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 348 }
349 mutex_unlock(&dev->struct_mutex);
350
351 kfree(work);
352}
353
354static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
355{
5c3fe8b0 356 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 357 return;
358
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
360
361 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 363 * entirely asynchronously.
364 */
5c3fe8b0 365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 366 /* tasklet was killed before being run, clean up */
5c3fe8b0 367 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 368
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
372 * necessary to run.
373 */
5c3fe8b0 374 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 375}
376
993495ae 377static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 378{
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382
383 if (!dev_priv->display.enable_fbc)
384 return;
385
386 intel_cancel_fbc_work(dev_priv);
387
b14c5679 388 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 389 if (work == NULL) {
6cdcb5e7 390 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 391 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 392 return;
393 }
394
395 work->crtc = crtc;
f4510a27 396 work->fb = crtc->primary->fb;
85208be0
ED		 397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
398
5c3fe8b0 399 dev_priv->fbc.fbc_work = work;
85208be0 400
85208be0
ED		 401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
406 *
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
7457d617
DL		 411 *
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 413 */
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
415}
416
417void intel_disable_fbc(struct drm_device *dev)
418{
419 struct drm_i915_private *dev_priv = dev->dev_private;
420
421 intel_cancel_fbc_work(dev_priv);
422
423 if (!dev_priv->display.disable_fbc)
424 return;
425
426 dev_priv->display.disable_fbc(dev);
5c3fe8b0 427 dev_priv->fbc.plane = -1;
85208be0
ED		 428}
429
29ebf90f
CW		 430static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
432{
433 if (dev_priv->fbc.no_fbc_reason == reason)
434 return false;
435
436 dev_priv->fbc.no_fbc_reason = reason;
437 return true;
438}
439
85208be0
ED		 440/**
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
443 *
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
449 * - no dual wide
f85da868 450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 451 *
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
455 * stolen memory.
456 *
457 * We need to enable/disable FBC on a global basis.
458 */
459void intel_update_fbc(struct drm_device *dev)
460{
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
ef644fda 467 const struct drm_display_mode *adjusted_mode;
37327abd 468 unsigned int max_width, max_height;
85208be0 469
3a77c4c4 470 if (!HAS_FBC(dev)) {
29ebf90f 471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 472 return;
29ebf90f 473 }
85208be0 474
d330a953 475 if (!i915.powersave) {
29ebf90f
CW		 476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 478 return;
29ebf90f 479 }
85208be0
ED		 480
481 /*
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
489 */
490 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 491 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 492 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 493 if (crtc) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 496 goto out_disable;
497 }
498 crtc = tmp_crtc;
499 }
500 }
501
f4510a27 502 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 505 goto out_disable;
506 }
507
508 intel_crtc = to_intel_crtc(crtc);
f4510a27 509 fb = crtc->primary->fb;
85208be0
ED		 510 intel_fb = to_intel_framebuffer(fb);
511 obj = intel_fb->obj;
ef644fda 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 513
d330a953 514 if (i915.enable_fbc < 0 &&
8a5729a3 515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 518 goto out_disable;
85208be0 519 }
d330a953 520 if (!i915.enable_fbc) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 523 goto out_disable;
524 }
ef644fda
VS		 525 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
526 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 527 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
529 "disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
f85da868
PZ		 532
533 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 534 max_width = 4096;
535 max_height = 2048;
f85da868 536 } else {
37327abd
VS		 537 max_width = 2048;
538 max_height = 1536;
f85da868 539 }
37327abd
VS		 540 if (intel_crtc->config.pipe_src_w > max_width ||
541 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 544 goto out_disable;
545 }
8f94d24b 546 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 547 intel_crtc->plane != PLANE_A) {
29ebf90f 548 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 550 goto out_disable;
551 }
552
553 /* The use of a CPU fence is mandatory in order to detect writes
554 * by the CPU to the scanout and trigger updates to the FBC.
555 */
556 if (obj->tiling_mode != I915_TILING_X ||
557 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 558 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
559 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 560 goto out_disable;
561 }
562
563 /* If the kernel debugger is active, always disable compression */
564 if (in_dbg_master())
565 goto out_disable;
566
11be49eb 567 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 568 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
569 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 570 goto out_disable;
571 }
572
85208be0
ED		 573 /* If the scanout has not changed, don't modify the FBC settings.
574 * Note that we make the fundamental assumption that the fb->obj
575 * cannot be unpinned (and have its GTT offset and fence revoked)
576 * without first being decoupled from the scanout and FBC disabled.
577 */
5c3fe8b0
BW		 578 if (dev_priv->fbc.plane == intel_crtc->plane &&
579 dev_priv->fbc.fb_id == fb->base.id &&
580 dev_priv->fbc.y == crtc->y)
85208be0
ED		 581 return;
582
583 if (intel_fbc_enabled(dev)) {
584 /* We update FBC along two paths, after changing fb/crtc
585 * configuration (modeswitching) and after page-flipping
586 * finishes. For the latter, we know that not only did
587 * we disable the FBC at the start of the page-flip
588 * sequence, but also more than one vblank has passed.
589 *
590 * For the former case of modeswitching, it is possible
591 * to switch between two FBC valid configurations
592 * instantaneously so we do need to disable the FBC
593 * before we can modify its control registers. We also
594 * have to wait for the next vblank for that to take
595 * effect. However, since we delay enabling FBC we can
596 * assume that a vblank has passed since disabling and
597 * that we can safely alter the registers in the deferred
598 * callback.
599 *
600 * In the scenario that we go from a valid to invalid
601 * and then back to valid FBC configuration we have
602 * no strict enforcement that a vblank occurred since
603 * disabling the FBC. However, along all current pipe
604 * disabling paths we do need to wait for a vblank at
605 * some point. And we wait before enabling FBC anyway.
606 */
607 DRM_DEBUG_KMS("disabling active FBC for update\n");
608 intel_disable_fbc(dev);
609 }
610
993495ae 611 intel_enable_fbc(crtc);
29ebf90f 612 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 613 return;
614
615out_disable:
616 /* Multiple disables should be harmless */
617 if (intel_fbc_enabled(dev)) {
618 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
619 intel_disable_fbc(dev);
620 }
11be49eb 621 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 622}
623
c921aba8
DV		 624static void i915_pineview_get_mem_freq(struct drm_device *dev)
625{
50227e1c 626 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 627 u32 tmp;
628
629 tmp = I915_READ(CLKCFG);
630
631 switch (tmp & CLKCFG_FSB_MASK) {
632 case CLKCFG_FSB_533:
633 dev_priv->fsb_freq = 533; /* 133*4 */
634 break;
635 case CLKCFG_FSB_800:
636 dev_priv->fsb_freq = 800; /* 200*4 */
637 break;
638 case CLKCFG_FSB_667:
639 dev_priv->fsb_freq = 667; /* 167*4 */
640 break;
641 case CLKCFG_FSB_400:
642 dev_priv->fsb_freq = 400; /* 100*4 */
643 break;
644 }
645
646 switch (tmp & CLKCFG_MEM_MASK) {
647 case CLKCFG_MEM_533:
648 dev_priv->mem_freq = 533;
649 break;
650 case CLKCFG_MEM_667:
651 dev_priv->mem_freq = 667;
652 break;
653 case CLKCFG_MEM_800:
654 dev_priv->mem_freq = 800;
655 break;
656 }
657
658 /* detect pineview DDR3 setting */
659 tmp = I915_READ(CSHRDDR3CTL);
660 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
661}
662
663static void i915_ironlake_get_mem_freq(struct drm_device *dev)
664{
50227e1c 665 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 666 u16 ddrpll, csipll;
667
668 ddrpll = I915_READ16(DDRMPLL1);
669 csipll = I915_READ16(CSIPLL0);
670
671 switch (ddrpll & 0xff) {
672 case 0xc:
673 dev_priv->mem_freq = 800;
674 break;
675 case 0x10:
676 dev_priv->mem_freq = 1066;
677 break;
678 case 0x14:
679 dev_priv->mem_freq = 1333;
680 break;
681 case 0x18:
682 dev_priv->mem_freq = 1600;
683 break;
684 default:
685 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
686 ddrpll & 0xff);
687 dev_priv->mem_freq = 0;
688 break;
689 }
690
20e4d407 691 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 692
693 switch (csipll & 0x3ff) {
694 case 0x00c:
695 dev_priv->fsb_freq = 3200;
696 break;
697 case 0x00e:
698 dev_priv->fsb_freq = 3733;
699 break;
700 case 0x010:
701 dev_priv->fsb_freq = 4266;
702 break;
703 case 0x012:
704 dev_priv->fsb_freq = 4800;
705 break;
706 case 0x014:
707 dev_priv->fsb_freq = 5333;
708 break;
709 case 0x016:
710 dev_priv->fsb_freq = 5866;
711 break;
712 case 0x018:
713 dev_priv->fsb_freq = 6400;
714 break;
715 default:
716 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
717 csipll & 0x3ff);
718 dev_priv->fsb_freq = 0;
719 break;
720 }
721
722 if (dev_priv->fsb_freq == 3200) {
20e4d407 723 dev_priv->ips.c_m = 0;
c921aba8 724 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 725 dev_priv->ips.c_m = 1;
c921aba8 726 } else {
20e4d407 727 dev_priv->ips.c_m = 2;
c921aba8
DV		 728 }
729}
730
b445e3b0
ED		 731static const struct cxsr_latency cxsr_latency_table[] = {
732 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
733 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
734 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
735 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
736 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
737
738 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
739 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
740 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
741 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
742 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
743
744 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
745 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
746 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
747 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
748 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
749
750 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
751 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
752 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
753 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
754 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
755
756 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
757 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
758 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
759 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
760 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
761
762 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
763 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
764 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
765 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
766 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
767};
768
63c62275 769static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 770 int is_ddr3,
771 int fsb,
772 int mem)
773{
774 const struct cxsr_latency *latency;
775 int i;
776
777 if (fsb == 0 || mem == 0)
778 return NULL;
779
780 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
781 latency = &cxsr_latency_table[i];
782 if (is_desktop == latency->is_desktop &&
783 is_ddr3 == latency->is_ddr3 &&
784 fsb == latency->fsb_freq && mem == latency->mem_freq)
785 return latency;
786 }
787
788 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
789
790 return NULL;
791}
792
1fa61106 793static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
796
797 /* deactivate cxsr */
798 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
799}
800
801/*
802 * Latency for FIFO fetches is dependent on several factors:
803 * - memory configuration (speed, channels)
804 * - chipset
805 * - current MCH state
806 * It can be fairly high in some situations, so here we assume a fairly
807 * pessimal value. It's a tradeoff between extra memory fetches (if we
808 * set this value too high, the FIFO will fetch frequently to stay full)
809 * and power consumption (set it too low to save power and we might see
810 * FIFO underruns and display "flicker").
811 *
812 * A value of 5us seems to be a good balance; safe for very low end
813 * platforms but not overly aggressive on lower latency configs.
814 */
815static const int latency_ns = 5000;
816
1fa61106 817static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 818{
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 uint32_t dsparb = I915_READ(DSPARB);
821 int size;
822
823 size = dsparb & 0x7f;
824 if (plane)
825 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
826
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
828 plane ? "B" : "A", size);
829
830 return size;
831}
832
feb56b93 833static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 834{
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 uint32_t dsparb = I915_READ(DSPARB);
837 int size;
838
839 size = dsparb & 0x1ff;
840 if (plane)
841 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
842 size >>= 1; /* Convert to cachelines */
843
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
846
847 return size;
848}
849
1fa61106 850static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 uint32_t dsparb = I915_READ(DSPARB);
854 int size;
855
856 size = dsparb & 0x7f;
857 size >>= 2; /* Convert to cachelines */
858
859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
860 plane ? "B" : "A",
861 size);
862
863 return size;
864}
865
b445e3b0
ED		 866/* Pineview has different values for various configs */
867static const struct intel_watermark_params pineview_display_wm = {
868 PINEVIEW_DISPLAY_FIFO,
869 PINEVIEW_MAX_WM,
870 PINEVIEW_DFT_WM,
871 PINEVIEW_GUARD_WM,
872 PINEVIEW_FIFO_LINE_SIZE
873};
874static const struct intel_watermark_params pineview_display_hplloff_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_HPLLOFF_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_cursor_wm = {
882 PINEVIEW_CURSOR_FIFO,
883 PINEVIEW_CURSOR_MAX_WM,
884 PINEVIEW_CURSOR_DFT_WM,
885 PINEVIEW_CURSOR_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE,
887};
888static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params g4x_wm_info = {
896 G4X_FIFO_SIZE,
897 G4X_MAX_WM,
898 G4X_MAX_WM,
899 2,
900 G4X_FIFO_LINE_SIZE,
901};
902static const struct intel_watermark_params g4x_cursor_wm_info = {
903 I965_CURSOR_FIFO,
904 I965_CURSOR_MAX_WM,
905 I965_CURSOR_DFT_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params valleyview_wm_info = {
910 VALLEYVIEW_FIFO_SIZE,
911 VALLEYVIEW_MAX_WM,
912 VALLEYVIEW_MAX_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_cursor_wm_info = {
917 I965_CURSOR_FIFO,
918 VALLEYVIEW_CURSOR_MAX_WM,
919 I965_CURSOR_DFT_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params i965_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 I965_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 I915_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i945_wm_info = {
931 I945_FIFO_SIZE,
932 I915_MAX_WM,
933 1,
934 2,
935 I915_FIFO_LINE_SIZE
936};
937static const struct intel_watermark_params i915_wm_info = {
938 I915_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
feb56b93 944static const struct intel_watermark_params i830_wm_info = {
b445e3b0
ED		 945 I855GM_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I830_FIFO_LINE_SIZE
950};
feb56b93 951static const struct intel_watermark_params i845_wm_info = {
b445e3b0
ED		 952 I830_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958
b445e3b0
ED		 959/**
960 * intel_calculate_wm - calculate watermark level
961 * @clock_in_khz: pixel clock
962 * @wm: chip FIFO params
963 * @pixel_size: display pixel size
964 * @latency_ns: memory latency for the platform
965 *
966 * Calculate the watermark level (the level at which the display plane will
967 * start fetching from memory again). Each chip has a different display
968 * FIFO size and allocation, so the caller needs to figure that out and pass
969 * in the correct intel_watermark_params structure.
970 *
971 * As the pixel clock runs, the FIFO will be drained at a rate that depends
972 * on the pixel size. When it reaches the watermark level, it'll start
973 * fetching FIFO line sized based chunks from memory until the FIFO fills
974 * past the watermark point. If the FIFO drains completely, a FIFO underrun
975 * will occur, and a display engine hang could result.
976 */
977static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
978 const struct intel_watermark_params *wm,
979 int fifo_size,
980 int pixel_size,
981 unsigned long latency_ns)
982{
983 long entries_required, wm_size;
984
985 /*
986 * Note: we need to make sure we don't overflow for various clock &
987 * latency values.
988 * clocks go from a few thousand to several hundred thousand.
989 * latency is usually a few thousand
990 */
991 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
992 1000;
993 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
994
995 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
996
997 wm_size = fifo_size - (entries_required + wm->guard_size);
998
999 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001 /* Don't promote wm_size to unsigned... */
1002 if (wm_size > (long)wm->max_wm)
1003 wm_size = wm->max_wm;
1004 if (wm_size <= 0)
1005 wm_size = wm->default_wm;
1006 return wm_size;
1007}
1008
1009static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010{
1011 struct drm_crtc *crtc, *enabled = NULL;
1012
1013 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1014 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1015 if (enabled)
1016 return NULL;
1017 enabled = crtc;
1018 }
1019 }
1020
1021 return enabled;
1022}
1023
46ba614c 1024static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1025{
46ba614c 1026 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_crtc *crtc;
1029 const struct cxsr_latency *latency;
1030 u32 reg;
1031 unsigned long wm;
1032
1033 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034 dev_priv->fsb_freq, dev_priv->mem_freq);
1035 if (!latency) {
1036 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037 pineview_disable_cxsr(dev);
1038 return;
1039 }
1040
1041 crtc = single_enabled_crtc(dev);
1042 if (crtc) {
241bfc38 1043 const struct drm_display_mode *adjusted_mode;
f4510a27 1044 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1045 int clock;
1046
1047 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1049
1050 /* Display SR */
1051 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052 pineview_display_wm.fifo_size,
1053 pixel_size, latency->display_sr);
1054 reg = I915_READ(DSPFW1);
1055 reg &= ~DSPFW_SR_MASK;
1056 reg |= wm << DSPFW_SR_SHIFT;
1057 I915_WRITE(DSPFW1, reg);
1058 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060 /* cursor SR */
1061 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062 pineview_display_wm.fifo_size,
1063 pixel_size, latency->cursor_sr);
1064 reg = I915_READ(DSPFW3);
1065 reg &= ~DSPFW_CURSOR_SR_MASK;
1066 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067 I915_WRITE(DSPFW3, reg);
1068
1069 /* Display HPLL off SR */
1070 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071 pineview_display_hplloff_wm.fifo_size,
1072 pixel_size, latency->display_hpll_disable);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_HPLL_SR_MASK;
1075 reg |= wm & DSPFW_HPLL_SR_MASK;
1076 I915_WRITE(DSPFW3, reg);
1077
1078 /* cursor HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->cursor_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085 I915_WRITE(DSPFW3, reg);
1086 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088 /* activate cxsr */
1089 I915_WRITE(DSPFW3,
1090 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092 } else {
1093 pineview_disable_cxsr(dev);
1094 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095 }
1096}
1097
1098static bool g4x_compute_wm0(struct drm_device *dev,
1099 int plane,
1100 const struct intel_watermark_params *display,
1101 int display_latency_ns,
1102 const struct intel_watermark_params *cursor,
1103 int cursor_latency_ns,
1104 int *plane_wm,
1105 int *cursor_wm)
1106{
1107 struct drm_crtc *crtc;
4fe8590a 1108 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1109 int htotal, hdisplay, clock, pixel_size;
1110 int line_time_us, line_count;
1111 int entries, tlb_miss;
1112
1113 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1114 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1115 *cursor_wm = cursor->guard_size;
1116 *plane_wm = display->guard_size;
1117 return false;
1118 }
1119
4fe8590a 1120 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1121 clock = adjusted_mode->crtc_clock;
fec8cba3 1122 htotal = adjusted_mode->crtc_htotal;
37327abd 1123 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1124 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1125
1126 /* Use the small buffer method to calculate plane watermark */
1127 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129 if (tlb_miss > 0)
1130 entries += tlb_miss;
1131 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132 *plane_wm = entries + display->guard_size;
1133 if (*plane_wm > (int)display->max_wm)
1134 *plane_wm = display->max_wm;
1135
1136 /* Use the large buffer method to calculate cursor watermark */
922044c9 1137 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1139 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141 if (tlb_miss > 0)
1142 entries += tlb_miss;
1143 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144 *cursor_wm = entries + cursor->guard_size;
1145 if (*cursor_wm > (int)cursor->max_wm)
1146 *cursor_wm = (int)cursor->max_wm;
1147
1148 return true;
1149}
1150
1151/*
1152 * Check the wm result.
1153 *
1154 * If any calculated watermark values is larger than the maximum value that
1155 * can be programmed into the associated watermark register, that watermark
1156 * must be disabled.
1157 */
1158static bool g4x_check_srwm(struct drm_device *dev,
1159 int display_wm, int cursor_wm,
1160 const struct intel_watermark_params *display,
1161 const struct intel_watermark_params *cursor)
1162{
1163 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164 display_wm, cursor_wm);
1165
1166 if (display_wm > display->max_wm) {
1167 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168 display_wm, display->max_wm);
1169 return false;
1170 }
1171
1172 if (cursor_wm > cursor->max_wm) {
1173 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174 cursor_wm, cursor->max_wm);
1175 return false;
1176 }
1177
1178 if (!(display_wm || cursor_wm)) {
1179 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180 return false;
1181 }
1182
1183 return true;
1184}
1185
1186static bool g4x_compute_srwm(struct drm_device *dev,
1187 int plane,
1188 int latency_ns,
1189 const struct intel_watermark_params *display,
1190 const struct intel_watermark_params *cursor,
1191 int *display_wm, int *cursor_wm)
1192{
1193 struct drm_crtc *crtc;
4fe8590a 1194 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1195 int hdisplay, htotal, pixel_size, clock;
1196 unsigned long line_time_us;
1197 int line_count, line_size;
1198 int small, large;
1199 int entries;
1200
1201 if (!latency_ns) {
1202 *display_wm = *cursor_wm = 0;
1203 return false;
1204 }
1205
1206 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1207 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1208 clock = adjusted_mode->crtc_clock;
fec8cba3 1209 htotal = adjusted_mode->crtc_htotal;
37327abd 1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1211 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1212
922044c9 1213 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1215 line_size = hdisplay * pixel_size;
1216
1217 /* Use the minimum of the small and large buffer method for primary */
1218 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219 large = line_count * line_size;
1220
1221 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222 *display_wm = entries + display->guard_size;
1223
1224 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1225 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1226 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227 *cursor_wm = entries + cursor->guard_size;
1228
1229 return g4x_check_srwm(dev,
1230 *display_wm, *cursor_wm,
1231 display, cursor);
1232}
1233
1234static bool vlv_compute_drain_latency(struct drm_device *dev,
1235 int plane,
1236 int *plane_prec_mult,
1237 int *plane_dl,
1238 int *cursor_prec_mult,
1239 int *cursor_dl)
1240{
1241 struct drm_crtc *crtc;
1242 int clock, pixel_size;
1243 int entries;
1244
1245 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1246 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1247 return false;
1248
241bfc38 1249 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1250 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1251
1252 entries = (clock / 1000) * pixel_size;
1253 *plane_prec_mult = (entries > 256) ?
1254 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256 pixel_size);
1257
1258 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1259 *cursor_prec_mult = (entries > 256) ?
1260 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263 return true;
1264}
1265
1266/*
1267 * Update drain latency registers of memory arbiter
1268 *
1269 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270 * to be programmed. Each plane has a drain latency multiplier and a drain
1271 * latency value.
1272 */
1273
1274static void vlv_update_drain_latency(struct drm_device *dev)
1275{
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280 either 16 or 32 */
1281
1282 /* For plane A, Cursor A */
1283 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284 &cursor_prec_mult, &cursora_dl)) {
1285 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290 I915_WRITE(VLV_DDL1, cursora_prec |
1291 (cursora_dl << DDL_CURSORA_SHIFT) |
1292 planea_prec | planea_dl);
1293 }
1294
1295 /* For plane B, Cursor B */
1296 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297 &cursor_prec_mult, &cursorb_dl)) {
1298 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303 I915_WRITE(VLV_DDL2, cursorb_prec |
1304 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305 planeb_prec | planeb_dl);
1306 }
1307}
1308
1309#define single_plane_enabled(mask) is_power_of_2(mask)
1310
46ba614c 1311static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1312{
46ba614c 1313 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1314 static const int sr_latency_ns = 12000;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317 int plane_sr, cursor_sr;
af6c4575 1318 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1319 unsigned int enabled = 0;
1320
1321 vlv_update_drain_latency(dev);
1322
51cea1f4 1323 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1324 &valleyview_wm_info, latency_ns,
1325 &valleyview_cursor_wm_info, latency_ns,
1326 &planea_wm, &cursora_wm))
51cea1f4 1327 enabled |= 1 << PIPE_A;
b445e3b0 1328
51cea1f4 1329 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1330 &valleyview_wm_info, latency_ns,
1331 &valleyview_cursor_wm_info, latency_ns,
1332 &planeb_wm, &cursorb_wm))
51cea1f4 1333 enabled |= 1 << PIPE_B;
b445e3b0 1334
b445e3b0
ED		 1335 if (single_plane_enabled(enabled) &&
1336 g4x_compute_srwm(dev, ffs(enabled) - 1,
1337 sr_latency_ns,
1338 &valleyview_wm_info,
1339 &valleyview_cursor_wm_info,
af6c4575
CW		 1340 &plane_sr, &ignore_cursor_sr) &&
1341 g4x_compute_srwm(dev, ffs(enabled) - 1,
1342 2*sr_latency_ns,
1343 &valleyview_wm_info,
1344 &valleyview_cursor_wm_info,
52bd02d8 1345 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1346 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1347 } else {
b445e3b0
ED		 1348 I915_WRITE(FW_BLC_SELF_VLV,
1349 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1350 plane_sr = cursor_sr = 0;
1351 }
b445e3b0
ED		 1352
1353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354 planea_wm, cursora_wm,
1355 planeb_wm, cursorb_wm,
1356 plane_sr, cursor_sr);
1357
1358 I915_WRITE(DSPFW1,
1359 (plane_sr << DSPFW_SR_SHIFT) |
1360 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362 planea_wm);
1363 I915_WRITE(DSPFW2,
8c919b28 1364 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1365 (cursora_wm << DSPFW_CURSORA_SHIFT));
1366 I915_WRITE(DSPFW3,
8c919b28
CW		 1367 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1369}
1370
46ba614c 1371static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1372{
46ba614c 1373 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 unsigned int enabled = 0;
1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1381 &g4x_wm_info, latency_ns,
1382 &g4x_cursor_wm_info, latency_ns,
1383 &planea_wm, &cursora_wm))
51cea1f4 1384 enabled |= 1 << PIPE_A;
b445e3b0 1385
51cea1f4 1386 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1387 &g4x_wm_info, latency_ns,
1388 &g4x_cursor_wm_info, latency_ns,
1389 &planeb_wm, &cursorb_wm))
51cea1f4 1390 enabled |= 1 << PIPE_B;
b445e3b0 1391
b445e3b0
ED		 1392 if (single_plane_enabled(enabled) &&
1393 g4x_compute_srwm(dev, ffs(enabled) - 1,
1394 sr_latency_ns,
1395 &g4x_wm_info,
1396 &g4x_cursor_wm_info,
52bd02d8 1397 &plane_sr, &cursor_sr)) {
b445e3b0 1398 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1399 } else {
b445e3b0
ED		 1400 I915_WRITE(FW_BLC_SELF,
1401 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1402 plane_sr = cursor_sr = 0;
1403 }
b445e3b0
ED		 1404
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406 planea_wm, cursora_wm,
1407 planeb_wm, cursorb_wm,
1408 plane_sr, cursor_sr);
1409
1410 I915_WRITE(DSPFW1,
1411 (plane_sr << DSPFW_SR_SHIFT) |
1412 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414 planea_wm);
1415 I915_WRITE(DSPFW2,
8c919b28 1416 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1417 (cursora_wm << DSPFW_CURSORA_SHIFT));
1418 /* HPLL off in SR has some issues on G4x... disable it */
1419 I915_WRITE(DSPFW3,
8c919b28 1420 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1421 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422}
1423
46ba614c 1424static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1425{
46ba614c 1426 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct drm_crtc *crtc;
1429 int srwm = 1;
1430 int cursor_sr = 16;
1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1437 const struct drm_display_mode *adjusted_mode =
1438 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1439 int clock = adjusted_mode->crtc_clock;
fec8cba3 1440 int htotal = adjusted_mode->crtc_htotal;
37327abd 1441 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1442 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1443 unsigned long line_time_us;
1444 int entries;
1445
922044c9 1446 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1447
1448 /* Use ns/us then divide to preserve precision */
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 pixel_size * hdisplay;
1451 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452 srwm = I965_FIFO_SIZE - entries;
1453 if (srwm < 0)
1454 srwm = 1;
1455 srwm &= 0x1ff;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457 entries, srwm);
1458
1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1460 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1461 entries = DIV_ROUND_UP(entries,
1462 i965_cursor_wm_info.cacheline_size);
1463 cursor_sr = i965_cursor_wm_info.fifo_size -
1464 (entries + i965_cursor_wm_info.guard_size);
1465
1466 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467 cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm, cursor_sr);
1471
1472 if (IS_CRESTLINE(dev))
1473 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474 } else {
1475 /* Turn off self refresh if both pipes are enabled */
1476 if (IS_CRESTLINE(dev))
1477 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478 & ~FW_BLC_SELF_EN);
1479 }
1480
1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482 srwm);
1483
1484 /* 965 has limitations... */
1485 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486 (8 << 16) | (8 << 8) | (8 << 0));
1487 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490}
1491
46ba614c 1492static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1493{
46ba614c 1494 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 const struct intel_watermark_params *wm_info;
1497 uint32_t fwater_lo;
1498 uint32_t fwater_hi;
1499 int cwm, srwm = 1;
1500 int fifo_size;
1501 int planea_wm, planeb_wm;
1502 struct drm_crtc *crtc, *enabled = NULL;
1503
1504 if (IS_I945GM(dev))
1505 wm_info = &i945_wm_info;
1506 else if (!IS_GEN2(dev))
1507 wm_info = &i915_wm_info;
1508 else
feb56b93 1509 wm_info = &i830_wm_info;
b445e3b0
ED		 1510
1511 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1513 if (intel_crtc_active(crtc)) {
241bfc38 1514 const struct drm_display_mode *adjusted_mode;
f4510a27 1515 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1516 if (IS_GEN2(dev))
1517 cpp = 4;
1518
241bfc38
DL		 1519 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1521 wm_info, fifo_size, cpp,
b445e3b0
ED		 1522 latency_ns);
1523 enabled = crtc;
1524 } else
1525 planea_wm = fifo_size - wm_info->guard_size;
1526
1527 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1529 if (intel_crtc_active(crtc)) {
241bfc38 1530 const struct drm_display_mode *adjusted_mode;
f4510a27 1531 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1532 if (IS_GEN2(dev))
1533 cpp = 4;
1534
241bfc38
DL		 1535 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1537 wm_info, fifo_size, cpp,
b445e3b0
ED		 1538 latency_ns);
1539 if (enabled == NULL)
1540 enabled = crtc;
1541 else
1542 enabled = NULL;
1543 } else
1544 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d
DV		 1548 if (IS_I915GM(dev) && enabled) {
1549 struct intel_framebuffer *fb;
1550
1551 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553 /* self-refresh seems busted with untiled */
1554 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 if (IS_I945G(dev) || IS_I945GM(dev))
1565 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566 else if (IS_I915GM(dev))
3f2dc5ac 1567 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1568
1569 /* Calc sr entries for one plane configs */
1570 if (HAS_FW_BLC(dev) && enabled) {
1571 /* self-refresh has much higher latency */
1572 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1573 const struct drm_display_mode *adjusted_mode =
1574 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1575 int clock = adjusted_mode->crtc_clock;
fec8cba3 1576 int htotal = adjusted_mode->crtc_htotal;
f727b490 1577 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1578 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1579 unsigned long line_time_us;
1580 int entries;
1581
922044c9 1582 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1583
1584 /* Use ns/us then divide to preserve precision */
1585 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586 pixel_size * hdisplay;
1587 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589 srwm = wm_info->fifo_size - entries;
1590 if (srwm < 0)
1591 srwm = 1;
1592
1593 if (IS_I945G(dev) || IS_I945GM(dev))
1594 I915_WRITE(FW_BLC_SELF,
1595 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596 else if (IS_I915GM(dev))
1597 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598 }
1599
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601 planea_wm, planeb_wm, cwm, srwm);
1602
1603 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604 fwater_hi = (cwm & 0x1f);
1605
1606 /* Set request length to 8 cachelines per fetch */
1607 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608 fwater_hi = fwater_hi | (1 << 8);
1609
1610 I915_WRITE(FW_BLC, fwater_lo);
1611 I915_WRITE(FW_BLC2, fwater_hi);
1612
1613 if (HAS_FW_BLC(dev)) {
1614 if (enabled) {
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF,
1617 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618 else if (IS_I915GM(dev))
3f2dc5ac 1619 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1620 DRM_DEBUG_KMS("memory self refresh enabled\n");
1621 } else
1622 DRM_DEBUG_KMS("memory self refresh disabled\n");
1623 }
1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
241bfc38
DL		 1639 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1643 4, latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
3658729a
VS		 1652static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653 struct drm_crtc *crtc)
801bcfff
PZ		 1654{
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1656 uint32_t pixel_rate;
801bcfff 1657
241bfc38 1658 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1659
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1662
fd4daa9c 1663 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1664 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1665 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1666
37327abd
VS		 1667 pipe_w = intel_crtc->config.pipe_src_w;
1668 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
1676 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677 pfit_w * pfit_h);
1678 }
1679
1680 return pixel_rate;
1681}
1682
37126462 1683/* latency must be in 0.1us units. */
23297044 1684static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1685 uint32_t latency)
1686{
1687 uint64_t ret;
1688
3312ba65
VS		 1689 if (WARN(latency == 0, "Latency value missing\n"))
1690 return UINT_MAX;
1691
801bcfff
PZ		 1692 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695 return ret;
1696}
1697
37126462 1698/* latency must be in 0.1us units. */
23297044 1699static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1700 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701 uint32_t latency)
1702{
1703 uint32_t ret;
1704
3312ba65
VS		 1705 if (WARN(latency == 0, "Latency value missing\n"))
1706 return UINT_MAX;
1707
801bcfff
PZ		 1708 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710 ret = DIV_ROUND_UP(ret, 64) + 2;
1711 return ret;
1712}
1713
23297044 1714static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1715 uint8_t bytes_per_pixel)
1716{
1717 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718}
1719
820c1980 1720struct ilk_pipe_wm_parameters {
801bcfff 1721 bool active;
801bcfff
PZ		 1722 uint32_t pipe_htotal;
1723 uint32_t pixel_rate;
c35426d2
VS		 1724 struct intel_plane_wm_parameters pri;
1725 struct intel_plane_wm_parameters spr;
1726 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1727};
1728
820c1980 1729struct ilk_wm_maximums {
cca32e9a
PZ		 1730 uint16_t pri;
1731 uint16_t spr;
1732 uint16_t cur;
1733 uint16_t fbc;
1734};
1735
240264f4
VS		 1736/* used in computing the new watermarks state */
1737struct intel_wm_config {
1738 unsigned int num_pipes_active;
1739 bool sprites_enabled;
1740 bool sprites_scaled;
240264f4
VS		 1741};
1742
37126462
VS		 1743/*
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1746 */
820c1980 1747static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
cca32e9a
PZ		 1751 uint32_t method1, method2;
1752
c35426d2 1753 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1754 return 0;
1755
23297044 1756 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1757 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1758 mem_value);
1759
1760 if (!is_lp)
1761 return method1;
1762
23297044 1763 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1764 params->pipe_htotal,
c35426d2
VS		 1765 params->pri.horiz_pixels,
1766 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1767 mem_value);
1768
1769 return min(method1, method2);
801bcfff
PZ		 1770}
1771
37126462
VS		 1772/*
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1775 */
820c1980 1776static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
1779 uint32_t method1, method2;
1780
c35426d2 1781 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1782 return 0;
1783
23297044 1784 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1785 params->spr.bytes_per_pixel,
801bcfff 1786 mem_value);
23297044 1787 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1788 params->pipe_htotal,
c35426d2
VS		 1789 params->spr.horiz_pixels,
1790 params->spr.bytes_per_pixel,
801bcfff
PZ		 1791 mem_value);
1792 return min(method1, method2);
1793}
1794
37126462
VS		 1795/*
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1798 */
820c1980 1799static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
c35426d2 1802 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1803 return 0;
1804
23297044 1805 return ilk_wm_method2(params->pixel_rate,
801bcfff 1806 params->pipe_htotal,
c35426d2
VS		 1807 params->cur.horiz_pixels,
1808 params->cur.bytes_per_pixel,
801bcfff
PZ		 1809 mem_value);
1810}
1811
cca32e9a 1812/* Only for WM_LP. */
820c1980 1813static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1814 uint32_t pri_val)
cca32e9a 1815{
c35426d2 1816 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1817 return 0;
1818
23297044 1819 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1820 params->pri.horiz_pixels,
1821 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1822}
1823
158ae64f
VS		 1824static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825{
416f4727
VS		 1826 if (INTEL_INFO(dev)->gen >= 8)
1827 return 3072;
1828 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1829 return 768;
1830 else
1831 return 512;
1832}
1833
4e975081
VS		 1834static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835 int level, bool is_sprite)
1836{
1837 if (INTEL_INFO(dev)->gen >= 8)
1838 /* BDW primary/sprite plane watermarks */
1839 return level == 0 ? 255 : 2047;
1840 else if (INTEL_INFO(dev)->gen >= 7)
1841 /* IVB/HSW primary/sprite plane watermarks */
1842 return level == 0 ? 127 : 1023;
1843 else if (!is_sprite)
1844 /* ILK/SNB primary plane watermarks */
1845 return level == 0 ? 127 : 511;
1846 else
1847 /* ILK/SNB sprite plane watermarks */
1848 return level == 0 ? 63 : 255;
1849}
1850
1851static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1852 int level)
1853{
1854 if (INTEL_INFO(dev)->gen >= 7)
1855 return level == 0 ? 63 : 255;
1856 else
1857 return level == 0 ? 31 : 63;
1858}
1859
1860static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861{
1862 if (INTEL_INFO(dev)->gen >= 8)
1863 return 31;
1864 else
1865 return 15;
1866}
1867
158ae64f
VS		 1868/* Calculate the maximum primary/sprite plane watermark */
1869static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870 int level,
240264f4 1871 const struct intel_wm_config *config,
158ae64f
VS		 1872 enum intel_ddb_partitioning ddb_partitioning,
1873 bool is_sprite)
1874{
1875 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1876
1877 /* if sprites aren't enabled, sprites get nothing */
240264f4 1878 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1879 return 0;
1880
1881 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1882 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1883 fifo_size /= INTEL_INFO(dev)->num_pipes;
1884
1885 /*
1886 * For some reason the non self refresh
1887 * FIFO size is only half of the self
1888 * refresh FIFO size on ILK/SNB.
1889 */
1890 if (INTEL_INFO(dev)->gen <= 6)
1891 fifo_size /= 2;
1892 }
1893
240264f4 1894 if (config->sprites_enabled) {
158ae64f
VS		 1895 /* level 0 is always calculated with 1:1 split */
1896 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1897 if (is_sprite)
1898 fifo_size *= 5;
1899 fifo_size /= 6;
1900 } else {
1901 fifo_size /= 2;
1902 }
1903 }
1904
1905 /* clamp to max that the registers can hold */
4e975081 1906 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1907}
1908
1909/* Calculate the maximum cursor plane watermark */
1910static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1911 int level,
1912 const struct intel_wm_config *config)
158ae64f
VS		 1913{
1914 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1915 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1916 return 64;
1917
1918 /* otherwise just report max that registers can hold */
4e975081 1919 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1920}
1921
d34ff9c6 1922static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1923 int level,
1924 const struct intel_wm_config *config,
1925 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1926 struct ilk_wm_maximums *max)
158ae64f 1927{
240264f4
VS		 1928 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1931 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1932}
1933
a3cb4048
VS		 1934static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1935 int level,
1936 struct ilk_wm_maximums *max)
1937{
1938 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1939 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1940 max->cur = ilk_cursor_wm_reg_max(dev, level);
1941 max->fbc = ilk_fbc_wm_reg_max(dev);
1942}
1943
d9395655 1944static bool ilk_validate_wm_level(int level,
820c1980 1945 const struct ilk_wm_maximums *max,
d9395655 1946 struct intel_wm_level *result)
a9786a11
VS		 1947{
1948 bool ret;
1949
1950 /* already determined to be invalid? */
1951 if (!result->enable)
1952 return false;
1953
1954 result->enable = result->pri_val <= max->pri &&
1955 result->spr_val <= max->spr &&
1956 result->cur_val <= max->cur;
1957
1958 ret = result->enable;
1959
1960 /*
1961 * HACK until we can pre-compute everything,
1962 * and thus fail gracefully if LP0 watermarks
1963 * are exceeded...
1964 */
1965 if (level == 0 && !result->enable) {
1966 if (result->pri_val > max->pri)
1967 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1968 level, result->pri_val, max->pri);
1969 if (result->spr_val > max->spr)
1970 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1971 level, result->spr_val, max->spr);
1972 if (result->cur_val > max->cur)
1973 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1974 level, result->cur_val, max->cur);
1975
1976 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1977 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1978 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1979 result->enable = true;
1980 }
1981
a9786a11
VS		 1982 return ret;
1983}
1984
d34ff9c6 1985static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1986 int level,
820c1980 1987 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1988 struct intel_wm_level *result)
6f5ddd17
VS		 1989{
1990 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1991 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1992 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1993
1994 /* WM1+ latency values stored in 0.5us units */
1995 if (level > 0) {
1996 pri_latency *= 5;
1997 spr_latency *= 5;
1998 cur_latency *= 5;
1999 }
2000
2001 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2002 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2003 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2004 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2005 result->enable = true;
2006}
2007
801bcfff
PZ		 2008static uint32_t
2009hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2010{
2011 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2013 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2014 u32 linetime, ips_linetime;
1f8eeabf 2015
801bcfff
PZ		 2016 if (!intel_crtc_active(crtc))
2017 return 0;
1011d8c4 2018
1f8eeabf
ED		 2019 /* The WM are computed with base on how long it takes to fill a single
2020 * row at the given clock rate, multiplied by 8.
2021 * */
fec8cba3
JB		 2022 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2023 mode->crtc_clock);
2024 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2025 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2026
801bcfff
PZ		 2027 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2028 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2029}
2030
12b134df
VS		 2031static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032{
2033 struct drm_i915_private *dev_priv = dev->dev_private;
2034
a42a5719 2035 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2036 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2037
2038 wm[0] = (sskpd >> 56) & 0xFF;
2039 if (wm[0] == 0)
2040 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2041 wm[1] = (sskpd >> 4) & 0xFF;
2042 wm[2] = (sskpd >> 12) & 0xFF;
2043 wm[3] = (sskpd >> 20) & 0x1FF;
2044 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2045 } else if (INTEL_INFO(dev)->gen >= 6) {
2046 uint32_t sskpd = I915_READ(MCH_SSKPD);
2047
2048 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2049 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2050 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2051 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2052 } else if (INTEL_INFO(dev)->gen >= 5) {
2053 uint32_t mltr = I915_READ(MLTR_ILK);
2054
2055 /* ILK primary LP0 latency is 700 ns */
2056 wm[0] = 7;
2057 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2058 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2059 }
2060}
2061
53615a5e
VS		 2062static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2063{
2064 /* ILK sprite LP0 latency is 1300 ns */
2065 if (INTEL_INFO(dev)->gen == 5)
2066 wm[0] = 13;
2067}
2068
2069static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2070{
2071 /* ILK cursor LP0 latency is 1300 ns */
2072 if (INTEL_INFO(dev)->gen == 5)
2073 wm[0] = 13;
2074
2075 /* WaDoubleCursorLP3Latency:ivb */
2076 if (IS_IVYBRIDGE(dev))
2077 wm[3] *= 2;
2078}
2079
ad0d6dc4 2080static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2081{
26ec971e 2082 /* how many WM levels are we expecting */
a42a5719 2083 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2084 return 4;
26ec971e 2085 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2086 return 3;
26ec971e 2087 else
ad0d6dc4
VS		 2088 return 2;
2089}
2090
2091static void intel_print_wm_latency(struct drm_device *dev,
2092 const char *name,
2093 const uint16_t wm[5])
2094{
2095 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2096
2097 for (level = 0; level <= max_level; level++) {
2098 unsigned int latency = wm[level];
2099
2100 if (latency == 0) {
2101 DRM_ERROR("%s WM%d latency not provided\n",
2102 name, level);
2103 continue;
2104 }
2105
2106 /* WM1+ latency values in 0.5us units */
2107 if (level > 0)
2108 latency *= 5;
2109
2110 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2111 name, level, wm[level],
2112 latency / 10, latency % 10);
2113 }
2114}
2115
fa50ad61 2116static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2117{
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119
2120 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2121
2122 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2123 sizeof(dev_priv->wm.pri_latency));
2124 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2125 sizeof(dev_priv->wm.pri_latency));
2126
2127 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2128 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2129
2130 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2131 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2132 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2133}
2134
820c1980 2135static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2136 struct ilk_pipe_wm_parameters *p)
1011d8c4 2137{
7c4a395f
VS		 2138 struct drm_device *dev = crtc->dev;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2141 struct drm_plane *plane;
1011d8c4 2142
2a44b76b
VS		 2143 if (!intel_crtc_active(crtc))
2144 return;
801bcfff 2145
2a44b76b
VS		 2146 p->active = true;
2147 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2148 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2149 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2150 p->cur.bytes_per_pixel = 4;
2151 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2152 p->cur.horiz_pixels = intel_crtc->cursor_width;
2153 /* TODO: for now, assume primary and cursor planes are always enabled. */
2154 p->pri.enabled = true;
2155 p->cur.enabled = true;
7c4a395f 2156
af2b653b 2157 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2158 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2159
2a44b76b 2160 if (intel_plane->pipe == pipe) {
7c4a395f 2161 p->spr = intel_plane->wm;
2a44b76b
VS		 2162 break;
2163 }
2164 }
2165}
2166
2167static void ilk_compute_wm_config(struct drm_device *dev,
2168 struct intel_wm_config *config)
2169{
2170 struct intel_crtc *intel_crtc;
2171
2172 /* Compute the currently _active_ config */
2173 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2174 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2175
2a44b76b
VS		 2176 if (!wm->pipe_enabled)
2177 continue;
cca32e9a 2178
2a44b76b
VS		 2179 config->sprites_enabled |= wm->sprites_enabled;
2180 config->sprites_scaled |= wm->sprites_scaled;
2181 config->num_pipes_active++;
cca32e9a 2182 }
801bcfff
PZ		 2183}
2184
0b2ae6d7
VS		 2185/* Compute new watermarks for the pipe */
2186static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2187 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2188 struct intel_pipe_wm *pipe_wm)
2189{
2190 struct drm_device *dev = crtc->dev;
d34ff9c6 2191 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2192 int level, max_level = ilk_wm_max_level(dev);
2193 /* LP0 watermark maximums depend on this pipe alone */
2194 struct intel_wm_config config = {
2195 .num_pipes_active = 1,
2196 .sprites_enabled = params->spr.enabled,
2197 .sprites_scaled = params->spr.scaled,
2198 };
820c1980 2199 struct ilk_wm_maximums max;
0b2ae6d7 2200
2a44b76b
VS		 2201 pipe_wm->pipe_enabled = params->active;
2202 pipe_wm->sprites_enabled = params->spr.enabled;
2203 pipe_wm->sprites_scaled = params->spr.scaled;
2204
7b39a0b7
VS		 2205 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2206 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2207 max_level = 1;
2208
2209 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2210 if (params->spr.scaled)
2211 max_level = 0;
2212
a3cb4048 2213 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2214
a42a5719 2215 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2216 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2217
a3cb4048
VS		 2218 /* LP0 watermarks always use 1/2 DDB partitioning */
2219 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2220
0b2ae6d7 2221 /* At least LP0 must be valid */
a3cb4048
VS		 2222 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2223 return false;
2224
2225 ilk_compute_wm_reg_maximums(dev, 1, &max);
2226
2227 for (level = 1; level <= max_level; level++) {
2228 struct intel_wm_level wm = {};
2229
2230 ilk_compute_wm_level(dev_priv, level, params, &wm);
2231
2232 /*
2233 * Disable any watermark level that exceeds the
2234 * register maximums since such watermarks are
2235 * always invalid.
2236 */
2237 if (!ilk_validate_wm_level(level, &max, &wm))
2238 break;
2239
2240 pipe_wm->wm[level] = wm;
2241 }
2242
2243 return true;
0b2ae6d7
VS		 2244}
2245
2246/*
2247 * Merge the watermarks from all active pipes for a specific level.
2248 */
2249static void ilk_merge_wm_level(struct drm_device *dev,
2250 int level,
2251 struct intel_wm_level *ret_wm)
2252{
2253 const struct intel_crtc *intel_crtc;
2254
d52fea5b
VS		 2255 ret_wm->enable = true;
2256
0b2ae6d7 2257 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
fe392efd
VS		 2258 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2259 const struct intel_wm_level *wm = &active->wm[level];
2260
2261 if (!active->pipe_enabled)
2262 continue;
0b2ae6d7 2263
d52fea5b
VS		 2264 /*
2265 * The watermark values may have been used in the past,
2266 * so we must maintain them in the registers for some
2267 * time even if the level is now disabled.
2268 */
0b2ae6d7 2269 if (!wm->enable)
d52fea5b 2270 ret_wm->enable = false;
0b2ae6d7
VS		 2271
2272 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2273 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2274 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2275 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2276 }
0b2ae6d7
VS		 2277}
2278
2279/*
2280 * Merge all low power watermarks for all active pipes.
2281 */
2282static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2283 const struct intel_wm_config *config,
820c1980 2284 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2285 struct intel_pipe_wm *merged)
2286{
2287 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2288 int last_enabled_level = max_level;
0b2ae6d7 2289
0ba22e26
VS		 2290 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2291 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2292 config->num_pipes_active > 1)
2293 return;
2294
6c8b6c28
VS		 2295 /* ILK: FBC WM must be disabled always */
2296 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2297
2298 /* merge each WM1+ level */
2299 for (level = 1; level <= max_level; level++) {
2300 struct intel_wm_level *wm = &merged->wm[level];
2301
2302 ilk_merge_wm_level(dev, level, wm);
2303
d52fea5b
VS		 2304 if (level > last_enabled_level)
2305 wm->enable = false;
2306 else if (!ilk_validate_wm_level(level, max, wm))
2307 /* make sure all following levels get disabled */
2308 last_enabled_level = level - 1;
0b2ae6d7
VS		 2309
2310 /*
2311 * The spec says it is preferred to disable
2312 * FBC WMs instead of disabling a WM level.
2313 */
2314 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2315 if (wm->enable)
2316 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2317 wm->fbc_val = 0;
2318 }
2319 }
6c8b6c28
VS		 2320
2321 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2322 /*
2323 * FIXME this is racy. FBC might get enabled later.
2324 * What we should check here is whether FBC can be
2325 * enabled sometime later.
2326 */
2327 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2328 for (level = 2; level <= max_level; level++) {
2329 struct intel_wm_level *wm = &merged->wm[level];
2330
2331 wm->enable = false;
2332 }
2333 }
0b2ae6d7
VS		 2334}
2335
b380ca3c
VS		 2336static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2337{
2338 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2339 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2340}
2341
a68d68ee
VS		 2342/* The value we need to program into the WM_LPx latency field */
2343static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2344{
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2346
a42a5719 2347 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2348 return 2 * level;
2349 else
2350 return dev_priv->wm.pri_latency[level];
2351}
2352
820c1980 2353static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2354 const struct intel_pipe_wm *merged,
609cedef 2355 enum intel_ddb_partitioning partitioning,
820c1980 2356 struct ilk_wm_values *results)
801bcfff 2357{
0b2ae6d7
VS		 2358 struct intel_crtc *intel_crtc;
2359 int level, wm_lp;
cca32e9a 2360
0362c781 2361 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2362 results->partitioning = partitioning;
cca32e9a 2363
0b2ae6d7 2364 /* LP1+ register values */
cca32e9a 2365 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2366 const struct intel_wm_level *r;
801bcfff 2367
b380ca3c 2368 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2369
0362c781 2370 r = &merged->wm[level];
cca32e9a 2371
d52fea5b
VS		 2372 /*
2373 * Maintain the watermark values even if the level is
2374 * disabled. Doing otherwise could cause underruns.
2375 */
2376 results->wm_lp[wm_lp - 1] =
a68d68ee 2377 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2378 (r->pri_val << WM1_LP_SR_SHIFT) |
2379 r->cur_val;
2380
d52fea5b
VS		 2381 if (r->enable)
2382 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2383
416f4727
VS		 2384 if (INTEL_INFO(dev)->gen >= 8)
2385 results->wm_lp[wm_lp - 1] |=
2386 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2387 else
2388 results->wm_lp[wm_lp - 1] |=
2389 r->fbc_val << WM1_LP_FBC_SHIFT;
2390
d52fea5b
VS		 2391 /*
2392 * Always set WM1S_LP_EN when spr_val != 0, even if the
2393 * level is disabled. Doing otherwise could cause underruns.
2394 */
6cef2b8a
VS		 2395 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2396 WARN_ON(wm_lp != 1);
2397 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2398 } else
2399 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2400 }
801bcfff 2401
0b2ae6d7
VS		 2402 /* LP0 register values */
2403 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2404 enum pipe pipe = intel_crtc->pipe;
2405 const struct intel_wm_level *r =
2406 &intel_crtc->wm.active.wm[0];
2407
2408 if (WARN_ON(!r->enable))
2409 continue;
2410
2411 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2412
0b2ae6d7
VS		 2413 results->wm_pipe[pipe] =
2414 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2415 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2416 r->cur_val;
801bcfff
PZ		 2417 }
2418}
2419
861f3389
PZ		 2420/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2421 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2422static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2423 struct intel_pipe_wm *r1,
2424 struct intel_pipe_wm *r2)
861f3389 2425{
198a1e9b
VS		 2426 int level, max_level = ilk_wm_max_level(dev);
2427 int level1 = 0, level2 = 0;
861f3389 2428
198a1e9b
VS		 2429 for (level = 1; level <= max_level; level++) {
2430 if (r1->wm[level].enable)
2431 level1 = level;
2432 if (r2->wm[level].enable)
2433 level2 = level;
861f3389
PZ		 2434 }
2435
198a1e9b
VS		 2436 if (level1 == level2) {
2437 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2438 return r2;
2439 else
2440 return r1;
198a1e9b 2441 } else if (level1 > level2) {
861f3389
PZ		 2442 return r1;
2443 } else {
2444 return r2;
2445 }
2446}
2447
49a687c4
VS		 2448/* dirty bits used to track which watermarks need changes */
2449#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2450#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2451#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2452#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2453#define WM_DIRTY_FBC (1 << 24)
2454#define WM_DIRTY_DDB (1 << 25)
2455
2456static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2457 const struct ilk_wm_values *old,
2458 const struct ilk_wm_values *new)
49a687c4
VS		 2459{
2460 unsigned int dirty = 0;
2461 enum pipe pipe;
2462 int wm_lp;
2463
2464 for_each_pipe(pipe) {
2465 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2466 dirty |= WM_DIRTY_LINETIME(pipe);
2467 /* Must disable LP1+ watermarks too */
2468 dirty |= WM_DIRTY_LP_ALL;
2469 }
2470
2471 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2472 dirty |= WM_DIRTY_PIPE(pipe);
2473 /* Must disable LP1+ watermarks too */
2474 dirty |= WM_DIRTY_LP_ALL;
2475 }
2476 }
2477
2478 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2479 dirty |= WM_DIRTY_FBC;
2480 /* Must disable LP1+ watermarks too */
2481 dirty |= WM_DIRTY_LP_ALL;
2482 }
2483
2484 if (old->partitioning != new->partitioning) {
2485 dirty |= WM_DIRTY_DDB;
2486 /* Must disable LP1+ watermarks too */
2487 dirty |= WM_DIRTY_LP_ALL;
2488 }
2489
2490 /* LP1+ watermarks already deemed dirty, no need to continue */
2491 if (dirty & WM_DIRTY_LP_ALL)
2492 return dirty;
2493
2494 /* Find the lowest numbered LP1+ watermark in need of an update... */
2495 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2496 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2497 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2498 break;
2499 }
2500
2501 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2502 for (; wm_lp <= 3; wm_lp++)
2503 dirty |= WM_DIRTY_LP(wm_lp);
2504
2505 return dirty;
2506}
2507
8553c18e
VS		 2508static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2509 unsigned int dirty)
801bcfff 2510{
820c1980 2511 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2512 bool changed = false;
801bcfff 2513
facd619b
VS		 2514 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2515 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2516 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2517 changed = true;
facd619b
VS		 2518 }
2519 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2520 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2521 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2522 changed = true;
facd619b
VS		 2523 }
2524 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2525 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2526 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2527 changed = true;
facd619b 2528 }
801bcfff 2529
facd619b
VS		 2530 /*
2531 * Don't touch WM1S_LP_EN here.
2532 * Doing so could cause underruns.
2533 */
6cef2b8a 2534
8553c18e
VS		 2535 return changed;
2536}
2537
2538/*
2539 * The spec says we shouldn't write when we don't need, because every write
2540 * causes WMs to be re-evaluated, expending some power.
2541 */
820c1980
ID		 2542static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2543 struct ilk_wm_values *results)
8553c18e
VS		 2544{
2545 struct drm_device *dev = dev_priv->dev;
820c1980 2546 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2547 unsigned int dirty;
2548 uint32_t val;
2549
2550 dirty = ilk_compute_wm_dirty(dev, previous, results);
2551 if (!dirty)
2552 return;
2553
2554 _ilk_disable_lp_wm(dev_priv, dirty);
2555
49a687c4 2556 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2557 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2558 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2559 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2560 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2561 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2562
49a687c4 2563 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2564 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2565 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2566 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2567 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2568 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2569
49a687c4 2570 if (dirty & WM_DIRTY_DDB) {
a42a5719 2571 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2572 val = I915_READ(WM_MISC);
2573 if (results->partitioning == INTEL_DDB_PART_1_2)
2574 val &= ~WM_MISC_DATA_PARTITION_5_6;
2575 else
2576 val |= WM_MISC_DATA_PARTITION_5_6;
2577 I915_WRITE(WM_MISC, val);
2578 } else {
2579 val = I915_READ(DISP_ARB_CTL2);
2580 if (results->partitioning == INTEL_DDB_PART_1_2)
2581 val &= ~DISP_DATA_PARTITION_5_6;
2582 else
2583 val |= DISP_DATA_PARTITION_5_6;
2584 I915_WRITE(DISP_ARB_CTL2, val);
2585 }
1011d8c4
PZ		 2586 }
2587
49a687c4 2588 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2589 val = I915_READ(DISP_ARB_CTL);
2590 if (results->enable_fbc_wm)
2591 val &= ~DISP_FBC_WM_DIS;
2592 else
2593 val |= DISP_FBC_WM_DIS;
2594 I915_WRITE(DISP_ARB_CTL, val);
2595 }
2596
954911eb
ID		 2597 if (dirty & WM_DIRTY_LP(1) &&
2598 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2599 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2600
2601 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2602 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2603 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2604 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2605 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2606 }
801bcfff 2607
facd619b 2608 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2609 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2610 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2611 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2612 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2613 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2614
2615 dev_priv->wm.hw = *results;
801bcfff
PZ		 2616}
2617
8553c18e
VS		 2618static bool ilk_disable_lp_wm(struct drm_device *dev)
2619{
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621
2622 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2623}
2624
820c1980 2625static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2626{
7c4a395f 2627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2628 struct drm_device *dev = crtc->dev;
801bcfff 2629 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2630 struct ilk_wm_maximums max;
2631 struct ilk_pipe_wm_parameters params = {};
2632 struct ilk_wm_values results = {};
77c122bc 2633 enum intel_ddb_partitioning partitioning;
7c4a395f 2634 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2635 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2636 struct intel_wm_config config = {};
7c4a395f 2637
2a44b76b 2638 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2639
2640 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2641
2642 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2643 return;
861f3389 2644
7c4a395f 2645 intel_crtc->wm.active = pipe_wm;
861f3389 2646
2a44b76b
VS		 2647 ilk_compute_wm_config(dev, &config);
2648
34982fe1 2649 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2650 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2651
2652 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2653 if (INTEL_INFO(dev)->gen >= 7 &&
2654 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2655 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2656 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2657
820c1980 2658 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2659 } else {
198a1e9b 2660 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2661 }
2662
198a1e9b 2663 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2664 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2665
820c1980 2666 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2667
820c1980 2668 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2669}
2670
820c1980 2671static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2672 struct drm_crtc *crtc,
526682e9 2673 uint32_t sprite_width, int pixel_size,
bdd57d03 2674 bool enabled, bool scaled)
526682e9 2675{
8553c18e 2676 struct drm_device *dev = plane->dev;
adf3d35e 2677 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2678
adf3d35e
VS		 2679 intel_plane->wm.enabled = enabled;
2680 intel_plane->wm.scaled = scaled;
2681 intel_plane->wm.horiz_pixels = sprite_width;
2682 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2683
8553c18e
VS		 2684 /*
2685 * IVB workaround: must disable low power watermarks for at least
2686 * one frame before enabling scaling. LP watermarks can be re-enabled
2687 * when scaling is disabled.
2688 *
2689 * WaCxSRDisabledForSpriteScaling:ivb
2690 */
2691 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2692 intel_wait_for_vblank(dev, intel_plane->pipe);
2693
820c1980 2694 ilk_update_wm(crtc);
526682e9
PZ		 2695}
2696
243e6a44
VS		 2697static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2698{
2699 struct drm_device *dev = crtc->dev;
2700 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2701 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2704 enum pipe pipe = intel_crtc->pipe;
2705 static const unsigned int wm0_pipe_reg[] = {
2706 [PIPE_A] = WM0_PIPEA_ILK,
2707 [PIPE_B] = WM0_PIPEB_ILK,
2708 [PIPE_C] = WM0_PIPEC_IVB,
2709 };
2710
2711 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2712 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2713 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2714
2a44b76b
VS		 2715 active->pipe_enabled = intel_crtc_active(crtc);
2716
2717 if (active->pipe_enabled) {
243e6a44
VS		 2718 u32 tmp = hw->wm_pipe[pipe];
2719
2720 /*
2721 * For active pipes LP0 watermark is marked as
2722 * enabled, and LP1+ watermaks as disabled since
2723 * we can't really reverse compute them in case
2724 * multiple pipes are active.
2725 */
2726 active->wm[0].enable = true;
2727 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2728 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2729 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2730 active->linetime = hw->wm_linetime[pipe];
2731 } else {
2732 int level, max_level = ilk_wm_max_level(dev);
2733
2734 /*
2735 * For inactive pipes, all watermark levels
2736 * should be marked as enabled but zeroed,
2737 * which is what we'd compute them to.
2738 */
2739 for (level = 0; level <= max_level; level++)
2740 active->wm[level].enable = true;
2741 }
2742}
2743
2744void ilk_wm_get_hw_state(struct drm_device *dev)
2745{
2746 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2747 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2748 struct drm_crtc *crtc;
2749
2750 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2751 ilk_pipe_wm_get_hw_state(crtc);
2752
2753 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2754 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2755 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2756
2757 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2758 if (INTEL_INFO(dev)->gen >= 7) {
2759 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2760 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2761 }
243e6a44 2762
a42a5719 2763 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2764 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2765 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2766 else if (IS_IVYBRIDGE(dev))
2767 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2768 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2769
2770 hw->enable_fbc_wm =
2771 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2772}
2773
b445e3b0
ED		 2774/**
2775 * intel_update_watermarks - update FIFO watermark values based on current modes
2776 *
2777 * Calculate watermark values for the various WM regs based on current mode
2778 * and plane configuration.
2779 *
2780 * There are several cases to deal with here:
2781 * - normal (i.e. non-self-refresh)
2782 * - self-refresh (SR) mode
2783 * - lines are large relative to FIFO size (buffer can hold up to 2)
2784 * - lines are small relative to FIFO size (buffer can hold more than 2
2785 * lines), so need to account for TLB latency
2786 *
2787 * The normal calculation is:
2788 * watermark = dotclock * bytes per pixel * latency
2789 * where latency is platform & configuration dependent (we assume pessimal
2790 * values here).
2791 *
2792 * The SR calculation is:
2793 * watermark = (trunc(latency/line time)+1) * surface width *
2794 * bytes per pixel
2795 * where
2796 * line time = htotal / dotclock
2797 * surface width = hdisplay for normal plane and 64 for cursor
2798 * and latency is assumed to be high, as above.
2799 *
2800 * The final value programmed to the register should always be rounded up,
2801 * and include an extra 2 entries to account for clock crossings.
2802 *
2803 * We don't use the sprite, so we can ignore that. And on Crestline we have
2804 * to set the non-SR watermarks to 8.
2805 */
46ba614c 2806void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2807{
46ba614c 2808 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2809
2810 if (dev_priv->display.update_wm)
46ba614c 2811 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2812}
2813
adf3d35e
VS		 2814void intel_update_sprite_watermarks(struct drm_plane *plane,
2815 struct drm_crtc *crtc,
4c4ff43a 2816 uint32_t sprite_width, int pixel_size,
39db4a4d 2817 bool enabled, bool scaled)
b445e3b0 2818{
adf3d35e 2819 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2820
2821 if (dev_priv->display.update_sprite_wm)
adf3d35e 2822 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2823 pixel_size, enabled, scaled);
b445e3b0
ED		 2824}
2825
2b4e57bd
ED		 2826static struct drm_i915_gem_object *
2827intel_alloc_context_page(struct drm_device *dev)
2828{
2829 struct drm_i915_gem_object *ctx;
2830 int ret;
2831
2832 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2833
2834 ctx = i915_gem_alloc_object(dev, 4096);
2835 if (!ctx) {
2836 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2837 return NULL;
2838 }
2839
c69766f2 2840 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2841 if (ret) {
2842 DRM_ERROR("failed to pin power context: %d\n", ret);
2843 goto err_unref;
2844 }
2845
2846 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2847 if (ret) {
2848 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2849 goto err_unpin;
2850 }
2851
2852 return ctx;
2853
2854err_unpin:
d7f46fc4 2855 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2856err_unref:
2857 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2858 return NULL;
2859}
2860
9270388e
DV		 2861/**
2862 * Lock protecting IPS related data structures
9270388e
DV		 2863 */
2864DEFINE_SPINLOCK(mchdev_lock);
2865
2866/* Global for IPS driver to get at the current i915 device. Protected by
2867 * mchdev_lock. */
2868static struct drm_i915_private *i915_mch_dev;
2869
2b4e57bd
ED		 2870bool ironlake_set_drps(struct drm_device *dev, u8 val)
2871{
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 u16 rgvswctl;
2874
9270388e
DV		 2875 assert_spin_locked(&mchdev_lock);
2876
2b4e57bd
ED		 2877 rgvswctl = I915_READ16(MEMSWCTL);
2878 if (rgvswctl & MEMCTL_CMD_STS) {
2879 DRM_DEBUG("gpu busy, RCS change rejected\n");
2880 return false; /* still busy with another command */
2881 }
2882
2883 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2884 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2885 I915_WRITE16(MEMSWCTL, rgvswctl);
2886 POSTING_READ16(MEMSWCTL);
2887
2888 rgvswctl |= MEMCTL_CMD_STS;
2889 I915_WRITE16(MEMSWCTL, rgvswctl);
2890
2891 return true;
2892}
2893
8090c6b9 2894static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2895{
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897 u32 rgvmodectl = I915_READ(MEMMODECTL);
2898 u8 fmax, fmin, fstart, vstart;
2899
9270388e
DV		 2900 spin_lock_irq(&mchdev_lock);
2901
2b4e57bd
ED		 2902 /* Enable temp reporting */
2903 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2904 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2905
2906 /* 100ms RC evaluation intervals */
2907 I915_WRITE(RCUPEI, 100000);
2908 I915_WRITE(RCDNEI, 100000);
2909
2910 /* Set max/min thresholds to 90ms and 80ms respectively */
2911 I915_WRITE(RCBMAXAVG, 90000);
2912 I915_WRITE(RCBMINAVG, 80000);
2913
2914 I915_WRITE(MEMIHYST, 1);
2915
2916 /* Set up min, max, and cur for interrupt handling */
2917 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2918 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2919 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2920 MEMMODE_FSTART_SHIFT;
2921
2922 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2923 PXVFREQ_PX_SHIFT;
2924
20e4d407
DV		 2925 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2926 dev_priv->ips.fstart = fstart;
2b4e57bd 2927
20e4d407
DV		 2928 dev_priv->ips.max_delay = fstart;
2929 dev_priv->ips.min_delay = fmin;
2930 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2931
2932 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2933 fmax, fmin, fstart);
2934
2935 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2936
2937 /*
2938 * Interrupts will be enabled in ironlake_irq_postinstall
2939 */
2940
2941 I915_WRITE(VIDSTART, vstart);
2942 POSTING_READ(VIDSTART);
2943
2944 rgvmodectl |= MEMMODE_SWMODE_EN;
2945 I915_WRITE(MEMMODECTL, rgvmodectl);
2946
9270388e 2947 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2948 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2949 mdelay(1);
2b4e57bd
ED		 2950
2951 ironlake_set_drps(dev, fstart);
2952
20e4d407 2953 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2954 I915_READ(0x112e0);
20e4d407
DV		 2955 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2956 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2957 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2958
2959 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2960}
2961
8090c6b9 2962static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2963{
2964 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2965 u16 rgvswctl;
2966
2967 spin_lock_irq(&mchdev_lock);
2968
2969 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2970
2971 /* Ack interrupts, disable EFC interrupt */
2972 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2973 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2974 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2975 I915_WRITE(DEIIR, DE_PCU_EVENT);
2976 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2977
2978 /* Go back to the starting frequency */
20e4d407 2979 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2980 mdelay(1);
2b4e57bd
ED		 2981 rgvswctl |= MEMCTL_CMD_STS;
2982 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2983 mdelay(1);
2b4e57bd 2984
9270388e 2985 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2986}
2987
acbe9475
DV		 2988/* There's a funny hw issue where the hw returns all 0 when reading from
2989 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2990 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2991 * all limits and the gpu stuck at whatever frequency it is at atm).
2992 */
6917c7b9 2993static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 2994{
7b9e0ae6 2995 u32 limits;
2b4e57bd 2996
20b46e59
DV		 2997 /* Only set the down limit when we've reached the lowest level to avoid
2998 * getting more interrupts, otherwise leave this clear. This prevents a
2999 * race in the hw when coming out of rc6: There's a tiny window where
3000 * the hw runs at the minimal clock before selecting the desired
3001 * frequency, if the down threshold expires in that window we will not
3002 * receive a down interrupt. */
b39fb297
BW		 3003 limits = dev_priv->rps.max_freq_softlimit << 24;
3004 if (val <= dev_priv->rps.min_freq_softlimit)
3005 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3006
3007 return limits;
3008}
3009
dd75fdc8
CW		 3010static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3011{
3012 int new_power;
3013
3014 new_power = dev_priv->rps.power;
3015 switch (dev_priv->rps.power) {
3016 case LOW_POWER:
b39fb297 3017 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3018 new_power = BETWEEN;
3019 break;
3020
3021 case BETWEEN:
b39fb297 3022 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3023 new_power = LOW_POWER;
b39fb297 3024 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3025 new_power = HIGH_POWER;
3026 break;
3027
3028 case HIGH_POWER:
b39fb297 3029 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3030 new_power = BETWEEN;
3031 break;
3032 }
3033 /* Max/min bins are special */
b39fb297 3034 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3035 new_power = LOW_POWER;
b39fb297 3036 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3037 new_power = HIGH_POWER;
3038 if (new_power == dev_priv->rps.power)
3039 return;
3040
3041 /* Note the units here are not exactly 1us, but 1280ns. */
3042 switch (new_power) {
3043 case LOW_POWER:
3044 /* Upclock if more than 95% busy over 16ms */
3045 I915_WRITE(GEN6_RP_UP_EI, 12500);
3046 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3047
3048 /* Downclock if less than 85% busy over 32ms */
3049 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3050 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3051
3052 I915_WRITE(GEN6_RP_CONTROL,
3053 GEN6_RP_MEDIA_TURBO |
3054 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3055 GEN6_RP_MEDIA_IS_GFX |
3056 GEN6_RP_ENABLE |
3057 GEN6_RP_UP_BUSY_AVG |
3058 GEN6_RP_DOWN_IDLE_AVG);
3059 break;
3060
3061 case BETWEEN:
3062 /* Upclock if more than 90% busy over 13ms */
3063 I915_WRITE(GEN6_RP_UP_EI, 10250);
3064 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3065
3066 /* Downclock if less than 75% busy over 32ms */
3067 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3068 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3069
3070 I915_WRITE(GEN6_RP_CONTROL,
3071 GEN6_RP_MEDIA_TURBO |
3072 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3073 GEN6_RP_MEDIA_IS_GFX |
3074 GEN6_RP_ENABLE |
3075 GEN6_RP_UP_BUSY_AVG |
3076 GEN6_RP_DOWN_IDLE_AVG);
3077 break;
3078
3079 case HIGH_POWER:
3080 /* Upclock if more than 85% busy over 10ms */
3081 I915_WRITE(GEN6_RP_UP_EI, 8000);
3082 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3083
3084 /* Downclock if less than 60% busy over 32ms */
3085 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3086 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3087
3088 I915_WRITE(GEN6_RP_CONTROL,
3089 GEN6_RP_MEDIA_TURBO |
3090 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3091 GEN6_RP_MEDIA_IS_GFX |
3092 GEN6_RP_ENABLE |
3093 GEN6_RP_UP_BUSY_AVG |
3094 GEN6_RP_DOWN_IDLE_AVG);
3095 break;
3096 }
3097
3098 dev_priv->rps.power = new_power;
3099 dev_priv->rps.last_adj = 0;
3100}
3101
2876ce73
CW		 3102static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3103{
3104 u32 mask = 0;
3105
3106 if (val > dev_priv->rps.min_freq_softlimit)
3107 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3108 if (val < dev_priv->rps.max_freq_softlimit)
3109 mask |= GEN6_PM_RP_UP_THRESHOLD;
3110
3111 /* IVB and SNB hard hangs on looping batchbuffer
3112 * if GEN6_PM_UP_EI_EXPIRED is masked.
3113 */
3114 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3115 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3116
3117 return ~mask;
3118}
3119
b8a5ff8d
JM		 3120/* gen6_set_rps is called to update the frequency request, but should also be
3121 * called when the range (min_delay and max_delay) is modified so that we can
3122 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3123void gen6_set_rps(struct drm_device *dev, u8 val)
3124{
3125 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3126
4fc688ce 3127 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3128 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3129 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3130
eb64cad1
CW		 3131 /* min/max delay may still have been modified so be sure to
3132 * write the limits value.
3133 */
3134 if (val != dev_priv->rps.cur_freq) {
3135 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3136
50e6a2a7 3137 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3138 I915_WRITE(GEN6_RPNSWREQ,
3139 HSW_FREQUENCY(val));
3140 else
3141 I915_WRITE(GEN6_RPNSWREQ,
3142 GEN6_FREQUENCY(val) |
3143 GEN6_OFFSET(0) |
3144 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3145 }
7b9e0ae6 3146
7b9e0ae6
CW		 3147 /* Make sure we continue to get interrupts
3148 * until we hit the minimum or maximum frequencies.
3149 */
eb64cad1 3150 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3151 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3152
d5570a72
BW		 3153 POSTING_READ(GEN6_RPNSWREQ);
3154
b39fb297 3155 dev_priv->rps.cur_freq = val;
be2cde9a 3156 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3157}
3158
76c3552f
D		 3159/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3160 *
3161 * * If Gfx is Idle, then
3162 * 1. Mask Turbo interrupts
3163 * 2. Bring up Gfx clock
3164 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3165 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3166 * 5. Unmask Turbo interrupts
3167*/
3168static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3169{
3170 /*
3171 * When we are idle. Drop to min voltage state.
3172 */
3173
b39fb297 3174 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3175 return;
3176
3177 /* Mask turbo interrupt so that they will not come in between */
3178 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3179
650ad970 3180 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3181
b39fb297 3182 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3183
3184 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3185 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3186
3187 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3188 & GENFREQSTATUS) == 0, 5))
3189 DRM_ERROR("timed out waiting for Punit\n");
3190
650ad970 3191 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3192
2876ce73
CW		 3193 I915_WRITE(GEN6_PMINTRMSK,
3194 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3195}
3196
b29c19b6
CW		 3197void gen6_rps_idle(struct drm_i915_private *dev_priv)
3198{
691bb717
DL		 3199 struct drm_device *dev = dev_priv->dev;
3200
b29c19b6 3201 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3202 if (dev_priv->rps.enabled) {
691bb717 3203 if (IS_VALLEYVIEW(dev))
76c3552f 3204 vlv_set_rps_idle(dev_priv);
c0951f0c 3205 else
b39fb297 3206 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3207 dev_priv->rps.last_adj = 0;
3208 }
b29c19b6
CW		 3209 mutex_unlock(&dev_priv->rps.hw_lock);
3210}
3211
3212void gen6_rps_boost(struct drm_i915_private *dev_priv)
3213{
691bb717
DL		 3214 struct drm_device *dev = dev_priv->dev;
3215
b29c19b6 3216 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3217 if (dev_priv->rps.enabled) {
691bb717 3218 if (IS_VALLEYVIEW(dev))
b39fb297 3219 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3220 else
b39fb297 3221 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3222 dev_priv->rps.last_adj = 0;
3223 }
b29c19b6
CW		 3224 mutex_unlock(&dev_priv->rps.hw_lock);
3225}
3226
0a073b84
JB		 3227void valleyview_set_rps(struct drm_device *dev, u8 val)
3228{
3229 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3230
0a073b84 3231 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3232 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3233 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3234
73008b98 3235 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3236 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3237 dev_priv->rps.cur_freq,
2ec3815f 3238 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3239
2876ce73
CW		 3240 if (val != dev_priv->rps.cur_freq)
3241 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3242
09c87db8 3243 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3244
b39fb297 3245 dev_priv->rps.cur_freq = val;
2ec3815f 3246 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3247}
3248
44fc7d5c 3249static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3250{
3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252
2b4e57bd 3253 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3254 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3255 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3256 /* Complete PM interrupt masking here doesn't race with the rps work
3257 * item again unmasking PM interrupts because that is using a different
3258 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3259 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3260
59cdb63d 3261 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3262 dev_priv->rps.pm_iir = 0;
59cdb63d 3263 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3264
a6706b45 3265 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3266}
3267
44fc7d5c 3268static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3269{
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271
3272 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3273 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3274
44fc7d5c
DV		 3275 gen6_disable_rps_interrupts(dev);
3276}
3277
3278static void valleyview_disable_rps(struct drm_device *dev)
3279{
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3283
44fc7d5c 3284 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3285}
3286
dc39fff7
BW		 3287static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3288{
91ca689a
ID		 3289 if (IS_VALLEYVIEW(dev)) {
3290 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3291 mode = GEN6_RC_CTL_RC6_ENABLE;
3292 else
3293 mode = 0;
3294 }
dc39fff7 3295 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1c79b42f
BW		 3296 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3297 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3298 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3299}
3300
e6069ca8 3301static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3302{
eb4926e4
DL		 3303 /* No RC6 before Ironlake */
3304 if (INTEL_INFO(dev)->gen < 5)
3305 return 0;
3306
e6069ca8
ID		 3307 /* RC6 is only on Ironlake mobile not on desktop */
3308 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3309 return 0;
3310
f033579f
ID		 3311 /* Disable RC6 on Broadwell for now */
3312 if (IS_BROADWELL(dev))
3313 return 0;
3314
456470eb 3315 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3316 if (enable_rc6 >= 0) {
3317 int mask;
3318
3319 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3320 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3321 INTEL_RC6pp_ENABLE;
3322 else
3323 mask = INTEL_RC6_ENABLE;
3324
3325 if ((enable_rc6 & mask) != enable_rc6)
3326 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3327 enable_rc6, enable_rc6 & mask, mask);
3328
3329 return enable_rc6 & mask;
3330 }
2b4e57bd 3331
6567d748
CW		 3332 /* Disable RC6 on Ironlake */
3333 if (INTEL_INFO(dev)->gen == 5)
3334 return 0;
2b4e57bd 3335
8bade1ad 3336 if (IS_IVYBRIDGE(dev))
cca84a1f 3337 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3338
3339 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3340}
3341
e6069ca8
ID		 3342int intel_enable_rc6(const struct drm_device *dev)
3343{
3344 return i915.enable_rc6;
3345}
3346
44fc7d5c
DV		 3347static void gen6_enable_rps_interrupts(struct drm_device *dev)
3348{
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350
3351 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3352 WARN_ON(dev_priv->rps.pm_iir);
a6706b45
D		 3353 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3354 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3355 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3356}
3357
3280e8b0
BW		 3358static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3359{
3360 /* All of these values are in units of 50MHz */
3361 dev_priv->rps.cur_freq = 0;
3362 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3363 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3364 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3365 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3366 /* XXX: only BYT has a special efficient freq */
3367 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3368 /* hw_max = RP0 until we check for overclocking */
3369 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3370
3371 /* Preserve min/max settings in case of re-init */
3372 if (dev_priv->rps.max_freq_softlimit == 0)
3373 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3374
3375 if (dev_priv->rps.min_freq_softlimit == 0)
3376 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3377}
3378
6edee7f3
BW		 3379static void gen8_enable_rps(struct drm_device *dev)
3380{
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_ring_buffer *ring;
3383 uint32_t rc6_mask = 0, rp_state_cap;
3384 int unused;
3385
3386 /* 1a: Software RC state - RC0 */
3387 I915_WRITE(GEN6_RC_STATE, 0);
3388
3389 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3390 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3391 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3392
3393 /* 2a: Disable RC states. */
3394 I915_WRITE(GEN6_RC_CONTROL, 0);
3395
3396 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3397 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3398
3399 /* 2b: Program RC6 thresholds.*/
3400 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3401 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3402 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3403 for_each_ring(ring, dev_priv, unused)
3404 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3405 I915_WRITE(GEN6_RC_SLEEP, 0);
3406 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3407
3408 /* 3: Enable RC6 */
3409 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3410 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3411 intel_print_rc6_info(dev, rc6_mask);
6edee7f3 3412 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
abbf9d2c
BW		 3413 GEN6_RC_CTL_EI_MODE(1) |
3414 rc6_mask);
6edee7f3
BW		 3415
3416 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3417 I915_WRITE(GEN6_RPNSWREQ,
3418 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3419 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3420 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3421 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3422 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3423
3424 /* Docs recommend 900MHz, and 300 MHz respectively */
3425 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3426 dev_priv->rps.max_freq_softlimit << 24 |
3427 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3428
3429 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3430 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3431 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3432 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3433
3434 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3435
3436 /* 5: Enable RPS */
3437 I915_WRITE(GEN6_RP_CONTROL,
3438 GEN6_RP_MEDIA_TURBO |
3439 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3440 GEN6_RP_MEDIA_IS_GFX |
3441 GEN6_RP_ENABLE |
3442 GEN6_RP_UP_BUSY_AVG |
3443 GEN6_RP_DOWN_IDLE_AVG);
3444
3445 /* 6: Ring frequency + overclocking (our driver does this later */
3446
3447 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3448
3449 gen6_enable_rps_interrupts(dev);
3450
c8d9a590 3451 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3452}
3453
79f5b2c7 3454static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3455{
79f5b2c7 3456 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3457 struct intel_ring_buffer *ring;
2a5913a8 3458 u32 rp_state_cap;
7b9e0ae6 3459 u32 gt_perf_status;
d060c169 3460 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3461 u32 gtfifodbg;
2b4e57bd 3462 int rc6_mode;
42c0526c 3463 int i, ret;
2b4e57bd 3464
4fc688ce 3465 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3466
2b4e57bd
ED		 3467 /* Here begins a magic sequence of register writes to enable
3468 * auto-downclocking.
3469 *
3470 * Perhaps there might be some value in exposing these to
3471 * userspace...
3472 */
3473 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3474
3475 /* Clear the DBG now so we don't confuse earlier errors */
3476 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3477 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3478 I915_WRITE(GTFIFODBG, gtfifodbg);
3479 }
3480
c8d9a590 3481 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3482
7b9e0ae6
CW		 3483 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3484 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3485
3280e8b0 3486 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3487
2b4e57bd
ED		 3488 /* disable the counters and set deterministic thresholds */
3489 I915_WRITE(GEN6_RC_CONTROL, 0);
3490
3491 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3492 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3493 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3494 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3495 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3496
b4519513
CW		 3497 for_each_ring(ring, dev_priv, i)
3498 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3499
3500 I915_WRITE(GEN6_RC_SLEEP, 0);
3501 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3502 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3503 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3504 else
3505 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3506 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3507 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3508
5a7dc92a 3509 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3510 rc6_mode = intel_enable_rc6(dev_priv->dev);
3511 if (rc6_mode & INTEL_RC6_ENABLE)
3512 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3513
5a7dc92a
ED		 3514 /* We don't use those on Haswell */
3515 if (!IS_HASWELL(dev)) {
3516 if (rc6_mode & INTEL_RC6p_ENABLE)
3517 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3518
5a7dc92a
ED		 3519 if (rc6_mode & INTEL_RC6pp_ENABLE)
3520 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3521 }
2b4e57bd 3522
dc39fff7 3523 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3524
3525 I915_WRITE(GEN6_RC_CONTROL,
3526 rc6_mask |
3527 GEN6_RC_CTL_EI_MODE(1) |
3528 GEN6_RC_CTL_HW_ENABLE);
3529
dd75fdc8
CW		 3530 /* Power down if completely idle for over 50ms */
3531 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3532 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3533
42c0526c 3534 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3535 if (ret)
42c0526c 3536 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3537
3538 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3539 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3540 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3541 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3542 (pcu_mbox & 0xff) * 50);
b39fb297 3543 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3544 }
3545
dd75fdc8 3546 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3547 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3548
44fc7d5c 3549 gen6_enable_rps_interrupts(dev);
2b4e57bd 3550
31643d54
BW		 3551 rc6vids = 0;
3552 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3553 if (IS_GEN6(dev) && ret) {
3554 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3555 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3556 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3557 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3558 rc6vids &= 0xffff00;
3559 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3560 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3561 if (ret)
3562 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3563 }
3564
c8d9a590 3565 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3566}
3567
c2bc2fc5 3568static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3569{
79f5b2c7 3570 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3571 int min_freq = 15;
3ebecd07
CW		 3572 unsigned int gpu_freq;
3573 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3574 int scaling_factor = 180;
eda79642 3575 struct cpufreq_policy *policy;
2b4e57bd 3576
4fc688ce 3577 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3578
eda79642
BW		 3579 policy = cpufreq_cpu_get(0);
3580 if (policy) {
3581 max_ia_freq = policy->cpuinfo.max_freq;
3582 cpufreq_cpu_put(policy);
3583 } else {
3584 /*
3585 * Default to measured freq if none found, PCU will ensure we
3586 * don't go over
3587 */
2b4e57bd 3588 max_ia_freq = tsc_khz;
eda79642 3589 }
2b4e57bd
ED		 3590
3591 /* Convert from kHz to MHz */
3592 max_ia_freq /= 1000;
3593
153b4b95 3594 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3595 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3596 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3597
2b4e57bd
ED		 3598 /*
3599 * For each potential GPU frequency, load a ring frequency we'd like
3600 * to use for memory access. We do this by specifying the IA frequency
3601 * the PCU should use as a reference to determine the ring frequency.
3602 */
b39fb297 3603 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3604 gpu_freq--) {
b39fb297 3605 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3606 unsigned int ia_freq = 0, ring_freq = 0;
3607
46c764d4
BW		 3608 if (INTEL_INFO(dev)->gen >= 8) {
3609 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3610 ring_freq = max(min_ring_freq, gpu_freq);
3611 } else if (IS_HASWELL(dev)) {
f6aca45c 3612 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3613 ring_freq = max(min_ring_freq, ring_freq);
3614 /* leave ia_freq as the default, chosen by cpufreq */
3615 } else {
3616 /* On older processors, there is no separate ring
3617 * clock domain, so in order to boost the bandwidth
3618 * of the ring, we need to upclock the CPU (ia_freq).
3619 *
3620 * For GPU frequencies less than 750MHz,
3621 * just use the lowest ring freq.
3622 */
3623 if (gpu_freq < min_freq)
3624 ia_freq = 800;
3625 else
3626 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3627 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3628 }
2b4e57bd 3629
42c0526c
BW		 3630 sandybridge_pcode_write(dev_priv,
3631 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3632 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3633 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3634 gpu_freq);
2b4e57bd 3635 }
2b4e57bd
ED		 3636}
3637
c2bc2fc5
ID		 3638void gen6_update_ring_freq(struct drm_device *dev)
3639{
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641
3642 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3643 return;
3644
3645 mutex_lock(&dev_priv->rps.hw_lock);
3646 __gen6_update_ring_freq(dev);
3647 mutex_unlock(&dev_priv->rps.hw_lock);
3648}
3649
0a073b84
JB		 3650int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3651{
3652 u32 val, rp0;
3653
64936258 3654 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3655
3656 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3657 /* Clamp to max */
3658 rp0 = min_t(u32, rp0, 0xea);
3659
3660 return rp0;
3661}
3662
3663static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3664{
3665 u32 val, rpe;
3666
64936258 3667 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3668 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3669 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3670 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3671
3672 return rpe;
3673}
3674
3675int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3676{
64936258 3677 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3678}
3679
ae48434c
ID		 3680/* Check that the pctx buffer wasn't move under us. */
3681static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3682{
3683 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3684
3685 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3686 dev_priv->vlv_pctx->stolen->start);
3687}
3688
c9cddffc
JB		 3689static void valleyview_setup_pctx(struct drm_device *dev)
3690{
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct drm_i915_gem_object *pctx;
3693 unsigned long pctx_paddr;
3694 u32 pcbr;
3695 int pctx_size = 24*1024;
3696
17b0c1f7
ID		 3697 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3698
c9cddffc
JB		 3699 pcbr = I915_READ(VLV_PCBR);
3700 if (pcbr) {
3701 /* BIOS set it up already, grab the pre-alloc'd space */
3702 int pcbr_offset;
3703
3704 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3705 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3706 pcbr_offset,
190d6cd5 3707 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3708 pctx_size);
3709 goto out;
3710 }
3711
3712 /*
3713 * From the Gunit register HAS:
3714 * The Gfx driver is expected to program this register and ensure
3715 * proper allocation within Gfx stolen memory. For example, this
3716 * register should be programmed such than the PCBR range does not
3717 * overlap with other ranges, such as the frame buffer, protected
3718 * memory, or any other relevant ranges.
3719 */
3720 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3721 if (!pctx) {
3722 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3723 return;
3724 }
3725
3726 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3727 I915_WRITE(VLV_PCBR, pctx_paddr);
3728
3729out:
3730 dev_priv->vlv_pctx = pctx;
3731}
3732
ae48434c
ID		 3733static void valleyview_cleanup_pctx(struct drm_device *dev)
3734{
3735 struct drm_i915_private *dev_priv = dev->dev_private;
3736
3737 if (WARN_ON(!dev_priv->vlv_pctx))
3738 return;
3739
3740 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3741 dev_priv->vlv_pctx = NULL;
3742}
3743
4e80519e
ID		 3744static void valleyview_init_gt_powersave(struct drm_device *dev)
3745{
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747
3748 valleyview_setup_pctx(dev);
3749
3750 mutex_lock(&dev_priv->rps.hw_lock);
3751
3752 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3753 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3754 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3755 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3756 dev_priv->rps.max_freq);
3757
3758 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3759 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3760 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3761 dev_priv->rps.efficient_freq);
3762
3763 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3764 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3765 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3766 dev_priv->rps.min_freq);
3767
3768 /* Preserve min/max settings in case of re-init */
3769 if (dev_priv->rps.max_freq_softlimit == 0)
3770 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3771
3772 if (dev_priv->rps.min_freq_softlimit == 0)
3773 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3774
3775 mutex_unlock(&dev_priv->rps.hw_lock);
3776}
3777
3778static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3779{
3780 valleyview_cleanup_pctx(dev);
3781}
3782
0a073b84
JB		 3783static void valleyview_enable_rps(struct drm_device *dev)
3784{
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_ring_buffer *ring;
2a5913a8 3787 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3788 int i;
3789
3790 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3791
ae48434c
ID		 3792 valleyview_check_pctx(dev_priv);
3793
0a073b84 3794 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3795 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3796 gtfifodbg);
0a073b84
JB		 3797 I915_WRITE(GTFIFODBG, gtfifodbg);
3798 }
3799
c8d9a590
D		 3800 /* If VLV, Forcewake all wells, else re-direct to regular path */
3801 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3802
3803 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3804 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3805 I915_WRITE(GEN6_RP_UP_EI, 66000);
3806 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3807
3808 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3809
3810 I915_WRITE(GEN6_RP_CONTROL,
3811 GEN6_RP_MEDIA_TURBO |
3812 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3813 GEN6_RP_MEDIA_IS_GFX |
3814 GEN6_RP_ENABLE |
3815 GEN6_RP_UP_BUSY_AVG |
3816 GEN6_RP_DOWN_IDLE_CONT);
3817
3818 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3819 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3820 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3821
3822 for_each_ring(ring, dev_priv, i)
3823 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3824
2f0aa304 3825 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 3826
3827 /* allows RC6 residency counter to work */
49798eb2
JB		 3828 I915_WRITE(VLV_COUNTER_CONTROL,
3829 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3830 VLV_MEDIA_RC6_COUNT_EN |
3831 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 3832 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 3833 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 3834
3835 intel_print_rc6_info(dev, rc6_mode);
3836
a2b23fe0 3837 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3838
64936258 3839 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3840
3841 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3842 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3843
b39fb297 3844 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 3845 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 3846 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3847 dev_priv->rps.cur_freq);
0a073b84 3848
73008b98 3849 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 3850 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3851 dev_priv->rps.efficient_freq);
0a073b84 3852
b39fb297 3853 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 3854
44fc7d5c 3855 gen6_enable_rps_interrupts(dev);
0a073b84 3856
c8d9a590 3857 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3858}
3859
930ebb46 3860void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3861{
3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863
3e373948 3864 if (dev_priv->ips.renderctx) {
d7f46fc4 3865 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 3866 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3867 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3868 }
3869
3e373948 3870 if (dev_priv->ips.pwrctx) {
d7f46fc4 3871 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 3872 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3873 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3874 }
3875}
3876
930ebb46 3877static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3878{
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880
3881 if (I915_READ(PWRCTXA)) {
3882 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3883 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3884 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3885 50);
3886
3887 I915_WRITE(PWRCTXA, 0);
3888 POSTING_READ(PWRCTXA);
3889
3890 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3891 POSTING_READ(RSTDBYCTL);
3892 }
2b4e57bd
ED		 3893}
3894
3895static int ironlake_setup_rc6(struct drm_device *dev)
3896{
3897 struct drm_i915_private *dev_priv = dev->dev_private;
3898
3e373948
DV		 3899 if (dev_priv->ips.renderctx == NULL)
3900 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3901 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3902 return -ENOMEM;
3903
3e373948
DV		 3904 if (dev_priv->ips.pwrctx == NULL)
3905 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3906 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3907 ironlake_teardown_rc6(dev);
3908 return -ENOMEM;
3909 }
3910
3911 return 0;
3912}
3913
930ebb46 3914static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3915{
3916 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3917 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3918 bool was_interruptible;
2b4e57bd
ED		 3919 int ret;
3920
3921 /* rc6 disabled by default due to repeated reports of hanging during
3922 * boot and resume.
3923 */
3924 if (!intel_enable_rc6(dev))
3925 return;
3926
79f5b2c7
DV		 3927 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3928
2b4e57bd 3929 ret = ironlake_setup_rc6(dev);
79f5b2c7 3930 if (ret)
2b4e57bd 3931 return;
2b4e57bd 3932
3e960501
CW		 3933 was_interruptible = dev_priv->mm.interruptible;
3934 dev_priv->mm.interruptible = false;
3935
2b4e57bd
ED		 3936 /*
3937 * GPU can automatically power down the render unit if given a page
3938 * to save state.
3939 */
6d90c952 3940 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3941 if (ret) {
3942 ironlake_teardown_rc6(dev);
3e960501 3943 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3944 return;
3945 }
3946
6d90c952
DV		 3947 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3948 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3949 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3950 MI_MM_SPACE_GTT |
3951 MI_SAVE_EXT_STATE_EN |
3952 MI_RESTORE_EXT_STATE_EN |
3953 MI_RESTORE_INHIBIT);
3954 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3955 intel_ring_emit(ring, MI_NOOP);
3956 intel_ring_emit(ring, MI_FLUSH);
3957 intel_ring_advance(ring);
2b4e57bd
ED		 3958
3959 /*
3960 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3961 * does an implicit flush, combined with MI_FLUSH above, it should be
3962 * safe to assume that renderctx is valid
3963 */
3e960501
CW		 3964 ret = intel_ring_idle(ring);
3965 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3966 if (ret) {
def27a58 3967 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3968 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3969 return;
3970 }
3971
f343c5f6 3972 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3973 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 3974
91ca689a 3975 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 3976}
3977
dde18883
ED		 3978static unsigned long intel_pxfreq(u32 vidfreq)
3979{
3980 unsigned long freq;
3981 int div = (vidfreq & 0x3f0000) >> 16;
3982 int post = (vidfreq & 0x3000) >> 12;
3983 int pre = (vidfreq & 0x7);
3984
3985 if (!pre)
3986 return 0;
3987
3988 freq = ((div * 133333) / ((1<<post) * pre));
3989
3990 return freq;
3991}
3992
eb48eb00
DV		 3993static const struct cparams {
3994 u16 i;
3995 u16 t;
3996 u16 m;
3997 u16 c;
3998} cparams[] = {
3999 { 1, 1333, 301, 28664 },
4000 { 1, 1066, 294, 24460 },
4001 { 1, 800, 294, 25192 },
4002 { 0, 1333, 276, 27605 },
4003 { 0, 1066, 276, 27605 },
4004 { 0, 800, 231, 23784 },
4005};
4006
f531dcb2 4007static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4008{
4009 u64 total_count, diff, ret;
4010 u32 count1, count2, count3, m = 0, c = 0;
4011 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4012 int i;
4013
02d71956
DV		 4014 assert_spin_locked(&mchdev_lock);
4015
20e4d407 4016 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4017
4018 /* Prevent division-by-zero if we are asking too fast.
4019 * Also, we don't get interesting results if we are polling
4020 * faster than once in 10ms, so just return the saved value
4021 * in such cases.
4022 */
4023 if (diff1 <= 10)
20e4d407 4024 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4025
4026 count1 = I915_READ(DMIEC);
4027 count2 = I915_READ(DDREC);
4028 count3 = I915_READ(CSIEC);
4029
4030 total_count = count1 + count2 + count3;
4031
4032 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4033 if (total_count < dev_priv->ips.last_count1) {
4034 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4035 diff += total_count;
4036 } else {
20e4d407 4037 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4038 }
4039
4040 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4041 if (cparams[i].i == dev_priv->ips.c_m &&
4042 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4043 m = cparams[i].m;
4044 c = cparams[i].c;
4045 break;
4046 }
4047 }
4048
4049 diff = div_u64(diff, diff1);
4050 ret = ((m * diff) + c);
4051 ret = div_u64(ret, 10);
4052
20e4d407
DV		 4053 dev_priv->ips.last_count1 = total_count;
4054 dev_priv->ips.last_time1 = now;
eb48eb00 4055
20e4d407 4056 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4057
4058 return ret;
4059}
4060
f531dcb2
CW		 4061unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4062{
3d13ef2e 4063 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4064 unsigned long val;
4065
3d13ef2e 4066 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4067 return 0;
4068
4069 spin_lock_irq(&mchdev_lock);
4070
4071 val = __i915_chipset_val(dev_priv);
4072
4073 spin_unlock_irq(&mchdev_lock);
4074
4075 return val;
4076}
4077
eb48eb00
DV		 4078unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4079{
4080 unsigned long m, x, b;
4081 u32 tsfs;
4082
4083 tsfs = I915_READ(TSFS);
4084
4085 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4086 x = I915_READ8(TR1);
4087
4088 b = tsfs & TSFS_INTR_MASK;
4089
4090 return ((m * x) / 127) - b;
4091}
4092
4093static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4094{
3d13ef2e 4095 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4096 static const struct v_table {
4097 u16 vd; /* in .1 mil */
4098 u16 vm; /* in .1 mil */
4099 } v_table[] = {
4100 { 0, 0, },
4101 { 375, 0, },
4102 { 500, 0, },
4103 { 625, 0, },
4104 { 750, 0, },
4105 { 875, 0, },
4106 { 1000, 0, },
4107 { 1125, 0, },
4108 { 4125, 3000, },
4109 { 4125, 3000, },
4110 { 4125, 3000, },
4111 { 4125, 3000, },
4112 { 4125, 3000, },
4113 { 4125, 3000, },
4114 { 4125, 3000, },
4115 { 4125, 3000, },
4116 { 4125, 3000, },
4117 { 4125, 3000, },
4118 { 4125, 3000, },
4119 { 4125, 3000, },
4120 { 4125, 3000, },
4121 { 4125, 3000, },
4122 { 4125, 3000, },
4123 { 4125, 3000, },
4124 { 4125, 3000, },
4125 { 4125, 3000, },
4126 { 4125, 3000, },
4127 { 4125, 3000, },
4128 { 4125, 3000, },
4129 { 4125, 3000, },
4130 { 4125, 3000, },
4131 { 4125, 3000, },
4132 { 4250, 3125, },
4133 { 4375, 3250, },
4134 { 4500, 3375, },
4135 { 4625, 3500, },
4136 { 4750, 3625, },
4137 { 4875, 3750, },
4138 { 5000, 3875, },
4139 { 5125, 4000, },
4140 { 5250, 4125, },
4141 { 5375, 4250, },
4142 { 5500, 4375, },
4143 { 5625, 4500, },
4144 { 5750, 4625, },
4145 { 5875, 4750, },
4146 { 6000, 4875, },
4147 { 6125, 5000, },
4148 { 6250, 5125, },
4149 { 6375, 5250, },
4150 { 6500, 5375, },
4151 { 6625, 5500, },
4152 { 6750, 5625, },
4153 { 6875, 5750, },
4154 { 7000, 5875, },
4155 { 7125, 6000, },
4156 { 7250, 6125, },
4157 { 7375, 6250, },
4158 { 7500, 6375, },
4159 { 7625, 6500, },
4160 { 7750, 6625, },
4161 { 7875, 6750, },
4162 { 8000, 6875, },
4163 { 8125, 7000, },
4164 { 8250, 7125, },
4165 { 8375, 7250, },
4166 { 8500, 7375, },
4167 { 8625, 7500, },
4168 { 8750, 7625, },
4169 { 8875, 7750, },
4170 { 9000, 7875, },
4171 { 9125, 8000, },
4172 { 9250, 8125, },
4173 { 9375, 8250, },
4174 { 9500, 8375, },
4175 { 9625, 8500, },
4176 { 9750, 8625, },
4177 { 9875, 8750, },
4178 { 10000, 8875, },
4179 { 10125, 9000, },
4180 { 10250, 9125, },
4181 { 10375, 9250, },
4182 { 10500, 9375, },
4183 { 10625, 9500, },
4184 { 10750, 9625, },
4185 { 10875, 9750, },
4186 { 11000, 9875, },
4187 { 11125, 10000, },
4188 { 11250, 10125, },
4189 { 11375, 10250, },
4190 { 11500, 10375, },
4191 { 11625, 10500, },
4192 { 11750, 10625, },
4193 { 11875, 10750, },
4194 { 12000, 10875, },
4195 { 12125, 11000, },
4196 { 12250, 11125, },
4197 { 12375, 11250, },
4198 { 12500, 11375, },
4199 { 12625, 11500, },
4200 { 12750, 11625, },
4201 { 12875, 11750, },
4202 { 13000, 11875, },
4203 { 13125, 12000, },
4204 { 13250, 12125, },
4205 { 13375, 12250, },
4206 { 13500, 12375, },
4207 { 13625, 12500, },
4208 { 13750, 12625, },
4209 { 13875, 12750, },
4210 { 14000, 12875, },
4211 { 14125, 13000, },
4212 { 14250, 13125, },
4213 { 14375, 13250, },
4214 { 14500, 13375, },
4215 { 14625, 13500, },
4216 { 14750, 13625, },
4217 { 14875, 13750, },
4218 { 15000, 13875, },
4219 { 15125, 14000, },
4220 { 15250, 14125, },
4221 { 15375, 14250, },
4222 { 15500, 14375, },
4223 { 15625, 14500, },
4224 { 15750, 14625, },
4225 { 15875, 14750, },
4226 { 16000, 14875, },
4227 { 16125, 15000, },
4228 };
3d13ef2e 4229 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4230 return v_table[pxvid].vm;
4231 else
4232 return v_table[pxvid].vd;
4233}
4234
02d71956 4235static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4236{
4237 struct timespec now, diff1;
4238 u64 diff;
4239 unsigned long diffms;
4240 u32 count;
4241
02d71956 4242 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4243
4244 getrawmonotonic(&now);
20e4d407 4245 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4246
4247 /* Don't divide by 0 */
4248 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4249 if (!diffms)
4250 return;
4251
4252 count = I915_READ(GFXEC);
4253
20e4d407
DV		 4254 if (count < dev_priv->ips.last_count2) {
4255 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4256 diff += count;
4257 } else {
20e4d407 4258 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4259 }
4260
20e4d407
DV		 4261 dev_priv->ips.last_count2 = count;
4262 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4263
4264 /* More magic constants... */
4265 diff = diff * 1181;
4266 diff = div_u64(diff, diffms * 10);
20e4d407 4267 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4268}
4269
02d71956
DV		 4270void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4271{
3d13ef2e
DL		 4272 struct drm_device *dev = dev_priv->dev;
4273
4274 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4275 return;
4276
9270388e 4277 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4278
4279 __i915_update_gfx_val(dev_priv);
4280
9270388e 4281 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4282}
4283
f531dcb2 4284static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4285{
4286 unsigned long t, corr, state1, corr2, state2;
4287 u32 pxvid, ext_v;
4288
02d71956
DV		 4289 assert_spin_locked(&mchdev_lock);
4290
b39fb297 4291 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4292 pxvid = (pxvid >> 24) & 0x7f;
4293 ext_v = pvid_to_extvid(dev_priv, pxvid);
4294
4295 state1 = ext_v;
4296
4297 t = i915_mch_val(dev_priv);
4298
4299 /* Revel in the empirically derived constants */
4300
4301 /* Correction factor in 1/100000 units */
4302 if (t > 80)
4303 corr = ((t * 2349) + 135940);
4304 else if (t >= 50)
4305 corr = ((t * 964) + 29317);
4306 else /* < 50 */
4307 corr = ((t * 301) + 1004);
4308
4309 corr = corr * ((150142 * state1) / 10000 - 78642);
4310 corr /= 100000;
20e4d407 4311 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4312
4313 state2 = (corr2 * state1) / 10000;
4314 state2 /= 100; /* convert to mW */
4315
02d71956 4316 __i915_update_gfx_val(dev_priv);
eb48eb00 4317
20e4d407 4318 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4319}
4320
f531dcb2
CW		 4321unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4322{
3d13ef2e 4323 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4324 unsigned long val;
4325
3d13ef2e 4326 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4327 return 0;
4328
4329 spin_lock_irq(&mchdev_lock);
4330
4331 val = __i915_gfx_val(dev_priv);
4332
4333 spin_unlock_irq(&mchdev_lock);
4334
4335 return val;
4336}
4337
eb48eb00
DV		 4338/**
4339 * i915_read_mch_val - return value for IPS use
4340 *
4341 * Calculate and return a value for the IPS driver to use when deciding whether
4342 * we have thermal and power headroom to increase CPU or GPU power budget.
4343 */
4344unsigned long i915_read_mch_val(void)
4345{
4346 struct drm_i915_private *dev_priv;
4347 unsigned long chipset_val, graphics_val, ret = 0;
4348
9270388e 4349 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4350 if (!i915_mch_dev)
4351 goto out_unlock;
4352 dev_priv = i915_mch_dev;
4353
f531dcb2
CW		 4354 chipset_val = __i915_chipset_val(dev_priv);
4355 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4356
4357 ret = chipset_val + graphics_val;
4358
4359out_unlock:
9270388e 4360 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4361
4362 return ret;
4363}
4364EXPORT_SYMBOL_GPL(i915_read_mch_val);
4365
4366/**
4367 * i915_gpu_raise - raise GPU frequency limit
4368 *
4369 * Raise the limit; IPS indicates we have thermal headroom.
4370 */
4371bool i915_gpu_raise(void)
4372{
4373 struct drm_i915_private *dev_priv;
4374 bool ret = true;
4375
9270388e 4376 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4377 if (!i915_mch_dev) {
4378 ret = false;
4379 goto out_unlock;
4380 }
4381 dev_priv = i915_mch_dev;
4382
20e4d407
DV		 4383 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4384 dev_priv->ips.max_delay--;
eb48eb00
DV		 4385
4386out_unlock:
9270388e 4387 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4388
4389 return ret;
4390}
4391EXPORT_SYMBOL_GPL(i915_gpu_raise);
4392
4393/**
4394 * i915_gpu_lower - lower GPU frequency limit
4395 *
4396 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4397 * frequency maximum.
4398 */
4399bool i915_gpu_lower(void)
4400{
4401 struct drm_i915_private *dev_priv;
4402 bool ret = true;
4403
9270388e 4404 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4405 if (!i915_mch_dev) {
4406 ret = false;
4407 goto out_unlock;
4408 }
4409 dev_priv = i915_mch_dev;
4410
20e4d407
DV		 4411 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4412 dev_priv->ips.max_delay++;
eb48eb00
DV		 4413
4414out_unlock:
9270388e 4415 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4416
4417 return ret;
4418}
4419EXPORT_SYMBOL_GPL(i915_gpu_lower);
4420
4421/**
4422 * i915_gpu_busy - indicate GPU business to IPS
4423 *
4424 * Tell the IPS driver whether or not the GPU is busy.
4425 */
4426bool i915_gpu_busy(void)
4427{
4428 struct drm_i915_private *dev_priv;
f047e395 4429 struct intel_ring_buffer *ring;
eb48eb00 4430 bool ret = false;
f047e395 4431 int i;
eb48eb00 4432
9270388e 4433 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4434 if (!i915_mch_dev)
4435 goto out_unlock;
4436 dev_priv = i915_mch_dev;
4437
f047e395
CW		 4438 for_each_ring(ring, dev_priv, i)
4439 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4440
4441out_unlock:
9270388e 4442 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4443
4444 return ret;
4445}
4446EXPORT_SYMBOL_GPL(i915_gpu_busy);
4447
4448/**
4449 * i915_gpu_turbo_disable - disable graphics turbo
4450 *
4451 * Disable graphics turbo by resetting the max frequency and setting the
4452 * current frequency to the default.
4453 */
4454bool i915_gpu_turbo_disable(void)
4455{
4456 struct drm_i915_private *dev_priv;
4457 bool ret = true;
4458
9270388e 4459 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4460 if (!i915_mch_dev) {
4461 ret = false;
4462 goto out_unlock;
4463 }
4464 dev_priv = i915_mch_dev;
4465
20e4d407 4466 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4467
20e4d407 4468 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4469 ret = false;
4470
4471out_unlock:
9270388e 4472 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4473
4474 return ret;
4475}
4476EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4477
4478/**
4479 * Tells the intel_ips driver that the i915 driver is now loaded, if
4480 * IPS got loaded first.
4481 *
4482 * This awkward dance is so that neither module has to depend on the
4483 * other in order for IPS to do the appropriate communication of
4484 * GPU turbo limits to i915.
4485 */
4486static void
4487ips_ping_for_i915_load(void)
4488{
4489 void (*link)(void);
4490
4491 link = symbol_get(ips_link_to_i915_driver);
4492 if (link) {
4493 link();
4494 symbol_put(ips_link_to_i915_driver);
4495 }
4496}
4497
4498void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4499{
02d71956
DV		 4500 /* We only register the i915 ips part with intel-ips once everything is
4501 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4502 spin_lock_irq(&mchdev_lock);
eb48eb00 4503 i915_mch_dev = dev_priv;
9270388e 4504 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4505
4506 ips_ping_for_i915_load();
4507}
4508
4509void intel_gpu_ips_teardown(void)
4510{
9270388e 4511 spin_lock_irq(&mchdev_lock);
eb48eb00 4512 i915_mch_dev = NULL;
9270388e 4513 spin_unlock_irq(&mchdev_lock);
eb48eb00 4514}
76c3552f 4515
8090c6b9 4516static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4517{
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519 u32 lcfuse;
4520 u8 pxw[16];
4521 int i;
4522
4523 /* Disable to program */
4524 I915_WRITE(ECR, 0);
4525 POSTING_READ(ECR);
4526
4527 /* Program energy weights for various events */
4528 I915_WRITE(SDEW, 0x15040d00);
4529 I915_WRITE(CSIEW0, 0x007f0000);
4530 I915_WRITE(CSIEW1, 0x1e220004);
4531 I915_WRITE(CSIEW2, 0x04000004);
4532
4533 for (i = 0; i < 5; i++)
4534 I915_WRITE(PEW + (i * 4), 0);
4535 for (i = 0; i < 3; i++)
4536 I915_WRITE(DEW + (i * 4), 0);
4537
4538 /* Program P-state weights to account for frequency power adjustment */
4539 for (i = 0; i < 16; i++) {
4540 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4541 unsigned long freq = intel_pxfreq(pxvidfreq);
4542 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4543 PXVFREQ_PX_SHIFT;
4544 unsigned long val;
4545
4546 val = vid * vid;
4547 val *= (freq / 1000);
4548 val *= 255;
4549 val /= (127*127*900);
4550 if (val > 0xff)
4551 DRM_ERROR("bad pxval: %ld\n", val);
4552 pxw[i] = val;
4553 }
4554 /* Render standby states get 0 weight */
4555 pxw[14] = 0;
4556 pxw[15] = 0;
4557
4558 for (i = 0; i < 4; i++) {
4559 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4560 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4561 I915_WRITE(PXW + (i * 4), val);
4562 }
4563
4564 /* Adjust magic regs to magic values (more experimental results) */
4565 I915_WRITE(OGW0, 0);
4566 I915_WRITE(OGW1, 0);
4567 I915_WRITE(EG0, 0x00007f00);
4568 I915_WRITE(EG1, 0x0000000e);
4569 I915_WRITE(EG2, 0x000e0000);
4570 I915_WRITE(EG3, 0x68000300);
4571 I915_WRITE(EG4, 0x42000000);
4572 I915_WRITE(EG5, 0x00140031);
4573 I915_WRITE(EG6, 0);
4574 I915_WRITE(EG7, 0);
4575
4576 for (i = 0; i < 8; i++)
4577 I915_WRITE(PXWL + (i * 4), 0);
4578
4579 /* Enable PMON + select events */
4580 I915_WRITE(ECR, 0x80000019);
4581
4582 lcfuse = I915_READ(LCFUSE02);
4583
20e4d407 4584 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4585}
4586
ae48434c
ID		 4587void intel_init_gt_powersave(struct drm_device *dev)
4588{
e6069ca8
ID		 4589 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4590
ae48434c 4591 if (IS_VALLEYVIEW(dev))
4e80519e 4592 valleyview_init_gt_powersave(dev);
ae48434c
ID		 4593}
4594
4595void intel_cleanup_gt_powersave(struct drm_device *dev)
4596{
4597 if (IS_VALLEYVIEW(dev))
4e80519e 4598 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 4599}
4600
8090c6b9
DV		 4601void intel_disable_gt_powersave(struct drm_device *dev)
4602{
1a01ab3b
JB		 4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604
fd0c0642
DV		 4605 /* Interrupts should be disabled already to avoid re-arming. */
4606 WARN_ON(dev->irq_enabled);
4607
930ebb46 4608 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4609 ironlake_disable_drps(dev);
930ebb46 4610 ironlake_disable_rc6(dev);
14dd0ea8 4611 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b 4612 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4613 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4614 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4615 if (IS_VALLEYVIEW(dev))
4616 valleyview_disable_rps(dev);
4617 else
4618 gen6_disable_rps(dev);
c0951f0c 4619 dev_priv->rps.enabled = false;
4fc688ce 4620 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4621 }
8090c6b9
DV		 4622}
4623
1a01ab3b
JB		 4624static void intel_gen6_powersave_work(struct work_struct *work)
4625{
4626 struct drm_i915_private *dev_priv =
4627 container_of(work, struct drm_i915_private,
4628 rps.delayed_resume_work.work);
4629 struct drm_device *dev = dev_priv->dev;
4630
4fc688ce 4631 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4632
4633 if (IS_VALLEYVIEW(dev)) {
4634 valleyview_enable_rps(dev);
6edee7f3
BW		 4635 } else if (IS_BROADWELL(dev)) {
4636 gen8_enable_rps(dev);
c2bc2fc5 4637 __gen6_update_ring_freq(dev);
0a073b84
JB		 4638 } else {
4639 gen6_enable_rps(dev);
c2bc2fc5 4640 __gen6_update_ring_freq(dev);
0a073b84 4641 }
c0951f0c 4642 dev_priv->rps.enabled = true;
4fc688ce 4643 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 4644
4645 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 4646}
4647
8090c6b9
DV		 4648void intel_enable_gt_powersave(struct drm_device *dev)
4649{
1a01ab3b
JB		 4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651
8090c6b9 4652 if (IS_IRONLAKE_M(dev)) {
dc1d0136 4653 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 4654 ironlake_enable_drps(dev);
4655 ironlake_enable_rc6(dev);
4656 intel_init_emon(dev);
dc1d0136 4657 mutex_unlock(&dev->struct_mutex);
0a073b84 4658 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4659 /*
4660 * PCU communication is slow and this doesn't need to be
4661 * done at any specific time, so do this out of our fast path
4662 * to make resume and init faster.
c6df39b5
ID		 4663 *
4664 * We depend on the HW RC6 power context save/restore
4665 * mechanism when entering D3 through runtime PM suspend. So
4666 * disable RPM until RPS/RC6 is properly setup. We can only
4667 * get here via the driver load/system resume/runtime resume
4668 * paths, so the _noresume version is enough (and in case of
4669 * runtime resume it's necessary).
1a01ab3b 4670 */
c6df39b5
ID		 4671 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4672 round_jiffies_up_relative(HZ)))
4673 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 4674 }
4675}
4676
c6df39b5
ID		 4677void intel_reset_gt_powersave(struct drm_device *dev)
4678{
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680
4681 dev_priv->rps.enabled = false;
4682 intel_enable_gt_powersave(dev);
4683}
4684
3107bd48
DV		 4685static void ibx_init_clock_gating(struct drm_device *dev)
4686{
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688
4689 /*
4690 * On Ibex Peak and Cougar Point, we need to disable clock
4691 * gating for the panel power sequencer or it will fail to
4692 * start up when no ports are active.
4693 */
4694 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4695}
4696
0e088b8f
VS		 4697static void g4x_disable_trickle_feed(struct drm_device *dev)
4698{
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 int pipe;
4701
4702 for_each_pipe(pipe) {
4703 I915_WRITE(DSPCNTR(pipe),
4704 I915_READ(DSPCNTR(pipe)) |
4705 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4706 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4707 }
4708}
4709
017636cc
VS		 4710static void ilk_init_lp_watermarks(struct drm_device *dev)
4711{
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4713
4714 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4715 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4716 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4717
4718 /*
4719 * Don't touch WM1S_LP_EN here.
4720 * Doing so could cause underruns.
4721 */
4722}
4723
1fa61106 4724static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4725{
4726 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4727 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4728
f1e8fa56
DL		 4729 /*
4730 * Required for FBC
4731 * WaFbcDisableDpfcClockGating:ilk
4732 */
4d47e4f5
DL		 4733 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4734 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4735 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4736
4737 I915_WRITE(PCH_3DCGDIS0,
4738 MARIUNIT_CLOCK_GATE_DISABLE |
4739 SVSMUNIT_CLOCK_GATE_DISABLE);
4740 I915_WRITE(PCH_3DCGDIS1,
4741 VFMUNIT_CLOCK_GATE_DISABLE);
4742
6f1d69b0
ED		 4743 /*
4744 * According to the spec the following bits should be set in
4745 * order to enable memory self-refresh
4746 * The bit 22/21 of 0x42004
4747 * The bit 5 of 0x42020
4748 * The bit 15 of 0x45000
4749 */
4750 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4751 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4752 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4753 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4754 I915_WRITE(DISP_ARB_CTL,
4755 (I915_READ(DISP_ARB_CTL) |
4756 DISP_FBC_WM_DIS));
017636cc
VS		 4757
4758 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 4759
4760 /*
4761 * Based on the document from hardware guys the following bits
4762 * should be set unconditionally in order to enable FBC.
4763 * The bit 22 of 0x42000
4764 * The bit 22 of 0x42004
4765 * The bit 7,8,9 of 0x42020.
4766 */
4767 if (IS_IRONLAKE_M(dev)) {
4bb35334 4768 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4769 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4770 I915_READ(ILK_DISPLAY_CHICKEN1) |
4771 ILK_FBCQ_DIS);
4772 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4773 I915_READ(ILK_DISPLAY_CHICKEN2) |
4774 ILK_DPARB_GATE);
6f1d69b0
ED		 4775 }
4776
4d47e4f5
DL		 4777 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4778
6f1d69b0
ED		 4779 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4780 I915_READ(ILK_DISPLAY_CHICKEN2) |
4781 ILK_ELPIN_409_SELECT);
4782 I915_WRITE(_3D_CHICKEN2,
4783 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4784 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4785
ecdb4eb7 4786 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4787 I915_WRITE(CACHE_MODE_0,
4788 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4789
4e04632e
AG		 4790 /* WaDisable_RenderCache_OperationalFlush:ilk */
4791 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4792
0e088b8f 4793 g4x_disable_trickle_feed(dev);
bdad2b2f 4794
3107bd48
DV		 4795 ibx_init_clock_gating(dev);
4796}
4797
4798static void cpt_init_clock_gating(struct drm_device *dev)
4799{
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801 int pipe;
3f704fa2 4802 uint32_t val;
3107bd48
DV		 4803
4804 /*
4805 * On Ibex Peak and Cougar Point, we need to disable clock
4806 * gating for the panel power sequencer or it will fail to
4807 * start up when no ports are active.
4808 */
cd664078
JB		 4809 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4810 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4811 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 4812 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4813 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4814 /* The below fixes the weird display corruption, a few pixels shifted
4815 * downward, on (only) LVDS of some HP laptops with IVY.
4816 */
3f704fa2 4817 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4818 val = I915_READ(TRANS_CHICKEN2(pipe));
4819 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4820 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4821 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4822 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4823 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4824 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4825 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4826 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4827 }
3107bd48
DV		 4828 /* WADP0ClockGatingDisable */
4829 for_each_pipe(pipe) {
4830 I915_WRITE(TRANS_CHICKEN1(pipe),
4831 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4832 }
6f1d69b0
ED		 4833}
4834
1d7aaa0c
DV		 4835static void gen6_check_mch_setup(struct drm_device *dev)
4836{
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 uint32_t tmp;
4839
4840 tmp = I915_READ(MCH_SSKPD);
4841 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4842 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4843 DRM_INFO("This can cause pipe underruns and display issues.\n");
4844 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4845 }
4846}
4847
1fa61106 4848static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4849{
4850 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4851 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4852
231e54f6 4853 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4854
4855 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4856 I915_READ(ILK_DISPLAY_CHICKEN2) |
4857 ILK_ELPIN_409_SELECT);
4858
ecdb4eb7 4859 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4860 I915_WRITE(_3D_CHICKEN,
4861 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4862
ecdb4eb7 4863 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4864 if (IS_SNB_GT1(dev))
4865 I915_WRITE(GEN6_GT_MODE,
4866 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4867
4e04632e
AG		 4868 /* WaDisable_RenderCache_OperationalFlush:snb */
4869 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4870
8d85d272
VS		 4871 /*
4872 * BSpec recoomends 8x4 when MSAA is used,
4873 * however in practice 16x4 seems fastest.
c5c98a58
VS		 4874 *
4875 * Note that PS/WM thread counts depend on the WIZ hashing
4876 * disable bit, which we don't touch here, but it's good
4877 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 4878 */
4879 I915_WRITE(GEN6_GT_MODE,
4880 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4881
017636cc 4882 ilk_init_lp_watermarks(dev);
6f1d69b0 4883
6f1d69b0 4884 I915_WRITE(CACHE_MODE_0,
50743298 4885 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4886
4887 I915_WRITE(GEN6_UCGCTL1,
4888 I915_READ(GEN6_UCGCTL1) |
4889 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4890 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4891
4892 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4893 * gating disable must be set. Failure to set it results in
4894 * flickering pixels due to Z write ordering failures after
4895 * some amount of runtime in the Mesa "fire" demo, and Unigine
4896 * Sanctuary and Tropics, and apparently anything else with
4897 * alpha test or pixel discard.
4898 *
4899 * According to the spec, bit 11 (RCCUNIT) must also be set,
4900 * but we didn't debug actual testcases to find it out.
0f846f81 4901 *
ef59318c
VS		 4902 * WaDisableRCCUnitClockGating:snb
4903 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 4904 */
4905 I915_WRITE(GEN6_UCGCTL2,
4906 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4907 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4908
5eb146dd 4909 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 4910 I915_WRITE(_3D_CHICKEN3,
4911 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 4912
e927ecde
VS		 4913 /*
4914 * Bspec says:
4915 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4916 * 3DSTATE_SF number of SF output attributes is more than 16."
4917 */
4918 I915_WRITE(_3D_CHICKEN3,
4919 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4920
6f1d69b0
ED		 4921 /*
4922 * According to the spec the following bits should be
4923 * set in order to enable memory self-refresh and fbc:
4924 * The bit21 and bit22 of 0x42000
4925 * The bit21 and bit22 of 0x42004
4926 * The bit5 and bit7 of 0x42020
4927 * The bit14 of 0x70180
4928 * The bit14 of 0x71180
4bb35334
DL		 4929 *
4930 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4931 */
4932 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4933 I915_READ(ILK_DISPLAY_CHICKEN1) |
4934 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4935 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4936 I915_READ(ILK_DISPLAY_CHICKEN2) |
4937 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4938 I915_WRITE(ILK_DSPCLK_GATE_D,
4939 I915_READ(ILK_DSPCLK_GATE_D) |
4940 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4941 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4942
0e088b8f 4943 g4x_disable_trickle_feed(dev);
f8f2ac9a 4944
3107bd48 4945 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4946
4947 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4948}
4949
4950static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4951{
4952 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4953
3aad9059 4954 /*
46680e0a 4955 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 4956 *
4957 * This actually overrides the dispatch
4958 * mode for all thread types.
4959 */
6f1d69b0
ED		 4960 reg &= ~GEN7_FF_SCHED_MASK;
4961 reg |= GEN7_FF_TS_SCHED_HW;
4962 reg |= GEN7_FF_VS_SCHED_HW;
4963 reg |= GEN7_FF_DS_SCHED_HW;
4964
4965 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4966}
4967
17a303ec
PZ		 4968static void lpt_init_clock_gating(struct drm_device *dev)
4969{
4970 struct drm_i915_private *dev_priv = dev->dev_private;
4971
4972 /*
4973 * TODO: this bit should only be enabled when really needed, then
4974 * disabled when not needed anymore in order to save power.
4975 */
4976 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4977 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4978 I915_READ(SOUTH_DSPCLK_GATE_D) |
4979 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4980
4981 /* WADPOClockGatingDisable:hsw */
4982 I915_WRITE(_TRANSA_CHICKEN1,
4983 I915_READ(_TRANSA_CHICKEN1) |
4984 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4985}
4986
7d708ee4
ID		 4987static void lpt_suspend_hw(struct drm_device *dev)
4988{
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990
4991 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4992 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4993
4994 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4995 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4996 }
4997}
4998
1020a5c2
BW		 4999static void gen8_init_clock_gating(struct drm_device *dev)
5000{
5001 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5002 enum pipe pipe;
1020a5c2
BW		 5003
5004 I915_WRITE(WM3_LP_ILK, 0);
5005 I915_WRITE(WM2_LP_ILK, 0);
5006 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5007
5008 /* FIXME(BDW): Check all the w/a, some might only apply to
5009 * pre-production hw. */
5010
c8966e10
KG		 5011 /* WaDisablePartialInstShootdown:bdw */
5012 I915_WRITE(GEN8_ROW_CHICKEN,
5013 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5014
1411e6a5
KG		 5015 /* WaDisableThreadStallDopClockGating:bdw */
5016 /* FIXME: Unclear whether we really need this on production bdw. */
5017 I915_WRITE(GEN8_ROW_CHICKEN,
5018 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5019
4167e32c
DL		 5020 /*
5021 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5022 * pre-production hardware
5023 */
fd392b60
BW		 5024 I915_WRITE(HALF_SLICE_CHICKEN3,
5025 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5026 I915_WRITE(HALF_SLICE_CHICKEN3,
5027 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5028 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5029
7f88da0c
BW		 5030 I915_WRITE(_3D_CHICKEN3,
5031 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5032
a75f3628
BW		 5033 I915_WRITE(COMMON_SLICE_CHICKEN2,
5034 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5035
4c2e7a5f
BW		 5036 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5037 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5038
242a4018
BW		 5039 /* WaDisableDopClockGating:bdw May not be needed for production */
5040 I915_WRITE(GEN7_ROW_CHICKEN2,
5041 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5042
ab57fff1 5043 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5044 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5045
ab57fff1 5046 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5047 I915_WRITE(CHICKEN_PAR1_1,
5048 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5049
ab57fff1 5050 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 5051 for_each_pipe(pipe) {
5052 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5053 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5054 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5055 }
63801f21
BW		 5056
5057 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5058 * workaround for for a possible hang in the unlikely event a TLB
5059 * invalidation occurs during a PSD flush.
5060 */
5061 I915_WRITE(HDC_CHICKEN0,
5062 I915_READ(HDC_CHICKEN0) |
5063 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5064
5065 /* WaVSRefCountFullforceMissDisable:bdw */
5066 /* WaDSRefCountFullforceMissDisable:bdw */
5067 I915_WRITE(GEN7_FF_THREAD_MODE,
5068 I915_READ(GEN7_FF_THREAD_MODE) &
5069 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5070
5071 /*
5072 * BSpec recommends 8x4 when MSAA is used,
5073 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5074 *
5075 * Note that PS/WM thread counts depend on the WIZ hashing
5076 * disable bit, which we don't touch here, but it's good
5077 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5078 */
5079 I915_WRITE(GEN7_GT_MODE,
5080 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5081
5082 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5083 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5084
5085 /* WaDisableSDEUnitClockGating:bdw */
5086 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5087 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5088
5089 /* Wa4x4STCOptimizationDisable:bdw */
5090 I915_WRITE(CACHE_MODE_1,
5091 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5092}
5093
cad2a2d7
ED		 5094static void haswell_init_clock_gating(struct drm_device *dev)
5095{
5096 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5097
017636cc 5098 ilk_init_lp_watermarks(dev);
cad2a2d7 5099
f3fc4884
FJ		 5100 /* L3 caching of data atomics doesn't work -- disable it. */
5101 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5102 I915_WRITE(HSW_ROW_CHICKEN3,
5103 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5104
ecdb4eb7 5105 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5106 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5107 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5108 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5109
e36ea7ff
VS		 5110 /* WaVSRefCountFullforceMissDisable:hsw */
5111 I915_WRITE(GEN7_FF_THREAD_MODE,
5112 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5113
4e04632e
AG		 5114 /* WaDisable_RenderCache_OperationalFlush:hsw */
5115 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5116
fe27c606
CW		 5117 /* enable HiZ Raw Stall Optimization */
5118 I915_WRITE(CACHE_MODE_0_GEN7,
5119 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5120
ecdb4eb7 5121 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5122 I915_WRITE(CACHE_MODE_1,
5123 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5124
a12c4967
VS		 5125 /*
5126 * BSpec recommends 8x4 when MSAA is used,
5127 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5128 *
5129 * Note that PS/WM thread counts depend on the WIZ hashing
5130 * disable bit, which we don't touch here, but it's good
5131 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5132 */
5133 I915_WRITE(GEN7_GT_MODE,
5134 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5135
ecdb4eb7 5136 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5137 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5138
90a88643
PZ		 5139 /* WaRsPkgCStateDisplayPMReq:hsw */
5140 I915_WRITE(CHICKEN_PAR1_1,
5141 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5142
17a303ec 5143 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5144}
5145
1fa61106 5146static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5147{
5148 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5149 uint32_t snpcr;
6f1d69b0 5150
017636cc 5151 ilk_init_lp_watermarks(dev);
6f1d69b0 5152
231e54f6 5153 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5154
ecdb4eb7 5155 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5156 I915_WRITE(_3D_CHICKEN3,
5157 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5158
ecdb4eb7 5159 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5160 I915_WRITE(IVB_CHICKEN3,
5161 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5162 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5163
ecdb4eb7 5164 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5165 if (IS_IVB_GT1(dev))
5166 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5167 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5168
4e04632e
AG		 5169 /* WaDisable_RenderCache_OperationalFlush:ivb */
5170 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5171
ecdb4eb7 5172 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5173 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5174 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5175
ecdb4eb7 5176 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5177 I915_WRITE(GEN7_L3CNTLREG1,
5178 GEN7_WA_FOR_GEN7_L3_CONTROL);
5179 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5180 GEN7_WA_L3_CHICKEN_MODE);
5181 if (IS_IVB_GT1(dev))
5182 I915_WRITE(GEN7_ROW_CHICKEN2,
5183 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5184 else {
5185 /* must write both registers */
5186 I915_WRITE(GEN7_ROW_CHICKEN2,
5187 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5188 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5189 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5190 }
6f1d69b0 5191
ecdb4eb7 5192 /* WaForceL3Serialization:ivb */
61939d97
JB		 5193 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5194 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5195
1b80a19a 5196 /*
0f846f81 5197 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5198 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5199 */
5200 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5201 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5202
ecdb4eb7 5203 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5204 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5205 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5206 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5207
0e088b8f 5208 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5209
5210 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5211
22721343
CW		 5212 if (0) { /* causes HiZ corruption on ivb:gt1 */
5213 /* enable HiZ Raw Stall Optimization */
5214 I915_WRITE(CACHE_MODE_0_GEN7,
5215 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5216 }
116f2b6d 5217
ecdb4eb7 5218 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5219 I915_WRITE(CACHE_MODE_1,
5220 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5221
a607c1a4
VS		 5222 /*
5223 * BSpec recommends 8x4 when MSAA is used,
5224 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5225 *
5226 * Note that PS/WM thread counts depend on the WIZ hashing
5227 * disable bit, which we don't touch here, but it's good
5228 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5229 */
5230 I915_WRITE(GEN7_GT_MODE,
5231 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5232
20848223
BW		 5233 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5234 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5235 snpcr |= GEN6_MBC_SNPCR_MED;
5236 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5237
ab5c608b
BW		 5238 if (!HAS_PCH_NOP(dev))
5239 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5240
5241 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5242}
5243
1fa61106 5244static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5245{
5246 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5247 u32 val;
5248
5249 mutex_lock(&dev_priv->rps.hw_lock);
5250 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5251 mutex_unlock(&dev_priv->rps.hw_lock);
5252 switch ((val >> 6) & 3) {
5253 case 0:
f64a28a7 5254 case 1:
f6d51948 5255 dev_priv->mem_freq = 800;
85b1d7b3 5256 break;
f64a28a7 5257 case 2:
f6d51948 5258 dev_priv->mem_freq = 1066;
85b1d7b3 5259 break;
f64a28a7 5260 case 3:
2325991e 5261 dev_priv->mem_freq = 1333;
f64a28a7 5262 break;
85b1d7b3
JB		 5263 }
5264 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5265
d60c4473
ID		 5266 dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5267 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5268 dev_priv->vlv_cdclk_freq);
5269
d7fe0cc0 5270 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5271
ecdb4eb7 5272 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5273 I915_WRITE(_3D_CHICKEN3,
5274 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5275
ecdb4eb7 5276 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5277 I915_WRITE(IVB_CHICKEN3,
5278 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5279 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5280
fad7d36e 5281 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5282 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5283 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5284 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5285 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5286
4e04632e
AG		 5287 /* WaDisable_RenderCache_OperationalFlush:vlv */
5288 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5289
ecdb4eb7 5290 /* WaForceL3Serialization:vlv */
61939d97
JB		 5291 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5292 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5293
ecdb4eb7 5294 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5295 I915_WRITE(GEN7_ROW_CHICKEN2,
5296 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5297
ecdb4eb7 5298 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5299 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5300 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5301 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5302
46680e0a
VS		 5303 gen7_setup_fixed_func_scheduler(dev_priv);
5304
3c0edaeb 5305 /*
0f846f81 5306 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5307 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5308 */
5309 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5310 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5311
c5c32cda 5312 /* WaDisableL3Bank2xClockGate:vlv */
e3f33d46
JB		 5313 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5314
e0d8d59b 5315 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5316
afd58e79
VS		 5317 /*
5318 * BSpec says this must be set, even though
5319 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5320 */
6b26c86d
DV		 5321 I915_WRITE(CACHE_MODE_1,
5322 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5323
031994ee
VS		 5324 /*
5325 * WaIncreaseL3CreditsForVLVB0:vlv
5326 * This is the hardware default actually.
5327 */
5328 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5329
2d809570 5330 /*
ecdb4eb7 5331 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5332 * Disable clock gating on th GCFG unit to prevent a delay
5333 * in the reporting of vblank events.
5334 */
7a0d1eed 5335 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5336}
5337
1fa61106 5338static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5339{
5340 struct drm_i915_private *dev_priv = dev->dev_private;
5341 uint32_t dspclk_gate;
5342
5343 I915_WRITE(RENCLK_GATE_D1, 0);
5344 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5345 GS_UNIT_CLOCK_GATE_DISABLE |
5346 CL_UNIT_CLOCK_GATE_DISABLE);
5347 I915_WRITE(RAMCLK_GATE_D, 0);
5348 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5349 OVRUNIT_CLOCK_GATE_DISABLE |
5350 OVCUNIT_CLOCK_GATE_DISABLE;
5351 if (IS_GM45(dev))
5352 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5353 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5354
5355 /* WaDisableRenderCachePipelinedFlush */
5356 I915_WRITE(CACHE_MODE_0,
5357 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5358
4e04632e
AG		 5359 /* WaDisable_RenderCache_OperationalFlush:g4x */
5360 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5361
0e088b8f 5362 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5363}
5364
1fa61106 5365static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5366{
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368
5369 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5370 I915_WRITE(RENCLK_GATE_D2, 0);
5371 I915_WRITE(DSPCLK_GATE_D, 0);
5372 I915_WRITE(RAMCLK_GATE_D, 0);
5373 I915_WRITE16(DEUC, 0);
20f94967
VS		 5374 I915_WRITE(MI_ARB_STATE,
5375 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5376
5377 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5378 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5379}
5380
1fa61106 5381static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5382{
5383 struct drm_i915_private *dev_priv = dev->dev_private;
5384
5385 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5386 I965_RCC_CLOCK_GATE_DISABLE |
5387 I965_RCPB_CLOCK_GATE_DISABLE |
5388 I965_ISC_CLOCK_GATE_DISABLE |
5389 I965_FBC_CLOCK_GATE_DISABLE);
5390 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5391 I915_WRITE(MI_ARB_STATE,
5392 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5393
5394 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5395 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5396}
5397
1fa61106 5398static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5399{
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 u32 dstate = I915_READ(D_STATE);
5402
5403 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5404 DSTATE_DOT_CLOCK_GATING;
5405 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5406
5407 if (IS_PINEVIEW(dev))
5408 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5409
5410 /* IIR "flip pending" means done if this bit is set */
5411 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5412}
5413
1fa61106 5414static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5415{
5416 struct drm_i915_private *dev_priv = dev->dev_private;
5417
5418 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5419}
5420
1fa61106 5421static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5422{
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5424
5425 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5426}
5427
6f1d69b0
ED		 5428void intel_init_clock_gating(struct drm_device *dev)
5429{
5430 struct drm_i915_private *dev_priv = dev->dev_private;
5431
5432 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5433}
5434
7d708ee4
ID		 5435void intel_suspend_hw(struct drm_device *dev)
5436{
5437 if (HAS_PCH_LPT(dev))
5438 lpt_suspend_hw(dev);
5439}
5440
c1ca727f
ID		 5441#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5442 for (i = 0; \
5443 i < (power_domains)->power_well_count && \
5444 ((power_well) = &(power_domains)->power_wells[i]); \
5445 i++) \
5446 if ((power_well)->domains & (domain_mask))
5447
5448#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5449 for (i = (power_domains)->power_well_count - 1; \
5450 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5451 i--) \
5452 if ((power_well)->domains & (domain_mask))
5453
15d199ea
PZ		 5454/**
5455 * We should only use the power well if we explicitly asked the hardware to
5456 * enable it, so check if it's enabled and also check if we've requested it to
5457 * be enabled.
5458 */
da7e29bd 5459static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5460 struct i915_power_well *power_well)
5461{
c1ca727f
ID		 5462 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5463 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5464}
5465
da7e29bd 5466bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536
ID		 5467 enum intel_display_power_domain domain)
5468{
ddf9c536
ID		 5469 struct i915_power_domains *power_domains;
5470
5471 power_domains = &dev_priv->power_domains;
5472
5473 return power_domains->domain_use_count[domain];
5474}
5475
da7e29bd 5476bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5477 enum intel_display_power_domain domain)
15d199ea 5478{
c1ca727f
ID		 5479 struct i915_power_domains *power_domains;
5480 struct i915_power_well *power_well;
5481 bool is_enabled;
5482 int i;
15d199ea 5483
882244a3
PZ		 5484 if (dev_priv->pm.suspended)
5485 return false;
5486
c1ca727f
ID		 5487 power_domains = &dev_priv->power_domains;
5488
5489 is_enabled = true;
5490
5491 mutex_lock(&power_domains->lock);
5492 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5493 if (power_well->always_on)
5494 continue;
5495
c6cb582e 5496 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
c1ca727f
ID		 5497 is_enabled = false;
5498 break;
5499 }
5500 }
5501 mutex_unlock(&power_domains->lock);
5502
5503 return is_enabled;
15d199ea
PZ		 5504}
5505
93c73e8c
ID		 5506/*
5507 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5508 * when not needed anymore. We have 4 registers that can request the power well
5509 * to be enabled, and it will only be disabled if none of the registers is
5510 * requesting it to be enabled.
5511 */
d5e8fdc8
PZ		 5512static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5513{
5514 struct drm_device *dev = dev_priv->dev;
5515 unsigned long irqflags;
5516
f9dcb0df
PZ		 5517 /*
5518 * After we re-enable the power well, if we touch VGA register 0x3d5
5519 * we'll get unclaimed register interrupts. This stops after we write
5520 * anything to the VGA MSR register. The vgacon module uses this
5521 * register all the time, so if we unbind our driver and, as a
5522 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5523 * console_unlock(). So make here we touch the VGA MSR register, making
5524 * sure vgacon can keep working normally without triggering interrupts
5525 * and error messages.
5526 */
5527 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5528 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5529 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5530
d5e8fdc8
PZ		 5531 if (IS_BROADWELL(dev)) {
5532 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5533 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5534 dev_priv->de_irq_mask[PIPE_B]);
5535 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5536 ~dev_priv->de_irq_mask[PIPE_B] |
5537 GEN8_PIPE_VBLANK);
5538 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5539 dev_priv->de_irq_mask[PIPE_C]);
5540 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5541 ~dev_priv->de_irq_mask[PIPE_C] |
5542 GEN8_PIPE_VBLANK);
5543 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5544 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5545 }
5546}
5547
dd7c0b66
ID		 5548static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5549{
5550 assert_spin_locked(&dev->vbl_lock);
5551
5552 dev->vblank[pipe].last = 0;
5553}
5554
d5e8fdc8
PZ		 5555static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5556{
5557 struct drm_device *dev = dev_priv->dev;
07d27e20 5558 enum pipe pipe;
d5e8fdc8
PZ		 5559 unsigned long irqflags;
5560
5561 /*
5562 * After this, the registers on the pipes that are part of the power
5563 * well will become zero, so we have to adjust our counters according to
5564 * that.
5565 *
5566 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5567 */
5568 spin_lock_irqsave(&dev->vbl_lock, irqflags);
07d27e20
DL		 5569 for_each_pipe(pipe)
5570 if (pipe != PIPE_A)
dd7c0b66 5571 reset_vblank_counter(dev, pipe);
d5e8fdc8
PZ		 5572 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5573}
5574
da7e29bd 5575static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 5576 struct i915_power_well *power_well, bool enable)
d0d3e513 5577{
fa42e23c
PZ		 5578 bool is_enabled, enable_requested;
5579 uint32_t tmp;
d0d3e513 5580
fa42e23c 5581 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5582 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5583 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5584
fa42e23c
PZ		 5585 if (enable) {
5586 if (!enable_requested)
6aedd1f5
PZ		 5587 I915_WRITE(HSW_PWR_WELL_DRIVER,
5588 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5589
fa42e23c
PZ		 5590 if (!is_enabled) {
5591 DRM_DEBUG_KMS("Enabling power well\n");
5592 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5593 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5594 DRM_ERROR("Timeout enabling power well\n");
5595 }
596cc11e 5596
d5e8fdc8 5597 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5598 } else {
5599 if (enable_requested) {
5600 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5601 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5602 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5603
d5e8fdc8 5604 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5605 }
5606 }
fa42e23c 5607}
d0d3e513 5608
c6cb582e
ID		 5609static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5610 struct i915_power_well *power_well)
5611{
5612 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5613
5614 /*
5615 * We're taking over the BIOS, so clear any requests made by it since
5616 * the driver is in charge now.
5617 */
5618 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5619 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5620}
5621
5622static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5623 struct i915_power_well *power_well)
5624{
c6cb582e
ID		 5625 hsw_set_power_well(dev_priv, power_well, true);
5626}
5627
5628static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5629 struct i915_power_well *power_well)
5630{
5631 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 5632}
5633
a45f4466
ID		 5634static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5635 struct i915_power_well *power_well)
5636{
5637}
5638
5639static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5640 struct i915_power_well *power_well)
5641{
5642 return true;
5643}
5644
77961eb9
ID		 5645static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5646 struct i915_power_well *power_well, bool enable)
5647{
5648 enum punit_power_well power_well_id = power_well->data;
5649 u32 mask;
5650 u32 state;
5651 u32 ctrl;
5652
5653 mask = PUNIT_PWRGT_MASK(power_well_id);
5654 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5655 PUNIT_PWRGT_PWR_GATE(power_well_id);
5656
5657 mutex_lock(&dev_priv->rps.hw_lock);
5658
5659#define COND \
5660 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5661
5662 if (COND)
5663 goto out;
5664
5665 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5666 ctrl &= ~mask;
5667 ctrl |= state;
5668 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5669
5670 if (wait_for(COND, 100))
5671 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5672 state,
5673 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5674
5675#undef COND
5676
5677out:
5678 mutex_unlock(&dev_priv->rps.hw_lock);
5679}
5680
5681static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5682 struct i915_power_well *power_well)
5683{
5684 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5685}
5686
5687static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5688 struct i915_power_well *power_well)
5689{
5690 vlv_set_power_well(dev_priv, power_well, true);
5691}
5692
5693static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5694 struct i915_power_well *power_well)
5695{
5696 vlv_set_power_well(dev_priv, power_well, false);
5697}
5698
5699static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5700 struct i915_power_well *power_well)
5701{
5702 int power_well_id = power_well->data;
5703 bool enabled = false;
5704 u32 mask;
5705 u32 state;
5706 u32 ctrl;
5707
5708 mask = PUNIT_PWRGT_MASK(power_well_id);
5709 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5710
5711 mutex_lock(&dev_priv->rps.hw_lock);
5712
5713 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5714 /*
5715 * We only ever set the power-on and power-gate states, anything
5716 * else is unexpected.
5717 */
5718 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5719 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5720 if (state == ctrl)
5721 enabled = true;
5722
5723 /*
5724 * A transient state at this point would mean some unexpected party
5725 * is poking at the power controls too.
5726 */
5727 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5728 WARN_ON(ctrl != state);
5729
5730 mutex_unlock(&dev_priv->rps.hw_lock);
5731
5732 return enabled;
5733}
5734
5735static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5736 struct i915_power_well *power_well)
5737{
5738 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5739
5740 vlv_set_power_well(dev_priv, power_well, true);
5741
5742 spin_lock_irq(&dev_priv->irq_lock);
5743 valleyview_enable_display_irqs(dev_priv);
5744 spin_unlock_irq(&dev_priv->irq_lock);
5745
5746 /*
0d116a29
ID		 5747 * During driver initialization/resume we can avoid restoring the
5748 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 5749 */
0d116a29
ID		 5750 if (dev_priv->power_domains.initializing)
5751 return;
5752
5753 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 5754
5755 i915_redisable_vga_power_on(dev_priv->dev);
5756}
5757
5758static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5759 struct i915_power_well *power_well)
5760{
5761 struct drm_device *dev = dev_priv->dev;
5762 enum pipe pipe;
5763
5764 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5765
5766 spin_lock_irq(&dev_priv->irq_lock);
5767 for_each_pipe(pipe)
5768 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5769
5770 valleyview_disable_display_irqs(dev_priv);
5771 spin_unlock_irq(&dev_priv->irq_lock);
5772
5773 spin_lock_irq(&dev->vbl_lock);
5774 for_each_pipe(pipe)
5775 reset_vblank_counter(dev, pipe);
5776 spin_unlock_irq(&dev->vbl_lock);
5777
5778 vlv_set_power_well(dev_priv, power_well, false);
5779}
5780
25eaa003
ID		 5781static void check_power_well_state(struct drm_i915_private *dev_priv,
5782 struct i915_power_well *power_well)
5783{
5784 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5785
5786 if (power_well->always_on || !i915.disable_power_well) {
5787 if (!enabled)
5788 goto mismatch;
5789
5790 return;
5791 }
5792
5793 if (enabled != (power_well->count > 0))
5794 goto mismatch;
5795
5796 return;
5797
5798mismatch:
5799 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5800 power_well->name, power_well->always_on, enabled,
5801 power_well->count, i915.disable_power_well);
5802}
5803
da7e29bd 5804void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 5805 enum intel_display_power_domain domain)
5806{
83c00f55 5807 struct i915_power_domains *power_domains;
c1ca727f
ID		 5808 struct i915_power_well *power_well;
5809 int i;
6765625e 5810
9e6ea71a
PZ		 5811 intel_runtime_pm_get(dev_priv);
5812
83c00f55
ID		 5813 power_domains = &dev_priv->power_domains;
5814
5815 mutex_lock(&power_domains->lock);
1da51581 5816
25eaa003
ID		 5817 for_each_power_well(i, power_well, BIT(domain), power_domains) {
5818 if (!power_well->count++) {
5819 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 5820 power_well->ops->enable(dev_priv, power_well);
25eaa003
ID		 5821 }
5822
5823 check_power_well_state(dev_priv, power_well);
5824 }
1da51581 5825
ddf9c536
ID		 5826 power_domains->domain_use_count[domain]++;
5827
83c00f55 5828 mutex_unlock(&power_domains->lock);
6765625e
VS		 5829}
5830
da7e29bd 5831void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 5832 enum intel_display_power_domain domain)
5833{
83c00f55 5834 struct i915_power_domains *power_domains;
c1ca727f
ID		 5835 struct i915_power_well *power_well;
5836 int i;
6765625e 5837
83c00f55
ID		 5838 power_domains = &dev_priv->power_domains;
5839
5840 mutex_lock(&power_domains->lock);
1da51581 5841
1da51581
ID		 5842 WARN_ON(!power_domains->domain_use_count[domain]);
5843 power_domains->domain_use_count[domain]--;
ddf9c536 5844
70bf407c
ID		 5845 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5846 WARN_ON(!power_well->count);
5847
25eaa003
ID		 5848 if (!--power_well->count && i915.disable_power_well) {
5849 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
c6cb582e 5850 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 5851 }
5852
5853 check_power_well_state(dev_priv, power_well);
70bf407c 5854 }
1da51581 5855
83c00f55 5856 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 5857
5858 intel_runtime_pm_put(dev_priv);
6765625e
VS		 5859}
5860
83c00f55 5861static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5862
5863/* Display audio driver power well request */
5864void i915_request_power_well(void)
5865{
b4ed4484
ID		 5866 struct drm_i915_private *dev_priv;
5867
a38911a3
WX		 5868 if (WARN_ON(!hsw_pwr))
5869 return;
5870
b4ed4484
ID		 5871 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5872 power_domains);
da7e29bd 5873 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5874}
5875EXPORT_SYMBOL_GPL(i915_request_power_well);
5876
5877/* Display audio driver power well release */
5878void i915_release_power_well(void)
5879{
b4ed4484
ID		 5880 struct drm_i915_private *dev_priv;
5881
a38911a3
WX		 5882 if (WARN_ON(!hsw_pwr))
5883 return;
5884
b4ed4484
ID		 5885 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5886 power_domains);
da7e29bd 5887 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5888}
5889EXPORT_SYMBOL_GPL(i915_release_power_well);
5890
efcad917
ID		 5891#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5892
5893#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
5894 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 5895 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 5896 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
5897 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
5898 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5899 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5900 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5901 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5902 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
5903 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
5904 BIT(POWER_DOMAIN_PORT_CRT) | \
f5938f36 5905 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 5906#define HSW_DISPLAY_POWER_DOMAINS ( \
5907 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
5908 BIT(POWER_DOMAIN_INIT))
5909
5910#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
5911 HSW_ALWAYS_ON_POWER_DOMAINS | \
5912 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5913#define BDW_DISPLAY_POWER_DOMAINS ( \
5914 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
5915 BIT(POWER_DOMAIN_INIT))
5916
77961eb9
ID		 5917#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
5918#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
5919
5920#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
5921 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5922 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5923 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5924 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5925 BIT(POWER_DOMAIN_PORT_CRT) | \
5926 BIT(POWER_DOMAIN_INIT))
5927
5928#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
5929 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5930 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5931 BIT(POWER_DOMAIN_INIT))
5932
5933#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
5934 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5935 BIT(POWER_DOMAIN_INIT))
5936
5937#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
5938 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5939 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5940 BIT(POWER_DOMAIN_INIT))
5941
5942#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
5943 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5944 BIT(POWER_DOMAIN_INIT))
5945
a45f4466
ID		 5946static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5947 .sync_hw = i9xx_always_on_power_well_noop,
5948 .enable = i9xx_always_on_power_well_noop,
5949 .disable = i9xx_always_on_power_well_noop,
5950 .is_enabled = i9xx_always_on_power_well_enabled,
5951};
c6cb582e 5952
1c2256df
ID		 5953static struct i915_power_well i9xx_always_on_power_well[] = {
5954 {
5955 .name = "always-on",
5956 .always_on = 1,
5957 .domains = POWER_DOMAIN_MASK,
c6cb582e 5958 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 5959 },
5960};
5961
c6cb582e
ID		 5962static const struct i915_power_well_ops hsw_power_well_ops = {
5963 .sync_hw = hsw_power_well_sync_hw,
5964 .enable = hsw_power_well_enable,
5965 .disable = hsw_power_well_disable,
5966 .is_enabled = hsw_power_well_enabled,
5967};
5968
c1ca727f 5969static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5970 {
5971 .name = "always-on",
5972 .always_on = 1,
5973 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 5974 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 5975 },
c1ca727f
ID		 5976 {
5977 .name = "display",
efcad917 5978 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 5979 .ops = &hsw_power_well_ops,
c1ca727f
ID		 5980 },
5981};
5982
5983static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5984 {
5985 .name = "always-on",
5986 .always_on = 1,
5987 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 5988 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 5989 },
c1ca727f
ID		 5990 {
5991 .name = "display",
efcad917 5992 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 5993 .ops = &hsw_power_well_ops,
c1ca727f
ID		 5994 },
5995};
5996
77961eb9
ID		 5997static const struct i915_power_well_ops vlv_display_power_well_ops = {
5998 .sync_hw = vlv_power_well_sync_hw,
5999 .enable = vlv_display_power_well_enable,
6000 .disable = vlv_display_power_well_disable,
6001 .is_enabled = vlv_power_well_enabled,
6002};
6003
6004static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6005 .sync_hw = vlv_power_well_sync_hw,
6006 .enable = vlv_power_well_enable,
6007 .disable = vlv_power_well_disable,
6008 .is_enabled = vlv_power_well_enabled,
6009};
6010
6011static struct i915_power_well vlv_power_wells[] = {
6012 {
6013 .name = "always-on",
6014 .always_on = 1,
6015 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6016 .ops = &i9xx_always_on_power_well_ops,
6017 },
6018 {
6019 .name = "display",
6020 .domains = VLV_DISPLAY_POWER_DOMAINS,
6021 .data = PUNIT_POWER_WELL_DISP2D,
6022 .ops = &vlv_display_power_well_ops,
6023 },
6024 {
6025 .name = "dpio-common",
6026 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6027 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6028 .ops = &vlv_dpio_power_well_ops,
6029 },
6030 {
6031 .name = "dpio-tx-b-01",
6032 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6033 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6034 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6035 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6036 .ops = &vlv_dpio_power_well_ops,
6037 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6038 },
6039 {
6040 .name = "dpio-tx-b-23",
6041 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6042 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6043 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6044 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6045 .ops = &vlv_dpio_power_well_ops,
6046 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6047 },
6048 {
6049 .name = "dpio-tx-c-01",
6050 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6051 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6052 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6053 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6054 .ops = &vlv_dpio_power_well_ops,
6055 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6056 },
6057 {
6058 .name = "dpio-tx-c-23",
6059 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6060 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6061 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6062 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6063 .ops = &vlv_dpio_power_well_ops,
6064 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6065 },
6066};
6067
c1ca727f
ID		 6068#define set_power_wells(power_domains, __power_wells) ({ \
6069 (power_domains)->power_wells = (__power_wells); \
6070 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6071})
6072
da7e29bd 6073int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6074{
83c00f55 6075 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6076
83c00f55 6077 mutex_init(&power_domains->lock);
a38911a3 6078
c1ca727f
ID		 6079 /*
6080 * The enabling order will be from lower to higher indexed wells,
6081 * the disabling order is reversed.
6082 */
da7e29bd 6083 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6084 set_power_wells(power_domains, hsw_power_wells);
6085 hsw_pwr = power_domains;
da7e29bd 6086 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6087 set_power_wells(power_domains, bdw_power_wells);
6088 hsw_pwr = power_domains;
77961eb9
ID		 6089 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6090 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6091 } else {
1c2256df 6092 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6093 }
a38911a3
WX		 6094
6095 return 0;
6096}
6097
da7e29bd 6098void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6099{
6100 hsw_pwr = NULL;
6101}
6102
da7e29bd 6103static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6104{
83c00f55
ID		 6105 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6106 struct i915_power_well *power_well;
c1ca727f 6107 int i;
9cdb826c 6108
83c00f55 6109 mutex_lock(&power_domains->lock);
a45f4466
ID		 6110 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6111 power_well->ops->sync_hw(dev_priv, power_well);
83c00f55 6112 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6113}
6114
da7e29bd 6115void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 6116{
0d116a29
ID		 6117 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6118
6119 power_domains->initializing = true;
fa42e23c 6120 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 6121 intel_display_set_init_power(dev_priv, true);
6122 intel_power_domains_resume(dev_priv);
0d116a29 6123 power_domains->initializing = false;
d0d3e513
ED		 6124}
6125
c67a470b
PZ		 6126void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6127{
d361ae26 6128 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 6129}
6130
6131void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6132{
d361ae26 6133 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6134}
6135
8a187455
PZ		 6136void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6137{
6138 struct drm_device *dev = dev_priv->dev;
6139 struct device *device = &dev->pdev->dev;
6140
6141 if (!HAS_RUNTIME_PM(dev))
6142 return;
6143
6144 pm_runtime_get_sync(device);
6145 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6146}
6147
c6df39b5
ID		 6148void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6149{
6150 struct drm_device *dev = dev_priv->dev;
6151 struct device *device = &dev->pdev->dev;
6152
6153 if (!HAS_RUNTIME_PM(dev))
6154 return;
6155
6156 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6157 pm_runtime_get_noresume(device);
6158}
6159
8a187455
PZ		 6160void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6161{
6162 struct drm_device *dev = dev_priv->dev;
6163 struct device *device = &dev->pdev->dev;
6164
6165 if (!HAS_RUNTIME_PM(dev))
6166 return;
6167
6168 pm_runtime_mark_last_busy(device);
6169 pm_runtime_put_autosuspend(device);
6170}
6171
6172void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6173{
6174 struct drm_device *dev = dev_priv->dev;
6175 struct device *device = &dev->pdev->dev;
6176
8a187455
PZ		 6177 if (!HAS_RUNTIME_PM(dev))
6178 return;
6179
6180 pm_runtime_set_active(device);
6181
aeab0b5a
ID		 6182 /*
6183 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6184 * requirement.
6185 */
6186 if (!intel_enable_rc6(dev)) {
6187 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6188 return;
6189 }
6190
8a187455
PZ		 6191 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6192 pm_runtime_mark_last_busy(device);
6193 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 6194
6195 pm_runtime_put_autosuspend(device);
8a187455
PZ		 6196}
6197
6198void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6199{
6200 struct drm_device *dev = dev_priv->dev;
6201 struct device *device = &dev->pdev->dev;
6202
6203 if (!HAS_RUNTIME_PM(dev))
6204 return;
6205
aeab0b5a
ID		 6206 if (!intel_enable_rc6(dev))
6207 return;
6208
8a187455
PZ		 6209 /* Make sure we're not suspended first. */
6210 pm_runtime_get_sync(device);
6211 pm_runtime_disable(device);
6212}
6213
1fa61106
ED		 6214/* Set up chip specific power management-related functions */
6215void intel_init_pm(struct drm_device *dev)
6216{
6217 struct drm_i915_private *dev_priv = dev->dev_private;
6218
3a77c4c4 6219 if (HAS_FBC(dev)) {
40045465 6220 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6221 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6222 dev_priv->display.enable_fbc = gen7_enable_fbc;
6223 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6224 } else if (INTEL_INFO(dev)->gen >= 5) {
6225 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6226 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6227 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6228 } else if (IS_GM45(dev)) {
6229 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6230 dev_priv->display.enable_fbc = g4x_enable_fbc;
6231 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6232 } else {
1fa61106
ED		 6233 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6234 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6235 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6236
6237 /* This value was pulled out of someone's hat */
6238 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6239 }
1fa61106
ED		 6240 }
6241
c921aba8
DV		 6242 /* For cxsr */
6243 if (IS_PINEVIEW(dev))
6244 i915_pineview_get_mem_freq(dev);
6245 else if (IS_GEN5(dev))
6246 i915_ironlake_get_mem_freq(dev);
6247
1fa61106
ED		 6248 /* For FIFO watermark updates */
6249 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6250 ilk_setup_wm_latency(dev);
53615a5e 6251
bd602544
VS		 6252 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6253 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6254 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6255 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6256 dev_priv->display.update_wm = ilk_update_wm;
6257 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6258 } else {
6259 DRM_DEBUG_KMS("Failed to read display plane latency. "
6260 "Disable CxSR\n");
6261 }
6262
6263 if (IS_GEN5(dev))
1fa61106 6264 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6265 else if (IS_GEN6(dev))
1fa61106 6266 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6267 else if (IS_IVYBRIDGE(dev))
1fa61106 6268 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6269 else if (IS_HASWELL(dev))
cad2a2d7 6270 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6271 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 6272 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 6273 } else if (IS_VALLEYVIEW(dev)) {
6274 dev_priv->display.update_wm = valleyview_update_wm;
6275 dev_priv->display.init_clock_gating =
6276 valleyview_init_clock_gating;
1fa61106
ED		 6277 } else if (IS_PINEVIEW(dev)) {
6278 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6279 dev_priv->is_ddr3,
6280 dev_priv->fsb_freq,
6281 dev_priv->mem_freq)) {
6282 DRM_INFO("failed to find known CxSR latency "
6283 "(found ddr%s fsb freq %d, mem freq %d), "
6284 "disabling CxSR\n",
6285 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6286 dev_priv->fsb_freq, dev_priv->mem_freq);
6287 /* Disable CxSR and never update its watermark again */
6288 pineview_disable_cxsr(dev);
6289 dev_priv->display.update_wm = NULL;
6290 } else
6291 dev_priv->display.update_wm = pineview_update_wm;
6292 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6293 } else if (IS_G4X(dev)) {
6294 dev_priv->display.update_wm = g4x_update_wm;
6295 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6296 } else if (IS_GEN4(dev)) {
6297 dev_priv->display.update_wm = i965_update_wm;
6298 if (IS_CRESTLINE(dev))
6299 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6300 else if (IS_BROADWATER(dev))
6301 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6302 } else if (IS_GEN3(dev)) {
6303 dev_priv->display.update_wm = i9xx_update_wm;
6304 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6305 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6306 } else if (IS_GEN2(dev)) {
6307 if (INTEL_INFO(dev)->num_pipes == 1) {
6308 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6309 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6310 } else {
6311 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6312 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6313 }
6314
6315 if (IS_I85X(dev) || IS_I865G(dev))
6316 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6317 else
6318 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6319 } else {
6320 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6321 }
6322}
6323
42c0526c
BW		 6324int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6325{
4fc688ce 6326 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6327
6328 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6329 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6330 return -EAGAIN;
6331 }
6332
6333 I915_WRITE(GEN6_PCODE_DATA, *val);
6334 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6335
6336 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6337 500)) {
6338 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6339 return -ETIMEDOUT;
6340 }
6341
6342 *val = I915_READ(GEN6_PCODE_DATA);
6343 I915_WRITE(GEN6_PCODE_DATA, 0);
6344
6345 return 0;
6346}
6347
6348int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6349{
4fc688ce 6350 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6351
6352 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6353 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6354 return -EAGAIN;
6355 }
6356
6357 I915_WRITE(GEN6_PCODE_DATA, val);
6358 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6359
6360 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6361 500)) {
6362 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6363 return -ETIMEDOUT;
6364 }
6365
6366 I915_WRITE(GEN6_PCODE_DATA, 0);
6367
6368 return 0;
6369}
a0e4e199 6370
2ec3815f 6371int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6372{
07ab118b 6373 int div;
855ba3be 6374
07ab118b 6375 /* 4 x czclk */
2ec3815f 6376 switch (dev_priv->mem_freq) {
855ba3be 6377 case 800:
07ab118b 6378 div = 10;
855ba3be
JB		 6379 break;
6380 case 1066:
07ab118b 6381 div = 12;
855ba3be
JB		 6382 break;
6383 case 1333:
07ab118b 6384 div = 16;
855ba3be
JB		 6385 break;
6386 default:
6387 return -1;
6388 }
6389
2ec3815f 6390 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6391}
6392
2ec3815f 6393int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6394{
07ab118b 6395 int mul;
855ba3be 6396
07ab118b 6397 /* 4 x czclk */
2ec3815f 6398 switch (dev_priv->mem_freq) {
855ba3be 6399 case 800:
07ab118b 6400 mul = 10;
855ba3be
JB		 6401 break;
6402 case 1066:
07ab118b 6403 mul = 12;
855ba3be
JB		 6404 break;
6405 case 1333:
07ab118b 6406 mul = 16;
855ba3be
JB		 6407 break;
6408 default:
6409 return -1;
6410 }
6411
2ec3815f 6412 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6413}
6414
f742a552 6415void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6416{
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418
f742a552
DV		 6419 mutex_init(&dev_priv->rps.hw_lock);
6420
907b28c5
CW		 6421 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6422 intel_gen6_powersave_work);
5d584b2e 6423
33688d95 6424 dev_priv->pm.suspended = false;
5d584b2e 6425 dev_priv->pm.irqs_disabled = false;
907b28c5 6426}
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