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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
9c2f7a9d | 29 | #include <drm/drm_plane_helper.h> |
85208be0 ED |
30 | #include "i915_drv.h" |
31 | #include "intel_drv.h" | |
eb48eb00 DV |
32 | #include "../../../platform/x86/intel_ips.h" |
33 | #include <linux/module.h> | |
c8fe32c1 | 34 | #include <drm/drm_atomic_helper.h> |
85208be0 | 35 | |
dc39fff7 | 36 | /** |
18afd443 JN |
37 | * DOC: RC6 |
38 | * | |
dc39fff7 BW |
39 | * RC6 is a special power stage which allows the GPU to enter an very |
40 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
41 | * stage is entered automatically when the GPU is idle when RC6 support is | |
42 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
43 | * | |
44 | * There are different RC6 modes available in Intel GPU, which differentiate | |
45 | * among each other with the latency required to enter and leave RC6 and | |
46 | * voltage consumed by the GPU in different states. | |
47 | * | |
48 | * The combination of the following flags define which states GPU is allowed | |
49 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
50 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
51 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
52 | * which brings the most power savings; deeper states save more power, but | |
53 | * require higher latency to switch to and wake up. | |
54 | */ | |
55 | #define INTEL_RC6_ENABLE (1<<0) | |
56 | #define INTEL_RC6p_ENABLE (1<<1) | |
57 | #define INTEL_RC6pp_ENABLE (1<<2) | |
58 | ||
46f16e63 | 59 | static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) |
a82abe43 | 60 | { |
b033bb6d | 61 | /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */ |
dc00b6a0 DV |
62 | I915_WRITE(CHICKEN_PAR1_1, |
63 | I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); | |
64 | ||
b033bb6d MK |
65 | I915_WRITE(GEN8_CONFIG0, |
66 | I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); | |
590e8ff0 | 67 | |
9fb5026f | 68 | /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ |
590e8ff0 MK |
69 | I915_WRITE(GEN8_CHICKEN_DCPR_1, |
70 | I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); | |
0f78dee6 MK |
71 | |
72 | /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ | |
9fb5026f | 73 | /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ |
303d4ea5 MK |
74 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
75 | DISP_FBC_WM_DIS | | |
76 | DISP_FBC_MEMORY_WAKE); | |
d1b4eefd MK |
77 | |
78 | /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */ | |
79 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
80 | ILK_DPFC_DISABLE_DUMMY0); | |
b033bb6d MK |
81 | } |
82 | ||
46f16e63 | 83 | static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) |
b033bb6d | 84 | { |
46f16e63 | 85 | gen9_init_clock_gating(dev_priv); |
b033bb6d | 86 | |
a7546159 NH |
87 | /* WaDisableSDEUnitClockGating:bxt */ |
88 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
89 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
90 | ||
32608ca2 ID |
91 | /* |
92 | * FIXME: | |
868434c5 | 93 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
32608ca2 | 94 | */ |
32608ca2 | 95 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
868434c5 | 96 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
d965e7ac ID |
97 | |
98 | /* | |
99 | * Wa: Backlight PWM may stop in the asserted state, causing backlight | |
100 | * to stay fully on. | |
101 | */ | |
8aeaf64c JN |
102 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | |
103 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
a82abe43 ID |
104 | } |
105 | ||
9fb5026f ACO |
106 | static void glk_init_clock_gating(struct drm_i915_private *dev_priv) |
107 | { | |
108 | gen9_init_clock_gating(dev_priv); | |
109 | ||
110 | /* | |
111 | * WaDisablePWMClockGating:glk | |
112 | * Backlight PWM may stop in the asserted state, causing backlight | |
113 | * to stay fully on. | |
114 | */ | |
115 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | | |
116 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
f4f4b59b ACO |
117 | |
118 | /* WaDDIIOTimeout:glk */ | |
119 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { | |
120 | u32 val = I915_READ(CHICKEN_MISC_2); | |
121 | val &= ~(GLK_CL0_PWR_DOWN | | |
122 | GLK_CL1_PWR_DOWN | | |
123 | GLK_CL2_PWR_DOWN); | |
124 | I915_WRITE(CHICKEN_MISC_2, val); | |
125 | } | |
126 | ||
9fb5026f ACO |
127 | } |
128 | ||
148ac1f3 | 129 | static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 130 | { |
c921aba8 DV |
131 | u32 tmp; |
132 | ||
133 | tmp = I915_READ(CLKCFG); | |
134 | ||
135 | switch (tmp & CLKCFG_FSB_MASK) { | |
136 | case CLKCFG_FSB_533: | |
137 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
138 | break; | |
139 | case CLKCFG_FSB_800: | |
140 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
141 | break; | |
142 | case CLKCFG_FSB_667: | |
143 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
144 | break; | |
145 | case CLKCFG_FSB_400: | |
146 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
147 | break; | |
148 | } | |
149 | ||
150 | switch (tmp & CLKCFG_MEM_MASK) { | |
151 | case CLKCFG_MEM_533: | |
152 | dev_priv->mem_freq = 533; | |
153 | break; | |
154 | case CLKCFG_MEM_667: | |
155 | dev_priv->mem_freq = 667; | |
156 | break; | |
157 | case CLKCFG_MEM_800: | |
158 | dev_priv->mem_freq = 800; | |
159 | break; | |
160 | } | |
161 | ||
162 | /* detect pineview DDR3 setting */ | |
163 | tmp = I915_READ(CSHRDDR3CTL); | |
164 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
165 | } | |
166 | ||
148ac1f3 | 167 | static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 168 | { |
c921aba8 DV |
169 | u16 ddrpll, csipll; |
170 | ||
171 | ddrpll = I915_READ16(DDRMPLL1); | |
172 | csipll = I915_READ16(CSIPLL0); | |
173 | ||
174 | switch (ddrpll & 0xff) { | |
175 | case 0xc: | |
176 | dev_priv->mem_freq = 800; | |
177 | break; | |
178 | case 0x10: | |
179 | dev_priv->mem_freq = 1066; | |
180 | break; | |
181 | case 0x14: | |
182 | dev_priv->mem_freq = 1333; | |
183 | break; | |
184 | case 0x18: | |
185 | dev_priv->mem_freq = 1600; | |
186 | break; | |
187 | default: | |
188 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
189 | ddrpll & 0xff); | |
190 | dev_priv->mem_freq = 0; | |
191 | break; | |
192 | } | |
193 | ||
20e4d407 | 194 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
195 | |
196 | switch (csipll & 0x3ff) { | |
197 | case 0x00c: | |
198 | dev_priv->fsb_freq = 3200; | |
199 | break; | |
200 | case 0x00e: | |
201 | dev_priv->fsb_freq = 3733; | |
202 | break; | |
203 | case 0x010: | |
204 | dev_priv->fsb_freq = 4266; | |
205 | break; | |
206 | case 0x012: | |
207 | dev_priv->fsb_freq = 4800; | |
208 | break; | |
209 | case 0x014: | |
210 | dev_priv->fsb_freq = 5333; | |
211 | break; | |
212 | case 0x016: | |
213 | dev_priv->fsb_freq = 5866; | |
214 | break; | |
215 | case 0x018: | |
216 | dev_priv->fsb_freq = 6400; | |
217 | break; | |
218 | default: | |
219 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
220 | csipll & 0x3ff); | |
221 | dev_priv->fsb_freq = 0; | |
222 | break; | |
223 | } | |
224 | ||
225 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 226 | dev_priv->ips.c_m = 0; |
c921aba8 | 227 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 228 | dev_priv->ips.c_m = 1; |
c921aba8 | 229 | } else { |
20e4d407 | 230 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
231 | } |
232 | } | |
233 | ||
b445e3b0 ED |
234 | static const struct cxsr_latency cxsr_latency_table[] = { |
235 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
236 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
237 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
238 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
239 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
240 | ||
241 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
242 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
243 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
244 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
245 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
246 | ||
247 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
248 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
249 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
250 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
251 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
252 | ||
253 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
254 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
255 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
256 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
257 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
258 | ||
259 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
260 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
261 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
262 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
263 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
264 | ||
265 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
266 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
267 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
268 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
269 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
270 | }; | |
271 | ||
44a655ca TU |
272 | static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop, |
273 | bool is_ddr3, | |
b445e3b0 ED |
274 | int fsb, |
275 | int mem) | |
276 | { | |
277 | const struct cxsr_latency *latency; | |
278 | int i; | |
279 | ||
280 | if (fsb == 0 || mem == 0) | |
281 | return NULL; | |
282 | ||
283 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
284 | latency = &cxsr_latency_table[i]; | |
285 | if (is_desktop == latency->is_desktop && | |
286 | is_ddr3 == latency->is_ddr3 && | |
287 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
288 | return latency; | |
289 | } | |
290 | ||
291 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
292 | ||
293 | return NULL; | |
294 | } | |
295 | ||
fc1ac8de VS |
296 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
297 | { | |
298 | u32 val; | |
299 | ||
300 | mutex_lock(&dev_priv->rps.hw_lock); | |
301 | ||
302 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
303 | if (enable) | |
304 | val &= ~FORCE_DDR_HIGH_FREQ; | |
305 | else | |
306 | val |= FORCE_DDR_HIGH_FREQ; | |
307 | val &= ~FORCE_DDR_LOW_FREQ; | |
308 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
309 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
310 | ||
311 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
312 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
313 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
314 | ||
315 | mutex_unlock(&dev_priv->rps.hw_lock); | |
316 | } | |
317 | ||
cfb41411 VS |
318 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
319 | { | |
320 | u32 val; | |
321 | ||
322 | mutex_lock(&dev_priv->rps.hw_lock); | |
323 | ||
324 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
325 | if (enable) | |
326 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
327 | else | |
328 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
329 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
330 | ||
331 | mutex_unlock(&dev_priv->rps.hw_lock); | |
332 | } | |
333 | ||
f4998963 VS |
334 | #define FW_WM(value, plane) \ |
335 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
336 | ||
11a85d6a | 337 | static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 338 | { |
11a85d6a | 339 | bool was_enabled; |
5209b1f4 | 340 | u32 val; |
b445e3b0 | 341 | |
920a14b2 | 342 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
11a85d6a | 343 | was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
5209b1f4 | 344 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
a7a6c498 | 345 | POSTING_READ(FW_BLC_SELF_VLV); |
c0f86832 | 346 | } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { |
11a85d6a | 347 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 | 348 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
a7a6c498 | 349 | POSTING_READ(FW_BLC_SELF); |
9b1e14f4 | 350 | } else if (IS_PINEVIEW(dev_priv)) { |
11a85d6a VS |
351 | val = I915_READ(DSPFW3); |
352 | was_enabled = val & PINEVIEW_SELF_REFRESH_EN; | |
353 | if (enable) | |
354 | val |= PINEVIEW_SELF_REFRESH_EN; | |
355 | else | |
356 | val &= ~PINEVIEW_SELF_REFRESH_EN; | |
5209b1f4 | 357 | I915_WRITE(DSPFW3, val); |
a7a6c498 | 358 | POSTING_READ(DSPFW3); |
50a0bc90 | 359 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { |
11a85d6a | 360 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 ID |
361 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
362 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
363 | I915_WRITE(FW_BLC_SELF, val); | |
a7a6c498 | 364 | POSTING_READ(FW_BLC_SELF); |
50a0bc90 | 365 | } else if (IS_I915GM(dev_priv)) { |
acb91359 VS |
366 | /* |
367 | * FIXME can't find a bit like this for 915G, and | |
368 | * and yet it does have the related watermark in | |
369 | * FW_BLC_SELF. What's going on? | |
370 | */ | |
11a85d6a | 371 | was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
5209b1f4 ID |
372 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
373 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
374 | I915_WRITE(INSTPM, val); | |
a7a6c498 | 375 | POSTING_READ(INSTPM); |
5209b1f4 | 376 | } else { |
11a85d6a | 377 | return false; |
5209b1f4 | 378 | } |
b445e3b0 | 379 | |
1489bba8 VS |
380 | trace_intel_memory_cxsr(dev_priv, was_enabled, enable); |
381 | ||
11a85d6a VS |
382 | DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n", |
383 | enableddisabled(enable), | |
384 | enableddisabled(was_enabled)); | |
385 | ||
386 | return was_enabled; | |
b445e3b0 ED |
387 | } |
388 | ||
62571fc3 VS |
389 | /** |
390 | * intel_set_memory_cxsr - Configure CxSR state | |
391 | * @dev_priv: i915 device | |
392 | * @enable: Allow vs. disallow CxSR | |
393 | * | |
394 | * Allow or disallow the system to enter a special CxSR | |
395 | * (C-state self refresh) state. What typically happens in CxSR mode | |
396 | * is that several display FIFOs may get combined into a single larger | |
397 | * FIFO for a particular plane (so called max FIFO mode) to allow the | |
398 | * system to defer memory fetches longer, and the memory will enter | |
399 | * self refresh. | |
400 | * | |
401 | * Note that enabling CxSR does not guarantee that the system enter | |
402 | * this special mode, nor does it guarantee that the system stays | |
403 | * in that mode once entered. So this just allows/disallows the system | |
404 | * to autonomously utilize the CxSR mode. Other factors such as core | |
405 | * C-states will affect when/if the system actually enters/exits the | |
406 | * CxSR mode. | |
407 | * | |
408 | * Note that on VLV/CHV this actually only controls the max FIFO mode, | |
409 | * and the system is free to enter/exit memory self refresh at any time | |
410 | * even when the use of CxSR has been disallowed. | |
411 | * | |
412 | * While the system is actually in the CxSR/max FIFO mode, some plane | |
413 | * control registers will not get latched on vblank. Thus in order to | |
414 | * guarantee the system will respond to changes in the plane registers | |
415 | * we must always disallow CxSR prior to making changes to those registers. | |
416 | * Unfortunately the system will re-evaluate the CxSR conditions at | |
417 | * frame start which happens after vblank start (which is when the plane | |
418 | * registers would get latched), so we can't proceed with the plane update | |
419 | * during the same frame where we disallowed CxSR. | |
420 | * | |
421 | * Certain platforms also have a deeper HPLL SR mode. Fortunately the | |
422 | * HPLL SR mode depends on CxSR itself, so we don't have to hand hold | |
423 | * the hardware w.r.t. HPLL SR when writing to plane registers. | |
424 | * Disallowing just CxSR is sufficient. | |
425 | */ | |
11a85d6a | 426 | bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
3d90e649 | 427 | { |
11a85d6a VS |
428 | bool ret; |
429 | ||
3d90e649 | 430 | mutex_lock(&dev_priv->wm.wm_mutex); |
11a85d6a | 431 | ret = _intel_set_memory_cxsr(dev_priv, enable); |
04548cba VS |
432 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
433 | dev_priv->wm.vlv.cxsr = enable; | |
434 | else if (IS_G4X(dev_priv)) | |
435 | dev_priv->wm.g4x.cxsr = enable; | |
3d90e649 | 436 | mutex_unlock(&dev_priv->wm.wm_mutex); |
11a85d6a VS |
437 | |
438 | return ret; | |
3d90e649 | 439 | } |
fc1ac8de | 440 | |
b445e3b0 ED |
441 | /* |
442 | * Latency for FIFO fetches is dependent on several factors: | |
443 | * - memory configuration (speed, channels) | |
444 | * - chipset | |
445 | * - current MCH state | |
446 | * It can be fairly high in some situations, so here we assume a fairly | |
447 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
448 | * set this value too high, the FIFO will fetch frequently to stay full) | |
449 | * and power consumption (set it too low to save power and we might see | |
450 | * FIFO underruns and display "flicker"). | |
451 | * | |
452 | * A value of 5us seems to be a good balance; safe for very low end | |
453 | * platforms but not overly aggressive on lower latency configs. | |
454 | */ | |
5aef6003 | 455 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 456 | |
b5004720 VS |
457 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
458 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
459 | ||
814e7f0b | 460 | static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) |
b5004720 | 461 | { |
814e7f0b | 462 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 463 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b | 464 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
f07d43d2 VS |
465 | enum pipe pipe = crtc->pipe; |
466 | int sprite0_start, sprite1_start; | |
49845a23 | 467 | |
f07d43d2 | 468 | switch (pipe) { |
b5004720 VS |
469 | uint32_t dsparb, dsparb2, dsparb3; |
470 | case PIPE_A: | |
471 | dsparb = I915_READ(DSPARB); | |
472 | dsparb2 = I915_READ(DSPARB2); | |
473 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
474 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
475 | break; | |
476 | case PIPE_B: | |
477 | dsparb = I915_READ(DSPARB); | |
478 | dsparb2 = I915_READ(DSPARB2); | |
479 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
480 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
481 | break; | |
482 | case PIPE_C: | |
483 | dsparb2 = I915_READ(DSPARB2); | |
484 | dsparb3 = I915_READ(DSPARB3); | |
485 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
486 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
487 | break; | |
488 | default: | |
f07d43d2 VS |
489 | MISSING_CASE(pipe); |
490 | return; | |
b5004720 VS |
491 | } |
492 | ||
f07d43d2 VS |
493 | fifo_state->plane[PLANE_PRIMARY] = sprite0_start; |
494 | fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start; | |
495 | fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start; | |
496 | fifo_state->plane[PLANE_CURSOR] = 63; | |
b5004720 VS |
497 | } |
498 | ||
ef0f5e93 | 499 | static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 500 | { |
b445e3b0 ED |
501 | uint32_t dsparb = I915_READ(DSPARB); |
502 | int size; | |
503 | ||
504 | size = dsparb & 0x7f; | |
505 | if (plane) | |
506 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
507 | ||
508 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
509 | plane ? "B" : "A", size); | |
510 | ||
511 | return size; | |
512 | } | |
513 | ||
ef0f5e93 | 514 | static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 515 | { |
b445e3b0 ED |
516 | uint32_t dsparb = I915_READ(DSPARB); |
517 | int size; | |
518 | ||
519 | size = dsparb & 0x1ff; | |
520 | if (plane) | |
521 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
522 | size >>= 1; /* Convert to cachelines */ | |
523 | ||
524 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
525 | plane ? "B" : "A", size); | |
526 | ||
527 | return size; | |
528 | } | |
529 | ||
ef0f5e93 | 530 | static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 531 | { |
b445e3b0 ED |
532 | uint32_t dsparb = I915_READ(DSPARB); |
533 | int size; | |
534 | ||
535 | size = dsparb & 0x7f; | |
536 | size >>= 2; /* Convert to cachelines */ | |
537 | ||
538 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
539 | plane ? "B" : "A", | |
540 | size); | |
541 | ||
542 | return size; | |
543 | } | |
544 | ||
b445e3b0 ED |
545 | /* Pineview has different values for various configs */ |
546 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
547 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
548 | .max_wm = PINEVIEW_MAX_WM, | |
549 | .default_wm = PINEVIEW_DFT_WM, | |
550 | .guard_size = PINEVIEW_GUARD_WM, | |
551 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
552 | }; |
553 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
554 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
555 | .max_wm = PINEVIEW_MAX_WM, | |
556 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
557 | .guard_size = PINEVIEW_GUARD_WM, | |
558 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
559 | }; |
560 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
561 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
562 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
563 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
564 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
565 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
566 | }; |
567 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
568 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
569 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
570 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
571 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
572 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 | 573 | }; |
b445e3b0 | 574 | static const struct intel_watermark_params i965_cursor_wm_info = { |
e0f0273e VS |
575 | .fifo_size = I965_CURSOR_FIFO, |
576 | .max_wm = I965_CURSOR_MAX_WM, | |
577 | .default_wm = I965_CURSOR_DFT_WM, | |
578 | .guard_size = 2, | |
579 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
580 | }; |
581 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
582 | .fifo_size = I945_FIFO_SIZE, |
583 | .max_wm = I915_MAX_WM, | |
584 | .default_wm = 1, | |
585 | .guard_size = 2, | |
586 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
587 | }; |
588 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
589 | .fifo_size = I915_FIFO_SIZE, |
590 | .max_wm = I915_MAX_WM, | |
591 | .default_wm = 1, | |
592 | .guard_size = 2, | |
593 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 594 | }; |
9d539105 | 595 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
596 | .fifo_size = I855GM_FIFO_SIZE, |
597 | .max_wm = I915_MAX_WM, | |
598 | .default_wm = 1, | |
599 | .guard_size = 2, | |
600 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 601 | }; |
9d539105 VS |
602 | static const struct intel_watermark_params i830_bc_wm_info = { |
603 | .fifo_size = I855GM_FIFO_SIZE, | |
604 | .max_wm = I915_MAX_WM/2, | |
605 | .default_wm = 1, | |
606 | .guard_size = 2, | |
607 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
608 | }; | |
feb56b93 | 609 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
610 | .fifo_size = I830_FIFO_SIZE, |
611 | .max_wm = I915_MAX_WM, | |
612 | .default_wm = 1, | |
613 | .guard_size = 2, | |
614 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
615 | }; |
616 | ||
baf69ca8 VS |
617 | /** |
618 | * intel_wm_method1 - Method 1 / "small buffer" watermark formula | |
619 | * @pixel_rate: Pipe pixel rate in kHz | |
620 | * @cpp: Plane bytes per pixel | |
621 | * @latency: Memory wakeup latency in 0.1us units | |
622 | * | |
623 | * Compute the watermark using the method 1 or "small buffer" | |
624 | * formula. The caller may additonally add extra cachelines | |
625 | * to account for TLB misses and clock crossings. | |
626 | * | |
627 | * This method is concerned with the short term drain rate | |
628 | * of the FIFO, ie. it does not account for blanking periods | |
629 | * which would effectively reduce the average drain rate across | |
630 | * a longer period. The name "small" refers to the fact the | |
631 | * FIFO is relatively small compared to the amount of data | |
632 | * fetched. | |
633 | * | |
634 | * The FIFO level vs. time graph might look something like: | |
635 | * | |
636 | * |\ |\ | |
637 | * | \ | \ | |
638 | * __---__---__ (- plane active, _ blanking) | |
639 | * -> time | |
640 | * | |
641 | * or perhaps like this: | |
642 | * | |
643 | * |\|\ |\|\ | |
644 | * __----__----__ (- plane active, _ blanking) | |
645 | * -> time | |
646 | * | |
647 | * Returns: | |
648 | * The watermark in bytes | |
649 | */ | |
650 | static unsigned int intel_wm_method1(unsigned int pixel_rate, | |
651 | unsigned int cpp, | |
652 | unsigned int latency) | |
653 | { | |
654 | uint64_t ret; | |
655 | ||
656 | ret = (uint64_t) pixel_rate * cpp * latency; | |
657 | ret = DIV_ROUND_UP_ULL(ret, 10000); | |
658 | ||
659 | return ret; | |
660 | } | |
661 | ||
662 | /** | |
663 | * intel_wm_method2 - Method 2 / "large buffer" watermark formula | |
664 | * @pixel_rate: Pipe pixel rate in kHz | |
665 | * @htotal: Pipe horizontal total | |
666 | * @width: Plane width in pixels | |
667 | * @cpp: Plane bytes per pixel | |
668 | * @latency: Memory wakeup latency in 0.1us units | |
669 | * | |
670 | * Compute the watermark using the method 2 or "large buffer" | |
671 | * formula. The caller may additonally add extra cachelines | |
672 | * to account for TLB misses and clock crossings. | |
673 | * | |
674 | * This method is concerned with the long term drain rate | |
675 | * of the FIFO, ie. it does account for blanking periods | |
676 | * which effectively reduce the average drain rate across | |
677 | * a longer period. The name "large" refers to the fact the | |
678 | * FIFO is relatively large compared to the amount of data | |
679 | * fetched. | |
680 | * | |
681 | * The FIFO level vs. time graph might look something like: | |
682 | * | |
683 | * |\___ |\___ | |
684 | * | \___ | \___ | |
685 | * | \ | \ | |
686 | * __ --__--__--__--__--__--__ (- plane active, _ blanking) | |
687 | * -> time | |
688 | * | |
689 | * Returns: | |
690 | * The watermark in bytes | |
691 | */ | |
692 | static unsigned int intel_wm_method2(unsigned int pixel_rate, | |
693 | unsigned int htotal, | |
694 | unsigned int width, | |
695 | unsigned int cpp, | |
696 | unsigned int latency) | |
697 | { | |
698 | unsigned int ret; | |
699 | ||
700 | /* | |
701 | * FIXME remove once all users are computing | |
702 | * watermarks in the correct place. | |
703 | */ | |
704 | if (WARN_ON_ONCE(htotal == 0)) | |
705 | htotal = 1; | |
706 | ||
707 | ret = (latency * pixel_rate) / (htotal * 10000); | |
708 | ret = (ret + 1) * width * cpp; | |
709 | ||
710 | return ret; | |
711 | } | |
712 | ||
b445e3b0 ED |
713 | /** |
714 | * intel_calculate_wm - calculate watermark level | |
baf69ca8 | 715 | * @pixel_rate: pixel clock |
b445e3b0 | 716 | * @wm: chip FIFO params |
ac484963 | 717 | * @cpp: bytes per pixel |
b445e3b0 ED |
718 | * @latency_ns: memory latency for the platform |
719 | * | |
720 | * Calculate the watermark level (the level at which the display plane will | |
721 | * start fetching from memory again). Each chip has a different display | |
722 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
723 | * in the correct intel_watermark_params structure. | |
724 | * | |
725 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
726 | * on the pixel size. When it reaches the watermark level, it'll start | |
727 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
728 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
729 | * will occur, and a display engine hang could result. | |
730 | */ | |
baf69ca8 VS |
731 | static unsigned int intel_calculate_wm(int pixel_rate, |
732 | const struct intel_watermark_params *wm, | |
733 | int fifo_size, int cpp, | |
734 | unsigned int latency_ns) | |
b445e3b0 | 735 | { |
baf69ca8 | 736 | int entries, wm_size; |
b445e3b0 ED |
737 | |
738 | /* | |
739 | * Note: we need to make sure we don't overflow for various clock & | |
740 | * latency values. | |
741 | * clocks go from a few thousand to several hundred thousand. | |
742 | * latency is usually a few thousand | |
743 | */ | |
baf69ca8 VS |
744 | entries = intel_wm_method1(pixel_rate, cpp, |
745 | latency_ns / 100); | |
746 | entries = DIV_ROUND_UP(entries, wm->cacheline_size) + | |
747 | wm->guard_size; | |
748 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries); | |
b445e3b0 | 749 | |
baf69ca8 VS |
750 | wm_size = fifo_size - entries; |
751 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); | |
b445e3b0 ED |
752 | |
753 | /* Don't promote wm_size to unsigned... */ | |
baf69ca8 | 754 | if (wm_size > wm->max_wm) |
b445e3b0 ED |
755 | wm_size = wm->max_wm; |
756 | if (wm_size <= 0) | |
757 | wm_size = wm->default_wm; | |
d6feb196 VS |
758 | |
759 | /* | |
760 | * Bspec seems to indicate that the value shouldn't be lower than | |
761 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
762 | * Lets go for 8 which is the burst size since certain platforms | |
763 | * already use a hardcoded 8 (which is what the spec says should be | |
764 | * done). | |
765 | */ | |
766 | if (wm_size <= 8) | |
767 | wm_size = 8; | |
768 | ||
b445e3b0 ED |
769 | return wm_size; |
770 | } | |
771 | ||
04548cba VS |
772 | static bool is_disabling(int old, int new, int threshold) |
773 | { | |
774 | return old >= threshold && new < threshold; | |
775 | } | |
776 | ||
777 | static bool is_enabling(int old, int new, int threshold) | |
778 | { | |
779 | return old < threshold && new >= threshold; | |
780 | } | |
781 | ||
6d5019b6 VS |
782 | static int intel_wm_num_levels(struct drm_i915_private *dev_priv) |
783 | { | |
784 | return dev_priv->wm.max_level + 1; | |
785 | } | |
786 | ||
24304d81 VS |
787 | static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, |
788 | const struct intel_plane_state *plane_state) | |
789 | { | |
790 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
791 | ||
792 | /* FIXME check the 'enable' instead */ | |
793 | if (!crtc_state->base.active) | |
794 | return false; | |
795 | ||
796 | /* | |
797 | * Treat cursor with fb as always visible since cursor updates | |
798 | * can happen faster than the vrefresh rate, and the current | |
799 | * watermark code doesn't handle that correctly. Cursor updates | |
800 | * which set/clear the fb or change the cursor size are going | |
801 | * to get throttled by intel_legacy_cursor_update() to work | |
802 | * around this problem with the watermark code. | |
803 | */ | |
804 | if (plane->id == PLANE_CURSOR) | |
805 | return plane_state->base.fb != NULL; | |
806 | else | |
807 | return plane_state->base.visible; | |
808 | } | |
809 | ||
ffc7a76b | 810 | static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv) |
b445e3b0 | 811 | { |
efc2611e | 812 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 813 | |
ffc7a76b | 814 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
efc2611e | 815 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
816 | if (enabled) |
817 | return NULL; | |
818 | enabled = crtc; | |
819 | } | |
820 | } | |
821 | ||
822 | return enabled; | |
823 | } | |
824 | ||
432081bc | 825 | static void pineview_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 826 | { |
ffc7a76b | 827 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 828 | struct intel_crtc *crtc; |
b445e3b0 ED |
829 | const struct cxsr_latency *latency; |
830 | u32 reg; | |
baf69ca8 | 831 | unsigned int wm; |
b445e3b0 | 832 | |
50a0bc90 TU |
833 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
834 | dev_priv->is_ddr3, | |
835 | dev_priv->fsb_freq, | |
836 | dev_priv->mem_freq); | |
b445e3b0 ED |
837 | if (!latency) { |
838 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 839 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
840 | return; |
841 | } | |
842 | ||
ffc7a76b | 843 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 | 844 | if (crtc) { |
efc2611e VS |
845 | const struct drm_display_mode *adjusted_mode = |
846 | &crtc->config->base.adjusted_mode; | |
847 | const struct drm_framebuffer *fb = | |
848 | crtc->base.primary->state->fb; | |
353c8598 | 849 | int cpp = fb->format->cpp[0]; |
7c5f93b0 | 850 | int clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
851 | |
852 | /* Display SR */ | |
853 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
854 | pineview_display_wm.fifo_size, | |
ac484963 | 855 | cpp, latency->display_sr); |
b445e3b0 ED |
856 | reg = I915_READ(DSPFW1); |
857 | reg &= ~DSPFW_SR_MASK; | |
f4998963 | 858 | reg |= FW_WM(wm, SR); |
b445e3b0 ED |
859 | I915_WRITE(DSPFW1, reg); |
860 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
861 | ||
862 | /* cursor SR */ | |
863 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
864 | pineview_display_wm.fifo_size, | |
99834b14 | 865 | 4, latency->cursor_sr); |
b445e3b0 ED |
866 | reg = I915_READ(DSPFW3); |
867 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
f4998963 | 868 | reg |= FW_WM(wm, CURSOR_SR); |
b445e3b0 ED |
869 | I915_WRITE(DSPFW3, reg); |
870 | ||
871 | /* Display HPLL off SR */ | |
872 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
873 | pineview_display_hplloff_wm.fifo_size, | |
ac484963 | 874 | cpp, latency->display_hpll_disable); |
b445e3b0 ED |
875 | reg = I915_READ(DSPFW3); |
876 | reg &= ~DSPFW_HPLL_SR_MASK; | |
f4998963 | 877 | reg |= FW_WM(wm, HPLL_SR); |
b445e3b0 ED |
878 | I915_WRITE(DSPFW3, reg); |
879 | ||
880 | /* cursor HPLL off SR */ | |
881 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
882 | pineview_display_hplloff_wm.fifo_size, | |
99834b14 | 883 | 4, latency->cursor_hpll_disable); |
b445e3b0 ED |
884 | reg = I915_READ(DSPFW3); |
885 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
f4998963 | 886 | reg |= FW_WM(wm, HPLL_CURSOR); |
b445e3b0 ED |
887 | I915_WRITE(DSPFW3, reg); |
888 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
889 | ||
5209b1f4 | 890 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 891 | } else { |
5209b1f4 | 892 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
893 | } |
894 | } | |
895 | ||
0f95ff85 VS |
896 | /* |
897 | * Documentation says: | |
898 | * "If the line size is small, the TLB fetches can get in the way of the | |
899 | * data fetches, causing some lag in the pixel data return which is not | |
900 | * accounted for in the above formulas. The following adjustment only | |
901 | * needs to be applied if eight whole lines fit in the buffer at once. | |
902 | * The WM is adjusted upwards by the difference between the FIFO size | |
903 | * and the size of 8 whole lines. This adjustment is always performed | |
904 | * in the actual pixel depth regardless of whether FBC is enabled or not." | |
905 | */ | |
906 | static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp) | |
907 | { | |
908 | int tlb_miss = fifo_size * 64 - width * cpp * 8; | |
909 | ||
910 | return max(0, tlb_miss); | |
911 | } | |
912 | ||
04548cba VS |
913 | static void g4x_write_wm_values(struct drm_i915_private *dev_priv, |
914 | const struct g4x_wm_values *wm) | |
b445e3b0 | 915 | { |
04548cba VS |
916 | I915_WRITE(DSPFW1, |
917 | FW_WM(wm->sr.plane, SR) | | |
918 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | | |
919 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | | |
920 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); | |
921 | I915_WRITE(DSPFW2, | |
922 | (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | | |
923 | FW_WM(wm->sr.fbc, FBC_SR) | | |
924 | FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | | |
925 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | | |
926 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | | |
927 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); | |
928 | I915_WRITE(DSPFW3, | |
929 | (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) | | |
930 | FW_WM(wm->sr.cursor, CURSOR_SR) | | |
931 | FW_WM(wm->hpll.cursor, HPLL_CURSOR) | | |
932 | FW_WM(wm->hpll.plane, HPLL_SR)); | |
b445e3b0 | 933 | |
04548cba | 934 | POSTING_READ(DSPFW1); |
b445e3b0 ED |
935 | } |
936 | ||
15665979 VS |
937 | #define FW_WM_VLV(value, plane) \ |
938 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
939 | ||
50f4caef | 940 | static void vlv_write_wm_values(struct drm_i915_private *dev_priv, |
0018fda1 VS |
941 | const struct vlv_wm_values *wm) |
942 | { | |
50f4caef VS |
943 | enum pipe pipe; |
944 | ||
945 | for_each_pipe(dev_priv, pipe) { | |
c137d660 VS |
946 | trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); |
947 | ||
50f4caef VS |
948 | I915_WRITE(VLV_DDL(pipe), |
949 | (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | | |
950 | (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | | |
951 | (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | | |
952 | (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); | |
953 | } | |
0018fda1 | 954 | |
6fe6a7ff VS |
955 | /* |
956 | * Zero the (unused) WM1 watermarks, and also clear all the | |
957 | * high order bits so that there are no out of bounds values | |
958 | * present in the registers during the reprogramming. | |
959 | */ | |
960 | I915_WRITE(DSPHOWM, 0); | |
961 | I915_WRITE(DSPHOWM1, 0); | |
962 | I915_WRITE(DSPFW4, 0); | |
963 | I915_WRITE(DSPFW5, 0); | |
964 | I915_WRITE(DSPFW6, 0); | |
965 | ||
ae80152d | 966 | I915_WRITE(DSPFW1, |
15665979 | 967 | FW_WM(wm->sr.plane, SR) | |
1b31389c VS |
968 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | |
969 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | | |
970 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); | |
ae80152d | 971 | I915_WRITE(DSPFW2, |
1b31389c VS |
972 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | |
973 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | | |
974 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); | |
ae80152d | 975 | I915_WRITE(DSPFW3, |
15665979 | 976 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
977 | |
978 | if (IS_CHERRYVIEW(dev_priv)) { | |
979 | I915_WRITE(DSPFW7_CHV, | |
1b31389c VS |
980 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
981 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 982 | I915_WRITE(DSPFW8_CHV, |
1b31389c VS |
983 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | |
984 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); | |
ae80152d | 985 | I915_WRITE(DSPFW9_CHV, |
1b31389c VS |
986 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | |
987 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); | |
ae80152d | 988 | I915_WRITE(DSPHOWM, |
15665979 | 989 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
990 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | |
991 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | | |
992 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | | |
993 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | | |
994 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
995 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
996 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
997 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
998 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
999 | } else { |
1000 | I915_WRITE(DSPFW7, | |
1b31389c VS |
1001 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
1002 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 1003 | I915_WRITE(DSPHOWM, |
15665979 | 1004 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
1005 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | |
1006 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
1007 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
1008 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
1009 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
1010 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
1011 | } |
1012 | ||
1013 | POSTING_READ(DSPFW1); | |
0018fda1 VS |
1014 | } |
1015 | ||
15665979 VS |
1016 | #undef FW_WM_VLV |
1017 | ||
04548cba VS |
1018 | static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv) |
1019 | { | |
1020 | /* all latencies in usec */ | |
1021 | dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; | |
1022 | dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; | |
79d94306 | 1023 | dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; |
04548cba | 1024 | |
79d94306 | 1025 | dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL; |
04548cba VS |
1026 | } |
1027 | ||
1028 | static int g4x_plane_fifo_size(enum plane_id plane_id, int level) | |
1029 | { | |
1030 | /* | |
1031 | * DSPCNTR[13] supposedly controls whether the | |
1032 | * primary plane can use the FIFO space otherwise | |
1033 | * reserved for the sprite plane. It's not 100% clear | |
1034 | * what the actual FIFO size is, but it looks like we | |
1035 | * can happily set both primary and sprite watermarks | |
1036 | * up to 127 cachelines. So that would seem to mean | |
1037 | * that either DSPCNTR[13] doesn't do anything, or that | |
1038 | * the total FIFO is >= 256 cachelines in size. Either | |
1039 | * way, we don't seem to have to worry about this | |
1040 | * repartitioning as the maximum watermark value the | |
1041 | * register can hold for each plane is lower than the | |
1042 | * minimum FIFO size. | |
1043 | */ | |
1044 | switch (plane_id) { | |
1045 | case PLANE_CURSOR: | |
1046 | return 63; | |
1047 | case PLANE_PRIMARY: | |
1048 | return level == G4X_WM_LEVEL_NORMAL ? 127 : 511; | |
1049 | case PLANE_SPRITE0: | |
1050 | return level == G4X_WM_LEVEL_NORMAL ? 127 : 0; | |
1051 | default: | |
1052 | MISSING_CASE(plane_id); | |
1053 | return 0; | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | static int g4x_fbc_fifo_size(int level) | |
1058 | { | |
1059 | switch (level) { | |
1060 | case G4X_WM_LEVEL_SR: | |
1061 | return 7; | |
1062 | case G4X_WM_LEVEL_HPLL: | |
1063 | return 15; | |
1064 | default: | |
1065 | MISSING_CASE(level); | |
1066 | return 0; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state, | |
1071 | const struct intel_plane_state *plane_state, | |
1072 | int level) | |
1073 | { | |
1074 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
1075 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
1076 | const struct drm_display_mode *adjusted_mode = | |
1077 | &crtc_state->base.adjusted_mode; | |
1078 | int clock, htotal, cpp, width, wm; | |
1079 | int latency = dev_priv->wm.pri_latency[level] * 10; | |
1080 | ||
1081 | if (latency == 0) | |
1082 | return USHRT_MAX; | |
1083 | ||
1084 | if (!intel_wm_plane_visible(crtc_state, plane_state)) | |
1085 | return 0; | |
1086 | ||
1087 | /* | |
1088 | * Not 100% sure which way ELK should go here as the | |
1089 | * spec only says CL/CTG should assume 32bpp and BW | |
1090 | * doesn't need to. But as these things followed the | |
1091 | * mobile vs. desktop lines on gen3 as well, let's | |
1092 | * assume ELK doesn't need this. | |
1093 | * | |
1094 | * The spec also fails to list such a restriction for | |
1095 | * the HPLL watermark, which seems a little strange. | |
1096 | * Let's use 32bpp for the HPLL watermark as well. | |
1097 | */ | |
1098 | if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY && | |
1099 | level != G4X_WM_LEVEL_NORMAL) | |
1100 | cpp = 4; | |
1101 | else | |
1102 | cpp = plane_state->base.fb->format->cpp[0]; | |
1103 | ||
1104 | clock = adjusted_mode->crtc_clock; | |
1105 | htotal = adjusted_mode->crtc_htotal; | |
1106 | ||
1107 | if (plane->id == PLANE_CURSOR) | |
1108 | width = plane_state->base.crtc_w; | |
1109 | else | |
1110 | width = drm_rect_width(&plane_state->base.dst); | |
1111 | ||
1112 | if (plane->id == PLANE_CURSOR) { | |
1113 | wm = intel_wm_method2(clock, htotal, width, cpp, latency); | |
1114 | } else if (plane->id == PLANE_PRIMARY && | |
1115 | level == G4X_WM_LEVEL_NORMAL) { | |
1116 | wm = intel_wm_method1(clock, cpp, latency); | |
1117 | } else { | |
1118 | int small, large; | |
1119 | ||
1120 | small = intel_wm_method1(clock, cpp, latency); | |
1121 | large = intel_wm_method2(clock, htotal, width, cpp, latency); | |
1122 | ||
1123 | wm = min(small, large); | |
1124 | } | |
1125 | ||
1126 | wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level), | |
1127 | width, cpp); | |
1128 | ||
1129 | wm = DIV_ROUND_UP(wm, 64) + 2; | |
1130 | ||
1131 | return min_t(int, wm, USHRT_MAX); | |
1132 | } | |
1133 | ||
1134 | static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state, | |
1135 | int level, enum plane_id plane_id, u16 value) | |
1136 | { | |
1137 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1138 | bool dirty = false; | |
1139 | ||
1140 | for (; level < intel_wm_num_levels(dev_priv); level++) { | |
1141 | struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1142 | ||
1143 | dirty |= raw->plane[plane_id] != value; | |
1144 | raw->plane[plane_id] = value; | |
1145 | } | |
1146 | ||
1147 | return dirty; | |
1148 | } | |
1149 | ||
1150 | static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state, | |
1151 | int level, u16 value) | |
1152 | { | |
1153 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1154 | bool dirty = false; | |
1155 | ||
1156 | /* NORMAL level doesn't have an FBC watermark */ | |
1157 | level = max(level, G4X_WM_LEVEL_SR); | |
1158 | ||
1159 | for (; level < intel_wm_num_levels(dev_priv); level++) { | |
1160 | struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1161 | ||
1162 | dirty |= raw->fbc != value; | |
1163 | raw->fbc = value; | |
1164 | } | |
1165 | ||
1166 | return dirty; | |
1167 | } | |
1168 | ||
1169 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, | |
1170 | const struct intel_plane_state *pstate, | |
1171 | uint32_t pri_val); | |
1172 | ||
1173 | static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, | |
1174 | const struct intel_plane_state *plane_state) | |
1175 | { | |
1176 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
1177 | int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); | |
1178 | enum plane_id plane_id = plane->id; | |
1179 | bool dirty = false; | |
1180 | int level; | |
1181 | ||
1182 | if (!intel_wm_plane_visible(crtc_state, plane_state)) { | |
1183 | dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); | |
1184 | if (plane_id == PLANE_PRIMARY) | |
1185 | dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0); | |
1186 | goto out; | |
1187 | } | |
1188 | ||
1189 | for (level = 0; level < num_levels; level++) { | |
1190 | struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1191 | int wm, max_wm; | |
1192 | ||
1193 | wm = g4x_compute_wm(crtc_state, plane_state, level); | |
1194 | max_wm = g4x_plane_fifo_size(plane_id, level); | |
1195 | ||
1196 | if (wm > max_wm) | |
1197 | break; | |
1198 | ||
1199 | dirty |= raw->plane[plane_id] != wm; | |
1200 | raw->plane[plane_id] = wm; | |
1201 | ||
1202 | if (plane_id != PLANE_PRIMARY || | |
1203 | level == G4X_WM_LEVEL_NORMAL) | |
1204 | continue; | |
1205 | ||
1206 | wm = ilk_compute_fbc_wm(crtc_state, plane_state, | |
1207 | raw->plane[plane_id]); | |
1208 | max_wm = g4x_fbc_fifo_size(level); | |
1209 | ||
1210 | /* | |
1211 | * FBC wm is not mandatory as we | |
1212 | * can always just disable its use. | |
1213 | */ | |
1214 | if (wm > max_wm) | |
1215 | wm = USHRT_MAX; | |
1216 | ||
1217 | dirty |= raw->fbc != wm; | |
1218 | raw->fbc = wm; | |
1219 | } | |
1220 | ||
1221 | /* mark watermarks as invalid */ | |
1222 | dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); | |
1223 | ||
1224 | if (plane_id == PLANE_PRIMARY) | |
1225 | dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); | |
1226 | ||
1227 | out: | |
1228 | if (dirty) { | |
1229 | DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n", | |
1230 | plane->base.name, | |
1231 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], | |
1232 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], | |
1233 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); | |
1234 | ||
1235 | if (plane_id == PLANE_PRIMARY) | |
1236 | DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n", | |
1237 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, | |
1238 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); | |
1239 | } | |
1240 | ||
1241 | return dirty; | |
1242 | } | |
1243 | ||
1244 | static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, | |
1245 | enum plane_id plane_id, int level) | |
1246 | { | |
1247 | const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1248 | ||
1249 | return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level); | |
1250 | } | |
1251 | ||
1252 | static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, | |
1253 | int level) | |
1254 | { | |
1255 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1256 | ||
1257 | if (level > dev_priv->wm.max_level) | |
1258 | return false; | |
1259 | ||
1260 | return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && | |
1261 | g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && | |
1262 | g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); | |
1263 | } | |
1264 | ||
1265 | /* mark all levels starting from 'level' as invalid */ | |
1266 | static void g4x_invalidate_wms(struct intel_crtc *crtc, | |
1267 | struct g4x_wm_state *wm_state, int level) | |
1268 | { | |
1269 | if (level <= G4X_WM_LEVEL_NORMAL) { | |
1270 | enum plane_id plane_id; | |
1271 | ||
1272 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1273 | wm_state->wm.plane[plane_id] = USHRT_MAX; | |
1274 | } | |
1275 | ||
1276 | if (level <= G4X_WM_LEVEL_SR) { | |
1277 | wm_state->cxsr = false; | |
1278 | wm_state->sr.cursor = USHRT_MAX; | |
1279 | wm_state->sr.plane = USHRT_MAX; | |
1280 | wm_state->sr.fbc = USHRT_MAX; | |
1281 | } | |
1282 | ||
1283 | if (level <= G4X_WM_LEVEL_HPLL) { | |
1284 | wm_state->hpll_en = false; | |
1285 | wm_state->hpll.cursor = USHRT_MAX; | |
1286 | wm_state->hpll.plane = USHRT_MAX; | |
1287 | wm_state->hpll.fbc = USHRT_MAX; | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) | |
1292 | { | |
1293 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1294 | struct intel_atomic_state *state = | |
1295 | to_intel_atomic_state(crtc_state->base.state); | |
1296 | struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; | |
1297 | int num_active_planes = hweight32(crtc_state->active_planes & | |
1298 | ~BIT(PLANE_CURSOR)); | |
1299 | const struct g4x_pipe_wm *raw; | |
1300 | struct intel_plane_state *plane_state; | |
1301 | struct intel_plane *plane; | |
1302 | enum plane_id plane_id; | |
1303 | int i, level; | |
1304 | unsigned int dirty = 0; | |
1305 | ||
1306 | for_each_intel_plane_in_state(state, plane, plane_state, i) { | |
1307 | const struct intel_plane_state *old_plane_state = | |
1308 | to_intel_plane_state(plane->base.state); | |
1309 | ||
1310 | if (plane_state->base.crtc != &crtc->base && | |
1311 | old_plane_state->base.crtc != &crtc->base) | |
1312 | continue; | |
1313 | ||
1314 | if (g4x_raw_plane_wm_compute(crtc_state, plane_state)) | |
1315 | dirty |= BIT(plane->id); | |
1316 | } | |
1317 | ||
1318 | if (!dirty) | |
1319 | return 0; | |
1320 | ||
1321 | level = G4X_WM_LEVEL_NORMAL; | |
1322 | if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) | |
1323 | goto out; | |
1324 | ||
1325 | raw = &crtc_state->wm.g4x.raw[level]; | |
1326 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1327 | wm_state->wm.plane[plane_id] = raw->plane[plane_id]; | |
1328 | ||
1329 | level = G4X_WM_LEVEL_SR; | |
1330 | ||
1331 | if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) | |
1332 | goto out; | |
1333 | ||
1334 | raw = &crtc_state->wm.g4x.raw[level]; | |
1335 | wm_state->sr.plane = raw->plane[PLANE_PRIMARY]; | |
1336 | wm_state->sr.cursor = raw->plane[PLANE_CURSOR]; | |
1337 | wm_state->sr.fbc = raw->fbc; | |
1338 | ||
1339 | wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); | |
1340 | ||
1341 | level = G4X_WM_LEVEL_HPLL; | |
1342 | ||
1343 | if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) | |
1344 | goto out; | |
1345 | ||
1346 | raw = &crtc_state->wm.g4x.raw[level]; | |
1347 | wm_state->hpll.plane = raw->plane[PLANE_PRIMARY]; | |
1348 | wm_state->hpll.cursor = raw->plane[PLANE_CURSOR]; | |
1349 | wm_state->hpll.fbc = raw->fbc; | |
1350 | ||
1351 | wm_state->hpll_en = wm_state->cxsr; | |
1352 | ||
1353 | level++; | |
1354 | ||
1355 | out: | |
1356 | if (level == G4X_WM_LEVEL_NORMAL) | |
1357 | return -EINVAL; | |
1358 | ||
1359 | /* invalidate the higher levels */ | |
1360 | g4x_invalidate_wms(crtc, wm_state, level); | |
1361 | ||
1362 | /* | |
1363 | * Determine if the FBC watermark(s) can be used. IF | |
1364 | * this isn't the case we prefer to disable the FBC | |
1365 | ( watermark(s) rather than disable the SR/HPLL | |
1366 | * level(s) entirely. | |
1367 | */ | |
1368 | wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL; | |
1369 | ||
1370 | if (level >= G4X_WM_LEVEL_SR && | |
1371 | wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) | |
1372 | wm_state->fbc_en = false; | |
1373 | else if (level >= G4X_WM_LEVEL_HPLL && | |
1374 | wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL)) | |
1375 | wm_state->fbc_en = false; | |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static int g4x_compute_intermediate_wm(struct drm_device *dev, | |
1381 | struct intel_crtc *crtc, | |
1382 | struct intel_crtc_state *crtc_state) | |
1383 | { | |
1384 | struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate; | |
1385 | const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal; | |
1386 | const struct g4x_wm_state *active = &crtc->wm.active.g4x; | |
1387 | enum plane_id plane_id; | |
1388 | ||
1389 | intermediate->cxsr = optimal->cxsr && active->cxsr && | |
1390 | !crtc_state->disable_cxsr; | |
1391 | intermediate->hpll_en = optimal->hpll_en && active->hpll_en && | |
1392 | !crtc_state->disable_cxsr; | |
1393 | intermediate->fbc_en = optimal->fbc_en && active->fbc_en; | |
1394 | ||
1395 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
1396 | intermediate->wm.plane[plane_id] = | |
1397 | max(optimal->wm.plane[plane_id], | |
1398 | active->wm.plane[plane_id]); | |
1399 | ||
1400 | WARN_ON(intermediate->wm.plane[plane_id] > | |
1401 | g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL)); | |
1402 | } | |
1403 | ||
1404 | intermediate->sr.plane = max(optimal->sr.plane, | |
1405 | active->sr.plane); | |
1406 | intermediate->sr.cursor = max(optimal->sr.cursor, | |
1407 | active->sr.cursor); | |
1408 | intermediate->sr.fbc = max(optimal->sr.fbc, | |
1409 | active->sr.fbc); | |
1410 | ||
1411 | intermediate->hpll.plane = max(optimal->hpll.plane, | |
1412 | active->hpll.plane); | |
1413 | intermediate->hpll.cursor = max(optimal->hpll.cursor, | |
1414 | active->hpll.cursor); | |
1415 | intermediate->hpll.fbc = max(optimal->hpll.fbc, | |
1416 | active->hpll.fbc); | |
1417 | ||
1418 | WARN_ON((intermediate->sr.plane > | |
1419 | g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) || | |
1420 | intermediate->sr.cursor > | |
1421 | g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) && | |
1422 | intermediate->cxsr); | |
1423 | WARN_ON((intermediate->sr.plane > | |
1424 | g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) || | |
1425 | intermediate->sr.cursor > | |
1426 | g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) && | |
1427 | intermediate->hpll_en); | |
1428 | ||
1429 | WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) && | |
1430 | intermediate->fbc_en && intermediate->cxsr); | |
1431 | WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) && | |
1432 | intermediate->fbc_en && intermediate->hpll_en); | |
1433 | ||
1434 | /* | |
1435 | * If our intermediate WM are identical to the final WM, then we can | |
1436 | * omit the post-vblank programming; only update if it's different. | |
1437 | */ | |
1438 | if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0) | |
1439 | crtc_state->wm.need_postvbl_update = true; | |
1440 | ||
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | static void g4x_merge_wm(struct drm_i915_private *dev_priv, | |
1445 | struct g4x_wm_values *wm) | |
1446 | { | |
1447 | struct intel_crtc *crtc; | |
1448 | int num_active_crtcs = 0; | |
1449 | ||
1450 | wm->cxsr = true; | |
1451 | wm->hpll_en = true; | |
1452 | wm->fbc_en = true; | |
1453 | ||
1454 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
1455 | const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; | |
1456 | ||
1457 | if (!crtc->active) | |
1458 | continue; | |
1459 | ||
1460 | if (!wm_state->cxsr) | |
1461 | wm->cxsr = false; | |
1462 | if (!wm_state->hpll_en) | |
1463 | wm->hpll_en = false; | |
1464 | if (!wm_state->fbc_en) | |
1465 | wm->fbc_en = false; | |
1466 | ||
1467 | num_active_crtcs++; | |
1468 | } | |
1469 | ||
1470 | if (num_active_crtcs != 1) { | |
1471 | wm->cxsr = false; | |
1472 | wm->hpll_en = false; | |
1473 | wm->fbc_en = false; | |
1474 | } | |
1475 | ||
1476 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
1477 | const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; | |
1478 | enum pipe pipe = crtc->pipe; | |
1479 | ||
1480 | wm->pipe[pipe] = wm_state->wm; | |
1481 | if (crtc->active && wm->cxsr) | |
1482 | wm->sr = wm_state->sr; | |
1483 | if (crtc->active && wm->hpll_en) | |
1484 | wm->hpll = wm_state->hpll; | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | static void g4x_program_watermarks(struct drm_i915_private *dev_priv) | |
1489 | { | |
1490 | struct g4x_wm_values *old_wm = &dev_priv->wm.g4x; | |
1491 | struct g4x_wm_values new_wm = {}; | |
1492 | ||
1493 | g4x_merge_wm(dev_priv, &new_wm); | |
1494 | ||
1495 | if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) | |
1496 | return; | |
1497 | ||
1498 | if (is_disabling(old_wm->cxsr, new_wm.cxsr, true)) | |
1499 | _intel_set_memory_cxsr(dev_priv, false); | |
1500 | ||
1501 | g4x_write_wm_values(dev_priv, &new_wm); | |
1502 | ||
1503 | if (is_enabling(old_wm->cxsr, new_wm.cxsr, true)) | |
1504 | _intel_set_memory_cxsr(dev_priv, true); | |
1505 | ||
1506 | *old_wm = new_wm; | |
1507 | } | |
1508 | ||
1509 | static void g4x_initial_watermarks(struct intel_atomic_state *state, | |
1510 | struct intel_crtc_state *crtc_state) | |
1511 | { | |
1512 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1513 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1514 | ||
1515 | mutex_lock(&dev_priv->wm.wm_mutex); | |
1516 | crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; | |
1517 | g4x_program_watermarks(dev_priv); | |
1518 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1519 | } | |
1520 | ||
1521 | static void g4x_optimize_watermarks(struct intel_atomic_state *state, | |
1522 | struct intel_crtc_state *crtc_state) | |
1523 | { | |
1524 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1525 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
1526 | ||
1527 | if (!crtc_state->wm.need_postvbl_update) | |
1528 | return; | |
1529 | ||
1530 | mutex_lock(&dev_priv->wm.wm_mutex); | |
1531 | intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; | |
1532 | g4x_program_watermarks(dev_priv); | |
1533 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1534 | } | |
1535 | ||
262cd2e1 VS |
1536 | /* latency must be in 0.1us units. */ |
1537 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, | |
baf69ca8 VS |
1538 | unsigned int htotal, |
1539 | unsigned int width, | |
ac484963 | 1540 | unsigned int cpp, |
262cd2e1 VS |
1541 | unsigned int latency) |
1542 | { | |
1543 | unsigned int ret; | |
1544 | ||
baf69ca8 VS |
1545 | ret = intel_wm_method2(pixel_rate, htotal, |
1546 | width, cpp, latency); | |
262cd2e1 VS |
1547 | ret = DIV_ROUND_UP(ret, 64); |
1548 | ||
1549 | return ret; | |
1550 | } | |
1551 | ||
bb726519 | 1552 | static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv) |
262cd2e1 | 1553 | { |
262cd2e1 VS |
1554 | /* all latencies in usec */ |
1555 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; | |
1556 | ||
58590c14 VS |
1557 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
1558 | ||
262cd2e1 VS |
1559 | if (IS_CHERRYVIEW(dev_priv)) { |
1560 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; | |
1561 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; | |
58590c14 VS |
1562 | |
1563 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; | |
262cd2e1 VS |
1564 | } |
1565 | } | |
1566 | ||
e339d67e VS |
1567 | static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, |
1568 | const struct intel_plane_state *plane_state, | |
262cd2e1 VS |
1569 | int level) |
1570 | { | |
e339d67e | 1571 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
262cd2e1 | 1572 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
e339d67e VS |
1573 | const struct drm_display_mode *adjusted_mode = |
1574 | &crtc_state->base.adjusted_mode; | |
ac484963 | 1575 | int clock, htotal, cpp, width, wm; |
262cd2e1 VS |
1576 | |
1577 | if (dev_priv->wm.pri_latency[level] == 0) | |
1578 | return USHRT_MAX; | |
1579 | ||
a07102f1 | 1580 | if (!intel_wm_plane_visible(crtc_state, plane_state)) |
262cd2e1 VS |
1581 | return 0; |
1582 | ||
ef426c10 | 1583 | cpp = plane_state->base.fb->format->cpp[0]; |
e339d67e VS |
1584 | clock = adjusted_mode->crtc_clock; |
1585 | htotal = adjusted_mode->crtc_htotal; | |
1586 | width = crtc_state->pipe_src_w; | |
262cd2e1 | 1587 | |
709f3fc9 | 1588 | if (plane->id == PLANE_CURSOR) { |
262cd2e1 VS |
1589 | /* |
1590 | * FIXME the formula gives values that are | |
1591 | * too big for the cursor FIFO, and hence we | |
1592 | * would never be able to use cursors. For | |
1593 | * now just hardcode the watermark. | |
1594 | */ | |
1595 | wm = 63; | |
1596 | } else { | |
ac484963 | 1597 | wm = vlv_wm_method2(clock, htotal, width, cpp, |
262cd2e1 VS |
1598 | dev_priv->wm.pri_latency[level] * 10); |
1599 | } | |
1600 | ||
1601 | return min_t(int, wm, USHRT_MAX); | |
1602 | } | |
1603 | ||
1a10ae6b VS |
1604 | static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes) |
1605 | { | |
1606 | return (active_planes & (BIT(PLANE_SPRITE0) | | |
1607 | BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1); | |
1608 | } | |
1609 | ||
5012e604 | 1610 | static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) |
54f1b6e1 | 1611 | { |
855c79f5 | 1612 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
114d7dc0 | 1613 | const struct g4x_pipe_wm *raw = |
5012e604 | 1614 | &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; |
814e7f0b | 1615 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
5012e604 VS |
1616 | unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); |
1617 | int num_active_planes = hweight32(active_planes); | |
1618 | const int fifo_size = 511; | |
54f1b6e1 | 1619 | int fifo_extra, fifo_left = fifo_size; |
1a10ae6b | 1620 | int sprite0_fifo_extra = 0; |
5012e604 VS |
1621 | unsigned int total_rate; |
1622 | enum plane_id plane_id; | |
54f1b6e1 | 1623 | |
1a10ae6b VS |
1624 | /* |
1625 | * When enabling sprite0 after sprite1 has already been enabled | |
1626 | * we tend to get an underrun unless sprite0 already has some | |
1627 | * FIFO space allcoated. Hence we always allocate at least one | |
1628 | * cacheline for sprite0 whenever sprite1 is enabled. | |
1629 | * | |
1630 | * All other plane enable sequences appear immune to this problem. | |
1631 | */ | |
1632 | if (vlv_need_sprite0_fifo_workaround(active_planes)) | |
1633 | sprite0_fifo_extra = 1; | |
1634 | ||
5012e604 VS |
1635 | total_rate = raw->plane[PLANE_PRIMARY] + |
1636 | raw->plane[PLANE_SPRITE0] + | |
1a10ae6b VS |
1637 | raw->plane[PLANE_SPRITE1] + |
1638 | sprite0_fifo_extra; | |
54f1b6e1 | 1639 | |
5012e604 VS |
1640 | if (total_rate > fifo_size) |
1641 | return -EINVAL; | |
54f1b6e1 | 1642 | |
5012e604 VS |
1643 | if (total_rate == 0) |
1644 | total_rate = 1; | |
54f1b6e1 | 1645 | |
5012e604 | 1646 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1647 | unsigned int rate; |
1648 | ||
5012e604 VS |
1649 | if ((active_planes & BIT(plane_id)) == 0) { |
1650 | fifo_state->plane[plane_id] = 0; | |
54f1b6e1 VS |
1651 | continue; |
1652 | } | |
1653 | ||
5012e604 VS |
1654 | rate = raw->plane[plane_id]; |
1655 | fifo_state->plane[plane_id] = fifo_size * rate / total_rate; | |
1656 | fifo_left -= fifo_state->plane[plane_id]; | |
54f1b6e1 VS |
1657 | } |
1658 | ||
1a10ae6b VS |
1659 | fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra; |
1660 | fifo_left -= sprite0_fifo_extra; | |
1661 | ||
5012e604 VS |
1662 | fifo_state->plane[PLANE_CURSOR] = 63; |
1663 | ||
1664 | fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1); | |
54f1b6e1 VS |
1665 | |
1666 | /* spread the remainder evenly */ | |
5012e604 | 1667 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1668 | int plane_extra; |
1669 | ||
1670 | if (fifo_left == 0) | |
1671 | break; | |
1672 | ||
5012e604 | 1673 | if ((active_planes & BIT(plane_id)) == 0) |
54f1b6e1 VS |
1674 | continue; |
1675 | ||
1676 | plane_extra = min(fifo_extra, fifo_left); | |
5012e604 | 1677 | fifo_state->plane[plane_id] += plane_extra; |
54f1b6e1 VS |
1678 | fifo_left -= plane_extra; |
1679 | } | |
1680 | ||
5012e604 VS |
1681 | WARN_ON(active_planes != 0 && fifo_left != 0); |
1682 | ||
1683 | /* give it all to the first plane if none are active */ | |
1684 | if (active_planes == 0) { | |
1685 | WARN_ON(fifo_left != fifo_size); | |
1686 | fifo_state->plane[PLANE_PRIMARY] = fifo_left; | |
1687 | } | |
1688 | ||
1689 | return 0; | |
54f1b6e1 VS |
1690 | } |
1691 | ||
ff32c54e VS |
1692 | /* mark all levels starting from 'level' as invalid */ |
1693 | static void vlv_invalidate_wms(struct intel_crtc *crtc, | |
1694 | struct vlv_wm_state *wm_state, int level) | |
1695 | { | |
1696 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1697 | ||
6d5019b6 | 1698 | for (; level < intel_wm_num_levels(dev_priv); level++) { |
ff32c54e VS |
1699 | enum plane_id plane_id; |
1700 | ||
1701 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1702 | wm_state->wm[level].plane[plane_id] = USHRT_MAX; | |
1703 | ||
1704 | wm_state->sr[level].cursor = USHRT_MAX; | |
1705 | wm_state->sr[level].plane = USHRT_MAX; | |
1706 | } | |
1707 | } | |
1708 | ||
26cca0e5 VS |
1709 | static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) |
1710 | { | |
1711 | if (wm > fifo_size) | |
1712 | return USHRT_MAX; | |
1713 | else | |
1714 | return fifo_size - wm; | |
1715 | } | |
1716 | ||
ff32c54e VS |
1717 | /* |
1718 | * Starting from 'level' set all higher | |
1719 | * levels to 'value' in the "raw" watermarks. | |
1720 | */ | |
236c48e6 | 1721 | static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state, |
ff32c54e | 1722 | int level, enum plane_id plane_id, u16 value) |
262cd2e1 | 1723 | { |
ff32c54e | 1724 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
6d5019b6 | 1725 | int num_levels = intel_wm_num_levels(dev_priv); |
236c48e6 | 1726 | bool dirty = false; |
262cd2e1 | 1727 | |
ff32c54e | 1728 | for (; level < num_levels; level++) { |
114d7dc0 | 1729 | struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
262cd2e1 | 1730 | |
236c48e6 | 1731 | dirty |= raw->plane[plane_id] != value; |
ff32c54e | 1732 | raw->plane[plane_id] = value; |
262cd2e1 | 1733 | } |
236c48e6 VS |
1734 | |
1735 | return dirty; | |
262cd2e1 VS |
1736 | } |
1737 | ||
77d14ee4 VS |
1738 | static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, |
1739 | const struct intel_plane_state *plane_state) | |
262cd2e1 | 1740 | { |
ff32c54e VS |
1741 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
1742 | enum plane_id plane_id = plane->id; | |
6d5019b6 | 1743 | int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); |
262cd2e1 | 1744 | int level; |
236c48e6 | 1745 | bool dirty = false; |
262cd2e1 | 1746 | |
a07102f1 | 1747 | if (!intel_wm_plane_visible(crtc_state, plane_state)) { |
236c48e6 VS |
1748 | dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0); |
1749 | goto out; | |
ff32c54e | 1750 | } |
262cd2e1 | 1751 | |
ff32c54e | 1752 | for (level = 0; level < num_levels; level++) { |
114d7dc0 | 1753 | struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
ff32c54e VS |
1754 | int wm = vlv_compute_wm_level(crtc_state, plane_state, level); |
1755 | int max_wm = plane_id == PLANE_CURSOR ? 63 : 511; | |
262cd2e1 | 1756 | |
ff32c54e VS |
1757 | if (wm > max_wm) |
1758 | break; | |
262cd2e1 | 1759 | |
236c48e6 | 1760 | dirty |= raw->plane[plane_id] != wm; |
ff32c54e VS |
1761 | raw->plane[plane_id] = wm; |
1762 | } | |
262cd2e1 | 1763 | |
ff32c54e | 1764 | /* mark all higher levels as invalid */ |
236c48e6 | 1765 | dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); |
262cd2e1 | 1766 | |
236c48e6 VS |
1767 | out: |
1768 | if (dirty) | |
57a6528a | 1769 | DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n", |
236c48e6 VS |
1770 | plane->base.name, |
1771 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], | |
1772 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], | |
1773 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); | |
1774 | ||
1775 | return dirty; | |
ff32c54e | 1776 | } |
262cd2e1 | 1777 | |
77d14ee4 VS |
1778 | static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, |
1779 | enum plane_id plane_id, int level) | |
ff32c54e | 1780 | { |
114d7dc0 | 1781 | const struct g4x_pipe_wm *raw = |
ff32c54e VS |
1782 | &crtc_state->wm.vlv.raw[level]; |
1783 | const struct vlv_fifo_state *fifo_state = | |
1784 | &crtc_state->wm.vlv.fifo_state; | |
262cd2e1 | 1785 | |
ff32c54e VS |
1786 | return raw->plane[plane_id] <= fifo_state->plane[plane_id]; |
1787 | } | |
262cd2e1 | 1788 | |
77d14ee4 | 1789 | static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level) |
ff32c54e | 1790 | { |
77d14ee4 VS |
1791 | return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && |
1792 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && | |
1793 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) && | |
1794 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); | |
ff32c54e VS |
1795 | } |
1796 | ||
1797 | static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) | |
1798 | { | |
1799 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1800 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1801 | struct intel_atomic_state *state = | |
1802 | to_intel_atomic_state(crtc_state->base.state); | |
1803 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
1804 | const struct vlv_fifo_state *fifo_state = | |
1805 | &crtc_state->wm.vlv.fifo_state; | |
1806 | int num_active_planes = hweight32(crtc_state->active_planes & | |
1807 | ~BIT(PLANE_CURSOR)); | |
236c48e6 | 1808 | bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); |
ff32c54e VS |
1809 | struct intel_plane_state *plane_state; |
1810 | struct intel_plane *plane; | |
1811 | enum plane_id plane_id; | |
1812 | int level, ret, i; | |
236c48e6 | 1813 | unsigned int dirty = 0; |
ff32c54e VS |
1814 | |
1815 | for_each_intel_plane_in_state(state, plane, plane_state, i) { | |
1816 | const struct intel_plane_state *old_plane_state = | |
1817 | to_intel_plane_state(plane->base.state); | |
1818 | ||
1819 | if (plane_state->base.crtc != &crtc->base && | |
1820 | old_plane_state->base.crtc != &crtc->base) | |
1821 | continue; | |
262cd2e1 | 1822 | |
77d14ee4 | 1823 | if (vlv_raw_plane_wm_compute(crtc_state, plane_state)) |
236c48e6 VS |
1824 | dirty |= BIT(plane->id); |
1825 | } | |
1826 | ||
1827 | /* | |
1828 | * DSPARB registers may have been reset due to the | |
1829 | * power well being turned off. Make sure we restore | |
1830 | * them to a consistent state even if no primary/sprite | |
1831 | * planes are initially active. | |
1832 | */ | |
1833 | if (needs_modeset) | |
1834 | crtc_state->fifo_changed = true; | |
1835 | ||
1836 | if (!dirty) | |
1837 | return 0; | |
1838 | ||
1839 | /* cursor changes don't warrant a FIFO recompute */ | |
1840 | if (dirty & ~BIT(PLANE_CURSOR)) { | |
1841 | const struct intel_crtc_state *old_crtc_state = | |
1842 | to_intel_crtc_state(crtc->base.state); | |
1843 | const struct vlv_fifo_state *old_fifo_state = | |
1844 | &old_crtc_state->wm.vlv.fifo_state; | |
1845 | ||
1846 | ret = vlv_compute_fifo(crtc_state); | |
1847 | if (ret) | |
1848 | return ret; | |
1849 | ||
1850 | if (needs_modeset || | |
1851 | memcmp(old_fifo_state, fifo_state, | |
1852 | sizeof(*fifo_state)) != 0) | |
1853 | crtc_state->fifo_changed = true; | |
5012e604 | 1854 | } |
262cd2e1 | 1855 | |
ff32c54e | 1856 | /* initially allow all levels */ |
6d5019b6 | 1857 | wm_state->num_levels = intel_wm_num_levels(dev_priv); |
ff32c54e VS |
1858 | /* |
1859 | * Note that enabling cxsr with no primary/sprite planes | |
1860 | * enabled can wedge the pipe. Hence we only allow cxsr | |
1861 | * with exactly one enabled primary/sprite plane. | |
1862 | */ | |
5eeb798b | 1863 | wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; |
ff32c54e | 1864 | |
5012e604 | 1865 | for (level = 0; level < wm_state->num_levels; level++) { |
114d7dc0 | 1866 | const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
ff32c54e | 1867 | const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; |
5012e604 | 1868 | |
77d14ee4 | 1869 | if (!vlv_raw_crtc_wm_is_valid(crtc_state, level)) |
ff32c54e | 1870 | break; |
5012e604 | 1871 | |
ff32c54e VS |
1872 | for_each_plane_id_on_crtc(crtc, plane_id) { |
1873 | wm_state->wm[level].plane[plane_id] = | |
1874 | vlv_invert_wm_value(raw->plane[plane_id], | |
1875 | fifo_state->plane[plane_id]); | |
1876 | } | |
1877 | ||
1878 | wm_state->sr[level].plane = | |
1879 | vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY], | |
5012e604 | 1880 | raw->plane[PLANE_SPRITE0], |
ff32c54e VS |
1881 | raw->plane[PLANE_SPRITE1]), |
1882 | sr_fifo_size); | |
262cd2e1 | 1883 | |
ff32c54e VS |
1884 | wm_state->sr[level].cursor = |
1885 | vlv_invert_wm_value(raw->plane[PLANE_CURSOR], | |
1886 | 63); | |
262cd2e1 VS |
1887 | } |
1888 | ||
ff32c54e VS |
1889 | if (level == 0) |
1890 | return -EINVAL; | |
1891 | ||
1892 | /* limit to only levels we can actually handle */ | |
1893 | wm_state->num_levels = level; | |
1894 | ||
1895 | /* invalidate the higher levels */ | |
1896 | vlv_invalidate_wms(crtc, wm_state, level); | |
1897 | ||
1898 | return 0; | |
262cd2e1 VS |
1899 | } |
1900 | ||
54f1b6e1 VS |
1901 | #define VLV_FIFO(plane, value) \ |
1902 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) | |
1903 | ||
ff32c54e VS |
1904 | static void vlv_atomic_update_fifo(struct intel_atomic_state *state, |
1905 | struct intel_crtc_state *crtc_state) | |
54f1b6e1 | 1906 | { |
814e7f0b | 1907 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 1908 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b VS |
1909 | const struct vlv_fifo_state *fifo_state = |
1910 | &crtc_state->wm.vlv.fifo_state; | |
f07d43d2 | 1911 | int sprite0_start, sprite1_start, fifo_size; |
54f1b6e1 | 1912 | |
236c48e6 VS |
1913 | if (!crtc_state->fifo_changed) |
1914 | return; | |
1915 | ||
f07d43d2 VS |
1916 | sprite0_start = fifo_state->plane[PLANE_PRIMARY]; |
1917 | sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start; | |
1918 | fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start; | |
54f1b6e1 | 1919 | |
f07d43d2 VS |
1920 | WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63); |
1921 | WARN_ON(fifo_size != 511); | |
54f1b6e1 | 1922 | |
c137d660 VS |
1923 | trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size); |
1924 | ||
44e921d4 VS |
1925 | /* |
1926 | * uncore.lock serves a double purpose here. It allows us to | |
1927 | * use the less expensive I915_{READ,WRITE}_FW() functions, and | |
1928 | * it protects the DSPARB registers from getting clobbered by | |
1929 | * parallel updates from multiple pipes. | |
1930 | * | |
1931 | * intel_pipe_update_start() has already disabled interrupts | |
1932 | * for us, so a plain spin_lock() is sufficient here. | |
1933 | */ | |
1934 | spin_lock(&dev_priv->uncore.lock); | |
467a14d9 | 1935 | |
54f1b6e1 VS |
1936 | switch (crtc->pipe) { |
1937 | uint32_t dsparb, dsparb2, dsparb3; | |
1938 | case PIPE_A: | |
44e921d4 VS |
1939 | dsparb = I915_READ_FW(DSPARB); |
1940 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1941 | |
1942 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | | |
1943 | VLV_FIFO(SPRITEB, 0xff)); | |
1944 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | | |
1945 | VLV_FIFO(SPRITEB, sprite1_start)); | |
1946 | ||
1947 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | | |
1948 | VLV_FIFO(SPRITEB_HI, 0x1)); | |
1949 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | | |
1950 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); | |
1951 | ||
44e921d4 VS |
1952 | I915_WRITE_FW(DSPARB, dsparb); |
1953 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1954 | break; |
1955 | case PIPE_B: | |
44e921d4 VS |
1956 | dsparb = I915_READ_FW(DSPARB); |
1957 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1958 | |
1959 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | | |
1960 | VLV_FIFO(SPRITED, 0xff)); | |
1961 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | | |
1962 | VLV_FIFO(SPRITED, sprite1_start)); | |
1963 | ||
1964 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | | |
1965 | VLV_FIFO(SPRITED_HI, 0xff)); | |
1966 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | | |
1967 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); | |
1968 | ||
44e921d4 VS |
1969 | I915_WRITE_FW(DSPARB, dsparb); |
1970 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1971 | break; |
1972 | case PIPE_C: | |
44e921d4 VS |
1973 | dsparb3 = I915_READ_FW(DSPARB3); |
1974 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1975 | |
1976 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | | |
1977 | VLV_FIFO(SPRITEF, 0xff)); | |
1978 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | | |
1979 | VLV_FIFO(SPRITEF, sprite1_start)); | |
1980 | ||
1981 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | | |
1982 | VLV_FIFO(SPRITEF_HI, 0xff)); | |
1983 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | | |
1984 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); | |
1985 | ||
44e921d4 VS |
1986 | I915_WRITE_FW(DSPARB3, dsparb3); |
1987 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1988 | break; |
1989 | default: | |
1990 | break; | |
1991 | } | |
467a14d9 | 1992 | |
44e921d4 | 1993 | POSTING_READ_FW(DSPARB); |
467a14d9 | 1994 | |
44e921d4 | 1995 | spin_unlock(&dev_priv->uncore.lock); |
54f1b6e1 VS |
1996 | } |
1997 | ||
1998 | #undef VLV_FIFO | |
1999 | ||
4841da51 VS |
2000 | static int vlv_compute_intermediate_wm(struct drm_device *dev, |
2001 | struct intel_crtc *crtc, | |
2002 | struct intel_crtc_state *crtc_state) | |
2003 | { | |
2004 | struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate; | |
2005 | const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal; | |
2006 | const struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
2007 | int level; | |
2008 | ||
2009 | intermediate->num_levels = min(optimal->num_levels, active->num_levels); | |
5eeb798b VS |
2010 | intermediate->cxsr = optimal->cxsr && active->cxsr && |
2011 | !crtc_state->disable_cxsr; | |
4841da51 VS |
2012 | |
2013 | for (level = 0; level < intermediate->num_levels; level++) { | |
2014 | enum plane_id plane_id; | |
2015 | ||
2016 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
2017 | intermediate->wm[level].plane[plane_id] = | |
2018 | min(optimal->wm[level].plane[plane_id], | |
2019 | active->wm[level].plane[plane_id]); | |
2020 | } | |
2021 | ||
2022 | intermediate->sr[level].plane = min(optimal->sr[level].plane, | |
2023 | active->sr[level].plane); | |
2024 | intermediate->sr[level].cursor = min(optimal->sr[level].cursor, | |
2025 | active->sr[level].cursor); | |
2026 | } | |
2027 | ||
2028 | vlv_invalidate_wms(crtc, intermediate, level); | |
2029 | ||
2030 | /* | |
2031 | * If our intermediate WM are identical to the final WM, then we can | |
2032 | * omit the post-vblank programming; only update if it's different. | |
2033 | */ | |
5eeb798b VS |
2034 | if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0) |
2035 | crtc_state->wm.need_postvbl_update = true; | |
4841da51 VS |
2036 | |
2037 | return 0; | |
2038 | } | |
2039 | ||
7c951c00 | 2040 | static void vlv_merge_wm(struct drm_i915_private *dev_priv, |
262cd2e1 VS |
2041 | struct vlv_wm_values *wm) |
2042 | { | |
2043 | struct intel_crtc *crtc; | |
2044 | int num_active_crtcs = 0; | |
2045 | ||
7c951c00 | 2046 | wm->level = dev_priv->wm.max_level; |
262cd2e1 VS |
2047 | wm->cxsr = true; |
2048 | ||
7c951c00 | 2049 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 2050 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
2051 | |
2052 | if (!crtc->active) | |
2053 | continue; | |
2054 | ||
2055 | if (!wm_state->cxsr) | |
2056 | wm->cxsr = false; | |
2057 | ||
2058 | num_active_crtcs++; | |
2059 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); | |
2060 | } | |
2061 | ||
2062 | if (num_active_crtcs != 1) | |
2063 | wm->cxsr = false; | |
2064 | ||
6f9c784b VS |
2065 | if (num_active_crtcs > 1) |
2066 | wm->level = VLV_WM_LEVEL_PM2; | |
2067 | ||
7c951c00 | 2068 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 2069 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
2070 | enum pipe pipe = crtc->pipe; |
2071 | ||
262cd2e1 | 2072 | wm->pipe[pipe] = wm_state->wm[wm->level]; |
ff32c54e | 2073 | if (crtc->active && wm->cxsr) |
262cd2e1 VS |
2074 | wm->sr = wm_state->sr[wm->level]; |
2075 | ||
1b31389c VS |
2076 | wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; |
2077 | wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; | |
2078 | wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; | |
2079 | wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; | |
262cd2e1 VS |
2080 | } |
2081 | } | |
2082 | ||
ff32c54e | 2083 | static void vlv_program_watermarks(struct drm_i915_private *dev_priv) |
262cd2e1 | 2084 | { |
fa292a4b VS |
2085 | struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; |
2086 | struct vlv_wm_values new_wm = {}; | |
262cd2e1 | 2087 | |
fa292a4b | 2088 | vlv_merge_wm(dev_priv, &new_wm); |
262cd2e1 | 2089 | |
ff32c54e | 2090 | if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) |
262cd2e1 VS |
2091 | return; |
2092 | ||
fa292a4b | 2093 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
2094 | chv_set_memory_dvfs(dev_priv, false); |
2095 | ||
fa292a4b | 2096 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
2097 | chv_set_memory_pm5(dev_priv, false); |
2098 | ||
fa292a4b | 2099 | if (is_disabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 2100 | _intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 2101 | |
fa292a4b | 2102 | vlv_write_wm_values(dev_priv, &new_wm); |
262cd2e1 | 2103 | |
fa292a4b | 2104 | if (is_enabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 2105 | _intel_set_memory_cxsr(dev_priv, true); |
262cd2e1 | 2106 | |
fa292a4b | 2107 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
2108 | chv_set_memory_pm5(dev_priv, true); |
2109 | ||
fa292a4b | 2110 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
2111 | chv_set_memory_dvfs(dev_priv, true); |
2112 | ||
fa292a4b | 2113 | *old_wm = new_wm; |
3c2777fd VS |
2114 | } |
2115 | ||
ff32c54e VS |
2116 | static void vlv_initial_watermarks(struct intel_atomic_state *state, |
2117 | struct intel_crtc_state *crtc_state) | |
2118 | { | |
2119 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
2120 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
2121 | ||
2122 | mutex_lock(&dev_priv->wm.wm_mutex); | |
4841da51 VS |
2123 | crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; |
2124 | vlv_program_watermarks(dev_priv); | |
2125 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2126 | } | |
2127 | ||
2128 | static void vlv_optimize_watermarks(struct intel_atomic_state *state, | |
2129 | struct intel_crtc_state *crtc_state) | |
2130 | { | |
2131 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
2132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2133 | ||
2134 | if (!crtc_state->wm.need_postvbl_update) | |
2135 | return; | |
2136 | ||
2137 | mutex_lock(&dev_priv->wm.wm_mutex); | |
2138 | intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
ff32c54e VS |
2139 | vlv_program_watermarks(dev_priv); |
2140 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2141 | } | |
2142 | ||
432081bc | 2143 | static void i965_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 2144 | { |
ffc7a76b | 2145 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 2146 | struct intel_crtc *crtc; |
b445e3b0 ED |
2147 | int srwm = 1; |
2148 | int cursor_sr = 16; | |
9858425c | 2149 | bool cxsr_enabled; |
b445e3b0 ED |
2150 | |
2151 | /* Calc sr entries for one plane configs */ | |
ffc7a76b | 2152 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
2153 | if (crtc) { |
2154 | /* self-refresh has much higher latency */ | |
2155 | static const int sr_latency_ns = 12000; | |
efc2611e VS |
2156 | const struct drm_display_mode *adjusted_mode = |
2157 | &crtc->config->base.adjusted_mode; | |
2158 | const struct drm_framebuffer *fb = | |
2159 | crtc->base.primary->state->fb; | |
241bfc38 | 2160 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 2161 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e | 2162 | int hdisplay = crtc->config->pipe_src_w; |
353c8598 | 2163 | int cpp = fb->format->cpp[0]; |
b445e3b0 ED |
2164 | int entries; |
2165 | ||
baf69ca8 VS |
2166 | entries = intel_wm_method2(clock, htotal, |
2167 | hdisplay, cpp, sr_latency_ns / 100); | |
b445e3b0 ED |
2168 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
2169 | srwm = I965_FIFO_SIZE - entries; | |
2170 | if (srwm < 0) | |
2171 | srwm = 1; | |
2172 | srwm &= 0x1ff; | |
2173 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
2174 | entries, srwm); | |
2175 | ||
baf69ca8 VS |
2176 | entries = intel_wm_method2(clock, htotal, |
2177 | crtc->base.cursor->state->crtc_w, 4, | |
2178 | sr_latency_ns / 100); | |
b445e3b0 | 2179 | entries = DIV_ROUND_UP(entries, |
baf69ca8 VS |
2180 | i965_cursor_wm_info.cacheline_size) + |
2181 | i965_cursor_wm_info.guard_size; | |
b445e3b0 | 2182 | |
baf69ca8 | 2183 | cursor_sr = i965_cursor_wm_info.fifo_size - entries; |
b445e3b0 ED |
2184 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
2185 | cursor_sr = i965_cursor_wm_info.max_wm; | |
2186 | ||
2187 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
2188 | "cursor %d\n", srwm, cursor_sr); | |
2189 | ||
9858425c | 2190 | cxsr_enabled = true; |
b445e3b0 | 2191 | } else { |
9858425c | 2192 | cxsr_enabled = false; |
b445e3b0 | 2193 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 2194 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
2195 | } |
2196 | ||
2197 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
2198 | srwm); | |
2199 | ||
2200 | /* 965 has limitations... */ | |
f4998963 VS |
2201 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
2202 | FW_WM(8, CURSORB) | | |
2203 | FW_WM(8, PLANEB) | | |
2204 | FW_WM(8, PLANEA)); | |
2205 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | | |
2206 | FW_WM(8, PLANEC_OLD)); | |
b445e3b0 | 2207 | /* update cursor SR watermark */ |
f4998963 | 2208 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
2209 | |
2210 | if (cxsr_enabled) | |
2211 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
2212 | } |
2213 | ||
f4998963 VS |
2214 | #undef FW_WM |
2215 | ||
432081bc | 2216 | static void i9xx_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 2217 | { |
ffc7a76b | 2218 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
b445e3b0 ED |
2219 | const struct intel_watermark_params *wm_info; |
2220 | uint32_t fwater_lo; | |
2221 | uint32_t fwater_hi; | |
2222 | int cwm, srwm = 1; | |
2223 | int fifo_size; | |
2224 | int planea_wm, planeb_wm; | |
efc2611e | 2225 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 2226 | |
a9097be4 | 2227 | if (IS_I945GM(dev_priv)) |
b445e3b0 | 2228 | wm_info = &i945_wm_info; |
5db94019 | 2229 | else if (!IS_GEN2(dev_priv)) |
b445e3b0 ED |
2230 | wm_info = &i915_wm_info; |
2231 | else | |
9d539105 | 2232 | wm_info = &i830_a_wm_info; |
b445e3b0 | 2233 | |
ef0f5e93 | 2234 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0); |
b91eb5cc | 2235 | crtc = intel_get_crtc_for_plane(dev_priv, 0); |
efc2611e VS |
2236 | if (intel_crtc_active(crtc)) { |
2237 | const struct drm_display_mode *adjusted_mode = | |
2238 | &crtc->config->base.adjusted_mode; | |
2239 | const struct drm_framebuffer *fb = | |
2240 | crtc->base.primary->state->fb; | |
2241 | int cpp; | |
2242 | ||
5db94019 | 2243 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 2244 | cpp = 4; |
efc2611e | 2245 | else |
353c8598 | 2246 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 2247 | |
241bfc38 | 2248 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 2249 | wm_info, fifo_size, cpp, |
5aef6003 | 2250 | pessimal_latency_ns); |
b445e3b0 | 2251 | enabled = crtc; |
9d539105 | 2252 | } else { |
b445e3b0 | 2253 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
2254 | if (planea_wm > (long)wm_info->max_wm) |
2255 | planea_wm = wm_info->max_wm; | |
2256 | } | |
2257 | ||
5db94019 | 2258 | if (IS_GEN2(dev_priv)) |
9d539105 | 2259 | wm_info = &i830_bc_wm_info; |
b445e3b0 | 2260 | |
ef0f5e93 | 2261 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1); |
b91eb5cc | 2262 | crtc = intel_get_crtc_for_plane(dev_priv, 1); |
efc2611e VS |
2263 | if (intel_crtc_active(crtc)) { |
2264 | const struct drm_display_mode *adjusted_mode = | |
2265 | &crtc->config->base.adjusted_mode; | |
2266 | const struct drm_framebuffer *fb = | |
2267 | crtc->base.primary->state->fb; | |
2268 | int cpp; | |
2269 | ||
5db94019 | 2270 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 2271 | cpp = 4; |
efc2611e | 2272 | else |
353c8598 | 2273 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 2274 | |
241bfc38 | 2275 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 2276 | wm_info, fifo_size, cpp, |
5aef6003 | 2277 | pessimal_latency_ns); |
b445e3b0 ED |
2278 | if (enabled == NULL) |
2279 | enabled = crtc; | |
2280 | else | |
2281 | enabled = NULL; | |
9d539105 | 2282 | } else { |
b445e3b0 | 2283 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
2284 | if (planeb_wm > (long)wm_info->max_wm) |
2285 | planeb_wm = wm_info->max_wm; | |
2286 | } | |
b445e3b0 ED |
2287 | |
2288 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
2289 | ||
50a0bc90 | 2290 | if (IS_I915GM(dev_priv) && enabled) { |
2ff8fde1 | 2291 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 2292 | |
efc2611e | 2293 | obj = intel_fb_obj(enabled->base.primary->state->fb); |
2ab1bc9d DV |
2294 | |
2295 | /* self-refresh seems busted with untiled */ | |
3e510a8e | 2296 | if (!i915_gem_object_is_tiled(obj)) |
2ab1bc9d DV |
2297 | enabled = NULL; |
2298 | } | |
2299 | ||
b445e3b0 ED |
2300 | /* |
2301 | * Overlay gets an aggressive default since video jitter is bad. | |
2302 | */ | |
2303 | cwm = 2; | |
2304 | ||
2305 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 2306 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
2307 | |
2308 | /* Calc sr entries for one plane configs */ | |
03427fcb | 2309 | if (HAS_FW_BLC(dev_priv) && enabled) { |
b445e3b0 ED |
2310 | /* self-refresh has much higher latency */ |
2311 | static const int sr_latency_ns = 6000; | |
efc2611e VS |
2312 | const struct drm_display_mode *adjusted_mode = |
2313 | &enabled->config->base.adjusted_mode; | |
2314 | const struct drm_framebuffer *fb = | |
2315 | enabled->base.primary->state->fb; | |
241bfc38 | 2316 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 2317 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e VS |
2318 | int hdisplay = enabled->config->pipe_src_w; |
2319 | int cpp; | |
b445e3b0 ED |
2320 | int entries; |
2321 | ||
50a0bc90 | 2322 | if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) |
2d1b5056 | 2323 | cpp = 4; |
efc2611e | 2324 | else |
353c8598 | 2325 | cpp = fb->format->cpp[0]; |
2d1b5056 | 2326 | |
baf69ca8 VS |
2327 | entries = intel_wm_method2(clock, htotal, hdisplay, cpp, |
2328 | sr_latency_ns / 100); | |
b445e3b0 ED |
2329 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
2330 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
2331 | srwm = wm_info->fifo_size - entries; | |
2332 | if (srwm < 0) | |
2333 | srwm = 1; | |
2334 | ||
50a0bc90 | 2335 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
b445e3b0 ED |
2336 | I915_WRITE(FW_BLC_SELF, |
2337 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
acb91359 | 2338 | else |
b445e3b0 ED |
2339 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
2340 | } | |
2341 | ||
2342 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
2343 | planea_wm, planeb_wm, cwm, srwm); | |
2344 | ||
2345 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
2346 | fwater_hi = (cwm & 0x1f); | |
2347 | ||
2348 | /* Set request length to 8 cachelines per fetch */ | |
2349 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
2350 | fwater_hi = fwater_hi | (1 << 8); | |
2351 | ||
2352 | I915_WRITE(FW_BLC, fwater_lo); | |
2353 | I915_WRITE(FW_BLC2, fwater_hi); | |
2354 | ||
5209b1f4 ID |
2355 | if (enabled) |
2356 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
2357 | } |
2358 | ||
432081bc | 2359 | static void i845_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 2360 | { |
ffc7a76b | 2361 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 2362 | struct intel_crtc *crtc; |
241bfc38 | 2363 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
2364 | uint32_t fwater_lo; |
2365 | int planea_wm; | |
2366 | ||
ffc7a76b | 2367 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
2368 | if (crtc == NULL) |
2369 | return; | |
2370 | ||
efc2611e | 2371 | adjusted_mode = &crtc->config->base.adjusted_mode; |
241bfc38 | 2372 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 2373 | &i845_wm_info, |
ef0f5e93 | 2374 | dev_priv->display.get_fifo_size(dev_priv, 0), |
5aef6003 | 2375 | 4, pessimal_latency_ns); |
b445e3b0 ED |
2376 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
2377 | fwater_lo |= (3<<8) | planea_wm; | |
2378 | ||
2379 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
2380 | ||
2381 | I915_WRITE(FW_BLC, fwater_lo); | |
2382 | } | |
2383 | ||
37126462 | 2384 | /* latency must be in 0.1us units. */ |
baf69ca8 VS |
2385 | static unsigned int ilk_wm_method1(unsigned int pixel_rate, |
2386 | unsigned int cpp, | |
2387 | unsigned int latency) | |
801bcfff | 2388 | { |
baf69ca8 | 2389 | unsigned int ret; |
3312ba65 | 2390 | |
baf69ca8 VS |
2391 | ret = intel_wm_method1(pixel_rate, cpp, latency); |
2392 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
801bcfff PZ |
2393 | |
2394 | return ret; | |
2395 | } | |
2396 | ||
37126462 | 2397 | /* latency must be in 0.1us units. */ |
baf69ca8 VS |
2398 | static unsigned int ilk_wm_method2(unsigned int pixel_rate, |
2399 | unsigned int htotal, | |
2400 | unsigned int width, | |
2401 | unsigned int cpp, | |
2402 | unsigned int latency) | |
801bcfff | 2403 | { |
baf69ca8 | 2404 | unsigned int ret; |
3312ba65 | 2405 | |
baf69ca8 VS |
2406 | ret = intel_wm_method2(pixel_rate, htotal, |
2407 | width, cpp, latency); | |
801bcfff | 2408 | ret = DIV_ROUND_UP(ret, 64) + 2; |
baf69ca8 | 2409 | |
801bcfff PZ |
2410 | return ret; |
2411 | } | |
2412 | ||
23297044 | 2413 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
ac484963 | 2414 | uint8_t cpp) |
cca32e9a | 2415 | { |
15126882 MR |
2416 | /* |
2417 | * Neither of these should be possible since this function shouldn't be | |
2418 | * called if the CRTC is off or the plane is invisible. But let's be | |
2419 | * extra paranoid to avoid a potential divide-by-zero if we screw up | |
2420 | * elsewhere in the driver. | |
2421 | */ | |
ac484963 | 2422 | if (WARN_ON(!cpp)) |
15126882 MR |
2423 | return 0; |
2424 | if (WARN_ON(!horiz_pixels)) | |
2425 | return 0; | |
2426 | ||
ac484963 | 2427 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2; |
cca32e9a PZ |
2428 | } |
2429 | ||
820c1980 | 2430 | struct ilk_wm_maximums { |
cca32e9a PZ |
2431 | uint16_t pri; |
2432 | uint16_t spr; | |
2433 | uint16_t cur; | |
2434 | uint16_t fbc; | |
2435 | }; | |
2436 | ||
37126462 VS |
2437 | /* |
2438 | * For both WM_PIPE and WM_LP. | |
2439 | * mem_value must be in 0.1us units. | |
2440 | */ | |
7221fc33 | 2441 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2442 | const struct intel_plane_state *pstate, |
cca32e9a PZ |
2443 | uint32_t mem_value, |
2444 | bool is_lp) | |
801bcfff | 2445 | { |
cca32e9a | 2446 | uint32_t method1, method2; |
8305494e | 2447 | int cpp; |
cca32e9a | 2448 | |
24304d81 | 2449 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2450 | return 0; |
2451 | ||
353c8598 | 2452 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2453 | |
a7d1b3f4 | 2454 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
cca32e9a PZ |
2455 | |
2456 | if (!is_lp) | |
2457 | return method1; | |
2458 | ||
a7d1b3f4 | 2459 | method2 = ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 2460 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 2461 | drm_rect_width(&pstate->base.dst), |
ac484963 | 2462 | cpp, mem_value); |
cca32e9a PZ |
2463 | |
2464 | return min(method1, method2); | |
801bcfff PZ |
2465 | } |
2466 | ||
37126462 VS |
2467 | /* |
2468 | * For both WM_PIPE and WM_LP. | |
2469 | * mem_value must be in 0.1us units. | |
2470 | */ | |
7221fc33 | 2471 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2472 | const struct intel_plane_state *pstate, |
801bcfff PZ |
2473 | uint32_t mem_value) |
2474 | { | |
2475 | uint32_t method1, method2; | |
8305494e | 2476 | int cpp; |
801bcfff | 2477 | |
24304d81 | 2478 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2479 | return 0; |
2480 | ||
353c8598 | 2481 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2482 | |
a7d1b3f4 VS |
2483 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
2484 | method2 = ilk_wm_method2(cstate->pixel_rate, | |
7221fc33 | 2485 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 2486 | drm_rect_width(&pstate->base.dst), |
ac484963 | 2487 | cpp, mem_value); |
801bcfff PZ |
2488 | return min(method1, method2); |
2489 | } | |
2490 | ||
37126462 VS |
2491 | /* |
2492 | * For both WM_PIPE and WM_LP. | |
2493 | * mem_value must be in 0.1us units. | |
2494 | */ | |
7221fc33 | 2495 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2496 | const struct intel_plane_state *pstate, |
801bcfff PZ |
2497 | uint32_t mem_value) |
2498 | { | |
a5509abd VS |
2499 | int cpp; |
2500 | ||
24304d81 | 2501 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2502 | return 0; |
2503 | ||
a5509abd VS |
2504 | cpp = pstate->base.fb->format->cpp[0]; |
2505 | ||
a7d1b3f4 | 2506 | return ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 2507 | cstate->base.adjusted_mode.crtc_htotal, |
a5509abd | 2508 | pstate->base.crtc_w, cpp, mem_value); |
801bcfff PZ |
2509 | } |
2510 | ||
cca32e9a | 2511 | /* Only for WM_LP. */ |
7221fc33 | 2512 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2513 | const struct intel_plane_state *pstate, |
1fda9882 | 2514 | uint32_t pri_val) |
cca32e9a | 2515 | { |
8305494e | 2516 | int cpp; |
43d59eda | 2517 | |
24304d81 | 2518 | if (!intel_wm_plane_visible(cstate, pstate)) |
cca32e9a PZ |
2519 | return 0; |
2520 | ||
353c8598 | 2521 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2522 | |
936e71e3 | 2523 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp); |
cca32e9a PZ |
2524 | } |
2525 | ||
175fded1 TU |
2526 | static unsigned int |
2527 | ilk_display_fifo_size(const struct drm_i915_private *dev_priv) | |
158ae64f | 2528 | { |
175fded1 | 2529 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 | 2530 | return 3072; |
175fded1 | 2531 | else if (INTEL_GEN(dev_priv) >= 7) |
158ae64f VS |
2532 | return 768; |
2533 | else | |
2534 | return 512; | |
2535 | } | |
2536 | ||
175fded1 TU |
2537 | static unsigned int |
2538 | ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, | |
2539 | int level, bool is_sprite) | |
4e975081 | 2540 | { |
175fded1 | 2541 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2542 | /* BDW primary/sprite plane watermarks */ |
2543 | return level == 0 ? 255 : 2047; | |
175fded1 | 2544 | else if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2545 | /* IVB/HSW primary/sprite plane watermarks */ |
2546 | return level == 0 ? 127 : 1023; | |
2547 | else if (!is_sprite) | |
2548 | /* ILK/SNB primary plane watermarks */ | |
2549 | return level == 0 ? 127 : 511; | |
2550 | else | |
2551 | /* ILK/SNB sprite plane watermarks */ | |
2552 | return level == 0 ? 63 : 255; | |
2553 | } | |
2554 | ||
175fded1 TU |
2555 | static unsigned int |
2556 | ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) | |
4e975081 | 2557 | { |
175fded1 | 2558 | if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2559 | return level == 0 ? 63 : 255; |
2560 | else | |
2561 | return level == 0 ? 31 : 63; | |
2562 | } | |
2563 | ||
175fded1 | 2564 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) |
4e975081 | 2565 | { |
175fded1 | 2566 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2567 | return 31; |
2568 | else | |
2569 | return 15; | |
2570 | } | |
2571 | ||
158ae64f VS |
2572 | /* Calculate the maximum primary/sprite plane watermark */ |
2573 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
2574 | int level, | |
240264f4 | 2575 | const struct intel_wm_config *config, |
158ae64f VS |
2576 | enum intel_ddb_partitioning ddb_partitioning, |
2577 | bool is_sprite) | |
2578 | { | |
175fded1 TU |
2579 | struct drm_i915_private *dev_priv = to_i915(dev); |
2580 | unsigned int fifo_size = ilk_display_fifo_size(dev_priv); | |
158ae64f VS |
2581 | |
2582 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 2583 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
2584 | return 0; |
2585 | ||
2586 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 2587 | if (level == 0 || config->num_pipes_active > 1) { |
175fded1 | 2588 | fifo_size /= INTEL_INFO(dev_priv)->num_pipes; |
158ae64f VS |
2589 | |
2590 | /* | |
2591 | * For some reason the non self refresh | |
2592 | * FIFO size is only half of the self | |
2593 | * refresh FIFO size on ILK/SNB. | |
2594 | */ | |
175fded1 | 2595 | if (INTEL_GEN(dev_priv) <= 6) |
158ae64f VS |
2596 | fifo_size /= 2; |
2597 | } | |
2598 | ||
240264f4 | 2599 | if (config->sprites_enabled) { |
158ae64f VS |
2600 | /* level 0 is always calculated with 1:1 split */ |
2601 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
2602 | if (is_sprite) | |
2603 | fifo_size *= 5; | |
2604 | fifo_size /= 6; | |
2605 | } else { | |
2606 | fifo_size /= 2; | |
2607 | } | |
2608 | } | |
2609 | ||
2610 | /* clamp to max that the registers can hold */ | |
175fded1 | 2611 | return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); |
158ae64f VS |
2612 | } |
2613 | ||
2614 | /* Calculate the maximum cursor plane watermark */ | |
2615 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
2616 | int level, |
2617 | const struct intel_wm_config *config) | |
158ae64f VS |
2618 | { |
2619 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 2620 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
2621 | return 64; |
2622 | ||
2623 | /* otherwise just report max that registers can hold */ | |
175fded1 | 2624 | return ilk_cursor_wm_reg_max(to_i915(dev), level); |
158ae64f VS |
2625 | } |
2626 | ||
d34ff9c6 | 2627 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
2628 | int level, |
2629 | const struct intel_wm_config *config, | |
2630 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 2631 | struct ilk_wm_maximums *max) |
158ae64f | 2632 | { |
240264f4 VS |
2633 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
2634 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
2635 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
175fded1 | 2636 | max->fbc = ilk_fbc_wm_reg_max(to_i915(dev)); |
158ae64f VS |
2637 | } |
2638 | ||
175fded1 | 2639 | static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, |
a3cb4048 VS |
2640 | int level, |
2641 | struct ilk_wm_maximums *max) | |
2642 | { | |
175fded1 TU |
2643 | max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); |
2644 | max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); | |
2645 | max->cur = ilk_cursor_wm_reg_max(dev_priv, level); | |
2646 | max->fbc = ilk_fbc_wm_reg_max(dev_priv); | |
a3cb4048 VS |
2647 | } |
2648 | ||
d9395655 | 2649 | static bool ilk_validate_wm_level(int level, |
820c1980 | 2650 | const struct ilk_wm_maximums *max, |
d9395655 | 2651 | struct intel_wm_level *result) |
a9786a11 VS |
2652 | { |
2653 | bool ret; | |
2654 | ||
2655 | /* already determined to be invalid? */ | |
2656 | if (!result->enable) | |
2657 | return false; | |
2658 | ||
2659 | result->enable = result->pri_val <= max->pri && | |
2660 | result->spr_val <= max->spr && | |
2661 | result->cur_val <= max->cur; | |
2662 | ||
2663 | ret = result->enable; | |
2664 | ||
2665 | /* | |
2666 | * HACK until we can pre-compute everything, | |
2667 | * and thus fail gracefully if LP0 watermarks | |
2668 | * are exceeded... | |
2669 | */ | |
2670 | if (level == 0 && !result->enable) { | |
2671 | if (result->pri_val > max->pri) | |
2672 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
2673 | level, result->pri_val, max->pri); | |
2674 | if (result->spr_val > max->spr) | |
2675 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
2676 | level, result->spr_val, max->spr); | |
2677 | if (result->cur_val > max->cur) | |
2678 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
2679 | level, result->cur_val, max->cur); | |
2680 | ||
2681 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
2682 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
2683 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
2684 | result->enable = true; | |
2685 | } | |
2686 | ||
a9786a11 VS |
2687 | return ret; |
2688 | } | |
2689 | ||
d34ff9c6 | 2690 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
43d59eda | 2691 | const struct intel_crtc *intel_crtc, |
6f5ddd17 | 2692 | int level, |
7221fc33 | 2693 | struct intel_crtc_state *cstate, |
86c8bbbe MR |
2694 | struct intel_plane_state *pristate, |
2695 | struct intel_plane_state *sprstate, | |
2696 | struct intel_plane_state *curstate, | |
1fd527cc | 2697 | struct intel_wm_level *result) |
6f5ddd17 VS |
2698 | { |
2699 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
2700 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
2701 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
2702 | ||
2703 | /* WM1+ latency values stored in 0.5us units */ | |
2704 | if (level > 0) { | |
2705 | pri_latency *= 5; | |
2706 | spr_latency *= 5; | |
2707 | cur_latency *= 5; | |
2708 | } | |
2709 | ||
e3bddded ML |
2710 | if (pristate) { |
2711 | result->pri_val = ilk_compute_pri_wm(cstate, pristate, | |
2712 | pri_latency, level); | |
2713 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); | |
2714 | } | |
2715 | ||
2716 | if (sprstate) | |
2717 | result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency); | |
2718 | ||
2719 | if (curstate) | |
2720 | result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency); | |
2721 | ||
6f5ddd17 VS |
2722 | result->enable = true; |
2723 | } | |
2724 | ||
801bcfff | 2725 | static uint32_t |
532f7a7f | 2726 | hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) |
1f8eeabf | 2727 | { |
532f7a7f VS |
2728 | const struct intel_atomic_state *intel_state = |
2729 | to_intel_atomic_state(cstate->base.state); | |
ee91a159 MR |
2730 | const struct drm_display_mode *adjusted_mode = |
2731 | &cstate->base.adjusted_mode; | |
85a02deb | 2732 | u32 linetime, ips_linetime; |
1f8eeabf | 2733 | |
ee91a159 MR |
2734 | if (!cstate->base.active) |
2735 | return 0; | |
2736 | if (WARN_ON(adjusted_mode->crtc_clock == 0)) | |
2737 | return 0; | |
bb0f4aab | 2738 | if (WARN_ON(intel_state->cdclk.logical.cdclk == 0)) |
801bcfff | 2739 | return 0; |
1011d8c4 | 2740 | |
1f8eeabf ED |
2741 | /* The WM are computed with base on how long it takes to fill a single |
2742 | * row at the given clock rate, multiplied by 8. | |
2743 | * */ | |
124abe07 VS |
2744 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2745 | adjusted_mode->crtc_clock); | |
2746 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, | |
bb0f4aab | 2747 | intel_state->cdclk.logical.cdclk); |
1f8eeabf | 2748 | |
801bcfff PZ |
2749 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2750 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2751 | } |
2752 | ||
bb726519 VS |
2753 | static void intel_read_wm_latency(struct drm_i915_private *dev_priv, |
2754 | uint16_t wm[8]) | |
12b134df | 2755 | { |
5db94019 | 2756 | if (IS_GEN9(dev_priv)) { |
2af30a5c | 2757 | uint32_t val; |
4f947386 | 2758 | int ret, i; |
5db94019 | 2759 | int level, max_level = ilk_wm_max_level(dev_priv); |
2af30a5c PB |
2760 | |
2761 | /* read the first set of memory latencies[0:3] */ | |
2762 | val = 0; /* data0 to be programmed to 0 for first set */ | |
2763 | mutex_lock(&dev_priv->rps.hw_lock); | |
2764 | ret = sandybridge_pcode_read(dev_priv, | |
2765 | GEN9_PCODE_READ_MEM_LATENCY, | |
2766 | &val); | |
2767 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2768 | ||
2769 | if (ret) { | |
2770 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2771 | return; | |
2772 | } | |
2773 | ||
2774 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2775 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2776 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2777 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2778 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2779 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2780 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2781 | ||
2782 | /* read the second set of memory latencies[4:7] */ | |
2783 | val = 1; /* data0 to be programmed to 1 for second set */ | |
2784 | mutex_lock(&dev_priv->rps.hw_lock); | |
2785 | ret = sandybridge_pcode_read(dev_priv, | |
2786 | GEN9_PCODE_READ_MEM_LATENCY, | |
2787 | &val); | |
2788 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2789 | if (ret) { | |
2790 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2791 | return; | |
2792 | } | |
2793 | ||
2794 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2795 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2796 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2797 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2798 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2799 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2800 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2801 | ||
0727e40a PZ |
2802 | /* |
2803 | * If a level n (n > 1) has a 0us latency, all levels m (m >= n) | |
2804 | * need to be disabled. We make sure to sanitize the values out | |
2805 | * of the punit to satisfy this requirement. | |
2806 | */ | |
2807 | for (level = 1; level <= max_level; level++) { | |
2808 | if (wm[level] == 0) { | |
2809 | for (i = level + 1; i <= max_level; i++) | |
2810 | wm[i] = 0; | |
2811 | break; | |
2812 | } | |
2813 | } | |
2814 | ||
367294be | 2815 | /* |
9fb5026f | 2816 | * WaWmMemoryReadLatency:skl,glk |
6f97235b | 2817 | * |
367294be | 2818 | * punit doesn't take into account the read latency so we need |
0727e40a PZ |
2819 | * to add 2us to the various latency levels we retrieve from the |
2820 | * punit when level 0 response data us 0us. | |
367294be | 2821 | */ |
0727e40a PZ |
2822 | if (wm[0] == 0) { |
2823 | wm[0] += 2; | |
2824 | for (level = 1; level <= max_level; level++) { | |
2825 | if (wm[level] == 0) | |
2826 | break; | |
367294be | 2827 | wm[level] += 2; |
4f947386 | 2828 | } |
0727e40a PZ |
2829 | } |
2830 | ||
8652744b | 2831 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
12b134df VS |
2832 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2833 | ||
2834 | wm[0] = (sskpd >> 56) & 0xFF; | |
2835 | if (wm[0] == 0) | |
2836 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2837 | wm[1] = (sskpd >> 4) & 0xFF; |
2838 | wm[2] = (sskpd >> 12) & 0xFF; | |
2839 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2840 | wm[4] = (sskpd >> 32) & 0x1FF; | |
bb726519 | 2841 | } else if (INTEL_GEN(dev_priv) >= 6) { |
63cf9a13 VS |
2842 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
2843 | ||
2844 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2845 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2846 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2847 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
bb726519 | 2848 | } else if (INTEL_GEN(dev_priv) >= 5) { |
3a88d0ac VS |
2849 | uint32_t mltr = I915_READ(MLTR_ILK); |
2850 | ||
2851 | /* ILK primary LP0 latency is 700 ns */ | |
2852 | wm[0] = 7; | |
2853 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2854 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2855 | } |
2856 | } | |
2857 | ||
5db94019 TU |
2858 | static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, |
2859 | uint16_t wm[5]) | |
53615a5e VS |
2860 | { |
2861 | /* ILK sprite LP0 latency is 1300 ns */ | |
5db94019 | 2862 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2863 | wm[0] = 13; |
2864 | } | |
2865 | ||
fd6b8f43 TU |
2866 | static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, |
2867 | uint16_t wm[5]) | |
53615a5e VS |
2868 | { |
2869 | /* ILK cursor LP0 latency is 1300 ns */ | |
fd6b8f43 | 2870 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2871 | wm[0] = 13; |
2872 | ||
2873 | /* WaDoubleCursorLP3Latency:ivb */ | |
fd6b8f43 | 2874 | if (IS_IVYBRIDGE(dev_priv)) |
53615a5e VS |
2875 | wm[3] *= 2; |
2876 | } | |
2877 | ||
5db94019 | 2878 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv) |
26ec971e | 2879 | { |
26ec971e | 2880 | /* how many WM levels are we expecting */ |
8652744b | 2881 | if (INTEL_GEN(dev_priv) >= 9) |
2af30a5c | 2882 | return 7; |
8652744b | 2883 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ad0d6dc4 | 2884 | return 4; |
8652744b | 2885 | else if (INTEL_GEN(dev_priv) >= 6) |
ad0d6dc4 | 2886 | return 3; |
26ec971e | 2887 | else |
ad0d6dc4 VS |
2888 | return 2; |
2889 | } | |
7526ed79 | 2890 | |
5db94019 | 2891 | static void intel_print_wm_latency(struct drm_i915_private *dev_priv, |
ad0d6dc4 | 2892 | const char *name, |
2af30a5c | 2893 | const uint16_t wm[8]) |
ad0d6dc4 | 2894 | { |
5db94019 | 2895 | int level, max_level = ilk_wm_max_level(dev_priv); |
26ec971e VS |
2896 | |
2897 | for (level = 0; level <= max_level; level++) { | |
2898 | unsigned int latency = wm[level]; | |
2899 | ||
2900 | if (latency == 0) { | |
2901 | DRM_ERROR("%s WM%d latency not provided\n", | |
2902 | name, level); | |
2903 | continue; | |
2904 | } | |
2905 | ||
2af30a5c PB |
2906 | /* |
2907 | * - latencies are in us on gen9. | |
2908 | * - before then, WM1+ latency values are in 0.5us units | |
2909 | */ | |
5db94019 | 2910 | if (IS_GEN9(dev_priv)) |
2af30a5c PB |
2911 | latency *= 10; |
2912 | else if (level > 0) | |
26ec971e VS |
2913 | latency *= 5; |
2914 | ||
2915 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2916 | name, level, wm[level], | |
2917 | latency / 10, latency % 10); | |
2918 | } | |
2919 | } | |
2920 | ||
e95a2f75 VS |
2921 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2922 | uint16_t wm[5], uint16_t min) | |
2923 | { | |
5db94019 | 2924 | int level, max_level = ilk_wm_max_level(dev_priv); |
e95a2f75 VS |
2925 | |
2926 | if (wm[0] >= min) | |
2927 | return false; | |
2928 | ||
2929 | wm[0] = max(wm[0], min); | |
2930 | for (level = 1; level <= max_level; level++) | |
2931 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2932 | ||
2933 | return true; | |
2934 | } | |
2935 | ||
bb726519 | 2936 | static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) |
e95a2f75 | 2937 | { |
e95a2f75 VS |
2938 | bool changed; |
2939 | ||
2940 | /* | |
2941 | * The BIOS provided WM memory latency values are often | |
2942 | * inadequate for high resolution displays. Adjust them. | |
2943 | */ | |
2944 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2945 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2946 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2947 | ||
2948 | if (!changed) | |
2949 | return; | |
2950 | ||
2951 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
5db94019 TU |
2952 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2953 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2954 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2955 | } |
2956 | ||
bb726519 | 2957 | static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) |
53615a5e | 2958 | { |
bb726519 | 2959 | intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); |
53615a5e VS |
2960 | |
2961 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2962 | sizeof(dev_priv->wm.pri_latency)); | |
2963 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2964 | sizeof(dev_priv->wm.pri_latency)); | |
2965 | ||
5db94019 | 2966 | intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); |
fd6b8f43 | 2967 | intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); |
26ec971e | 2968 | |
5db94019 TU |
2969 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2970 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2971 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 | 2972 | |
5db94019 | 2973 | if (IS_GEN6(dev_priv)) |
bb726519 | 2974 | snb_wm_latency_quirk(dev_priv); |
53615a5e VS |
2975 | } |
2976 | ||
bb726519 | 2977 | static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) |
2af30a5c | 2978 | { |
bb726519 | 2979 | intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); |
5db94019 | 2980 | intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); |
2af30a5c PB |
2981 | } |
2982 | ||
ed4a6a7c MR |
2983 | static bool ilk_validate_pipe_wm(struct drm_device *dev, |
2984 | struct intel_pipe_wm *pipe_wm) | |
2985 | { | |
2986 | /* LP0 watermark maximums depend on this pipe alone */ | |
2987 | const struct intel_wm_config config = { | |
2988 | .num_pipes_active = 1, | |
2989 | .sprites_enabled = pipe_wm->sprites_enabled, | |
2990 | .sprites_scaled = pipe_wm->sprites_scaled, | |
2991 | }; | |
2992 | struct ilk_wm_maximums max; | |
2993 | ||
2994 | /* LP0 watermarks always use 1/2 DDB partitioning */ | |
2995 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2996 | ||
2997 | /* At least LP0 must be valid */ | |
2998 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { | |
2999 | DRM_DEBUG_KMS("LP0 watermark invalid\n"); | |
3000 | return false; | |
3001 | } | |
3002 | ||
3003 | return true; | |
3004 | } | |
3005 | ||
0b2ae6d7 | 3006 | /* Compute new watermarks for the pipe */ |
e3bddded | 3007 | static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) |
0b2ae6d7 | 3008 | { |
e3bddded ML |
3009 | struct drm_atomic_state *state = cstate->base.state; |
3010 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
86c8bbbe | 3011 | struct intel_pipe_wm *pipe_wm; |
e3bddded | 3012 | struct drm_device *dev = state->dev; |
fac5e23e | 3013 | const struct drm_i915_private *dev_priv = to_i915(dev); |
43d59eda | 3014 | struct intel_plane *intel_plane; |
86c8bbbe | 3015 | struct intel_plane_state *pristate = NULL; |
43d59eda | 3016 | struct intel_plane_state *sprstate = NULL; |
86c8bbbe | 3017 | struct intel_plane_state *curstate = NULL; |
5db94019 | 3018 | int level, max_level = ilk_wm_max_level(dev_priv), usable_level; |
820c1980 | 3019 | struct ilk_wm_maximums max; |
0b2ae6d7 | 3020 | |
e8f1f02e | 3021 | pipe_wm = &cstate->wm.ilk.optimal; |
86c8bbbe | 3022 | |
43d59eda | 3023 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
e3bddded ML |
3024 | struct intel_plane_state *ps; |
3025 | ||
3026 | ps = intel_atomic_get_existing_plane_state(state, | |
3027 | intel_plane); | |
3028 | if (!ps) | |
3029 | continue; | |
86c8bbbe MR |
3030 | |
3031 | if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
e3bddded | 3032 | pristate = ps; |
86c8bbbe | 3033 | else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) |
e3bddded | 3034 | sprstate = ps; |
86c8bbbe | 3035 | else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) |
e3bddded | 3036 | curstate = ps; |
43d59eda MR |
3037 | } |
3038 | ||
ed4a6a7c | 3039 | pipe_wm->pipe_enabled = cstate->base.active; |
e3bddded | 3040 | if (sprstate) { |
936e71e3 VS |
3041 | pipe_wm->sprites_enabled = sprstate->base.visible; |
3042 | pipe_wm->sprites_scaled = sprstate->base.visible && | |
3043 | (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 || | |
3044 | drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16); | |
e3bddded ML |
3045 | } |
3046 | ||
d81f04c5 ML |
3047 | usable_level = max_level; |
3048 | ||
7b39a0b7 | 3049 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
175fded1 | 3050 | if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) |
d81f04c5 | 3051 | usable_level = 1; |
7b39a0b7 VS |
3052 | |
3053 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
ed4a6a7c | 3054 | if (pipe_wm->sprites_scaled) |
d81f04c5 | 3055 | usable_level = 0; |
7b39a0b7 | 3056 | |
86c8bbbe | 3057 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
71f0a626 ML |
3058 | pristate, sprstate, curstate, &pipe_wm->raw_wm[0]); |
3059 | ||
3060 | memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); | |
3061 | pipe_wm->wm[0] = pipe_wm->raw_wm[0]; | |
0b2ae6d7 | 3062 | |
8652744b | 3063 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
532f7a7f | 3064 | pipe_wm->linetime = hsw_compute_linetime_wm(cstate); |
0b2ae6d7 | 3065 | |
ed4a6a7c | 3066 | if (!ilk_validate_pipe_wm(dev, pipe_wm)) |
1a426d61 | 3067 | return -EINVAL; |
a3cb4048 | 3068 | |
175fded1 | 3069 | ilk_compute_wm_reg_maximums(dev_priv, 1, &max); |
a3cb4048 VS |
3070 | |
3071 | for (level = 1; level <= max_level; level++) { | |
71f0a626 | 3072 | struct intel_wm_level *wm = &pipe_wm->raw_wm[level]; |
a3cb4048 | 3073 | |
86c8bbbe | 3074 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, |
d81f04c5 | 3075 | pristate, sprstate, curstate, wm); |
a3cb4048 VS |
3076 | |
3077 | /* | |
3078 | * Disable any watermark level that exceeds the | |
3079 | * register maximums since such watermarks are | |
3080 | * always invalid. | |
3081 | */ | |
71f0a626 ML |
3082 | if (level > usable_level) |
3083 | continue; | |
3084 | ||
3085 | if (ilk_validate_wm_level(level, &max, wm)) | |
3086 | pipe_wm->wm[level] = *wm; | |
3087 | else | |
d81f04c5 | 3088 | usable_level = level; |
a3cb4048 VS |
3089 | } |
3090 | ||
86c8bbbe | 3091 | return 0; |
0b2ae6d7 VS |
3092 | } |
3093 | ||
ed4a6a7c MR |
3094 | /* |
3095 | * Build a set of 'intermediate' watermark values that satisfy both the old | |
3096 | * state and the new state. These can be programmed to the hardware | |
3097 | * immediately. | |
3098 | */ | |
3099 | static int ilk_compute_intermediate_wm(struct drm_device *dev, | |
3100 | struct intel_crtc *intel_crtc, | |
3101 | struct intel_crtc_state *newstate) | |
3102 | { | |
e8f1f02e | 3103 | struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; |
ed4a6a7c | 3104 | struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk; |
5db94019 | 3105 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
ed4a6a7c MR |
3106 | |
3107 | /* | |
3108 | * Start with the final, target watermarks, then combine with the | |
3109 | * currently active watermarks to get values that are safe both before | |
3110 | * and after the vblank. | |
3111 | */ | |
e8f1f02e | 3112 | *a = newstate->wm.ilk.optimal; |
ed4a6a7c MR |
3113 | a->pipe_enabled |= b->pipe_enabled; |
3114 | a->sprites_enabled |= b->sprites_enabled; | |
3115 | a->sprites_scaled |= b->sprites_scaled; | |
3116 | ||
3117 | for (level = 0; level <= max_level; level++) { | |
3118 | struct intel_wm_level *a_wm = &a->wm[level]; | |
3119 | const struct intel_wm_level *b_wm = &b->wm[level]; | |
3120 | ||
3121 | a_wm->enable &= b_wm->enable; | |
3122 | a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val); | |
3123 | a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val); | |
3124 | a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val); | |
3125 | a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val); | |
3126 | } | |
3127 | ||
3128 | /* | |
3129 | * We need to make sure that these merged watermark values are | |
3130 | * actually a valid configuration themselves. If they're not, | |
3131 | * there's no safe way to transition from the old state to | |
3132 | * the new state, so we need to fail the atomic transaction. | |
3133 | */ | |
3134 | if (!ilk_validate_pipe_wm(dev, a)) | |
3135 | return -EINVAL; | |
3136 | ||
3137 | /* | |
3138 | * If our intermediate WM are identical to the final WM, then we can | |
3139 | * omit the post-vblank programming; only update if it's different. | |
3140 | */ | |
5eeb798b VS |
3141 | if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0) |
3142 | newstate->wm.need_postvbl_update = true; | |
ed4a6a7c MR |
3143 | |
3144 | return 0; | |
3145 | } | |
3146 | ||
0b2ae6d7 VS |
3147 | /* |
3148 | * Merge the watermarks from all active pipes for a specific level. | |
3149 | */ | |
3150 | static void ilk_merge_wm_level(struct drm_device *dev, | |
3151 | int level, | |
3152 | struct intel_wm_level *ret_wm) | |
3153 | { | |
3154 | const struct intel_crtc *intel_crtc; | |
3155 | ||
d52fea5b VS |
3156 | ret_wm->enable = true; |
3157 | ||
d3fcc808 | 3158 | for_each_intel_crtc(dev, intel_crtc) { |
ed4a6a7c | 3159 | const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; |
fe392efd VS |
3160 | const struct intel_wm_level *wm = &active->wm[level]; |
3161 | ||
3162 | if (!active->pipe_enabled) | |
3163 | continue; | |
0b2ae6d7 | 3164 | |
d52fea5b VS |
3165 | /* |
3166 | * The watermark values may have been used in the past, | |
3167 | * so we must maintain them in the registers for some | |
3168 | * time even if the level is now disabled. | |
3169 | */ | |
0b2ae6d7 | 3170 | if (!wm->enable) |
d52fea5b | 3171 | ret_wm->enable = false; |
0b2ae6d7 VS |
3172 | |
3173 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
3174 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
3175 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
3176 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
3177 | } | |
0b2ae6d7 VS |
3178 | } |
3179 | ||
3180 | /* | |
3181 | * Merge all low power watermarks for all active pipes. | |
3182 | */ | |
3183 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 3184 | const struct intel_wm_config *config, |
820c1980 | 3185 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
3186 | struct intel_pipe_wm *merged) |
3187 | { | |
fac5e23e | 3188 | struct drm_i915_private *dev_priv = to_i915(dev); |
5db94019 | 3189 | int level, max_level = ilk_wm_max_level(dev_priv); |
d52fea5b | 3190 | int last_enabled_level = max_level; |
0b2ae6d7 | 3191 | |
0ba22e26 | 3192 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
fd6b8f43 | 3193 | if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) && |
0ba22e26 | 3194 | config->num_pipes_active > 1) |
1204d5ba | 3195 | last_enabled_level = 0; |
0ba22e26 | 3196 | |
6c8b6c28 | 3197 | /* ILK: FBC WM must be disabled always */ |
175fded1 | 3198 | merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; |
0b2ae6d7 VS |
3199 | |
3200 | /* merge each WM1+ level */ | |
3201 | for (level = 1; level <= max_level; level++) { | |
3202 | struct intel_wm_level *wm = &merged->wm[level]; | |
3203 | ||
3204 | ilk_merge_wm_level(dev, level, wm); | |
3205 | ||
d52fea5b VS |
3206 | if (level > last_enabled_level) |
3207 | wm->enable = false; | |
3208 | else if (!ilk_validate_wm_level(level, max, wm)) | |
3209 | /* make sure all following levels get disabled */ | |
3210 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
3211 | |
3212 | /* | |
3213 | * The spec says it is preferred to disable | |
3214 | * FBC WMs instead of disabling a WM level. | |
3215 | */ | |
3216 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
3217 | if (wm->enable) |
3218 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
3219 | wm->fbc_val = 0; |
3220 | } | |
3221 | } | |
6c8b6c28 VS |
3222 | |
3223 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
3224 | /* | |
3225 | * FIXME this is racy. FBC might get enabled later. | |
3226 | * What we should check here is whether FBC can be | |
3227 | * enabled sometime later. | |
3228 | */ | |
5db94019 | 3229 | if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && |
0e631adc | 3230 | intel_fbc_is_active(dev_priv)) { |
6c8b6c28 VS |
3231 | for (level = 2; level <= max_level; level++) { |
3232 | struct intel_wm_level *wm = &merged->wm[level]; | |
3233 | ||
3234 | wm->enable = false; | |
3235 | } | |
3236 | } | |
0b2ae6d7 VS |
3237 | } |
3238 | ||
b380ca3c VS |
3239 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
3240 | { | |
3241 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
3242 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
3243 | } | |
3244 | ||
a68d68ee VS |
3245 | /* The value we need to program into the WM_LPx latency field */ |
3246 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
3247 | { | |
fac5e23e | 3248 | struct drm_i915_private *dev_priv = to_i915(dev); |
a68d68ee | 3249 | |
8652744b | 3250 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
a68d68ee VS |
3251 | return 2 * level; |
3252 | else | |
3253 | return dev_priv->wm.pri_latency[level]; | |
3254 | } | |
3255 | ||
820c1980 | 3256 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 3257 | const struct intel_pipe_wm *merged, |
609cedef | 3258 | enum intel_ddb_partitioning partitioning, |
820c1980 | 3259 | struct ilk_wm_values *results) |
801bcfff | 3260 | { |
175fded1 | 3261 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b2ae6d7 VS |
3262 | struct intel_crtc *intel_crtc; |
3263 | int level, wm_lp; | |
cca32e9a | 3264 | |
0362c781 | 3265 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 3266 | results->partitioning = partitioning; |
cca32e9a | 3267 | |
0b2ae6d7 | 3268 | /* LP1+ register values */ |
cca32e9a | 3269 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 3270 | const struct intel_wm_level *r; |
801bcfff | 3271 | |
b380ca3c | 3272 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 3273 | |
0362c781 | 3274 | r = &merged->wm[level]; |
cca32e9a | 3275 | |
d52fea5b VS |
3276 | /* |
3277 | * Maintain the watermark values even if the level is | |
3278 | * disabled. Doing otherwise could cause underruns. | |
3279 | */ | |
3280 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 3281 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
3282 | (r->pri_val << WM1_LP_SR_SHIFT) | |
3283 | r->cur_val; | |
3284 | ||
d52fea5b VS |
3285 | if (r->enable) |
3286 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
3287 | ||
175fded1 | 3288 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 VS |
3289 | results->wm_lp[wm_lp - 1] |= |
3290 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
3291 | else | |
3292 | results->wm_lp[wm_lp - 1] |= | |
3293 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
3294 | ||
d52fea5b VS |
3295 | /* |
3296 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
3297 | * level is disabled. Doing otherwise could cause underruns. | |
3298 | */ | |
175fded1 | 3299 | if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { |
6cef2b8a VS |
3300 | WARN_ON(wm_lp != 1); |
3301 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
3302 | } else | |
3303 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 3304 | } |
801bcfff | 3305 | |
0b2ae6d7 | 3306 | /* LP0 register values */ |
d3fcc808 | 3307 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 | 3308 | enum pipe pipe = intel_crtc->pipe; |
ed4a6a7c MR |
3309 | const struct intel_wm_level *r = |
3310 | &intel_crtc->wm.active.ilk.wm[0]; | |
0b2ae6d7 VS |
3311 | |
3312 | if (WARN_ON(!r->enable)) | |
3313 | continue; | |
3314 | ||
ed4a6a7c | 3315 | results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; |
1011d8c4 | 3316 | |
0b2ae6d7 VS |
3317 | results->wm_pipe[pipe] = |
3318 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
3319 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
3320 | r->cur_val; | |
801bcfff PZ |
3321 | } |
3322 | } | |
3323 | ||
861f3389 PZ |
3324 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
3325 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 3326 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
3327 | struct intel_pipe_wm *r1, |
3328 | struct intel_pipe_wm *r2) | |
861f3389 | 3329 | { |
5db94019 | 3330 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
198a1e9b | 3331 | int level1 = 0, level2 = 0; |
861f3389 | 3332 | |
198a1e9b VS |
3333 | for (level = 1; level <= max_level; level++) { |
3334 | if (r1->wm[level].enable) | |
3335 | level1 = level; | |
3336 | if (r2->wm[level].enable) | |
3337 | level2 = level; | |
861f3389 PZ |
3338 | } |
3339 | ||
198a1e9b VS |
3340 | if (level1 == level2) { |
3341 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
3342 | return r2; |
3343 | else | |
3344 | return r1; | |
198a1e9b | 3345 | } else if (level1 > level2) { |
861f3389 PZ |
3346 | return r1; |
3347 | } else { | |
3348 | return r2; | |
3349 | } | |
3350 | } | |
3351 | ||
49a687c4 VS |
3352 | /* dirty bits used to track which watermarks need changes */ |
3353 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
3354 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
3355 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
3356 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
3357 | #define WM_DIRTY_FBC (1 << 24) | |
3358 | #define WM_DIRTY_DDB (1 << 25) | |
3359 | ||
055e393f | 3360 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
3361 | const struct ilk_wm_values *old, |
3362 | const struct ilk_wm_values *new) | |
49a687c4 VS |
3363 | { |
3364 | unsigned int dirty = 0; | |
3365 | enum pipe pipe; | |
3366 | int wm_lp; | |
3367 | ||
055e393f | 3368 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
3369 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
3370 | dirty |= WM_DIRTY_LINETIME(pipe); | |
3371 | /* Must disable LP1+ watermarks too */ | |
3372 | dirty |= WM_DIRTY_LP_ALL; | |
3373 | } | |
3374 | ||
3375 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
3376 | dirty |= WM_DIRTY_PIPE(pipe); | |
3377 | /* Must disable LP1+ watermarks too */ | |
3378 | dirty |= WM_DIRTY_LP_ALL; | |
3379 | } | |
3380 | } | |
3381 | ||
3382 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
3383 | dirty |= WM_DIRTY_FBC; | |
3384 | /* Must disable LP1+ watermarks too */ | |
3385 | dirty |= WM_DIRTY_LP_ALL; | |
3386 | } | |
3387 | ||
3388 | if (old->partitioning != new->partitioning) { | |
3389 | dirty |= WM_DIRTY_DDB; | |
3390 | /* Must disable LP1+ watermarks too */ | |
3391 | dirty |= WM_DIRTY_LP_ALL; | |
3392 | } | |
3393 | ||
3394 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
3395 | if (dirty & WM_DIRTY_LP_ALL) | |
3396 | return dirty; | |
3397 | ||
3398 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
3399 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
3400 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
3401 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
3402 | break; | |
3403 | } | |
3404 | ||
3405 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
3406 | for (; wm_lp <= 3; wm_lp++) | |
3407 | dirty |= WM_DIRTY_LP(wm_lp); | |
3408 | ||
3409 | return dirty; | |
3410 | } | |
3411 | ||
8553c18e VS |
3412 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
3413 | unsigned int dirty) | |
801bcfff | 3414 | { |
820c1980 | 3415 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 3416 | bool changed = false; |
801bcfff | 3417 | |
facd619b VS |
3418 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
3419 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
3420 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 3421 | changed = true; |
facd619b VS |
3422 | } |
3423 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
3424 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
3425 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 3426 | changed = true; |
facd619b VS |
3427 | } |
3428 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
3429 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
3430 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 3431 | changed = true; |
facd619b | 3432 | } |
801bcfff | 3433 | |
facd619b VS |
3434 | /* |
3435 | * Don't touch WM1S_LP_EN here. | |
3436 | * Doing so could cause underruns. | |
3437 | */ | |
6cef2b8a | 3438 | |
8553c18e VS |
3439 | return changed; |
3440 | } | |
3441 | ||
3442 | /* | |
3443 | * The spec says we shouldn't write when we don't need, because every write | |
3444 | * causes WMs to be re-evaluated, expending some power. | |
3445 | */ | |
820c1980 ID |
3446 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
3447 | struct ilk_wm_values *results) | |
8553c18e | 3448 | { |
820c1980 | 3449 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
3450 | unsigned int dirty; |
3451 | uint32_t val; | |
3452 | ||
055e393f | 3453 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
3454 | if (!dirty) |
3455 | return; | |
3456 | ||
3457 | _ilk_disable_lp_wm(dev_priv, dirty); | |
3458 | ||
49a687c4 | 3459 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 3460 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 3461 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 3462 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 3463 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
3464 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
3465 | ||
49a687c4 | 3466 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 3467 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 3468 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 3469 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 3470 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
3471 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
3472 | ||
49a687c4 | 3473 | if (dirty & WM_DIRTY_DDB) { |
8652744b | 3474 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
ac9545fd VS |
3475 | val = I915_READ(WM_MISC); |
3476 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3477 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
3478 | else | |
3479 | val |= WM_MISC_DATA_PARTITION_5_6; | |
3480 | I915_WRITE(WM_MISC, val); | |
3481 | } else { | |
3482 | val = I915_READ(DISP_ARB_CTL2); | |
3483 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3484 | val &= ~DISP_DATA_PARTITION_5_6; | |
3485 | else | |
3486 | val |= DISP_DATA_PARTITION_5_6; | |
3487 | I915_WRITE(DISP_ARB_CTL2, val); | |
3488 | } | |
1011d8c4 PZ |
3489 | } |
3490 | ||
49a687c4 | 3491 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
3492 | val = I915_READ(DISP_ARB_CTL); |
3493 | if (results->enable_fbc_wm) | |
3494 | val &= ~DISP_FBC_WM_DIS; | |
3495 | else | |
3496 | val |= DISP_FBC_WM_DIS; | |
3497 | I915_WRITE(DISP_ARB_CTL, val); | |
3498 | } | |
3499 | ||
954911eb ID |
3500 | if (dirty & WM_DIRTY_LP(1) && |
3501 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
3502 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
3503 | ||
175fded1 | 3504 | if (INTEL_GEN(dev_priv) >= 7) { |
6cef2b8a VS |
3505 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
3506 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
3507 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
3508 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
3509 | } | |
801bcfff | 3510 | |
facd619b | 3511 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 3512 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 3513 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 3514 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 3515 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 3516 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
3517 | |
3518 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
3519 | } |
3520 | ||
ed4a6a7c | 3521 | bool ilk_disable_lp_wm(struct drm_device *dev) |
8553c18e | 3522 | { |
fac5e23e | 3523 | struct drm_i915_private *dev_priv = to_i915(dev); |
8553c18e VS |
3524 | |
3525 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
3526 | } | |
3527 | ||
656d1b89 | 3528 | #define SKL_SAGV_BLOCK_TIME 30 /* µs */ |
b9cec075 | 3529 | |
ee3d532f PZ |
3530 | /* |
3531 | * FIXME: We still don't have the proper code detect if we need to apply the WA, | |
3532 | * so assume we'll always need it in order to avoid underruns. | |
3533 | */ | |
3534 | static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) | |
3535 | { | |
3536 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
3537 | ||
b976dc53 | 3538 | if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) |
ee3d532f PZ |
3539 | return true; |
3540 | ||
3541 | return false; | |
3542 | } | |
3543 | ||
56feca91 PZ |
3544 | static bool |
3545 | intel_has_sagv(struct drm_i915_private *dev_priv) | |
3546 | { | |
6e3100ec PZ |
3547 | if (IS_KABYLAKE(dev_priv)) |
3548 | return true; | |
3549 | ||
3550 | if (IS_SKYLAKE(dev_priv) && | |
3551 | dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED) | |
3552 | return true; | |
3553 | ||
3554 | return false; | |
56feca91 PZ |
3555 | } |
3556 | ||
656d1b89 L |
3557 | /* |
3558 | * SAGV dynamically adjusts the system agent voltage and clock frequencies | |
3559 | * depending on power and performance requirements. The display engine access | |
3560 | * to system memory is blocked during the adjustment time. Because of the | |
3561 | * blocking time, having this enabled can cause full system hangs and/or pipe | |
3562 | * underruns if we don't meet all of the following requirements: | |
3563 | * | |
3564 | * - <= 1 pipe enabled | |
3565 | * - All planes can enable watermarks for latencies >= SAGV engine block time | |
3566 | * - We're not using an interlaced display configuration | |
3567 | */ | |
3568 | int | |
16dcdc4e | 3569 | intel_enable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 L |
3570 | { |
3571 | int ret; | |
3572 | ||
56feca91 PZ |
3573 | if (!intel_has_sagv(dev_priv)) |
3574 | return 0; | |
3575 | ||
3576 | if (dev_priv->sagv_status == I915_SAGV_ENABLED) | |
656d1b89 L |
3577 | return 0; |
3578 | ||
3579 | DRM_DEBUG_KMS("Enabling the SAGV\n"); | |
3580 | mutex_lock(&dev_priv->rps.hw_lock); | |
3581 | ||
3582 | ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, | |
3583 | GEN9_SAGV_ENABLE); | |
3584 | ||
3585 | /* We don't need to wait for the SAGV when enabling */ | |
3586 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3587 | ||
3588 | /* | |
3589 | * Some skl systems, pre-release machines in particular, | |
3590 | * don't actually have an SAGV. | |
3591 | */ | |
6e3100ec | 3592 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3593 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3594 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 L |
3595 | return 0; |
3596 | } else if (ret < 0) { | |
3597 | DRM_ERROR("Failed to enable the SAGV\n"); | |
3598 | return ret; | |
3599 | } | |
3600 | ||
16dcdc4e | 3601 | dev_priv->sagv_status = I915_SAGV_ENABLED; |
656d1b89 L |
3602 | return 0; |
3603 | } | |
3604 | ||
656d1b89 | 3605 | int |
16dcdc4e | 3606 | intel_disable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 | 3607 | { |
b3b8e999 | 3608 | int ret; |
656d1b89 | 3609 | |
56feca91 PZ |
3610 | if (!intel_has_sagv(dev_priv)) |
3611 | return 0; | |
3612 | ||
3613 | if (dev_priv->sagv_status == I915_SAGV_DISABLED) | |
656d1b89 L |
3614 | return 0; |
3615 | ||
3616 | DRM_DEBUG_KMS("Disabling the SAGV\n"); | |
3617 | mutex_lock(&dev_priv->rps.hw_lock); | |
3618 | ||
3619 | /* bspec says to keep retrying for at least 1 ms */ | |
b3b8e999 ID |
3620 | ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL, |
3621 | GEN9_SAGV_DISABLE, | |
3622 | GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, | |
3623 | 1); | |
656d1b89 L |
3624 | mutex_unlock(&dev_priv->rps.hw_lock); |
3625 | ||
656d1b89 L |
3626 | /* |
3627 | * Some skl systems, pre-release machines in particular, | |
3628 | * don't actually have an SAGV. | |
3629 | */ | |
b3b8e999 | 3630 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3631 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3632 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 | 3633 | return 0; |
b3b8e999 ID |
3634 | } else if (ret < 0) { |
3635 | DRM_ERROR("Failed to disable the SAGV (%d)\n", ret); | |
3636 | return ret; | |
656d1b89 L |
3637 | } |
3638 | ||
16dcdc4e | 3639 | dev_priv->sagv_status = I915_SAGV_DISABLED; |
656d1b89 L |
3640 | return 0; |
3641 | } | |
3642 | ||
16dcdc4e | 3643 | bool intel_can_enable_sagv(struct drm_atomic_state *state) |
656d1b89 L |
3644 | { |
3645 | struct drm_device *dev = state->dev; | |
3646 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3647 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
ee3d532f PZ |
3648 | struct intel_crtc *crtc; |
3649 | struct intel_plane *plane; | |
d8c0fafc | 3650 | struct intel_crtc_state *cstate; |
656d1b89 | 3651 | enum pipe pipe; |
d8c0fafc | 3652 | int level, latency; |
656d1b89 | 3653 | |
56feca91 PZ |
3654 | if (!intel_has_sagv(dev_priv)) |
3655 | return false; | |
3656 | ||
656d1b89 L |
3657 | /* |
3658 | * SKL workaround: bspec recommends we disable the SAGV when we have | |
3659 | * more then one pipe enabled | |
3660 | * | |
3661 | * If there are no active CRTCs, no additional checks need be performed | |
3662 | */ | |
3663 | if (hweight32(intel_state->active_crtcs) == 0) | |
3664 | return true; | |
3665 | else if (hweight32(intel_state->active_crtcs) > 1) | |
3666 | return false; | |
3667 | ||
3668 | /* Since we're now guaranteed to only have one active CRTC... */ | |
3669 | pipe = ffs(intel_state->active_crtcs) - 1; | |
98187836 | 3670 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
d8c0fafc | 3671 | cstate = to_intel_crtc_state(crtc->base.state); |
656d1b89 | 3672 | |
c89cadd5 | 3673 | if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
656d1b89 L |
3674 | return false; |
3675 | ||
ee3d532f | 3676 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
d5cdfdf5 VS |
3677 | struct skl_plane_wm *wm = |
3678 | &cstate->wm.skl.optimal.planes[plane->id]; | |
ee3d532f | 3679 | |
656d1b89 | 3680 | /* Skip this plane if it's not enabled */ |
d8c0fafc | 3681 | if (!wm->wm[0].plane_en) |
656d1b89 L |
3682 | continue; |
3683 | ||
3684 | /* Find the highest enabled wm level for this plane */ | |
5db94019 | 3685 | for (level = ilk_wm_max_level(dev_priv); |
d8c0fafc | 3686 | !wm->wm[level].plane_en; --level) |
656d1b89 L |
3687 | { } |
3688 | ||
ee3d532f PZ |
3689 | latency = dev_priv->wm.skl_latency[level]; |
3690 | ||
3691 | if (skl_needs_memory_bw_wa(intel_state) && | |
bae781b2 | 3692 | plane->base.state->fb->modifier == |
ee3d532f PZ |
3693 | I915_FORMAT_MOD_X_TILED) |
3694 | latency += 15; | |
3695 | ||
656d1b89 L |
3696 | /* |
3697 | * If any of the planes on this pipe don't enable wm levels | |
3698 | * that incur memory latencies higher then 30µs we can't enable | |
3699 | * the SAGV | |
3700 | */ | |
ee3d532f | 3701 | if (latency < SKL_SAGV_BLOCK_TIME) |
656d1b89 L |
3702 | return false; |
3703 | } | |
3704 | ||
3705 | return true; | |
3706 | } | |
3707 | ||
b9cec075 DL |
3708 | static void |
3709 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
024c9045 | 3710 | const struct intel_crtc_state *cstate, |
c107acfe MR |
3711 | struct skl_ddb_entry *alloc, /* out */ |
3712 | int *num_active /* out */) | |
b9cec075 | 3713 | { |
c107acfe MR |
3714 | struct drm_atomic_state *state = cstate->base.state; |
3715 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
3716 | struct drm_i915_private *dev_priv = to_i915(dev); | |
024c9045 | 3717 | struct drm_crtc *for_crtc = cstate->base.crtc; |
b9cec075 DL |
3718 | unsigned int pipe_size, ddb_size; |
3719 | int nth_active_pipe; | |
c107acfe | 3720 | |
a6d3460e | 3721 | if (WARN_ON(!state) || !cstate->base.active) { |
b9cec075 DL |
3722 | alloc->start = 0; |
3723 | alloc->end = 0; | |
a6d3460e | 3724 | *num_active = hweight32(dev_priv->active_crtcs); |
b9cec075 DL |
3725 | return; |
3726 | } | |
3727 | ||
a6d3460e MR |
3728 | if (intel_state->active_pipe_changes) |
3729 | *num_active = hweight32(intel_state->active_crtcs); | |
3730 | else | |
3731 | *num_active = hweight32(dev_priv->active_crtcs); | |
3732 | ||
6f3fff60 D |
3733 | ddb_size = INTEL_INFO(dev_priv)->ddb_size; |
3734 | WARN_ON(ddb_size == 0); | |
b9cec075 DL |
3735 | |
3736 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
3737 | ||
c107acfe | 3738 | /* |
a6d3460e MR |
3739 | * If the state doesn't change the active CRTC's, then there's |
3740 | * no need to recalculate; the existing pipe allocation limits | |
3741 | * should remain unchanged. Note that we're safe from racing | |
3742 | * commits since any racing commit that changes the active CRTC | |
3743 | * list would need to grab _all_ crtc locks, including the one | |
3744 | * we currently hold. | |
c107acfe | 3745 | */ |
a6d3460e | 3746 | if (!intel_state->active_pipe_changes) { |
512b5527 ML |
3747 | /* |
3748 | * alloc may be cleared by clear_intel_crtc_state, | |
3749 | * copy from old state to be sure | |
3750 | */ | |
3751 | *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; | |
a6d3460e | 3752 | return; |
c107acfe | 3753 | } |
a6d3460e MR |
3754 | |
3755 | nth_active_pipe = hweight32(intel_state->active_crtcs & | |
3756 | (drm_crtc_mask(for_crtc) - 1)); | |
3757 | pipe_size = ddb_size / hweight32(intel_state->active_crtcs); | |
3758 | alloc->start = nth_active_pipe * ddb_size / *num_active; | |
3759 | alloc->end = alloc->start + pipe_size; | |
b9cec075 DL |
3760 | } |
3761 | ||
c107acfe | 3762 | static unsigned int skl_cursor_allocation(int num_active) |
b9cec075 | 3763 | { |
c107acfe | 3764 | if (num_active == 1) |
b9cec075 DL |
3765 | return 32; |
3766 | ||
3767 | return 8; | |
3768 | } | |
3769 | ||
a269c583 DL |
3770 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
3771 | { | |
3772 | entry->start = reg & 0x3ff; | |
3773 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
3774 | if (entry->end) |
3775 | entry->end += 1; | |
a269c583 DL |
3776 | } |
3777 | ||
08db6652 DL |
3778 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
3779 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 3780 | { |
d5cdfdf5 | 3781 | struct intel_crtc *crtc; |
a269c583 | 3782 | |
b10f1b20 ML |
3783 | memset(ddb, 0, sizeof(*ddb)); |
3784 | ||
d5cdfdf5 | 3785 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
4d800030 | 3786 | enum intel_display_power_domain power_domain; |
d5cdfdf5 VS |
3787 | enum plane_id plane_id; |
3788 | enum pipe pipe = crtc->pipe; | |
4d800030 ID |
3789 | |
3790 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
3791 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b10f1b20 ML |
3792 | continue; |
3793 | ||
d5cdfdf5 VS |
3794 | for_each_plane_id_on_crtc(crtc, plane_id) { |
3795 | u32 val; | |
3796 | ||
3797 | if (plane_id != PLANE_CURSOR) | |
3798 | val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); | |
3799 | else | |
3800 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
a269c583 | 3801 | |
d5cdfdf5 VS |
3802 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val); |
3803 | } | |
4d800030 ID |
3804 | |
3805 | intel_display_power_put(dev_priv, power_domain); | |
a269c583 DL |
3806 | } |
3807 | } | |
3808 | ||
9c2f7a9d KM |
3809 | /* |
3810 | * Determines the downscale amount of a plane for the purposes of watermark calculations. | |
3811 | * The bspec defines downscale amount as: | |
3812 | * | |
3813 | * """ | |
3814 | * Horizontal down scale amount = maximum[1, Horizontal source size / | |
3815 | * Horizontal destination size] | |
3816 | * Vertical down scale amount = maximum[1, Vertical source size / | |
3817 | * Vertical destination size] | |
3818 | * Total down scale amount = Horizontal down scale amount * | |
3819 | * Vertical down scale amount | |
3820 | * """ | |
3821 | * | |
3822 | * Return value is provided in 16.16 fixed point form to retain fractional part. | |
3823 | * Caller should take care of dividing & rounding off the value. | |
3824 | */ | |
3825 | static uint32_t | |
93aa2a1c VS |
3826 | skl_plane_downscale_amount(const struct intel_crtc_state *cstate, |
3827 | const struct intel_plane_state *pstate) | |
9c2f7a9d | 3828 | { |
93aa2a1c | 3829 | struct intel_plane *plane = to_intel_plane(pstate->base.plane); |
9c2f7a9d KM |
3830 | uint32_t downscale_h, downscale_w; |
3831 | uint32_t src_w, src_h, dst_w, dst_h; | |
3832 | ||
93aa2a1c | 3833 | if (WARN_ON(!intel_wm_plane_visible(cstate, pstate))) |
9c2f7a9d KM |
3834 | return DRM_PLANE_HELPER_NO_SCALING; |
3835 | ||
3836 | /* n.b., src is 16.16 fixed point, dst is whole integer */ | |
93aa2a1c VS |
3837 | if (plane->id == PLANE_CURSOR) { |
3838 | src_w = pstate->base.src_w; | |
3839 | src_h = pstate->base.src_h; | |
3840 | dst_w = pstate->base.crtc_w; | |
3841 | dst_h = pstate->base.crtc_h; | |
3842 | } else { | |
3843 | src_w = drm_rect_width(&pstate->base.src); | |
3844 | src_h = drm_rect_height(&pstate->base.src); | |
3845 | dst_w = drm_rect_width(&pstate->base.dst); | |
3846 | dst_h = drm_rect_height(&pstate->base.dst); | |
3847 | } | |
3848 | ||
bd2ef25d | 3849 | if (drm_rotation_90_or_270(pstate->base.rotation)) |
9c2f7a9d KM |
3850 | swap(dst_w, dst_h); |
3851 | ||
3852 | downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING); | |
3853 | downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING); | |
3854 | ||
3855 | /* Provide result in 16.16 fixed point */ | |
3856 | return (uint64_t)downscale_w * downscale_h >> 16; | |
3857 | } | |
3858 | ||
b9cec075 | 3859 | static unsigned int |
024c9045 MR |
3860 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
3861 | const struct drm_plane_state *pstate, | |
3862 | int y) | |
b9cec075 | 3863 | { |
93aa2a1c | 3864 | struct intel_plane *plane = to_intel_plane(pstate->plane); |
a280f7dd | 3865 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); |
8d19d7d9 | 3866 | uint32_t down_scale_amount, data_rate; |
a280f7dd | 3867 | uint32_t width = 0, height = 0; |
8305494e VS |
3868 | struct drm_framebuffer *fb; |
3869 | u32 format; | |
a1de91e5 | 3870 | |
936e71e3 | 3871 | if (!intel_pstate->base.visible) |
a1de91e5 | 3872 | return 0; |
8305494e VS |
3873 | |
3874 | fb = pstate->fb; | |
438b74a5 | 3875 | format = fb->format->format; |
8305494e | 3876 | |
93aa2a1c | 3877 | if (plane->id == PLANE_CURSOR) |
a1de91e5 MR |
3878 | return 0; |
3879 | if (y && format != DRM_FORMAT_NV12) | |
3880 | return 0; | |
a280f7dd | 3881 | |
936e71e3 VS |
3882 | width = drm_rect_width(&intel_pstate->base.src) >> 16; |
3883 | height = drm_rect_height(&intel_pstate->base.src) >> 16; | |
a280f7dd | 3884 | |
bd2ef25d | 3885 | if (drm_rotation_90_or_270(pstate->rotation)) |
a280f7dd | 3886 | swap(width, height); |
2cd601c6 CK |
3887 | |
3888 | /* for planar format */ | |
a1de91e5 | 3889 | if (format == DRM_FORMAT_NV12) { |
2cd601c6 | 3890 | if (y) /* y-plane data rate */ |
8d19d7d9 | 3891 | data_rate = width * height * |
353c8598 | 3892 | fb->format->cpp[0]; |
2cd601c6 | 3893 | else /* uv-plane data rate */ |
8d19d7d9 | 3894 | data_rate = (width / 2) * (height / 2) * |
353c8598 | 3895 | fb->format->cpp[1]; |
8d19d7d9 KM |
3896 | } else { |
3897 | /* for packed formats */ | |
353c8598 | 3898 | data_rate = width * height * fb->format->cpp[0]; |
2cd601c6 CK |
3899 | } |
3900 | ||
93aa2a1c | 3901 | down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate); |
8d19d7d9 KM |
3902 | |
3903 | return (uint64_t)data_rate * down_scale_amount >> 16; | |
b9cec075 DL |
3904 | } |
3905 | ||
3906 | /* | |
3907 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
3908 | * a 8192x4096@32bpp framebuffer: | |
3909 | * 3 * 4096 * 8192 * 4 < 2^32 | |
3910 | */ | |
3911 | static unsigned int | |
1e6ee542 ML |
3912 | skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate, |
3913 | unsigned *plane_data_rate, | |
3914 | unsigned *plane_y_data_rate) | |
b9cec075 | 3915 | { |
9c74d826 MR |
3916 | struct drm_crtc_state *cstate = &intel_cstate->base; |
3917 | struct drm_atomic_state *state = cstate->state; | |
c8fe32c1 | 3918 | struct drm_plane *plane; |
c8fe32c1 | 3919 | const struct drm_plane_state *pstate; |
d5cdfdf5 | 3920 | unsigned int total_data_rate = 0; |
a6d3460e MR |
3921 | |
3922 | if (WARN_ON(!state)) | |
3923 | return 0; | |
b9cec075 | 3924 | |
a1de91e5 | 3925 | /* Calculate and cache data rate for each plane */ |
c8fe32c1 | 3926 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) { |
d5cdfdf5 VS |
3927 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3928 | unsigned int rate; | |
a6d3460e | 3929 | |
a6d3460e MR |
3930 | /* packed/uv */ |
3931 | rate = skl_plane_relative_data_rate(intel_cstate, | |
3932 | pstate, 0); | |
d5cdfdf5 | 3933 | plane_data_rate[plane_id] = rate; |
1e6ee542 ML |
3934 | |
3935 | total_data_rate += rate; | |
a6d3460e MR |
3936 | |
3937 | /* y-plane */ | |
3938 | rate = skl_plane_relative_data_rate(intel_cstate, | |
3939 | pstate, 1); | |
d5cdfdf5 | 3940 | plane_y_data_rate[plane_id] = rate; |
024c9045 | 3941 | |
1e6ee542 | 3942 | total_data_rate += rate; |
b9cec075 DL |
3943 | } |
3944 | ||
3945 | return total_data_rate; | |
3946 | } | |
3947 | ||
cbcfd14b KM |
3948 | static uint16_t |
3949 | skl_ddb_min_alloc(const struct drm_plane_state *pstate, | |
3950 | const int y) | |
3951 | { | |
3952 | struct drm_framebuffer *fb = pstate->fb; | |
3953 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); | |
3954 | uint32_t src_w, src_h; | |
3955 | uint32_t min_scanlines = 8; | |
3956 | uint8_t plane_bpp; | |
3957 | ||
3958 | if (WARN_ON(!fb)) | |
3959 | return 0; | |
3960 | ||
3961 | /* For packed formats, no y-plane, return 0 */ | |
438b74a5 | 3962 | if (y && fb->format->format != DRM_FORMAT_NV12) |
cbcfd14b KM |
3963 | return 0; |
3964 | ||
3965 | /* For Non Y-tile return 8-blocks */ | |
bae781b2 VS |
3966 | if (fb->modifier != I915_FORMAT_MOD_Y_TILED && |
3967 | fb->modifier != I915_FORMAT_MOD_Yf_TILED) | |
cbcfd14b KM |
3968 | return 8; |
3969 | ||
936e71e3 VS |
3970 | src_w = drm_rect_width(&intel_pstate->base.src) >> 16; |
3971 | src_h = drm_rect_height(&intel_pstate->base.src) >> 16; | |
cbcfd14b | 3972 | |
bd2ef25d | 3973 | if (drm_rotation_90_or_270(pstate->rotation)) |
cbcfd14b KM |
3974 | swap(src_w, src_h); |
3975 | ||
3976 | /* Halve UV plane width and height for NV12 */ | |
438b74a5 | 3977 | if (fb->format->format == DRM_FORMAT_NV12 && !y) { |
cbcfd14b KM |
3978 | src_w /= 2; |
3979 | src_h /= 2; | |
3980 | } | |
3981 | ||
438b74a5 | 3982 | if (fb->format->format == DRM_FORMAT_NV12 && !y) |
353c8598 | 3983 | plane_bpp = fb->format->cpp[1]; |
cbcfd14b | 3984 | else |
353c8598 | 3985 | plane_bpp = fb->format->cpp[0]; |
cbcfd14b | 3986 | |
bd2ef25d | 3987 | if (drm_rotation_90_or_270(pstate->rotation)) { |
cbcfd14b KM |
3988 | switch (plane_bpp) { |
3989 | case 1: | |
3990 | min_scanlines = 32; | |
3991 | break; | |
3992 | case 2: | |
3993 | min_scanlines = 16; | |
3994 | break; | |
3995 | case 4: | |
3996 | min_scanlines = 8; | |
3997 | break; | |
3998 | case 8: | |
3999 | min_scanlines = 4; | |
4000 | break; | |
4001 | default: | |
4002 | WARN(1, "Unsupported pixel depth %u for rotation", | |
4003 | plane_bpp); | |
4004 | min_scanlines = 32; | |
4005 | } | |
4006 | } | |
4007 | ||
4008 | return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3; | |
4009 | } | |
4010 | ||
49845a7a ML |
4011 | static void |
4012 | skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active, | |
4013 | uint16_t *minimum, uint16_t *y_minimum) | |
4014 | { | |
4015 | const struct drm_plane_state *pstate; | |
4016 | struct drm_plane *plane; | |
4017 | ||
4018 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) { | |
d5cdfdf5 | 4019 | enum plane_id plane_id = to_intel_plane(plane)->id; |
49845a7a | 4020 | |
d5cdfdf5 | 4021 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
4022 | continue; |
4023 | ||
4024 | if (!pstate->visible) | |
4025 | continue; | |
4026 | ||
d5cdfdf5 VS |
4027 | minimum[plane_id] = skl_ddb_min_alloc(pstate, 0); |
4028 | y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1); | |
49845a7a ML |
4029 | } |
4030 | ||
4031 | minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active); | |
4032 | } | |
4033 | ||
c107acfe | 4034 | static int |
024c9045 | 4035 | skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, |
b9cec075 DL |
4036 | struct skl_ddb_allocation *ddb /* out */) |
4037 | { | |
c107acfe | 4038 | struct drm_atomic_state *state = cstate->base.state; |
024c9045 | 4039 | struct drm_crtc *crtc = cstate->base.crtc; |
b9cec075 DL |
4040 | struct drm_device *dev = crtc->dev; |
4041 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4042 | enum pipe pipe = intel_crtc->pipe; | |
ce0ba283 | 4043 | struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb; |
49845a7a | 4044 | uint16_t alloc_size, start; |
fefdd810 ML |
4045 | uint16_t minimum[I915_MAX_PLANES] = {}; |
4046 | uint16_t y_minimum[I915_MAX_PLANES] = {}; | |
b9cec075 | 4047 | unsigned int total_data_rate; |
d5cdfdf5 | 4048 | enum plane_id plane_id; |
c107acfe | 4049 | int num_active; |
1e6ee542 ML |
4050 | unsigned plane_data_rate[I915_MAX_PLANES] = {}; |
4051 | unsigned plane_y_data_rate[I915_MAX_PLANES] = {}; | |
b9cec075 | 4052 | |
5a920b85 PZ |
4053 | /* Clear the partitioning for disabled planes. */ |
4054 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
4055 | memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe])); | |
4056 | ||
a6d3460e MR |
4057 | if (WARN_ON(!state)) |
4058 | return 0; | |
4059 | ||
c107acfe | 4060 | if (!cstate->base.active) { |
ce0ba283 | 4061 | alloc->start = alloc->end = 0; |
c107acfe MR |
4062 | return 0; |
4063 | } | |
4064 | ||
a6d3460e | 4065 | skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active); |
34bb56af | 4066 | alloc_size = skl_ddb_entry_size(alloc); |
b9cec075 DL |
4067 | if (alloc_size == 0) { |
4068 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
c107acfe | 4069 | return 0; |
b9cec075 DL |
4070 | } |
4071 | ||
49845a7a | 4072 | skl_ddb_calc_min(cstate, num_active, minimum, y_minimum); |
a6d3460e | 4073 | |
49845a7a ML |
4074 | /* |
4075 | * 1. Allocate the mininum required blocks for each active plane | |
4076 | * and allocate the cursor, it doesn't require extra allocation | |
4077 | * proportional to the data rate. | |
4078 | */ | |
80958155 | 4079 | |
d5cdfdf5 VS |
4080 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
4081 | alloc_size -= minimum[plane_id]; | |
4082 | alloc_size -= y_minimum[plane_id]; | |
80958155 DL |
4083 | } |
4084 | ||
49845a7a ML |
4085 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR]; |
4086 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; | |
4087 | ||
b9cec075 | 4088 | /* |
80958155 DL |
4089 | * 2. Distribute the remaining space in proportion to the amount of |
4090 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
4091 | * |
4092 | * FIXME: we may not allocate every single block here. | |
4093 | */ | |
1e6ee542 ML |
4094 | total_data_rate = skl_get_total_relative_data_rate(cstate, |
4095 | plane_data_rate, | |
4096 | plane_y_data_rate); | |
a1de91e5 | 4097 | if (total_data_rate == 0) |
c107acfe | 4098 | return 0; |
b9cec075 | 4099 | |
34bb56af | 4100 | start = alloc->start; |
d5cdfdf5 | 4101 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
2cd601c6 CK |
4102 | unsigned int data_rate, y_data_rate; |
4103 | uint16_t plane_blocks, y_plane_blocks = 0; | |
b9cec075 | 4104 | |
d5cdfdf5 | 4105 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
4106 | continue; |
4107 | ||
d5cdfdf5 | 4108 | data_rate = plane_data_rate[plane_id]; |
b9cec075 DL |
4109 | |
4110 | /* | |
2cd601c6 | 4111 | * allocation for (packed formats) or (uv-plane part of planar format): |
b9cec075 DL |
4112 | * promote the expression to 64 bits to avoid overflowing, the |
4113 | * result is < available as data_rate / total_data_rate < 1 | |
4114 | */ | |
d5cdfdf5 | 4115 | plane_blocks = minimum[plane_id]; |
80958155 DL |
4116 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
4117 | total_data_rate); | |
b9cec075 | 4118 | |
c107acfe MR |
4119 | /* Leave disabled planes at (0,0) */ |
4120 | if (data_rate) { | |
d5cdfdf5 VS |
4121 | ddb->plane[pipe][plane_id].start = start; |
4122 | ddb->plane[pipe][plane_id].end = start + plane_blocks; | |
c107acfe | 4123 | } |
b9cec075 DL |
4124 | |
4125 | start += plane_blocks; | |
2cd601c6 CK |
4126 | |
4127 | /* | |
4128 | * allocation for y_plane part of planar format: | |
4129 | */ | |
d5cdfdf5 | 4130 | y_data_rate = plane_y_data_rate[plane_id]; |
a1de91e5 | 4131 | |
d5cdfdf5 | 4132 | y_plane_blocks = y_minimum[plane_id]; |
a1de91e5 MR |
4133 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
4134 | total_data_rate); | |
2cd601c6 | 4135 | |
c107acfe | 4136 | if (y_data_rate) { |
d5cdfdf5 VS |
4137 | ddb->y_plane[pipe][plane_id].start = start; |
4138 | ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks; | |
c107acfe | 4139 | } |
a1de91e5 MR |
4140 | |
4141 | start += y_plane_blocks; | |
b9cec075 DL |
4142 | } |
4143 | ||
c107acfe | 4144 | return 0; |
b9cec075 DL |
4145 | } |
4146 | ||
2d41c0b5 PB |
4147 | /* |
4148 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
ac484963 | 4149 | * for the read latency) and cpp should always be <= 8, so that |
2d41c0b5 PB |
4150 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
4151 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
4152 | */ | |
b95320bd MK |
4153 | static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, |
4154 | uint32_t latency) | |
2d41c0b5 | 4155 | { |
b95320bd MK |
4156 | uint32_t wm_intermediate_val; |
4157 | uint_fixed_16_16_t ret; | |
2d41c0b5 PB |
4158 | |
4159 | if (latency == 0) | |
b95320bd | 4160 | return FP_16_16_MAX; |
2d41c0b5 | 4161 | |
b95320bd MK |
4162 | wm_intermediate_val = latency * pixel_rate * cpp; |
4163 | ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512); | |
2d41c0b5 PB |
4164 | return ret; |
4165 | } | |
4166 | ||
b95320bd MK |
4167 | static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate, |
4168 | uint32_t pipe_htotal, | |
4169 | uint32_t latency, | |
4170 | uint_fixed_16_16_t plane_blocks_per_line) | |
2d41c0b5 | 4171 | { |
d4c2aa60 | 4172 | uint32_t wm_intermediate_val; |
b95320bd | 4173 | uint_fixed_16_16_t ret; |
2d41c0b5 PB |
4174 | |
4175 | if (latency == 0) | |
b95320bd | 4176 | return FP_16_16_MAX; |
2d41c0b5 | 4177 | |
2d41c0b5 | 4178 | wm_intermediate_val = latency * pixel_rate; |
b95320bd MK |
4179 | wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, |
4180 | pipe_htotal * 1000); | |
4181 | ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line); | |
2d41c0b5 PB |
4182 | return ret; |
4183 | } | |
4184 | ||
9c2f7a9d KM |
4185 | static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, |
4186 | struct intel_plane_state *pstate) | |
4187 | { | |
4188 | uint64_t adjusted_pixel_rate; | |
4189 | uint64_t downscale_amount; | |
4190 | uint64_t pixel_rate; | |
4191 | ||
4192 | /* Shouldn't reach here on disabled planes... */ | |
93aa2a1c | 4193 | if (WARN_ON(!intel_wm_plane_visible(cstate, pstate))) |
9c2f7a9d KM |
4194 | return 0; |
4195 | ||
4196 | /* | |
4197 | * Adjusted plane pixel rate is just the pipe's adjusted pixel rate | |
4198 | * with additional adjustments for plane-specific scaling. | |
4199 | */ | |
a7d1b3f4 | 4200 | adjusted_pixel_rate = cstate->pixel_rate; |
93aa2a1c | 4201 | downscale_amount = skl_plane_downscale_amount(cstate, pstate); |
9c2f7a9d KM |
4202 | |
4203 | pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; | |
4204 | WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0)); | |
4205 | ||
4206 | return pixel_rate; | |
4207 | } | |
4208 | ||
55994c2c MR |
4209 | static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
4210 | struct intel_crtc_state *cstate, | |
4211 | struct intel_plane_state *intel_pstate, | |
4212 | uint16_t ddb_allocation, | |
4213 | int level, | |
4214 | uint16_t *out_blocks, /* out */ | |
4215 | uint8_t *out_lines, /* out */ | |
4216 | bool *enabled /* out */) | |
2d41c0b5 | 4217 | { |
93aa2a1c | 4218 | struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane); |
33815fa5 MR |
4219 | struct drm_plane_state *pstate = &intel_pstate->base; |
4220 | struct drm_framebuffer *fb = pstate->fb; | |
d4c2aa60 | 4221 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
b95320bd MK |
4222 | uint_fixed_16_16_t method1, method2; |
4223 | uint_fixed_16_16_t plane_blocks_per_line; | |
4224 | uint_fixed_16_16_t selected_result; | |
4225 | uint32_t interm_pbpl; | |
4226 | uint32_t plane_bytes_per_line; | |
d4c2aa60 | 4227 | uint32_t res_blocks, res_lines; |
ac484963 | 4228 | uint8_t cpp; |
a280f7dd | 4229 | uint32_t width = 0, height = 0; |
9c2f7a9d | 4230 | uint32_t plane_pixel_rate; |
b95320bd MK |
4231 | uint_fixed_16_16_t y_tile_minimum; |
4232 | uint32_t y_min_scanlines; | |
ee3d532f PZ |
4233 | struct intel_atomic_state *state = |
4234 | to_intel_atomic_state(cstate->base.state); | |
4235 | bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); | |
ef8a4fb4 | 4236 | bool y_tiled, x_tiled; |
2d41c0b5 | 4237 | |
93aa2a1c VS |
4238 | if (latency == 0 || |
4239 | !intel_wm_plane_visible(cstate, intel_pstate)) { | |
55994c2c MR |
4240 | *enabled = false; |
4241 | return 0; | |
4242 | } | |
2d41c0b5 | 4243 | |
ef8a4fb4 MK |
4244 | y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED || |
4245 | fb->modifier == I915_FORMAT_MOD_Yf_TILED; | |
4246 | x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; | |
4247 | ||
4b7b2331 MK |
4248 | /* Display WA #1141: kbl. */ |
4249 | if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled) | |
4250 | latency += 4; | |
4251 | ||
ef8a4fb4 | 4252 | if (apply_memory_bw_wa && x_tiled) |
ee3d532f PZ |
4253 | latency += 15; |
4254 | ||
93aa2a1c VS |
4255 | if (plane->id == PLANE_CURSOR) { |
4256 | width = intel_pstate->base.crtc_w; | |
4257 | height = intel_pstate->base.crtc_h; | |
4258 | } else { | |
4259 | width = drm_rect_width(&intel_pstate->base.src) >> 16; | |
4260 | height = drm_rect_height(&intel_pstate->base.src) >> 16; | |
4261 | } | |
a280f7dd | 4262 | |
bd2ef25d | 4263 | if (drm_rotation_90_or_270(pstate->rotation)) |
a280f7dd KM |
4264 | swap(width, height); |
4265 | ||
353c8598 | 4266 | cpp = fb->format->cpp[0]; |
9c2f7a9d KM |
4267 | plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate); |
4268 | ||
61d0a04d | 4269 | if (drm_rotation_90_or_270(pstate->rotation)) { |
438b74a5 | 4270 | int cpp = (fb->format->format == DRM_FORMAT_NV12) ? |
353c8598 VS |
4271 | fb->format->cpp[1] : |
4272 | fb->format->cpp[0]; | |
1186fa85 PZ |
4273 | |
4274 | switch (cpp) { | |
4275 | case 1: | |
4276 | y_min_scanlines = 16; | |
4277 | break; | |
4278 | case 2: | |
4279 | y_min_scanlines = 8; | |
4280 | break; | |
1186fa85 PZ |
4281 | case 4: |
4282 | y_min_scanlines = 4; | |
4283 | break; | |
86a462bc PZ |
4284 | default: |
4285 | MISSING_CASE(cpp); | |
4286 | return -EINVAL; | |
1186fa85 PZ |
4287 | } |
4288 | } else { | |
4289 | y_min_scanlines = 4; | |
4290 | } | |
4291 | ||
2ef32dee PZ |
4292 | if (apply_memory_bw_wa) |
4293 | y_min_scanlines *= 2; | |
4294 | ||
7a1a8aed | 4295 | plane_bytes_per_line = width * cpp; |
ef8a4fb4 | 4296 | if (y_tiled) { |
b95320bd MK |
4297 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * |
4298 | y_min_scanlines, 512); | |
7a1a8aed | 4299 | plane_blocks_per_line = |
b95320bd | 4300 | fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines); |
ef8a4fb4 | 4301 | } else if (x_tiled) { |
b95320bd MK |
4302 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); |
4303 | plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); | |
ef8a4fb4 | 4304 | } else { |
b95320bd MK |
4305 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1; |
4306 | plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); | |
7a1a8aed PZ |
4307 | } |
4308 | ||
9c2f7a9d KM |
4309 | method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); |
4310 | method2 = skl_wm_method2(plane_pixel_rate, | |
024c9045 | 4311 | cstate->base.adjusted_mode.crtc_htotal, |
1186fa85 | 4312 | latency, |
7a1a8aed | 4313 | plane_blocks_per_line); |
2d41c0b5 | 4314 | |
b95320bd MK |
4315 | y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines, |
4316 | plane_blocks_per_line); | |
75676ed4 | 4317 | |
ef8a4fb4 | 4318 | if (y_tiled) { |
b95320bd | 4319 | selected_result = max_fixed_16_16(method2, y_tile_minimum); |
0fda6568 | 4320 | } else { |
f1db3eaf PZ |
4321 | if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) && |
4322 | (plane_bytes_per_line / 512 < 1)) | |
4323 | selected_result = method2; | |
b95320bd MK |
4324 | else if ((ddb_allocation / |
4325 | fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1) | |
4326 | selected_result = min_fixed_16_16(method1, method2); | |
0fda6568 TU |
4327 | else |
4328 | selected_result = method1; | |
4329 | } | |
2d41c0b5 | 4330 | |
b95320bd MK |
4331 | res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1; |
4332 | res_lines = DIV_ROUND_UP(selected_result.val, | |
4333 | plane_blocks_per_line.val); | |
e6d66171 | 4334 | |
0fda6568 | 4335 | if (level >= 1 && level <= 7) { |
ef8a4fb4 | 4336 | if (y_tiled) { |
b95320bd | 4337 | res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum); |
1186fa85 | 4338 | res_lines += y_min_scanlines; |
75676ed4 | 4339 | } else { |
0fda6568 | 4340 | res_blocks++; |
75676ed4 | 4341 | } |
0fda6568 | 4342 | } |
e6d66171 | 4343 | |
55994c2c MR |
4344 | if (res_blocks >= ddb_allocation || res_lines > 31) { |
4345 | *enabled = false; | |
6b6bada7 MR |
4346 | |
4347 | /* | |
4348 | * If there are no valid level 0 watermarks, then we can't | |
4349 | * support this display configuration. | |
4350 | */ | |
4351 | if (level) { | |
4352 | return 0; | |
4353 | } else { | |
d5cdfdf5 VS |
4354 | struct drm_plane *plane = pstate->plane; |
4355 | ||
6b6bada7 | 4356 | DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n"); |
d5cdfdf5 VS |
4357 | DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n", |
4358 | plane->base.id, plane->name, | |
6b6bada7 | 4359 | res_blocks, ddb_allocation, res_lines); |
6b6bada7 MR |
4360 | return -EINVAL; |
4361 | } | |
55994c2c | 4362 | } |
e6d66171 DL |
4363 | |
4364 | *out_blocks = res_blocks; | |
4365 | *out_lines = res_lines; | |
55994c2c | 4366 | *enabled = true; |
2d41c0b5 | 4367 | |
55994c2c | 4368 | return 0; |
2d41c0b5 PB |
4369 | } |
4370 | ||
f4a96752 MR |
4371 | static int |
4372 | skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
4373 | struct skl_ddb_allocation *ddb, | |
4374 | struct intel_crtc_state *cstate, | |
a62163e9 | 4375 | struct intel_plane *intel_plane, |
f4a96752 MR |
4376 | int level, |
4377 | struct skl_wm_level *result) | |
2d41c0b5 | 4378 | { |
f4a96752 | 4379 | struct drm_atomic_state *state = cstate->base.state; |
024c9045 | 4380 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
a62163e9 L |
4381 | struct drm_plane *plane = &intel_plane->base; |
4382 | struct intel_plane_state *intel_pstate = NULL; | |
2d41c0b5 | 4383 | uint16_t ddb_blocks; |
024c9045 | 4384 | enum pipe pipe = intel_crtc->pipe; |
55994c2c | 4385 | int ret; |
a62163e9 L |
4386 | |
4387 | if (state) | |
4388 | intel_pstate = | |
4389 | intel_atomic_get_existing_plane_state(state, | |
4390 | intel_plane); | |
024c9045 | 4391 | |
f4a96752 | 4392 | /* |
a62163e9 L |
4393 | * Note: If we start supporting multiple pending atomic commits against |
4394 | * the same planes/CRTC's in the future, plane->state will no longer be | |
4395 | * the correct pre-state to use for the calculations here and we'll | |
4396 | * need to change where we get the 'unchanged' plane data from. | |
4397 | * | |
4398 | * For now this is fine because we only allow one queued commit against | |
4399 | * a CRTC. Even if the plane isn't modified by this transaction and we | |
4400 | * don't have a plane lock, we still have the CRTC's lock, so we know | |
4401 | * that no other transactions are racing with us to update it. | |
f4a96752 | 4402 | */ |
a62163e9 L |
4403 | if (!intel_pstate) |
4404 | intel_pstate = to_intel_plane_state(plane->state); | |
f4a96752 | 4405 | |
a62163e9 | 4406 | WARN_ON(!intel_pstate->base.fb); |
f4a96752 | 4407 | |
d5cdfdf5 | 4408 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); |
2d41c0b5 | 4409 | |
a62163e9 L |
4410 | ret = skl_compute_plane_wm(dev_priv, |
4411 | cstate, | |
4412 | intel_pstate, | |
4413 | ddb_blocks, | |
4414 | level, | |
4415 | &result->plane_res_b, | |
4416 | &result->plane_res_l, | |
4417 | &result->plane_en); | |
4418 | if (ret) | |
4419 | return ret; | |
f4a96752 MR |
4420 | |
4421 | return 0; | |
2d41c0b5 PB |
4422 | } |
4423 | ||
407b50f3 | 4424 | static uint32_t |
024c9045 | 4425 | skl_compute_linetime_wm(struct intel_crtc_state *cstate) |
407b50f3 | 4426 | { |
a3a8986c MK |
4427 | struct drm_atomic_state *state = cstate->base.state; |
4428 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
30d1b5fe | 4429 | uint32_t pixel_rate; |
a3a8986c | 4430 | uint32_t linetime_wm; |
30d1b5fe | 4431 | |
024c9045 | 4432 | if (!cstate->base.active) |
407b50f3 DL |
4433 | return 0; |
4434 | ||
a7d1b3f4 | 4435 | pixel_rate = cstate->pixel_rate; |
30d1b5fe PZ |
4436 | |
4437 | if (WARN_ON(pixel_rate == 0)) | |
661abfc0 | 4438 | return 0; |
407b50f3 | 4439 | |
a3a8986c MK |
4440 | linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * |
4441 | 1000, pixel_rate); | |
4442 | ||
4443 | /* Display WA #1135: bxt. */ | |
4444 | if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled) | |
4445 | linetime_wm = DIV_ROUND_UP(linetime_wm, 2); | |
4446 | ||
4447 | return linetime_wm; | |
407b50f3 DL |
4448 | } |
4449 | ||
024c9045 | 4450 | static void skl_compute_transition_wm(struct intel_crtc_state *cstate, |
9414f563 | 4451 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 4452 | { |
024c9045 | 4453 | if (!cstate->base.active) |
407b50f3 | 4454 | return; |
9414f563 DL |
4455 | |
4456 | /* Until we know more, just disable transition WMs */ | |
a62163e9 | 4457 | trans_wm->plane_en = false; |
407b50f3 DL |
4458 | } |
4459 | ||
55994c2c MR |
4460 | static int skl_build_pipe_wm(struct intel_crtc_state *cstate, |
4461 | struct skl_ddb_allocation *ddb, | |
4462 | struct skl_pipe_wm *pipe_wm) | |
2d41c0b5 | 4463 | { |
024c9045 | 4464 | struct drm_device *dev = cstate->base.crtc->dev; |
fac5e23e | 4465 | const struct drm_i915_private *dev_priv = to_i915(dev); |
a62163e9 L |
4466 | struct intel_plane *intel_plane; |
4467 | struct skl_plane_wm *wm; | |
5db94019 | 4468 | int level, max_level = ilk_wm_max_level(dev_priv); |
55994c2c | 4469 | int ret; |
2d41c0b5 | 4470 | |
a62163e9 L |
4471 | /* |
4472 | * We'll only calculate watermarks for planes that are actually | |
4473 | * enabled, so make sure all other planes are set as disabled. | |
4474 | */ | |
4475 | memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes)); | |
4476 | ||
4477 | for_each_intel_plane_mask(&dev_priv->drm, | |
4478 | intel_plane, | |
4479 | cstate->base.plane_mask) { | |
d5cdfdf5 | 4480 | wm = &pipe_wm->planes[intel_plane->id]; |
a62163e9 L |
4481 | |
4482 | for (level = 0; level <= max_level; level++) { | |
4483 | ret = skl_compute_wm_level(dev_priv, ddb, cstate, | |
4484 | intel_plane, level, | |
4485 | &wm->wm[level]); | |
4486 | if (ret) | |
4487 | return ret; | |
4488 | } | |
4489 | skl_compute_transition_wm(cstate, &wm->trans_wm); | |
2d41c0b5 | 4490 | } |
024c9045 | 4491 | pipe_wm->linetime = skl_compute_linetime_wm(cstate); |
2d41c0b5 | 4492 | |
55994c2c | 4493 | return 0; |
2d41c0b5 PB |
4494 | } |
4495 | ||
f0f59a00 VS |
4496 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, |
4497 | i915_reg_t reg, | |
16160e3d DL |
4498 | const struct skl_ddb_entry *entry) |
4499 | { | |
4500 | if (entry->end) | |
4501 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
4502 | else | |
4503 | I915_WRITE(reg, 0); | |
4504 | } | |
4505 | ||
d8c0fafc | 4506 | static void skl_write_wm_level(struct drm_i915_private *dev_priv, |
4507 | i915_reg_t reg, | |
4508 | const struct skl_wm_level *level) | |
4509 | { | |
4510 | uint32_t val = 0; | |
4511 | ||
4512 | if (level->plane_en) { | |
4513 | val |= PLANE_WM_EN; | |
4514 | val |= level->plane_res_b; | |
4515 | val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; | |
4516 | } | |
4517 | ||
4518 | I915_WRITE(reg, val); | |
4519 | } | |
4520 | ||
d9348dec VS |
4521 | static void skl_write_plane_wm(struct intel_crtc *intel_crtc, |
4522 | const struct skl_plane_wm *wm, | |
4523 | const struct skl_ddb_allocation *ddb, | |
d5cdfdf5 | 4524 | enum plane_id plane_id) |
62e0fb88 L |
4525 | { |
4526 | struct drm_crtc *crtc = &intel_crtc->base; | |
4527 | struct drm_device *dev = crtc->dev; | |
4528 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4529 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4530 | enum pipe pipe = intel_crtc->pipe; |
4531 | ||
4532 | for (level = 0; level <= max_level; level++) { | |
d5cdfdf5 | 4533 | skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), |
d8c0fafc | 4534 | &wm->wm[level]); |
62e0fb88 | 4535 | } |
d5cdfdf5 | 4536 | skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), |
d8c0fafc | 4537 | &wm->trans_wm); |
27082493 | 4538 | |
d5cdfdf5 VS |
4539 | skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), |
4540 | &ddb->plane[pipe][plane_id]); | |
4541 | skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id), | |
4542 | &ddb->y_plane[pipe][plane_id]); | |
62e0fb88 L |
4543 | } |
4544 | ||
d9348dec VS |
4545 | static void skl_write_cursor_wm(struct intel_crtc *intel_crtc, |
4546 | const struct skl_plane_wm *wm, | |
4547 | const struct skl_ddb_allocation *ddb) | |
62e0fb88 L |
4548 | { |
4549 | struct drm_crtc *crtc = &intel_crtc->base; | |
4550 | struct drm_device *dev = crtc->dev; | |
4551 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4552 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4553 | enum pipe pipe = intel_crtc->pipe; |
4554 | ||
4555 | for (level = 0; level <= max_level; level++) { | |
d8c0fafc | 4556 | skl_write_wm_level(dev_priv, CUR_WM(pipe, level), |
4557 | &wm->wm[level]); | |
62e0fb88 | 4558 | } |
d8c0fafc | 4559 | skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); |
5d374d96 | 4560 | |
27082493 | 4561 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
d8c0fafc | 4562 | &ddb->plane[pipe][PLANE_CURSOR]); |
2d41c0b5 PB |
4563 | } |
4564 | ||
45ece230 | 4565 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
4566 | const struct skl_wm_level *l2) | |
4567 | { | |
4568 | if (l1->plane_en != l2->plane_en) | |
4569 | return false; | |
4570 | ||
4571 | /* If both planes aren't enabled, the rest shouldn't matter */ | |
4572 | if (!l1->plane_en) | |
4573 | return true; | |
4574 | ||
4575 | return (l1->plane_res_l == l2->plane_res_l && | |
4576 | l1->plane_res_b == l2->plane_res_b); | |
4577 | } | |
4578 | ||
27082493 L |
4579 | static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, |
4580 | const struct skl_ddb_entry *b) | |
0e8fb7ba | 4581 | { |
27082493 | 4582 | return a->start < b->end && b->start < a->end; |
0e8fb7ba DL |
4583 | } |
4584 | ||
5eff503b ML |
4585 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, |
4586 | const struct skl_ddb_entry *ddb, | |
4587 | int ignore) | |
0e8fb7ba | 4588 | { |
ce0ba283 | 4589 | int i; |
0e8fb7ba | 4590 | |
5eff503b ML |
4591 | for (i = 0; i < I915_MAX_PIPES; i++) |
4592 | if (i != ignore && entries[i] && | |
4593 | skl_ddb_entries_overlap(ddb, entries[i])) | |
27082493 | 4594 | return true; |
0e8fb7ba | 4595 | |
27082493 | 4596 | return false; |
0e8fb7ba DL |
4597 | } |
4598 | ||
55994c2c | 4599 | static int skl_update_pipe_wm(struct drm_crtc_state *cstate, |
03af79e0 | 4600 | const struct skl_pipe_wm *old_pipe_wm, |
55994c2c | 4601 | struct skl_pipe_wm *pipe_wm, /* out */ |
03af79e0 | 4602 | struct skl_ddb_allocation *ddb, /* out */ |
55994c2c | 4603 | bool *changed /* out */) |
2d41c0b5 | 4604 | { |
f4a96752 | 4605 | struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate); |
55994c2c | 4606 | int ret; |
2d41c0b5 | 4607 | |
55994c2c MR |
4608 | ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm); |
4609 | if (ret) | |
4610 | return ret; | |
2d41c0b5 | 4611 | |
03af79e0 | 4612 | if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm))) |
55994c2c MR |
4613 | *changed = false; |
4614 | else | |
4615 | *changed = true; | |
2d41c0b5 | 4616 | |
55994c2c | 4617 | return 0; |
2d41c0b5 PB |
4618 | } |
4619 | ||
9b613022 MR |
4620 | static uint32_t |
4621 | pipes_modified(struct drm_atomic_state *state) | |
4622 | { | |
4623 | struct drm_crtc *crtc; | |
4624 | struct drm_crtc_state *cstate; | |
4625 | uint32_t i, ret = 0; | |
4626 | ||
6ebdb5a0 | 4627 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
9b613022 MR |
4628 | ret |= drm_crtc_mask(crtc); |
4629 | ||
4630 | return ret; | |
4631 | } | |
4632 | ||
bb7791bd | 4633 | static int |
7f60e200 PZ |
4634 | skl_ddb_add_affected_planes(struct intel_crtc_state *cstate) |
4635 | { | |
4636 | struct drm_atomic_state *state = cstate->base.state; | |
4637 | struct drm_device *dev = state->dev; | |
4638 | struct drm_crtc *crtc = cstate->base.crtc; | |
4639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4640 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4641 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4642 | struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
4643 | struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
4644 | struct drm_plane_state *plane_state; | |
4645 | struct drm_plane *plane; | |
4646 | enum pipe pipe = intel_crtc->pipe; | |
7f60e200 PZ |
4647 | |
4648 | WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc)); | |
4649 | ||
220b0965 | 4650 | drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) { |
d5cdfdf5 | 4651 | enum plane_id plane_id = to_intel_plane(plane)->id; |
7f60e200 | 4652 | |
d5cdfdf5 VS |
4653 | if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id], |
4654 | &new_ddb->plane[pipe][plane_id]) && | |
4655 | skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id], | |
4656 | &new_ddb->y_plane[pipe][plane_id])) | |
7f60e200 PZ |
4657 | continue; |
4658 | ||
4659 | plane_state = drm_atomic_get_plane_state(state, plane); | |
4660 | if (IS_ERR(plane_state)) | |
4661 | return PTR_ERR(plane_state); | |
4662 | } | |
4663 | ||
4664 | return 0; | |
4665 | } | |
4666 | ||
98d39494 MR |
4667 | static int |
4668 | skl_compute_ddb(struct drm_atomic_state *state) | |
4669 | { | |
4670 | struct drm_device *dev = state->dev; | |
4671 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4672 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4673 | struct intel_crtc *intel_crtc; | |
734fa01f | 4674 | struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb; |
9b613022 | 4675 | uint32_t realloc_pipes = pipes_modified(state); |
98d39494 MR |
4676 | int ret; |
4677 | ||
4678 | /* | |
4679 | * If this is our first atomic update following hardware readout, | |
4680 | * we can't trust the DDB that the BIOS programmed for us. Let's | |
4681 | * pretend that all pipes switched active status so that we'll | |
4682 | * ensure a full DDB recompute. | |
4683 | */ | |
1b54a880 MR |
4684 | if (dev_priv->wm.distrust_bios_wm) { |
4685 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, | |
4686 | state->acquire_ctx); | |
4687 | if (ret) | |
4688 | return ret; | |
4689 | ||
98d39494 MR |
4690 | intel_state->active_pipe_changes = ~0; |
4691 | ||
1b54a880 MR |
4692 | /* |
4693 | * We usually only initialize intel_state->active_crtcs if we | |
4694 | * we're doing a modeset; make sure this field is always | |
4695 | * initialized during the sanitization process that happens | |
4696 | * on the first commit too. | |
4697 | */ | |
4698 | if (!intel_state->modeset) | |
4699 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
4700 | } | |
4701 | ||
98d39494 MR |
4702 | /* |
4703 | * If the modeset changes which CRTC's are active, we need to | |
4704 | * recompute the DDB allocation for *all* active pipes, even | |
4705 | * those that weren't otherwise being modified in any way by this | |
4706 | * atomic commit. Due to the shrinking of the per-pipe allocations | |
4707 | * when new active CRTC's are added, it's possible for a pipe that | |
4708 | * we were already using and aren't changing at all here to suddenly | |
4709 | * become invalid if its DDB needs exceeds its new allocation. | |
4710 | * | |
4711 | * Note that if we wind up doing a full DDB recompute, we can't let | |
4712 | * any other display updates race with this transaction, so we need | |
4713 | * to grab the lock on *all* CRTC's. | |
4714 | */ | |
734fa01f | 4715 | if (intel_state->active_pipe_changes) { |
98d39494 | 4716 | realloc_pipes = ~0; |
734fa01f MR |
4717 | intel_state->wm_results.dirty_pipes = ~0; |
4718 | } | |
98d39494 | 4719 | |
5a920b85 PZ |
4720 | /* |
4721 | * We're not recomputing for the pipes not included in the commit, so | |
4722 | * make sure we start with the current state. | |
4723 | */ | |
4724 | memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); | |
4725 | ||
98d39494 MR |
4726 | for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { |
4727 | struct intel_crtc_state *cstate; | |
4728 | ||
4729 | cstate = intel_atomic_get_crtc_state(state, intel_crtc); | |
4730 | if (IS_ERR(cstate)) | |
4731 | return PTR_ERR(cstate); | |
4732 | ||
734fa01f | 4733 | ret = skl_allocate_pipe_ddb(cstate, ddb); |
98d39494 MR |
4734 | if (ret) |
4735 | return ret; | |
05a76d3d | 4736 | |
7f60e200 | 4737 | ret = skl_ddb_add_affected_planes(cstate); |
05a76d3d L |
4738 | if (ret) |
4739 | return ret; | |
98d39494 MR |
4740 | } |
4741 | ||
4742 | return 0; | |
4743 | } | |
4744 | ||
2722efb9 MR |
4745 | static void |
4746 | skl_copy_wm_for_pipe(struct skl_wm_values *dst, | |
4747 | struct skl_wm_values *src, | |
4748 | enum pipe pipe) | |
4749 | { | |
2722efb9 MR |
4750 | memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe], |
4751 | sizeof(dst->ddb.y_plane[pipe])); | |
4752 | memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe], | |
4753 | sizeof(dst->ddb.plane[pipe])); | |
4754 | } | |
4755 | ||
413fc530 | 4756 | static void |
4757 | skl_print_wm_changes(const struct drm_atomic_state *state) | |
4758 | { | |
4759 | const struct drm_device *dev = state->dev; | |
4760 | const struct drm_i915_private *dev_priv = to_i915(dev); | |
4761 | const struct intel_atomic_state *intel_state = | |
4762 | to_intel_atomic_state(state); | |
4763 | const struct drm_crtc *crtc; | |
4764 | const struct drm_crtc_state *cstate; | |
413fc530 | 4765 | const struct intel_plane *intel_plane; |
413fc530 | 4766 | const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; |
4767 | const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
7570498e | 4768 | int i; |
413fc530 | 4769 | |
6ebdb5a0 | 4770 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
7570498e ML |
4771 | const struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4772 | enum pipe pipe = intel_crtc->pipe; | |
413fc530 | 4773 | |
7570498e | 4774 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
d5cdfdf5 | 4775 | enum plane_id plane_id = intel_plane->id; |
413fc530 | 4776 | const struct skl_ddb_entry *old, *new; |
4777 | ||
d5cdfdf5 VS |
4778 | old = &old_ddb->plane[pipe][plane_id]; |
4779 | new = &new_ddb->plane[pipe][plane_id]; | |
413fc530 | 4780 | |
413fc530 | 4781 | if (skl_ddb_entry_equal(old, new)) |
4782 | continue; | |
4783 | ||
7570498e ML |
4784 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n", |
4785 | intel_plane->base.base.id, | |
4786 | intel_plane->base.name, | |
4787 | old->start, old->end, | |
4788 | new->start, new->end); | |
413fc530 | 4789 | } |
4790 | } | |
4791 | } | |
4792 | ||
98d39494 MR |
4793 | static int |
4794 | skl_compute_wm(struct drm_atomic_state *state) | |
4795 | { | |
4796 | struct drm_crtc *crtc; | |
4797 | struct drm_crtc_state *cstate; | |
734fa01f MR |
4798 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
4799 | struct skl_wm_values *results = &intel_state->wm_results; | |
4800 | struct skl_pipe_wm *pipe_wm; | |
98d39494 | 4801 | bool changed = false; |
734fa01f | 4802 | int ret, i; |
98d39494 MR |
4803 | |
4804 | /* | |
4805 | * If this transaction isn't actually touching any CRTC's, don't | |
4806 | * bother with watermark calculation. Note that if we pass this | |
4807 | * test, we're guaranteed to hold at least one CRTC state mutex, | |
4808 | * which means we can safely use values like dev_priv->active_crtcs | |
4809 | * since any racing commits that want to update them would need to | |
4810 | * hold _all_ CRTC state mutexes. | |
4811 | */ | |
6ebdb5a0 | 4812 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
98d39494 MR |
4813 | changed = true; |
4814 | if (!changed) | |
4815 | return 0; | |
4816 | ||
734fa01f MR |
4817 | /* Clear all dirty flags */ |
4818 | results->dirty_pipes = 0; | |
4819 | ||
98d39494 MR |
4820 | ret = skl_compute_ddb(state); |
4821 | if (ret) | |
4822 | return ret; | |
4823 | ||
734fa01f MR |
4824 | /* |
4825 | * Calculate WM's for all pipes that are part of this transaction. | |
4826 | * Note that the DDB allocation above may have added more CRTC's that | |
4827 | * weren't otherwise being modified (and set bits in dirty_pipes) if | |
4828 | * pipe allocations had to change. | |
4829 | * | |
4830 | * FIXME: Now that we're doing this in the atomic check phase, we | |
4831 | * should allow skl_update_pipe_wm() to return failure in cases where | |
4832 | * no suitable watermark values can be found. | |
4833 | */ | |
6ebdb5a0 | 4834 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
734fa01f MR |
4835 | struct intel_crtc_state *intel_cstate = |
4836 | to_intel_crtc_state(cstate); | |
03af79e0 ML |
4837 | const struct skl_pipe_wm *old_pipe_wm = |
4838 | &to_intel_crtc_state(crtc->state)->wm.skl.optimal; | |
734fa01f MR |
4839 | |
4840 | pipe_wm = &intel_cstate->wm.skl.optimal; | |
03af79e0 ML |
4841 | ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, |
4842 | &results->ddb, &changed); | |
734fa01f MR |
4843 | if (ret) |
4844 | return ret; | |
4845 | ||
4846 | if (changed) | |
4847 | results->dirty_pipes |= drm_crtc_mask(crtc); | |
4848 | ||
4849 | if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0) | |
4850 | /* This pipe's WM's did not change */ | |
4851 | continue; | |
4852 | ||
4853 | intel_cstate->update_wm_pre = true; | |
734fa01f MR |
4854 | } |
4855 | ||
413fc530 | 4856 | skl_print_wm_changes(state); |
4857 | ||
98d39494 MR |
4858 | return 0; |
4859 | } | |
4860 | ||
ccf010fb ML |
4861 | static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, |
4862 | struct intel_crtc_state *cstate) | |
4863 | { | |
4864 | struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); | |
4865 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
4866 | struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal; | |
e62929b3 | 4867 | const struct skl_ddb_allocation *ddb = &state->wm_results.ddb; |
ccf010fb | 4868 | enum pipe pipe = crtc->pipe; |
d5cdfdf5 | 4869 | enum plane_id plane_id; |
e62929b3 ML |
4870 | |
4871 | if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base))) | |
4872 | return; | |
ccf010fb ML |
4873 | |
4874 | I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); | |
e62929b3 | 4875 | |
d5cdfdf5 VS |
4876 | for_each_plane_id_on_crtc(crtc, plane_id) { |
4877 | if (plane_id != PLANE_CURSOR) | |
4878 | skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id], | |
4879 | ddb, plane_id); | |
4880 | else | |
4881 | skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id], | |
4882 | ddb); | |
4883 | } | |
ccf010fb ML |
4884 | } |
4885 | ||
e62929b3 ML |
4886 | static void skl_initial_wm(struct intel_atomic_state *state, |
4887 | struct intel_crtc_state *cstate) | |
2d41c0b5 | 4888 | { |
e62929b3 | 4889 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
432081bc | 4890 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4891 | struct drm_i915_private *dev_priv = to_i915(dev); |
e62929b3 | 4892 | struct skl_wm_values *results = &state->wm_results; |
2722efb9 | 4893 | struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw; |
27082493 | 4894 | enum pipe pipe = intel_crtc->pipe; |
adda50b8 | 4895 | |
432081bc | 4896 | if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0) |
2d41c0b5 PB |
4897 | return; |
4898 | ||
734fa01f | 4899 | mutex_lock(&dev_priv->wm.wm_mutex); |
2d41c0b5 | 4900 | |
e62929b3 ML |
4901 | if (cstate->base.active_changed) |
4902 | skl_atomic_update_crtc_wm(state, cstate); | |
27082493 L |
4903 | |
4904 | skl_copy_wm_for_pipe(hw_vals, results, pipe); | |
734fa01f MR |
4905 | |
4906 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2d41c0b5 PB |
4907 | } |
4908 | ||
d890565c VS |
4909 | static void ilk_compute_wm_config(struct drm_device *dev, |
4910 | struct intel_wm_config *config) | |
4911 | { | |
4912 | struct intel_crtc *crtc; | |
4913 | ||
4914 | /* Compute the currently _active_ config */ | |
4915 | for_each_intel_crtc(dev, crtc) { | |
4916 | const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; | |
4917 | ||
4918 | if (!wm->pipe_enabled) | |
4919 | continue; | |
4920 | ||
4921 | config->sprites_enabled |= wm->sprites_enabled; | |
4922 | config->sprites_scaled |= wm->sprites_scaled; | |
4923 | config->num_pipes_active++; | |
4924 | } | |
4925 | } | |
4926 | ||
ed4a6a7c | 4927 | static void ilk_program_watermarks(struct drm_i915_private *dev_priv) |
801bcfff | 4928 | { |
91c8a326 | 4929 | struct drm_device *dev = &dev_priv->drm; |
b9d5c839 | 4930 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
820c1980 | 4931 | struct ilk_wm_maximums max; |
d890565c | 4932 | struct intel_wm_config config = {}; |
820c1980 | 4933 | struct ilk_wm_values results = {}; |
77c122bc | 4934 | enum intel_ddb_partitioning partitioning; |
261a27d1 | 4935 | |
d890565c VS |
4936 | ilk_compute_wm_config(dev, &config); |
4937 | ||
4938 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); | |
4939 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); | |
a485bfb8 VS |
4940 | |
4941 | /* 5/6 split only in single pipe config on IVB+ */ | |
175fded1 | 4942 | if (INTEL_GEN(dev_priv) >= 7 && |
d890565c VS |
4943 | config.num_pipes_active == 1 && config.sprites_enabled) { |
4944 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); | |
4945 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); | |
0362c781 | 4946 | |
820c1980 | 4947 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 4948 | } else { |
198a1e9b | 4949 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
4950 | } |
4951 | ||
198a1e9b | 4952 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 4953 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 4954 | |
820c1980 | 4955 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 4956 | |
820c1980 | 4957 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
4958 | } |
4959 | ||
ccf010fb ML |
4960 | static void ilk_initial_watermarks(struct intel_atomic_state *state, |
4961 | struct intel_crtc_state *cstate) | |
b9d5c839 | 4962 | { |
ed4a6a7c MR |
4963 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); |
4964 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
b9d5c839 | 4965 | |
ed4a6a7c | 4966 | mutex_lock(&dev_priv->wm.wm_mutex); |
e8f1f02e | 4967 | intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate; |
ed4a6a7c MR |
4968 | ilk_program_watermarks(dev_priv); |
4969 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
4970 | } | |
bf220452 | 4971 | |
ccf010fb ML |
4972 | static void ilk_optimize_watermarks(struct intel_atomic_state *state, |
4973 | struct intel_crtc_state *cstate) | |
ed4a6a7c MR |
4974 | { |
4975 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); | |
4976 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
bf220452 | 4977 | |
ed4a6a7c MR |
4978 | mutex_lock(&dev_priv->wm.wm_mutex); |
4979 | if (cstate->wm.need_postvbl_update) { | |
e8f1f02e | 4980 | intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal; |
ed4a6a7c MR |
4981 | ilk_program_watermarks(dev_priv); |
4982 | } | |
4983 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
b9d5c839 VS |
4984 | } |
4985 | ||
d8c0fafc | 4986 | static inline void skl_wm_level_from_reg_val(uint32_t val, |
4987 | struct skl_wm_level *level) | |
3078999f | 4988 | { |
d8c0fafc | 4989 | level->plane_en = val & PLANE_WM_EN; |
4990 | level->plane_res_b = val & PLANE_WM_BLOCKS_MASK; | |
4991 | level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) & | |
4992 | PLANE_WM_LINES_MASK; | |
3078999f PB |
4993 | } |
4994 | ||
bf9d99ad | 4995 | void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, |
4996 | struct skl_pipe_wm *out) | |
3078999f | 4997 | { |
d5cdfdf5 | 4998 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
3078999f | 4999 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3078999f | 5000 | enum pipe pipe = intel_crtc->pipe; |
d5cdfdf5 VS |
5001 | int level, max_level; |
5002 | enum plane_id plane_id; | |
d8c0fafc | 5003 | uint32_t val; |
3078999f | 5004 | |
5db94019 | 5005 | max_level = ilk_wm_max_level(dev_priv); |
3078999f | 5006 | |
d5cdfdf5 VS |
5007 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
5008 | struct skl_plane_wm *wm = &out->planes[plane_id]; | |
3078999f | 5009 | |
d8c0fafc | 5010 | for (level = 0; level <= max_level; level++) { |
d5cdfdf5 VS |
5011 | if (plane_id != PLANE_CURSOR) |
5012 | val = I915_READ(PLANE_WM(pipe, plane_id, level)); | |
d8c0fafc | 5013 | else |
5014 | val = I915_READ(CUR_WM(pipe, level)); | |
3078999f | 5015 | |
d8c0fafc | 5016 | skl_wm_level_from_reg_val(val, &wm->wm[level]); |
3078999f | 5017 | } |
3078999f | 5018 | |
d5cdfdf5 VS |
5019 | if (plane_id != PLANE_CURSOR) |
5020 | val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); | |
d8c0fafc | 5021 | else |
5022 | val = I915_READ(CUR_WM_TRANS(pipe)); | |
5023 | ||
5024 | skl_wm_level_from_reg_val(val, &wm->trans_wm); | |
3078999f PB |
5025 | } |
5026 | ||
d8c0fafc | 5027 | if (!intel_crtc->active) |
5028 | return; | |
4e0963c7 | 5029 | |
bf9d99ad | 5030 | out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); |
3078999f PB |
5031 | } |
5032 | ||
5033 | void skl_wm_get_hw_state(struct drm_device *dev) | |
5034 | { | |
fac5e23e | 5035 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf9d99ad | 5036 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
a269c583 | 5037 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
3078999f | 5038 | struct drm_crtc *crtc; |
bf9d99ad | 5039 | struct intel_crtc *intel_crtc; |
5040 | struct intel_crtc_state *cstate; | |
3078999f | 5041 | |
a269c583 | 5042 | skl_ddb_get_hw_state(dev_priv, ddb); |
bf9d99ad | 5043 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
5044 | intel_crtc = to_intel_crtc(crtc); | |
5045 | cstate = to_intel_crtc_state(crtc->state); | |
5046 | ||
5047 | skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal); | |
5048 | ||
03af79e0 | 5049 | if (intel_crtc->active) |
bf9d99ad | 5050 | hw->dirty_pipes |= drm_crtc_mask(crtc); |
bf9d99ad | 5051 | } |
a1de91e5 | 5052 | |
279e99d7 MR |
5053 | if (dev_priv->active_crtcs) { |
5054 | /* Fully recompute DDB on first atomic commit */ | |
5055 | dev_priv->wm.distrust_bios_wm = true; | |
5056 | } else { | |
5057 | /* Easy/common case; just sanitize DDB now if everything off */ | |
5058 | memset(ddb, 0, sizeof(*ddb)); | |
5059 | } | |
3078999f PB |
5060 | } |
5061 | ||
243e6a44 VS |
5062 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
5063 | { | |
5064 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5065 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 5066 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 | 5067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4e0963c7 | 5068 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
e8f1f02e | 5069 | struct intel_pipe_wm *active = &cstate->wm.ilk.optimal; |
243e6a44 | 5070 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 | 5071 | static const i915_reg_t wm0_pipe_reg[] = { |
243e6a44 VS |
5072 | [PIPE_A] = WM0_PIPEA_ILK, |
5073 | [PIPE_B] = WM0_PIPEB_ILK, | |
5074 | [PIPE_C] = WM0_PIPEC_IVB, | |
5075 | }; | |
5076 | ||
5077 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
8652744b | 5078 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ce0e0713 | 5079 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 5080 | |
15606534 VS |
5081 | memset(active, 0, sizeof(*active)); |
5082 | ||
3ef00284 | 5083 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
5084 | |
5085 | if (active->pipe_enabled) { | |
243e6a44 VS |
5086 | u32 tmp = hw->wm_pipe[pipe]; |
5087 | ||
5088 | /* | |
5089 | * For active pipes LP0 watermark is marked as | |
5090 | * enabled, and LP1+ watermaks as disabled since | |
5091 | * we can't really reverse compute them in case | |
5092 | * multiple pipes are active. | |
5093 | */ | |
5094 | active->wm[0].enable = true; | |
5095 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
5096 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
5097 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
5098 | active->linetime = hw->wm_linetime[pipe]; | |
5099 | } else { | |
5db94019 | 5100 | int level, max_level = ilk_wm_max_level(dev_priv); |
243e6a44 VS |
5101 | |
5102 | /* | |
5103 | * For inactive pipes, all watermark levels | |
5104 | * should be marked as enabled but zeroed, | |
5105 | * which is what we'd compute them to. | |
5106 | */ | |
5107 | for (level = 0; level <= max_level; level++) | |
5108 | active->wm[level].enable = true; | |
5109 | } | |
4e0963c7 MR |
5110 | |
5111 | intel_crtc->wm.active.ilk = *active; | |
243e6a44 VS |
5112 | } |
5113 | ||
6eb1a681 VS |
5114 | #define _FW_WM(value, plane) \ |
5115 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) | |
5116 | #define _FW_WM_VLV(value, plane) \ | |
5117 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) | |
5118 | ||
04548cba VS |
5119 | static void g4x_read_wm_values(struct drm_i915_private *dev_priv, |
5120 | struct g4x_wm_values *wm) | |
5121 | { | |
5122 | uint32_t tmp; | |
5123 | ||
5124 | tmp = I915_READ(DSPFW1); | |
5125 | wm->sr.plane = _FW_WM(tmp, SR); | |
5126 | wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); | |
5127 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); | |
5128 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); | |
5129 | ||
5130 | tmp = I915_READ(DSPFW2); | |
5131 | wm->fbc_en = tmp & DSPFW_FBC_SR_EN; | |
5132 | wm->sr.fbc = _FW_WM(tmp, FBC_SR); | |
5133 | wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR); | |
5134 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); | |
5135 | wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); | |
5136 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); | |
5137 | ||
5138 | tmp = I915_READ(DSPFW3); | |
5139 | wm->hpll_en = tmp & DSPFW_HPLL_SR_EN; | |
5140 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
5141 | wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR); | |
5142 | wm->hpll.plane = _FW_WM(tmp, HPLL_SR); | |
5143 | } | |
5144 | ||
6eb1a681 VS |
5145 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, |
5146 | struct vlv_wm_values *wm) | |
5147 | { | |
5148 | enum pipe pipe; | |
5149 | uint32_t tmp; | |
5150 | ||
5151 | for_each_pipe(dev_priv, pipe) { | |
5152 | tmp = I915_READ(VLV_DDL(pipe)); | |
5153 | ||
1b31389c | 5154 | wm->ddl[pipe].plane[PLANE_PRIMARY] = |
6eb1a681 | 5155 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 5156 | wm->ddl[pipe].plane[PLANE_CURSOR] = |
6eb1a681 | 5157 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 5158 | wm->ddl[pipe].plane[PLANE_SPRITE0] = |
6eb1a681 | 5159 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 5160 | wm->ddl[pipe].plane[PLANE_SPRITE1] = |
6eb1a681 VS |
5161 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
5162 | } | |
5163 | ||
5164 | tmp = I915_READ(DSPFW1); | |
5165 | wm->sr.plane = _FW_WM(tmp, SR); | |
1b31389c VS |
5166 | wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); |
5167 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); | |
5168 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); | |
6eb1a681 VS |
5169 | |
5170 | tmp = I915_READ(DSPFW2); | |
1b31389c VS |
5171 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); |
5172 | wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); | |
5173 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); | |
6eb1a681 VS |
5174 | |
5175 | tmp = I915_READ(DSPFW3); | |
5176 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
5177 | ||
5178 | if (IS_CHERRYVIEW(dev_priv)) { | |
5179 | tmp = I915_READ(DSPFW7_CHV); | |
1b31389c VS |
5180 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
5181 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
5182 | |
5183 | tmp = I915_READ(DSPFW8_CHV); | |
1b31389c VS |
5184 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); |
5185 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); | |
6eb1a681 VS |
5186 | |
5187 | tmp = I915_READ(DSPFW9_CHV); | |
1b31389c VS |
5188 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); |
5189 | wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); | |
6eb1a681 VS |
5190 | |
5191 | tmp = I915_READ(DSPHOWM); | |
5192 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
5193 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; |
5194 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; | |
5195 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; | |
5196 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
5197 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
5198 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
5199 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
5200 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
5201 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
5202 | } else { |
5203 | tmp = I915_READ(DSPFW7); | |
1b31389c VS |
5204 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
5205 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
5206 | |
5207 | tmp = I915_READ(DSPHOWM); | |
5208 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
5209 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
5210 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
5211 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
5212 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
5213 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
5214 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
5215 | } |
5216 | } | |
5217 | ||
5218 | #undef _FW_WM | |
5219 | #undef _FW_WM_VLV | |
5220 | ||
04548cba VS |
5221 | void g4x_wm_get_hw_state(struct drm_device *dev) |
5222 | { | |
5223 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5224 | struct g4x_wm_values *wm = &dev_priv->wm.g4x; | |
5225 | struct intel_crtc *crtc; | |
5226 | ||
5227 | g4x_read_wm_values(dev_priv, wm); | |
5228 | ||
5229 | wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; | |
5230 | ||
5231 | for_each_intel_crtc(dev, crtc) { | |
5232 | struct intel_crtc_state *crtc_state = | |
5233 | to_intel_crtc_state(crtc->base.state); | |
5234 | struct g4x_wm_state *active = &crtc->wm.active.g4x; | |
5235 | struct g4x_pipe_wm *raw; | |
5236 | enum pipe pipe = crtc->pipe; | |
5237 | enum plane_id plane_id; | |
5238 | int level, max_level; | |
5239 | ||
5240 | active->cxsr = wm->cxsr; | |
5241 | active->hpll_en = wm->hpll_en; | |
5242 | active->fbc_en = wm->fbc_en; | |
5243 | ||
5244 | active->sr = wm->sr; | |
5245 | active->hpll = wm->hpll; | |
5246 | ||
5247 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
5248 | active->wm.plane[plane_id] = | |
5249 | wm->pipe[pipe].plane[plane_id]; | |
5250 | } | |
5251 | ||
5252 | if (wm->cxsr && wm->hpll_en) | |
5253 | max_level = G4X_WM_LEVEL_HPLL; | |
5254 | else if (wm->cxsr) | |
5255 | max_level = G4X_WM_LEVEL_SR; | |
5256 | else | |
5257 | max_level = G4X_WM_LEVEL_NORMAL; | |
5258 | ||
5259 | level = G4X_WM_LEVEL_NORMAL; | |
5260 | raw = &crtc_state->wm.g4x.raw[level]; | |
5261 | for_each_plane_id_on_crtc(crtc, plane_id) | |
5262 | raw->plane[plane_id] = active->wm.plane[plane_id]; | |
5263 | ||
5264 | if (++level > max_level) | |
5265 | goto out; | |
5266 | ||
5267 | raw = &crtc_state->wm.g4x.raw[level]; | |
5268 | raw->plane[PLANE_PRIMARY] = active->sr.plane; | |
5269 | raw->plane[PLANE_CURSOR] = active->sr.cursor; | |
5270 | raw->plane[PLANE_SPRITE0] = 0; | |
5271 | raw->fbc = active->sr.fbc; | |
5272 | ||
5273 | if (++level > max_level) | |
5274 | goto out; | |
5275 | ||
5276 | raw = &crtc_state->wm.g4x.raw[level]; | |
5277 | raw->plane[PLANE_PRIMARY] = active->hpll.plane; | |
5278 | raw->plane[PLANE_CURSOR] = active->hpll.cursor; | |
5279 | raw->plane[PLANE_SPRITE0] = 0; | |
5280 | raw->fbc = active->hpll.fbc; | |
5281 | ||
5282 | out: | |
5283 | for_each_plane_id_on_crtc(crtc, plane_id) | |
5284 | g4x_raw_plane_wm_set(crtc_state, level, | |
5285 | plane_id, USHRT_MAX); | |
5286 | g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); | |
5287 | ||
5288 | crtc_state->wm.g4x.optimal = *active; | |
5289 | crtc_state->wm.g4x.intermediate = *active; | |
5290 | ||
5291 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n", | |
5292 | pipe_name(pipe), | |
5293 | wm->pipe[pipe].plane[PLANE_PRIMARY], | |
5294 | wm->pipe[pipe].plane[PLANE_CURSOR], | |
5295 | wm->pipe[pipe].plane[PLANE_SPRITE0]); | |
5296 | } | |
5297 | ||
5298 | DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n", | |
5299 | wm->sr.plane, wm->sr.cursor, wm->sr.fbc); | |
5300 | DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n", | |
5301 | wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc); | |
5302 | DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n", | |
5303 | yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en)); | |
5304 | } | |
5305 | ||
5306 | void g4x_wm_sanitize(struct drm_i915_private *dev_priv) | |
5307 | { | |
5308 | struct intel_plane *plane; | |
5309 | struct intel_crtc *crtc; | |
5310 | ||
5311 | mutex_lock(&dev_priv->wm.wm_mutex); | |
5312 | ||
5313 | for_each_intel_plane(&dev_priv->drm, plane) { | |
5314 | struct intel_crtc *crtc = | |
5315 | intel_get_crtc_for_pipe(dev_priv, plane->pipe); | |
5316 | struct intel_crtc_state *crtc_state = | |
5317 | to_intel_crtc_state(crtc->base.state); | |
5318 | struct intel_plane_state *plane_state = | |
5319 | to_intel_plane_state(plane->base.state); | |
5320 | struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; | |
5321 | enum plane_id plane_id = plane->id; | |
5322 | int level; | |
5323 | ||
5324 | if (plane_state->base.visible) | |
5325 | continue; | |
5326 | ||
5327 | for (level = 0; level < 3; level++) { | |
5328 | struct g4x_pipe_wm *raw = | |
5329 | &crtc_state->wm.g4x.raw[level]; | |
5330 | ||
5331 | raw->plane[plane_id] = 0; | |
5332 | wm_state->wm.plane[plane_id] = 0; | |
5333 | } | |
5334 | ||
5335 | if (plane_id == PLANE_PRIMARY) { | |
5336 | for (level = 0; level < 3; level++) { | |
5337 | struct g4x_pipe_wm *raw = | |
5338 | &crtc_state->wm.g4x.raw[level]; | |
5339 | raw->fbc = 0; | |
5340 | } | |
5341 | ||
5342 | wm_state->sr.fbc = 0; | |
5343 | wm_state->hpll.fbc = 0; | |
5344 | wm_state->fbc_en = false; | |
5345 | } | |
5346 | } | |
5347 | ||
5348 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
5349 | struct intel_crtc_state *crtc_state = | |
5350 | to_intel_crtc_state(crtc->base.state); | |
5351 | ||
5352 | crtc_state->wm.g4x.intermediate = | |
5353 | crtc_state->wm.g4x.optimal; | |
5354 | crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; | |
5355 | } | |
5356 | ||
5357 | g4x_program_watermarks(dev_priv); | |
5358 | ||
5359 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
5360 | } | |
5361 | ||
6eb1a681 VS |
5362 | void vlv_wm_get_hw_state(struct drm_device *dev) |
5363 | { | |
5364 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5365 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; | |
f07d43d2 | 5366 | struct intel_crtc *crtc; |
6eb1a681 VS |
5367 | u32 val; |
5368 | ||
5369 | vlv_read_wm_values(dev_priv, wm); | |
5370 | ||
6eb1a681 VS |
5371 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
5372 | wm->level = VLV_WM_LEVEL_PM2; | |
5373 | ||
5374 | if (IS_CHERRYVIEW(dev_priv)) { | |
5375 | mutex_lock(&dev_priv->rps.hw_lock); | |
5376 | ||
5377 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5378 | if (val & DSP_MAXFIFO_PM5_ENABLE) | |
5379 | wm->level = VLV_WM_LEVEL_PM5; | |
5380 | ||
58590c14 VS |
5381 | /* |
5382 | * If DDR DVFS is disabled in the BIOS, Punit | |
5383 | * will never ack the request. So if that happens | |
5384 | * assume we don't have to enable/disable DDR DVFS | |
5385 | * dynamically. To test that just set the REQ_ACK | |
5386 | * bit to poke the Punit, but don't change the | |
5387 | * HIGH/LOW bits so that we don't actually change | |
5388 | * the current state. | |
5389 | */ | |
6eb1a681 | 5390 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
58590c14 VS |
5391 | val |= FORCE_DDR_FREQ_REQ_ACK; |
5392 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
5393 | ||
5394 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
5395 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { | |
5396 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " | |
5397 | "assuming DDR DVFS is disabled\n"); | |
5398 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; | |
5399 | } else { | |
5400 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
5401 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) | |
5402 | wm->level = VLV_WM_LEVEL_DDR_DVFS; | |
5403 | } | |
6eb1a681 VS |
5404 | |
5405 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5406 | } | |
5407 | ||
ff32c54e VS |
5408 | for_each_intel_crtc(dev, crtc) { |
5409 | struct intel_crtc_state *crtc_state = | |
5410 | to_intel_crtc_state(crtc->base.state); | |
5411 | struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
5412 | const struct vlv_fifo_state *fifo_state = | |
5413 | &crtc_state->wm.vlv.fifo_state; | |
5414 | enum pipe pipe = crtc->pipe; | |
5415 | enum plane_id plane_id; | |
5416 | int level; | |
5417 | ||
5418 | vlv_get_fifo_size(crtc_state); | |
5419 | ||
5420 | active->num_levels = wm->level + 1; | |
5421 | active->cxsr = wm->cxsr; | |
5422 | ||
ff32c54e | 5423 | for (level = 0; level < active->num_levels; level++) { |
114d7dc0 | 5424 | struct g4x_pipe_wm *raw = |
ff32c54e VS |
5425 | &crtc_state->wm.vlv.raw[level]; |
5426 | ||
5427 | active->sr[level].plane = wm->sr.plane; | |
5428 | active->sr[level].cursor = wm->sr.cursor; | |
5429 | ||
5430 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
5431 | active->wm[level].plane[plane_id] = | |
5432 | wm->pipe[pipe].plane[plane_id]; | |
5433 | ||
5434 | raw->plane[plane_id] = | |
5435 | vlv_invert_wm_value(active->wm[level].plane[plane_id], | |
5436 | fifo_state->plane[plane_id]); | |
5437 | } | |
5438 | } | |
5439 | ||
5440 | for_each_plane_id_on_crtc(crtc, plane_id) | |
5441 | vlv_raw_plane_wm_set(crtc_state, level, | |
5442 | plane_id, USHRT_MAX); | |
5443 | vlv_invalidate_wms(crtc, active, level); | |
5444 | ||
5445 | crtc_state->wm.vlv.optimal = *active; | |
4841da51 | 5446 | crtc_state->wm.vlv.intermediate = *active; |
ff32c54e | 5447 | |
6eb1a681 | 5448 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", |
1b31389c VS |
5449 | pipe_name(pipe), |
5450 | wm->pipe[pipe].plane[PLANE_PRIMARY], | |
5451 | wm->pipe[pipe].plane[PLANE_CURSOR], | |
5452 | wm->pipe[pipe].plane[PLANE_SPRITE0], | |
5453 | wm->pipe[pipe].plane[PLANE_SPRITE1]); | |
ff32c54e | 5454 | } |
6eb1a681 VS |
5455 | |
5456 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", | |
5457 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); | |
5458 | } | |
5459 | ||
602ae835 VS |
5460 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv) |
5461 | { | |
5462 | struct intel_plane *plane; | |
5463 | struct intel_crtc *crtc; | |
5464 | ||
5465 | mutex_lock(&dev_priv->wm.wm_mutex); | |
5466 | ||
5467 | for_each_intel_plane(&dev_priv->drm, plane) { | |
5468 | struct intel_crtc *crtc = | |
5469 | intel_get_crtc_for_pipe(dev_priv, plane->pipe); | |
5470 | struct intel_crtc_state *crtc_state = | |
5471 | to_intel_crtc_state(crtc->base.state); | |
5472 | struct intel_plane_state *plane_state = | |
5473 | to_intel_plane_state(plane->base.state); | |
5474 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
5475 | const struct vlv_fifo_state *fifo_state = | |
5476 | &crtc_state->wm.vlv.fifo_state; | |
5477 | enum plane_id plane_id = plane->id; | |
5478 | int level; | |
5479 | ||
5480 | if (plane_state->base.visible) | |
5481 | continue; | |
5482 | ||
5483 | for (level = 0; level < wm_state->num_levels; level++) { | |
114d7dc0 | 5484 | struct g4x_pipe_wm *raw = |
602ae835 VS |
5485 | &crtc_state->wm.vlv.raw[level]; |
5486 | ||
5487 | raw->plane[plane_id] = 0; | |
5488 | ||
5489 | wm_state->wm[level].plane[plane_id] = | |
5490 | vlv_invert_wm_value(raw->plane[plane_id], | |
5491 | fifo_state->plane[plane_id]); | |
5492 | } | |
5493 | } | |
5494 | ||
5495 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
5496 | struct intel_crtc_state *crtc_state = | |
5497 | to_intel_crtc_state(crtc->base.state); | |
5498 | ||
5499 | crtc_state->wm.vlv.intermediate = | |
5500 | crtc_state->wm.vlv.optimal; | |
5501 | crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
5502 | } | |
5503 | ||
5504 | vlv_program_watermarks(dev_priv); | |
5505 | ||
5506 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
5507 | } | |
5508 | ||
243e6a44 VS |
5509 | void ilk_wm_get_hw_state(struct drm_device *dev) |
5510 | { | |
fac5e23e | 5511 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 5512 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
5513 | struct drm_crtc *crtc; |
5514 | ||
70e1e0ec | 5515 | for_each_crtc(dev, crtc) |
243e6a44 VS |
5516 | ilk_pipe_wm_get_hw_state(crtc); |
5517 | ||
5518 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
5519 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
5520 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
5521 | ||
5522 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
175fded1 | 5523 | if (INTEL_GEN(dev_priv) >= 7) { |
cfa7698b VS |
5524 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
5525 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
5526 | } | |
243e6a44 | 5527 | |
8652744b | 5528 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ac9545fd VS |
5529 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
5530 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
fd6b8f43 | 5531 | else if (IS_IVYBRIDGE(dev_priv)) |
ac9545fd VS |
5532 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
5533 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
5534 | |
5535 | hw->enable_fbc_wm = | |
5536 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
5537 | } | |
5538 | ||
b445e3b0 ED |
5539 | /** |
5540 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
5541 | * | |
5542 | * Calculate watermark values for the various WM regs based on current mode | |
5543 | * and plane configuration. | |
5544 | * | |
5545 | * There are several cases to deal with here: | |
5546 | * - normal (i.e. non-self-refresh) | |
5547 | * - self-refresh (SR) mode | |
5548 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
5549 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
5550 | * lines), so need to account for TLB latency | |
5551 | * | |
5552 | * The normal calculation is: | |
5553 | * watermark = dotclock * bytes per pixel * latency | |
5554 | * where latency is platform & configuration dependent (we assume pessimal | |
5555 | * values here). | |
5556 | * | |
5557 | * The SR calculation is: | |
5558 | * watermark = (trunc(latency/line time)+1) * surface width * | |
5559 | * bytes per pixel | |
5560 | * where | |
5561 | * line time = htotal / dotclock | |
5562 | * surface width = hdisplay for normal plane and 64 for cursor | |
5563 | * and latency is assumed to be high, as above. | |
5564 | * | |
5565 | * The final value programmed to the register should always be rounded up, | |
5566 | * and include an extra 2 entries to account for clock crossings. | |
5567 | * | |
5568 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
5569 | * to set the non-SR watermarks to 8. | |
5570 | */ | |
432081bc | 5571 | void intel_update_watermarks(struct intel_crtc *crtc) |
b445e3b0 | 5572 | { |
432081bc | 5573 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b445e3b0 ED |
5574 | |
5575 | if (dev_priv->display.update_wm) | |
46ba614c | 5576 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
5577 | } |
5578 | ||
e2828914 | 5579 | /* |
9270388e | 5580 | * Lock protecting IPS related data structures |
9270388e DV |
5581 | */ |
5582 | DEFINE_SPINLOCK(mchdev_lock); | |
5583 | ||
5584 | /* Global for IPS driver to get at the current i915 device. Protected by | |
5585 | * mchdev_lock. */ | |
5586 | static struct drm_i915_private *i915_mch_dev; | |
5587 | ||
91d14251 | 5588 | bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 5589 | { |
2b4e57bd ED |
5590 | u16 rgvswctl; |
5591 | ||
67520415 | 5592 | lockdep_assert_held(&mchdev_lock); |
9270388e | 5593 | |
2b4e57bd ED |
5594 | rgvswctl = I915_READ16(MEMSWCTL); |
5595 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5596 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5597 | return false; /* still busy with another command */ | |
5598 | } | |
5599 | ||
5600 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5601 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5602 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5603 | POSTING_READ16(MEMSWCTL); | |
5604 | ||
5605 | rgvswctl |= MEMCTL_CMD_STS; | |
5606 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5607 | ||
5608 | return true; | |
5609 | } | |
5610 | ||
91d14251 | 5611 | static void ironlake_enable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5612 | { |
84f1b20f | 5613 | u32 rgvmodectl; |
2b4e57bd ED |
5614 | u8 fmax, fmin, fstart, vstart; |
5615 | ||
9270388e DV |
5616 | spin_lock_irq(&mchdev_lock); |
5617 | ||
84f1b20f TU |
5618 | rgvmodectl = I915_READ(MEMMODECTL); |
5619 | ||
2b4e57bd ED |
5620 | /* Enable temp reporting */ |
5621 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
5622 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
5623 | ||
5624 | /* 100ms RC evaluation intervals */ | |
5625 | I915_WRITE(RCUPEI, 100000); | |
5626 | I915_WRITE(RCDNEI, 100000); | |
5627 | ||
5628 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
5629 | I915_WRITE(RCBMAXAVG, 90000); | |
5630 | I915_WRITE(RCBMINAVG, 80000); | |
5631 | ||
5632 | I915_WRITE(MEMIHYST, 1); | |
5633 | ||
5634 | /* Set up min, max, and cur for interrupt handling */ | |
5635 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
5636 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
5637 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
5638 | MEMMODE_FSTART_SHIFT; | |
5639 | ||
616847e7 | 5640 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
2b4e57bd ED |
5641 | PXVFREQ_PX_SHIFT; |
5642 | ||
20e4d407 DV |
5643 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
5644 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 5645 | |
20e4d407 DV |
5646 | dev_priv->ips.max_delay = fstart; |
5647 | dev_priv->ips.min_delay = fmin; | |
5648 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
5649 | |
5650 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
5651 | fmax, fmin, fstart); | |
5652 | ||
5653 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
5654 | ||
5655 | /* | |
5656 | * Interrupts will be enabled in ironlake_irq_postinstall | |
5657 | */ | |
5658 | ||
5659 | I915_WRITE(VIDSTART, vstart); | |
5660 | POSTING_READ(VIDSTART); | |
5661 | ||
5662 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5663 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5664 | ||
9270388e | 5665 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 5666 | DRM_ERROR("stuck trying to change perf mode\n"); |
dd92d8de | 5667 | mdelay(1); |
2b4e57bd | 5668 | |
91d14251 | 5669 | ironlake_set_drps(dev_priv, fstart); |
2b4e57bd | 5670 | |
7d81c3e0 VS |
5671 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
5672 | I915_READ(DDREC) + I915_READ(CSIEC); | |
20e4d407 | 5673 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
7d81c3e0 | 5674 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
5ed0bdf2 | 5675 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
5676 | |
5677 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
5678 | } |
5679 | ||
91d14251 | 5680 | static void ironlake_disable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5681 | { |
9270388e DV |
5682 | u16 rgvswctl; |
5683 | ||
5684 | spin_lock_irq(&mchdev_lock); | |
5685 | ||
5686 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
5687 | |
5688 | /* Ack interrupts, disable EFC interrupt */ | |
5689 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5690 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5691 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5692 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5693 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5694 | ||
5695 | /* Go back to the starting frequency */ | |
91d14251 | 5696 | ironlake_set_drps(dev_priv, dev_priv->ips.fstart); |
dd92d8de | 5697 | mdelay(1); |
2b4e57bd ED |
5698 | rgvswctl |= MEMCTL_CMD_STS; |
5699 | I915_WRITE(MEMSWCTL, rgvswctl); | |
dd92d8de | 5700 | mdelay(1); |
2b4e57bd | 5701 | |
9270388e | 5702 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
5703 | } |
5704 | ||
acbe9475 DV |
5705 | /* There's a funny hw issue where the hw returns all 0 when reading from |
5706 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
5707 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
5708 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
5709 | */ | |
74ef1173 | 5710 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 5711 | { |
7b9e0ae6 | 5712 | u32 limits; |
2b4e57bd | 5713 | |
20b46e59 DV |
5714 | /* Only set the down limit when we've reached the lowest level to avoid |
5715 | * getting more interrupts, otherwise leave this clear. This prevents a | |
5716 | * race in the hw when coming out of rc6: There's a tiny window where | |
5717 | * the hw runs at the minimal clock before selecting the desired | |
5718 | * frequency, if the down threshold expires in that window we will not | |
5719 | * receive a down interrupt. */ | |
2d1fe073 | 5720 | if (IS_GEN9(dev_priv)) { |
74ef1173 AG |
5721 | limits = (dev_priv->rps.max_freq_softlimit) << 23; |
5722 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5723 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; | |
5724 | } else { | |
5725 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
5726 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5727 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
5728 | } | |
20b46e59 DV |
5729 | |
5730 | return limits; | |
5731 | } | |
5732 | ||
dd75fdc8 CW |
5733 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
5734 | { | |
5735 | int new_power; | |
8a586437 AG |
5736 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
5737 | u32 ei_up = 0, ei_down = 0; | |
dd75fdc8 CW |
5738 | |
5739 | new_power = dev_priv->rps.power; | |
5740 | switch (dev_priv->rps.power) { | |
5741 | case LOW_POWER: | |
a72b5623 CW |
5742 | if (val > dev_priv->rps.efficient_freq + 1 && |
5743 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5744 | new_power = BETWEEN; |
5745 | break; | |
5746 | ||
5747 | case BETWEEN: | |
a72b5623 CW |
5748 | if (val <= dev_priv->rps.efficient_freq && |
5749 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 | 5750 | new_power = LOW_POWER; |
a72b5623 CW |
5751 | else if (val >= dev_priv->rps.rp0_freq && |
5752 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5753 | new_power = HIGH_POWER; |
5754 | break; | |
5755 | ||
5756 | case HIGH_POWER: | |
a72b5623 CW |
5757 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && |
5758 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5759 | new_power = BETWEEN; |
5760 | break; | |
5761 | } | |
5762 | /* Max/min bins are special */ | |
aed242ff | 5763 | if (val <= dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 5764 | new_power = LOW_POWER; |
aed242ff | 5765 | if (val >= dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
5766 | new_power = HIGH_POWER; |
5767 | if (new_power == dev_priv->rps.power) | |
5768 | return; | |
5769 | ||
5770 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
5771 | switch (new_power) { | |
5772 | case LOW_POWER: | |
5773 | /* Upclock if more than 95% busy over 16ms */ | |
8a586437 AG |
5774 | ei_up = 16000; |
5775 | threshold_up = 95; | |
dd75fdc8 CW |
5776 | |
5777 | /* Downclock if less than 85% busy over 32ms */ | |
8a586437 AG |
5778 | ei_down = 32000; |
5779 | threshold_down = 85; | |
dd75fdc8 CW |
5780 | break; |
5781 | ||
5782 | case BETWEEN: | |
5783 | /* Upclock if more than 90% busy over 13ms */ | |
8a586437 AG |
5784 | ei_up = 13000; |
5785 | threshold_up = 90; | |
dd75fdc8 CW |
5786 | |
5787 | /* Downclock if less than 75% busy over 32ms */ | |
8a586437 AG |
5788 | ei_down = 32000; |
5789 | threshold_down = 75; | |
dd75fdc8 CW |
5790 | break; |
5791 | ||
5792 | case HIGH_POWER: | |
5793 | /* Upclock if more than 85% busy over 10ms */ | |
8a586437 AG |
5794 | ei_up = 10000; |
5795 | threshold_up = 85; | |
dd75fdc8 CW |
5796 | |
5797 | /* Downclock if less than 60% busy over 32ms */ | |
8a586437 AG |
5798 | ei_down = 32000; |
5799 | threshold_down = 60; | |
dd75fdc8 CW |
5800 | break; |
5801 | } | |
5802 | ||
6067a27d MK |
5803 | /* When byt can survive without system hang with dynamic |
5804 | * sw freq adjustments, this restriction can be lifted. | |
5805 | */ | |
5806 | if (IS_VALLEYVIEW(dev_priv)) | |
5807 | goto skip_hw_write; | |
5808 | ||
8a586437 | 5809 | I915_WRITE(GEN6_RP_UP_EI, |
a72b5623 | 5810 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
8a586437 | 5811 | I915_WRITE(GEN6_RP_UP_THRESHOLD, |
a72b5623 CW |
5812 | GT_INTERVAL_FROM_US(dev_priv, |
5813 | ei_up * threshold_up / 100)); | |
8a586437 AG |
5814 | |
5815 | I915_WRITE(GEN6_RP_DOWN_EI, | |
a72b5623 | 5816 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); |
8a586437 | 5817 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, |
a72b5623 CW |
5818 | GT_INTERVAL_FROM_US(dev_priv, |
5819 | ei_down * threshold_down / 100)); | |
5820 | ||
5821 | I915_WRITE(GEN6_RP_CONTROL, | |
5822 | GEN6_RP_MEDIA_TURBO | | |
5823 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5824 | GEN6_RP_MEDIA_IS_GFX | | |
5825 | GEN6_RP_ENABLE | | |
5826 | GEN6_RP_UP_BUSY_AVG | | |
5827 | GEN6_RP_DOWN_IDLE_AVG); | |
8a586437 | 5828 | |
6067a27d | 5829 | skip_hw_write: |
dd75fdc8 | 5830 | dev_priv->rps.power = new_power; |
8fb55197 CW |
5831 | dev_priv->rps.up_threshold = threshold_up; |
5832 | dev_priv->rps.down_threshold = threshold_down; | |
dd75fdc8 CW |
5833 | dev_priv->rps.last_adj = 0; |
5834 | } | |
5835 | ||
2876ce73 CW |
5836 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
5837 | { | |
5838 | u32 mask = 0; | |
5839 | ||
e0e8c7cb | 5840 | /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ |
2876ce73 | 5841 | if (val > dev_priv->rps.min_freq_softlimit) |
e0e8c7cb | 5842 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
2876ce73 | 5843 | if (val < dev_priv->rps.max_freq_softlimit) |
6f4b12f8 | 5844 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
2876ce73 | 5845 | |
7b3c29f6 CW |
5846 | mask &= dev_priv->pm_rps_events; |
5847 | ||
59d02a1f | 5848 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
5849 | } |
5850 | ||
b8a5ff8d JM |
5851 | /* gen6_set_rps is called to update the frequency request, but should also be |
5852 | * called when the range (min_delay and max_delay) is modified so that we can | |
5853 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
9fcee2f7 | 5854 | static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) |
20b46e59 | 5855 | { |
eb64cad1 CW |
5856 | /* min/max delay may still have been modified so be sure to |
5857 | * write the limits value. | |
5858 | */ | |
5859 | if (val != dev_priv->rps.cur_freq) { | |
5860 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 5861 | |
dc97997a | 5862 | if (IS_GEN9(dev_priv)) |
5704195c AG |
5863 | I915_WRITE(GEN6_RPNSWREQ, |
5864 | GEN9_FREQUENCY(val)); | |
dc97997a | 5865 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
eb64cad1 CW |
5866 | I915_WRITE(GEN6_RPNSWREQ, |
5867 | HSW_FREQUENCY(val)); | |
5868 | else | |
5869 | I915_WRITE(GEN6_RPNSWREQ, | |
5870 | GEN6_FREQUENCY(val) | | |
5871 | GEN6_OFFSET(0) | | |
5872 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 5873 | } |
7b9e0ae6 | 5874 | |
7b9e0ae6 CW |
5875 | /* Make sure we continue to get interrupts |
5876 | * until we hit the minimum or maximum frequencies. | |
5877 | */ | |
74ef1173 | 5878 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
2876ce73 | 5879 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 5880 | |
b39fb297 | 5881 | dev_priv->rps.cur_freq = val; |
0f94592e | 5882 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
9fcee2f7 CW |
5883 | |
5884 | return 0; | |
2b4e57bd ED |
5885 | } |
5886 | ||
9fcee2f7 | 5887 | static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val) |
ffe02b40 | 5888 | { |
9fcee2f7 CW |
5889 | int err; |
5890 | ||
dc97997a | 5891 | if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1), |
ffe02b40 VS |
5892 | "Odd GPU freq value\n")) |
5893 | val &= ~1; | |
5894 | ||
cd25dd5b D |
5895 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
5896 | ||
8fb55197 | 5897 | if (val != dev_priv->rps.cur_freq) { |
9fcee2f7 CW |
5898 | err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
5899 | if (err) | |
5900 | return err; | |
5901 | ||
db4c5e0b | 5902 | gen6_set_rps_thresholds(dev_priv, val); |
8fb55197 | 5903 | } |
ffe02b40 | 5904 | |
ffe02b40 VS |
5905 | dev_priv->rps.cur_freq = val; |
5906 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
9fcee2f7 CW |
5907 | |
5908 | return 0; | |
ffe02b40 VS |
5909 | } |
5910 | ||
a7f6e231 | 5911 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
76c3552f D |
5912 | * |
5913 | * * If Gfx is Idle, then | |
a7f6e231 D |
5914 | * 1. Forcewake Media well. |
5915 | * 2. Request idle freq. | |
5916 | * 3. Release Forcewake of Media well. | |
76c3552f D |
5917 | */ |
5918 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
5919 | { | |
aed242ff | 5920 | u32 val = dev_priv->rps.idle_freq; |
9fcee2f7 | 5921 | int err; |
5549d25f | 5922 | |
aed242ff | 5923 | if (dev_priv->rps.cur_freq <= val) |
76c3552f D |
5924 | return; |
5925 | ||
c9efef7b CW |
5926 | /* The punit delays the write of the frequency and voltage until it |
5927 | * determines the GPU is awake. During normal usage we don't want to | |
5928 | * waste power changing the frequency if the GPU is sleeping (rc6). | |
5929 | * However, the GPU and driver is now idle and we do not want to delay | |
5930 | * switching to minimum voltage (reducing power whilst idle) as we do | |
5931 | * not expect to be woken in the near future and so must flush the | |
5932 | * change by waking the device. | |
5933 | * | |
5934 | * We choose to take the media powerwell (either would do to trick the | |
5935 | * punit into committing the voltage change) as that takes a lot less | |
5936 | * power than the render powerwell. | |
5937 | */ | |
a7f6e231 | 5938 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 | 5939 | err = valleyview_set_rps(dev_priv, val); |
a7f6e231 | 5940 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 CW |
5941 | |
5942 | if (err) | |
5943 | DRM_ERROR("Failed to set RPS for idle\n"); | |
76c3552f D |
5944 | } |
5945 | ||
43cf3bf0 CW |
5946 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
5947 | { | |
5948 | mutex_lock(&dev_priv->rps.hw_lock); | |
5949 | if (dev_priv->rps.enabled) { | |
bd64818d CW |
5950 | u8 freq; |
5951 | ||
e0e8c7cb | 5952 | if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) |
43cf3bf0 CW |
5953 | gen6_rps_reset_ei(dev_priv); |
5954 | I915_WRITE(GEN6_PMINTRMSK, | |
5955 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
2b83c4c4 | 5956 | |
c33d247d CW |
5957 | gen6_enable_rps_interrupts(dev_priv); |
5958 | ||
bd64818d CW |
5959 | /* Use the user's desired frequency as a guide, but for better |
5960 | * performance, jump directly to RPe as our starting frequency. | |
5961 | */ | |
5962 | freq = max(dev_priv->rps.cur_freq, | |
5963 | dev_priv->rps.efficient_freq); | |
5964 | ||
9fcee2f7 | 5965 | if (intel_set_rps(dev_priv, |
bd64818d | 5966 | clamp(freq, |
9fcee2f7 CW |
5967 | dev_priv->rps.min_freq_softlimit, |
5968 | dev_priv->rps.max_freq_softlimit))) | |
5969 | DRM_DEBUG_DRIVER("Failed to set idle frequency\n"); | |
43cf3bf0 CW |
5970 | } |
5971 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5972 | } | |
5973 | ||
b29c19b6 CW |
5974 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
5975 | { | |
c33d247d CW |
5976 | /* Flush our bottom-half so that it does not race with us |
5977 | * setting the idle frequency and so that it is bounded by | |
5978 | * our rpm wakeref. And then disable the interrupts to stop any | |
5979 | * futher RPS reclocking whilst we are asleep. | |
5980 | */ | |
5981 | gen6_disable_rps_interrupts(dev_priv); | |
5982 | ||
b29c19b6 | 5983 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 5984 | if (dev_priv->rps.enabled) { |
dc97997a | 5985 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
76c3552f | 5986 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 5987 | else |
dc97997a | 5988 | gen6_set_rps(dev_priv, dev_priv->rps.idle_freq); |
c0951f0c | 5989 | dev_priv->rps.last_adj = 0; |
12c100bf VS |
5990 | I915_WRITE(GEN6_PMINTRMSK, |
5991 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); | |
c0951f0c | 5992 | } |
8d3afd7d | 5993 | mutex_unlock(&dev_priv->rps.hw_lock); |
1854d5ca | 5994 | |
8d3afd7d | 5995 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
5996 | while (!list_empty(&dev_priv->rps.clients)) |
5997 | list_del_init(dev_priv->rps.clients.next); | |
8d3afd7d | 5998 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
5999 | } |
6000 | ||
1854d5ca | 6001 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
6002 | struct intel_rps_client *rps, |
6003 | unsigned long submitted) | |
b29c19b6 | 6004 | { |
8d3afd7d CW |
6005 | /* This is intentionally racy! We peek at the state here, then |
6006 | * validate inside the RPS worker. | |
6007 | */ | |
67d97da3 | 6008 | if (!(dev_priv->gt.awake && |
8d3afd7d | 6009 | dev_priv->rps.enabled && |
29ecd78d | 6010 | dev_priv->rps.cur_freq < dev_priv->rps.boost_freq)) |
8d3afd7d | 6011 | return; |
43cf3bf0 | 6012 | |
e61b9958 CW |
6013 | /* Force a RPS boost (and don't count it against the client) if |
6014 | * the GPU is severely congested. | |
6015 | */ | |
d0bc54f2 | 6016 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
e61b9958 CW |
6017 | rps = NULL; |
6018 | ||
8d3afd7d CW |
6019 | spin_lock(&dev_priv->rps.client_lock); |
6020 | if (rps == NULL || list_empty(&rps->link)) { | |
6021 | spin_lock_irq(&dev_priv->irq_lock); | |
6022 | if (dev_priv->rps.interrupts_enabled) { | |
6023 | dev_priv->rps.client_boost = true; | |
c33d247d | 6024 | schedule_work(&dev_priv->rps.work); |
8d3afd7d CW |
6025 | } |
6026 | spin_unlock_irq(&dev_priv->irq_lock); | |
1854d5ca | 6027 | |
2e1b8730 CW |
6028 | if (rps != NULL) { |
6029 | list_add(&rps->link, &dev_priv->rps.clients); | |
6030 | rps->boosts++; | |
1854d5ca CW |
6031 | } else |
6032 | dev_priv->rps.boosts++; | |
c0951f0c | 6033 | } |
8d3afd7d | 6034 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
6035 | } |
6036 | ||
9fcee2f7 | 6037 | int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) |
0a073b84 | 6038 | { |
9fcee2f7 CW |
6039 | int err; |
6040 | ||
cfd1c488 CW |
6041 | lockdep_assert_held(&dev_priv->rps.hw_lock); |
6042 | GEM_BUG_ON(val > dev_priv->rps.max_freq); | |
6043 | GEM_BUG_ON(val < dev_priv->rps.min_freq); | |
6044 | ||
76e4e4b5 CW |
6045 | if (!dev_priv->rps.enabled) { |
6046 | dev_priv->rps.cur_freq = val; | |
6047 | return 0; | |
6048 | } | |
6049 | ||
dc97997a | 6050 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
9fcee2f7 | 6051 | err = valleyview_set_rps(dev_priv, val); |
ffe02b40 | 6052 | else |
9fcee2f7 CW |
6053 | err = gen6_set_rps(dev_priv, val); |
6054 | ||
6055 | return err; | |
0a073b84 JB |
6056 | } |
6057 | ||
dc97997a | 6058 | static void gen9_disable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 6059 | { |
20e49366 | 6060 | I915_WRITE(GEN6_RC_CONTROL, 0); |
38c23527 | 6061 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
6062 | } |
6063 | ||
dc97997a | 6064 | static void gen9_disable_rps(struct drm_i915_private *dev_priv) |
2030d684 | 6065 | { |
2030d684 AG |
6066 | I915_WRITE(GEN6_RP_CONTROL, 0); |
6067 | } | |
6068 | ||
dc97997a | 6069 | static void gen6_disable_rps(struct drm_i915_private *dev_priv) |
d20d4f0c | 6070 | { |
d20d4f0c | 6071 | I915_WRITE(GEN6_RC_CONTROL, 0); |
44fc7d5c | 6072 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2030d684 | 6073 | I915_WRITE(GEN6_RP_CONTROL, 0); |
44fc7d5c DV |
6074 | } |
6075 | ||
dc97997a | 6076 | static void cherryview_disable_rps(struct drm_i915_private *dev_priv) |
38807746 | 6077 | { |
38807746 D |
6078 | I915_WRITE(GEN6_RC_CONTROL, 0); |
6079 | } | |
6080 | ||
dc97997a | 6081 | static void valleyview_disable_rps(struct drm_i915_private *dev_priv) |
44fc7d5c | 6082 | { |
98a2e5f9 D |
6083 | /* we're doing forcewake before Disabling RC6, |
6084 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 6085 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 6086 | |
44fc7d5c | 6087 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 6088 | |
59bad947 | 6089 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
6090 | } |
6091 | ||
dc97997a | 6092 | static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) |
dc39fff7 | 6093 | { |
dc97997a | 6094 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
91ca689a ID |
6095 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
6096 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
6097 | else | |
6098 | mode = 0; | |
6099 | } | |
dc97997a | 6100 | if (HAS_RC6p(dev_priv)) |
b99d49cc ID |
6101 | DRM_DEBUG_DRIVER("Enabling RC6 states: " |
6102 | "RC6 %s RC6p %s RC6pp %s\n", | |
6103 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE), | |
6104 | onoff(mode & GEN6_RC_CTL_RC6p_ENABLE), | |
6105 | onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE)); | |
58abf1da RV |
6106 | |
6107 | else | |
b99d49cc ID |
6108 | DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n", |
6109 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE)); | |
dc39fff7 BW |
6110 | } |
6111 | ||
dc97997a | 6112 | static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) |
274008e8 | 6113 | { |
72e96d64 | 6114 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
274008e8 SAK |
6115 | bool enable_rc6 = true; |
6116 | unsigned long rc6_ctx_base; | |
fc619841 ID |
6117 | u32 rc_ctl; |
6118 | int rc_sw_target; | |
6119 | ||
6120 | rc_ctl = I915_READ(GEN6_RC_CONTROL); | |
6121 | rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >> | |
6122 | RC_SW_TARGET_STATE_SHIFT; | |
6123 | DRM_DEBUG_DRIVER("BIOS enabled RC states: " | |
6124 | "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", | |
6125 | onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE), | |
6126 | onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), | |
6127 | rc_sw_target); | |
274008e8 SAK |
6128 | |
6129 | if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { | |
b99d49cc | 6130 | DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n"); |
274008e8 SAK |
6131 | enable_rc6 = false; |
6132 | } | |
6133 | ||
6134 | /* | |
6135 | * The exact context size is not known for BXT, so assume a page size | |
6136 | * for this check. | |
6137 | */ | |
6138 | rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; | |
72e96d64 JL |
6139 | if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) && |
6140 | (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base + | |
6141 | ggtt->stolen_reserved_size))) { | |
b99d49cc | 6142 | DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n"); |
274008e8 SAK |
6143 | enable_rc6 = false; |
6144 | } | |
6145 | ||
6146 | if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && | |
6147 | ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && | |
6148 | ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && | |
6149 | ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { | |
b99d49cc | 6150 | DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n"); |
274008e8 SAK |
6151 | enable_rc6 = false; |
6152 | } | |
6153 | ||
fc619841 ID |
6154 | if (!I915_READ(GEN8_PUSHBUS_CONTROL) || |
6155 | !I915_READ(GEN8_PUSHBUS_ENABLE) || | |
6156 | !I915_READ(GEN8_PUSHBUS_SHIFT)) { | |
6157 | DRM_DEBUG_DRIVER("Pushbus not setup properly.\n"); | |
6158 | enable_rc6 = false; | |
6159 | } | |
6160 | ||
6161 | if (!I915_READ(GEN6_GFXPAUSE)) { | |
6162 | DRM_DEBUG_DRIVER("GFX pause not setup properly.\n"); | |
6163 | enable_rc6 = false; | |
6164 | } | |
6165 | ||
6166 | if (!I915_READ(GEN8_MISC_CTRL0)) { | |
6167 | DRM_DEBUG_DRIVER("GPM control not setup properly.\n"); | |
274008e8 SAK |
6168 | enable_rc6 = false; |
6169 | } | |
6170 | ||
6171 | return enable_rc6; | |
6172 | } | |
6173 | ||
dc97997a | 6174 | int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6) |
2b4e57bd | 6175 | { |
e7d66d89 | 6176 | /* No RC6 before Ironlake and code is gone for ilk. */ |
dc97997a | 6177 | if (INTEL_INFO(dev_priv)->gen < 6) |
e6069ca8 ID |
6178 | return 0; |
6179 | ||
274008e8 SAK |
6180 | if (!enable_rc6) |
6181 | return 0; | |
6182 | ||
cc3f90f0 | 6183 | if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) { |
274008e8 SAK |
6184 | DRM_INFO("RC6 disabled by BIOS\n"); |
6185 | return 0; | |
6186 | } | |
6187 | ||
456470eb | 6188 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
6189 | if (enable_rc6 >= 0) { |
6190 | int mask; | |
6191 | ||
dc97997a | 6192 | if (HAS_RC6p(dev_priv)) |
e6069ca8 ID |
6193 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
6194 | INTEL_RC6pp_ENABLE; | |
6195 | else | |
6196 | mask = INTEL_RC6_ENABLE; | |
6197 | ||
6198 | if ((enable_rc6 & mask) != enable_rc6) | |
b99d49cc ID |
6199 | DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d " |
6200 | "(requested %d, valid %d)\n", | |
6201 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
6202 | |
6203 | return enable_rc6 & mask; | |
6204 | } | |
2b4e57bd | 6205 | |
dc97997a | 6206 | if (IS_IVYBRIDGE(dev_priv)) |
cca84a1f | 6207 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
6208 | |
6209 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
6210 | } |
6211 | ||
dc97997a | 6212 | static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) |
3280e8b0 BW |
6213 | { |
6214 | /* All of these values are in units of 50MHz */ | |
773ea9a8 | 6215 | |
93ee2920 | 6216 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
cc3f90f0 | 6217 | if (IS_GEN9_LP(dev_priv)) { |
773ea9a8 | 6218 | u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
35040562 BP |
6219 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; |
6220 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
6221 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; | |
6222 | } else { | |
773ea9a8 | 6223 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
35040562 BP |
6224 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
6225 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
6226 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
6227 | } | |
3280e8b0 | 6228 | /* hw_max = RP0 until we check for overclocking */ |
773ea9a8 | 6229 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
3280e8b0 | 6230 | |
93ee2920 | 6231 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
dc97997a | 6232 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || |
b976dc53 | 6233 | IS_GEN9_BC(dev_priv)) { |
773ea9a8 CW |
6234 | u32 ddcc_status = 0; |
6235 | ||
6236 | if (sandybridge_pcode_read(dev_priv, | |
6237 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
6238 | &ddcc_status) == 0) | |
93ee2920 | 6239 | dev_priv->rps.efficient_freq = |
46efa4ab TR |
6240 | clamp_t(u8, |
6241 | ((ddcc_status >> 8) & 0xff), | |
6242 | dev_priv->rps.min_freq, | |
6243 | dev_priv->rps.max_freq); | |
93ee2920 TR |
6244 | } |
6245 | ||
b976dc53 | 6246 | if (IS_GEN9_BC(dev_priv)) { |
c5e0688c | 6247 | /* Store the frequency values in 16.66 MHZ units, which is |
773ea9a8 CW |
6248 | * the natural hardware unit for SKL |
6249 | */ | |
c5e0688c AG |
6250 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; |
6251 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; | |
6252 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; | |
6253 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; | |
6254 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; | |
6255 | } | |
3280e8b0 BW |
6256 | } |
6257 | ||
3a45b05c | 6258 | static void reset_rps(struct drm_i915_private *dev_priv, |
9fcee2f7 | 6259 | int (*set)(struct drm_i915_private *, u8)) |
3a45b05c CW |
6260 | { |
6261 | u8 freq = dev_priv->rps.cur_freq; | |
6262 | ||
6263 | /* force a reset */ | |
6264 | dev_priv->rps.power = -1; | |
6265 | dev_priv->rps.cur_freq = -1; | |
6266 | ||
9fcee2f7 CW |
6267 | if (set(dev_priv, freq)) |
6268 | DRM_ERROR("Failed to reset RPS to initial values\n"); | |
3a45b05c CW |
6269 | } |
6270 | ||
b6fef0ef | 6271 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
dc97997a | 6272 | static void gen9_enable_rps(struct drm_i915_private *dev_priv) |
b6fef0ef | 6273 | { |
b6fef0ef JB |
6274 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6275 | ||
0beb059a AG |
6276 | /* Program defaults and thresholds for RPS*/ |
6277 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
6278 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); | |
6279 | ||
6280 | /* 1 second timeout*/ | |
6281 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, | |
6282 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); | |
6283 | ||
b6fef0ef | 6284 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
b6fef0ef | 6285 | |
0beb059a AG |
6286 | /* Leaning on the below call to gen6_set_rps to program/setup the |
6287 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, | |
6288 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ | |
3a45b05c | 6289 | reset_rps(dev_priv, gen6_set_rps); |
b6fef0ef JB |
6290 | |
6291 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
6292 | } | |
6293 | ||
dc97997a | 6294 | static void gen9_enable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 6295 | { |
e2f80391 | 6296 | struct intel_engine_cs *engine; |
3b3f1650 | 6297 | enum intel_engine_id id; |
20e49366 | 6298 | uint32_t rc6_mask = 0; |
20e49366 ZW |
6299 | |
6300 | /* 1a: Software RC state - RC0 */ | |
6301 | I915_WRITE(GEN6_RC_STATE, 0); | |
6302 | ||
6303 | /* 1b: Get forcewake during program sequence. Although the driver | |
6304 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 6305 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
6306 | |
6307 | /* 2a: Disable RC states. */ | |
6308 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6309 | ||
6310 | /* 2b: Program RC6 thresholds.*/ | |
63a4dec2 SAK |
6311 | |
6312 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ | |
dc97997a | 6313 | if (IS_SKYLAKE(dev_priv)) |
63a4dec2 SAK |
6314 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
6315 | else | |
6316 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
20e49366 ZW |
6317 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
6318 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 6319 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6320 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
97c322e7 | 6321 | |
1a3d1898 | 6322 | if (HAS_GUC(dev_priv)) |
97c322e7 SAK |
6323 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); |
6324 | ||
20e49366 | 6325 | I915_WRITE(GEN6_RC_SLEEP, 0); |
20e49366 | 6326 | |
38c23527 ZW |
6327 | /* 2c: Program Coarse Power Gating Policies. */ |
6328 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
6329 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
6330 | ||
20e49366 | 6331 | /* 3a: Enable RC6 */ |
dc97997a | 6332 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
20e49366 | 6333 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
87ad3212 | 6334 | DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); |
1c044f9b CW |
6335 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
6336 | I915_WRITE(GEN6_RC_CONTROL, | |
6337 | GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask); | |
20e49366 | 6338 | |
cb07bae0 SK |
6339 | /* |
6340 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. | |
f2d2fe95 | 6341 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
cb07bae0 | 6342 | */ |
dc97997a | 6343 | if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) |
f2d2fe95 SAK |
6344 | I915_WRITE(GEN9_PG_ENABLE, 0); |
6345 | else | |
6346 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
6347 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); | |
38c23527 | 6348 | |
59bad947 | 6349 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
6350 | } |
6351 | ||
dc97997a | 6352 | static void gen8_enable_rps(struct drm_i915_private *dev_priv) |
6edee7f3 | 6353 | { |
e2f80391 | 6354 | struct intel_engine_cs *engine; |
3b3f1650 | 6355 | enum intel_engine_id id; |
93ee2920 | 6356 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
6357 | |
6358 | /* 1a: Software RC state - RC0 */ | |
6359 | I915_WRITE(GEN6_RC_STATE, 0); | |
6360 | ||
6361 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
6362 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 6363 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
6364 | |
6365 | /* 2a: Disable RC states. */ | |
6366 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6367 | ||
6edee7f3 BW |
6368 | /* 2b: Program RC6 thresholds.*/ |
6369 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
6370 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
6371 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 6372 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6373 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
6edee7f3 | 6374 | I915_WRITE(GEN6_RC_SLEEP, 0); |
dc97997a | 6375 | if (IS_BROADWELL(dev_priv)) |
0d68b25e TR |
6376 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
6377 | else | |
6378 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
6379 | |
6380 | /* 3: Enable RC6 */ | |
dc97997a | 6381 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6edee7f3 | 6382 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
dc97997a CW |
6383 | intel_print_rc6_info(dev_priv, rc6_mask); |
6384 | if (IS_BROADWELL(dev_priv)) | |
0d68b25e TR |
6385 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
6386 | GEN7_RC_CTL_TO_MODE | | |
6387 | rc6_mask); | |
6388 | else | |
6389 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
6390 | GEN6_RC_CTL_EI_MODE(1) | | |
6391 | rc6_mask); | |
6edee7f3 BW |
6392 | |
6393 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
6394 | I915_WRITE(GEN6_RPNSWREQ, |
6395 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
6396 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
6397 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
6398 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
6399 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
6400 | ||
6401 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
6402 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
6403 | dev_priv->rps.max_freq_softlimit << 24 | | |
6404 | dev_priv->rps.min_freq_softlimit << 16); | |
6405 | ||
6406 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
6407 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
6408 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
6409 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
6410 | ||
6411 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
6412 | |
6413 | /* 5: Enable RPS */ | |
7526ed79 DV |
6414 | I915_WRITE(GEN6_RP_CONTROL, |
6415 | GEN6_RP_MEDIA_TURBO | | |
6416 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
6417 | GEN6_RP_MEDIA_IS_GFX | | |
6418 | GEN6_RP_ENABLE | | |
6419 | GEN6_RP_UP_BUSY_AVG | | |
6420 | GEN6_RP_DOWN_IDLE_AVG); | |
6421 | ||
6422 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
6423 | ||
3a45b05c | 6424 | reset_rps(dev_priv, gen6_set_rps); |
7526ed79 | 6425 | |
59bad947 | 6426 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
6427 | } |
6428 | ||
dc97997a | 6429 | static void gen6_enable_rps(struct drm_i915_private *dev_priv) |
2b4e57bd | 6430 | { |
e2f80391 | 6431 | struct intel_engine_cs *engine; |
3b3f1650 | 6432 | enum intel_engine_id id; |
99ac9612 | 6433 | u32 rc6vids, rc6_mask = 0; |
2b4e57bd | 6434 | u32 gtfifodbg; |
2b4e57bd | 6435 | int rc6_mode; |
b4ac5afc | 6436 | int ret; |
2b4e57bd | 6437 | |
4fc688ce | 6438 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 6439 | |
2b4e57bd ED |
6440 | /* Here begins a magic sequence of register writes to enable |
6441 | * auto-downclocking. | |
6442 | * | |
6443 | * Perhaps there might be some value in exposing these to | |
6444 | * userspace... | |
6445 | */ | |
6446 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
6447 | |
6448 | /* Clear the DBG now so we don't confuse earlier errors */ | |
297b32ec VS |
6449 | gtfifodbg = I915_READ(GTFIFODBG); |
6450 | if (gtfifodbg) { | |
2b4e57bd ED |
6451 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
6452 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
6453 | } | |
6454 | ||
59bad947 | 6455 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
6456 | |
6457 | /* disable the counters and set deterministic thresholds */ | |
6458 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6459 | ||
6460 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
6461 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
6462 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
6463 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
6464 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
6465 | ||
3b3f1650 | 6466 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6467 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
2b4e57bd ED |
6468 | |
6469 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
6470 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
dc97997a | 6471 | if (IS_IVYBRIDGE(dev_priv)) |
351aa566 SM |
6472 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
6473 | else | |
6474 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 6475 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
6476 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
6477 | ||
5a7dc92a | 6478 | /* Check if we are enabling RC6 */ |
dc97997a | 6479 | rc6_mode = intel_enable_rc6(); |
2b4e57bd ED |
6480 | if (rc6_mode & INTEL_RC6_ENABLE) |
6481 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
6482 | ||
5a7dc92a | 6483 | /* We don't use those on Haswell */ |
dc97997a | 6484 | if (!IS_HASWELL(dev_priv)) { |
5a7dc92a ED |
6485 | if (rc6_mode & INTEL_RC6p_ENABLE) |
6486 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 6487 | |
5a7dc92a ED |
6488 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
6489 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
6490 | } | |
2b4e57bd | 6491 | |
dc97997a | 6492 | intel_print_rc6_info(dev_priv, rc6_mask); |
2b4e57bd ED |
6493 | |
6494 | I915_WRITE(GEN6_RC_CONTROL, | |
6495 | rc6_mask | | |
6496 | GEN6_RC_CTL_EI_MODE(1) | | |
6497 | GEN6_RC_CTL_HW_ENABLE); | |
6498 | ||
dd75fdc8 CW |
6499 | /* Power down if completely idle for over 50ms */ |
6500 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 6501 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 6502 | |
3a45b05c | 6503 | reset_rps(dev_priv, gen6_set_rps); |
2b4e57bd | 6504 | |
31643d54 BW |
6505 | rc6vids = 0; |
6506 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
dc97997a | 6507 | if (IS_GEN6(dev_priv) && ret) { |
31643d54 | 6508 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
dc97997a | 6509 | } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
31643d54 BW |
6510 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
6511 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
6512 | rc6vids &= 0xffff00; | |
6513 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
6514 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
6515 | if (ret) | |
6516 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
6517 | } | |
6518 | ||
59bad947 | 6519 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
6520 | } |
6521 | ||
fb7404e8 | 6522 | static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
2b4e57bd ED |
6523 | { |
6524 | int min_freq = 15; | |
3ebecd07 CW |
6525 | unsigned int gpu_freq; |
6526 | unsigned int max_ia_freq, min_ring_freq; | |
4c8c7743 | 6527 | unsigned int max_gpu_freq, min_gpu_freq; |
2b4e57bd | 6528 | int scaling_factor = 180; |
eda79642 | 6529 | struct cpufreq_policy *policy; |
2b4e57bd | 6530 | |
4fc688ce | 6531 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 6532 | |
eda79642 BW |
6533 | policy = cpufreq_cpu_get(0); |
6534 | if (policy) { | |
6535 | max_ia_freq = policy->cpuinfo.max_freq; | |
6536 | cpufreq_cpu_put(policy); | |
6537 | } else { | |
6538 | /* | |
6539 | * Default to measured freq if none found, PCU will ensure we | |
6540 | * don't go over | |
6541 | */ | |
2b4e57bd | 6542 | max_ia_freq = tsc_khz; |
eda79642 | 6543 | } |
2b4e57bd ED |
6544 | |
6545 | /* Convert from kHz to MHz */ | |
6546 | max_ia_freq /= 1000; | |
6547 | ||
153b4b95 | 6548 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
6549 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
6550 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 6551 | |
b976dc53 | 6552 | if (IS_GEN9_BC(dev_priv)) { |
4c8c7743 AG |
6553 | /* Convert GT frequency to 50 HZ units */ |
6554 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; | |
6555 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; | |
6556 | } else { | |
6557 | min_gpu_freq = dev_priv->rps.min_freq; | |
6558 | max_gpu_freq = dev_priv->rps.max_freq; | |
6559 | } | |
6560 | ||
2b4e57bd ED |
6561 | /* |
6562 | * For each potential GPU frequency, load a ring frequency we'd like | |
6563 | * to use for memory access. We do this by specifying the IA frequency | |
6564 | * the PCU should use as a reference to determine the ring frequency. | |
6565 | */ | |
4c8c7743 AG |
6566 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
6567 | int diff = max_gpu_freq - gpu_freq; | |
3ebecd07 CW |
6568 | unsigned int ia_freq = 0, ring_freq = 0; |
6569 | ||
b976dc53 | 6570 | if (IS_GEN9_BC(dev_priv)) { |
4c8c7743 AG |
6571 | /* |
6572 | * ring_freq = 2 * GT. ring_freq is in 100MHz units | |
6573 | * No floor required for ring frequency on SKL. | |
6574 | */ | |
6575 | ring_freq = gpu_freq; | |
dc97997a | 6576 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
46c764d4 BW |
6577 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
6578 | ring_freq = max(min_ring_freq, gpu_freq); | |
dc97997a | 6579 | } else if (IS_HASWELL(dev_priv)) { |
f6aca45c | 6580 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
6581 | ring_freq = max(min_ring_freq, ring_freq); |
6582 | /* leave ia_freq as the default, chosen by cpufreq */ | |
6583 | } else { | |
6584 | /* On older processors, there is no separate ring | |
6585 | * clock domain, so in order to boost the bandwidth | |
6586 | * of the ring, we need to upclock the CPU (ia_freq). | |
6587 | * | |
6588 | * For GPU frequencies less than 750MHz, | |
6589 | * just use the lowest ring freq. | |
6590 | */ | |
6591 | if (gpu_freq < min_freq) | |
6592 | ia_freq = 800; | |
6593 | else | |
6594 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
6595 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
6596 | } | |
2b4e57bd | 6597 | |
42c0526c BW |
6598 | sandybridge_pcode_write(dev_priv, |
6599 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
6600 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
6601 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
6602 | gpu_freq); | |
2b4e57bd | 6603 | } |
2b4e57bd ED |
6604 | } |
6605 | ||
03af2045 | 6606 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
6607 | { |
6608 | u32 val, rp0; | |
6609 | ||
5b5929cb | 6610 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
2b6b3a09 | 6611 | |
43b67998 | 6612 | switch (INTEL_INFO(dev_priv)->sseu.eu_total) { |
5b5929cb JN |
6613 | case 8: |
6614 | /* (2 * 4) config */ | |
6615 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
6616 | break; | |
6617 | case 12: | |
6618 | /* (2 * 6) config */ | |
6619 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
6620 | break; | |
6621 | case 16: | |
6622 | /* (2 * 8) config */ | |
6623 | default: | |
6624 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
6625 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
6626 | break; | |
095acd5f | 6627 | } |
5b5929cb JN |
6628 | |
6629 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
6630 | ||
2b6b3a09 D |
6631 | return rp0; |
6632 | } | |
6633 | ||
6634 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
6635 | { | |
6636 | u32 val, rpe; | |
6637 | ||
6638 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
6639 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
6640 | ||
6641 | return rpe; | |
6642 | } | |
6643 | ||
7707df4a D |
6644 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
6645 | { | |
6646 | u32 val, rp1; | |
6647 | ||
5b5929cb JN |
6648 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
6649 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
6650 | ||
7707df4a D |
6651 | return rp1; |
6652 | } | |
6653 | ||
96676fe3 D |
6654 | static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
6655 | { | |
6656 | u32 val, rpn; | |
6657 | ||
6658 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); | |
6659 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & | |
6660 | FB_GFX_FREQ_FUSE_MASK); | |
6661 | ||
6662 | return rpn; | |
6663 | } | |
6664 | ||
f8f2b001 D |
6665 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
6666 | { | |
6667 | u32 val, rp1; | |
6668 | ||
6669 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
6670 | ||
6671 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
6672 | ||
6673 | return rp1; | |
6674 | } | |
6675 | ||
03af2045 | 6676 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
6677 | { |
6678 | u32 val, rp0; | |
6679 | ||
64936258 | 6680 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
6681 | |
6682 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
6683 | /* Clamp to max */ | |
6684 | rp0 = min_t(u32, rp0, 0xea); | |
6685 | ||
6686 | return rp0; | |
6687 | } | |
6688 | ||
6689 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
6690 | { | |
6691 | u32 val, rpe; | |
6692 | ||
64936258 | 6693 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 6694 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 6695 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
6696 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
6697 | ||
6698 | return rpe; | |
6699 | } | |
6700 | ||
03af2045 | 6701 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 6702 | { |
36146035 ID |
6703 | u32 val; |
6704 | ||
6705 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; | |
6706 | /* | |
6707 | * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value | |
6708 | * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on | |
6709 | * a BYT-M B0 the above register contains 0xbf. Moreover when setting | |
6710 | * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 | |
6711 | * to make sure it matches what Punit accepts. | |
6712 | */ | |
6713 | return max_t(u32, val, 0xc0); | |
0a073b84 JB |
6714 | } |
6715 | ||
ae48434c ID |
6716 | /* Check that the pctx buffer wasn't move under us. */ |
6717 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
6718 | { | |
6719 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6720 | ||
6721 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
6722 | dev_priv->vlv_pctx->stolen->start); | |
6723 | } | |
6724 | ||
38807746 D |
6725 | |
6726 | /* Check that the pcbr address is not empty. */ | |
6727 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
6728 | { | |
6729 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6730 | ||
6731 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
6732 | } | |
6733 | ||
dc97997a | 6734 | static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) |
38807746 | 6735 | { |
62106b4f | 6736 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 6737 | unsigned long pctx_paddr, paddr; |
38807746 D |
6738 | u32 pcbr; |
6739 | int pctx_size = 32*1024; | |
6740 | ||
38807746 D |
6741 | pcbr = I915_READ(VLV_PCBR); |
6742 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 6743 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 | 6744 | paddr = (dev_priv->mm.stolen_base + |
62106b4f | 6745 | (ggtt->stolen_size - pctx_size)); |
38807746 D |
6746 | |
6747 | pctx_paddr = (paddr & (~4095)); | |
6748 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6749 | } | |
ce611ef8 VS |
6750 | |
6751 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
6752 | } |
6753 | ||
dc97997a | 6754 | static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) |
c9cddffc | 6755 | { |
c9cddffc JB |
6756 | struct drm_i915_gem_object *pctx; |
6757 | unsigned long pctx_paddr; | |
6758 | u32 pcbr; | |
6759 | int pctx_size = 24*1024; | |
6760 | ||
6761 | pcbr = I915_READ(VLV_PCBR); | |
6762 | if (pcbr) { | |
6763 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
6764 | int pcbr_offset; | |
6765 | ||
6766 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
187685cb | 6767 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
c9cddffc | 6768 | pcbr_offset, |
190d6cd5 | 6769 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
6770 | pctx_size); |
6771 | goto out; | |
6772 | } | |
6773 | ||
ce611ef8 VS |
6774 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
6775 | ||
c9cddffc JB |
6776 | /* |
6777 | * From the Gunit register HAS: | |
6778 | * The Gfx driver is expected to program this register and ensure | |
6779 | * proper allocation within Gfx stolen memory. For example, this | |
6780 | * register should be programmed such than the PCBR range does not | |
6781 | * overlap with other ranges, such as the frame buffer, protected | |
6782 | * memory, or any other relevant ranges. | |
6783 | */ | |
187685cb | 6784 | pctx = i915_gem_object_create_stolen(dev_priv, pctx_size); |
c9cddffc JB |
6785 | if (!pctx) { |
6786 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
ee504898 | 6787 | goto out; |
c9cddffc JB |
6788 | } |
6789 | ||
6790 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
6791 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6792 | ||
6793 | out: | |
ce611ef8 | 6794 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
6795 | dev_priv->vlv_pctx = pctx; |
6796 | } | |
6797 | ||
dc97997a | 6798 | static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv) |
ae48434c | 6799 | { |
ae48434c ID |
6800 | if (WARN_ON(!dev_priv->vlv_pctx)) |
6801 | return; | |
6802 | ||
f0cd5182 | 6803 | i915_gem_object_put(dev_priv->vlv_pctx); |
ae48434c ID |
6804 | dev_priv->vlv_pctx = NULL; |
6805 | } | |
6806 | ||
c30fec65 VS |
6807 | static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv) |
6808 | { | |
6809 | dev_priv->rps.gpll_ref_freq = | |
6810 | vlv_get_cck_clock(dev_priv, "GPLL ref", | |
6811 | CCK_GPLL_CLOCK_CONTROL, | |
6812 | dev_priv->czclk_freq); | |
6813 | ||
6814 | DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n", | |
6815 | dev_priv->rps.gpll_ref_freq); | |
6816 | } | |
6817 | ||
dc97997a | 6818 | static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 6819 | { |
2bb25c17 | 6820 | u32 val; |
4e80519e | 6821 | |
dc97997a | 6822 | valleyview_setup_pctx(dev_priv); |
4e80519e | 6823 | |
c30fec65 VS |
6824 | vlv_init_gpll_ref_freq(dev_priv); |
6825 | ||
2bb25c17 VS |
6826 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
6827 | switch ((val >> 6) & 3) { | |
6828 | case 0: | |
6829 | case 1: | |
6830 | dev_priv->mem_freq = 800; | |
6831 | break; | |
6832 | case 2: | |
6833 | dev_priv->mem_freq = 1066; | |
6834 | break; | |
6835 | case 3: | |
6836 | dev_priv->mem_freq = 1333; | |
6837 | break; | |
6838 | } | |
80b83b62 | 6839 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 6840 | |
4e80519e ID |
6841 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
6842 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
6843 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6844 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
6845 | dev_priv->rps.max_freq); |
6846 | ||
6847 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
6848 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6849 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
6850 | dev_priv->rps.efficient_freq); |
6851 | ||
f8f2b001 D |
6852 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
6853 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6854 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
6855 | dev_priv->rps.rp1_freq); |
6856 | ||
4e80519e ID |
6857 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
6858 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6859 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e | 6860 | dev_priv->rps.min_freq); |
4e80519e ID |
6861 | } |
6862 | ||
dc97997a | 6863 | static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) |
38807746 | 6864 | { |
2bb25c17 | 6865 | u32 val; |
2b6b3a09 | 6866 | |
dc97997a | 6867 | cherryview_setup_pctx(dev_priv); |
2b6b3a09 | 6868 | |
c30fec65 VS |
6869 | vlv_init_gpll_ref_freq(dev_priv); |
6870 | ||
a580516d | 6871 | mutex_lock(&dev_priv->sb_lock); |
c6e8f39d | 6872 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
a580516d | 6873 | mutex_unlock(&dev_priv->sb_lock); |
c6e8f39d | 6874 | |
2bb25c17 | 6875 | switch ((val >> 2) & 0x7) { |
2bb25c17 | 6876 | case 3: |
2bb25c17 VS |
6877 | dev_priv->mem_freq = 2000; |
6878 | break; | |
bfa7df01 | 6879 | default: |
2bb25c17 VS |
6880 | dev_priv->mem_freq = 1600; |
6881 | break; | |
6882 | } | |
80b83b62 | 6883 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 6884 | |
2b6b3a09 D |
6885 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
6886 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
6887 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6888 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
6889 | dev_priv->rps.max_freq); |
6890 | ||
6891 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
6892 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6893 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
6894 | dev_priv->rps.efficient_freq); |
6895 | ||
7707df4a D |
6896 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
6897 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6898 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
6899 | dev_priv->rps.rp1_freq); |
6900 | ||
96676fe3 | 6901 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
2b6b3a09 | 6902 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 6903 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
6904 | dev_priv->rps.min_freq); |
6905 | ||
1c14762d VS |
6906 | WARN_ONCE((dev_priv->rps.max_freq | |
6907 | dev_priv->rps.efficient_freq | | |
6908 | dev_priv->rps.rp1_freq | | |
6909 | dev_priv->rps.min_freq) & 1, | |
6910 | "Odd GPU freq values\n"); | |
38807746 D |
6911 | } |
6912 | ||
dc97997a | 6913 | static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 6914 | { |
dc97997a | 6915 | valleyview_cleanup_pctx(dev_priv); |
4e80519e ID |
6916 | } |
6917 | ||
dc97997a | 6918 | static void cherryview_enable_rps(struct drm_i915_private *dev_priv) |
38807746 | 6919 | { |
e2f80391 | 6920 | struct intel_engine_cs *engine; |
3b3f1650 | 6921 | enum intel_engine_id id; |
2b6b3a09 | 6922 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
6923 | |
6924 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
6925 | ||
297b32ec VS |
6926 | gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | |
6927 | GT_FIFO_FREE_ENTRIES_CHV); | |
38807746 D |
6928 | if (gtfifodbg) { |
6929 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
6930 | gtfifodbg); | |
6931 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
6932 | } | |
6933 | ||
6934 | cherryview_check_pctx(dev_priv); | |
6935 | ||
6936 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
6937 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 6938 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 6939 | |
160614a2 VS |
6940 | /* Disable RC states. */ |
6941 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6942 | ||
38807746 D |
6943 | /* 2a: Program RC6 thresholds.*/ |
6944 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
6945 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
6946 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
6947 | ||
3b3f1650 | 6948 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6949 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
38807746 D |
6950 | I915_WRITE(GEN6_RC_SLEEP, 0); |
6951 | ||
f4f71c7d D |
6952 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
6953 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); | |
38807746 D |
6954 | |
6955 | /* allows RC6 residency counter to work */ | |
6956 | I915_WRITE(VLV_COUNTER_CONTROL, | |
6957 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
6958 | VLV_MEDIA_RC6_COUNT_EN | | |
6959 | VLV_RENDER_RC6_COUNT_EN)); | |
6960 | ||
6961 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
6962 | pcbr = I915_READ(VLV_PCBR); | |
6963 | ||
38807746 | 6964 | /* 3: Enable RC6 */ |
dc97997a CW |
6965 | if ((intel_enable_rc6() & INTEL_RC6_ENABLE) && |
6966 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 6967 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
6968 | |
6969 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
6970 | ||
2b6b3a09 | 6971 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 6972 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
6973 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
6974 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
6975 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
6976 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
6977 | ||
6978 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6979 | ||
6980 | /* 5: Enable RPS */ | |
6981 | I915_WRITE(GEN6_RP_CONTROL, | |
6982 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 6983 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
6984 | GEN6_RP_ENABLE | |
6985 | GEN6_RP_UP_BUSY_AVG | | |
6986 | GEN6_RP_DOWN_IDLE_AVG); | |
6987 | ||
3ef62342 D |
6988 | /* Setting Fixed Bias */ |
6989 | val = VLV_OVERRIDE_EN | | |
6990 | VLV_SOC_TDP_EN | | |
6991 | CHV_BIAS_CPU_50_SOC_50; | |
6992 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
6993 | ||
2b6b3a09 D |
6994 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
6995 | ||
8d40c3ae VS |
6996 | /* RPS code assumes GPLL is used */ |
6997 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
6998 | ||
742f491d | 6999 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
2b6b3a09 D |
7000 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
7001 | ||
3a45b05c | 7002 | reset_rps(dev_priv, valleyview_set_rps); |
2b6b3a09 | 7003 | |
59bad947 | 7004 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
7005 | } |
7006 | ||
dc97997a | 7007 | static void valleyview_enable_rps(struct drm_i915_private *dev_priv) |
0a073b84 | 7008 | { |
e2f80391 | 7009 | struct intel_engine_cs *engine; |
3b3f1650 | 7010 | enum intel_engine_id id; |
2a5913a8 | 7011 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
7012 | |
7013 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
7014 | ||
ae48434c ID |
7015 | valleyview_check_pctx(dev_priv); |
7016 | ||
297b32ec VS |
7017 | gtfifodbg = I915_READ(GTFIFODBG); |
7018 | if (gtfifodbg) { | |
f7d85c1e JB |
7019 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
7020 | gtfifodbg); | |
0a073b84 JB |
7021 | I915_WRITE(GTFIFODBG, gtfifodbg); |
7022 | } | |
7023 | ||
c8d9a590 | 7024 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 7025 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 7026 | |
160614a2 VS |
7027 | /* Disable RC states. */ |
7028 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
7029 | ||
cad725fe | 7030 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
7031 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
7032 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
7033 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
7034 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
7035 | ||
7036 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
7037 | ||
7038 | I915_WRITE(GEN6_RP_CONTROL, | |
7039 | GEN6_RP_MEDIA_TURBO | | |
7040 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
7041 | GEN6_RP_MEDIA_IS_GFX | | |
7042 | GEN6_RP_ENABLE | | |
7043 | GEN6_RP_UP_BUSY_AVG | | |
7044 | GEN6_RP_DOWN_IDLE_CONT); | |
7045 | ||
7046 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
7047 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
7048 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
7049 | ||
3b3f1650 | 7050 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 7051 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
0a073b84 | 7052 | |
2f0aa304 | 7053 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
7054 | |
7055 | /* allows RC6 residency counter to work */ | |
49798eb2 | 7056 | I915_WRITE(VLV_COUNTER_CONTROL, |
6b7f6aa7 MK |
7057 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
7058 | VLV_MEDIA_RC0_COUNT_EN | | |
31685c25 | 7059 | VLV_RENDER_RC0_COUNT_EN | |
49798eb2 JB |
7060 | VLV_MEDIA_RC6_COUNT_EN | |
7061 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 7062 | |
dc97997a | 7063 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6b88f295 | 7064 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 | 7065 | |
dc97997a | 7066 | intel_print_rc6_info(dev_priv, rc6_mode); |
dc39fff7 | 7067 | |
a2b23fe0 | 7068 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 7069 | |
3ef62342 D |
7070 | /* Setting Fixed Bias */ |
7071 | val = VLV_OVERRIDE_EN | | |
7072 | VLV_SOC_TDP_EN | | |
7073 | VLV_BIAS_CPU_125_SOC_875; | |
7074 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
7075 | ||
64936258 | 7076 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 7077 | |
8d40c3ae VS |
7078 | /* RPS code assumes GPLL is used */ |
7079 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
7080 | ||
742f491d | 7081 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
0a073b84 JB |
7082 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
7083 | ||
3a45b05c | 7084 | reset_rps(dev_priv, valleyview_set_rps); |
0a073b84 | 7085 | |
59bad947 | 7086 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
7087 | } |
7088 | ||
dde18883 ED |
7089 | static unsigned long intel_pxfreq(u32 vidfreq) |
7090 | { | |
7091 | unsigned long freq; | |
7092 | int div = (vidfreq & 0x3f0000) >> 16; | |
7093 | int post = (vidfreq & 0x3000) >> 12; | |
7094 | int pre = (vidfreq & 0x7); | |
7095 | ||
7096 | if (!pre) | |
7097 | return 0; | |
7098 | ||
7099 | freq = ((div * 133333) / ((1<<post) * pre)); | |
7100 | ||
7101 | return freq; | |
7102 | } | |
7103 | ||
eb48eb00 DV |
7104 | static const struct cparams { |
7105 | u16 i; | |
7106 | u16 t; | |
7107 | u16 m; | |
7108 | u16 c; | |
7109 | } cparams[] = { | |
7110 | { 1, 1333, 301, 28664 }, | |
7111 | { 1, 1066, 294, 24460 }, | |
7112 | { 1, 800, 294, 25192 }, | |
7113 | { 0, 1333, 276, 27605 }, | |
7114 | { 0, 1066, 276, 27605 }, | |
7115 | { 0, 800, 231, 23784 }, | |
7116 | }; | |
7117 | ||
f531dcb2 | 7118 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
7119 | { |
7120 | u64 total_count, diff, ret; | |
7121 | u32 count1, count2, count3, m = 0, c = 0; | |
7122 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
7123 | int i; | |
7124 | ||
67520415 | 7125 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 7126 | |
20e4d407 | 7127 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
7128 | |
7129 | /* Prevent division-by-zero if we are asking too fast. | |
7130 | * Also, we don't get interesting results if we are polling | |
7131 | * faster than once in 10ms, so just return the saved value | |
7132 | * in such cases. | |
7133 | */ | |
7134 | if (diff1 <= 10) | |
20e4d407 | 7135 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
7136 | |
7137 | count1 = I915_READ(DMIEC); | |
7138 | count2 = I915_READ(DDREC); | |
7139 | count3 = I915_READ(CSIEC); | |
7140 | ||
7141 | total_count = count1 + count2 + count3; | |
7142 | ||
7143 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
7144 | if (total_count < dev_priv->ips.last_count1) { |
7145 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
7146 | diff += total_count; |
7147 | } else { | |
20e4d407 | 7148 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
7149 | } |
7150 | ||
7151 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
7152 | if (cparams[i].i == dev_priv->ips.c_m && |
7153 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
7154 | m = cparams[i].m; |
7155 | c = cparams[i].c; | |
7156 | break; | |
7157 | } | |
7158 | } | |
7159 | ||
7160 | diff = div_u64(diff, diff1); | |
7161 | ret = ((m * diff) + c); | |
7162 | ret = div_u64(ret, 10); | |
7163 | ||
20e4d407 DV |
7164 | dev_priv->ips.last_count1 = total_count; |
7165 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 7166 | |
20e4d407 | 7167 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
7168 | |
7169 | return ret; | |
7170 | } | |
7171 | ||
f531dcb2 CW |
7172 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
7173 | { | |
7174 | unsigned long val; | |
7175 | ||
dc97997a | 7176 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
7177 | return 0; |
7178 | ||
7179 | spin_lock_irq(&mchdev_lock); | |
7180 | ||
7181 | val = __i915_chipset_val(dev_priv); | |
7182 | ||
7183 | spin_unlock_irq(&mchdev_lock); | |
7184 | ||
7185 | return val; | |
7186 | } | |
7187 | ||
eb48eb00 DV |
7188 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
7189 | { | |
7190 | unsigned long m, x, b; | |
7191 | u32 tsfs; | |
7192 | ||
7193 | tsfs = I915_READ(TSFS); | |
7194 | ||
7195 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
7196 | x = I915_READ8(TR1); | |
7197 | ||
7198 | b = tsfs & TSFS_INTR_MASK; | |
7199 | ||
7200 | return ((m * x) / 127) - b; | |
7201 | } | |
7202 | ||
d972d6ee MK |
7203 | static int _pxvid_to_vd(u8 pxvid) |
7204 | { | |
7205 | if (pxvid == 0) | |
7206 | return 0; | |
7207 | ||
7208 | if (pxvid >= 8 && pxvid < 31) | |
7209 | pxvid = 31; | |
7210 | ||
7211 | return (pxvid + 2) * 125; | |
7212 | } | |
7213 | ||
7214 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 7215 | { |
d972d6ee MK |
7216 | const int vd = _pxvid_to_vd(pxvid); |
7217 | const int vm = vd - 1125; | |
7218 | ||
dc97997a | 7219 | if (INTEL_INFO(dev_priv)->is_mobile) |
d972d6ee MK |
7220 | return vm > 0 ? vm : 0; |
7221 | ||
7222 | return vd; | |
eb48eb00 DV |
7223 | } |
7224 | ||
02d71956 | 7225 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 7226 | { |
5ed0bdf2 | 7227 | u64 now, diff, diffms; |
eb48eb00 DV |
7228 | u32 count; |
7229 | ||
67520415 | 7230 | lockdep_assert_held(&mchdev_lock); |
eb48eb00 | 7231 | |
5ed0bdf2 TG |
7232 | now = ktime_get_raw_ns(); |
7233 | diffms = now - dev_priv->ips.last_time2; | |
7234 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
7235 | |
7236 | /* Don't divide by 0 */ | |
eb48eb00 DV |
7237 | if (!diffms) |
7238 | return; | |
7239 | ||
7240 | count = I915_READ(GFXEC); | |
7241 | ||
20e4d407 DV |
7242 | if (count < dev_priv->ips.last_count2) { |
7243 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
7244 | diff += count; |
7245 | } else { | |
20e4d407 | 7246 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
7247 | } |
7248 | ||
20e4d407 DV |
7249 | dev_priv->ips.last_count2 = count; |
7250 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
7251 | |
7252 | /* More magic constants... */ | |
7253 | diff = diff * 1181; | |
7254 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 7255 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
7256 | } |
7257 | ||
02d71956 DV |
7258 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
7259 | { | |
dc97997a | 7260 | if (INTEL_INFO(dev_priv)->gen != 5) |
02d71956 DV |
7261 | return; |
7262 | ||
9270388e | 7263 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
7264 | |
7265 | __i915_update_gfx_val(dev_priv); | |
7266 | ||
9270388e | 7267 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
7268 | } |
7269 | ||
f531dcb2 | 7270 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
7271 | { |
7272 | unsigned long t, corr, state1, corr2, state2; | |
7273 | u32 pxvid, ext_v; | |
7274 | ||
67520415 | 7275 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 7276 | |
616847e7 | 7277 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
eb48eb00 DV |
7278 | pxvid = (pxvid >> 24) & 0x7f; |
7279 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
7280 | ||
7281 | state1 = ext_v; | |
7282 | ||
7283 | t = i915_mch_val(dev_priv); | |
7284 | ||
7285 | /* Revel in the empirically derived constants */ | |
7286 | ||
7287 | /* Correction factor in 1/100000 units */ | |
7288 | if (t > 80) | |
7289 | corr = ((t * 2349) + 135940); | |
7290 | else if (t >= 50) | |
7291 | corr = ((t * 964) + 29317); | |
7292 | else /* < 50 */ | |
7293 | corr = ((t * 301) + 1004); | |
7294 | ||
7295 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
7296 | corr /= 100000; | |
20e4d407 | 7297 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
7298 | |
7299 | state2 = (corr2 * state1) / 10000; | |
7300 | state2 /= 100; /* convert to mW */ | |
7301 | ||
02d71956 | 7302 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 7303 | |
20e4d407 | 7304 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
7305 | } |
7306 | ||
f531dcb2 CW |
7307 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
7308 | { | |
7309 | unsigned long val; | |
7310 | ||
dc97997a | 7311 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
7312 | return 0; |
7313 | ||
7314 | spin_lock_irq(&mchdev_lock); | |
7315 | ||
7316 | val = __i915_gfx_val(dev_priv); | |
7317 | ||
7318 | spin_unlock_irq(&mchdev_lock); | |
7319 | ||
7320 | return val; | |
7321 | } | |
7322 | ||
eb48eb00 DV |
7323 | /** |
7324 | * i915_read_mch_val - return value for IPS use | |
7325 | * | |
7326 | * Calculate and return a value for the IPS driver to use when deciding whether | |
7327 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
7328 | */ | |
7329 | unsigned long i915_read_mch_val(void) | |
7330 | { | |
7331 | struct drm_i915_private *dev_priv; | |
7332 | unsigned long chipset_val, graphics_val, ret = 0; | |
7333 | ||
9270388e | 7334 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7335 | if (!i915_mch_dev) |
7336 | goto out_unlock; | |
7337 | dev_priv = i915_mch_dev; | |
7338 | ||
f531dcb2 CW |
7339 | chipset_val = __i915_chipset_val(dev_priv); |
7340 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
7341 | |
7342 | ret = chipset_val + graphics_val; | |
7343 | ||
7344 | out_unlock: | |
9270388e | 7345 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7346 | |
7347 | return ret; | |
7348 | } | |
7349 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
7350 | ||
7351 | /** | |
7352 | * i915_gpu_raise - raise GPU frequency limit | |
7353 | * | |
7354 | * Raise the limit; IPS indicates we have thermal headroom. | |
7355 | */ | |
7356 | bool i915_gpu_raise(void) | |
7357 | { | |
7358 | struct drm_i915_private *dev_priv; | |
7359 | bool ret = true; | |
7360 | ||
9270388e | 7361 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7362 | if (!i915_mch_dev) { |
7363 | ret = false; | |
7364 | goto out_unlock; | |
7365 | } | |
7366 | dev_priv = i915_mch_dev; | |
7367 | ||
20e4d407 DV |
7368 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
7369 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
7370 | |
7371 | out_unlock: | |
9270388e | 7372 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7373 | |
7374 | return ret; | |
7375 | } | |
7376 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
7377 | ||
7378 | /** | |
7379 | * i915_gpu_lower - lower GPU frequency limit | |
7380 | * | |
7381 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
7382 | * frequency maximum. | |
7383 | */ | |
7384 | bool i915_gpu_lower(void) | |
7385 | { | |
7386 | struct drm_i915_private *dev_priv; | |
7387 | bool ret = true; | |
7388 | ||
9270388e | 7389 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7390 | if (!i915_mch_dev) { |
7391 | ret = false; | |
7392 | goto out_unlock; | |
7393 | } | |
7394 | dev_priv = i915_mch_dev; | |
7395 | ||
20e4d407 DV |
7396 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
7397 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
7398 | |
7399 | out_unlock: | |
9270388e | 7400 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7401 | |
7402 | return ret; | |
7403 | } | |
7404 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
7405 | ||
7406 | /** | |
7407 | * i915_gpu_busy - indicate GPU business to IPS | |
7408 | * | |
7409 | * Tell the IPS driver whether or not the GPU is busy. | |
7410 | */ | |
7411 | bool i915_gpu_busy(void) | |
7412 | { | |
eb48eb00 DV |
7413 | bool ret = false; |
7414 | ||
9270388e | 7415 | spin_lock_irq(&mchdev_lock); |
dcff85c8 CW |
7416 | if (i915_mch_dev) |
7417 | ret = i915_mch_dev->gt.awake; | |
9270388e | 7418 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7419 | |
7420 | return ret; | |
7421 | } | |
7422 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
7423 | ||
7424 | /** | |
7425 | * i915_gpu_turbo_disable - disable graphics turbo | |
7426 | * | |
7427 | * Disable graphics turbo by resetting the max frequency and setting the | |
7428 | * current frequency to the default. | |
7429 | */ | |
7430 | bool i915_gpu_turbo_disable(void) | |
7431 | { | |
7432 | struct drm_i915_private *dev_priv; | |
7433 | bool ret = true; | |
7434 | ||
9270388e | 7435 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7436 | if (!i915_mch_dev) { |
7437 | ret = false; | |
7438 | goto out_unlock; | |
7439 | } | |
7440 | dev_priv = i915_mch_dev; | |
7441 | ||
20e4d407 | 7442 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 7443 | |
91d14251 | 7444 | if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart)) |
eb48eb00 DV |
7445 | ret = false; |
7446 | ||
7447 | out_unlock: | |
9270388e | 7448 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7449 | |
7450 | return ret; | |
7451 | } | |
7452 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
7453 | ||
7454 | /** | |
7455 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
7456 | * IPS got loaded first. | |
7457 | * | |
7458 | * This awkward dance is so that neither module has to depend on the | |
7459 | * other in order for IPS to do the appropriate communication of | |
7460 | * GPU turbo limits to i915. | |
7461 | */ | |
7462 | static void | |
7463 | ips_ping_for_i915_load(void) | |
7464 | { | |
7465 | void (*link)(void); | |
7466 | ||
7467 | link = symbol_get(ips_link_to_i915_driver); | |
7468 | if (link) { | |
7469 | link(); | |
7470 | symbol_put(ips_link_to_i915_driver); | |
7471 | } | |
7472 | } | |
7473 | ||
7474 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
7475 | { | |
02d71956 DV |
7476 | /* We only register the i915 ips part with intel-ips once everything is |
7477 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 7478 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 7479 | i915_mch_dev = dev_priv; |
9270388e | 7480 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7481 | |
7482 | ips_ping_for_i915_load(); | |
7483 | } | |
7484 | ||
7485 | void intel_gpu_ips_teardown(void) | |
7486 | { | |
9270388e | 7487 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 7488 | i915_mch_dev = NULL; |
9270388e | 7489 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 7490 | } |
76c3552f | 7491 | |
dc97997a | 7492 | static void intel_init_emon(struct drm_i915_private *dev_priv) |
dde18883 | 7493 | { |
dde18883 ED |
7494 | u32 lcfuse; |
7495 | u8 pxw[16]; | |
7496 | int i; | |
7497 | ||
7498 | /* Disable to program */ | |
7499 | I915_WRITE(ECR, 0); | |
7500 | POSTING_READ(ECR); | |
7501 | ||
7502 | /* Program energy weights for various events */ | |
7503 | I915_WRITE(SDEW, 0x15040d00); | |
7504 | I915_WRITE(CSIEW0, 0x007f0000); | |
7505 | I915_WRITE(CSIEW1, 0x1e220004); | |
7506 | I915_WRITE(CSIEW2, 0x04000004); | |
7507 | ||
7508 | for (i = 0; i < 5; i++) | |
616847e7 | 7509 | I915_WRITE(PEW(i), 0); |
dde18883 | 7510 | for (i = 0; i < 3; i++) |
616847e7 | 7511 | I915_WRITE(DEW(i), 0); |
dde18883 ED |
7512 | |
7513 | /* Program P-state weights to account for frequency power adjustment */ | |
7514 | for (i = 0; i < 16; i++) { | |
616847e7 | 7515 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
dde18883 ED |
7516 | unsigned long freq = intel_pxfreq(pxvidfreq); |
7517 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
7518 | PXVFREQ_PX_SHIFT; | |
7519 | unsigned long val; | |
7520 | ||
7521 | val = vid * vid; | |
7522 | val *= (freq / 1000); | |
7523 | val *= 255; | |
7524 | val /= (127*127*900); | |
7525 | if (val > 0xff) | |
7526 | DRM_ERROR("bad pxval: %ld\n", val); | |
7527 | pxw[i] = val; | |
7528 | } | |
7529 | /* Render standby states get 0 weight */ | |
7530 | pxw[14] = 0; | |
7531 | pxw[15] = 0; | |
7532 | ||
7533 | for (i = 0; i < 4; i++) { | |
7534 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
7535 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
616847e7 | 7536 | I915_WRITE(PXW(i), val); |
dde18883 ED |
7537 | } |
7538 | ||
7539 | /* Adjust magic regs to magic values (more experimental results) */ | |
7540 | I915_WRITE(OGW0, 0); | |
7541 | I915_WRITE(OGW1, 0); | |
7542 | I915_WRITE(EG0, 0x00007f00); | |
7543 | I915_WRITE(EG1, 0x0000000e); | |
7544 | I915_WRITE(EG2, 0x000e0000); | |
7545 | I915_WRITE(EG3, 0x68000300); | |
7546 | I915_WRITE(EG4, 0x42000000); | |
7547 | I915_WRITE(EG5, 0x00140031); | |
7548 | I915_WRITE(EG6, 0); | |
7549 | I915_WRITE(EG7, 0); | |
7550 | ||
7551 | for (i = 0; i < 8; i++) | |
616847e7 | 7552 | I915_WRITE(PXWL(i), 0); |
dde18883 ED |
7553 | |
7554 | /* Enable PMON + select events */ | |
7555 | I915_WRITE(ECR, 0x80000019); | |
7556 | ||
7557 | lcfuse = I915_READ(LCFUSE02); | |
7558 | ||
20e4d407 | 7559 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
7560 | } |
7561 | ||
dc97997a | 7562 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 7563 | { |
b268c699 ID |
7564 | /* |
7565 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
7566 | * requirement. | |
7567 | */ | |
7568 | if (!i915.enable_rc6) { | |
7569 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
7570 | intel_runtime_pm_get(dev_priv); | |
7571 | } | |
e6069ca8 | 7572 | |
b5163dbb | 7573 | mutex_lock(&dev_priv->drm.struct_mutex); |
773ea9a8 CW |
7574 | mutex_lock(&dev_priv->rps.hw_lock); |
7575 | ||
7576 | /* Initialize RPS limits (for userspace) */ | |
dc97997a CW |
7577 | if (IS_CHERRYVIEW(dev_priv)) |
7578 | cherryview_init_gt_powersave(dev_priv); | |
7579 | else if (IS_VALLEYVIEW(dev_priv)) | |
7580 | valleyview_init_gt_powersave(dev_priv); | |
2a13ae79 | 7581 | else if (INTEL_GEN(dev_priv) >= 6) |
773ea9a8 CW |
7582 | gen6_init_rps_frequencies(dev_priv); |
7583 | ||
7584 | /* Derive initial user preferences/limits from the hardware limits */ | |
7585 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; | |
7586 | dev_priv->rps.cur_freq = dev_priv->rps.idle_freq; | |
7587 | ||
7588 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
7589 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
7590 | ||
7591 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
7592 | dev_priv->rps.min_freq_softlimit = | |
7593 | max_t(int, | |
7594 | dev_priv->rps.efficient_freq, | |
7595 | intel_freq_opcode(dev_priv, 450)); | |
7596 | ||
99ac9612 CW |
7597 | /* After setting max-softlimit, find the overclock max freq */ |
7598 | if (IS_GEN6(dev_priv) || | |
7599 | IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { | |
7600 | u32 params = 0; | |
7601 | ||
7602 | sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms); | |
7603 | if (params & BIT(31)) { /* OC supported */ | |
7604 | DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n", | |
7605 | (dev_priv->rps.max_freq & 0xff) * 50, | |
7606 | (params & 0xff) * 50); | |
7607 | dev_priv->rps.max_freq = params & 0xff; | |
7608 | } | |
7609 | } | |
7610 | ||
29ecd78d CW |
7611 | /* Finally allow us to boost to max by default */ |
7612 | dev_priv->rps.boost_freq = dev_priv->rps.max_freq; | |
7613 | ||
773ea9a8 | 7614 | mutex_unlock(&dev_priv->rps.hw_lock); |
b5163dbb | 7615 | mutex_unlock(&dev_priv->drm.struct_mutex); |
54b4f68f CW |
7616 | |
7617 | intel_autoenable_gt_powersave(dev_priv); | |
ae48434c ID |
7618 | } |
7619 | ||
dc97997a | 7620 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 7621 | { |
8dac1e1f | 7622 | if (IS_VALLEYVIEW(dev_priv)) |
dc97997a | 7623 | valleyview_cleanup_gt_powersave(dev_priv); |
b268c699 ID |
7624 | |
7625 | if (!i915.enable_rc6) | |
7626 | intel_runtime_pm_put(dev_priv); | |
ae48434c ID |
7627 | } |
7628 | ||
54b4f68f CW |
7629 | /** |
7630 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
7631 | * @dev_priv: i915 device | |
7632 | * | |
7633 | * We don't want to disable RC6 or other features here, we just want | |
7634 | * to make sure any work we've queued has finished and won't bother | |
7635 | * us while we're suspended. | |
7636 | */ | |
7637 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) | |
7638 | { | |
7639 | if (INTEL_GEN(dev_priv) < 6) | |
7640 | return; | |
7641 | ||
7642 | if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) | |
7643 | intel_runtime_pm_put(dev_priv); | |
7644 | ||
7645 | /* gen6_rps_idle() will be called later to disable interrupts */ | |
7646 | } | |
7647 | ||
b7137e0c CW |
7648 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) |
7649 | { | |
7650 | dev_priv->rps.enabled = true; /* force disabling */ | |
7651 | intel_disable_gt_powersave(dev_priv); | |
54b4f68f CW |
7652 | |
7653 | gen6_reset_rps_interrupts(dev_priv); | |
156c7ca0 JB |
7654 | } |
7655 | ||
dc97997a | 7656 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) |
8090c6b9 | 7657 | { |
b7137e0c CW |
7658 | if (!READ_ONCE(dev_priv->rps.enabled)) |
7659 | return; | |
e494837a | 7660 | |
b7137e0c | 7661 | mutex_lock(&dev_priv->rps.hw_lock); |
e534770a | 7662 | |
b7137e0c CW |
7663 | if (INTEL_GEN(dev_priv) >= 9) { |
7664 | gen9_disable_rc6(dev_priv); | |
7665 | gen9_disable_rps(dev_priv); | |
7666 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
7667 | cherryview_disable_rps(dev_priv); | |
7668 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7669 | valleyview_disable_rps(dev_priv); | |
7670 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
7671 | gen6_disable_rps(dev_priv); | |
7672 | } else if (IS_IRONLAKE_M(dev_priv)) { | |
7673 | ironlake_disable_drps(dev_priv); | |
930ebb46 | 7674 | } |
b7137e0c CW |
7675 | |
7676 | dev_priv->rps.enabled = false; | |
7677 | mutex_unlock(&dev_priv->rps.hw_lock); | |
8090c6b9 DV |
7678 | } |
7679 | ||
b7137e0c | 7680 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) |
1a01ab3b | 7681 | { |
54b4f68f CW |
7682 | /* We shouldn't be disabling as we submit, so this should be less |
7683 | * racy than it appears! | |
7684 | */ | |
b7137e0c CW |
7685 | if (READ_ONCE(dev_priv->rps.enabled)) |
7686 | return; | |
1a01ab3b | 7687 | |
b7137e0c CW |
7688 | /* Powersaving is controlled by the host when inside a VM */ |
7689 | if (intel_vgpu_active(dev_priv)) | |
7690 | return; | |
0a073b84 | 7691 | |
b7137e0c | 7692 | mutex_lock(&dev_priv->rps.hw_lock); |
dc97997a CW |
7693 | |
7694 | if (IS_CHERRYVIEW(dev_priv)) { | |
7695 | cherryview_enable_rps(dev_priv); | |
7696 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7697 | valleyview_enable_rps(dev_priv); | |
b7137e0c | 7698 | } else if (INTEL_GEN(dev_priv) >= 9) { |
dc97997a CW |
7699 | gen9_enable_rc6(dev_priv); |
7700 | gen9_enable_rps(dev_priv); | |
b976dc53 | 7701 | if (IS_GEN9_BC(dev_priv)) |
fb7404e8 | 7702 | gen6_update_ring_freq(dev_priv); |
dc97997a CW |
7703 | } else if (IS_BROADWELL(dev_priv)) { |
7704 | gen8_enable_rps(dev_priv); | |
fb7404e8 | 7705 | gen6_update_ring_freq(dev_priv); |
b7137e0c | 7706 | } else if (INTEL_GEN(dev_priv) >= 6) { |
dc97997a | 7707 | gen6_enable_rps(dev_priv); |
fb7404e8 | 7708 | gen6_update_ring_freq(dev_priv); |
b7137e0c CW |
7709 | } else if (IS_IRONLAKE_M(dev_priv)) { |
7710 | ironlake_enable_drps(dev_priv); | |
7711 | intel_init_emon(dev_priv); | |
0a073b84 | 7712 | } |
aed242ff CW |
7713 | |
7714 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); | |
7715 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); | |
7716 | ||
7717 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); | |
7718 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); | |
7719 | ||
54b4f68f | 7720 | dev_priv->rps.enabled = true; |
b7137e0c CW |
7721 | mutex_unlock(&dev_priv->rps.hw_lock); |
7722 | } | |
3cc134e3 | 7723 | |
54b4f68f CW |
7724 | static void __intel_autoenable_gt_powersave(struct work_struct *work) |
7725 | { | |
7726 | struct drm_i915_private *dev_priv = | |
7727 | container_of(work, typeof(*dev_priv), rps.autoenable_work.work); | |
7728 | struct intel_engine_cs *rcs; | |
7729 | struct drm_i915_gem_request *req; | |
7730 | ||
7731 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7732 | goto out; | |
7733 | ||
3b3f1650 | 7734 | rcs = dev_priv->engine[RCS]; |
e8a9c58f | 7735 | if (rcs->last_retired_context) |
54b4f68f CW |
7736 | goto out; |
7737 | ||
7738 | if (!rcs->init_context) | |
7739 | goto out; | |
7740 | ||
7741 | mutex_lock(&dev_priv->drm.struct_mutex); | |
7742 | ||
7743 | req = i915_gem_request_alloc(rcs, dev_priv->kernel_context); | |
7744 | if (IS_ERR(req)) | |
7745 | goto unlock; | |
7746 | ||
7747 | if (!i915.enable_execlists && i915_switch_context(req) == 0) | |
7748 | rcs->init_context(req); | |
7749 | ||
7750 | /* Mark the device busy, calling intel_enable_gt_powersave() */ | |
e642c85b | 7751 | i915_add_request(req); |
54b4f68f CW |
7752 | |
7753 | unlock: | |
7754 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
7755 | out: | |
7756 | intel_runtime_pm_put(dev_priv); | |
7757 | } | |
7758 | ||
7759 | void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv) | |
7760 | { | |
7761 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7762 | return; | |
7763 | ||
7764 | if (IS_IRONLAKE_M(dev_priv)) { | |
7765 | ironlake_enable_drps(dev_priv); | |
54b4f68f | 7766 | intel_init_emon(dev_priv); |
54b4f68f CW |
7767 | } else if (INTEL_INFO(dev_priv)->gen >= 6) { |
7768 | /* | |
7769 | * PCU communication is slow and this doesn't need to be | |
7770 | * done at any specific time, so do this out of our fast path | |
7771 | * to make resume and init faster. | |
7772 | * | |
7773 | * We depend on the HW RC6 power context save/restore | |
7774 | * mechanism when entering D3 through runtime PM suspend. So | |
7775 | * disable RPM until RPS/RC6 is properly setup. We can only | |
7776 | * get here via the driver load/system resume/runtime resume | |
7777 | * paths, so the _noresume version is enough (and in case of | |
7778 | * runtime resume it's necessary). | |
7779 | */ | |
7780 | if (queue_delayed_work(dev_priv->wq, | |
7781 | &dev_priv->rps.autoenable_work, | |
7782 | round_jiffies_up_relative(HZ))) | |
7783 | intel_runtime_pm_get_noresume(dev_priv); | |
7784 | } | |
7785 | } | |
7786 | ||
46f16e63 | 7787 | static void ibx_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 7788 | { |
3107bd48 DV |
7789 | /* |
7790 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7791 | * gating for the panel power sequencer or it will fail to | |
7792 | * start up when no ports are active. | |
7793 | */ | |
7794 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
7795 | } | |
7796 | ||
46f16e63 | 7797 | static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) |
0e088b8f | 7798 | { |
b12ce1d8 | 7799 | enum pipe pipe; |
0e088b8f | 7800 | |
055e393f | 7801 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
7802 | I915_WRITE(DSPCNTR(pipe), |
7803 | I915_READ(DSPCNTR(pipe)) | | |
7804 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
b12ce1d8 VS |
7805 | |
7806 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); | |
7807 | POSTING_READ(DSPSURF(pipe)); | |
0e088b8f VS |
7808 | } |
7809 | } | |
7810 | ||
46f16e63 | 7811 | static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) |
017636cc | 7812 | { |
017636cc VS |
7813 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
7814 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
7815 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
7816 | ||
7817 | /* | |
7818 | * Don't touch WM1S_LP_EN here. | |
7819 | * Doing so could cause underruns. | |
7820 | */ | |
7821 | } | |
7822 | ||
46f16e63 | 7823 | static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7824 | { |
231e54f6 | 7825 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 7826 | |
f1e8fa56 DL |
7827 | /* |
7828 | * Required for FBC | |
7829 | * WaFbcDisableDpfcClockGating:ilk | |
7830 | */ | |
4d47e4f5 DL |
7831 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
7832 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
7833 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
7834 | |
7835 | I915_WRITE(PCH_3DCGDIS0, | |
7836 | MARIUNIT_CLOCK_GATE_DISABLE | | |
7837 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
7838 | I915_WRITE(PCH_3DCGDIS1, | |
7839 | VFMUNIT_CLOCK_GATE_DISABLE); | |
7840 | ||
6f1d69b0 ED |
7841 | /* |
7842 | * According to the spec the following bits should be set in | |
7843 | * order to enable memory self-refresh | |
7844 | * The bit 22/21 of 0x42004 | |
7845 | * The bit 5 of 0x42020 | |
7846 | * The bit 15 of 0x45000 | |
7847 | */ | |
7848 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7849 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7850 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 7851 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
7852 | I915_WRITE(DISP_ARB_CTL, |
7853 | (I915_READ(DISP_ARB_CTL) | | |
7854 | DISP_FBC_WM_DIS)); | |
017636cc | 7855 | |
46f16e63 | 7856 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 ED |
7857 | |
7858 | /* | |
7859 | * Based on the document from hardware guys the following bits | |
7860 | * should be set unconditionally in order to enable FBC. | |
7861 | * The bit 22 of 0x42000 | |
7862 | * The bit 22 of 0x42004 | |
7863 | * The bit 7,8,9 of 0x42020. | |
7864 | */ | |
50a0bc90 | 7865 | if (IS_IRONLAKE_M(dev_priv)) { |
4bb35334 | 7866 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
7867 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
7868 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7869 | ILK_FBCQ_DIS); | |
7870 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7871 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7872 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
7873 | } |
7874 | ||
4d47e4f5 DL |
7875 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
7876 | ||
6f1d69b0 ED |
7877 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
7878 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7879 | ILK_ELPIN_409_SELECT); | |
7880 | I915_WRITE(_3D_CHICKEN2, | |
7881 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
7882 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 7883 | |
ecdb4eb7 | 7884 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
7885 | I915_WRITE(CACHE_MODE_0, |
7886 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 7887 | |
4e04632e AG |
7888 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
7889 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7890 | ||
46f16e63 | 7891 | g4x_disable_trickle_feed(dev_priv); |
bdad2b2f | 7892 | |
46f16e63 | 7893 | ibx_init_clock_gating(dev_priv); |
3107bd48 DV |
7894 | } |
7895 | ||
46f16e63 | 7896 | static void cpt_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 7897 | { |
3107bd48 | 7898 | int pipe; |
3f704fa2 | 7899 | uint32_t val; |
3107bd48 DV |
7900 | |
7901 | /* | |
7902 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7903 | * gating for the panel power sequencer or it will fail to | |
7904 | * start up when no ports are active. | |
7905 | */ | |
cd664078 JB |
7906 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
7907 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
7908 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
7909 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
7910 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
7911 | /* The below fixes the weird display corruption, a few pixels shifted |
7912 | * downward, on (only) LVDS of some HP laptops with IVY. | |
7913 | */ | |
055e393f | 7914 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
7915 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
7916 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
7917 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 7918 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 7919 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
7920 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
7921 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
7922 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
7923 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
7924 | } | |
3107bd48 | 7925 | /* WADP0ClockGatingDisable */ |
055e393f | 7926 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
7927 | I915_WRITE(TRANS_CHICKEN1(pipe), |
7928 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
7929 | } | |
6f1d69b0 ED |
7930 | } |
7931 | ||
46f16e63 | 7932 | static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) |
1d7aaa0c | 7933 | { |
1d7aaa0c DV |
7934 | uint32_t tmp; |
7935 | ||
7936 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
7937 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
7938 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
7939 | tmp); | |
1d7aaa0c DV |
7940 | } |
7941 | ||
46f16e63 | 7942 | static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7943 | { |
231e54f6 | 7944 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 7945 | |
231e54f6 | 7946 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
7947 | |
7948 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7949 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7950 | ILK_ELPIN_409_SELECT); | |
7951 | ||
ecdb4eb7 | 7952 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
7953 | I915_WRITE(_3D_CHICKEN, |
7954 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
7955 | ||
4e04632e AG |
7956 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
7957 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7958 | ||
8d85d272 VS |
7959 | /* |
7960 | * BSpec recoomends 8x4 when MSAA is used, | |
7961 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
7962 | * |
7963 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7964 | * disable bit, which we don't touch here, but it's good | |
7965 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
7966 | */ |
7967 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 7968 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 7969 | |
46f16e63 | 7970 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 7971 | |
6f1d69b0 | 7972 | I915_WRITE(CACHE_MODE_0, |
50743298 | 7973 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
7974 | |
7975 | I915_WRITE(GEN6_UCGCTL1, | |
7976 | I915_READ(GEN6_UCGCTL1) | | |
7977 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
7978 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
7979 | ||
7980 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
7981 | * gating disable must be set. Failure to set it results in | |
7982 | * flickering pixels due to Z write ordering failures after | |
7983 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
7984 | * Sanctuary and Tropics, and apparently anything else with | |
7985 | * alpha test or pixel discard. | |
7986 | * | |
7987 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
7988 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 7989 | * |
ef59318c VS |
7990 | * WaDisableRCCUnitClockGating:snb |
7991 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
7992 | */ |
7993 | I915_WRITE(GEN6_UCGCTL2, | |
7994 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
7995 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
7996 | ||
5eb146dd | 7997 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
7998 | I915_WRITE(_3D_CHICKEN3, |
7999 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 8000 | |
e927ecde VS |
8001 | /* |
8002 | * Bspec says: | |
8003 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
8004 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
8005 | */ | |
8006 | I915_WRITE(_3D_CHICKEN3, | |
8007 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
8008 | ||
6f1d69b0 ED |
8009 | /* |
8010 | * According to the spec the following bits should be | |
8011 | * set in order to enable memory self-refresh and fbc: | |
8012 | * The bit21 and bit22 of 0x42000 | |
8013 | * The bit21 and bit22 of 0x42004 | |
8014 | * The bit5 and bit7 of 0x42020 | |
8015 | * The bit14 of 0x70180 | |
8016 | * The bit14 of 0x71180 | |
4bb35334 DL |
8017 | * |
8018 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
8019 | */ |
8020 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
8021 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8022 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8023 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8024 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8025 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
8026 | I915_WRITE(ILK_DSPCLK_GATE_D, |
8027 | I915_READ(ILK_DSPCLK_GATE_D) | | |
8028 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
8029 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 8030 | |
46f16e63 | 8031 | g4x_disable_trickle_feed(dev_priv); |
f8f2ac9a | 8032 | |
46f16e63 | 8033 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 8034 | |
46f16e63 | 8035 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
8036 | } |
8037 | ||
8038 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
8039 | { | |
8040 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
8041 | ||
3aad9059 | 8042 | /* |
46680e0a | 8043 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
8044 | * |
8045 | * This actually overrides the dispatch | |
8046 | * mode for all thread types. | |
8047 | */ | |
6f1d69b0 ED |
8048 | reg &= ~GEN7_FF_SCHED_MASK; |
8049 | reg |= GEN7_FF_TS_SCHED_HW; | |
8050 | reg |= GEN7_FF_VS_SCHED_HW; | |
8051 | reg |= GEN7_FF_DS_SCHED_HW; | |
8052 | ||
8053 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
8054 | } | |
8055 | ||
46f16e63 | 8056 | static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) |
17a303ec | 8057 | { |
17a303ec PZ |
8058 | /* |
8059 | * TODO: this bit should only be enabled when really needed, then | |
8060 | * disabled when not needed anymore in order to save power. | |
8061 | */ | |
4f8036a2 | 8062 | if (HAS_PCH_LPT_LP(dev_priv)) |
17a303ec PZ |
8063 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
8064 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
8065 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
8066 | |
8067 | /* WADPOClockGatingDisable:hsw */ | |
36c0d0cf VS |
8068 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
8069 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | | |
0a790cdb | 8070 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
17a303ec PZ |
8071 | } |
8072 | ||
712bf364 | 8073 | static void lpt_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 8074 | { |
4f8036a2 | 8075 | if (HAS_PCH_LPT_LP(dev_priv)) { |
7d708ee4 ID |
8076 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8077 | ||
8078 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8079 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8080 | } | |
8081 | } | |
8082 | ||
450174fe ID |
8083 | static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, |
8084 | int general_prio_credits, | |
8085 | int high_prio_credits) | |
8086 | { | |
8087 | u32 misccpctl; | |
8088 | ||
8089 | /* WaTempDisableDOPClkGating:bdw */ | |
8090 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
8091 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
8092 | ||
8093 | I915_WRITE(GEN8_L3SQCREG1, | |
8094 | L3_GENERAL_PRIO_CREDITS(general_prio_credits) | | |
8095 | L3_HIGH_PRIO_CREDITS(high_prio_credits)); | |
8096 | ||
8097 | /* | |
8098 | * Wait at least 100 clocks before re-enabling clock gating. | |
8099 | * See the definition of L3SQCREG1 in BSpec. | |
8100 | */ | |
8101 | POSTING_READ(GEN8_L3SQCREG1); | |
8102 | udelay(1); | |
8103 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
8104 | } | |
8105 | ||
46f16e63 | 8106 | static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) |
9498dba7 | 8107 | { |
46f16e63 | 8108 | gen9_init_clock_gating(dev_priv); |
9498dba7 MK |
8109 | |
8110 | /* WaDisableSDEUnitClockGating:kbl */ | |
8111 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
8112 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
8113 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
8aeb7f62 MK |
8114 | |
8115 | /* WaDisableGamClockGating:kbl */ | |
8116 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
8117 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
8118 | GEN6_GAMUNIT_CLOCK_GATE_DISABLE); | |
031cd8c8 MK |
8119 | |
8120 | /* WaFbcNukeOnHostModify:kbl */ | |
8121 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
8122 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
9498dba7 MK |
8123 | } |
8124 | ||
46f16e63 | 8125 | static void skylake_init_clock_gating(struct drm_i915_private *dev_priv) |
dc00b6a0 | 8126 | { |
46f16e63 | 8127 | gen9_init_clock_gating(dev_priv); |
44fff99f MK |
8128 | |
8129 | /* WAC6entrylatency:skl */ | |
8130 | I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | | |
8131 | FBC_LLC_FULLY_OPEN); | |
031cd8c8 MK |
8132 | |
8133 | /* WaFbcNukeOnHostModify:skl */ | |
8134 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
8135 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
dc00b6a0 DV |
8136 | } |
8137 | ||
46f16e63 | 8138 | static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) |
1020a5c2 | 8139 | { |
07d27e20 | 8140 | enum pipe pipe; |
1020a5c2 | 8141 | |
46f16e63 | 8142 | ilk_init_lp_watermarks(dev_priv); |
50ed5fbd | 8143 | |
ab57fff1 | 8144 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 8145 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 8146 | |
ab57fff1 | 8147 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
8148 | I915_WRITE(CHICKEN_PAR1_1, |
8149 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
8150 | ||
ab57fff1 | 8151 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 8152 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 8153 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 8154 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 8155 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 8156 | } |
63801f21 | 8157 | |
ab57fff1 BW |
8158 | /* WaVSRefCountFullforceMissDisable:bdw */ |
8159 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
8160 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
8161 | I915_READ(GEN7_FF_THREAD_MODE) & | |
8162 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 8163 | |
295e8bb7 VS |
8164 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
8165 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
8166 | |
8167 | /* WaDisableSDEUnitClockGating:bdw */ | |
8168 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
8169 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 8170 | |
450174fe ID |
8171 | /* WaProgramL3SqcReg1Default:bdw */ |
8172 | gen8_set_l3sqc_credits(dev_priv, 30, 2); | |
4d487cff | 8173 | |
6d50b065 VS |
8174 | /* |
8175 | * WaGttCachingOffByDefault:bdw | |
8176 | * GTT cache may not work with big pages, so if those | |
8177 | * are ever enabled GTT cache may need to be disabled. | |
8178 | */ | |
8179 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
8180 | ||
17e0adf0 MK |
8181 | /* WaKVMNotificationOnConfigChange:bdw */ |
8182 | I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) | |
8183 | | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); | |
8184 | ||
46f16e63 | 8185 | lpt_init_clock_gating(dev_priv); |
9cc19733 RB |
8186 | |
8187 | /* WaDisableDopClockGating:bdw | |
8188 | * | |
8189 | * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP | |
8190 | * clock gating. | |
8191 | */ | |
8192 | I915_WRITE(GEN6_UCGCTL1, | |
8193 | I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); | |
1020a5c2 BW |
8194 | } |
8195 | ||
46f16e63 | 8196 | static void haswell_init_clock_gating(struct drm_i915_private *dev_priv) |
cad2a2d7 | 8197 | { |
46f16e63 | 8198 | ilk_init_lp_watermarks(dev_priv); |
cad2a2d7 | 8199 | |
f3fc4884 FJ |
8200 | /* L3 caching of data atomics doesn't work -- disable it. */ |
8201 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
8202 | I915_WRITE(HSW_ROW_CHICKEN3, | |
8203 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
8204 | ||
ecdb4eb7 | 8205 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
8206 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
8207 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8208 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8209 | ||
e36ea7ff VS |
8210 | /* WaVSRefCountFullforceMissDisable:hsw */ |
8211 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
8212 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 8213 | |
4e04632e AG |
8214 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
8215 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8216 | ||
fe27c606 CW |
8217 | /* enable HiZ Raw Stall Optimization */ |
8218 | I915_WRITE(CACHE_MODE_0_GEN7, | |
8219 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
8220 | ||
ecdb4eb7 | 8221 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
8222 | I915_WRITE(CACHE_MODE_1, |
8223 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 8224 | |
a12c4967 VS |
8225 | /* |
8226 | * BSpec recommends 8x4 when MSAA is used, | |
8227 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
8228 | * |
8229 | * Note that PS/WM thread counts depend on the WIZ hashing | |
8230 | * disable bit, which we don't touch here, but it's good | |
8231 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
8232 | */ |
8233 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 8234 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 8235 | |
94411593 KG |
8236 | /* WaSampleCChickenBitEnable:hsw */ |
8237 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
8238 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
8239 | ||
ecdb4eb7 | 8240 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
8241 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
8242 | ||
90a88643 PZ |
8243 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
8244 | I915_WRITE(CHICKEN_PAR1_1, | |
8245 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 8246 | |
46f16e63 | 8247 | lpt_init_clock_gating(dev_priv); |
cad2a2d7 ED |
8248 | } |
8249 | ||
46f16e63 | 8250 | static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8251 | { |
20848223 | 8252 | uint32_t snpcr; |
6f1d69b0 | 8253 | |
46f16e63 | 8254 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 8255 | |
231e54f6 | 8256 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 8257 | |
ecdb4eb7 | 8258 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
8259 | I915_WRITE(_3D_CHICKEN3, |
8260 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
8261 | ||
ecdb4eb7 | 8262 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
8263 | I915_WRITE(IVB_CHICKEN3, |
8264 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8265 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8266 | ||
ecdb4eb7 | 8267 | /* WaDisablePSDDualDispatchEnable:ivb */ |
50a0bc90 | 8268 | if (IS_IVB_GT1(dev_priv)) |
12f3382b JB |
8269 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
8270 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 8271 | |
4e04632e AG |
8272 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
8273 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8274 | ||
ecdb4eb7 | 8275 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
8276 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
8277 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
8278 | ||
ecdb4eb7 | 8279 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
8280 | I915_WRITE(GEN7_L3CNTLREG1, |
8281 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
8282 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 | 8283 | GEN7_WA_L3_CHICKEN_MODE); |
50a0bc90 | 8284 | if (IS_IVB_GT1(dev_priv)) |
8ab43976 JB |
8285 | I915_WRITE(GEN7_ROW_CHICKEN2, |
8286 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
8287 | else { |
8288 | /* must write both registers */ | |
8289 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
8290 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
8291 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
8292 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 8293 | } |
6f1d69b0 | 8294 | |
ecdb4eb7 | 8295 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
8296 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
8297 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
8298 | ||
1b80a19a | 8299 | /* |
0f846f81 | 8300 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 8301 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
8302 | */ |
8303 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 8304 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 8305 | |
ecdb4eb7 | 8306 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
8307 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
8308 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8309 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8310 | ||
46f16e63 | 8311 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
8312 | |
8313 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 8314 | |
22721343 CW |
8315 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
8316 | /* enable HiZ Raw Stall Optimization */ | |
8317 | I915_WRITE(CACHE_MODE_0_GEN7, | |
8318 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
8319 | } | |
116f2b6d | 8320 | |
ecdb4eb7 | 8321 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
8322 | I915_WRITE(CACHE_MODE_1, |
8323 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 8324 | |
a607c1a4 VS |
8325 | /* |
8326 | * BSpec recommends 8x4 when MSAA is used, | |
8327 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
8328 | * |
8329 | * Note that PS/WM thread counts depend on the WIZ hashing | |
8330 | * disable bit, which we don't touch here, but it's good | |
8331 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
8332 | */ |
8333 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 8334 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 8335 | |
20848223 BW |
8336 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
8337 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
8338 | snpcr |= GEN6_MBC_SNPCR_MED; | |
8339 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 8340 | |
6e266956 | 8341 | if (!HAS_PCH_NOP(dev_priv)) |
46f16e63 | 8342 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 8343 | |
46f16e63 | 8344 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
8345 | } |
8346 | ||
46f16e63 | 8347 | static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8348 | { |
ecdb4eb7 | 8349 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
8350 | I915_WRITE(_3D_CHICKEN3, |
8351 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
8352 | ||
ecdb4eb7 | 8353 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
8354 | I915_WRITE(IVB_CHICKEN3, |
8355 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8356 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8357 | ||
fad7d36e | 8358 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 8359 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 8360 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
8361 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
8362 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 8363 | |
4e04632e AG |
8364 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
8365 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8366 | ||
ecdb4eb7 | 8367 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
8368 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
8369 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
8370 | ||
ecdb4eb7 | 8371 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
8372 | I915_WRITE(GEN7_ROW_CHICKEN2, |
8373 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8374 | ||
ecdb4eb7 | 8375 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
8376 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
8377 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8378 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8379 | ||
46680e0a VS |
8380 | gen7_setup_fixed_func_scheduler(dev_priv); |
8381 | ||
3c0edaeb | 8382 | /* |
0f846f81 | 8383 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 8384 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
8385 | */ |
8386 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 8387 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 8388 | |
c98f5062 AG |
8389 | /* WaDisableL3Bank2xClockGate:vlv |
8390 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
8391 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
8392 | I915_WRITE(GEN7_UCGCTL4, | |
8393 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 8394 | |
afd58e79 VS |
8395 | /* |
8396 | * BSpec says this must be set, even though | |
8397 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
8398 | */ | |
6b26c86d DV |
8399 | I915_WRITE(CACHE_MODE_1, |
8400 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 8401 | |
da2518f9 VS |
8402 | /* |
8403 | * BSpec recommends 8x4 when MSAA is used, | |
8404 | * however in practice 16x4 seems fastest. | |
8405 | * | |
8406 | * Note that PS/WM thread counts depend on the WIZ hashing | |
8407 | * disable bit, which we don't touch here, but it's good | |
8408 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8409 | */ | |
8410 | I915_WRITE(GEN7_GT_MODE, | |
8411 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
8412 | ||
031994ee VS |
8413 | /* |
8414 | * WaIncreaseL3CreditsForVLVB0:vlv | |
8415 | * This is the hardware default actually. | |
8416 | */ | |
8417 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
8418 | ||
2d809570 | 8419 | /* |
ecdb4eb7 | 8420 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
8421 | * Disable clock gating on th GCFG unit to prevent a delay |
8422 | * in the reporting of vblank events. | |
8423 | */ | |
7a0d1eed | 8424 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
8425 | } |
8426 | ||
46f16e63 | 8427 | static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) |
a4565da8 | 8428 | { |
232ce337 VS |
8429 | /* WaVSRefCountFullforceMissDisable:chv */ |
8430 | /* WaDSRefCountFullforceMissDisable:chv */ | |
8431 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
8432 | I915_READ(GEN7_FF_THREAD_MODE) & | |
8433 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
8434 | |
8435 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
8436 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
8437 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
8438 | |
8439 | /* WaDisableCSUnitClockGating:chv */ | |
8440 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
8441 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
8442 | |
8443 | /* WaDisableSDEUnitClockGating:chv */ | |
8444 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
8445 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6d50b065 | 8446 | |
450174fe ID |
8447 | /* |
8448 | * WaProgramL3SqcReg1Default:chv | |
8449 | * See gfxspecs/Related Documents/Performance Guide/ | |
8450 | * LSQC Setting Recommendations. | |
8451 | */ | |
8452 | gen8_set_l3sqc_credits(dev_priv, 38, 2); | |
8453 | ||
6d50b065 VS |
8454 | /* |
8455 | * GTT cache may not work with big pages, so if those | |
8456 | * are ever enabled GTT cache may need to be disabled. | |
8457 | */ | |
8458 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
a4565da8 VS |
8459 | } |
8460 | ||
46f16e63 | 8461 | static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8462 | { |
6f1d69b0 ED |
8463 | uint32_t dspclk_gate; |
8464 | ||
8465 | I915_WRITE(RENCLK_GATE_D1, 0); | |
8466 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
8467 | GS_UNIT_CLOCK_GATE_DISABLE | | |
8468 | CL_UNIT_CLOCK_GATE_DISABLE); | |
8469 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8470 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
8471 | OVRUNIT_CLOCK_GATE_DISABLE | | |
8472 | OVCUNIT_CLOCK_GATE_DISABLE; | |
50a0bc90 | 8473 | if (IS_GM45(dev_priv)) |
6f1d69b0 ED |
8474 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
8475 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
8476 | |
8477 | /* WaDisableRenderCachePipelinedFlush */ | |
8478 | I915_WRITE(CACHE_MODE_0, | |
8479 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 8480 | |
4e04632e AG |
8481 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
8482 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8483 | ||
46f16e63 | 8484 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
8485 | } |
8486 | ||
46f16e63 | 8487 | static void crestline_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8488 | { |
6f1d69b0 ED |
8489 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
8490 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8491 | I915_WRITE(DSPCLK_GATE_D, 0); | |
8492 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8493 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
8494 | I915_WRITE(MI_ARB_STATE, |
8495 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
8496 | |
8497 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
8498 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
8499 | } |
8500 | ||
46f16e63 | 8501 | static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8502 | { |
6f1d69b0 ED |
8503 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
8504 | I965_RCC_CLOCK_GATE_DISABLE | | |
8505 | I965_RCPB_CLOCK_GATE_DISABLE | | |
8506 | I965_ISC_CLOCK_GATE_DISABLE | | |
8507 | I965_FBC_CLOCK_GATE_DISABLE); | |
8508 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
8509 | I915_WRITE(MI_ARB_STATE, |
8510 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
8511 | |
8512 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
8513 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
8514 | } |
8515 | ||
46f16e63 | 8516 | static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8517 | { |
6f1d69b0 ED |
8518 | u32 dstate = I915_READ(D_STATE); |
8519 | ||
8520 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
8521 | DSTATE_DOT_CLOCK_GATING; | |
8522 | I915_WRITE(D_STATE, dstate); | |
13a86b85 | 8523 | |
9b1e14f4 | 8524 | if (IS_PINEVIEW(dev_priv)) |
13a86b85 | 8525 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
974a3b0f DV |
8526 | |
8527 | /* IIR "flip pending" means done if this bit is set */ | |
8528 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
8529 | |
8530 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 8531 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
8532 | |
8533 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
8534 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
8535 | |
8536 | I915_WRITE(MI_ARB_STATE, | |
8537 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
8538 | } |
8539 | ||
46f16e63 | 8540 | static void i85x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8541 | { |
6f1d69b0 | 8542 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
54e472ae VS |
8543 | |
8544 | /* interrupts should cause a wake up from C3 */ | |
8545 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
8546 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
8547 | |
8548 | I915_WRITE(MEM_MODE, | |
8549 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
8550 | } |
8551 | ||
46f16e63 | 8552 | static void i830_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8553 | { |
1038392b VS |
8554 | I915_WRITE(MEM_MODE, |
8555 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
8556 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
8557 | } |
8558 | ||
46f16e63 | 8559 | void intel_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8560 | { |
46f16e63 | 8561 | dev_priv->display.init_clock_gating(dev_priv); |
6f1d69b0 ED |
8562 | } |
8563 | ||
712bf364 | 8564 | void intel_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 8565 | { |
712bf364 VS |
8566 | if (HAS_PCH_LPT(dev_priv)) |
8567 | lpt_suspend_hw(dev_priv); | |
7d708ee4 ID |
8568 | } |
8569 | ||
46f16e63 | 8570 | static void nop_init_clock_gating(struct drm_i915_private *dev_priv) |
bb400da9 ID |
8571 | { |
8572 | DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n"); | |
8573 | } | |
8574 | ||
8575 | /** | |
8576 | * intel_init_clock_gating_hooks - setup the clock gating hooks | |
8577 | * @dev_priv: device private | |
8578 | * | |
8579 | * Setup the hooks that configure which clocks of a given platform can be | |
8580 | * gated and also apply various GT and display specific workarounds for these | |
8581 | * platforms. Note that some GT specific workarounds are applied separately | |
8582 | * when GPU contexts or batchbuffers start their execution. | |
8583 | */ | |
8584 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) | |
8585 | { | |
8586 | if (IS_SKYLAKE(dev_priv)) | |
dc00b6a0 | 8587 | dev_priv->display.init_clock_gating = skylake_init_clock_gating; |
bb400da9 | 8588 | else if (IS_KABYLAKE(dev_priv)) |
9498dba7 | 8589 | dev_priv->display.init_clock_gating = kabylake_init_clock_gating; |
9fb5026f | 8590 | else if (IS_BROXTON(dev_priv)) |
bb400da9 | 8591 | dev_priv->display.init_clock_gating = bxt_init_clock_gating; |
9fb5026f ACO |
8592 | else if (IS_GEMINILAKE(dev_priv)) |
8593 | dev_priv->display.init_clock_gating = glk_init_clock_gating; | |
bb400da9 ID |
8594 | else if (IS_BROADWELL(dev_priv)) |
8595 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; | |
8596 | else if (IS_CHERRYVIEW(dev_priv)) | |
8597 | dev_priv->display.init_clock_gating = cherryview_init_clock_gating; | |
8598 | else if (IS_HASWELL(dev_priv)) | |
8599 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; | |
8600 | else if (IS_IVYBRIDGE(dev_priv)) | |
8601 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; | |
8602 | else if (IS_VALLEYVIEW(dev_priv)) | |
8603 | dev_priv->display.init_clock_gating = valleyview_init_clock_gating; | |
8604 | else if (IS_GEN6(dev_priv)) | |
8605 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; | |
8606 | else if (IS_GEN5(dev_priv)) | |
8607 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; | |
8608 | else if (IS_G4X(dev_priv)) | |
8609 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
c0f86832 | 8610 | else if (IS_I965GM(dev_priv)) |
bb400da9 | 8611 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
c0f86832 | 8612 | else if (IS_I965G(dev_priv)) |
bb400da9 ID |
8613 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
8614 | else if (IS_GEN3(dev_priv)) | |
8615 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
8616 | else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) | |
8617 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8618 | else if (IS_GEN2(dev_priv)) | |
8619 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
8620 | else { | |
8621 | MISSING_CASE(INTEL_DEVID(dev_priv)); | |
8622 | dev_priv->display.init_clock_gating = nop_init_clock_gating; | |
8623 | } | |
8624 | } | |
8625 | ||
1fa61106 | 8626 | /* Set up chip specific power management-related functions */ |
62d75df7 | 8627 | void intel_init_pm(struct drm_i915_private *dev_priv) |
1fa61106 | 8628 | { |
7ff0ebcc | 8629 | intel_fbc_init(dev_priv); |
1fa61106 | 8630 | |
c921aba8 | 8631 | /* For cxsr */ |
9b1e14f4 | 8632 | if (IS_PINEVIEW(dev_priv)) |
148ac1f3 | 8633 | i915_pineview_get_mem_freq(dev_priv); |
5db94019 | 8634 | else if (IS_GEN5(dev_priv)) |
148ac1f3 | 8635 | i915_ironlake_get_mem_freq(dev_priv); |
c921aba8 | 8636 | |
1fa61106 | 8637 | /* For FIFO watermark updates */ |
62d75df7 | 8638 | if (INTEL_GEN(dev_priv) >= 9) { |
bb726519 | 8639 | skl_setup_wm_latency(dev_priv); |
e62929b3 | 8640 | dev_priv->display.initial_watermarks = skl_initial_wm; |
ccf010fb | 8641 | dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; |
98d39494 | 8642 | dev_priv->display.compute_global_watermarks = skl_compute_wm; |
6e266956 | 8643 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bb726519 | 8644 | ilk_setup_wm_latency(dev_priv); |
53615a5e | 8645 | |
5db94019 | 8646 | if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && |
bd602544 | 8647 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
5db94019 | 8648 | (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && |
bd602544 | 8649 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
86c8bbbe | 8650 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
ed4a6a7c MR |
8651 | dev_priv->display.compute_intermediate_wm = |
8652 | ilk_compute_intermediate_wm; | |
8653 | dev_priv->display.initial_watermarks = | |
8654 | ilk_initial_watermarks; | |
8655 | dev_priv->display.optimize_watermarks = | |
8656 | ilk_optimize_watermarks; | |
bd602544 VS |
8657 | } else { |
8658 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8659 | "Disable CxSR\n"); | |
8660 | } | |
6b6b3eef | 8661 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bb726519 | 8662 | vlv_setup_wm_latency(dev_priv); |
ff32c54e | 8663 | dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm; |
4841da51 | 8664 | dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm; |
ff32c54e | 8665 | dev_priv->display.initial_watermarks = vlv_initial_watermarks; |
4841da51 | 8666 | dev_priv->display.optimize_watermarks = vlv_optimize_watermarks; |
ff32c54e | 8667 | dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo; |
04548cba VS |
8668 | } else if (IS_G4X(dev_priv)) { |
8669 | g4x_setup_wm_latency(dev_priv); | |
8670 | dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm; | |
8671 | dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm; | |
8672 | dev_priv->display.initial_watermarks = g4x_initial_watermarks; | |
8673 | dev_priv->display.optimize_watermarks = g4x_optimize_watermarks; | |
9b1e14f4 | 8674 | } else if (IS_PINEVIEW(dev_priv)) { |
50a0bc90 | 8675 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
1fa61106 ED |
8676 | dev_priv->is_ddr3, |
8677 | dev_priv->fsb_freq, | |
8678 | dev_priv->mem_freq)) { | |
8679 | DRM_INFO("failed to find known CxSR latency " | |
8680 | "(found ddr%s fsb freq %d, mem freq %d), " | |
8681 | "disabling CxSR\n", | |
8682 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
8683 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
8684 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 8685 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
8686 | dev_priv->display.update_wm = NULL; |
8687 | } else | |
8688 | dev_priv->display.update_wm = pineview_update_wm; | |
5db94019 | 8689 | } else if (IS_GEN4(dev_priv)) { |
1fa61106 | 8690 | dev_priv->display.update_wm = i965_update_wm; |
5db94019 | 8691 | } else if (IS_GEN3(dev_priv)) { |
1fa61106 ED |
8692 | dev_priv->display.update_wm = i9xx_update_wm; |
8693 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
5db94019 | 8694 | } else if (IS_GEN2(dev_priv)) { |
62d75df7 | 8695 | if (INTEL_INFO(dev_priv)->num_pipes == 1) { |
feb56b93 | 8696 | dev_priv->display.update_wm = i845_update_wm; |
1fa61106 | 8697 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
8698 | } else { |
8699 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 8700 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 | 8701 | } |
feb56b93 DV |
8702 | } else { |
8703 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
8704 | } |
8705 | } | |
8706 | ||
87660502 L |
8707 | static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv) |
8708 | { | |
8709 | uint32_t flags = | |
8710 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8711 | ||
8712 | switch (flags) { | |
8713 | case GEN6_PCODE_SUCCESS: | |
8714 | return 0; | |
8715 | case GEN6_PCODE_UNIMPLEMENTED_CMD: | |
8716 | case GEN6_PCODE_ILLEGAL_CMD: | |
8717 | return -ENXIO; | |
8718 | case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
7850d1c3 | 8719 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: |
87660502 L |
8720 | return -EOVERFLOW; |
8721 | case GEN6_PCODE_TIMEOUT: | |
8722 | return -ETIMEDOUT; | |
8723 | default: | |
f0d66153 | 8724 | MISSING_CASE(flags); |
87660502 L |
8725 | return 0; |
8726 | } | |
8727 | } | |
8728 | ||
8729 | static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv) | |
8730 | { | |
8731 | uint32_t flags = | |
8732 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8733 | ||
8734 | switch (flags) { | |
8735 | case GEN6_PCODE_SUCCESS: | |
8736 | return 0; | |
8737 | case GEN6_PCODE_ILLEGAL_CMD: | |
8738 | return -ENXIO; | |
8739 | case GEN7_PCODE_TIMEOUT: | |
8740 | return -ETIMEDOUT; | |
8741 | case GEN7_PCODE_ILLEGAL_DATA: | |
8742 | return -EINVAL; | |
8743 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
8744 | return -EOVERFLOW; | |
8745 | default: | |
8746 | MISSING_CASE(flags); | |
8747 | return 0; | |
8748 | } | |
8749 | } | |
8750 | ||
151a49d0 | 8751 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 8752 | { |
87660502 L |
8753 | int status; |
8754 | ||
4fc688ce | 8755 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8756 | |
3f5582dd CW |
8757 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8758 | * use te fw I915_READ variants to reduce the amount of work | |
8759 | * required when reading/writing. | |
8760 | */ | |
8761 | ||
8762 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
42c0526c BW |
8763 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
8764 | return -EAGAIN; | |
8765 | } | |
8766 | ||
3f5582dd CW |
8767 | I915_WRITE_FW(GEN6_PCODE_DATA, *val); |
8768 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); | |
8769 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
42c0526c | 8770 | |
e09a3036 CW |
8771 | if (__intel_wait_for_register_fw(dev_priv, |
8772 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
8773 | 500, 0, NULL)) { | |
42c0526c BW |
8774 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
8775 | return -ETIMEDOUT; | |
8776 | } | |
8777 | ||
3f5582dd CW |
8778 | *val = I915_READ_FW(GEN6_PCODE_DATA); |
8779 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); | |
42c0526c | 8780 | |
87660502 L |
8781 | if (INTEL_GEN(dev_priv) > 6) |
8782 | status = gen7_check_mailbox_status(dev_priv); | |
8783 | else | |
8784 | status = gen6_check_mailbox_status(dev_priv); | |
8785 | ||
8786 | if (status) { | |
8787 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n", | |
8788 | status); | |
8789 | return status; | |
8790 | } | |
8791 | ||
42c0526c BW |
8792 | return 0; |
8793 | } | |
8794 | ||
3f5582dd | 8795 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, |
87660502 | 8796 | u32 mbox, u32 val) |
42c0526c | 8797 | { |
87660502 L |
8798 | int status; |
8799 | ||
4fc688ce | 8800 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8801 | |
3f5582dd CW |
8802 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8803 | * use te fw I915_READ variants to reduce the amount of work | |
8804 | * required when reading/writing. | |
8805 | */ | |
8806 | ||
8807 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
42c0526c BW |
8808 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
8809 | return -EAGAIN; | |
8810 | } | |
8811 | ||
3f5582dd | 8812 | I915_WRITE_FW(GEN6_PCODE_DATA, val); |
8bf41b72 | 8813 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); |
3f5582dd | 8814 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
42c0526c | 8815 | |
e09a3036 CW |
8816 | if (__intel_wait_for_register_fw(dev_priv, |
8817 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
8818 | 500, 0, NULL)) { | |
42c0526c BW |
8819 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
8820 | return -ETIMEDOUT; | |
8821 | } | |
8822 | ||
3f5582dd | 8823 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); |
42c0526c | 8824 | |
87660502 L |
8825 | if (INTEL_GEN(dev_priv) > 6) |
8826 | status = gen7_check_mailbox_status(dev_priv); | |
8827 | else | |
8828 | status = gen6_check_mailbox_status(dev_priv); | |
8829 | ||
8830 | if (status) { | |
8831 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n", | |
8832 | status); | |
8833 | return status; | |
8834 | } | |
8835 | ||
42c0526c BW |
8836 | return 0; |
8837 | } | |
a0e4e199 | 8838 | |
a0b8a1fe ID |
8839 | static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox, |
8840 | u32 request, u32 reply_mask, u32 reply, | |
8841 | u32 *status) | |
8842 | { | |
8843 | u32 val = request; | |
8844 | ||
8845 | *status = sandybridge_pcode_read(dev_priv, mbox, &val); | |
8846 | ||
8847 | return *status || ((val & reply_mask) == reply); | |
8848 | } | |
8849 | ||
8850 | /** | |
8851 | * skl_pcode_request - send PCODE request until acknowledgment | |
8852 | * @dev_priv: device private | |
8853 | * @mbox: PCODE mailbox ID the request is targeted for | |
8854 | * @request: request ID | |
8855 | * @reply_mask: mask used to check for request acknowledgment | |
8856 | * @reply: value used to check for request acknowledgment | |
8857 | * @timeout_base_ms: timeout for polling with preemption enabled | |
8858 | * | |
8859 | * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE | |
0129936d | 8860 | * reports an error or an overall timeout of @timeout_base_ms+50 ms expires. |
a0b8a1fe ID |
8861 | * The request is acknowledged once the PCODE reply dword equals @reply after |
8862 | * applying @reply_mask. Polling is first attempted with preemption enabled | |
0129936d | 8863 | * for @timeout_base_ms and if this times out for another 50 ms with |
a0b8a1fe ID |
8864 | * preemption disabled. |
8865 | * | |
8866 | * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some | |
8867 | * other error as reported by PCODE. | |
8868 | */ | |
8869 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, | |
8870 | u32 reply_mask, u32 reply, int timeout_base_ms) | |
8871 | { | |
8872 | u32 status; | |
8873 | int ret; | |
8874 | ||
8875 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
8876 | ||
8877 | #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \ | |
8878 | &status) | |
8879 | ||
8880 | /* | |
8881 | * Prime the PCODE by doing a request first. Normally it guarantees | |
8882 | * that a subsequent request, at most @timeout_base_ms later, succeeds. | |
8883 | * _wait_for() doesn't guarantee when its passed condition is evaluated | |
8884 | * first, so send the first request explicitly. | |
8885 | */ | |
8886 | if (COND) { | |
8887 | ret = 0; | |
8888 | goto out; | |
8889 | } | |
8890 | ret = _wait_for(COND, timeout_base_ms * 1000, 10); | |
8891 | if (!ret) | |
8892 | goto out; | |
8893 | ||
8894 | /* | |
8895 | * The above can time out if the number of requests was low (2 in the | |
8896 | * worst case) _and_ PCODE was busy for some reason even after a | |
8897 | * (queued) request and @timeout_base_ms delay. As a workaround retry | |
8898 | * the poll with preemption disabled to maximize the number of | |
0129936d | 8899 | * requests. Increase the timeout from @timeout_base_ms to 50ms to |
a0b8a1fe | 8900 | * account for interrupts that could reduce the number of these |
0129936d ID |
8901 | * requests, and for any quirks of the PCODE firmware that delays |
8902 | * the request completion. | |
a0b8a1fe ID |
8903 | */ |
8904 | DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n"); | |
8905 | WARN_ON_ONCE(timeout_base_ms > 3); | |
8906 | preempt_disable(); | |
0129936d | 8907 | ret = wait_for_atomic(COND, 50); |
a0b8a1fe ID |
8908 | preempt_enable(); |
8909 | ||
8910 | out: | |
8911 | return ret ? ret : status; | |
8912 | #undef COND | |
8913 | } | |
8914 | ||
dd06f88c VS |
8915 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
8916 | { | |
c30fec65 VS |
8917 | /* |
8918 | * N = val - 0xb7 | |
8919 | * Slow = Fast = GPLL ref * N | |
8920 | */ | |
8921 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000); | |
855ba3be JB |
8922 | } |
8923 | ||
b55dd647 | 8924 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 8925 | { |
c30fec65 | 8926 | return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7; |
855ba3be JB |
8927 | } |
8928 | ||
b55dd647 | 8929 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8930 | { |
c30fec65 VS |
8931 | /* |
8932 | * N = val / 2 | |
8933 | * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 | |
8934 | */ | |
8935 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000); | |
22b1b2f8 D |
8936 | } |
8937 | ||
b55dd647 | 8938 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8939 | { |
1c14762d | 8940 | /* CHV needs even values */ |
c30fec65 | 8941 | return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2; |
22b1b2f8 D |
8942 | } |
8943 | ||
616bc820 | 8944 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8945 | { |
2d1fe073 | 8946 | if (IS_GEN9(dev_priv)) |
500a3d2e MK |
8947 | return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, |
8948 | GEN9_FREQ_SCALER); | |
2d1fe073 | 8949 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 8950 | return chv_gpu_freq(dev_priv, val); |
2d1fe073 | 8951 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
8952 | return byt_gpu_freq(dev_priv, val); |
8953 | else | |
8954 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
8955 | } |
8956 | ||
616bc820 VS |
8957 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
8958 | { | |
2d1fe073 | 8959 | if (IS_GEN9(dev_priv)) |
500a3d2e MK |
8960 | return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, |
8961 | GT_FREQUENCY_MULTIPLIER); | |
2d1fe073 | 8962 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 8963 | return chv_freq_opcode(dev_priv, val); |
2d1fe073 | 8964 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
8965 | return byt_freq_opcode(dev_priv, val); |
8966 | else | |
500a3d2e | 8967 | return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); |
616bc820 | 8968 | } |
22b1b2f8 | 8969 | |
6ad790c0 CW |
8970 | struct request_boost { |
8971 | struct work_struct work; | |
eed29a5b | 8972 | struct drm_i915_gem_request *req; |
6ad790c0 CW |
8973 | }; |
8974 | ||
8975 | static void __intel_rps_boost_work(struct work_struct *work) | |
8976 | { | |
8977 | struct request_boost *boost = container_of(work, struct request_boost, work); | |
e61b9958 | 8978 | struct drm_i915_gem_request *req = boost->req; |
6ad790c0 | 8979 | |
f69a02c9 | 8980 | if (!i915_gem_request_completed(req)) |
c033666a | 8981 | gen6_rps_boost(req->i915, NULL, req->emitted_jiffies); |
6ad790c0 | 8982 | |
e8a261ea | 8983 | i915_gem_request_put(req); |
6ad790c0 CW |
8984 | kfree(boost); |
8985 | } | |
8986 | ||
91d14251 | 8987 | void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req) |
6ad790c0 CW |
8988 | { |
8989 | struct request_boost *boost; | |
8990 | ||
91d14251 | 8991 | if (req == NULL || INTEL_GEN(req->i915) < 6) |
6ad790c0 CW |
8992 | return; |
8993 | ||
f69a02c9 | 8994 | if (i915_gem_request_completed(req)) |
e61b9958 CW |
8995 | return; |
8996 | ||
6ad790c0 CW |
8997 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
8998 | if (boost == NULL) | |
8999 | return; | |
9000 | ||
e8a261ea | 9001 | boost->req = i915_gem_request_get(req); |
6ad790c0 CW |
9002 | |
9003 | INIT_WORK(&boost->work, __intel_rps_boost_work); | |
91d14251 | 9004 | queue_work(req->i915->wq, &boost->work); |
6ad790c0 CW |
9005 | } |
9006 | ||
192aa181 | 9007 | void intel_pm_setup(struct drm_i915_private *dev_priv) |
907b28c5 | 9008 | { |
f742a552 | 9009 | mutex_init(&dev_priv->rps.hw_lock); |
8d3afd7d | 9010 | spin_lock_init(&dev_priv->rps.client_lock); |
f742a552 | 9011 | |
54b4f68f CW |
9012 | INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work, |
9013 | __intel_autoenable_gt_powersave); | |
1854d5ca | 9014 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
5d584b2e | 9015 | |
33688d95 | 9016 | dev_priv->pm.suspended = false; |
1f814dac | 9017 | atomic_set(&dev_priv->pm.wakeref_count, 0); |
907b28c5 | 9018 | } |
135bafa5 | 9019 | |
47c21d9a MK |
9020 | static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, |
9021 | const i915_reg_t reg) | |
9022 | { | |
facbecad | 9023 | u32 lower, upper, tmp; |
71cc2b18 | 9024 | int loop = 2; |
47c21d9a MK |
9025 | |
9026 | /* The register accessed do not need forcewake. We borrow | |
9027 | * uncore lock to prevent concurrent access to range reg. | |
9028 | */ | |
9029 | spin_lock_irq(&dev_priv->uncore.lock); | |
47c21d9a MK |
9030 | |
9031 | /* vlv and chv residency counters are 40 bits in width. | |
9032 | * With a control bit, we can choose between upper or lower | |
9033 | * 32bit window into this counter. | |
facbecad CW |
9034 | * |
9035 | * Although we always use the counter in high-range mode elsewhere, | |
9036 | * userspace may attempt to read the value before rc6 is initialised, | |
9037 | * before we have set the default VLV_COUNTER_CONTROL value. So always | |
9038 | * set the high bit to be safe. | |
47c21d9a | 9039 | */ |
facbecad CW |
9040 | I915_WRITE_FW(VLV_COUNTER_CONTROL, |
9041 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); | |
47c21d9a MK |
9042 | upper = I915_READ_FW(reg); |
9043 | do { | |
9044 | tmp = upper; | |
9045 | ||
9046 | I915_WRITE_FW(VLV_COUNTER_CONTROL, | |
9047 | _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); | |
9048 | lower = I915_READ_FW(reg); | |
9049 | ||
9050 | I915_WRITE_FW(VLV_COUNTER_CONTROL, | |
9051 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); | |
9052 | upper = I915_READ_FW(reg); | |
71cc2b18 | 9053 | } while (upper != tmp && --loop); |
47c21d9a | 9054 | |
facbecad CW |
9055 | /* Everywhere else we always use VLV_COUNTER_CONTROL with the |
9056 | * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set | |
9057 | * now. | |
9058 | */ | |
9059 | ||
47c21d9a MK |
9060 | spin_unlock_irq(&dev_priv->uncore.lock); |
9061 | ||
9062 | return lower | (u64)upper << 8; | |
9063 | } | |
9064 | ||
c5a0ad11 MK |
9065 | u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
9066 | const i915_reg_t reg) | |
135bafa5 | 9067 | { |
47c21d9a | 9068 | u64 time_hw, units, div; |
135bafa5 MK |
9069 | |
9070 | if (!intel_enable_rc6()) | |
9071 | return 0; | |
9072 | ||
9073 | intel_runtime_pm_get(dev_priv); | |
9074 | ||
9075 | /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ | |
9076 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
c5a0ad11 | 9077 | units = 1000; |
135bafa5 MK |
9078 | div = dev_priv->czclk_freq; |
9079 | ||
47c21d9a | 9080 | time_hw = vlv_residency_raw(dev_priv, reg); |
135bafa5 | 9081 | } else if (IS_GEN9_LP(dev_priv)) { |
c5a0ad11 | 9082 | units = 1000; |
135bafa5 | 9083 | div = 1200; /* 833.33ns */ |
135bafa5 | 9084 | |
47c21d9a MK |
9085 | time_hw = I915_READ(reg); |
9086 | } else { | |
9087 | units = 128000; /* 1.28us */ | |
9088 | div = 100000; | |
9089 | ||
9090 | time_hw = I915_READ(reg); | |
9091 | } | |
135bafa5 MK |
9092 | |
9093 | intel_runtime_pm_put(dev_priv); | |
47c21d9a | 9094 | return DIV_ROUND_UP_ULL(time_hw * units, div); |
135bafa5 | 9095 | } |