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drm/i915: properly set HSW WM_PIPE registers
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
3490ea5d
CW		 47static bool intel_crtc_active(struct drm_crtc *crtc)
48{
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53}
54
1fa61106 55static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 56{
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75}
76
1fa61106 77static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 78{
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
84f44ce7
VS		 116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 118}
119
1fa61106 120static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125}
126
1fa61106 127static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 128{
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
84f44ce7 151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 152}
153
1fa61106 154static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 155{
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167}
168
1fa61106 169static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 170{
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174}
175
176static void sandybridge_blit_fbc_update(struct drm_device *dev)
177{
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194}
195
1fa61106 196static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 197{
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
84f44ce7 231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 232}
233
1fa61106 234static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 235{
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
b74ea102 245 if (IS_IVYBRIDGE(dev))
7dd23ba0 246 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 247 I915_WRITE(ILK_DSPCLK_GATE_D,
248 I915_READ(ILK_DSPCLK_GATE_D) &
249 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
250
d89f2071 251 if (IS_HASWELL(dev))
7dd23ba0 252 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 253 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
254 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
255 ~HSW_DPFC_GATING_DISABLE);
256
85208be0
ED		 257 DRM_DEBUG_KMS("disabled FBC\n");
258 }
259}
260
1fa61106 261static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264
265 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
266}
267
abe959c7
RV		 268static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269{
270 struct drm_device *dev = crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 struct drm_framebuffer *fb = crtc->fb;
273 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276
277 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
278
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN |
281 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282
891348b2 283 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 285 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 286 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 287 I915_WRITE(ILK_DSPCLK_GATE_D,
288 I915_READ(ILK_DSPCLK_GATE_D) |
289 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 290 } else {
7dd23ba0 291 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 292 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
293 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 294 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 295 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
296 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
297 HSW_DPFC_GATING_DISABLE);
891348b2 298 }
b74ea102 299
abe959c7
RV		 300 I915_WRITE(SNB_DPFC_CTL_SA,
301 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
302 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
303
304 sandybridge_blit_fbc_update(dev);
305
306 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
307}
308
85208be0
ED		 309bool intel_fbc_enabled(struct drm_device *dev)
310{
311 struct drm_i915_private *dev_priv = dev->dev_private;
312
313 if (!dev_priv->display.fbc_enabled)
314 return false;
315
316 return dev_priv->display.fbc_enabled(dev);
317}
318
319static void intel_fbc_work_fn(struct work_struct *__work)
320{
321 struct intel_fbc_work *work =
322 container_of(to_delayed_work(__work),
323 struct intel_fbc_work, work);
324 struct drm_device *dev = work->crtc->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326
327 mutex_lock(&dev->struct_mutex);
328 if (work == dev_priv->fbc_work) {
329 /* Double check that we haven't switched fb without cancelling
330 * the prior work.
331 */
332 if (work->crtc->fb == work->fb) {
333 dev_priv->display.enable_fbc(work->crtc,
334 work->interval);
335
336 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->cfb_fb = work->crtc->fb->base.id;
338 dev_priv->cfb_y = work->crtc->y;
339 }
340
341 dev_priv->fbc_work = NULL;
342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346}
347
348static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349{
350 if (dev_priv->fbc_work == NULL)
351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
358 */
359 if (cancel_delayed_work(&dev_priv->fbc_work->work))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv->fbc_work);
362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
368 dev_priv->fbc_work = NULL;
369}
370
371void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
372{
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
382 work = kzalloc(sizeof *work, GFP_KERNEL);
383 if (work == NULL) {
384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
393 dev_priv->fbc_work = work;
394
395 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
396
397 /* Delay the actual enabling to let pageflipping cease and the
398 * display to settle before starting the compression. Note that
399 * this delay also serves a second purpose: it allows for a
400 * vblank to pass after disabling the FBC before we attempt
401 * to modify the control registers.
402 *
403 * A more complicated solution would involve tracking vblanks
404 * following the termination of the page-flipping sequence
405 * and indeed performing the enable as a co-routine and not
406 * waiting synchronously upon the vblank.
407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
421 dev_priv->cfb_plane = -1;
422}
423
424/**
425 * intel_update_fbc - enable/disable FBC as needed
426 * @dev: the drm_device
427 *
428 * Set up the framebuffer compression hardware at mode set time. We
429 * enable it if possible:
430 * - plane A only (on pre-965)
431 * - no pixel mulitply/line duplication
432 * - no alpha buffer discard
433 * - no dual wide
434 * - framebuffer <= 2048 in width, 1536 in height
435 *
436 * We can't assume that any compression will take place (worst case),
437 * so the compressed buffer has to be the same size as the uncompressed
438 * one. It also must reside (along with the line length buffer) in
439 * stolen memory.
440 *
441 * We need to enable/disable FBC on a global basis.
442 */
443void intel_update_fbc(struct drm_device *dev)
444{
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 struct drm_crtc *crtc = NULL, *tmp_crtc;
447 struct intel_crtc *intel_crtc;
448 struct drm_framebuffer *fb;
449 struct intel_framebuffer *intel_fb;
450 struct drm_i915_gem_object *obj;
451 int enable_fbc;
452
85208be0
ED		 453 if (!i915_powersave)
454 return;
455
456 if (!I915_HAS_FBC(dev))
457 return;
458
459 /*
460 * If FBC is already on, we just have to verify that we can
461 * keep it that way...
462 * Need to disable if:
463 * - more than one pipe is active
464 * - changing FBC params (stride, fence, mode)
465 * - new fb is too large to fit in compressed buffer
466 * - going to an unsupported config (interlace, pixel multiply, etc.)
467 */
468 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 469 if (intel_crtc_active(tmp_crtc) &&
470 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 471 if (crtc) {
472 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
473 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
474 goto out_disable;
475 }
476 crtc = tmp_crtc;
477 }
478 }
479
480 if (!crtc || crtc->fb == NULL) {
481 DRM_DEBUG_KMS("no output, disabling\n");
482 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
483 goto out_disable;
484 }
485
486 intel_crtc = to_intel_crtc(crtc);
487 fb = crtc->fb;
488 intel_fb = to_intel_framebuffer(fb);
489 obj = intel_fb->obj;
490
491 enable_fbc = i915_enable_fbc;
492 if (enable_fbc < 0) {
493 DRM_DEBUG_KMS("fbc set to per-chip default\n");
494 enable_fbc = 1;
891348b2 495 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
85208be0
ED		 496 enable_fbc = 0;
497 }
498 if (!enable_fbc) {
499 DRM_DEBUG_KMS("fbc disabled per module param\n");
500 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
501 goto out_disable;
502 }
85208be0
ED		 503 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
504 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
505 DRM_DEBUG_KMS("mode incompatible with compression, "
506 "disabling\n");
507 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
508 goto out_disable;
509 }
510 if ((crtc->mode.hdisplay > 2048) ||
511 (crtc->mode.vdisplay > 1536)) {
512 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
513 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
514 goto out_disable;
515 }
891348b2
RV		 516 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
517 intel_crtc->plane != 0) {
85208be0
ED		 518 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
519 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
520 goto out_disable;
521 }
522
523 /* The use of a CPU fence is mandatory in order to detect writes
524 * by the CPU to the scanout and trigger updates to the FBC.
525 */
526 if (obj->tiling_mode != I915_TILING_X ||
527 obj->fence_reg == I915_FENCE_REG_NONE) {
528 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
529 dev_priv->no_fbc_reason = FBC_NOT_TILED;
530 goto out_disable;
531 }
532
533 /* If the kernel debugger is active, always disable compression */
534 if (in_dbg_master())
535 goto out_disable;
536
11be49eb 537 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
11be49eb
CW		 538 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
539 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
540 goto out_disable;
541 }
542
85208be0
ED		 543 /* If the scanout has not changed, don't modify the FBC settings.
544 * Note that we make the fundamental assumption that the fb->obj
545 * cannot be unpinned (and have its GTT offset and fence revoked)
546 * without first being decoupled from the scanout and FBC disabled.
547 */
548 if (dev_priv->cfb_plane == intel_crtc->plane &&
549 dev_priv->cfb_fb == fb->base.id &&
550 dev_priv->cfb_y == crtc->y)
551 return;
552
553 if (intel_fbc_enabled(dev)) {
554 /* We update FBC along two paths, after changing fb/crtc
555 * configuration (modeswitching) and after page-flipping
556 * finishes. For the latter, we know that not only did
557 * we disable the FBC at the start of the page-flip
558 * sequence, but also more than one vblank has passed.
559 *
560 * For the former case of modeswitching, it is possible
561 * to switch between two FBC valid configurations
562 * instantaneously so we do need to disable the FBC
563 * before we can modify its control registers. We also
564 * have to wait for the next vblank for that to take
565 * effect. However, since we delay enabling FBC we can
566 * assume that a vblank has passed since disabling and
567 * that we can safely alter the registers in the deferred
568 * callback.
569 *
570 * In the scenario that we go from a valid to invalid
571 * and then back to valid FBC configuration we have
572 * no strict enforcement that a vblank occurred since
573 * disabling the FBC. However, along all current pipe
574 * disabling paths we do need to wait for a vblank at
575 * some point. And we wait before enabling FBC anyway.
576 */
577 DRM_DEBUG_KMS("disabling active FBC for update\n");
578 intel_disable_fbc(dev);
579 }
580
581 intel_enable_fbc(crtc, 500);
582 return;
583
584out_disable:
585 /* Multiple disables should be harmless */
586 if (intel_fbc_enabled(dev)) {
587 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
588 intel_disable_fbc(dev);
589 }
11be49eb 590 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 591}
592
c921aba8
DV		 593static void i915_pineview_get_mem_freq(struct drm_device *dev)
594{
595 drm_i915_private_t *dev_priv = dev->dev_private;
596 u32 tmp;
597
598 tmp = I915_READ(CLKCFG);
599
600 switch (tmp & CLKCFG_FSB_MASK) {
601 case CLKCFG_FSB_533:
602 dev_priv->fsb_freq = 533; /* 133*4 */
603 break;
604 case CLKCFG_FSB_800:
605 dev_priv->fsb_freq = 800; /* 200*4 */
606 break;
607 case CLKCFG_FSB_667:
608 dev_priv->fsb_freq = 667; /* 167*4 */
609 break;
610 case CLKCFG_FSB_400:
611 dev_priv->fsb_freq = 400; /* 100*4 */
612 break;
613 }
614
615 switch (tmp & CLKCFG_MEM_MASK) {
616 case CLKCFG_MEM_533:
617 dev_priv->mem_freq = 533;
618 break;
619 case CLKCFG_MEM_667:
620 dev_priv->mem_freq = 667;
621 break;
622 case CLKCFG_MEM_800:
623 dev_priv->mem_freq = 800;
624 break;
625 }
626
627 /* detect pineview DDR3 setting */
628 tmp = I915_READ(CSHRDDR3CTL);
629 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
630}
631
632static void i915_ironlake_get_mem_freq(struct drm_device *dev)
633{
634 drm_i915_private_t *dev_priv = dev->dev_private;
635 u16 ddrpll, csipll;
636
637 ddrpll = I915_READ16(DDRMPLL1);
638 csipll = I915_READ16(CSIPLL0);
639
640 switch (ddrpll & 0xff) {
641 case 0xc:
642 dev_priv->mem_freq = 800;
643 break;
644 case 0x10:
645 dev_priv->mem_freq = 1066;
646 break;
647 case 0x14:
648 dev_priv->mem_freq = 1333;
649 break;
650 case 0x18:
651 dev_priv->mem_freq = 1600;
652 break;
653 default:
654 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
655 ddrpll & 0xff);
656 dev_priv->mem_freq = 0;
657 break;
658 }
659
20e4d407 660 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 661
662 switch (csipll & 0x3ff) {
663 case 0x00c:
664 dev_priv->fsb_freq = 3200;
665 break;
666 case 0x00e:
667 dev_priv->fsb_freq = 3733;
668 break;
669 case 0x010:
670 dev_priv->fsb_freq = 4266;
671 break;
672 case 0x012:
673 dev_priv->fsb_freq = 4800;
674 break;
675 case 0x014:
676 dev_priv->fsb_freq = 5333;
677 break;
678 case 0x016:
679 dev_priv->fsb_freq = 5866;
680 break;
681 case 0x018:
682 dev_priv->fsb_freq = 6400;
683 break;
684 default:
685 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
686 csipll & 0x3ff);
687 dev_priv->fsb_freq = 0;
688 break;
689 }
690
691 if (dev_priv->fsb_freq == 3200) {
20e4d407 692 dev_priv->ips.c_m = 0;
c921aba8 693 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 694 dev_priv->ips.c_m = 1;
c921aba8 695 } else {
20e4d407 696 dev_priv->ips.c_m = 2;
c921aba8
DV		 697 }
698}
699
b445e3b0
ED		 700static const struct cxsr_latency cxsr_latency_table[] = {
701 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
702 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
703 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
704 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
705 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
706
707 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
708 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
709 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
710 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
711 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
712
713 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
714 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
715 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
716 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
717 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
718
719 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
720 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
721 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
722 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
723 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
724
725 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
726 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
727 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
728 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
729 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
730
731 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
732 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
733 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
734 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
735 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
736};
737
63c62275 738static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 739 int is_ddr3,
740 int fsb,
741 int mem)
742{
743 const struct cxsr_latency *latency;
744 int i;
745
746 if (fsb == 0 || mem == 0)
747 return NULL;
748
749 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
750 latency = &cxsr_latency_table[i];
751 if (is_desktop == latency->is_desktop &&
752 is_ddr3 == latency->is_ddr3 &&
753 fsb == latency->fsb_freq && mem == latency->mem_freq)
754 return latency;
755 }
756
757 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
758
759 return NULL;
760}
761
1fa61106 762static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765
766 /* deactivate cxsr */
767 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
768}
769
770/*
771 * Latency for FIFO fetches is dependent on several factors:
772 * - memory configuration (speed, channels)
773 * - chipset
774 * - current MCH state
775 * It can be fairly high in some situations, so here we assume a fairly
776 * pessimal value. It's a tradeoff between extra memory fetches (if we
777 * set this value too high, the FIFO will fetch frequently to stay full)
778 * and power consumption (set it too low to save power and we might see
779 * FIFO underruns and display "flicker").
780 *
781 * A value of 5us seems to be a good balance; safe for very low end
782 * platforms but not overly aggressive on lower latency configs.
783 */
784static const int latency_ns = 5000;
785
1fa61106 786static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 787{
788 struct drm_i915_private *dev_priv = dev->dev_private;
789 uint32_t dsparb = I915_READ(DSPARB);
790 int size;
791
792 size = dsparb & 0x7f;
793 if (plane)
794 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
795
796 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
797 plane ? "B" : "A", size);
798
799 return size;
800}
801
1fa61106 802static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 803{
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 uint32_t dsparb = I915_READ(DSPARB);
806 int size;
807
808 size = dsparb & 0x1ff;
809 if (plane)
810 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
811 size >>= 1; /* Convert to cachelines */
812
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
815
816 return size;
817}
818
1fa61106 819static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 820{
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
823 int size;
824
825 size = dsparb & 0x7f;
826 size >>= 2; /* Convert to cachelines */
827
828 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
829 plane ? "B" : "A",
830 size);
831
832 return size;
833}
834
1fa61106 835static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 836{
837 struct drm_i915_private *dev_priv = dev->dev_private;
838 uint32_t dsparb = I915_READ(DSPARB);
839 int size;
840
841 size = dsparb & 0x7f;
842 size >>= 1; /* Convert to cachelines */
843
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
846
847 return size;
848}
849
850/* Pineview has different values for various configs */
851static const struct intel_watermark_params pineview_display_wm = {
852 PINEVIEW_DISPLAY_FIFO,
853 PINEVIEW_MAX_WM,
854 PINEVIEW_DFT_WM,
855 PINEVIEW_GUARD_WM,
856 PINEVIEW_FIFO_LINE_SIZE
857};
858static const struct intel_watermark_params pineview_display_hplloff_wm = {
859 PINEVIEW_DISPLAY_FIFO,
860 PINEVIEW_MAX_WM,
861 PINEVIEW_DFT_HPLLOFF_WM,
862 PINEVIEW_GUARD_WM,
863 PINEVIEW_FIFO_LINE_SIZE
864};
865static const struct intel_watermark_params pineview_cursor_wm = {
866 PINEVIEW_CURSOR_FIFO,
867 PINEVIEW_CURSOR_MAX_WM,
868 PINEVIEW_CURSOR_DFT_WM,
869 PINEVIEW_CURSOR_GUARD_WM,
870 PINEVIEW_FIFO_LINE_SIZE,
871};
872static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
873 PINEVIEW_CURSOR_FIFO,
874 PINEVIEW_CURSOR_MAX_WM,
875 PINEVIEW_CURSOR_DFT_WM,
876 PINEVIEW_CURSOR_GUARD_WM,
877 PINEVIEW_FIFO_LINE_SIZE
878};
879static const struct intel_watermark_params g4x_wm_info = {
880 G4X_FIFO_SIZE,
881 G4X_MAX_WM,
882 G4X_MAX_WM,
883 2,
884 G4X_FIFO_LINE_SIZE,
885};
886static const struct intel_watermark_params g4x_cursor_wm_info = {
887 I965_CURSOR_FIFO,
888 I965_CURSOR_MAX_WM,
889 I965_CURSOR_DFT_WM,
890 2,
891 G4X_FIFO_LINE_SIZE,
892};
893static const struct intel_watermark_params valleyview_wm_info = {
894 VALLEYVIEW_FIFO_SIZE,
895 VALLEYVIEW_MAX_WM,
896 VALLEYVIEW_MAX_WM,
897 2,
898 G4X_FIFO_LINE_SIZE,
899};
900static const struct intel_watermark_params valleyview_cursor_wm_info = {
901 I965_CURSOR_FIFO,
902 VALLEYVIEW_CURSOR_MAX_WM,
903 I965_CURSOR_DFT_WM,
904 2,
905 G4X_FIFO_LINE_SIZE,
906};
907static const struct intel_watermark_params i965_cursor_wm_info = {
908 I965_CURSOR_FIFO,
909 I965_CURSOR_MAX_WM,
910 I965_CURSOR_DFT_WM,
911 2,
912 I915_FIFO_LINE_SIZE,
913};
914static const struct intel_watermark_params i945_wm_info = {
915 I945_FIFO_SIZE,
916 I915_MAX_WM,
917 1,
918 2,
919 I915_FIFO_LINE_SIZE
920};
921static const struct intel_watermark_params i915_wm_info = {
922 I915_FIFO_SIZE,
923 I915_MAX_WM,
924 1,
925 2,
926 I915_FIFO_LINE_SIZE
927};
928static const struct intel_watermark_params i855_wm_info = {
929 I855GM_FIFO_SIZE,
930 I915_MAX_WM,
931 1,
932 2,
933 I830_FIFO_LINE_SIZE
934};
935static const struct intel_watermark_params i830_wm_info = {
936 I830_FIFO_SIZE,
937 I915_MAX_WM,
938 1,
939 2,
940 I830_FIFO_LINE_SIZE
941};
942
943static const struct intel_watermark_params ironlake_display_wm_info = {
944 ILK_DISPLAY_FIFO,
945 ILK_DISPLAY_MAXWM,
946 ILK_DISPLAY_DFTWM,
947 2,
948 ILK_FIFO_LINE_SIZE
949};
950static const struct intel_watermark_params ironlake_cursor_wm_info = {
951 ILK_CURSOR_FIFO,
952 ILK_CURSOR_MAXWM,
953 ILK_CURSOR_DFTWM,
954 2,
955 ILK_FIFO_LINE_SIZE
956};
957static const struct intel_watermark_params ironlake_display_srwm_info = {
958 ILK_DISPLAY_SR_FIFO,
959 ILK_DISPLAY_MAX_SRWM,
960 ILK_DISPLAY_DFT_SRWM,
961 2,
962 ILK_FIFO_LINE_SIZE
963};
964static const struct intel_watermark_params ironlake_cursor_srwm_info = {
965 ILK_CURSOR_SR_FIFO,
966 ILK_CURSOR_MAX_SRWM,
967 ILK_CURSOR_DFT_SRWM,
968 2,
969 ILK_FIFO_LINE_SIZE
970};
971
972static const struct intel_watermark_params sandybridge_display_wm_info = {
973 SNB_DISPLAY_FIFO,
974 SNB_DISPLAY_MAXWM,
975 SNB_DISPLAY_DFTWM,
976 2,
977 SNB_FIFO_LINE_SIZE
978};
979static const struct intel_watermark_params sandybridge_cursor_wm_info = {
980 SNB_CURSOR_FIFO,
981 SNB_CURSOR_MAXWM,
982 SNB_CURSOR_DFTWM,
983 2,
984 SNB_FIFO_LINE_SIZE
985};
986static const struct intel_watermark_params sandybridge_display_srwm_info = {
987 SNB_DISPLAY_SR_FIFO,
988 SNB_DISPLAY_MAX_SRWM,
989 SNB_DISPLAY_DFT_SRWM,
990 2,
991 SNB_FIFO_LINE_SIZE
992};
993static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
994 SNB_CURSOR_SR_FIFO,
995 SNB_CURSOR_MAX_SRWM,
996 SNB_CURSOR_DFT_SRWM,
997 2,
998 SNB_FIFO_LINE_SIZE
999};
1000
1001
1002/**
1003 * intel_calculate_wm - calculate watermark level
1004 * @clock_in_khz: pixel clock
1005 * @wm: chip FIFO params
1006 * @pixel_size: display pixel size
1007 * @latency_ns: memory latency for the platform
1008 *
1009 * Calculate the watermark level (the level at which the display plane will
1010 * start fetching from memory again). Each chip has a different display
1011 * FIFO size and allocation, so the caller needs to figure that out and pass
1012 * in the correct intel_watermark_params structure.
1013 *
1014 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1015 * on the pixel size. When it reaches the watermark level, it'll start
1016 * fetching FIFO line sized based chunks from memory until the FIFO fills
1017 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1018 * will occur, and a display engine hang could result.
1019 */
1020static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1021 const struct intel_watermark_params *wm,
1022 int fifo_size,
1023 int pixel_size,
1024 unsigned long latency_ns)
1025{
1026 long entries_required, wm_size;
1027
1028 /*
1029 * Note: we need to make sure we don't overflow for various clock &
1030 * latency values.
1031 * clocks go from a few thousand to several hundred thousand.
1032 * latency is usually a few thousand
1033 */
1034 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1035 1000;
1036 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1037
1038 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1039
1040 wm_size = fifo_size - (entries_required + wm->guard_size);
1041
1042 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1043
1044 /* Don't promote wm_size to unsigned... */
1045 if (wm_size > (long)wm->max_wm)
1046 wm_size = wm->max_wm;
1047 if (wm_size <= 0)
1048 wm_size = wm->default_wm;
1049 return wm_size;
1050}
1051
1052static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1053{
1054 struct drm_crtc *crtc, *enabled = NULL;
1055
1056 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1057 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1058 if (enabled)
1059 return NULL;
1060 enabled = crtc;
1061 }
1062 }
1063
1064 return enabled;
1065}
1066
1fa61106 1067static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1068{
1069 struct drm_i915_private *dev_priv = dev->dev_private;
1070 struct drm_crtc *crtc;
1071 const struct cxsr_latency *latency;
1072 u32 reg;
1073 unsigned long wm;
1074
1075 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1076 dev_priv->fsb_freq, dev_priv->mem_freq);
1077 if (!latency) {
1078 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1079 pineview_disable_cxsr(dev);
1080 return;
1081 }
1082
1083 crtc = single_enabled_crtc(dev);
1084 if (crtc) {
1085 int clock = crtc->mode.clock;
1086 int pixel_size = crtc->fb->bits_per_pixel / 8;
1087
1088 /* Display SR */
1089 wm = intel_calculate_wm(clock, &pineview_display_wm,
1090 pineview_display_wm.fifo_size,
1091 pixel_size, latency->display_sr);
1092 reg = I915_READ(DSPFW1);
1093 reg &= ~DSPFW_SR_MASK;
1094 reg |= wm << DSPFW_SR_SHIFT;
1095 I915_WRITE(DSPFW1, reg);
1096 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1097
1098 /* cursor SR */
1099 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1100 pineview_display_wm.fifo_size,
1101 pixel_size, latency->cursor_sr);
1102 reg = I915_READ(DSPFW3);
1103 reg &= ~DSPFW_CURSOR_SR_MASK;
1104 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1105 I915_WRITE(DSPFW3, reg);
1106
1107 /* Display HPLL off SR */
1108 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1109 pineview_display_hplloff_wm.fifo_size,
1110 pixel_size, latency->display_hpll_disable);
1111 reg = I915_READ(DSPFW3);
1112 reg &= ~DSPFW_HPLL_SR_MASK;
1113 reg |= wm & DSPFW_HPLL_SR_MASK;
1114 I915_WRITE(DSPFW3, reg);
1115
1116 /* cursor HPLL off SR */
1117 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1118 pineview_display_hplloff_wm.fifo_size,
1119 pixel_size, latency->cursor_hpll_disable);
1120 reg = I915_READ(DSPFW3);
1121 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1122 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1123 I915_WRITE(DSPFW3, reg);
1124 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1125
1126 /* activate cxsr */
1127 I915_WRITE(DSPFW3,
1128 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1129 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1130 } else {
1131 pineview_disable_cxsr(dev);
1132 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1133 }
1134}
1135
1136static bool g4x_compute_wm0(struct drm_device *dev,
1137 int plane,
1138 const struct intel_watermark_params *display,
1139 int display_latency_ns,
1140 const struct intel_watermark_params *cursor,
1141 int cursor_latency_ns,
1142 int *plane_wm,
1143 int *cursor_wm)
1144{
1145 struct drm_crtc *crtc;
1146 int htotal, hdisplay, clock, pixel_size;
1147 int line_time_us, line_count;
1148 int entries, tlb_miss;
1149
1150 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1151 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1152 *cursor_wm = cursor->guard_size;
1153 *plane_wm = display->guard_size;
1154 return false;
1155 }
1156
1157 htotal = crtc->mode.htotal;
1158 hdisplay = crtc->mode.hdisplay;
1159 clock = crtc->mode.clock;
1160 pixel_size = crtc->fb->bits_per_pixel / 8;
1161
1162 /* Use the small buffer method to calculate plane watermark */
1163 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1164 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1165 if (tlb_miss > 0)
1166 entries += tlb_miss;
1167 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1168 *plane_wm = entries + display->guard_size;
1169 if (*plane_wm > (int)display->max_wm)
1170 *plane_wm = display->max_wm;
1171
1172 /* Use the large buffer method to calculate cursor watermark */
1173 line_time_us = ((htotal * 1000) / clock);
1174 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1175 entries = line_count * 64 * pixel_size;
1176 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1177 if (tlb_miss > 0)
1178 entries += tlb_miss;
1179 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1180 *cursor_wm = entries + cursor->guard_size;
1181 if (*cursor_wm > (int)cursor->max_wm)
1182 *cursor_wm = (int)cursor->max_wm;
1183
1184 return true;
1185}
1186
1187/*
1188 * Check the wm result.
1189 *
1190 * If any calculated watermark values is larger than the maximum value that
1191 * can be programmed into the associated watermark register, that watermark
1192 * must be disabled.
1193 */
1194static bool g4x_check_srwm(struct drm_device *dev,
1195 int display_wm, int cursor_wm,
1196 const struct intel_watermark_params *display,
1197 const struct intel_watermark_params *cursor)
1198{
1199 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1200 display_wm, cursor_wm);
1201
1202 if (display_wm > display->max_wm) {
1203 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1204 display_wm, display->max_wm);
1205 return false;
1206 }
1207
1208 if (cursor_wm > cursor->max_wm) {
1209 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1210 cursor_wm, cursor->max_wm);
1211 return false;
1212 }
1213
1214 if (!(display_wm || cursor_wm)) {
1215 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1216 return false;
1217 }
1218
1219 return true;
1220}
1221
1222static bool g4x_compute_srwm(struct drm_device *dev,
1223 int plane,
1224 int latency_ns,
1225 const struct intel_watermark_params *display,
1226 const struct intel_watermark_params *cursor,
1227 int *display_wm, int *cursor_wm)
1228{
1229 struct drm_crtc *crtc;
1230 int hdisplay, htotal, pixel_size, clock;
1231 unsigned long line_time_us;
1232 int line_count, line_size;
1233 int small, large;
1234 int entries;
1235
1236 if (!latency_ns) {
1237 *display_wm = *cursor_wm = 0;
1238 return false;
1239 }
1240
1241 crtc = intel_get_crtc_for_plane(dev, plane);
1242 hdisplay = crtc->mode.hdisplay;
1243 htotal = crtc->mode.htotal;
1244 clock = crtc->mode.clock;
1245 pixel_size = crtc->fb->bits_per_pixel / 8;
1246
1247 line_time_us = (htotal * 1000) / clock;
1248 line_count = (latency_ns / line_time_us + 1000) / 1000;
1249 line_size = hdisplay * pixel_size;
1250
1251 /* Use the minimum of the small and large buffer method for primary */
1252 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1253 large = line_count * line_size;
1254
1255 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1256 *display_wm = entries + display->guard_size;
1257
1258 /* calculate the self-refresh watermark for display cursor */
1259 entries = line_count * pixel_size * 64;
1260 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1261 *cursor_wm = entries + cursor->guard_size;
1262
1263 return g4x_check_srwm(dev,
1264 *display_wm, *cursor_wm,
1265 display, cursor);
1266}
1267
1268static bool vlv_compute_drain_latency(struct drm_device *dev,
1269 int plane,
1270 int *plane_prec_mult,
1271 int *plane_dl,
1272 int *cursor_prec_mult,
1273 int *cursor_dl)
1274{
1275 struct drm_crtc *crtc;
1276 int clock, pixel_size;
1277 int entries;
1278
1279 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1280 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1281 return false;
1282
1283 clock = crtc->mode.clock; /* VESA DOT Clock */
1284 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1285
1286 entries = (clock / 1000) * pixel_size;
1287 *plane_prec_mult = (entries > 256) ?
1288 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1289 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1290 pixel_size);
1291
1292 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1293 *cursor_prec_mult = (entries > 256) ?
1294 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1295 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1296
1297 return true;
1298}
1299
1300/*
1301 * Update drain latency registers of memory arbiter
1302 *
1303 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1304 * to be programmed. Each plane has a drain latency multiplier and a drain
1305 * latency value.
1306 */
1307
1308static void vlv_update_drain_latency(struct drm_device *dev)
1309{
1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1312 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1313 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1314 either 16 or 32 */
1315
1316 /* For plane A, Cursor A */
1317 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1318 &cursor_prec_mult, &cursora_dl)) {
1319 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1320 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1321 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1322 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1323
1324 I915_WRITE(VLV_DDL1, cursora_prec |
1325 (cursora_dl << DDL_CURSORA_SHIFT) |
1326 planea_prec | planea_dl);
1327 }
1328
1329 /* For plane B, Cursor B */
1330 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1331 &cursor_prec_mult, &cursorb_dl)) {
1332 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1333 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1334 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1335 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1336
1337 I915_WRITE(VLV_DDL2, cursorb_prec |
1338 (cursorb_dl << DDL_CURSORB_SHIFT) |
1339 planeb_prec | planeb_dl);
1340 }
1341}
1342
1343#define single_plane_enabled(mask) is_power_of_2(mask)
1344
1fa61106 1345static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1346{
1347 static const int sr_latency_ns = 12000;
1348 struct drm_i915_private *dev_priv = dev->dev_private;
1349 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350 int plane_sr, cursor_sr;
af6c4575 1351 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1352 unsigned int enabled = 0;
1353
1354 vlv_update_drain_latency(dev);
1355
51cea1f4 1356 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1357 &valleyview_wm_info, latency_ns,
1358 &valleyview_cursor_wm_info, latency_ns,
1359 &planea_wm, &cursora_wm))
51cea1f4 1360 enabled |= 1 << PIPE_A;
b445e3b0 1361
51cea1f4 1362 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1363 &valleyview_wm_info, latency_ns,
1364 &valleyview_cursor_wm_info, latency_ns,
1365 &planeb_wm, &cursorb_wm))
51cea1f4 1366 enabled |= 1 << PIPE_B;
b445e3b0 1367
b445e3b0
ED		 1368 if (single_plane_enabled(enabled) &&
1369 g4x_compute_srwm(dev, ffs(enabled) - 1,
1370 sr_latency_ns,
1371 &valleyview_wm_info,
1372 &valleyview_cursor_wm_info,
af6c4575
CW		 1373 &plane_sr, &ignore_cursor_sr) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 2*sr_latency_ns,
1376 &valleyview_wm_info,
1377 &valleyview_cursor_wm_info,
52bd02d8 1378 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1379 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1380 } else {
b445e3b0
ED		 1381 I915_WRITE(FW_BLC_SELF_VLV,
1382 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1383 plane_sr = cursor_sr = 0;
1384 }
b445e3b0
ED		 1385
1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387 planea_wm, cursora_wm,
1388 planeb_wm, cursorb_wm,
1389 plane_sr, cursor_sr);
1390
1391 I915_WRITE(DSPFW1,
1392 (plane_sr << DSPFW_SR_SHIFT) |
1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1395 planea_wm);
1396 I915_WRITE(DSPFW2,
8c919b28 1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1398 (cursora_wm << DSPFW_CURSORA_SHIFT));
1399 I915_WRITE(DSPFW3,
8c919b28
CW		 1400 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1401 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1402}
1403
1fa61106 1404static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1405{
1406 static const int sr_latency_ns = 12000;
1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1409 int plane_sr, cursor_sr;
1410 unsigned int enabled = 0;
1411
51cea1f4 1412 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1413 &g4x_wm_info, latency_ns,
1414 &g4x_cursor_wm_info, latency_ns,
1415 &planea_wm, &cursora_wm))
51cea1f4 1416 enabled |= 1 << PIPE_A;
b445e3b0 1417
51cea1f4 1418 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1419 &g4x_wm_info, latency_ns,
1420 &g4x_cursor_wm_info, latency_ns,
1421 &planeb_wm, &cursorb_wm))
51cea1f4 1422 enabled |= 1 << PIPE_B;
b445e3b0 1423
b445e3b0
ED		 1424 if (single_plane_enabled(enabled) &&
1425 g4x_compute_srwm(dev, ffs(enabled) - 1,
1426 sr_latency_ns,
1427 &g4x_wm_info,
1428 &g4x_cursor_wm_info,
52bd02d8 1429 &plane_sr, &cursor_sr)) {
b445e3b0 1430 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1431 } else {
b445e3b0
ED		 1432 I915_WRITE(FW_BLC_SELF,
1433 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1434 plane_sr = cursor_sr = 0;
1435 }
b445e3b0
ED		 1436
1437 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1438 planea_wm, cursora_wm,
1439 planeb_wm, cursorb_wm,
1440 plane_sr, cursor_sr);
1441
1442 I915_WRITE(DSPFW1,
1443 (plane_sr << DSPFW_SR_SHIFT) |
1444 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1445 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1446 planea_wm);
1447 I915_WRITE(DSPFW2,
8c919b28 1448 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1449 (cursora_wm << DSPFW_CURSORA_SHIFT));
1450 /* HPLL off in SR has some issues on G4x... disable it */
1451 I915_WRITE(DSPFW3,
8c919b28 1452 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1453 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1454}
1455
1fa61106 1456static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1457{
1458 struct drm_i915_private *dev_priv = dev->dev_private;
1459 struct drm_crtc *crtc;
1460 int srwm = 1;
1461 int cursor_sr = 16;
1462
1463 /* Calc sr entries for one plane configs */
1464 crtc = single_enabled_crtc(dev);
1465 if (crtc) {
1466 /* self-refresh has much higher latency */
1467 static const int sr_latency_ns = 12000;
1468 int clock = crtc->mode.clock;
1469 int htotal = crtc->mode.htotal;
1470 int hdisplay = crtc->mode.hdisplay;
1471 int pixel_size = crtc->fb->bits_per_pixel / 8;
1472 unsigned long line_time_us;
1473 int entries;
1474
1475 line_time_us = ((htotal * 1000) / clock);
1476
1477 /* Use ns/us then divide to preserve precision */
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479 pixel_size * hdisplay;
1480 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1481 srwm = I965_FIFO_SIZE - entries;
1482 if (srwm < 0)
1483 srwm = 1;
1484 srwm &= 0x1ff;
1485 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1486 entries, srwm);
1487
1488 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1489 pixel_size * 64;
1490 entries = DIV_ROUND_UP(entries,
1491 i965_cursor_wm_info.cacheline_size);
1492 cursor_sr = i965_cursor_wm_info.fifo_size -
1493 (entries + i965_cursor_wm_info.guard_size);
1494
1495 if (cursor_sr > i965_cursor_wm_info.max_wm)
1496 cursor_sr = i965_cursor_wm_info.max_wm;
1497
1498 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499 "cursor %d\n", srwm, cursor_sr);
1500
1501 if (IS_CRESTLINE(dev))
1502 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1503 } else {
1504 /* Turn off self refresh if both pipes are enabled */
1505 if (IS_CRESTLINE(dev))
1506 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1507 & ~FW_BLC_SELF_EN);
1508 }
1509
1510 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1511 srwm);
1512
1513 /* 965 has limitations... */
1514 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1515 (8 << 16) | (8 << 8) | (8 << 0));
1516 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1517 /* update cursor SR watermark */
1518 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1519}
1520
1fa61106 1521static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1522{
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 const struct intel_watermark_params *wm_info;
1525 uint32_t fwater_lo;
1526 uint32_t fwater_hi;
1527 int cwm, srwm = 1;
1528 int fifo_size;
1529 int planea_wm, planeb_wm;
1530 struct drm_crtc *crtc, *enabled = NULL;
1531
1532 if (IS_I945GM(dev))
1533 wm_info = &i945_wm_info;
1534 else if (!IS_GEN2(dev))
1535 wm_info = &i915_wm_info;
1536 else
1537 wm_info = &i855_wm_info;
1538
1539 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1541 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1542 int cpp = crtc->fb->bits_per_pixel / 8;
1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
b445e3b0 1546 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
b445e3b0
ED		 1548 latency_ns);
1549 enabled = crtc;
1550 } else
1551 planea_wm = fifo_size - wm_info->guard_size;
1552
1553 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1555 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1556 int cpp = crtc->fb->bits_per_pixel / 8;
1557 if (IS_GEN2(dev))
1558 cpp = 4;
1559
b445e3b0 1560 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1561 wm_info, fifo_size, cpp,
b445e3b0
ED		 1562 latency_ns);
1563 if (enabled == NULL)
1564 enabled = crtc;
1565 else
1566 enabled = NULL;
1567 } else
1568 planeb_wm = fifo_size - wm_info->guard_size;
1569
1570 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1571
1572 /*
1573 * Overlay gets an aggressive default since video jitter is bad.
1574 */
1575 cwm = 2;
1576
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
1578 if (IS_I945G(dev) || IS_I945GM(dev))
1579 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1580 else if (IS_I915GM(dev))
1581 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1582
1583 /* Calc sr entries for one plane configs */
1584 if (HAS_FW_BLC(dev) && enabled) {
1585 /* self-refresh has much higher latency */
1586 static const int sr_latency_ns = 6000;
1587 int clock = enabled->mode.clock;
1588 int htotal = enabled->mode.htotal;
1589 int hdisplay = enabled->mode.hdisplay;
1590 int pixel_size = enabled->fb->bits_per_pixel / 8;
1591 unsigned long line_time_us;
1592 int entries;
1593
1594 line_time_us = (htotal * 1000) / clock;
1595
1596 /* Use ns/us then divide to preserve precision */
1597 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1598 pixel_size * hdisplay;
1599 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1600 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1601 srwm = wm_info->fifo_size - entries;
1602 if (srwm < 0)
1603 srwm = 1;
1604
1605 if (IS_I945G(dev) || IS_I945GM(dev))
1606 I915_WRITE(FW_BLC_SELF,
1607 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1608 else if (IS_I915GM(dev))
1609 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1610 }
1611
1612 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613 planea_wm, planeb_wm, cwm, srwm);
1614
1615 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1616 fwater_hi = (cwm & 0x1f);
1617
1618 /* Set request length to 8 cachelines per fetch */
1619 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1620 fwater_hi = fwater_hi | (1 << 8);
1621
1622 I915_WRITE(FW_BLC, fwater_lo);
1623 I915_WRITE(FW_BLC2, fwater_hi);
1624
1625 if (HAS_FW_BLC(dev)) {
1626 if (enabled) {
1627 if (IS_I945G(dev) || IS_I945GM(dev))
1628 I915_WRITE(FW_BLC_SELF,
1629 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1630 else if (IS_I915GM(dev))
1631 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1632 DRM_DEBUG_KMS("memory self refresh enabled\n");
1633 } else
1634 DRM_DEBUG_KMS("memory self refresh disabled\n");
1635 }
1636}
1637
1fa61106 1638static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1639{
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 struct drm_crtc *crtc;
1642 uint32_t fwater_lo;
1643 int planea_wm;
1644
1645 crtc = single_enabled_crtc(dev);
1646 if (crtc == NULL)
1647 return;
1648
1649 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1650 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1651 4, latency_ns);
b445e3b0
ED		 1652 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1653 fwater_lo |= (3<<8) | planea_wm;
1654
1655 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1656
1657 I915_WRITE(FW_BLC, fwater_lo);
1658}
1659
1660#define ILK_LP0_PLANE_LATENCY 700
1661#define ILK_LP0_CURSOR_LATENCY 1300
1662
1663/*
1664 * Check the wm result.
1665 *
1666 * If any calculated watermark values is larger than the maximum value that
1667 * can be programmed into the associated watermark register, that watermark
1668 * must be disabled.
1669 */
1670static bool ironlake_check_srwm(struct drm_device *dev, int level,
1671 int fbc_wm, int display_wm, int cursor_wm,
1672 const struct intel_watermark_params *display,
1673 const struct intel_watermark_params *cursor)
1674{
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1678 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1679
1680 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1681 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1682 fbc_wm, SNB_FBC_MAX_SRWM, level);
1683
1684 /* fbc has it's own way to disable FBC WM */
1685 I915_WRITE(DISP_ARB_CTL,
1686 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1687 return false;
615aaa5f
VS		 1688 } else if (INTEL_INFO(dev)->gen >= 6) {
1689 /* enable FBC WM (except on ILK, where it must remain off) */
1690 I915_WRITE(DISP_ARB_CTL,
1691 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1692 }
1693
1694 if (display_wm > display->max_wm) {
1695 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1696 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1697 return false;
1698 }
1699
1700 if (cursor_wm > cursor->max_wm) {
1701 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1702 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1703 return false;
1704 }
1705
1706 if (!(fbc_wm || display_wm || cursor_wm)) {
1707 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1708 return false;
1709 }
1710
1711 return true;
1712}
1713
1714/*
1715 * Compute watermark values of WM[1-3],
1716 */
1717static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1718 int latency_ns,
1719 const struct intel_watermark_params *display,
1720 const struct intel_watermark_params *cursor,
1721 int *fbc_wm, int *display_wm, int *cursor_wm)
1722{
1723 struct drm_crtc *crtc;
1724 unsigned long line_time_us;
1725 int hdisplay, htotal, pixel_size, clock;
1726 int line_count, line_size;
1727 int small, large;
1728 int entries;
1729
1730 if (!latency_ns) {
1731 *fbc_wm = *display_wm = *cursor_wm = 0;
1732 return false;
1733 }
1734
1735 crtc = intel_get_crtc_for_plane(dev, plane);
1736 hdisplay = crtc->mode.hdisplay;
1737 htotal = crtc->mode.htotal;
1738 clock = crtc->mode.clock;
1739 pixel_size = crtc->fb->bits_per_pixel / 8;
1740
1741 line_time_us = (htotal * 1000) / clock;
1742 line_count = (latency_ns / line_time_us + 1000) / 1000;
1743 line_size = hdisplay * pixel_size;
1744
1745 /* Use the minimum of the small and large buffer method for primary */
1746 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1747 large = line_count * line_size;
1748
1749 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1750 *display_wm = entries + display->guard_size;
1751
1752 /*
1753 * Spec says:
1754 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1755 */
1756 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1757
1758 /* calculate the self-refresh watermark for display cursor */
1759 entries = line_count * pixel_size * 64;
1760 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1761 *cursor_wm = entries + cursor->guard_size;
1762
1763 return ironlake_check_srwm(dev, level,
1764 *fbc_wm, *display_wm, *cursor_wm,
1765 display, cursor);
1766}
1767
1fa61106 1768static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1769{
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 int fbc_wm, plane_wm, cursor_wm;
1772 unsigned int enabled;
1773
1774 enabled = 0;
51cea1f4 1775 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1776 &ironlake_display_wm_info,
1777 ILK_LP0_PLANE_LATENCY,
1778 &ironlake_cursor_wm_info,
1779 ILK_LP0_CURSOR_LATENCY,
1780 &plane_wm, &cursor_wm)) {
1781 I915_WRITE(WM0_PIPEA_ILK,
1782 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1783 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1784 " plane %d, " "cursor: %d\n",
1785 plane_wm, cursor_wm);
51cea1f4 1786 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1787 }
1788
51cea1f4 1789 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1790 &ironlake_display_wm_info,
1791 ILK_LP0_PLANE_LATENCY,
1792 &ironlake_cursor_wm_info,
1793 ILK_LP0_CURSOR_LATENCY,
1794 &plane_wm, &cursor_wm)) {
1795 I915_WRITE(WM0_PIPEB_ILK,
1796 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1797 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1798 " plane %d, cursor: %d\n",
1799 plane_wm, cursor_wm);
51cea1f4 1800 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1801 }
1802
1803 /*
1804 * Calculate and update the self-refresh watermark only when one
1805 * display plane is used.
1806 */
1807 I915_WRITE(WM3_LP_ILK, 0);
1808 I915_WRITE(WM2_LP_ILK, 0);
1809 I915_WRITE(WM1_LP_ILK, 0);
1810
1811 if (!single_plane_enabled(enabled))
1812 return;
1813 enabled = ffs(enabled) - 1;
1814
1815 /* WM1 */
1816 if (!ironlake_compute_srwm(dev, 1, enabled,
1817 ILK_READ_WM1_LATENCY() * 500,
1818 &ironlake_display_srwm_info,
1819 &ironlake_cursor_srwm_info,
1820 &fbc_wm, &plane_wm, &cursor_wm))
1821 return;
1822
1823 I915_WRITE(WM1_LP_ILK,
1824 WM1_LP_SR_EN |
1825 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1826 (fbc_wm << WM1_LP_FBC_SHIFT) |
1827 (plane_wm << WM1_LP_SR_SHIFT) |
1828 cursor_wm);
1829
1830 /* WM2 */
1831 if (!ironlake_compute_srwm(dev, 2, enabled,
1832 ILK_READ_WM2_LATENCY() * 500,
1833 &ironlake_display_srwm_info,
1834 &ironlake_cursor_srwm_info,
1835 &fbc_wm, &plane_wm, &cursor_wm))
1836 return;
1837
1838 I915_WRITE(WM2_LP_ILK,
1839 WM2_LP_EN |
1840 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1841 (fbc_wm << WM1_LP_FBC_SHIFT) |
1842 (plane_wm << WM1_LP_SR_SHIFT) |
1843 cursor_wm);
1844
1845 /*
1846 * WM3 is unsupported on ILK, probably because we don't have latency
1847 * data for that power state
1848 */
1849}
1850
1fa61106 1851static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1852{
1853 struct drm_i915_private *dev_priv = dev->dev_private;
1854 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1855 u32 val;
1856 int fbc_wm, plane_wm, cursor_wm;
1857 unsigned int enabled;
1858
1859 enabled = 0;
51cea1f4 1860 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1861 &sandybridge_display_wm_info, latency,
1862 &sandybridge_cursor_wm_info, latency,
1863 &plane_wm, &cursor_wm)) {
1864 val = I915_READ(WM0_PIPEA_ILK);
1865 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1866 I915_WRITE(WM0_PIPEA_ILK, val |
1867 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1868 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1869 " plane %d, " "cursor: %d\n",
1870 plane_wm, cursor_wm);
51cea1f4 1871 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1872 }
1873
51cea1f4 1874 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1875 &sandybridge_display_wm_info, latency,
1876 &sandybridge_cursor_wm_info, latency,
1877 &plane_wm, &cursor_wm)) {
1878 val = I915_READ(WM0_PIPEB_ILK);
1879 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1880 I915_WRITE(WM0_PIPEB_ILK, val |
1881 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1882 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1883 " plane %d, cursor: %d\n",
1884 plane_wm, cursor_wm);
51cea1f4 1885 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1886 }
1887
c43d0188
CW		 1888 /*
1889 * Calculate and update the self-refresh watermark only when one
1890 * display plane is used.
1891 *
1892 * SNB support 3 levels of watermark.
1893 *
1894 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1895 * and disabled in the descending order
1896 *
1897 */
1898 I915_WRITE(WM3_LP_ILK, 0);
1899 I915_WRITE(WM2_LP_ILK, 0);
1900 I915_WRITE(WM1_LP_ILK, 0);
1901
1902 if (!single_plane_enabled(enabled) ||
1903 dev_priv->sprite_scaling_enabled)
1904 return;
1905 enabled = ffs(enabled) - 1;
1906
1907 /* WM1 */
1908 if (!ironlake_compute_srwm(dev, 1, enabled,
1909 SNB_READ_WM1_LATENCY() * 500,
1910 &sandybridge_display_srwm_info,
1911 &sandybridge_cursor_srwm_info,
1912 &fbc_wm, &plane_wm, &cursor_wm))
1913 return;
1914
1915 I915_WRITE(WM1_LP_ILK,
1916 WM1_LP_SR_EN |
1917 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1918 (fbc_wm << WM1_LP_FBC_SHIFT) |
1919 (plane_wm << WM1_LP_SR_SHIFT) |
1920 cursor_wm);
1921
1922 /* WM2 */
1923 if (!ironlake_compute_srwm(dev, 2, enabled,
1924 SNB_READ_WM2_LATENCY() * 500,
1925 &sandybridge_display_srwm_info,
1926 &sandybridge_cursor_srwm_info,
1927 &fbc_wm, &plane_wm, &cursor_wm))
1928 return;
1929
1930 I915_WRITE(WM2_LP_ILK,
1931 WM2_LP_EN |
1932 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1933 (fbc_wm << WM1_LP_FBC_SHIFT) |
1934 (plane_wm << WM1_LP_SR_SHIFT) |
1935 cursor_wm);
1936
1937 /* WM3 */
1938 if (!ironlake_compute_srwm(dev, 3, enabled,
1939 SNB_READ_WM3_LATENCY() * 500,
1940 &sandybridge_display_srwm_info,
1941 &sandybridge_cursor_srwm_info,
1942 &fbc_wm, &plane_wm, &cursor_wm))
1943 return;
1944
1945 I915_WRITE(WM3_LP_ILK,
1946 WM3_LP_EN |
1947 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1948 (fbc_wm << WM1_LP_FBC_SHIFT) |
1949 (plane_wm << WM1_LP_SR_SHIFT) |
1950 cursor_wm);
1951}
1952
1953static void ivybridge_update_wm(struct drm_device *dev)
1954{
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1957 u32 val;
1958 int fbc_wm, plane_wm, cursor_wm;
1959 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1960 unsigned int enabled;
1961
1962 enabled = 0;
51cea1f4 1963 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1964 &sandybridge_display_wm_info, latency,
1965 &sandybridge_cursor_wm_info, latency,
1966 &plane_wm, &cursor_wm)) {
1967 val = I915_READ(WM0_PIPEA_ILK);
1968 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1969 I915_WRITE(WM0_PIPEA_ILK, val |
1970 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1971 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1972 " plane %d, " "cursor: %d\n",
1973 plane_wm, cursor_wm);
51cea1f4 1974 enabled |= 1 << PIPE_A;
c43d0188
CW		 1975 }
1976
51cea1f4 1977 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 1978 &sandybridge_display_wm_info, latency,
1979 &sandybridge_cursor_wm_info, latency,
1980 &plane_wm, &cursor_wm)) {
1981 val = I915_READ(WM0_PIPEB_ILK);
1982 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1983 I915_WRITE(WM0_PIPEB_ILK, val |
1984 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1985 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1986 " plane %d, cursor: %d\n",
1987 plane_wm, cursor_wm);
51cea1f4 1988 enabled |= 1 << PIPE_B;
c43d0188
CW		 1989 }
1990
51cea1f4 1991 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 1992 &sandybridge_display_wm_info, latency,
1993 &sandybridge_cursor_wm_info, latency,
1994 &plane_wm, &cursor_wm)) {
1995 val = I915_READ(WM0_PIPEC_IVB);
1996 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1997 I915_WRITE(WM0_PIPEC_IVB, val |
1998 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1999 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2000 " plane %d, cursor: %d\n",
2001 plane_wm, cursor_wm);
51cea1f4 2002 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2003 }
2004
2005 /*
2006 * Calculate and update the self-refresh watermark only when one
2007 * display plane is used.
2008 *
2009 * SNB support 3 levels of watermark.
2010 *
2011 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2012 * and disabled in the descending order
2013 *
2014 */
2015 I915_WRITE(WM3_LP_ILK, 0);
2016 I915_WRITE(WM2_LP_ILK, 0);
2017 I915_WRITE(WM1_LP_ILK, 0);
2018
2019 if (!single_plane_enabled(enabled) ||
2020 dev_priv->sprite_scaling_enabled)
2021 return;
2022 enabled = ffs(enabled) - 1;
2023
2024 /* WM1 */
2025 if (!ironlake_compute_srwm(dev, 1, enabled,
2026 SNB_READ_WM1_LATENCY() * 500,
2027 &sandybridge_display_srwm_info,
2028 &sandybridge_cursor_srwm_info,
2029 &fbc_wm, &plane_wm, &cursor_wm))
2030 return;
2031
2032 I915_WRITE(WM1_LP_ILK,
2033 WM1_LP_SR_EN |
2034 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2035 (fbc_wm << WM1_LP_FBC_SHIFT) |
2036 (plane_wm << WM1_LP_SR_SHIFT) |
2037 cursor_wm);
2038
2039 /* WM2 */
2040 if (!ironlake_compute_srwm(dev, 2, enabled,
2041 SNB_READ_WM2_LATENCY() * 500,
2042 &sandybridge_display_srwm_info,
2043 &sandybridge_cursor_srwm_info,
2044 &fbc_wm, &plane_wm, &cursor_wm))
2045 return;
2046
2047 I915_WRITE(WM2_LP_ILK,
2048 WM2_LP_EN |
2049 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2050 (fbc_wm << WM1_LP_FBC_SHIFT) |
2051 (plane_wm << WM1_LP_SR_SHIFT) |
2052 cursor_wm);
2053
c43d0188 2054 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2055 if (!ironlake_compute_srwm(dev, 3, enabled,
2056 SNB_READ_WM3_LATENCY() * 500,
2057 &sandybridge_display_srwm_info,
2058 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2059 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2060 !ironlake_compute_srwm(dev, 3, enabled,
2061 2 * SNB_READ_WM3_LATENCY() * 500,
2062 &sandybridge_display_srwm_info,
2063 &sandybridge_cursor_srwm_info,
2064 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2065 return;
2066
2067 I915_WRITE(WM3_LP_ILK,
2068 WM3_LP_EN |
2069 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2070 (fbc_wm << WM1_LP_FBC_SHIFT) |
2071 (plane_wm << WM1_LP_SR_SHIFT) |
2072 cursor_wm);
2073}
2074
801bcfff
PZ		 2075static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2076 struct drm_crtc *crtc)
2077{
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 uint32_t pixel_rate, pfit_size;
2080
2081 if (intel_crtc->config.pixel_target_clock)
2082 pixel_rate = intel_crtc->config.pixel_target_clock;
2083 else
2084 pixel_rate = intel_crtc->config.adjusted_mode.clock;
2085
2086 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2087 * adjust the pixel_rate here. */
2088
2089 pfit_size = intel_crtc->config.pch_pfit.size;
2090 if (pfit_size) {
2091 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2092
2093 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2094 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2095 pfit_w = (pfit_size >> 16) & 0xFFFF;
2096 pfit_h = pfit_size & 0xFFFF;
2097 if (pipe_w < pfit_w)
2098 pipe_w = pfit_w;
2099 if (pipe_h < pfit_h)
2100 pipe_h = pfit_h;
2101
2102 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2103 pfit_w * pfit_h);
2104 }
2105
2106 return pixel_rate;
2107}
2108
2109static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2110 uint32_t latency)
2111{
2112 uint64_t ret;
2113
2114 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2115 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2116
2117 return ret;
2118}
2119
2120static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2121 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2122 uint32_t latency)
2123{
2124 uint32_t ret;
2125
2126 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2127 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2128 ret = DIV_ROUND_UP(ret, 64) + 2;
2129 return ret;
2130}
2131
2132struct hsw_pipe_wm_parameters {
2133 bool active;
2134 bool sprite_enabled;
2135 uint8_t pri_bytes_per_pixel;
2136 uint8_t spr_bytes_per_pixel;
2137 uint8_t cur_bytes_per_pixel;
2138 uint32_t pri_horiz_pixels;
2139 uint32_t spr_horiz_pixels;
2140 uint32_t cur_horiz_pixels;
2141 uint32_t pipe_htotal;
2142 uint32_t pixel_rate;
2143};
2144
2145struct hsw_wm_values {
2146 uint32_t wm_pipe[3];
2147 uint32_t wm_lp[3];
2148 uint32_t wm_lp_spr[3];
2149 uint32_t wm_linetime[3];
2150};
2151
2152enum hsw_data_buf_partitioning {
2153 HSW_DATA_BUF_PART_1_2,
2154 HSW_DATA_BUF_PART_5_6,
2155};
2156
2157/* Only for WM_PIPE. */
2158static uint32_t hsw_compute_pri_wm_pipe(struct hsw_pipe_wm_parameters *params,
2159 uint32_t mem_value)
2160{
2161 /* TODO: for now, assume the primary plane is always enabled. */
2162 if (!params->active)
2163 return 0;
2164
2165 return hsw_wm_method1(params->pixel_rate,
2166 params->pri_bytes_per_pixel,
2167 mem_value);
2168}
2169
2170/* For both WM_PIPE and WM_LP. */
2171static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2172 uint32_t mem_value)
2173{
2174 uint32_t method1, method2;
2175
2176 if (!params->active || !params->sprite_enabled)
2177 return 0;
2178
2179 method1 = hsw_wm_method1(params->pixel_rate,
2180 params->spr_bytes_per_pixel,
2181 mem_value);
2182 method2 = hsw_wm_method2(params->pixel_rate,
2183 params->pipe_htotal,
2184 params->spr_horiz_pixels,
2185 params->spr_bytes_per_pixel,
2186 mem_value);
2187 return min(method1, method2);
2188}
2189
2190/* For both WM_PIPE and WM_LP. */
2191static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2192 uint32_t mem_value)
2193{
2194 if (!params->active)
2195 return 0;
2196
2197 return hsw_wm_method2(params->pixel_rate,
2198 params->pipe_htotal,
2199 params->cur_horiz_pixels,
2200 params->cur_bytes_per_pixel,
2201 mem_value);
2202}
2203
2204static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2205 uint32_t mem_value, enum pipe pipe,
2206 struct hsw_pipe_wm_parameters *params)
2207{
2208 uint32_t pri_val, cur_val, spr_val;
2209
2210 pri_val = hsw_compute_pri_wm_pipe(params, mem_value);
2211 spr_val = hsw_compute_spr_wm(params, mem_value);
2212 cur_val = hsw_compute_cur_wm(params, mem_value);
2213
2214 WARN(pri_val > 127,
2215 "Primary WM error, mode not supported for pipe %c\n",
2216 pipe_name(pipe));
2217 WARN(spr_val > 127,
2218 "Sprite WM error, mode not supported for pipe %c\n",
2219 pipe_name(pipe));
2220 WARN(cur_val > 63,
2221 "Cursor WM error, mode not supported for pipe %c\n",
2222 pipe_name(pipe));
2223
2224 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2225 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2226 cur_val;
2227}
2228
2229static uint32_t
2230hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2231{
2232 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2234 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2235 u32 linetime, ips_linetime;
1f8eeabf 2236
801bcfff
PZ		 2237 if (!intel_crtc_active(crtc))
2238 return 0;
1011d8c4 2239
1f8eeabf
ED		 2240 /* The WM are computed with base on how long it takes to fill a single
2241 * row at the given clock rate, multiplied by 8.
2242 * */
85a02deb
PZ		 2243 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2244 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2245 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2246
801bcfff
PZ		 2247 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2248 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2249}
2250
801bcfff
PZ		 2251static void hsw_compute_wm_parameters(struct drm_device *dev,
2252 struct hsw_pipe_wm_parameters *params,
2253 uint32_t *wm)
1011d8c4
PZ		 2254{
2255 struct drm_i915_private *dev_priv = dev->dev_private;
2256 struct drm_crtc *crtc;
801bcfff
PZ		 2257 struct drm_plane *plane;
2258 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1011d8c4
PZ		 2259 enum pipe pipe;
2260
801bcfff
PZ		 2261 if ((sskpd >> 56) & 0xFF)
2262 wm[0] = (sskpd >> 56) & 0xFF;
2263 else
2264 wm[0] = sskpd & 0xF;
2265 wm[1] = ((sskpd >> 4) & 0xFF) * 5;
2266 wm[2] = ((sskpd >> 12) & 0xFF) * 5;
2267 wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
2268 wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
2269
2270 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2272 struct hsw_pipe_wm_parameters *p;
2273
2274 pipe = intel_crtc->pipe;
2275 p = &params[pipe];
2276
2277 p->active = intel_crtc_active(crtc);
2278 if (!p->active)
2279 continue;
2280
2281 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2282 p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2283 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2284 p->cur_bytes_per_pixel = 4;
2285 p->pri_horiz_pixels =
2286 intel_crtc->config.requested_mode.hdisplay;
2287 p->cur_horiz_pixels = 64;
2288 }
2289
2290 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2291 struct intel_plane *intel_plane = to_intel_plane(plane);
2292 struct hsw_pipe_wm_parameters *p;
2293
2294 pipe = intel_plane->pipe;
2295 p = &params[pipe];
2296
2297 p->sprite_enabled = intel_plane->wm.enable;
2298 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2299 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
2300 }
2301}
2302
2303static void hsw_compute_wm_results(struct drm_device *dev,
2304 struct hsw_pipe_wm_parameters *params,
2305 uint32_t *wm,
2306 struct hsw_wm_values *results)
2307{
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309 struct drm_crtc *crtc;
2310 enum pipe pipe;
2311
2312 /* No support for LP WMs yet. */
2313 results->wm_lp[2] = 0;
2314 results->wm_lp[1] = 0;
2315 results->wm_lp[0] = 0;
2316 results->wm_lp_spr[2] = 0;
2317 results->wm_lp_spr[1] = 0;
2318 results->wm_lp_spr[0] = 0;
2319
2320 for_each_pipe(pipe)
2321 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2322 pipe,
2323 &params[pipe]);
1011d8c4
PZ		 2324
2325 for_each_pipe(pipe) {
2326 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2327 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2328 }
2329}
2330
2331/*
2332 * The spec says we shouldn't write when we don't need, because every write
2333 * causes WMs to be re-evaluated, expending some power.
2334 */
2335static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2336 struct hsw_wm_values *results,
2337 enum hsw_data_buf_partitioning partitioning)
2338{
2339 struct hsw_wm_values previous;
2340 uint32_t val;
2341 enum hsw_data_buf_partitioning prev_partitioning;
2342
2343 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2344 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2345 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2346 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2347 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2348 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2349 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2350 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2351 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2352 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2353 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2354 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2355
2356 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2357 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2358
2359 if (memcmp(results->wm_pipe, previous.wm_pipe,
2360 sizeof(results->wm_pipe)) == 0 &&
2361 memcmp(results->wm_lp, previous.wm_lp,
2362 sizeof(results->wm_lp)) == 0 &&
2363 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2364 sizeof(results->wm_lp_spr)) == 0 &&
2365 memcmp(results->wm_linetime, previous.wm_linetime,
2366 sizeof(results->wm_linetime)) == 0 &&
2367 partitioning == prev_partitioning)
2368 return;
2369
2370 if (previous.wm_lp[2] != 0)
2371 I915_WRITE(WM3_LP_ILK, 0);
2372 if (previous.wm_lp[1] != 0)
2373 I915_WRITE(WM2_LP_ILK, 0);
2374 if (previous.wm_lp[0] != 0)
2375 I915_WRITE(WM1_LP_ILK, 0);
2376
2377 if (previous.wm_pipe[0] != results->wm_pipe[0])
2378 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2379 if (previous.wm_pipe[1] != results->wm_pipe[1])
2380 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2381 if (previous.wm_pipe[2] != results->wm_pipe[2])
2382 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2383
2384 if (previous.wm_linetime[0] != results->wm_linetime[0])
2385 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2386 if (previous.wm_linetime[1] != results->wm_linetime[1])
2387 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2388 if (previous.wm_linetime[2] != results->wm_linetime[2])
2389 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2390
2391 if (prev_partitioning != partitioning) {
2392 val = I915_READ(WM_MISC);
2393 if (partitioning == HSW_DATA_BUF_PART_1_2)
2394 val &= ~WM_MISC_DATA_PARTITION_5_6;
2395 else
2396 val |= WM_MISC_DATA_PARTITION_5_6;
2397 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2398 }
2399
801bcfff
PZ		 2400 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2401 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2402 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2403 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2404 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2405 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2406
2407 if (results->wm_lp[0] != 0)
2408 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2409 if (results->wm_lp[1] != 0)
2410 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2411 if (results->wm_lp[2] != 0)
2412 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2413}
2414
2415static void haswell_update_wm(struct drm_device *dev)
2416{
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct hsw_pipe_wm_parameters params[3];
2419 struct hsw_wm_values results;
2420 uint32_t wm[5];
2421
2422 hsw_compute_wm_parameters(dev, params, wm);
2423 hsw_compute_wm_results(dev, params, wm, &results);
2424 hsw_write_wm_values(dev_priv, &results, HSW_DATA_BUF_PART_1_2);
1011d8c4
PZ		 2425}
2426
526682e9
PZ		 2427static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2428 uint32_t sprite_width, int pixel_size,
2429 bool enable)
2430{
2431 struct drm_plane *plane;
2432
2433 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2434 struct intel_plane *intel_plane = to_intel_plane(plane);
2435
2436 if (intel_plane->pipe == pipe) {
2437 intel_plane->wm.enable = enable;
2438 intel_plane->wm.horiz_pixels = sprite_width + 1;
2439 intel_plane->wm.bytes_per_pixel = pixel_size;
2440 break;
2441 }
2442 }
2443
2444 haswell_update_wm(dev);
2445}
2446
b445e3b0
ED		 2447static bool
2448sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2449 uint32_t sprite_width, int pixel_size,
2450 const struct intel_watermark_params *display,
2451 int display_latency_ns, int *sprite_wm)
2452{
2453 struct drm_crtc *crtc;
2454 int clock;
2455 int entries, tlb_miss;
2456
2457 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2458 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2459 *sprite_wm = display->guard_size;
2460 return false;
2461 }
2462
2463 clock = crtc->mode.clock;
2464
2465 /* Use the small buffer method to calculate the sprite watermark */
2466 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2467 tlb_miss = display->fifo_size*display->cacheline_size -
2468 sprite_width * 8;
2469 if (tlb_miss > 0)
2470 entries += tlb_miss;
2471 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2472 *sprite_wm = entries + display->guard_size;
2473 if (*sprite_wm > (int)display->max_wm)
2474 *sprite_wm = display->max_wm;
2475
2476 return true;
2477}
2478
2479static bool
2480sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2481 uint32_t sprite_width, int pixel_size,
2482 const struct intel_watermark_params *display,
2483 int latency_ns, int *sprite_wm)
2484{
2485 struct drm_crtc *crtc;
2486 unsigned long line_time_us;
2487 int clock;
2488 int line_count, line_size;
2489 int small, large;
2490 int entries;
2491
2492 if (!latency_ns) {
2493 *sprite_wm = 0;
2494 return false;
2495 }
2496
2497 crtc = intel_get_crtc_for_plane(dev, plane);
2498 clock = crtc->mode.clock;
2499 if (!clock) {
2500 *sprite_wm = 0;
2501 return false;
2502 }
2503
2504 line_time_us = (sprite_width * 1000) / clock;
2505 if (!line_time_us) {
2506 *sprite_wm = 0;
2507 return false;
2508 }
2509
2510 line_count = (latency_ns / line_time_us + 1000) / 1000;
2511 line_size = sprite_width * pixel_size;
2512
2513 /* Use the minimum of the small and large buffer method for primary */
2514 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2515 large = line_count * line_size;
2516
2517 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2518 *sprite_wm = entries + display->guard_size;
2519
2520 return *sprite_wm > 0x3ff ? false : true;
2521}
2522
1fa61106 2523static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2524 uint32_t sprite_width, int pixel_size,
2525 bool enable)
b445e3b0
ED		 2526{
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2529 u32 val;
2530 int sprite_wm, reg;
2531 int ret;
2532
4c4ff43a
PZ		 2533 if (!enable)
2534 return;
2535
b445e3b0
ED		 2536 switch (pipe) {
2537 case 0:
2538 reg = WM0_PIPEA_ILK;
2539 break;
2540 case 1:
2541 reg = WM0_PIPEB_ILK;
2542 break;
2543 case 2:
2544 reg = WM0_PIPEC_IVB;
2545 break;
2546 default:
2547 return; /* bad pipe */
2548 }
2549
2550 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2551 &sandybridge_display_wm_info,
2552 latency, &sprite_wm);
2553 if (!ret) {
84f44ce7
VS		 2554 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2555 pipe_name(pipe));
b445e3b0
ED		 2556 return;
2557 }
2558
2559 val = I915_READ(reg);
2560 val &= ~WM0_PIPE_SPRITE_MASK;
2561 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2562 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2563
2564
2565 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2566 pixel_size,
2567 &sandybridge_display_srwm_info,
2568 SNB_READ_WM1_LATENCY() * 500,
2569 &sprite_wm);
2570 if (!ret) {
84f44ce7
VS		 2571 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2572 pipe_name(pipe));
b445e3b0
ED		 2573 return;
2574 }
2575 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2576
2577 /* Only IVB has two more LP watermarks for sprite */
2578 if (!IS_IVYBRIDGE(dev))
2579 return;
2580
2581 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2582 pixel_size,
2583 &sandybridge_display_srwm_info,
2584 SNB_READ_WM2_LATENCY() * 500,
2585 &sprite_wm);
2586 if (!ret) {
84f44ce7
VS		 2587 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2588 pipe_name(pipe));
b445e3b0
ED		 2589 return;
2590 }
2591 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2592
2593 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2594 pixel_size,
2595 &sandybridge_display_srwm_info,
2596 SNB_READ_WM3_LATENCY() * 500,
2597 &sprite_wm);
2598 if (!ret) {
84f44ce7
VS		 2599 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2600 pipe_name(pipe));
b445e3b0
ED		 2601 return;
2602 }
2603 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2604}
2605
2606/**
2607 * intel_update_watermarks - update FIFO watermark values based on current modes
2608 *
2609 * Calculate watermark values for the various WM regs based on current mode
2610 * and plane configuration.
2611 *
2612 * There are several cases to deal with here:
2613 * - normal (i.e. non-self-refresh)
2614 * - self-refresh (SR) mode
2615 * - lines are large relative to FIFO size (buffer can hold up to 2)
2616 * - lines are small relative to FIFO size (buffer can hold more than 2
2617 * lines), so need to account for TLB latency
2618 *
2619 * The normal calculation is:
2620 * watermark = dotclock * bytes per pixel * latency
2621 * where latency is platform & configuration dependent (we assume pessimal
2622 * values here).
2623 *
2624 * The SR calculation is:
2625 * watermark = (trunc(latency/line time)+1) * surface width *
2626 * bytes per pixel
2627 * where
2628 * line time = htotal / dotclock
2629 * surface width = hdisplay for normal plane and 64 for cursor
2630 * and latency is assumed to be high, as above.
2631 *
2632 * The final value programmed to the register should always be rounded up,
2633 * and include an extra 2 entries to account for clock crossings.
2634 *
2635 * We don't use the sprite, so we can ignore that. And on Crestline we have
2636 * to set the non-SR watermarks to 8.
2637 */
2638void intel_update_watermarks(struct drm_device *dev)
2639{
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641
2642 if (dev_priv->display.update_wm)
2643 dev_priv->display.update_wm(dev);
2644}
2645
2646void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2647 uint32_t sprite_width, int pixel_size,
2648 bool enable)
b445e3b0
ED		 2649{
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651
2652 if (dev_priv->display.update_sprite_wm)
2653 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4c4ff43a 2654 pixel_size, enable);
b445e3b0
ED		 2655}
2656
2b4e57bd
ED		 2657static struct drm_i915_gem_object *
2658intel_alloc_context_page(struct drm_device *dev)
2659{
2660 struct drm_i915_gem_object *ctx;
2661 int ret;
2662
2663 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2664
2665 ctx = i915_gem_alloc_object(dev, 4096);
2666 if (!ctx) {
2667 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2668 return NULL;
2669 }
2670
86a1ee26 2671 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2672 if (ret) {
2673 DRM_ERROR("failed to pin power context: %d\n", ret);
2674 goto err_unref;
2675 }
2676
2677 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2678 if (ret) {
2679 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2680 goto err_unpin;
2681 }
2682
2683 return ctx;
2684
2685err_unpin:
2686 i915_gem_object_unpin(ctx);
2687err_unref:
2688 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2689 return NULL;
2690}
2691
9270388e
DV		 2692/**
2693 * Lock protecting IPS related data structures
9270388e
DV		 2694 */
2695DEFINE_SPINLOCK(mchdev_lock);
2696
2697/* Global for IPS driver to get at the current i915 device. Protected by
2698 * mchdev_lock. */
2699static struct drm_i915_private *i915_mch_dev;
2700
2b4e57bd
ED		 2701bool ironlake_set_drps(struct drm_device *dev, u8 val)
2702{
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 u16 rgvswctl;
2705
9270388e
DV		 2706 assert_spin_locked(&mchdev_lock);
2707
2b4e57bd
ED		 2708 rgvswctl = I915_READ16(MEMSWCTL);
2709 if (rgvswctl & MEMCTL_CMD_STS) {
2710 DRM_DEBUG("gpu busy, RCS change rejected\n");
2711 return false; /* still busy with another command */
2712 }
2713
2714 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2715 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2716 I915_WRITE16(MEMSWCTL, rgvswctl);
2717 POSTING_READ16(MEMSWCTL);
2718
2719 rgvswctl |= MEMCTL_CMD_STS;
2720 I915_WRITE16(MEMSWCTL, rgvswctl);
2721
2722 return true;
2723}
2724
8090c6b9 2725static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2726{
2727 struct drm_i915_private *dev_priv = dev->dev_private;
2728 u32 rgvmodectl = I915_READ(MEMMODECTL);
2729 u8 fmax, fmin, fstart, vstart;
2730
9270388e
DV		 2731 spin_lock_irq(&mchdev_lock);
2732
2b4e57bd
ED		 2733 /* Enable temp reporting */
2734 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2735 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2736
2737 /* 100ms RC evaluation intervals */
2738 I915_WRITE(RCUPEI, 100000);
2739 I915_WRITE(RCDNEI, 100000);
2740
2741 /* Set max/min thresholds to 90ms and 80ms respectively */
2742 I915_WRITE(RCBMAXAVG, 90000);
2743 I915_WRITE(RCBMINAVG, 80000);
2744
2745 I915_WRITE(MEMIHYST, 1);
2746
2747 /* Set up min, max, and cur for interrupt handling */
2748 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2749 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2750 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2751 MEMMODE_FSTART_SHIFT;
2752
2753 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2754 PXVFREQ_PX_SHIFT;
2755
20e4d407
DV		 2756 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2757 dev_priv->ips.fstart = fstart;
2b4e57bd 2758
20e4d407
DV		 2759 dev_priv->ips.max_delay = fstart;
2760 dev_priv->ips.min_delay = fmin;
2761 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2762
2763 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2764 fmax, fmin, fstart);
2765
2766 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2767
2768 /*
2769 * Interrupts will be enabled in ironlake_irq_postinstall
2770 */
2771
2772 I915_WRITE(VIDSTART, vstart);
2773 POSTING_READ(VIDSTART);
2774
2775 rgvmodectl |= MEMMODE_SWMODE_EN;
2776 I915_WRITE(MEMMODECTL, rgvmodectl);
2777
9270388e 2778 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2779 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2780 mdelay(1);
2b4e57bd
ED		 2781
2782 ironlake_set_drps(dev, fstart);
2783
20e4d407 2784 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2785 I915_READ(0x112e0);
20e4d407
DV		 2786 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2787 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2788 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2789
2790 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2791}
2792
8090c6b9 2793static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2794{
2795 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2796 u16 rgvswctl;
2797
2798 spin_lock_irq(&mchdev_lock);
2799
2800 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2801
2802 /* Ack interrupts, disable EFC interrupt */
2803 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2804 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2805 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2806 I915_WRITE(DEIIR, DE_PCU_EVENT);
2807 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2808
2809 /* Go back to the starting frequency */
20e4d407 2810 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2811 mdelay(1);
2b4e57bd
ED		 2812 rgvswctl |= MEMCTL_CMD_STS;
2813 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2814 mdelay(1);
2b4e57bd 2815
9270388e 2816 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2817}
2818
acbe9475
DV		 2819/* There's a funny hw issue where the hw returns all 0 when reading from
2820 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2821 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2822 * all limits and the gpu stuck at whatever frequency it is at atm).
2823 */
65bccb5c 2824static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2825{
7b9e0ae6 2826 u32 limits;
2b4e57bd 2827
7b9e0ae6 2828 limits = 0;
c6a828d3
DV		 2829
2830 if (*val >= dev_priv->rps.max_delay)
2831 *val = dev_priv->rps.max_delay;
2832 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2833
2834 /* Only set the down limit when we've reached the lowest level to avoid
2835 * getting more interrupts, otherwise leave this clear. This prevents a
2836 * race in the hw when coming out of rc6: There's a tiny window where
2837 * the hw runs at the minimal clock before selecting the desired
2838 * frequency, if the down threshold expires in that window we will not
2839 * receive a down interrupt. */
c6a828d3
DV		 2840 if (*val <= dev_priv->rps.min_delay) {
2841 *val = dev_priv->rps.min_delay;
2842 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2843 }
2844
2845 return limits;
2846}
2847
2848void gen6_set_rps(struct drm_device *dev, u8 val)
2849{
2850 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2851 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2852
4fc688ce 2853 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 2854 WARN_ON(val > dev_priv->rps.max_delay);
2855 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2856
c6a828d3 2857 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2858 return;
2859
92bd1bf0
RV		 2860 if (IS_HASWELL(dev))
2861 I915_WRITE(GEN6_RPNSWREQ,
2862 HSW_FREQUENCY(val));
2863 else
2864 I915_WRITE(GEN6_RPNSWREQ,
2865 GEN6_FREQUENCY(val) |
2866 GEN6_OFFSET(0) |
2867 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 2868
2869 /* Make sure we continue to get interrupts
2870 * until we hit the minimum or maximum frequencies.
2871 */
2872 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2873
d5570a72
BW		 2874 POSTING_READ(GEN6_RPNSWREQ);
2875
c6a828d3 2876 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2877
2878 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2879}
2880
0a073b84
JB		 2881void valleyview_set_rps(struct drm_device *dev, u8 val)
2882{
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884 unsigned long timeout = jiffies + msecs_to_jiffies(10);
2885 u32 limits = gen6_rps_limits(dev_priv, &val);
2886 u32 pval;
2887
2888 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2889 WARN_ON(val > dev_priv->rps.max_delay);
2890 WARN_ON(val < dev_priv->rps.min_delay);
2891
2892 DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2893 vlv_gpu_freq(dev_priv->mem_freq,
2894 dev_priv->rps.cur_delay),
2895 vlv_gpu_freq(dev_priv->mem_freq, val));
2896
2897 if (val == dev_priv->rps.cur_delay)
2898 return;
2899
ae99258f 2900 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84
JB		 2901
2902 do {
64936258 2903 pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 2904 if (time_after(jiffies, timeout)) {
2905 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2906 break;
2907 }
2908 udelay(10);
2909 } while (pval & 1);
2910
64936258 2911 pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 2912 if ((pval >> 8) != val)
2913 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2914 val, pval >> 8);
2915
2916 /* Make sure we continue to get interrupts
2917 * until we hit the minimum or maximum frequencies.
2918 */
2919 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2920
2921 dev_priv->rps.cur_delay = pval >> 8;
2922
2923 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2924}
2925
2926
8090c6b9 2927static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2928{
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930
88509484 2931 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2932 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2933 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2934 I915_WRITE(GEN6_PMIER, 0);
2935 /* Complete PM interrupt masking here doesn't race with the rps work
2936 * item again unmasking PM interrupts because that is using a different
2937 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2938 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2939
c6a828d3
DV		 2940 spin_lock_irq(&dev_priv->rps.lock);
2941 dev_priv->rps.pm_iir = 0;
2942 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2943
2944 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2945}
2946
d20d4f0c
JB		 2947static void valleyview_disable_rps(struct drm_device *dev)
2948{
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951 I915_WRITE(GEN6_RC_CONTROL, 0);
2952 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2953 I915_WRITE(GEN6_PMIER, 0);
2954 /* Complete PM interrupt masking here doesn't race with the rps work
2955 * item again unmasking PM interrupts because that is using a different
2956 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2957 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2958
2959 spin_lock_irq(&dev_priv->rps.lock);
2960 dev_priv->rps.pm_iir = 0;
2961 spin_unlock_irq(&dev_priv->rps.lock);
2962
2963 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
c9cddffc
JB		 2964
2965 if (dev_priv->vlv_pctx) {
2966 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2967 dev_priv->vlv_pctx = NULL;
2968 }
d20d4f0c
JB		 2969}
2970
2b4e57bd
ED		 2971int intel_enable_rc6(const struct drm_device *dev)
2972{
456470eb 2973 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2974 if (i915_enable_rc6 >= 0)
2975 return i915_enable_rc6;
2976
6567d748
CW		 2977 /* Disable RC6 on Ironlake */
2978 if (INTEL_INFO(dev)->gen == 5)
2979 return 0;
2b4e57bd 2980
456470eb
DV		 2981 if (IS_HASWELL(dev)) {
2982 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2983 return INTEL_RC6_ENABLE;
456470eb 2984 }
2b4e57bd 2985
456470eb 2986 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2987 if (INTEL_INFO(dev)->gen == 6) {
2988 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2989 return INTEL_RC6_ENABLE;
2990 }
456470eb 2991
2b4e57bd
ED		 2992 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2993 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2994}
2995
79f5b2c7 2996static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2997{
79f5b2c7 2998 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2999 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3000 u32 rp_state_cap;
3001 u32 gt_perf_status;
31643d54 3002 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3003 u32 gtfifodbg;
2b4e57bd 3004 int rc6_mode;
42c0526c 3005 int i, ret;
2b4e57bd 3006
4fc688ce 3007 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3008
2b4e57bd
ED		 3009 /* Here begins a magic sequence of register writes to enable
3010 * auto-downclocking.
3011 *
3012 * Perhaps there might be some value in exposing these to
3013 * userspace...
3014 */
3015 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3016
3017 /* Clear the DBG now so we don't confuse earlier errors */
3018 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3019 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3020 I915_WRITE(GTFIFODBG, gtfifodbg);
3021 }
3022
3023 gen6_gt_force_wake_get(dev_priv);
3024
7b9e0ae6
CW		 3025 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3026 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3027
31c77388
BW		 3028 /* In units of 50MHz */
3029 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3030 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3031 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3032
2b4e57bd
ED		 3033 /* disable the counters and set deterministic thresholds */
3034 I915_WRITE(GEN6_RC_CONTROL, 0);
3035
3036 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3037 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3038 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3039 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3040 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3041
b4519513
CW		 3042 for_each_ring(ring, dev_priv, i)
3043 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3044
3045 I915_WRITE(GEN6_RC_SLEEP, 0);
3046 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3047 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3048 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3049 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3050
5a7dc92a 3051 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3052 rc6_mode = intel_enable_rc6(dev_priv->dev);
3053 if (rc6_mode & INTEL_RC6_ENABLE)
3054 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3055
5a7dc92a
ED		 3056 /* We don't use those on Haswell */
3057 if (!IS_HASWELL(dev)) {
3058 if (rc6_mode & INTEL_RC6p_ENABLE)
3059 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3060
5a7dc92a
ED		 3061 if (rc6_mode & INTEL_RC6pp_ENABLE)
3062 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3063 }
2b4e57bd
ED		 3064
3065 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3066 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3067 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3068 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3069
3070 I915_WRITE(GEN6_RC_CONTROL,
3071 rc6_mask |
3072 GEN6_RC_CTL_EI_MODE(1) |
3073 GEN6_RC_CTL_HW_ENABLE);
3074
92bd1bf0
RV		 3075 if (IS_HASWELL(dev)) {
3076 I915_WRITE(GEN6_RPNSWREQ,
3077 HSW_FREQUENCY(10));
3078 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3079 HSW_FREQUENCY(12));
3080 } else {
3081 I915_WRITE(GEN6_RPNSWREQ,
3082 GEN6_FREQUENCY(10) |
3083 GEN6_OFFSET(0) |
3084 GEN6_AGGRESSIVE_TURBO);
3085 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3086 GEN6_FREQUENCY(12));
3087 }
2b4e57bd
ED		 3088
3089 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3090 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3091 dev_priv->rps.max_delay << 24 |
3092 dev_priv->rps.min_delay << 16);
5a7dc92a 3093
1ee9ae32
DV		 3094 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3095 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3096 I915_WRITE(GEN6_RP_UP_EI, 66000);
3097 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3098
2b4e57bd
ED		 3099 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3100 I915_WRITE(GEN6_RP_CONTROL,
3101 GEN6_RP_MEDIA_TURBO |
89ba829e 3102 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3103 GEN6_RP_MEDIA_IS_GFX |
3104 GEN6_RP_ENABLE |
3105 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3106 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3107
42c0526c 3108 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3109 if (!ret) {
42c0526c
BW		 3110 pcu_mbox = 0;
3111 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3112 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3113 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3114 (dev_priv->rps.max_delay & 0xff) * 50,
3115 (pcu_mbox & 0xff) * 50);
31c77388 3116 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3117 }
3118 } else {
3119 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3120 }
3121
7b9e0ae6 3122 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 3123
3124 /* requires MSI enabled */
ff928261 3125 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 3126 spin_lock_irq(&dev_priv->rps.lock);
3127 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 3128 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 3129 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 3130 /* enable all PM interrupts */
3131 I915_WRITE(GEN6_PMINTRMSK, 0);
3132
31643d54
BW		 3133 rc6vids = 0;
3134 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3135 if (IS_GEN6(dev) && ret) {
3136 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3137 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3138 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3139 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3140 rc6vids &= 0xffff00;
3141 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3142 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3143 if (ret)
3144 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3145 }
3146
2b4e57bd 3147 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3148}
3149
79f5b2c7 3150static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3151{
79f5b2c7 3152 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3153 int min_freq = 15;
3ebecd07
CW		 3154 unsigned int gpu_freq;
3155 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3156 int scaling_factor = 180;
3157
4fc688ce 3158 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3159
2b4e57bd
ED		 3160 max_ia_freq = cpufreq_quick_get_max(0);
3161 /*
3162 * Default to measured freq if none found, PCU will ensure we don't go
3163 * over
3164 */
3165 if (!max_ia_freq)
3166 max_ia_freq = tsc_khz;
3167
3168 /* Convert from kHz to MHz */
3169 max_ia_freq /= 1000;
3170
3ebecd07
CW		 3171 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3172 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3173 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3174
2b4e57bd
ED		 3175 /*
3176 * For each potential GPU frequency, load a ring frequency we'd like
3177 * to use for memory access. We do this by specifying the IA frequency
3178 * the PCU should use as a reference to determine the ring frequency.
3179 */
c6a828d3 3180 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3181 gpu_freq--) {
c6a828d3 3182 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3183 unsigned int ia_freq = 0, ring_freq = 0;
3184
3185 if (IS_HASWELL(dev)) {
3186 ring_freq = (gpu_freq * 5 + 3) / 4;
3187 ring_freq = max(min_ring_freq, ring_freq);
3188 /* leave ia_freq as the default, chosen by cpufreq */
3189 } else {
3190 /* On older processors, there is no separate ring
3191 * clock domain, so in order to boost the bandwidth
3192 * of the ring, we need to upclock the CPU (ia_freq).
3193 *
3194 * For GPU frequencies less than 750MHz,
3195 * just use the lowest ring freq.
3196 */
3197 if (gpu_freq < min_freq)
3198 ia_freq = 800;
3199 else
3200 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3201 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3202 }
2b4e57bd 3203
42c0526c
BW		 3204 sandybridge_pcode_write(dev_priv,
3205 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3206 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3207 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3208 gpu_freq);
2b4e57bd 3209 }
2b4e57bd
ED		 3210}
3211
0a073b84
JB		 3212int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3213{
3214 u32 val, rp0;
3215
64936258 3216 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3217
3218 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3219 /* Clamp to max */
3220 rp0 = min_t(u32, rp0, 0xea);
3221
3222 return rp0;
3223}
3224
3225static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3226{
3227 u32 val, rpe;
3228
64936258 3229 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3230 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3231 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3232 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3233
3234 return rpe;
3235}
3236
3237int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3238{
64936258 3239 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3240}
3241
52ceb908
JB		 3242static void vlv_rps_timer_work(struct work_struct *work)
3243{
3244 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3245 rps.vlv_work.work);
3246
3247 /*
3248 * Timer fired, we must be idle. Drop to min voltage state.
3249 * Note: we use RPe here since it should match the
3250 * Vmin we were shooting for. That should give us better
3251 * perf when we come back out of RC6 than if we used the
3252 * min freq available.
3253 */
3254 mutex_lock(&dev_priv->rps.hw_lock);
3255 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3256 mutex_unlock(&dev_priv->rps.hw_lock);
3257}
3258
c9cddffc
JB		 3259static void valleyview_setup_pctx(struct drm_device *dev)
3260{
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct drm_i915_gem_object *pctx;
3263 unsigned long pctx_paddr;
3264 u32 pcbr;
3265 int pctx_size = 24*1024;
3266
3267 pcbr = I915_READ(VLV_PCBR);
3268 if (pcbr) {
3269 /* BIOS set it up already, grab the pre-alloc'd space */
3270 int pcbr_offset;
3271
3272 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3273 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3274 pcbr_offset,
3727d55e 3275 -1,
c9cddffc
JB		 3276 pctx_size);
3277 goto out;
3278 }
3279
3280 /*
3281 * From the Gunit register HAS:
3282 * The Gfx driver is expected to program this register and ensure
3283 * proper allocation within Gfx stolen memory. For example, this
3284 * register should be programmed such than the PCBR range does not
3285 * overlap with other ranges, such as the frame buffer, protected
3286 * memory, or any other relevant ranges.
3287 */
3288 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3289 if (!pctx) {
3290 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3291 return;
3292 }
3293
3294 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3295 I915_WRITE(VLV_PCBR, pctx_paddr);
3296
3297out:
3298 dev_priv->vlv_pctx = pctx;
3299}
3300
0a073b84
JB		 3301static void valleyview_enable_rps(struct drm_device *dev)
3302{
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304 struct intel_ring_buffer *ring;
3305 u32 gtfifodbg, val, rpe;
3306 int i;
3307
3308 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3309
3310 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3311 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3312 I915_WRITE(GTFIFODBG, gtfifodbg);
3313 }
3314
c9cddffc
JB		 3315 valleyview_setup_pctx(dev);
3316
0a073b84
JB		 3317 gen6_gt_force_wake_get(dev_priv);
3318
3319 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3320 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3321 I915_WRITE(GEN6_RP_UP_EI, 66000);
3322 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3323
3324 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3325
3326 I915_WRITE(GEN6_RP_CONTROL,
3327 GEN6_RP_MEDIA_TURBO |
3328 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3329 GEN6_RP_MEDIA_IS_GFX |
3330 GEN6_RP_ENABLE |
3331 GEN6_RP_UP_BUSY_AVG |
3332 GEN6_RP_DOWN_IDLE_CONT);
3333
3334 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3335 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3336 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3337
3338 for_each_ring(ring, dev_priv, i)
3339 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3340
3341 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3342
3343 /* allows RC6 residency counter to work */
3344 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3345 I915_WRITE(GEN6_RC_CONTROL,
3346 GEN7_RC_CTL_TO_MODE);
3347
64936258 3348 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3349 switch ((val >> 6) & 3) {
3350 case 0:
3351 case 1:
3352 dev_priv->mem_freq = 800;
3353 break;
3354 case 2:
3355 dev_priv->mem_freq = 1066;
3356 break;
3357 case 3:
3358 dev_priv->mem_freq = 1333;
3359 break;
3360 }
0a073b84
JB		 3361 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3362
3363 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3364 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3365
3366 DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3367 vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3368 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3369
3370 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3371 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3372 DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3373 dev_priv->rps.max_delay));
3374
3375 rpe = valleyview_rps_rpe_freq(dev_priv);
3376 DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3377 vlv_gpu_freq(dev_priv->mem_freq, rpe));
52ceb908 3378 dev_priv->rps.rpe_delay = rpe;
0a073b84
JB		 3379
3380 val = valleyview_rps_min_freq(dev_priv);
3381 DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3382 val));
3383 dev_priv->rps.min_delay = val;
3384
3385 DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3386 vlv_gpu_freq(dev_priv->mem_freq, rpe));
3387
52ceb908
JB		 3388 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3389
0a073b84
JB		 3390 valleyview_set_rps(dev_priv->dev, rpe);
3391
3392 /* requires MSI enabled */
3393 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3394 spin_lock_irq(&dev_priv->rps.lock);
3395 WARN_ON(dev_priv->rps.pm_iir != 0);
3396 I915_WRITE(GEN6_PMIMR, 0);
3397 spin_unlock_irq(&dev_priv->rps.lock);
3398 /* enable all PM interrupts */
3399 I915_WRITE(GEN6_PMINTRMSK, 0);
3400
3401 gen6_gt_force_wake_put(dev_priv);
3402}
3403
930ebb46 3404void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3405{
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407
3e373948
DV		 3408 if (dev_priv->ips.renderctx) {
3409 i915_gem_object_unpin(dev_priv->ips.renderctx);
3410 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3411 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3412 }
3413
3e373948
DV		 3414 if (dev_priv->ips.pwrctx) {
3415 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3416 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3417 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3418 }
3419}
3420
930ebb46 3421static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3422{
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424
3425 if (I915_READ(PWRCTXA)) {
3426 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3427 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3428 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3429 50);
3430
3431 I915_WRITE(PWRCTXA, 0);
3432 POSTING_READ(PWRCTXA);
3433
3434 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3435 POSTING_READ(RSTDBYCTL);
3436 }
2b4e57bd
ED		 3437}
3438
3439static int ironlake_setup_rc6(struct drm_device *dev)
3440{
3441 struct drm_i915_private *dev_priv = dev->dev_private;
3442
3e373948
DV		 3443 if (dev_priv->ips.renderctx == NULL)
3444 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3445 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3446 return -ENOMEM;
3447
3e373948
DV		 3448 if (dev_priv->ips.pwrctx == NULL)
3449 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3450 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3451 ironlake_teardown_rc6(dev);
3452 return -ENOMEM;
3453 }
3454
3455 return 0;
3456}
3457
930ebb46 3458static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3459{
3460 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3461 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3462 bool was_interruptible;
2b4e57bd
ED		 3463 int ret;
3464
3465 /* rc6 disabled by default due to repeated reports of hanging during
3466 * boot and resume.
3467 */
3468 if (!intel_enable_rc6(dev))
3469 return;
3470
79f5b2c7
DV		 3471 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3472
2b4e57bd 3473 ret = ironlake_setup_rc6(dev);
79f5b2c7 3474 if (ret)
2b4e57bd 3475 return;
2b4e57bd 3476
3e960501
CW		 3477 was_interruptible = dev_priv->mm.interruptible;
3478 dev_priv->mm.interruptible = false;
3479
2b4e57bd
ED		 3480 /*
3481 * GPU can automatically power down the render unit if given a page
3482 * to save state.
3483 */
6d90c952 3484 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3485 if (ret) {
3486 ironlake_teardown_rc6(dev);
3e960501 3487 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3488 return;
3489 }
3490
6d90c952
DV		 3491 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3492 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 3493 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 3494 MI_MM_SPACE_GTT |
3495 MI_SAVE_EXT_STATE_EN |
3496 MI_RESTORE_EXT_STATE_EN |
3497 MI_RESTORE_INHIBIT);
3498 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3499 intel_ring_emit(ring, MI_NOOP);
3500 intel_ring_emit(ring, MI_FLUSH);
3501 intel_ring_advance(ring);
2b4e57bd
ED		 3502
3503 /*
3504 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3505 * does an implicit flush, combined with MI_FLUSH above, it should be
3506 * safe to assume that renderctx is valid
3507 */
3e960501
CW		 3508 ret = intel_ring_idle(ring);
3509 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3510 if (ret) {
def27a58 3511 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3512 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3513 return;
3514 }
3515
3e373948 3516 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 3517 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3518}
3519
dde18883
ED		 3520static unsigned long intel_pxfreq(u32 vidfreq)
3521{
3522 unsigned long freq;
3523 int div = (vidfreq & 0x3f0000) >> 16;
3524 int post = (vidfreq & 0x3000) >> 12;
3525 int pre = (vidfreq & 0x7);
3526
3527 if (!pre)
3528 return 0;
3529
3530 freq = ((div * 133333) / ((1<<post) * pre));
3531
3532 return freq;
3533}
3534
eb48eb00
DV		 3535static const struct cparams {
3536 u16 i;
3537 u16 t;
3538 u16 m;
3539 u16 c;
3540} cparams[] = {
3541 { 1, 1333, 301, 28664 },
3542 { 1, 1066, 294, 24460 },
3543 { 1, 800, 294, 25192 },
3544 { 0, 1333, 276, 27605 },
3545 { 0, 1066, 276, 27605 },
3546 { 0, 800, 231, 23784 },
3547};
3548
f531dcb2 3549static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3550{
3551 u64 total_count, diff, ret;
3552 u32 count1, count2, count3, m = 0, c = 0;
3553 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3554 int i;
3555
02d71956
DV		 3556 assert_spin_locked(&mchdev_lock);
3557
20e4d407 3558 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3559
3560 /* Prevent division-by-zero if we are asking too fast.
3561 * Also, we don't get interesting results if we are polling
3562 * faster than once in 10ms, so just return the saved value
3563 * in such cases.
3564 */
3565 if (diff1 <= 10)
20e4d407 3566 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3567
3568 count1 = I915_READ(DMIEC);
3569 count2 = I915_READ(DDREC);
3570 count3 = I915_READ(CSIEC);
3571
3572 total_count = count1 + count2 + count3;
3573
3574 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3575 if (total_count < dev_priv->ips.last_count1) {
3576 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3577 diff += total_count;
3578 } else {
20e4d407 3579 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3580 }
3581
3582 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3583 if (cparams[i].i == dev_priv->ips.c_m &&
3584 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3585 m = cparams[i].m;
3586 c = cparams[i].c;
3587 break;
3588 }
3589 }
3590
3591 diff = div_u64(diff, diff1);
3592 ret = ((m * diff) + c);
3593 ret = div_u64(ret, 10);
3594
20e4d407
DV		 3595 dev_priv->ips.last_count1 = total_count;
3596 dev_priv->ips.last_time1 = now;
eb48eb00 3597
20e4d407 3598 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3599
3600 return ret;
3601}
3602
f531dcb2
CW		 3603unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3604{
3605 unsigned long val;
3606
3607 if (dev_priv->info->gen != 5)
3608 return 0;
3609
3610 spin_lock_irq(&mchdev_lock);
3611
3612 val = __i915_chipset_val(dev_priv);
3613
3614 spin_unlock_irq(&mchdev_lock);
3615
3616 return val;
3617}
3618
eb48eb00
DV		 3619unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3620{
3621 unsigned long m, x, b;
3622 u32 tsfs;
3623
3624 tsfs = I915_READ(TSFS);
3625
3626 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3627 x = I915_READ8(TR1);
3628
3629 b = tsfs & TSFS_INTR_MASK;
3630
3631 return ((m * x) / 127) - b;
3632}
3633
3634static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3635{
3636 static const struct v_table {
3637 u16 vd; /* in .1 mil */
3638 u16 vm; /* in .1 mil */
3639 } v_table[] = {
3640 { 0, 0, },
3641 { 375, 0, },
3642 { 500, 0, },
3643 { 625, 0, },
3644 { 750, 0, },
3645 { 875, 0, },
3646 { 1000, 0, },
3647 { 1125, 0, },
3648 { 4125, 3000, },
3649 { 4125, 3000, },
3650 { 4125, 3000, },
3651 { 4125, 3000, },
3652 { 4125, 3000, },
3653 { 4125, 3000, },
3654 { 4125, 3000, },
3655 { 4125, 3000, },
3656 { 4125, 3000, },
3657 { 4125, 3000, },
3658 { 4125, 3000, },
3659 { 4125, 3000, },
3660 { 4125, 3000, },
3661 { 4125, 3000, },
3662 { 4125, 3000, },
3663 { 4125, 3000, },
3664 { 4125, 3000, },
3665 { 4125, 3000, },
3666 { 4125, 3000, },
3667 { 4125, 3000, },
3668 { 4125, 3000, },
3669 { 4125, 3000, },
3670 { 4125, 3000, },
3671 { 4125, 3000, },
3672 { 4250, 3125, },
3673 { 4375, 3250, },
3674 { 4500, 3375, },
3675 { 4625, 3500, },
3676 { 4750, 3625, },
3677 { 4875, 3750, },
3678 { 5000, 3875, },
3679 { 5125, 4000, },
3680 { 5250, 4125, },
3681 { 5375, 4250, },
3682 { 5500, 4375, },
3683 { 5625, 4500, },
3684 { 5750, 4625, },
3685 { 5875, 4750, },
3686 { 6000, 4875, },
3687 { 6125, 5000, },
3688 { 6250, 5125, },
3689 { 6375, 5250, },
3690 { 6500, 5375, },
3691 { 6625, 5500, },
3692 { 6750, 5625, },
3693 { 6875, 5750, },
3694 { 7000, 5875, },
3695 { 7125, 6000, },
3696 { 7250, 6125, },
3697 { 7375, 6250, },
3698 { 7500, 6375, },
3699 { 7625, 6500, },
3700 { 7750, 6625, },
3701 { 7875, 6750, },
3702 { 8000, 6875, },
3703 { 8125, 7000, },
3704 { 8250, 7125, },
3705 { 8375, 7250, },
3706 { 8500, 7375, },
3707 { 8625, 7500, },
3708 { 8750, 7625, },
3709 { 8875, 7750, },
3710 { 9000, 7875, },
3711 { 9125, 8000, },
3712 { 9250, 8125, },
3713 { 9375, 8250, },
3714 { 9500, 8375, },
3715 { 9625, 8500, },
3716 { 9750, 8625, },
3717 { 9875, 8750, },
3718 { 10000, 8875, },
3719 { 10125, 9000, },
3720 { 10250, 9125, },
3721 { 10375, 9250, },
3722 { 10500, 9375, },
3723 { 10625, 9500, },
3724 { 10750, 9625, },
3725 { 10875, 9750, },
3726 { 11000, 9875, },
3727 { 11125, 10000, },
3728 { 11250, 10125, },
3729 { 11375, 10250, },
3730 { 11500, 10375, },
3731 { 11625, 10500, },
3732 { 11750, 10625, },
3733 { 11875, 10750, },
3734 { 12000, 10875, },
3735 { 12125, 11000, },
3736 { 12250, 11125, },
3737 { 12375, 11250, },
3738 { 12500, 11375, },
3739 { 12625, 11500, },
3740 { 12750, 11625, },
3741 { 12875, 11750, },
3742 { 13000, 11875, },
3743 { 13125, 12000, },
3744 { 13250, 12125, },
3745 { 13375, 12250, },
3746 { 13500, 12375, },
3747 { 13625, 12500, },
3748 { 13750, 12625, },
3749 { 13875, 12750, },
3750 { 14000, 12875, },
3751 { 14125, 13000, },
3752 { 14250, 13125, },
3753 { 14375, 13250, },
3754 { 14500, 13375, },
3755 { 14625, 13500, },
3756 { 14750, 13625, },
3757 { 14875, 13750, },
3758 { 15000, 13875, },
3759 { 15125, 14000, },
3760 { 15250, 14125, },
3761 { 15375, 14250, },
3762 { 15500, 14375, },
3763 { 15625, 14500, },
3764 { 15750, 14625, },
3765 { 15875, 14750, },
3766 { 16000, 14875, },
3767 { 16125, 15000, },
3768 };
3769 if (dev_priv->info->is_mobile)
3770 return v_table[pxvid].vm;
3771 else
3772 return v_table[pxvid].vd;
3773}
3774
02d71956 3775static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3776{
3777 struct timespec now, diff1;
3778 u64 diff;
3779 unsigned long diffms;
3780 u32 count;
3781
02d71956 3782 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3783
3784 getrawmonotonic(&now);
20e4d407 3785 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3786
3787 /* Don't divide by 0 */
3788 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3789 if (!diffms)
3790 return;
3791
3792 count = I915_READ(GFXEC);
3793
20e4d407
DV		 3794 if (count < dev_priv->ips.last_count2) {
3795 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 3796 diff += count;
3797 } else {
20e4d407 3798 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 3799 }
3800
20e4d407
DV		 3801 dev_priv->ips.last_count2 = count;
3802 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 3803
3804 /* More magic constants... */
3805 diff = diff * 1181;
3806 diff = div_u64(diff, diffms * 10);
20e4d407 3807 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 3808}
3809
02d71956
DV		 3810void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3811{
3812 if (dev_priv->info->gen != 5)
3813 return;
3814
9270388e 3815 spin_lock_irq(&mchdev_lock);
02d71956
DV		 3816
3817 __i915_update_gfx_val(dev_priv);
3818
9270388e 3819 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3820}
3821
f531dcb2 3822static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3823{
3824 unsigned long t, corr, state1, corr2, state2;
3825 u32 pxvid, ext_v;
3826
02d71956
DV		 3827 assert_spin_locked(&mchdev_lock);
3828
c6a828d3 3829 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3830 pxvid = (pxvid >> 24) & 0x7f;
3831 ext_v = pvid_to_extvid(dev_priv, pxvid);
3832
3833 state1 = ext_v;
3834
3835 t = i915_mch_val(dev_priv);
3836
3837 /* Revel in the empirically derived constants */
3838
3839 /* Correction factor in 1/100000 units */
3840 if (t > 80)
3841 corr = ((t * 2349) + 135940);
3842 else if (t >= 50)
3843 corr = ((t * 964) + 29317);
3844 else /* < 50 */
3845 corr = ((t * 301) + 1004);
3846
3847 corr = corr * ((150142 * state1) / 10000 - 78642);
3848 corr /= 100000;
20e4d407 3849 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3850
3851 state2 = (corr2 * state1) / 10000;
3852 state2 /= 100; /* convert to mW */
3853
02d71956 3854 __i915_update_gfx_val(dev_priv);
eb48eb00 3855
20e4d407 3856 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3857}
3858
f531dcb2
CW		 3859unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3860{
3861 unsigned long val;
3862
3863 if (dev_priv->info->gen != 5)
3864 return 0;
3865
3866 spin_lock_irq(&mchdev_lock);
3867
3868 val = __i915_gfx_val(dev_priv);
3869
3870 spin_unlock_irq(&mchdev_lock);
3871
3872 return val;
3873}
3874
eb48eb00
DV		 3875/**
3876 * i915_read_mch_val - return value for IPS use
3877 *
3878 * Calculate and return a value for the IPS driver to use when deciding whether
3879 * we have thermal and power headroom to increase CPU or GPU power budget.
3880 */
3881unsigned long i915_read_mch_val(void)
3882{
3883 struct drm_i915_private *dev_priv;
3884 unsigned long chipset_val, graphics_val, ret = 0;
3885
9270388e 3886 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3887 if (!i915_mch_dev)
3888 goto out_unlock;
3889 dev_priv = i915_mch_dev;
3890
f531dcb2
CW		 3891 chipset_val = __i915_chipset_val(dev_priv);
3892 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3893
3894 ret = chipset_val + graphics_val;
3895
3896out_unlock:
9270388e 3897 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3898
3899 return ret;
3900}
3901EXPORT_SYMBOL_GPL(i915_read_mch_val);
3902
3903/**
3904 * i915_gpu_raise - raise GPU frequency limit
3905 *
3906 * Raise the limit; IPS indicates we have thermal headroom.
3907 */
3908bool i915_gpu_raise(void)
3909{
3910 struct drm_i915_private *dev_priv;
3911 bool ret = true;
3912
9270388e 3913 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3914 if (!i915_mch_dev) {
3915 ret = false;
3916 goto out_unlock;
3917 }
3918 dev_priv = i915_mch_dev;
3919
20e4d407
DV		 3920 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3921 dev_priv->ips.max_delay--;
eb48eb00
DV		 3922
3923out_unlock:
9270388e 3924 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3925
3926 return ret;
3927}
3928EXPORT_SYMBOL_GPL(i915_gpu_raise);
3929
3930/**
3931 * i915_gpu_lower - lower GPU frequency limit
3932 *
3933 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3934 * frequency maximum.
3935 */
3936bool i915_gpu_lower(void)
3937{
3938 struct drm_i915_private *dev_priv;
3939 bool ret = true;
3940
9270388e 3941 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3942 if (!i915_mch_dev) {
3943 ret = false;
3944 goto out_unlock;
3945 }
3946 dev_priv = i915_mch_dev;
3947
20e4d407
DV		 3948 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3949 dev_priv->ips.max_delay++;
eb48eb00
DV		 3950
3951out_unlock:
9270388e 3952 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3953
3954 return ret;
3955}
3956EXPORT_SYMBOL_GPL(i915_gpu_lower);
3957
3958/**
3959 * i915_gpu_busy - indicate GPU business to IPS
3960 *
3961 * Tell the IPS driver whether or not the GPU is busy.
3962 */
3963bool i915_gpu_busy(void)
3964{
3965 struct drm_i915_private *dev_priv;
f047e395 3966 struct intel_ring_buffer *ring;
eb48eb00 3967 bool ret = false;
f047e395 3968 int i;
eb48eb00 3969
9270388e 3970 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3971 if (!i915_mch_dev)
3972 goto out_unlock;
3973 dev_priv = i915_mch_dev;
3974
f047e395
CW		 3975 for_each_ring(ring, dev_priv, i)
3976 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3977
3978out_unlock:
9270388e 3979 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3980
3981 return ret;
3982}
3983EXPORT_SYMBOL_GPL(i915_gpu_busy);
3984
3985/**
3986 * i915_gpu_turbo_disable - disable graphics turbo
3987 *
3988 * Disable graphics turbo by resetting the max frequency and setting the
3989 * current frequency to the default.
3990 */
3991bool i915_gpu_turbo_disable(void)
3992{
3993 struct drm_i915_private *dev_priv;
3994 bool ret = true;
3995
9270388e 3996 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3997 if (!i915_mch_dev) {
3998 ret = false;
3999 goto out_unlock;
4000 }
4001 dev_priv = i915_mch_dev;
4002
20e4d407 4003 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4004
20e4d407 4005 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4006 ret = false;
4007
4008out_unlock:
9270388e 4009 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4010
4011 return ret;
4012}
4013EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4014
4015/**
4016 * Tells the intel_ips driver that the i915 driver is now loaded, if
4017 * IPS got loaded first.
4018 *
4019 * This awkward dance is so that neither module has to depend on the
4020 * other in order for IPS to do the appropriate communication of
4021 * GPU turbo limits to i915.
4022 */
4023static void
4024ips_ping_for_i915_load(void)
4025{
4026 void (*link)(void);
4027
4028 link = symbol_get(ips_link_to_i915_driver);
4029 if (link) {
4030 link();
4031 symbol_put(ips_link_to_i915_driver);
4032 }
4033}
4034
4035void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4036{
02d71956
DV		 4037 /* We only register the i915 ips part with intel-ips once everything is
4038 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4039 spin_lock_irq(&mchdev_lock);
eb48eb00 4040 i915_mch_dev = dev_priv;
9270388e 4041 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4042
4043 ips_ping_for_i915_load();
4044}
4045
4046void intel_gpu_ips_teardown(void)
4047{
9270388e 4048 spin_lock_irq(&mchdev_lock);
eb48eb00 4049 i915_mch_dev = NULL;
9270388e 4050 spin_unlock_irq(&mchdev_lock);
eb48eb00 4051}
8090c6b9 4052static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4053{
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 u32 lcfuse;
4056 u8 pxw[16];
4057 int i;
4058
4059 /* Disable to program */
4060 I915_WRITE(ECR, 0);
4061 POSTING_READ(ECR);
4062
4063 /* Program energy weights for various events */
4064 I915_WRITE(SDEW, 0x15040d00);
4065 I915_WRITE(CSIEW0, 0x007f0000);
4066 I915_WRITE(CSIEW1, 0x1e220004);
4067 I915_WRITE(CSIEW2, 0x04000004);
4068
4069 for (i = 0; i < 5; i++)
4070 I915_WRITE(PEW + (i * 4), 0);
4071 for (i = 0; i < 3; i++)
4072 I915_WRITE(DEW + (i * 4), 0);
4073
4074 /* Program P-state weights to account for frequency power adjustment */
4075 for (i = 0; i < 16; i++) {
4076 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4077 unsigned long freq = intel_pxfreq(pxvidfreq);
4078 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4079 PXVFREQ_PX_SHIFT;
4080 unsigned long val;
4081
4082 val = vid * vid;
4083 val *= (freq / 1000);
4084 val *= 255;
4085 val /= (127*127*900);
4086 if (val > 0xff)
4087 DRM_ERROR("bad pxval: %ld\n", val);
4088 pxw[i] = val;
4089 }
4090 /* Render standby states get 0 weight */
4091 pxw[14] = 0;
4092 pxw[15] = 0;
4093
4094 for (i = 0; i < 4; i++) {
4095 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4096 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4097 I915_WRITE(PXW + (i * 4), val);
4098 }
4099
4100 /* Adjust magic regs to magic values (more experimental results) */
4101 I915_WRITE(OGW0, 0);
4102 I915_WRITE(OGW1, 0);
4103 I915_WRITE(EG0, 0x00007f00);
4104 I915_WRITE(EG1, 0x0000000e);
4105 I915_WRITE(EG2, 0x000e0000);
4106 I915_WRITE(EG3, 0x68000300);
4107 I915_WRITE(EG4, 0x42000000);
4108 I915_WRITE(EG5, 0x00140031);
4109 I915_WRITE(EG6, 0);
4110 I915_WRITE(EG7, 0);
4111
4112 for (i = 0; i < 8; i++)
4113 I915_WRITE(PXWL + (i * 4), 0);
4114
4115 /* Enable PMON + select events */
4116 I915_WRITE(ECR, 0x80000019);
4117
4118 lcfuse = I915_READ(LCFUSE02);
4119
20e4d407 4120 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4121}
4122
8090c6b9
DV		 4123void intel_disable_gt_powersave(struct drm_device *dev)
4124{
1a01ab3b
JB		 4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126
fd0c0642
DV		 4127 /* Interrupts should be disabled already to avoid re-arming. */
4128 WARN_ON(dev->irq_enabled);
4129
930ebb46 4130 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4131 ironlake_disable_drps(dev);
930ebb46 4132 ironlake_disable_rc6(dev);
0a073b84 4133 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4134 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4135 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4136 if (IS_VALLEYVIEW(dev))
4137 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4138 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4139 if (IS_VALLEYVIEW(dev))
4140 valleyview_disable_rps(dev);
4141 else
4142 gen6_disable_rps(dev);
4fc688ce 4143 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4144 }
8090c6b9
DV		 4145}
4146
1a01ab3b
JB		 4147static void intel_gen6_powersave_work(struct work_struct *work)
4148{
4149 struct drm_i915_private *dev_priv =
4150 container_of(work, struct drm_i915_private,
4151 rps.delayed_resume_work.work);
4152 struct drm_device *dev = dev_priv->dev;
4153
4fc688ce 4154 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4155
4156 if (IS_VALLEYVIEW(dev)) {
4157 valleyview_enable_rps(dev);
4158 } else {
4159 gen6_enable_rps(dev);
4160 gen6_update_ring_freq(dev);
4161 }
4fc688ce 4162 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4163}
4164
8090c6b9
DV		 4165void intel_enable_gt_powersave(struct drm_device *dev)
4166{
1a01ab3b
JB		 4167 struct drm_i915_private *dev_priv = dev->dev_private;
4168
8090c6b9
DV		 4169 if (IS_IRONLAKE_M(dev)) {
4170 ironlake_enable_drps(dev);
4171 ironlake_enable_rc6(dev);
4172 intel_init_emon(dev);
0a073b84 4173 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4174 /*
4175 * PCU communication is slow and this doesn't need to be
4176 * done at any specific time, so do this out of our fast path
4177 * to make resume and init faster.
4178 */
4179 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4180 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4181 }
4182}
4183
3107bd48
DV		 4184static void ibx_init_clock_gating(struct drm_device *dev)
4185{
4186 struct drm_i915_private *dev_priv = dev->dev_private;
4187
4188 /*
4189 * On Ibex Peak and Cougar Point, we need to disable clock
4190 * gating for the panel power sequencer or it will fail to
4191 * start up when no ports are active.
4192 */
4193 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4194}
4195
1fa61106 4196static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4197{
4198 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4199 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 4200
4201 /* Required for FBC */
4d47e4f5
DL		 4202 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4203 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4204 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4205
4206 I915_WRITE(PCH_3DCGDIS0,
4207 MARIUNIT_CLOCK_GATE_DISABLE |
4208 SVSMUNIT_CLOCK_GATE_DISABLE);
4209 I915_WRITE(PCH_3DCGDIS1,
4210 VFMUNIT_CLOCK_GATE_DISABLE);
4211
6f1d69b0
ED		 4212 /*
4213 * According to the spec the following bits should be set in
4214 * order to enable memory self-refresh
4215 * The bit 22/21 of 0x42004
4216 * The bit 5 of 0x42020
4217 * The bit 15 of 0x45000
4218 */
4219 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4220 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4221 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4222 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4223 I915_WRITE(DISP_ARB_CTL,
4224 (I915_READ(DISP_ARB_CTL) |
4225 DISP_FBC_WM_DIS));
4226 I915_WRITE(WM3_LP_ILK, 0);
4227 I915_WRITE(WM2_LP_ILK, 0);
4228 I915_WRITE(WM1_LP_ILK, 0);
4229
4230 /*
4231 * Based on the document from hardware guys the following bits
4232 * should be set unconditionally in order to enable FBC.
4233 * The bit 22 of 0x42000
4234 * The bit 22 of 0x42004
4235 * The bit 7,8,9 of 0x42020.
4236 */
4237 if (IS_IRONLAKE_M(dev)) {
4238 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4239 I915_READ(ILK_DISPLAY_CHICKEN1) |
4240 ILK_FBCQ_DIS);
4241 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4242 I915_READ(ILK_DISPLAY_CHICKEN2) |
4243 ILK_DPARB_GATE);
6f1d69b0
ED		 4244 }
4245
4d47e4f5
DL		 4246 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4247
6f1d69b0
ED		 4248 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4249 I915_READ(ILK_DISPLAY_CHICKEN2) |
4250 ILK_ELPIN_409_SELECT);
4251 I915_WRITE(_3D_CHICKEN2,
4252 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4253 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4254
ecdb4eb7 4255 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4256 I915_WRITE(CACHE_MODE_0,
4257 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 4258
4259 ibx_init_clock_gating(dev);
4260}
4261
4262static void cpt_init_clock_gating(struct drm_device *dev)
4263{
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 int pipe;
3f704fa2 4266 uint32_t val;
3107bd48
DV		 4267
4268 /*
4269 * On Ibex Peak and Cougar Point, we need to disable clock
4270 * gating for the panel power sequencer or it will fail to
4271 * start up when no ports are active.
4272 */
4273 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4274 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4275 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4276 /* The below fixes the weird display corruption, a few pixels shifted
4277 * downward, on (only) LVDS of some HP laptops with IVY.
4278 */
3f704fa2 4279 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4280 val = I915_READ(TRANS_CHICKEN2(pipe));
4281 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4282 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4283 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4284 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4285 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4286 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4287 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4288 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4289 }
3107bd48
DV		 4290 /* WADP0ClockGatingDisable */
4291 for_each_pipe(pipe) {
4292 I915_WRITE(TRANS_CHICKEN1(pipe),
4293 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4294 }
6f1d69b0
ED		 4295}
4296
1d7aaa0c
DV		 4297static void gen6_check_mch_setup(struct drm_device *dev)
4298{
4299 struct drm_i915_private *dev_priv = dev->dev_private;
4300 uint32_t tmp;
4301
4302 tmp = I915_READ(MCH_SSKPD);
4303 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4304 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4305 DRM_INFO("This can cause pipe underruns and display issues.\n");
4306 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4307 }
4308}
4309
1fa61106 4310static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4311{
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe;
231e54f6 4314 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4315
231e54f6 4316 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4317
4318 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4319 I915_READ(ILK_DISPLAY_CHICKEN2) |
4320 ILK_ELPIN_409_SELECT);
4321
ecdb4eb7 4322 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4323 I915_WRITE(_3D_CHICKEN,
4324 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4325
ecdb4eb7 4326 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4327 if (IS_SNB_GT1(dev))
4328 I915_WRITE(GEN6_GT_MODE,
4329 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4330
6f1d69b0
ED		 4331 I915_WRITE(WM3_LP_ILK, 0);
4332 I915_WRITE(WM2_LP_ILK, 0);
4333 I915_WRITE(WM1_LP_ILK, 0);
4334
6f1d69b0 4335 I915_WRITE(CACHE_MODE_0,
50743298 4336 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4337
4338 I915_WRITE(GEN6_UCGCTL1,
4339 I915_READ(GEN6_UCGCTL1) |
4340 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4341 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4342
4343 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4344 * gating disable must be set. Failure to set it results in
4345 * flickering pixels due to Z write ordering failures after
4346 * some amount of runtime in the Mesa "fire" demo, and Unigine
4347 * Sanctuary and Tropics, and apparently anything else with
4348 * alpha test or pixel discard.
4349 *
4350 * According to the spec, bit 11 (RCCUNIT) must also be set,
4351 * but we didn't debug actual testcases to find it out.
0f846f81 4352 *
ecdb4eb7
DL		 4353 * Also apply WaDisableVDSUnitClockGating:snb and
4354 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4355 */
4356 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4357 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4358 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4359 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4360
4361 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4362 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4363 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4364
4365 /*
4366 * According to the spec the following bits should be
4367 * set in order to enable memory self-refresh and fbc:
4368 * The bit21 and bit22 of 0x42000
4369 * The bit21 and bit22 of 0x42004
4370 * The bit5 and bit7 of 0x42020
4371 * The bit14 of 0x70180
4372 * The bit14 of 0x71180
4373 */
4374 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4375 I915_READ(ILK_DISPLAY_CHICKEN1) |
4376 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4377 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4378 I915_READ(ILK_DISPLAY_CHICKEN2) |
4379 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4380 I915_WRITE(ILK_DSPCLK_GATE_D,
4381 I915_READ(ILK_DSPCLK_GATE_D) |
4382 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4383 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4384
ecdb4eb7 4385 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4386 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4387 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4388
6f1d69b0
ED		 4389 for_each_pipe(pipe) {
4390 I915_WRITE(DSPCNTR(pipe),
4391 I915_READ(DSPCNTR(pipe)) |
4392 DISPPLANE_TRICKLE_FEED_DISABLE);
4393 intel_flush_display_plane(dev_priv, pipe);
4394 }
f8f2ac9a
BW		 4395
4396 /* The default value should be 0x200 according to docs, but the two
4397 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4398 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4399 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4400
4401 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4402
4403 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4404}
4405
4406static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4407{
4408 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4409
4410 reg &= ~GEN7_FF_SCHED_MASK;
4411 reg |= GEN7_FF_TS_SCHED_HW;
4412 reg |= GEN7_FF_VS_SCHED_HW;
4413 reg |= GEN7_FF_DS_SCHED_HW;
4414
41c0b3a8
BW		 4415 if (IS_HASWELL(dev_priv->dev))
4416 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4417
6f1d69b0
ED		 4418 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4419}
4420
17a303ec
PZ		 4421static void lpt_init_clock_gating(struct drm_device *dev)
4422{
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424
4425 /*
4426 * TODO: this bit should only be enabled when really needed, then
4427 * disabled when not needed anymore in order to save power.
4428 */
4429 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4430 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4431 I915_READ(SOUTH_DSPCLK_GATE_D) |
4432 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4433
4434 /* WADPOClockGatingDisable:hsw */
4435 I915_WRITE(_TRANSA_CHICKEN1,
4436 I915_READ(_TRANSA_CHICKEN1) |
4437 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4438}
4439
7d708ee4
ID		 4440static void lpt_suspend_hw(struct drm_device *dev)
4441{
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443
4444 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4445 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4446
4447 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4448 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4449 }
4450}
4451
cad2a2d7
ED		 4452static void haswell_init_clock_gating(struct drm_device *dev)
4453{
4454 struct drm_i915_private *dev_priv = dev->dev_private;
4455 int pipe;
cad2a2d7
ED		 4456
4457 I915_WRITE(WM3_LP_ILK, 0);
4458 I915_WRITE(WM2_LP_ILK, 0);
4459 I915_WRITE(WM1_LP_ILK, 0);
4460
4461 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4462 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4463 */
4464 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4465
ecdb4eb7 4466 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4467 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4468 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4469
ecdb4eb7 4470 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4471 I915_WRITE(GEN7_L3CNTLREG1,
4472 GEN7_WA_FOR_GEN7_L3_CONTROL);
4473 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4474 GEN7_WA_L3_CHICKEN_MODE);
4475
ecdb4eb7 4476 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4477 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4478 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4479 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4480
4481 for_each_pipe(pipe) {
4482 I915_WRITE(DSPCNTR(pipe),
4483 I915_READ(DSPCNTR(pipe)) |
4484 DISPPLANE_TRICKLE_FEED_DISABLE);
4485 intel_flush_display_plane(dev_priv, pipe);
4486 }
4487
ecdb4eb7 4488 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4489 gen7_setup_fixed_func_scheduler(dev_priv);
4490
ecdb4eb7 4491 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4492 I915_WRITE(CACHE_MODE_1,
4493 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4494
ecdb4eb7 4495 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4496 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4497 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4498
ecdb4eb7 4499 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4500 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4501
90a88643
PZ		 4502 /* WaRsPkgCStateDisplayPMReq:hsw */
4503 I915_WRITE(CHICKEN_PAR1_1,
4504 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4505
17a303ec 4506 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4507}
4508
1fa61106 4509static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4510{
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 int pipe;
20848223 4513 uint32_t snpcr;
6f1d69b0 4514
6f1d69b0
ED		 4515 I915_WRITE(WM3_LP_ILK, 0);
4516 I915_WRITE(WM2_LP_ILK, 0);
4517 I915_WRITE(WM1_LP_ILK, 0);
4518
231e54f6 4519 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4520
ecdb4eb7 4521 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4522 I915_WRITE(_3D_CHICKEN3,
4523 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4524
ecdb4eb7 4525 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4526 I915_WRITE(IVB_CHICKEN3,
4527 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4528 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4529
ecdb4eb7 4530 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4531 if (IS_IVB_GT1(dev))
4532 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4533 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4534 else
4535 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4536 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4537
ecdb4eb7 4538 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4539 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4540 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4541
ecdb4eb7 4542 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4543 I915_WRITE(GEN7_L3CNTLREG1,
4544 GEN7_WA_FOR_GEN7_L3_CONTROL);
4545 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4546 GEN7_WA_L3_CHICKEN_MODE);
4547 if (IS_IVB_GT1(dev))
4548 I915_WRITE(GEN7_ROW_CHICKEN2,
4549 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4550 else
4551 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4552 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4553
6f1d69b0 4554
ecdb4eb7 4555 /* WaForceL3Serialization:ivb */
61939d97
JB		 4556 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4557 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4558
0f846f81
JB		 4559 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4560 * gating disable must be set. Failure to set it results in
4561 * flickering pixels due to Z write ordering failures after
4562 * some amount of runtime in the Mesa "fire" demo, and Unigine
4563 * Sanctuary and Tropics, and apparently anything else with
4564 * alpha test or pixel discard.
4565 *
4566 * According to the spec, bit 11 (RCCUNIT) must also be set,
4567 * but we didn't debug actual testcases to find it out.
4568 *
4569 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4570 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4571 */
4572 I915_WRITE(GEN6_UCGCTL2,
4573 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4574 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4575
ecdb4eb7 4576 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4577 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4578 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4579 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4580
4581 for_each_pipe(pipe) {
4582 I915_WRITE(DSPCNTR(pipe),
4583 I915_READ(DSPCNTR(pipe)) |
4584 DISPPLANE_TRICKLE_FEED_DISABLE);
4585 intel_flush_display_plane(dev_priv, pipe);
4586 }
4587
ecdb4eb7 4588 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4589 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4590 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4591
ecdb4eb7 4592 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4593 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4594
ecdb4eb7 4595 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4596 I915_WRITE(CACHE_MODE_1,
4597 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4598
4599 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4600 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4601 snpcr |= GEN6_MBC_SNPCR_MED;
4602 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4603
ab5c608b
BW		 4604 if (!HAS_PCH_NOP(dev))
4605 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4606
4607 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4608}
4609
1fa61106 4610static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4611{
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613 int pipe;
6f1d69b0
ED		 4614
4615 I915_WRITE(WM3_LP_ILK, 0);
4616 I915_WRITE(WM2_LP_ILK, 0);
4617 I915_WRITE(WM1_LP_ILK, 0);
4618
231e54f6 4619 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4620
ecdb4eb7 4621 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4622 I915_WRITE(_3D_CHICKEN3,
4623 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4624
ecdb4eb7 4625 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4626 I915_WRITE(IVB_CHICKEN3,
4627 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4628 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4629
ecdb4eb7 4630 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4631 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4632 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4633 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4634
ecdb4eb7 4635 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4636 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4637 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4638
ecdb4eb7 4639 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4640 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4641 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4642
ecdb4eb7 4643 /* WaForceL3Serialization:vlv */
61939d97
JB		 4644 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4645 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4646
ecdb4eb7 4647 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4648 I915_WRITE(GEN7_ROW_CHICKEN2,
4649 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4650
ecdb4eb7 4651 /* WaForceL3Serialization:vlv */
5c9664d7
JB		 4652 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4653 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4654
ecdb4eb7 4655 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4656 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4657 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4658 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4659
ecdb4eb7 4660 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4661 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4662 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4663
0f846f81
JB		 4664
4665 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4666 * gating disable must be set. Failure to set it results in
4667 * flickering pixels due to Z write ordering failures after
4668 * some amount of runtime in the Mesa "fire" demo, and Unigine
4669 * Sanctuary and Tropics, and apparently anything else with
4670 * alpha test or pixel discard.
4671 *
4672 * According to the spec, bit 11 (RCCUNIT) must also be set,
4673 * but we didn't debug actual testcases to find it out.
4674 *
4675 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4676 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4677 *
ecdb4eb7
DL		 4678 * Also apply WaDisableVDSUnitClockGating:vlv and
4679 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4680 */
4681 I915_WRITE(GEN6_UCGCTL2,
4682 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4683 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4684 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4685 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4686 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4687
e3f33d46
JB		 4688 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4689
6f1d69b0
ED		 4690 for_each_pipe(pipe) {
4691 I915_WRITE(DSPCNTR(pipe),
4692 I915_READ(DSPCNTR(pipe)) |
4693 DISPPLANE_TRICKLE_FEED_DISABLE);
4694 intel_flush_display_plane(dev_priv, pipe);
4695 }
4696
6b26c86d
DV		 4697 I915_WRITE(CACHE_MODE_1,
4698 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4699
2d809570 4700 /*
ecdb4eb7 4701 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4702 * Disable clock gating on th GCFG unit to prevent a delay
4703 * in the reporting of vblank events.
4704 */
4e8c84a5
JB		 4705 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4706
4707 /* Conservative clock gating settings for now */
4708 I915_WRITE(0x9400, 0xffffffff);
4709 I915_WRITE(0x9404, 0xffffffff);
4710 I915_WRITE(0x9408, 0xffffffff);
4711 I915_WRITE(0x940c, 0xffffffff);
4712 I915_WRITE(0x9410, 0xffffffff);
4713 I915_WRITE(0x9414, 0xffffffff);
4714 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4715}
4716
1fa61106 4717static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4718{
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4720 uint32_t dspclk_gate;
4721
4722 I915_WRITE(RENCLK_GATE_D1, 0);
4723 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4724 GS_UNIT_CLOCK_GATE_DISABLE |
4725 CL_UNIT_CLOCK_GATE_DISABLE);
4726 I915_WRITE(RAMCLK_GATE_D, 0);
4727 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4728 OVRUNIT_CLOCK_GATE_DISABLE |
4729 OVCUNIT_CLOCK_GATE_DISABLE;
4730 if (IS_GM45(dev))
4731 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4732 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4733
4734 /* WaDisableRenderCachePipelinedFlush */
4735 I915_WRITE(CACHE_MODE_0,
4736 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 4737}
4738
1fa61106 4739static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4740{
4741 struct drm_i915_private *dev_priv = dev->dev_private;
4742
4743 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4744 I915_WRITE(RENCLK_GATE_D2, 0);
4745 I915_WRITE(DSPCLK_GATE_D, 0);
4746 I915_WRITE(RAMCLK_GATE_D, 0);
4747 I915_WRITE16(DEUC, 0);
4748}
4749
1fa61106 4750static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4751{
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4753
4754 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4755 I965_RCC_CLOCK_GATE_DISABLE |
4756 I965_RCPB_CLOCK_GATE_DISABLE |
4757 I965_ISC_CLOCK_GATE_DISABLE |
4758 I965_FBC_CLOCK_GATE_DISABLE);
4759 I915_WRITE(RENCLK_GATE_D2, 0);
4760}
4761
1fa61106 4762static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4763{
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 u32 dstate = I915_READ(D_STATE);
4766
4767 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4768 DSTATE_DOT_CLOCK_GATING;
4769 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4770
4771 if (IS_PINEVIEW(dev))
4772 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4773
4774 /* IIR "flip pending" means done if this bit is set */
4775 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4776}
4777
1fa61106 4778static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4779{
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781
4782 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4783}
4784
1fa61106 4785static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4786{
4787 struct drm_i915_private *dev_priv = dev->dev_private;
4788
4789 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4790}
4791
6f1d69b0
ED		 4792void intel_init_clock_gating(struct drm_device *dev)
4793{
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795
4796 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4797}
4798
7d708ee4
ID		 4799void intel_suspend_hw(struct drm_device *dev)
4800{
4801 if (HAS_PCH_LPT(dev))
4802 lpt_suspend_hw(dev);
4803}
4804
15d199ea
PZ		 4805/**
4806 * We should only use the power well if we explicitly asked the hardware to
4807 * enable it, so check if it's enabled and also check if we've requested it to
4808 * be enabled.
4809 */
b97186f0
PZ		 4810bool intel_display_power_enabled(struct drm_device *dev,
4811 enum intel_display_power_domain domain)
15d199ea
PZ		 4812{
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4814
b97186f0
PZ		 4815 if (!HAS_POWER_WELL(dev))
4816 return true;
4817
4818 switch (domain) {
4819 case POWER_DOMAIN_PIPE_A:
4820 case POWER_DOMAIN_TRANSCODER_EDP:
4821 return true;
4822 case POWER_DOMAIN_PIPE_B:
4823 case POWER_DOMAIN_PIPE_C:
4824 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4825 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4826 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4827 case POWER_DOMAIN_TRANSCODER_A:
4828 case POWER_DOMAIN_TRANSCODER_B:
4829 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 4830 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4831 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 4832 default:
4833 BUG();
4834 }
15d199ea
PZ		 4835}
4836
cb10799c 4837void intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 4838{
4839 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 4840 bool is_enabled, enable_requested;
4841 uint32_t tmp;
d0d3e513 4842
86d52df6 4843 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 4844 return;
4845
2124b72e
PZ		 4846 if (!i915_disable_power_well && !enable)
4847 return;
4848
fa42e23c
PZ		 4849 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4850 is_enabled = tmp & HSW_PWR_WELL_STATE;
4851 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 4852
fa42e23c
PZ		 4853 if (enable) {
4854 if (!enable_requested)
4855 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 4856
fa42e23c
PZ		 4857 if (!is_enabled) {
4858 DRM_DEBUG_KMS("Enabling power well\n");
4859 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4860 HSW_PWR_WELL_STATE), 20))
4861 DRM_ERROR("Timeout enabling power well\n");
4862 }
4863 } else {
4864 if (enable_requested) {
4865 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4866 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 4867 }
4868 }
fa42e23c 4869}
d0d3e513 4870
fa42e23c
PZ		 4871/*
4872 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4873 * when not needed anymore. We have 4 registers that can request the power well
4874 * to be enabled, and it will only be disabled if none of the registers is
4875 * requesting it to be enabled.
d0d3e513 4876 */
fa42e23c 4877void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 4878{
4879 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 4880
86d52df6 4881 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 4882 return;
4883
fa42e23c
PZ		 4884 /* For now, we need the power well to be always enabled. */
4885 intel_set_power_well(dev, true);
d0d3e513 4886
fa42e23c
PZ		 4887 /* We're taking over the BIOS, so clear any requests made by it since
4888 * the driver is in charge now. */
4889 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4890 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 4891}
4892
1fa61106
ED		 4893/* Set up chip specific power management-related functions */
4894void intel_init_pm(struct drm_device *dev)
4895{
4896 struct drm_i915_private *dev_priv = dev->dev_private;
4897
4898 if (I915_HAS_FBC(dev)) {
4899 if (HAS_PCH_SPLIT(dev)) {
4900 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 4901 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 4902 dev_priv->display.enable_fbc =
4903 gen7_enable_fbc;
4904 else
4905 dev_priv->display.enable_fbc =
4906 ironlake_enable_fbc;
1fa61106
ED		 4907 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4908 } else if (IS_GM45(dev)) {
4909 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4910 dev_priv->display.enable_fbc = g4x_enable_fbc;
4911 dev_priv->display.disable_fbc = g4x_disable_fbc;
4912 } else if (IS_CRESTLINE(dev)) {
4913 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4914 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4915 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4916 }
4917 /* 855GM needs testing */
4918 }
4919
c921aba8
DV		 4920 /* For cxsr */
4921 if (IS_PINEVIEW(dev))
4922 i915_pineview_get_mem_freq(dev);
4923 else if (IS_GEN5(dev))
4924 i915_ironlake_get_mem_freq(dev);
4925
1fa61106
ED		 4926 /* For FIFO watermark updates */
4927 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 4928 if (IS_GEN5(dev)) {
4929 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4930 dev_priv->display.update_wm = ironlake_update_wm;
4931 else {
4932 DRM_DEBUG_KMS("Failed to get proper latency. "
4933 "Disable CxSR\n");
4934 dev_priv->display.update_wm = NULL;
4935 }
4936 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4937 } else if (IS_GEN6(dev)) {
4938 if (SNB_READ_WM0_LATENCY()) {
4939 dev_priv->display.update_wm = sandybridge_update_wm;
4940 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4941 } else {
4942 DRM_DEBUG_KMS("Failed to read display plane latency. "
4943 "Disable CxSR\n");
4944 dev_priv->display.update_wm = NULL;
4945 }
4946 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4947 } else if (IS_IVYBRIDGE(dev)) {
1fa61106 4948 if (SNB_READ_WM0_LATENCY()) {
c43d0188 4949 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 4950 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4951 } else {
4952 DRM_DEBUG_KMS("Failed to read display plane latency. "
4953 "Disable CxSR\n");
4954 dev_priv->display.update_wm = NULL;
4955 }
4956 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 4957 } else if (IS_HASWELL(dev)) {
3e1f7266 4958 if (I915_READ64(MCH_SSKPD)) {
1011d8c4 4959 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 4960 dev_priv->display.update_sprite_wm =
4961 haswell_update_sprite_wm;
6b8a5eeb
ED		 4962 } else {
4963 DRM_DEBUG_KMS("Failed to read display plane latency. "
4964 "Disable CxSR\n");
4965 dev_priv->display.update_wm = NULL;
4966 }
cad2a2d7 4967 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 4968 } else
4969 dev_priv->display.update_wm = NULL;
4970 } else if (IS_VALLEYVIEW(dev)) {
4971 dev_priv->display.update_wm = valleyview_update_wm;
4972 dev_priv->display.init_clock_gating =
4973 valleyview_init_clock_gating;
1fa61106
ED		 4974 } else if (IS_PINEVIEW(dev)) {
4975 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4976 dev_priv->is_ddr3,
4977 dev_priv->fsb_freq,
4978 dev_priv->mem_freq)) {
4979 DRM_INFO("failed to find known CxSR latency "
4980 "(found ddr%s fsb freq %d, mem freq %d), "
4981 "disabling CxSR\n",
4982 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4983 dev_priv->fsb_freq, dev_priv->mem_freq);
4984 /* Disable CxSR and never update its watermark again */
4985 pineview_disable_cxsr(dev);
4986 dev_priv->display.update_wm = NULL;
4987 } else
4988 dev_priv->display.update_wm = pineview_update_wm;
4989 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4990 } else if (IS_G4X(dev)) {
4991 dev_priv->display.update_wm = g4x_update_wm;
4992 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4993 } else if (IS_GEN4(dev)) {
4994 dev_priv->display.update_wm = i965_update_wm;
4995 if (IS_CRESTLINE(dev))
4996 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4997 else if (IS_BROADWATER(dev))
4998 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4999 } else if (IS_GEN3(dev)) {
5000 dev_priv->display.update_wm = i9xx_update_wm;
5001 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5002 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5003 } else if (IS_I865G(dev)) {
5004 dev_priv->display.update_wm = i830_update_wm;
5005 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5006 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5007 } else if (IS_I85X(dev)) {
5008 dev_priv->display.update_wm = i9xx_update_wm;
5009 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5010 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5011 } else {
5012 dev_priv->display.update_wm = i830_update_wm;
5013 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5014 if (IS_845G(dev))
5015 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5016 else
5017 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5018 }
5019}
5020
6590190d
ED		 5021static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
5022{
5023 u32 gt_thread_status_mask;
5024
5025 if (IS_HASWELL(dev_priv->dev))
5026 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
5027 else
5028 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
5029
5030 /* w/a for a sporadic read returning 0 by waiting for the GT
5031 * thread to wake up.
5032 */
5033 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
5034 DRM_ERROR("GT thread status wait timed out\n");
5035}
5036
16995a9f
CW		 5037static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
5038{
5039 I915_WRITE_NOTRACE(FORCEWAKE, 0);
5040 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
5041}
5042
6590190d
ED		 5043static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5044{
ebd37ce1 5045 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
057d3860 5046 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5047 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5048
30771e16 5049 I915_WRITE_NOTRACE(FORCEWAKE, 1);
8dee3eea 5050 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 5051
ebd37ce1 5052 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
057d3860 5053 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5054 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5055
8693a824 5056 /* WaRsForcewakeWaitTC0:snb */
6590190d
ED		 5057 __gen6_gt_wait_for_thread_c0(dev_priv);
5058}
5059
16995a9f
CW		 5060static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
5061{
5062 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5063 /* something from same cacheline, but !FORCEWAKE_MT */
5064 POSTING_READ(ECOBUS);
16995a9f
CW		 5065}
5066
6590190d
ED		 5067static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
5068{
5069 u32 forcewake_ack;
5070
5071 if (IS_HASWELL(dev_priv->dev))
5072 forcewake_ack = FORCEWAKE_ACK_HSW;
5073 else
5074 forcewake_ack = FORCEWAKE_MT_ACK;
5075
83983c8b 5076 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
057d3860 5077 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5078 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5079
c5836c27 5080 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5081 /* something from same cacheline, but !FORCEWAKE_MT */
5082 POSTING_READ(ECOBUS);
6590190d 5083
83983c8b 5084 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
057d3860 5085 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5086 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5087
8693a824 5088 /* WaRsForcewakeWaitTC0:ivb,hsw */
6590190d
ED		 5089 __gen6_gt_wait_for_thread_c0(dev_priv);
5090}
5091
5092/*
5093 * Generally this is called implicitly by the register read function. However,
5094 * if some sequence requires the GT to not power down then this function should
5095 * be called at the beginning of the sequence followed by a call to
5096 * gen6_gt_force_wake_put() at the end of the sequence.
5097 */
5098void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5099{
5100 unsigned long irqflags;
5101
5102 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5103 if (dev_priv->forcewake_count++ == 0)
5104 dev_priv->gt.force_wake_get(dev_priv);
5105 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5106}
5107
5108void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
5109{
5110 u32 gtfifodbg;
5111 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
5112 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
5113 "MMIO read or write has been dropped %x\n", gtfifodbg))
5114 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
5115}
5116
5117static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5118{
5119 I915_WRITE_NOTRACE(FORCEWAKE, 0);
b5144075
JN		 5120 /* something from same cacheline, but !FORCEWAKE */
5121 POSTING_READ(ECOBUS);
6590190d
ED		 5122 gen6_gt_check_fifodbg(dev_priv);
5123}
5124
5125static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
5126{
c5836c27 5127 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5128 /* something from same cacheline, but !FORCEWAKE_MT */
5129 POSTING_READ(ECOBUS);
6590190d
ED		 5130 gen6_gt_check_fifodbg(dev_priv);
5131}
5132
5133/*
5134 * see gen6_gt_force_wake_get()
5135 */
5136void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5137{
5138 unsigned long irqflags;
5139
5140 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5141 if (--dev_priv->forcewake_count == 0)
5142 dev_priv->gt.force_wake_put(dev_priv);
5143 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5144}
5145
5146int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
5147{
5148 int ret = 0;
5149
5150 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
5151 int loop = 500;
5152 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5153 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
5154 udelay(10);
5155 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5156 }
5157 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
5158 ++ret;
5159 dev_priv->gt_fifo_count = fifo;
5160 }
5161 dev_priv->gt_fifo_count--;
5162
5163 return ret;
5164}
5165
16995a9f
CW		 5166static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
5167{
5168 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5169 /* something from same cacheline, but !FORCEWAKE_VLV */
5170 POSTING_READ(FORCEWAKE_ACK_VLV);
16995a9f
CW		 5171}
5172
6590190d
ED		 5173static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
5174{
83983c8b 5175 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
057d3860 5176 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5177 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5178
c5836c27 5179 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5180 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5181 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 5182
83983c8b 5183 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
057d3860 5184 FORCEWAKE_ACK_TIMEOUT_MS))
ed5de399
JB		 5185 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
5186
5187 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
5188 FORCEWAKE_KERNEL),
5189 FORCEWAKE_ACK_TIMEOUT_MS))
5190 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
6590190d 5191
8693a824 5192 /* WaRsForcewakeWaitTC0:vlv */
6590190d
ED		 5193 __gen6_gt_wait_for_thread_c0(dev_priv);
5194}
5195
5196static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
5197{
c5836c27 5198 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5199 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5200 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5201 /* The below doubles as a POSTING_READ */
5ab140a4 5202 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 5203}
5204
16995a9f
CW		 5205void intel_gt_reset(struct drm_device *dev)
5206{
5207 struct drm_i915_private *dev_priv = dev->dev_private;
5208
5209 if (IS_VALLEYVIEW(dev)) {
5210 vlv_force_wake_reset(dev_priv);
5211 } else if (INTEL_INFO(dev)->gen >= 6) {
5212 __gen6_gt_force_wake_reset(dev_priv);
5213 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5214 __gen6_gt_force_wake_mt_reset(dev_priv);
5215 }
5216}
5217
6590190d
ED		 5218void intel_gt_init(struct drm_device *dev)
5219{
5220 struct drm_i915_private *dev_priv = dev->dev_private;
5221
5222 spin_lock_init(&dev_priv->gt_lock);
5223
16995a9f
CW		 5224 intel_gt_reset(dev);
5225
6590190d
ED		 5226 if (IS_VALLEYVIEW(dev)) {
5227 dev_priv->gt.force_wake_get = vlv_force_wake_get;
5228 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 5229 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5230 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
5231 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
5232 } else if (IS_GEN6(dev)) {
6590190d
ED		 5233 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
5234 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 5235 }
1a01ab3b
JB		 5236 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5237 intel_gen6_powersave_work);
6590190d
ED		 5238}
5239
42c0526c
BW		 5240int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5241{
4fc688ce 5242 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5243
5244 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5245 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5246 return -EAGAIN;
5247 }
5248
5249 I915_WRITE(GEN6_PCODE_DATA, *val);
5250 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5251
5252 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5253 500)) {
5254 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5255 return -ETIMEDOUT;
5256 }
5257
5258 *val = I915_READ(GEN6_PCODE_DATA);
5259 I915_WRITE(GEN6_PCODE_DATA, 0);
5260
5261 return 0;
5262}
5263
5264int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5265{
4fc688ce 5266 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5267
5268 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5269 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5270 return -EAGAIN;
5271 }
5272
5273 I915_WRITE(GEN6_PCODE_DATA, val);
5274 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5275
5276 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5277 500)) {
5278 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5279 return -ETIMEDOUT;
5280 }
5281
5282 I915_WRITE(GEN6_PCODE_DATA, 0);
5283
5284 return 0;
5285}
a0e4e199 5286
855ba3be
JB		 5287int vlv_gpu_freq(int ddr_freq, int val)
5288{
5289 int mult, base;
5290
5291 switch (ddr_freq) {
5292 case 800:
5293 mult = 20;
5294 base = 120;
5295 break;
5296 case 1066:
5297 mult = 22;
5298 base = 133;
5299 break;
5300 case 1333:
5301 mult = 21;
5302 base = 125;
5303 break;
5304 default:
5305 return -1;
5306 }
5307
5308 return ((val - 0xbd) * mult) + base;
5309}
5310
5311int vlv_freq_opcode(int ddr_freq, int val)
5312{
5313 int mult, base;
5314
5315 switch (ddr_freq) {
5316 case 800:
5317 mult = 20;
5318 base = 120;
5319 break;
5320 case 1066:
5321 mult = 22;
5322 base = 133;
5323 break;
5324 case 1333:
5325 mult = 21;
5326 base = 125;
5327 break;
5328 default:
5329 return -1;
5330 }
5331
5332 val /= mult;
5333 val -= base / mult;
5334 val += 0xbd;
5335
5336 if (val > 0xea)
5337 val = 0xea;
5338
5339 return val;
5340}
5341
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