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Revert "drm/i915/sprite: Always enable the scaler on IronLake"
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int plane, i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
113
114 /* Clear old tags */
115 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
116 I915_WRITE(FBC_TAG + (i * 4), 0);
117
159f9875
VS		 118 if (IS_GEN4(dev)) {
119 u32 fbc_ctl2;
120
121 /* Set it up... */
122 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
123 fbc_ctl2 |= plane;
124 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
125 I915_WRITE(FBC_FENCE_OFF, crtc->y);
126 }
85208be0
ED		 127
128 /* enable it... */
993495ae
VS		 129 fbc_ctl = I915_READ(FBC_CONTROL);
130 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
131 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 132 if (IS_I945GM(dev))
133 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
134 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 135 fbc_ctl |= obj->fence_reg;
136 I915_WRITE(FBC_CONTROL, fbc_ctl);
137
84f44ce7
VS		 138 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
139 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 140}
141
1fa61106 142static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 143{
144 struct drm_i915_private *dev_priv = dev->dev_private;
145
146 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
147}
148
993495ae 149static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 150{
151 struct drm_device *dev = crtc->dev;
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 struct drm_framebuffer *fb = crtc->fb;
154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
155 struct drm_i915_gem_object *obj = intel_fb->obj;
156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
157 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
85208be0
ED		 158 u32 dpfc_ctl;
159
160 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
163
85208be0
ED		 164 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
165
166 /* enable it... */
167 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
168
84f44ce7 169 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 170}
171
1fa61106 172static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 u32 dpfc_ctl;
176
177 /* Disable compression */
178 dpfc_ctl = I915_READ(DPFC_CONTROL);
179 if (dpfc_ctl & DPFC_CTL_EN) {
180 dpfc_ctl &= ~DPFC_CTL_EN;
181 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
182
183 DRM_DEBUG_KMS("disabled FBC\n");
184 }
185}
186
1fa61106 187static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 188{
189 struct drm_i915_private *dev_priv = dev->dev_private;
190
191 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
192}
193
194static void sandybridge_blit_fbc_update(struct drm_device *dev)
195{
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 u32 blt_ecoskpd;
198
199 /* Make sure blitter notifies FBC of writes */
940aece4
D		 200
201 /* Blitter is part of Media powerwell on VLV. No impact of
202 * his param in other platforms for now */
203 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 204
85208be0
ED		 205 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
206 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
207 GEN6_BLITTER_LOCK_SHIFT;
208 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
209 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
210 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
211 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
212 GEN6_BLITTER_LOCK_SHIFT);
213 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
214 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 215
940aece4 216 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 217}
218
993495ae 219static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 220{
221 struct drm_device *dev = crtc->dev;
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 struct drm_framebuffer *fb = crtc->fb;
224 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
225 struct drm_i915_gem_object *obj = intel_fb->obj;
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
85208be0
ED		 228 u32 dpfc_ctl;
229
230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
231 dpfc_ctl &= DPFC_RESERVED;
232 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
233 /* Set persistent mode for front-buffer rendering, ala X. */
234 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0
ED		 238 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
239
85208be0 240 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 241 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 242 /* enable it... */
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
244
245 if (IS_GEN6(dev)) {
246 I915_WRITE(SNB_DPFC_CTL_SA,
247 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
249 sandybridge_blit_fbc_update(dev);
250 }
251
84f44ce7 252 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 253}
254
1fa61106 255static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 u32 dpfc_ctl;
259
260 /* Disable compression */
261 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
262 if (dpfc_ctl & DPFC_CTL_EN) {
263 dpfc_ctl &= ~DPFC_CTL_EN;
264 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265
266 DRM_DEBUG_KMS("disabled FBC\n");
267 }
268}
269
1fa61106 270static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 271{
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
275}
276
993495ae 277static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 278{
279 struct drm_device *dev = crtc->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct drm_framebuffer *fb = crtc->fb;
282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
283 struct drm_i915_gem_object *obj = intel_fb->obj;
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
285
f343c5f6 286 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 287
288 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
289 IVB_DPFC_CTL_FENCE_EN |
290 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291
891348b2 292 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 294 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 295 } else {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
298 HSW_BYPASS_FBC_QUEUE);
891348b2 299 }
b74ea102 300
abe959c7
RV		 301 I915_WRITE(SNB_DPFC_CTL_SA,
302 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304
305 sandybridge_blit_fbc_update(dev);
306
b19870ee 307 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 308}
309
85208be0
ED		 310bool intel_fbc_enabled(struct drm_device *dev)
311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.fbc_enabled)
315 return false;
316
317 return dev_priv->display.fbc_enabled(dev);
318}
319
320static void intel_fbc_work_fn(struct work_struct *__work)
321{
322 struct intel_fbc_work *work =
323 container_of(to_delayed_work(__work),
324 struct intel_fbc_work, work);
325 struct drm_device *dev = work->crtc->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327
328 mutex_lock(&dev->struct_mutex);
5c3fe8b0 329 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 330 /* Double check that we haven't switched fb without cancelling
331 * the prior work.
332 */
333 if (work->crtc->fb == work->fb) {
993495ae 334 dev_priv->display.enable_fbc(work->crtc);
85208be0 335
5c3fe8b0
BW		 336 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
338 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 339 }
340
5c3fe8b0 341 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346}
347
348static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349{
5c3fe8b0 350 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 357 * entirely asynchronously.
358 */
5c3fe8b0 359 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 360 /* tasklet was killed before being run, clean up */
5c3fe8b0 361 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
5c3fe8b0 368 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 369}
370
993495ae 371static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 372{
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
b14c5679 382 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 383 if (work == NULL) {
6cdcb5e7 384 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 385 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 386 return;
387 }
388
389 work->crtc = crtc;
390 work->fb = crtc->fb;
85208be0
ED		 391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
ef644fda 461 const struct drm_display_mode *adjusted_mode;
37327abd 462 unsigned int max_width, max_height;
85208be0 463
29ebf90f
CW		 464 if (!I915_HAS_FBC(dev)) {
465 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 466 return;
29ebf90f 467 }
85208be0 468
29ebf90f
CW		 469 if (!i915_powersave) {
470 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
471 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 472 return;
29ebf90f 473 }
85208be0
ED		 474
475 /*
476 * If FBC is already on, we just have to verify that we can
477 * keep it that way...
478 * Need to disable if:
479 * - more than one pipe is active
480 * - changing FBC params (stride, fence, mode)
481 * - new fb is too large to fit in compressed buffer
482 * - going to an unsupported config (interlace, pixel multiply, etc.)
483 */
484 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 485 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 486 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 487 if (crtc) {
29ebf90f
CW		 488 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
489 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 490 goto out_disable;
491 }
492 crtc = tmp_crtc;
493 }
494 }
495
496 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 497 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
498 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 499 goto out_disable;
500 }
501
502 intel_crtc = to_intel_crtc(crtc);
503 fb = crtc->fb;
504 intel_fb = to_intel_framebuffer(fb);
505 obj = intel_fb->obj;
ef644fda 506 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 507
8a5729a3
DL		 508 if (i915_enable_fbc < 0 &&
509 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 510 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
511 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 512 goto out_disable;
85208be0 513 }
8a5729a3 514 if (!i915_enable_fbc) {
29ebf90f
CW		 515 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
516 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 517 goto out_disable;
518 }
ef644fda
VS		 519 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
520 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
522 DRM_DEBUG_KMS("mode incompatible with compression, "
523 "disabling\n");
85208be0
ED		 524 goto out_disable;
525 }
f85da868
PZ		 526
527 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 528 max_width = 4096;
529 max_height = 2048;
f85da868 530 } else {
37327abd
VS		 531 max_width = 2048;
532 max_height = 1536;
f85da868 533 }
37327abd
VS		 534 if (intel_crtc->config.pipe_src_w > max_width ||
535 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 536 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 538 goto out_disable;
539 }
c5a44aa0
VS		 540 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
541 intel_crtc->plane != PLANE_A) {
29ebf90f 542 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 543 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 544 goto out_disable;
545 }
546
547 /* The use of a CPU fence is mandatory in order to detect writes
548 * by the CPU to the scanout and trigger updates to the FBC.
549 */
550 if (obj->tiling_mode != I915_TILING_X ||
551 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 552 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
553 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 554 goto out_disable;
555 }
556
557 /* If the kernel debugger is active, always disable compression */
558 if (in_dbg_master())
559 goto out_disable;
560
11be49eb 561 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 562 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
563 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 564 goto out_disable;
565 }
566
85208be0
ED		 567 /* If the scanout has not changed, don't modify the FBC settings.
568 * Note that we make the fundamental assumption that the fb->obj
569 * cannot be unpinned (and have its GTT offset and fence revoked)
570 * without first being decoupled from the scanout and FBC disabled.
571 */
5c3fe8b0
BW		 572 if (dev_priv->fbc.plane == intel_crtc->plane &&
573 dev_priv->fbc.fb_id == fb->base.id &&
574 dev_priv->fbc.y == crtc->y)
85208be0
ED		 575 return;
576
577 if (intel_fbc_enabled(dev)) {
578 /* We update FBC along two paths, after changing fb/crtc
579 * configuration (modeswitching) and after page-flipping
580 * finishes. For the latter, we know that not only did
581 * we disable the FBC at the start of the page-flip
582 * sequence, but also more than one vblank has passed.
583 *
584 * For the former case of modeswitching, it is possible
585 * to switch between two FBC valid configurations
586 * instantaneously so we do need to disable the FBC
587 * before we can modify its control registers. We also
588 * have to wait for the next vblank for that to take
589 * effect. However, since we delay enabling FBC we can
590 * assume that a vblank has passed since disabling and
591 * that we can safely alter the registers in the deferred
592 * callback.
593 *
594 * In the scenario that we go from a valid to invalid
595 * and then back to valid FBC configuration we have
596 * no strict enforcement that a vblank occurred since
597 * disabling the FBC. However, along all current pipe
598 * disabling paths we do need to wait for a vblank at
599 * some point. And we wait before enabling FBC anyway.
600 */
601 DRM_DEBUG_KMS("disabling active FBC for update\n");
602 intel_disable_fbc(dev);
603 }
604
993495ae 605 intel_enable_fbc(crtc);
29ebf90f 606 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 607 return;
608
609out_disable:
610 /* Multiple disables should be harmless */
611 if (intel_fbc_enabled(dev)) {
612 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
613 intel_disable_fbc(dev);
614 }
11be49eb 615 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 616}
617
c921aba8
DV		 618static void i915_pineview_get_mem_freq(struct drm_device *dev)
619{
620 drm_i915_private_t *dev_priv = dev->dev_private;
621 u32 tmp;
622
623 tmp = I915_READ(CLKCFG);
624
625 switch (tmp & CLKCFG_FSB_MASK) {
626 case CLKCFG_FSB_533:
627 dev_priv->fsb_freq = 533; /* 133*4 */
628 break;
629 case CLKCFG_FSB_800:
630 dev_priv->fsb_freq = 800; /* 200*4 */
631 break;
632 case CLKCFG_FSB_667:
633 dev_priv->fsb_freq = 667; /* 167*4 */
634 break;
635 case CLKCFG_FSB_400:
636 dev_priv->fsb_freq = 400; /* 100*4 */
637 break;
638 }
639
640 switch (tmp & CLKCFG_MEM_MASK) {
641 case CLKCFG_MEM_533:
642 dev_priv->mem_freq = 533;
643 break;
644 case CLKCFG_MEM_667:
645 dev_priv->mem_freq = 667;
646 break;
647 case CLKCFG_MEM_800:
648 dev_priv->mem_freq = 800;
649 break;
650 }
651
652 /* detect pineview DDR3 setting */
653 tmp = I915_READ(CSHRDDR3CTL);
654 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
655}
656
657static void i915_ironlake_get_mem_freq(struct drm_device *dev)
658{
659 drm_i915_private_t *dev_priv = dev->dev_private;
660 u16 ddrpll, csipll;
661
662 ddrpll = I915_READ16(DDRMPLL1);
663 csipll = I915_READ16(CSIPLL0);
664
665 switch (ddrpll & 0xff) {
666 case 0xc:
667 dev_priv->mem_freq = 800;
668 break;
669 case 0x10:
670 dev_priv->mem_freq = 1066;
671 break;
672 case 0x14:
673 dev_priv->mem_freq = 1333;
674 break;
675 case 0x18:
676 dev_priv->mem_freq = 1600;
677 break;
678 default:
679 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
680 ddrpll & 0xff);
681 dev_priv->mem_freq = 0;
682 break;
683 }
684
20e4d407 685 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 686
687 switch (csipll & 0x3ff) {
688 case 0x00c:
689 dev_priv->fsb_freq = 3200;
690 break;
691 case 0x00e:
692 dev_priv->fsb_freq = 3733;
693 break;
694 case 0x010:
695 dev_priv->fsb_freq = 4266;
696 break;
697 case 0x012:
698 dev_priv->fsb_freq = 4800;
699 break;
700 case 0x014:
701 dev_priv->fsb_freq = 5333;
702 break;
703 case 0x016:
704 dev_priv->fsb_freq = 5866;
705 break;
706 case 0x018:
707 dev_priv->fsb_freq = 6400;
708 break;
709 default:
710 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
711 csipll & 0x3ff);
712 dev_priv->fsb_freq = 0;
713 break;
714 }
715
716 if (dev_priv->fsb_freq == 3200) {
20e4d407 717 dev_priv->ips.c_m = 0;
c921aba8 718 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 719 dev_priv->ips.c_m = 1;
c921aba8 720 } else {
20e4d407 721 dev_priv->ips.c_m = 2;
c921aba8
DV		 722 }
723}
724
b445e3b0
ED		 725static const struct cxsr_latency cxsr_latency_table[] = {
726 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
727 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
728 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
729 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
730 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
731
732 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
733 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
734 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
735 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
736 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
737
738 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
739 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
740 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
741 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
742 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
743
744 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
745 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
746 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
747 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
748 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
749
750 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
751 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
752 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
753 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
754 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
755
756 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
757 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
758 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
759 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
760 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
761};
762
63c62275 763static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 764 int is_ddr3,
765 int fsb,
766 int mem)
767{
768 const struct cxsr_latency *latency;
769 int i;
770
771 if (fsb == 0 || mem == 0)
772 return NULL;
773
774 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
775 latency = &cxsr_latency_table[i];
776 if (is_desktop == latency->is_desktop &&
777 is_ddr3 == latency->is_ddr3 &&
778 fsb == latency->fsb_freq && mem == latency->mem_freq)
779 return latency;
780 }
781
782 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
783
784 return NULL;
785}
786
1fa61106 787static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* deactivate cxsr */
792 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
793}
794
795/*
796 * Latency for FIFO fetches is dependent on several factors:
797 * - memory configuration (speed, channels)
798 * - chipset
799 * - current MCH state
800 * It can be fairly high in some situations, so here we assume a fairly
801 * pessimal value. It's a tradeoff between extra memory fetches (if we
802 * set this value too high, the FIFO will fetch frequently to stay full)
803 * and power consumption (set it too low to save power and we might see
804 * FIFO underruns and display "flicker").
805 *
806 * A value of 5us seems to be a good balance; safe for very low end
807 * platforms but not overly aggressive on lower latency configs.
808 */
809static const int latency_ns = 5000;
810
1fa61106 811static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 812{
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t dsparb = I915_READ(DSPARB);
815 int size;
816
817 size = dsparb & 0x7f;
818 if (plane)
819 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
820
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
822 plane ? "B" : "A", size);
823
824 return size;
825}
826
1fa61106 827static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 828{
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 uint32_t dsparb = I915_READ(DSPARB);
831 int size;
832
833 size = dsparb & 0x1ff;
834 if (plane)
835 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
836 size >>= 1; /* Convert to cachelines */
837
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
839 plane ? "B" : "A", size);
840
841 return size;
842}
843
1fa61106 844static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 845{
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 uint32_t dsparb = I915_READ(DSPARB);
848 int size;
849
850 size = dsparb & 0x7f;
851 size >>= 2; /* Convert to cachelines */
852
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
854 plane ? "B" : "A",
855 size);
856
857 return size;
858}
859
1fa61106 860static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 861{
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 uint32_t dsparb = I915_READ(DSPARB);
864 int size;
865
866 size = dsparb & 0x7f;
867 size >>= 1; /* Convert to cachelines */
868
869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
870 plane ? "B" : "A", size);
871
872 return size;
873}
874
875/* Pineview has different values for various configs */
876static const struct intel_watermark_params pineview_display_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882};
883static const struct intel_watermark_params pineview_display_hplloff_wm = {
884 PINEVIEW_DISPLAY_FIFO,
885 PINEVIEW_MAX_WM,
886 PINEVIEW_DFT_HPLLOFF_WM,
887 PINEVIEW_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE
889};
890static const struct intel_watermark_params pineview_cursor_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE,
896};
897static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
898 PINEVIEW_CURSOR_FIFO,
899 PINEVIEW_CURSOR_MAX_WM,
900 PINEVIEW_CURSOR_DFT_WM,
901 PINEVIEW_CURSOR_GUARD_WM,
902 PINEVIEW_FIFO_LINE_SIZE
903};
904static const struct intel_watermark_params g4x_wm_info = {
905 G4X_FIFO_SIZE,
906 G4X_MAX_WM,
907 G4X_MAX_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910};
911static const struct intel_watermark_params g4x_cursor_wm_info = {
912 I965_CURSOR_FIFO,
913 I965_CURSOR_MAX_WM,
914 I965_CURSOR_DFT_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917};
918static const struct intel_watermark_params valleyview_wm_info = {
919 VALLEYVIEW_FIFO_SIZE,
920 VALLEYVIEW_MAX_WM,
921 VALLEYVIEW_MAX_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924};
925static const struct intel_watermark_params valleyview_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 VALLEYVIEW_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 G4X_FIFO_LINE_SIZE,
931};
932static const struct intel_watermark_params i965_cursor_wm_info = {
933 I965_CURSOR_FIFO,
934 I965_CURSOR_MAX_WM,
935 I965_CURSOR_DFT_WM,
936 2,
937 I915_FIFO_LINE_SIZE,
938};
939static const struct intel_watermark_params i945_wm_info = {
940 I945_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945};
946static const struct intel_watermark_params i915_wm_info = {
947 I915_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I915_FIFO_LINE_SIZE
952};
953static const struct intel_watermark_params i855_wm_info = {
954 I855GM_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959};
960static const struct intel_watermark_params i830_wm_info = {
961 I830_FIFO_SIZE,
962 I915_MAX_WM,
963 1,
964 2,
965 I830_FIFO_LINE_SIZE
966};
967
b445e3b0
ED		 968/**
969 * intel_calculate_wm - calculate watermark level
970 * @clock_in_khz: pixel clock
971 * @wm: chip FIFO params
972 * @pixel_size: display pixel size
973 * @latency_ns: memory latency for the platform
974 *
975 * Calculate the watermark level (the level at which the display plane will
976 * start fetching from memory again). Each chip has a different display
977 * FIFO size and allocation, so the caller needs to figure that out and pass
978 * in the correct intel_watermark_params structure.
979 *
980 * As the pixel clock runs, the FIFO will be drained at a rate that depends
981 * on the pixel size. When it reaches the watermark level, it'll start
982 * fetching FIFO line sized based chunks from memory until the FIFO fills
983 * past the watermark point. If the FIFO drains completely, a FIFO underrun
984 * will occur, and a display engine hang could result.
985 */
986static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
987 const struct intel_watermark_params *wm,
988 int fifo_size,
989 int pixel_size,
990 unsigned long latency_ns)
991{
992 long entries_required, wm_size;
993
994 /*
995 * Note: we need to make sure we don't overflow for various clock &
996 * latency values.
997 * clocks go from a few thousand to several hundred thousand.
998 * latency is usually a few thousand
999 */
1000 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1001 1000;
1002 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1003
1004 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1005
1006 wm_size = fifo_size - (entries_required + wm->guard_size);
1007
1008 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1009
1010 /* Don't promote wm_size to unsigned... */
1011 if (wm_size > (long)wm->max_wm)
1012 wm_size = wm->max_wm;
1013 if (wm_size <= 0)
1014 wm_size = wm->default_wm;
1015 return wm_size;
1016}
1017
1018static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1019{
1020 struct drm_crtc *crtc, *enabled = NULL;
1021
1022 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1023 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1024 if (enabled)
1025 return NULL;
1026 enabled = crtc;
1027 }
1028 }
1029
1030 return enabled;
1031}
1032
46ba614c 1033static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1034{
46ba614c 1035 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 struct drm_crtc *crtc;
1038 const struct cxsr_latency *latency;
1039 u32 reg;
1040 unsigned long wm;
1041
1042 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1043 dev_priv->fsb_freq, dev_priv->mem_freq);
1044 if (!latency) {
1045 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1046 pineview_disable_cxsr(dev);
1047 return;
1048 }
1049
1050 crtc = single_enabled_crtc(dev);
1051 if (crtc) {
241bfc38 1052 const struct drm_display_mode *adjusted_mode;
b445e3b0 1053 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1054 int clock;
1055
1056 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1057 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1058
1059 /* Display SR */
1060 wm = intel_calculate_wm(clock, &pineview_display_wm,
1061 pineview_display_wm.fifo_size,
1062 pixel_size, latency->display_sr);
1063 reg = I915_READ(DSPFW1);
1064 reg &= ~DSPFW_SR_MASK;
1065 reg |= wm << DSPFW_SR_SHIFT;
1066 I915_WRITE(DSPFW1, reg);
1067 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1068
1069 /* cursor SR */
1070 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1071 pineview_display_wm.fifo_size,
1072 pixel_size, latency->cursor_sr);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_CURSOR_SR_MASK;
1075 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1076 I915_WRITE(DSPFW3, reg);
1077
1078 /* Display HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->display_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_SR_MASK;
1084 reg |= wm & DSPFW_HPLL_SR_MASK;
1085 I915_WRITE(DSPFW3, reg);
1086
1087 /* cursor HPLL off SR */
1088 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1089 pineview_display_hplloff_wm.fifo_size,
1090 pixel_size, latency->cursor_hpll_disable);
1091 reg = I915_READ(DSPFW3);
1092 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1093 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1094 I915_WRITE(DSPFW3, reg);
1095 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1096
1097 /* activate cxsr */
1098 I915_WRITE(DSPFW3,
1099 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1100 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1101 } else {
1102 pineview_disable_cxsr(dev);
1103 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1104 }
1105}
1106
1107static bool g4x_compute_wm0(struct drm_device *dev,
1108 int plane,
1109 const struct intel_watermark_params *display,
1110 int display_latency_ns,
1111 const struct intel_watermark_params *cursor,
1112 int cursor_latency_ns,
1113 int *plane_wm,
1114 int *cursor_wm)
1115{
1116 struct drm_crtc *crtc;
4fe8590a 1117 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1118 int htotal, hdisplay, clock, pixel_size;
1119 int line_time_us, line_count;
1120 int entries, tlb_miss;
1121
1122 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1123 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1124 *cursor_wm = cursor->guard_size;
1125 *plane_wm = display->guard_size;
1126 return false;
1127 }
1128
4fe8590a 1129 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1130 clock = adjusted_mode->crtc_clock;
4fe8590a 1131 htotal = adjusted_mode->htotal;
37327abd 1132 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1133 pixel_size = crtc->fb->bits_per_pixel / 8;
1134
1135 /* Use the small buffer method to calculate plane watermark */
1136 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1137 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1138 if (tlb_miss > 0)
1139 entries += tlb_miss;
1140 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1141 *plane_wm = entries + display->guard_size;
1142 if (*plane_wm > (int)display->max_wm)
1143 *plane_wm = display->max_wm;
1144
1145 /* Use the large buffer method to calculate cursor watermark */
1146 line_time_us = ((htotal * 1000) / clock);
1147 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1148 entries = line_count * 64 * pixel_size;
1149 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1150 if (tlb_miss > 0)
1151 entries += tlb_miss;
1152 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1153 *cursor_wm = entries + cursor->guard_size;
1154 if (*cursor_wm > (int)cursor->max_wm)
1155 *cursor_wm = (int)cursor->max_wm;
1156
1157 return true;
1158}
1159
1160/*
1161 * Check the wm result.
1162 *
1163 * If any calculated watermark values is larger than the maximum value that
1164 * can be programmed into the associated watermark register, that watermark
1165 * must be disabled.
1166 */
1167static bool g4x_check_srwm(struct drm_device *dev,
1168 int display_wm, int cursor_wm,
1169 const struct intel_watermark_params *display,
1170 const struct intel_watermark_params *cursor)
1171{
1172 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1173 display_wm, cursor_wm);
1174
1175 if (display_wm > display->max_wm) {
1176 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1177 display_wm, display->max_wm);
1178 return false;
1179 }
1180
1181 if (cursor_wm > cursor->max_wm) {
1182 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1183 cursor_wm, cursor->max_wm);
1184 return false;
1185 }
1186
1187 if (!(display_wm || cursor_wm)) {
1188 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1189 return false;
1190 }
1191
1192 return true;
1193}
1194
1195static bool g4x_compute_srwm(struct drm_device *dev,
1196 int plane,
1197 int latency_ns,
1198 const struct intel_watermark_params *display,
1199 const struct intel_watermark_params *cursor,
1200 int *display_wm, int *cursor_wm)
1201{
1202 struct drm_crtc *crtc;
4fe8590a 1203 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1204 int hdisplay, htotal, pixel_size, clock;
1205 unsigned long line_time_us;
1206 int line_count, line_size;
1207 int small, large;
1208 int entries;
1209
1210 if (!latency_ns) {
1211 *display_wm = *cursor_wm = 0;
1212 return false;
1213 }
1214
1215 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1216 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1217 clock = adjusted_mode->crtc_clock;
4fe8590a 1218 htotal = adjusted_mode->htotal;
37327abd 1219 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1220 pixel_size = crtc->fb->bits_per_pixel / 8;
1221
1222 line_time_us = (htotal * 1000) / clock;
1223 line_count = (latency_ns / line_time_us + 1000) / 1000;
1224 line_size = hdisplay * pixel_size;
1225
1226 /* Use the minimum of the small and large buffer method for primary */
1227 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1228 large = line_count * line_size;
1229
1230 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1231 *display_wm = entries + display->guard_size;
1232
1233 /* calculate the self-refresh watermark for display cursor */
1234 entries = line_count * pixel_size * 64;
1235 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1236 *cursor_wm = entries + cursor->guard_size;
1237
1238 return g4x_check_srwm(dev,
1239 *display_wm, *cursor_wm,
1240 display, cursor);
1241}
1242
1243static bool vlv_compute_drain_latency(struct drm_device *dev,
1244 int plane,
1245 int *plane_prec_mult,
1246 int *plane_dl,
1247 int *cursor_prec_mult,
1248 int *cursor_dl)
1249{
1250 struct drm_crtc *crtc;
1251 int clock, pixel_size;
1252 int entries;
1253
1254 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1255 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1256 return false;
1257
241bfc38 1258 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1259 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1260
1261 entries = (clock / 1000) * pixel_size;
1262 *plane_prec_mult = (entries > 256) ?
1263 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1264 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1265 pixel_size);
1266
1267 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1268 *cursor_prec_mult = (entries > 256) ?
1269 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1270 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1271
1272 return true;
1273}
1274
1275/*
1276 * Update drain latency registers of memory arbiter
1277 *
1278 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1279 * to be programmed. Each plane has a drain latency multiplier and a drain
1280 * latency value.
1281 */
1282
1283static void vlv_update_drain_latency(struct drm_device *dev)
1284{
1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1287 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1288 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1289 either 16 or 32 */
1290
1291 /* For plane A, Cursor A */
1292 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1293 &cursor_prec_mult, &cursora_dl)) {
1294 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1295 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1296 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1297 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1298
1299 I915_WRITE(VLV_DDL1, cursora_prec |
1300 (cursora_dl << DDL_CURSORA_SHIFT) |
1301 planea_prec | planea_dl);
1302 }
1303
1304 /* For plane B, Cursor B */
1305 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1306 &cursor_prec_mult, &cursorb_dl)) {
1307 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1308 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1309 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1310 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1311
1312 I915_WRITE(VLV_DDL2, cursorb_prec |
1313 (cursorb_dl << DDL_CURSORB_SHIFT) |
1314 planeb_prec | planeb_dl);
1315 }
1316}
1317
1318#define single_plane_enabled(mask) is_power_of_2(mask)
1319
46ba614c 1320static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1321{
46ba614c 1322 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1323 static const int sr_latency_ns = 12000;
1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1326 int plane_sr, cursor_sr;
af6c4575 1327 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1328 unsigned int enabled = 0;
1329
1330 vlv_update_drain_latency(dev);
1331
51cea1f4 1332 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1333 &valleyview_wm_info, latency_ns,
1334 &valleyview_cursor_wm_info, latency_ns,
1335 &planea_wm, &cursora_wm))
51cea1f4 1336 enabled |= 1 << PIPE_A;
b445e3b0 1337
51cea1f4 1338 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1339 &valleyview_wm_info, latency_ns,
1340 &valleyview_cursor_wm_info, latency_ns,
1341 &planeb_wm, &cursorb_wm))
51cea1f4 1342 enabled |= 1 << PIPE_B;
b445e3b0 1343
b445e3b0
ED		 1344 if (single_plane_enabled(enabled) &&
1345 g4x_compute_srwm(dev, ffs(enabled) - 1,
1346 sr_latency_ns,
1347 &valleyview_wm_info,
1348 &valleyview_cursor_wm_info,
af6c4575
CW		 1349 &plane_sr, &ignore_cursor_sr) &&
1350 g4x_compute_srwm(dev, ffs(enabled) - 1,
1351 2*sr_latency_ns,
1352 &valleyview_wm_info,
1353 &valleyview_cursor_wm_info,
52bd02d8 1354 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1355 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1356 } else {
b445e3b0
ED		 1357 I915_WRITE(FW_BLC_SELF_VLV,
1358 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1359 plane_sr = cursor_sr = 0;
1360 }
b445e3b0
ED		 1361
1362 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1363 planea_wm, cursora_wm,
1364 planeb_wm, cursorb_wm,
1365 plane_sr, cursor_sr);
1366
1367 I915_WRITE(DSPFW1,
1368 (plane_sr << DSPFW_SR_SHIFT) |
1369 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1370 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1371 planea_wm);
1372 I915_WRITE(DSPFW2,
8c919b28 1373 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1374 (cursora_wm << DSPFW_CURSORA_SHIFT));
1375 I915_WRITE(DSPFW3,
8c919b28
CW		 1376 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1377 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1378}
1379
46ba614c 1380static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1381{
46ba614c 1382 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1383 static const int sr_latency_ns = 12000;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 unsigned int enabled = 0;
1388
51cea1f4 1389 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1390 &g4x_wm_info, latency_ns,
1391 &g4x_cursor_wm_info, latency_ns,
1392 &planea_wm, &cursora_wm))
51cea1f4 1393 enabled |= 1 << PIPE_A;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1396 &g4x_wm_info, latency_ns,
1397 &g4x_cursor_wm_info, latency_ns,
1398 &planeb_wm, &cursorb_wm))
51cea1f4 1399 enabled |= 1 << PIPE_B;
b445e3b0 1400
b445e3b0
ED		 1401 if (single_plane_enabled(enabled) &&
1402 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 sr_latency_ns,
1404 &g4x_wm_info,
1405 &g4x_cursor_wm_info,
52bd02d8 1406 &plane_sr, &cursor_sr)) {
b445e3b0 1407 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1408 } else {
b445e3b0
ED		 1409 I915_WRITE(FW_BLC_SELF,
1410 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1411 plane_sr = cursor_sr = 0;
1412 }
b445e3b0
ED		 1413
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1415 planea_wm, cursora_wm,
1416 planeb_wm, cursorb_wm,
1417 plane_sr, cursor_sr);
1418
1419 I915_WRITE(DSPFW1,
1420 (plane_sr << DSPFW_SR_SHIFT) |
1421 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1422 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1423 planea_wm);
1424 I915_WRITE(DSPFW2,
8c919b28 1425 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1426 (cursora_wm << DSPFW_CURSORA_SHIFT));
1427 /* HPLL off in SR has some issues on G4x... disable it */
1428 I915_WRITE(DSPFW3,
8c919b28 1429 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1430 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1431}
1432
46ba614c 1433static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1434{
46ba614c 1435 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 struct drm_crtc *crtc;
1438 int srwm = 1;
1439 int cursor_sr = 16;
1440
1441 /* Calc sr entries for one plane configs */
1442 crtc = single_enabled_crtc(dev);
1443 if (crtc) {
1444 /* self-refresh has much higher latency */
1445 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1446 const struct drm_display_mode *adjusted_mode =
1447 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1448 int clock = adjusted_mode->crtc_clock;
4fe8590a 1449 int htotal = adjusted_mode->htotal;
37327abd 1450 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1451 int pixel_size = crtc->fb->bits_per_pixel / 8;
1452 unsigned long line_time_us;
1453 int entries;
1454
1455 line_time_us = ((htotal * 1000) / clock);
1456
1457 /* Use ns/us then divide to preserve precision */
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1459 pixel_size * hdisplay;
1460 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1461 srwm = I965_FIFO_SIZE - entries;
1462 if (srwm < 0)
1463 srwm = 1;
1464 srwm &= 0x1ff;
1465 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1466 entries, srwm);
1467
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469 pixel_size * 64;
1470 entries = DIV_ROUND_UP(entries,
1471 i965_cursor_wm_info.cacheline_size);
1472 cursor_sr = i965_cursor_wm_info.fifo_size -
1473 (entries + i965_cursor_wm_info.guard_size);
1474
1475 if (cursor_sr > i965_cursor_wm_info.max_wm)
1476 cursor_sr = i965_cursor_wm_info.max_wm;
1477
1478 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1479 "cursor %d\n", srwm, cursor_sr);
1480
1481 if (IS_CRESTLINE(dev))
1482 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1483 } else {
1484 /* Turn off self refresh if both pipes are enabled */
1485 if (IS_CRESTLINE(dev))
1486 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1487 & ~FW_BLC_SELF_EN);
1488 }
1489
1490 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1491 srwm);
1492
1493 /* 965 has limitations... */
1494 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1495 (8 << 16) | (8 << 8) | (8 << 0));
1496 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1497 /* update cursor SR watermark */
1498 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1499}
1500
46ba614c 1501static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1502{
46ba614c 1503 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 const struct intel_watermark_params *wm_info;
1506 uint32_t fwater_lo;
1507 uint32_t fwater_hi;
1508 int cwm, srwm = 1;
1509 int fifo_size;
1510 int planea_wm, planeb_wm;
1511 struct drm_crtc *crtc, *enabled = NULL;
1512
1513 if (IS_I945GM(dev))
1514 wm_info = &i945_wm_info;
1515 else if (!IS_GEN2(dev))
1516 wm_info = &i915_wm_info;
1517 else
1518 wm_info = &i855_wm_info;
1519
1520 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1521 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1522 if (intel_crtc_active(crtc)) {
241bfc38 1523 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1524 int cpp = crtc->fb->bits_per_pixel / 8;
1525 if (IS_GEN2(dev))
1526 cpp = 4;
1527
241bfc38
DL		 1528 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1529 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1530 wm_info, fifo_size, cpp,
b445e3b0
ED		 1531 latency_ns);
1532 enabled = crtc;
1533 } else
1534 planea_wm = fifo_size - wm_info->guard_size;
1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1537 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1540 int cpp = crtc->fb->bits_per_pixel / 8;
1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
241bfc38
DL		 1544 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1545 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
b445e3b0
ED		 1547 latency_ns);
1548 if (enabled == NULL)
1549 enabled = crtc;
1550 else
1551 enabled = NULL;
1552 } else
1553 planeb_wm = fifo_size - wm_info->guard_size;
1554
1555 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1556
1557 /*
1558 * Overlay gets an aggressive default since video jitter is bad.
1559 */
1560 cwm = 2;
1561
1562 /* Play safe and disable self-refresh before adjusting watermarks. */
1563 if (IS_I945G(dev) || IS_I945GM(dev))
1564 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1565 else if (IS_I915GM(dev))
1566 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1567
1568 /* Calc sr entries for one plane configs */
1569 if (HAS_FW_BLC(dev) && enabled) {
1570 /* self-refresh has much higher latency */
1571 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1572 const struct drm_display_mode *adjusted_mode =
1573 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1574 int clock = adjusted_mode->crtc_clock;
4fe8590a 1575 int htotal = adjusted_mode->htotal;
f727b490 1576 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
b445e3b0
ED		 1577 int pixel_size = enabled->fb->bits_per_pixel / 8;
1578 unsigned long line_time_us;
1579 int entries;
1580
1581 line_time_us = (htotal * 1000) / clock;
1582
1583 /* Use ns/us then divide to preserve precision */
1584 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1585 pixel_size * hdisplay;
1586 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1587 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1588 srwm = wm_info->fifo_size - entries;
1589 if (srwm < 0)
1590 srwm = 1;
1591
1592 if (IS_I945G(dev) || IS_I945GM(dev))
1593 I915_WRITE(FW_BLC_SELF,
1594 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1595 else if (IS_I915GM(dev))
1596 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1597 }
1598
1599 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1600 planea_wm, planeb_wm, cwm, srwm);
1601
1602 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1603 fwater_hi = (cwm & 0x1f);
1604
1605 /* Set request length to 8 cachelines per fetch */
1606 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1607 fwater_hi = fwater_hi | (1 << 8);
1608
1609 I915_WRITE(FW_BLC, fwater_lo);
1610 I915_WRITE(FW_BLC2, fwater_hi);
1611
1612 if (HAS_FW_BLC(dev)) {
1613 if (enabled) {
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF,
1616 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1617 else if (IS_I915GM(dev))
1618 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1619 DRM_DEBUG_KMS("memory self refresh enabled\n");
1620 } else
1621 DRM_DEBUG_KMS("memory self refresh disabled\n");
1622 }
1623}
1624
46ba614c 1625static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1626{
46ba614c 1627 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629 struct drm_crtc *crtc;
241bfc38 1630 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1631 uint32_t fwater_lo;
1632 int planea_wm;
1633
1634 crtc = single_enabled_crtc(dev);
1635 if (crtc == NULL)
1636 return;
1637
241bfc38
DL		 1638 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1639 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1640 &i830_wm_info,
b445e3b0 1641 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1642 4, latency_ns);
b445e3b0
ED		 1643 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1644 fwater_lo |= (3<<8) | planea_wm;
1645
1646 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1647
1648 I915_WRITE(FW_BLC, fwater_lo);
1649}
1650
3658729a
VS		 1651static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1652 struct drm_crtc *crtc)
801bcfff
PZ		 1653{
1654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1655 uint32_t pixel_rate;
801bcfff 1656
241bfc38 1657 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1658
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1661
fd4daa9c 1662 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1664 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1665
37327abd
VS		 1666 pipe_w = intel_crtc->config.pipe_src_w;
1667 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1671 pipe_w = pfit_w;
1672 if (pipe_h < pfit_h)
1673 pipe_h = pfit_h;
1674
1675 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1676 pfit_w * pfit_h);
1677 }
1678
1679 return pixel_rate;
1680}
1681
37126462 1682/* latency must be in 0.1us units. */
23297044 1683static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1684 uint32_t latency)
1685{
1686 uint64_t ret;
1687
3312ba65
VS		 1688 if (WARN(latency == 0, "Latency value missing\n"))
1689 return UINT_MAX;
1690
801bcfff
PZ		 1691 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1692 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1693
1694 return ret;
1695}
1696
37126462 1697/* latency must be in 0.1us units. */
23297044 1698static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1699 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1700 uint32_t latency)
1701{
1702 uint32_t ret;
1703
3312ba65
VS		 1704 if (WARN(latency == 0, "Latency value missing\n"))
1705 return UINT_MAX;
1706
801bcfff
PZ		 1707 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1708 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1709 ret = DIV_ROUND_UP(ret, 64) + 2;
1710 return ret;
1711}
1712
23297044 1713static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1714 uint8_t bytes_per_pixel)
1715{
1716 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1717}
1718
801bcfff
PZ		 1719struct hsw_pipe_wm_parameters {
1720 bool active;
801bcfff
PZ		 1721 uint32_t pipe_htotal;
1722 uint32_t pixel_rate;
c35426d2
VS		 1723 struct intel_plane_wm_parameters pri;
1724 struct intel_plane_wm_parameters spr;
1725 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1726};
1727
cca32e9a
PZ		 1728struct hsw_wm_maximums {
1729 uint16_t pri;
1730 uint16_t spr;
1731 uint16_t cur;
1732 uint16_t fbc;
1733};
1734
240264f4
VS		 1735/* used in computing the new watermarks state */
1736struct intel_wm_config {
1737 unsigned int num_pipes_active;
1738 bool sprites_enabled;
1739 bool sprites_scaled;
240264f4
VS		 1740};
1741
37126462
VS		 1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
ac830fe1 1746static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 1747 uint32_t mem_value,
1748 bool is_lp)
801bcfff 1749{
cca32e9a
PZ		 1750 uint32_t method1, method2;
1751
c35426d2 1752 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1753 return 0;
1754
23297044 1755 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1756 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1757 mem_value);
1758
1759 if (!is_lp)
1760 return method1;
1761
23297044 1762 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1763 params->pipe_htotal,
c35426d2
VS		 1764 params->pri.horiz_pixels,
1765 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1766 mem_value);
1767
1768 return min(method1, method2);
801bcfff
PZ		 1769}
1770
37126462
VS		 1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
ac830fe1 1775static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 1776 uint32_t mem_value)
1777{
1778 uint32_t method1, method2;
1779
c35426d2 1780 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1781 return 0;
1782
23297044 1783 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1784 params->spr.bytes_per_pixel,
801bcfff 1785 mem_value);
23297044 1786 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1787 params->pipe_htotal,
c35426d2
VS		 1788 params->spr.horiz_pixels,
1789 params->spr.bytes_per_pixel,
801bcfff
PZ		 1790 mem_value);
1791 return min(method1, method2);
1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
ac830fe1 1798static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 1799 uint32_t mem_value)
1800{
c35426d2 1801 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1802 return 0;
1803
23297044 1804 return ilk_wm_method2(params->pixel_rate,
801bcfff 1805 params->pipe_htotal,
c35426d2
VS		 1806 params->cur.horiz_pixels,
1807 params->cur.bytes_per_pixel,
801bcfff
PZ		 1808 mem_value);
1809}
1810
cca32e9a 1811/* Only for WM_LP. */
ac830fe1 1812static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 1813 uint32_t pri_val)
cca32e9a 1814{
c35426d2 1815 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1816 return 0;
1817
23297044 1818 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1819 params->pri.horiz_pixels,
1820 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1821}
1822
158ae64f
VS		 1823static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1824{
416f4727
VS		 1825 if (INTEL_INFO(dev)->gen >= 8)
1826 return 3072;
1827 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1828 return 768;
1829 else
1830 return 512;
1831}
1832
1833/* Calculate the maximum primary/sprite plane watermark */
1834static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1835 int level,
240264f4 1836 const struct intel_wm_config *config,
158ae64f
VS		 1837 enum intel_ddb_partitioning ddb_partitioning,
1838 bool is_sprite)
1839{
1840 unsigned int fifo_size = ilk_display_fifo_size(dev);
1841 unsigned int max;
1842
1843 /* if sprites aren't enabled, sprites get nothing */
240264f4 1844 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1845 return 0;
1846
1847 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1848 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1849 fifo_size /= INTEL_INFO(dev)->num_pipes;
1850
1851 /*
1852 * For some reason the non self refresh
1853 * FIFO size is only half of the self
1854 * refresh FIFO size on ILK/SNB.
1855 */
1856 if (INTEL_INFO(dev)->gen <= 6)
1857 fifo_size /= 2;
1858 }
1859
240264f4 1860 if (config->sprites_enabled) {
158ae64f
VS		 1861 /* level 0 is always calculated with 1:1 split */
1862 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1863 if (is_sprite)
1864 fifo_size *= 5;
1865 fifo_size /= 6;
1866 } else {
1867 fifo_size /= 2;
1868 }
1869 }
1870
1871 /* clamp to max that the registers can hold */
416f4727
VS		 1872 if (INTEL_INFO(dev)->gen >= 8)
1873 max = level == 0 ? 255 : 2047;
1874 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1875 /* IVB/HSW primary/sprite plane watermarks */
1876 max = level == 0 ? 127 : 1023;
1877 else if (!is_sprite)
1878 /* ILK/SNB primary plane watermarks */
1879 max = level == 0 ? 127 : 511;
1880 else
1881 /* ILK/SNB sprite plane watermarks */
1882 max = level == 0 ? 63 : 255;
1883
1884 return min(fifo_size, max);
1885}
1886
1887/* Calculate the maximum cursor plane watermark */
1888static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1889 int level,
1890 const struct intel_wm_config *config)
158ae64f
VS		 1891{
1892 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1893 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1894 return 64;
1895
1896 /* otherwise just report max that registers can hold */
1897 if (INTEL_INFO(dev)->gen >= 7)
1898 return level == 0 ? 63 : 255;
1899 else
1900 return level == 0 ? 31 : 63;
1901}
1902
1903/* Calculate the maximum FBC watermark */
416f4727 1904static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
158ae64f
VS		 1905{
1906 /* max that registers can hold */
416f4727
VS		 1907 if (INTEL_INFO(dev)->gen >= 8)
1908 return 31;
1909 else
1910 return 15;
158ae64f
VS		 1911}
1912
34982fe1
VS		 1913static void ilk_compute_wm_maximums(struct drm_device *dev,
1914 int level,
1915 const struct intel_wm_config *config,
1916 enum intel_ddb_partitioning ddb_partitioning,
1917 struct hsw_wm_maximums *max)
158ae64f 1918{
240264f4
VS		 1919 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1920 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1921 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 1922 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 1923}
1924
d9395655
VS		 1925static bool ilk_validate_wm_level(int level,
1926 const struct hsw_wm_maximums *max,
1927 struct intel_wm_level *result)
a9786a11
VS		 1928{
1929 bool ret;
1930
1931 /* already determined to be invalid? */
1932 if (!result->enable)
1933 return false;
1934
1935 result->enable = result->pri_val <= max->pri &&
1936 result->spr_val <= max->spr &&
1937 result->cur_val <= max->cur;
1938
1939 ret = result->enable;
1940
1941 /*
1942 * HACK until we can pre-compute everything,
1943 * and thus fail gracefully if LP0 watermarks
1944 * are exceeded...
1945 */
1946 if (level == 0 && !result->enable) {
1947 if (result->pri_val > max->pri)
1948 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1949 level, result->pri_val, max->pri);
1950 if (result->spr_val > max->spr)
1951 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1952 level, result->spr_val, max->spr);
1953 if (result->cur_val > max->cur)
1954 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1955 level, result->cur_val, max->cur);
1956
1957 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1958 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1959 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1960 result->enable = true;
1961 }
1962
a9786a11
VS		 1963 return ret;
1964}
1965
6f5ddd17
VS		 1966static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
1967 int level,
ac830fe1 1968 const struct hsw_pipe_wm_parameters *p,
1fd527cc 1969 struct intel_wm_level *result)
6f5ddd17
VS		 1970{
1971 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1972 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1973 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1974
1975 /* WM1+ latency values stored in 0.5us units */
1976 if (level > 0) {
1977 pri_latency *= 5;
1978 spr_latency *= 5;
1979 cur_latency *= 5;
1980 }
1981
1982 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1983 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1984 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1985 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1986 result->enable = true;
1987}
1988
801bcfff
PZ		 1989static uint32_t
1990hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1991{
1992 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 1994 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 1995 u32 linetime, ips_linetime;
1f8eeabf 1996
801bcfff
PZ		 1997 if (!intel_crtc_active(crtc))
1998 return 0;
1011d8c4 1999
1f8eeabf
ED		 2000 /* The WM are computed with base on how long it takes to fill a single
2001 * row at the given clock rate, multiplied by 8.
2002 * */
85a02deb
PZ		 2003 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2004 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2005 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2006
801bcfff
PZ		 2007 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2008 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2009}
2010
12b134df
VS		 2011static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2012{
2013 struct drm_i915_private *dev_priv = dev->dev_private;
2014
2015 if (IS_HASWELL(dev)) {
2016 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2017
2018 wm[0] = (sskpd >> 56) & 0xFF;
2019 if (wm[0] == 0)
2020 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2021 wm[1] = (sskpd >> 4) & 0xFF;
2022 wm[2] = (sskpd >> 12) & 0xFF;
2023 wm[3] = (sskpd >> 20) & 0x1FF;
2024 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2025 } else if (INTEL_INFO(dev)->gen >= 6) {
2026 uint32_t sskpd = I915_READ(MCH_SSKPD);
2027
2028 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2029 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2030 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2031 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2032 } else if (INTEL_INFO(dev)->gen >= 5) {
2033 uint32_t mltr = I915_READ(MLTR_ILK);
2034
2035 /* ILK primary LP0 latency is 700 ns */
2036 wm[0] = 7;
2037 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2038 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2039 }
2040}
2041
53615a5e
VS		 2042static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2043{
2044 /* ILK sprite LP0 latency is 1300 ns */
2045 if (INTEL_INFO(dev)->gen == 5)
2046 wm[0] = 13;
2047}
2048
2049static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2050{
2051 /* ILK cursor LP0 latency is 1300 ns */
2052 if (INTEL_INFO(dev)->gen == 5)
2053 wm[0] = 13;
2054
2055 /* WaDoubleCursorLP3Latency:ivb */
2056 if (IS_IVYBRIDGE(dev))
2057 wm[3] *= 2;
2058}
2059
ad0d6dc4 2060static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2061{
26ec971e
VS		 2062 /* how many WM levels are we expecting */
2063 if (IS_HASWELL(dev))
ad0d6dc4 2064 return 4;
26ec971e 2065 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2066 return 3;
26ec971e 2067 else
ad0d6dc4
VS		 2068 return 2;
2069}
2070
2071static void intel_print_wm_latency(struct drm_device *dev,
2072 const char *name,
2073 const uint16_t wm[5])
2074{
2075 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2076
2077 for (level = 0; level <= max_level; level++) {
2078 unsigned int latency = wm[level];
2079
2080 if (latency == 0) {
2081 DRM_ERROR("%s WM%d latency not provided\n",
2082 name, level);
2083 continue;
2084 }
2085
2086 /* WM1+ latency values in 0.5us units */
2087 if (level > 0)
2088 latency *= 5;
2089
2090 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2091 name, level, wm[level],
2092 latency / 10, latency % 10);
2093 }
2094}
2095
53615a5e
VS		 2096static void intel_setup_wm_latency(struct drm_device *dev)
2097{
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099
2100 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2101
2102 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2103 sizeof(dev_priv->wm.pri_latency));
2104 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2105 sizeof(dev_priv->wm.pri_latency));
2106
2107 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2108 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2109
2110 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2111 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2112 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2113}
2114
7c4a395f
VS		 2115static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2116 struct hsw_pipe_wm_parameters *p,
a485bfb8 2117 struct intel_wm_config *config)
1011d8c4 2118{
7c4a395f
VS		 2119 struct drm_device *dev = crtc->dev;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2122 struct drm_plane *plane;
1011d8c4 2123
7c4a395f
VS		 2124 p->active = intel_crtc_active(crtc);
2125 if (p->active) {
801bcfff 2126 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2127 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2128 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2129 p->cur.bytes_per_pixel = 4;
37327abd 2130 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2131 p->cur.horiz_pixels = 64;
2132 /* TODO: for now, assume primary and cursor planes are always enabled. */
2133 p->pri.enabled = true;
2134 p->cur.enabled = true;
801bcfff
PZ		 2135 }
2136
7c4a395f 2137 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2138 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2139
801bcfff
PZ		 2140 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2141 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2142
7c4a395f
VS		 2143 if (intel_plane->pipe == pipe)
2144 p->spr = intel_plane->wm;
cca32e9a 2145
a485bfb8
VS		 2146 config->sprites_enabled |= intel_plane->wm.enabled;
2147 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2148 }
801bcfff
PZ		 2149}
2150
0b2ae6d7
VS		 2151/* Compute new watermarks for the pipe */
2152static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2153 const struct hsw_pipe_wm_parameters *params,
2154 struct intel_pipe_wm *pipe_wm)
2155{
2156 struct drm_device *dev = crtc->dev;
2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 int level, max_level = ilk_wm_max_level(dev);
2159 /* LP0 watermark maximums depend on this pipe alone */
2160 struct intel_wm_config config = {
2161 .num_pipes_active = 1,
2162 .sprites_enabled = params->spr.enabled,
2163 .sprites_scaled = params->spr.scaled,
2164 };
2165 struct hsw_wm_maximums max;
2166
0b2ae6d7 2167 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2168 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7 2169
7b39a0b7
VS		 2170 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2171 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2172 max_level = 1;
2173
2174 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2175 if (params->spr.scaled)
2176 max_level = 0;
2177
0b2ae6d7
VS		 2178 for (level = 0; level <= max_level; level++)
2179 ilk_compute_wm_level(dev_priv, level, params,
2180 &pipe_wm->wm[level]);
2181
ce0e0713
VS		 2182 if (IS_HASWELL(dev))
2183 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7
VS		 2184
2185 /* At least LP0 must be valid */
d9395655 2186 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2187}
2188
2189/*
2190 * Merge the watermarks from all active pipes for a specific level.
2191 */
2192static void ilk_merge_wm_level(struct drm_device *dev,
2193 int level,
2194 struct intel_wm_level *ret_wm)
2195{
2196 const struct intel_crtc *intel_crtc;
2197
2198 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2199 const struct intel_wm_level *wm =
2200 &intel_crtc->wm.active.wm[level];
2201
2202 if (!wm->enable)
2203 return;
2204
2205 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2206 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2207 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2208 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2209 }
2210
2211 ret_wm->enable = true;
2212}
2213
2214/*
2215 * Merge all low power watermarks for all active pipes.
2216 */
2217static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2218 const struct intel_wm_config *config,
0b2ae6d7
VS		 2219 const struct hsw_wm_maximums *max,
2220 struct intel_pipe_wm *merged)
2221{
2222 int level, max_level = ilk_wm_max_level(dev);
2223
0ba22e26
VS		 2224 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2225 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2226 config->num_pipes_active > 1)
2227 return;
2228
6c8b6c28
VS		 2229 /* ILK: FBC WM must be disabled always */
2230 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2231
2232 /* merge each WM1+ level */
2233 for (level = 1; level <= max_level; level++) {
2234 struct intel_wm_level *wm = &merged->wm[level];
2235
2236 ilk_merge_wm_level(dev, level, wm);
2237
d9395655 2238 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2239 break;
2240
2241 /*
2242 * The spec says it is preferred to disable
2243 * FBC WMs instead of disabling a WM level.
2244 */
2245 if (wm->fbc_val > max->fbc) {
2246 merged->fbc_wm_enabled = false;
2247 wm->fbc_val = 0;
2248 }
2249 }
6c8b6c28
VS		 2250
2251 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2252 /*
2253 * FIXME this is racy. FBC might get enabled later.
2254 * What we should check here is whether FBC can be
2255 * enabled sometime later.
2256 */
2257 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2258 for (level = 2; level <= max_level; level++) {
2259 struct intel_wm_level *wm = &merged->wm[level];
2260
2261 wm->enable = false;
2262 }
2263 }
0b2ae6d7
VS		 2264}
2265
b380ca3c
VS		 2266static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2267{
2268 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2269 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2270}
2271
a68d68ee
VS		 2272/* The value we need to program into the WM_LPx latency field */
2273static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
2277 if (IS_HASWELL(dev))
2278 return 2 * level;
2279 else
2280 return dev_priv->wm.pri_latency[level];
2281}
2282
801bcfff 2283static void hsw_compute_wm_results(struct drm_device *dev,
0362c781 2284 const struct intel_pipe_wm *merged,
609cedef 2285 enum intel_ddb_partitioning partitioning,
801bcfff
PZ		 2286 struct hsw_wm_values *results)
2287{
0b2ae6d7
VS		 2288 struct intel_crtc *intel_crtc;
2289 int level, wm_lp;
cca32e9a 2290
0362c781 2291 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2292 results->partitioning = partitioning;
cca32e9a 2293
0b2ae6d7 2294 /* LP1+ register values */
cca32e9a 2295 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2296 const struct intel_wm_level *r;
801bcfff 2297
b380ca3c 2298 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2299
0362c781 2300 r = &merged->wm[level];
0b2ae6d7 2301 if (!r->enable)
cca32e9a
PZ		 2302 break;
2303
416f4727 2304 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
a68d68ee 2305 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2306 (r->pri_val << WM1_LP_SR_SHIFT) |
2307 r->cur_val;
2308
2309 if (INTEL_INFO(dev)->gen >= 8)
2310 results->wm_lp[wm_lp - 1] |=
2311 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2312 else
2313 results->wm_lp[wm_lp - 1] |=
2314 r->fbc_val << WM1_LP_FBC_SHIFT;
2315
6cef2b8a
VS		 2316 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2317 WARN_ON(wm_lp != 1);
2318 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2319 } else
2320 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2321 }
801bcfff 2322
0b2ae6d7
VS		 2323 /* LP0 register values */
2324 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2325 enum pipe pipe = intel_crtc->pipe;
2326 const struct intel_wm_level *r =
2327 &intel_crtc->wm.active.wm[0];
2328
2329 if (WARN_ON(!r->enable))
2330 continue;
2331
2332 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2333
0b2ae6d7
VS		 2334 results->wm_pipe[pipe] =
2335 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2336 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2337 r->cur_val;
801bcfff
PZ		 2338 }
2339}
2340
861f3389
PZ		 2341/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2342 * case both are at the same level. Prefer r1 in case they're the same. */
198a1e9b
VS		 2343static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2344 struct intel_pipe_wm *r1,
2345 struct intel_pipe_wm *r2)
861f3389 2346{
198a1e9b
VS		 2347 int level, max_level = ilk_wm_max_level(dev);
2348 int level1 = 0, level2 = 0;
861f3389 2349
198a1e9b
VS		 2350 for (level = 1; level <= max_level; level++) {
2351 if (r1->wm[level].enable)
2352 level1 = level;
2353 if (r2->wm[level].enable)
2354 level2 = level;
861f3389
PZ		 2355 }
2356
198a1e9b
VS		 2357 if (level1 == level2) {
2358 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2359 return r2;
2360 else
2361 return r1;
198a1e9b 2362 } else if (level1 > level2) {
861f3389
PZ		 2363 return r1;
2364 } else {
2365 return r2;
2366 }
2367}
2368
49a687c4
VS		 2369/* dirty bits used to track which watermarks need changes */
2370#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2371#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2372#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2373#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2374#define WM_DIRTY_FBC (1 << 24)
2375#define WM_DIRTY_DDB (1 << 25)
2376
2377static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2378 const struct hsw_wm_values *old,
2379 const struct hsw_wm_values *new)
2380{
2381 unsigned int dirty = 0;
2382 enum pipe pipe;
2383 int wm_lp;
2384
2385 for_each_pipe(pipe) {
2386 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2387 dirty |= WM_DIRTY_LINETIME(pipe);
2388 /* Must disable LP1+ watermarks too */
2389 dirty |= WM_DIRTY_LP_ALL;
2390 }
2391
2392 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2393 dirty |= WM_DIRTY_PIPE(pipe);
2394 /* Must disable LP1+ watermarks too */
2395 dirty |= WM_DIRTY_LP_ALL;
2396 }
2397 }
2398
2399 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2400 dirty |= WM_DIRTY_FBC;
2401 /* Must disable LP1+ watermarks too */
2402 dirty |= WM_DIRTY_LP_ALL;
2403 }
2404
2405 if (old->partitioning != new->partitioning) {
2406 dirty |= WM_DIRTY_DDB;
2407 /* Must disable LP1+ watermarks too */
2408 dirty |= WM_DIRTY_LP_ALL;
2409 }
2410
2411 /* LP1+ watermarks already deemed dirty, no need to continue */
2412 if (dirty & WM_DIRTY_LP_ALL)
2413 return dirty;
2414
2415 /* Find the lowest numbered LP1+ watermark in need of an update... */
2416 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2417 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2418 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2419 break;
2420 }
2421
2422 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2423 for (; wm_lp <= 3; wm_lp++)
2424 dirty |= WM_DIRTY_LP(wm_lp);
2425
2426 return dirty;
2427}
2428
8553c18e
VS		 2429static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2430 unsigned int dirty)
801bcfff 2431{
243e6a44 2432 struct hsw_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2433 bool changed = false;
801bcfff 2434
facd619b
VS		 2435 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2436 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2437 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2438 changed = true;
facd619b
VS		 2439 }
2440 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2441 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2442 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2443 changed = true;
facd619b
VS		 2444 }
2445 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2446 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2447 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2448 changed = true;
facd619b 2449 }
801bcfff 2450
facd619b
VS		 2451 /*
2452 * Don't touch WM1S_LP_EN here.
2453 * Doing so could cause underruns.
2454 */
6cef2b8a 2455
8553c18e
VS		 2456 return changed;
2457}
2458
2459/*
2460 * The spec says we shouldn't write when we don't need, because every write
2461 * causes WMs to be re-evaluated, expending some power.
2462 */
2463static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2464 struct hsw_wm_values *results)
2465{
2466 struct drm_device *dev = dev_priv->dev;
2467 struct hsw_wm_values *previous = &dev_priv->wm.hw;
2468 unsigned int dirty;
2469 uint32_t val;
2470
2471 dirty = ilk_compute_wm_dirty(dev, previous, results);
2472 if (!dirty)
2473 return;
2474
2475 _ilk_disable_lp_wm(dev_priv, dirty);
2476
49a687c4 2477 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2478 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2479 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2480 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2481 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2482 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2483
49a687c4 2484 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2485 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2486 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2487 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2488 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2489 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2490
49a687c4 2491 if (dirty & WM_DIRTY_DDB) {
ac9545fd
VS		 2492 if (IS_HASWELL(dev)) {
2493 val = I915_READ(WM_MISC);
2494 if (results->partitioning == INTEL_DDB_PART_1_2)
2495 val &= ~WM_MISC_DATA_PARTITION_5_6;
2496 else
2497 val |= WM_MISC_DATA_PARTITION_5_6;
2498 I915_WRITE(WM_MISC, val);
2499 } else {
2500 val = I915_READ(DISP_ARB_CTL2);
2501 if (results->partitioning == INTEL_DDB_PART_1_2)
2502 val &= ~DISP_DATA_PARTITION_5_6;
2503 else
2504 val |= DISP_DATA_PARTITION_5_6;
2505 I915_WRITE(DISP_ARB_CTL2, val);
2506 }
1011d8c4
PZ		 2507 }
2508
49a687c4 2509 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2510 val = I915_READ(DISP_ARB_CTL);
2511 if (results->enable_fbc_wm)
2512 val &= ~DISP_FBC_WM_DIS;
2513 else
2514 val |= DISP_FBC_WM_DIS;
2515 I915_WRITE(DISP_ARB_CTL, val);
2516 }
2517
6cef2b8a 2518 if (INTEL_INFO(dev)->gen <= 6) {
facd619b 2519 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
6cef2b8a
VS		 2520 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2521 } else {
2522 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2523 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2524 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2525 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2526 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2527 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2528 }
801bcfff 2529
facd619b 2530 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2531 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2532 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2533 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2534 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2535 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2536
2537 dev_priv->wm.hw = *results;
801bcfff
PZ		 2538}
2539
8553c18e
VS		 2540static bool ilk_disable_lp_wm(struct drm_device *dev)
2541{
2542 struct drm_i915_private *dev_priv = dev->dev_private;
2543
2544 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2545}
2546
46ba614c 2547static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2548{
7c4a395f 2549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2550 struct drm_device *dev = crtc->dev;
801bcfff 2551 struct drm_i915_private *dev_priv = dev->dev_private;
a485bfb8 2552 struct hsw_wm_maximums max;
7c4a395f 2553 struct hsw_pipe_wm_parameters params = {};
198a1e9b 2554 struct hsw_wm_values results = {};
77c122bc 2555 enum intel_ddb_partitioning partitioning;
7c4a395f 2556 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2557 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2558 struct intel_wm_config config = {};
7c4a395f 2559
a485bfb8 2560 hsw_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2561
2562 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2563
2564 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2565 return;
861f3389 2566
7c4a395f 2567 intel_crtc->wm.active = pipe_wm;
861f3389 2568
34982fe1 2569 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2570 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2571
2572 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2573 if (INTEL_INFO(dev)->gen >= 7 &&
2574 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2575 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2576 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2577
198a1e9b 2578 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2579 } else {
198a1e9b 2580 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2581 }
2582
198a1e9b 2583 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2584 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2585
609cedef
VS		 2586 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2587
2588 hsw_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2589}
2590
adf3d35e
VS		 2591static void haswell_update_sprite_wm(struct drm_plane *plane,
2592 struct drm_crtc *crtc,
526682e9 2593 uint32_t sprite_width, int pixel_size,
bdd57d03 2594 bool enabled, bool scaled)
526682e9 2595{
8553c18e 2596 struct drm_device *dev = plane->dev;
adf3d35e 2597 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2598
adf3d35e
VS		 2599 intel_plane->wm.enabled = enabled;
2600 intel_plane->wm.scaled = scaled;
2601 intel_plane->wm.horiz_pixels = sprite_width;
2602 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2603
8553c18e
VS		 2604 /*
2605 * IVB workaround: must disable low power watermarks for at least
2606 * one frame before enabling scaling. LP watermarks can be re-enabled
2607 * when scaling is disabled.
2608 *
2609 * WaCxSRDisabledForSpriteScaling:ivb
2610 */
2611 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2612 intel_wait_for_vblank(dev, intel_plane->pipe);
2613
46ba614c 2614 haswell_update_wm(crtc);
526682e9
PZ		 2615}
2616
243e6a44
VS		 2617static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2618{
2619 struct drm_device *dev = crtc->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct hsw_wm_values *hw = &dev_priv->wm.hw;
2622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2623 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2624 enum pipe pipe = intel_crtc->pipe;
2625 static const unsigned int wm0_pipe_reg[] = {
2626 [PIPE_A] = WM0_PIPEA_ILK,
2627 [PIPE_B] = WM0_PIPEB_ILK,
2628 [PIPE_C] = WM0_PIPEC_IVB,
2629 };
2630
2631 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
ce0e0713
VS		 2632 if (IS_HASWELL(dev))
2633 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44
VS		 2634
2635 if (intel_crtc_active(crtc)) {
2636 u32 tmp = hw->wm_pipe[pipe];
2637
2638 /*
2639 * For active pipes LP0 watermark is marked as
2640 * enabled, and LP1+ watermaks as disabled since
2641 * we can't really reverse compute them in case
2642 * multiple pipes are active.
2643 */
2644 active->wm[0].enable = true;
2645 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2646 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2647 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2648 active->linetime = hw->wm_linetime[pipe];
2649 } else {
2650 int level, max_level = ilk_wm_max_level(dev);
2651
2652 /*
2653 * For inactive pipes, all watermark levels
2654 * should be marked as enabled but zeroed,
2655 * which is what we'd compute them to.
2656 */
2657 for (level = 0; level <= max_level; level++)
2658 active->wm[level].enable = true;
2659 }
2660}
2661
2662void ilk_wm_get_hw_state(struct drm_device *dev)
2663{
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct hsw_wm_values *hw = &dev_priv->wm.hw;
2666 struct drm_crtc *crtc;
2667
2668 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2669 ilk_pipe_wm_get_hw_state(crtc);
2670
2671 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2672 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2673 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2674
2675 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2676 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2677 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2678
ac9545fd
VS		 2679 if (IS_HASWELL(dev))
2680 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2681 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2682 else if (IS_IVYBRIDGE(dev))
2683 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2684 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2685
2686 hw->enable_fbc_wm =
2687 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2688}
2689
b445e3b0
ED		 2690/**
2691 * intel_update_watermarks - update FIFO watermark values based on current modes
2692 *
2693 * Calculate watermark values for the various WM regs based on current mode
2694 * and plane configuration.
2695 *
2696 * There are several cases to deal with here:
2697 * - normal (i.e. non-self-refresh)
2698 * - self-refresh (SR) mode
2699 * - lines are large relative to FIFO size (buffer can hold up to 2)
2700 * - lines are small relative to FIFO size (buffer can hold more than 2
2701 * lines), so need to account for TLB latency
2702 *
2703 * The normal calculation is:
2704 * watermark = dotclock * bytes per pixel * latency
2705 * where latency is platform & configuration dependent (we assume pessimal
2706 * values here).
2707 *
2708 * The SR calculation is:
2709 * watermark = (trunc(latency/line time)+1) * surface width *
2710 * bytes per pixel
2711 * where
2712 * line time = htotal / dotclock
2713 * surface width = hdisplay for normal plane and 64 for cursor
2714 * and latency is assumed to be high, as above.
2715 *
2716 * The final value programmed to the register should always be rounded up,
2717 * and include an extra 2 entries to account for clock crossings.
2718 *
2719 * We don't use the sprite, so we can ignore that. And on Crestline we have
2720 * to set the non-SR watermarks to 8.
2721 */
46ba614c 2722void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2723{
46ba614c 2724 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2725
2726 if (dev_priv->display.update_wm)
46ba614c 2727 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2728}
2729
adf3d35e
VS		 2730void intel_update_sprite_watermarks(struct drm_plane *plane,
2731 struct drm_crtc *crtc,
4c4ff43a 2732 uint32_t sprite_width, int pixel_size,
39db4a4d 2733 bool enabled, bool scaled)
b445e3b0 2734{
adf3d35e 2735 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2736
2737 if (dev_priv->display.update_sprite_wm)
adf3d35e 2738 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2739 pixel_size, enabled, scaled);
b445e3b0
ED		 2740}
2741
2b4e57bd
ED		 2742static struct drm_i915_gem_object *
2743intel_alloc_context_page(struct drm_device *dev)
2744{
2745 struct drm_i915_gem_object *ctx;
2746 int ret;
2747
2748 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2749
2750 ctx = i915_gem_alloc_object(dev, 4096);
2751 if (!ctx) {
2752 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2753 return NULL;
2754 }
2755
c37e2204 2756 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2757 if (ret) {
2758 DRM_ERROR("failed to pin power context: %d\n", ret);
2759 goto err_unref;
2760 }
2761
2762 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2763 if (ret) {
2764 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2765 goto err_unpin;
2766 }
2767
2768 return ctx;
2769
2770err_unpin:
2771 i915_gem_object_unpin(ctx);
2772err_unref:
2773 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2774 return NULL;
2775}
2776
9270388e
DV		 2777/**
2778 * Lock protecting IPS related data structures
9270388e
DV		 2779 */
2780DEFINE_SPINLOCK(mchdev_lock);
2781
2782/* Global for IPS driver to get at the current i915 device. Protected by
2783 * mchdev_lock. */
2784static struct drm_i915_private *i915_mch_dev;
2785
2b4e57bd
ED		 2786bool ironlake_set_drps(struct drm_device *dev, u8 val)
2787{
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 u16 rgvswctl;
2790
9270388e
DV		 2791 assert_spin_locked(&mchdev_lock);
2792
2b4e57bd
ED		 2793 rgvswctl = I915_READ16(MEMSWCTL);
2794 if (rgvswctl & MEMCTL_CMD_STS) {
2795 DRM_DEBUG("gpu busy, RCS change rejected\n");
2796 return false; /* still busy with another command */
2797 }
2798
2799 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2800 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2801 I915_WRITE16(MEMSWCTL, rgvswctl);
2802 POSTING_READ16(MEMSWCTL);
2803
2804 rgvswctl |= MEMCTL_CMD_STS;
2805 I915_WRITE16(MEMSWCTL, rgvswctl);
2806
2807 return true;
2808}
2809
8090c6b9 2810static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2811{
2812 struct drm_i915_private *dev_priv = dev->dev_private;
2813 u32 rgvmodectl = I915_READ(MEMMODECTL);
2814 u8 fmax, fmin, fstart, vstart;
2815
9270388e
DV		 2816 spin_lock_irq(&mchdev_lock);
2817
2b4e57bd
ED		 2818 /* Enable temp reporting */
2819 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2820 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2821
2822 /* 100ms RC evaluation intervals */
2823 I915_WRITE(RCUPEI, 100000);
2824 I915_WRITE(RCDNEI, 100000);
2825
2826 /* Set max/min thresholds to 90ms and 80ms respectively */
2827 I915_WRITE(RCBMAXAVG, 90000);
2828 I915_WRITE(RCBMINAVG, 80000);
2829
2830 I915_WRITE(MEMIHYST, 1);
2831
2832 /* Set up min, max, and cur for interrupt handling */
2833 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2834 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2835 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2836 MEMMODE_FSTART_SHIFT;
2837
2838 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2839 PXVFREQ_PX_SHIFT;
2840
20e4d407
DV		 2841 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2842 dev_priv->ips.fstart = fstart;
2b4e57bd 2843
20e4d407
DV		 2844 dev_priv->ips.max_delay = fstart;
2845 dev_priv->ips.min_delay = fmin;
2846 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2847
2848 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2849 fmax, fmin, fstart);
2850
2851 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2852
2853 /*
2854 * Interrupts will be enabled in ironlake_irq_postinstall
2855 */
2856
2857 I915_WRITE(VIDSTART, vstart);
2858 POSTING_READ(VIDSTART);
2859
2860 rgvmodectl |= MEMMODE_SWMODE_EN;
2861 I915_WRITE(MEMMODECTL, rgvmodectl);
2862
9270388e 2863 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2864 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2865 mdelay(1);
2b4e57bd
ED		 2866
2867 ironlake_set_drps(dev, fstart);
2868
20e4d407 2869 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2870 I915_READ(0x112e0);
20e4d407
DV		 2871 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2872 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2873 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2874
2875 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2876}
2877
8090c6b9 2878static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2879{
2880 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2881 u16 rgvswctl;
2882
2883 spin_lock_irq(&mchdev_lock);
2884
2885 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2886
2887 /* Ack interrupts, disable EFC interrupt */
2888 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2889 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2890 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2891 I915_WRITE(DEIIR, DE_PCU_EVENT);
2892 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2893
2894 /* Go back to the starting frequency */
20e4d407 2895 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2896 mdelay(1);
2b4e57bd
ED		 2897 rgvswctl |= MEMCTL_CMD_STS;
2898 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2899 mdelay(1);
2b4e57bd 2900
9270388e 2901 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2902}
2903
acbe9475
DV		 2904/* There's a funny hw issue where the hw returns all 0 when reading from
2905 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2906 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2907 * all limits and the gpu stuck at whatever frequency it is at atm).
2908 */
6917c7b9 2909static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 2910{
7b9e0ae6 2911 u32 limits;
2b4e57bd 2912
20b46e59
DV		 2913 /* Only set the down limit when we've reached the lowest level to avoid
2914 * getting more interrupts, otherwise leave this clear. This prevents a
2915 * race in the hw when coming out of rc6: There's a tiny window where
2916 * the hw runs at the minimal clock before selecting the desired
2917 * frequency, if the down threshold expires in that window we will not
2918 * receive a down interrupt. */
6917c7b9
CW		 2919 limits = dev_priv->rps.max_delay << 24;
2920 if (val <= dev_priv->rps.min_delay)
c6a828d3 2921 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2922
2923 return limits;
2924}
2925
dd75fdc8
CW		 2926static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2927{
2928 int new_power;
2929
2930 new_power = dev_priv->rps.power;
2931 switch (dev_priv->rps.power) {
2932 case LOW_POWER:
2933 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
2934 new_power = BETWEEN;
2935 break;
2936
2937 case BETWEEN:
2938 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
2939 new_power = LOW_POWER;
2940 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
2941 new_power = HIGH_POWER;
2942 break;
2943
2944 case HIGH_POWER:
2945 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
2946 new_power = BETWEEN;
2947 break;
2948 }
2949 /* Max/min bins are special */
2950 if (val == dev_priv->rps.min_delay)
2951 new_power = LOW_POWER;
2952 if (val == dev_priv->rps.max_delay)
2953 new_power = HIGH_POWER;
2954 if (new_power == dev_priv->rps.power)
2955 return;
2956
2957 /* Note the units here are not exactly 1us, but 1280ns. */
2958 switch (new_power) {
2959 case LOW_POWER:
2960 /* Upclock if more than 95% busy over 16ms */
2961 I915_WRITE(GEN6_RP_UP_EI, 12500);
2962 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
2963
2964 /* Downclock if less than 85% busy over 32ms */
2965 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2966 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
2967
2968 I915_WRITE(GEN6_RP_CONTROL,
2969 GEN6_RP_MEDIA_TURBO |
2970 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2971 GEN6_RP_MEDIA_IS_GFX |
2972 GEN6_RP_ENABLE |
2973 GEN6_RP_UP_BUSY_AVG |
2974 GEN6_RP_DOWN_IDLE_AVG);
2975 break;
2976
2977 case BETWEEN:
2978 /* Upclock if more than 90% busy over 13ms */
2979 I915_WRITE(GEN6_RP_UP_EI, 10250);
2980 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
2981
2982 /* Downclock if less than 75% busy over 32ms */
2983 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
2984 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
2985
2986 I915_WRITE(GEN6_RP_CONTROL,
2987 GEN6_RP_MEDIA_TURBO |
2988 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2989 GEN6_RP_MEDIA_IS_GFX |
2990 GEN6_RP_ENABLE |
2991 GEN6_RP_UP_BUSY_AVG |
2992 GEN6_RP_DOWN_IDLE_AVG);
2993 break;
2994
2995 case HIGH_POWER:
2996 /* Upclock if more than 85% busy over 10ms */
2997 I915_WRITE(GEN6_RP_UP_EI, 8000);
2998 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
2999
3000 /* Downclock if less than 60% busy over 32ms */
3001 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3002 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3003
3004 I915_WRITE(GEN6_RP_CONTROL,
3005 GEN6_RP_MEDIA_TURBO |
3006 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3007 GEN6_RP_MEDIA_IS_GFX |
3008 GEN6_RP_ENABLE |
3009 GEN6_RP_UP_BUSY_AVG |
3010 GEN6_RP_DOWN_IDLE_AVG);
3011 break;
3012 }
3013
3014 dev_priv->rps.power = new_power;
3015 dev_priv->rps.last_adj = 0;
3016}
3017
20b46e59
DV		 3018void gen6_set_rps(struct drm_device *dev, u8 val)
3019{
3020 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3021
4fc688ce 3022 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3023 WARN_ON(val > dev_priv->rps.max_delay);
3024 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3025
c6a828d3 3026 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3027 return;
3028
dd75fdc8
CW		 3029 gen6_set_rps_thresholds(dev_priv, val);
3030
92bd1bf0
RV		 3031 if (IS_HASWELL(dev))
3032 I915_WRITE(GEN6_RPNSWREQ,
3033 HSW_FREQUENCY(val));
3034 else
3035 I915_WRITE(GEN6_RPNSWREQ,
3036 GEN6_FREQUENCY(val) |
3037 GEN6_OFFSET(0) |
3038 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3039
3040 /* Make sure we continue to get interrupts
3041 * until we hit the minimum or maximum frequencies.
3042 */
6917c7b9
CW		 3043 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3044 gen6_rps_limits(dev_priv, val));
7b9e0ae6 3045
d5570a72
BW		 3046 POSTING_READ(GEN6_RPNSWREQ);
3047
c6a828d3 3048 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3049
3050 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3051}
3052
b29c19b6
CW		 3053void gen6_rps_idle(struct drm_i915_private *dev_priv)
3054{
691bb717
DL		 3055 struct drm_device *dev = dev_priv->dev;
3056
b29c19b6 3057 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3058 if (dev_priv->rps.enabled) {
691bb717 3059 if (IS_VALLEYVIEW(dev))
c0951f0c
CW		 3060 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3061 else
3062 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3063 dev_priv->rps.last_adj = 0;
3064 }
b29c19b6
CW		 3065 mutex_unlock(&dev_priv->rps.hw_lock);
3066}
3067
3068void gen6_rps_boost(struct drm_i915_private *dev_priv)
3069{
691bb717
DL		 3070 struct drm_device *dev = dev_priv->dev;
3071
b29c19b6 3072 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3073 if (dev_priv->rps.enabled) {
691bb717 3074 if (IS_VALLEYVIEW(dev))
c0951f0c
CW		 3075 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3076 else
3077 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3078 dev_priv->rps.last_adj = 0;
3079 }
b29c19b6
CW		 3080 mutex_unlock(&dev_priv->rps.hw_lock);
3081}
3082
0a073b84
JB		 3083void valleyview_set_rps(struct drm_device *dev, u8 val)
3084{
3085 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3086
0a073b84
JB		 3087 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3088 WARN_ON(val > dev_priv->rps.max_delay);
3089 WARN_ON(val < dev_priv->rps.min_delay);
3090
73008b98 3091 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
2ec3815f 3092 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3093 dev_priv->rps.cur_delay,
2ec3815f 3094 vlv_gpu_freq(dev_priv, val), val);
0a073b84
JB		 3095
3096 if (val == dev_priv->rps.cur_delay)
3097 return;
3098
ae99258f 3099 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3100
80814ae4 3101 dev_priv->rps.cur_delay = val;
0a073b84 3102
2ec3815f 3103 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3104}
3105
44fc7d5c 3106static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3107{
3108 struct drm_i915_private *dev_priv = dev->dev_private;
3109
2b4e57bd 3110 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3111 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3112 /* Complete PM interrupt masking here doesn't race with the rps work
3113 * item again unmasking PM interrupts because that is using a different
3114 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3115 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3116
59cdb63d 3117 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3118 dev_priv->rps.pm_iir = 0;
59cdb63d 3119 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3120
4848405c 3121 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3122}
3123
44fc7d5c 3124static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3125{
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127
3128 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3129 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3130
44fc7d5c
DV		 3131 gen6_disable_rps_interrupts(dev);
3132}
3133
3134static void valleyview_disable_rps(struct drm_device *dev)
3135{
3136 struct drm_i915_private *dev_priv = dev->dev_private;
3137
3138 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3139
44fc7d5c 3140 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3141
3142 if (dev_priv->vlv_pctx) {
3143 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3144 dev_priv->vlv_pctx = NULL;
3145 }
d20d4f0c
JB		 3146}
3147
dc39fff7
BW		 3148static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3149{
3150 if (IS_GEN6(dev))
3151 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3152
3153 if (IS_HASWELL(dev))
3154 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3155
3156 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3157 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3158 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3159 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3160}
3161
2b4e57bd
ED		 3162int intel_enable_rc6(const struct drm_device *dev)
3163{
eb4926e4
DL		 3164 /* No RC6 before Ironlake */
3165 if (INTEL_INFO(dev)->gen < 5)
3166 return 0;
3167
456470eb 3168 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3169 if (i915_enable_rc6 >= 0)
3170 return i915_enable_rc6;
3171
6567d748
CW		 3172 /* Disable RC6 on Ironlake */
3173 if (INTEL_INFO(dev)->gen == 5)
3174 return 0;
2b4e57bd 3175
dc39fff7 3176 if (IS_HASWELL(dev))
4a637c2c 3177 return INTEL_RC6_ENABLE;
2b4e57bd 3178
456470eb 3179 /* snb/ivb have more than one rc6 state. */
dc39fff7 3180 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3181 return INTEL_RC6_ENABLE;
456470eb 3182
2b4e57bd
ED		 3183 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3184}
3185
44fc7d5c
DV		 3186static void gen6_enable_rps_interrupts(struct drm_device *dev)
3187{
3188 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3189 u32 enabled_intrs;
44fc7d5c
DV		 3190
3191 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3192 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3193 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3194 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3195 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3196
fd547d25 3197 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3198 enabled_intrs = GEN6_PM_RPS_EVENTS;
3199
3200 /* IVB and SNB hard hangs on looping batchbuffer
3201 * if GEN6_PM_UP_EI_EXPIRED is masked.
3202 */
3203 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3204 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3205
3206 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3207}
3208
6edee7f3
BW		 3209static void gen8_enable_rps(struct drm_device *dev)
3210{
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3212 struct intel_ring_buffer *ring;
3213 uint32_t rc6_mask = 0, rp_state_cap;
3214 int unused;
3215
3216 /* 1a: Software RC state - RC0 */
3217 I915_WRITE(GEN6_RC_STATE, 0);
3218
3219 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3220 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3221 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3222
3223 /* 2a: Disable RC states. */
3224 I915_WRITE(GEN6_RC_CONTROL, 0);
3225
3226 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3227
3228 /* 2b: Program RC6 thresholds.*/
3229 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3230 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3231 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3232 for_each_ring(ring, dev_priv, unused)
3233 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3234 I915_WRITE(GEN6_RC_SLEEP, 0);
3235 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3236
3237 /* 3: Enable RC6 */
3238 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3239 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3240 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3241 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3242 GEN6_RC_CTL_EI_MODE(1) |
3243 rc6_mask);
3244
3245 /* 4 Program defaults and thresholds for RPS*/
3246 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3247 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3248 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3249 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3250
3251 /* Docs recommend 900MHz, and 300 MHz respectively */
3252 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3253 dev_priv->rps.max_delay << 24 |
3254 dev_priv->rps.min_delay << 16);
3255
3256 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3257 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3258 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3259 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3260
3261 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3262
3263 /* 5: Enable RPS */
3264 I915_WRITE(GEN6_RP_CONTROL,
3265 GEN6_RP_MEDIA_TURBO |
3266 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3267 GEN6_RP_MEDIA_IS_GFX |
3268 GEN6_RP_ENABLE |
3269 GEN6_RP_UP_BUSY_AVG |
3270 GEN6_RP_DOWN_IDLE_AVG);
3271
3272 /* 6: Ring frequency + overclocking (our driver does this later */
3273
3274 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3275
3276 gen6_enable_rps_interrupts(dev);
3277
c8d9a590 3278 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3279}
3280
79f5b2c7 3281static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3282{
79f5b2c7 3283 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3284 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3285 u32 rp_state_cap;
3286 u32 gt_perf_status;
31643d54 3287 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3288 u32 gtfifodbg;
2b4e57bd 3289 int rc6_mode;
42c0526c 3290 int i, ret;
2b4e57bd 3291
4fc688ce 3292 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3293
2b4e57bd
ED		 3294 /* Here begins a magic sequence of register writes to enable
3295 * auto-downclocking.
3296 *
3297 * Perhaps there might be some value in exposing these to
3298 * userspace...
3299 */
3300 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3301
3302 /* Clear the DBG now so we don't confuse earlier errors */
3303 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3304 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3305 I915_WRITE(GTFIFODBG, gtfifodbg);
3306 }
3307
c8d9a590 3308 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3309
7b9e0ae6
CW		 3310 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3311 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3312
31c77388
BW		 3313 /* In units of 50MHz */
3314 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3315 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3316 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3317 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3318 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3319 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3320
2b4e57bd
ED		 3321 /* disable the counters and set deterministic thresholds */
3322 I915_WRITE(GEN6_RC_CONTROL, 0);
3323
3324 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3325 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3326 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3327 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3328 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3329
b4519513
CW		 3330 for_each_ring(ring, dev_priv, i)
3331 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3332
3333 I915_WRITE(GEN6_RC_SLEEP, 0);
3334 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3335 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3336 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3337 else
3338 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3339 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3340 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3341
5a7dc92a 3342 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3343 rc6_mode = intel_enable_rc6(dev_priv->dev);
3344 if (rc6_mode & INTEL_RC6_ENABLE)
3345 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3346
5a7dc92a
ED		 3347 /* We don't use those on Haswell */
3348 if (!IS_HASWELL(dev)) {
3349 if (rc6_mode & INTEL_RC6p_ENABLE)
3350 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3351
5a7dc92a
ED		 3352 if (rc6_mode & INTEL_RC6pp_ENABLE)
3353 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3354 }
2b4e57bd 3355
dc39fff7 3356 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3357
3358 I915_WRITE(GEN6_RC_CONTROL,
3359 rc6_mask |
3360 GEN6_RC_CTL_EI_MODE(1) |
3361 GEN6_RC_CTL_HW_ENABLE);
3362
dd75fdc8
CW		 3363 /* Power down if completely idle for over 50ms */
3364 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3365 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3366
42c0526c 3367 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3368 if (!ret) {
42c0526c
BW		 3369 pcu_mbox = 0;
3370 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3371 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3372 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3373 (dev_priv->rps.max_delay & 0xff) * 50,
3374 (pcu_mbox & 0xff) * 50);
31c77388 3375 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3376 }
3377 } else {
3378 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3379 }
3380
dd75fdc8
CW		 3381 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3382 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3383
44fc7d5c 3384 gen6_enable_rps_interrupts(dev);
2b4e57bd 3385
31643d54
BW		 3386 rc6vids = 0;
3387 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3388 if (IS_GEN6(dev) && ret) {
3389 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3390 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3391 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3392 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3393 rc6vids &= 0xffff00;
3394 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3395 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3396 if (ret)
3397 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3398 }
3399
c8d9a590 3400 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3401}
3402
c67a470b 3403void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3404{
79f5b2c7 3405 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3406 int min_freq = 15;
3ebecd07
CW		 3407 unsigned int gpu_freq;
3408 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3409 int scaling_factor = 180;
eda79642 3410 struct cpufreq_policy *policy;
2b4e57bd 3411
4fc688ce 3412 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3413
eda79642
BW		 3414 policy = cpufreq_cpu_get(0);
3415 if (policy) {
3416 max_ia_freq = policy->cpuinfo.max_freq;
3417 cpufreq_cpu_put(policy);
3418 } else {
3419 /*
3420 * Default to measured freq if none found, PCU will ensure we
3421 * don't go over
3422 */
2b4e57bd 3423 max_ia_freq = tsc_khz;
eda79642 3424 }
2b4e57bd
ED		 3425
3426 /* Convert from kHz to MHz */
3427 max_ia_freq /= 1000;
3428
153b4b95 3429 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3430 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3431 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3432
2b4e57bd
ED		 3433 /*
3434 * For each potential GPU frequency, load a ring frequency we'd like
3435 * to use for memory access. We do this by specifying the IA frequency
3436 * the PCU should use as a reference to determine the ring frequency.
3437 */
c6a828d3 3438 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3439 gpu_freq--) {
c6a828d3 3440 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3441 unsigned int ia_freq = 0, ring_freq = 0;
3442
46c764d4
BW		 3443 if (INTEL_INFO(dev)->gen >= 8) {
3444 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3445 ring_freq = max(min_ring_freq, gpu_freq);
3446 } else if (IS_HASWELL(dev)) {
f6aca45c 3447 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3448 ring_freq = max(min_ring_freq, ring_freq);
3449 /* leave ia_freq as the default, chosen by cpufreq */
3450 } else {
3451 /* On older processors, there is no separate ring
3452 * clock domain, so in order to boost the bandwidth
3453 * of the ring, we need to upclock the CPU (ia_freq).
3454 *
3455 * For GPU frequencies less than 750MHz,
3456 * just use the lowest ring freq.
3457 */
3458 if (gpu_freq < min_freq)
3459 ia_freq = 800;
3460 else
3461 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3462 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3463 }
2b4e57bd 3464
42c0526c
BW		 3465 sandybridge_pcode_write(dev_priv,
3466 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3467 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3468 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3469 gpu_freq);
2b4e57bd 3470 }
2b4e57bd
ED		 3471}
3472
0a073b84
JB		 3473int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3474{
3475 u32 val, rp0;
3476
64936258 3477 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3478
3479 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3480 /* Clamp to max */
3481 rp0 = min_t(u32, rp0, 0xea);
3482
3483 return rp0;
3484}
3485
3486static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3487{
3488 u32 val, rpe;
3489
64936258 3490 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3491 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3492 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3493 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3494
3495 return rpe;
3496}
3497
3498int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3499{
64936258 3500 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3501}
3502
c9cddffc
JB		 3503static void valleyview_setup_pctx(struct drm_device *dev)
3504{
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct drm_i915_gem_object *pctx;
3507 unsigned long pctx_paddr;
3508 u32 pcbr;
3509 int pctx_size = 24*1024;
3510
3511 pcbr = I915_READ(VLV_PCBR);
3512 if (pcbr) {
3513 /* BIOS set it up already, grab the pre-alloc'd space */
3514 int pcbr_offset;
3515
3516 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3517 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3518 pcbr_offset,
190d6cd5 3519 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3520 pctx_size);
3521 goto out;
3522 }
3523
3524 /*
3525 * From the Gunit register HAS:
3526 * The Gfx driver is expected to program this register and ensure
3527 * proper allocation within Gfx stolen memory. For example, this
3528 * register should be programmed such than the PCBR range does not
3529 * overlap with other ranges, such as the frame buffer, protected
3530 * memory, or any other relevant ranges.
3531 */
3532 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3533 if (!pctx) {
3534 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3535 return;
3536 }
3537
3538 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3539 I915_WRITE(VLV_PCBR, pctx_paddr);
3540
3541out:
3542 dev_priv->vlv_pctx = pctx;
3543}
3544
0a073b84
JB		 3545static void valleyview_enable_rps(struct drm_device *dev)
3546{
3547 struct drm_i915_private *dev_priv = dev->dev_private;
3548 struct intel_ring_buffer *ring;
a2b23fe0 3549 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3550 int i;
3551
3552 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3553
3554 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3555 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3556 gtfifodbg);
0a073b84
JB		 3557 I915_WRITE(GTFIFODBG, gtfifodbg);
3558 }
3559
c9cddffc
JB		 3560 valleyview_setup_pctx(dev);
3561
c8d9a590
D		 3562 /* If VLV, Forcewake all wells, else re-direct to regular path */
3563 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3564
3565 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3566 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3567 I915_WRITE(GEN6_RP_UP_EI, 66000);
3568 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3569
3570 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3571
3572 I915_WRITE(GEN6_RP_CONTROL,
3573 GEN6_RP_MEDIA_TURBO |
3574 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3575 GEN6_RP_MEDIA_IS_GFX |
3576 GEN6_RP_ENABLE |
3577 GEN6_RP_UP_BUSY_AVG |
3578 GEN6_RP_DOWN_IDLE_CONT);
3579
3580 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3581 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3582 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3583
3584 for_each_ring(ring, dev_priv, i)
3585 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3586
2f0aa304 3587 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 3588
3589 /* allows RC6 residency counter to work */
49798eb2
JB		 3590 I915_WRITE(VLV_COUNTER_CONTROL,
3591 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3592 VLV_MEDIA_RC6_COUNT_EN |
3593 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 3594 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 3595 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 3596
3597 intel_print_rc6_info(dev, rc6_mode);
3598
a2b23fe0 3599 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3600
64936258 3601 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3602
3603 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3604 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3605
0a073b84 3606 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98 3607 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
2ec3815f 3608 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3609 dev_priv->rps.cur_delay);
0a073b84
JB		 3610
3611 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3612 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98 3613 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
2ec3815f 3614 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
73008b98 3615 dev_priv->rps.max_delay);
0a073b84 3616
73008b98
VS		 3617 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3618 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
2ec3815f 3619 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 3620 dev_priv->rps.rpe_delay);
0a073b84 3621
73008b98
VS		 3622 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3623 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
2ec3815f 3624 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
73008b98 3625 dev_priv->rps.min_delay);
0a073b84 3626
73008b98 3627 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
2ec3815f 3628 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 3629 dev_priv->rps.rpe_delay);
0a073b84 3630
73008b98 3631 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3632
44fc7d5c 3633 gen6_enable_rps_interrupts(dev);
0a073b84 3634
c8d9a590 3635 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3636}
3637
930ebb46 3638void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3639{
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641
3e373948
DV		 3642 if (dev_priv->ips.renderctx) {
3643 i915_gem_object_unpin(dev_priv->ips.renderctx);
3644 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3645 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3646 }
3647
3e373948
DV		 3648 if (dev_priv->ips.pwrctx) {
3649 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3650 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3651 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3652 }
3653}
3654
930ebb46 3655static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3656{
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658
3659 if (I915_READ(PWRCTXA)) {
3660 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3661 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3662 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3663 50);
3664
3665 I915_WRITE(PWRCTXA, 0);
3666 POSTING_READ(PWRCTXA);
3667
3668 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3669 POSTING_READ(RSTDBYCTL);
3670 }
2b4e57bd
ED		 3671}
3672
3673static int ironlake_setup_rc6(struct drm_device *dev)
3674{
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676
3e373948
DV		 3677 if (dev_priv->ips.renderctx == NULL)
3678 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3679 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3680 return -ENOMEM;
3681
3e373948
DV		 3682 if (dev_priv->ips.pwrctx == NULL)
3683 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3684 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3685 ironlake_teardown_rc6(dev);
3686 return -ENOMEM;
3687 }
3688
3689 return 0;
3690}
3691
930ebb46 3692static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3693{
3694 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3695 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3696 bool was_interruptible;
2b4e57bd
ED		 3697 int ret;
3698
3699 /* rc6 disabled by default due to repeated reports of hanging during
3700 * boot and resume.
3701 */
3702 if (!intel_enable_rc6(dev))
3703 return;
3704
79f5b2c7
DV		 3705 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3706
2b4e57bd 3707 ret = ironlake_setup_rc6(dev);
79f5b2c7 3708 if (ret)
2b4e57bd 3709 return;
2b4e57bd 3710
3e960501
CW		 3711 was_interruptible = dev_priv->mm.interruptible;
3712 dev_priv->mm.interruptible = false;
3713
2b4e57bd
ED		 3714 /*
3715 * GPU can automatically power down the render unit if given a page
3716 * to save state.
3717 */
6d90c952 3718 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3719 if (ret) {
3720 ironlake_teardown_rc6(dev);
3e960501 3721 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3722 return;
3723 }
3724
6d90c952
DV		 3725 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3726 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3727 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3728 MI_MM_SPACE_GTT |
3729 MI_SAVE_EXT_STATE_EN |
3730 MI_RESTORE_EXT_STATE_EN |
3731 MI_RESTORE_INHIBIT);
3732 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3733 intel_ring_emit(ring, MI_NOOP);
3734 intel_ring_emit(ring, MI_FLUSH);
3735 intel_ring_advance(ring);
2b4e57bd
ED		 3736
3737 /*
3738 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3739 * does an implicit flush, combined with MI_FLUSH above, it should be
3740 * safe to assume that renderctx is valid
3741 */
3e960501
CW		 3742 ret = intel_ring_idle(ring);
3743 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3744 if (ret) {
def27a58 3745 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3746 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3747 return;
3748 }
3749
f343c5f6 3750 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3751 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 3752
3753 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 3754}
3755
dde18883
ED		 3756static unsigned long intel_pxfreq(u32 vidfreq)
3757{
3758 unsigned long freq;
3759 int div = (vidfreq & 0x3f0000) >> 16;
3760 int post = (vidfreq & 0x3000) >> 12;
3761 int pre = (vidfreq & 0x7);
3762
3763 if (!pre)
3764 return 0;
3765
3766 freq = ((div * 133333) / ((1<<post) * pre));
3767
3768 return freq;
3769}
3770
eb48eb00
DV		 3771static const struct cparams {
3772 u16 i;
3773 u16 t;
3774 u16 m;
3775 u16 c;
3776} cparams[] = {
3777 { 1, 1333, 301, 28664 },
3778 { 1, 1066, 294, 24460 },
3779 { 1, 800, 294, 25192 },
3780 { 0, 1333, 276, 27605 },
3781 { 0, 1066, 276, 27605 },
3782 { 0, 800, 231, 23784 },
3783};
3784
f531dcb2 3785static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3786{
3787 u64 total_count, diff, ret;
3788 u32 count1, count2, count3, m = 0, c = 0;
3789 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3790 int i;
3791
02d71956
DV		 3792 assert_spin_locked(&mchdev_lock);
3793
20e4d407 3794 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3795
3796 /* Prevent division-by-zero if we are asking too fast.
3797 * Also, we don't get interesting results if we are polling
3798 * faster than once in 10ms, so just return the saved value
3799 * in such cases.
3800 */
3801 if (diff1 <= 10)
20e4d407 3802 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3803
3804 count1 = I915_READ(DMIEC);
3805 count2 = I915_READ(DDREC);
3806 count3 = I915_READ(CSIEC);
3807
3808 total_count = count1 + count2 + count3;
3809
3810 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3811 if (total_count < dev_priv->ips.last_count1) {
3812 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3813 diff += total_count;
3814 } else {
20e4d407 3815 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3816 }
3817
3818 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3819 if (cparams[i].i == dev_priv->ips.c_m &&
3820 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3821 m = cparams[i].m;
3822 c = cparams[i].c;
3823 break;
3824 }
3825 }
3826
3827 diff = div_u64(diff, diff1);
3828 ret = ((m * diff) + c);
3829 ret = div_u64(ret, 10);
3830
20e4d407
DV		 3831 dev_priv->ips.last_count1 = total_count;
3832 dev_priv->ips.last_time1 = now;
eb48eb00 3833
20e4d407 3834 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3835
3836 return ret;
3837}
3838
f531dcb2
CW		 3839unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3840{
3841 unsigned long val;
3842
3843 if (dev_priv->info->gen != 5)
3844 return 0;
3845
3846 spin_lock_irq(&mchdev_lock);
3847
3848 val = __i915_chipset_val(dev_priv);
3849
3850 spin_unlock_irq(&mchdev_lock);
3851
3852 return val;
3853}
3854
eb48eb00
DV		 3855unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3856{
3857 unsigned long m, x, b;
3858 u32 tsfs;
3859
3860 tsfs = I915_READ(TSFS);
3861
3862 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3863 x = I915_READ8(TR1);
3864
3865 b = tsfs & TSFS_INTR_MASK;
3866
3867 return ((m * x) / 127) - b;
3868}
3869
3870static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3871{
3872 static const struct v_table {
3873 u16 vd; /* in .1 mil */
3874 u16 vm; /* in .1 mil */
3875 } v_table[] = {
3876 { 0, 0, },
3877 { 375, 0, },
3878 { 500, 0, },
3879 { 625, 0, },
3880 { 750, 0, },
3881 { 875, 0, },
3882 { 1000, 0, },
3883 { 1125, 0, },
3884 { 4125, 3000, },
3885 { 4125, 3000, },
3886 { 4125, 3000, },
3887 { 4125, 3000, },
3888 { 4125, 3000, },
3889 { 4125, 3000, },
3890 { 4125, 3000, },
3891 { 4125, 3000, },
3892 { 4125, 3000, },
3893 { 4125, 3000, },
3894 { 4125, 3000, },
3895 { 4125, 3000, },
3896 { 4125, 3000, },
3897 { 4125, 3000, },
3898 { 4125, 3000, },
3899 { 4125, 3000, },
3900 { 4125, 3000, },
3901 { 4125, 3000, },
3902 { 4125, 3000, },
3903 { 4125, 3000, },
3904 { 4125, 3000, },
3905 { 4125, 3000, },
3906 { 4125, 3000, },
3907 { 4125, 3000, },
3908 { 4250, 3125, },
3909 { 4375, 3250, },
3910 { 4500, 3375, },
3911 { 4625, 3500, },
3912 { 4750, 3625, },
3913 { 4875, 3750, },
3914 { 5000, 3875, },
3915 { 5125, 4000, },
3916 { 5250, 4125, },
3917 { 5375, 4250, },
3918 { 5500, 4375, },
3919 { 5625, 4500, },
3920 { 5750, 4625, },
3921 { 5875, 4750, },
3922 { 6000, 4875, },
3923 { 6125, 5000, },
3924 { 6250, 5125, },
3925 { 6375, 5250, },
3926 { 6500, 5375, },
3927 { 6625, 5500, },
3928 { 6750, 5625, },
3929 { 6875, 5750, },
3930 { 7000, 5875, },
3931 { 7125, 6000, },
3932 { 7250, 6125, },
3933 { 7375, 6250, },
3934 { 7500, 6375, },
3935 { 7625, 6500, },
3936 { 7750, 6625, },
3937 { 7875, 6750, },
3938 { 8000, 6875, },
3939 { 8125, 7000, },
3940 { 8250, 7125, },
3941 { 8375, 7250, },
3942 { 8500, 7375, },
3943 { 8625, 7500, },
3944 { 8750, 7625, },
3945 { 8875, 7750, },
3946 { 9000, 7875, },
3947 { 9125, 8000, },
3948 { 9250, 8125, },
3949 { 9375, 8250, },
3950 { 9500, 8375, },
3951 { 9625, 8500, },
3952 { 9750, 8625, },
3953 { 9875, 8750, },
3954 { 10000, 8875, },
3955 { 10125, 9000, },
3956 { 10250, 9125, },
3957 { 10375, 9250, },
3958 { 10500, 9375, },
3959 { 10625, 9500, },
3960 { 10750, 9625, },
3961 { 10875, 9750, },
3962 { 11000, 9875, },
3963 { 11125, 10000, },
3964 { 11250, 10125, },
3965 { 11375, 10250, },
3966 { 11500, 10375, },
3967 { 11625, 10500, },
3968 { 11750, 10625, },
3969 { 11875, 10750, },
3970 { 12000, 10875, },
3971 { 12125, 11000, },
3972 { 12250, 11125, },
3973 { 12375, 11250, },
3974 { 12500, 11375, },
3975 { 12625, 11500, },
3976 { 12750, 11625, },
3977 { 12875, 11750, },
3978 { 13000, 11875, },
3979 { 13125, 12000, },
3980 { 13250, 12125, },
3981 { 13375, 12250, },
3982 { 13500, 12375, },
3983 { 13625, 12500, },
3984 { 13750, 12625, },
3985 { 13875, 12750, },
3986 { 14000, 12875, },
3987 { 14125, 13000, },
3988 { 14250, 13125, },
3989 { 14375, 13250, },
3990 { 14500, 13375, },
3991 { 14625, 13500, },
3992 { 14750, 13625, },
3993 { 14875, 13750, },
3994 { 15000, 13875, },
3995 { 15125, 14000, },
3996 { 15250, 14125, },
3997 { 15375, 14250, },
3998 { 15500, 14375, },
3999 { 15625, 14500, },
4000 { 15750, 14625, },
4001 { 15875, 14750, },
4002 { 16000, 14875, },
4003 { 16125, 15000, },
4004 };
4005 if (dev_priv->info->is_mobile)
4006 return v_table[pxvid].vm;
4007 else
4008 return v_table[pxvid].vd;
4009}
4010
02d71956 4011static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4012{
4013 struct timespec now, diff1;
4014 u64 diff;
4015 unsigned long diffms;
4016 u32 count;
4017
02d71956 4018 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4019
4020 getrawmonotonic(&now);
20e4d407 4021 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4022
4023 /* Don't divide by 0 */
4024 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4025 if (!diffms)
4026 return;
4027
4028 count = I915_READ(GFXEC);
4029
20e4d407
DV		 4030 if (count < dev_priv->ips.last_count2) {
4031 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4032 diff += count;
4033 } else {
20e4d407 4034 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4035 }
4036
20e4d407
DV		 4037 dev_priv->ips.last_count2 = count;
4038 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4039
4040 /* More magic constants... */
4041 diff = diff * 1181;
4042 diff = div_u64(diff, diffms * 10);
20e4d407 4043 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4044}
4045
02d71956
DV		 4046void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4047{
4048 if (dev_priv->info->gen != 5)
4049 return;
4050
9270388e 4051 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4052
4053 __i915_update_gfx_val(dev_priv);
4054
9270388e 4055 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4056}
4057
f531dcb2 4058static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4059{
4060 unsigned long t, corr, state1, corr2, state2;
4061 u32 pxvid, ext_v;
4062
02d71956
DV		 4063 assert_spin_locked(&mchdev_lock);
4064
c6a828d3 4065 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4066 pxvid = (pxvid >> 24) & 0x7f;
4067 ext_v = pvid_to_extvid(dev_priv, pxvid);
4068
4069 state1 = ext_v;
4070
4071 t = i915_mch_val(dev_priv);
4072
4073 /* Revel in the empirically derived constants */
4074
4075 /* Correction factor in 1/100000 units */
4076 if (t > 80)
4077 corr = ((t * 2349) + 135940);
4078 else if (t >= 50)
4079 corr = ((t * 964) + 29317);
4080 else /* < 50 */
4081 corr = ((t * 301) + 1004);
4082
4083 corr = corr * ((150142 * state1) / 10000 - 78642);
4084 corr /= 100000;
20e4d407 4085 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4086
4087 state2 = (corr2 * state1) / 10000;
4088 state2 /= 100; /* convert to mW */
4089
02d71956 4090 __i915_update_gfx_val(dev_priv);
eb48eb00 4091
20e4d407 4092 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4093}
4094
f531dcb2
CW		 4095unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4096{
4097 unsigned long val;
4098
4099 if (dev_priv->info->gen != 5)
4100 return 0;
4101
4102 spin_lock_irq(&mchdev_lock);
4103
4104 val = __i915_gfx_val(dev_priv);
4105
4106 spin_unlock_irq(&mchdev_lock);
4107
4108 return val;
4109}
4110
eb48eb00
DV		 4111/**
4112 * i915_read_mch_val - return value for IPS use
4113 *
4114 * Calculate and return a value for the IPS driver to use when deciding whether
4115 * we have thermal and power headroom to increase CPU or GPU power budget.
4116 */
4117unsigned long i915_read_mch_val(void)
4118{
4119 struct drm_i915_private *dev_priv;
4120 unsigned long chipset_val, graphics_val, ret = 0;
4121
9270388e 4122 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4123 if (!i915_mch_dev)
4124 goto out_unlock;
4125 dev_priv = i915_mch_dev;
4126
f531dcb2
CW		 4127 chipset_val = __i915_chipset_val(dev_priv);
4128 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4129
4130 ret = chipset_val + graphics_val;
4131
4132out_unlock:
9270388e 4133 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4134
4135 return ret;
4136}
4137EXPORT_SYMBOL_GPL(i915_read_mch_val);
4138
4139/**
4140 * i915_gpu_raise - raise GPU frequency limit
4141 *
4142 * Raise the limit; IPS indicates we have thermal headroom.
4143 */
4144bool i915_gpu_raise(void)
4145{
4146 struct drm_i915_private *dev_priv;
4147 bool ret = true;
4148
9270388e 4149 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4150 if (!i915_mch_dev) {
4151 ret = false;
4152 goto out_unlock;
4153 }
4154 dev_priv = i915_mch_dev;
4155
20e4d407
DV		 4156 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4157 dev_priv->ips.max_delay--;
eb48eb00
DV		 4158
4159out_unlock:
9270388e 4160 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4161
4162 return ret;
4163}
4164EXPORT_SYMBOL_GPL(i915_gpu_raise);
4165
4166/**
4167 * i915_gpu_lower - lower GPU frequency limit
4168 *
4169 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4170 * frequency maximum.
4171 */
4172bool i915_gpu_lower(void)
4173{
4174 struct drm_i915_private *dev_priv;
4175 bool ret = true;
4176
9270388e 4177 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4178 if (!i915_mch_dev) {
4179 ret = false;
4180 goto out_unlock;
4181 }
4182 dev_priv = i915_mch_dev;
4183
20e4d407
DV		 4184 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4185 dev_priv->ips.max_delay++;
eb48eb00
DV		 4186
4187out_unlock:
9270388e 4188 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4189
4190 return ret;
4191}
4192EXPORT_SYMBOL_GPL(i915_gpu_lower);
4193
4194/**
4195 * i915_gpu_busy - indicate GPU business to IPS
4196 *
4197 * Tell the IPS driver whether or not the GPU is busy.
4198 */
4199bool i915_gpu_busy(void)
4200{
4201 struct drm_i915_private *dev_priv;
f047e395 4202 struct intel_ring_buffer *ring;
eb48eb00 4203 bool ret = false;
f047e395 4204 int i;
eb48eb00 4205
9270388e 4206 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4207 if (!i915_mch_dev)
4208 goto out_unlock;
4209 dev_priv = i915_mch_dev;
4210
f047e395
CW		 4211 for_each_ring(ring, dev_priv, i)
4212 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4213
4214out_unlock:
9270388e 4215 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4216
4217 return ret;
4218}
4219EXPORT_SYMBOL_GPL(i915_gpu_busy);
4220
4221/**
4222 * i915_gpu_turbo_disable - disable graphics turbo
4223 *
4224 * Disable graphics turbo by resetting the max frequency and setting the
4225 * current frequency to the default.
4226 */
4227bool i915_gpu_turbo_disable(void)
4228{
4229 struct drm_i915_private *dev_priv;
4230 bool ret = true;
4231
9270388e 4232 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4233 if (!i915_mch_dev) {
4234 ret = false;
4235 goto out_unlock;
4236 }
4237 dev_priv = i915_mch_dev;
4238
20e4d407 4239 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4240
20e4d407 4241 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4242 ret = false;
4243
4244out_unlock:
9270388e 4245 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4246
4247 return ret;
4248}
4249EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4250
4251/**
4252 * Tells the intel_ips driver that the i915 driver is now loaded, if
4253 * IPS got loaded first.
4254 *
4255 * This awkward dance is so that neither module has to depend on the
4256 * other in order for IPS to do the appropriate communication of
4257 * GPU turbo limits to i915.
4258 */
4259static void
4260ips_ping_for_i915_load(void)
4261{
4262 void (*link)(void);
4263
4264 link = symbol_get(ips_link_to_i915_driver);
4265 if (link) {
4266 link();
4267 symbol_put(ips_link_to_i915_driver);
4268 }
4269}
4270
4271void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4272{
02d71956
DV		 4273 /* We only register the i915 ips part with intel-ips once everything is
4274 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4275 spin_lock_irq(&mchdev_lock);
eb48eb00 4276 i915_mch_dev = dev_priv;
9270388e 4277 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4278
4279 ips_ping_for_i915_load();
4280}
4281
4282void intel_gpu_ips_teardown(void)
4283{
9270388e 4284 spin_lock_irq(&mchdev_lock);
eb48eb00 4285 i915_mch_dev = NULL;
9270388e 4286 spin_unlock_irq(&mchdev_lock);
eb48eb00 4287}
8090c6b9 4288static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4289{
4290 struct drm_i915_private *dev_priv = dev->dev_private;
4291 u32 lcfuse;
4292 u8 pxw[16];
4293 int i;
4294
4295 /* Disable to program */
4296 I915_WRITE(ECR, 0);
4297 POSTING_READ(ECR);
4298
4299 /* Program energy weights for various events */
4300 I915_WRITE(SDEW, 0x15040d00);
4301 I915_WRITE(CSIEW0, 0x007f0000);
4302 I915_WRITE(CSIEW1, 0x1e220004);
4303 I915_WRITE(CSIEW2, 0x04000004);
4304
4305 for (i = 0; i < 5; i++)
4306 I915_WRITE(PEW + (i * 4), 0);
4307 for (i = 0; i < 3; i++)
4308 I915_WRITE(DEW + (i * 4), 0);
4309
4310 /* Program P-state weights to account for frequency power adjustment */
4311 for (i = 0; i < 16; i++) {
4312 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4313 unsigned long freq = intel_pxfreq(pxvidfreq);
4314 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4315 PXVFREQ_PX_SHIFT;
4316 unsigned long val;
4317
4318 val = vid * vid;
4319 val *= (freq / 1000);
4320 val *= 255;
4321 val /= (127*127*900);
4322 if (val > 0xff)
4323 DRM_ERROR("bad pxval: %ld\n", val);
4324 pxw[i] = val;
4325 }
4326 /* Render standby states get 0 weight */
4327 pxw[14] = 0;
4328 pxw[15] = 0;
4329
4330 for (i = 0; i < 4; i++) {
4331 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4332 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4333 I915_WRITE(PXW + (i * 4), val);
4334 }
4335
4336 /* Adjust magic regs to magic values (more experimental results) */
4337 I915_WRITE(OGW0, 0);
4338 I915_WRITE(OGW1, 0);
4339 I915_WRITE(EG0, 0x00007f00);
4340 I915_WRITE(EG1, 0x0000000e);
4341 I915_WRITE(EG2, 0x000e0000);
4342 I915_WRITE(EG3, 0x68000300);
4343 I915_WRITE(EG4, 0x42000000);
4344 I915_WRITE(EG5, 0x00140031);
4345 I915_WRITE(EG6, 0);
4346 I915_WRITE(EG7, 0);
4347
4348 for (i = 0; i < 8; i++)
4349 I915_WRITE(PXWL + (i * 4), 0);
4350
4351 /* Enable PMON + select events */
4352 I915_WRITE(ECR, 0x80000019);
4353
4354 lcfuse = I915_READ(LCFUSE02);
4355
20e4d407 4356 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4357}
4358
8090c6b9
DV		 4359void intel_disable_gt_powersave(struct drm_device *dev)
4360{
1a01ab3b
JB		 4361 struct drm_i915_private *dev_priv = dev->dev_private;
4362
fd0c0642
DV		 4363 /* Interrupts should be disabled already to avoid re-arming. */
4364 WARN_ON(dev->irq_enabled);
4365
930ebb46 4366 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4367 ironlake_disable_drps(dev);
930ebb46 4368 ironlake_disable_rc6(dev);
0a073b84 4369 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4370 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4371 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4372 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4373 if (IS_VALLEYVIEW(dev))
4374 valleyview_disable_rps(dev);
4375 else
4376 gen6_disable_rps(dev);
c0951f0c 4377 dev_priv->rps.enabled = false;
4fc688ce 4378 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4379 }
8090c6b9
DV		 4380}
4381
1a01ab3b
JB		 4382static void intel_gen6_powersave_work(struct work_struct *work)
4383{
4384 struct drm_i915_private *dev_priv =
4385 container_of(work, struct drm_i915_private,
4386 rps.delayed_resume_work.work);
4387 struct drm_device *dev = dev_priv->dev;
4388
4fc688ce 4389 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4390
4391 if (IS_VALLEYVIEW(dev)) {
4392 valleyview_enable_rps(dev);
6edee7f3
BW		 4393 } else if (IS_BROADWELL(dev)) {
4394 gen8_enable_rps(dev);
4395 gen6_update_ring_freq(dev);
0a073b84
JB		 4396 } else {
4397 gen6_enable_rps(dev);
4398 gen6_update_ring_freq(dev);
4399 }
c0951f0c 4400 dev_priv->rps.enabled = true;
4fc688ce 4401 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4402}
4403
8090c6b9
DV		 4404void intel_enable_gt_powersave(struct drm_device *dev)
4405{
1a01ab3b
JB		 4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407
8090c6b9
DV		 4408 if (IS_IRONLAKE_M(dev)) {
4409 ironlake_enable_drps(dev);
4410 ironlake_enable_rc6(dev);
4411 intel_init_emon(dev);
0a073b84 4412 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4413 /*
4414 * PCU communication is slow and this doesn't need to be
4415 * done at any specific time, so do this out of our fast path
4416 * to make resume and init faster.
4417 */
4418 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4419 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4420 }
4421}
4422
3107bd48
DV		 4423static void ibx_init_clock_gating(struct drm_device *dev)
4424{
4425 struct drm_i915_private *dev_priv = dev->dev_private;
4426
4427 /*
4428 * On Ibex Peak and Cougar Point, we need to disable clock
4429 * gating for the panel power sequencer or it will fail to
4430 * start up when no ports are active.
4431 */
4432 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4433}
4434
0e088b8f
VS		 4435static void g4x_disable_trickle_feed(struct drm_device *dev)
4436{
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4438 int pipe;
4439
4440 for_each_pipe(pipe) {
4441 I915_WRITE(DSPCNTR(pipe),
4442 I915_READ(DSPCNTR(pipe)) |
4443 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4444 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4445 }
4446}
4447
017636cc
VS		 4448static void ilk_init_lp_watermarks(struct drm_device *dev)
4449{
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451
4452 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4453 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4454 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4455
4456 /*
4457 * Don't touch WM1S_LP_EN here.
4458 * Doing so could cause underruns.
4459 */
4460}
4461
1fa61106 4462static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4463{
4464 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4465 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4466
f1e8fa56
DL		 4467 /*
4468 * Required for FBC
4469 * WaFbcDisableDpfcClockGating:ilk
4470 */
4d47e4f5
DL		 4471 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4472 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4473 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4474
4475 I915_WRITE(PCH_3DCGDIS0,
4476 MARIUNIT_CLOCK_GATE_DISABLE |
4477 SVSMUNIT_CLOCK_GATE_DISABLE);
4478 I915_WRITE(PCH_3DCGDIS1,
4479 VFMUNIT_CLOCK_GATE_DISABLE);
4480
6f1d69b0
ED		 4481 /*
4482 * According to the spec the following bits should be set in
4483 * order to enable memory self-refresh
4484 * The bit 22/21 of 0x42004
4485 * The bit 5 of 0x42020
4486 * The bit 15 of 0x45000
4487 */
4488 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4489 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4490 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4491 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4492 I915_WRITE(DISP_ARB_CTL,
4493 (I915_READ(DISP_ARB_CTL) |
4494 DISP_FBC_WM_DIS));
017636cc
VS		 4495
4496 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 4497
4498 /*
4499 * Based on the document from hardware guys the following bits
4500 * should be set unconditionally in order to enable FBC.
4501 * The bit 22 of 0x42000
4502 * The bit 22 of 0x42004
4503 * The bit 7,8,9 of 0x42020.
4504 */
4505 if (IS_IRONLAKE_M(dev)) {
4bb35334 4506 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4507 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4508 I915_READ(ILK_DISPLAY_CHICKEN1) |
4509 ILK_FBCQ_DIS);
4510 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4511 I915_READ(ILK_DISPLAY_CHICKEN2) |
4512 ILK_DPARB_GATE);
6f1d69b0
ED		 4513 }
4514
4d47e4f5
DL		 4515 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4516
6f1d69b0
ED		 4517 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4518 I915_READ(ILK_DISPLAY_CHICKEN2) |
4519 ILK_ELPIN_409_SELECT);
4520 I915_WRITE(_3D_CHICKEN2,
4521 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4522 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4523
ecdb4eb7 4524 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4525 I915_WRITE(CACHE_MODE_0,
4526 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4527
0e088b8f 4528 g4x_disable_trickle_feed(dev);
bdad2b2f 4529
3107bd48
DV		 4530 ibx_init_clock_gating(dev);
4531}
4532
4533static void cpt_init_clock_gating(struct drm_device *dev)
4534{
4535 struct drm_i915_private *dev_priv = dev->dev_private;
4536 int pipe;
3f704fa2 4537 uint32_t val;
3107bd48
DV		 4538
4539 /*
4540 * On Ibex Peak and Cougar Point, we need to disable clock
4541 * gating for the panel power sequencer or it will fail to
4542 * start up when no ports are active.
4543 */
cd664078
JB		 4544 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4545 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4546 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 4547 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4548 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4549 /* The below fixes the weird display corruption, a few pixels shifted
4550 * downward, on (only) LVDS of some HP laptops with IVY.
4551 */
3f704fa2 4552 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4553 val = I915_READ(TRANS_CHICKEN2(pipe));
4554 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4555 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4556 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4557 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4558 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4559 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4560 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4561 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4562 }
3107bd48
DV		 4563 /* WADP0ClockGatingDisable */
4564 for_each_pipe(pipe) {
4565 I915_WRITE(TRANS_CHICKEN1(pipe),
4566 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4567 }
6f1d69b0
ED		 4568}
4569
1d7aaa0c
DV		 4570static void gen6_check_mch_setup(struct drm_device *dev)
4571{
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 uint32_t tmp;
4574
4575 tmp = I915_READ(MCH_SSKPD);
4576 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4577 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4578 DRM_INFO("This can cause pipe underruns and display issues.\n");
4579 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4580 }
4581}
4582
1fa61106 4583static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4584{
4585 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4586 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4587
231e54f6 4588 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4589
4590 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4591 I915_READ(ILK_DISPLAY_CHICKEN2) |
4592 ILK_ELPIN_409_SELECT);
4593
ecdb4eb7 4594 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4595 I915_WRITE(_3D_CHICKEN,
4596 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4597
ecdb4eb7 4598 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4599 if (IS_SNB_GT1(dev))
4600 I915_WRITE(GEN6_GT_MODE,
4601 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4602
017636cc 4603 ilk_init_lp_watermarks(dev);
6f1d69b0 4604
6f1d69b0 4605 I915_WRITE(CACHE_MODE_0,
50743298 4606 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4607
4608 I915_WRITE(GEN6_UCGCTL1,
4609 I915_READ(GEN6_UCGCTL1) |
4610 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4611 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4612
4613 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4614 * gating disable must be set. Failure to set it results in
4615 * flickering pixels due to Z write ordering failures after
4616 * some amount of runtime in the Mesa "fire" demo, and Unigine
4617 * Sanctuary and Tropics, and apparently anything else with
4618 * alpha test or pixel discard.
4619 *
4620 * According to the spec, bit 11 (RCCUNIT) must also be set,
4621 * but we didn't debug actual testcases to find it out.
0f846f81 4622 *
ecdb4eb7
DL		 4623 * Also apply WaDisableVDSUnitClockGating:snb and
4624 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4625 */
4626 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4627 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4628 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4629 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4630
4631 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4632 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4633 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4634
4635 /*
4636 * According to the spec the following bits should be
4637 * set in order to enable memory self-refresh and fbc:
4638 * The bit21 and bit22 of 0x42000
4639 * The bit21 and bit22 of 0x42004
4640 * The bit5 and bit7 of 0x42020
4641 * The bit14 of 0x70180
4642 * The bit14 of 0x71180
4bb35334
DL		 4643 *
4644 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4645 */
4646 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4647 I915_READ(ILK_DISPLAY_CHICKEN1) |
4648 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4649 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4650 I915_READ(ILK_DISPLAY_CHICKEN2) |
4651 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4652 I915_WRITE(ILK_DSPCLK_GATE_D,
4653 I915_READ(ILK_DSPCLK_GATE_D) |
4654 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4655 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4656
0e088b8f 4657 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4658
4659 /* The default value should be 0x200 according to docs, but the two
4660 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4661 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4662 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4663
4664 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4665
4666 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4667}
4668
4669static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4670{
4671 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4672
4673 reg &= ~GEN7_FF_SCHED_MASK;
4674 reg |= GEN7_FF_TS_SCHED_HW;
4675 reg |= GEN7_FF_VS_SCHED_HW;
4676 reg |= GEN7_FF_DS_SCHED_HW;
4677
41c0b3a8
BW		 4678 if (IS_HASWELL(dev_priv->dev))
4679 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4680
6f1d69b0
ED		 4681 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4682}
4683
17a303ec
PZ		 4684static void lpt_init_clock_gating(struct drm_device *dev)
4685{
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687
4688 /*
4689 * TODO: this bit should only be enabled when really needed, then
4690 * disabled when not needed anymore in order to save power.
4691 */
4692 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4693 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4694 I915_READ(SOUTH_DSPCLK_GATE_D) |
4695 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4696
4697 /* WADPOClockGatingDisable:hsw */
4698 I915_WRITE(_TRANSA_CHICKEN1,
4699 I915_READ(_TRANSA_CHICKEN1) |
4700 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4701}
4702
7d708ee4
ID		 4703static void lpt_suspend_hw(struct drm_device *dev)
4704{
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706
4707 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4708 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4709
4710 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4711 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4712 }
4713}
4714
1020a5c2
BW		 4715static void gen8_init_clock_gating(struct drm_device *dev)
4716{
4717 struct drm_i915_private *dev_priv = dev->dev_private;
fe4ab3ce 4718 enum pipe i;
1020a5c2
BW		 4719
4720 I915_WRITE(WM3_LP_ILK, 0);
4721 I915_WRITE(WM2_LP_ILK, 0);
4722 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 4723
4724 /* FIXME(BDW): Check all the w/a, some might only apply to
4725 * pre-production hw. */
4726
fd392b60
BW		 4727 WARN(!i915_preliminary_hw_support,
4728 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
4729 I915_WRITE(HALF_SLICE_CHICKEN3,
4730 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 4731 I915_WRITE(HALF_SLICE_CHICKEN3,
4732 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 4733 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
4734
7f88da0c
BW		 4735 I915_WRITE(_3D_CHICKEN3,
4736 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
4737
a75f3628
BW		 4738 I915_WRITE(COMMON_SLICE_CHICKEN2,
4739 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
4740
4c2e7a5f
BW		 4741 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4742 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
4743
ab57fff1 4744 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 4745 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 4746
ab57fff1 4747 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4748 I915_WRITE(CHICKEN_PAR1_1,
4749 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4750
ab57fff1 4751 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
fe4ab3ce
BW		 4752 for_each_pipe(i) {
4753 I915_WRITE(CHICKEN_PIPESL_1(i),
4754 I915_READ(CHICKEN_PIPESL_1(i) |
4755 DPRS_MASK_VBLANK_SRD));
4756 }
63801f21
BW		 4757
4758 /* Use Force Non-Coherent whenever executing a 3D context. This is a
4759 * workaround for for a possible hang in the unlikely event a TLB
4760 * invalidation occurs during a PSD flush.
4761 */
4762 I915_WRITE(HDC_CHICKEN0,
4763 I915_READ(HDC_CHICKEN0) |
4764 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 4765
4766 /* WaVSRefCountFullforceMissDisable:bdw */
4767 /* WaDSRefCountFullforceMissDisable:bdw */
4768 I915_WRITE(GEN7_FF_THREAD_MODE,
4769 I915_READ(GEN7_FF_THREAD_MODE) &
4770 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
1020a5c2
BW		 4771}
4772
cad2a2d7
ED		 4773static void haswell_init_clock_gating(struct drm_device *dev)
4774{
4775 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 4776
017636cc 4777 ilk_init_lp_watermarks(dev);
cad2a2d7
ED		 4778
4779 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4780 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4781 */
4782 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4783
ecdb4eb7 4784 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4785 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4786 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4787
ecdb4eb7 4788 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4789 I915_WRITE(GEN7_L3CNTLREG1,
4790 GEN7_WA_FOR_GEN7_L3_CONTROL);
4791 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4792 GEN7_WA_L3_CHICKEN_MODE);
4793
f3fc4884
FJ		 4794 /* L3 caching of data atomics doesn't work -- disable it. */
4795 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4796 I915_WRITE(HSW_ROW_CHICKEN3,
4797 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
4798
ecdb4eb7 4799 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4800 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4801 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4802 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4803
ecdb4eb7 4804 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4805 gen7_setup_fixed_func_scheduler(dev_priv);
4806
ecdb4eb7 4807 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4808 I915_WRITE(CACHE_MODE_1,
4809 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4810
ecdb4eb7 4811 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4812 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4813
90a88643
PZ		 4814 /* WaRsPkgCStateDisplayPMReq:hsw */
4815 I915_WRITE(CHICKEN_PAR1_1,
4816 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4817
17a303ec 4818 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4819}
4820
1fa61106 4821static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4822{
4823 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4824 uint32_t snpcr;
6f1d69b0 4825
017636cc 4826 ilk_init_lp_watermarks(dev);
6f1d69b0 4827
231e54f6 4828 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4829
ecdb4eb7 4830 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4831 I915_WRITE(_3D_CHICKEN3,
4832 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4833
ecdb4eb7 4834 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4835 I915_WRITE(IVB_CHICKEN3,
4836 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4837 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4838
ecdb4eb7 4839 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4840 if (IS_IVB_GT1(dev))
4841 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4842 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4843 else
4844 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4845 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4846
ecdb4eb7 4847 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4848 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4849 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4850
ecdb4eb7 4851 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4852 I915_WRITE(GEN7_L3CNTLREG1,
4853 GEN7_WA_FOR_GEN7_L3_CONTROL);
4854 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4855 GEN7_WA_L3_CHICKEN_MODE);
4856 if (IS_IVB_GT1(dev))
4857 I915_WRITE(GEN7_ROW_CHICKEN2,
4858 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4859 else
4860 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4861 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4862
6f1d69b0 4863
ecdb4eb7 4864 /* WaForceL3Serialization:ivb */
61939d97
JB		 4865 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4866 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4867
0f846f81
JB		 4868 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4869 * gating disable must be set. Failure to set it results in
4870 * flickering pixels due to Z write ordering failures after
4871 * some amount of runtime in the Mesa "fire" demo, and Unigine
4872 * Sanctuary and Tropics, and apparently anything else with
4873 * alpha test or pixel discard.
4874 *
4875 * According to the spec, bit 11 (RCCUNIT) must also be set,
4876 * but we didn't debug actual testcases to find it out.
4877 *
4878 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4879 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4880 */
4881 I915_WRITE(GEN6_UCGCTL2,
4882 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4883 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4884
ecdb4eb7 4885 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4886 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4887 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4888 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4889
0e088b8f 4890 g4x_disable_trickle_feed(dev);
6f1d69b0 4891
ecdb4eb7 4892 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4893 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4894
ecdb4eb7 4895 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4896 I915_WRITE(CACHE_MODE_1,
4897 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4898
4899 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4900 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4901 snpcr |= GEN6_MBC_SNPCR_MED;
4902 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4903
ab5c608b
BW		 4904 if (!HAS_PCH_NOP(dev))
4905 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4906
4907 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4908}
4909
1fa61106 4910static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4911{
4912 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 4913 u32 val;
4914
4915 mutex_lock(&dev_priv->rps.hw_lock);
4916 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4917 mutex_unlock(&dev_priv->rps.hw_lock);
4918 switch ((val >> 6) & 3) {
4919 case 0:
85b1d7b3
JB		 4920 dev_priv->mem_freq = 800;
4921 break;
f64a28a7 4922 case 1:
85b1d7b3
JB		 4923 dev_priv->mem_freq = 1066;
4924 break;
f64a28a7 4925 case 2:
85b1d7b3
JB		 4926 dev_priv->mem_freq = 1333;
4927 break;
f64a28a7 4928 case 3:
2325991e 4929 dev_priv->mem_freq = 1333;
f64a28a7 4930 break;
85b1d7b3
JB		 4931 }
4932 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 4933
d7fe0cc0 4934 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4935
ecdb4eb7 4936 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4937 I915_WRITE(_3D_CHICKEN3,
4938 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4939
ecdb4eb7 4940 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4941 I915_WRITE(IVB_CHICKEN3,
4942 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4943 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4944
ecdb4eb7 4945 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4946 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4947 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4948 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4949
ecdb4eb7 4950 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4951 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4952 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4953
ecdb4eb7 4954 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4955 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4956 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4957
ecdb4eb7 4958 /* WaForceL3Serialization:vlv */
61939d97
JB		 4959 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4960 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4961
ecdb4eb7 4962 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4963 I915_WRITE(GEN7_ROW_CHICKEN2,
4964 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4965
ecdb4eb7 4966 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4967 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4968 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4969 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4970
0f846f81
JB		 4971 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4972 * gating disable must be set. Failure to set it results in
4973 * flickering pixels due to Z write ordering failures after
4974 * some amount of runtime in the Mesa "fire" demo, and Unigine
4975 * Sanctuary and Tropics, and apparently anything else with
4976 * alpha test or pixel discard.
4977 *
4978 * According to the spec, bit 11 (RCCUNIT) must also be set,
4979 * but we didn't debug actual testcases to find it out.
4980 *
4981 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4982 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4983 *
ecdb4eb7
DL		 4984 * Also apply WaDisableVDSUnitClockGating:vlv and
4985 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4986 */
4987 I915_WRITE(GEN6_UCGCTL2,
4988 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4989 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4990 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4991 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4992 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4993
e3f33d46
JB		 4994 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4995
e0d8d59b 4996 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 4997
6b26c86d
DV		 4998 I915_WRITE(CACHE_MODE_1,
4999 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5000
2d809570 5001 /*
ecdb4eb7 5002 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5003 * Disable clock gating on th GCFG unit to prevent a delay
5004 * in the reporting of vblank events.
5005 */
4e8c84a5
JB		 5006 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5007
5008 /* Conservative clock gating settings for now */
5009 I915_WRITE(0x9400, 0xffffffff);
5010 I915_WRITE(0x9404, 0xffffffff);
5011 I915_WRITE(0x9408, 0xffffffff);
5012 I915_WRITE(0x940c, 0xffffffff);
5013 I915_WRITE(0x9410, 0xffffffff);
5014 I915_WRITE(0x9414, 0xffffffff);
5015 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5016}
5017
1fa61106 5018static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5019{
5020 struct drm_i915_private *dev_priv = dev->dev_private;
5021 uint32_t dspclk_gate;
5022
5023 I915_WRITE(RENCLK_GATE_D1, 0);
5024 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5025 GS_UNIT_CLOCK_GATE_DISABLE |
5026 CL_UNIT_CLOCK_GATE_DISABLE);
5027 I915_WRITE(RAMCLK_GATE_D, 0);
5028 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5029 OVRUNIT_CLOCK_GATE_DISABLE |
5030 OVCUNIT_CLOCK_GATE_DISABLE;
5031 if (IS_GM45(dev))
5032 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5033 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5034
5035 /* WaDisableRenderCachePipelinedFlush */
5036 I915_WRITE(CACHE_MODE_0,
5037 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5038
0e088b8f 5039 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5040}
5041
1fa61106 5042static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5043{
5044 struct drm_i915_private *dev_priv = dev->dev_private;
5045
5046 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5047 I915_WRITE(RENCLK_GATE_D2, 0);
5048 I915_WRITE(DSPCLK_GATE_D, 0);
5049 I915_WRITE(RAMCLK_GATE_D, 0);
5050 I915_WRITE16(DEUC, 0);
20f94967
VS		 5051 I915_WRITE(MI_ARB_STATE,
5052 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5053}
5054
1fa61106 5055static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5056{
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058
5059 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5060 I965_RCC_CLOCK_GATE_DISABLE |
5061 I965_RCPB_CLOCK_GATE_DISABLE |
5062 I965_ISC_CLOCK_GATE_DISABLE |
5063 I965_FBC_CLOCK_GATE_DISABLE);
5064 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5065 I915_WRITE(MI_ARB_STATE,
5066 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5067}
5068
1fa61106 5069static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5070{
5071 struct drm_i915_private *dev_priv = dev->dev_private;
5072 u32 dstate = I915_READ(D_STATE);
5073
5074 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5075 DSTATE_DOT_CLOCK_GATING;
5076 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5077
5078 if (IS_PINEVIEW(dev))
5079 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5080
5081 /* IIR "flip pending" means done if this bit is set */
5082 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5083}
5084
1fa61106 5085static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5086{
5087 struct drm_i915_private *dev_priv = dev->dev_private;
5088
5089 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5090}
5091
1fa61106 5092static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5093{
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095
5096 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5097}
5098
6f1d69b0
ED		 5099void intel_init_clock_gating(struct drm_device *dev)
5100{
5101 struct drm_i915_private *dev_priv = dev->dev_private;
5102
5103 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5104}
5105
7d708ee4
ID		 5106void intel_suspend_hw(struct drm_device *dev)
5107{
5108 if (HAS_PCH_LPT(dev))
5109 lpt_suspend_hw(dev);
5110}
5111
c1ca727f
ID		 5112#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5113 for (i = 0; \
5114 i < (power_domains)->power_well_count && \
5115 ((power_well) = &(power_domains)->power_wells[i]); \
5116 i++) \
5117 if ((power_well)->domains & (domain_mask))
5118
5119#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5120 for (i = (power_domains)->power_well_count - 1; \
5121 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5122 i--) \
5123 if ((power_well)->domains & (domain_mask))
5124
15d199ea
PZ		 5125/**
5126 * We should only use the power well if we explicitly asked the hardware to
5127 * enable it, so check if it's enabled and also check if we've requested it to
5128 * be enabled.
5129 */
c1ca727f
ID		 5130static bool hsw_power_well_enabled(struct drm_device *dev,
5131 struct i915_power_well *power_well)
5132{
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134
5135 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5136 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5137}
5138
ddf9c536
ID		 5139bool intel_display_power_enabled_sw(struct drm_device *dev,
5140 enum intel_display_power_domain domain)
5141{
5142 struct drm_i915_private *dev_priv = dev->dev_private;
5143 struct i915_power_domains *power_domains;
5144
5145 power_domains = &dev_priv->power_domains;
5146
5147 return power_domains->domain_use_count[domain];
5148}
5149
b97186f0
PZ		 5150bool intel_display_power_enabled(struct drm_device *dev,
5151 enum intel_display_power_domain domain)
15d199ea
PZ		 5152{
5153 struct drm_i915_private *dev_priv = dev->dev_private;
c1ca727f
ID		 5154 struct i915_power_domains *power_domains;
5155 struct i915_power_well *power_well;
5156 bool is_enabled;
5157 int i;
15d199ea 5158
c1ca727f
ID		 5159 power_domains = &dev_priv->power_domains;
5160
5161 is_enabled = true;
5162
5163 mutex_lock(&power_domains->lock);
5164 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5165 if (power_well->always_on)
5166 continue;
5167
c1ca727f
ID		 5168 if (!power_well->is_enabled(dev, power_well)) {
5169 is_enabled = false;
5170 break;
5171 }
5172 }
5173 mutex_unlock(&power_domains->lock);
5174
5175 return is_enabled;
15d199ea
PZ		 5176}
5177
d5e8fdc8
PZ		 5178static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5179{
5180 struct drm_device *dev = dev_priv->dev;
5181 unsigned long irqflags;
5182
f9dcb0df
PZ		 5183 /*
5184 * After we re-enable the power well, if we touch VGA register 0x3d5
5185 * we'll get unclaimed register interrupts. This stops after we write
5186 * anything to the VGA MSR register. The vgacon module uses this
5187 * register all the time, so if we unbind our driver and, as a
5188 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5189 * console_unlock(). So make here we touch the VGA MSR register, making
5190 * sure vgacon can keep working normally without triggering interrupts
5191 * and error messages.
5192 */
5193 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5194 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5195 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5196
d5e8fdc8
PZ		 5197 if (IS_BROADWELL(dev)) {
5198 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5199 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5200 dev_priv->de_irq_mask[PIPE_B]);
5201 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5202 ~dev_priv->de_irq_mask[PIPE_B] |
5203 GEN8_PIPE_VBLANK);
5204 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5205 dev_priv->de_irq_mask[PIPE_C]);
5206 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5207 ~dev_priv->de_irq_mask[PIPE_C] |
5208 GEN8_PIPE_VBLANK);
5209 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5210 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5211 }
5212}
5213
5214static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5215{
5216 struct drm_device *dev = dev_priv->dev;
5217 enum pipe p;
5218 unsigned long irqflags;
5219
5220 /*
5221 * After this, the registers on the pipes that are part of the power
5222 * well will become zero, so we have to adjust our counters according to
5223 * that.
5224 *
5225 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5226 */
5227 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5228 for_each_pipe(p)
5229 if (p != PIPE_A)
5230 dev->vblank[p].last = 0;
5231 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5232}
5233
c1ca727f
ID		 5234static void hsw_set_power_well(struct drm_device *dev,
5235 struct i915_power_well *power_well, bool enable)
d0d3e513
ED		 5236{
5237 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5238 bool is_enabled, enable_requested;
5239 uint32_t tmp;
d0d3e513 5240
d62292c8
PZ		 5241 WARN_ON(dev_priv->pc8.enabled);
5242
fa42e23c 5243 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5244 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5245 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5246
fa42e23c
PZ		 5247 if (enable) {
5248 if (!enable_requested)
6aedd1f5
PZ		 5249 I915_WRITE(HSW_PWR_WELL_DRIVER,
5250 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5251
fa42e23c
PZ		 5252 if (!is_enabled) {
5253 DRM_DEBUG_KMS("Enabling power well\n");
5254 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5255 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5256 DRM_ERROR("Timeout enabling power well\n");
5257 }
596cc11e 5258
d5e8fdc8 5259 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5260 } else {
5261 if (enable_requested) {
5262 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5263 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5264 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5265
d5e8fdc8 5266 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5267 }
5268 }
fa42e23c 5269}
d0d3e513 5270
b4ed4484
ID		 5271static void __intel_power_well_get(struct drm_device *dev,
5272 struct i915_power_well *power_well)
2d66aef5 5273{
d62292c8
PZ		 5274 struct drm_i915_private *dev_priv = dev->dev_private;
5275
5276 if (!power_well->count++ && power_well->set) {
5277 hsw_disable_package_c8(dev_priv);
c1ca727f 5278 power_well->set(dev, power_well, true);
d62292c8 5279 }
2d66aef5
VS		 5280}
5281
b4ed4484
ID		 5282static void __intel_power_well_put(struct drm_device *dev,
5283 struct i915_power_well *power_well)
2d66aef5 5284{
d62292c8
PZ		 5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286
2d66aef5 5287 WARN_ON(!power_well->count);
c1ca727f 5288
d62292c8
PZ		 5289 if (!--power_well->count && power_well->set &&
5290 i915_disable_power_well) {
c1ca727f 5291 power_well->set(dev, power_well, false);
d62292c8
PZ		 5292 hsw_enable_package_c8(dev_priv);
5293 }
2d66aef5
VS		 5294}
5295
6765625e
VS		 5296void intel_display_power_get(struct drm_device *dev,
5297 enum intel_display_power_domain domain)
5298{
5299 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5300 struct i915_power_domains *power_domains;
c1ca727f
ID		 5301 struct i915_power_well *power_well;
5302 int i;
6765625e 5303
83c00f55
ID		 5304 power_domains = &dev_priv->power_domains;
5305
5306 mutex_lock(&power_domains->lock);
1da51581 5307
c1ca727f
ID		 5308 for_each_power_well(i, power_well, BIT(domain), power_domains)
5309 __intel_power_well_get(dev, power_well);
1da51581 5310
ddf9c536
ID		 5311 power_domains->domain_use_count[domain]++;
5312
83c00f55 5313 mutex_unlock(&power_domains->lock);
6765625e
VS		 5314}
5315
5316void intel_display_power_put(struct drm_device *dev,
5317 enum intel_display_power_domain domain)
5318{
5319 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5320 struct i915_power_domains *power_domains;
c1ca727f
ID		 5321 struct i915_power_well *power_well;
5322 int i;
6765625e 5323
83c00f55
ID		 5324 power_domains = &dev_priv->power_domains;
5325
5326 mutex_lock(&power_domains->lock);
1da51581 5327
1da51581
ID		 5328 WARN_ON(!power_domains->domain_use_count[domain]);
5329 power_domains->domain_use_count[domain]--;
ddf9c536
ID		 5330
5331 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5332 __intel_power_well_put(dev, power_well);
1da51581 5333
83c00f55 5334 mutex_unlock(&power_domains->lock);
6765625e
VS		 5335}
5336
83c00f55 5337static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5338
5339/* Display audio driver power well request */
5340void i915_request_power_well(void)
5341{
b4ed4484
ID		 5342 struct drm_i915_private *dev_priv;
5343
a38911a3
WX		 5344 if (WARN_ON(!hsw_pwr))
5345 return;
5346
b4ed4484
ID		 5347 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5348 power_domains);
fbeeaa23 5349 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5350}
5351EXPORT_SYMBOL_GPL(i915_request_power_well);
5352
5353/* Display audio driver power well release */
5354void i915_release_power_well(void)
5355{
b4ed4484
ID		 5356 struct drm_i915_private *dev_priv;
5357
a38911a3
WX		 5358 if (WARN_ON(!hsw_pwr))
5359 return;
5360
b4ed4484
ID		 5361 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5362 power_domains);
fbeeaa23 5363 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5364}
5365EXPORT_SYMBOL_GPL(i915_release_power_well);
5366
1c2256df
ID		 5367static struct i915_power_well i9xx_always_on_power_well[] = {
5368 {
5369 .name = "always-on",
5370 .always_on = 1,
5371 .domains = POWER_DOMAIN_MASK,
5372 },
5373};
5374
c1ca727f 5375static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5376 {
5377 .name = "always-on",
5378 .always_on = 1,
5379 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5380 },
c1ca727f
ID		 5381 {
5382 .name = "display",
5383 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5384 .is_enabled = hsw_power_well_enabled,
5385 .set = hsw_set_power_well,
5386 },
5387};
5388
5389static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5390 {
5391 .name = "always-on",
5392 .always_on = 1,
5393 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5394 },
c1ca727f
ID		 5395 {
5396 .name = "display",
5397 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5398 .is_enabled = hsw_power_well_enabled,
5399 .set = hsw_set_power_well,
5400 },
5401};
5402
5403#define set_power_wells(power_domains, __power_wells) ({ \
5404 (power_domains)->power_wells = (__power_wells); \
5405 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5406})
5407
ddb642fb 5408int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 5409{
5410 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5411 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 5412
83c00f55 5413 mutex_init(&power_domains->lock);
a38911a3 5414
c1ca727f
ID		 5415 /*
5416 * The enabling order will be from lower to higher indexed wells,
5417 * the disabling order is reversed.
5418 */
5419 if (IS_HASWELL(dev)) {
5420 set_power_wells(power_domains, hsw_power_wells);
5421 hsw_pwr = power_domains;
5422 } else if (IS_BROADWELL(dev)) {
5423 set_power_wells(power_domains, bdw_power_wells);
5424 hsw_pwr = power_domains;
5425 } else {
1c2256df 5426 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 5427 }
a38911a3
WX		 5428
5429 return 0;
5430}
5431
ddb642fb 5432void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 5433{
5434 hsw_pwr = NULL;
5435}
5436
ddb642fb 5437static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 5438{
5439 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5440 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5441 struct i915_power_well *power_well;
c1ca727f 5442 int i;
9cdb826c 5443
83c00f55 5444 mutex_lock(&power_domains->lock);
c1ca727f
ID		 5445 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5446 if (power_well->set)
5447 power_well->set(dev, power_well, power_well->count > 0);
5448 }
83c00f55 5449 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5450}
5451
fa42e23c
PZ		 5452/*
5453 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5454 * when not needed anymore. We have 4 registers that can request the power well
5455 * to be enabled, and it will only be disabled if none of the registers is
5456 * requesting it to be enabled.
d0d3e513 5457 */
ddb642fb 5458void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 5459{
5460 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5461
fa42e23c 5462 /* For now, we need the power well to be always enabled. */
baa70707 5463 intel_display_set_init_power(dev, true);
ddb642fb 5464 intel_power_domains_resume(dev);
d0d3e513 5465
f7243ac9
ID		 5466 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5467 return;
5468
fa42e23c
PZ		 5469 /* We're taking over the BIOS, so clear any requests made by it since
5470 * the driver is in charge now. */
6aedd1f5 5471 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5472 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5473}
5474
c67a470b
PZ		 5475/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5476void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5477{
5478 hsw_disable_package_c8(dev_priv);
5479}
5480
5481void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5482{
5483 hsw_enable_package_c8(dev_priv);
5484}
5485
8a187455
PZ		 5486void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
5487{
5488 struct drm_device *dev = dev_priv->dev;
5489 struct device *device = &dev->pdev->dev;
5490
5491 if (!HAS_RUNTIME_PM(dev))
5492 return;
5493
5494 pm_runtime_get_sync(device);
5495 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
5496}
5497
5498void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
5499{
5500 struct drm_device *dev = dev_priv->dev;
5501 struct device *device = &dev->pdev->dev;
5502
5503 if (!HAS_RUNTIME_PM(dev))
5504 return;
5505
5506 pm_runtime_mark_last_busy(device);
5507 pm_runtime_put_autosuspend(device);
5508}
5509
5510void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5511{
5512 struct drm_device *dev = dev_priv->dev;
5513 struct device *device = &dev->pdev->dev;
5514
5515 dev_priv->pm.suspended = false;
5516
5517 if (!HAS_RUNTIME_PM(dev))
5518 return;
5519
5520 pm_runtime_set_active(device);
5521
5522 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5523 pm_runtime_mark_last_busy(device);
5524 pm_runtime_use_autosuspend(device);
5525}
5526
5527void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
5528{
5529 struct drm_device *dev = dev_priv->dev;
5530 struct device *device = &dev->pdev->dev;
5531
5532 if (!HAS_RUNTIME_PM(dev))
5533 return;
5534
5535 /* Make sure we're not suspended first. */
5536 pm_runtime_get_sync(device);
5537 pm_runtime_disable(device);
5538}
5539
1fa61106
ED		 5540/* Set up chip specific power management-related functions */
5541void intel_init_pm(struct drm_device *dev)
5542{
5543 struct drm_i915_private *dev_priv = dev->dev_private;
5544
5545 if (I915_HAS_FBC(dev)) {
40045465 5546 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 5547 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 5548 dev_priv->display.enable_fbc = gen7_enable_fbc;
5549 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5550 } else if (INTEL_INFO(dev)->gen >= 5) {
5551 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5552 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 5553 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5554 } else if (IS_GM45(dev)) {
5555 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5556 dev_priv->display.enable_fbc = g4x_enable_fbc;
5557 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 5558 } else {
1fa61106
ED		 5559 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5560 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5561 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 5562
5563 /* This value was pulled out of someone's hat */
5564 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 5565 }
1fa61106
ED		 5566 }
5567
c921aba8
DV		 5568 /* For cxsr */
5569 if (IS_PINEVIEW(dev))
5570 i915_pineview_get_mem_freq(dev);
5571 else if (IS_GEN5(dev))
5572 i915_ironlake_get_mem_freq(dev);
5573
1fa61106
ED		 5574 /* For FIFO watermark updates */
5575 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5576 intel_setup_wm_latency(dev);
5577
1fa61106 5578 if (IS_GEN5(dev)) {
53615a5e
VS		 5579 if (dev_priv->wm.pri_latency[1] &&
5580 dev_priv->wm.spr_latency[1] &&
96f90c54
VS		 5581 dev_priv->wm.cur_latency[1]) {
5582 dev_priv->display.update_wm = haswell_update_wm;
5583 dev_priv->display.update_sprite_wm =
5584 haswell_update_sprite_wm;
5585 } else {
1fa61106
ED		 5586 DRM_DEBUG_KMS("Failed to get proper latency. "
5587 "Disable CxSR\n");
5588 dev_priv->display.update_wm = NULL;
5589 }
5590 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5591 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5592 if (dev_priv->wm.pri_latency[0] &&
5593 dev_priv->wm.spr_latency[0] &&
5594 dev_priv->wm.cur_latency[0]) {
96f90c54
VS		 5595 dev_priv->display.update_wm = haswell_update_wm;
5596 dev_priv->display.update_sprite_wm =
5597 haswell_update_sprite_wm;
1fa61106
ED		 5598 } else {
5599 DRM_DEBUG_KMS("Failed to read display plane latency. "
5600 "Disable CxSR\n");
5601 dev_priv->display.update_wm = NULL;
5602 }
5603 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5604 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5605 if (dev_priv->wm.pri_latency[0] &&
5606 dev_priv->wm.spr_latency[0] &&
5607 dev_priv->wm.cur_latency[0]) {
96f90c54
VS		 5608 dev_priv->display.update_wm = haswell_update_wm;
5609 dev_priv->display.update_sprite_wm =
5610 haswell_update_sprite_wm;
1fa61106
ED		 5611 } else {
5612 DRM_DEBUG_KMS("Failed to read display plane latency. "
5613 "Disable CxSR\n");
5614 dev_priv->display.update_wm = NULL;
5615 }
5616 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5617 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5618 if (dev_priv->wm.pri_latency[0] &&
5619 dev_priv->wm.spr_latency[0] &&
5620 dev_priv->wm.cur_latency[0]) {
1011d8c4 5621 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5622 dev_priv->display.update_sprite_wm =
5623 haswell_update_sprite_wm;
6b8a5eeb
ED		 5624 } else {
5625 DRM_DEBUG_KMS("Failed to read display plane latency. "
5626 "Disable CxSR\n");
5627 dev_priv->display.update_wm = NULL;
5628 }
cad2a2d7 5629 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1020a5c2
BW		 5630 } else if (INTEL_INFO(dev)->gen == 8) {
5631 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 5632 } else
5633 dev_priv->display.update_wm = NULL;
5634 } else if (IS_VALLEYVIEW(dev)) {
5635 dev_priv->display.update_wm = valleyview_update_wm;
5636 dev_priv->display.init_clock_gating =
5637 valleyview_init_clock_gating;
1fa61106
ED		 5638 } else if (IS_PINEVIEW(dev)) {
5639 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5640 dev_priv->is_ddr3,
5641 dev_priv->fsb_freq,
5642 dev_priv->mem_freq)) {
5643 DRM_INFO("failed to find known CxSR latency "
5644 "(found ddr%s fsb freq %d, mem freq %d), "
5645 "disabling CxSR\n",
5646 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5647 dev_priv->fsb_freq, dev_priv->mem_freq);
5648 /* Disable CxSR and never update its watermark again */
5649 pineview_disable_cxsr(dev);
5650 dev_priv->display.update_wm = NULL;
5651 } else
5652 dev_priv->display.update_wm = pineview_update_wm;
5653 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5654 } else if (IS_G4X(dev)) {
5655 dev_priv->display.update_wm = g4x_update_wm;
5656 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5657 } else if (IS_GEN4(dev)) {
5658 dev_priv->display.update_wm = i965_update_wm;
5659 if (IS_CRESTLINE(dev))
5660 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5661 else if (IS_BROADWATER(dev))
5662 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5663 } else if (IS_GEN3(dev)) {
5664 dev_priv->display.update_wm = i9xx_update_wm;
5665 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5666 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5667 } else if (IS_I865G(dev)) {
5668 dev_priv->display.update_wm = i830_update_wm;
5669 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5670 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5671 } else if (IS_I85X(dev)) {
5672 dev_priv->display.update_wm = i9xx_update_wm;
5673 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5674 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5675 } else {
5676 dev_priv->display.update_wm = i830_update_wm;
5677 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5678 if (IS_845G(dev))
5679 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5680 else
5681 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5682 }
5683}
5684
42c0526c
BW		 5685int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5686{
4fc688ce 5687 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5688
5689 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5690 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5691 return -EAGAIN;
5692 }
5693
5694 I915_WRITE(GEN6_PCODE_DATA, *val);
5695 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5696
5697 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5698 500)) {
5699 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5700 return -ETIMEDOUT;
5701 }
5702
5703 *val = I915_READ(GEN6_PCODE_DATA);
5704 I915_WRITE(GEN6_PCODE_DATA, 0);
5705
5706 return 0;
5707}
5708
5709int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5710{
4fc688ce 5711 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5712
5713 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5714 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5715 return -EAGAIN;
5716 }
5717
5718 I915_WRITE(GEN6_PCODE_DATA, val);
5719 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5720
5721 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5722 500)) {
5723 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5724 return -ETIMEDOUT;
5725 }
5726
5727 I915_WRITE(GEN6_PCODE_DATA, 0);
5728
5729 return 0;
5730}
a0e4e199 5731
2ec3815f 5732int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 5733{
07ab118b 5734 int div;
855ba3be 5735
07ab118b 5736 /* 4 x czclk */
2ec3815f 5737 switch (dev_priv->mem_freq) {
855ba3be 5738 case 800:
07ab118b 5739 div = 10;
855ba3be
JB		 5740 break;
5741 case 1066:
07ab118b 5742 div = 12;
855ba3be
JB		 5743 break;
5744 case 1333:
07ab118b 5745 div = 16;
855ba3be
JB		 5746 break;
5747 default:
5748 return -1;
5749 }
5750
2ec3815f 5751 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 5752}
5753
2ec3815f 5754int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 5755{
07ab118b 5756 int mul;
855ba3be 5757
07ab118b 5758 /* 4 x czclk */
2ec3815f 5759 switch (dev_priv->mem_freq) {
855ba3be 5760 case 800:
07ab118b 5761 mul = 10;
855ba3be
JB		 5762 break;
5763 case 1066:
07ab118b 5764 mul = 12;
855ba3be
JB		 5765 break;
5766 case 1333:
07ab118b 5767 mul = 16;
855ba3be
JB		 5768 break;
5769 default:
5770 return -1;
5771 }
5772
2ec3815f 5773 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 5774}
5775
907b28c5
CW		 5776void intel_pm_init(struct drm_device *dev)
5777{
5778 struct drm_i915_private *dev_priv = dev->dev_private;
5779
5780 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5781 intel_gen6_powersave_work);
5782}
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