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drm/i915: Renaming CCK related reg definitions
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
6381b550
NH		 62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
77719d28 66}
91e41d16 67
45db2194 68static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 69{
acd5c346 70 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 71
77719d28
DL		 72 gen9_init_clock_gating(dev);
73
2caa3b26 74 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 75 /* WaDisableHDCInvalidation:skl */
76 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
77 BDW_DISABLE_HDC_INVALIDATION);
78
2caa3b26
DL		 79 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
80 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 81 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 82 }
81e231af 83
a4106a78
AS		 84 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
85 * involving this register should also be added to WA batch as required.
86 */
8bc0ccf6
DL		 87 if (INTEL_REVID(dev) <= SKL_REVID_E0)
88 /* WaDisableLSQCROPERFforOCL:skl */
89 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
90 GEN8_LQSC_RO_PERF_DIS);
245d9667
AS		 91
92 /* WaEnableGapsTsvCreditFix:skl */
93 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
94 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
95 GEN9_GAPS_TSV_CREDIT_DISABLE));
96 }
da2078cd
DL		 97}
98
a82abe43
ID		 99static void bxt_init_clock_gating(struct drm_device *dev)
100{
32608ca2
ID		 101 struct drm_i915_private *dev_priv = dev->dev_private;
102
a82abe43 103 gen9_init_clock_gating(dev);
32608ca2 104
a7546159
NH		 105 /* WaDisableSDEUnitClockGating:bxt */
106 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
107 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
108
32608ca2
ID		 109 /*
110 * FIXME:
868434c5 111 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 112 */
32608ca2 113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 115
aa66c506
AS		 116 /* WaStoreMultiplePTEenable:bxt */
117 /* This is a requirement according to Hardware specification */
118 if (INTEL_REVID(dev) == BXT_REVID_A0)
a7546159 119 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
5b88abac
AS		 120
121 /* WaSetClckGatingDisableMedia:bxt */
122 if (INTEL_REVID(dev) == BXT_REVID_A0) {
123 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
124 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
125 }
a82abe43
ID		 126}
127
c921aba8
DV		 128static void i915_pineview_get_mem_freq(struct drm_device *dev)
129{
50227e1c 130 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 131 u32 tmp;
132
133 tmp = I915_READ(CLKCFG);
134
135 switch (tmp & CLKCFG_FSB_MASK) {
136 case CLKCFG_FSB_533:
137 dev_priv->fsb_freq = 533; /* 133*4 */
138 break;
139 case CLKCFG_FSB_800:
140 dev_priv->fsb_freq = 800; /* 200*4 */
141 break;
142 case CLKCFG_FSB_667:
143 dev_priv->fsb_freq = 667; /* 167*4 */
144 break;
145 case CLKCFG_FSB_400:
146 dev_priv->fsb_freq = 400; /* 100*4 */
147 break;
148 }
149
150 switch (tmp & CLKCFG_MEM_MASK) {
151 case CLKCFG_MEM_533:
152 dev_priv->mem_freq = 533;
153 break;
154 case CLKCFG_MEM_667:
155 dev_priv->mem_freq = 667;
156 break;
157 case CLKCFG_MEM_800:
158 dev_priv->mem_freq = 800;
159 break;
160 }
161
162 /* detect pineview DDR3 setting */
163 tmp = I915_READ(CSHRDDR3CTL);
164 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
165}
166
167static void i915_ironlake_get_mem_freq(struct drm_device *dev)
168{
50227e1c 169 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 170 u16 ddrpll, csipll;
171
172 ddrpll = I915_READ16(DDRMPLL1);
173 csipll = I915_READ16(CSIPLL0);
174
175 switch (ddrpll & 0xff) {
176 case 0xc:
177 dev_priv->mem_freq = 800;
178 break;
179 case 0x10:
180 dev_priv->mem_freq = 1066;
181 break;
182 case 0x14:
183 dev_priv->mem_freq = 1333;
184 break;
185 case 0x18:
186 dev_priv->mem_freq = 1600;
187 break;
188 default:
189 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 ddrpll & 0xff);
191 dev_priv->mem_freq = 0;
192 break;
193 }
194
20e4d407 195 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 196
197 switch (csipll & 0x3ff) {
198 case 0x00c:
199 dev_priv->fsb_freq = 3200;
200 break;
201 case 0x00e:
202 dev_priv->fsb_freq = 3733;
203 break;
204 case 0x010:
205 dev_priv->fsb_freq = 4266;
206 break;
207 case 0x012:
208 dev_priv->fsb_freq = 4800;
209 break;
210 case 0x014:
211 dev_priv->fsb_freq = 5333;
212 break;
213 case 0x016:
214 dev_priv->fsb_freq = 5866;
215 break;
216 case 0x018:
217 dev_priv->fsb_freq = 6400;
218 break;
219 default:
220 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 csipll & 0x3ff);
222 dev_priv->fsb_freq = 0;
223 break;
224 }
225
226 if (dev_priv->fsb_freq == 3200) {
20e4d407 227 dev_priv->ips.c_m = 0;
c921aba8 228 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 229 dev_priv->ips.c_m = 1;
c921aba8 230 } else {
20e4d407 231 dev_priv->ips.c_m = 2;
c921aba8
DV		 232 }
233}
234
b445e3b0
ED		 235static const struct cxsr_latency cxsr_latency_table[] = {
236 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
237 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
238 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
239 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
240 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241
242 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
243 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
244 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
245 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
246 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247
248 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
249 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
250 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
251 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
252 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253
254 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
255 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
256 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
257 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
258 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259
260 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
261 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
262 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
263 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
264 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265
266 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
267 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
268 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
269 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
270 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
271};
272
63c62275 273static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 274 int is_ddr3,
275 int fsb,
276 int mem)
277{
278 const struct cxsr_latency *latency;
279 int i;
280
281 if (fsb == 0 || mem == 0)
282 return NULL;
283
284 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
285 latency = &cxsr_latency_table[i];
286 if (is_desktop == latency->is_desktop &&
287 is_ddr3 == latency->is_ddr3 &&
288 fsb == latency->fsb_freq && mem == latency->mem_freq)
289 return latency;
290 }
291
292 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
293
294 return NULL;
295}
296
fc1ac8de
VS		 297static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
298{
299 u32 val;
300
301 mutex_lock(&dev_priv->rps.hw_lock);
302
303 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
304 if (enable)
305 val &= ~FORCE_DDR_HIGH_FREQ;
306 else
307 val |= FORCE_DDR_HIGH_FREQ;
308 val &= ~FORCE_DDR_LOW_FREQ;
309 val |= FORCE_DDR_FREQ_REQ_ACK;
310 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
311
312 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
313 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
314 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315
316 mutex_unlock(&dev_priv->rps.hw_lock);
317}
318
cfb41411
VS		 319static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
320{
321 u32 val;
322
323 mutex_lock(&dev_priv->rps.hw_lock);
324
325 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
326 if (enable)
327 val |= DSP_MAXFIFO_PM5_ENABLE;
328 else
329 val &= ~DSP_MAXFIFO_PM5_ENABLE;
330 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
331
332 mutex_unlock(&dev_priv->rps.hw_lock);
333}
334
f4998963
VS		 335#define FW_WM(value, plane) \
336 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337
5209b1f4 338void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 339{
5209b1f4
ID		 340 struct drm_device *dev = dev_priv->dev;
341 u32 val;
b445e3b0 342
5209b1f4
ID		 343 if (IS_VALLEYVIEW(dev)) {
344 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 345 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 346 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 347 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
348 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 349 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 350 } else if (IS_PINEVIEW(dev)) {
351 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
352 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
353 I915_WRITE(DSPFW3, val);
a7a6c498 354 POSTING_READ(DSPFW3);
5209b1f4
ID		 355 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
356 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
357 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
358 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 359 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 360 } else if (IS_I915GM(dev)) {
361 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
362 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
363 I915_WRITE(INSTPM, val);
a7a6c498 364 POSTING_READ(INSTPM);
5209b1f4
ID		 365 } else {
366 return;
367 }
b445e3b0 368
5209b1f4
ID		 369 DRM_DEBUG_KMS("memory self-refresh is %s\n",
370 enable ? "enabled" : "disabled");
b445e3b0
ED		 371}
372
fc1ac8de 373
b445e3b0
ED		 374/*
375 * Latency for FIFO fetches is dependent on several factors:
376 * - memory configuration (speed, channels)
377 * - chipset
378 * - current MCH state
379 * It can be fairly high in some situations, so here we assume a fairly
380 * pessimal value. It's a tradeoff between extra memory fetches (if we
381 * set this value too high, the FIFO will fetch frequently to stay full)
382 * and power consumption (set it too low to save power and we might see
383 * FIFO underruns and display "flicker").
384 *
385 * A value of 5us seems to be a good balance; safe for very low end
386 * platforms but not overly aggressive on lower latency configs.
387 */
5aef6003 388static const int pessimal_latency_ns = 5000;
b445e3b0 389
b5004720
VS		 390#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
391 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
392
393static int vlv_get_fifo_size(struct drm_device *dev,
394 enum pipe pipe, int plane)
395{
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 int sprite0_start, sprite1_start, size;
398
399 switch (pipe) {
400 uint32_t dsparb, dsparb2, dsparb3;
401 case PIPE_A:
402 dsparb = I915_READ(DSPARB);
403 dsparb2 = I915_READ(DSPARB2);
404 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
405 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
406 break;
407 case PIPE_B:
408 dsparb = I915_READ(DSPARB);
409 dsparb2 = I915_READ(DSPARB2);
410 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
411 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
412 break;
413 case PIPE_C:
414 dsparb2 = I915_READ(DSPARB2);
415 dsparb3 = I915_READ(DSPARB3);
416 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
417 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
418 break;
419 default:
420 return 0;
421 }
422
423 switch (plane) {
424 case 0:
425 size = sprite0_start;
426 break;
427 case 1:
428 size = sprite1_start - sprite0_start;
429 break;
430 case 2:
431 size = 512 - 1 - sprite1_start;
432 break;
433 default:
434 return 0;
435 }
436
437 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
438 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
439 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
440 size);
441
442 return size;
443}
444
1fa61106 445static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 uint32_t dsparb = I915_READ(DSPARB);
449 int size;
450
451 size = dsparb & 0x7f;
452 if (plane)
453 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
454
455 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
456 plane ? "B" : "A", size);
457
458 return size;
459}
460
feb56b93 461static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 462{
463 struct drm_i915_private *dev_priv = dev->dev_private;
464 uint32_t dsparb = I915_READ(DSPARB);
465 int size;
466
467 size = dsparb & 0x1ff;
468 if (plane)
469 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
470 size >>= 1; /* Convert to cachelines */
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476}
477
1fa61106 478static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 479{
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 uint32_t dsparb = I915_READ(DSPARB);
482 int size;
483
484 size = dsparb & 0x7f;
485 size >>= 2; /* Convert to cachelines */
486
487 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
488 plane ? "B" : "A",
489 size);
490
491 return size;
492}
493
b445e3b0
ED		 494/* Pineview has different values for various configs */
495static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 496 .fifo_size = PINEVIEW_DISPLAY_FIFO,
497 .max_wm = PINEVIEW_MAX_WM,
498 .default_wm = PINEVIEW_DFT_WM,
499 .guard_size = PINEVIEW_GUARD_WM,
500 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 503 .fifo_size = PINEVIEW_DISPLAY_FIFO,
504 .max_wm = PINEVIEW_MAX_WM,
505 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
506 .guard_size = PINEVIEW_GUARD_WM,
507 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 510 .fifo_size = PINEVIEW_CURSOR_FIFO,
511 .max_wm = PINEVIEW_CURSOR_MAX_WM,
512 .default_wm = PINEVIEW_CURSOR_DFT_WM,
513 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
514 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 517 .fifo_size = PINEVIEW_CURSOR_FIFO,
518 .max_wm = PINEVIEW_CURSOR_MAX_WM,
519 .default_wm = PINEVIEW_CURSOR_DFT_WM,
520 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
521 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 522};
523static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 524 .fifo_size = G4X_FIFO_SIZE,
525 .max_wm = G4X_MAX_WM,
526 .default_wm = G4X_MAX_WM,
527 .guard_size = 2,
528 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 529};
530static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 531 .fifo_size = I965_CURSOR_FIFO,
532 .max_wm = I965_CURSOR_MAX_WM,
533 .default_wm = I965_CURSOR_DFT_WM,
534 .guard_size = 2,
535 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 536};
537static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 538 .fifo_size = VALLEYVIEW_FIFO_SIZE,
539 .max_wm = VALLEYVIEW_MAX_WM,
540 .default_wm = VALLEYVIEW_MAX_WM,
541 .guard_size = 2,
542 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 543};
544static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 545 .fifo_size = I965_CURSOR_FIFO,
546 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
547 .default_wm = I965_CURSOR_DFT_WM,
548 .guard_size = 2,
549 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 550};
551static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 552 .fifo_size = I965_CURSOR_FIFO,
553 .max_wm = I965_CURSOR_MAX_WM,
554 .default_wm = I965_CURSOR_DFT_WM,
555 .guard_size = 2,
556 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 557};
558static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 559 .fifo_size = I945_FIFO_SIZE,
560 .max_wm = I915_MAX_WM,
561 .default_wm = 1,
562 .guard_size = 2,
563 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 564};
565static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 566 .fifo_size = I915_FIFO_SIZE,
567 .max_wm = I915_MAX_WM,
568 .default_wm = 1,
569 .guard_size = 2,
570 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 571};
9d539105 572static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 573 .fifo_size = I855GM_FIFO_SIZE,
574 .max_wm = I915_MAX_WM,
575 .default_wm = 1,
576 .guard_size = 2,
577 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 578};
9d539105
VS		 579static const struct intel_watermark_params i830_bc_wm_info = {
580 .fifo_size = I855GM_FIFO_SIZE,
581 .max_wm = I915_MAX_WM/2,
582 .default_wm = 1,
583 .guard_size = 2,
584 .cacheline_size = I830_FIFO_LINE_SIZE,
585};
feb56b93 586static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 587 .fifo_size = I830_FIFO_SIZE,
588 .max_wm = I915_MAX_WM,
589 .default_wm = 1,
590 .guard_size = 2,
591 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 592};
593
b445e3b0
ED		 594/**
595 * intel_calculate_wm - calculate watermark level
596 * @clock_in_khz: pixel clock
597 * @wm: chip FIFO params
598 * @pixel_size: display pixel size
599 * @latency_ns: memory latency for the platform
600 *
601 * Calculate the watermark level (the level at which the display plane will
602 * start fetching from memory again). Each chip has a different display
603 * FIFO size and allocation, so the caller needs to figure that out and pass
604 * in the correct intel_watermark_params structure.
605 *
606 * As the pixel clock runs, the FIFO will be drained at a rate that depends
607 * on the pixel size. When it reaches the watermark level, it'll start
608 * fetching FIFO line sized based chunks from memory until the FIFO fills
609 * past the watermark point. If the FIFO drains completely, a FIFO underrun
610 * will occur, and a display engine hang could result.
611 */
612static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
613 const struct intel_watermark_params *wm,
614 int fifo_size,
615 int pixel_size,
616 unsigned long latency_ns)
617{
618 long entries_required, wm_size;
619
620 /*
621 * Note: we need to make sure we don't overflow for various clock &
622 * latency values.
623 * clocks go from a few thousand to several hundred thousand.
624 * latency is usually a few thousand
625 */
626 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
627 1000;
628 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
629
630 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
631
632 wm_size = fifo_size - (entries_required + wm->guard_size);
633
634 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
635
636 /* Don't promote wm_size to unsigned... */
637 if (wm_size > (long)wm->max_wm)
638 wm_size = wm->max_wm;
639 if (wm_size <= 0)
640 wm_size = wm->default_wm;
d6feb196
VS		 641
642 /*
643 * Bspec seems to indicate that the value shouldn't be lower than
644 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
645 * Lets go for 8 which is the burst size since certain platforms
646 * already use a hardcoded 8 (which is what the spec says should be
647 * done).
648 */
649 if (wm_size <= 8)
650 wm_size = 8;
651
b445e3b0
ED		 652 return wm_size;
653}
654
655static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
656{
657 struct drm_crtc *crtc, *enabled = NULL;
658
70e1e0ec 659 for_each_crtc(dev, crtc) {
3490ea5d 660 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 661 if (enabled)
662 return NULL;
663 enabled = crtc;
664 }
665 }
666
667 return enabled;
668}
669
46ba614c 670static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 671{
46ba614c 672 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 673 struct drm_i915_private *dev_priv = dev->dev_private;
674 struct drm_crtc *crtc;
675 const struct cxsr_latency *latency;
676 u32 reg;
677 unsigned long wm;
678
679 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
680 dev_priv->fsb_freq, dev_priv->mem_freq);
681 if (!latency) {
682 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 683 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 684 return;
685 }
686
687 crtc = single_enabled_crtc(dev);
688 if (crtc) {
7c5f93b0 689 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 690 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 691 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 692
693 /* Display SR */
694 wm = intel_calculate_wm(clock, &pineview_display_wm,
695 pineview_display_wm.fifo_size,
696 pixel_size, latency->display_sr);
697 reg = I915_READ(DSPFW1);
698 reg &= ~DSPFW_SR_MASK;
f4998963 699 reg |= FW_WM(wm, SR);
b445e3b0
ED		 700 I915_WRITE(DSPFW1, reg);
701 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
702
703 /* cursor SR */
704 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
705 pineview_display_wm.fifo_size,
706 pixel_size, latency->cursor_sr);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 709 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 710 I915_WRITE(DSPFW3, reg);
711
712 /* Display HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 pixel_size, latency->display_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 718 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 719 I915_WRITE(DSPFW3, reg);
720
721 /* cursor HPLL off SR */
722 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
723 pineview_display_hplloff_wm.fifo_size,
724 pixel_size, latency->cursor_hpll_disable);
725 reg = I915_READ(DSPFW3);
726 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 727 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 728 I915_WRITE(DSPFW3, reg);
729 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
730
5209b1f4 731 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 732 } else {
5209b1f4 733 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 734 }
735}
736
737static bool g4x_compute_wm0(struct drm_device *dev,
738 int plane,
739 const struct intel_watermark_params *display,
740 int display_latency_ns,
741 const struct intel_watermark_params *cursor,
742 int cursor_latency_ns,
743 int *plane_wm,
744 int *cursor_wm)
745{
746 struct drm_crtc *crtc;
4fe8590a 747 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 748 int htotal, hdisplay, clock, pixel_size;
749 int line_time_us, line_count;
750 int entries, tlb_miss;
751
752 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 753 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 754 *cursor_wm = cursor->guard_size;
755 *plane_wm = display->guard_size;
756 return false;
757 }
758
6e3c9717 759 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 760 clock = adjusted_mode->crtc_clock;
fec8cba3 761 htotal = adjusted_mode->crtc_htotal;
6e3c9717 762 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 763 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 764
765 /* Use the small buffer method to calculate plane watermark */
766 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
767 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
768 if (tlb_miss > 0)
769 entries += tlb_miss;
770 entries = DIV_ROUND_UP(entries, display->cacheline_size);
771 *plane_wm = entries + display->guard_size;
772 if (*plane_wm > (int)display->max_wm)
773 *plane_wm = display->max_wm;
774
775 /* Use the large buffer method to calculate cursor watermark */
922044c9 776 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 777 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 778 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 779 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
780 if (tlb_miss > 0)
781 entries += tlb_miss;
782 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
783 *cursor_wm = entries + cursor->guard_size;
784 if (*cursor_wm > (int)cursor->max_wm)
785 *cursor_wm = (int)cursor->max_wm;
786
787 return true;
788}
789
790/*
791 * Check the wm result.
792 *
793 * If any calculated watermark values is larger than the maximum value that
794 * can be programmed into the associated watermark register, that watermark
795 * must be disabled.
796 */
797static bool g4x_check_srwm(struct drm_device *dev,
798 int display_wm, int cursor_wm,
799 const struct intel_watermark_params *display,
800 const struct intel_watermark_params *cursor)
801{
802 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
803 display_wm, cursor_wm);
804
805 if (display_wm > display->max_wm) {
806 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
807 display_wm, display->max_wm);
808 return false;
809 }
810
811 if (cursor_wm > cursor->max_wm) {
812 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
813 cursor_wm, cursor->max_wm);
814 return false;
815 }
816
817 if (!(display_wm || cursor_wm)) {
818 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
819 return false;
820 }
821
822 return true;
823}
824
825static bool g4x_compute_srwm(struct drm_device *dev,
826 int plane,
827 int latency_ns,
828 const struct intel_watermark_params *display,
829 const struct intel_watermark_params *cursor,
830 int *display_wm, int *cursor_wm)
831{
832 struct drm_crtc *crtc;
4fe8590a 833 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 834 int hdisplay, htotal, pixel_size, clock;
835 unsigned long line_time_us;
836 int line_count, line_size;
837 int small, large;
838 int entries;
839
840 if (!latency_ns) {
841 *display_wm = *cursor_wm = 0;
842 return false;
843 }
844
845 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 846 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 847 clock = adjusted_mode->crtc_clock;
fec8cba3 848 htotal = adjusted_mode->crtc_htotal;
6e3c9717 849 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 850 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 851
922044c9 852 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 853 line_count = (latency_ns / line_time_us + 1000) / 1000;
854 line_size = hdisplay * pixel_size;
855
856 /* Use the minimum of the small and large buffer method for primary */
857 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
858 large = line_count * line_size;
859
860 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
861 *display_wm = entries + display->guard_size;
862
863 /* calculate the self-refresh watermark for display cursor */
3dd512fb 864 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 865 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
866 *cursor_wm = entries + cursor->guard_size;
867
868 return g4x_check_srwm(dev,
869 *display_wm, *cursor_wm,
870 display, cursor);
871}
872
15665979
VS		 873#define FW_WM_VLV(value, plane) \
874 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
875
0018fda1
VS		 876static void vlv_write_wm_values(struct intel_crtc *crtc,
877 const struct vlv_wm_values *wm)
878{
879 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
880 enum pipe pipe = crtc->pipe;
881
882 I915_WRITE(VLV_DDL(pipe),
883 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
884 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
885 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
886 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
887
ae80152d 888 I915_WRITE(DSPFW1,
15665979
VS		 889 FW_WM(wm->sr.plane, SR) |
890 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
891 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
892 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 893 I915_WRITE(DSPFW2,
15665979
VS		 894 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
895 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
896 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 897 I915_WRITE(DSPFW3,
15665979 898 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 899
900 if (IS_CHERRYVIEW(dev_priv)) {
901 I915_WRITE(DSPFW7_CHV,
15665979
VS		 902 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
903 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 904 I915_WRITE(DSPFW8_CHV,
15665979
VS		 905 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
906 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 907 I915_WRITE(DSPFW9_CHV,
15665979
VS		 908 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
909 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 910 I915_WRITE(DSPHOWM,
15665979
VS		 911 FW_WM(wm->sr.plane >> 9, SR_HI) |
912 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
913 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
914 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
915 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
916 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
917 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
918 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
919 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
920 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 921 } else {
922 I915_WRITE(DSPFW7,
15665979
VS		 923 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
924 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 925 I915_WRITE(DSPHOWM,
15665979
VS		 926 FW_WM(wm->sr.plane >> 9, SR_HI) |
927 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
928 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
929 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
930 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
931 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
932 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 933 }
934
2cb389b7
VS		 935 /* zero (unused) WM1 watermarks */
936 I915_WRITE(DSPFW4, 0);
937 I915_WRITE(DSPFW5, 0);
938 I915_WRITE(DSPFW6, 0);
939 I915_WRITE(DSPHOWM1, 0);
940
ae80152d 941 POSTING_READ(DSPFW1);
0018fda1
VS		 942}
943
15665979
VS		 944#undef FW_WM_VLV
945
6eb1a681
VS		 946enum vlv_wm_level {
947 VLV_WM_LEVEL_PM2,
948 VLV_WM_LEVEL_PM5,
949 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 950};
951
262cd2e1
VS		 952/* latency must be in 0.1us units. */
953static unsigned int vlv_wm_method2(unsigned int pixel_rate,
954 unsigned int pipe_htotal,
955 unsigned int horiz_pixels,
956 unsigned int bytes_per_pixel,
957 unsigned int latency)
958{
959 unsigned int ret;
960
961 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
962 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
963 ret = DIV_ROUND_UP(ret, 64);
964
965 return ret;
966}
967
968static void vlv_setup_wm_latency(struct drm_device *dev)
969{
970 struct drm_i915_private *dev_priv = dev->dev_private;
971
972 /* all latencies in usec */
973 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
974
58590c14
VS		 975 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
976
262cd2e1
VS		 977 if (IS_CHERRYVIEW(dev_priv)) {
978 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
979 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 980
981 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 982 }
983}
984
985static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
986 struct intel_crtc *crtc,
987 const struct intel_plane_state *state,
988 int level)
989{
990 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
991 int clock, htotal, pixel_size, width, wm;
992
993 if (dev_priv->wm.pri_latency[level] == 0)
994 return USHRT_MAX;
995
996 if (!state->visible)
997 return 0;
998
999 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1000 clock = crtc->config->base.adjusted_mode.crtc_clock;
1001 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1002 width = crtc->config->pipe_src_w;
1003 if (WARN_ON(htotal == 0))
1004 htotal = 1;
1005
1006 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007 /*
1008 * FIXME the formula gives values that are
1009 * too big for the cursor FIFO, and hence we
1010 * would never be able to use cursors. For
1011 * now just hardcode the watermark.
1012 */
1013 wm = 63;
1014 } else {
1015 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1016 dev_priv->wm.pri_latency[level] * 10);
1017 }
1018
1019 return min_t(int, wm, USHRT_MAX);
1020}
1021
54f1b6e1
VS		 1022static void vlv_compute_fifo(struct intel_crtc *crtc)
1023{
1024 struct drm_device *dev = crtc->base.dev;
1025 struct vlv_wm_state *wm_state = &crtc->wm_state;
1026 struct intel_plane *plane;
1027 unsigned int total_rate = 0;
1028 const int fifo_size = 512 - 1;
1029 int fifo_extra, fifo_left = fifo_size;
1030
1031 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1032 struct intel_plane_state *state =
1033 to_intel_plane_state(plane->base.state);
1034
1035 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036 continue;
1037
1038 if (state->visible) {
1039 wm_state->num_active_planes++;
1040 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041 }
1042 }
1043
1044 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045 struct intel_plane_state *state =
1046 to_intel_plane_state(plane->base.state);
1047 unsigned int rate;
1048
1049 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1050 plane->wm.fifo_size = 63;
1051 continue;
1052 }
1053
1054 if (!state->visible) {
1055 plane->wm.fifo_size = 0;
1056 continue;
1057 }
1058
1059 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1060 plane->wm.fifo_size = fifo_size * rate / total_rate;
1061 fifo_left -= plane->wm.fifo_size;
1062 }
1063
1064 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1065
1066 /* spread the remainder evenly */
1067 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1068 int plane_extra;
1069
1070 if (fifo_left == 0)
1071 break;
1072
1073 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1074 continue;
1075
1076 /* give it all to the first plane if none are active */
1077 if (plane->wm.fifo_size == 0 &&
1078 wm_state->num_active_planes)
1079 continue;
1080
1081 plane_extra = min(fifo_extra, fifo_left);
1082 plane->wm.fifo_size += plane_extra;
1083 fifo_left -= plane_extra;
1084 }
1085
1086 WARN_ON(fifo_left != 0);
1087}
1088
262cd2e1
VS		 1089static void vlv_invert_wms(struct intel_crtc *crtc)
1090{
1091 struct vlv_wm_state *wm_state = &crtc->wm_state;
1092 int level;
1093
1094 for (level = 0; level < wm_state->num_levels; level++) {
1095 struct drm_device *dev = crtc->base.dev;
1096 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097 struct intel_plane *plane;
1098
1099 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1100 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 switch (plane->base.type) {
1104 int sprite;
1105 case DRM_PLANE_TYPE_CURSOR:
1106 wm_state->wm[level].cursor = plane->wm.fifo_size -
1107 wm_state->wm[level].cursor;
1108 break;
1109 case DRM_PLANE_TYPE_PRIMARY:
1110 wm_state->wm[level].primary = plane->wm.fifo_size -
1111 wm_state->wm[level].primary;
1112 break;
1113 case DRM_PLANE_TYPE_OVERLAY:
1114 sprite = plane->plane;
1115 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1116 wm_state->wm[level].sprite[sprite];
1117 break;
1118 }
1119 }
1120 }
1121}
1122
26e1fe4f 1123static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1124{
1125 struct drm_device *dev = crtc->base.dev;
1126 struct vlv_wm_state *wm_state = &crtc->wm_state;
1127 struct intel_plane *plane;
1128 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1129 int level;
1130
1131 memset(wm_state, 0, sizeof(*wm_state));
1132
852eb00d 1133 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1134 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1135
1136 wm_state->num_active_planes = 0;
262cd2e1 1137
54f1b6e1 1138 vlv_compute_fifo(crtc);
262cd2e1
VS		 1139
1140 if (wm_state->num_active_planes != 1)
1141 wm_state->cxsr = false;
1142
1143 if (wm_state->cxsr) {
1144 for (level = 0; level < wm_state->num_levels; level++) {
1145 wm_state->sr[level].plane = sr_fifo_size;
1146 wm_state->sr[level].cursor = 63;
1147 }
1148 }
1149
1150 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1151 struct intel_plane_state *state =
1152 to_intel_plane_state(plane->base.state);
1153
1154 if (!state->visible)
1155 continue;
1156
1157 /* normal watermarks */
1158 for (level = 0; level < wm_state->num_levels; level++) {
1159 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1160 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1161
1162 /* hack */
1163 if (WARN_ON(level == 0 && wm > max_wm))
1164 wm = max_wm;
1165
1166 if (wm > plane->wm.fifo_size)
1167 break;
1168
1169 switch (plane->base.type) {
1170 int sprite;
1171 case DRM_PLANE_TYPE_CURSOR:
1172 wm_state->wm[level].cursor = wm;
1173 break;
1174 case DRM_PLANE_TYPE_PRIMARY:
1175 wm_state->wm[level].primary = wm;
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 wm_state->wm[level].sprite[sprite] = wm;
1180 break;
1181 }
1182 }
1183
1184 wm_state->num_levels = level;
1185
1186 if (!wm_state->cxsr)
1187 continue;
1188
1189 /* maxfifo watermarks */
1190 switch (plane->base.type) {
1191 int sprite, level;
1192 case DRM_PLANE_TYPE_CURSOR:
1193 for (level = 0; level < wm_state->num_levels; level++)
1194 wm_state->sr[level].cursor =
1195 wm_state->sr[level].cursor;
1196 break;
1197 case DRM_PLANE_TYPE_PRIMARY:
1198 for (level = 0; level < wm_state->num_levels; level++)
1199 wm_state->sr[level].plane =
1200 min(wm_state->sr[level].plane,
1201 wm_state->wm[level].primary);
1202 break;
1203 case DRM_PLANE_TYPE_OVERLAY:
1204 sprite = plane->plane;
1205 for (level = 0; level < wm_state->num_levels; level++)
1206 wm_state->sr[level].plane =
1207 min(wm_state->sr[level].plane,
1208 wm_state->wm[level].sprite[sprite]);
1209 break;
1210 }
1211 }
1212
1213 /* clear any (partially) filled invalid levels */
58590c14 1214 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1215 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1216 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1217 }
1218
1219 vlv_invert_wms(crtc);
1220}
1221
54f1b6e1
VS		 1222#define VLV_FIFO(plane, value) \
1223 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1224
1225static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1226{
1227 struct drm_device *dev = crtc->base.dev;
1228 struct drm_i915_private *dev_priv = to_i915(dev);
1229 struct intel_plane *plane;
1230 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1231
1232 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1233 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1234 WARN_ON(plane->wm.fifo_size != 63);
1235 continue;
1236 }
1237
1238 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1239 sprite0_start = plane->wm.fifo_size;
1240 else if (plane->plane == 0)
1241 sprite1_start = sprite0_start + plane->wm.fifo_size;
1242 else
1243 fifo_size = sprite1_start + plane->wm.fifo_size;
1244 }
1245
1246 WARN_ON(fifo_size != 512 - 1);
1247
1248 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1249 pipe_name(crtc->pipe), sprite0_start,
1250 sprite1_start, fifo_size);
1251
1252 switch (crtc->pipe) {
1253 uint32_t dsparb, dsparb2, dsparb3;
1254 case PIPE_A:
1255 dsparb = I915_READ(DSPARB);
1256 dsparb2 = I915_READ(DSPARB2);
1257
1258 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1259 VLV_FIFO(SPRITEB, 0xff));
1260 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1261 VLV_FIFO(SPRITEB, sprite1_start));
1262
1263 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1264 VLV_FIFO(SPRITEB_HI, 0x1));
1265 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1266 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1267
1268 I915_WRITE(DSPARB, dsparb);
1269 I915_WRITE(DSPARB2, dsparb2);
1270 break;
1271 case PIPE_B:
1272 dsparb = I915_READ(DSPARB);
1273 dsparb2 = I915_READ(DSPARB2);
1274
1275 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1276 VLV_FIFO(SPRITED, 0xff));
1277 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1278 VLV_FIFO(SPRITED, sprite1_start));
1279
1280 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1281 VLV_FIFO(SPRITED_HI, 0xff));
1282 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1283 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1284
1285 I915_WRITE(DSPARB, dsparb);
1286 I915_WRITE(DSPARB2, dsparb2);
1287 break;
1288 case PIPE_C:
1289 dsparb3 = I915_READ(DSPARB3);
1290 dsparb2 = I915_READ(DSPARB2);
1291
1292 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1293 VLV_FIFO(SPRITEF, 0xff));
1294 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1295 VLV_FIFO(SPRITEF, sprite1_start));
1296
1297 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1298 VLV_FIFO(SPRITEF_HI, 0xff));
1299 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1300 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1301
1302 I915_WRITE(DSPARB3, dsparb3);
1303 I915_WRITE(DSPARB2, dsparb2);
1304 break;
1305 default:
1306 break;
1307 }
1308}
1309
1310#undef VLV_FIFO
1311
262cd2e1
VS		 1312static void vlv_merge_wm(struct drm_device *dev,
1313 struct vlv_wm_values *wm)
1314{
1315 struct intel_crtc *crtc;
1316 int num_active_crtcs = 0;
1317
58590c14 1318 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1319 wm->cxsr = true;
1320
1321 for_each_intel_crtc(dev, crtc) {
1322 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1323
1324 if (!crtc->active)
1325 continue;
1326
1327 if (!wm_state->cxsr)
1328 wm->cxsr = false;
1329
1330 num_active_crtcs++;
1331 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1332 }
1333
1334 if (num_active_crtcs != 1)
1335 wm->cxsr = false;
1336
6f9c784b
VS		 1337 if (num_active_crtcs > 1)
1338 wm->level = VLV_WM_LEVEL_PM2;
1339
262cd2e1
VS		 1340 for_each_intel_crtc(dev, crtc) {
1341 struct vlv_wm_state *wm_state = &crtc->wm_state;
1342 enum pipe pipe = crtc->pipe;
1343
1344 if (!crtc->active)
1345 continue;
1346
1347 wm->pipe[pipe] = wm_state->wm[wm->level];
1348 if (wm->cxsr)
1349 wm->sr = wm_state->sr[wm->level];
1350
1351 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1352 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1353 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1354 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1355 }
1356}
1357
1358static void vlv_update_wm(struct drm_crtc *crtc)
1359{
1360 struct drm_device *dev = crtc->dev;
1361 struct drm_i915_private *dev_priv = dev->dev_private;
1362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1363 enum pipe pipe = intel_crtc->pipe;
1364 struct vlv_wm_values wm = {};
1365
26e1fe4f 1366 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1367 vlv_merge_wm(dev, &wm);
1368
54f1b6e1
VS		 1369 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1370 /* FIXME should be part of crtc atomic commit */
1371 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1372 return;
54f1b6e1 1373 }
262cd2e1
VS		 1374
1375 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1376 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1377 chv_set_memory_dvfs(dev_priv, false);
1378
1379 if (wm.level < VLV_WM_LEVEL_PM5 &&
1380 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1381 chv_set_memory_pm5(dev_priv, false);
1382
852eb00d 1383 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1384 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1385
54f1b6e1
VS		 1386 /* FIXME should be part of crtc atomic commit */
1387 vlv_pipe_set_fifo_size(intel_crtc);
1388
262cd2e1
VS		 1389 vlv_write_wm_values(intel_crtc, &wm);
1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1393 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1394 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1395 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1396
852eb00d 1397 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1398 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1399
1400 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1401 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1402 chv_set_memory_pm5(dev_priv, true);
1403
1404 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1405 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1406 chv_set_memory_dvfs(dev_priv, true);
1407
1408 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1409}
1410
ae80152d
VS		 1411#define single_plane_enabled(mask) is_power_of_2(mask)
1412
46ba614c 1413static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1414{
46ba614c 1415 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1416 static const int sr_latency_ns = 12000;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1419 int plane_sr, cursor_sr;
1420 unsigned int enabled = 0;
9858425c 1421 bool cxsr_enabled;
b445e3b0 1422
51cea1f4 1423 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1424 &g4x_wm_info, pessimal_latency_ns,
1425 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1426 &planea_wm, &cursora_wm))
51cea1f4 1427 enabled |= 1 << PIPE_A;
b445e3b0 1428
51cea1f4 1429 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1430 &g4x_wm_info, pessimal_latency_ns,
1431 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1432 &planeb_wm, &cursorb_wm))
51cea1f4 1433 enabled |= 1 << PIPE_B;
b445e3b0 1434
b445e3b0
ED		 1435 if (single_plane_enabled(enabled) &&
1436 g4x_compute_srwm(dev, ffs(enabled) - 1,
1437 sr_latency_ns,
1438 &g4x_wm_info,
1439 &g4x_cursor_wm_info,
52bd02d8 1440 &plane_sr, &cursor_sr)) {
9858425c 1441 cxsr_enabled = true;
52bd02d8 1442 } else {
9858425c 1443 cxsr_enabled = false;
5209b1f4 1444 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1445 plane_sr = cursor_sr = 0;
1446 }
b445e3b0 1447
a5043453
VS		 1448 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1449 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1450 planea_wm, cursora_wm,
1451 planeb_wm, cursorb_wm,
1452 plane_sr, cursor_sr);
1453
1454 I915_WRITE(DSPFW1,
f4998963
VS		 1455 FW_WM(plane_sr, SR) |
1456 FW_WM(cursorb_wm, CURSORB) |
1457 FW_WM(planeb_wm, PLANEB) |
1458 FW_WM(planea_wm, PLANEA));
b445e3b0 1459 I915_WRITE(DSPFW2,
8c919b28 1460 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1461 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1462 /* HPLL off in SR has some issues on G4x... disable it */
1463 I915_WRITE(DSPFW3,
8c919b28 1464 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1465 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1466
1467 if (cxsr_enabled)
1468 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1469}
1470
46ba614c 1471static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1472{
46ba614c 1473 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_crtc *crtc;
1476 int srwm = 1;
1477 int cursor_sr = 16;
9858425c 1478 bool cxsr_enabled;
b445e3b0
ED		 1479
1480 /* Calc sr entries for one plane configs */
1481 crtc = single_enabled_crtc(dev);
1482 if (crtc) {
1483 /* self-refresh has much higher latency */
1484 static const int sr_latency_ns = 12000;
124abe07 1485 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1486 int clock = adjusted_mode->crtc_clock;
fec8cba3 1487 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1488 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1489 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1490 unsigned long line_time_us;
1491 int entries;
1492
922044c9 1493 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1494
1495 /* Use ns/us then divide to preserve precision */
1496 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497 pixel_size * hdisplay;
1498 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499 srwm = I965_FIFO_SIZE - entries;
1500 if (srwm < 0)
1501 srwm = 1;
1502 srwm &= 0x1ff;
1503 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504 entries, srwm);
1505
1506 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1507 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1508 entries = DIV_ROUND_UP(entries,
1509 i965_cursor_wm_info.cacheline_size);
1510 cursor_sr = i965_cursor_wm_info.fifo_size -
1511 (entries + i965_cursor_wm_info.guard_size);
1512
1513 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514 cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517 "cursor %d\n", srwm, cursor_sr);
1518
9858425c 1519 cxsr_enabled = true;
b445e3b0 1520 } else {
9858425c 1521 cxsr_enabled = false;
b445e3b0 1522 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1523 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1524 }
1525
1526 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527 srwm);
1528
1529 /* 965 has limitations... */
f4998963
VS		 1530 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531 FW_WM(8, CURSORB) |
1532 FW_WM(8, PLANEB) |
1533 FW_WM(8, PLANEA));
1534 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535 FW_WM(8, PLANEC_OLD));
b445e3b0 1536 /* update cursor SR watermark */
f4998963 1537 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1538
1539 if (cxsr_enabled)
1540 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1541}
1542
f4998963
VS		 1543#undef FW_WM
1544
46ba614c 1545static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1546{
46ba614c 1547 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 const struct intel_watermark_params *wm_info;
1550 uint32_t fwater_lo;
1551 uint32_t fwater_hi;
1552 int cwm, srwm = 1;
1553 int fifo_size;
1554 int planea_wm, planeb_wm;
1555 struct drm_crtc *crtc, *enabled = NULL;
1556
1557 if (IS_I945GM(dev))
1558 wm_info = &i945_wm_info;
1559 else if (!IS_GEN2(dev))
1560 wm_info = &i915_wm_info;
1561 else
9d539105 1562 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1563
1564 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1566 if (intel_crtc_active(crtc)) {
241bfc38 1567 const struct drm_display_mode *adjusted_mode;
59bea882 1568 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1569 if (IS_GEN2(dev))
1570 cpp = 4;
1571
6e3c9717 1572 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1573 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1574 wm_info, fifo_size, cpp,
5aef6003 1575 pessimal_latency_ns);
b445e3b0 1576 enabled = crtc;
9d539105 1577 } else {
b445e3b0 1578 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1579 if (planea_wm > (long)wm_info->max_wm)
1580 planea_wm = wm_info->max_wm;
1581 }
1582
1583 if (IS_GEN2(dev))
1584 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1585
1586 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1588 if (intel_crtc_active(crtc)) {
241bfc38 1589 const struct drm_display_mode *adjusted_mode;
59bea882 1590 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1591 if (IS_GEN2(dev))
1592 cpp = 4;
1593
6e3c9717 1594 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1595 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1596 wm_info, fifo_size, cpp,
5aef6003 1597 pessimal_latency_ns);
b445e3b0
ED		 1598 if (enabled == NULL)
1599 enabled = crtc;
1600 else
1601 enabled = NULL;
9d539105 1602 } else {
b445e3b0 1603 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1604 if (planeb_wm > (long)wm_info->max_wm)
1605 planeb_wm = wm_info->max_wm;
1606 }
b445e3b0
ED		 1607
1608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
2ab1bc9d 1610 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1611 struct drm_i915_gem_object *obj;
2ab1bc9d 1612
59bea882 1613 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1614
1615 /* self-refresh seems busted with untiled */
2ff8fde1 1616 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1617 enabled = NULL;
1618 }
1619
b445e3b0
ED		 1620 /*
1621 * Overlay gets an aggressive default since video jitter is bad.
1622 */
1623 cwm = 2;
1624
1625 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1626 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1627
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev) && enabled) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns = 6000;
124abe07 1632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1633 int clock = adjusted_mode->crtc_clock;
fec8cba3 1634 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1635 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1636 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1637 unsigned long line_time_us;
1638 int entries;
1639
922044c9 1640 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644 pixel_size * hdisplay;
1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
1651 if (IS_I945G(dev) || IS_I945GM(dev))
1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654 else if (IS_I915GM(dev))
1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
5209b1f4
ID		 1671 if (enabled)
1672 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1673}
1674
feb56b93 1675static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1676{
46ba614c 1677 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 struct drm_crtc *crtc;
241bfc38 1680 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1681 uint32_t fwater_lo;
1682 int planea_wm;
1683
1684 crtc = single_enabled_crtc(dev);
1685 if (crtc == NULL)
1686 return;
1687
6e3c9717 1688 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1689 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1690 &i845_wm_info,
b445e3b0 1691 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1692 4, pessimal_latency_ns);
b445e3b0
ED		 1693 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1694 fwater_lo |= (3<<8) | planea_wm;
1695
1696 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1697
1698 I915_WRITE(FW_BLC, fwater_lo);
1699}
1700
8cfb3407 1701uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1702{
fd4daa9c 1703 uint32_t pixel_rate;
801bcfff 1704
8cfb3407 1705 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1706
1707 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1708 * adjust the pixel_rate here. */
1709
8cfb3407 1710 if (pipe_config->pch_pfit.enabled) {
801bcfff 1711 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1712 uint32_t pfit_size = pipe_config->pch_pfit.size;
1713
1714 pipe_w = pipe_config->pipe_src_w;
1715 pipe_h = pipe_config->pipe_src_h;
801bcfff 1716
801bcfff
PZ		 1717 pfit_w = (pfit_size >> 16) & 0xFFFF;
1718 pfit_h = pfit_size & 0xFFFF;
1719 if (pipe_w < pfit_w)
1720 pipe_w = pfit_w;
1721 if (pipe_h < pfit_h)
1722 pipe_h = pfit_h;
1723
1724 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1725 pfit_w * pfit_h);
1726 }
1727
1728 return pixel_rate;
1729}
1730
37126462 1731/* latency must be in 0.1us units. */
23297044 1732static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1733 uint32_t latency)
1734{
1735 uint64_t ret;
1736
3312ba65
VS		 1737 if (WARN(latency == 0, "Latency value missing\n"))
1738 return UINT_MAX;
1739
801bcfff
PZ		 1740 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1741 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1742
1743 return ret;
1744}
1745
37126462 1746/* latency must be in 0.1us units. */
23297044 1747static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1748 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1749 uint32_t latency)
1750{
1751 uint32_t ret;
1752
3312ba65
VS		 1753 if (WARN(latency == 0, "Latency value missing\n"))
1754 return UINT_MAX;
1755
801bcfff
PZ		 1756 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1757 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1758 ret = DIV_ROUND_UP(ret, 64) + 2;
1759 return ret;
1760}
1761
23297044 1762static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1763 uint8_t bytes_per_pixel)
1764{
1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1766}
1767
2ac96d2a
PB		 1768struct skl_pipe_wm_parameters {
1769 bool active;
1770 uint32_t pipe_htotal;
1771 uint32_t pixel_rate; /* in KHz */
1772 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1773 struct intel_plane_wm_parameters cursor;
1774};
1775
820c1980 1776struct ilk_pipe_wm_parameters {
801bcfff 1777 bool active;
801bcfff
PZ		 1778 uint32_t pipe_htotal;
1779 uint32_t pixel_rate;
c35426d2
VS		 1780 struct intel_plane_wm_parameters pri;
1781 struct intel_plane_wm_parameters spr;
1782 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1783};
1784
820c1980 1785struct ilk_wm_maximums {
cca32e9a
PZ		 1786 uint16_t pri;
1787 uint16_t spr;
1788 uint16_t cur;
1789 uint16_t fbc;
1790};
1791
240264f4
VS		 1792/* used in computing the new watermarks state */
1793struct intel_wm_config {
1794 unsigned int num_pipes_active;
1795 bool sprites_enabled;
1796 bool sprites_scaled;
240264f4
VS		 1797};
1798
37126462
VS		 1799/*
1800 * For both WM_PIPE and WM_LP.
1801 * mem_value must be in 0.1us units.
1802 */
820c1980 1803static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1804 uint32_t mem_value,
1805 bool is_lp)
801bcfff 1806{
cca32e9a
PZ		 1807 uint32_t method1, method2;
1808
c35426d2 1809 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1810 return 0;
1811
23297044 1812 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1813 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1814 mem_value);
1815
1816 if (!is_lp)
1817 return method1;
1818
23297044 1819 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1820 params->pipe_htotal,
c35426d2
VS		 1821 params->pri.horiz_pixels,
1822 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1823 mem_value);
1824
1825 return min(method1, method2);
801bcfff
PZ		 1826}
1827
37126462
VS		 1828/*
1829 * For both WM_PIPE and WM_LP.
1830 * mem_value must be in 0.1us units.
1831 */
820c1980 1832static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1833 uint32_t mem_value)
1834{
1835 uint32_t method1, method2;
1836
c35426d2 1837 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1838 return 0;
1839
23297044 1840 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1841 params->spr.bytes_per_pixel,
801bcfff 1842 mem_value);
23297044 1843 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1844 params->pipe_htotal,
c35426d2
VS		 1845 params->spr.horiz_pixels,
1846 params->spr.bytes_per_pixel,
801bcfff
PZ		 1847 mem_value);
1848 return min(method1, method2);
1849}
1850
37126462
VS		 1851/*
1852 * For both WM_PIPE and WM_LP.
1853 * mem_value must be in 0.1us units.
1854 */
820c1980 1855static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1856 uint32_t mem_value)
1857{
c35426d2 1858 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1859 return 0;
1860
23297044 1861 return ilk_wm_method2(params->pixel_rate,
801bcfff 1862 params->pipe_htotal,
c35426d2
VS		 1863 params->cur.horiz_pixels,
1864 params->cur.bytes_per_pixel,
801bcfff
PZ		 1865 mem_value);
1866}
1867
cca32e9a 1868/* Only for WM_LP. */
820c1980 1869static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1870 uint32_t pri_val)
cca32e9a 1871{
c35426d2 1872 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1873 return 0;
1874
23297044 1875 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1876 params->pri.horiz_pixels,
1877 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1878}
1879
158ae64f
VS		 1880static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1881{
416f4727
VS		 1882 if (INTEL_INFO(dev)->gen >= 8)
1883 return 3072;
1884 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1885 return 768;
1886 else
1887 return 512;
1888}
1889
4e975081
VS		 1890static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1891 int level, bool is_sprite)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 /* BDW primary/sprite plane watermarks */
1895 return level == 0 ? 255 : 2047;
1896 else if (INTEL_INFO(dev)->gen >= 7)
1897 /* IVB/HSW primary/sprite plane watermarks */
1898 return level == 0 ? 127 : 1023;
1899 else if (!is_sprite)
1900 /* ILK/SNB primary plane watermarks */
1901 return level == 0 ? 127 : 511;
1902 else
1903 /* ILK/SNB sprite plane watermarks */
1904 return level == 0 ? 63 : 255;
1905}
1906
1907static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1908 int level)
1909{
1910 if (INTEL_INFO(dev)->gen >= 7)
1911 return level == 0 ? 63 : 255;
1912 else
1913 return level == 0 ? 31 : 63;
1914}
1915
1916static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1917{
1918 if (INTEL_INFO(dev)->gen >= 8)
1919 return 31;
1920 else
1921 return 15;
1922}
1923
158ae64f
VS		 1924/* Calculate the maximum primary/sprite plane watermark */
1925static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1926 int level,
240264f4 1927 const struct intel_wm_config *config,
158ae64f
VS		 1928 enum intel_ddb_partitioning ddb_partitioning,
1929 bool is_sprite)
1930{
1931 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1932
1933 /* if sprites aren't enabled, sprites get nothing */
240264f4 1934 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1935 return 0;
1936
1937 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1938 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1939 fifo_size /= INTEL_INFO(dev)->num_pipes;
1940
1941 /*
1942 * For some reason the non self refresh
1943 * FIFO size is only half of the self
1944 * refresh FIFO size on ILK/SNB.
1945 */
1946 if (INTEL_INFO(dev)->gen <= 6)
1947 fifo_size /= 2;
1948 }
1949
240264f4 1950 if (config->sprites_enabled) {
158ae64f
VS		 1951 /* level 0 is always calculated with 1:1 split */
1952 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1953 if (is_sprite)
1954 fifo_size *= 5;
1955 fifo_size /= 6;
1956 } else {
1957 fifo_size /= 2;
1958 }
1959 }
1960
1961 /* clamp to max that the registers can hold */
4e975081 1962 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1963}
1964
1965/* Calculate the maximum cursor plane watermark */
1966static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1967 int level,
1968 const struct intel_wm_config *config)
158ae64f
VS		 1969{
1970 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1971 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1972 return 64;
1973
1974 /* otherwise just report max that registers can hold */
4e975081 1975 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1976}
1977
d34ff9c6 1978static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1979 int level,
1980 const struct intel_wm_config *config,
1981 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1982 struct ilk_wm_maximums *max)
158ae64f 1983{
240264f4
VS		 1984 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1985 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1986 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1987 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1988}
1989
a3cb4048
VS		 1990static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1991 int level,
1992 struct ilk_wm_maximums *max)
1993{
1994 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1995 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1996 max->cur = ilk_cursor_wm_reg_max(dev, level);
1997 max->fbc = ilk_fbc_wm_reg_max(dev);
1998}
1999
d9395655 2000static bool ilk_validate_wm_level(int level,
820c1980 2001 const struct ilk_wm_maximums *max,
d9395655 2002 struct intel_wm_level *result)
a9786a11
VS		 2003{
2004 bool ret;
2005
2006 /* already determined to be invalid? */
2007 if (!result->enable)
2008 return false;
2009
2010 result->enable = result->pri_val <= max->pri &&
2011 result->spr_val <= max->spr &&
2012 result->cur_val <= max->cur;
2013
2014 ret = result->enable;
2015
2016 /*
2017 * HACK until we can pre-compute everything,
2018 * and thus fail gracefully if LP0 watermarks
2019 * are exceeded...
2020 */
2021 if (level == 0 && !result->enable) {
2022 if (result->pri_val > max->pri)
2023 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2024 level, result->pri_val, max->pri);
2025 if (result->spr_val > max->spr)
2026 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2027 level, result->spr_val, max->spr);
2028 if (result->cur_val > max->cur)
2029 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2030 level, result->cur_val, max->cur);
2031
2032 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2033 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2034 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2035 result->enable = true;
2036 }
2037
a9786a11
VS		 2038 return ret;
2039}
2040
d34ff9c6 2041static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2042 int level,
820c1980 2043 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2044 struct intel_wm_level *result)
6f5ddd17
VS		 2045{
2046 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2047 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2048 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2049
2050 /* WM1+ latency values stored in 0.5us units */
2051 if (level > 0) {
2052 pri_latency *= 5;
2053 spr_latency *= 5;
2054 cur_latency *= 5;
2055 }
2056
2057 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2058 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2059 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2060 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2061 result->enable = true;
2062}
2063
801bcfff
PZ		 2064static uint32_t
2065hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2066{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7c5f93b0 2069 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2070 u32 linetime, ips_linetime;
1f8eeabf 2071
3ef00284 2072 if (!intel_crtc->active)
801bcfff 2073 return 0;
1011d8c4 2074
1f8eeabf
ED		 2075 /* The WM are computed with base on how long it takes to fill a single
2076 * row at the given clock rate, multiplied by 8.
2077 * */
124abe07
VS		 2078 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2079 adjusted_mode->crtc_clock);
2080 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2081 dev_priv->cdclk_freq);
1f8eeabf 2082
801bcfff
PZ		 2083 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2084 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2085}
2086
2af30a5c 2087static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2088{
2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090
2af30a5c
PB		 2091 if (IS_GEN9(dev)) {
2092 uint32_t val;
4f947386 2093 int ret, i;
367294be 2094 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2095
2096 /* read the first set of memory latencies[0:3] */
2097 val = 0; /* data0 to be programmed to 0 for first set */
2098 mutex_lock(&dev_priv->rps.hw_lock);
2099 ret = sandybridge_pcode_read(dev_priv,
2100 GEN9_PCODE_READ_MEM_LATENCY,
2101 &val);
2102 mutex_unlock(&dev_priv->rps.hw_lock);
2103
2104 if (ret) {
2105 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2106 return;
2107 }
2108
2109 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2110 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2111 GEN9_MEM_LATENCY_LEVEL_MASK;
2112 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2113 GEN9_MEM_LATENCY_LEVEL_MASK;
2114 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2115 GEN9_MEM_LATENCY_LEVEL_MASK;
2116
2117 /* read the second set of memory latencies[4:7] */
2118 val = 1; /* data0 to be programmed to 1 for second set */
2119 mutex_lock(&dev_priv->rps.hw_lock);
2120 ret = sandybridge_pcode_read(dev_priv,
2121 GEN9_PCODE_READ_MEM_LATENCY,
2122 &val);
2123 mutex_unlock(&dev_priv->rps.hw_lock);
2124 if (ret) {
2125 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2126 return;
2127 }
2128
2129 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2130 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2131 GEN9_MEM_LATENCY_LEVEL_MASK;
2132 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2133 GEN9_MEM_LATENCY_LEVEL_MASK;
2134 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2135 GEN9_MEM_LATENCY_LEVEL_MASK;
2136
367294be 2137 /*
6f97235b
DL		 2138 * WaWmMemoryReadLatency:skl
2139 *
367294be
VK		 2140 * punit doesn't take into account the read latency so we need
2141 * to add 2us to the various latency levels we retrieve from
2142 * the punit.
2143 * - W0 is a bit special in that it's the only level that
2144 * can't be disabled if we want to have display working, so
2145 * we always add 2us there.
2146 * - For levels >=1, punit returns 0us latency when they are
2147 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2148 *
2149 * Additionally, if a level n (n > 1) has a 0us latency, all
2150 * levels m (m >= n) need to be disabled. We make sure to
2151 * sanitize the values out of the punit to satisfy this
2152 * requirement.
367294be
VK		 2153 */
2154 wm[0] += 2;
2155 for (level = 1; level <= max_level; level++)
2156 if (wm[level] != 0)
2157 wm[level] += 2;
4f947386
VK		 2158 else {
2159 for (i = level + 1; i <= max_level; i++)
2160 wm[i] = 0;
367294be 2161
4f947386
VK		 2162 break;
2163 }
2af30a5c 2164 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2165 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2166
2167 wm[0] = (sskpd >> 56) & 0xFF;
2168 if (wm[0] == 0)
2169 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2170 wm[1] = (sskpd >> 4) & 0xFF;
2171 wm[2] = (sskpd >> 12) & 0xFF;
2172 wm[3] = (sskpd >> 20) & 0x1FF;
2173 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2174 } else if (INTEL_INFO(dev)->gen >= 6) {
2175 uint32_t sskpd = I915_READ(MCH_SSKPD);
2176
2177 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2178 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2179 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2180 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2181 } else if (INTEL_INFO(dev)->gen >= 5) {
2182 uint32_t mltr = I915_READ(MLTR_ILK);
2183
2184 /* ILK primary LP0 latency is 700 ns */
2185 wm[0] = 7;
2186 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2187 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2188 }
2189}
2190
53615a5e
VS		 2191static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2192{
2193 /* ILK sprite LP0 latency is 1300 ns */
2194 if (INTEL_INFO(dev)->gen == 5)
2195 wm[0] = 13;
2196}
2197
2198static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2199{
2200 /* ILK cursor LP0 latency is 1300 ns */
2201 if (INTEL_INFO(dev)->gen == 5)
2202 wm[0] = 13;
2203
2204 /* WaDoubleCursorLP3Latency:ivb */
2205 if (IS_IVYBRIDGE(dev))
2206 wm[3] *= 2;
2207}
2208
546c81fd 2209int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2210{
26ec971e 2211 /* how many WM levels are we expecting */
b6e742f6 2212 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2213 return 7;
2214 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2215 return 4;
26ec971e 2216 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2217 return 3;
26ec971e 2218 else
ad0d6dc4
VS		 2219 return 2;
2220}
7526ed79 2221
ad0d6dc4
VS		 2222static void intel_print_wm_latency(struct drm_device *dev,
2223 const char *name,
2af30a5c 2224 const uint16_t wm[8])
ad0d6dc4
VS		 2225{
2226 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2227
2228 for (level = 0; level <= max_level; level++) {
2229 unsigned int latency = wm[level];
2230
2231 if (latency == 0) {
2232 DRM_ERROR("%s WM%d latency not provided\n",
2233 name, level);
2234 continue;
2235 }
2236
2af30a5c
PB		 2237 /*
2238 * - latencies are in us on gen9.
2239 * - before then, WM1+ latency values are in 0.5us units
2240 */
2241 if (IS_GEN9(dev))
2242 latency *= 10;
2243 else if (level > 0)
26ec971e
VS		 2244 latency *= 5;
2245
2246 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2247 name, level, wm[level],
2248 latency / 10, latency % 10);
2249 }
2250}
2251
e95a2f75
VS		 2252static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2253 uint16_t wm[5], uint16_t min)
2254{
2255 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2256
2257 if (wm[0] >= min)
2258 return false;
2259
2260 wm[0] = max(wm[0], min);
2261 for (level = 1; level <= max_level; level++)
2262 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2263
2264 return true;
2265}
2266
2267static void snb_wm_latency_quirk(struct drm_device *dev)
2268{
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270 bool changed;
2271
2272 /*
2273 * The BIOS provided WM memory latency values are often
2274 * inadequate for high resolution displays. Adjust them.
2275 */
2276 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2277 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2278 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2279
2280 if (!changed)
2281 return;
2282
2283 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2284 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2285 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2286 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2287}
2288
fa50ad61 2289static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2290{
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292
2293 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2294
2295 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2296 sizeof(dev_priv->wm.pri_latency));
2297 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2298 sizeof(dev_priv->wm.pri_latency));
2299
2300 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2301 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2302
2303 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2304 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2305 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2306
2307 if (IS_GEN6(dev))
2308 snb_wm_latency_quirk(dev);
53615a5e
VS		 2309}
2310
2af30a5c
PB		 2311static void skl_setup_wm_latency(struct drm_device *dev)
2312{
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314
2315 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2316 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2317}
2318
820c1980 2319static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2320 struct ilk_pipe_wm_parameters *p)
1011d8c4 2321{
7c4a395f
VS		 2322 struct drm_device *dev = crtc->dev;
2323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2325 struct drm_plane *plane;
1011d8c4 2326
3ef00284 2327 if (!intel_crtc->active)
2a44b76b 2328 return;
801bcfff 2329
2a44b76b 2330 p->active = true;
6e3c9717 2331 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2332 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2333
54da691d 2334 if (crtc->primary->state->fb)
c9f038a1
MR		 2335 p->pri.bytes_per_pixel =
2336 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG		 2337 else
2338 p->pri.bytes_per_pixel = 4;
2339
2340 p->cur.bytes_per_pixel = 4;
2341 /*
2342 * TODO: for now, assume primary and cursor planes are always enabled.
2343 * Setting them to false makes the screen flicker.
2344 */
2345 p->pri.enabled = true;
2346 p->cur.enabled = true;
c9f038a1 2347
6e3c9717 2348 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2349 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2350
4ea50e99 2351 drm_for_each_legacy_plane(plane, dev) {
801bcfff 2352 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2353
2a44b76b 2354 if (intel_plane->pipe == pipe) {
7c4a395f 2355 p->spr = intel_plane->wm;
2a44b76b
VS		 2356 break;
2357 }
2358 }
2359}
2360
2361static void ilk_compute_wm_config(struct drm_device *dev,
2362 struct intel_wm_config *config)
2363{
2364 struct intel_crtc *intel_crtc;
2365
2366 /* Compute the currently _active_ config */
d3fcc808 2367 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2368 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2369
2a44b76b
VS		 2370 if (!wm->pipe_enabled)
2371 continue;
cca32e9a 2372
2a44b76b
VS		 2373 config->sprites_enabled |= wm->sprites_enabled;
2374 config->sprites_scaled |= wm->sprites_scaled;
2375 config->num_pipes_active++;
cca32e9a 2376 }
801bcfff
PZ		 2377}
2378
0b2ae6d7
VS		 2379/* Compute new watermarks for the pipe */
2380static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2381 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2382 struct intel_pipe_wm *pipe_wm)
2383{
2384 struct drm_device *dev = crtc->dev;
d34ff9c6 2385 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2386 int level, max_level = ilk_wm_max_level(dev);
2387 /* LP0 watermark maximums depend on this pipe alone */
2388 struct intel_wm_config config = {
2389 .num_pipes_active = 1,
2390 .sprites_enabled = params->spr.enabled,
2391 .sprites_scaled = params->spr.scaled,
2392 };
820c1980 2393 struct ilk_wm_maximums max;
0b2ae6d7 2394
2a44b76b
VS		 2395 pipe_wm->pipe_enabled = params->active;
2396 pipe_wm->sprites_enabled = params->spr.enabled;
2397 pipe_wm->sprites_scaled = params->spr.scaled;
2398
7b39a0b7
VS		 2399 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2400 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2401 max_level = 1;
2402
2403 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2404 if (params->spr.scaled)
2405 max_level = 0;
2406
a3cb4048 2407 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2408
a42a5719 2409 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2410 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2411
a3cb4048
VS		 2412 /* LP0 watermarks always use 1/2 DDB partitioning */
2413 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2414
0b2ae6d7 2415 /* At least LP0 must be valid */
a3cb4048
VS		 2416 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2417 return false;
2418
2419 ilk_compute_wm_reg_maximums(dev, 1, &max);
2420
2421 for (level = 1; level <= max_level; level++) {
2422 struct intel_wm_level wm = {};
2423
2424 ilk_compute_wm_level(dev_priv, level, params, &wm);
2425
2426 /*
2427 * Disable any watermark level that exceeds the
2428 * register maximums since such watermarks are
2429 * always invalid.
2430 */
2431 if (!ilk_validate_wm_level(level, &max, &wm))
2432 break;
2433
2434 pipe_wm->wm[level] = wm;
2435 }
2436
2437 return true;
0b2ae6d7
VS		 2438}
2439
2440/*
2441 * Merge the watermarks from all active pipes for a specific level.
2442 */
2443static void ilk_merge_wm_level(struct drm_device *dev,
2444 int level,
2445 struct intel_wm_level *ret_wm)
2446{
2447 const struct intel_crtc *intel_crtc;
2448
d52fea5b
VS		 2449 ret_wm->enable = true;
2450
d3fcc808 2451 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2452 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2453 const struct intel_wm_level *wm = &active->wm[level];
2454
2455 if (!active->pipe_enabled)
2456 continue;
0b2ae6d7 2457
d52fea5b
VS		 2458 /*
2459 * The watermark values may have been used in the past,
2460 * so we must maintain them in the registers for some
2461 * time even if the level is now disabled.
2462 */
0b2ae6d7 2463 if (!wm->enable)
d52fea5b 2464 ret_wm->enable = false;
0b2ae6d7
VS		 2465
2466 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2467 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2468 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2469 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2470 }
0b2ae6d7
VS		 2471}
2472
2473/*
2474 * Merge all low power watermarks for all active pipes.
2475 */
2476static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2477 const struct intel_wm_config *config,
820c1980 2478 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2479 struct intel_pipe_wm *merged)
2480{
7733b49b 2481 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2482 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2483 int last_enabled_level = max_level;
0b2ae6d7 2484
0ba22e26
VS		 2485 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2486 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2487 config->num_pipes_active > 1)
2488 return;
2489
6c8b6c28
VS		 2490 /* ILK: FBC WM must be disabled always */
2491 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2492
2493 /* merge each WM1+ level */
2494 for (level = 1; level <= max_level; level++) {
2495 struct intel_wm_level *wm = &merged->wm[level];
2496
2497 ilk_merge_wm_level(dev, level, wm);
2498
d52fea5b
VS		 2499 if (level > last_enabled_level)
2500 wm->enable = false;
2501 else if (!ilk_validate_wm_level(level, max, wm))
2502 /* make sure all following levels get disabled */
2503 last_enabled_level = level - 1;
0b2ae6d7
VS		 2504
2505 /*
2506 * The spec says it is preferred to disable
2507 * FBC WMs instead of disabling a WM level.
2508 */
2509 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2510 if (wm->enable)
2511 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2512 wm->fbc_val = 0;
2513 }
2514 }
6c8b6c28
VS		 2515
2516 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2517 /*
2518 * FIXME this is racy. FBC might get enabled later.
2519 * What we should check here is whether FBC can be
2520 * enabled sometime later.
2521 */
7733b49b
PZ		 2522 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2523 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2524 for (level = 2; level <= max_level; level++) {
2525 struct intel_wm_level *wm = &merged->wm[level];
2526
2527 wm->enable = false;
2528 }
2529 }
0b2ae6d7
VS		 2530}
2531
b380ca3c
VS		 2532static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2533{
2534 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2535 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2536}
2537
a68d68ee
VS		 2538/* The value we need to program into the WM_LPx latency field */
2539static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2540{
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542
a42a5719 2543 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2544 return 2 * level;
2545 else
2546 return dev_priv->wm.pri_latency[level];
2547}
2548
820c1980 2549static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2550 const struct intel_pipe_wm *merged,
609cedef 2551 enum intel_ddb_partitioning partitioning,
820c1980 2552 struct ilk_wm_values *results)
801bcfff 2553{
0b2ae6d7
VS		 2554 struct intel_crtc *intel_crtc;
2555 int level, wm_lp;
cca32e9a 2556
0362c781 2557 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2558 results->partitioning = partitioning;
cca32e9a 2559
0b2ae6d7 2560 /* LP1+ register values */
cca32e9a 2561 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2562 const struct intel_wm_level *r;
801bcfff 2563
b380ca3c 2564 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2565
0362c781 2566 r = &merged->wm[level];
cca32e9a 2567
d52fea5b
VS		 2568 /*
2569 * Maintain the watermark values even if the level is
2570 * disabled. Doing otherwise could cause underruns.
2571 */
2572 results->wm_lp[wm_lp - 1] =
a68d68ee 2573 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2574 (r->pri_val << WM1_LP_SR_SHIFT) |
2575 r->cur_val;
2576
d52fea5b
VS		 2577 if (r->enable)
2578 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2579
416f4727
VS		 2580 if (INTEL_INFO(dev)->gen >= 8)
2581 results->wm_lp[wm_lp - 1] |=
2582 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2583 else
2584 results->wm_lp[wm_lp - 1] |=
2585 r->fbc_val << WM1_LP_FBC_SHIFT;
2586
d52fea5b
VS		 2587 /*
2588 * Always set WM1S_LP_EN when spr_val != 0, even if the
2589 * level is disabled. Doing otherwise could cause underruns.
2590 */
6cef2b8a
VS		 2591 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2592 WARN_ON(wm_lp != 1);
2593 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2594 } else
2595 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2596 }
801bcfff 2597
0b2ae6d7 2598 /* LP0 register values */
d3fcc808 2599 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2600 enum pipe pipe = intel_crtc->pipe;
2601 const struct intel_wm_level *r =
2602 &intel_crtc->wm.active.wm[0];
2603
2604 if (WARN_ON(!r->enable))
2605 continue;
2606
2607 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2608
0b2ae6d7
VS		 2609 results->wm_pipe[pipe] =
2610 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2611 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2612 r->cur_val;
801bcfff
PZ		 2613 }
2614}
2615
861f3389
PZ		 2616/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2617 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2618static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2619 struct intel_pipe_wm *r1,
2620 struct intel_pipe_wm *r2)
861f3389 2621{
198a1e9b
VS		 2622 int level, max_level = ilk_wm_max_level(dev);
2623 int level1 = 0, level2 = 0;
861f3389 2624
198a1e9b
VS		 2625 for (level = 1; level <= max_level; level++) {
2626 if (r1->wm[level].enable)
2627 level1 = level;
2628 if (r2->wm[level].enable)
2629 level2 = level;
861f3389
PZ		 2630 }
2631
198a1e9b
VS		 2632 if (level1 == level2) {
2633 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2634 return r2;
2635 else
2636 return r1;
198a1e9b 2637 } else if (level1 > level2) {
861f3389
PZ		 2638 return r1;
2639 } else {
2640 return r2;
2641 }
2642}
2643
49a687c4
VS		 2644/* dirty bits used to track which watermarks need changes */
2645#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2646#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2647#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2648#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2649#define WM_DIRTY_FBC (1 << 24)
2650#define WM_DIRTY_DDB (1 << 25)
2651
055e393f 2652static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2653 const struct ilk_wm_values *old,
2654 const struct ilk_wm_values *new)
49a687c4
VS		 2655{
2656 unsigned int dirty = 0;
2657 enum pipe pipe;
2658 int wm_lp;
2659
055e393f 2660 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2661 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2662 dirty |= WM_DIRTY_LINETIME(pipe);
2663 /* Must disable LP1+ watermarks too */
2664 dirty |= WM_DIRTY_LP_ALL;
2665 }
2666
2667 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2668 dirty |= WM_DIRTY_PIPE(pipe);
2669 /* Must disable LP1+ watermarks too */
2670 dirty |= WM_DIRTY_LP_ALL;
2671 }
2672 }
2673
2674 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2675 dirty |= WM_DIRTY_FBC;
2676 /* Must disable LP1+ watermarks too */
2677 dirty |= WM_DIRTY_LP_ALL;
2678 }
2679
2680 if (old->partitioning != new->partitioning) {
2681 dirty |= WM_DIRTY_DDB;
2682 /* Must disable LP1+ watermarks too */
2683 dirty |= WM_DIRTY_LP_ALL;
2684 }
2685
2686 /* LP1+ watermarks already deemed dirty, no need to continue */
2687 if (dirty & WM_DIRTY_LP_ALL)
2688 return dirty;
2689
2690 /* Find the lowest numbered LP1+ watermark in need of an update... */
2691 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2692 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2693 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2694 break;
2695 }
2696
2697 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2698 for (; wm_lp <= 3; wm_lp++)
2699 dirty |= WM_DIRTY_LP(wm_lp);
2700
2701 return dirty;
2702}
2703
8553c18e
VS		 2704static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2705 unsigned int dirty)
801bcfff 2706{
820c1980 2707 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2708 bool changed = false;
801bcfff 2709
facd619b
VS		 2710 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2711 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2712 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2713 changed = true;
facd619b
VS		 2714 }
2715 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2716 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2717 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2718 changed = true;
facd619b
VS		 2719 }
2720 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2721 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2722 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2723 changed = true;
facd619b 2724 }
801bcfff 2725
facd619b
VS		 2726 /*
2727 * Don't touch WM1S_LP_EN here.
2728 * Doing so could cause underruns.
2729 */
6cef2b8a 2730
8553c18e
VS		 2731 return changed;
2732}
2733
2734/*
2735 * The spec says we shouldn't write when we don't need, because every write
2736 * causes WMs to be re-evaluated, expending some power.
2737 */
820c1980
ID		 2738static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2739 struct ilk_wm_values *results)
8553c18e
VS		 2740{
2741 struct drm_device *dev = dev_priv->dev;
820c1980 2742 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2743 unsigned int dirty;
2744 uint32_t val;
2745
055e393f 2746 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2747 if (!dirty)
2748 return;
2749
2750 _ilk_disable_lp_wm(dev_priv, dirty);
2751
49a687c4 2752 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2753 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2754 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2755 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2756 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2757 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2758
49a687c4 2759 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2761 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2763 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2764 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2765
49a687c4 2766 if (dirty & WM_DIRTY_DDB) {
a42a5719 2767 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2768 val = I915_READ(WM_MISC);
2769 if (results->partitioning == INTEL_DDB_PART_1_2)
2770 val &= ~WM_MISC_DATA_PARTITION_5_6;
2771 else
2772 val |= WM_MISC_DATA_PARTITION_5_6;
2773 I915_WRITE(WM_MISC, val);
2774 } else {
2775 val = I915_READ(DISP_ARB_CTL2);
2776 if (results->partitioning == INTEL_DDB_PART_1_2)
2777 val &= ~DISP_DATA_PARTITION_5_6;
2778 else
2779 val |= DISP_DATA_PARTITION_5_6;
2780 I915_WRITE(DISP_ARB_CTL2, val);
2781 }
1011d8c4
PZ		 2782 }
2783
49a687c4 2784 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2785 val = I915_READ(DISP_ARB_CTL);
2786 if (results->enable_fbc_wm)
2787 val &= ~DISP_FBC_WM_DIS;
2788 else
2789 val |= DISP_FBC_WM_DIS;
2790 I915_WRITE(DISP_ARB_CTL, val);
2791 }
2792
954911eb
ID		 2793 if (dirty & WM_DIRTY_LP(1) &&
2794 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2795 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2796
2797 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2798 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2799 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2800 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2801 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2802 }
801bcfff 2803
facd619b 2804 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2805 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2806 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2807 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2808 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2809 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2810
2811 dev_priv->wm.hw = *results;
801bcfff
PZ		 2812}
2813
8553c18e
VS		 2814static bool ilk_disable_lp_wm(struct drm_device *dev)
2815{
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2817
2818 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2819}
2820
b9cec075
DL		 2821/*
2822 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2823 * different active planes.
2824 */
2825
2826#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2827#define BXT_DDB_SIZE 512
b9cec075
DL		 2828
2829static void
2830skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2831 struct drm_crtc *for_crtc,
2832 const struct intel_wm_config *config,
2833 const struct skl_pipe_wm_parameters *params,
2834 struct skl_ddb_entry *alloc /* out */)
2835{
2836 struct drm_crtc *crtc;
2837 unsigned int pipe_size, ddb_size;
2838 int nth_active_pipe;
2839
2840 if (!params->active) {
2841 alloc->start = 0;
2842 alloc->end = 0;
2843 return;
2844 }
2845
43d735a6
DL		 2846 if (IS_BROXTON(dev))
2847 ddb_size = BXT_DDB_SIZE;
2848 else
2849 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2850
2851 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2852
2853 nth_active_pipe = 0;
2854 for_each_crtc(dev, crtc) {
3ef00284 2855 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2856 continue;
2857
2858 if (crtc == for_crtc)
2859 break;
2860
2861 nth_active_pipe++;
2862 }
2863
2864 pipe_size = ddb_size / config->num_pipes_active;
2865 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2866 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2867}
2868
2869static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2870{
2871 if (config->num_pipes_active == 1)
2872 return 32;
2873
2874 return 8;
2875}
2876
a269c583
DL		 2877static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2878{
2879 entry->start = reg & 0x3ff;
2880 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2881 if (entry->end)
2882 entry->end += 1;
a269c583
DL		 2883}
2884
08db6652
DL		 2885void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2886 struct skl_ddb_allocation *ddb /* out */)
a269c583 2887{
a269c583
DL		 2888 enum pipe pipe;
2889 int plane;
2890 u32 val;
2891
2892 for_each_pipe(dev_priv, pipe) {
dd740780 2893 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2894 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2895 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2896 val);
2897 }
2898
2899 val = I915_READ(CUR_BUF_CFG(pipe));
2900 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2901 }
2902}
2903
b9cec075 2904static unsigned int
2cd601c6 2905skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2906{
2cd601c6
CK		 2907
2908 /* for planar format */
2909 if (p->y_bytes_per_pixel) {
2910 if (y) /* y-plane data rate */
2911 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2912 else /* uv-plane data rate */
2913 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2914 }
2915
2916 /* for packed formats */
b9cec075
DL		 2917 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2918}
2919
2920/*
2921 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2922 * a 8192x4096@32bpp framebuffer:
2923 * 3 * 4096 * 8192 * 4 < 2^32
2924 */
2925static unsigned int
2926skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2927 const struct skl_pipe_wm_parameters *params)
2928{
2929 unsigned int total_data_rate = 0;
2930 int plane;
2931
2932 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2933 const struct intel_plane_wm_parameters *p;
2934
2935 p = &params->plane[plane];
2936 if (!p->enabled)
2937 continue;
2938
2cd601c6
CK		 2939 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2940 if (p->y_bytes_per_pixel) {
2941 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2942 }
b9cec075
DL		 2943 }
2944
2945 return total_data_rate;
2946}
2947
2948static void
2949skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2950 const struct intel_wm_config *config,
2951 const struct skl_pipe_wm_parameters *params,
2952 struct skl_ddb_allocation *ddb /* out */)
2953{
2954 struct drm_device *dev = crtc->dev;
dd740780 2955 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2957 enum pipe pipe = intel_crtc->pipe;
34bb56af 2958 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2959 uint16_t alloc_size, start, cursor_blocks;
80958155 2960 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2961 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2962 unsigned int total_data_rate;
2963 int plane;
2964
34bb56af
DL		 2965 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2966 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2967 if (alloc_size == 0) {
2968 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2969 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2970 return;
2971 }
2972
2973 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2974 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2975 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2976
2977 alloc_size -= cursor_blocks;
34bb56af 2978 alloc->end -= cursor_blocks;
b9cec075 2979
80958155 2980 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2981 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2982 const struct intel_plane_wm_parameters *p;
2983
2984 p = &params->plane[plane];
2985 if (!p->enabled)
2986 continue;
2987
2988 minimum[plane] = 8;
2989 alloc_size -= minimum[plane];
2cd601c6
CK		 2990 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2991 alloc_size -= y_minimum[plane];
80958155
DL		 2992 }
2993
b9cec075 2994 /*
80958155
DL		 2995 * 2. Distribute the remaining space in proportion to the amount of
2996 * data each plane needs to fetch from memory.
b9cec075
DL		 2997 *
2998 * FIXME: we may not allocate every single block here.
2999 */
3000 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3001
34bb56af 3002 start = alloc->start;
b9cec075
DL		 3003 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3004 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 3005 unsigned int data_rate, y_data_rate;
3006 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 3007
3008 p = &params->plane[plane];
3009 if (!p->enabled)
3010 continue;
3011
2cd601c6 3012 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 3013
3014 /*
2cd601c6 3015 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3016 * promote the expression to 64 bits to avoid overflowing, the
3017 * result is < available as data_rate / total_data_rate < 1
3018 */
80958155
DL		 3019 plane_blocks = minimum[plane];
3020 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3021 total_data_rate);
b9cec075
DL		 3022
3023 ddb->plane[pipe][plane].start = start;
16160e3d 3024 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3025
3026 start += plane_blocks;
2cd601c6
CK		 3027
3028 /*
3029 * allocation for y_plane part of planar format:
3030 */
3031 if (p->y_bytes_per_pixel) {
3032 y_data_rate = skl_plane_relative_data_rate(p, 1);
3033 y_plane_blocks = y_minimum[plane];
3034 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3035 total_data_rate);
3036
3037 ddb->y_plane[pipe][plane].start = start;
3038 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3039
3040 start += y_plane_blocks;
3041 }
3042
b9cec075
DL		 3043 }
3044
3045}
3046
5cec258b 3047static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3048{
3049 /* TODO: Take into account the scalers once we support them */
2d112de7 3050 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3051}
3052
3053/*
3054 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3055 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3056 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3057 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3058*/
3059static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3060 uint32_t latency)
3061{
3062 uint32_t wm_intermediate_val, ret;
3063
3064 if (latency == 0)
3065 return UINT_MAX;
3066
d4c2aa60 3067 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3068 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3069
3070 return ret;
3071}
3072
3073static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3074 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3075 uint64_t tiling, uint32_t latency)
2d41c0b5 3076{
d4c2aa60
TU		 3077 uint32_t ret;
3078 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3079 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3080
3081 if (latency == 0)
3082 return UINT_MAX;
3083
3084 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3085
3086 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3087 tiling == I915_FORMAT_MOD_Yf_TILED) {
3088 plane_bytes_per_line *= 4;
3089 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3090 plane_blocks_per_line /= 4;
3091 } else {
3092 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3093 }
3094
2d41c0b5
PB		 3095 wm_intermediate_val = latency * pixel_rate;
3096 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3097 plane_blocks_per_line;
2d41c0b5
PB		 3098
3099 return ret;
3100}
3101
2d41c0b5
PB		 3102static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3103 const struct intel_crtc *intel_crtc)
3104{
3105 struct drm_device *dev = intel_crtc->base.dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3108 enum pipe pipe = intel_crtc->pipe;
3109
3110 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3111 sizeof(new_ddb->plane[pipe])))
3112 return true;
3113
3114 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3115 sizeof(new_ddb->cursor[pipe])))
3116 return true;
3117
3118 return false;
3119}
3120
3121static void skl_compute_wm_global_parameters(struct drm_device *dev,
3122 struct intel_wm_config *config)
3123{
3124 struct drm_crtc *crtc;
3125 struct drm_plane *plane;
3126
3127 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 3128 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 3129
3130 /* FIXME: I don't think we need those two global parameters on SKL */
3131 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3132 struct intel_plane *intel_plane = to_intel_plane(plane);
3133
3134 config->sprites_enabled |= intel_plane->wm.enabled;
3135 config->sprites_scaled |= intel_plane->wm.scaled;
3136 }
3137}
3138
3139static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3140 struct skl_pipe_wm_parameters *p)
3141{
3142 struct drm_device *dev = crtc->dev;
3143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3144 enum pipe pipe = intel_crtc->pipe;
3145 struct drm_plane *plane;
0fda6568 3146 struct drm_framebuffer *fb;
2d41c0b5
PB		 3147 int i = 1; /* Index for sprite planes start */
3148
3ef00284 3149 p->active = intel_crtc->active;
2d41c0b5 3150 if (p->active) {
6e3c9717
ACO		 3151 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3152 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 3153
0fda6568 3154 fb = crtc->primary->state->fb;
2cd601c6 3155 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 3156 if (fb) {
3157 p->plane[0].enabled = true;
2cd601c6 3158 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
395ab754
KM		 3159 drm_format_plane_cpp(fb->pixel_format, 1) :
3160 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6
CK		 3161 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3162 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 3163 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 3164 } else {
3165 p->plane[0].enabled = false;
3166 p->plane[0].bytes_per_pixel = 0;
2cd601c6 3167 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 3168 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3169 }
3170 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3171 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 3172 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 3173
c9f038a1 3174 fb = crtc->cursor->state->fb;
2cd601c6 3175 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 3176 if (fb) {
3177 p->cursor.enabled = true;
3178 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3179 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3180 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3181 } else {
3182 p->cursor.enabled = false;
3183 p->cursor.bytes_per_pixel = 0;
3184 p->cursor.horiz_pixels = 64;
3185 p->cursor.vert_pixels = 64;
3186 }
2d41c0b5
PB		 3187 }
3188
3189 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3190 struct intel_plane *intel_plane = to_intel_plane(plane);
3191
a712f8eb
SJ		 3192 if (intel_plane->pipe == pipe &&
3193 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 3194 p->plane[i++] = intel_plane->wm;
3195 }
3196}
3197
d4c2aa60
TU		 3198static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3199 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 3200 struct intel_plane_wm_parameters *p_params,
3201 uint16_t ddb_allocation,
d4c2aa60 3202 int level,
afb024aa
DL		 3203 uint16_t *out_blocks, /* out */
3204 uint8_t *out_lines /* out */)
2d41c0b5 3205{
d4c2aa60
TU		 3206 uint32_t latency = dev_priv->wm.skl_latency[level];
3207 uint32_t method1, method2;
3208 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3209 uint32_t res_blocks, res_lines;
3210 uint32_t selected_result;
2cd601c6 3211 uint8_t bytes_per_pixel;
2d41c0b5 3212
d4c2aa60 3213 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3214 return false;
3215
2cd601c6
CK		 3216 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3217 p_params->y_bytes_per_pixel :
3218 p_params->bytes_per_pixel;
2d41c0b5 3219 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 3220 bytes_per_pixel,
d4c2aa60 3221 latency);
2d41c0b5
PB		 3222 method2 = skl_wm_method2(p->pixel_rate,
3223 p->pipe_htotal,
3224 p_params->horiz_pixels,
2cd601c6 3225 bytes_per_pixel,
0fda6568 3226 p_params->tiling,
d4c2aa60 3227 latency);
2d41c0b5 3228
2cd601c6 3229 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 3230 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3231
0fda6568
TU		 3232 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3233 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3234 uint32_t min_scanlines = 4;
3235 uint32_t y_tile_minimum;
3236 if (intel_rotation_90_or_270(p_params->rotation)) {
3237 switch (p_params->bytes_per_pixel) {
3238 case 1:
3239 min_scanlines = 16;
3240 break;
3241 case 2:
3242 min_scanlines = 8;
3243 break;
3244 case 8:
3245 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3246 }
1fc0a8f7
TU		 3247 }
3248 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3249 selected_result = max(method2, y_tile_minimum);
3250 } else {
3251 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3252 selected_result = min(method1, method2);
3253 else
3254 selected_result = method1;
3255 }
2d41c0b5 3256
d4c2aa60
TU		 3257 res_blocks = selected_result + 1;
3258 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3259
0fda6568
TU		 3260 if (level >= 1 && level <= 7) {
3261 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3262 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3263 res_lines += 4;
3264 else
3265 res_blocks++;
3266 }
e6d66171 3267
d4c2aa60 3268 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3269 return false;
3270
3271 *out_blocks = res_blocks;
3272 *out_lines = res_lines;
2d41c0b5
PB		 3273
3274 return true;
3275}
3276
3277static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3278 struct skl_ddb_allocation *ddb,
3279 struct skl_pipe_wm_parameters *p,
3280 enum pipe pipe,
3281 int level,
3282 int num_planes,
3283 struct skl_wm_level *result)
3284{
2d41c0b5
PB		 3285 uint16_t ddb_blocks;
3286 int i;
3287
3288 for (i = 0; i < num_planes; i++) {
3289 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3290
d4c2aa60
TU		 3291 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3292 p, &p->plane[i],
2d41c0b5 3293 ddb_blocks,
d4c2aa60 3294 level,
2d41c0b5
PB		 3295 &result->plane_res_b[i],
3296 &result->plane_res_l[i]);
3297 }
3298
3299 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3300 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3301 ddb_blocks, level,
3302 &result->cursor_res_b,
2d41c0b5
PB		 3303 &result->cursor_res_l);
3304}
3305
407b50f3
DL		 3306static uint32_t
3307skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3308{
3ef00284 3309 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3310 return 0;
3311
661abfc0
MK		 3312 if (WARN_ON(p->pixel_rate == 0))
3313 return 0;
407b50f3 3314
661abfc0 3315 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
407b50f3
DL		 3316}
3317
3318static void skl_compute_transition_wm(struct drm_crtc *crtc,
3319 struct skl_pipe_wm_parameters *params,
9414f563 3320 struct skl_wm_level *trans_wm /* out */)
407b50f3 3321{
9414f563
DL		 3322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323 int i;
3324
407b50f3
DL		 3325 if (!params->active)
3326 return;
9414f563
DL		 3327
3328 /* Until we know more, just disable transition WMs */
3329 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3330 trans_wm->plane_en[i] = false;
3331 trans_wm->cursor_en = false;
407b50f3
DL		 3332}
3333
2d41c0b5
PB		 3334static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3335 struct skl_ddb_allocation *ddb,
3336 struct skl_pipe_wm_parameters *params,
3337 struct skl_pipe_wm *pipe_wm)
3338{
3339 struct drm_device *dev = crtc->dev;
3340 const struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3342 int level, max_level = ilk_wm_max_level(dev);
3343
3344 for (level = 0; level <= max_level; level++) {
3345 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3346 level, intel_num_planes(intel_crtc),
3347 &pipe_wm->wm[level]);
3348 }
3349 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3350
9414f563 3351 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3352}
3353
3354static void skl_compute_wm_results(struct drm_device *dev,
3355 struct skl_pipe_wm_parameters *p,
3356 struct skl_pipe_wm *p_wm,
3357 struct skl_wm_values *r,
3358 struct intel_crtc *intel_crtc)
3359{
3360 int level, max_level = ilk_wm_max_level(dev);
3361 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3362 uint32_t temp;
3363 int i;
2d41c0b5
PB		 3364
3365 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3366 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3367 temp = 0;
2d41c0b5
PB		 3368
3369 temp |= p_wm->wm[level].plane_res_l[i] <<
3370 PLANE_WM_LINES_SHIFT;
3371 temp |= p_wm->wm[level].plane_res_b[i];
3372 if (p_wm->wm[level].plane_en[i])
3373 temp |= PLANE_WM_EN;
3374
3375 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3376 }
3377
3378 temp = 0;
2d41c0b5
PB		 3379
3380 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3381 temp |= p_wm->wm[level].cursor_res_b;
3382
3383 if (p_wm->wm[level].cursor_en)
3384 temp |= PLANE_WM_EN;
3385
3386 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3387
3388 }
3389
9414f563
DL		 3390 /* transition WMs */
3391 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3392 temp = 0;
3393 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3394 temp |= p_wm->trans_wm.plane_res_b[i];
3395 if (p_wm->trans_wm.plane_en[i])
3396 temp |= PLANE_WM_EN;
3397
3398 r->plane_trans[pipe][i] = temp;
3399 }
3400
3401 temp = 0;
3402 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3403 temp |= p_wm->trans_wm.cursor_res_b;
3404 if (p_wm->trans_wm.cursor_en)
3405 temp |= PLANE_WM_EN;
3406
3407 r->cursor_trans[pipe] = temp;
3408
2d41c0b5
PB		 3409 r->wm_linetime[pipe] = p_wm->linetime;
3410}
3411
16160e3d
DL		 3412static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3413 const struct skl_ddb_entry *entry)
3414{
3415 if (entry->end)
3416 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3417 else
3418 I915_WRITE(reg, 0);
3419}
3420
2d41c0b5
PB		 3421static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3422 const struct skl_wm_values *new)
3423{
3424 struct drm_device *dev = dev_priv->dev;
3425 struct intel_crtc *crtc;
3426
3427 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3428 int i, level, max_level = ilk_wm_max_level(dev);
3429 enum pipe pipe = crtc->pipe;
3430
5d374d96
DL		 3431 if (!new->dirty[pipe])
3432 continue;
8211bd5b 3433
5d374d96 3434 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3435
5d374d96
DL		 3436 for (level = 0; level <= max_level; level++) {
3437 for (i = 0; i < intel_num_planes(crtc); i++)
3438 I915_WRITE(PLANE_WM(pipe, i, level),
3439 new->plane[pipe][i][level]);
3440 I915_WRITE(CUR_WM(pipe, level),
3441 new->cursor[pipe][level]);
2d41c0b5 3442 }
5d374d96
DL		 3443 for (i = 0; i < intel_num_planes(crtc); i++)
3444 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3445 new->plane_trans[pipe][i]);
3446 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3447
2cd601c6 3448 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3449 skl_ddb_entry_write(dev_priv,
3450 PLANE_BUF_CFG(pipe, i),
3451 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3452 skl_ddb_entry_write(dev_priv,
3453 PLANE_NV12_BUF_CFG(pipe, i),
3454 &new->ddb.y_plane[pipe][i]);
3455 }
5d374d96
DL		 3456
3457 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3458 &new->ddb.cursor[pipe]);
2d41c0b5 3459 }
2d41c0b5
PB		 3460}
3461
0e8fb7ba
DL		 3462/*
3463 * When setting up a new DDB allocation arrangement, we need to correctly
3464 * sequence the times at which the new allocations for the pipes are taken into
3465 * account or we'll have pipes fetching from space previously allocated to
3466 * another pipe.
3467 *
3468 * Roughly the sequence looks like:
3469 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3470 * overlapping with a previous light-up pipe (another way to put it is:
3471 * pipes with their new allocation strickly included into their old ones).
3472 * 2. re-allocate the other pipes that get their allocation reduced
3473 * 3. allocate the pipes having their allocation increased
3474 *
3475 * Steps 1. and 2. are here to take care of the following case:
3476 * - Initially DDB looks like this:
3477 * | B | C |
3478 * - enable pipe A.
3479 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3480 * allocation
3481 * | A | B | C |
3482 *
3483 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3484 */
3485
d21b795c
DL		 3486static void
3487skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3488{
0e8fb7ba
DL		 3489 int plane;
3490
d21b795c
DL		 3491 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3492
dd740780 3493 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3494 I915_WRITE(PLANE_SURF(pipe, plane),
3495 I915_READ(PLANE_SURF(pipe, plane)));
3496 }
3497 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3498}
3499
3500static bool
3501skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3502 const struct skl_ddb_allocation *new,
3503 enum pipe pipe)
3504{
3505 uint16_t old_size, new_size;
3506
3507 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3508 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3509
3510 return old_size != new_size &&
3511 new->pipe[pipe].start >= old->pipe[pipe].start &&
3512 new->pipe[pipe].end <= old->pipe[pipe].end;
3513}
3514
3515static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3516 struct skl_wm_values *new_values)
3517{
3518 struct drm_device *dev = dev_priv->dev;
3519 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3520 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3521 struct intel_crtc *crtc;
3522 enum pipe pipe;
3523
3524 new_ddb = &new_values->ddb;
3525 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3526
3527 /*
3528 * First pass: flush the pipes with the new allocation contained into
3529 * the old space.
3530 *
3531 * We'll wait for the vblank on those pipes to ensure we can safely
3532 * re-allocate the freed space without this pipe fetching from it.
3533 */
3534 for_each_intel_crtc(dev, crtc) {
3535 if (!crtc->active)
3536 continue;
3537
3538 pipe = crtc->pipe;
3539
3540 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3541 continue;
3542
d21b795c 3543 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3544 intel_wait_for_vblank(dev, pipe);
3545
3546 reallocated[pipe] = true;
3547 }
3548
3549
3550 /*
3551 * Second pass: flush the pipes that are having their allocation
3552 * reduced, but overlapping with a previous allocation.
3553 *
3554 * Here as well we need to wait for the vblank to make sure the freed
3555 * space is not used anymore.
3556 */
3557 for_each_intel_crtc(dev, crtc) {
3558 if (!crtc->active)
3559 continue;
3560
3561 pipe = crtc->pipe;
3562
3563 if (reallocated[pipe])
3564 continue;
3565
3566 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3567 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3568 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3569 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3570 reallocated[pipe] = true;
0e8fb7ba 3571 }
0e8fb7ba
DL		 3572 }
3573
3574 /*
3575 * Third pass: flush the pipes that got more space allocated.
3576 *
3577 * We don't need to actively wait for the update here, next vblank
3578 * will just get more DDB space with the correct WM values.
3579 */
3580 for_each_intel_crtc(dev, crtc) {
3581 if (!crtc->active)
3582 continue;
3583
3584 pipe = crtc->pipe;
3585
3586 /*
3587 * At this point, only the pipes more space than before are
3588 * left to re-allocate.
3589 */
3590 if (reallocated[pipe])
3591 continue;
3592
d21b795c 3593 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3594 }
3595}
3596
2d41c0b5
PB		 3597static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3598 struct skl_pipe_wm_parameters *params,
3599 struct intel_wm_config *config,
3600 struct skl_ddb_allocation *ddb, /* out */
3601 struct skl_pipe_wm *pipe_wm /* out */)
3602{
3603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3604
3605 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3606 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3607 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3608
3609 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3610 return false;
3611
3612 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3613
2d41c0b5
PB		 3614 return true;
3615}
3616
3617static void skl_update_other_pipe_wm(struct drm_device *dev,
3618 struct drm_crtc *crtc,
3619 struct intel_wm_config *config,
3620 struct skl_wm_values *r)
3621{
3622 struct intel_crtc *intel_crtc;
3623 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3624
3625 /*
3626 * If the WM update hasn't changed the allocation for this_crtc (the
3627 * crtc we are currently computing the new WM values for), other
3628 * enabled crtcs will keep the same allocation and we don't need to
3629 * recompute anything for them.
3630 */
3631 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3632 return;
3633
3634 /*
3635 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3636 * other active pipes need new DDB allocation and WM values.
3637 */
3638 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3639 base.head) {
3640 struct skl_pipe_wm_parameters params = {};
3641 struct skl_pipe_wm pipe_wm = {};
3642 bool wm_changed;
3643
3644 if (this_crtc->pipe == intel_crtc->pipe)
3645 continue;
3646
3647 if (!intel_crtc->active)
3648 continue;
3649
3650 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3651 &params, config,
3652 &r->ddb, &pipe_wm);
3653
3654 /*
3655 * If we end up re-computing the other pipe WM values, it's
3656 * because it was really needed, so we expect the WM values to
3657 * be different.
3658 */
3659 WARN_ON(!wm_changed);
3660
3661 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3662 r->dirty[intel_crtc->pipe] = true;
3663 }
3664}
3665
adda50b8
BP		 3666static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3667{
3668 watermarks->wm_linetime[pipe] = 0;
3669 memset(watermarks->plane[pipe], 0,
3670 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3671 memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
3672 memset(watermarks->plane_trans[pipe],
3673 0, sizeof(uint32_t) * I915_MAX_PLANES);
3674 watermarks->cursor_trans[pipe] = 0;
3675
3676 /* Clear ddb entries for pipe */
3677 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3678 memset(&watermarks->ddb.plane[pipe], 0,
3679 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3680 memset(&watermarks->ddb.y_plane[pipe], 0,
3681 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3682 memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
3683
3684}
3685
2d41c0b5
PB		 3686static void skl_update_wm(struct drm_crtc *crtc)
3687{
3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3689 struct drm_device *dev = crtc->dev;
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 struct skl_pipe_wm_parameters params = {};
3692 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3693 struct skl_pipe_wm pipe_wm = {};
3694 struct intel_wm_config config = {};
3695
adda50b8
BP		 3696
3697 /* Clear all dirty flags */
3698 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3699
3700 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5
PB		 3701
3702 skl_compute_wm_global_parameters(dev, &config);
3703
3704 if (!skl_update_pipe_wm(crtc, &params, &config,
3705 &results->ddb, &pipe_wm))
3706 return;
3707
3708 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3709 results->dirty[intel_crtc->pipe] = true;
3710
3711 skl_update_other_pipe_wm(dev, crtc, &config, results);
3712 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3713 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3714
3715 /* store the new configuration */
3716 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3717}
3718
3719static void
3720skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3721 uint32_t sprite_width, uint32_t sprite_height,
3722 int pixel_size, bool enabled, bool scaled)
3723{
3724 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3725 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3726
3727 intel_plane->wm.enabled = enabled;
3728 intel_plane->wm.scaled = scaled;
3729 intel_plane->wm.horiz_pixels = sprite_width;
3730 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3731 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3732
3733 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3734 intel_plane->wm.bytes_per_pixel =
3735 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3736 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3737 intel_plane->wm.y_bytes_per_pixel =
3738 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3739 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3740
0fda6568
TU		 3741 /*
3742 * Framebuffer can be NULL on plane disable, but it does not
3743 * matter for watermarks if we assume no tiling in that case.
3744 */
3745 if (fb)
3746 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3747 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3748
3749 skl_update_wm(crtc);
3750}
3751
820c1980 3752static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3753{
7c4a395f 3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3755 struct drm_device *dev = crtc->dev;
801bcfff 3756 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3757 struct ilk_wm_maximums max;
3758 struct ilk_pipe_wm_parameters params = {};
3759 struct ilk_wm_values results = {};
77c122bc 3760 enum intel_ddb_partitioning partitioning;
7c4a395f 3761 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3762 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3763 struct intel_wm_config config = {};
7c4a395f 3764
2a44b76b 3765 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3766
3767 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3768
3769 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3770 return;
861f3389 3771
7c4a395f 3772 intel_crtc->wm.active = pipe_wm;
861f3389 3773
2a44b76b
VS		 3774 ilk_compute_wm_config(dev, &config);
3775
34982fe1 3776 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3777 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3778
3779 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3780 if (INTEL_INFO(dev)->gen >= 7 &&
3781 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3782 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3783 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3784
820c1980 3785 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3786 } else {
198a1e9b 3787 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3788 }
3789
198a1e9b 3790 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3791 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3792
820c1980 3793 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3794
820c1980 3795 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3796}
3797
ed57cb8a
DL		 3798static void
3799ilk_update_sprite_wm(struct drm_plane *plane,
3800 struct drm_crtc *crtc,
3801 uint32_t sprite_width, uint32_t sprite_height,
3802 int pixel_size, bool enabled, bool scaled)
526682e9 3803{
8553c18e 3804 struct drm_device *dev = plane->dev;
adf3d35e 3805 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3806
adf3d35e
VS		 3807 intel_plane->wm.enabled = enabled;
3808 intel_plane->wm.scaled = scaled;
3809 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3810 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3811 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3812
8553c18e
VS		 3813 /*
3814 * IVB workaround: must disable low power watermarks for at least
3815 * one frame before enabling scaling. LP watermarks can be re-enabled
3816 * when scaling is disabled.
3817 *
3818 * WaCxSRDisabledForSpriteScaling:ivb
3819 */
3820 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3821 intel_wait_for_vblank(dev, intel_plane->pipe);
3822
820c1980 3823 ilk_update_wm(crtc);
526682e9
PZ		 3824}
3825
3078999f
PB		 3826static void skl_pipe_wm_active_state(uint32_t val,
3827 struct skl_pipe_wm *active,
3828 bool is_transwm,
3829 bool is_cursor,
3830 int i,
3831 int level)
3832{
3833 bool is_enabled = (val & PLANE_WM_EN) != 0;
3834
3835 if (!is_transwm) {
3836 if (!is_cursor) {
3837 active->wm[level].plane_en[i] = is_enabled;
3838 active->wm[level].plane_res_b[i] =
3839 val & PLANE_WM_BLOCKS_MASK;
3840 active->wm[level].plane_res_l[i] =
3841 (val >> PLANE_WM_LINES_SHIFT) &
3842 PLANE_WM_LINES_MASK;
3843 } else {
3844 active->wm[level].cursor_en = is_enabled;
3845 active->wm[level].cursor_res_b =
3846 val & PLANE_WM_BLOCKS_MASK;
3847 active->wm[level].cursor_res_l =
3848 (val >> PLANE_WM_LINES_SHIFT) &
3849 PLANE_WM_LINES_MASK;
3850 }
3851 } else {
3852 if (!is_cursor) {
3853 active->trans_wm.plane_en[i] = is_enabled;
3854 active->trans_wm.plane_res_b[i] =
3855 val & PLANE_WM_BLOCKS_MASK;
3856 active->trans_wm.plane_res_l[i] =
3857 (val >> PLANE_WM_LINES_SHIFT) &
3858 PLANE_WM_LINES_MASK;
3859 } else {
3860 active->trans_wm.cursor_en = is_enabled;
3861 active->trans_wm.cursor_res_b =
3862 val & PLANE_WM_BLOCKS_MASK;
3863 active->trans_wm.cursor_res_l =
3864 (val >> PLANE_WM_LINES_SHIFT) &
3865 PLANE_WM_LINES_MASK;
3866 }
3867 }
3868}
3869
3870static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3871{
3872 struct drm_device *dev = crtc->dev;
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3876 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3877 enum pipe pipe = intel_crtc->pipe;
3878 int level, i, max_level;
3879 uint32_t temp;
3880
3881 max_level = ilk_wm_max_level(dev);
3882
3883 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3884
3885 for (level = 0; level <= max_level; level++) {
3886 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3887 hw->plane[pipe][i][level] =
3888 I915_READ(PLANE_WM(pipe, i, level));
3889 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3890 }
3891
3892 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3893 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3894 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3895
3ef00284 3896 if (!intel_crtc->active)
3078999f
PB		 3897 return;
3898
3899 hw->dirty[pipe] = true;
3900
3901 active->linetime = hw->wm_linetime[pipe];
3902
3903 for (level = 0; level <= max_level; level++) {
3904 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3905 temp = hw->plane[pipe][i][level];
3906 skl_pipe_wm_active_state(temp, active, false,
3907 false, i, level);
3908 }
3909 temp = hw->cursor[pipe][level];
3910 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3911 }
3912
3913 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3914 temp = hw->plane_trans[pipe][i];
3915 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3916 }
3917
3918 temp = hw->cursor_trans[pipe];
3919 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3920}
3921
3922void skl_wm_get_hw_state(struct drm_device *dev)
3923{
a269c583
DL		 3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3926 struct drm_crtc *crtc;
3927
a269c583 3928 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3929 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3930 skl_pipe_wm_get_hw_state(crtc);
3931}
3932
243e6a44
VS		 3933static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3934{
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3937 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3939 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3940 enum pipe pipe = intel_crtc->pipe;
3941 static const unsigned int wm0_pipe_reg[] = {
3942 [PIPE_A] = WM0_PIPEA_ILK,
3943 [PIPE_B] = WM0_PIPEB_ILK,
3944 [PIPE_C] = WM0_PIPEC_IVB,
3945 };
3946
3947 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3948 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3949 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3950
3ef00284 3951 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3952
3953 if (active->pipe_enabled) {
243e6a44
VS		 3954 u32 tmp = hw->wm_pipe[pipe];
3955
3956 /*
3957 * For active pipes LP0 watermark is marked as
3958 * enabled, and LP1+ watermaks as disabled since
3959 * we can't really reverse compute them in case
3960 * multiple pipes are active.
3961 */
3962 active->wm[0].enable = true;
3963 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3964 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3965 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3966 active->linetime = hw->wm_linetime[pipe];
3967 } else {
3968 int level, max_level = ilk_wm_max_level(dev);
3969
3970 /*
3971 * For inactive pipes, all watermark levels
3972 * should be marked as enabled but zeroed,
3973 * which is what we'd compute them to.
3974 */
3975 for (level = 0; level <= max_level; level++)
3976 active->wm[level].enable = true;
3977 }
3978}
3979
6eb1a681
VS		 3980#define _FW_WM(value, plane) \
3981 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3982#define _FW_WM_VLV(value, plane) \
3983 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3984
3985static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3986 struct vlv_wm_values *wm)
3987{
3988 enum pipe pipe;
3989 uint32_t tmp;
3990
3991 for_each_pipe(dev_priv, pipe) {
3992 tmp = I915_READ(VLV_DDL(pipe));
3993
3994 wm->ddl[pipe].primary =
3995 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3996 wm->ddl[pipe].cursor =
3997 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3998 wm->ddl[pipe].sprite[0] =
3999 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4000 wm->ddl[pipe].sprite[1] =
4001 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4002 }
4003
4004 tmp = I915_READ(DSPFW1);
4005 wm->sr.plane = _FW_WM(tmp, SR);
4006 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4007 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4008 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4009
4010 tmp = I915_READ(DSPFW2);
4011 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4012 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4013 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4014
4015 tmp = I915_READ(DSPFW3);
4016 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4017
4018 if (IS_CHERRYVIEW(dev_priv)) {
4019 tmp = I915_READ(DSPFW7_CHV);
4020 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4021 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4022
4023 tmp = I915_READ(DSPFW8_CHV);
4024 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4025 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4026
4027 tmp = I915_READ(DSPFW9_CHV);
4028 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4029 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4030
4031 tmp = I915_READ(DSPHOWM);
4032 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4033 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4034 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4035 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4036 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4037 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4038 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4039 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4040 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4041 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4042 } else {
4043 tmp = I915_READ(DSPFW7);
4044 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4045 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4046
4047 tmp = I915_READ(DSPHOWM);
4048 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4049 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4050 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4051 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4052 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4053 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4054 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4055 }
4056}
4057
4058#undef _FW_WM
4059#undef _FW_WM_VLV
4060
4061void vlv_wm_get_hw_state(struct drm_device *dev)
4062{
4063 struct drm_i915_private *dev_priv = to_i915(dev);
4064 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4065 struct intel_plane *plane;
4066 enum pipe pipe;
4067 u32 val;
4068
4069 vlv_read_wm_values(dev_priv, wm);
4070
4071 for_each_intel_plane(dev, plane) {
4072 switch (plane->base.type) {
4073 int sprite;
4074 case DRM_PLANE_TYPE_CURSOR:
4075 plane->wm.fifo_size = 63;
4076 break;
4077 case DRM_PLANE_TYPE_PRIMARY:
4078 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4079 break;
4080 case DRM_PLANE_TYPE_OVERLAY:
4081 sprite = plane->plane;
4082 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4083 break;
4084 }
4085 }
4086
4087 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4088 wm->level = VLV_WM_LEVEL_PM2;
4089
4090 if (IS_CHERRYVIEW(dev_priv)) {
4091 mutex_lock(&dev_priv->rps.hw_lock);
4092
4093 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4094 if (val & DSP_MAXFIFO_PM5_ENABLE)
4095 wm->level = VLV_WM_LEVEL_PM5;
4096
58590c14
VS		 4097 /*
4098 * If DDR DVFS is disabled in the BIOS, Punit
4099 * will never ack the request. So if that happens
4100 * assume we don't have to enable/disable DDR DVFS
4101 * dynamically. To test that just set the REQ_ACK
4102 * bit to poke the Punit, but don't change the
4103 * HIGH/LOW bits so that we don't actually change
4104 * the current state.
4105 */
6eb1a681 4106 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4107 val |= FORCE_DDR_FREQ_REQ_ACK;
4108 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4109
4110 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4111 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4112 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4113 "assuming DDR DVFS is disabled\n");
4114 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4115 } else {
4116 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4117 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4118 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4119 }
6eb1a681
VS		 4120
4121 mutex_unlock(&dev_priv->rps.hw_lock);
4122 }
4123
4124 for_each_pipe(dev_priv, pipe)
4125 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4126 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4127 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4128
4129 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4130 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4131}
4132
243e6a44
VS		 4133void ilk_wm_get_hw_state(struct drm_device *dev)
4134{
4135 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4136 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4137 struct drm_crtc *crtc;
4138
70e1e0ec 4139 for_each_crtc(dev, crtc)
243e6a44
VS		 4140 ilk_pipe_wm_get_hw_state(crtc);
4141
4142 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4143 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4144 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4145
4146 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4147 if (INTEL_INFO(dev)->gen >= 7) {
4148 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4149 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4150 }
243e6a44 4151
a42a5719 4152 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4153 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4154 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4155 else if (IS_IVYBRIDGE(dev))
4156 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4157 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4158
4159 hw->enable_fbc_wm =
4160 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4161}
4162
b445e3b0
ED		 4163/**
4164 * intel_update_watermarks - update FIFO watermark values based on current modes
4165 *
4166 * Calculate watermark values for the various WM regs based on current mode
4167 * and plane configuration.
4168 *
4169 * There are several cases to deal with here:
4170 * - normal (i.e. non-self-refresh)
4171 * - self-refresh (SR) mode
4172 * - lines are large relative to FIFO size (buffer can hold up to 2)
4173 * - lines are small relative to FIFO size (buffer can hold more than 2
4174 * lines), so need to account for TLB latency
4175 *
4176 * The normal calculation is:
4177 * watermark = dotclock * bytes per pixel * latency
4178 * where latency is platform & configuration dependent (we assume pessimal
4179 * values here).
4180 *
4181 * The SR calculation is:
4182 * watermark = (trunc(latency/line time)+1) * surface width *
4183 * bytes per pixel
4184 * where
4185 * line time = htotal / dotclock
4186 * surface width = hdisplay for normal plane and 64 for cursor
4187 * and latency is assumed to be high, as above.
4188 *
4189 * The final value programmed to the register should always be rounded up,
4190 * and include an extra 2 entries to account for clock crossings.
4191 *
4192 * We don't use the sprite, so we can ignore that. And on Crestline we have
4193 * to set the non-SR watermarks to 8.
4194 */
46ba614c 4195void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4196{
46ba614c 4197 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4198
4199 if (dev_priv->display.update_wm)
46ba614c 4200 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4201}
4202
adf3d35e
VS		 4203void intel_update_sprite_watermarks(struct drm_plane *plane,
4204 struct drm_crtc *crtc,
ed57cb8a
DL		 4205 uint32_t sprite_width,
4206 uint32_t sprite_height,
4207 int pixel_size,
39db4a4d 4208 bool enabled, bool scaled)
b445e3b0 4209{
adf3d35e 4210 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 4211
4212 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 4213 dev_priv->display.update_sprite_wm(plane, crtc,
4214 sprite_width, sprite_height,
39db4a4d 4215 pixel_size, enabled, scaled);
b445e3b0
ED		 4216}
4217
9270388e
DV		 4218/**
4219 * Lock protecting IPS related data structures
9270388e
DV		 4220 */
4221DEFINE_SPINLOCK(mchdev_lock);
4222
4223/* Global for IPS driver to get at the current i915 device. Protected by
4224 * mchdev_lock. */
4225static struct drm_i915_private *i915_mch_dev;
4226
2b4e57bd
ED		 4227bool ironlake_set_drps(struct drm_device *dev, u8 val)
4228{
4229 struct drm_i915_private *dev_priv = dev->dev_private;
4230 u16 rgvswctl;
4231
9270388e
DV		 4232 assert_spin_locked(&mchdev_lock);
4233
2b4e57bd
ED		 4234 rgvswctl = I915_READ16(MEMSWCTL);
4235 if (rgvswctl & MEMCTL_CMD_STS) {
4236 DRM_DEBUG("gpu busy, RCS change rejected\n");
4237 return false; /* still busy with another command */
4238 }
4239
4240 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4241 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4242 I915_WRITE16(MEMSWCTL, rgvswctl);
4243 POSTING_READ16(MEMSWCTL);
4244
4245 rgvswctl |= MEMCTL_CMD_STS;
4246 I915_WRITE16(MEMSWCTL, rgvswctl);
4247
4248 return true;
4249}
4250
8090c6b9 4251static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4252{
4253 struct drm_i915_private *dev_priv = dev->dev_private;
4254 u32 rgvmodectl = I915_READ(MEMMODECTL);
4255 u8 fmax, fmin, fstart, vstart;
4256
9270388e
DV		 4257 spin_lock_irq(&mchdev_lock);
4258
2b4e57bd
ED		 4259 /* Enable temp reporting */
4260 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4261 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4262
4263 /* 100ms RC evaluation intervals */
4264 I915_WRITE(RCUPEI, 100000);
4265 I915_WRITE(RCDNEI, 100000);
4266
4267 /* Set max/min thresholds to 90ms and 80ms respectively */
4268 I915_WRITE(RCBMAXAVG, 90000);
4269 I915_WRITE(RCBMINAVG, 80000);
4270
4271 I915_WRITE(MEMIHYST, 1);
4272
4273 /* Set up min, max, and cur for interrupt handling */
4274 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4275 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4276 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4277 MEMMODE_FSTART_SHIFT;
4278
616847e7 4279 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4280 PXVFREQ_PX_SHIFT;
4281
20e4d407
DV		 4282 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4283 dev_priv->ips.fstart = fstart;
2b4e57bd 4284
20e4d407
DV		 4285 dev_priv->ips.max_delay = fstart;
4286 dev_priv->ips.min_delay = fmin;
4287 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4288
4289 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4290 fmax, fmin, fstart);
4291
4292 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4293
4294 /*
4295 * Interrupts will be enabled in ironlake_irq_postinstall
4296 */
4297
4298 I915_WRITE(VIDSTART, vstart);
4299 POSTING_READ(VIDSTART);
4300
4301 rgvmodectl |= MEMMODE_SWMODE_EN;
4302 I915_WRITE(MEMMODECTL, rgvmodectl);
4303
9270388e 4304 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4305 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4306 mdelay(1);
2b4e57bd
ED		 4307
4308 ironlake_set_drps(dev, fstart);
4309
7d81c3e0
VS		 4310 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4311 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4312 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4313 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4314 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4315
4316 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4317}
4318
8090c6b9 4319static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4320{
4321 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4322 u16 rgvswctl;
4323
4324 spin_lock_irq(&mchdev_lock);
4325
4326 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4327
4328 /* Ack interrupts, disable EFC interrupt */
4329 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4330 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4331 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4332 I915_WRITE(DEIIR, DE_PCU_EVENT);
4333 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4334
4335 /* Go back to the starting frequency */
20e4d407 4336 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4337 mdelay(1);
2b4e57bd
ED		 4338 rgvswctl |= MEMCTL_CMD_STS;
4339 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4340 mdelay(1);
2b4e57bd 4341
9270388e 4342 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4343}
4344
acbe9475
DV		 4345/* There's a funny hw issue where the hw returns all 0 when reading from
4346 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4347 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4348 * all limits and the gpu stuck at whatever frequency it is at atm).
4349 */
74ef1173 4350static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4351{
7b9e0ae6 4352 u32 limits;
2b4e57bd 4353
20b46e59
DV		 4354 /* Only set the down limit when we've reached the lowest level to avoid
4355 * getting more interrupts, otherwise leave this clear. This prevents a
4356 * race in the hw when coming out of rc6: There's a tiny window where
4357 * the hw runs at the minimal clock before selecting the desired
4358 * frequency, if the down threshold expires in that window we will not
4359 * receive a down interrupt. */
74ef1173
AG		 4360 if (IS_GEN9(dev_priv->dev)) {
4361 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4362 if (val <= dev_priv->rps.min_freq_softlimit)
4363 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4364 } else {
4365 limits = dev_priv->rps.max_freq_softlimit << 24;
4366 if (val <= dev_priv->rps.min_freq_softlimit)
4367 limits |= dev_priv->rps.min_freq_softlimit << 16;
4368 }
20b46e59
DV		 4369
4370 return limits;
4371}
4372
dd75fdc8
CW		 4373static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4374{
4375 int new_power;
8a586437
AG		 4376 u32 threshold_up = 0, threshold_down = 0; /* in % */
4377 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4378
4379 new_power = dev_priv->rps.power;
4380 switch (dev_priv->rps.power) {
4381 case LOW_POWER:
b39fb297 4382 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4383 new_power = BETWEEN;
4384 break;
4385
4386 case BETWEEN:
b39fb297 4387 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4388 new_power = LOW_POWER;
b39fb297 4389 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4390 new_power = HIGH_POWER;
4391 break;
4392
4393 case HIGH_POWER:
b39fb297 4394 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4395 new_power = BETWEEN;
4396 break;
4397 }
4398 /* Max/min bins are special */
aed242ff 4399 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4400 new_power = LOW_POWER;
aed242ff 4401 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4402 new_power = HIGH_POWER;
4403 if (new_power == dev_priv->rps.power)
4404 return;
4405
4406 /* Note the units here are not exactly 1us, but 1280ns. */
4407 switch (new_power) {
4408 case LOW_POWER:
4409 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4410 ei_up = 16000;
4411 threshold_up = 95;
dd75fdc8
CW		 4412
4413 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4414 ei_down = 32000;
4415 threshold_down = 85;
dd75fdc8
CW		 4416 break;
4417
4418 case BETWEEN:
4419 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4420 ei_up = 13000;
4421 threshold_up = 90;
dd75fdc8
CW		 4422
4423 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4424 ei_down = 32000;
4425 threshold_down = 75;
dd75fdc8
CW		 4426 break;
4427
4428 case HIGH_POWER:
4429 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4430 ei_up = 10000;
4431 threshold_up = 85;
dd75fdc8
CW		 4432
4433 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4434 ei_down = 32000;
4435 threshold_down = 60;
dd75fdc8
CW		 4436 break;
4437 }
4438
8a586437
AG		 4439 I915_WRITE(GEN6_RP_UP_EI,
4440 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4441 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4442 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4443
4444 I915_WRITE(GEN6_RP_DOWN_EI,
4445 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4446 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4447 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4448
4449 I915_WRITE(GEN6_RP_CONTROL,
4450 GEN6_RP_MEDIA_TURBO |
4451 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4452 GEN6_RP_MEDIA_IS_GFX |
4453 GEN6_RP_ENABLE |
4454 GEN6_RP_UP_BUSY_AVG |
4455 GEN6_RP_DOWN_IDLE_AVG);
4456
dd75fdc8 4457 dev_priv->rps.power = new_power;
8fb55197
CW		 4458 dev_priv->rps.up_threshold = threshold_up;
4459 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4460 dev_priv->rps.last_adj = 0;
4461}
4462
2876ce73
CW		 4463static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4464{
4465 u32 mask = 0;
4466
4467 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4468 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4469 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4470 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4471
7b3c29f6
CW		 4472 mask &= dev_priv->pm_rps_events;
4473
59d02a1f 4474 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4475}
4476
b8a5ff8d
JM		 4477/* gen6_set_rps is called to update the frequency request, but should also be
4478 * called when the range (min_delay and max_delay) is modified so that we can
4479 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4480static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4481{
4482 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4483
23eafea6
SAK		 4484 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4485 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4486 return;
4487
4fc688ce 4488 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4489 WARN_ON(val > dev_priv->rps.max_freq);
4490 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4491
eb64cad1
CW		 4492 /* min/max delay may still have been modified so be sure to
4493 * write the limits value.
4494 */
4495 if (val != dev_priv->rps.cur_freq) {
4496 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4497
5704195c
AG		 4498 if (IS_GEN9(dev))
4499 I915_WRITE(GEN6_RPNSWREQ,
4500 GEN9_FREQUENCY(val));
4501 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4502 I915_WRITE(GEN6_RPNSWREQ,
4503 HSW_FREQUENCY(val));
4504 else
4505 I915_WRITE(GEN6_RPNSWREQ,
4506 GEN6_FREQUENCY(val) |
4507 GEN6_OFFSET(0) |
4508 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4509 }
7b9e0ae6 4510
7b9e0ae6
CW		 4511 /* Make sure we continue to get interrupts
4512 * until we hit the minimum or maximum frequencies.
4513 */
74ef1173 4514 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4515 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4516
d5570a72
BW		 4517 POSTING_READ(GEN6_RPNSWREQ);
4518
b39fb297 4519 dev_priv->rps.cur_freq = val;
be2cde9a 4520 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4521}
4522
ffe02b40
VS		 4523static void valleyview_set_rps(struct drm_device *dev, u8 val)
4524{
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526
4527 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4528 WARN_ON(val > dev_priv->rps.max_freq);
4529 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4530
4531 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4532 "Odd GPU freq value\n"))
4533 val &= ~1;
4534
cd25dd5b
D		 4535 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4536
8fb55197 4537 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4538 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4539 if (!IS_CHERRYVIEW(dev_priv))
4540 gen6_set_rps_thresholds(dev_priv, val);
4541 }
ffe02b40 4542
ffe02b40
VS		 4543 dev_priv->rps.cur_freq = val;
4544 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4545}
4546
a7f6e231 4547/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4548 *
4549 * * If Gfx is Idle, then
a7f6e231
D		 4550 * 1. Forcewake Media well.
4551 * 2. Request idle freq.
4552 * 3. Release Forcewake of Media well.
76c3552f
D		 4553*/
4554static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4555{
aed242ff 4556 u32 val = dev_priv->rps.idle_freq;
5549d25f 4557
aed242ff 4558 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4559 return;
4560
a7f6e231
D		 4561 /* Wake up the media well, as that takes a lot less
4562 * power than the Render well. */
4563 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4564 valleyview_set_rps(dev_priv->dev, val);
4565 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4566}
4567
43cf3bf0
CW		 4568void gen6_rps_busy(struct drm_i915_private *dev_priv)
4569{
4570 mutex_lock(&dev_priv->rps.hw_lock);
4571 if (dev_priv->rps.enabled) {
4572 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4573 gen6_rps_reset_ei(dev_priv);
4574 I915_WRITE(GEN6_PMINTRMSK,
4575 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4576 }
4577 mutex_unlock(&dev_priv->rps.hw_lock);
4578}
4579
b29c19b6
CW		 4580void gen6_rps_idle(struct drm_i915_private *dev_priv)
4581{
691bb717
DL		 4582 struct drm_device *dev = dev_priv->dev;
4583
b29c19b6 4584 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4585 if (dev_priv->rps.enabled) {
21a11fff 4586 if (IS_VALLEYVIEW(dev))
76c3552f 4587 vlv_set_rps_idle(dev_priv);
7526ed79 4588 else
aed242ff 4589 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4590 dev_priv->rps.last_adj = 0;
43cf3bf0 4591 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4592 }
8d3afd7d 4593 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4594
8d3afd7d 4595 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4596 while (!list_empty(&dev_priv->rps.clients))
4597 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4598 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4599}
4600
1854d5ca 4601void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4602 struct intel_rps_client *rps,
4603 unsigned long submitted)
b29c19b6 4604{
8d3afd7d
CW		 4605 /* This is intentionally racy! We peek at the state here, then
4606 * validate inside the RPS worker.
4607 */
4608 if (!(dev_priv->mm.busy &&
4609 dev_priv->rps.enabled &&
4610 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4611 return;
43cf3bf0 4612
e61b9958
CW		 4613 /* Force a RPS boost (and don't count it against the client) if
4614 * the GPU is severely congested.
4615 */
d0bc54f2 4616 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4617 rps = NULL;
4618
8d3afd7d
CW		 4619 spin_lock(&dev_priv->rps.client_lock);
4620 if (rps == NULL || list_empty(&rps->link)) {
4621 spin_lock_irq(&dev_priv->irq_lock);
4622 if (dev_priv->rps.interrupts_enabled) {
4623 dev_priv->rps.client_boost = true;
4624 queue_work(dev_priv->wq, &dev_priv->rps.work);
4625 }
4626 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4627
2e1b8730
CW		 4628 if (rps != NULL) {
4629 list_add(&rps->link, &dev_priv->rps.clients);
4630 rps->boosts++;
1854d5ca
CW		 4631 } else
4632 dev_priv->rps.boosts++;
c0951f0c 4633 }
8d3afd7d 4634 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4635}
4636
ffe02b40 4637void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4638{
ffe02b40
VS		 4639 if (IS_VALLEYVIEW(dev))
4640 valleyview_set_rps(dev, val);
4641 else
4642 gen6_set_rps(dev, val);
0a073b84
JB		 4643}
4644
20e49366
ZW		 4645static void gen9_disable_rps(struct drm_device *dev)
4646{
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648
4649 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4650 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4651}
4652
44fc7d5c 4653static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4654{
4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656
4657 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4658 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4659}
4660
38807746
D		 4661static void cherryview_disable_rps(struct drm_device *dev)
4662{
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4664
4665 I915_WRITE(GEN6_RC_CONTROL, 0);
4666}
4667
44fc7d5c
DV		 4668static void valleyview_disable_rps(struct drm_device *dev)
4669{
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671
98a2e5f9
D		 4672 /* we're doing forcewake before Disabling RC6,
4673 * This what the BIOS expects when going into suspend */
59bad947 4674 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4675
44fc7d5c 4676 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4677
59bad947 4678 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4679}
4680
dc39fff7
BW		 4681static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4682{
91ca689a
ID		 4683 if (IS_VALLEYVIEW(dev)) {
4684 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4685 mode = GEN6_RC_CTL_RC6_ENABLE;
4686 else
4687 mode = 0;
4688 }
58abf1da
RV		 4689 if (HAS_RC6p(dev))
4690 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4691 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4692 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4693 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4694
4695 else
4696 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4697 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4698}
4699
e6069ca8 4700static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4701{
e7d66d89
DV		 4702 /* No RC6 before Ironlake and code is gone for ilk. */
4703 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4704 return 0;
4705
456470eb 4706 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4707 if (enable_rc6 >= 0) {
4708 int mask;
4709
58abf1da 4710 if (HAS_RC6p(dev))
e6069ca8
ID		 4711 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4712 INTEL_RC6pp_ENABLE;
4713 else
4714 mask = INTEL_RC6_ENABLE;
4715
4716 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4717 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4718 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4719
4720 return enable_rc6 & mask;
4721 }
2b4e57bd 4722
8bade1ad 4723 if (IS_IVYBRIDGE(dev))
cca84a1f 4724 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4725
4726 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4727}
4728
e6069ca8
ID		 4729int intel_enable_rc6(const struct drm_device *dev)
4730{
4731 return i915.enable_rc6;
4732}
4733
93ee2920 4734static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4735{
93ee2920
TR		 4736 struct drm_i915_private *dev_priv = dev->dev_private;
4737 uint32_t rp_state_cap;
4738 u32 ddcc_status = 0;
4739 int ret;
4740
3280e8b0
BW		 4741 /* All of these values are in units of 50MHz */
4742 dev_priv->rps.cur_freq = 0;
93ee2920 4743 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4744 if (IS_BROXTON(dev)) {
4745 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4746 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4747 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4748 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4749 } else {
4750 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4751 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4752 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4753 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4754 }
4755
3280e8b0
BW		 4756 /* hw_max = RP0 until we check for overclocking */
4757 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4758
93ee2920 4759 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4760 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4761 ret = sandybridge_pcode_read(dev_priv,
4762 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4763 &ddcc_status);
4764 if (0 == ret)
4765 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4766 clamp_t(u8,
4767 ((ddcc_status >> 8) & 0xff),
4768 dev_priv->rps.min_freq,
4769 dev_priv->rps.max_freq);
93ee2920
TR		 4770 }
4771
c5e0688c
AG		 4772 if (IS_SKYLAKE(dev)) {
4773 /* Store the frequency values in 16.66 MHZ units, which is
4774 the natural hardware unit for SKL */
4775 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4776 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4777 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4778 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4779 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4780 }
4781
aed242ff
CW		 4782 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4783
3280e8b0
BW		 4784 /* Preserve min/max settings in case of re-init */
4785 if (dev_priv->rps.max_freq_softlimit == 0)
4786 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4787
93ee2920
TR		 4788 if (dev_priv->rps.min_freq_softlimit == 0) {
4789 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4790 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4791 max_t(int, dev_priv->rps.efficient_freq,
4792 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4793 else
4794 dev_priv->rps.min_freq_softlimit =
4795 dev_priv->rps.min_freq;
4796 }
3280e8b0
BW		 4797}
4798
b6fef0ef 4799/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4800static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4801{
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803
4804 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4805
ba1c554c
DL		 4806 gen6_init_rps_frequencies(dev);
4807
23eafea6
SAK		 4808 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4809 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4810 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4811 return;
4812 }
4813
0beb059a
AG		 4814 /* Program defaults and thresholds for RPS*/
4815 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4816 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4817
4818 /* 1 second timeout*/
4819 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4820 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4821
b6fef0ef 4822 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4823
0beb059a
AG		 4824 /* Leaning on the below call to gen6_set_rps to program/setup the
4825 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4826 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4827 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4828 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4829
4830 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4831}
4832
4833static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4834{
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4836 struct intel_engine_cs *ring;
4837 uint32_t rc6_mask = 0;
4838 int unused;
4839
4840 /* 1a: Software RC state - RC0 */
4841 I915_WRITE(GEN6_RC_STATE, 0);
4842
4843 /* 1b: Get forcewake during program sequence. Although the driver
4844 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4845 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4846
4847 /* 2a: Disable RC states. */
4848 I915_WRITE(GEN6_RC_CONTROL, 0);
4849
4850 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4851
4852 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4853 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4854 (INTEL_REVID(dev) <= SKL_REVID_E0)))
4855 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4856 else
4857 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4858 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4859 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4860 for_each_ring(ring, dev_priv, unused)
4861 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4862
4863 if (HAS_GUC_UCODE(dev))
4864 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4865
20e49366
ZW		 4866 I915_WRITE(GEN6_RC_SLEEP, 0);
4867 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4868
38c23527
ZW		 4869 /* 2c: Program Coarse Power Gating Policies. */
4870 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4871 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4872
20e49366
ZW		 4873 /* 3a: Enable RC6 */
4874 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4875 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4876 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4877 "on" : "off");
e3429cd2
SAK		 4878
4879 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4880 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
4881 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4882 GEN7_RC_CTL_TO_MODE |
4883 rc6_mask);
4884 else
4885 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4886 GEN6_RC_CTL_EI_MODE(1) |
4887 rc6_mask);
20e49366 4888
cb07bae0
SK		 4889 /*
4890 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4891 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4892 */
f2d2fe95
SAK		 4893 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4894 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4895 I915_WRITE(GEN9_PG_ENABLE, 0);
4896 else
4897 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4898 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4899
59bad947 4900 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4901
4902}
4903
6edee7f3
BW		 4904static void gen8_enable_rps(struct drm_device *dev)
4905{
4906 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4907 struct intel_engine_cs *ring;
93ee2920 4908 uint32_t rc6_mask = 0;
6edee7f3
BW		 4909 int unused;
4910
4911 /* 1a: Software RC state - RC0 */
4912 I915_WRITE(GEN6_RC_STATE, 0);
4913
4914 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4915 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4916 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4917
4918 /* 2a: Disable RC states. */
4919 I915_WRITE(GEN6_RC_CONTROL, 0);
4920
93ee2920
TR		 4921 /* Initialize rps frequencies */
4922 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4923
4924 /* 2b: Program RC6 thresholds.*/
4925 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4926 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4927 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4928 for_each_ring(ring, dev_priv, unused)
4929 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4930 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4931 if (IS_BROADWELL(dev))
4932 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4933 else
4934 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4935
4936 /* 3: Enable RC6 */
4937 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4938 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4939 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4940 if (IS_BROADWELL(dev))
4941 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4942 GEN7_RC_CTL_TO_MODE |
4943 rc6_mask);
4944 else
4945 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4946 GEN6_RC_CTL_EI_MODE(1) |
4947 rc6_mask);
6edee7f3
BW		 4948
4949 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4950 I915_WRITE(GEN6_RPNSWREQ,
4951 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4952 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4953 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4954 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4955 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4956
4957 /* Docs recommend 900MHz, and 300 MHz respectively */
4958 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4959 dev_priv->rps.max_freq_softlimit << 24 |
4960 dev_priv->rps.min_freq_softlimit << 16);
4961
4962 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4963 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4964 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4965 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4966
4967 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4968
4969 /* 5: Enable RPS */
7526ed79
DV		 4970 I915_WRITE(GEN6_RP_CONTROL,
4971 GEN6_RP_MEDIA_TURBO |
4972 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4973 GEN6_RP_MEDIA_IS_GFX |
4974 GEN6_RP_ENABLE |
4975 GEN6_RP_UP_BUSY_AVG |
4976 GEN6_RP_DOWN_IDLE_AVG);
4977
4978 /* 6: Ring frequency + overclocking (our driver does this later */
4979
c7f3153a 4980 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4981 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4982
59bad947 4983 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4984}
4985
79f5b2c7 4986static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4987{
79f5b2c7 4988 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4989 struct intel_engine_cs *ring;
d060c169 4990 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4991 u32 gtfifodbg;
2b4e57bd 4992 int rc6_mode;
42c0526c 4993 int i, ret;
2b4e57bd 4994
4fc688ce 4995 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4996
2b4e57bd
ED		 4997 /* Here begins a magic sequence of register writes to enable
4998 * auto-downclocking.
4999 *
5000 * Perhaps there might be some value in exposing these to
5001 * userspace...
5002 */
5003 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5004
5005 /* Clear the DBG now so we don't confuse earlier errors */
5006 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5007 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5008 I915_WRITE(GTFIFODBG, gtfifodbg);
5009 }
5010
59bad947 5011 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5012
93ee2920
TR		 5013 /* Initialize rps frequencies */
5014 gen6_init_rps_frequencies(dev);
dd0a1aa1 5015
2b4e57bd
ED		 5016 /* disable the counters and set deterministic thresholds */
5017 I915_WRITE(GEN6_RC_CONTROL, 0);
5018
5019 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5020 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5021 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5022 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5023 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5024
b4519513
CW		 5025 for_each_ring(ring, dev_priv, i)
5026 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 5027
5028 I915_WRITE(GEN6_RC_SLEEP, 0);
5029 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 5030 if (IS_IVYBRIDGE(dev))
351aa566
SM		 5031 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5032 else
5033 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5034 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5035 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5036
5a7dc92a 5037 /* Check if we are enabling RC6 */
2b4e57bd
ED		 5038 rc6_mode = intel_enable_rc6(dev_priv->dev);
5039 if (rc6_mode & INTEL_RC6_ENABLE)
5040 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5041
5a7dc92a
ED		 5042 /* We don't use those on Haswell */
5043 if (!IS_HASWELL(dev)) {
5044 if (rc6_mode & INTEL_RC6p_ENABLE)
5045 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5046
5a7dc92a
ED		 5047 if (rc6_mode & INTEL_RC6pp_ENABLE)
5048 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5049 }
2b4e57bd 5050
dc39fff7 5051 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 5052
5053 I915_WRITE(GEN6_RC_CONTROL,
5054 rc6_mask |
5055 GEN6_RC_CTL_EI_MODE(1) |
5056 GEN6_RC_CTL_HW_ENABLE);
5057
dd75fdc8
CW		 5058 /* Power down if completely idle for over 50ms */
5059 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5060 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5061
42c0526c 5062 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5063 if (ret)
42c0526c 5064 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5065
5066 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5067 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5068 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5069 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5070 (pcu_mbox & 0xff) * 50);
b39fb297 5071 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5072 }
5073
dd75fdc8 5074 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5075 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5076
31643d54
BW		 5077 rc6vids = 0;
5078 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5079 if (IS_GEN6(dev) && ret) {
5080 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5081 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5082 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5083 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5084 rc6vids &= 0xffff00;
5085 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5086 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5087 if (ret)
5088 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5089 }
5090
59bad947 5091 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5092}
5093
c2bc2fc5 5094static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5095{
79f5b2c7 5096 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5097 int min_freq = 15;
3ebecd07
CW		 5098 unsigned int gpu_freq;
5099 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5100 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5101 int scaling_factor = 180;
eda79642 5102 struct cpufreq_policy *policy;
2b4e57bd 5103
4fc688ce 5104 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5105
eda79642
BW		 5106 policy = cpufreq_cpu_get(0);
5107 if (policy) {
5108 max_ia_freq = policy->cpuinfo.max_freq;
5109 cpufreq_cpu_put(policy);
5110 } else {
5111 /*
5112 * Default to measured freq if none found, PCU will ensure we
5113 * don't go over
5114 */
2b4e57bd 5115 max_ia_freq = tsc_khz;
eda79642 5116 }
2b4e57bd
ED		 5117
5118 /* Convert from kHz to MHz */
5119 max_ia_freq /= 1000;
5120
153b4b95 5121 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5122 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5123 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5124
4c8c7743
AG		 5125 if (IS_SKYLAKE(dev)) {
5126 /* Convert GT frequency to 50 HZ units */
5127 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5128 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5129 } else {
5130 min_gpu_freq = dev_priv->rps.min_freq;
5131 max_gpu_freq = dev_priv->rps.max_freq;
5132 }
5133
2b4e57bd
ED		 5134 /*
5135 * For each potential GPU frequency, load a ring frequency we'd like
5136 * to use for memory access. We do this by specifying the IA frequency
5137 * the PCU should use as a reference to determine the ring frequency.
5138 */
4c8c7743
AG		 5139 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5140 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5141 unsigned int ia_freq = 0, ring_freq = 0;
5142
4c8c7743
AG		 5143 if (IS_SKYLAKE(dev)) {
5144 /*
5145 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5146 * No floor required for ring frequency on SKL.
5147 */
5148 ring_freq = gpu_freq;
5149 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5150 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5151 ring_freq = max(min_ring_freq, gpu_freq);
5152 } else if (IS_HASWELL(dev)) {
f6aca45c 5153 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5154 ring_freq = max(min_ring_freq, ring_freq);
5155 /* leave ia_freq as the default, chosen by cpufreq */
5156 } else {
5157 /* On older processors, there is no separate ring
5158 * clock domain, so in order to boost the bandwidth
5159 * of the ring, we need to upclock the CPU (ia_freq).
5160 *
5161 * For GPU frequencies less than 750MHz,
5162 * just use the lowest ring freq.
5163 */
5164 if (gpu_freq < min_freq)
5165 ia_freq = 800;
5166 else
5167 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5168 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5169 }
2b4e57bd 5170
42c0526c
BW		 5171 sandybridge_pcode_write(dev_priv,
5172 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5173 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5174 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5175 gpu_freq);
2b4e57bd 5176 }
2b4e57bd
ED		 5177}
5178
c2bc2fc5
ID		 5179void gen6_update_ring_freq(struct drm_device *dev)
5180{
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182
97d3308a 5183 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5184 return;
5185
5186 mutex_lock(&dev_priv->rps.hw_lock);
5187 __gen6_update_ring_freq(dev);
5188 mutex_unlock(&dev_priv->rps.hw_lock);
5189}
5190
03af2045 5191static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5192{
095acd5f 5193 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5194 u32 val, rp0;
5195
095acd5f
D		 5196 if (dev->pdev->revision >= 0x20) {
5197 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5198
095acd5f
D		 5199 switch (INTEL_INFO(dev)->eu_total) {
5200 case 8:
5201 /* (2 * 4) config */
5202 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5203 break;
5204 case 12:
5205 /* (2 * 6) config */
5206 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5207 break;
5208 case 16:
5209 /* (2 * 8) config */
5210 default:
5211 /* Setting (2 * 8) Min RP0 for any other combination */
5212 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5213 break;
5214 }
5215 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5216 } else {
5217 /* For pre-production hardware */
5218 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5219 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5220 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5221 }
2b6b3a09
D		 5222 return rp0;
5223}
5224
5225static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5226{
5227 u32 val, rpe;
5228
5229 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5230 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5231
5232 return rpe;
5233}
5234
7707df4a
D		 5235static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5236{
095acd5f 5237 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5238 u32 val, rp1;
5239
095acd5f
D		 5240 if (dev->pdev->revision >= 0x20) {
5241 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5242 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5243 } else {
5244 /* For pre-production hardware */
5245 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5246 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5247 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5248 }
7707df4a
D		 5249 return rp1;
5250}
5251
f8f2b001
D		 5252static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5253{
5254 u32 val, rp1;
5255
5256 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5257
5258 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5259
5260 return rp1;
5261}
5262
03af2045 5263static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5264{
5265 u32 val, rp0;
5266
64936258 5267 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5268
5269 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5270 /* Clamp to max */
5271 rp0 = min_t(u32, rp0, 0xea);
5272
5273 return rp0;
5274}
5275
5276static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5277{
5278 u32 val, rpe;
5279
64936258 5280 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5281 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5282 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5283 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5284
5285 return rpe;
5286}
5287
03af2045 5288static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5289{
64936258 5290 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5291}
5292
ae48434c
ID		 5293/* Check that the pctx buffer wasn't move under us. */
5294static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5295{
5296 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5297
5298 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5299 dev_priv->vlv_pctx->stolen->start);
5300}
5301
38807746
D		 5302
5303/* Check that the pcbr address is not empty. */
5304static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5305{
5306 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5307
5308 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5309}
5310
5311static void cherryview_setup_pctx(struct drm_device *dev)
5312{
5313 struct drm_i915_private *dev_priv = dev->dev_private;
5314 unsigned long pctx_paddr, paddr;
5315 struct i915_gtt *gtt = &dev_priv->gtt;
5316 u32 pcbr;
5317 int pctx_size = 32*1024;
5318
5319 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5320
5321 pcbr = I915_READ(VLV_PCBR);
5322 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5323 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5324 paddr = (dev_priv->mm.stolen_base +
5325 (gtt->stolen_size - pctx_size));
5326
5327 pctx_paddr = (paddr & (~4095));
5328 I915_WRITE(VLV_PCBR, pctx_paddr);
5329 }
ce611ef8
VS		 5330
5331 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5332}
5333
c9cddffc
JB		 5334static void valleyview_setup_pctx(struct drm_device *dev)
5335{
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct drm_i915_gem_object *pctx;
5338 unsigned long pctx_paddr;
5339 u32 pcbr;
5340 int pctx_size = 24*1024;
5341
17b0c1f7
ID		 5342 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5343
c9cddffc
JB		 5344 pcbr = I915_READ(VLV_PCBR);
5345 if (pcbr) {
5346 /* BIOS set it up already, grab the pre-alloc'd space */
5347 int pcbr_offset;
5348
5349 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5350 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5351 pcbr_offset,
190d6cd5 5352 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5353 pctx_size);
5354 goto out;
5355 }
5356
ce611ef8
VS		 5357 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5358
c9cddffc
JB		 5359 /*
5360 * From the Gunit register HAS:
5361 * The Gfx driver is expected to program this register and ensure
5362 * proper allocation within Gfx stolen memory. For example, this
5363 * register should be programmed such than the PCBR range does not
5364 * overlap with other ranges, such as the frame buffer, protected
5365 * memory, or any other relevant ranges.
5366 */
5367 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5368 if (!pctx) {
5369 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5370 return;
5371 }
5372
5373 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5374 I915_WRITE(VLV_PCBR, pctx_paddr);
5375
5376out:
ce611ef8 5377 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5378 dev_priv->vlv_pctx = pctx;
5379}
5380
ae48434c
ID		 5381static void valleyview_cleanup_pctx(struct drm_device *dev)
5382{
5383 struct drm_i915_private *dev_priv = dev->dev_private;
5384
5385 if (WARN_ON(!dev_priv->vlv_pctx))
5386 return;
5387
5388 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5389 dev_priv->vlv_pctx = NULL;
5390}
5391
4e80519e
ID		 5392static void valleyview_init_gt_powersave(struct drm_device *dev)
5393{
5394 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5395 u32 val;
4e80519e
ID		 5396
5397 valleyview_setup_pctx(dev);
5398
5399 mutex_lock(&dev_priv->rps.hw_lock);
5400
2bb25c17
VS		 5401 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5402 switch ((val >> 6) & 3) {
5403 case 0:
5404 case 1:
5405 dev_priv->mem_freq = 800;
5406 break;
5407 case 2:
5408 dev_priv->mem_freq = 1066;
5409 break;
5410 case 3:
5411 dev_priv->mem_freq = 1333;
5412 break;
5413 }
80b83b62 5414 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5415
4e80519e
ID		 5416 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5417 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5418 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5419 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5420 dev_priv->rps.max_freq);
5421
5422 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5423 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5424 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5425 dev_priv->rps.efficient_freq);
5426
f8f2b001
D		 5427 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5428 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5429 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5430 dev_priv->rps.rp1_freq);
5431
4e80519e
ID		 5432 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5433 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5434 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5435 dev_priv->rps.min_freq);
5436
aed242ff
CW		 5437 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5438
4e80519e
ID		 5439 /* Preserve min/max settings in case of re-init */
5440 if (dev_priv->rps.max_freq_softlimit == 0)
5441 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5442
5443 if (dev_priv->rps.min_freq_softlimit == 0)
5444 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5445
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447}
5448
38807746
D		 5449static void cherryview_init_gt_powersave(struct drm_device *dev)
5450{
2b6b3a09 5451 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5452 u32 val;
2b6b3a09 5453
38807746 5454 cherryview_setup_pctx(dev);
2b6b3a09
D		 5455
5456 mutex_lock(&dev_priv->rps.hw_lock);
5457
a580516d 5458 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5459 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5460 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5461
2bb25c17
VS		 5462 switch ((val >> 2) & 0x7) {
5463 case 0:
5464 case 1:
5465 dev_priv->rps.cz_freq = 200;
5466 dev_priv->mem_freq = 1600;
5467 break;
5468 case 2:
5469 dev_priv->rps.cz_freq = 267;
5470 dev_priv->mem_freq = 1600;
5471 break;
5472 case 3:
5473 dev_priv->rps.cz_freq = 333;
5474 dev_priv->mem_freq = 2000;
5475 break;
5476 case 4:
5477 dev_priv->rps.cz_freq = 320;
5478 dev_priv->mem_freq = 1600;
5479 break;
5480 case 5:
5481 dev_priv->rps.cz_freq = 400;
5482 dev_priv->mem_freq = 1600;
5483 break;
5484 }
80b83b62 5485 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5486
2b6b3a09
D		 5487 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5488 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5489 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5490 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5491 dev_priv->rps.max_freq);
5492
5493 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5494 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5495 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5496 dev_priv->rps.efficient_freq);
5497
7707df4a
D		 5498 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5499 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5500 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5501 dev_priv->rps.rp1_freq);
5502
5b7c91b7
D		 5503 /* PUnit validated range is only [RPe, RP0] */
5504 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5505 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5506 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5507 dev_priv->rps.min_freq);
5508
1c14762d
VS		 5509 WARN_ONCE((dev_priv->rps.max_freq |
5510 dev_priv->rps.efficient_freq |
5511 dev_priv->rps.rp1_freq |
5512 dev_priv->rps.min_freq) & 1,
5513 "Odd GPU freq values\n");
5514
aed242ff
CW		 5515 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5516
2b6b3a09
D		 5517 /* Preserve min/max settings in case of re-init */
5518 if (dev_priv->rps.max_freq_softlimit == 0)
5519 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5520
5521 if (dev_priv->rps.min_freq_softlimit == 0)
5522 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5523
5524 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5525}
5526
4e80519e
ID		 5527static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5528{
5529 valleyview_cleanup_pctx(dev);
5530}
5531
38807746
D		 5532static void cherryview_enable_rps(struct drm_device *dev)
5533{
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535 struct intel_engine_cs *ring;
2b6b3a09 5536 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5537 int i;
5538
5539 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5540
5541 gtfifodbg = I915_READ(GTFIFODBG);
5542 if (gtfifodbg) {
5543 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5544 gtfifodbg);
5545 I915_WRITE(GTFIFODBG, gtfifodbg);
5546 }
5547
5548 cherryview_check_pctx(dev_priv);
5549
5550 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5551 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5552 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5553
160614a2
VS		 5554 /* Disable RC states. */
5555 I915_WRITE(GEN6_RC_CONTROL, 0);
5556
38807746
D		 5557 /* 2a: Program RC6 thresholds.*/
5558 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5559 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5560 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5561
5562 for_each_ring(ring, dev_priv, i)
5563 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5564 I915_WRITE(GEN6_RC_SLEEP, 0);
5565
f4f71c7d
D		 5566 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5567 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5568
5569 /* allows RC6 residency counter to work */
5570 I915_WRITE(VLV_COUNTER_CONTROL,
5571 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5572 VLV_MEDIA_RC6_COUNT_EN |
5573 VLV_RENDER_RC6_COUNT_EN));
5574
5575 /* For now we assume BIOS is allocating and populating the PCBR */
5576 pcbr = I915_READ(VLV_PCBR);
5577
38807746
D		 5578 /* 3: Enable RC6 */
5579 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5580 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5581 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5582
5583 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5584
2b6b3a09 5585 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5586 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5587 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5588 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5589 I915_WRITE(GEN6_RP_UP_EI, 66000);
5590 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5591
5592 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5593
5594 /* 5: Enable RPS */
5595 I915_WRITE(GEN6_RP_CONTROL,
5596 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5597 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5598 GEN6_RP_ENABLE |
5599 GEN6_RP_UP_BUSY_AVG |
5600 GEN6_RP_DOWN_IDLE_AVG);
5601
3ef62342
D		 5602 /* Setting Fixed Bias */
5603 val = VLV_OVERRIDE_EN |
5604 VLV_SOC_TDP_EN |
5605 CHV_BIAS_CPU_50_SOC_50;
5606 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5607
2b6b3a09
D		 5608 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5609
8d40c3ae
VS		 5610 /* RPS code assumes GPLL is used */
5611 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5612
742f491d 5613 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5614 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5615
5616 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5617 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5618 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5619 dev_priv->rps.cur_freq);
5620
5621 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5622 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5623 dev_priv->rps.efficient_freq);
5624
5625 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5626
59bad947 5627 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5628}
5629
0a073b84
JB		 5630static void valleyview_enable_rps(struct drm_device *dev)
5631{
5632 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5633 struct intel_engine_cs *ring;
2a5913a8 5634 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5635 int i;
5636
5637 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5638
ae48434c
ID		 5639 valleyview_check_pctx(dev_priv);
5640
0a073b84 5641 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5642 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5643 gtfifodbg);
0a073b84
JB		 5644 I915_WRITE(GTFIFODBG, gtfifodbg);
5645 }
5646
c8d9a590 5647 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5648 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5649
160614a2
VS		 5650 /* Disable RC states. */
5651 I915_WRITE(GEN6_RC_CONTROL, 0);
5652
cad725fe 5653 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5654 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5655 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5656 I915_WRITE(GEN6_RP_UP_EI, 66000);
5657 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5658
5659 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5660
5661 I915_WRITE(GEN6_RP_CONTROL,
5662 GEN6_RP_MEDIA_TURBO |
5663 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5664 GEN6_RP_MEDIA_IS_GFX |
5665 GEN6_RP_ENABLE |
5666 GEN6_RP_UP_BUSY_AVG |
5667 GEN6_RP_DOWN_IDLE_CONT);
5668
5669 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5670 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5671 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5672
5673 for_each_ring(ring, dev_priv, i)
5674 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5675
2f0aa304 5676 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5677
5678 /* allows RC6 residency counter to work */
49798eb2 5679 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5680 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5681 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5682 VLV_MEDIA_RC6_COUNT_EN |
5683 VLV_RENDER_RC6_COUNT_EN));
31685c25 5684
a2b23fe0 5685 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5686 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5687
5688 intel_print_rc6_info(dev, rc6_mode);
5689
a2b23fe0 5690 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5691
3ef62342
D		 5692 /* Setting Fixed Bias */
5693 val = VLV_OVERRIDE_EN |
5694 VLV_SOC_TDP_EN |
5695 VLV_BIAS_CPU_125_SOC_875;
5696 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5697
64936258 5698 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5699
8d40c3ae
VS		 5700 /* RPS code assumes GPLL is used */
5701 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5702
742f491d 5703 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5704 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5705
b39fb297 5706 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5707 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5708 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5709 dev_priv->rps.cur_freq);
0a073b84 5710
73008b98 5711 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5712 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5713 dev_priv->rps.efficient_freq);
0a073b84 5714
b39fb297 5715 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5716
59bad947 5717 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5718}
5719
dde18883
ED		 5720static unsigned long intel_pxfreq(u32 vidfreq)
5721{
5722 unsigned long freq;
5723 int div = (vidfreq & 0x3f0000) >> 16;
5724 int post = (vidfreq & 0x3000) >> 12;
5725 int pre = (vidfreq & 0x7);
5726
5727 if (!pre)
5728 return 0;
5729
5730 freq = ((div * 133333) / ((1<<post) * pre));
5731
5732 return freq;
5733}
5734
eb48eb00
DV		 5735static const struct cparams {
5736 u16 i;
5737 u16 t;
5738 u16 m;
5739 u16 c;
5740} cparams[] = {
5741 { 1, 1333, 301, 28664 },
5742 { 1, 1066, 294, 24460 },
5743 { 1, 800, 294, 25192 },
5744 { 0, 1333, 276, 27605 },
5745 { 0, 1066, 276, 27605 },
5746 { 0, 800, 231, 23784 },
5747};
5748
f531dcb2 5749static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5750{
5751 u64 total_count, diff, ret;
5752 u32 count1, count2, count3, m = 0, c = 0;
5753 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5754 int i;
5755
02d71956
DV		 5756 assert_spin_locked(&mchdev_lock);
5757
20e4d407 5758 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5759
5760 /* Prevent division-by-zero if we are asking too fast.
5761 * Also, we don't get interesting results if we are polling
5762 * faster than once in 10ms, so just return the saved value
5763 * in such cases.
5764 */
5765 if (diff1 <= 10)
20e4d407 5766 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5767
5768 count1 = I915_READ(DMIEC);
5769 count2 = I915_READ(DDREC);
5770 count3 = I915_READ(CSIEC);
5771
5772 total_count = count1 + count2 + count3;
5773
5774 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5775 if (total_count < dev_priv->ips.last_count1) {
5776 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5777 diff += total_count;
5778 } else {
20e4d407 5779 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5780 }
5781
5782 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5783 if (cparams[i].i == dev_priv->ips.c_m &&
5784 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5785 m = cparams[i].m;
5786 c = cparams[i].c;
5787 break;
5788 }
5789 }
5790
5791 diff = div_u64(diff, diff1);
5792 ret = ((m * diff) + c);
5793 ret = div_u64(ret, 10);
5794
20e4d407
DV		 5795 dev_priv->ips.last_count1 = total_count;
5796 dev_priv->ips.last_time1 = now;
eb48eb00 5797
20e4d407 5798 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5799
5800 return ret;
5801}
5802
f531dcb2
CW		 5803unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5804{
3d13ef2e 5805 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5806 unsigned long val;
5807
3d13ef2e 5808 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5809 return 0;
5810
5811 spin_lock_irq(&mchdev_lock);
5812
5813 val = __i915_chipset_val(dev_priv);
5814
5815 spin_unlock_irq(&mchdev_lock);
5816
5817 return val;
5818}
5819
eb48eb00
DV		 5820unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5821{
5822 unsigned long m, x, b;
5823 u32 tsfs;
5824
5825 tsfs = I915_READ(TSFS);
5826
5827 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5828 x = I915_READ8(TR1);
5829
5830 b = tsfs & TSFS_INTR_MASK;
5831
5832 return ((m * x) / 127) - b;
5833}
5834
d972d6ee
MK		 5835static int _pxvid_to_vd(u8 pxvid)
5836{
5837 if (pxvid == 0)
5838 return 0;
5839
5840 if (pxvid >= 8 && pxvid < 31)
5841 pxvid = 31;
5842
5843 return (pxvid + 2) * 125;
5844}
5845
5846static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5847{
3d13ef2e 5848 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5849 const int vd = _pxvid_to_vd(pxvid);
5850 const int vm = vd - 1125;
5851
3d13ef2e 5852 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5853 return vm > 0 ? vm : 0;
5854
5855 return vd;
eb48eb00
DV		 5856}
5857
02d71956 5858static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5859{
5ed0bdf2 5860 u64 now, diff, diffms;
eb48eb00
DV		 5861 u32 count;
5862
02d71956 5863 assert_spin_locked(&mchdev_lock);
eb48eb00 5864
5ed0bdf2
TG		 5865 now = ktime_get_raw_ns();
5866 diffms = now - dev_priv->ips.last_time2;
5867 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5868
5869 /* Don't divide by 0 */
eb48eb00
DV		 5870 if (!diffms)
5871 return;
5872
5873 count = I915_READ(GFXEC);
5874
20e4d407
DV		 5875 if (count < dev_priv->ips.last_count2) {
5876 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5877 diff += count;
5878 } else {
20e4d407 5879 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5880 }
5881
20e4d407
DV		 5882 dev_priv->ips.last_count2 = count;
5883 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5884
5885 /* More magic constants... */
5886 diff = diff * 1181;
5887 diff = div_u64(diff, diffms * 10);
20e4d407 5888 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5889}
5890
02d71956
DV		 5891void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5892{
3d13ef2e
DL		 5893 struct drm_device *dev = dev_priv->dev;
5894
5895 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5896 return;
5897
9270388e 5898 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5899
5900 __i915_update_gfx_val(dev_priv);
5901
9270388e 5902 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5903}
5904
f531dcb2 5905static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5906{
5907 unsigned long t, corr, state1, corr2, state2;
5908 u32 pxvid, ext_v;
5909
02d71956
DV		 5910 assert_spin_locked(&mchdev_lock);
5911
616847e7 5912 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5913 pxvid = (pxvid >> 24) & 0x7f;
5914 ext_v = pvid_to_extvid(dev_priv, pxvid);
5915
5916 state1 = ext_v;
5917
5918 t = i915_mch_val(dev_priv);
5919
5920 /* Revel in the empirically derived constants */
5921
5922 /* Correction factor in 1/100000 units */
5923 if (t > 80)
5924 corr = ((t * 2349) + 135940);
5925 else if (t >= 50)
5926 corr = ((t * 964) + 29317);
5927 else /* < 50 */
5928 corr = ((t * 301) + 1004);
5929
5930 corr = corr * ((150142 * state1) / 10000 - 78642);
5931 corr /= 100000;
20e4d407 5932 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5933
5934 state2 = (corr2 * state1) / 10000;
5935 state2 /= 100; /* convert to mW */
5936
02d71956 5937 __i915_update_gfx_val(dev_priv);
eb48eb00 5938
20e4d407 5939 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5940}
5941
f531dcb2
CW		 5942unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5943{
3d13ef2e 5944 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5945 unsigned long val;
5946
3d13ef2e 5947 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5948 return 0;
5949
5950 spin_lock_irq(&mchdev_lock);
5951
5952 val = __i915_gfx_val(dev_priv);
5953
5954 spin_unlock_irq(&mchdev_lock);
5955
5956 return val;
5957}
5958
eb48eb00
DV		 5959/**
5960 * i915_read_mch_val - return value for IPS use
5961 *
5962 * Calculate and return a value for the IPS driver to use when deciding whether
5963 * we have thermal and power headroom to increase CPU or GPU power budget.
5964 */
5965unsigned long i915_read_mch_val(void)
5966{
5967 struct drm_i915_private *dev_priv;
5968 unsigned long chipset_val, graphics_val, ret = 0;
5969
9270388e 5970 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5971 if (!i915_mch_dev)
5972 goto out_unlock;
5973 dev_priv = i915_mch_dev;
5974
f531dcb2
CW		 5975 chipset_val = __i915_chipset_val(dev_priv);
5976 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5977
5978 ret = chipset_val + graphics_val;
5979
5980out_unlock:
9270388e 5981 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5982
5983 return ret;
5984}
5985EXPORT_SYMBOL_GPL(i915_read_mch_val);
5986
5987/**
5988 * i915_gpu_raise - raise GPU frequency limit
5989 *
5990 * Raise the limit; IPS indicates we have thermal headroom.
5991 */
5992bool i915_gpu_raise(void)
5993{
5994 struct drm_i915_private *dev_priv;
5995 bool ret = true;
5996
9270388e 5997 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5998 if (!i915_mch_dev) {
5999 ret = false;
6000 goto out_unlock;
6001 }
6002 dev_priv = i915_mch_dev;
6003
20e4d407
DV		 6004 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6005 dev_priv->ips.max_delay--;
eb48eb00
DV		 6006
6007out_unlock:
9270388e 6008 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6009
6010 return ret;
6011}
6012EXPORT_SYMBOL_GPL(i915_gpu_raise);
6013
6014/**
6015 * i915_gpu_lower - lower GPU frequency limit
6016 *
6017 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6018 * frequency maximum.
6019 */
6020bool i915_gpu_lower(void)
6021{
6022 struct drm_i915_private *dev_priv;
6023 bool ret = true;
6024
9270388e 6025 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6026 if (!i915_mch_dev) {
6027 ret = false;
6028 goto out_unlock;
6029 }
6030 dev_priv = i915_mch_dev;
6031
20e4d407
DV		 6032 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6033 dev_priv->ips.max_delay++;
eb48eb00
DV		 6034
6035out_unlock:
9270388e 6036 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6037
6038 return ret;
6039}
6040EXPORT_SYMBOL_GPL(i915_gpu_lower);
6041
6042/**
6043 * i915_gpu_busy - indicate GPU business to IPS
6044 *
6045 * Tell the IPS driver whether or not the GPU is busy.
6046 */
6047bool i915_gpu_busy(void)
6048{
6049 struct drm_i915_private *dev_priv;
a4872ba6 6050 struct intel_engine_cs *ring;
eb48eb00 6051 bool ret = false;
f047e395 6052 int i;
eb48eb00 6053
9270388e 6054 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6055 if (!i915_mch_dev)
6056 goto out_unlock;
6057 dev_priv = i915_mch_dev;
6058
f047e395
CW		 6059 for_each_ring(ring, dev_priv, i)
6060 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 6061
6062out_unlock:
9270388e 6063 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6064
6065 return ret;
6066}
6067EXPORT_SYMBOL_GPL(i915_gpu_busy);
6068
6069/**
6070 * i915_gpu_turbo_disable - disable graphics turbo
6071 *
6072 * Disable graphics turbo by resetting the max frequency and setting the
6073 * current frequency to the default.
6074 */
6075bool i915_gpu_turbo_disable(void)
6076{
6077 struct drm_i915_private *dev_priv;
6078 bool ret = true;
6079
9270388e 6080 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6081 if (!i915_mch_dev) {
6082 ret = false;
6083 goto out_unlock;
6084 }
6085 dev_priv = i915_mch_dev;
6086
20e4d407 6087 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6088
20e4d407 6089 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6090 ret = false;
6091
6092out_unlock:
9270388e 6093 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6094
6095 return ret;
6096}
6097EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6098
6099/**
6100 * Tells the intel_ips driver that the i915 driver is now loaded, if
6101 * IPS got loaded first.
6102 *
6103 * This awkward dance is so that neither module has to depend on the
6104 * other in order for IPS to do the appropriate communication of
6105 * GPU turbo limits to i915.
6106 */
6107static void
6108ips_ping_for_i915_load(void)
6109{
6110 void (*link)(void);
6111
6112 link = symbol_get(ips_link_to_i915_driver);
6113 if (link) {
6114 link();
6115 symbol_put(ips_link_to_i915_driver);
6116 }
6117}
6118
6119void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6120{
02d71956
DV		 6121 /* We only register the i915 ips part with intel-ips once everything is
6122 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6123 spin_lock_irq(&mchdev_lock);
eb48eb00 6124 i915_mch_dev = dev_priv;
9270388e 6125 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6126
6127 ips_ping_for_i915_load();
6128}
6129
6130void intel_gpu_ips_teardown(void)
6131{
9270388e 6132 spin_lock_irq(&mchdev_lock);
eb48eb00 6133 i915_mch_dev = NULL;
9270388e 6134 spin_unlock_irq(&mchdev_lock);
eb48eb00 6135}
76c3552f 6136
8090c6b9 6137static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6138{
6139 struct drm_i915_private *dev_priv = dev->dev_private;
6140 u32 lcfuse;
6141 u8 pxw[16];
6142 int i;
6143
6144 /* Disable to program */
6145 I915_WRITE(ECR, 0);
6146 POSTING_READ(ECR);
6147
6148 /* Program energy weights for various events */
6149 I915_WRITE(SDEW, 0x15040d00);
6150 I915_WRITE(CSIEW0, 0x007f0000);
6151 I915_WRITE(CSIEW1, 0x1e220004);
6152 I915_WRITE(CSIEW2, 0x04000004);
6153
6154 for (i = 0; i < 5; i++)
616847e7 6155 I915_WRITE(PEW(i), 0);
dde18883 6156 for (i = 0; i < 3; i++)
616847e7 6157 I915_WRITE(DEW(i), 0);
dde18883
ED		 6158
6159 /* Program P-state weights to account for frequency power adjustment */
6160 for (i = 0; i < 16; i++) {
616847e7 6161 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6162 unsigned long freq = intel_pxfreq(pxvidfreq);
6163 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6164 PXVFREQ_PX_SHIFT;
6165 unsigned long val;
6166
6167 val = vid * vid;
6168 val *= (freq / 1000);
6169 val *= 255;
6170 val /= (127*127*900);
6171 if (val > 0xff)
6172 DRM_ERROR("bad pxval: %ld\n", val);
6173 pxw[i] = val;
6174 }
6175 /* Render standby states get 0 weight */
6176 pxw[14] = 0;
6177 pxw[15] = 0;
6178
6179 for (i = 0; i < 4; i++) {
6180 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6181 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6182 I915_WRITE(PXW(i), val);
dde18883
ED		 6183 }
6184
6185 /* Adjust magic regs to magic values (more experimental results) */
6186 I915_WRITE(OGW0, 0);
6187 I915_WRITE(OGW1, 0);
6188 I915_WRITE(EG0, 0x00007f00);
6189 I915_WRITE(EG1, 0x0000000e);
6190 I915_WRITE(EG2, 0x000e0000);
6191 I915_WRITE(EG3, 0x68000300);
6192 I915_WRITE(EG4, 0x42000000);
6193 I915_WRITE(EG5, 0x00140031);
6194 I915_WRITE(EG6, 0);
6195 I915_WRITE(EG7, 0);
6196
6197 for (i = 0; i < 8; i++)
616847e7 6198 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6199
6200 /* Enable PMON + select events */
6201 I915_WRITE(ECR, 0x80000019);
6202
6203 lcfuse = I915_READ(LCFUSE02);
6204
20e4d407 6205 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6206}
6207
ae48434c
ID		 6208void intel_init_gt_powersave(struct drm_device *dev)
6209{
e6069ca8
ID		 6210 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6211
38807746
D		 6212 if (IS_CHERRYVIEW(dev))
6213 cherryview_init_gt_powersave(dev);
6214 else if (IS_VALLEYVIEW(dev))
4e80519e 6215 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6216}
6217
6218void intel_cleanup_gt_powersave(struct drm_device *dev)
6219{
38807746
D		 6220 if (IS_CHERRYVIEW(dev))
6221 return;
6222 else if (IS_VALLEYVIEW(dev))
4e80519e 6223 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6224}
6225
dbea3cea
ID		 6226static void gen6_suspend_rps(struct drm_device *dev)
6227{
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229
6230 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6231
4c2a8897 6232 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6233}
6234
156c7ca0
JB		 6235/**
6236 * intel_suspend_gt_powersave - suspend PM work and helper threads
6237 * @dev: drm device
6238 *
6239 * We don't want to disable RC6 or other features here, we just want
6240 * to make sure any work we've queued has finished and won't bother
6241 * us while we're suspended.
6242 */
6243void intel_suspend_gt_powersave(struct drm_device *dev)
6244{
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246
d4d70aa5
ID		 6247 if (INTEL_INFO(dev)->gen < 6)
6248 return;
6249
dbea3cea 6250 gen6_suspend_rps(dev);
b47adc17
D		 6251
6252 /* Force GPU to min freq during suspend */
6253 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6254}
6255
8090c6b9
DV		 6256void intel_disable_gt_powersave(struct drm_device *dev)
6257{
1a01ab3b
JB		 6258 struct drm_i915_private *dev_priv = dev->dev_private;
6259
930ebb46 6260 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6261 ironlake_disable_drps(dev);
38807746 6262 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6263 intel_suspend_gt_powersave(dev);
e494837a 6264
4fc688ce 6265 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6266 if (INTEL_INFO(dev)->gen >= 9)
6267 gen9_disable_rps(dev);
6268 else if (IS_CHERRYVIEW(dev))
38807746
D		 6269 cherryview_disable_rps(dev);
6270 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6271 valleyview_disable_rps(dev);
6272 else
6273 gen6_disable_rps(dev);
e534770a 6274
c0951f0c 6275 dev_priv->rps.enabled = false;
4fc688ce 6276 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6277 }
8090c6b9
DV		 6278}
6279
1a01ab3b
JB		 6280static void intel_gen6_powersave_work(struct work_struct *work)
6281{
6282 struct drm_i915_private *dev_priv =
6283 container_of(work, struct drm_i915_private,
6284 rps.delayed_resume_work.work);
6285 struct drm_device *dev = dev_priv->dev;
6286
4fc688ce 6287 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6288
4c2a8897 6289 gen6_reset_rps_interrupts(dev);
3cc134e3 6290
38807746
D		 6291 if (IS_CHERRYVIEW(dev)) {
6292 cherryview_enable_rps(dev);
6293 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6294 valleyview_enable_rps(dev);
20e49366 6295 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6296 gen9_enable_rc6(dev);
20e49366 6297 gen9_enable_rps(dev);
cc017fb4
AG		 6298 if (IS_SKYLAKE(dev))
6299 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6300 } else if (IS_BROADWELL(dev)) {
6301 gen8_enable_rps(dev);
c2bc2fc5 6302 __gen6_update_ring_freq(dev);
0a073b84
JB		 6303 } else {
6304 gen6_enable_rps(dev);
c2bc2fc5 6305 __gen6_update_ring_freq(dev);
0a073b84 6306 }
aed242ff
CW		 6307
6308 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6309 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6310
6311 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6312 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6313
c0951f0c 6314 dev_priv->rps.enabled = true;
3cc134e3 6315
4c2a8897 6316 gen6_enable_rps_interrupts(dev);
3cc134e3 6317
4fc688ce 6318 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6319
6320 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6321}
6322
8090c6b9
DV		 6323void intel_enable_gt_powersave(struct drm_device *dev)
6324{
1a01ab3b
JB		 6325 struct drm_i915_private *dev_priv = dev->dev_private;
6326
f61018b1
YZ		 6327 /* Powersaving is controlled by the host when inside a VM */
6328 if (intel_vgpu_active(dev))
6329 return;
6330
8090c6b9 6331 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6332 mutex_lock(&dev->struct_mutex);
8090c6b9 6333 ironlake_enable_drps(dev);
8090c6b9 6334 intel_init_emon(dev);
dc1d0136 6335 mutex_unlock(&dev->struct_mutex);
38807746 6336 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6337 /*
6338 * PCU communication is slow and this doesn't need to be
6339 * done at any specific time, so do this out of our fast path
6340 * to make resume and init faster.
c6df39b5
ID		 6341 *
6342 * We depend on the HW RC6 power context save/restore
6343 * mechanism when entering D3 through runtime PM suspend. So
6344 * disable RPM until RPS/RC6 is properly setup. We can only
6345 * get here via the driver load/system resume/runtime resume
6346 * paths, so the _noresume version is enough (and in case of
6347 * runtime resume it's necessary).
1a01ab3b 6348 */
c6df39b5
ID		 6349 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6350 round_jiffies_up_relative(HZ)))
6351 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6352 }
6353}
6354
c6df39b5
ID		 6355void intel_reset_gt_powersave(struct drm_device *dev)
6356{
6357 struct drm_i915_private *dev_priv = dev->dev_private;
6358
dbea3cea
ID		 6359 if (INTEL_INFO(dev)->gen < 6)
6360 return;
6361
6362 gen6_suspend_rps(dev);
c6df39b5 6363 dev_priv->rps.enabled = false;
c6df39b5
ID		 6364}
6365
3107bd48
DV		 6366static void ibx_init_clock_gating(struct drm_device *dev)
6367{
6368 struct drm_i915_private *dev_priv = dev->dev_private;
6369
6370 /*
6371 * On Ibex Peak and Cougar Point, we need to disable clock
6372 * gating for the panel power sequencer or it will fail to
6373 * start up when no ports are active.
6374 */
6375 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6376}
6377
0e088b8f
VS		 6378static void g4x_disable_trickle_feed(struct drm_device *dev)
6379{
6380 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6381 enum pipe pipe;
0e088b8f 6382
055e393f 6383 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6384 I915_WRITE(DSPCNTR(pipe),
6385 I915_READ(DSPCNTR(pipe)) |
6386 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6387
6388 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6389 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6390 }
6391}
6392
017636cc
VS		 6393static void ilk_init_lp_watermarks(struct drm_device *dev)
6394{
6395 struct drm_i915_private *dev_priv = dev->dev_private;
6396
6397 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6398 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6399 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6400
6401 /*
6402 * Don't touch WM1S_LP_EN here.
6403 * Doing so could cause underruns.
6404 */
6405}
6406
1fa61106 6407static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6408{
6409 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6410 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6411
f1e8fa56
DL		 6412 /*
6413 * Required for FBC
6414 * WaFbcDisableDpfcClockGating:ilk
6415 */
4d47e4f5
DL		 6416 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6417 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6418 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6419
6420 I915_WRITE(PCH_3DCGDIS0,
6421 MARIUNIT_CLOCK_GATE_DISABLE |
6422 SVSMUNIT_CLOCK_GATE_DISABLE);
6423 I915_WRITE(PCH_3DCGDIS1,
6424 VFMUNIT_CLOCK_GATE_DISABLE);
6425
6f1d69b0
ED		 6426 /*
6427 * According to the spec the following bits should be set in
6428 * order to enable memory self-refresh
6429 * The bit 22/21 of 0x42004
6430 * The bit 5 of 0x42020
6431 * The bit 15 of 0x45000
6432 */
6433 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6434 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6435 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6436 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6437 I915_WRITE(DISP_ARB_CTL,
6438 (I915_READ(DISP_ARB_CTL) |
6439 DISP_FBC_WM_DIS));
017636cc
VS		 6440
6441 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6442
6443 /*
6444 * Based on the document from hardware guys the following bits
6445 * should be set unconditionally in order to enable FBC.
6446 * The bit 22 of 0x42000
6447 * The bit 22 of 0x42004
6448 * The bit 7,8,9 of 0x42020.
6449 */
6450 if (IS_IRONLAKE_M(dev)) {
4bb35334 6451 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6452 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6453 I915_READ(ILK_DISPLAY_CHICKEN1) |
6454 ILK_FBCQ_DIS);
6455 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6456 I915_READ(ILK_DISPLAY_CHICKEN2) |
6457 ILK_DPARB_GATE);
6f1d69b0
ED		 6458 }
6459
4d47e4f5
DL		 6460 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6461
6f1d69b0
ED		 6462 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6463 I915_READ(ILK_DISPLAY_CHICKEN2) |
6464 ILK_ELPIN_409_SELECT);
6465 I915_WRITE(_3D_CHICKEN2,
6466 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6467 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6468
ecdb4eb7 6469 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6470 I915_WRITE(CACHE_MODE_0,
6471 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6472
4e04632e
AG		 6473 /* WaDisable_RenderCache_OperationalFlush:ilk */
6474 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6475
0e088b8f 6476 g4x_disable_trickle_feed(dev);
bdad2b2f 6477
3107bd48
DV		 6478 ibx_init_clock_gating(dev);
6479}
6480
6481static void cpt_init_clock_gating(struct drm_device *dev)
6482{
6483 struct drm_i915_private *dev_priv = dev->dev_private;
6484 int pipe;
3f704fa2 6485 uint32_t val;
3107bd48
DV		 6486
6487 /*
6488 * On Ibex Peak and Cougar Point, we need to disable clock
6489 * gating for the panel power sequencer or it will fail to
6490 * start up when no ports are active.
6491 */
cd664078
JB		 6492 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6493 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6494 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6495 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6496 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6497 /* The below fixes the weird display corruption, a few pixels shifted
6498 * downward, on (only) LVDS of some HP laptops with IVY.
6499 */
055e393f 6500 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6501 val = I915_READ(TRANS_CHICKEN2(pipe));
6502 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6503 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6504 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6505 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6506 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6507 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6508 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6509 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6510 }
3107bd48 6511 /* WADP0ClockGatingDisable */
055e393f 6512 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6513 I915_WRITE(TRANS_CHICKEN1(pipe),
6514 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6515 }
6f1d69b0
ED		 6516}
6517
1d7aaa0c
DV		 6518static void gen6_check_mch_setup(struct drm_device *dev)
6519{
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521 uint32_t tmp;
6522
6523 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6524 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6525 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6526 tmp);
1d7aaa0c
DV		 6527}
6528
1fa61106 6529static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6530{
6531 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6532 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6533
231e54f6 6534 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6535
6536 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6537 I915_READ(ILK_DISPLAY_CHICKEN2) |
6538 ILK_ELPIN_409_SELECT);
6539
ecdb4eb7 6540 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6541 I915_WRITE(_3D_CHICKEN,
6542 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6543
4e04632e
AG		 6544 /* WaDisable_RenderCache_OperationalFlush:snb */
6545 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6546
8d85d272
VS		 6547 /*
6548 * BSpec recoomends 8x4 when MSAA is used,
6549 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6550 *
6551 * Note that PS/WM thread counts depend on the WIZ hashing
6552 * disable bit, which we don't touch here, but it's good
6553 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6554 */
6555 I915_WRITE(GEN6_GT_MODE,
98533251 6556 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6557
017636cc 6558 ilk_init_lp_watermarks(dev);
6f1d69b0 6559
6f1d69b0 6560 I915_WRITE(CACHE_MODE_0,
50743298 6561 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6562
6563 I915_WRITE(GEN6_UCGCTL1,
6564 I915_READ(GEN6_UCGCTL1) |
6565 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6566 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6567
6568 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6569 * gating disable must be set. Failure to set it results in
6570 * flickering pixels due to Z write ordering failures after
6571 * some amount of runtime in the Mesa "fire" demo, and Unigine
6572 * Sanctuary and Tropics, and apparently anything else with
6573 * alpha test or pixel discard.
6574 *
6575 * According to the spec, bit 11 (RCCUNIT) must also be set,
6576 * but we didn't debug actual testcases to find it out.
0f846f81 6577 *
ef59318c
VS		 6578 * WaDisableRCCUnitClockGating:snb
6579 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6580 */
6581 I915_WRITE(GEN6_UCGCTL2,
6582 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6583 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6584
5eb146dd 6585 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6586 I915_WRITE(_3D_CHICKEN3,
6587 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6588
e927ecde
VS		 6589 /*
6590 * Bspec says:
6591 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6592 * 3DSTATE_SF number of SF output attributes is more than 16."
6593 */
6594 I915_WRITE(_3D_CHICKEN3,
6595 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6596
6f1d69b0
ED		 6597 /*
6598 * According to the spec the following bits should be
6599 * set in order to enable memory self-refresh and fbc:
6600 * The bit21 and bit22 of 0x42000
6601 * The bit21 and bit22 of 0x42004
6602 * The bit5 and bit7 of 0x42020
6603 * The bit14 of 0x70180
6604 * The bit14 of 0x71180
4bb35334
DL		 6605 *
6606 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6607 */
6608 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6609 I915_READ(ILK_DISPLAY_CHICKEN1) |
6610 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6611 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6612 I915_READ(ILK_DISPLAY_CHICKEN2) |
6613 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6614 I915_WRITE(ILK_DSPCLK_GATE_D,
6615 I915_READ(ILK_DSPCLK_GATE_D) |
6616 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6617 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6618
0e088b8f 6619 g4x_disable_trickle_feed(dev);
f8f2ac9a 6620
3107bd48 6621 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6622
6623 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6624}
6625
6626static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6627{
6628 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6629
3aad9059 6630 /*
46680e0a 6631 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6632 *
6633 * This actually overrides the dispatch
6634 * mode for all thread types.
6635 */
6f1d69b0
ED		 6636 reg &= ~GEN7_FF_SCHED_MASK;
6637 reg |= GEN7_FF_TS_SCHED_HW;
6638 reg |= GEN7_FF_VS_SCHED_HW;
6639 reg |= GEN7_FF_DS_SCHED_HW;
6640
6641 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6642}
6643
17a303ec
PZ		 6644static void lpt_init_clock_gating(struct drm_device *dev)
6645{
6646 struct drm_i915_private *dev_priv = dev->dev_private;
6647
6648 /*
6649 * TODO: this bit should only be enabled when really needed, then
6650 * disabled when not needed anymore in order to save power.
6651 */
c2699524 6652 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6653 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6654 I915_READ(SOUTH_DSPCLK_GATE_D) |
6655 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6656
6657 /* WADPOClockGatingDisable:hsw */
6658 I915_WRITE(_TRANSA_CHICKEN1,
6659 I915_READ(_TRANSA_CHICKEN1) |
6660 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6661}
6662
7d708ee4
ID		 6663static void lpt_suspend_hw(struct drm_device *dev)
6664{
6665 struct drm_i915_private *dev_priv = dev->dev_private;
6666
c2699524 6667 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6668 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6669
6670 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6671 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6672 }
6673}
6674
47c2bd97 6675static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6676{
6677 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6678 enum pipe pipe;
4d487cff 6679 uint32_t misccpctl;
1020a5c2 6680
7ad0dbab 6681 ilk_init_lp_watermarks(dev);
50ed5fbd 6682
ab57fff1 6683 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6684 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6685
ab57fff1 6686 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6687 I915_WRITE(CHICKEN_PAR1_1,
6688 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6689
ab57fff1 6690 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6691 for_each_pipe(dev_priv, pipe) {
07d27e20 6692 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6693 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6694 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6695 }
63801f21 6696
ab57fff1
BW		 6697 /* WaVSRefCountFullforceMissDisable:bdw */
6698 /* WaDSRefCountFullforceMissDisable:bdw */
6699 I915_WRITE(GEN7_FF_THREAD_MODE,
6700 I915_READ(GEN7_FF_THREAD_MODE) &
6701 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6702
295e8bb7
VS		 6703 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6704 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6705
6706 /* WaDisableSDEUnitClockGating:bdw */
6707 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6708 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6709
4d487cff
VS		 6710 /*
6711 * WaProgramL3SqcReg1Default:bdw
6712 * WaTempDisableDOPClkGating:bdw
6713 */
6714 misccpctl = I915_READ(GEN7_MISCCPCTL);
6715 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6716 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6717 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6718
6d50b065
VS		 6719 /*
6720 * WaGttCachingOffByDefault:bdw
6721 * GTT cache may not work with big pages, so if those
6722 * are ever enabled GTT cache may need to be disabled.
6723 */
6724 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6725
89d6b2b8 6726 lpt_init_clock_gating(dev);
1020a5c2
BW		 6727}
6728
cad2a2d7
ED		 6729static void haswell_init_clock_gating(struct drm_device *dev)
6730{
6731 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6732
017636cc 6733 ilk_init_lp_watermarks(dev);
cad2a2d7 6734
f3fc4884
FJ		 6735 /* L3 caching of data atomics doesn't work -- disable it. */
6736 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6737 I915_WRITE(HSW_ROW_CHICKEN3,
6738 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6739
ecdb4eb7 6740 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6741 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6742 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6743 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6744
e36ea7ff
VS		 6745 /* WaVSRefCountFullforceMissDisable:hsw */
6746 I915_WRITE(GEN7_FF_THREAD_MODE,
6747 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6748
4e04632e
AG		 6749 /* WaDisable_RenderCache_OperationalFlush:hsw */
6750 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6751
fe27c606
CW		 6752 /* enable HiZ Raw Stall Optimization */
6753 I915_WRITE(CACHE_MODE_0_GEN7,
6754 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6755
ecdb4eb7 6756 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6757 I915_WRITE(CACHE_MODE_1,
6758 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6759
a12c4967
VS		 6760 /*
6761 * BSpec recommends 8x4 when MSAA is used,
6762 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6763 *
6764 * Note that PS/WM thread counts depend on the WIZ hashing
6765 * disable bit, which we don't touch here, but it's good
6766 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6767 */
6768 I915_WRITE(GEN7_GT_MODE,
98533251 6769 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6770
94411593
KG		 6771 /* WaSampleCChickenBitEnable:hsw */
6772 I915_WRITE(HALF_SLICE_CHICKEN3,
6773 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6774
ecdb4eb7 6775 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6776 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6777
90a88643
PZ		 6778 /* WaRsPkgCStateDisplayPMReq:hsw */
6779 I915_WRITE(CHICKEN_PAR1_1,
6780 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6781
17a303ec 6782 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6783}
6784
1fa61106 6785static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6786{
6787 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6788 uint32_t snpcr;
6f1d69b0 6789
017636cc 6790 ilk_init_lp_watermarks(dev);
6f1d69b0 6791
231e54f6 6792 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6793
ecdb4eb7 6794 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6795 I915_WRITE(_3D_CHICKEN3,
6796 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6797
ecdb4eb7 6798 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6799 I915_WRITE(IVB_CHICKEN3,
6800 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6801 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6802
ecdb4eb7 6803 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6804 if (IS_IVB_GT1(dev))
6805 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6806 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6807
4e04632e
AG		 6808 /* WaDisable_RenderCache_OperationalFlush:ivb */
6809 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6810
ecdb4eb7 6811 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6812 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6813 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6814
ecdb4eb7 6815 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6816 I915_WRITE(GEN7_L3CNTLREG1,
6817 GEN7_WA_FOR_GEN7_L3_CONTROL);
6818 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6819 GEN7_WA_L3_CHICKEN_MODE);
6820 if (IS_IVB_GT1(dev))
6821 I915_WRITE(GEN7_ROW_CHICKEN2,
6822 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6823 else {
6824 /* must write both registers */
6825 I915_WRITE(GEN7_ROW_CHICKEN2,
6826 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6827 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6828 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6829 }
6f1d69b0 6830
ecdb4eb7 6831 /* WaForceL3Serialization:ivb */
61939d97
JB		 6832 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6833 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6834
1b80a19a 6835 /*
0f846f81 6836 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6837 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6838 */
6839 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6840 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6841
ecdb4eb7 6842 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6843 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6844 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6845 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6846
0e088b8f 6847 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6848
6849 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6850
22721343
CW		 6851 if (0) { /* causes HiZ corruption on ivb:gt1 */
6852 /* enable HiZ Raw Stall Optimization */
6853 I915_WRITE(CACHE_MODE_0_GEN7,
6854 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6855 }
116f2b6d 6856
ecdb4eb7 6857 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6858 I915_WRITE(CACHE_MODE_1,
6859 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6860
a607c1a4
VS		 6861 /*
6862 * BSpec recommends 8x4 when MSAA is used,
6863 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6864 *
6865 * Note that PS/WM thread counts depend on the WIZ hashing
6866 * disable bit, which we don't touch here, but it's good
6867 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6868 */
6869 I915_WRITE(GEN7_GT_MODE,
98533251 6870 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6871
20848223
BW		 6872 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6873 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6874 snpcr |= GEN6_MBC_SNPCR_MED;
6875 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6876
ab5c608b
BW		 6877 if (!HAS_PCH_NOP(dev))
6878 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6879
6880 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6881}
6882
c6beb13e
VS		 6883static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6884{
6885 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6886
6887 /*
6888 * Disable trickle feed and enable pnd deadline calculation
6889 */
6890 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6891 I915_WRITE(CBR1_VLV, 0);
6892}
6893
1fa61106 6894static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6895{
6896 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6897
c6beb13e 6898 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6899
ecdb4eb7 6900 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6901 I915_WRITE(_3D_CHICKEN3,
6902 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6903
ecdb4eb7 6904 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6905 I915_WRITE(IVB_CHICKEN3,
6906 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6907 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6908
fad7d36e 6909 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6910 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6911 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6912 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6913 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6914
4e04632e
AG		 6915 /* WaDisable_RenderCache_OperationalFlush:vlv */
6916 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6917
ecdb4eb7 6918 /* WaForceL3Serialization:vlv */
61939d97
JB		 6919 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6920 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6921
ecdb4eb7 6922 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6923 I915_WRITE(GEN7_ROW_CHICKEN2,
6924 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6925
ecdb4eb7 6926 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6927 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6928 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6929 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6930
46680e0a
VS		 6931 gen7_setup_fixed_func_scheduler(dev_priv);
6932
3c0edaeb 6933 /*
0f846f81 6934 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6935 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6936 */
6937 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6938 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6939
c98f5062
AG		 6940 /* WaDisableL3Bank2xClockGate:vlv
6941 * Disabling L3 clock gating- MMIO 940c[25] = 1
6942 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6943 I915_WRITE(GEN7_UCGCTL4,
6944 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6945
afd58e79
VS		 6946 /*
6947 * BSpec says this must be set, even though
6948 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6949 */
6b26c86d
DV		 6950 I915_WRITE(CACHE_MODE_1,
6951 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6952
da2518f9
VS		 6953 /*
6954 * BSpec recommends 8x4 when MSAA is used,
6955 * however in practice 16x4 seems fastest.
6956 *
6957 * Note that PS/WM thread counts depend on the WIZ hashing
6958 * disable bit, which we don't touch here, but it's good
6959 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6960 */
6961 I915_WRITE(GEN7_GT_MODE,
6962 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6963
031994ee
VS		 6964 /*
6965 * WaIncreaseL3CreditsForVLVB0:vlv
6966 * This is the hardware default actually.
6967 */
6968 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6969
2d809570 6970 /*
ecdb4eb7 6971 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6972 * Disable clock gating on th GCFG unit to prevent a delay
6973 * in the reporting of vblank events.
6974 */
7a0d1eed 6975 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6976}
6977
a4565da8
VS		 6978static void cherryview_init_clock_gating(struct drm_device *dev)
6979{
6980 struct drm_i915_private *dev_priv = dev->dev_private;
6981
c6beb13e 6982 vlv_init_display_clock_gating(dev_priv);
dd811e70 6983
232ce337
VS		 6984 /* WaVSRefCountFullforceMissDisable:chv */
6985 /* WaDSRefCountFullforceMissDisable:chv */
6986 I915_WRITE(GEN7_FF_THREAD_MODE,
6987 I915_READ(GEN7_FF_THREAD_MODE) &
6988 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6989
6990 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6991 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6992 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6993
6994 /* WaDisableCSUnitClockGating:chv */
6995 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6996 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6997
6998 /* WaDisableSDEUnitClockGating:chv */
6999 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7000 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 7001
7002 /*
7003 * GTT cache may not work with big pages, so if those
7004 * are ever enabled GTT cache may need to be disabled.
7005 */
7006 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7007}
7008
1fa61106 7009static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7010{
7011 struct drm_i915_private *dev_priv = dev->dev_private;
7012 uint32_t dspclk_gate;
7013
7014 I915_WRITE(RENCLK_GATE_D1, 0);
7015 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7016 GS_UNIT_CLOCK_GATE_DISABLE |
7017 CL_UNIT_CLOCK_GATE_DISABLE);
7018 I915_WRITE(RAMCLK_GATE_D, 0);
7019 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7020 OVRUNIT_CLOCK_GATE_DISABLE |
7021 OVCUNIT_CLOCK_GATE_DISABLE;
7022 if (IS_GM45(dev))
7023 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7024 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7025
7026 /* WaDisableRenderCachePipelinedFlush */
7027 I915_WRITE(CACHE_MODE_0,
7028 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7029
4e04632e
AG		 7030 /* WaDisable_RenderCache_OperationalFlush:g4x */
7031 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7032
0e088b8f 7033 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7034}
7035
1fa61106 7036static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7037{
7038 struct drm_i915_private *dev_priv = dev->dev_private;
7039
7040 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7041 I915_WRITE(RENCLK_GATE_D2, 0);
7042 I915_WRITE(DSPCLK_GATE_D, 0);
7043 I915_WRITE(RAMCLK_GATE_D, 0);
7044 I915_WRITE16(DEUC, 0);
20f94967
VS		 7045 I915_WRITE(MI_ARB_STATE,
7046 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7047
7048 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7049 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7050}
7051
1fa61106 7052static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7053{
7054 struct drm_i915_private *dev_priv = dev->dev_private;
7055
7056 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7057 I965_RCC_CLOCK_GATE_DISABLE |
7058 I965_RCPB_CLOCK_GATE_DISABLE |
7059 I965_ISC_CLOCK_GATE_DISABLE |
7060 I965_FBC_CLOCK_GATE_DISABLE);
7061 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7062 I915_WRITE(MI_ARB_STATE,
7063 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7064
7065 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7066 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7067}
7068
1fa61106 7069static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7070{
7071 struct drm_i915_private *dev_priv = dev->dev_private;
7072 u32 dstate = I915_READ(D_STATE);
7073
7074 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7075 DSTATE_DOT_CLOCK_GATING;
7076 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7077
7078 if (IS_PINEVIEW(dev))
7079 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7080
7081 /* IIR "flip pending" means done if this bit is set */
7082 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7083
7084 /* interrupts should cause a wake up from C3 */
3299254f 7085 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7086
7087 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7088 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7089
7090 I915_WRITE(MI_ARB_STATE,
7091 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7092}
7093
1fa61106 7094static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7095{
7096 struct drm_i915_private *dev_priv = dev->dev_private;
7097
7098 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7099
7100 /* interrupts should cause a wake up from C3 */
7101 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7102 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7103
7104 I915_WRITE(MEM_MODE,
7105 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7106}
7107
1fa61106 7108static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7109{
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111
7112 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7113
7114 I915_WRITE(MEM_MODE,
7115 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7116 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7117}
7118
6f1d69b0
ED		 7119void intel_init_clock_gating(struct drm_device *dev)
7120{
7121 struct drm_i915_private *dev_priv = dev->dev_private;
7122
c57e3551
DL		 7123 if (dev_priv->display.init_clock_gating)
7124 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7125}
7126
7d708ee4
ID		 7127void intel_suspend_hw(struct drm_device *dev)
7128{
7129 if (HAS_PCH_LPT(dev))
7130 lpt_suspend_hw(dev);
7131}
7132
1fa61106
ED		 7133/* Set up chip specific power management-related functions */
7134void intel_init_pm(struct drm_device *dev)
7135{
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7137
7ff0ebcc 7138 intel_fbc_init(dev_priv);
1fa61106 7139
c921aba8
DV		 7140 /* For cxsr */
7141 if (IS_PINEVIEW(dev))
7142 i915_pineview_get_mem_freq(dev);
7143 else if (IS_GEN5(dev))
7144 i915_ironlake_get_mem_freq(dev);
7145
1fa61106 7146 /* For FIFO watermark updates */
f5ed50cb 7147 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7148 skl_setup_wm_latency(dev);
7149
a82abe43
ID		 7150 if (IS_BROXTON(dev))
7151 dev_priv->display.init_clock_gating =
7152 bxt_init_clock_gating;
7153 else if (IS_SKYLAKE(dev))
7154 dev_priv->display.init_clock_gating =
7155 skl_init_clock_gating;
2d41c0b5
PB		 7156 dev_priv->display.update_wm = skl_update_wm;
7157 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 7158 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7159 ilk_setup_wm_latency(dev);
53615a5e 7160
bd602544
VS		 7161 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7162 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7163 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7164 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7165 dev_priv->display.update_wm = ilk_update_wm;
7166 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7167 } else {
7168 DRM_DEBUG_KMS("Failed to read display plane latency. "
7169 "Disable CxSR\n");
7170 }
7171
7172 if (IS_GEN5(dev))
1fa61106 7173 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7174 else if (IS_GEN6(dev))
1fa61106 7175 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7176 else if (IS_IVYBRIDGE(dev))
1fa61106 7177 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7178 else if (IS_HASWELL(dev))
cad2a2d7 7179 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7180 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7181 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7182 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7183 vlv_setup_wm_latency(dev);
7184
7185 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7186 dev_priv->display.init_clock_gating =
7187 cherryview_init_clock_gating;
1fa61106 7188 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7189 vlv_setup_wm_latency(dev);
7190
7191 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7192 dev_priv->display.init_clock_gating =
7193 valleyview_init_clock_gating;
1fa61106
ED		 7194 } else if (IS_PINEVIEW(dev)) {
7195 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7196 dev_priv->is_ddr3,
7197 dev_priv->fsb_freq,
7198 dev_priv->mem_freq)) {
7199 DRM_INFO("failed to find known CxSR latency "
7200 "(found ddr%s fsb freq %d, mem freq %d), "
7201 "disabling CxSR\n",
7202 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7203 dev_priv->fsb_freq, dev_priv->mem_freq);
7204 /* Disable CxSR and never update its watermark again */
5209b1f4 7205 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7206 dev_priv->display.update_wm = NULL;
7207 } else
7208 dev_priv->display.update_wm = pineview_update_wm;
7209 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7210 } else if (IS_G4X(dev)) {
7211 dev_priv->display.update_wm = g4x_update_wm;
7212 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7213 } else if (IS_GEN4(dev)) {
7214 dev_priv->display.update_wm = i965_update_wm;
7215 if (IS_CRESTLINE(dev))
7216 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7217 else if (IS_BROADWATER(dev))
7218 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7219 } else if (IS_GEN3(dev)) {
7220 dev_priv->display.update_wm = i9xx_update_wm;
7221 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7222 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7223 } else if (IS_GEN2(dev)) {
7224 if (INTEL_INFO(dev)->num_pipes == 1) {
7225 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7226 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7227 } else {
7228 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7229 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7230 }
7231
7232 if (IS_I85X(dev) || IS_I865G(dev))
7233 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7234 else
7235 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7236 } else {
7237 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7238 }
7239}
7240
151a49d0 7241int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7242{
4fc688ce 7243 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7244
7245 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7246 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7247 return -EAGAIN;
7248 }
7249
7250 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7251 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7252 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7253
7254 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7255 500)) {
7256 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7257 return -ETIMEDOUT;
7258 }
7259
7260 *val = I915_READ(GEN6_PCODE_DATA);
7261 I915_WRITE(GEN6_PCODE_DATA, 0);
7262
7263 return 0;
7264}
7265
151a49d0 7266int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7267{
4fc688ce 7268 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7269
7270 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7271 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7272 return -EAGAIN;
7273 }
7274
7275 I915_WRITE(GEN6_PCODE_DATA, val);
7276 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7277
7278 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7279 500)) {
7280 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7281 return -ETIMEDOUT;
7282 }
7283
7284 I915_WRITE(GEN6_PCODE_DATA, 0);
7285
7286 return 0;
7287}
a0e4e199 7288
dd06f88c 7289static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7290{
dd06f88c
VS		 7291 switch (czclk_freq) {
7292 case 200:
7293 return 10;
7294 case 267:
7295 return 12;
7296 case 320:
7297 case 333:
dd06f88c 7298 return 16;
ab3fb157
VS		 7299 case 400:
7300 return 20;
855ba3be
JB		 7301 default:
7302 return -1;
7303 }
dd06f88c 7304}
855ba3be 7305
dd06f88c
VS		 7306static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7307{
7308 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7309
7310 div = vlv_gpu_freq_div(czclk_freq);
7311 if (div < 0)
7312 return div;
7313
7314 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7315}
7316
b55dd647 7317static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7318{
dd06f88c 7319 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 7320
dd06f88c
VS		 7321 mul = vlv_gpu_freq_div(czclk_freq);
7322 if (mul < 0)
7323 return mul;
855ba3be 7324
dd06f88c 7325 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7326}
7327
b55dd647 7328static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7329{
dd06f88c 7330 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7331
dd06f88c
VS		 7332 div = vlv_gpu_freq_div(czclk_freq) / 2;
7333 if (div < 0)
7334 return div;
22b1b2f8 7335
dd06f88c 7336 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7337}
7338
b55dd647 7339static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7340{
dd06f88c 7341 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7342
dd06f88c
VS		 7343 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7344 if (mul < 0)
7345 return mul;
22b1b2f8 7346
1c14762d 7347 /* CHV needs even values */
dd06f88c 7348 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7349}
7350
616bc820 7351int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7352{
80b6dda4
AG		 7353 if (IS_GEN9(dev_priv->dev))
7354 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7355 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7356 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7357 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7358 return byt_gpu_freq(dev_priv, val);
7359 else
7360 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7361}
7362
616bc820
VS		 7363int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7364{
80b6dda4
AG		 7365 if (IS_GEN9(dev_priv->dev))
7366 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7367 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7368 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7369 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7370 return byt_freq_opcode(dev_priv, val);
7371 else
7372 return val / GT_FREQUENCY_MULTIPLIER;
7373}
22b1b2f8 7374
6ad790c0
CW		 7375struct request_boost {
7376 struct work_struct work;
eed29a5b 7377 struct drm_i915_gem_request *req;
6ad790c0
CW		 7378};
7379
7380static void __intel_rps_boost_work(struct work_struct *work)
7381{
7382 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7383 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7384
e61b9958
CW		 7385 if (!i915_gem_request_completed(req, true))
7386 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7387 req->emitted_jiffies);
6ad790c0 7388
e61b9958 7389 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7390 kfree(boost);
7391}
7392
7393void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7394 struct drm_i915_gem_request *req)
6ad790c0
CW		 7395{
7396 struct request_boost *boost;
7397
eed29a5b 7398 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7399 return;
7400
e61b9958
CW		 7401 if (i915_gem_request_completed(req, true))
7402 return;
7403
6ad790c0
CW		 7404 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7405 if (boost == NULL)
7406 return;
7407
eed29a5b
DV		 7408 i915_gem_request_reference(req);
7409 boost->req = req;
6ad790c0
CW		 7410
7411 INIT_WORK(&boost->work, __intel_rps_boost_work);
7412 queue_work(to_i915(dev)->wq, &boost->work);
7413}
7414
f742a552 7415void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7416{
7417 struct drm_i915_private *dev_priv = dev->dev_private;
7418
f742a552 7419 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7420 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7421
907b28c5
CW		 7422 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7423 intel_gen6_powersave_work);
1854d5ca 7424 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7425 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7426 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7427
33688d95 7428 dev_priv->pm.suspended = false;
907b28c5 7429}
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