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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
85208be0 | 33 | |
dc39fff7 BW |
34 | /** |
35 | * RC6 is a special power stage which allows the GPU to enter an very | |
36 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
37 | * stage is entered automatically when the GPU is idle when RC6 support is | |
38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
39 | * | |
40 | * There are different RC6 modes available in Intel GPU, which differentiate | |
41 | * among each other with the latency required to enter and leave RC6 and | |
42 | * voltage consumed by the GPU in different states. | |
43 | * | |
44 | * The combination of the following flags define which states GPU is allowed | |
45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
46 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
48 | * which brings the most power savings; deeper states save more power, but | |
49 | * require higher latency to switch to and wake up. | |
50 | */ | |
51 | #define INTEL_RC6_ENABLE (1<<0) | |
52 | #define INTEL_RC6p_ENABLE (1<<1) | |
53 | #define INTEL_RC6pp_ENABLE (1<<2) | |
54 | ||
a82abe43 ID |
55 | static void bxt_init_clock_gating(struct drm_device *dev) |
56 | { | |
32608ca2 ID |
57 | struct drm_i915_private *dev_priv = dev->dev_private; |
58 | ||
a7546159 NH |
59 | /* WaDisableSDEUnitClockGating:bxt */ |
60 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
61 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
62 | ||
32608ca2 ID |
63 | /* |
64 | * FIXME: | |
868434c5 | 65 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
32608ca2 | 66 | */ |
32608ca2 | 67 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
868434c5 | 68 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
a82abe43 ID |
69 | } |
70 | ||
c921aba8 DV |
71 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
72 | { | |
50227e1c | 73 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
74 | u32 tmp; |
75 | ||
76 | tmp = I915_READ(CLKCFG); | |
77 | ||
78 | switch (tmp & CLKCFG_FSB_MASK) { | |
79 | case CLKCFG_FSB_533: | |
80 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
81 | break; | |
82 | case CLKCFG_FSB_800: | |
83 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
84 | break; | |
85 | case CLKCFG_FSB_667: | |
86 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
87 | break; | |
88 | case CLKCFG_FSB_400: | |
89 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
90 | break; | |
91 | } | |
92 | ||
93 | switch (tmp & CLKCFG_MEM_MASK) { | |
94 | case CLKCFG_MEM_533: | |
95 | dev_priv->mem_freq = 533; | |
96 | break; | |
97 | case CLKCFG_MEM_667: | |
98 | dev_priv->mem_freq = 667; | |
99 | break; | |
100 | case CLKCFG_MEM_800: | |
101 | dev_priv->mem_freq = 800; | |
102 | break; | |
103 | } | |
104 | ||
105 | /* detect pineview DDR3 setting */ | |
106 | tmp = I915_READ(CSHRDDR3CTL); | |
107 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
108 | } | |
109 | ||
110 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
111 | { | |
50227e1c | 112 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
113 | u16 ddrpll, csipll; |
114 | ||
115 | ddrpll = I915_READ16(DDRMPLL1); | |
116 | csipll = I915_READ16(CSIPLL0); | |
117 | ||
118 | switch (ddrpll & 0xff) { | |
119 | case 0xc: | |
120 | dev_priv->mem_freq = 800; | |
121 | break; | |
122 | case 0x10: | |
123 | dev_priv->mem_freq = 1066; | |
124 | break; | |
125 | case 0x14: | |
126 | dev_priv->mem_freq = 1333; | |
127 | break; | |
128 | case 0x18: | |
129 | dev_priv->mem_freq = 1600; | |
130 | break; | |
131 | default: | |
132 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
133 | ddrpll & 0xff); | |
134 | dev_priv->mem_freq = 0; | |
135 | break; | |
136 | } | |
137 | ||
20e4d407 | 138 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
139 | |
140 | switch (csipll & 0x3ff) { | |
141 | case 0x00c: | |
142 | dev_priv->fsb_freq = 3200; | |
143 | break; | |
144 | case 0x00e: | |
145 | dev_priv->fsb_freq = 3733; | |
146 | break; | |
147 | case 0x010: | |
148 | dev_priv->fsb_freq = 4266; | |
149 | break; | |
150 | case 0x012: | |
151 | dev_priv->fsb_freq = 4800; | |
152 | break; | |
153 | case 0x014: | |
154 | dev_priv->fsb_freq = 5333; | |
155 | break; | |
156 | case 0x016: | |
157 | dev_priv->fsb_freq = 5866; | |
158 | break; | |
159 | case 0x018: | |
160 | dev_priv->fsb_freq = 6400; | |
161 | break; | |
162 | default: | |
163 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
164 | csipll & 0x3ff); | |
165 | dev_priv->fsb_freq = 0; | |
166 | break; | |
167 | } | |
168 | ||
169 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 170 | dev_priv->ips.c_m = 0; |
c921aba8 | 171 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 172 | dev_priv->ips.c_m = 1; |
c921aba8 | 173 | } else { |
20e4d407 | 174 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
175 | } |
176 | } | |
177 | ||
b445e3b0 ED |
178 | static const struct cxsr_latency cxsr_latency_table[] = { |
179 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
180 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
181 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
182 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
183 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
184 | ||
185 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
186 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
187 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
188 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
189 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
190 | ||
191 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
192 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
193 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
194 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
195 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
196 | ||
197 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
198 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
199 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
200 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
201 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
202 | ||
203 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
204 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
205 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
206 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
207 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
208 | ||
209 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
210 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
211 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
212 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
213 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
214 | }; | |
215 | ||
63c62275 | 216 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
217 | int is_ddr3, |
218 | int fsb, | |
219 | int mem) | |
220 | { | |
221 | const struct cxsr_latency *latency; | |
222 | int i; | |
223 | ||
224 | if (fsb == 0 || mem == 0) | |
225 | return NULL; | |
226 | ||
227 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
228 | latency = &cxsr_latency_table[i]; | |
229 | if (is_desktop == latency->is_desktop && | |
230 | is_ddr3 == latency->is_ddr3 && | |
231 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
232 | return latency; | |
233 | } | |
234 | ||
235 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
236 | ||
237 | return NULL; | |
238 | } | |
239 | ||
fc1ac8de VS |
240 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
241 | { | |
242 | u32 val; | |
243 | ||
244 | mutex_lock(&dev_priv->rps.hw_lock); | |
245 | ||
246 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
247 | if (enable) | |
248 | val &= ~FORCE_DDR_HIGH_FREQ; | |
249 | else | |
250 | val |= FORCE_DDR_HIGH_FREQ; | |
251 | val &= ~FORCE_DDR_LOW_FREQ; | |
252 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
253 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
254 | ||
255 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
256 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
257 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
258 | ||
259 | mutex_unlock(&dev_priv->rps.hw_lock); | |
260 | } | |
261 | ||
cfb41411 VS |
262 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
263 | { | |
264 | u32 val; | |
265 | ||
266 | mutex_lock(&dev_priv->rps.hw_lock); | |
267 | ||
268 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
269 | if (enable) | |
270 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
271 | else | |
272 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
273 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
274 | ||
275 | mutex_unlock(&dev_priv->rps.hw_lock); | |
276 | } | |
277 | ||
f4998963 VS |
278 | #define FW_WM(value, plane) \ |
279 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
280 | ||
5209b1f4 | 281 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 282 | { |
5209b1f4 ID |
283 | struct drm_device *dev = dev_priv->dev; |
284 | u32 val; | |
b445e3b0 | 285 | |
5209b1f4 ID |
286 | if (IS_VALLEYVIEW(dev)) { |
287 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
a7a6c498 | 288 | POSTING_READ(FW_BLC_SELF_VLV); |
852eb00d | 289 | dev_priv->wm.vlv.cxsr = enable; |
5209b1f4 ID |
290 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
291 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
a7a6c498 | 292 | POSTING_READ(FW_BLC_SELF); |
5209b1f4 ID |
293 | } else if (IS_PINEVIEW(dev)) { |
294 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
295 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
296 | I915_WRITE(DSPFW3, val); | |
a7a6c498 | 297 | POSTING_READ(DSPFW3); |
5209b1f4 ID |
298 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
299 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
300 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
301 | I915_WRITE(FW_BLC_SELF, val); | |
a7a6c498 | 302 | POSTING_READ(FW_BLC_SELF); |
5209b1f4 ID |
303 | } else if (IS_I915GM(dev)) { |
304 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
305 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
306 | I915_WRITE(INSTPM, val); | |
a7a6c498 | 307 | POSTING_READ(INSTPM); |
5209b1f4 ID |
308 | } else { |
309 | return; | |
310 | } | |
b445e3b0 | 311 | |
5209b1f4 ID |
312 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
313 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
314 | } |
315 | ||
fc1ac8de | 316 | |
b445e3b0 ED |
317 | /* |
318 | * Latency for FIFO fetches is dependent on several factors: | |
319 | * - memory configuration (speed, channels) | |
320 | * - chipset | |
321 | * - current MCH state | |
322 | * It can be fairly high in some situations, so here we assume a fairly | |
323 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
324 | * set this value too high, the FIFO will fetch frequently to stay full) | |
325 | * and power consumption (set it too low to save power and we might see | |
326 | * FIFO underruns and display "flicker"). | |
327 | * | |
328 | * A value of 5us seems to be a good balance; safe for very low end | |
329 | * platforms but not overly aggressive on lower latency configs. | |
330 | */ | |
5aef6003 | 331 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 332 | |
b5004720 VS |
333 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
334 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
335 | ||
336 | static int vlv_get_fifo_size(struct drm_device *dev, | |
337 | enum pipe pipe, int plane) | |
338 | { | |
339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
340 | int sprite0_start, sprite1_start, size; | |
341 | ||
342 | switch (pipe) { | |
343 | uint32_t dsparb, dsparb2, dsparb3; | |
344 | case PIPE_A: | |
345 | dsparb = I915_READ(DSPARB); | |
346 | dsparb2 = I915_READ(DSPARB2); | |
347 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
348 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
349 | break; | |
350 | case PIPE_B: | |
351 | dsparb = I915_READ(DSPARB); | |
352 | dsparb2 = I915_READ(DSPARB2); | |
353 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
354 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
355 | break; | |
356 | case PIPE_C: | |
357 | dsparb2 = I915_READ(DSPARB2); | |
358 | dsparb3 = I915_READ(DSPARB3); | |
359 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
360 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
361 | break; | |
362 | default: | |
363 | return 0; | |
364 | } | |
365 | ||
366 | switch (plane) { | |
367 | case 0: | |
368 | size = sprite0_start; | |
369 | break; | |
370 | case 1: | |
371 | size = sprite1_start - sprite0_start; | |
372 | break; | |
373 | case 2: | |
374 | size = 512 - 1 - sprite1_start; | |
375 | break; | |
376 | default: | |
377 | return 0; | |
378 | } | |
379 | ||
380 | DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", | |
381 | pipe_name(pipe), plane == 0 ? "primary" : "sprite", | |
382 | plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), | |
383 | size); | |
384 | ||
385 | return size; | |
386 | } | |
387 | ||
1fa61106 | 388 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
389 | { |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
391 | uint32_t dsparb = I915_READ(DSPARB); | |
392 | int size; | |
393 | ||
394 | size = dsparb & 0x7f; | |
395 | if (plane) | |
396 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
397 | ||
398 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
399 | plane ? "B" : "A", size); | |
400 | ||
401 | return size; | |
402 | } | |
403 | ||
feb56b93 | 404 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
405 | { |
406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
407 | uint32_t dsparb = I915_READ(DSPARB); | |
408 | int size; | |
409 | ||
410 | size = dsparb & 0x1ff; | |
411 | if (plane) | |
412 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
413 | size >>= 1; /* Convert to cachelines */ | |
414 | ||
415 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
416 | plane ? "B" : "A", size); | |
417 | ||
418 | return size; | |
419 | } | |
420 | ||
1fa61106 | 421 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
422 | { |
423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
424 | uint32_t dsparb = I915_READ(DSPARB); | |
425 | int size; | |
426 | ||
427 | size = dsparb & 0x7f; | |
428 | size >>= 2; /* Convert to cachelines */ | |
429 | ||
430 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
431 | plane ? "B" : "A", | |
432 | size); | |
433 | ||
434 | return size; | |
435 | } | |
436 | ||
b445e3b0 ED |
437 | /* Pineview has different values for various configs */ |
438 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
439 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
440 | .max_wm = PINEVIEW_MAX_WM, | |
441 | .default_wm = PINEVIEW_DFT_WM, | |
442 | .guard_size = PINEVIEW_GUARD_WM, | |
443 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
444 | }; |
445 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
446 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
447 | .max_wm = PINEVIEW_MAX_WM, | |
448 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
449 | .guard_size = PINEVIEW_GUARD_WM, | |
450 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
451 | }; |
452 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
453 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
454 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
455 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
456 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
457 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
458 | }; |
459 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
460 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
461 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
462 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
463 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
464 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
465 | }; |
466 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
467 | .fifo_size = G4X_FIFO_SIZE, |
468 | .max_wm = G4X_MAX_WM, | |
469 | .default_wm = G4X_MAX_WM, | |
470 | .guard_size = 2, | |
471 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
472 | }; |
473 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
474 | .fifo_size = I965_CURSOR_FIFO, |
475 | .max_wm = I965_CURSOR_MAX_WM, | |
476 | .default_wm = I965_CURSOR_DFT_WM, | |
477 | .guard_size = 2, | |
478 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
479 | }; |
480 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
481 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
482 | .max_wm = VALLEYVIEW_MAX_WM, | |
483 | .default_wm = VALLEYVIEW_MAX_WM, | |
484 | .guard_size = 2, | |
485 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
486 | }; |
487 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
488 | .fifo_size = I965_CURSOR_FIFO, |
489 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
490 | .default_wm = I965_CURSOR_DFT_WM, | |
491 | .guard_size = 2, | |
492 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
493 | }; |
494 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
495 | .fifo_size = I965_CURSOR_FIFO, |
496 | .max_wm = I965_CURSOR_MAX_WM, | |
497 | .default_wm = I965_CURSOR_DFT_WM, | |
498 | .guard_size = 2, | |
499 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
500 | }; |
501 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
502 | .fifo_size = I945_FIFO_SIZE, |
503 | .max_wm = I915_MAX_WM, | |
504 | .default_wm = 1, | |
505 | .guard_size = 2, | |
506 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
507 | }; |
508 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
509 | .fifo_size = I915_FIFO_SIZE, |
510 | .max_wm = I915_MAX_WM, | |
511 | .default_wm = 1, | |
512 | .guard_size = 2, | |
513 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 514 | }; |
9d539105 | 515 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
516 | .fifo_size = I855GM_FIFO_SIZE, |
517 | .max_wm = I915_MAX_WM, | |
518 | .default_wm = 1, | |
519 | .guard_size = 2, | |
520 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 521 | }; |
9d539105 VS |
522 | static const struct intel_watermark_params i830_bc_wm_info = { |
523 | .fifo_size = I855GM_FIFO_SIZE, | |
524 | .max_wm = I915_MAX_WM/2, | |
525 | .default_wm = 1, | |
526 | .guard_size = 2, | |
527 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
528 | }; | |
feb56b93 | 529 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
530 | .fifo_size = I830_FIFO_SIZE, |
531 | .max_wm = I915_MAX_WM, | |
532 | .default_wm = 1, | |
533 | .guard_size = 2, | |
534 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
535 | }; |
536 | ||
b445e3b0 ED |
537 | /** |
538 | * intel_calculate_wm - calculate watermark level | |
539 | * @clock_in_khz: pixel clock | |
540 | * @wm: chip FIFO params | |
541 | * @pixel_size: display pixel size | |
542 | * @latency_ns: memory latency for the platform | |
543 | * | |
544 | * Calculate the watermark level (the level at which the display plane will | |
545 | * start fetching from memory again). Each chip has a different display | |
546 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
547 | * in the correct intel_watermark_params structure. | |
548 | * | |
549 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
550 | * on the pixel size. When it reaches the watermark level, it'll start | |
551 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
552 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
553 | * will occur, and a display engine hang could result. | |
554 | */ | |
555 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
556 | const struct intel_watermark_params *wm, | |
557 | int fifo_size, | |
558 | int pixel_size, | |
559 | unsigned long latency_ns) | |
560 | { | |
561 | long entries_required, wm_size; | |
562 | ||
563 | /* | |
564 | * Note: we need to make sure we don't overflow for various clock & | |
565 | * latency values. | |
566 | * clocks go from a few thousand to several hundred thousand. | |
567 | * latency is usually a few thousand | |
568 | */ | |
569 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
570 | 1000; | |
571 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
572 | ||
573 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
574 | ||
575 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
576 | ||
577 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
578 | ||
579 | /* Don't promote wm_size to unsigned... */ | |
580 | if (wm_size > (long)wm->max_wm) | |
581 | wm_size = wm->max_wm; | |
582 | if (wm_size <= 0) | |
583 | wm_size = wm->default_wm; | |
d6feb196 VS |
584 | |
585 | /* | |
586 | * Bspec seems to indicate that the value shouldn't be lower than | |
587 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
588 | * Lets go for 8 which is the burst size since certain platforms | |
589 | * already use a hardcoded 8 (which is what the spec says should be | |
590 | * done). | |
591 | */ | |
592 | if (wm_size <= 8) | |
593 | wm_size = 8; | |
594 | ||
b445e3b0 ED |
595 | return wm_size; |
596 | } | |
597 | ||
598 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
599 | { | |
600 | struct drm_crtc *crtc, *enabled = NULL; | |
601 | ||
70e1e0ec | 602 | for_each_crtc(dev, crtc) { |
3490ea5d | 603 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
604 | if (enabled) |
605 | return NULL; | |
606 | enabled = crtc; | |
607 | } | |
608 | } | |
609 | ||
610 | return enabled; | |
611 | } | |
612 | ||
46ba614c | 613 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 614 | { |
46ba614c | 615 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
616 | struct drm_i915_private *dev_priv = dev->dev_private; |
617 | struct drm_crtc *crtc; | |
618 | const struct cxsr_latency *latency; | |
619 | u32 reg; | |
620 | unsigned long wm; | |
621 | ||
622 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
623 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
624 | if (!latency) { | |
625 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 626 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
627 | return; |
628 | } | |
629 | ||
630 | crtc = single_enabled_crtc(dev); | |
631 | if (crtc) { | |
7c5f93b0 | 632 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
59bea882 | 633 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
7c5f93b0 | 634 | int clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
635 | |
636 | /* Display SR */ | |
637 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
638 | pineview_display_wm.fifo_size, | |
639 | pixel_size, latency->display_sr); | |
640 | reg = I915_READ(DSPFW1); | |
641 | reg &= ~DSPFW_SR_MASK; | |
f4998963 | 642 | reg |= FW_WM(wm, SR); |
b445e3b0 ED |
643 | I915_WRITE(DSPFW1, reg); |
644 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
645 | ||
646 | /* cursor SR */ | |
647 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
648 | pineview_display_wm.fifo_size, | |
649 | pixel_size, latency->cursor_sr); | |
650 | reg = I915_READ(DSPFW3); | |
651 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
f4998963 | 652 | reg |= FW_WM(wm, CURSOR_SR); |
b445e3b0 ED |
653 | I915_WRITE(DSPFW3, reg); |
654 | ||
655 | /* Display HPLL off SR */ | |
656 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
657 | pineview_display_hplloff_wm.fifo_size, | |
658 | pixel_size, latency->display_hpll_disable); | |
659 | reg = I915_READ(DSPFW3); | |
660 | reg &= ~DSPFW_HPLL_SR_MASK; | |
f4998963 | 661 | reg |= FW_WM(wm, HPLL_SR); |
b445e3b0 ED |
662 | I915_WRITE(DSPFW3, reg); |
663 | ||
664 | /* cursor HPLL off SR */ | |
665 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
666 | pineview_display_hplloff_wm.fifo_size, | |
667 | pixel_size, latency->cursor_hpll_disable); | |
668 | reg = I915_READ(DSPFW3); | |
669 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
f4998963 | 670 | reg |= FW_WM(wm, HPLL_CURSOR); |
b445e3b0 ED |
671 | I915_WRITE(DSPFW3, reg); |
672 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
673 | ||
5209b1f4 | 674 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 675 | } else { |
5209b1f4 | 676 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
677 | } |
678 | } | |
679 | ||
680 | static bool g4x_compute_wm0(struct drm_device *dev, | |
681 | int plane, | |
682 | const struct intel_watermark_params *display, | |
683 | int display_latency_ns, | |
684 | const struct intel_watermark_params *cursor, | |
685 | int cursor_latency_ns, | |
686 | int *plane_wm, | |
687 | int *cursor_wm) | |
688 | { | |
689 | struct drm_crtc *crtc; | |
4fe8590a | 690 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
691 | int htotal, hdisplay, clock, pixel_size; |
692 | int line_time_us, line_count; | |
693 | int entries, tlb_miss; | |
694 | ||
695 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 696 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
697 | *cursor_wm = cursor->guard_size; |
698 | *plane_wm = display->guard_size; | |
699 | return false; | |
700 | } | |
701 | ||
6e3c9717 | 702 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 703 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 704 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 705 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 706 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
707 | |
708 | /* Use the small buffer method to calculate plane watermark */ | |
709 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
710 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
711 | if (tlb_miss > 0) | |
712 | entries += tlb_miss; | |
713 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
714 | *plane_wm = entries + display->guard_size; | |
715 | if (*plane_wm > (int)display->max_wm) | |
716 | *plane_wm = display->max_wm; | |
717 | ||
718 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 719 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 720 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
3dd512fb | 721 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
b445e3b0 ED |
722 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
723 | if (tlb_miss > 0) | |
724 | entries += tlb_miss; | |
725 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
726 | *cursor_wm = entries + cursor->guard_size; | |
727 | if (*cursor_wm > (int)cursor->max_wm) | |
728 | *cursor_wm = (int)cursor->max_wm; | |
729 | ||
730 | return true; | |
731 | } | |
732 | ||
733 | /* | |
734 | * Check the wm result. | |
735 | * | |
736 | * If any calculated watermark values is larger than the maximum value that | |
737 | * can be programmed into the associated watermark register, that watermark | |
738 | * must be disabled. | |
739 | */ | |
740 | static bool g4x_check_srwm(struct drm_device *dev, | |
741 | int display_wm, int cursor_wm, | |
742 | const struct intel_watermark_params *display, | |
743 | const struct intel_watermark_params *cursor) | |
744 | { | |
745 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
746 | display_wm, cursor_wm); | |
747 | ||
748 | if (display_wm > display->max_wm) { | |
749 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
750 | display_wm, display->max_wm); | |
751 | return false; | |
752 | } | |
753 | ||
754 | if (cursor_wm > cursor->max_wm) { | |
755 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
756 | cursor_wm, cursor->max_wm); | |
757 | return false; | |
758 | } | |
759 | ||
760 | if (!(display_wm || cursor_wm)) { | |
761 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
762 | return false; | |
763 | } | |
764 | ||
765 | return true; | |
766 | } | |
767 | ||
768 | static bool g4x_compute_srwm(struct drm_device *dev, | |
769 | int plane, | |
770 | int latency_ns, | |
771 | const struct intel_watermark_params *display, | |
772 | const struct intel_watermark_params *cursor, | |
773 | int *display_wm, int *cursor_wm) | |
774 | { | |
775 | struct drm_crtc *crtc; | |
4fe8590a | 776 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
777 | int hdisplay, htotal, pixel_size, clock; |
778 | unsigned long line_time_us; | |
779 | int line_count, line_size; | |
780 | int small, large; | |
781 | int entries; | |
782 | ||
783 | if (!latency_ns) { | |
784 | *display_wm = *cursor_wm = 0; | |
785 | return false; | |
786 | } | |
787 | ||
788 | crtc = intel_get_crtc_for_plane(dev, plane); | |
6e3c9717 | 789 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 790 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 791 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 792 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 793 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 | 794 | |
922044c9 | 795 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
796 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
797 | line_size = hdisplay * pixel_size; | |
798 | ||
799 | /* Use the minimum of the small and large buffer method for primary */ | |
800 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
801 | large = line_count * line_size; | |
802 | ||
803 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
804 | *display_wm = entries + display->guard_size; | |
805 | ||
806 | /* calculate the self-refresh watermark for display cursor */ | |
3dd512fb | 807 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
808 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
809 | *cursor_wm = entries + cursor->guard_size; | |
810 | ||
811 | return g4x_check_srwm(dev, | |
812 | *display_wm, *cursor_wm, | |
813 | display, cursor); | |
814 | } | |
815 | ||
15665979 VS |
816 | #define FW_WM_VLV(value, plane) \ |
817 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
818 | ||
0018fda1 VS |
819 | static void vlv_write_wm_values(struct intel_crtc *crtc, |
820 | const struct vlv_wm_values *wm) | |
821 | { | |
822 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
823 | enum pipe pipe = crtc->pipe; | |
824 | ||
825 | I915_WRITE(VLV_DDL(pipe), | |
826 | (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | | |
827 | (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | | |
828 | (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | | |
829 | (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); | |
830 | ||
ae80152d | 831 | I915_WRITE(DSPFW1, |
15665979 VS |
832 | FW_WM(wm->sr.plane, SR) | |
833 | FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | | |
834 | FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | | |
835 | FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); | |
ae80152d | 836 | I915_WRITE(DSPFW2, |
15665979 VS |
837 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | |
838 | FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | | |
839 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); | |
ae80152d | 840 | I915_WRITE(DSPFW3, |
15665979 | 841 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
842 | |
843 | if (IS_CHERRYVIEW(dev_priv)) { | |
844 | I915_WRITE(DSPFW7_CHV, | |
15665979 VS |
845 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
846 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 847 | I915_WRITE(DSPFW8_CHV, |
15665979 VS |
848 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | |
849 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); | |
ae80152d | 850 | I915_WRITE(DSPFW9_CHV, |
15665979 VS |
851 | FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | |
852 | FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); | |
ae80152d | 853 | I915_WRITE(DSPHOWM, |
15665979 VS |
854 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
855 | FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | | |
856 | FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | | |
857 | FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | | |
858 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
859 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
860 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
861 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
862 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
863 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
864 | } else { |
865 | I915_WRITE(DSPFW7, | |
15665979 VS |
866 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
867 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 868 | I915_WRITE(DSPHOWM, |
15665979 VS |
869 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
870 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
871 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
872 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
873 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
874 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
875 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
876 | } |
877 | ||
2cb389b7 VS |
878 | /* zero (unused) WM1 watermarks */ |
879 | I915_WRITE(DSPFW4, 0); | |
880 | I915_WRITE(DSPFW5, 0); | |
881 | I915_WRITE(DSPFW6, 0); | |
882 | I915_WRITE(DSPHOWM1, 0); | |
883 | ||
ae80152d | 884 | POSTING_READ(DSPFW1); |
0018fda1 VS |
885 | } |
886 | ||
15665979 VS |
887 | #undef FW_WM_VLV |
888 | ||
6eb1a681 VS |
889 | enum vlv_wm_level { |
890 | VLV_WM_LEVEL_PM2, | |
891 | VLV_WM_LEVEL_PM5, | |
892 | VLV_WM_LEVEL_DDR_DVFS, | |
6eb1a681 VS |
893 | }; |
894 | ||
262cd2e1 VS |
895 | /* latency must be in 0.1us units. */ |
896 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, | |
897 | unsigned int pipe_htotal, | |
898 | unsigned int horiz_pixels, | |
899 | unsigned int bytes_per_pixel, | |
900 | unsigned int latency) | |
901 | { | |
902 | unsigned int ret; | |
903 | ||
904 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); | |
905 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
906 | ret = DIV_ROUND_UP(ret, 64); | |
907 | ||
908 | return ret; | |
909 | } | |
910 | ||
911 | static void vlv_setup_wm_latency(struct drm_device *dev) | |
912 | { | |
913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
914 | ||
915 | /* all latencies in usec */ | |
916 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; | |
917 | ||
58590c14 VS |
918 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
919 | ||
262cd2e1 VS |
920 | if (IS_CHERRYVIEW(dev_priv)) { |
921 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; | |
922 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; | |
58590c14 VS |
923 | |
924 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; | |
262cd2e1 VS |
925 | } |
926 | } | |
927 | ||
928 | static uint16_t vlv_compute_wm_level(struct intel_plane *plane, | |
929 | struct intel_crtc *crtc, | |
930 | const struct intel_plane_state *state, | |
931 | int level) | |
932 | { | |
933 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
934 | int clock, htotal, pixel_size, width, wm; | |
935 | ||
936 | if (dev_priv->wm.pri_latency[level] == 0) | |
937 | return USHRT_MAX; | |
938 | ||
939 | if (!state->visible) | |
940 | return 0; | |
941 | ||
942 | pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); | |
943 | clock = crtc->config->base.adjusted_mode.crtc_clock; | |
944 | htotal = crtc->config->base.adjusted_mode.crtc_htotal; | |
945 | width = crtc->config->pipe_src_w; | |
946 | if (WARN_ON(htotal == 0)) | |
947 | htotal = 1; | |
948 | ||
949 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { | |
950 | /* | |
951 | * FIXME the formula gives values that are | |
952 | * too big for the cursor FIFO, and hence we | |
953 | * would never be able to use cursors. For | |
954 | * now just hardcode the watermark. | |
955 | */ | |
956 | wm = 63; | |
957 | } else { | |
958 | wm = vlv_wm_method2(clock, htotal, width, pixel_size, | |
959 | dev_priv->wm.pri_latency[level] * 10); | |
960 | } | |
961 | ||
962 | return min_t(int, wm, USHRT_MAX); | |
963 | } | |
964 | ||
54f1b6e1 VS |
965 | static void vlv_compute_fifo(struct intel_crtc *crtc) |
966 | { | |
967 | struct drm_device *dev = crtc->base.dev; | |
968 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
969 | struct intel_plane *plane; | |
970 | unsigned int total_rate = 0; | |
971 | const int fifo_size = 512 - 1; | |
972 | int fifo_extra, fifo_left = fifo_size; | |
973 | ||
974 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
975 | struct intel_plane_state *state = | |
976 | to_intel_plane_state(plane->base.state); | |
977 | ||
978 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) | |
979 | continue; | |
980 | ||
981 | if (state->visible) { | |
982 | wm_state->num_active_planes++; | |
983 | total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); | |
984 | } | |
985 | } | |
986 | ||
987 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
988 | struct intel_plane_state *state = | |
989 | to_intel_plane_state(plane->base.state); | |
990 | unsigned int rate; | |
991 | ||
992 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { | |
993 | plane->wm.fifo_size = 63; | |
994 | continue; | |
995 | } | |
996 | ||
997 | if (!state->visible) { | |
998 | plane->wm.fifo_size = 0; | |
999 | continue; | |
1000 | } | |
1001 | ||
1002 | rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); | |
1003 | plane->wm.fifo_size = fifo_size * rate / total_rate; | |
1004 | fifo_left -= plane->wm.fifo_size; | |
1005 | } | |
1006 | ||
1007 | fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); | |
1008 | ||
1009 | /* spread the remainder evenly */ | |
1010 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1011 | int plane_extra; | |
1012 | ||
1013 | if (fifo_left == 0) | |
1014 | break; | |
1015 | ||
1016 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) | |
1017 | continue; | |
1018 | ||
1019 | /* give it all to the first plane if none are active */ | |
1020 | if (plane->wm.fifo_size == 0 && | |
1021 | wm_state->num_active_planes) | |
1022 | continue; | |
1023 | ||
1024 | plane_extra = min(fifo_extra, fifo_left); | |
1025 | plane->wm.fifo_size += plane_extra; | |
1026 | fifo_left -= plane_extra; | |
1027 | } | |
1028 | ||
1029 | WARN_ON(fifo_left != 0); | |
1030 | } | |
1031 | ||
262cd2e1 VS |
1032 | static void vlv_invert_wms(struct intel_crtc *crtc) |
1033 | { | |
1034 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1035 | int level; | |
1036 | ||
1037 | for (level = 0; level < wm_state->num_levels; level++) { | |
1038 | struct drm_device *dev = crtc->base.dev; | |
1039 | const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; | |
1040 | struct intel_plane *plane; | |
1041 | ||
1042 | wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; | |
1043 | wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; | |
1044 | ||
1045 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1046 | switch (plane->base.type) { | |
1047 | int sprite; | |
1048 | case DRM_PLANE_TYPE_CURSOR: | |
1049 | wm_state->wm[level].cursor = plane->wm.fifo_size - | |
1050 | wm_state->wm[level].cursor; | |
1051 | break; | |
1052 | case DRM_PLANE_TYPE_PRIMARY: | |
1053 | wm_state->wm[level].primary = plane->wm.fifo_size - | |
1054 | wm_state->wm[level].primary; | |
1055 | break; | |
1056 | case DRM_PLANE_TYPE_OVERLAY: | |
1057 | sprite = plane->plane; | |
1058 | wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - | |
1059 | wm_state->wm[level].sprite[sprite]; | |
1060 | break; | |
1061 | } | |
1062 | } | |
1063 | } | |
1064 | } | |
1065 | ||
26e1fe4f | 1066 | static void vlv_compute_wm(struct intel_crtc *crtc) |
262cd2e1 VS |
1067 | { |
1068 | struct drm_device *dev = crtc->base.dev; | |
1069 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1070 | struct intel_plane *plane; | |
1071 | int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; | |
1072 | int level; | |
1073 | ||
1074 | memset(wm_state, 0, sizeof(*wm_state)); | |
1075 | ||
852eb00d | 1076 | wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; |
58590c14 | 1077 | wm_state->num_levels = to_i915(dev)->wm.max_level + 1; |
262cd2e1 VS |
1078 | |
1079 | wm_state->num_active_planes = 0; | |
262cd2e1 | 1080 | |
54f1b6e1 | 1081 | vlv_compute_fifo(crtc); |
262cd2e1 VS |
1082 | |
1083 | if (wm_state->num_active_planes != 1) | |
1084 | wm_state->cxsr = false; | |
1085 | ||
1086 | if (wm_state->cxsr) { | |
1087 | for (level = 0; level < wm_state->num_levels; level++) { | |
1088 | wm_state->sr[level].plane = sr_fifo_size; | |
1089 | wm_state->sr[level].cursor = 63; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1094 | struct intel_plane_state *state = | |
1095 | to_intel_plane_state(plane->base.state); | |
1096 | ||
1097 | if (!state->visible) | |
1098 | continue; | |
1099 | ||
1100 | /* normal watermarks */ | |
1101 | for (level = 0; level < wm_state->num_levels; level++) { | |
1102 | int wm = vlv_compute_wm_level(plane, crtc, state, level); | |
1103 | int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; | |
1104 | ||
1105 | /* hack */ | |
1106 | if (WARN_ON(level == 0 && wm > max_wm)) | |
1107 | wm = max_wm; | |
1108 | ||
1109 | if (wm > plane->wm.fifo_size) | |
1110 | break; | |
1111 | ||
1112 | switch (plane->base.type) { | |
1113 | int sprite; | |
1114 | case DRM_PLANE_TYPE_CURSOR: | |
1115 | wm_state->wm[level].cursor = wm; | |
1116 | break; | |
1117 | case DRM_PLANE_TYPE_PRIMARY: | |
1118 | wm_state->wm[level].primary = wm; | |
1119 | break; | |
1120 | case DRM_PLANE_TYPE_OVERLAY: | |
1121 | sprite = plane->plane; | |
1122 | wm_state->wm[level].sprite[sprite] = wm; | |
1123 | break; | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | wm_state->num_levels = level; | |
1128 | ||
1129 | if (!wm_state->cxsr) | |
1130 | continue; | |
1131 | ||
1132 | /* maxfifo watermarks */ | |
1133 | switch (plane->base.type) { | |
1134 | int sprite, level; | |
1135 | case DRM_PLANE_TYPE_CURSOR: | |
1136 | for (level = 0; level < wm_state->num_levels; level++) | |
1137 | wm_state->sr[level].cursor = | |
1138 | wm_state->sr[level].cursor; | |
1139 | break; | |
1140 | case DRM_PLANE_TYPE_PRIMARY: | |
1141 | for (level = 0; level < wm_state->num_levels; level++) | |
1142 | wm_state->sr[level].plane = | |
1143 | min(wm_state->sr[level].plane, | |
1144 | wm_state->wm[level].primary); | |
1145 | break; | |
1146 | case DRM_PLANE_TYPE_OVERLAY: | |
1147 | sprite = plane->plane; | |
1148 | for (level = 0; level < wm_state->num_levels; level++) | |
1149 | wm_state->sr[level].plane = | |
1150 | min(wm_state->sr[level].plane, | |
1151 | wm_state->wm[level].sprite[sprite]); | |
1152 | break; | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | /* clear any (partially) filled invalid levels */ | |
58590c14 | 1157 | for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { |
262cd2e1 VS |
1158 | memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); |
1159 | memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); | |
1160 | } | |
1161 | ||
1162 | vlv_invert_wms(crtc); | |
1163 | } | |
1164 | ||
54f1b6e1 VS |
1165 | #define VLV_FIFO(plane, value) \ |
1166 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) | |
1167 | ||
1168 | static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) | |
1169 | { | |
1170 | struct drm_device *dev = crtc->base.dev; | |
1171 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1172 | struct intel_plane *plane; | |
1173 | int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; | |
1174 | ||
1175 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
1176 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { | |
1177 | WARN_ON(plane->wm.fifo_size != 63); | |
1178 | continue; | |
1179 | } | |
1180 | ||
1181 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
1182 | sprite0_start = plane->wm.fifo_size; | |
1183 | else if (plane->plane == 0) | |
1184 | sprite1_start = sprite0_start + plane->wm.fifo_size; | |
1185 | else | |
1186 | fifo_size = sprite1_start + plane->wm.fifo_size; | |
1187 | } | |
1188 | ||
1189 | WARN_ON(fifo_size != 512 - 1); | |
1190 | ||
1191 | DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", | |
1192 | pipe_name(crtc->pipe), sprite0_start, | |
1193 | sprite1_start, fifo_size); | |
1194 | ||
1195 | switch (crtc->pipe) { | |
1196 | uint32_t dsparb, dsparb2, dsparb3; | |
1197 | case PIPE_A: | |
1198 | dsparb = I915_READ(DSPARB); | |
1199 | dsparb2 = I915_READ(DSPARB2); | |
1200 | ||
1201 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | | |
1202 | VLV_FIFO(SPRITEB, 0xff)); | |
1203 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | | |
1204 | VLV_FIFO(SPRITEB, sprite1_start)); | |
1205 | ||
1206 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | | |
1207 | VLV_FIFO(SPRITEB_HI, 0x1)); | |
1208 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | | |
1209 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); | |
1210 | ||
1211 | I915_WRITE(DSPARB, dsparb); | |
1212 | I915_WRITE(DSPARB2, dsparb2); | |
1213 | break; | |
1214 | case PIPE_B: | |
1215 | dsparb = I915_READ(DSPARB); | |
1216 | dsparb2 = I915_READ(DSPARB2); | |
1217 | ||
1218 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | | |
1219 | VLV_FIFO(SPRITED, 0xff)); | |
1220 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | | |
1221 | VLV_FIFO(SPRITED, sprite1_start)); | |
1222 | ||
1223 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | | |
1224 | VLV_FIFO(SPRITED_HI, 0xff)); | |
1225 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | | |
1226 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); | |
1227 | ||
1228 | I915_WRITE(DSPARB, dsparb); | |
1229 | I915_WRITE(DSPARB2, dsparb2); | |
1230 | break; | |
1231 | case PIPE_C: | |
1232 | dsparb3 = I915_READ(DSPARB3); | |
1233 | dsparb2 = I915_READ(DSPARB2); | |
1234 | ||
1235 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | | |
1236 | VLV_FIFO(SPRITEF, 0xff)); | |
1237 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | | |
1238 | VLV_FIFO(SPRITEF, sprite1_start)); | |
1239 | ||
1240 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | | |
1241 | VLV_FIFO(SPRITEF_HI, 0xff)); | |
1242 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | | |
1243 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); | |
1244 | ||
1245 | I915_WRITE(DSPARB3, dsparb3); | |
1246 | I915_WRITE(DSPARB2, dsparb2); | |
1247 | break; | |
1248 | default: | |
1249 | break; | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | #undef VLV_FIFO | |
1254 | ||
262cd2e1 VS |
1255 | static void vlv_merge_wm(struct drm_device *dev, |
1256 | struct vlv_wm_values *wm) | |
1257 | { | |
1258 | struct intel_crtc *crtc; | |
1259 | int num_active_crtcs = 0; | |
1260 | ||
58590c14 | 1261 | wm->level = to_i915(dev)->wm.max_level; |
262cd2e1 VS |
1262 | wm->cxsr = true; |
1263 | ||
1264 | for_each_intel_crtc(dev, crtc) { | |
1265 | const struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1266 | ||
1267 | if (!crtc->active) | |
1268 | continue; | |
1269 | ||
1270 | if (!wm_state->cxsr) | |
1271 | wm->cxsr = false; | |
1272 | ||
1273 | num_active_crtcs++; | |
1274 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); | |
1275 | } | |
1276 | ||
1277 | if (num_active_crtcs != 1) | |
1278 | wm->cxsr = false; | |
1279 | ||
6f9c784b VS |
1280 | if (num_active_crtcs > 1) |
1281 | wm->level = VLV_WM_LEVEL_PM2; | |
1282 | ||
262cd2e1 VS |
1283 | for_each_intel_crtc(dev, crtc) { |
1284 | struct vlv_wm_state *wm_state = &crtc->wm_state; | |
1285 | enum pipe pipe = crtc->pipe; | |
1286 | ||
1287 | if (!crtc->active) | |
1288 | continue; | |
1289 | ||
1290 | wm->pipe[pipe] = wm_state->wm[wm->level]; | |
1291 | if (wm->cxsr) | |
1292 | wm->sr = wm_state->sr[wm->level]; | |
1293 | ||
1294 | wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; | |
1295 | wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; | |
1296 | wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; | |
1297 | wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | static void vlv_update_wm(struct drm_crtc *crtc) | |
1302 | { | |
1303 | struct drm_device *dev = crtc->dev; | |
1304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1305 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1306 | enum pipe pipe = intel_crtc->pipe; | |
1307 | struct vlv_wm_values wm = {}; | |
1308 | ||
26e1fe4f | 1309 | vlv_compute_wm(intel_crtc); |
262cd2e1 VS |
1310 | vlv_merge_wm(dev, &wm); |
1311 | ||
54f1b6e1 VS |
1312 | if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { |
1313 | /* FIXME should be part of crtc atomic commit */ | |
1314 | vlv_pipe_set_fifo_size(intel_crtc); | |
262cd2e1 | 1315 | return; |
54f1b6e1 | 1316 | } |
262cd2e1 VS |
1317 | |
1318 | if (wm.level < VLV_WM_LEVEL_DDR_DVFS && | |
1319 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) | |
1320 | chv_set_memory_dvfs(dev_priv, false); | |
1321 | ||
1322 | if (wm.level < VLV_WM_LEVEL_PM5 && | |
1323 | dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) | |
1324 | chv_set_memory_pm5(dev_priv, false); | |
1325 | ||
852eb00d | 1326 | if (!wm.cxsr && dev_priv->wm.vlv.cxsr) |
262cd2e1 | 1327 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 1328 | |
54f1b6e1 VS |
1329 | /* FIXME should be part of crtc atomic commit */ |
1330 | vlv_pipe_set_fifo_size(intel_crtc); | |
1331 | ||
262cd2e1 VS |
1332 | vlv_write_wm_values(intel_crtc, &wm); |
1333 | ||
1334 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " | |
1335 | "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", | |
1336 | pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, | |
1337 | wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], | |
1338 | wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); | |
1339 | ||
852eb00d | 1340 | if (wm.cxsr && !dev_priv->wm.vlv.cxsr) |
262cd2e1 | 1341 | intel_set_memory_cxsr(dev_priv, true); |
262cd2e1 VS |
1342 | |
1343 | if (wm.level >= VLV_WM_LEVEL_PM5 && | |
1344 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) | |
1345 | chv_set_memory_pm5(dev_priv, true); | |
1346 | ||
1347 | if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && | |
1348 | dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) | |
1349 | chv_set_memory_dvfs(dev_priv, true); | |
1350 | ||
1351 | dev_priv->wm.vlv = wm; | |
3c2777fd VS |
1352 | } |
1353 | ||
ae80152d VS |
1354 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1355 | ||
46ba614c | 1356 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1357 | { |
46ba614c | 1358 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1359 | static const int sr_latency_ns = 12000; |
1360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1361 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1362 | int plane_sr, cursor_sr; | |
1363 | unsigned int enabled = 0; | |
9858425c | 1364 | bool cxsr_enabled; |
b445e3b0 | 1365 | |
51cea1f4 | 1366 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1367 | &g4x_wm_info, pessimal_latency_ns, |
1368 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1369 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1370 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1371 | |
51cea1f4 | 1372 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1373 | &g4x_wm_info, pessimal_latency_ns, |
1374 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1375 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1376 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1377 | |
b445e3b0 ED |
1378 | if (single_plane_enabled(enabled) && |
1379 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1380 | sr_latency_ns, | |
1381 | &g4x_wm_info, | |
1382 | &g4x_cursor_wm_info, | |
52bd02d8 | 1383 | &plane_sr, &cursor_sr)) { |
9858425c | 1384 | cxsr_enabled = true; |
52bd02d8 | 1385 | } else { |
9858425c | 1386 | cxsr_enabled = false; |
5209b1f4 | 1387 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1388 | plane_sr = cursor_sr = 0; |
1389 | } | |
b445e3b0 | 1390 | |
a5043453 VS |
1391 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1392 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1393 | planea_wm, cursora_wm, |
1394 | planeb_wm, cursorb_wm, | |
1395 | plane_sr, cursor_sr); | |
1396 | ||
1397 | I915_WRITE(DSPFW1, | |
f4998963 VS |
1398 | FW_WM(plane_sr, SR) | |
1399 | FW_WM(cursorb_wm, CURSORB) | | |
1400 | FW_WM(planeb_wm, PLANEB) | | |
1401 | FW_WM(planea_wm, PLANEA)); | |
b445e3b0 | 1402 | I915_WRITE(DSPFW2, |
8c919b28 | 1403 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
f4998963 | 1404 | FW_WM(cursora_wm, CURSORA)); |
b445e3b0 ED |
1405 | /* HPLL off in SR has some issues on G4x... disable it */ |
1406 | I915_WRITE(DSPFW3, | |
8c919b28 | 1407 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
f4998963 | 1408 | FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1409 | |
1410 | if (cxsr_enabled) | |
1411 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1412 | } |
1413 | ||
46ba614c | 1414 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1415 | { |
46ba614c | 1416 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1417 | struct drm_i915_private *dev_priv = dev->dev_private; |
1418 | struct drm_crtc *crtc; | |
1419 | int srwm = 1; | |
1420 | int cursor_sr = 16; | |
9858425c | 1421 | bool cxsr_enabled; |
b445e3b0 ED |
1422 | |
1423 | /* Calc sr entries for one plane configs */ | |
1424 | crtc = single_enabled_crtc(dev); | |
1425 | if (crtc) { | |
1426 | /* self-refresh has much higher latency */ | |
1427 | static const int sr_latency_ns = 12000; | |
124abe07 | 1428 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1429 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1430 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1431 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 1432 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1433 | unsigned long line_time_us; |
1434 | int entries; | |
1435 | ||
922044c9 | 1436 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1437 | |
1438 | /* Use ns/us then divide to preserve precision */ | |
1439 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1440 | pixel_size * hdisplay; | |
1441 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1442 | srwm = I965_FIFO_SIZE - entries; | |
1443 | if (srwm < 0) | |
1444 | srwm = 1; | |
1445 | srwm &= 0x1ff; | |
1446 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1447 | entries, srwm); | |
1448 | ||
1449 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
3dd512fb | 1450 | pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
1451 | entries = DIV_ROUND_UP(entries, |
1452 | i965_cursor_wm_info.cacheline_size); | |
1453 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1454 | (entries + i965_cursor_wm_info.guard_size); | |
1455 | ||
1456 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1457 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1458 | ||
1459 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1460 | "cursor %d\n", srwm, cursor_sr); | |
1461 | ||
9858425c | 1462 | cxsr_enabled = true; |
b445e3b0 | 1463 | } else { |
9858425c | 1464 | cxsr_enabled = false; |
b445e3b0 | 1465 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1466 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1467 | } |
1468 | ||
1469 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1470 | srwm); | |
1471 | ||
1472 | /* 965 has limitations... */ | |
f4998963 VS |
1473 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
1474 | FW_WM(8, CURSORB) | | |
1475 | FW_WM(8, PLANEB) | | |
1476 | FW_WM(8, PLANEA)); | |
1477 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | | |
1478 | FW_WM(8, PLANEC_OLD)); | |
b445e3b0 | 1479 | /* update cursor SR watermark */ |
f4998963 | 1480 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1481 | |
1482 | if (cxsr_enabled) | |
1483 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1484 | } |
1485 | ||
f4998963 VS |
1486 | #undef FW_WM |
1487 | ||
46ba614c | 1488 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1489 | { |
46ba614c | 1490 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1491 | struct drm_i915_private *dev_priv = dev->dev_private; |
1492 | const struct intel_watermark_params *wm_info; | |
1493 | uint32_t fwater_lo; | |
1494 | uint32_t fwater_hi; | |
1495 | int cwm, srwm = 1; | |
1496 | int fifo_size; | |
1497 | int planea_wm, planeb_wm; | |
1498 | struct drm_crtc *crtc, *enabled = NULL; | |
1499 | ||
1500 | if (IS_I945GM(dev)) | |
1501 | wm_info = &i945_wm_info; | |
1502 | else if (!IS_GEN2(dev)) | |
1503 | wm_info = &i915_wm_info; | |
1504 | else | |
9d539105 | 1505 | wm_info = &i830_a_wm_info; |
b445e3b0 ED |
1506 | |
1507 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1508 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1509 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1510 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1511 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1512 | if (IS_GEN2(dev)) |
1513 | cpp = 4; | |
1514 | ||
6e3c9717 | 1515 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1516 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1517 | wm_info, fifo_size, cpp, |
5aef6003 | 1518 | pessimal_latency_ns); |
b445e3b0 | 1519 | enabled = crtc; |
9d539105 | 1520 | } else { |
b445e3b0 | 1521 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1522 | if (planea_wm > (long)wm_info->max_wm) |
1523 | planea_wm = wm_info->max_wm; | |
1524 | } | |
1525 | ||
1526 | if (IS_GEN2(dev)) | |
1527 | wm_info = &i830_bc_wm_info; | |
b445e3b0 ED |
1528 | |
1529 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1530 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1531 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1532 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1533 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1534 | if (IS_GEN2(dev)) |
1535 | cpp = 4; | |
1536 | ||
6e3c9717 | 1537 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1538 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1539 | wm_info, fifo_size, cpp, |
5aef6003 | 1540 | pessimal_latency_ns); |
b445e3b0 ED |
1541 | if (enabled == NULL) |
1542 | enabled = crtc; | |
1543 | else | |
1544 | enabled = NULL; | |
9d539105 | 1545 | } else { |
b445e3b0 | 1546 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1547 | if (planeb_wm > (long)wm_info->max_wm) |
1548 | planeb_wm = wm_info->max_wm; | |
1549 | } | |
b445e3b0 ED |
1550 | |
1551 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1552 | ||
2ab1bc9d | 1553 | if (IS_I915GM(dev) && enabled) { |
2ff8fde1 | 1554 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1555 | |
59bea882 | 1556 | obj = intel_fb_obj(enabled->primary->state->fb); |
2ab1bc9d DV |
1557 | |
1558 | /* self-refresh seems busted with untiled */ | |
2ff8fde1 | 1559 | if (obj->tiling_mode == I915_TILING_NONE) |
2ab1bc9d DV |
1560 | enabled = NULL; |
1561 | } | |
1562 | ||
b445e3b0 ED |
1563 | /* |
1564 | * Overlay gets an aggressive default since video jitter is bad. | |
1565 | */ | |
1566 | cwm = 2; | |
1567 | ||
1568 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1569 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1570 | |
1571 | /* Calc sr entries for one plane configs */ | |
1572 | if (HAS_FW_BLC(dev) && enabled) { | |
1573 | /* self-refresh has much higher latency */ | |
1574 | static const int sr_latency_ns = 6000; | |
124abe07 | 1575 | const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; |
241bfc38 | 1576 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1577 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1578 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
59bea882 | 1579 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1580 | unsigned long line_time_us; |
1581 | int entries; | |
1582 | ||
922044c9 | 1583 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1584 | |
1585 | /* Use ns/us then divide to preserve precision */ | |
1586 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1587 | pixel_size * hdisplay; | |
1588 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1589 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1590 | srwm = wm_info->fifo_size - entries; | |
1591 | if (srwm < 0) | |
1592 | srwm = 1; | |
1593 | ||
1594 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1595 | I915_WRITE(FW_BLC_SELF, | |
1596 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1597 | else if (IS_I915GM(dev)) | |
1598 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1599 | } | |
1600 | ||
1601 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1602 | planea_wm, planeb_wm, cwm, srwm); | |
1603 | ||
1604 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1605 | fwater_hi = (cwm & 0x1f); | |
1606 | ||
1607 | /* Set request length to 8 cachelines per fetch */ | |
1608 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1609 | fwater_hi = fwater_hi | (1 << 8); | |
1610 | ||
1611 | I915_WRITE(FW_BLC, fwater_lo); | |
1612 | I915_WRITE(FW_BLC2, fwater_hi); | |
1613 | ||
5209b1f4 ID |
1614 | if (enabled) |
1615 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1616 | } |
1617 | ||
feb56b93 | 1618 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1619 | { |
46ba614c | 1620 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1621 | struct drm_i915_private *dev_priv = dev->dev_private; |
1622 | struct drm_crtc *crtc; | |
241bfc38 | 1623 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1624 | uint32_t fwater_lo; |
1625 | int planea_wm; | |
1626 | ||
1627 | crtc = single_enabled_crtc(dev); | |
1628 | if (crtc == NULL) | |
1629 | return; | |
1630 | ||
6e3c9717 | 1631 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1632 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 1633 | &i845_wm_info, |
b445e3b0 | 1634 | dev_priv->display.get_fifo_size(dev, 0), |
5aef6003 | 1635 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1636 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1637 | fwater_lo |= (3<<8) | planea_wm; | |
1638 | ||
1639 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1640 | ||
1641 | I915_WRITE(FW_BLC, fwater_lo); | |
1642 | } | |
1643 | ||
8cfb3407 | 1644 | uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
801bcfff | 1645 | { |
fd4daa9c | 1646 | uint32_t pixel_rate; |
801bcfff | 1647 | |
8cfb3407 | 1648 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; |
801bcfff PZ |
1649 | |
1650 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1651 | * adjust the pixel_rate here. */ | |
1652 | ||
8cfb3407 | 1653 | if (pipe_config->pch_pfit.enabled) { |
801bcfff | 1654 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
8cfb3407 VS |
1655 | uint32_t pfit_size = pipe_config->pch_pfit.size; |
1656 | ||
1657 | pipe_w = pipe_config->pipe_src_w; | |
1658 | pipe_h = pipe_config->pipe_src_h; | |
801bcfff | 1659 | |
801bcfff PZ |
1660 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1661 | pfit_h = pfit_size & 0xFFFF; | |
1662 | if (pipe_w < pfit_w) | |
1663 | pipe_w = pfit_w; | |
1664 | if (pipe_h < pfit_h) | |
1665 | pipe_h = pfit_h; | |
1666 | ||
1667 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1668 | pfit_w * pfit_h); | |
1669 | } | |
1670 | ||
1671 | return pixel_rate; | |
1672 | } | |
1673 | ||
37126462 | 1674 | /* latency must be in 0.1us units. */ |
23297044 | 1675 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1676 | uint32_t latency) |
1677 | { | |
1678 | uint64_t ret; | |
1679 | ||
3312ba65 VS |
1680 | if (WARN(latency == 0, "Latency value missing\n")) |
1681 | return UINT_MAX; | |
1682 | ||
801bcfff PZ |
1683 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1684 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1685 | ||
1686 | return ret; | |
1687 | } | |
1688 | ||
37126462 | 1689 | /* latency must be in 0.1us units. */ |
23297044 | 1690 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1691 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1692 | uint32_t latency) | |
1693 | { | |
1694 | uint32_t ret; | |
1695 | ||
3312ba65 VS |
1696 | if (WARN(latency == 0, "Latency value missing\n")) |
1697 | return UINT_MAX; | |
1698 | ||
801bcfff PZ |
1699 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1700 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1701 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1702 | return ret; | |
1703 | } | |
1704 | ||
23297044 | 1705 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1706 | uint8_t bytes_per_pixel) |
1707 | { | |
1708 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1709 | } | |
1710 | ||
820c1980 | 1711 | struct ilk_wm_maximums { |
cca32e9a PZ |
1712 | uint16_t pri; |
1713 | uint16_t spr; | |
1714 | uint16_t cur; | |
1715 | uint16_t fbc; | |
1716 | }; | |
1717 | ||
37126462 VS |
1718 | /* |
1719 | * For both WM_PIPE and WM_LP. | |
1720 | * mem_value must be in 0.1us units. | |
1721 | */ | |
7221fc33 | 1722 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1723 | const struct intel_plane_state *pstate, |
cca32e9a PZ |
1724 | uint32_t mem_value, |
1725 | bool is_lp) | |
801bcfff | 1726 | { |
43d59eda | 1727 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
cca32e9a PZ |
1728 | uint32_t method1, method2; |
1729 | ||
7221fc33 | 1730 | if (!cstate->base.active || !pstate->visible) |
801bcfff PZ |
1731 | return 0; |
1732 | ||
7221fc33 | 1733 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
cca32e9a PZ |
1734 | |
1735 | if (!is_lp) | |
1736 | return method1; | |
1737 | ||
7221fc33 MR |
1738 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1739 | cstate->base.adjusted_mode.crtc_htotal, | |
43d59eda MR |
1740 | drm_rect_width(&pstate->dst), |
1741 | bpp, | |
cca32e9a PZ |
1742 | mem_value); |
1743 | ||
1744 | return min(method1, method2); | |
801bcfff PZ |
1745 | } |
1746 | ||
37126462 VS |
1747 | /* |
1748 | * For both WM_PIPE and WM_LP. | |
1749 | * mem_value must be in 0.1us units. | |
1750 | */ | |
7221fc33 | 1751 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1752 | const struct intel_plane_state *pstate, |
801bcfff PZ |
1753 | uint32_t mem_value) |
1754 | { | |
43d59eda | 1755 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
801bcfff PZ |
1756 | uint32_t method1, method2; |
1757 | ||
7221fc33 | 1758 | if (!cstate->base.active || !pstate->visible) |
801bcfff PZ |
1759 | return 0; |
1760 | ||
7221fc33 MR |
1761 | method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value); |
1762 | method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), | |
1763 | cstate->base.adjusted_mode.crtc_htotal, | |
43d59eda MR |
1764 | drm_rect_width(&pstate->dst), |
1765 | bpp, | |
801bcfff PZ |
1766 | mem_value); |
1767 | return min(method1, method2); | |
1768 | } | |
1769 | ||
37126462 VS |
1770 | /* |
1771 | * For both WM_PIPE and WM_LP. | |
1772 | * mem_value must be in 0.1us units. | |
1773 | */ | |
7221fc33 | 1774 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1775 | const struct intel_plane_state *pstate, |
801bcfff PZ |
1776 | uint32_t mem_value) |
1777 | { | |
43d59eda MR |
1778 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1779 | ||
7221fc33 | 1780 | if (!cstate->base.active || !pstate->visible) |
801bcfff PZ |
1781 | return 0; |
1782 | ||
7221fc33 MR |
1783 | return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), |
1784 | cstate->base.adjusted_mode.crtc_htotal, | |
43d59eda MR |
1785 | drm_rect_width(&pstate->dst), |
1786 | bpp, | |
801bcfff PZ |
1787 | mem_value); |
1788 | } | |
1789 | ||
cca32e9a | 1790 | /* Only for WM_LP. */ |
7221fc33 | 1791 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1792 | const struct intel_plane_state *pstate, |
1fda9882 | 1793 | uint32_t pri_val) |
cca32e9a | 1794 | { |
43d59eda MR |
1795 | int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0; |
1796 | ||
7221fc33 | 1797 | if (!cstate->base.active || !pstate->visible) |
cca32e9a PZ |
1798 | return 0; |
1799 | ||
43d59eda | 1800 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp); |
cca32e9a PZ |
1801 | } |
1802 | ||
158ae64f VS |
1803 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1804 | { | |
416f4727 VS |
1805 | if (INTEL_INFO(dev)->gen >= 8) |
1806 | return 3072; | |
1807 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1808 | return 768; |
1809 | else | |
1810 | return 512; | |
1811 | } | |
1812 | ||
4e975081 VS |
1813 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1814 | int level, bool is_sprite) | |
1815 | { | |
1816 | if (INTEL_INFO(dev)->gen >= 8) | |
1817 | /* BDW primary/sprite plane watermarks */ | |
1818 | return level == 0 ? 255 : 2047; | |
1819 | else if (INTEL_INFO(dev)->gen >= 7) | |
1820 | /* IVB/HSW primary/sprite plane watermarks */ | |
1821 | return level == 0 ? 127 : 1023; | |
1822 | else if (!is_sprite) | |
1823 | /* ILK/SNB primary plane watermarks */ | |
1824 | return level == 0 ? 127 : 511; | |
1825 | else | |
1826 | /* ILK/SNB sprite plane watermarks */ | |
1827 | return level == 0 ? 63 : 255; | |
1828 | } | |
1829 | ||
1830 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
1831 | int level) | |
1832 | { | |
1833 | if (INTEL_INFO(dev)->gen >= 7) | |
1834 | return level == 0 ? 63 : 255; | |
1835 | else | |
1836 | return level == 0 ? 31 : 63; | |
1837 | } | |
1838 | ||
1839 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
1840 | { | |
1841 | if (INTEL_INFO(dev)->gen >= 8) | |
1842 | return 31; | |
1843 | else | |
1844 | return 15; | |
1845 | } | |
1846 | ||
158ae64f VS |
1847 | /* Calculate the maximum primary/sprite plane watermark */ |
1848 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1849 | int level, | |
240264f4 | 1850 | const struct intel_wm_config *config, |
158ae64f VS |
1851 | enum intel_ddb_partitioning ddb_partitioning, |
1852 | bool is_sprite) | |
1853 | { | |
1854 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
1855 | |
1856 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 1857 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
1858 | return 0; |
1859 | ||
1860 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 1861 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
1862 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1863 | ||
1864 | /* | |
1865 | * For some reason the non self refresh | |
1866 | * FIFO size is only half of the self | |
1867 | * refresh FIFO size on ILK/SNB. | |
1868 | */ | |
1869 | if (INTEL_INFO(dev)->gen <= 6) | |
1870 | fifo_size /= 2; | |
1871 | } | |
1872 | ||
240264f4 | 1873 | if (config->sprites_enabled) { |
158ae64f VS |
1874 | /* level 0 is always calculated with 1:1 split */ |
1875 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1876 | if (is_sprite) | |
1877 | fifo_size *= 5; | |
1878 | fifo_size /= 6; | |
1879 | } else { | |
1880 | fifo_size /= 2; | |
1881 | } | |
1882 | } | |
1883 | ||
1884 | /* clamp to max that the registers can hold */ | |
4e975081 | 1885 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
1886 | } |
1887 | ||
1888 | /* Calculate the maximum cursor plane watermark */ | |
1889 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
1890 | int level, |
1891 | const struct intel_wm_config *config) | |
158ae64f VS |
1892 | { |
1893 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 1894 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
1895 | return 64; |
1896 | ||
1897 | /* otherwise just report max that registers can hold */ | |
4e975081 | 1898 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
1899 | } |
1900 | ||
d34ff9c6 | 1901 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
1902 | int level, |
1903 | const struct intel_wm_config *config, | |
1904 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 1905 | struct ilk_wm_maximums *max) |
158ae64f | 1906 | { |
240264f4 VS |
1907 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1908 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1909 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 1910 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
1911 | } |
1912 | ||
a3cb4048 VS |
1913 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1914 | int level, | |
1915 | struct ilk_wm_maximums *max) | |
1916 | { | |
1917 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
1918 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
1919 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
1920 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1921 | } | |
1922 | ||
d9395655 | 1923 | static bool ilk_validate_wm_level(int level, |
820c1980 | 1924 | const struct ilk_wm_maximums *max, |
d9395655 | 1925 | struct intel_wm_level *result) |
a9786a11 VS |
1926 | { |
1927 | bool ret; | |
1928 | ||
1929 | /* already determined to be invalid? */ | |
1930 | if (!result->enable) | |
1931 | return false; | |
1932 | ||
1933 | result->enable = result->pri_val <= max->pri && | |
1934 | result->spr_val <= max->spr && | |
1935 | result->cur_val <= max->cur; | |
1936 | ||
1937 | ret = result->enable; | |
1938 | ||
1939 | /* | |
1940 | * HACK until we can pre-compute everything, | |
1941 | * and thus fail gracefully if LP0 watermarks | |
1942 | * are exceeded... | |
1943 | */ | |
1944 | if (level == 0 && !result->enable) { | |
1945 | if (result->pri_val > max->pri) | |
1946 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1947 | level, result->pri_val, max->pri); | |
1948 | if (result->spr_val > max->spr) | |
1949 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1950 | level, result->spr_val, max->spr); | |
1951 | if (result->cur_val > max->cur) | |
1952 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
1953 | level, result->cur_val, max->cur); | |
1954 | ||
1955 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
1956 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
1957 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
1958 | result->enable = true; | |
1959 | } | |
1960 | ||
a9786a11 VS |
1961 | return ret; |
1962 | } | |
1963 | ||
d34ff9c6 | 1964 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
43d59eda | 1965 | const struct intel_crtc *intel_crtc, |
6f5ddd17 | 1966 | int level, |
7221fc33 | 1967 | struct intel_crtc_state *cstate, |
86c8bbbe MR |
1968 | struct intel_plane_state *pristate, |
1969 | struct intel_plane_state *sprstate, | |
1970 | struct intel_plane_state *curstate, | |
1fd527cc | 1971 | struct intel_wm_level *result) |
6f5ddd17 VS |
1972 | { |
1973 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
1974 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
1975 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
1976 | ||
1977 | /* WM1+ latency values stored in 0.5us units */ | |
1978 | if (level > 0) { | |
1979 | pri_latency *= 5; | |
1980 | spr_latency *= 5; | |
1981 | cur_latency *= 5; | |
1982 | } | |
1983 | ||
86c8bbbe MR |
1984 | result->pri_val = ilk_compute_pri_wm(cstate, pristate, |
1985 | pri_latency, level); | |
1986 | result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency); | |
1987 | result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency); | |
1988 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); | |
6f5ddd17 VS |
1989 | result->enable = true; |
1990 | } | |
1991 | ||
801bcfff PZ |
1992 | static uint32_t |
1993 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
1994 | { |
1995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 1996 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7c5f93b0 | 1997 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
85a02deb | 1998 | u32 linetime, ips_linetime; |
1f8eeabf | 1999 | |
3ef00284 | 2000 | if (!intel_crtc->active) |
801bcfff | 2001 | return 0; |
1011d8c4 | 2002 | |
1f8eeabf ED |
2003 | /* The WM are computed with base on how long it takes to fill a single |
2004 | * row at the given clock rate, multiplied by 8. | |
2005 | * */ | |
124abe07 VS |
2006 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2007 | adjusted_mode->crtc_clock); | |
2008 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, | |
05024da3 | 2009 | dev_priv->cdclk_freq); |
1f8eeabf | 2010 | |
801bcfff PZ |
2011 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2012 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2013 | } |
2014 | ||
2af30a5c | 2015 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
12b134df VS |
2016 | { |
2017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2018 | ||
2af30a5c PB |
2019 | if (IS_GEN9(dev)) { |
2020 | uint32_t val; | |
4f947386 | 2021 | int ret, i; |
367294be | 2022 | int level, max_level = ilk_wm_max_level(dev); |
2af30a5c PB |
2023 | |
2024 | /* read the first set of memory latencies[0:3] */ | |
2025 | val = 0; /* data0 to be programmed to 0 for first set */ | |
2026 | mutex_lock(&dev_priv->rps.hw_lock); | |
2027 | ret = sandybridge_pcode_read(dev_priv, | |
2028 | GEN9_PCODE_READ_MEM_LATENCY, | |
2029 | &val); | |
2030 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2031 | ||
2032 | if (ret) { | |
2033 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2034 | return; | |
2035 | } | |
2036 | ||
2037 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2038 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2039 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2040 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2041 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2042 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2043 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2044 | ||
2045 | /* read the second set of memory latencies[4:7] */ | |
2046 | val = 1; /* data0 to be programmed to 1 for second set */ | |
2047 | mutex_lock(&dev_priv->rps.hw_lock); | |
2048 | ret = sandybridge_pcode_read(dev_priv, | |
2049 | GEN9_PCODE_READ_MEM_LATENCY, | |
2050 | &val); | |
2051 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2052 | if (ret) { | |
2053 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2054 | return; | |
2055 | } | |
2056 | ||
2057 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2058 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2059 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2060 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2061 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2062 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2063 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2064 | ||
367294be | 2065 | /* |
6f97235b DL |
2066 | * WaWmMemoryReadLatency:skl |
2067 | * | |
367294be VK |
2068 | * punit doesn't take into account the read latency so we need |
2069 | * to add 2us to the various latency levels we retrieve from | |
2070 | * the punit. | |
2071 | * - W0 is a bit special in that it's the only level that | |
2072 | * can't be disabled if we want to have display working, so | |
2073 | * we always add 2us there. | |
2074 | * - For levels >=1, punit returns 0us latency when they are | |
2075 | * disabled, so we respect that and don't add 2us then | |
4f947386 VK |
2076 | * |
2077 | * Additionally, if a level n (n > 1) has a 0us latency, all | |
2078 | * levels m (m >= n) need to be disabled. We make sure to | |
2079 | * sanitize the values out of the punit to satisfy this | |
2080 | * requirement. | |
367294be VK |
2081 | */ |
2082 | wm[0] += 2; | |
2083 | for (level = 1; level <= max_level; level++) | |
2084 | if (wm[level] != 0) | |
2085 | wm[level] += 2; | |
4f947386 VK |
2086 | else { |
2087 | for (i = level + 1; i <= max_level; i++) | |
2088 | wm[i] = 0; | |
367294be | 2089 | |
4f947386 VK |
2090 | break; |
2091 | } | |
2af30a5c | 2092 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
2093 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2094 | ||
2095 | wm[0] = (sskpd >> 56) & 0xFF; | |
2096 | if (wm[0] == 0) | |
2097 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2098 | wm[1] = (sskpd >> 4) & 0xFF; |
2099 | wm[2] = (sskpd >> 12) & 0xFF; | |
2100 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2101 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
2102 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2103 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
2104 | ||
2105 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2106 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2107 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2108 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
2109 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2110 | uint32_t mltr = I915_READ(MLTR_ILK); | |
2111 | ||
2112 | /* ILK primary LP0 latency is 700 ns */ | |
2113 | wm[0] = 7; | |
2114 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2115 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2116 | } |
2117 | } | |
2118 | ||
53615a5e VS |
2119 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2120 | { | |
2121 | /* ILK sprite LP0 latency is 1300 ns */ | |
2122 | if (INTEL_INFO(dev)->gen == 5) | |
2123 | wm[0] = 13; | |
2124 | } | |
2125 | ||
2126 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
2127 | { | |
2128 | /* ILK cursor LP0 latency is 1300 ns */ | |
2129 | if (INTEL_INFO(dev)->gen == 5) | |
2130 | wm[0] = 13; | |
2131 | ||
2132 | /* WaDoubleCursorLP3Latency:ivb */ | |
2133 | if (IS_IVYBRIDGE(dev)) | |
2134 | wm[3] *= 2; | |
2135 | } | |
2136 | ||
546c81fd | 2137 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 2138 | { |
26ec971e | 2139 | /* how many WM levels are we expecting */ |
b6e742f6 | 2140 | if (INTEL_INFO(dev)->gen >= 9) |
2af30a5c PB |
2141 | return 7; |
2142 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
ad0d6dc4 | 2143 | return 4; |
26ec971e | 2144 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 2145 | return 3; |
26ec971e | 2146 | else |
ad0d6dc4 VS |
2147 | return 2; |
2148 | } | |
7526ed79 | 2149 | |
ad0d6dc4 VS |
2150 | static void intel_print_wm_latency(struct drm_device *dev, |
2151 | const char *name, | |
2af30a5c | 2152 | const uint16_t wm[8]) |
ad0d6dc4 VS |
2153 | { |
2154 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
2155 | |
2156 | for (level = 0; level <= max_level; level++) { | |
2157 | unsigned int latency = wm[level]; | |
2158 | ||
2159 | if (latency == 0) { | |
2160 | DRM_ERROR("%s WM%d latency not provided\n", | |
2161 | name, level); | |
2162 | continue; | |
2163 | } | |
2164 | ||
2af30a5c PB |
2165 | /* |
2166 | * - latencies are in us on gen9. | |
2167 | * - before then, WM1+ latency values are in 0.5us units | |
2168 | */ | |
2169 | if (IS_GEN9(dev)) | |
2170 | latency *= 10; | |
2171 | else if (level > 0) | |
26ec971e VS |
2172 | latency *= 5; |
2173 | ||
2174 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2175 | name, level, wm[level], | |
2176 | latency / 10, latency % 10); | |
2177 | } | |
2178 | } | |
2179 | ||
e95a2f75 VS |
2180 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2181 | uint16_t wm[5], uint16_t min) | |
2182 | { | |
2183 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
2184 | ||
2185 | if (wm[0] >= min) | |
2186 | return false; | |
2187 | ||
2188 | wm[0] = max(wm[0], min); | |
2189 | for (level = 1; level <= max_level; level++) | |
2190 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2191 | ||
2192 | return true; | |
2193 | } | |
2194 | ||
2195 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
2196 | { | |
2197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2198 | bool changed; | |
2199 | ||
2200 | /* | |
2201 | * The BIOS provided WM memory latency values are often | |
2202 | * inadequate for high resolution displays. Adjust them. | |
2203 | */ | |
2204 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2205 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2206 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2207 | ||
2208 | if (!changed) | |
2209 | return; | |
2210 | ||
2211 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
2212 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2213 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2214 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
2215 | } | |
2216 | ||
fa50ad61 | 2217 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2218 | { |
2219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2220 | ||
2221 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2222 | ||
2223 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2224 | sizeof(dev_priv->wm.pri_latency)); | |
2225 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2226 | sizeof(dev_priv->wm.pri_latency)); | |
2227 | ||
2228 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2229 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2230 | |
2231 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2232 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2233 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2234 | |
2235 | if (IS_GEN6(dev)) | |
2236 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
2237 | } |
2238 | ||
2af30a5c PB |
2239 | static void skl_setup_wm_latency(struct drm_device *dev) |
2240 | { | |
2241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2242 | ||
2243 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); | |
2244 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); | |
2245 | } | |
2246 | ||
0b2ae6d7 | 2247 | /* Compute new watermarks for the pipe */ |
86c8bbbe MR |
2248 | static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc, |
2249 | struct drm_atomic_state *state) | |
0b2ae6d7 | 2250 | { |
86c8bbbe MR |
2251 | struct intel_pipe_wm *pipe_wm; |
2252 | struct drm_device *dev = intel_crtc->base.dev; | |
d34ff9c6 | 2253 | const struct drm_i915_private *dev_priv = dev->dev_private; |
86c8bbbe | 2254 | struct intel_crtc_state *cstate = NULL; |
43d59eda | 2255 | struct intel_plane *intel_plane; |
86c8bbbe MR |
2256 | struct drm_plane_state *ps; |
2257 | struct intel_plane_state *pristate = NULL; | |
43d59eda | 2258 | struct intel_plane_state *sprstate = NULL; |
86c8bbbe | 2259 | struct intel_plane_state *curstate = NULL; |
0b2ae6d7 VS |
2260 | int level, max_level = ilk_wm_max_level(dev); |
2261 | /* LP0 watermark maximums depend on this pipe alone */ | |
2262 | struct intel_wm_config config = { | |
2263 | .num_pipes_active = 1, | |
0b2ae6d7 | 2264 | }; |
820c1980 | 2265 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2266 | |
86c8bbbe MR |
2267 | cstate = intel_atomic_get_crtc_state(state, intel_crtc); |
2268 | if (IS_ERR(cstate)) | |
2269 | return PTR_ERR(cstate); | |
2270 | ||
2271 | pipe_wm = &cstate->wm.optimal.ilk; | |
2272 | ||
43d59eda | 2273 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
86c8bbbe MR |
2274 | ps = drm_atomic_get_plane_state(state, |
2275 | &intel_plane->base); | |
2276 | if (IS_ERR(ps)) | |
2277 | return PTR_ERR(ps); | |
2278 | ||
2279 | if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
2280 | pristate = to_intel_plane_state(ps); | |
2281 | else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) | |
2282 | sprstate = to_intel_plane_state(ps); | |
2283 | else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) | |
2284 | curstate = to_intel_plane_state(ps); | |
43d59eda MR |
2285 | } |
2286 | ||
2287 | config.sprites_enabled = sprstate->visible; | |
2288 | config.sprites_scaled = sprstate->visible && | |
2289 | (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || | |
2290 | drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); | |
2291 | ||
7221fc33 | 2292 | pipe_wm->pipe_enabled = cstate->base.active; |
86c8bbbe | 2293 | pipe_wm->sprites_enabled = config.sprites_enabled; |
43d59eda | 2294 | pipe_wm->sprites_scaled = config.sprites_scaled; |
2a44b76b | 2295 | |
7b39a0b7 | 2296 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
43d59eda | 2297 | if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) |
7b39a0b7 VS |
2298 | max_level = 1; |
2299 | ||
2300 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
43d59eda | 2301 | if (config.sprites_scaled) |
7b39a0b7 VS |
2302 | max_level = 0; |
2303 | ||
86c8bbbe MR |
2304 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
2305 | pristate, sprstate, curstate, &pipe_wm->wm[0]); | |
0b2ae6d7 | 2306 | |
a42a5719 | 2307 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
86c8bbbe MR |
2308 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, |
2309 | &intel_crtc->base); | |
0b2ae6d7 | 2310 | |
a3cb4048 VS |
2311 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2312 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2313 | ||
0b2ae6d7 | 2314 | /* At least LP0 must be valid */ |
a3cb4048 | 2315 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
86c8bbbe | 2316 | return -EINVAL; |
a3cb4048 VS |
2317 | |
2318 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2319 | ||
2320 | for (level = 1; level <= max_level; level++) { | |
2321 | struct intel_wm_level wm = {}; | |
2322 | ||
86c8bbbe MR |
2323 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, |
2324 | pristate, sprstate, curstate, &wm); | |
a3cb4048 VS |
2325 | |
2326 | /* | |
2327 | * Disable any watermark level that exceeds the | |
2328 | * register maximums since such watermarks are | |
2329 | * always invalid. | |
2330 | */ | |
2331 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2332 | break; | |
2333 | ||
2334 | pipe_wm->wm[level] = wm; | |
2335 | } | |
2336 | ||
86c8bbbe | 2337 | return 0; |
0b2ae6d7 VS |
2338 | } |
2339 | ||
2340 | /* | |
2341 | * Merge the watermarks from all active pipes for a specific level. | |
2342 | */ | |
2343 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2344 | int level, | |
2345 | struct intel_wm_level *ret_wm) | |
2346 | { | |
2347 | const struct intel_crtc *intel_crtc; | |
2348 | ||
d52fea5b VS |
2349 | ret_wm->enable = true; |
2350 | ||
d3fcc808 | 2351 | for_each_intel_crtc(dev, intel_crtc) { |
4e0963c7 MR |
2352 | const struct intel_crtc_state *cstate = |
2353 | to_intel_crtc_state(intel_crtc->base.state); | |
2354 | const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk; | |
fe392efd VS |
2355 | const struct intel_wm_level *wm = &active->wm[level]; |
2356 | ||
2357 | if (!active->pipe_enabled) | |
2358 | continue; | |
0b2ae6d7 | 2359 | |
d52fea5b VS |
2360 | /* |
2361 | * The watermark values may have been used in the past, | |
2362 | * so we must maintain them in the registers for some | |
2363 | * time even if the level is now disabled. | |
2364 | */ | |
0b2ae6d7 | 2365 | if (!wm->enable) |
d52fea5b | 2366 | ret_wm->enable = false; |
0b2ae6d7 VS |
2367 | |
2368 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2369 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2370 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2371 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2372 | } | |
0b2ae6d7 VS |
2373 | } |
2374 | ||
2375 | /* | |
2376 | * Merge all low power watermarks for all active pipes. | |
2377 | */ | |
2378 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2379 | const struct intel_wm_config *config, |
820c1980 | 2380 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2381 | struct intel_pipe_wm *merged) |
2382 | { | |
7733b49b | 2383 | struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 | 2384 | int level, max_level = ilk_wm_max_level(dev); |
d52fea5b | 2385 | int last_enabled_level = max_level; |
0b2ae6d7 | 2386 | |
0ba22e26 VS |
2387 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2388 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2389 | config->num_pipes_active > 1) | |
2390 | return; | |
2391 | ||
6c8b6c28 VS |
2392 | /* ILK: FBC WM must be disabled always */ |
2393 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2394 | |
2395 | /* merge each WM1+ level */ | |
2396 | for (level = 1; level <= max_level; level++) { | |
2397 | struct intel_wm_level *wm = &merged->wm[level]; | |
2398 | ||
2399 | ilk_merge_wm_level(dev, level, wm); | |
2400 | ||
d52fea5b VS |
2401 | if (level > last_enabled_level) |
2402 | wm->enable = false; | |
2403 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2404 | /* make sure all following levels get disabled */ | |
2405 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2406 | |
2407 | /* | |
2408 | * The spec says it is preferred to disable | |
2409 | * FBC WMs instead of disabling a WM level. | |
2410 | */ | |
2411 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2412 | if (wm->enable) |
2413 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2414 | wm->fbc_val = 0; |
2415 | } | |
2416 | } | |
6c8b6c28 VS |
2417 | |
2418 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2419 | /* | |
2420 | * FIXME this is racy. FBC might get enabled later. | |
2421 | * What we should check here is whether FBC can be | |
2422 | * enabled sometime later. | |
2423 | */ | |
7733b49b PZ |
2424 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && |
2425 | intel_fbc_enabled(dev_priv)) { | |
6c8b6c28 VS |
2426 | for (level = 2; level <= max_level; level++) { |
2427 | struct intel_wm_level *wm = &merged->wm[level]; | |
2428 | ||
2429 | wm->enable = false; | |
2430 | } | |
2431 | } | |
0b2ae6d7 VS |
2432 | } |
2433 | ||
b380ca3c VS |
2434 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2435 | { | |
2436 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2437 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2438 | } | |
2439 | ||
a68d68ee VS |
2440 | /* The value we need to program into the WM_LPx latency field */ |
2441 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2442 | { | |
2443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2444 | ||
a42a5719 | 2445 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2446 | return 2 * level; |
2447 | else | |
2448 | return dev_priv->wm.pri_latency[level]; | |
2449 | } | |
2450 | ||
820c1980 | 2451 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2452 | const struct intel_pipe_wm *merged, |
609cedef | 2453 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2454 | struct ilk_wm_values *results) |
801bcfff | 2455 | { |
0b2ae6d7 VS |
2456 | struct intel_crtc *intel_crtc; |
2457 | int level, wm_lp; | |
cca32e9a | 2458 | |
0362c781 | 2459 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2460 | results->partitioning = partitioning; |
cca32e9a | 2461 | |
0b2ae6d7 | 2462 | /* LP1+ register values */ |
cca32e9a | 2463 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2464 | const struct intel_wm_level *r; |
801bcfff | 2465 | |
b380ca3c | 2466 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2467 | |
0362c781 | 2468 | r = &merged->wm[level]; |
cca32e9a | 2469 | |
d52fea5b VS |
2470 | /* |
2471 | * Maintain the watermark values even if the level is | |
2472 | * disabled. Doing otherwise could cause underruns. | |
2473 | */ | |
2474 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2475 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2476 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2477 | r->cur_val; | |
2478 | ||
d52fea5b VS |
2479 | if (r->enable) |
2480 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2481 | ||
416f4727 VS |
2482 | if (INTEL_INFO(dev)->gen >= 8) |
2483 | results->wm_lp[wm_lp - 1] |= | |
2484 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2485 | else | |
2486 | results->wm_lp[wm_lp - 1] |= | |
2487 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2488 | ||
d52fea5b VS |
2489 | /* |
2490 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2491 | * level is disabled. Doing otherwise could cause underruns. | |
2492 | */ | |
6cef2b8a VS |
2493 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2494 | WARN_ON(wm_lp != 1); | |
2495 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2496 | } else | |
2497 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2498 | } |
801bcfff | 2499 | |
0b2ae6d7 | 2500 | /* LP0 register values */ |
d3fcc808 | 2501 | for_each_intel_crtc(dev, intel_crtc) { |
4e0963c7 MR |
2502 | const struct intel_crtc_state *cstate = |
2503 | to_intel_crtc_state(intel_crtc->base.state); | |
0b2ae6d7 | 2504 | enum pipe pipe = intel_crtc->pipe; |
4e0963c7 | 2505 | const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0]; |
0b2ae6d7 VS |
2506 | |
2507 | if (WARN_ON(!r->enable)) | |
2508 | continue; | |
2509 | ||
4e0963c7 | 2510 | results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime; |
1011d8c4 | 2511 | |
0b2ae6d7 VS |
2512 | results->wm_pipe[pipe] = |
2513 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2514 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2515 | r->cur_val; | |
801bcfff PZ |
2516 | } |
2517 | } | |
2518 | ||
861f3389 PZ |
2519 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2520 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2521 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2522 | struct intel_pipe_wm *r1, |
2523 | struct intel_pipe_wm *r2) | |
861f3389 | 2524 | { |
198a1e9b VS |
2525 | int level, max_level = ilk_wm_max_level(dev); |
2526 | int level1 = 0, level2 = 0; | |
861f3389 | 2527 | |
198a1e9b VS |
2528 | for (level = 1; level <= max_level; level++) { |
2529 | if (r1->wm[level].enable) | |
2530 | level1 = level; | |
2531 | if (r2->wm[level].enable) | |
2532 | level2 = level; | |
861f3389 PZ |
2533 | } |
2534 | ||
198a1e9b VS |
2535 | if (level1 == level2) { |
2536 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2537 | return r2; |
2538 | else | |
2539 | return r1; | |
198a1e9b | 2540 | } else if (level1 > level2) { |
861f3389 PZ |
2541 | return r1; |
2542 | } else { | |
2543 | return r2; | |
2544 | } | |
2545 | } | |
2546 | ||
49a687c4 VS |
2547 | /* dirty bits used to track which watermarks need changes */ |
2548 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2549 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2550 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2551 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2552 | #define WM_DIRTY_FBC (1 << 24) | |
2553 | #define WM_DIRTY_DDB (1 << 25) | |
2554 | ||
055e393f | 2555 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2556 | const struct ilk_wm_values *old, |
2557 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2558 | { |
2559 | unsigned int dirty = 0; | |
2560 | enum pipe pipe; | |
2561 | int wm_lp; | |
2562 | ||
055e393f | 2563 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2564 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2565 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2566 | /* Must disable LP1+ watermarks too */ | |
2567 | dirty |= WM_DIRTY_LP_ALL; | |
2568 | } | |
2569 | ||
2570 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2571 | dirty |= WM_DIRTY_PIPE(pipe); | |
2572 | /* Must disable LP1+ watermarks too */ | |
2573 | dirty |= WM_DIRTY_LP_ALL; | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2578 | dirty |= WM_DIRTY_FBC; | |
2579 | /* Must disable LP1+ watermarks too */ | |
2580 | dirty |= WM_DIRTY_LP_ALL; | |
2581 | } | |
2582 | ||
2583 | if (old->partitioning != new->partitioning) { | |
2584 | dirty |= WM_DIRTY_DDB; | |
2585 | /* Must disable LP1+ watermarks too */ | |
2586 | dirty |= WM_DIRTY_LP_ALL; | |
2587 | } | |
2588 | ||
2589 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2590 | if (dirty & WM_DIRTY_LP_ALL) | |
2591 | return dirty; | |
2592 | ||
2593 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2594 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2595 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2596 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2597 | break; | |
2598 | } | |
2599 | ||
2600 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2601 | for (; wm_lp <= 3; wm_lp++) | |
2602 | dirty |= WM_DIRTY_LP(wm_lp); | |
2603 | ||
2604 | return dirty; | |
2605 | } | |
2606 | ||
8553c18e VS |
2607 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2608 | unsigned int dirty) | |
801bcfff | 2609 | { |
820c1980 | 2610 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2611 | bool changed = false; |
801bcfff | 2612 | |
facd619b VS |
2613 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2614 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2615 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2616 | changed = true; |
facd619b VS |
2617 | } |
2618 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2619 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2620 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2621 | changed = true; |
facd619b VS |
2622 | } |
2623 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2624 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2625 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2626 | changed = true; |
facd619b | 2627 | } |
801bcfff | 2628 | |
facd619b VS |
2629 | /* |
2630 | * Don't touch WM1S_LP_EN here. | |
2631 | * Doing so could cause underruns. | |
2632 | */ | |
6cef2b8a | 2633 | |
8553c18e VS |
2634 | return changed; |
2635 | } | |
2636 | ||
2637 | /* | |
2638 | * The spec says we shouldn't write when we don't need, because every write | |
2639 | * causes WMs to be re-evaluated, expending some power. | |
2640 | */ | |
820c1980 ID |
2641 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2642 | struct ilk_wm_values *results) | |
8553c18e VS |
2643 | { |
2644 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2645 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2646 | unsigned int dirty; |
2647 | uint32_t val; | |
2648 | ||
055e393f | 2649 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2650 | if (!dirty) |
2651 | return; | |
2652 | ||
2653 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2654 | ||
49a687c4 | 2655 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2656 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2657 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2658 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2659 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2660 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2661 | ||
49a687c4 | 2662 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2663 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2664 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2665 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2666 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2667 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2668 | ||
49a687c4 | 2669 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2670 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2671 | val = I915_READ(WM_MISC); |
2672 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2673 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2674 | else | |
2675 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2676 | I915_WRITE(WM_MISC, val); | |
2677 | } else { | |
2678 | val = I915_READ(DISP_ARB_CTL2); | |
2679 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2680 | val &= ~DISP_DATA_PARTITION_5_6; | |
2681 | else | |
2682 | val |= DISP_DATA_PARTITION_5_6; | |
2683 | I915_WRITE(DISP_ARB_CTL2, val); | |
2684 | } | |
1011d8c4 PZ |
2685 | } |
2686 | ||
49a687c4 | 2687 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2688 | val = I915_READ(DISP_ARB_CTL); |
2689 | if (results->enable_fbc_wm) | |
2690 | val &= ~DISP_FBC_WM_DIS; | |
2691 | else | |
2692 | val |= DISP_FBC_WM_DIS; | |
2693 | I915_WRITE(DISP_ARB_CTL, val); | |
2694 | } | |
2695 | ||
954911eb ID |
2696 | if (dirty & WM_DIRTY_LP(1) && |
2697 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2698 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2699 | ||
2700 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2701 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2702 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2703 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2704 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2705 | } | |
801bcfff | 2706 | |
facd619b | 2707 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2708 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2709 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2710 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2711 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2712 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2713 | |
2714 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2715 | } |
2716 | ||
8553c18e VS |
2717 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2718 | { | |
2719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2720 | ||
2721 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2722 | } | |
2723 | ||
b9cec075 DL |
2724 | /* |
2725 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the | |
2726 | * different active planes. | |
2727 | */ | |
2728 | ||
2729 | #define SKL_DDB_SIZE 896 /* in blocks */ | |
43d735a6 | 2730 | #define BXT_DDB_SIZE 512 |
b9cec075 | 2731 | |
024c9045 MR |
2732 | /* |
2733 | * Return the index of a plane in the SKL DDB and wm result arrays. Primary | |
2734 | * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and | |
2735 | * other universal planes are in indices 1..n. Note that this may leave unused | |
2736 | * indices between the top "sprite" plane and the cursor. | |
2737 | */ | |
2738 | static int | |
2739 | skl_wm_plane_id(const struct intel_plane *plane) | |
2740 | { | |
2741 | switch (plane->base.type) { | |
2742 | case DRM_PLANE_TYPE_PRIMARY: | |
2743 | return 0; | |
2744 | case DRM_PLANE_TYPE_CURSOR: | |
2745 | return PLANE_CURSOR; | |
2746 | case DRM_PLANE_TYPE_OVERLAY: | |
2747 | return plane->plane + 1; | |
2748 | default: | |
2749 | MISSING_CASE(plane->base.type); | |
2750 | return plane->plane; | |
2751 | } | |
2752 | } | |
2753 | ||
b9cec075 DL |
2754 | static void |
2755 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
024c9045 | 2756 | const struct intel_crtc_state *cstate, |
b9cec075 | 2757 | const struct intel_wm_config *config, |
b9cec075 DL |
2758 | struct skl_ddb_entry *alloc /* out */) |
2759 | { | |
024c9045 | 2760 | struct drm_crtc *for_crtc = cstate->base.crtc; |
b9cec075 DL |
2761 | struct drm_crtc *crtc; |
2762 | unsigned int pipe_size, ddb_size; | |
2763 | int nth_active_pipe; | |
2764 | ||
024c9045 | 2765 | if (!cstate->base.active) { |
b9cec075 DL |
2766 | alloc->start = 0; |
2767 | alloc->end = 0; | |
2768 | return; | |
2769 | } | |
2770 | ||
43d735a6 DL |
2771 | if (IS_BROXTON(dev)) |
2772 | ddb_size = BXT_DDB_SIZE; | |
2773 | else | |
2774 | ddb_size = SKL_DDB_SIZE; | |
b9cec075 DL |
2775 | |
2776 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
2777 | ||
2778 | nth_active_pipe = 0; | |
2779 | for_each_crtc(dev, crtc) { | |
3ef00284 | 2780 | if (!to_intel_crtc(crtc)->active) |
b9cec075 DL |
2781 | continue; |
2782 | ||
2783 | if (crtc == for_crtc) | |
2784 | break; | |
2785 | ||
2786 | nth_active_pipe++; | |
2787 | } | |
2788 | ||
2789 | pipe_size = ddb_size / config->num_pipes_active; | |
2790 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; | |
16160e3d | 2791 | alloc->end = alloc->start + pipe_size; |
b9cec075 DL |
2792 | } |
2793 | ||
2794 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) | |
2795 | { | |
2796 | if (config->num_pipes_active == 1) | |
2797 | return 32; | |
2798 | ||
2799 | return 8; | |
2800 | } | |
2801 | ||
a269c583 DL |
2802 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
2803 | { | |
2804 | entry->start = reg & 0x3ff; | |
2805 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
2806 | if (entry->end) |
2807 | entry->end += 1; | |
a269c583 DL |
2808 | } |
2809 | ||
08db6652 DL |
2810 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2811 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 2812 | { |
a269c583 DL |
2813 | enum pipe pipe; |
2814 | int plane; | |
2815 | u32 val; | |
2816 | ||
2817 | for_each_pipe(dev_priv, pipe) { | |
dd740780 | 2818 | for_each_plane(dev_priv, pipe, plane) { |
a269c583 DL |
2819 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
2820 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], | |
2821 | val); | |
2822 | } | |
2823 | ||
2824 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
4969d33e MR |
2825 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], |
2826 | val); | |
a269c583 DL |
2827 | } |
2828 | } | |
2829 | ||
b9cec075 | 2830 | static unsigned int |
024c9045 MR |
2831 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
2832 | const struct drm_plane_state *pstate, | |
2833 | int y) | |
b9cec075 | 2834 | { |
024c9045 MR |
2835 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
2836 | struct drm_framebuffer *fb = pstate->fb; | |
2cd601c6 CK |
2837 | |
2838 | /* for planar format */ | |
024c9045 | 2839 | if (fb->pixel_format == DRM_FORMAT_NV12) { |
2cd601c6 | 2840 | if (y) /* y-plane data rate */ |
024c9045 MR |
2841 | return intel_crtc->config->pipe_src_w * |
2842 | intel_crtc->config->pipe_src_h * | |
2843 | drm_format_plane_cpp(fb->pixel_format, 0); | |
2cd601c6 | 2844 | else /* uv-plane data rate */ |
024c9045 MR |
2845 | return (intel_crtc->config->pipe_src_w/2) * |
2846 | (intel_crtc->config->pipe_src_h/2) * | |
2847 | drm_format_plane_cpp(fb->pixel_format, 1); | |
2cd601c6 CK |
2848 | } |
2849 | ||
2850 | /* for packed formats */ | |
024c9045 MR |
2851 | return intel_crtc->config->pipe_src_w * |
2852 | intel_crtc->config->pipe_src_h * | |
2853 | drm_format_plane_cpp(fb->pixel_format, 0); | |
b9cec075 DL |
2854 | } |
2855 | ||
2856 | /* | |
2857 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
2858 | * a 8192x4096@32bpp framebuffer: | |
2859 | * 3 * 4096 * 8192 * 4 < 2^32 | |
2860 | */ | |
2861 | static unsigned int | |
024c9045 | 2862 | skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate) |
b9cec075 | 2863 | { |
024c9045 MR |
2864 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
2865 | struct drm_device *dev = intel_crtc->base.dev; | |
2866 | const struct intel_plane *intel_plane; | |
b9cec075 | 2867 | unsigned int total_data_rate = 0; |
b9cec075 | 2868 | |
024c9045 MR |
2869 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
2870 | const struct drm_plane_state *pstate = intel_plane->base.state; | |
b9cec075 | 2871 | |
024c9045 | 2872 | if (pstate->fb == NULL) |
b9cec075 DL |
2873 | continue; |
2874 | ||
024c9045 MR |
2875 | if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) |
2876 | continue; | |
2877 | ||
2878 | /* packed/uv */ | |
2879 | total_data_rate += skl_plane_relative_data_rate(cstate, | |
2880 | pstate, | |
2881 | 0); | |
2882 | ||
2883 | if (pstate->fb->pixel_format == DRM_FORMAT_NV12) | |
2884 | /* y-plane */ | |
2885 | total_data_rate += skl_plane_relative_data_rate(cstate, | |
2886 | pstate, | |
2887 | 1); | |
b9cec075 DL |
2888 | } |
2889 | ||
2890 | return total_data_rate; | |
2891 | } | |
2892 | ||
2893 | static void | |
024c9045 | 2894 | skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, |
b9cec075 DL |
2895 | struct skl_ddb_allocation *ddb /* out */) |
2896 | { | |
024c9045 | 2897 | struct drm_crtc *crtc = cstate->base.crtc; |
b9cec075 | 2898 | struct drm_device *dev = crtc->dev; |
aa363136 MR |
2899 | struct drm_i915_private *dev_priv = to_i915(dev); |
2900 | struct intel_wm_config *config = &dev_priv->wm.config; | |
b9cec075 | 2901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
024c9045 | 2902 | struct intel_plane *intel_plane; |
b9cec075 | 2903 | enum pipe pipe = intel_crtc->pipe; |
34bb56af | 2904 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
b9cec075 | 2905 | uint16_t alloc_size, start, cursor_blocks; |
80958155 | 2906 | uint16_t minimum[I915_MAX_PLANES]; |
2cd601c6 | 2907 | uint16_t y_minimum[I915_MAX_PLANES]; |
b9cec075 | 2908 | unsigned int total_data_rate; |
b9cec075 | 2909 | |
024c9045 | 2910 | skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc); |
34bb56af | 2911 | alloc_size = skl_ddb_entry_size(alloc); |
b9cec075 DL |
2912 | if (alloc_size == 0) { |
2913 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
4969d33e MR |
2914 | memset(&ddb->plane[pipe][PLANE_CURSOR], 0, |
2915 | sizeof(ddb->plane[pipe][PLANE_CURSOR])); | |
b9cec075 DL |
2916 | return; |
2917 | } | |
2918 | ||
2919 | cursor_blocks = skl_cursor_allocation(config); | |
4969d33e MR |
2920 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; |
2921 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; | |
b9cec075 DL |
2922 | |
2923 | alloc_size -= cursor_blocks; | |
34bb56af | 2924 | alloc->end -= cursor_blocks; |
b9cec075 | 2925 | |
80958155 | 2926 | /* 1. Allocate the mininum required blocks for each active plane */ |
024c9045 MR |
2927 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
2928 | struct drm_plane *plane = &intel_plane->base; | |
2929 | struct drm_framebuffer *fb = plane->state->fb; | |
2930 | int id = skl_wm_plane_id(intel_plane); | |
80958155 | 2931 | |
024c9045 MR |
2932 | if (fb == NULL) |
2933 | continue; | |
2934 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
80958155 DL |
2935 | continue; |
2936 | ||
024c9045 MR |
2937 | minimum[id] = 8; |
2938 | alloc_size -= minimum[id]; | |
2939 | y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0; | |
2940 | alloc_size -= y_minimum[id]; | |
80958155 DL |
2941 | } |
2942 | ||
b9cec075 | 2943 | /* |
80958155 DL |
2944 | * 2. Distribute the remaining space in proportion to the amount of |
2945 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
2946 | * |
2947 | * FIXME: we may not allocate every single block here. | |
2948 | */ | |
024c9045 | 2949 | total_data_rate = skl_get_total_relative_data_rate(cstate); |
b9cec075 | 2950 | |
34bb56af | 2951 | start = alloc->start; |
024c9045 MR |
2952 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
2953 | struct drm_plane *plane = &intel_plane->base; | |
2954 | struct drm_plane_state *pstate = intel_plane->base.state; | |
2cd601c6 CK |
2955 | unsigned int data_rate, y_data_rate; |
2956 | uint16_t plane_blocks, y_plane_blocks = 0; | |
024c9045 | 2957 | int id = skl_wm_plane_id(intel_plane); |
b9cec075 | 2958 | |
024c9045 MR |
2959 | if (pstate->fb == NULL) |
2960 | continue; | |
2961 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
b9cec075 DL |
2962 | continue; |
2963 | ||
024c9045 | 2964 | data_rate = skl_plane_relative_data_rate(cstate, pstate, 0); |
b9cec075 DL |
2965 | |
2966 | /* | |
2cd601c6 | 2967 | * allocation for (packed formats) or (uv-plane part of planar format): |
b9cec075 DL |
2968 | * promote the expression to 64 bits to avoid overflowing, the |
2969 | * result is < available as data_rate / total_data_rate < 1 | |
2970 | */ | |
024c9045 | 2971 | plane_blocks = minimum[id]; |
80958155 DL |
2972 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
2973 | total_data_rate); | |
b9cec075 | 2974 | |
024c9045 MR |
2975 | ddb->plane[pipe][id].start = start; |
2976 | ddb->plane[pipe][id].end = start + plane_blocks; | |
b9cec075 DL |
2977 | |
2978 | start += plane_blocks; | |
2cd601c6 CK |
2979 | |
2980 | /* | |
2981 | * allocation for y_plane part of planar format: | |
2982 | */ | |
024c9045 MR |
2983 | if (pstate->fb->pixel_format == DRM_FORMAT_NV12) { |
2984 | y_data_rate = skl_plane_relative_data_rate(cstate, | |
2985 | pstate, | |
2986 | 1); | |
2987 | y_plane_blocks = y_minimum[id]; | |
2cd601c6 CK |
2988 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
2989 | total_data_rate); | |
2990 | ||
024c9045 MR |
2991 | ddb->y_plane[pipe][id].start = start; |
2992 | ddb->y_plane[pipe][id].end = start + y_plane_blocks; | |
2cd601c6 CK |
2993 | |
2994 | start += y_plane_blocks; | |
2995 | } | |
2996 | ||
b9cec075 DL |
2997 | } |
2998 | ||
2999 | } | |
3000 | ||
5cec258b | 3001 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
2d41c0b5 PB |
3002 | { |
3003 | /* TODO: Take into account the scalers once we support them */ | |
2d112de7 | 3004 | return config->base.adjusted_mode.crtc_clock; |
2d41c0b5 PB |
3005 | } |
3006 | ||
3007 | /* | |
3008 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
3009 | * for the read latency) and bytes_per_pixel should always be <= 8, so that | |
3010 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max | |
3011 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
3012 | */ | |
3013 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
3014 | uint32_t latency) | |
3015 | { | |
3016 | uint32_t wm_intermediate_val, ret; | |
3017 | ||
3018 | if (latency == 0) | |
3019 | return UINT_MAX; | |
3020 | ||
d4c2aa60 | 3021 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
2d41c0b5 PB |
3022 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
3023 | ||
3024 | return ret; | |
3025 | } | |
3026 | ||
3027 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
3028 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
0fda6568 | 3029 | uint64_t tiling, uint32_t latency) |
2d41c0b5 | 3030 | { |
d4c2aa60 TU |
3031 | uint32_t ret; |
3032 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
3033 | uint32_t wm_intermediate_val; | |
2d41c0b5 PB |
3034 | |
3035 | if (latency == 0) | |
3036 | return UINT_MAX; | |
3037 | ||
3038 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; | |
0fda6568 TU |
3039 | |
3040 | if (tiling == I915_FORMAT_MOD_Y_TILED || | |
3041 | tiling == I915_FORMAT_MOD_Yf_TILED) { | |
3042 | plane_bytes_per_line *= 4; | |
3043 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
3044 | plane_blocks_per_line /= 4; | |
3045 | } else { | |
3046 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
3047 | } | |
3048 | ||
2d41c0b5 PB |
3049 | wm_intermediate_val = latency * pixel_rate; |
3050 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * | |
d4c2aa60 | 3051 | plane_blocks_per_line; |
2d41c0b5 PB |
3052 | |
3053 | return ret; | |
3054 | } | |
3055 | ||
2d41c0b5 PB |
3056 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
3057 | const struct intel_crtc *intel_crtc) | |
3058 | { | |
3059 | struct drm_device *dev = intel_crtc->base.dev; | |
3060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3061 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3062 | enum pipe pipe = intel_crtc->pipe; | |
3063 | ||
3064 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], | |
3065 | sizeof(new_ddb->plane[pipe]))) | |
3066 | return true; | |
3067 | ||
4969d33e MR |
3068 | if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR], |
3069 | sizeof(new_ddb->plane[pipe][PLANE_CURSOR]))) | |
2d41c0b5 PB |
3070 | return true; |
3071 | ||
3072 | return false; | |
3073 | } | |
3074 | ||
d4c2aa60 | 3075 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
024c9045 MR |
3076 | struct intel_crtc_state *cstate, |
3077 | struct intel_plane *intel_plane, | |
afb024aa | 3078 | uint16_t ddb_allocation, |
d4c2aa60 | 3079 | int level, |
afb024aa DL |
3080 | uint16_t *out_blocks, /* out */ |
3081 | uint8_t *out_lines /* out */) | |
2d41c0b5 | 3082 | { |
024c9045 MR |
3083 | struct drm_plane *plane = &intel_plane->base; |
3084 | struct drm_framebuffer *fb = plane->state->fb; | |
d4c2aa60 TU |
3085 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
3086 | uint32_t method1, method2; | |
3087 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
3088 | uint32_t res_blocks, res_lines; | |
3089 | uint32_t selected_result; | |
2cd601c6 | 3090 | uint8_t bytes_per_pixel; |
2d41c0b5 | 3091 | |
024c9045 | 3092 | if (latency == 0 || !cstate->base.active || !fb) |
2d41c0b5 PB |
3093 | return false; |
3094 | ||
024c9045 MR |
3095 | bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0); |
3096 | method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate), | |
2cd601c6 | 3097 | bytes_per_pixel, |
d4c2aa60 | 3098 | latency); |
024c9045 MR |
3099 | method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate), |
3100 | cstate->base.adjusted_mode.crtc_htotal, | |
3101 | cstate->pipe_src_w, | |
2cd601c6 | 3102 | bytes_per_pixel, |
024c9045 | 3103 | fb->modifier[0], |
d4c2aa60 | 3104 | latency); |
2d41c0b5 | 3105 | |
024c9045 | 3106 | plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel; |
d4c2aa60 | 3107 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
2d41c0b5 | 3108 | |
024c9045 MR |
3109 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
3110 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { | |
1fc0a8f7 TU |
3111 | uint32_t min_scanlines = 4; |
3112 | uint32_t y_tile_minimum; | |
024c9045 MR |
3113 | if (intel_rotation_90_or_270(plane->state->rotation)) { |
3114 | int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ? | |
3115 | drm_format_plane_cpp(fb->pixel_format, 1) : | |
3116 | drm_format_plane_cpp(fb->pixel_format, 0); | |
3117 | ||
3118 | switch (bpp) { | |
1fc0a8f7 TU |
3119 | case 1: |
3120 | min_scanlines = 16; | |
3121 | break; | |
3122 | case 2: | |
3123 | min_scanlines = 8; | |
3124 | break; | |
3125 | case 8: | |
3126 | WARN(1, "Unsupported pixel depth for rotation"); | |
2f0b5790 | 3127 | } |
1fc0a8f7 TU |
3128 | } |
3129 | y_tile_minimum = plane_blocks_per_line * min_scanlines; | |
0fda6568 TU |
3130 | selected_result = max(method2, y_tile_minimum); |
3131 | } else { | |
3132 | if ((ddb_allocation / plane_blocks_per_line) >= 1) | |
3133 | selected_result = min(method1, method2); | |
3134 | else | |
3135 | selected_result = method1; | |
3136 | } | |
2d41c0b5 | 3137 | |
d4c2aa60 TU |
3138 | res_blocks = selected_result + 1; |
3139 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); | |
e6d66171 | 3140 | |
0fda6568 | 3141 | if (level >= 1 && level <= 7) { |
024c9045 MR |
3142 | if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || |
3143 | fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) | |
0fda6568 TU |
3144 | res_lines += 4; |
3145 | else | |
3146 | res_blocks++; | |
3147 | } | |
e6d66171 | 3148 | |
d4c2aa60 | 3149 | if (res_blocks >= ddb_allocation || res_lines > 31) |
e6d66171 DL |
3150 | return false; |
3151 | ||
3152 | *out_blocks = res_blocks; | |
3153 | *out_lines = res_lines; | |
2d41c0b5 PB |
3154 | |
3155 | return true; | |
3156 | } | |
3157 | ||
3158 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
3159 | struct skl_ddb_allocation *ddb, | |
024c9045 | 3160 | struct intel_crtc_state *cstate, |
2d41c0b5 | 3161 | int level, |
2d41c0b5 PB |
3162 | struct skl_wm_level *result) |
3163 | { | |
024c9045 MR |
3164 | struct drm_device *dev = dev_priv->dev; |
3165 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
3166 | struct intel_plane *intel_plane; | |
2d41c0b5 | 3167 | uint16_t ddb_blocks; |
024c9045 MR |
3168 | enum pipe pipe = intel_crtc->pipe; |
3169 | ||
3170 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { | |
3171 | int i = skl_wm_plane_id(intel_plane); | |
2d41c0b5 | 3172 | |
2d41c0b5 PB |
3173 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); |
3174 | ||
d4c2aa60 | 3175 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
024c9045 MR |
3176 | cstate, |
3177 | intel_plane, | |
2d41c0b5 | 3178 | ddb_blocks, |
d4c2aa60 | 3179 | level, |
2d41c0b5 PB |
3180 | &result->plane_res_b[i], |
3181 | &result->plane_res_l[i]); | |
3182 | } | |
2d41c0b5 PB |
3183 | } |
3184 | ||
407b50f3 | 3185 | static uint32_t |
024c9045 | 3186 | skl_compute_linetime_wm(struct intel_crtc_state *cstate) |
407b50f3 | 3187 | { |
024c9045 | 3188 | if (!cstate->base.active) |
407b50f3 DL |
3189 | return 0; |
3190 | ||
024c9045 | 3191 | if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) |
661abfc0 | 3192 | return 0; |
407b50f3 | 3193 | |
024c9045 MR |
3194 | return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, |
3195 | skl_pipe_pixel_rate(cstate)); | |
407b50f3 DL |
3196 | } |
3197 | ||
024c9045 | 3198 | static void skl_compute_transition_wm(struct intel_crtc_state *cstate, |
9414f563 | 3199 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 3200 | { |
024c9045 | 3201 | struct drm_crtc *crtc = cstate->base.crtc; |
9414f563 | 3202 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
024c9045 | 3203 | struct intel_plane *intel_plane; |
9414f563 | 3204 | |
024c9045 | 3205 | if (!cstate->base.active) |
407b50f3 | 3206 | return; |
9414f563 DL |
3207 | |
3208 | /* Until we know more, just disable transition WMs */ | |
024c9045 MR |
3209 | for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) { |
3210 | int i = skl_wm_plane_id(intel_plane); | |
3211 | ||
9414f563 | 3212 | trans_wm->plane_en[i] = false; |
024c9045 | 3213 | } |
407b50f3 DL |
3214 | } |
3215 | ||
024c9045 | 3216 | static void skl_compute_pipe_wm(struct intel_crtc_state *cstate, |
2d41c0b5 | 3217 | struct skl_ddb_allocation *ddb, |
2d41c0b5 PB |
3218 | struct skl_pipe_wm *pipe_wm) |
3219 | { | |
024c9045 | 3220 | struct drm_device *dev = cstate->base.crtc->dev; |
2d41c0b5 | 3221 | const struct drm_i915_private *dev_priv = dev->dev_private; |
2d41c0b5 PB |
3222 | int level, max_level = ilk_wm_max_level(dev); |
3223 | ||
3224 | for (level = 0; level <= max_level; level++) { | |
024c9045 MR |
3225 | skl_compute_wm_level(dev_priv, ddb, cstate, |
3226 | level, &pipe_wm->wm[level]); | |
2d41c0b5 | 3227 | } |
024c9045 | 3228 | pipe_wm->linetime = skl_compute_linetime_wm(cstate); |
2d41c0b5 | 3229 | |
024c9045 | 3230 | skl_compute_transition_wm(cstate, &pipe_wm->trans_wm); |
2d41c0b5 PB |
3231 | } |
3232 | ||
3233 | static void skl_compute_wm_results(struct drm_device *dev, | |
2d41c0b5 PB |
3234 | struct skl_pipe_wm *p_wm, |
3235 | struct skl_wm_values *r, | |
3236 | struct intel_crtc *intel_crtc) | |
3237 | { | |
3238 | int level, max_level = ilk_wm_max_level(dev); | |
3239 | enum pipe pipe = intel_crtc->pipe; | |
9414f563 DL |
3240 | uint32_t temp; |
3241 | int i; | |
2d41c0b5 PB |
3242 | |
3243 | for (level = 0; level <= max_level; level++) { | |
2d41c0b5 PB |
3244 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3245 | temp = 0; | |
2d41c0b5 PB |
3246 | |
3247 | temp |= p_wm->wm[level].plane_res_l[i] << | |
3248 | PLANE_WM_LINES_SHIFT; | |
3249 | temp |= p_wm->wm[level].plane_res_b[i]; | |
3250 | if (p_wm->wm[level].plane_en[i]) | |
3251 | temp |= PLANE_WM_EN; | |
3252 | ||
3253 | r->plane[pipe][i][level] = temp; | |
2d41c0b5 PB |
3254 | } |
3255 | ||
3256 | temp = 0; | |
2d41c0b5 | 3257 | |
4969d33e MR |
3258 | temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3259 | temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; | |
2d41c0b5 | 3260 | |
4969d33e | 3261 | if (p_wm->wm[level].plane_en[PLANE_CURSOR]) |
2d41c0b5 PB |
3262 | temp |= PLANE_WM_EN; |
3263 | ||
4969d33e | 3264 | r->plane[pipe][PLANE_CURSOR][level] = temp; |
2d41c0b5 PB |
3265 | |
3266 | } | |
3267 | ||
9414f563 DL |
3268 | /* transition WMs */ |
3269 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3270 | temp = 0; | |
3271 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; | |
3272 | temp |= p_wm->trans_wm.plane_res_b[i]; | |
3273 | if (p_wm->trans_wm.plane_en[i]) | |
3274 | temp |= PLANE_WM_EN; | |
3275 | ||
3276 | r->plane_trans[pipe][i] = temp; | |
3277 | } | |
3278 | ||
3279 | temp = 0; | |
4969d33e MR |
3280 | temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; |
3281 | temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; | |
3282 | if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) | |
9414f563 DL |
3283 | temp |= PLANE_WM_EN; |
3284 | ||
4969d33e | 3285 | r->plane_trans[pipe][PLANE_CURSOR] = temp; |
9414f563 | 3286 | |
2d41c0b5 PB |
3287 | r->wm_linetime[pipe] = p_wm->linetime; |
3288 | } | |
3289 | ||
16160e3d DL |
3290 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
3291 | const struct skl_ddb_entry *entry) | |
3292 | { | |
3293 | if (entry->end) | |
3294 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
3295 | else | |
3296 | I915_WRITE(reg, 0); | |
3297 | } | |
3298 | ||
2d41c0b5 PB |
3299 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
3300 | const struct skl_wm_values *new) | |
3301 | { | |
3302 | struct drm_device *dev = dev_priv->dev; | |
3303 | struct intel_crtc *crtc; | |
3304 | ||
3305 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3306 | int i, level, max_level = ilk_wm_max_level(dev); | |
3307 | enum pipe pipe = crtc->pipe; | |
3308 | ||
5d374d96 DL |
3309 | if (!new->dirty[pipe]) |
3310 | continue; | |
8211bd5b | 3311 | |
5d374d96 | 3312 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
8211bd5b | 3313 | |
5d374d96 DL |
3314 | for (level = 0; level <= max_level; level++) { |
3315 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3316 | I915_WRITE(PLANE_WM(pipe, i, level), | |
3317 | new->plane[pipe][i][level]); | |
3318 | I915_WRITE(CUR_WM(pipe, level), | |
4969d33e | 3319 | new->plane[pipe][PLANE_CURSOR][level]); |
2d41c0b5 | 3320 | } |
5d374d96 DL |
3321 | for (i = 0; i < intel_num_planes(crtc); i++) |
3322 | I915_WRITE(PLANE_WM_TRANS(pipe, i), | |
3323 | new->plane_trans[pipe][i]); | |
4969d33e MR |
3324 | I915_WRITE(CUR_WM_TRANS(pipe), |
3325 | new->plane_trans[pipe][PLANE_CURSOR]); | |
5d374d96 | 3326 | |
2cd601c6 | 3327 | for (i = 0; i < intel_num_planes(crtc); i++) { |
5d374d96 DL |
3328 | skl_ddb_entry_write(dev_priv, |
3329 | PLANE_BUF_CFG(pipe, i), | |
3330 | &new->ddb.plane[pipe][i]); | |
2cd601c6 CK |
3331 | skl_ddb_entry_write(dev_priv, |
3332 | PLANE_NV12_BUF_CFG(pipe, i), | |
3333 | &new->ddb.y_plane[pipe][i]); | |
3334 | } | |
5d374d96 DL |
3335 | |
3336 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), | |
4969d33e | 3337 | &new->ddb.plane[pipe][PLANE_CURSOR]); |
2d41c0b5 | 3338 | } |
2d41c0b5 PB |
3339 | } |
3340 | ||
0e8fb7ba DL |
3341 | /* |
3342 | * When setting up a new DDB allocation arrangement, we need to correctly | |
3343 | * sequence the times at which the new allocations for the pipes are taken into | |
3344 | * account or we'll have pipes fetching from space previously allocated to | |
3345 | * another pipe. | |
3346 | * | |
3347 | * Roughly the sequence looks like: | |
3348 | * 1. re-allocate the pipe(s) with the allocation being reduced and not | |
3349 | * overlapping with a previous light-up pipe (another way to put it is: | |
3350 | * pipes with their new allocation strickly included into their old ones). | |
3351 | * 2. re-allocate the other pipes that get their allocation reduced | |
3352 | * 3. allocate the pipes having their allocation increased | |
3353 | * | |
3354 | * Steps 1. and 2. are here to take care of the following case: | |
3355 | * - Initially DDB looks like this: | |
3356 | * | B | C | | |
3357 | * - enable pipe A. | |
3358 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C | |
3359 | * allocation | |
3360 | * | A | B | C | | |
3361 | * | |
3362 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). | |
3363 | */ | |
3364 | ||
d21b795c DL |
3365 | static void |
3366 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) | |
0e8fb7ba | 3367 | { |
0e8fb7ba DL |
3368 | int plane; |
3369 | ||
d21b795c DL |
3370 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
3371 | ||
dd740780 | 3372 | for_each_plane(dev_priv, pipe, plane) { |
0e8fb7ba DL |
3373 | I915_WRITE(PLANE_SURF(pipe, plane), |
3374 | I915_READ(PLANE_SURF(pipe, plane))); | |
3375 | } | |
3376 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3377 | } | |
3378 | ||
3379 | static bool | |
3380 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, | |
3381 | const struct skl_ddb_allocation *new, | |
3382 | enum pipe pipe) | |
3383 | { | |
3384 | uint16_t old_size, new_size; | |
3385 | ||
3386 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); | |
3387 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); | |
3388 | ||
3389 | return old_size != new_size && | |
3390 | new->pipe[pipe].start >= old->pipe[pipe].start && | |
3391 | new->pipe[pipe].end <= old->pipe[pipe].end; | |
3392 | } | |
3393 | ||
3394 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, | |
3395 | struct skl_wm_values *new_values) | |
3396 | { | |
3397 | struct drm_device *dev = dev_priv->dev; | |
3398 | struct skl_ddb_allocation *cur_ddb, *new_ddb; | |
c929cb45 | 3399 | bool reallocated[I915_MAX_PIPES] = {}; |
0e8fb7ba DL |
3400 | struct intel_crtc *crtc; |
3401 | enum pipe pipe; | |
3402 | ||
3403 | new_ddb = &new_values->ddb; | |
3404 | cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3405 | ||
3406 | /* | |
3407 | * First pass: flush the pipes with the new allocation contained into | |
3408 | * the old space. | |
3409 | * | |
3410 | * We'll wait for the vblank on those pipes to ensure we can safely | |
3411 | * re-allocate the freed space without this pipe fetching from it. | |
3412 | */ | |
3413 | for_each_intel_crtc(dev, crtc) { | |
3414 | if (!crtc->active) | |
3415 | continue; | |
3416 | ||
3417 | pipe = crtc->pipe; | |
3418 | ||
3419 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) | |
3420 | continue; | |
3421 | ||
d21b795c | 3422 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
0e8fb7ba DL |
3423 | intel_wait_for_vblank(dev, pipe); |
3424 | ||
3425 | reallocated[pipe] = true; | |
3426 | } | |
3427 | ||
3428 | ||
3429 | /* | |
3430 | * Second pass: flush the pipes that are having their allocation | |
3431 | * reduced, but overlapping with a previous allocation. | |
3432 | * | |
3433 | * Here as well we need to wait for the vblank to make sure the freed | |
3434 | * space is not used anymore. | |
3435 | */ | |
3436 | for_each_intel_crtc(dev, crtc) { | |
3437 | if (!crtc->active) | |
3438 | continue; | |
3439 | ||
3440 | pipe = crtc->pipe; | |
3441 | ||
3442 | if (reallocated[pipe]) | |
3443 | continue; | |
3444 | ||
3445 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < | |
3446 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { | |
d21b795c | 3447 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
0e8fb7ba | 3448 | intel_wait_for_vblank(dev, pipe); |
d9d8e6b3 | 3449 | reallocated[pipe] = true; |
0e8fb7ba | 3450 | } |
0e8fb7ba DL |
3451 | } |
3452 | ||
3453 | /* | |
3454 | * Third pass: flush the pipes that got more space allocated. | |
3455 | * | |
3456 | * We don't need to actively wait for the update here, next vblank | |
3457 | * will just get more DDB space with the correct WM values. | |
3458 | */ | |
3459 | for_each_intel_crtc(dev, crtc) { | |
3460 | if (!crtc->active) | |
3461 | continue; | |
3462 | ||
3463 | pipe = crtc->pipe; | |
3464 | ||
3465 | /* | |
3466 | * At this point, only the pipes more space than before are | |
3467 | * left to re-allocate. | |
3468 | */ | |
3469 | if (reallocated[pipe]) | |
3470 | continue; | |
3471 | ||
d21b795c | 3472 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
0e8fb7ba DL |
3473 | } |
3474 | } | |
3475 | ||
2d41c0b5 | 3476 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
2d41c0b5 PB |
3477 | struct skl_ddb_allocation *ddb, /* out */ |
3478 | struct skl_pipe_wm *pipe_wm /* out */) | |
3479 | { | |
3480 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
024c9045 | 3481 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
2d41c0b5 | 3482 | |
aa363136 | 3483 | skl_allocate_pipe_ddb(cstate, ddb); |
024c9045 | 3484 | skl_compute_pipe_wm(cstate, ddb, pipe_wm); |
2d41c0b5 | 3485 | |
4e0963c7 | 3486 | if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm))) |
2d41c0b5 PB |
3487 | return false; |
3488 | ||
4e0963c7 | 3489 | intel_crtc->wm.active.skl = *pipe_wm; |
2cd601c6 | 3490 | |
2d41c0b5 PB |
3491 | return true; |
3492 | } | |
3493 | ||
3494 | static void skl_update_other_pipe_wm(struct drm_device *dev, | |
3495 | struct drm_crtc *crtc, | |
2d41c0b5 PB |
3496 | struct skl_wm_values *r) |
3497 | { | |
3498 | struct intel_crtc *intel_crtc; | |
3499 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); | |
3500 | ||
3501 | /* | |
3502 | * If the WM update hasn't changed the allocation for this_crtc (the | |
3503 | * crtc we are currently computing the new WM values for), other | |
3504 | * enabled crtcs will keep the same allocation and we don't need to | |
3505 | * recompute anything for them. | |
3506 | */ | |
3507 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) | |
3508 | return; | |
3509 | ||
3510 | /* | |
3511 | * Otherwise, because of this_crtc being freshly enabled/disabled, the | |
3512 | * other active pipes need new DDB allocation and WM values. | |
3513 | */ | |
3514 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
3515 | base.head) { | |
2d41c0b5 PB |
3516 | struct skl_pipe_wm pipe_wm = {}; |
3517 | bool wm_changed; | |
3518 | ||
3519 | if (this_crtc->pipe == intel_crtc->pipe) | |
3520 | continue; | |
3521 | ||
3522 | if (!intel_crtc->active) | |
3523 | continue; | |
3524 | ||
aa363136 | 3525 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, |
2d41c0b5 PB |
3526 | &r->ddb, &pipe_wm); |
3527 | ||
3528 | /* | |
3529 | * If we end up re-computing the other pipe WM values, it's | |
3530 | * because it was really needed, so we expect the WM values to | |
3531 | * be different. | |
3532 | */ | |
3533 | WARN_ON(!wm_changed); | |
3534 | ||
024c9045 | 3535 | skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc); |
2d41c0b5 PB |
3536 | r->dirty[intel_crtc->pipe] = true; |
3537 | } | |
3538 | } | |
3539 | ||
adda50b8 BP |
3540 | static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe) |
3541 | { | |
3542 | watermarks->wm_linetime[pipe] = 0; | |
3543 | memset(watermarks->plane[pipe], 0, | |
3544 | sizeof(uint32_t) * 8 * I915_MAX_PLANES); | |
adda50b8 BP |
3545 | memset(watermarks->plane_trans[pipe], |
3546 | 0, sizeof(uint32_t) * I915_MAX_PLANES); | |
4969d33e | 3547 | watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; |
adda50b8 BP |
3548 | |
3549 | /* Clear ddb entries for pipe */ | |
3550 | memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); | |
3551 | memset(&watermarks->ddb.plane[pipe], 0, | |
3552 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); | |
3553 | memset(&watermarks->ddb.y_plane[pipe], 0, | |
3554 | sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); | |
4969d33e MR |
3555 | memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, |
3556 | sizeof(struct skl_ddb_entry)); | |
adda50b8 BP |
3557 | |
3558 | } | |
3559 | ||
2d41c0b5 PB |
3560 | static void skl_update_wm(struct drm_crtc *crtc) |
3561 | { | |
3562 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3563 | struct drm_device *dev = crtc->dev; | |
3564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2d41c0b5 | 3565 | struct skl_wm_values *results = &dev_priv->wm.skl_results; |
4e0963c7 MR |
3566 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3567 | struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl; | |
2d41c0b5 | 3568 | |
adda50b8 BP |
3569 | |
3570 | /* Clear all dirty flags */ | |
3571 | memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); | |
3572 | ||
3573 | skl_clear_wm(results, intel_crtc->pipe); | |
2d41c0b5 | 3574 | |
aa363136 | 3575 | if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm)) |
2d41c0b5 PB |
3576 | return; |
3577 | ||
4e0963c7 | 3578 | skl_compute_wm_results(dev, pipe_wm, results, intel_crtc); |
2d41c0b5 PB |
3579 | results->dirty[intel_crtc->pipe] = true; |
3580 | ||
aa363136 | 3581 | skl_update_other_pipe_wm(dev, crtc, results); |
2d41c0b5 | 3582 | skl_write_wm_values(dev_priv, results); |
0e8fb7ba | 3583 | skl_flush_wm_values(dev_priv, results); |
53b0deb4 DL |
3584 | |
3585 | /* store the new configuration */ | |
3586 | dev_priv->wm.skl_hw = *results; | |
2d41c0b5 PB |
3587 | } |
3588 | ||
b9d5c839 | 3589 | static void ilk_program_watermarks(struct drm_i915_private *dev_priv) |
801bcfff | 3590 | { |
b9d5c839 VS |
3591 | struct drm_device *dev = dev_priv->dev; |
3592 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; | |
820c1980 | 3593 | struct ilk_wm_maximums max; |
aa363136 | 3594 | struct intel_wm_config *config = &dev_priv->wm.config; |
820c1980 | 3595 | struct ilk_wm_values results = {}; |
77c122bc | 3596 | enum intel_ddb_partitioning partitioning; |
261a27d1 | 3597 | |
aa363136 MR |
3598 | ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max); |
3599 | ilk_wm_merge(dev, config, &max, &lp_wm_1_2); | |
a485bfb8 VS |
3600 | |
3601 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 | 3602 | if (INTEL_INFO(dev)->gen >= 7 && |
aa363136 MR |
3603 | config->num_pipes_active == 1 && config->sprites_enabled) { |
3604 | ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max); | |
3605 | ilk_wm_merge(dev, config, &max, &lp_wm_5_6); | |
0362c781 | 3606 | |
820c1980 | 3607 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 3608 | } else { |
198a1e9b | 3609 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
3610 | } |
3611 | ||
198a1e9b | 3612 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 3613 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 3614 | |
820c1980 | 3615 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 3616 | |
820c1980 | 3617 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
3618 | } |
3619 | ||
b9d5c839 VS |
3620 | static void ilk_update_wm(struct drm_crtc *crtc) |
3621 | { | |
3622 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
3623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3624 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); | |
b9d5c839 VS |
3625 | |
3626 | WARN_ON(cstate->base.active != intel_crtc->active); | |
3627 | ||
3628 | /* | |
3629 | * IVB workaround: must disable low power watermarks for at least | |
3630 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
3631 | * when scaling is disabled. | |
3632 | * | |
3633 | * WaCxSRDisabledForSpriteScaling:ivb | |
3634 | */ | |
3635 | if (cstate->disable_lp_wm) { | |
3636 | ilk_disable_lp_wm(crtc->dev); | |
3637 | intel_wait_for_vblank(crtc->dev, intel_crtc->pipe); | |
3638 | } | |
3639 | ||
4e0963c7 | 3640 | intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk; |
b9d5c839 VS |
3641 | |
3642 | ilk_program_watermarks(dev_priv); | |
3643 | } | |
3644 | ||
3078999f PB |
3645 | static void skl_pipe_wm_active_state(uint32_t val, |
3646 | struct skl_pipe_wm *active, | |
3647 | bool is_transwm, | |
3648 | bool is_cursor, | |
3649 | int i, | |
3650 | int level) | |
3651 | { | |
3652 | bool is_enabled = (val & PLANE_WM_EN) != 0; | |
3653 | ||
3654 | if (!is_transwm) { | |
3655 | if (!is_cursor) { | |
3656 | active->wm[level].plane_en[i] = is_enabled; | |
3657 | active->wm[level].plane_res_b[i] = | |
3658 | val & PLANE_WM_BLOCKS_MASK; | |
3659 | active->wm[level].plane_res_l[i] = | |
3660 | (val >> PLANE_WM_LINES_SHIFT) & | |
3661 | PLANE_WM_LINES_MASK; | |
3662 | } else { | |
4969d33e MR |
3663 | active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; |
3664 | active->wm[level].plane_res_b[PLANE_CURSOR] = | |
3078999f | 3665 | val & PLANE_WM_BLOCKS_MASK; |
4969d33e | 3666 | active->wm[level].plane_res_l[PLANE_CURSOR] = |
3078999f PB |
3667 | (val >> PLANE_WM_LINES_SHIFT) & |
3668 | PLANE_WM_LINES_MASK; | |
3669 | } | |
3670 | } else { | |
3671 | if (!is_cursor) { | |
3672 | active->trans_wm.plane_en[i] = is_enabled; | |
3673 | active->trans_wm.plane_res_b[i] = | |
3674 | val & PLANE_WM_BLOCKS_MASK; | |
3675 | active->trans_wm.plane_res_l[i] = | |
3676 | (val >> PLANE_WM_LINES_SHIFT) & | |
3677 | PLANE_WM_LINES_MASK; | |
3678 | } else { | |
4969d33e MR |
3679 | active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; |
3680 | active->trans_wm.plane_res_b[PLANE_CURSOR] = | |
3078999f | 3681 | val & PLANE_WM_BLOCKS_MASK; |
4969d33e | 3682 | active->trans_wm.plane_res_l[PLANE_CURSOR] = |
3078999f PB |
3683 | (val >> PLANE_WM_LINES_SHIFT) & |
3684 | PLANE_WM_LINES_MASK; | |
3685 | } | |
3686 | } | |
3687 | } | |
3688 | ||
3689 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3690 | { | |
3691 | struct drm_device *dev = crtc->dev; | |
3692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3693 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; | |
3694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4e0963c7 MR |
3695 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3696 | struct skl_pipe_wm *active = &cstate->wm.optimal.skl; | |
3078999f PB |
3697 | enum pipe pipe = intel_crtc->pipe; |
3698 | int level, i, max_level; | |
3699 | uint32_t temp; | |
3700 | ||
3701 | max_level = ilk_wm_max_level(dev); | |
3702 | ||
3703 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3704 | ||
3705 | for (level = 0; level <= max_level; level++) { | |
3706 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3707 | hw->plane[pipe][i][level] = | |
3708 | I915_READ(PLANE_WM(pipe, i, level)); | |
4969d33e | 3709 | hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); |
3078999f PB |
3710 | } |
3711 | ||
3712 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3713 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); | |
4969d33e | 3714 | hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); |
3078999f | 3715 | |
3ef00284 | 3716 | if (!intel_crtc->active) |
3078999f PB |
3717 | return; |
3718 | ||
3719 | hw->dirty[pipe] = true; | |
3720 | ||
3721 | active->linetime = hw->wm_linetime[pipe]; | |
3722 | ||
3723 | for (level = 0; level <= max_level; level++) { | |
3724 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3725 | temp = hw->plane[pipe][i][level]; | |
3726 | skl_pipe_wm_active_state(temp, active, false, | |
3727 | false, i, level); | |
3728 | } | |
4969d33e | 3729 | temp = hw->plane[pipe][PLANE_CURSOR][level]; |
3078999f PB |
3730 | skl_pipe_wm_active_state(temp, active, false, true, i, level); |
3731 | } | |
3732 | ||
3733 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3734 | temp = hw->plane_trans[pipe][i]; | |
3735 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); | |
3736 | } | |
3737 | ||
4969d33e | 3738 | temp = hw->plane_trans[pipe][PLANE_CURSOR]; |
3078999f | 3739 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); |
4e0963c7 MR |
3740 | |
3741 | intel_crtc->wm.active.skl = *active; | |
3078999f PB |
3742 | } |
3743 | ||
3744 | void skl_wm_get_hw_state(struct drm_device *dev) | |
3745 | { | |
a269c583 DL |
3746 | struct drm_i915_private *dev_priv = dev->dev_private; |
3747 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; | |
3078999f PB |
3748 | struct drm_crtc *crtc; |
3749 | ||
a269c583 | 3750 | skl_ddb_get_hw_state(dev_priv, ddb); |
3078999f PB |
3751 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
3752 | skl_pipe_wm_get_hw_state(crtc); | |
3753 | } | |
3754 | ||
243e6a44 VS |
3755 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3756 | { | |
3757 | struct drm_device *dev = crtc->dev; | |
3758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3759 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 | 3760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4e0963c7 MR |
3761 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3762 | struct intel_pipe_wm *active = &cstate->wm.optimal.ilk; | |
243e6a44 VS |
3763 | enum pipe pipe = intel_crtc->pipe; |
3764 | static const unsigned int wm0_pipe_reg[] = { | |
3765 | [PIPE_A] = WM0_PIPEA_ILK, | |
3766 | [PIPE_B] = WM0_PIPEB_ILK, | |
3767 | [PIPE_C] = WM0_PIPEC_IVB, | |
3768 | }; | |
3769 | ||
3770 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 3771 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 3772 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 3773 | |
3ef00284 | 3774 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
3775 | |
3776 | if (active->pipe_enabled) { | |
243e6a44 VS |
3777 | u32 tmp = hw->wm_pipe[pipe]; |
3778 | ||
3779 | /* | |
3780 | * For active pipes LP0 watermark is marked as | |
3781 | * enabled, and LP1+ watermaks as disabled since | |
3782 | * we can't really reverse compute them in case | |
3783 | * multiple pipes are active. | |
3784 | */ | |
3785 | active->wm[0].enable = true; | |
3786 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
3787 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
3788 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
3789 | active->linetime = hw->wm_linetime[pipe]; | |
3790 | } else { | |
3791 | int level, max_level = ilk_wm_max_level(dev); | |
3792 | ||
3793 | /* | |
3794 | * For inactive pipes, all watermark levels | |
3795 | * should be marked as enabled but zeroed, | |
3796 | * which is what we'd compute them to. | |
3797 | */ | |
3798 | for (level = 0; level <= max_level; level++) | |
3799 | active->wm[level].enable = true; | |
3800 | } | |
4e0963c7 MR |
3801 | |
3802 | intel_crtc->wm.active.ilk = *active; | |
243e6a44 VS |
3803 | } |
3804 | ||
6eb1a681 VS |
3805 | #define _FW_WM(value, plane) \ |
3806 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) | |
3807 | #define _FW_WM_VLV(value, plane) \ | |
3808 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) | |
3809 | ||
3810 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, | |
3811 | struct vlv_wm_values *wm) | |
3812 | { | |
3813 | enum pipe pipe; | |
3814 | uint32_t tmp; | |
3815 | ||
3816 | for_each_pipe(dev_priv, pipe) { | |
3817 | tmp = I915_READ(VLV_DDL(pipe)); | |
3818 | ||
3819 | wm->ddl[pipe].primary = | |
3820 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3821 | wm->ddl[pipe].cursor = | |
3822 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3823 | wm->ddl[pipe].sprite[0] = | |
3824 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3825 | wm->ddl[pipe].sprite[1] = | |
3826 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); | |
3827 | } | |
3828 | ||
3829 | tmp = I915_READ(DSPFW1); | |
3830 | wm->sr.plane = _FW_WM(tmp, SR); | |
3831 | wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); | |
3832 | wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); | |
3833 | wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); | |
3834 | ||
3835 | tmp = I915_READ(DSPFW2); | |
3836 | wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); | |
3837 | wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); | |
3838 | wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); | |
3839 | ||
3840 | tmp = I915_READ(DSPFW3); | |
3841 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
3842 | ||
3843 | if (IS_CHERRYVIEW(dev_priv)) { | |
3844 | tmp = I915_READ(DSPFW7_CHV); | |
3845 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); | |
3846 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); | |
3847 | ||
3848 | tmp = I915_READ(DSPFW8_CHV); | |
3849 | wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); | |
3850 | wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); | |
3851 | ||
3852 | tmp = I915_READ(DSPFW9_CHV); | |
3853 | wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); | |
3854 | wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); | |
3855 | ||
3856 | tmp = I915_READ(DSPHOWM); | |
3857 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
3858 | wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; | |
3859 | wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; | |
3860 | wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; | |
3861 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
3862 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
3863 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; | |
3864 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
3865 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
3866 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; | |
3867 | } else { | |
3868 | tmp = I915_READ(DSPFW7); | |
3869 | wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); | |
3870 | wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); | |
3871 | ||
3872 | tmp = I915_READ(DSPHOWM); | |
3873 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
3874 | wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
3875 | wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
3876 | wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; | |
3877 | wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
3878 | wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
3879 | wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; | |
3880 | } | |
3881 | } | |
3882 | ||
3883 | #undef _FW_WM | |
3884 | #undef _FW_WM_VLV | |
3885 | ||
3886 | void vlv_wm_get_hw_state(struct drm_device *dev) | |
3887 | { | |
3888 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3889 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; | |
3890 | struct intel_plane *plane; | |
3891 | enum pipe pipe; | |
3892 | u32 val; | |
3893 | ||
3894 | vlv_read_wm_values(dev_priv, wm); | |
3895 | ||
3896 | for_each_intel_plane(dev, plane) { | |
3897 | switch (plane->base.type) { | |
3898 | int sprite; | |
3899 | case DRM_PLANE_TYPE_CURSOR: | |
3900 | plane->wm.fifo_size = 63; | |
3901 | break; | |
3902 | case DRM_PLANE_TYPE_PRIMARY: | |
3903 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); | |
3904 | break; | |
3905 | case DRM_PLANE_TYPE_OVERLAY: | |
3906 | sprite = plane->plane; | |
3907 | plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); | |
3908 | break; | |
3909 | } | |
3910 | } | |
3911 | ||
3912 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; | |
3913 | wm->level = VLV_WM_LEVEL_PM2; | |
3914 | ||
3915 | if (IS_CHERRYVIEW(dev_priv)) { | |
3916 | mutex_lock(&dev_priv->rps.hw_lock); | |
3917 | ||
3918 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
3919 | if (val & DSP_MAXFIFO_PM5_ENABLE) | |
3920 | wm->level = VLV_WM_LEVEL_PM5; | |
3921 | ||
58590c14 VS |
3922 | /* |
3923 | * If DDR DVFS is disabled in the BIOS, Punit | |
3924 | * will never ack the request. So if that happens | |
3925 | * assume we don't have to enable/disable DDR DVFS | |
3926 | * dynamically. To test that just set the REQ_ACK | |
3927 | * bit to poke the Punit, but don't change the | |
3928 | * HIGH/LOW bits so that we don't actually change | |
3929 | * the current state. | |
3930 | */ | |
6eb1a681 | 3931 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
58590c14 VS |
3932 | val |= FORCE_DDR_FREQ_REQ_ACK; |
3933 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
3934 | ||
3935 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
3936 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { | |
3937 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " | |
3938 | "assuming DDR DVFS is disabled\n"); | |
3939 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; | |
3940 | } else { | |
3941 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
3942 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) | |
3943 | wm->level = VLV_WM_LEVEL_DDR_DVFS; | |
3944 | } | |
6eb1a681 VS |
3945 | |
3946 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3947 | } | |
3948 | ||
3949 | for_each_pipe(dev_priv, pipe) | |
3950 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", | |
3951 | pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, | |
3952 | wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); | |
3953 | ||
3954 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", | |
3955 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); | |
3956 | } | |
3957 | ||
243e6a44 VS |
3958 | void ilk_wm_get_hw_state(struct drm_device *dev) |
3959 | { | |
3960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3961 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3962 | struct drm_crtc *crtc; |
3963 | ||
70e1e0ec | 3964 | for_each_crtc(dev, crtc) |
243e6a44 VS |
3965 | ilk_pipe_wm_get_hw_state(crtc); |
3966 | ||
3967 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
3968 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
3969 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
3970 | ||
3971 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
3972 | if (INTEL_INFO(dev)->gen >= 7) { |
3973 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
3974 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
3975 | } | |
243e6a44 | 3976 | |
a42a5719 | 3977 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
3978 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
3979 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
3980 | else if (IS_IVYBRIDGE(dev)) | |
3981 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
3982 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
3983 | |
3984 | hw->enable_fbc_wm = | |
3985 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
3986 | } | |
3987 | ||
b445e3b0 ED |
3988 | /** |
3989 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3990 | * | |
3991 | * Calculate watermark values for the various WM regs based on current mode | |
3992 | * and plane configuration. | |
3993 | * | |
3994 | * There are several cases to deal with here: | |
3995 | * - normal (i.e. non-self-refresh) | |
3996 | * - self-refresh (SR) mode | |
3997 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3998 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3999 | * lines), so need to account for TLB latency | |
4000 | * | |
4001 | * The normal calculation is: | |
4002 | * watermark = dotclock * bytes per pixel * latency | |
4003 | * where latency is platform & configuration dependent (we assume pessimal | |
4004 | * values here). | |
4005 | * | |
4006 | * The SR calculation is: | |
4007 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4008 | * bytes per pixel | |
4009 | * where | |
4010 | * line time = htotal / dotclock | |
4011 | * surface width = hdisplay for normal plane and 64 for cursor | |
4012 | * and latency is assumed to be high, as above. | |
4013 | * | |
4014 | * The final value programmed to the register should always be rounded up, | |
4015 | * and include an extra 2 entries to account for clock crossings. | |
4016 | * | |
4017 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4018 | * to set the non-SR watermarks to 8. | |
4019 | */ | |
46ba614c | 4020 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 4021 | { |
46ba614c | 4022 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
4023 | |
4024 | if (dev_priv->display.update_wm) | |
46ba614c | 4025 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
4026 | } |
4027 | ||
9270388e DV |
4028 | /** |
4029 | * Lock protecting IPS related data structures | |
9270388e DV |
4030 | */ |
4031 | DEFINE_SPINLOCK(mchdev_lock); | |
4032 | ||
4033 | /* Global for IPS driver to get at the current i915 device. Protected by | |
4034 | * mchdev_lock. */ | |
4035 | static struct drm_i915_private *i915_mch_dev; | |
4036 | ||
2b4e57bd ED |
4037 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
4038 | { | |
4039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4040 | u16 rgvswctl; | |
4041 | ||
9270388e DV |
4042 | assert_spin_locked(&mchdev_lock); |
4043 | ||
2b4e57bd ED |
4044 | rgvswctl = I915_READ16(MEMSWCTL); |
4045 | if (rgvswctl & MEMCTL_CMD_STS) { | |
4046 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
4047 | return false; /* still busy with another command */ | |
4048 | } | |
4049 | ||
4050 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
4051 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
4052 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
4053 | POSTING_READ16(MEMSWCTL); | |
4054 | ||
4055 | rgvswctl |= MEMCTL_CMD_STS; | |
4056 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
4057 | ||
4058 | return true; | |
4059 | } | |
4060 | ||
8090c6b9 | 4061 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
4062 | { |
4063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4064 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
4065 | u8 fmax, fmin, fstart, vstart; | |
4066 | ||
9270388e DV |
4067 | spin_lock_irq(&mchdev_lock); |
4068 | ||
2b4e57bd ED |
4069 | /* Enable temp reporting */ |
4070 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
4071 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
4072 | ||
4073 | /* 100ms RC evaluation intervals */ | |
4074 | I915_WRITE(RCUPEI, 100000); | |
4075 | I915_WRITE(RCDNEI, 100000); | |
4076 | ||
4077 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
4078 | I915_WRITE(RCBMAXAVG, 90000); | |
4079 | I915_WRITE(RCBMINAVG, 80000); | |
4080 | ||
4081 | I915_WRITE(MEMIHYST, 1); | |
4082 | ||
4083 | /* Set up min, max, and cur for interrupt handling */ | |
4084 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
4085 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
4086 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
4087 | MEMMODE_FSTART_SHIFT; | |
4088 | ||
616847e7 | 4089 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
2b4e57bd ED |
4090 | PXVFREQ_PX_SHIFT; |
4091 | ||
20e4d407 DV |
4092 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
4093 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 4094 | |
20e4d407 DV |
4095 | dev_priv->ips.max_delay = fstart; |
4096 | dev_priv->ips.min_delay = fmin; | |
4097 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
4098 | |
4099 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
4100 | fmax, fmin, fstart); | |
4101 | ||
4102 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
4103 | ||
4104 | /* | |
4105 | * Interrupts will be enabled in ironlake_irq_postinstall | |
4106 | */ | |
4107 | ||
4108 | I915_WRITE(VIDSTART, vstart); | |
4109 | POSTING_READ(VIDSTART); | |
4110 | ||
4111 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
4112 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
4113 | ||
9270388e | 4114 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 4115 | DRM_ERROR("stuck trying to change perf mode\n"); |
dd92d8de | 4116 | mdelay(1); |
2b4e57bd ED |
4117 | |
4118 | ironlake_set_drps(dev, fstart); | |
4119 | ||
7d81c3e0 VS |
4120 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
4121 | I915_READ(DDREC) + I915_READ(CSIEC); | |
20e4d407 | 4122 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
7d81c3e0 | 4123 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
5ed0bdf2 | 4124 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
4125 | |
4126 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
4127 | } |
4128 | ||
8090c6b9 | 4129 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
4130 | { |
4131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
4132 | u16 rgvswctl; |
4133 | ||
4134 | spin_lock_irq(&mchdev_lock); | |
4135 | ||
4136 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
4137 | |
4138 | /* Ack interrupts, disable EFC interrupt */ | |
4139 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
4140 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
4141 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
4142 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
4143 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
4144 | ||
4145 | /* Go back to the starting frequency */ | |
20e4d407 | 4146 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
dd92d8de | 4147 | mdelay(1); |
2b4e57bd ED |
4148 | rgvswctl |= MEMCTL_CMD_STS; |
4149 | I915_WRITE(MEMSWCTL, rgvswctl); | |
dd92d8de | 4150 | mdelay(1); |
2b4e57bd | 4151 | |
9270388e | 4152 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
4153 | } |
4154 | ||
acbe9475 DV |
4155 | /* There's a funny hw issue where the hw returns all 0 when reading from |
4156 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
4157 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
4158 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
4159 | */ | |
74ef1173 | 4160 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 4161 | { |
7b9e0ae6 | 4162 | u32 limits; |
2b4e57bd | 4163 | |
20b46e59 DV |
4164 | /* Only set the down limit when we've reached the lowest level to avoid |
4165 | * getting more interrupts, otherwise leave this clear. This prevents a | |
4166 | * race in the hw when coming out of rc6: There's a tiny window where | |
4167 | * the hw runs at the minimal clock before selecting the desired | |
4168 | * frequency, if the down threshold expires in that window we will not | |
4169 | * receive a down interrupt. */ | |
74ef1173 AG |
4170 | if (IS_GEN9(dev_priv->dev)) { |
4171 | limits = (dev_priv->rps.max_freq_softlimit) << 23; | |
4172 | if (val <= dev_priv->rps.min_freq_softlimit) | |
4173 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; | |
4174 | } else { | |
4175 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
4176 | if (val <= dev_priv->rps.min_freq_softlimit) | |
4177 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
4178 | } | |
20b46e59 DV |
4179 | |
4180 | return limits; | |
4181 | } | |
4182 | ||
dd75fdc8 CW |
4183 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
4184 | { | |
4185 | int new_power; | |
8a586437 AG |
4186 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
4187 | u32 ei_up = 0, ei_down = 0; | |
dd75fdc8 CW |
4188 | |
4189 | new_power = dev_priv->rps.power; | |
4190 | switch (dev_priv->rps.power) { | |
4191 | case LOW_POWER: | |
b39fb297 | 4192 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4193 | new_power = BETWEEN; |
4194 | break; | |
4195 | ||
4196 | case BETWEEN: | |
b39fb297 | 4197 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 4198 | new_power = LOW_POWER; |
b39fb297 | 4199 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4200 | new_power = HIGH_POWER; |
4201 | break; | |
4202 | ||
4203 | case HIGH_POWER: | |
b39fb297 | 4204 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4205 | new_power = BETWEEN; |
4206 | break; | |
4207 | } | |
4208 | /* Max/min bins are special */ | |
aed242ff | 4209 | if (val <= dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 4210 | new_power = LOW_POWER; |
aed242ff | 4211 | if (val >= dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
4212 | new_power = HIGH_POWER; |
4213 | if (new_power == dev_priv->rps.power) | |
4214 | return; | |
4215 | ||
4216 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
4217 | switch (new_power) { | |
4218 | case LOW_POWER: | |
4219 | /* Upclock if more than 95% busy over 16ms */ | |
8a586437 AG |
4220 | ei_up = 16000; |
4221 | threshold_up = 95; | |
dd75fdc8 CW |
4222 | |
4223 | /* Downclock if less than 85% busy over 32ms */ | |
8a586437 AG |
4224 | ei_down = 32000; |
4225 | threshold_down = 85; | |
dd75fdc8 CW |
4226 | break; |
4227 | ||
4228 | case BETWEEN: | |
4229 | /* Upclock if more than 90% busy over 13ms */ | |
8a586437 AG |
4230 | ei_up = 13000; |
4231 | threshold_up = 90; | |
dd75fdc8 CW |
4232 | |
4233 | /* Downclock if less than 75% busy over 32ms */ | |
8a586437 AG |
4234 | ei_down = 32000; |
4235 | threshold_down = 75; | |
dd75fdc8 CW |
4236 | break; |
4237 | ||
4238 | case HIGH_POWER: | |
4239 | /* Upclock if more than 85% busy over 10ms */ | |
8a586437 AG |
4240 | ei_up = 10000; |
4241 | threshold_up = 85; | |
dd75fdc8 CW |
4242 | |
4243 | /* Downclock if less than 60% busy over 32ms */ | |
8a586437 AG |
4244 | ei_down = 32000; |
4245 | threshold_down = 60; | |
dd75fdc8 CW |
4246 | break; |
4247 | } | |
4248 | ||
8a586437 AG |
4249 | I915_WRITE(GEN6_RP_UP_EI, |
4250 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); | |
4251 | I915_WRITE(GEN6_RP_UP_THRESHOLD, | |
4252 | GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); | |
4253 | ||
4254 | I915_WRITE(GEN6_RP_DOWN_EI, | |
4255 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); | |
4256 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, | |
4257 | GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); | |
4258 | ||
4259 | I915_WRITE(GEN6_RP_CONTROL, | |
4260 | GEN6_RP_MEDIA_TURBO | | |
4261 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4262 | GEN6_RP_MEDIA_IS_GFX | | |
4263 | GEN6_RP_ENABLE | | |
4264 | GEN6_RP_UP_BUSY_AVG | | |
4265 | GEN6_RP_DOWN_IDLE_AVG); | |
4266 | ||
dd75fdc8 | 4267 | dev_priv->rps.power = new_power; |
8fb55197 CW |
4268 | dev_priv->rps.up_threshold = threshold_up; |
4269 | dev_priv->rps.down_threshold = threshold_down; | |
dd75fdc8 CW |
4270 | dev_priv->rps.last_adj = 0; |
4271 | } | |
4272 | ||
2876ce73 CW |
4273 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
4274 | { | |
4275 | u32 mask = 0; | |
4276 | ||
4277 | if (val > dev_priv->rps.min_freq_softlimit) | |
6f4b12f8 | 4278 | mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
2876ce73 | 4279 | if (val < dev_priv->rps.max_freq_softlimit) |
6f4b12f8 | 4280 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
2876ce73 | 4281 | |
7b3c29f6 CW |
4282 | mask &= dev_priv->pm_rps_events; |
4283 | ||
59d02a1f | 4284 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
4285 | } |
4286 | ||
b8a5ff8d JM |
4287 | /* gen6_set_rps is called to update the frequency request, but should also be |
4288 | * called when the range (min_delay and max_delay) is modified so that we can | |
4289 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
ffe02b40 | 4290 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
20b46e59 DV |
4291 | { |
4292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 4293 | |
23eafea6 | 4294 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
e87a005d | 4295 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
23eafea6 SAK |
4296 | return; |
4297 | ||
4fc688ce | 4298 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
aed242ff CW |
4299 | WARN_ON(val > dev_priv->rps.max_freq); |
4300 | WARN_ON(val < dev_priv->rps.min_freq); | |
004777cb | 4301 | |
eb64cad1 CW |
4302 | /* min/max delay may still have been modified so be sure to |
4303 | * write the limits value. | |
4304 | */ | |
4305 | if (val != dev_priv->rps.cur_freq) { | |
4306 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 4307 | |
5704195c AG |
4308 | if (IS_GEN9(dev)) |
4309 | I915_WRITE(GEN6_RPNSWREQ, | |
4310 | GEN9_FREQUENCY(val)); | |
4311 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
eb64cad1 CW |
4312 | I915_WRITE(GEN6_RPNSWREQ, |
4313 | HSW_FREQUENCY(val)); | |
4314 | else | |
4315 | I915_WRITE(GEN6_RPNSWREQ, | |
4316 | GEN6_FREQUENCY(val) | | |
4317 | GEN6_OFFSET(0) | | |
4318 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 4319 | } |
7b9e0ae6 | 4320 | |
7b9e0ae6 CW |
4321 | /* Make sure we continue to get interrupts |
4322 | * until we hit the minimum or maximum frequencies. | |
4323 | */ | |
74ef1173 | 4324 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
2876ce73 | 4325 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 4326 | |
d5570a72 BW |
4327 | POSTING_READ(GEN6_RPNSWREQ); |
4328 | ||
b39fb297 | 4329 | dev_priv->rps.cur_freq = val; |
be2cde9a | 4330 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
4331 | } |
4332 | ||
ffe02b40 VS |
4333 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
4334 | { | |
4335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4336 | ||
4337 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
aed242ff CW |
4338 | WARN_ON(val > dev_priv->rps.max_freq); |
4339 | WARN_ON(val < dev_priv->rps.min_freq); | |
ffe02b40 VS |
4340 | |
4341 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), | |
4342 | "Odd GPU freq value\n")) | |
4343 | val &= ~1; | |
4344 | ||
cd25dd5b D |
4345 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
4346 | ||
8fb55197 | 4347 | if (val != dev_priv->rps.cur_freq) { |
ffe02b40 | 4348 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
8fb55197 CW |
4349 | if (!IS_CHERRYVIEW(dev_priv)) |
4350 | gen6_set_rps_thresholds(dev_priv, val); | |
4351 | } | |
ffe02b40 | 4352 | |
ffe02b40 VS |
4353 | dev_priv->rps.cur_freq = val; |
4354 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
4355 | } | |
4356 | ||
a7f6e231 | 4357 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
76c3552f D |
4358 | * |
4359 | * * If Gfx is Idle, then | |
a7f6e231 D |
4360 | * 1. Forcewake Media well. |
4361 | * 2. Request idle freq. | |
4362 | * 3. Release Forcewake of Media well. | |
76c3552f D |
4363 | */ |
4364 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
4365 | { | |
aed242ff | 4366 | u32 val = dev_priv->rps.idle_freq; |
5549d25f | 4367 | |
aed242ff | 4368 | if (dev_priv->rps.cur_freq <= val) |
76c3552f D |
4369 | return; |
4370 | ||
a7f6e231 D |
4371 | /* Wake up the media well, as that takes a lot less |
4372 | * power than the Render well. */ | |
4373 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); | |
4374 | valleyview_set_rps(dev_priv->dev, val); | |
4375 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); | |
76c3552f D |
4376 | } |
4377 | ||
43cf3bf0 CW |
4378 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
4379 | { | |
4380 | mutex_lock(&dev_priv->rps.hw_lock); | |
4381 | if (dev_priv->rps.enabled) { | |
4382 | if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) | |
4383 | gen6_rps_reset_ei(dev_priv); | |
4384 | I915_WRITE(GEN6_PMINTRMSK, | |
4385 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
4386 | } | |
4387 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4388 | } | |
4389 | ||
b29c19b6 CW |
4390 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
4391 | { | |
691bb717 DL |
4392 | struct drm_device *dev = dev_priv->dev; |
4393 | ||
b29c19b6 | 4394 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 4395 | if (dev_priv->rps.enabled) { |
21a11fff | 4396 | if (IS_VALLEYVIEW(dev)) |
76c3552f | 4397 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 4398 | else |
aed242ff | 4399 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
c0951f0c | 4400 | dev_priv->rps.last_adj = 0; |
43cf3bf0 | 4401 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
c0951f0c | 4402 | } |
8d3afd7d | 4403 | mutex_unlock(&dev_priv->rps.hw_lock); |
1854d5ca | 4404 | |
8d3afd7d | 4405 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
4406 | while (!list_empty(&dev_priv->rps.clients)) |
4407 | list_del_init(dev_priv->rps.clients.next); | |
8d3afd7d | 4408 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
4409 | } |
4410 | ||
1854d5ca | 4411 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
4412 | struct intel_rps_client *rps, |
4413 | unsigned long submitted) | |
b29c19b6 | 4414 | { |
8d3afd7d CW |
4415 | /* This is intentionally racy! We peek at the state here, then |
4416 | * validate inside the RPS worker. | |
4417 | */ | |
4418 | if (!(dev_priv->mm.busy && | |
4419 | dev_priv->rps.enabled && | |
4420 | dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) | |
4421 | return; | |
43cf3bf0 | 4422 | |
e61b9958 CW |
4423 | /* Force a RPS boost (and don't count it against the client) if |
4424 | * the GPU is severely congested. | |
4425 | */ | |
d0bc54f2 | 4426 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
e61b9958 CW |
4427 | rps = NULL; |
4428 | ||
8d3afd7d CW |
4429 | spin_lock(&dev_priv->rps.client_lock); |
4430 | if (rps == NULL || list_empty(&rps->link)) { | |
4431 | spin_lock_irq(&dev_priv->irq_lock); | |
4432 | if (dev_priv->rps.interrupts_enabled) { | |
4433 | dev_priv->rps.client_boost = true; | |
4434 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
4435 | } | |
4436 | spin_unlock_irq(&dev_priv->irq_lock); | |
1854d5ca | 4437 | |
2e1b8730 CW |
4438 | if (rps != NULL) { |
4439 | list_add(&rps->link, &dev_priv->rps.clients); | |
4440 | rps->boosts++; | |
1854d5ca CW |
4441 | } else |
4442 | dev_priv->rps.boosts++; | |
c0951f0c | 4443 | } |
8d3afd7d | 4444 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
4445 | } |
4446 | ||
ffe02b40 | 4447 | void intel_set_rps(struct drm_device *dev, u8 val) |
0a073b84 | 4448 | { |
ffe02b40 VS |
4449 | if (IS_VALLEYVIEW(dev)) |
4450 | valleyview_set_rps(dev, val); | |
4451 | else | |
4452 | gen6_set_rps(dev, val); | |
0a073b84 JB |
4453 | } |
4454 | ||
20e49366 ZW |
4455 | static void gen9_disable_rps(struct drm_device *dev) |
4456 | { | |
4457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4458 | ||
4459 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
38c23527 | 4460 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
4461 | } |
4462 | ||
44fc7d5c | 4463 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
4464 | { |
4465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4466 | ||
4467 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 4468 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
44fc7d5c DV |
4469 | } |
4470 | ||
38807746 D |
4471 | static void cherryview_disable_rps(struct drm_device *dev) |
4472 | { | |
4473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4474 | ||
4475 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4476 | } | |
4477 | ||
44fc7d5c DV |
4478 | static void valleyview_disable_rps(struct drm_device *dev) |
4479 | { | |
4480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4481 | ||
98a2e5f9 D |
4482 | /* we're doing forcewake before Disabling RC6, |
4483 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 4484 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 4485 | |
44fc7d5c | 4486 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 4487 | |
59bad947 | 4488 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
4489 | } |
4490 | ||
dc39fff7 BW |
4491 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
4492 | { | |
91ca689a ID |
4493 | if (IS_VALLEYVIEW(dev)) { |
4494 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
4495 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
4496 | else | |
4497 | mode = 0; | |
4498 | } | |
58abf1da RV |
4499 | if (HAS_RC6p(dev)) |
4500 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", | |
4501 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
4502 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
4503 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
4504 | ||
4505 | else | |
4506 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", | |
4507 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
4508 | } |
4509 | ||
e6069ca8 | 4510 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 4511 | { |
e7d66d89 DV |
4512 | /* No RC6 before Ironlake and code is gone for ilk. */ |
4513 | if (INTEL_INFO(dev)->gen < 6) | |
e6069ca8 ID |
4514 | return 0; |
4515 | ||
456470eb | 4516 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
4517 | if (enable_rc6 >= 0) { |
4518 | int mask; | |
4519 | ||
58abf1da | 4520 | if (HAS_RC6p(dev)) |
e6069ca8 ID |
4521 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4522 | INTEL_RC6pp_ENABLE; | |
4523 | else | |
4524 | mask = INTEL_RC6_ENABLE; | |
4525 | ||
4526 | if ((enable_rc6 & mask) != enable_rc6) | |
8dfd1f04 DV |
4527 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4528 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
4529 | |
4530 | return enable_rc6 & mask; | |
4531 | } | |
2b4e57bd | 4532 | |
8bade1ad | 4533 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 4534 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
4535 | |
4536 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
4537 | } |
4538 | ||
e6069ca8 ID |
4539 | int intel_enable_rc6(const struct drm_device *dev) |
4540 | { | |
4541 | return i915.enable_rc6; | |
4542 | } | |
4543 | ||
93ee2920 | 4544 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
3280e8b0 | 4545 | { |
93ee2920 TR |
4546 | struct drm_i915_private *dev_priv = dev->dev_private; |
4547 | uint32_t rp_state_cap; | |
4548 | u32 ddcc_status = 0; | |
4549 | int ret; | |
4550 | ||
3280e8b0 BW |
4551 | /* All of these values are in units of 50MHz */ |
4552 | dev_priv->rps.cur_freq = 0; | |
93ee2920 | 4553 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
35040562 BP |
4554 | if (IS_BROXTON(dev)) { |
4555 | rp_state_cap = I915_READ(BXT_RP_STATE_CAP); | |
4556 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; | |
4557 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
4558 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; | |
4559 | } else { | |
4560 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
4561 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
4562 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
4563 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
4564 | } | |
4565 | ||
3280e8b0 BW |
4566 | /* hw_max = RP0 until we check for overclocking */ |
4567 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
4568 | ||
93ee2920 | 4569 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
ef11bdb3 RV |
4570 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || |
4571 | IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { | |
93ee2920 TR |
4572 | ret = sandybridge_pcode_read(dev_priv, |
4573 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
4574 | &ddcc_status); | |
4575 | if (0 == ret) | |
4576 | dev_priv->rps.efficient_freq = | |
46efa4ab TR |
4577 | clamp_t(u8, |
4578 | ((ddcc_status >> 8) & 0xff), | |
4579 | dev_priv->rps.min_freq, | |
4580 | dev_priv->rps.max_freq); | |
93ee2920 TR |
4581 | } |
4582 | ||
ef11bdb3 | 4583 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
c5e0688c AG |
4584 | /* Store the frequency values in 16.66 MHZ units, which is |
4585 | the natural hardware unit for SKL */ | |
4586 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; | |
4587 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; | |
4588 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; | |
4589 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; | |
4590 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; | |
4591 | } | |
4592 | ||
aed242ff CW |
4593 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
4594 | ||
3280e8b0 BW |
4595 | /* Preserve min/max settings in case of re-init */ |
4596 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4597 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4598 | ||
93ee2920 TR |
4599 | if (dev_priv->rps.min_freq_softlimit == 0) { |
4600 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
4601 | dev_priv->rps.min_freq_softlimit = | |
813b5e69 VS |
4602 | max_t(int, dev_priv->rps.efficient_freq, |
4603 | intel_freq_opcode(dev_priv, 450)); | |
93ee2920 TR |
4604 | else |
4605 | dev_priv->rps.min_freq_softlimit = | |
4606 | dev_priv->rps.min_freq; | |
4607 | } | |
3280e8b0 BW |
4608 | } |
4609 | ||
b6fef0ef | 4610 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
20e49366 | 4611 | static void gen9_enable_rps(struct drm_device *dev) |
b6fef0ef JB |
4612 | { |
4613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4614 | ||
4615 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4616 | ||
ba1c554c DL |
4617 | gen6_init_rps_frequencies(dev); |
4618 | ||
23eafea6 | 4619 | /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ |
e87a005d | 4620 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
23eafea6 SAK |
4621 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4622 | return; | |
4623 | } | |
4624 | ||
0beb059a AG |
4625 | /* Program defaults and thresholds for RPS*/ |
4626 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4627 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4628 | ||
4629 | /* 1 second timeout*/ | |
4630 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, | |
4631 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); | |
4632 | ||
b6fef0ef | 4633 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
b6fef0ef | 4634 | |
0beb059a AG |
4635 | /* Leaning on the below call to gen6_set_rps to program/setup the |
4636 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, | |
4637 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ | |
4638 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ | |
4639 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
b6fef0ef JB |
4640 | |
4641 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4642 | } | |
4643 | ||
4644 | static void gen9_enable_rc6(struct drm_device *dev) | |
20e49366 ZW |
4645 | { |
4646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4647 | struct intel_engine_cs *ring; | |
4648 | uint32_t rc6_mask = 0; | |
4649 | int unused; | |
4650 | ||
4651 | /* 1a: Software RC state - RC0 */ | |
4652 | I915_WRITE(GEN6_RC_STATE, 0); | |
4653 | ||
4654 | /* 1b: Get forcewake during program sequence. Although the driver | |
4655 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4656 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4657 | |
4658 | /* 2a: Disable RC states. */ | |
4659 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4660 | ||
4661 | /* 2b: Program RC6 thresholds.*/ | |
63a4dec2 SAK |
4662 | |
4663 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ | |
4664 | if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && | |
e87a005d | 4665 | IS_SKL_REVID(dev, 0, SKL_REVID_E0))) |
63a4dec2 SAK |
4666 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
4667 | else | |
4668 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
20e49366 ZW |
4669 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
4670 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4671 | for_each_ring(ring, dev_priv, unused) | |
4672 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
97c322e7 SAK |
4673 | |
4674 | if (HAS_GUC_UCODE(dev)) | |
4675 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); | |
4676 | ||
20e49366 | 4677 | I915_WRITE(GEN6_RC_SLEEP, 0); |
20e49366 | 4678 | |
38c23527 ZW |
4679 | /* 2c: Program Coarse Power Gating Policies. */ |
4680 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
4681 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
4682 | ||
20e49366 ZW |
4683 | /* 3a: Enable RC6 */ |
4684 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4685 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
4686 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4687 | "on" : "off"); | |
3e7732a0 | 4688 | /* WaRsUseTimeoutMode */ |
e87a005d JN |
4689 | if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || |
4690 | IS_BXT_REVID(dev, 0, BXT_REVID_A0)) { | |
3e7732a0 | 4691 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ |
e3429cd2 SAK |
4692 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4693 | GEN7_RC_CTL_TO_MODE | | |
4694 | rc6_mask); | |
3e7732a0 SAK |
4695 | } else { |
4696 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ | |
e3429cd2 SAK |
4697 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
4698 | GEN6_RC_CTL_EI_MODE(1) | | |
4699 | rc6_mask); | |
3e7732a0 | 4700 | } |
20e49366 | 4701 | |
cb07bae0 SK |
4702 | /* |
4703 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. | |
f2d2fe95 | 4704 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
cb07bae0 | 4705 | */ |
e87a005d JN |
4706 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || |
4707 | ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && | |
4708 | IS_SKL_REVID(dev, 0, SKL_REVID_E0))) | |
f2d2fe95 SAK |
4709 | I915_WRITE(GEN9_PG_ENABLE, 0); |
4710 | else | |
4711 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4712 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); | |
38c23527 | 4713 | |
59bad947 | 4714 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4715 | |
4716 | } | |
4717 | ||
6edee7f3 BW |
4718 | static void gen8_enable_rps(struct drm_device *dev) |
4719 | { | |
4720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4721 | struct intel_engine_cs *ring; |
93ee2920 | 4722 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
4723 | int unused; |
4724 | ||
4725 | /* 1a: Software RC state - RC0 */ | |
4726 | I915_WRITE(GEN6_RC_STATE, 0); | |
4727 | ||
4728 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
4729 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4730 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4731 | |
4732 | /* 2a: Disable RC states. */ | |
4733 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4734 | ||
93ee2920 TR |
4735 | /* Initialize rps frequencies */ |
4736 | gen6_init_rps_frequencies(dev); | |
6edee7f3 BW |
4737 | |
4738 | /* 2b: Program RC6 thresholds.*/ | |
4739 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4740 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4741 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4742 | for_each_ring(ring, dev_priv, unused) | |
4743 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4744 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
4745 | if (IS_BROADWELL(dev)) |
4746 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
4747 | else | |
4748 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
4749 | |
4750 | /* 3: Enable RC6 */ | |
4751 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4752 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 4753 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
4754 | if (IS_BROADWELL(dev)) |
4755 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4756 | GEN7_RC_CTL_TO_MODE | | |
4757 | rc6_mask); | |
4758 | else | |
4759 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4760 | GEN6_RC_CTL_EI_MODE(1) | | |
4761 | rc6_mask); | |
6edee7f3 BW |
4762 | |
4763 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
4764 | I915_WRITE(GEN6_RPNSWREQ, |
4765 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4766 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4767 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
4768 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4769 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
4770 | ||
4771 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
4772 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
4773 | dev_priv->rps.max_freq_softlimit << 24 | | |
4774 | dev_priv->rps.min_freq_softlimit << 16); | |
4775 | ||
4776 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
4777 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
4778 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
4779 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
4780 | ||
4781 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
4782 | |
4783 | /* 5: Enable RPS */ | |
7526ed79 DV |
4784 | I915_WRITE(GEN6_RP_CONTROL, |
4785 | GEN6_RP_MEDIA_TURBO | | |
4786 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4787 | GEN6_RP_MEDIA_IS_GFX | | |
4788 | GEN6_RP_ENABLE | | |
4789 | GEN6_RP_UP_BUSY_AVG | | |
4790 | GEN6_RP_DOWN_IDLE_AVG); | |
4791 | ||
4792 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
4793 | ||
c7f3153a | 4794 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
aed242ff | 4795 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
7526ed79 | 4796 | |
59bad947 | 4797 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4798 | } |
4799 | ||
79f5b2c7 | 4800 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 4801 | { |
79f5b2c7 | 4802 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4803 | struct intel_engine_cs *ring; |
d060c169 | 4804 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 4805 | u32 gtfifodbg; |
2b4e57bd | 4806 | int rc6_mode; |
42c0526c | 4807 | int i, ret; |
2b4e57bd | 4808 | |
4fc688ce | 4809 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4810 | |
2b4e57bd ED |
4811 | /* Here begins a magic sequence of register writes to enable |
4812 | * auto-downclocking. | |
4813 | * | |
4814 | * Perhaps there might be some value in exposing these to | |
4815 | * userspace... | |
4816 | */ | |
4817 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
4818 | |
4819 | /* Clear the DBG now so we don't confuse earlier errors */ | |
4820 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4821 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
4822 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4823 | } | |
4824 | ||
59bad947 | 4825 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 4826 | |
93ee2920 TR |
4827 | /* Initialize rps frequencies */ |
4828 | gen6_init_rps_frequencies(dev); | |
dd0a1aa1 | 4829 | |
2b4e57bd ED |
4830 | /* disable the counters and set deterministic thresholds */ |
4831 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4832 | ||
4833 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
4834 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
4835 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
4836 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4837 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4838 | ||
b4519513 CW |
4839 | for_each_ring(ring, dev_priv, i) |
4840 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
4841 | |
4842 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4843 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 4844 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
4845 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4846 | else | |
4847 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 4848 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
4849 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4850 | ||
5a7dc92a | 4851 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
4852 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4853 | if (rc6_mode & INTEL_RC6_ENABLE) | |
4854 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
4855 | ||
5a7dc92a ED |
4856 | /* We don't use those on Haswell */ |
4857 | if (!IS_HASWELL(dev)) { | |
4858 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
4859 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 4860 | |
5a7dc92a ED |
4861 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
4862 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
4863 | } | |
2b4e57bd | 4864 | |
dc39fff7 | 4865 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
4866 | |
4867 | I915_WRITE(GEN6_RC_CONTROL, | |
4868 | rc6_mask | | |
4869 | GEN6_RC_CTL_EI_MODE(1) | | |
4870 | GEN6_RC_CTL_HW_ENABLE); | |
4871 | ||
dd75fdc8 CW |
4872 | /* Power down if completely idle for over 50ms */ |
4873 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 4874 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 4875 | |
42c0526c | 4876 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 4877 | if (ret) |
42c0526c | 4878 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
4879 | |
4880 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
4881 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
4882 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 4883 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 4884 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 4885 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
4886 | } |
4887 | ||
dd75fdc8 | 4888 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
aed242ff | 4889 | gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); |
2b4e57bd | 4890 | |
31643d54 BW |
4891 | rc6vids = 0; |
4892 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
4893 | if (IS_GEN6(dev) && ret) { | |
4894 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
4895 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
4896 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
4897 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
4898 | rc6vids &= 0xffff00; | |
4899 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
4900 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
4901 | if (ret) | |
4902 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
4903 | } | |
4904 | ||
59bad947 | 4905 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
4906 | } |
4907 | ||
c2bc2fc5 | 4908 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 4909 | { |
79f5b2c7 | 4910 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 4911 | int min_freq = 15; |
3ebecd07 CW |
4912 | unsigned int gpu_freq; |
4913 | unsigned int max_ia_freq, min_ring_freq; | |
4c8c7743 | 4914 | unsigned int max_gpu_freq, min_gpu_freq; |
2b4e57bd | 4915 | int scaling_factor = 180; |
eda79642 | 4916 | struct cpufreq_policy *policy; |
2b4e57bd | 4917 | |
4fc688ce | 4918 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4919 | |
eda79642 BW |
4920 | policy = cpufreq_cpu_get(0); |
4921 | if (policy) { | |
4922 | max_ia_freq = policy->cpuinfo.max_freq; | |
4923 | cpufreq_cpu_put(policy); | |
4924 | } else { | |
4925 | /* | |
4926 | * Default to measured freq if none found, PCU will ensure we | |
4927 | * don't go over | |
4928 | */ | |
2b4e57bd | 4929 | max_ia_freq = tsc_khz; |
eda79642 | 4930 | } |
2b4e57bd ED |
4931 | |
4932 | /* Convert from kHz to MHz */ | |
4933 | max_ia_freq /= 1000; | |
4934 | ||
153b4b95 | 4935 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
4936 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
4937 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 4938 | |
ef11bdb3 | 4939 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
4c8c7743 AG |
4940 | /* Convert GT frequency to 50 HZ units */ |
4941 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; | |
4942 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; | |
4943 | } else { | |
4944 | min_gpu_freq = dev_priv->rps.min_freq; | |
4945 | max_gpu_freq = dev_priv->rps.max_freq; | |
4946 | } | |
4947 | ||
2b4e57bd ED |
4948 | /* |
4949 | * For each potential GPU frequency, load a ring frequency we'd like | |
4950 | * to use for memory access. We do this by specifying the IA frequency | |
4951 | * the PCU should use as a reference to determine the ring frequency. | |
4952 | */ | |
4c8c7743 AG |
4953 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
4954 | int diff = max_gpu_freq - gpu_freq; | |
3ebecd07 CW |
4955 | unsigned int ia_freq = 0, ring_freq = 0; |
4956 | ||
ef11bdb3 | 4957 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
4c8c7743 AG |
4958 | /* |
4959 | * ring_freq = 2 * GT. ring_freq is in 100MHz units | |
4960 | * No floor required for ring frequency on SKL. | |
4961 | */ | |
4962 | ring_freq = gpu_freq; | |
4963 | } else if (INTEL_INFO(dev)->gen >= 8) { | |
46c764d4 BW |
4964 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
4965 | ring_freq = max(min_ring_freq, gpu_freq); | |
4966 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 4967 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
4968 | ring_freq = max(min_ring_freq, ring_freq); |
4969 | /* leave ia_freq as the default, chosen by cpufreq */ | |
4970 | } else { | |
4971 | /* On older processors, there is no separate ring | |
4972 | * clock domain, so in order to boost the bandwidth | |
4973 | * of the ring, we need to upclock the CPU (ia_freq). | |
4974 | * | |
4975 | * For GPU frequencies less than 750MHz, | |
4976 | * just use the lowest ring freq. | |
4977 | */ | |
4978 | if (gpu_freq < min_freq) | |
4979 | ia_freq = 800; | |
4980 | else | |
4981 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
4982 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
4983 | } | |
2b4e57bd | 4984 | |
42c0526c BW |
4985 | sandybridge_pcode_write(dev_priv, |
4986 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
4987 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
4988 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
4989 | gpu_freq); | |
2b4e57bd | 4990 | } |
2b4e57bd ED |
4991 | } |
4992 | ||
c2bc2fc5 ID |
4993 | void gen6_update_ring_freq(struct drm_device *dev) |
4994 | { | |
4995 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4996 | ||
97d3308a | 4997 | if (!HAS_CORE_RING_FREQ(dev)) |
c2bc2fc5 ID |
4998 | return; |
4999 | ||
5000 | mutex_lock(&dev_priv->rps.hw_lock); | |
5001 | __gen6_update_ring_freq(dev); | |
5002 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5003 | } | |
5004 | ||
03af2045 | 5005 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 | 5006 | { |
095acd5f | 5007 | struct drm_device *dev = dev_priv->dev; |
2b6b3a09 D |
5008 | u32 val, rp0; |
5009 | ||
5b5929cb | 5010 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
2b6b3a09 | 5011 | |
5b5929cb JN |
5012 | switch (INTEL_INFO(dev)->eu_total) { |
5013 | case 8: | |
5014 | /* (2 * 4) config */ | |
5015 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
5016 | break; | |
5017 | case 12: | |
5018 | /* (2 * 6) config */ | |
5019 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
5020 | break; | |
5021 | case 16: | |
5022 | /* (2 * 8) config */ | |
5023 | default: | |
5024 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
5025 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
5026 | break; | |
095acd5f | 5027 | } |
5b5929cb JN |
5028 | |
5029 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
5030 | ||
2b6b3a09 D |
5031 | return rp0; |
5032 | } | |
5033 | ||
5034 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
5035 | { | |
5036 | u32 val, rpe; | |
5037 | ||
5038 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
5039 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
5040 | ||
5041 | return rpe; | |
5042 | } | |
5043 | ||
7707df4a D |
5044 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5045 | { | |
5046 | u32 val, rp1; | |
5047 | ||
5b5929cb JN |
5048 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
5049 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
5050 | ||
7707df4a D |
5051 | return rp1; |
5052 | } | |
5053 | ||
f8f2b001 D |
5054 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5055 | { | |
5056 | u32 val, rp1; | |
5057 | ||
5058 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
5059 | ||
5060 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
5061 | ||
5062 | return rp1; | |
5063 | } | |
5064 | ||
03af2045 | 5065 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
5066 | { |
5067 | u32 val, rp0; | |
5068 | ||
64936258 | 5069 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
5070 | |
5071 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
5072 | /* Clamp to max */ | |
5073 | rp0 = min_t(u32, rp0, 0xea); | |
5074 | ||
5075 | return rp0; | |
5076 | } | |
5077 | ||
5078 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
5079 | { | |
5080 | u32 val, rpe; | |
5081 | ||
64936258 | 5082 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 5083 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 5084 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
5085 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
5086 | ||
5087 | return rpe; | |
5088 | } | |
5089 | ||
03af2045 | 5090 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 5091 | { |
64936258 | 5092 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
5093 | } |
5094 | ||
ae48434c ID |
5095 | /* Check that the pctx buffer wasn't move under us. */ |
5096 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
5097 | { | |
5098 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
5099 | ||
5100 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
5101 | dev_priv->vlv_pctx->stolen->start); | |
5102 | } | |
5103 | ||
38807746 D |
5104 | |
5105 | /* Check that the pcbr address is not empty. */ | |
5106 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
5107 | { | |
5108 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
5109 | ||
5110 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
5111 | } | |
5112 | ||
5113 | static void cherryview_setup_pctx(struct drm_device *dev) | |
5114 | { | |
5115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5116 | unsigned long pctx_paddr, paddr; | |
5117 | struct i915_gtt *gtt = &dev_priv->gtt; | |
5118 | u32 pcbr; | |
5119 | int pctx_size = 32*1024; | |
5120 | ||
5121 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
5122 | ||
5123 | pcbr = I915_READ(VLV_PCBR); | |
5124 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 5125 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 D |
5126 | paddr = (dev_priv->mm.stolen_base + |
5127 | (gtt->stolen_size - pctx_size)); | |
5128 | ||
5129 | pctx_paddr = (paddr & (~4095)); | |
5130 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
5131 | } | |
ce611ef8 VS |
5132 | |
5133 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
5134 | } |
5135 | ||
c9cddffc JB |
5136 | static void valleyview_setup_pctx(struct drm_device *dev) |
5137 | { | |
5138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5139 | struct drm_i915_gem_object *pctx; | |
5140 | unsigned long pctx_paddr; | |
5141 | u32 pcbr; | |
5142 | int pctx_size = 24*1024; | |
5143 | ||
17b0c1f7 ID |
5144 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5145 | ||
c9cddffc JB |
5146 | pcbr = I915_READ(VLV_PCBR); |
5147 | if (pcbr) { | |
5148 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
5149 | int pcbr_offset; | |
5150 | ||
5151 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
5152 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
5153 | pcbr_offset, | |
190d6cd5 | 5154 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
5155 | pctx_size); |
5156 | goto out; | |
5157 | } | |
5158 | ||
ce611ef8 VS |
5159 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
5160 | ||
c9cddffc JB |
5161 | /* |
5162 | * From the Gunit register HAS: | |
5163 | * The Gfx driver is expected to program this register and ensure | |
5164 | * proper allocation within Gfx stolen memory. For example, this | |
5165 | * register should be programmed such than the PCBR range does not | |
5166 | * overlap with other ranges, such as the frame buffer, protected | |
5167 | * memory, or any other relevant ranges. | |
5168 | */ | |
5169 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
5170 | if (!pctx) { | |
5171 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
5172 | return; | |
5173 | } | |
5174 | ||
5175 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
5176 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
5177 | ||
5178 | out: | |
ce611ef8 | 5179 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
5180 | dev_priv->vlv_pctx = pctx; |
5181 | } | |
5182 | ||
ae48434c ID |
5183 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
5184 | { | |
5185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5186 | ||
5187 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
5188 | return; | |
5189 | ||
5190 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
5191 | dev_priv->vlv_pctx = NULL; | |
5192 | } | |
5193 | ||
4e80519e ID |
5194 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
5195 | { | |
5196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bb25c17 | 5197 | u32 val; |
4e80519e ID |
5198 | |
5199 | valleyview_setup_pctx(dev); | |
5200 | ||
5201 | mutex_lock(&dev_priv->rps.hw_lock); | |
5202 | ||
2bb25c17 VS |
5203 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5204 | switch ((val >> 6) & 3) { | |
5205 | case 0: | |
5206 | case 1: | |
5207 | dev_priv->mem_freq = 800; | |
5208 | break; | |
5209 | case 2: | |
5210 | dev_priv->mem_freq = 1066; | |
5211 | break; | |
5212 | case 3: | |
5213 | dev_priv->mem_freq = 1333; | |
5214 | break; | |
5215 | } | |
80b83b62 | 5216 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 5217 | |
4e80519e ID |
5218 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
5219 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
5220 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5221 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
5222 | dev_priv->rps.max_freq); |
5223 | ||
5224 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
5225 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5226 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
5227 | dev_priv->rps.efficient_freq); |
5228 | ||
f8f2b001 D |
5229 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
5230 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5231 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
5232 | dev_priv->rps.rp1_freq); |
5233 | ||
4e80519e ID |
5234 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
5235 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5236 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e ID |
5237 | dev_priv->rps.min_freq); |
5238 | ||
aed242ff CW |
5239 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5240 | ||
4e80519e ID |
5241 | /* Preserve min/max settings in case of re-init */ |
5242 | if (dev_priv->rps.max_freq_softlimit == 0) | |
5243 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
5244 | ||
5245 | if (dev_priv->rps.min_freq_softlimit == 0) | |
5246 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
5247 | ||
5248 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5249 | } | |
5250 | ||
38807746 D |
5251 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
5252 | { | |
2b6b3a09 | 5253 | struct drm_i915_private *dev_priv = dev->dev_private; |
2bb25c17 | 5254 | u32 val; |
2b6b3a09 | 5255 | |
38807746 | 5256 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
5257 | |
5258 | mutex_lock(&dev_priv->rps.hw_lock); | |
5259 | ||
a580516d | 5260 | mutex_lock(&dev_priv->sb_lock); |
c6e8f39d | 5261 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
a580516d | 5262 | mutex_unlock(&dev_priv->sb_lock); |
c6e8f39d | 5263 | |
2bb25c17 | 5264 | switch ((val >> 2) & 0x7) { |
2bb25c17 | 5265 | case 3: |
2bb25c17 VS |
5266 | dev_priv->mem_freq = 2000; |
5267 | break; | |
bfa7df01 | 5268 | default: |
2bb25c17 VS |
5269 | dev_priv->mem_freq = 1600; |
5270 | break; | |
5271 | } | |
80b83b62 | 5272 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 5273 | |
2b6b3a09 D |
5274 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
5275 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
5276 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5277 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
5278 | dev_priv->rps.max_freq); |
5279 | ||
5280 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
5281 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5282 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
5283 | dev_priv->rps.efficient_freq); |
5284 | ||
7707df4a D |
5285 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
5286 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5287 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
5288 | dev_priv->rps.rp1_freq); |
5289 | ||
5b7c91b7 D |
5290 | /* PUnit validated range is only [RPe, RP0] */ |
5291 | dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; | |
2b6b3a09 | 5292 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 5293 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
5294 | dev_priv->rps.min_freq); |
5295 | ||
1c14762d VS |
5296 | WARN_ONCE((dev_priv->rps.max_freq | |
5297 | dev_priv->rps.efficient_freq | | |
5298 | dev_priv->rps.rp1_freq | | |
5299 | dev_priv->rps.min_freq) & 1, | |
5300 | "Odd GPU freq values\n"); | |
5301 | ||
aed242ff CW |
5302 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; |
5303 | ||
2b6b3a09 D |
5304 | /* Preserve min/max settings in case of re-init */ |
5305 | if (dev_priv->rps.max_freq_softlimit == 0) | |
5306 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
5307 | ||
5308 | if (dev_priv->rps.min_freq_softlimit == 0) | |
5309 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
5310 | ||
5311 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
5312 | } |
5313 | ||
4e80519e ID |
5314 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
5315 | { | |
5316 | valleyview_cleanup_pctx(dev); | |
5317 | } | |
5318 | ||
38807746 D |
5319 | static void cherryview_enable_rps(struct drm_device *dev) |
5320 | { | |
5321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5322 | struct intel_engine_cs *ring; | |
2b6b3a09 | 5323 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
5324 | int i; |
5325 | ||
5326 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5327 | ||
5328 | gtfifodbg = I915_READ(GTFIFODBG); | |
5329 | if (gtfifodbg) { | |
5330 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
5331 | gtfifodbg); | |
5332 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
5333 | } | |
5334 | ||
5335 | cherryview_check_pctx(dev_priv); | |
5336 | ||
5337 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
5338 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 5339 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 5340 | |
160614a2 VS |
5341 | /* Disable RC states. */ |
5342 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5343 | ||
38807746 D |
5344 | /* 2a: Program RC6 thresholds.*/ |
5345 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
5346 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
5347 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
5348 | ||
5349 | for_each_ring(ring, dev_priv, i) | |
5350 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5351 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
5352 | ||
f4f71c7d D |
5353 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
5354 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); | |
38807746 D |
5355 | |
5356 | /* allows RC6 residency counter to work */ | |
5357 | I915_WRITE(VLV_COUNTER_CONTROL, | |
5358 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
5359 | VLV_MEDIA_RC6_COUNT_EN | | |
5360 | VLV_RENDER_RC6_COUNT_EN)); | |
5361 | ||
5362 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
5363 | pcbr = I915_READ(VLV_PCBR); | |
5364 | ||
38807746 D |
5365 | /* 3: Enable RC6 */ |
5366 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
5367 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 5368 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
5369 | |
5370 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
5371 | ||
2b6b3a09 | 5372 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 5373 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
5374 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5375 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5376 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5377 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5378 | ||
5379 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5380 | ||
5381 | /* 5: Enable RPS */ | |
5382 | I915_WRITE(GEN6_RP_CONTROL, | |
5383 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 5384 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
5385 | GEN6_RP_ENABLE | |
5386 | GEN6_RP_UP_BUSY_AVG | | |
5387 | GEN6_RP_DOWN_IDLE_AVG); | |
5388 | ||
3ef62342 D |
5389 | /* Setting Fixed Bias */ |
5390 | val = VLV_OVERRIDE_EN | | |
5391 | VLV_SOC_TDP_EN | | |
5392 | CHV_BIAS_CPU_50_SOC_50; | |
5393 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
5394 | ||
2b6b3a09 D |
5395 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
5396 | ||
8d40c3ae VS |
5397 | /* RPS code assumes GPLL is used */ |
5398 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
5399 | ||
742f491d | 5400 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
2b6b3a09 D |
5401 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5402 | ||
5403 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
5404 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 5405 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
2b6b3a09 D |
5406 | dev_priv->rps.cur_freq); |
5407 | ||
5408 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
7c59a9c1 | 5409 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
5410 | dev_priv->rps.efficient_freq); |
5411 | ||
5412 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
5413 | ||
59bad947 | 5414 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
5415 | } |
5416 | ||
0a073b84 JB |
5417 | static void valleyview_enable_rps(struct drm_device *dev) |
5418 | { | |
5419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 5420 | struct intel_engine_cs *ring; |
2a5913a8 | 5421 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
5422 | int i; |
5423 | ||
5424 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5425 | ||
ae48434c ID |
5426 | valleyview_check_pctx(dev_priv); |
5427 | ||
0a073b84 | 5428 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
5429 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5430 | gtfifodbg); | |
0a073b84 JB |
5431 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5432 | } | |
5433 | ||
c8d9a590 | 5434 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 5435 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 5436 | |
160614a2 VS |
5437 | /* Disable RC states. */ |
5438 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5439 | ||
cad725fe | 5440 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
5441 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5442 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5443 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5444 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5445 | ||
5446 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5447 | ||
5448 | I915_WRITE(GEN6_RP_CONTROL, | |
5449 | GEN6_RP_MEDIA_TURBO | | |
5450 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5451 | GEN6_RP_MEDIA_IS_GFX | | |
5452 | GEN6_RP_ENABLE | | |
5453 | GEN6_RP_UP_BUSY_AVG | | |
5454 | GEN6_RP_DOWN_IDLE_CONT); | |
5455 | ||
5456 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
5457 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
5458 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
5459 | ||
5460 | for_each_ring(ring, dev_priv, i) | |
5461 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5462 | ||
2f0aa304 | 5463 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
5464 | |
5465 | /* allows RC6 residency counter to work */ | |
49798eb2 | 5466 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
5467 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
5468 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
5469 | VLV_MEDIA_RC6_COUNT_EN | |
5470 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 5471 | |
a2b23fe0 | 5472 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 5473 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
5474 | |
5475 | intel_print_rc6_info(dev, rc6_mode); | |
5476 | ||
a2b23fe0 | 5477 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 5478 | |
3ef62342 D |
5479 | /* Setting Fixed Bias */ |
5480 | val = VLV_OVERRIDE_EN | | |
5481 | VLV_SOC_TDP_EN | | |
5482 | VLV_BIAS_CPU_125_SOC_875; | |
5483 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
5484 | ||
64936258 | 5485 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 5486 | |
8d40c3ae VS |
5487 | /* RPS code assumes GPLL is used */ |
5488 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
5489 | ||
742f491d | 5490 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
0a073b84 JB |
5491 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5492 | ||
b39fb297 | 5493 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 5494 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 5495 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
b39fb297 | 5496 | dev_priv->rps.cur_freq); |
0a073b84 | 5497 | |
73008b98 | 5498 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
7c59a9c1 | 5499 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
b39fb297 | 5500 | dev_priv->rps.efficient_freq); |
0a073b84 | 5501 | |
b39fb297 | 5502 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 5503 | |
59bad947 | 5504 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
5505 | } |
5506 | ||
dde18883 ED |
5507 | static unsigned long intel_pxfreq(u32 vidfreq) |
5508 | { | |
5509 | unsigned long freq; | |
5510 | int div = (vidfreq & 0x3f0000) >> 16; | |
5511 | int post = (vidfreq & 0x3000) >> 12; | |
5512 | int pre = (vidfreq & 0x7); | |
5513 | ||
5514 | if (!pre) | |
5515 | return 0; | |
5516 | ||
5517 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5518 | ||
5519 | return freq; | |
5520 | } | |
5521 | ||
eb48eb00 DV |
5522 | static const struct cparams { |
5523 | u16 i; | |
5524 | u16 t; | |
5525 | u16 m; | |
5526 | u16 c; | |
5527 | } cparams[] = { | |
5528 | { 1, 1333, 301, 28664 }, | |
5529 | { 1, 1066, 294, 24460 }, | |
5530 | { 1, 800, 294, 25192 }, | |
5531 | { 0, 1333, 276, 27605 }, | |
5532 | { 0, 1066, 276, 27605 }, | |
5533 | { 0, 800, 231, 23784 }, | |
5534 | }; | |
5535 | ||
f531dcb2 | 5536 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5537 | { |
5538 | u64 total_count, diff, ret; | |
5539 | u32 count1, count2, count3, m = 0, c = 0; | |
5540 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
5541 | int i; | |
5542 | ||
02d71956 DV |
5543 | assert_spin_locked(&mchdev_lock); |
5544 | ||
20e4d407 | 5545 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
5546 | |
5547 | /* Prevent division-by-zero if we are asking too fast. | |
5548 | * Also, we don't get interesting results if we are polling | |
5549 | * faster than once in 10ms, so just return the saved value | |
5550 | * in such cases. | |
5551 | */ | |
5552 | if (diff1 <= 10) | |
20e4d407 | 5553 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
5554 | |
5555 | count1 = I915_READ(DMIEC); | |
5556 | count2 = I915_READ(DDREC); | |
5557 | count3 = I915_READ(CSIEC); | |
5558 | ||
5559 | total_count = count1 + count2 + count3; | |
5560 | ||
5561 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
5562 | if (total_count < dev_priv->ips.last_count1) { |
5563 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
5564 | diff += total_count; |
5565 | } else { | |
20e4d407 | 5566 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
5567 | } |
5568 | ||
5569 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
5570 | if (cparams[i].i == dev_priv->ips.c_m && |
5571 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
5572 | m = cparams[i].m; |
5573 | c = cparams[i].c; | |
5574 | break; | |
5575 | } | |
5576 | } | |
5577 | ||
5578 | diff = div_u64(diff, diff1); | |
5579 | ret = ((m * diff) + c); | |
5580 | ret = div_u64(ret, 10); | |
5581 | ||
20e4d407 DV |
5582 | dev_priv->ips.last_count1 = total_count; |
5583 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 5584 | |
20e4d407 | 5585 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
5586 | |
5587 | return ret; | |
5588 | } | |
5589 | ||
f531dcb2 CW |
5590 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5591 | { | |
3d13ef2e | 5592 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5593 | unsigned long val; |
5594 | ||
3d13ef2e | 5595 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5596 | return 0; |
5597 | ||
5598 | spin_lock_irq(&mchdev_lock); | |
5599 | ||
5600 | val = __i915_chipset_val(dev_priv); | |
5601 | ||
5602 | spin_unlock_irq(&mchdev_lock); | |
5603 | ||
5604 | return val; | |
5605 | } | |
5606 | ||
eb48eb00 DV |
5607 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5608 | { | |
5609 | unsigned long m, x, b; | |
5610 | u32 tsfs; | |
5611 | ||
5612 | tsfs = I915_READ(TSFS); | |
5613 | ||
5614 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
5615 | x = I915_READ8(TR1); | |
5616 | ||
5617 | b = tsfs & TSFS_INTR_MASK; | |
5618 | ||
5619 | return ((m * x) / 127) - b; | |
5620 | } | |
5621 | ||
d972d6ee MK |
5622 | static int _pxvid_to_vd(u8 pxvid) |
5623 | { | |
5624 | if (pxvid == 0) | |
5625 | return 0; | |
5626 | ||
5627 | if (pxvid >= 8 && pxvid < 31) | |
5628 | pxvid = 31; | |
5629 | ||
5630 | return (pxvid + 2) * 125; | |
5631 | } | |
5632 | ||
5633 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 5634 | { |
3d13ef2e | 5635 | struct drm_device *dev = dev_priv->dev; |
d972d6ee MK |
5636 | const int vd = _pxvid_to_vd(pxvid); |
5637 | const int vm = vd - 1125; | |
5638 | ||
3d13ef2e | 5639 | if (INTEL_INFO(dev)->is_mobile) |
d972d6ee MK |
5640 | return vm > 0 ? vm : 0; |
5641 | ||
5642 | return vd; | |
eb48eb00 DV |
5643 | } |
5644 | ||
02d71956 | 5645 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 5646 | { |
5ed0bdf2 | 5647 | u64 now, diff, diffms; |
eb48eb00 DV |
5648 | u32 count; |
5649 | ||
02d71956 | 5650 | assert_spin_locked(&mchdev_lock); |
eb48eb00 | 5651 | |
5ed0bdf2 TG |
5652 | now = ktime_get_raw_ns(); |
5653 | diffms = now - dev_priv->ips.last_time2; | |
5654 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
5655 | |
5656 | /* Don't divide by 0 */ | |
eb48eb00 DV |
5657 | if (!diffms) |
5658 | return; | |
5659 | ||
5660 | count = I915_READ(GFXEC); | |
5661 | ||
20e4d407 DV |
5662 | if (count < dev_priv->ips.last_count2) { |
5663 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
5664 | diff += count; |
5665 | } else { | |
20e4d407 | 5666 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
5667 | } |
5668 | ||
20e4d407 DV |
5669 | dev_priv->ips.last_count2 = count; |
5670 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
5671 | |
5672 | /* More magic constants... */ | |
5673 | diff = diff * 1181; | |
5674 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 5675 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
5676 | } |
5677 | ||
02d71956 DV |
5678 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5679 | { | |
3d13ef2e DL |
5680 | struct drm_device *dev = dev_priv->dev; |
5681 | ||
5682 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
5683 | return; |
5684 | ||
9270388e | 5685 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
5686 | |
5687 | __i915_update_gfx_val(dev_priv); | |
5688 | ||
9270388e | 5689 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
5690 | } |
5691 | ||
f531dcb2 | 5692 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5693 | { |
5694 | unsigned long t, corr, state1, corr2, state2; | |
5695 | u32 pxvid, ext_v; | |
5696 | ||
02d71956 DV |
5697 | assert_spin_locked(&mchdev_lock); |
5698 | ||
616847e7 | 5699 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
eb48eb00 DV |
5700 | pxvid = (pxvid >> 24) & 0x7f; |
5701 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5702 | ||
5703 | state1 = ext_v; | |
5704 | ||
5705 | t = i915_mch_val(dev_priv); | |
5706 | ||
5707 | /* Revel in the empirically derived constants */ | |
5708 | ||
5709 | /* Correction factor in 1/100000 units */ | |
5710 | if (t > 80) | |
5711 | corr = ((t * 2349) + 135940); | |
5712 | else if (t >= 50) | |
5713 | corr = ((t * 964) + 29317); | |
5714 | else /* < 50 */ | |
5715 | corr = ((t * 301) + 1004); | |
5716 | ||
5717 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5718 | corr /= 100000; | |
20e4d407 | 5719 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
5720 | |
5721 | state2 = (corr2 * state1) / 10000; | |
5722 | state2 /= 100; /* convert to mW */ | |
5723 | ||
02d71956 | 5724 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 5725 | |
20e4d407 | 5726 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
5727 | } |
5728 | ||
f531dcb2 CW |
5729 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5730 | { | |
3d13ef2e | 5731 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5732 | unsigned long val; |
5733 | ||
3d13ef2e | 5734 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5735 | return 0; |
5736 | ||
5737 | spin_lock_irq(&mchdev_lock); | |
5738 | ||
5739 | val = __i915_gfx_val(dev_priv); | |
5740 | ||
5741 | spin_unlock_irq(&mchdev_lock); | |
5742 | ||
5743 | return val; | |
5744 | } | |
5745 | ||
eb48eb00 DV |
5746 | /** |
5747 | * i915_read_mch_val - return value for IPS use | |
5748 | * | |
5749 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5750 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5751 | */ | |
5752 | unsigned long i915_read_mch_val(void) | |
5753 | { | |
5754 | struct drm_i915_private *dev_priv; | |
5755 | unsigned long chipset_val, graphics_val, ret = 0; | |
5756 | ||
9270388e | 5757 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5758 | if (!i915_mch_dev) |
5759 | goto out_unlock; | |
5760 | dev_priv = i915_mch_dev; | |
5761 | ||
f531dcb2 CW |
5762 | chipset_val = __i915_chipset_val(dev_priv); |
5763 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
5764 | |
5765 | ret = chipset_val + graphics_val; | |
5766 | ||
5767 | out_unlock: | |
9270388e | 5768 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5769 | |
5770 | return ret; | |
5771 | } | |
5772 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5773 | ||
5774 | /** | |
5775 | * i915_gpu_raise - raise GPU frequency limit | |
5776 | * | |
5777 | * Raise the limit; IPS indicates we have thermal headroom. | |
5778 | */ | |
5779 | bool i915_gpu_raise(void) | |
5780 | { | |
5781 | struct drm_i915_private *dev_priv; | |
5782 | bool ret = true; | |
5783 | ||
9270388e | 5784 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5785 | if (!i915_mch_dev) { |
5786 | ret = false; | |
5787 | goto out_unlock; | |
5788 | } | |
5789 | dev_priv = i915_mch_dev; | |
5790 | ||
20e4d407 DV |
5791 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5792 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
5793 | |
5794 | out_unlock: | |
9270388e | 5795 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5796 | |
5797 | return ret; | |
5798 | } | |
5799 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5800 | ||
5801 | /** | |
5802 | * i915_gpu_lower - lower GPU frequency limit | |
5803 | * | |
5804 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5805 | * frequency maximum. | |
5806 | */ | |
5807 | bool i915_gpu_lower(void) | |
5808 | { | |
5809 | struct drm_i915_private *dev_priv; | |
5810 | bool ret = true; | |
5811 | ||
9270388e | 5812 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5813 | if (!i915_mch_dev) { |
5814 | ret = false; | |
5815 | goto out_unlock; | |
5816 | } | |
5817 | dev_priv = i915_mch_dev; | |
5818 | ||
20e4d407 DV |
5819 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5820 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
5821 | |
5822 | out_unlock: | |
9270388e | 5823 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5824 | |
5825 | return ret; | |
5826 | } | |
5827 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5828 | ||
5829 | /** | |
5830 | * i915_gpu_busy - indicate GPU business to IPS | |
5831 | * | |
5832 | * Tell the IPS driver whether or not the GPU is busy. | |
5833 | */ | |
5834 | bool i915_gpu_busy(void) | |
5835 | { | |
5836 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 5837 | struct intel_engine_cs *ring; |
eb48eb00 | 5838 | bool ret = false; |
f047e395 | 5839 | int i; |
eb48eb00 | 5840 | |
9270388e | 5841 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5842 | if (!i915_mch_dev) |
5843 | goto out_unlock; | |
5844 | dev_priv = i915_mch_dev; | |
5845 | ||
f047e395 CW |
5846 | for_each_ring(ring, dev_priv, i) |
5847 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
5848 | |
5849 | out_unlock: | |
9270388e | 5850 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5851 | |
5852 | return ret; | |
5853 | } | |
5854 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5855 | ||
5856 | /** | |
5857 | * i915_gpu_turbo_disable - disable graphics turbo | |
5858 | * | |
5859 | * Disable graphics turbo by resetting the max frequency and setting the | |
5860 | * current frequency to the default. | |
5861 | */ | |
5862 | bool i915_gpu_turbo_disable(void) | |
5863 | { | |
5864 | struct drm_i915_private *dev_priv; | |
5865 | bool ret = true; | |
5866 | ||
9270388e | 5867 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5868 | if (!i915_mch_dev) { |
5869 | ret = false; | |
5870 | goto out_unlock; | |
5871 | } | |
5872 | dev_priv = i915_mch_dev; | |
5873 | ||
20e4d407 | 5874 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 5875 | |
20e4d407 | 5876 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
5877 | ret = false; |
5878 | ||
5879 | out_unlock: | |
9270388e | 5880 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5881 | |
5882 | return ret; | |
5883 | } | |
5884 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
5885 | ||
5886 | /** | |
5887 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
5888 | * IPS got loaded first. | |
5889 | * | |
5890 | * This awkward dance is so that neither module has to depend on the | |
5891 | * other in order for IPS to do the appropriate communication of | |
5892 | * GPU turbo limits to i915. | |
5893 | */ | |
5894 | static void | |
5895 | ips_ping_for_i915_load(void) | |
5896 | { | |
5897 | void (*link)(void); | |
5898 | ||
5899 | link = symbol_get(ips_link_to_i915_driver); | |
5900 | if (link) { | |
5901 | link(); | |
5902 | symbol_put(ips_link_to_i915_driver); | |
5903 | } | |
5904 | } | |
5905 | ||
5906 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
5907 | { | |
02d71956 DV |
5908 | /* We only register the i915 ips part with intel-ips once everything is |
5909 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 5910 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5911 | i915_mch_dev = dev_priv; |
9270388e | 5912 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5913 | |
5914 | ips_ping_for_i915_load(); | |
5915 | } | |
5916 | ||
5917 | void intel_gpu_ips_teardown(void) | |
5918 | { | |
9270388e | 5919 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5920 | i915_mch_dev = NULL; |
9270388e | 5921 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 5922 | } |
76c3552f | 5923 | |
8090c6b9 | 5924 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
5925 | { |
5926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5927 | u32 lcfuse; | |
5928 | u8 pxw[16]; | |
5929 | int i; | |
5930 | ||
5931 | /* Disable to program */ | |
5932 | I915_WRITE(ECR, 0); | |
5933 | POSTING_READ(ECR); | |
5934 | ||
5935 | /* Program energy weights for various events */ | |
5936 | I915_WRITE(SDEW, 0x15040d00); | |
5937 | I915_WRITE(CSIEW0, 0x007f0000); | |
5938 | I915_WRITE(CSIEW1, 0x1e220004); | |
5939 | I915_WRITE(CSIEW2, 0x04000004); | |
5940 | ||
5941 | for (i = 0; i < 5; i++) | |
616847e7 | 5942 | I915_WRITE(PEW(i), 0); |
dde18883 | 5943 | for (i = 0; i < 3; i++) |
616847e7 | 5944 | I915_WRITE(DEW(i), 0); |
dde18883 ED |
5945 | |
5946 | /* Program P-state weights to account for frequency power adjustment */ | |
5947 | for (i = 0; i < 16; i++) { | |
616847e7 | 5948 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
dde18883 ED |
5949 | unsigned long freq = intel_pxfreq(pxvidfreq); |
5950 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5951 | PXVFREQ_PX_SHIFT; | |
5952 | unsigned long val; | |
5953 | ||
5954 | val = vid * vid; | |
5955 | val *= (freq / 1000); | |
5956 | val *= 255; | |
5957 | val /= (127*127*900); | |
5958 | if (val > 0xff) | |
5959 | DRM_ERROR("bad pxval: %ld\n", val); | |
5960 | pxw[i] = val; | |
5961 | } | |
5962 | /* Render standby states get 0 weight */ | |
5963 | pxw[14] = 0; | |
5964 | pxw[15] = 0; | |
5965 | ||
5966 | for (i = 0; i < 4; i++) { | |
5967 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5968 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
616847e7 | 5969 | I915_WRITE(PXW(i), val); |
dde18883 ED |
5970 | } |
5971 | ||
5972 | /* Adjust magic regs to magic values (more experimental results) */ | |
5973 | I915_WRITE(OGW0, 0); | |
5974 | I915_WRITE(OGW1, 0); | |
5975 | I915_WRITE(EG0, 0x00007f00); | |
5976 | I915_WRITE(EG1, 0x0000000e); | |
5977 | I915_WRITE(EG2, 0x000e0000); | |
5978 | I915_WRITE(EG3, 0x68000300); | |
5979 | I915_WRITE(EG4, 0x42000000); | |
5980 | I915_WRITE(EG5, 0x00140031); | |
5981 | I915_WRITE(EG6, 0); | |
5982 | I915_WRITE(EG7, 0); | |
5983 | ||
5984 | for (i = 0; i < 8; i++) | |
616847e7 | 5985 | I915_WRITE(PXWL(i), 0); |
dde18883 ED |
5986 | |
5987 | /* Enable PMON + select events */ | |
5988 | I915_WRITE(ECR, 0x80000019); | |
5989 | ||
5990 | lcfuse = I915_READ(LCFUSE02); | |
5991 | ||
20e4d407 | 5992 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
5993 | } |
5994 | ||
ae48434c ID |
5995 | void intel_init_gt_powersave(struct drm_device *dev) |
5996 | { | |
e6069ca8 ID |
5997 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
5998 | ||
38807746 D |
5999 | if (IS_CHERRYVIEW(dev)) |
6000 | cherryview_init_gt_powersave(dev); | |
6001 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 6002 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
6003 | } |
6004 | ||
6005 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
6006 | { | |
38807746 D |
6007 | if (IS_CHERRYVIEW(dev)) |
6008 | return; | |
6009 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 6010 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
6011 | } |
6012 | ||
dbea3cea ID |
6013 | static void gen6_suspend_rps(struct drm_device *dev) |
6014 | { | |
6015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6016 | ||
6017 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
6018 | ||
4c2a8897 | 6019 | gen6_disable_rps_interrupts(dev); |
dbea3cea ID |
6020 | } |
6021 | ||
156c7ca0 JB |
6022 | /** |
6023 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
6024 | * @dev: drm device | |
6025 | * | |
6026 | * We don't want to disable RC6 or other features here, we just want | |
6027 | * to make sure any work we've queued has finished and won't bother | |
6028 | * us while we're suspended. | |
6029 | */ | |
6030 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
6031 | { | |
6032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6033 | ||
d4d70aa5 ID |
6034 | if (INTEL_INFO(dev)->gen < 6) |
6035 | return; | |
6036 | ||
dbea3cea | 6037 | gen6_suspend_rps(dev); |
b47adc17 D |
6038 | |
6039 | /* Force GPU to min freq during suspend */ | |
6040 | gen6_rps_idle(dev_priv); | |
156c7ca0 JB |
6041 | } |
6042 | ||
8090c6b9 DV |
6043 | void intel_disable_gt_powersave(struct drm_device *dev) |
6044 | { | |
1a01ab3b JB |
6045 | struct drm_i915_private *dev_priv = dev->dev_private; |
6046 | ||
930ebb46 | 6047 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 6048 | ironlake_disable_drps(dev); |
38807746 | 6049 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 6050 | intel_suspend_gt_powersave(dev); |
e494837a | 6051 | |
4fc688ce | 6052 | mutex_lock(&dev_priv->rps.hw_lock); |
20e49366 ZW |
6053 | if (INTEL_INFO(dev)->gen >= 9) |
6054 | gen9_disable_rps(dev); | |
6055 | else if (IS_CHERRYVIEW(dev)) | |
38807746 D |
6056 | cherryview_disable_rps(dev); |
6057 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
6058 | valleyview_disable_rps(dev); |
6059 | else | |
6060 | gen6_disable_rps(dev); | |
e534770a | 6061 | |
c0951f0c | 6062 | dev_priv->rps.enabled = false; |
4fc688ce | 6063 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 6064 | } |
8090c6b9 DV |
6065 | } |
6066 | ||
1a01ab3b JB |
6067 | static void intel_gen6_powersave_work(struct work_struct *work) |
6068 | { | |
6069 | struct drm_i915_private *dev_priv = | |
6070 | container_of(work, struct drm_i915_private, | |
6071 | rps.delayed_resume_work.work); | |
6072 | struct drm_device *dev = dev_priv->dev; | |
6073 | ||
4fc688ce | 6074 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 6075 | |
4c2a8897 | 6076 | gen6_reset_rps_interrupts(dev); |
3cc134e3 | 6077 | |
38807746 D |
6078 | if (IS_CHERRYVIEW(dev)) { |
6079 | cherryview_enable_rps(dev); | |
6080 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 6081 | valleyview_enable_rps(dev); |
20e49366 | 6082 | } else if (INTEL_INFO(dev)->gen >= 9) { |
b6fef0ef | 6083 | gen9_enable_rc6(dev); |
20e49366 | 6084 | gen9_enable_rps(dev); |
ef11bdb3 | 6085 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
cc017fb4 | 6086 | __gen6_update_ring_freq(dev); |
6edee7f3 BW |
6087 | } else if (IS_BROADWELL(dev)) { |
6088 | gen8_enable_rps(dev); | |
c2bc2fc5 | 6089 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
6090 | } else { |
6091 | gen6_enable_rps(dev); | |
c2bc2fc5 | 6092 | __gen6_update_ring_freq(dev); |
0a073b84 | 6093 | } |
aed242ff CW |
6094 | |
6095 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); | |
6096 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); | |
6097 | ||
6098 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); | |
6099 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); | |
6100 | ||
c0951f0c | 6101 | dev_priv->rps.enabled = true; |
3cc134e3 | 6102 | |
4c2a8897 | 6103 | gen6_enable_rps_interrupts(dev); |
3cc134e3 | 6104 | |
4fc688ce | 6105 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
6106 | |
6107 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
6108 | } |
6109 | ||
8090c6b9 DV |
6110 | void intel_enable_gt_powersave(struct drm_device *dev) |
6111 | { | |
1a01ab3b JB |
6112 | struct drm_i915_private *dev_priv = dev->dev_private; |
6113 | ||
f61018b1 YZ |
6114 | /* Powersaving is controlled by the host when inside a VM */ |
6115 | if (intel_vgpu_active(dev)) | |
6116 | return; | |
6117 | ||
8090c6b9 | 6118 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 6119 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 6120 | ironlake_enable_drps(dev); |
8090c6b9 | 6121 | intel_init_emon(dev); |
dc1d0136 | 6122 | mutex_unlock(&dev->struct_mutex); |
38807746 | 6123 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
6124 | /* |
6125 | * PCU communication is slow and this doesn't need to be | |
6126 | * done at any specific time, so do this out of our fast path | |
6127 | * to make resume and init faster. | |
c6df39b5 ID |
6128 | * |
6129 | * We depend on the HW RC6 power context save/restore | |
6130 | * mechanism when entering D3 through runtime PM suspend. So | |
6131 | * disable RPM until RPS/RC6 is properly setup. We can only | |
6132 | * get here via the driver load/system resume/runtime resume | |
6133 | * paths, so the _noresume version is enough (and in case of | |
6134 | * runtime resume it's necessary). | |
1a01ab3b | 6135 | */ |
c6df39b5 ID |
6136 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
6137 | round_jiffies_up_relative(HZ))) | |
6138 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
6139 | } |
6140 | } | |
6141 | ||
c6df39b5 ID |
6142 | void intel_reset_gt_powersave(struct drm_device *dev) |
6143 | { | |
6144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6145 | ||
dbea3cea ID |
6146 | if (INTEL_INFO(dev)->gen < 6) |
6147 | return; | |
6148 | ||
6149 | gen6_suspend_rps(dev); | |
c6df39b5 | 6150 | dev_priv->rps.enabled = false; |
c6df39b5 ID |
6151 | } |
6152 | ||
3107bd48 DV |
6153 | static void ibx_init_clock_gating(struct drm_device *dev) |
6154 | { | |
6155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6156 | ||
6157 | /* | |
6158 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6159 | * gating for the panel power sequencer or it will fail to | |
6160 | * start up when no ports are active. | |
6161 | */ | |
6162 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
6163 | } | |
6164 | ||
0e088b8f VS |
6165 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
6166 | { | |
6167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b12ce1d8 | 6168 | enum pipe pipe; |
0e088b8f | 6169 | |
055e393f | 6170 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
6171 | I915_WRITE(DSPCNTR(pipe), |
6172 | I915_READ(DSPCNTR(pipe)) | | |
6173 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
b12ce1d8 VS |
6174 | |
6175 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); | |
6176 | POSTING_READ(DSPSURF(pipe)); | |
0e088b8f VS |
6177 | } |
6178 | } | |
6179 | ||
017636cc VS |
6180 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
6181 | { | |
6182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6183 | ||
6184 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
6185 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
6186 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
6187 | ||
6188 | /* | |
6189 | * Don't touch WM1S_LP_EN here. | |
6190 | * Doing so could cause underruns. | |
6191 | */ | |
6192 | } | |
6193 | ||
1fa61106 | 6194 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6195 | { |
6196 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 6197 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 6198 | |
f1e8fa56 DL |
6199 | /* |
6200 | * Required for FBC | |
6201 | * WaFbcDisableDpfcClockGating:ilk | |
6202 | */ | |
4d47e4f5 DL |
6203 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
6204 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
6205 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
6206 | |
6207 | I915_WRITE(PCH_3DCGDIS0, | |
6208 | MARIUNIT_CLOCK_GATE_DISABLE | | |
6209 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
6210 | I915_WRITE(PCH_3DCGDIS1, | |
6211 | VFMUNIT_CLOCK_GATE_DISABLE); | |
6212 | ||
6f1d69b0 ED |
6213 | /* |
6214 | * According to the spec the following bits should be set in | |
6215 | * order to enable memory self-refresh | |
6216 | * The bit 22/21 of 0x42004 | |
6217 | * The bit 5 of 0x42020 | |
6218 | * The bit 15 of 0x45000 | |
6219 | */ | |
6220 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6221 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6222 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 6223 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
6224 | I915_WRITE(DISP_ARB_CTL, |
6225 | (I915_READ(DISP_ARB_CTL) | | |
6226 | DISP_FBC_WM_DIS)); | |
017636cc VS |
6227 | |
6228 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
6229 | |
6230 | /* | |
6231 | * Based on the document from hardware guys the following bits | |
6232 | * should be set unconditionally in order to enable FBC. | |
6233 | * The bit 22 of 0x42000 | |
6234 | * The bit 22 of 0x42004 | |
6235 | * The bit 7,8,9 of 0x42020. | |
6236 | */ | |
6237 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 6238 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
6239 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
6240 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6241 | ILK_FBCQ_DIS); | |
6242 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6243 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6244 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
6245 | } |
6246 | ||
4d47e4f5 DL |
6247 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6248 | ||
6f1d69b0 ED |
6249 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6250 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6251 | ILK_ELPIN_409_SELECT); | |
6252 | I915_WRITE(_3D_CHICKEN2, | |
6253 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
6254 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 6255 | |
ecdb4eb7 | 6256 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
6257 | I915_WRITE(CACHE_MODE_0, |
6258 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 6259 | |
4e04632e AG |
6260 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
6261 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6262 | ||
0e088b8f | 6263 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 6264 | |
3107bd48 DV |
6265 | ibx_init_clock_gating(dev); |
6266 | } | |
6267 | ||
6268 | static void cpt_init_clock_gating(struct drm_device *dev) | |
6269 | { | |
6270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6271 | int pipe; | |
3f704fa2 | 6272 | uint32_t val; |
3107bd48 DV |
6273 | |
6274 | /* | |
6275 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6276 | * gating for the panel power sequencer or it will fail to | |
6277 | * start up when no ports are active. | |
6278 | */ | |
cd664078 JB |
6279 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
6280 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
6281 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
6282 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
6283 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
6284 | /* The below fixes the weird display corruption, a few pixels shifted |
6285 | * downward, on (only) LVDS of some HP laptops with IVY. | |
6286 | */ | |
055e393f | 6287 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
6288 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
6289 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
6290 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 6291 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 6292 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
6293 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
6294 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
6295 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
6296 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
6297 | } | |
3107bd48 | 6298 | /* WADP0ClockGatingDisable */ |
055e393f | 6299 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
6300 | I915_WRITE(TRANS_CHICKEN1(pipe), |
6301 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
6302 | } | |
6f1d69b0 ED |
6303 | } |
6304 | ||
1d7aaa0c DV |
6305 | static void gen6_check_mch_setup(struct drm_device *dev) |
6306 | { | |
6307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6308 | uint32_t tmp; | |
6309 | ||
6310 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
6311 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
6312 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
6313 | tmp); | |
1d7aaa0c DV |
6314 | } |
6315 | ||
1fa61106 | 6316 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6317 | { |
6318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 6319 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 6320 | |
231e54f6 | 6321 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
6322 | |
6323 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6324 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6325 | ILK_ELPIN_409_SELECT); | |
6326 | ||
ecdb4eb7 | 6327 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
6328 | I915_WRITE(_3D_CHICKEN, |
6329 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
6330 | ||
4e04632e AG |
6331 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
6332 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6333 | ||
8d85d272 VS |
6334 | /* |
6335 | * BSpec recoomends 8x4 when MSAA is used, | |
6336 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6337 | * |
6338 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6339 | * disable bit, which we don't touch here, but it's good | |
6340 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
6341 | */ |
6342 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 6343 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 6344 | |
017636cc | 6345 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6346 | |
6f1d69b0 | 6347 | I915_WRITE(CACHE_MODE_0, |
50743298 | 6348 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
6349 | |
6350 | I915_WRITE(GEN6_UCGCTL1, | |
6351 | I915_READ(GEN6_UCGCTL1) | | |
6352 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
6353 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
6354 | ||
6355 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
6356 | * gating disable must be set. Failure to set it results in | |
6357 | * flickering pixels due to Z write ordering failures after | |
6358 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
6359 | * Sanctuary and Tropics, and apparently anything else with | |
6360 | * alpha test or pixel discard. | |
6361 | * | |
6362 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
6363 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 6364 | * |
ef59318c VS |
6365 | * WaDisableRCCUnitClockGating:snb |
6366 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
6367 | */ |
6368 | I915_WRITE(GEN6_UCGCTL2, | |
6369 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
6370 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
6371 | ||
5eb146dd | 6372 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
6373 | I915_WRITE(_3D_CHICKEN3, |
6374 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 6375 | |
e927ecde VS |
6376 | /* |
6377 | * Bspec says: | |
6378 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
6379 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
6380 | */ | |
6381 | I915_WRITE(_3D_CHICKEN3, | |
6382 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
6383 | ||
6f1d69b0 ED |
6384 | /* |
6385 | * According to the spec the following bits should be | |
6386 | * set in order to enable memory self-refresh and fbc: | |
6387 | * The bit21 and bit22 of 0x42000 | |
6388 | * The bit21 and bit22 of 0x42004 | |
6389 | * The bit5 and bit7 of 0x42020 | |
6390 | * The bit14 of 0x70180 | |
6391 | * The bit14 of 0x71180 | |
4bb35334 DL |
6392 | * |
6393 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
6394 | */ |
6395 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6396 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6397 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
6398 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6399 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6400 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
6401 | I915_WRITE(ILK_DSPCLK_GATE_D, |
6402 | I915_READ(ILK_DSPCLK_GATE_D) | | |
6403 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
6404 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 6405 | |
0e088b8f | 6406 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 6407 | |
3107bd48 | 6408 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
6409 | |
6410 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6411 | } |
6412 | ||
6413 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
6414 | { | |
6415 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
6416 | ||
3aad9059 | 6417 | /* |
46680e0a | 6418 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
6419 | * |
6420 | * This actually overrides the dispatch | |
6421 | * mode for all thread types. | |
6422 | */ | |
6f1d69b0 ED |
6423 | reg &= ~GEN7_FF_SCHED_MASK; |
6424 | reg |= GEN7_FF_TS_SCHED_HW; | |
6425 | reg |= GEN7_FF_VS_SCHED_HW; | |
6426 | reg |= GEN7_FF_DS_SCHED_HW; | |
6427 | ||
6428 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
6429 | } | |
6430 | ||
17a303ec PZ |
6431 | static void lpt_init_clock_gating(struct drm_device *dev) |
6432 | { | |
6433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6434 | ||
6435 | /* | |
6436 | * TODO: this bit should only be enabled when really needed, then | |
6437 | * disabled when not needed anymore in order to save power. | |
6438 | */ | |
c2699524 | 6439 | if (HAS_PCH_LPT_LP(dev)) |
17a303ec PZ |
6440 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
6441 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
6442 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
6443 | |
6444 | /* WADPOClockGatingDisable:hsw */ | |
36c0d0cf VS |
6445 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
6446 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | | |
0a790cdb | 6447 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
17a303ec PZ |
6448 | } |
6449 | ||
7d708ee4 ID |
6450 | static void lpt_suspend_hw(struct drm_device *dev) |
6451 | { | |
6452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6453 | ||
c2699524 | 6454 | if (HAS_PCH_LPT_LP(dev)) { |
7d708ee4 ID |
6455 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
6456 | ||
6457 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6458 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6459 | } | |
6460 | } | |
6461 | ||
47c2bd97 | 6462 | static void broadwell_init_clock_gating(struct drm_device *dev) |
1020a5c2 BW |
6463 | { |
6464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 6465 | enum pipe pipe; |
4d487cff | 6466 | uint32_t misccpctl; |
1020a5c2 | 6467 | |
7ad0dbab | 6468 | ilk_init_lp_watermarks(dev); |
50ed5fbd | 6469 | |
ab57fff1 | 6470 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 6471 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 6472 | |
ab57fff1 | 6473 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
6474 | I915_WRITE(CHICKEN_PAR1_1, |
6475 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
6476 | ||
ab57fff1 | 6477 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 6478 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 6479 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 6480 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 6481 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 6482 | } |
63801f21 | 6483 | |
ab57fff1 BW |
6484 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6485 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
6486 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6487 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6488 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 6489 | |
295e8bb7 VS |
6490 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6491 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
6492 | |
6493 | /* WaDisableSDEUnitClockGating:bdw */ | |
6494 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6495 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 6496 | |
4d487cff VS |
6497 | /* |
6498 | * WaProgramL3SqcReg1Default:bdw | |
6499 | * WaTempDisableDOPClkGating:bdw | |
6500 | */ | |
6501 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
6502 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
6503 | I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); | |
6504 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
6505 | ||
6d50b065 VS |
6506 | /* |
6507 | * WaGttCachingOffByDefault:bdw | |
6508 | * GTT cache may not work with big pages, so if those | |
6509 | * are ever enabled GTT cache may need to be disabled. | |
6510 | */ | |
6511 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
6512 | ||
89d6b2b8 | 6513 | lpt_init_clock_gating(dev); |
1020a5c2 BW |
6514 | } |
6515 | ||
cad2a2d7 ED |
6516 | static void haswell_init_clock_gating(struct drm_device *dev) |
6517 | { | |
6518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 6519 | |
017636cc | 6520 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 6521 | |
f3fc4884 FJ |
6522 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6523 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
6524 | I915_WRITE(HSW_ROW_CHICKEN3, | |
6525 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
6526 | ||
ecdb4eb7 | 6527 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
6528 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6529 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6530 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6531 | ||
e36ea7ff VS |
6532 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6533 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6534 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 6535 | |
4e04632e AG |
6536 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6537 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6538 | ||
fe27c606 CW |
6539 | /* enable HiZ Raw Stall Optimization */ |
6540 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6541 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6542 | ||
ecdb4eb7 | 6543 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
6544 | I915_WRITE(CACHE_MODE_1, |
6545 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 6546 | |
a12c4967 VS |
6547 | /* |
6548 | * BSpec recommends 8x4 when MSAA is used, | |
6549 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6550 | * |
6551 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6552 | * disable bit, which we don't touch here, but it's good | |
6553 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
6554 | */ |
6555 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6556 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 6557 | |
94411593 KG |
6558 | /* WaSampleCChickenBitEnable:hsw */ |
6559 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
6560 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
6561 | ||
ecdb4eb7 | 6562 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
6563 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6564 | ||
90a88643 PZ |
6565 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6566 | I915_WRITE(CHICKEN_PAR1_1, | |
6567 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 6568 | |
17a303ec | 6569 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
6570 | } |
6571 | ||
1fa61106 | 6572 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6573 | { |
6574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 6575 | uint32_t snpcr; |
6f1d69b0 | 6576 | |
017636cc | 6577 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6578 | |
231e54f6 | 6579 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6580 | |
ecdb4eb7 | 6581 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
6582 | I915_WRITE(_3D_CHICKEN3, |
6583 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6584 | ||
ecdb4eb7 | 6585 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
6586 | I915_WRITE(IVB_CHICKEN3, |
6587 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6588 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6589 | ||
ecdb4eb7 | 6590 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
6591 | if (IS_IVB_GT1(dev)) |
6592 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6593 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6594 | |
4e04632e AG |
6595 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6596 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6597 | ||
ecdb4eb7 | 6598 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
6599 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6600 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
6601 | ||
ecdb4eb7 | 6602 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
6603 | I915_WRITE(GEN7_L3CNTLREG1, |
6604 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
6605 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
6606 | GEN7_WA_L3_CHICKEN_MODE); |
6607 | if (IS_IVB_GT1(dev)) | |
6608 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6609 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
6610 | else { |
6611 | /* must write both registers */ | |
6612 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6613 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
6614 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6615 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 6616 | } |
6f1d69b0 | 6617 | |
ecdb4eb7 | 6618 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
6619 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6620 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6621 | ||
1b80a19a | 6622 | /* |
0f846f81 | 6623 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6624 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
6625 | */ |
6626 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 6627 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6628 | |
ecdb4eb7 | 6629 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
6630 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6631 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6632 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6633 | ||
0e088b8f | 6634 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6635 | |
6636 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 6637 | |
22721343 CW |
6638 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6639 | /* enable HiZ Raw Stall Optimization */ | |
6640 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6641 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6642 | } | |
116f2b6d | 6643 | |
ecdb4eb7 | 6644 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
6645 | I915_WRITE(CACHE_MODE_1, |
6646 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 6647 | |
a607c1a4 VS |
6648 | /* |
6649 | * BSpec recommends 8x4 when MSAA is used, | |
6650 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6651 | * |
6652 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6653 | * disable bit, which we don't touch here, but it's good | |
6654 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
6655 | */ |
6656 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6657 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 6658 | |
20848223 BW |
6659 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6660 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
6661 | snpcr |= GEN6_MBC_SNPCR_MED; | |
6662 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 6663 | |
ab5c608b BW |
6664 | if (!HAS_PCH_NOP(dev)) |
6665 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
6666 | |
6667 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6668 | } |
6669 | ||
c6beb13e VS |
6670 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
6671 | { | |
6672 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6673 | ||
6674 | /* | |
6675 | * Disable trickle feed and enable pnd deadline calculation | |
6676 | */ | |
6677 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
6678 | I915_WRITE(CBR1_VLV, 0); | |
6679 | } | |
6680 | ||
1fa61106 | 6681 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6682 | { |
6683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6f1d69b0 | 6684 | |
c6beb13e | 6685 | vlv_init_display_clock_gating(dev_priv); |
6f1d69b0 | 6686 | |
ecdb4eb7 | 6687 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
6688 | I915_WRITE(_3D_CHICKEN3, |
6689 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6690 | ||
ecdb4eb7 | 6691 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
6692 | I915_WRITE(IVB_CHICKEN3, |
6693 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6694 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6695 | ||
fad7d36e | 6696 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 6697 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 6698 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
6699 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6700 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6701 | |
4e04632e AG |
6702 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6703 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6704 | ||
ecdb4eb7 | 6705 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
6706 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6707 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6708 | ||
ecdb4eb7 | 6709 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
6710 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6711 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6712 | ||
ecdb4eb7 | 6713 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
6714 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6715 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6716 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6717 | ||
46680e0a VS |
6718 | gen7_setup_fixed_func_scheduler(dev_priv); |
6719 | ||
3c0edaeb | 6720 | /* |
0f846f81 | 6721 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6722 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
6723 | */ |
6724 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 6725 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6726 | |
c98f5062 AG |
6727 | /* WaDisableL3Bank2xClockGate:vlv |
6728 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
6729 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6730 | I915_WRITE(GEN7_UCGCTL4, | |
6731 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 6732 | |
afd58e79 VS |
6733 | /* |
6734 | * BSpec says this must be set, even though | |
6735 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6736 | */ | |
6b26c86d DV |
6737 | I915_WRITE(CACHE_MODE_1, |
6738 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 6739 | |
da2518f9 VS |
6740 | /* |
6741 | * BSpec recommends 8x4 when MSAA is used, | |
6742 | * however in practice 16x4 seems fastest. | |
6743 | * | |
6744 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6745 | * disable bit, which we don't touch here, but it's good | |
6746 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6747 | */ | |
6748 | I915_WRITE(GEN7_GT_MODE, | |
6749 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6750 | ||
031994ee VS |
6751 | /* |
6752 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6753 | * This is the hardware default actually. | |
6754 | */ | |
6755 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6756 | ||
2d809570 | 6757 | /* |
ecdb4eb7 | 6758 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
6759 | * Disable clock gating on th GCFG unit to prevent a delay |
6760 | * in the reporting of vblank events. | |
6761 | */ | |
7a0d1eed | 6762 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
6763 | } |
6764 | ||
a4565da8 VS |
6765 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6766 | { | |
6767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6768 | ||
c6beb13e | 6769 | vlv_init_display_clock_gating(dev_priv); |
dd811e70 | 6770 | |
232ce337 VS |
6771 | /* WaVSRefCountFullforceMissDisable:chv */ |
6772 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6773 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6774 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6775 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
6776 | |
6777 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6778 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6779 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
6780 | |
6781 | /* WaDisableCSUnitClockGating:chv */ | |
6782 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6783 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
6784 | |
6785 | /* WaDisableSDEUnitClockGating:chv */ | |
6786 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6787 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6d50b065 VS |
6788 | |
6789 | /* | |
6790 | * GTT cache may not work with big pages, so if those | |
6791 | * are ever enabled GTT cache may need to be disabled. | |
6792 | */ | |
6793 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
a4565da8 VS |
6794 | } |
6795 | ||
1fa61106 | 6796 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6797 | { |
6798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6799 | uint32_t dspclk_gate; | |
6800 | ||
6801 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6802 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6803 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6804 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6805 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6806 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6807 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6808 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6809 | if (IS_GM45(dev)) | |
6810 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6811 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
6812 | |
6813 | /* WaDisableRenderCachePipelinedFlush */ | |
6814 | I915_WRITE(CACHE_MODE_0, | |
6815 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 6816 | |
4e04632e AG |
6817 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6818 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6819 | ||
0e088b8f | 6820 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6821 | } |
6822 | ||
1fa61106 | 6823 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6824 | { |
6825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6826 | ||
6827 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6828 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6829 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6830 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6831 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
6832 | I915_WRITE(MI_ARB_STATE, |
6833 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6834 | |
6835 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6836 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6837 | } |
6838 | ||
1fa61106 | 6839 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6840 | { |
6841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6842 | ||
6843 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6844 | I965_RCC_CLOCK_GATE_DISABLE | | |
6845 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6846 | I965_ISC_CLOCK_GATE_DISABLE | | |
6847 | I965_FBC_CLOCK_GATE_DISABLE); | |
6848 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
6849 | I915_WRITE(MI_ARB_STATE, |
6850 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6851 | |
6852 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6853 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6854 | } |
6855 | ||
1fa61106 | 6856 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6857 | { |
6858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6859 | u32 dstate = I915_READ(D_STATE); | |
6860 | ||
6861 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6862 | DSTATE_DOT_CLOCK_GATING; | |
6863 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
6864 | |
6865 | if (IS_PINEVIEW(dev)) | |
6866 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
6867 | |
6868 | /* IIR "flip pending" means done if this bit is set */ | |
6869 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
6870 | |
6871 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 6872 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
6873 | |
6874 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6875 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
6876 | |
6877 | I915_WRITE(MI_ARB_STATE, | |
6878 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6879 | } |
6880 | ||
1fa61106 | 6881 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6882 | { |
6883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6884 | ||
6885 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
6886 | |
6887 | /* interrupts should cause a wake up from C3 */ | |
6888 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
6889 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
6890 | |
6891 | I915_WRITE(MEM_MODE, | |
6892 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6893 | } |
6894 | ||
1fa61106 | 6895 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6896 | { |
6897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6898 | ||
6899 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
1038392b VS |
6900 | |
6901 | I915_WRITE(MEM_MODE, | |
6902 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
6903 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6904 | } |
6905 | ||
6f1d69b0 ED |
6906 | void intel_init_clock_gating(struct drm_device *dev) |
6907 | { | |
6908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6909 | ||
c57e3551 DL |
6910 | if (dev_priv->display.init_clock_gating) |
6911 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
6912 | } |
6913 | ||
7d708ee4 ID |
6914 | void intel_suspend_hw(struct drm_device *dev) |
6915 | { | |
6916 | if (HAS_PCH_LPT(dev)) | |
6917 | lpt_suspend_hw(dev); | |
6918 | } | |
6919 | ||
1fa61106 ED |
6920 | /* Set up chip specific power management-related functions */ |
6921 | void intel_init_pm(struct drm_device *dev) | |
6922 | { | |
6923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6924 | ||
7ff0ebcc | 6925 | intel_fbc_init(dev_priv); |
1fa61106 | 6926 | |
c921aba8 DV |
6927 | /* For cxsr */ |
6928 | if (IS_PINEVIEW(dev)) | |
6929 | i915_pineview_get_mem_freq(dev); | |
6930 | else if (IS_GEN5(dev)) | |
6931 | i915_ironlake_get_mem_freq(dev); | |
6932 | ||
1fa61106 | 6933 | /* For FIFO watermark updates */ |
f5ed50cb | 6934 | if (INTEL_INFO(dev)->gen >= 9) { |
2af30a5c PB |
6935 | skl_setup_wm_latency(dev); |
6936 | ||
a82abe43 ID |
6937 | if (IS_BROXTON(dev)) |
6938 | dev_priv->display.init_clock_gating = | |
6939 | bxt_init_clock_gating; | |
2d41c0b5 | 6940 | dev_priv->display.update_wm = skl_update_wm; |
c83155a6 | 6941 | } else if (HAS_PCH_SPLIT(dev)) { |
fa50ad61 | 6942 | ilk_setup_wm_latency(dev); |
53615a5e | 6943 | |
bd602544 VS |
6944 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
6945 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
6946 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
6947 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6948 | dev_priv->display.update_wm = ilk_update_wm; | |
86c8bbbe | 6949 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
bd602544 VS |
6950 | } else { |
6951 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6952 | "Disable CxSR\n"); | |
6953 | } | |
6954 | ||
6955 | if (IS_GEN5(dev)) | |
1fa61106 | 6956 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 6957 | else if (IS_GEN6(dev)) |
1fa61106 | 6958 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 6959 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 6960 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 6961 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 6962 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 6963 | else if (INTEL_INFO(dev)->gen == 8) |
47c2bd97 | 6964 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
a4565da8 | 6965 | } else if (IS_CHERRYVIEW(dev)) { |
262cd2e1 VS |
6966 | vlv_setup_wm_latency(dev); |
6967 | ||
6968 | dev_priv->display.update_wm = vlv_update_wm; | |
a4565da8 VS |
6969 | dev_priv->display.init_clock_gating = |
6970 | cherryview_init_clock_gating; | |
1fa61106 | 6971 | } else if (IS_VALLEYVIEW(dev)) { |
26e1fe4f VS |
6972 | vlv_setup_wm_latency(dev); |
6973 | ||
6974 | dev_priv->display.update_wm = vlv_update_wm; | |
1fa61106 ED |
6975 | dev_priv->display.init_clock_gating = |
6976 | valleyview_init_clock_gating; | |
1fa61106 ED |
6977 | } else if (IS_PINEVIEW(dev)) { |
6978 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6979 | dev_priv->is_ddr3, | |
6980 | dev_priv->fsb_freq, | |
6981 | dev_priv->mem_freq)) { | |
6982 | DRM_INFO("failed to find known CxSR latency " | |
6983 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6984 | "disabling CxSR\n", | |
6985 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6986 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6987 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 6988 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
6989 | dev_priv->display.update_wm = NULL; |
6990 | } else | |
6991 | dev_priv->display.update_wm = pineview_update_wm; | |
6992 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6993 | } else if (IS_G4X(dev)) { | |
6994 | dev_priv->display.update_wm = g4x_update_wm; | |
6995 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6996 | } else if (IS_GEN4(dev)) { | |
6997 | dev_priv->display.update_wm = i965_update_wm; | |
6998 | if (IS_CRESTLINE(dev)) | |
6999 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
7000 | else if (IS_BROADWATER(dev)) | |
7001 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
7002 | } else if (IS_GEN3(dev)) { | |
7003 | dev_priv->display.update_wm = i9xx_update_wm; | |
7004 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
7005 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
7006 | } else if (IS_GEN2(dev)) { |
7007 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
7008 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 7009 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
7010 | } else { |
7011 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 7012 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
7013 | } |
7014 | ||
7015 | if (IS_I85X(dev) || IS_I865G(dev)) | |
7016 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
7017 | else | |
7018 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
7019 | } else { | |
7020 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
7021 | } |
7022 | } | |
7023 | ||
151a49d0 | 7024 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 7025 | { |
4fc688ce | 7026 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
7027 | |
7028 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
7029 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
7030 | return -EAGAIN; | |
7031 | } | |
7032 | ||
7033 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
dddab346 | 7034 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
42c0526c BW |
7035 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
7036 | ||
7037 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7038 | 500)) { | |
7039 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
7040 | return -ETIMEDOUT; | |
7041 | } | |
7042 | ||
7043 | *val = I915_READ(GEN6_PCODE_DATA); | |
7044 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7045 | ||
7046 | return 0; | |
7047 | } | |
7048 | ||
151a49d0 | 7049 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
42c0526c | 7050 | { |
4fc688ce | 7051 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
7052 | |
7053 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
7054 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
7055 | return -EAGAIN; | |
7056 | } | |
7057 | ||
7058 | I915_WRITE(GEN6_PCODE_DATA, val); | |
7059 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
7060 | ||
7061 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7062 | 500)) { | |
7063 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
7064 | return -ETIMEDOUT; | |
7065 | } | |
7066 | ||
7067 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7068 | ||
7069 | return 0; | |
7070 | } | |
a0e4e199 | 7071 | |
dd06f88c | 7072 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
855ba3be | 7073 | { |
dd06f88c VS |
7074 | switch (czclk_freq) { |
7075 | case 200: | |
7076 | return 10; | |
7077 | case 267: | |
7078 | return 12; | |
7079 | case 320: | |
7080 | case 333: | |
dd06f88c | 7081 | return 16; |
ab3fb157 VS |
7082 | case 400: |
7083 | return 20; | |
855ba3be JB |
7084 | default: |
7085 | return -1; | |
7086 | } | |
dd06f88c | 7087 | } |
855ba3be | 7088 | |
dd06f88c VS |
7089 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
7090 | { | |
bfa7df01 | 7091 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
dd06f88c VS |
7092 | |
7093 | div = vlv_gpu_freq_div(czclk_freq); | |
7094 | if (div < 0) | |
7095 | return div; | |
7096 | ||
7097 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); | |
855ba3be JB |
7098 | } |
7099 | ||
b55dd647 | 7100 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 7101 | { |
bfa7df01 | 7102 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
855ba3be | 7103 | |
dd06f88c VS |
7104 | mul = vlv_gpu_freq_div(czclk_freq); |
7105 | if (mul < 0) | |
7106 | return mul; | |
855ba3be | 7107 | |
dd06f88c | 7108 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
855ba3be JB |
7109 | } |
7110 | ||
b55dd647 | 7111 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 7112 | { |
bfa7df01 | 7113 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
22b1b2f8 | 7114 | |
dd06f88c VS |
7115 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
7116 | if (div < 0) | |
7117 | return div; | |
22b1b2f8 | 7118 | |
dd06f88c | 7119 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
22b1b2f8 D |
7120 | } |
7121 | ||
b55dd647 | 7122 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 7123 | { |
bfa7df01 | 7124 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); |
22b1b2f8 | 7125 | |
dd06f88c VS |
7126 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
7127 | if (mul < 0) | |
7128 | return mul; | |
22b1b2f8 | 7129 | |
1c14762d | 7130 | /* CHV needs even values */ |
dd06f88c | 7131 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
22b1b2f8 D |
7132 | } |
7133 | ||
616bc820 | 7134 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 7135 | { |
80b6dda4 AG |
7136 | if (IS_GEN9(dev_priv->dev)) |
7137 | return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER; | |
7138 | else if (IS_CHERRYVIEW(dev_priv->dev)) | |
616bc820 | 7139 | return chv_gpu_freq(dev_priv, val); |
22b1b2f8 | 7140 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
7141 | return byt_gpu_freq(dev_priv, val); |
7142 | else | |
7143 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
7144 | } |
7145 | ||
616bc820 VS |
7146 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
7147 | { | |
80b6dda4 AG |
7148 | if (IS_GEN9(dev_priv->dev)) |
7149 | return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER; | |
7150 | else if (IS_CHERRYVIEW(dev_priv->dev)) | |
616bc820 | 7151 | return chv_freq_opcode(dev_priv, val); |
22b1b2f8 | 7152 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
7153 | return byt_freq_opcode(dev_priv, val); |
7154 | else | |
7155 | return val / GT_FREQUENCY_MULTIPLIER; | |
7156 | } | |
22b1b2f8 | 7157 | |
6ad790c0 CW |
7158 | struct request_boost { |
7159 | struct work_struct work; | |
eed29a5b | 7160 | struct drm_i915_gem_request *req; |
6ad790c0 CW |
7161 | }; |
7162 | ||
7163 | static void __intel_rps_boost_work(struct work_struct *work) | |
7164 | { | |
7165 | struct request_boost *boost = container_of(work, struct request_boost, work); | |
e61b9958 | 7166 | struct drm_i915_gem_request *req = boost->req; |
6ad790c0 | 7167 | |
e61b9958 CW |
7168 | if (!i915_gem_request_completed(req, true)) |
7169 | gen6_rps_boost(to_i915(req->ring->dev), NULL, | |
7170 | req->emitted_jiffies); | |
6ad790c0 | 7171 | |
e61b9958 | 7172 | i915_gem_request_unreference__unlocked(req); |
6ad790c0 CW |
7173 | kfree(boost); |
7174 | } | |
7175 | ||
7176 | void intel_queue_rps_boost_for_request(struct drm_device *dev, | |
eed29a5b | 7177 | struct drm_i915_gem_request *req) |
6ad790c0 CW |
7178 | { |
7179 | struct request_boost *boost; | |
7180 | ||
eed29a5b | 7181 | if (req == NULL || INTEL_INFO(dev)->gen < 6) |
6ad790c0 CW |
7182 | return; |
7183 | ||
e61b9958 CW |
7184 | if (i915_gem_request_completed(req, true)) |
7185 | return; | |
7186 | ||
6ad790c0 CW |
7187 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
7188 | if (boost == NULL) | |
7189 | return; | |
7190 | ||
eed29a5b DV |
7191 | i915_gem_request_reference(req); |
7192 | boost->req = req; | |
6ad790c0 CW |
7193 | |
7194 | INIT_WORK(&boost->work, __intel_rps_boost_work); | |
7195 | queue_work(to_i915(dev)->wq, &boost->work); | |
7196 | } | |
7197 | ||
f742a552 | 7198 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
7199 | { |
7200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7201 | ||
f742a552 | 7202 | mutex_init(&dev_priv->rps.hw_lock); |
8d3afd7d | 7203 | spin_lock_init(&dev_priv->rps.client_lock); |
f742a552 | 7204 | |
907b28c5 CW |
7205 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
7206 | intel_gen6_powersave_work); | |
1854d5ca | 7207 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
2e1b8730 CW |
7208 | INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); |
7209 | INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); | |
5d584b2e | 7210 | |
33688d95 | 7211 | dev_priv->pm.suspended = false; |
907b28c5 | 7212 | } |