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drm/i915: Pass dev_priv to IS_PINEVIEW()
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
b033bb6d 59static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 60{
32608ca2
ID		 61 struct drm_i915_private *dev_priv = dev->dev_private;
62
b033bb6d 63 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 64 I915_WRITE(CHICKEN_PAR1_1,
65 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
66
b033bb6d
MK		 67 I915_WRITE(GEN8_CONFIG0,
68 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 69
70 /* WaEnableChickenDCPR:skl,bxt,kbl */
71 I915_WRITE(GEN8_CHICKEN_DCPR_1,
72 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 73
74 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 75 /* WaFbcWakeMemOn:skl,bxt,kbl */
76 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
77 DISP_FBC_WM_DIS |
78 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 79
80 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
81 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
82 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 83}
84
85static void bxt_init_clock_gating(struct drm_device *dev)
86{
fac5e23e 87 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 88
89 gen9_init_clock_gating(dev);
90
a7546159
NH		 91 /* WaDisableSDEUnitClockGating:bxt */
92 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
93 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
94
32608ca2
ID		 95 /*
96 * FIXME:
868434c5 97 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 98 */
32608ca2 99 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 100 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 101
102 /*
103 * Wa: Backlight PWM may stop in the asserted state, causing backlight
104 * to stay fully on.
105 */
106 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
107 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
108 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 109}
110
c921aba8
DV		 111static void i915_pineview_get_mem_freq(struct drm_device *dev)
112{
fac5e23e 113 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 114 u32 tmp;
115
116 tmp = I915_READ(CLKCFG);
117
118 switch (tmp & CLKCFG_FSB_MASK) {
119 case CLKCFG_FSB_533:
120 dev_priv->fsb_freq = 533; /* 133*4 */
121 break;
122 case CLKCFG_FSB_800:
123 dev_priv->fsb_freq = 800; /* 200*4 */
124 break;
125 case CLKCFG_FSB_667:
126 dev_priv->fsb_freq = 667; /* 167*4 */
127 break;
128 case CLKCFG_FSB_400:
129 dev_priv->fsb_freq = 400; /* 100*4 */
130 break;
131 }
132
133 switch (tmp & CLKCFG_MEM_MASK) {
134 case CLKCFG_MEM_533:
135 dev_priv->mem_freq = 533;
136 break;
137 case CLKCFG_MEM_667:
138 dev_priv->mem_freq = 667;
139 break;
140 case CLKCFG_MEM_800:
141 dev_priv->mem_freq = 800;
142 break;
143 }
144
145 /* detect pineview DDR3 setting */
146 tmp = I915_READ(CSHRDDR3CTL);
147 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
148}
149
150static void i915_ironlake_get_mem_freq(struct drm_device *dev)
151{
fac5e23e 152 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 153 u16 ddrpll, csipll;
154
155 ddrpll = I915_READ16(DDRMPLL1);
156 csipll = I915_READ16(CSIPLL0);
157
158 switch (ddrpll & 0xff) {
159 case 0xc:
160 dev_priv->mem_freq = 800;
161 break;
162 case 0x10:
163 dev_priv->mem_freq = 1066;
164 break;
165 case 0x14:
166 dev_priv->mem_freq = 1333;
167 break;
168 case 0x18:
169 dev_priv->mem_freq = 1600;
170 break;
171 default:
172 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
173 ddrpll & 0xff);
174 dev_priv->mem_freq = 0;
175 break;
176 }
177
20e4d407 178 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 179
180 switch (csipll & 0x3ff) {
181 case 0x00c:
182 dev_priv->fsb_freq = 3200;
183 break;
184 case 0x00e:
185 dev_priv->fsb_freq = 3733;
186 break;
187 case 0x010:
188 dev_priv->fsb_freq = 4266;
189 break;
190 case 0x012:
191 dev_priv->fsb_freq = 4800;
192 break;
193 case 0x014:
194 dev_priv->fsb_freq = 5333;
195 break;
196 case 0x016:
197 dev_priv->fsb_freq = 5866;
198 break;
199 case 0x018:
200 dev_priv->fsb_freq = 6400;
201 break;
202 default:
203 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
204 csipll & 0x3ff);
205 dev_priv->fsb_freq = 0;
206 break;
207 }
208
209 if (dev_priv->fsb_freq == 3200) {
20e4d407 210 dev_priv->ips.c_m = 0;
c921aba8 211 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 212 dev_priv->ips.c_m = 1;
c921aba8 213 } else {
20e4d407 214 dev_priv->ips.c_m = 2;
c921aba8
DV		 215 }
216}
217
b445e3b0
ED		 218static const struct cxsr_latency cxsr_latency_table[] = {
219 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
220 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
221 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
222 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
223 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
224
225 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
226 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
227 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
228 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
229 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
230
231 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
232 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
233 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
234 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
235 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
236
237 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
238 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
239 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
240 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
241 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
242
243 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
244 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
245 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
246 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
247 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
248
249 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
250 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
251 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
252 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
253 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
254};
255
44a655ca
TU		 256static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
257 bool is_ddr3,
b445e3b0
ED		 258 int fsb,
259 int mem)
260{
261 const struct cxsr_latency *latency;
262 int i;
263
264 if (fsb == 0 || mem == 0)
265 return NULL;
266
267 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
268 latency = &cxsr_latency_table[i];
269 if (is_desktop == latency->is_desktop &&
270 is_ddr3 == latency->is_ddr3 &&
271 fsb == latency->fsb_freq && mem == latency->mem_freq)
272 return latency;
273 }
274
275 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
276
277 return NULL;
278}
279
fc1ac8de
VS		 280static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
281{
282 u32 val;
283
284 mutex_lock(&dev_priv->rps.hw_lock);
285
286 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
287 if (enable)
288 val &= ~FORCE_DDR_HIGH_FREQ;
289 else
290 val |= FORCE_DDR_HIGH_FREQ;
291 val &= ~FORCE_DDR_LOW_FREQ;
292 val |= FORCE_DDR_FREQ_REQ_ACK;
293 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
294
295 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
296 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
297 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
298
299 mutex_unlock(&dev_priv->rps.hw_lock);
300}
301
cfb41411
VS		 302static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
303{
304 u32 val;
305
306 mutex_lock(&dev_priv->rps.hw_lock);
307
308 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
309 if (enable)
310 val |= DSP_MAXFIFO_PM5_ENABLE;
311 else
312 val &= ~DSP_MAXFIFO_PM5_ENABLE;
313 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
314
315 mutex_unlock(&dev_priv->rps.hw_lock);
316}
317
f4998963
VS		 318#define FW_WM(value, plane) \
319 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
320
5209b1f4 321void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 322{
5209b1f4 323 u32 val;
b445e3b0 324
920a14b2 325 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 329 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
9b1e14f4 332 } else if (IS_PINEVIEW(dev_priv)) {
5209b1f4
ID		 333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
50a0bc90 337 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
50a0bc90 342 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
efc2611e 627static struct intel_crtc *single_enabled_crtc(struct drm_device *dev)
b445e3b0 628{
efc2611e 629 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 630
efc2611e
VS		 631 for_each_intel_crtc(dev, crtc) {
632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
432081bc 642static void pineview_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 643{
432081bc 644 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
efc2611e 646 struct intel_crtc *crtc;
b445e3b0
ED		 647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
50a0bc90
TU		 651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
652 dev_priv->is_ddr3,
653 dev_priv->fsb_freq,
654 dev_priv->mem_freq);
b445e3b0
ED		 655 if (!latency) {
656 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 657 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 658 return;
659 }
660
661 crtc = single_enabled_crtc(dev);
662 if (crtc) {
efc2611e
VS		 663 const struct drm_display_mode *adjusted_mode =
664 &crtc->config->base.adjusted_mode;
665 const struct drm_framebuffer *fb =
666 crtc->base.primary->state->fb;
667 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
7c5f93b0 668 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 669
670 /* Display SR */
671 wm = intel_calculate_wm(clock, &pineview_display_wm,
672 pineview_display_wm.fifo_size,
ac484963 673 cpp, latency->display_sr);
b445e3b0
ED		 674 reg = I915_READ(DSPFW1);
675 reg &= ~DSPFW_SR_MASK;
f4998963 676 reg |= FW_WM(wm, SR);
b445e3b0
ED		 677 I915_WRITE(DSPFW1, reg);
678 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
679
680 /* cursor SR */
681 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
682 pineview_display_wm.fifo_size,
ac484963 683 cpp, latency->cursor_sr);
b445e3b0
ED		 684 reg = I915_READ(DSPFW3);
685 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 686 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 687 I915_WRITE(DSPFW3, reg);
688
689 /* Display HPLL off SR */
690 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
691 pineview_display_hplloff_wm.fifo_size,
ac484963 692 cpp, latency->display_hpll_disable);
b445e3b0
ED		 693 reg = I915_READ(DSPFW3);
694 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 695 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 696 I915_WRITE(DSPFW3, reg);
697
698 /* cursor HPLL off SR */
699 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
700 pineview_display_hplloff_wm.fifo_size,
ac484963 701 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 702 reg = I915_READ(DSPFW3);
703 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 704 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 705 I915_WRITE(DSPFW3, reg);
706 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
707
5209b1f4 708 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 709 } else {
5209b1f4 710 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 711 }
712}
713
f0ce2310 714static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
b445e3b0
ED		 715 int plane,
716 const struct intel_watermark_params *display,
717 int display_latency_ns,
718 const struct intel_watermark_params *cursor,
719 int cursor_latency_ns,
720 int *plane_wm,
721 int *cursor_wm)
722{
efc2611e 723 struct intel_crtc *crtc;
4fe8590a 724 const struct drm_display_mode *adjusted_mode;
efc2611e 725 const struct drm_framebuffer *fb;
ac484963 726 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 727 int line_time_us, line_count;
728 int entries, tlb_miss;
729
b91eb5cc 730 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e 731 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 732 *cursor_wm = cursor->guard_size;
733 *plane_wm = display->guard_size;
734 return false;
735 }
736
efc2611e
VS		 737 adjusted_mode = &crtc->config->base.adjusted_mode;
738 fb = crtc->base.primary->state->fb;
241bfc38 739 clock = adjusted_mode->crtc_clock;
fec8cba3 740 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 741 hdisplay = crtc->config->pipe_src_w;
742 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 743
744 /* Use the small buffer method to calculate plane watermark */
ac484963 745 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 746 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
747 if (tlb_miss > 0)
748 entries += tlb_miss;
749 entries = DIV_ROUND_UP(entries, display->cacheline_size);
750 *plane_wm = entries + display->guard_size;
751 if (*plane_wm > (int)display->max_wm)
752 *plane_wm = display->max_wm;
753
754 /* Use the large buffer method to calculate cursor watermark */
922044c9 755 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 756 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
efc2611e 757 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
b445e3b0
ED		 758 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
759 if (tlb_miss > 0)
760 entries += tlb_miss;
761 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
762 *cursor_wm = entries + cursor->guard_size;
763 if (*cursor_wm > (int)cursor->max_wm)
764 *cursor_wm = (int)cursor->max_wm;
765
766 return true;
767}
768
769/*
770 * Check the wm result.
771 *
772 * If any calculated watermark values is larger than the maximum value that
773 * can be programmed into the associated watermark register, that watermark
774 * must be disabled.
775 */
f0ce2310 776static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 777 int display_wm, int cursor_wm,
778 const struct intel_watermark_params *display,
779 const struct intel_watermark_params *cursor)
780{
781 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
782 display_wm, cursor_wm);
783
784 if (display_wm > display->max_wm) {
ae9400ca 785 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 786 display_wm, display->max_wm);
787 return false;
788 }
789
790 if (cursor_wm > cursor->max_wm) {
ae9400ca 791 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 792 cursor_wm, cursor->max_wm);
793 return false;
794 }
795
796 if (!(display_wm || cursor_wm)) {
797 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
798 return false;
799 }
800
801 return true;
802}
803
f0ce2310 804static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 805 int plane,
806 int latency_ns,
807 const struct intel_watermark_params *display,
808 const struct intel_watermark_params *cursor,
809 int *display_wm, int *cursor_wm)
810{
efc2611e 811 struct intel_crtc *crtc;
4fe8590a 812 const struct drm_display_mode *adjusted_mode;
efc2611e 813 const struct drm_framebuffer *fb;
ac484963 814 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 815 unsigned long line_time_us;
816 int line_count, line_size;
817 int small, large;
818 int entries;
819
820 if (!latency_ns) {
821 *display_wm = *cursor_wm = 0;
822 return false;
823 }
824
b91eb5cc 825 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e
VS		 826 adjusted_mode = &crtc->config->base.adjusted_mode;
827 fb = crtc->base.primary->state->fb;
241bfc38 828 clock = adjusted_mode->crtc_clock;
fec8cba3 829 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 830 hdisplay = crtc->config->pipe_src_w;
831 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0 832
922044c9 833 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 834 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 835 line_size = hdisplay * cpp;
b445e3b0
ED		 836
837 /* Use the minimum of the small and large buffer method for primary */
ac484963 838 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 839 large = line_count * line_size;
840
841 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
842 *display_wm = entries + display->guard_size;
843
844 /* calculate the self-refresh watermark for display cursor */
efc2611e 845 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 846 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
847 *cursor_wm = entries + cursor->guard_size;
848
f0ce2310 849 return g4x_check_srwm(dev_priv,
b445e3b0
ED		 850 *display_wm, *cursor_wm,
851 display, cursor);
852}
853
15665979
VS		 854#define FW_WM_VLV(value, plane) \
855 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
856
0018fda1
VS		 857static void vlv_write_wm_values(struct intel_crtc *crtc,
858 const struct vlv_wm_values *wm)
859{
860 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
861 enum pipe pipe = crtc->pipe;
862
863 I915_WRITE(VLV_DDL(pipe),
864 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
865 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
866 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
867 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
868
ae80152d 869 I915_WRITE(DSPFW1,
15665979
VS		 870 FW_WM(wm->sr.plane, SR) |
871 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
872 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
873 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 874 I915_WRITE(DSPFW2,
15665979
VS		 875 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
876 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
877 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 878 I915_WRITE(DSPFW3,
15665979 879 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 880
881 if (IS_CHERRYVIEW(dev_priv)) {
882 I915_WRITE(DSPFW7_CHV,
15665979
VS		 883 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
884 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 885 I915_WRITE(DSPFW8_CHV,
15665979
VS		 886 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
887 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 888 I915_WRITE(DSPFW9_CHV,
15665979
VS		 889 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
890 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 891 I915_WRITE(DSPHOWM,
15665979
VS		 892 FW_WM(wm->sr.plane >> 9, SR_HI) |
893 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
894 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
895 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
896 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
897 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
898 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
899 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
900 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
901 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 902 } else {
903 I915_WRITE(DSPFW7,
15665979
VS		 904 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
905 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 906 I915_WRITE(DSPHOWM,
15665979
VS		 907 FW_WM(wm->sr.plane >> 9, SR_HI) |
908 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
909 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
910 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
911 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
912 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
913 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 914 }
915
2cb389b7
VS		 916 /* zero (unused) WM1 watermarks */
917 I915_WRITE(DSPFW4, 0);
918 I915_WRITE(DSPFW5, 0);
919 I915_WRITE(DSPFW6, 0);
920 I915_WRITE(DSPHOWM1, 0);
921
ae80152d 922 POSTING_READ(DSPFW1);
0018fda1
VS		 923}
924
15665979
VS		 925#undef FW_WM_VLV
926
6eb1a681
VS		 927enum vlv_wm_level {
928 VLV_WM_LEVEL_PM2,
929 VLV_WM_LEVEL_PM5,
930 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 931};
932
262cd2e1
VS		 933/* latency must be in 0.1us units. */
934static unsigned int vlv_wm_method2(unsigned int pixel_rate,
935 unsigned int pipe_htotal,
936 unsigned int horiz_pixels,
ac484963 937 unsigned int cpp,
262cd2e1
VS		 938 unsigned int latency)
939{
940 unsigned int ret;
941
942 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 943 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 944 ret = DIV_ROUND_UP(ret, 64);
945
946 return ret;
947}
948
949static void vlv_setup_wm_latency(struct drm_device *dev)
950{
fac5e23e 951 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 952
953 /* all latencies in usec */
954 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
955
58590c14
VS		 956 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
957
262cd2e1
VS		 958 if (IS_CHERRYVIEW(dev_priv)) {
959 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
960 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 961
962 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 963 }
964}
965
966static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
967 struct intel_crtc *crtc,
968 const struct intel_plane_state *state,
969 int level)
970{
971 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 972 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 973
974 if (dev_priv->wm.pri_latency[level] == 0)
975 return USHRT_MAX;
976
936e71e3 977 if (!state->base.visible)
262cd2e1
VS		 978 return 0;
979
ac484963 980 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 981 clock = crtc->config->base.adjusted_mode.crtc_clock;
982 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
983 width = crtc->config->pipe_src_w;
984 if (WARN_ON(htotal == 0))
985 htotal = 1;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 /*
989 * FIXME the formula gives values that are
990 * too big for the cursor FIFO, and hence we
991 * would never be able to use cursors. For
992 * now just hardcode the watermark.
993 */
994 wm = 63;
995 } else {
ac484963 996 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 997 dev_priv->wm.pri_latency[level] * 10);
998 }
999
1000 return min_t(int, wm, USHRT_MAX);
1001}
1002
54f1b6e1
VS		 1003static void vlv_compute_fifo(struct intel_crtc *crtc)
1004{
1005 struct drm_device *dev = crtc->base.dev;
1006 struct vlv_wm_state *wm_state = &crtc->wm_state;
1007 struct intel_plane *plane;
1008 unsigned int total_rate = 0;
1009 const int fifo_size = 512 - 1;
1010 int fifo_extra, fifo_left = fifo_size;
1011
1012 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1013 struct intel_plane_state *state =
1014 to_intel_plane_state(plane->base.state);
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017 continue;
1018
936e71e3 1019 if (state->base.visible) {
54f1b6e1
VS		 1020 wm_state->num_active_planes++;
1021 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1022 }
1023 }
1024
1025 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1026 struct intel_plane_state *state =
1027 to_intel_plane_state(plane->base.state);
1028 unsigned int rate;
1029
1030 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1031 plane->wm.fifo_size = 63;
1032 continue;
1033 }
1034
936e71e3 1035 if (!state->base.visible) {
54f1b6e1
VS		 1036 plane->wm.fifo_size = 0;
1037 continue;
1038 }
1039
1040 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041 plane->wm.fifo_size = fifo_size * rate / total_rate;
1042 fifo_left -= plane->wm.fifo_size;
1043 }
1044
1045 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1046
1047 /* spread the remainder evenly */
1048 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1049 int plane_extra;
1050
1051 if (fifo_left == 0)
1052 break;
1053
1054 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1055 continue;
1056
1057 /* give it all to the first plane if none are active */
1058 if (plane->wm.fifo_size == 0 &&
1059 wm_state->num_active_planes)
1060 continue;
1061
1062 plane_extra = min(fifo_extra, fifo_left);
1063 plane->wm.fifo_size += plane_extra;
1064 fifo_left -= plane_extra;
1065 }
1066
1067 WARN_ON(fifo_left != 0);
1068}
1069
262cd2e1
VS		 1070static void vlv_invert_wms(struct intel_crtc *crtc)
1071{
1072 struct vlv_wm_state *wm_state = &crtc->wm_state;
1073 int level;
1074
1075 for (level = 0; level < wm_state->num_levels; level++) {
1076 struct drm_device *dev = crtc->base.dev;
1077 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1078 struct intel_plane *plane;
1079
1080 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1081 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1082
1083 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1084 switch (plane->base.type) {
1085 int sprite;
1086 case DRM_PLANE_TYPE_CURSOR:
1087 wm_state->wm[level].cursor = plane->wm.fifo_size -
1088 wm_state->wm[level].cursor;
1089 break;
1090 case DRM_PLANE_TYPE_PRIMARY:
1091 wm_state->wm[level].primary = plane->wm.fifo_size -
1092 wm_state->wm[level].primary;
1093 break;
1094 case DRM_PLANE_TYPE_OVERLAY:
1095 sprite = plane->plane;
1096 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1097 wm_state->wm[level].sprite[sprite];
1098 break;
1099 }
1100 }
1101 }
1102}
1103
26e1fe4f 1104static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1105{
1106 struct drm_device *dev = crtc->base.dev;
1107 struct vlv_wm_state *wm_state = &crtc->wm_state;
1108 struct intel_plane *plane;
1109 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1110 int level;
1111
1112 memset(wm_state, 0, sizeof(*wm_state));
1113
852eb00d 1114 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1115 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1116
1117 wm_state->num_active_planes = 0;
262cd2e1 1118
54f1b6e1 1119 vlv_compute_fifo(crtc);
262cd2e1
VS		 1120
1121 if (wm_state->num_active_planes != 1)
1122 wm_state->cxsr = false;
1123
1124 if (wm_state->cxsr) {
1125 for (level = 0; level < wm_state->num_levels; level++) {
1126 wm_state->sr[level].plane = sr_fifo_size;
1127 wm_state->sr[level].cursor = 63;
1128 }
1129 }
1130
1131 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1132 struct intel_plane_state *state =
1133 to_intel_plane_state(plane->base.state);
1134
936e71e3 1135 if (!state->base.visible)
262cd2e1
VS		 1136 continue;
1137
1138 /* normal watermarks */
1139 for (level = 0; level < wm_state->num_levels; level++) {
1140 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1141 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1142
1143 /* hack */
1144 if (WARN_ON(level == 0 && wm > max_wm))
1145 wm = max_wm;
1146
1147 if (wm > plane->wm.fifo_size)
1148 break;
1149
1150 switch (plane->base.type) {
1151 int sprite;
1152 case DRM_PLANE_TYPE_CURSOR:
1153 wm_state->wm[level].cursor = wm;
1154 break;
1155 case DRM_PLANE_TYPE_PRIMARY:
1156 wm_state->wm[level].primary = wm;
1157 break;
1158 case DRM_PLANE_TYPE_OVERLAY:
1159 sprite = plane->plane;
1160 wm_state->wm[level].sprite[sprite] = wm;
1161 break;
1162 }
1163 }
1164
1165 wm_state->num_levels = level;
1166
1167 if (!wm_state->cxsr)
1168 continue;
1169
1170 /* maxfifo watermarks */
1171 switch (plane->base.type) {
1172 int sprite, level;
1173 case DRM_PLANE_TYPE_CURSOR:
1174 for (level = 0; level < wm_state->num_levels; level++)
1175 wm_state->sr[level].cursor =
5a37ed0a 1176 wm_state->wm[level].cursor;
262cd2e1
VS		 1177 break;
1178 case DRM_PLANE_TYPE_PRIMARY:
1179 for (level = 0; level < wm_state->num_levels; level++)
1180 wm_state->sr[level].plane =
1181 min(wm_state->sr[level].plane,
1182 wm_state->wm[level].primary);
1183 break;
1184 case DRM_PLANE_TYPE_OVERLAY:
1185 sprite = plane->plane;
1186 for (level = 0; level < wm_state->num_levels; level++)
1187 wm_state->sr[level].plane =
1188 min(wm_state->sr[level].plane,
1189 wm_state->wm[level].sprite[sprite]);
1190 break;
1191 }
1192 }
1193
1194 /* clear any (partially) filled invalid levels */
58590c14 1195 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1196 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1197 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1198 }
1199
1200 vlv_invert_wms(crtc);
1201}
1202
54f1b6e1
VS		 1203#define VLV_FIFO(plane, value) \
1204 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1205
1206static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1207{
1208 struct drm_device *dev = crtc->base.dev;
1209 struct drm_i915_private *dev_priv = to_i915(dev);
1210 struct intel_plane *plane;
1211 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1212
1213 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1214 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1215 WARN_ON(plane->wm.fifo_size != 63);
1216 continue;
1217 }
1218
1219 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1220 sprite0_start = plane->wm.fifo_size;
1221 else if (plane->plane == 0)
1222 sprite1_start = sprite0_start + plane->wm.fifo_size;
1223 else
1224 fifo_size = sprite1_start + plane->wm.fifo_size;
1225 }
1226
1227 WARN_ON(fifo_size != 512 - 1);
1228
1229 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1230 pipe_name(crtc->pipe), sprite0_start,
1231 sprite1_start, fifo_size);
1232
1233 switch (crtc->pipe) {
1234 uint32_t dsparb, dsparb2, dsparb3;
1235 case PIPE_A:
1236 dsparb = I915_READ(DSPARB);
1237 dsparb2 = I915_READ(DSPARB2);
1238
1239 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1240 VLV_FIFO(SPRITEB, 0xff));
1241 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1242 VLV_FIFO(SPRITEB, sprite1_start));
1243
1244 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1245 VLV_FIFO(SPRITEB_HI, 0x1));
1246 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1247 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1248
1249 I915_WRITE(DSPARB, dsparb);
1250 I915_WRITE(DSPARB2, dsparb2);
1251 break;
1252 case PIPE_B:
1253 dsparb = I915_READ(DSPARB);
1254 dsparb2 = I915_READ(DSPARB2);
1255
1256 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1257 VLV_FIFO(SPRITED, 0xff));
1258 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1259 VLV_FIFO(SPRITED, sprite1_start));
1260
1261 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1262 VLV_FIFO(SPRITED_HI, 0xff));
1263 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1264 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1265
1266 I915_WRITE(DSPARB, dsparb);
1267 I915_WRITE(DSPARB2, dsparb2);
1268 break;
1269 case PIPE_C:
1270 dsparb3 = I915_READ(DSPARB3);
1271 dsparb2 = I915_READ(DSPARB2);
1272
1273 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1274 VLV_FIFO(SPRITEF, 0xff));
1275 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1276 VLV_FIFO(SPRITEF, sprite1_start));
1277
1278 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1279 VLV_FIFO(SPRITEF_HI, 0xff));
1280 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1281 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1282
1283 I915_WRITE(DSPARB3, dsparb3);
1284 I915_WRITE(DSPARB2, dsparb2);
1285 break;
1286 default:
1287 break;
1288 }
1289}
1290
1291#undef VLV_FIFO
1292
262cd2e1
VS		 1293static void vlv_merge_wm(struct drm_device *dev,
1294 struct vlv_wm_values *wm)
1295{
1296 struct intel_crtc *crtc;
1297 int num_active_crtcs = 0;
1298
58590c14 1299 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1300 wm->cxsr = true;
1301
1302 for_each_intel_crtc(dev, crtc) {
1303 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1304
1305 if (!crtc->active)
1306 continue;
1307
1308 if (!wm_state->cxsr)
1309 wm->cxsr = false;
1310
1311 num_active_crtcs++;
1312 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1313 }
1314
1315 if (num_active_crtcs != 1)
1316 wm->cxsr = false;
1317
6f9c784b
VS		 1318 if (num_active_crtcs > 1)
1319 wm->level = VLV_WM_LEVEL_PM2;
1320
262cd2e1
VS		 1321 for_each_intel_crtc(dev, crtc) {
1322 struct vlv_wm_state *wm_state = &crtc->wm_state;
1323 enum pipe pipe = crtc->pipe;
1324
1325 if (!crtc->active)
1326 continue;
1327
1328 wm->pipe[pipe] = wm_state->wm[wm->level];
1329 if (wm->cxsr)
1330 wm->sr = wm_state->sr[wm->level];
1331
1332 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1333 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1334 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1335 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1336 }
1337}
1338
432081bc 1339static void vlv_update_wm(struct intel_crtc *crtc)
262cd2e1 1340{
432081bc 1341 struct drm_device *dev = crtc->base.dev;
fac5e23e 1342 struct drm_i915_private *dev_priv = to_i915(dev);
432081bc 1343 enum pipe pipe = crtc->pipe;
262cd2e1
VS		 1344 struct vlv_wm_values wm = {};
1345
432081bc 1346 vlv_compute_wm(crtc);
262cd2e1
VS		 1347 vlv_merge_wm(dev, &wm);
1348
54f1b6e1
VS		 1349 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1350 /* FIXME should be part of crtc atomic commit */
432081bc 1351 vlv_pipe_set_fifo_size(crtc);
262cd2e1 1352 return;
54f1b6e1 1353 }
262cd2e1
VS		 1354
1355 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1356 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1357 chv_set_memory_dvfs(dev_priv, false);
1358
1359 if (wm.level < VLV_WM_LEVEL_PM5 &&
1360 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1361 chv_set_memory_pm5(dev_priv, false);
1362
852eb00d 1363 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1364 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1365
54f1b6e1 1366 /* FIXME should be part of crtc atomic commit */
432081bc 1367 vlv_pipe_set_fifo_size(crtc);
54f1b6e1 1368
432081bc 1369 vlv_write_wm_values(crtc, &wm);
262cd2e1
VS		 1370
1371 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1372 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1373 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1374 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1375 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1376
852eb00d 1377 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1378 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1379
1380 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1381 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1382 chv_set_memory_pm5(dev_priv, true);
1383
1384 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1385 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1386 chv_set_memory_dvfs(dev_priv, true);
1387
1388 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1389}
1390
ae80152d
VS		 1391#define single_plane_enabled(mask) is_power_of_2(mask)
1392
432081bc 1393static void g4x_update_wm(struct intel_crtc *crtc)
b445e3b0 1394{
b91eb5cc 1395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0 1396 static const int sr_latency_ns = 12000;
b445e3b0
ED		 1397 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1398 int plane_sr, cursor_sr;
1399 unsigned int enabled = 0;
9858425c 1400 bool cxsr_enabled;
b445e3b0 1401
f0ce2310 1402 if (g4x_compute_wm0(dev_priv, PIPE_A,
5aef6003
CW		 1403 &g4x_wm_info, pessimal_latency_ns,
1404 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1405 &planea_wm, &cursora_wm))
51cea1f4 1406 enabled |= 1 << PIPE_A;
b445e3b0 1407
f0ce2310 1408 if (g4x_compute_wm0(dev_priv, PIPE_B,
5aef6003
CW		 1409 &g4x_wm_info, pessimal_latency_ns,
1410 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1411 &planeb_wm, &cursorb_wm))
51cea1f4 1412 enabled |= 1 << PIPE_B;
b445e3b0 1413
b445e3b0 1414 if (single_plane_enabled(enabled) &&
f0ce2310 1415 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
b445e3b0
ED		 1416 sr_latency_ns,
1417 &g4x_wm_info,
1418 &g4x_cursor_wm_info,
52bd02d8 1419 &plane_sr, &cursor_sr)) {
9858425c 1420 cxsr_enabled = true;
52bd02d8 1421 } else {
9858425c 1422 cxsr_enabled = false;
5209b1f4 1423 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1424 plane_sr = cursor_sr = 0;
1425 }
b445e3b0 1426
a5043453
VS		 1427 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1428 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1429 planea_wm, cursora_wm,
1430 planeb_wm, cursorb_wm,
1431 plane_sr, cursor_sr);
1432
1433 I915_WRITE(DSPFW1,
f4998963
VS		 1434 FW_WM(plane_sr, SR) |
1435 FW_WM(cursorb_wm, CURSORB) |
1436 FW_WM(planeb_wm, PLANEB) |
1437 FW_WM(planea_wm, PLANEA));
b445e3b0 1438 I915_WRITE(DSPFW2,
8c919b28 1439 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1440 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1441 /* HPLL off in SR has some issues on G4x... disable it */
1442 I915_WRITE(DSPFW3,
8c919b28 1443 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1444 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1445
1446 if (cxsr_enabled)
1447 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1448}
1449
432081bc 1450static void i965_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1451{
432081bc 1452 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1453 struct drm_i915_private *dev_priv = to_i915(dev);
efc2611e 1454 struct intel_crtc *crtc;
b445e3b0
ED		 1455 int srwm = 1;
1456 int cursor_sr = 16;
9858425c 1457 bool cxsr_enabled;
b445e3b0
ED		 1458
1459 /* Calc sr entries for one plane configs */
1460 crtc = single_enabled_crtc(dev);
1461 if (crtc) {
1462 /* self-refresh has much higher latency */
1463 static const int sr_latency_ns = 12000;
efc2611e
VS		 1464 const struct drm_display_mode *adjusted_mode =
1465 &crtc->config->base.adjusted_mode;
1466 const struct drm_framebuffer *fb =
1467 crtc->base.primary->state->fb;
241bfc38 1468 int clock = adjusted_mode->crtc_clock;
fec8cba3 1469 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1470 int hdisplay = crtc->config->pipe_src_w;
1471 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 1472 unsigned long line_time_us;
1473 int entries;
1474
922044c9 1475 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1476
1477 /* Use ns/us then divide to preserve precision */
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * hdisplay;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1481 srwm = I965_FIFO_SIZE - entries;
1482 if (srwm < 0)
1483 srwm = 1;
1484 srwm &= 0x1ff;
1485 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1486 entries, srwm);
1487
1488 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
efc2611e 1489 cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 1490 entries = DIV_ROUND_UP(entries,
1491 i965_cursor_wm_info.cacheline_size);
1492 cursor_sr = i965_cursor_wm_info.fifo_size -
1493 (entries + i965_cursor_wm_info.guard_size);
1494
1495 if (cursor_sr > i965_cursor_wm_info.max_wm)
1496 cursor_sr = i965_cursor_wm_info.max_wm;
1497
1498 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499 "cursor %d\n", srwm, cursor_sr);
1500
9858425c 1501 cxsr_enabled = true;
b445e3b0 1502 } else {
9858425c 1503 cxsr_enabled = false;
b445e3b0 1504 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1505 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1506 }
1507
1508 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1509 srwm);
1510
1511 /* 965 has limitations... */
f4998963
VS		 1512 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1513 FW_WM(8, CURSORB) |
1514 FW_WM(8, PLANEB) |
1515 FW_WM(8, PLANEA));
1516 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1517 FW_WM(8, PLANEC_OLD));
b445e3b0 1518 /* update cursor SR watermark */
f4998963 1519 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1520
1521 if (cxsr_enabled)
1522 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1523}
1524
f4998963
VS		 1525#undef FW_WM
1526
432081bc 1527static void i9xx_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1528{
432081bc 1529 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1530 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1531 const struct intel_watermark_params *wm_info;
1532 uint32_t fwater_lo;
1533 uint32_t fwater_hi;
1534 int cwm, srwm = 1;
1535 int fifo_size;
1536 int planea_wm, planeb_wm;
efc2611e 1537 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0
ED		 1538
1539 if (IS_I945GM(dev))
1540 wm_info = &i945_wm_info;
5db94019 1541 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1542 wm_info = &i915_wm_info;
1543 else
9d539105 1544 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1545
1546 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
b91eb5cc 1547 crtc = intel_get_crtc_for_plane(dev_priv, 0);
efc2611e
VS		 1548 if (intel_crtc_active(crtc)) {
1549 const struct drm_display_mode *adjusted_mode =
1550 &crtc->config->base.adjusted_mode;
1551 const struct drm_framebuffer *fb =
1552 crtc->base.primary->state->fb;
1553 int cpp;
1554
5db94019 1555 if (IS_GEN2(dev_priv))
b9e0bda3 1556 cpp = 4;
efc2611e
VS		 1557 else
1558 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1559
241bfc38 1560 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1561 wm_info, fifo_size, cpp,
5aef6003 1562 pessimal_latency_ns);
b445e3b0 1563 enabled = crtc;
9d539105 1564 } else {
b445e3b0 1565 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1566 if (planea_wm > (long)wm_info->max_wm)
1567 planea_wm = wm_info->max_wm;
1568 }
1569
5db94019 1570 if (IS_GEN2(dev_priv))
9d539105 1571 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1572
1573 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
b91eb5cc 1574 crtc = intel_get_crtc_for_plane(dev_priv, 1);
efc2611e
VS		 1575 if (intel_crtc_active(crtc)) {
1576 const struct drm_display_mode *adjusted_mode =
1577 &crtc->config->base.adjusted_mode;
1578 const struct drm_framebuffer *fb =
1579 crtc->base.primary->state->fb;
1580 int cpp;
1581
5db94019 1582 if (IS_GEN2(dev_priv))
b9e0bda3 1583 cpp = 4;
efc2611e
VS		 1584 else
1585 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1586
241bfc38 1587 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1588 wm_info, fifo_size, cpp,
5aef6003 1589 pessimal_latency_ns);
b445e3b0
ED		 1590 if (enabled == NULL)
1591 enabled = crtc;
1592 else
1593 enabled = NULL;
9d539105 1594 } else {
b445e3b0 1595 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1596 if (planeb_wm > (long)wm_info->max_wm)
1597 planeb_wm = wm_info->max_wm;
1598 }
b445e3b0
ED		 1599
1600 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1601
50a0bc90 1602 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1603 struct drm_i915_gem_object *obj;
2ab1bc9d 1604
efc2611e 1605 obj = intel_fb_obj(enabled->base.primary->state->fb);
2ab1bc9d
DV		 1606
1607 /* self-refresh seems busted with untiled */
3e510a8e 1608 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1609 enabled = NULL;
1610 }
1611
b445e3b0
ED		 1612 /*
1613 * Overlay gets an aggressive default since video jitter is bad.
1614 */
1615 cwm = 2;
1616
1617 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1618 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1619
1620 /* Calc sr entries for one plane configs */
1621 if (HAS_FW_BLC(dev) && enabled) {
1622 /* self-refresh has much higher latency */
1623 static const int sr_latency_ns = 6000;
efc2611e
VS		 1624 const struct drm_display_mode *adjusted_mode =
1625 &enabled->config->base.adjusted_mode;
1626 const struct drm_framebuffer *fb =
1627 enabled->base.primary->state->fb;
241bfc38 1628 int clock = adjusted_mode->crtc_clock;
fec8cba3 1629 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1630 int hdisplay = enabled->config->pipe_src_w;
1631 int cpp;
b445e3b0
ED		 1632 unsigned long line_time_us;
1633 int entries;
1634
50a0bc90 1635 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056 1636 cpp = 4;
efc2611e
VS		 1637 else
1638 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2d1b5056 1639
922044c9 1640 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1644 cpp * hdisplay;
b445e3b0
ED		 1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
50a0bc90 1651 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1654 else
b445e3b0
ED		 1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
5209b1f4
ID		 1671 if (enabled)
1672 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1673}
1674
432081bc 1675static void i845_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1676{
432081bc 1677 struct drm_device *dev = unused_crtc->base.dev;
fac5e23e 1678 struct drm_i915_private *dev_priv = to_i915(dev);
efc2611e 1679 struct intel_crtc *crtc;
241bfc38 1680 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1681 uint32_t fwater_lo;
1682 int planea_wm;
1683
1684 crtc = single_enabled_crtc(dev);
1685 if (crtc == NULL)
1686 return;
1687
efc2611e 1688 adjusted_mode = &crtc->config->base.adjusted_mode;
241bfc38 1689 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1690 &i845_wm_info,
b445e3b0 1691 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1692 4, pessimal_latency_ns);
b445e3b0
ED		 1693 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1694 fwater_lo |= (3<<8) | planea_wm;
1695
1696 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1697
1698 I915_WRITE(FW_BLC, fwater_lo);
1699}
1700
8cfb3407 1701uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1702{
fd4daa9c 1703 uint32_t pixel_rate;
801bcfff 1704
8cfb3407 1705 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1706
1707 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1708 * adjust the pixel_rate here. */
1709
8cfb3407 1710 if (pipe_config->pch_pfit.enabled) {
801bcfff 1711 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1712 uint32_t pfit_size = pipe_config->pch_pfit.size;
1713
1714 pipe_w = pipe_config->pipe_src_w;
1715 pipe_h = pipe_config->pipe_src_h;
801bcfff 1716
801bcfff
PZ		 1717 pfit_w = (pfit_size >> 16) & 0xFFFF;
1718 pfit_h = pfit_size & 0xFFFF;
1719 if (pipe_w < pfit_w)
1720 pipe_w = pfit_w;
1721 if (pipe_h < pfit_h)
1722 pipe_h = pfit_h;
1723
15126882
MR		 1724 if (WARN_ON(!pfit_w || !pfit_h))
1725 return pixel_rate;
1726
801bcfff
PZ		 1727 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1728 pfit_w * pfit_h);
1729 }
1730
1731 return pixel_rate;
1732}
1733
37126462 1734/* latency must be in 0.1us units. */
ac484963 1735static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1736{
1737 uint64_t ret;
1738
3312ba65
VS		 1739 if (WARN(latency == 0, "Latency value missing\n"))
1740 return UINT_MAX;
1741
ac484963 1742 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1743 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1744
1745 return ret;
1746}
1747
37126462 1748/* latency must be in 0.1us units. */
23297044 1749static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1750 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1751 uint32_t latency)
1752{
1753 uint32_t ret;
1754
3312ba65
VS		 1755 if (WARN(latency == 0, "Latency value missing\n"))
1756 return UINT_MAX;
15126882
MR		 1757 if (WARN_ON(!pipe_htotal))
1758 return UINT_MAX;
3312ba65 1759
801bcfff 1760 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1761 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1762 ret = DIV_ROUND_UP(ret, 64) + 2;
1763 return ret;
1764}
1765
23297044 1766static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1767 uint8_t cpp)
cca32e9a 1768{
15126882
MR		 1769 /*
1770 * Neither of these should be possible since this function shouldn't be
1771 * called if the CRTC is off or the plane is invisible. But let's be
1772 * extra paranoid to avoid a potential divide-by-zero if we screw up
1773 * elsewhere in the driver.
1774 */
ac484963 1775 if (WARN_ON(!cpp))
15126882
MR		 1776 return 0;
1777 if (WARN_ON(!horiz_pixels))
1778 return 0;
1779
ac484963 1780 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1781}
1782
820c1980 1783struct ilk_wm_maximums {
cca32e9a
PZ		 1784 uint16_t pri;
1785 uint16_t spr;
1786 uint16_t cur;
1787 uint16_t fbc;
1788};
1789
37126462
VS		 1790/*
1791 * For both WM_PIPE and WM_LP.
1792 * mem_value must be in 0.1us units.
1793 */
7221fc33 1794static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1795 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1796 uint32_t mem_value,
1797 bool is_lp)
801bcfff 1798{
ac484963
VS		 1799 int cpp = pstate->base.fb ?
1800 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1801 uint32_t method1, method2;
1802
936e71e3 1803 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1804 return 0;
1805
ac484963 1806 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1807
1808 if (!is_lp)
1809 return method1;
1810
7221fc33
MR		 1811 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1812 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1813 drm_rect_width(&pstate->base.dst),
ac484963 1814 cpp, mem_value);
cca32e9a
PZ		 1815
1816 return min(method1, method2);
801bcfff
PZ		 1817}
1818
37126462
VS		 1819/*
1820 * For both WM_PIPE and WM_LP.
1821 * mem_value must be in 0.1us units.
1822 */
7221fc33 1823static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1824 const struct intel_plane_state *pstate,
801bcfff
PZ		 1825 uint32_t mem_value)
1826{
ac484963
VS		 1827 int cpp = pstate->base.fb ?
1828 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1829 uint32_t method1, method2;
1830
936e71e3 1831 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1832 return 0;
1833
ac484963 1834 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1835 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1836 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1837 drm_rect_width(&pstate->base.dst),
ac484963 1838 cpp, mem_value);
801bcfff
PZ		 1839 return min(method1, method2);
1840}
1841
37126462
VS		 1842/*
1843 * For both WM_PIPE and WM_LP.
1844 * mem_value must be in 0.1us units.
1845 */
7221fc33 1846static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1847 const struct intel_plane_state *pstate,
801bcfff
PZ		 1848 uint32_t mem_value)
1849{
b2435692
MR		 1850 /*
1851 * We treat the cursor plane as always-on for the purposes of watermark
1852 * calculation. Until we have two-stage watermark programming merged,
1853 * this is necessary to avoid flickering.
1854 */
1855 int cpp = 4;
936e71e3 1856 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1857
b2435692 1858 if (!cstate->base.active)
801bcfff
PZ		 1859 return 0;
1860
7221fc33
MR		 1861 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1862 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1863 width, cpp, mem_value);
801bcfff
PZ		 1864}
1865
cca32e9a 1866/* Only for WM_LP. */
7221fc33 1867static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1868 const struct intel_plane_state *pstate,
1fda9882 1869 uint32_t pri_val)
cca32e9a 1870{
ac484963
VS		 1871 int cpp = pstate->base.fb ?
1872 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1873
936e71e3 1874 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1875 return 0;
1876
936e71e3 1877 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1878}
1879
158ae64f
VS		 1880static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1881{
416f4727
VS		 1882 if (INTEL_INFO(dev)->gen >= 8)
1883 return 3072;
1884 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1885 return 768;
1886 else
1887 return 512;
1888}
1889
4e975081
VS		 1890static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1891 int level, bool is_sprite)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 /* BDW primary/sprite plane watermarks */
1895 return level == 0 ? 255 : 2047;
1896 else if (INTEL_INFO(dev)->gen >= 7)
1897 /* IVB/HSW primary/sprite plane watermarks */
1898 return level == 0 ? 127 : 1023;
1899 else if (!is_sprite)
1900 /* ILK/SNB primary plane watermarks */
1901 return level == 0 ? 127 : 511;
1902 else
1903 /* ILK/SNB sprite plane watermarks */
1904 return level == 0 ? 63 : 255;
1905}
1906
1907static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1908 int level)
1909{
1910 if (INTEL_INFO(dev)->gen >= 7)
1911 return level == 0 ? 63 : 255;
1912 else
1913 return level == 0 ? 31 : 63;
1914}
1915
1916static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1917{
1918 if (INTEL_INFO(dev)->gen >= 8)
1919 return 31;
1920 else
1921 return 15;
1922}
1923
158ae64f
VS		 1924/* Calculate the maximum primary/sprite plane watermark */
1925static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1926 int level,
240264f4 1927 const struct intel_wm_config *config,
158ae64f
VS		 1928 enum intel_ddb_partitioning ddb_partitioning,
1929 bool is_sprite)
1930{
1931 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1932
1933 /* if sprites aren't enabled, sprites get nothing */
240264f4 1934 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1935 return 0;
1936
1937 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1938 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1939 fifo_size /= INTEL_INFO(dev)->num_pipes;
1940
1941 /*
1942 * For some reason the non self refresh
1943 * FIFO size is only half of the self
1944 * refresh FIFO size on ILK/SNB.
1945 */
1946 if (INTEL_INFO(dev)->gen <= 6)
1947 fifo_size /= 2;
1948 }
1949
240264f4 1950 if (config->sprites_enabled) {
158ae64f
VS		 1951 /* level 0 is always calculated with 1:1 split */
1952 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1953 if (is_sprite)
1954 fifo_size *= 5;
1955 fifo_size /= 6;
1956 } else {
1957 fifo_size /= 2;
1958 }
1959 }
1960
1961 /* clamp to max that the registers can hold */
4e975081 1962 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1963}
1964
1965/* Calculate the maximum cursor plane watermark */
1966static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1967 int level,
1968 const struct intel_wm_config *config)
158ae64f
VS		 1969{
1970 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1971 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1972 return 64;
1973
1974 /* otherwise just report max that registers can hold */
4e975081 1975 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1976}
1977
d34ff9c6 1978static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1979 int level,
1980 const struct intel_wm_config *config,
1981 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1982 struct ilk_wm_maximums *max)
158ae64f 1983{
240264f4
VS		 1984 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1985 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1986 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1987 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1988}
1989
a3cb4048
VS		 1990static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1991 int level,
1992 struct ilk_wm_maximums *max)
1993{
1994 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1995 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1996 max->cur = ilk_cursor_wm_reg_max(dev, level);
1997 max->fbc = ilk_fbc_wm_reg_max(dev);
1998}
1999
d9395655 2000static bool ilk_validate_wm_level(int level,
820c1980 2001 const struct ilk_wm_maximums *max,
d9395655 2002 struct intel_wm_level *result)
a9786a11
VS		 2003{
2004 bool ret;
2005
2006 /* already determined to be invalid? */
2007 if (!result->enable)
2008 return false;
2009
2010 result->enable = result->pri_val <= max->pri &&
2011 result->spr_val <= max->spr &&
2012 result->cur_val <= max->cur;
2013
2014 ret = result->enable;
2015
2016 /*
2017 * HACK until we can pre-compute everything,
2018 * and thus fail gracefully if LP0 watermarks
2019 * are exceeded...
2020 */
2021 if (level == 0 && !result->enable) {
2022 if (result->pri_val > max->pri)
2023 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2024 level, result->pri_val, max->pri);
2025 if (result->spr_val > max->spr)
2026 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2027 level, result->spr_val, max->spr);
2028 if (result->cur_val > max->cur)
2029 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2030 level, result->cur_val, max->cur);
2031
2032 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2033 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2034 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2035 result->enable = true;
2036 }
2037
a9786a11
VS		 2038 return ret;
2039}
2040
d34ff9c6 2041static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2042 const struct intel_crtc *intel_crtc,
6f5ddd17 2043 int level,
7221fc33 2044 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2045 struct intel_plane_state *pristate,
2046 struct intel_plane_state *sprstate,
2047 struct intel_plane_state *curstate,
1fd527cc 2048 struct intel_wm_level *result)
6f5ddd17
VS		 2049{
2050 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2051 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2052 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2053
2054 /* WM1+ latency values stored in 0.5us units */
2055 if (level > 0) {
2056 pri_latency *= 5;
2057 spr_latency *= 5;
2058 cur_latency *= 5;
2059 }
2060
e3bddded
ML		 2061 if (pristate) {
2062 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2063 pri_latency, level);
2064 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2065 }
2066
2067 if (sprstate)
2068 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2069
2070 if (curstate)
2071 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2072
6f5ddd17
VS		 2073 result->enable = true;
2074}
2075
801bcfff 2076static uint32_t
532f7a7f 2077hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2078{
532f7a7f
VS		 2079 const struct intel_atomic_state *intel_state =
2080 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2081 const struct drm_display_mode *adjusted_mode =
2082 &cstate->base.adjusted_mode;
85a02deb 2083 u32 linetime, ips_linetime;
1f8eeabf 2084
ee91a159
MR		 2085 if (!cstate->base.active)
2086 return 0;
2087 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2088 return 0;
532f7a7f 2089 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2090 return 0;
1011d8c4 2091
1f8eeabf
ED		 2092 /* The WM are computed with base on how long it takes to fill a single
2093 * row at the given clock rate, multiplied by 8.
2094 * */
124abe07
VS		 2095 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2096 adjusted_mode->crtc_clock);
2097 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2098 intel_state->cdclk);
1f8eeabf 2099
801bcfff
PZ		 2100 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2101 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2102}
2103
2af30a5c 2104static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2105{
fac5e23e 2106 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2107
5db94019 2108 if (IS_GEN9(dev_priv)) {
2af30a5c 2109 uint32_t val;
4f947386 2110 int ret, i;
5db94019 2111 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2112
2113 /* read the first set of memory latencies[0:3] */
2114 val = 0; /* data0 to be programmed to 0 for first set */
2115 mutex_lock(&dev_priv->rps.hw_lock);
2116 ret = sandybridge_pcode_read(dev_priv,
2117 GEN9_PCODE_READ_MEM_LATENCY,
2118 &val);
2119 mutex_unlock(&dev_priv->rps.hw_lock);
2120
2121 if (ret) {
2122 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2123 return;
2124 }
2125
2126 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2127 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2128 GEN9_MEM_LATENCY_LEVEL_MASK;
2129 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2130 GEN9_MEM_LATENCY_LEVEL_MASK;
2131 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2132 GEN9_MEM_LATENCY_LEVEL_MASK;
2133
2134 /* read the second set of memory latencies[4:7] */
2135 val = 1; /* data0 to be programmed to 1 for second set */
2136 mutex_lock(&dev_priv->rps.hw_lock);
2137 ret = sandybridge_pcode_read(dev_priv,
2138 GEN9_PCODE_READ_MEM_LATENCY,
2139 &val);
2140 mutex_unlock(&dev_priv->rps.hw_lock);
2141 if (ret) {
2142 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2143 return;
2144 }
2145
2146 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2147 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2148 GEN9_MEM_LATENCY_LEVEL_MASK;
2149 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2150 GEN9_MEM_LATENCY_LEVEL_MASK;
2151 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2152 GEN9_MEM_LATENCY_LEVEL_MASK;
2153
0727e40a
PZ		 2154 /*
2155 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2156 * need to be disabled. We make sure to sanitize the values out
2157 * of the punit to satisfy this requirement.
2158 */
2159 for (level = 1; level <= max_level; level++) {
2160 if (wm[level] == 0) {
2161 for (i = level + 1; i <= max_level; i++)
2162 wm[i] = 0;
2163 break;
2164 }
2165 }
2166
367294be 2167 /*
6f97235b
DL		 2168 * WaWmMemoryReadLatency:skl
2169 *
367294be 2170 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2171 * to add 2us to the various latency levels we retrieve from the
2172 * punit when level 0 response data us 0us.
367294be 2173 */
0727e40a
PZ		 2174 if (wm[0] == 0) {
2175 wm[0] += 2;
2176 for (level = 1; level <= max_level; level++) {
2177 if (wm[level] == 0)
2178 break;
367294be 2179 wm[level] += 2;
4f947386 2180 }
0727e40a
PZ		 2181 }
2182
8652744b 2183 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2184 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2185
2186 wm[0] = (sskpd >> 56) & 0xFF;
2187 if (wm[0] == 0)
2188 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2189 wm[1] = (sskpd >> 4) & 0xFF;
2190 wm[2] = (sskpd >> 12) & 0xFF;
2191 wm[3] = (sskpd >> 20) & 0x1FF;
2192 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2193 } else if (INTEL_INFO(dev)->gen >= 6) {
2194 uint32_t sskpd = I915_READ(MCH_SSKPD);
2195
2196 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2197 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2198 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2199 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2200 } else if (INTEL_INFO(dev)->gen >= 5) {
2201 uint32_t mltr = I915_READ(MLTR_ILK);
2202
2203 /* ILK primary LP0 latency is 700 ns */
2204 wm[0] = 7;
2205 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2206 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2207 }
2208}
2209
5db94019
TU		 2210static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2211 uint16_t wm[5])
53615a5e
VS		 2212{
2213 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2214 if (IS_GEN5(dev_priv))
53615a5e
VS		 2215 wm[0] = 13;
2216}
2217
fd6b8f43
TU		 2218static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2219 uint16_t wm[5])
53615a5e
VS		 2220{
2221 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2222 if (IS_GEN5(dev_priv))
53615a5e
VS		 2223 wm[0] = 13;
2224
2225 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2226 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2227 wm[3] *= 2;
2228}
2229
5db94019 2230int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2231{
26ec971e 2232 /* how many WM levels are we expecting */
8652744b 2233 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2234 return 7;
8652744b 2235 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2236 return 4;
8652744b 2237 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2238 return 3;
26ec971e 2239 else
ad0d6dc4
VS		 2240 return 2;
2241}
7526ed79 2242
5db94019 2243static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2244 const char *name,
2af30a5c 2245 const uint16_t wm[8])
ad0d6dc4 2246{
5db94019 2247 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2248
2249 for (level = 0; level <= max_level; level++) {
2250 unsigned int latency = wm[level];
2251
2252 if (latency == 0) {
2253 DRM_ERROR("%s WM%d latency not provided\n",
2254 name, level);
2255 continue;
2256 }
2257
2af30a5c
PB		 2258 /*
2259 * - latencies are in us on gen9.
2260 * - before then, WM1+ latency values are in 0.5us units
2261 */
5db94019 2262 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2263 latency *= 10;
2264 else if (level > 0)
26ec971e
VS		 2265 latency *= 5;
2266
2267 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2268 name, level, wm[level],
2269 latency / 10, latency % 10);
2270 }
2271}
2272
e95a2f75
VS		 2273static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2274 uint16_t wm[5], uint16_t min)
2275{
5db94019 2276 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2277
2278 if (wm[0] >= min)
2279 return false;
2280
2281 wm[0] = max(wm[0], min);
2282 for (level = 1; level <= max_level; level++)
2283 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2284
2285 return true;
2286}
2287
2288static void snb_wm_latency_quirk(struct drm_device *dev)
2289{
fac5e23e 2290 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2291 bool changed;
2292
2293 /*
2294 * The BIOS provided WM memory latency values are often
2295 * inadequate for high resolution displays. Adjust them.
2296 */
2297 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2298 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2299 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2300
2301 if (!changed)
2302 return;
2303
2304 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2305 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2306 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2307 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2308}
2309
fa50ad61 2310static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2311{
fac5e23e 2312 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2313
2314 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2315
2316 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2317 sizeof(dev_priv->wm.pri_latency));
2318 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2319 sizeof(dev_priv->wm.pri_latency));
2320
5db94019 2321 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2322 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2323
5db94019
TU		 2324 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2325 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2326 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2327
5db94019 2328 if (IS_GEN6(dev_priv))
e95a2f75 2329 snb_wm_latency_quirk(dev);
53615a5e
VS		 2330}
2331
2af30a5c
PB		 2332static void skl_setup_wm_latency(struct drm_device *dev)
2333{
fac5e23e 2334 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2335
2336 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
5db94019 2337 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2338}
2339
ed4a6a7c
MR		 2340static bool ilk_validate_pipe_wm(struct drm_device *dev,
2341 struct intel_pipe_wm *pipe_wm)
2342{
2343 /* LP0 watermark maximums depend on this pipe alone */
2344 const struct intel_wm_config config = {
2345 .num_pipes_active = 1,
2346 .sprites_enabled = pipe_wm->sprites_enabled,
2347 .sprites_scaled = pipe_wm->sprites_scaled,
2348 };
2349 struct ilk_wm_maximums max;
2350
2351 /* LP0 watermarks always use 1/2 DDB partitioning */
2352 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2353
2354 /* At least LP0 must be valid */
2355 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2356 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2357 return false;
2358 }
2359
2360 return true;
2361}
2362
0b2ae6d7 2363/* Compute new watermarks for the pipe */
e3bddded 2364static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2365{
e3bddded
ML		 2366 struct drm_atomic_state *state = cstate->base.state;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2368 struct intel_pipe_wm *pipe_wm;
e3bddded 2369 struct drm_device *dev = state->dev;
fac5e23e 2370 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2371 struct intel_plane *intel_plane;
86c8bbbe 2372 struct intel_plane_state *pristate = NULL;
43d59eda 2373 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2374 struct intel_plane_state *curstate = NULL;
5db94019 2375 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2376 struct ilk_wm_maximums max;
0b2ae6d7 2377
e8f1f02e 2378 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2379
43d59eda 2380 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2381 struct intel_plane_state *ps;
2382
2383 ps = intel_atomic_get_existing_plane_state(state,
2384 intel_plane);
2385 if (!ps)
2386 continue;
86c8bbbe
MR		 2387
2388 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2389 pristate = ps;
86c8bbbe 2390 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2391 sprstate = ps;
86c8bbbe 2392 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2393 curstate = ps;
43d59eda
MR		 2394 }
2395
ed4a6a7c 2396 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2397 if (sprstate) {
936e71e3
VS		 2398 pipe_wm->sprites_enabled = sprstate->base.visible;
2399 pipe_wm->sprites_scaled = sprstate->base.visible &&
2400 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2401 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2402 }
2403
d81f04c5
ML		 2404 usable_level = max_level;
2405
7b39a0b7 2406 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2407 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2408 usable_level = 1;
7b39a0b7
VS		 2409
2410 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2411 if (pipe_wm->sprites_scaled)
d81f04c5 2412 usable_level = 0;
7b39a0b7 2413
86c8bbbe 2414 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2415 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2416
2417 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2418 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2419
8652744b 2420 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2421 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2422
ed4a6a7c 2423 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2424 return -EINVAL;
a3cb4048
VS		 2425
2426 ilk_compute_wm_reg_maximums(dev, 1, &max);
2427
2428 for (level = 1; level <= max_level; level++) {
71f0a626 2429 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2430
86c8bbbe 2431 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2432 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2433
2434 /*
2435 * Disable any watermark level that exceeds the
2436 * register maximums since such watermarks are
2437 * always invalid.
2438 */
71f0a626
ML		 2439 if (level > usable_level)
2440 continue;
2441
2442 if (ilk_validate_wm_level(level, &max, wm))
2443 pipe_wm->wm[level] = *wm;
2444 else
d81f04c5 2445 usable_level = level;
a3cb4048
VS		 2446 }
2447
86c8bbbe 2448 return 0;
0b2ae6d7
VS		 2449}
2450
ed4a6a7c
MR		 2451/*
2452 * Build a set of 'intermediate' watermark values that satisfy both the old
2453 * state and the new state. These can be programmed to the hardware
2454 * immediately.
2455 */
2456static int ilk_compute_intermediate_wm(struct drm_device *dev,
2457 struct intel_crtc *intel_crtc,
2458 struct intel_crtc_state *newstate)
2459{
e8f1f02e 2460 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2461 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2462 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2463
2464 /*
2465 * Start with the final, target watermarks, then combine with the
2466 * currently active watermarks to get values that are safe both before
2467 * and after the vblank.
2468 */
e8f1f02e 2469 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2470 a->pipe_enabled |= b->pipe_enabled;
2471 a->sprites_enabled |= b->sprites_enabled;
2472 a->sprites_scaled |= b->sprites_scaled;
2473
2474 for (level = 0; level <= max_level; level++) {
2475 struct intel_wm_level *a_wm = &a->wm[level];
2476 const struct intel_wm_level *b_wm = &b->wm[level];
2477
2478 a_wm->enable &= b_wm->enable;
2479 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2480 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2481 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2482 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2483 }
2484
2485 /*
2486 * We need to make sure that these merged watermark values are
2487 * actually a valid configuration themselves. If they're not,
2488 * there's no safe way to transition from the old state to
2489 * the new state, so we need to fail the atomic transaction.
2490 */
2491 if (!ilk_validate_pipe_wm(dev, a))
2492 return -EINVAL;
2493
2494 /*
2495 * If our intermediate WM are identical to the final WM, then we can
2496 * omit the post-vblank programming; only update if it's different.
2497 */
e8f1f02e 2498 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2499 newstate->wm.need_postvbl_update = false;
2500
2501 return 0;
2502}
2503
0b2ae6d7
VS		 2504/*
2505 * Merge the watermarks from all active pipes for a specific level.
2506 */
2507static void ilk_merge_wm_level(struct drm_device *dev,
2508 int level,
2509 struct intel_wm_level *ret_wm)
2510{
2511 const struct intel_crtc *intel_crtc;
2512
d52fea5b
VS		 2513 ret_wm->enable = true;
2514
d3fcc808 2515 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2516 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2517 const struct intel_wm_level *wm = &active->wm[level];
2518
2519 if (!active->pipe_enabled)
2520 continue;
0b2ae6d7 2521
d52fea5b
VS		 2522 /*
2523 * The watermark values may have been used in the past,
2524 * so we must maintain them in the registers for some
2525 * time even if the level is now disabled.
2526 */
0b2ae6d7 2527 if (!wm->enable)
d52fea5b 2528 ret_wm->enable = false;
0b2ae6d7
VS		 2529
2530 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2531 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2532 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2533 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2534 }
0b2ae6d7
VS		 2535}
2536
2537/*
2538 * Merge all low power watermarks for all active pipes.
2539 */
2540static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2541 const struct intel_wm_config *config,
820c1980 2542 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2543 struct intel_pipe_wm *merged)
2544{
fac5e23e 2545 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2546 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2547 int last_enabled_level = max_level;
0b2ae6d7 2548
0ba22e26 2549 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2550 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2551 config->num_pipes_active > 1)
1204d5ba 2552 last_enabled_level = 0;
0ba22e26 2553
6c8b6c28
VS		 2554 /* ILK: FBC WM must be disabled always */
2555 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2556
2557 /* merge each WM1+ level */
2558 for (level = 1; level <= max_level; level++) {
2559 struct intel_wm_level *wm = &merged->wm[level];
2560
2561 ilk_merge_wm_level(dev, level, wm);
2562
d52fea5b
VS		 2563 if (level > last_enabled_level)
2564 wm->enable = false;
2565 else if (!ilk_validate_wm_level(level, max, wm))
2566 /* make sure all following levels get disabled */
2567 last_enabled_level = level - 1;
0b2ae6d7
VS		 2568
2569 /*
2570 * The spec says it is preferred to disable
2571 * FBC WMs instead of disabling a WM level.
2572 */
2573 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2574 if (wm->enable)
2575 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2576 wm->fbc_val = 0;
2577 }
2578 }
6c8b6c28
VS		 2579
2580 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2581 /*
2582 * FIXME this is racy. FBC might get enabled later.
2583 * What we should check here is whether FBC can be
2584 * enabled sometime later.
2585 */
5db94019 2586 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2587 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2588 for (level = 2; level <= max_level; level++) {
2589 struct intel_wm_level *wm = &merged->wm[level];
2590
2591 wm->enable = false;
2592 }
2593 }
0b2ae6d7
VS		 2594}
2595
b380ca3c
VS		 2596static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2597{
2598 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2599 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2600}
2601
a68d68ee
VS		 2602/* The value we need to program into the WM_LPx latency field */
2603static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2604{
fac5e23e 2605 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2606
8652744b 2607 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2608 return 2 * level;
2609 else
2610 return dev_priv->wm.pri_latency[level];
2611}
2612
820c1980 2613static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2614 const struct intel_pipe_wm *merged,
609cedef 2615 enum intel_ddb_partitioning partitioning,
820c1980 2616 struct ilk_wm_values *results)
801bcfff 2617{
0b2ae6d7
VS		 2618 struct intel_crtc *intel_crtc;
2619 int level, wm_lp;
cca32e9a 2620
0362c781 2621 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2622 results->partitioning = partitioning;
cca32e9a 2623
0b2ae6d7 2624 /* LP1+ register values */
cca32e9a 2625 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2626 const struct intel_wm_level *r;
801bcfff 2627
b380ca3c 2628 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2629
0362c781 2630 r = &merged->wm[level];
cca32e9a 2631
d52fea5b
VS		 2632 /*
2633 * Maintain the watermark values even if the level is
2634 * disabled. Doing otherwise could cause underruns.
2635 */
2636 results->wm_lp[wm_lp - 1] =
a68d68ee 2637 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2638 (r->pri_val << WM1_LP_SR_SHIFT) |
2639 r->cur_val;
2640
d52fea5b
VS		 2641 if (r->enable)
2642 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2643
416f4727
VS		 2644 if (INTEL_INFO(dev)->gen >= 8)
2645 results->wm_lp[wm_lp - 1] |=
2646 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2647 else
2648 results->wm_lp[wm_lp - 1] |=
2649 r->fbc_val << WM1_LP_FBC_SHIFT;
2650
d52fea5b
VS		 2651 /*
2652 * Always set WM1S_LP_EN when spr_val != 0, even if the
2653 * level is disabled. Doing otherwise could cause underruns.
2654 */
6cef2b8a
VS		 2655 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2656 WARN_ON(wm_lp != 1);
2657 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2658 } else
2659 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2660 }
801bcfff 2661
0b2ae6d7 2662 /* LP0 register values */
d3fcc808 2663 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2664 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2665 const struct intel_wm_level *r =
2666 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2667
2668 if (WARN_ON(!r->enable))
2669 continue;
2670
ed4a6a7c 2671 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2672
0b2ae6d7
VS		 2673 results->wm_pipe[pipe] =
2674 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2675 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2676 r->cur_val;
801bcfff
PZ		 2677 }
2678}
2679
861f3389
PZ		 2680/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2681 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2682static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2683 struct intel_pipe_wm *r1,
2684 struct intel_pipe_wm *r2)
861f3389 2685{
5db94019 2686 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2687 int level1 = 0, level2 = 0;
861f3389 2688
198a1e9b
VS		 2689 for (level = 1; level <= max_level; level++) {
2690 if (r1->wm[level].enable)
2691 level1 = level;
2692 if (r2->wm[level].enable)
2693 level2 = level;
861f3389
PZ		 2694 }
2695
198a1e9b
VS		 2696 if (level1 == level2) {
2697 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2698 return r2;
2699 else
2700 return r1;
198a1e9b 2701 } else if (level1 > level2) {
861f3389
PZ		 2702 return r1;
2703 } else {
2704 return r2;
2705 }
2706}
2707
49a687c4
VS		 2708/* dirty bits used to track which watermarks need changes */
2709#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2710#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2711#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2712#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2713#define WM_DIRTY_FBC (1 << 24)
2714#define WM_DIRTY_DDB (1 << 25)
2715
055e393f 2716static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2717 const struct ilk_wm_values *old,
2718 const struct ilk_wm_values *new)
49a687c4
VS		 2719{
2720 unsigned int dirty = 0;
2721 enum pipe pipe;
2722 int wm_lp;
2723
055e393f 2724 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2725 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2726 dirty |= WM_DIRTY_LINETIME(pipe);
2727 /* Must disable LP1+ watermarks too */
2728 dirty |= WM_DIRTY_LP_ALL;
2729 }
2730
2731 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2732 dirty |= WM_DIRTY_PIPE(pipe);
2733 /* Must disable LP1+ watermarks too */
2734 dirty |= WM_DIRTY_LP_ALL;
2735 }
2736 }
2737
2738 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2739 dirty |= WM_DIRTY_FBC;
2740 /* Must disable LP1+ watermarks too */
2741 dirty |= WM_DIRTY_LP_ALL;
2742 }
2743
2744 if (old->partitioning != new->partitioning) {
2745 dirty |= WM_DIRTY_DDB;
2746 /* Must disable LP1+ watermarks too */
2747 dirty |= WM_DIRTY_LP_ALL;
2748 }
2749
2750 /* LP1+ watermarks already deemed dirty, no need to continue */
2751 if (dirty & WM_DIRTY_LP_ALL)
2752 return dirty;
2753
2754 /* Find the lowest numbered LP1+ watermark in need of an update... */
2755 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2756 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2757 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2758 break;
2759 }
2760
2761 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2762 for (; wm_lp <= 3; wm_lp++)
2763 dirty |= WM_DIRTY_LP(wm_lp);
2764
2765 return dirty;
2766}
2767
8553c18e
VS		 2768static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2769 unsigned int dirty)
801bcfff 2770{
820c1980 2771 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2772 bool changed = false;
801bcfff 2773
facd619b
VS		 2774 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2775 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2776 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2777 changed = true;
facd619b
VS		 2778 }
2779 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2780 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2781 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2782 changed = true;
facd619b
VS		 2783 }
2784 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2785 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2786 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2787 changed = true;
facd619b 2788 }
801bcfff 2789
facd619b
VS		 2790 /*
2791 * Don't touch WM1S_LP_EN here.
2792 * Doing so could cause underruns.
2793 */
6cef2b8a 2794
8553c18e
VS		 2795 return changed;
2796}
2797
2798/*
2799 * The spec says we shouldn't write when we don't need, because every write
2800 * causes WMs to be re-evaluated, expending some power.
2801 */
820c1980
ID		 2802static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2803 struct ilk_wm_values *results)
8553c18e 2804{
91c8a326 2805 struct drm_device *dev = &dev_priv->drm;
820c1980 2806 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2807 unsigned int dirty;
2808 uint32_t val;
2809
055e393f 2810 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2811 if (!dirty)
2812 return;
2813
2814 _ilk_disable_lp_wm(dev_priv, dirty);
2815
49a687c4 2816 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2817 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2818 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2819 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2820 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2821 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2822
49a687c4 2823 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2824 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2825 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2826 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2827 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2828 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2829
49a687c4 2830 if (dirty & WM_DIRTY_DDB) {
8652744b 2831 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2832 val = I915_READ(WM_MISC);
2833 if (results->partitioning == INTEL_DDB_PART_1_2)
2834 val &= ~WM_MISC_DATA_PARTITION_5_6;
2835 else
2836 val |= WM_MISC_DATA_PARTITION_5_6;
2837 I915_WRITE(WM_MISC, val);
2838 } else {
2839 val = I915_READ(DISP_ARB_CTL2);
2840 if (results->partitioning == INTEL_DDB_PART_1_2)
2841 val &= ~DISP_DATA_PARTITION_5_6;
2842 else
2843 val |= DISP_DATA_PARTITION_5_6;
2844 I915_WRITE(DISP_ARB_CTL2, val);
2845 }
1011d8c4
PZ		 2846 }
2847
49a687c4 2848 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2849 val = I915_READ(DISP_ARB_CTL);
2850 if (results->enable_fbc_wm)
2851 val &= ~DISP_FBC_WM_DIS;
2852 else
2853 val |= DISP_FBC_WM_DIS;
2854 I915_WRITE(DISP_ARB_CTL, val);
2855 }
2856
954911eb
ID		 2857 if (dirty & WM_DIRTY_LP(1) &&
2858 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2859 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2860
2861 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2862 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2863 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2864 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2865 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2866 }
801bcfff 2867
facd619b 2868 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2869 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2870 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2871 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2872 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2873 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2874
2875 dev_priv->wm.hw = *results;
801bcfff
PZ		 2876}
2877
ed4a6a7c 2878bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2879{
fac5e23e 2880 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2881
2882 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2883}
2884
656d1b89 2885#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2886
024c9045
MR		 2887/*
2888 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2889 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2890 * other universal planes are in indices 1..n. Note that this may leave unused
2891 * indices between the top "sprite" plane and the cursor.
2892 */
2893static int
2894skl_wm_plane_id(const struct intel_plane *plane)
2895{
2896 switch (plane->base.type) {
2897 case DRM_PLANE_TYPE_PRIMARY:
2898 return 0;
2899 case DRM_PLANE_TYPE_CURSOR:
2900 return PLANE_CURSOR;
2901 case DRM_PLANE_TYPE_OVERLAY:
2902 return plane->plane + 1;
2903 default:
2904 MISSING_CASE(plane->base.type);
2905 return plane->plane;
2906 }
2907}
2908
ee3d532f
PZ		 2909/*
2910 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2911 * so assume we'll always need it in order to avoid underruns.
2912 */
2913static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2914{
2915 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2916
2917 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2918 IS_KABYLAKE(dev_priv))
2919 return true;
2920
2921 return false;
2922}
2923
56feca91
PZ		 2924static bool
2925intel_has_sagv(struct drm_i915_private *dev_priv)
2926{
6e3100ec
PZ		 2927 if (IS_KABYLAKE(dev_priv))
2928 return true;
2929
2930 if (IS_SKYLAKE(dev_priv) &&
2931 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2932 return true;
2933
2934 return false;
56feca91
PZ		 2935}
2936
656d1b89
L		 2937/*
2938 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2939 * depending on power and performance requirements. The display engine access
2940 * to system memory is blocked during the adjustment time. Because of the
2941 * blocking time, having this enabled can cause full system hangs and/or pipe
2942 * underruns if we don't meet all of the following requirements:
2943 *
2944 * - <= 1 pipe enabled
2945 * - All planes can enable watermarks for latencies >= SAGV engine block time
2946 * - We're not using an interlaced display configuration
2947 */
2948int
16dcdc4e 2949intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2950{
2951 int ret;
2952
56feca91
PZ		 2953 if (!intel_has_sagv(dev_priv))
2954 return 0;
2955
2956 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2957 return 0;
2958
2959 DRM_DEBUG_KMS("Enabling the SAGV\n");
2960 mutex_lock(&dev_priv->rps.hw_lock);
2961
2962 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2963 GEN9_SAGV_ENABLE);
2964
2965 /* We don't need to wait for the SAGV when enabling */
2966 mutex_unlock(&dev_priv->rps.hw_lock);
2967
2968 /*
2969 * Some skl systems, pre-release machines in particular,
2970 * don't actually have an SAGV.
2971 */
6e3100ec 2972 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2973 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2974 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2975 return 0;
2976 } else if (ret < 0) {
2977 DRM_ERROR("Failed to enable the SAGV\n");
2978 return ret;
2979 }
2980
16dcdc4e 2981 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2982 return 0;
2983}
2984
2985static int
16dcdc4e 2986intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2987{
2988 int ret;
2989 uint32_t temp = GEN9_SAGV_DISABLE;
2990
2991 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2992 &temp);
2993 if (ret)
2994 return ret;
2995 else
2996 return temp & GEN9_SAGV_IS_DISABLED;
2997}
2998
2999int
16dcdc4e 3000intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 3001{
3002 int ret, result;
3003
56feca91
PZ		 3004 if (!intel_has_sagv(dev_priv))
3005 return 0;
3006
3007 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 3008 return 0;
3009
3010 DRM_DEBUG_KMS("Disabling the SAGV\n");
3011 mutex_lock(&dev_priv->rps.hw_lock);
3012
3013 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 3014 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 3015 mutex_unlock(&dev_priv->rps.hw_lock);
3016
3017 if (ret == -ETIMEDOUT) {
3018 DRM_ERROR("Request to disable SAGV timed out\n");
3019 return -ETIMEDOUT;
3020 }
3021
3022 /*
3023 * Some skl systems, pre-release machines in particular,
3024 * don't actually have an SAGV.
3025 */
6e3100ec 3026 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 3027 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3028 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3029 return 0;
3030 } else if (result < 0) {
3031 DRM_ERROR("Failed to disable the SAGV\n");
3032 return result;
3033 }
3034
16dcdc4e 3035 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3036 return 0;
3037}
3038
16dcdc4e 3039bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3040{
3041 struct drm_device *dev = state->dev;
3042 struct drm_i915_private *dev_priv = to_i915(dev);
3043 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3044 struct intel_crtc *crtc;
3045 struct intel_plane *plane;
d8c0fafc 3046 struct intel_crtc_state *cstate;
3047 struct skl_plane_wm *wm;
656d1b89 3048 enum pipe pipe;
d8c0fafc 3049 int level, latency;
656d1b89 3050
56feca91
PZ		 3051 if (!intel_has_sagv(dev_priv))
3052 return false;
3053
656d1b89
L		 3054 /*
3055 * SKL workaround: bspec recommends we disable the SAGV when we have
3056 * more then one pipe enabled
3057 *
3058 * If there are no active CRTCs, no additional checks need be performed
3059 */
3060 if (hweight32(intel_state->active_crtcs) == 0)
3061 return true;
3062 else if (hweight32(intel_state->active_crtcs) > 1)
3063 return false;
3064
3065 /* Since we're now guaranteed to only have one active CRTC... */
3066 pipe = ffs(intel_state->active_crtcs) - 1;
98187836 3067 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
d8c0fafc 3068 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3069
c89cadd5 3070 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3071 return false;
3072
ee3d532f 3073 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d8c0fafc 3074 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
ee3d532f 3075
656d1b89 3076 /* Skip this plane if it's not enabled */
d8c0fafc 3077 if (!wm->wm[0].plane_en)
656d1b89
L		 3078 continue;
3079
3080 /* Find the highest enabled wm level for this plane */
5db94019 3081 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3082 !wm->wm[level].plane_en; --level)
656d1b89
L		 3083 { }
3084
ee3d532f
PZ		 3085 latency = dev_priv->wm.skl_latency[level];
3086
3087 if (skl_needs_memory_bw_wa(intel_state) &&
3088 plane->base.state->fb->modifier[0] ==
3089 I915_FORMAT_MOD_X_TILED)
3090 latency += 15;
3091
656d1b89
L		 3092 /*
3093 * If any of the planes on this pipe don't enable wm levels
3094 * that incur memory latencies higher then 30µs we can't enable
3095 * the SAGV
3096 */
ee3d532f 3097 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3098 return false;
3099 }
3100
3101 return true;
3102}
3103
b9cec075
DL		 3104static void
3105skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3106 const struct intel_crtc_state *cstate,
c107acfe
MR		 3107 struct skl_ddb_entry *alloc, /* out */
3108 int *num_active /* out */)
b9cec075 3109{
c107acfe
MR		 3110 struct drm_atomic_state *state = cstate->base.state;
3111 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3112 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3113 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3114 unsigned int pipe_size, ddb_size;
3115 int nth_active_pipe;
c107acfe 3116
a6d3460e 3117 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3118 alloc->start = 0;
3119 alloc->end = 0;
a6d3460e 3120 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3121 return;
3122 }
3123
a6d3460e
MR		 3124 if (intel_state->active_pipe_changes)
3125 *num_active = hweight32(intel_state->active_crtcs);
3126 else
3127 *num_active = hweight32(dev_priv->active_crtcs);
3128
6f3fff60
D		 3129 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3130 WARN_ON(ddb_size == 0);
b9cec075
DL		 3131
3132 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3133
c107acfe 3134 /*
a6d3460e
MR		 3135 * If the state doesn't change the active CRTC's, then there's
3136 * no need to recalculate; the existing pipe allocation limits
3137 * should remain unchanged. Note that we're safe from racing
3138 * commits since any racing commit that changes the active CRTC
3139 * list would need to grab _all_ crtc locks, including the one
3140 * we currently hold.
c107acfe 3141 */
a6d3460e 3142 if (!intel_state->active_pipe_changes) {
ce0ba283 3143 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
a6d3460e 3144 return;
c107acfe 3145 }
a6d3460e
MR		 3146
3147 nth_active_pipe = hweight32(intel_state->active_crtcs &
3148 (drm_crtc_mask(for_crtc) - 1));
3149 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3150 alloc->start = nth_active_pipe * ddb_size / *num_active;
3151 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3152}
3153
c107acfe 3154static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3155{
c107acfe 3156 if (num_active == 1)
b9cec075
DL		 3157 return 32;
3158
3159 return 8;
3160}
3161
a269c583
DL		 3162static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3163{
3164 entry->start = reg & 0x3ff;
3165 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3166 if (entry->end)
3167 entry->end += 1;
a269c583
DL		 3168}
3169
08db6652
DL		 3170void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3171 struct skl_ddb_allocation *ddb /* out */)
a269c583 3172{
a269c583
DL		 3173 enum pipe pipe;
3174 int plane;
3175 u32 val;
3176
b10f1b20
ML		 3177 memset(ddb, 0, sizeof(*ddb));
3178
a269c583 3179 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3180 enum intel_display_power_domain power_domain;
3181
3182 power_domain = POWER_DOMAIN_PIPE(pipe);
3183 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3184 continue;
3185
8b364b41 3186 for_each_universal_plane(dev_priv, pipe, plane) {
a269c583
DL		 3187 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3188 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3189 val);
3190 }
3191
3192 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3193 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3194 val);
4d800030
ID		 3195
3196 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3197 }
3198}
3199
9c2f7a9d
KM		 3200/*
3201 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3202 * The bspec defines downscale amount as:
3203 *
3204 * """
3205 * Horizontal down scale amount = maximum[1, Horizontal source size /
3206 * Horizontal destination size]
3207 * Vertical down scale amount = maximum[1, Vertical source size /
3208 * Vertical destination size]
3209 * Total down scale amount = Horizontal down scale amount *
3210 * Vertical down scale amount
3211 * """
3212 *
3213 * Return value is provided in 16.16 fixed point form to retain fractional part.
3214 * Caller should take care of dividing & rounding off the value.
3215 */
3216static uint32_t
3217skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3218{
3219 uint32_t downscale_h, downscale_w;
3220 uint32_t src_w, src_h, dst_w, dst_h;
3221
936e71e3 3222 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3223 return DRM_PLANE_HELPER_NO_SCALING;
3224
3225 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3226 src_w = drm_rect_width(&pstate->base.src);
3227 src_h = drm_rect_height(&pstate->base.src);
3228 dst_w = drm_rect_width(&pstate->base.dst);
3229 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3230 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3231 swap(dst_w, dst_h);
3232
3233 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3234 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3235
3236 /* Provide result in 16.16 fixed point */
3237 return (uint64_t)downscale_w * downscale_h >> 16;
3238}
3239
b9cec075 3240static unsigned int
024c9045
MR		 3241skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3242 const struct drm_plane_state *pstate,
3243 int y)
b9cec075 3244{
a280f7dd 3245 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3246 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3247 uint32_t down_scale_amount, data_rate;
a280f7dd 3248 uint32_t width = 0, height = 0;
a1de91e5
MR		 3249 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3250
936e71e3 3251 if (!intel_pstate->base.visible)
a1de91e5
MR		 3252 return 0;
3253 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3254 return 0;
3255 if (y && format != DRM_FORMAT_NV12)
3256 return 0;
a280f7dd 3257
936e71e3
VS		 3258 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3259 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3260
bd2ef25d 3261 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3262 swap(width, height);
2cd601c6
CK		 3263
3264 /* for planar format */
a1de91e5 3265 if (format == DRM_FORMAT_NV12) {
2cd601c6 3266 if (y) /* y-plane data rate */
8d19d7d9 3267 data_rate = width * height *
a1de91e5 3268 drm_format_plane_cpp(format, 0);
2cd601c6 3269 else /* uv-plane data rate */
8d19d7d9 3270 data_rate = (width / 2) * (height / 2) *
a1de91e5 3271 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3272 } else {
3273 /* for packed formats */
3274 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3275 }
3276
8d19d7d9
KM		 3277 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3278
3279 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3280}
3281
3282/*
3283 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3284 * a 8192x4096@32bpp framebuffer:
3285 * 3 * 4096 * 8192 * 4 < 2^32
3286 */
3287static unsigned int
1e6ee542
ML		 3288skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3289 unsigned *plane_data_rate,
3290 unsigned *plane_y_data_rate)
b9cec075 3291{
9c74d826
MR		 3292 struct drm_crtc_state *cstate = &intel_cstate->base;
3293 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3294 struct drm_plane *plane;
024c9045 3295 const struct intel_plane *intel_plane;
c8fe32c1 3296 const struct drm_plane_state *pstate;
a1de91e5 3297 unsigned int rate, total_data_rate = 0;
9c74d826 3298 int id;
a6d3460e
MR		 3299
3300 if (WARN_ON(!state))
3301 return 0;
b9cec075 3302
a1de91e5 3303 /* Calculate and cache data rate for each plane */
c8fe32c1 3304 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
a6d3460e
MR		 3305 id = skl_wm_plane_id(to_intel_plane(plane));
3306 intel_plane = to_intel_plane(plane);
3307
a6d3460e
MR		 3308 /* packed/uv */
3309 rate = skl_plane_relative_data_rate(intel_cstate,
3310 pstate, 0);
1e6ee542
ML		 3311 plane_data_rate[id] = rate;
3312
3313 total_data_rate += rate;
a6d3460e
MR		 3314
3315 /* y-plane */
3316 rate = skl_plane_relative_data_rate(intel_cstate,
3317 pstate, 1);
1e6ee542 3318 plane_y_data_rate[id] = rate;
024c9045 3319
1e6ee542 3320 total_data_rate += rate;
b9cec075
DL		 3321 }
3322
3323 return total_data_rate;
3324}
3325
cbcfd14b
KM		 3326static uint16_t
3327skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3328 const int y)
3329{
3330 struct drm_framebuffer *fb = pstate->fb;
3331 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3332 uint32_t src_w, src_h;
3333 uint32_t min_scanlines = 8;
3334 uint8_t plane_bpp;
3335
3336 if (WARN_ON(!fb))
3337 return 0;
3338
3339 /* For packed formats, no y-plane, return 0 */
3340 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3341 return 0;
3342
3343 /* For Non Y-tile return 8-blocks */
3344 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3345 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3346 return 8;
3347
936e71e3
VS		 3348 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3349 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3350
bd2ef25d 3351 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3352 swap(src_w, src_h);
3353
3354 /* Halve UV plane width and height for NV12 */
3355 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3356 src_w /= 2;
3357 src_h /= 2;
3358 }
3359
3360 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3361 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3362 else
3363 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3364
bd2ef25d 3365 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3366 switch (plane_bpp) {
3367 case 1:
3368 min_scanlines = 32;
3369 break;
3370 case 2:
3371 min_scanlines = 16;
3372 break;
3373 case 4:
3374 min_scanlines = 8;
3375 break;
3376 case 8:
3377 min_scanlines = 4;
3378 break;
3379 default:
3380 WARN(1, "Unsupported pixel depth %u for rotation",
3381 plane_bpp);
3382 min_scanlines = 32;
3383 }
3384 }
3385
3386 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3387}
3388
49845a7a
ML		 3389static void
3390skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3391 uint16_t *minimum, uint16_t *y_minimum)
3392{
3393 const struct drm_plane_state *pstate;
3394 struct drm_plane *plane;
3395
3396 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3397 struct intel_plane *intel_plane = to_intel_plane(plane);
3398 int id = skl_wm_plane_id(intel_plane);
3399
3400 if (id == PLANE_CURSOR)
3401 continue;
3402
3403 if (!pstate->visible)
3404 continue;
3405
3406 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3407 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3408 }
3409
3410 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3411}
3412
c107acfe 3413static int
024c9045 3414skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3415 struct skl_ddb_allocation *ddb /* out */)
3416{
c107acfe 3417 struct drm_atomic_state *state = cstate->base.state;
024c9045 3418 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3419 struct drm_device *dev = crtc->dev;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3422 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
49845a7a 3423 uint16_t alloc_size, start;
fefdd810
ML		 3424 uint16_t minimum[I915_MAX_PLANES] = {};
3425 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3426 unsigned int total_data_rate;
c107acfe
MR		 3427 int num_active;
3428 int id, i;
1e6ee542
ML		 3429 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3430 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3431
5a920b85
PZ		 3432 /* Clear the partitioning for disabled planes. */
3433 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3434 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3435
a6d3460e
MR		 3436 if (WARN_ON(!state))
3437 return 0;
3438
c107acfe 3439 if (!cstate->base.active) {
ce0ba283 3440 alloc->start = alloc->end = 0;
c107acfe
MR		 3441 return 0;
3442 }
3443
a6d3460e 3444 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3445 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3446 if (alloc_size == 0) {
3447 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3448 return 0;
b9cec075
DL		 3449 }
3450
49845a7a 3451 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
a6d3460e 3452
49845a7a
ML		 3453 /*
3454 * 1. Allocate the mininum required blocks for each active plane
3455 * and allocate the cursor, it doesn't require extra allocation
3456 * proportional to the data rate.
3457 */
80958155 3458
49845a7a 3459 for (i = 0; i < I915_MAX_PLANES; i++) {
c107acfe
MR		 3460 alloc_size -= minimum[i];
3461 alloc_size -= y_minimum[i];
80958155
DL		 3462 }
3463
49845a7a
ML		 3464 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3465 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3466
b9cec075 3467 /*
80958155
DL		 3468 * 2. Distribute the remaining space in proportion to the amount of
3469 * data each plane needs to fetch from memory.
b9cec075
DL		 3470 *
3471 * FIXME: we may not allocate every single block here.
3472 */
1e6ee542
ML		 3473 total_data_rate = skl_get_total_relative_data_rate(cstate,
3474 plane_data_rate,
3475 plane_y_data_rate);
a1de91e5 3476 if (total_data_rate == 0)
c107acfe 3477 return 0;
b9cec075 3478
34bb56af 3479 start = alloc->start;
1e6ee542 3480 for (id = 0; id < I915_MAX_PLANES; id++) {
2cd601c6
CK		 3481 unsigned int data_rate, y_data_rate;
3482 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3483
49845a7a
ML		 3484 if (id == PLANE_CURSOR)
3485 continue;
3486
1e6ee542 3487 data_rate = plane_data_rate[id];
b9cec075
DL		 3488
3489 /*
2cd601c6 3490 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3491 * promote the expression to 64 bits to avoid overflowing, the
3492 * result is < available as data_rate / total_data_rate < 1
3493 */
024c9045 3494 plane_blocks = minimum[id];
80958155
DL		 3495 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3496 total_data_rate);
b9cec075 3497
c107acfe
MR		 3498 /* Leave disabled planes at (0,0) */
3499 if (data_rate) {
3500 ddb->plane[pipe][id].start = start;
3501 ddb->plane[pipe][id].end = start + plane_blocks;
3502 }
b9cec075
DL		 3503
3504 start += plane_blocks;
2cd601c6
CK		 3505
3506 /*
3507 * allocation for y_plane part of planar format:
3508 */
1e6ee542 3509 y_data_rate = plane_y_data_rate[id];
a1de91e5
MR		 3510
3511 y_plane_blocks = y_minimum[id];
3512 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3513 total_data_rate);
2cd601c6 3514
c107acfe
MR		 3515 if (y_data_rate) {
3516 ddb->y_plane[pipe][id].start = start;
3517 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3518 }
a1de91e5
MR		 3519
3520 start += y_plane_blocks;
b9cec075
DL		 3521 }
3522
c107acfe 3523 return 0;
b9cec075
DL		 3524}
3525
2d41c0b5
PB		 3526/*
3527 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3528 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3529 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3530 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3531*/
ac484963 3532static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3533{
3534 uint32_t wm_intermediate_val, ret;
3535
3536 if (latency == 0)
3537 return UINT_MAX;
3538
ac484963 3539 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3540 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3541
3542 return ret;
3543}
3544
3545static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3546 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3547{
d4c2aa60 3548 uint32_t ret;
d4c2aa60 3549 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3550
3551 if (latency == 0)
3552 return UINT_MAX;
3553
2d41c0b5
PB		 3554 wm_intermediate_val = latency * pixel_rate;
3555 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3556 plane_blocks_per_line;
2d41c0b5
PB		 3557
3558 return ret;
3559}
3560
9c2f7a9d
KM		 3561static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3562 struct intel_plane_state *pstate)
3563{
3564 uint64_t adjusted_pixel_rate;
3565 uint64_t downscale_amount;
3566 uint64_t pixel_rate;
3567
3568 /* Shouldn't reach here on disabled planes... */
936e71e3 3569 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3570 return 0;
3571
3572 /*
3573 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3574 * with additional adjustments for plane-specific scaling.
3575 */
cfd7e3a2 3576 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
9c2f7a9d
KM		 3577 downscale_amount = skl_plane_downscale_amount(pstate);
3578
3579 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3580 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3581
3582 return pixel_rate;
3583}
3584
55994c2c
MR		 3585static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3586 struct intel_crtc_state *cstate,
3587 struct intel_plane_state *intel_pstate,
3588 uint16_t ddb_allocation,
3589 int level,
3590 uint16_t *out_blocks, /* out */
3591 uint8_t *out_lines, /* out */
3592 bool *enabled /* out */)
2d41c0b5 3593{
33815fa5
MR		 3594 struct drm_plane_state *pstate = &intel_pstate->base;
3595 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3596 uint32_t latency = dev_priv->wm.skl_latency[level];
3597 uint32_t method1, method2;
3598 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3599 uint32_t res_blocks, res_lines;
3600 uint32_t selected_result;
ac484963 3601 uint8_t cpp;
a280f7dd 3602 uint32_t width = 0, height = 0;
9c2f7a9d 3603 uint32_t plane_pixel_rate;
75676ed4 3604 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3605 struct intel_atomic_state *state =
3606 to_intel_atomic_state(cstate->base.state);
3607 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3608
936e71e3 3609 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3610 *enabled = false;
3611 return 0;
3612 }
2d41c0b5 3613
ee3d532f
PZ		 3614 if (apply_memory_bw_wa && fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3615 latency += 15;
3616
936e71e3
VS		 3617 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3618 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3619
bd2ef25d 3620 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3621 swap(width, height);
3622
ac484963 3623 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3624 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3625
61d0a04d 3626 if (drm_rotation_90_or_270(pstate->rotation)) {
1186fa85
PZ		 3627 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3628 drm_format_plane_cpp(fb->pixel_format, 1) :
3629 drm_format_plane_cpp(fb->pixel_format, 0);
3630
3631 switch (cpp) {
3632 case 1:
3633 y_min_scanlines = 16;
3634 break;
3635 case 2:
3636 y_min_scanlines = 8;
3637 break;
1186fa85
PZ		 3638 case 4:
3639 y_min_scanlines = 4;
3640 break;
86a462bc
PZ		 3641 default:
3642 MISSING_CASE(cpp);
3643 return -EINVAL;
1186fa85
PZ		 3644 }
3645 } else {
3646 y_min_scanlines = 4;
3647 }
3648
7a1a8aed
PZ		 3649 plane_bytes_per_line = width * cpp;
3650 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3651 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3652 plane_blocks_per_line =
3653 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3654 plane_blocks_per_line /= y_min_scanlines;
3655 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3656 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3657 + 1;
3658 } else {
3659 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3660 }
3661
9c2f7a9d
KM		 3662 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3663 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3664 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3665 latency,
7a1a8aed 3666 plane_blocks_per_line);
2d41c0b5 3667
75676ed4 3668 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
ee3d532f
PZ		 3669 if (apply_memory_bw_wa)
3670 y_tile_minimum *= 2;
75676ed4 3671
024c9045
MR		 3672 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3673 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3674 selected_result = max(method2, y_tile_minimum);
3675 } else {
f1db3eaf
PZ		 3676 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3677 (plane_bytes_per_line / 512 < 1))
3678 selected_result = method2;
3679 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3680 selected_result = min(method1, method2);
3681 else
3682 selected_result = method1;
3683 }
2d41c0b5 3684
d4c2aa60
TU		 3685 res_blocks = selected_result + 1;
3686 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3687
0fda6568 3688 if (level >= 1 && level <= 7) {
024c9045 3689 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3690 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3691 res_blocks += y_tile_minimum;
1186fa85 3692 res_lines += y_min_scanlines;
75676ed4 3693 } else {
0fda6568 3694 res_blocks++;
75676ed4 3695 }
0fda6568 3696 }
e6d66171 3697
55994c2c
MR		 3698 if (res_blocks >= ddb_allocation || res_lines > 31) {
3699 *enabled = false;
6b6bada7
MR		 3700
3701 /*
3702 * If there are no valid level 0 watermarks, then we can't
3703 * support this display configuration.
3704 */
3705 if (level) {
3706 return 0;
3707 } else {
3708 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3709 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3710 to_intel_crtc(cstate->base.crtc)->pipe,
3711 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3712 res_blocks, ddb_allocation, res_lines);
3713
3714 return -EINVAL;
3715 }
55994c2c 3716 }
e6d66171
DL		 3717
3718 *out_blocks = res_blocks;
3719 *out_lines = res_lines;
55994c2c 3720 *enabled = true;
2d41c0b5 3721
55994c2c 3722 return 0;
2d41c0b5
PB		 3723}
3724
f4a96752
MR		 3725static int
3726skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3727 struct skl_ddb_allocation *ddb,
3728 struct intel_crtc_state *cstate,
a62163e9 3729 struct intel_plane *intel_plane,
f4a96752
MR		 3730 int level,
3731 struct skl_wm_level *result)
2d41c0b5 3732{
f4a96752 3733 struct drm_atomic_state *state = cstate->base.state;
024c9045 3734 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3735 struct drm_plane *plane = &intel_plane->base;
3736 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3737 uint16_t ddb_blocks;
024c9045 3738 enum pipe pipe = intel_crtc->pipe;
55994c2c 3739 int ret;
a62163e9
L		 3740 int i = skl_wm_plane_id(intel_plane);
3741
3742 if (state)
3743 intel_pstate =
3744 intel_atomic_get_existing_plane_state(state,
3745 intel_plane);
024c9045 3746
f4a96752 3747 /*
a62163e9
L		 3748 * Note: If we start supporting multiple pending atomic commits against
3749 * the same planes/CRTC's in the future, plane->state will no longer be
3750 * the correct pre-state to use for the calculations here and we'll
3751 * need to change where we get the 'unchanged' plane data from.
3752 *
3753 * For now this is fine because we only allow one queued commit against
3754 * a CRTC. Even if the plane isn't modified by this transaction and we
3755 * don't have a plane lock, we still have the CRTC's lock, so we know
3756 * that no other transactions are racing with us to update it.
f4a96752 3757 */
a62163e9
L		 3758 if (!intel_pstate)
3759 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3760
a62163e9 3761 WARN_ON(!intel_pstate->base.fb);
f4a96752 3762
a62163e9 3763 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2d41c0b5 3764
a62163e9
L		 3765 ret = skl_compute_plane_wm(dev_priv,
3766 cstate,
3767 intel_pstate,
3768 ddb_blocks,
3769 level,
3770 &result->plane_res_b,
3771 &result->plane_res_l,
3772 &result->plane_en);
3773 if (ret)
3774 return ret;
f4a96752
MR		 3775
3776 return 0;
2d41c0b5
PB		 3777}
3778
407b50f3 3779static uint32_t
024c9045 3780skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3781{
30d1b5fe
PZ		 3782 uint32_t pixel_rate;
3783
024c9045 3784 if (!cstate->base.active)
407b50f3
DL		 3785 return 0;
3786
30d1b5fe
PZ		 3787 pixel_rate = ilk_pipe_pixel_rate(cstate);
3788
3789 if (WARN_ON(pixel_rate == 0))
661abfc0 3790 return 0;
407b50f3 3791
024c9045 3792 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
30d1b5fe 3793 pixel_rate);
407b50f3
DL		 3794}
3795
024c9045 3796static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3797 struct skl_wm_level *trans_wm /* out */)
407b50f3 3798{
024c9045 3799 if (!cstate->base.active)
407b50f3 3800 return;
9414f563
DL		 3801
3802 /* Until we know more, just disable transition WMs */
a62163e9 3803 trans_wm->plane_en = false;
407b50f3
DL		 3804}
3805
55994c2c
MR		 3806static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3807 struct skl_ddb_allocation *ddb,
3808 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3809{
024c9045 3810 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3811 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3812 struct intel_plane *intel_plane;
3813 struct skl_plane_wm *wm;
5db94019 3814 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3815 int ret;
2d41c0b5 3816
a62163e9
L		 3817 /*
3818 * We'll only calculate watermarks for planes that are actually
3819 * enabled, so make sure all other planes are set as disabled.
3820 */
3821 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3822
3823 for_each_intel_plane_mask(&dev_priv->drm,
3824 intel_plane,
3825 cstate->base.plane_mask) {
3826 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3827
3828 for (level = 0; level <= max_level; level++) {
3829 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3830 intel_plane, level,
3831 &wm->wm[level]);
3832 if (ret)
3833 return ret;
3834 }
3835 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3836 }
024c9045 3837 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3838
55994c2c 3839 return 0;
2d41c0b5
PB		 3840}
3841
f0f59a00
VS		 3842static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3843 i915_reg_t reg,
16160e3d
DL		 3844 const struct skl_ddb_entry *entry)
3845{
3846 if (entry->end)
3847 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3848 else
3849 I915_WRITE(reg, 0);
3850}
3851
d8c0fafc 3852static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3853 i915_reg_t reg,
3854 const struct skl_wm_level *level)
3855{
3856 uint32_t val = 0;
3857
3858 if (level->plane_en) {
3859 val |= PLANE_WM_EN;
3860 val |= level->plane_res_b;
3861 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3862 }
3863
3864 I915_WRITE(reg, val);
3865}
3866
62e0fb88 3867void skl_write_plane_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3868 const struct skl_plane_wm *wm,
3869 const struct skl_ddb_allocation *ddb,
62e0fb88
L		 3870 int plane)
3871{
3872 struct drm_crtc *crtc = &intel_crtc->base;
3873 struct drm_device *dev = crtc->dev;
3874 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3875 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3876 enum pipe pipe = intel_crtc->pipe;
3877
3878 for (level = 0; level <= max_level; level++) {
d8c0fafc 3879 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3880 &wm->wm[level]);
62e0fb88 3881 }
d8c0fafc 3882 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3883 &wm->trans_wm);
27082493
L		 3884
3885 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
d8c0fafc 3886 &ddb->plane[pipe][plane]);
27082493 3887 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
d8c0fafc 3888 &ddb->y_plane[pipe][plane]);
62e0fb88
L		 3889}
3890
3891void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
d8c0fafc 3892 const struct skl_plane_wm *wm,
3893 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3894{
3895 struct drm_crtc *crtc = &intel_crtc->base;
3896 struct drm_device *dev = crtc->dev;
3897 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3898 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3899 enum pipe pipe = intel_crtc->pipe;
3900
3901 for (level = 0; level <= max_level; level++) {
d8c0fafc 3902 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3903 &wm->wm[level]);
62e0fb88 3904 }
d8c0fafc 3905 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3906
27082493 3907 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3908 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3909}
3910
45ece230 3911bool skl_wm_level_equals(const struct skl_wm_level *l1,
3912 const struct skl_wm_level *l2)
3913{
3914 if (l1->plane_en != l2->plane_en)
3915 return false;
3916
3917 /* If both planes aren't enabled, the rest shouldn't matter */
3918 if (!l1->plane_en)
3919 return true;
3920
3921 return (l1->plane_res_l == l2->plane_res_l &&
3922 l1->plane_res_b == l2->plane_res_b);
3923}
3924
27082493
L		 3925static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3926 const struct skl_ddb_entry *b)
0e8fb7ba 3927{
27082493 3928 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3929}
3930
27082493 3931bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
ce0ba283 3932 struct intel_crtc *intel_crtc)
0e8fb7ba 3933{
ce0ba283
L		 3934 struct drm_crtc *other_crtc;
3935 struct drm_crtc_state *other_cstate;
3936 struct intel_crtc *other_intel_crtc;
3937 const struct skl_ddb_entry *ddb =
3938 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3939 int i;
0e8fb7ba 3940
ce0ba283
L		 3941 for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3942 other_intel_crtc = to_intel_crtc(other_crtc);
0e8fb7ba 3943
ce0ba283 3944 if (other_intel_crtc == intel_crtc)
0e8fb7ba
DL		 3945 continue;
3946
ce0ba283 3947 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
27082493 3948 return true;
0e8fb7ba
DL		 3949 }
3950
27082493 3951 return false;
0e8fb7ba
DL		 3952}
3953
55994c2c 3954static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
03af79e0 3955 const struct skl_pipe_wm *old_pipe_wm,
55994c2c 3956 struct skl_pipe_wm *pipe_wm, /* out */
03af79e0 3957 struct skl_ddb_allocation *ddb, /* out */
55994c2c 3958 bool *changed /* out */)
2d41c0b5 3959{
f4a96752 3960 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3961 int ret;
2d41c0b5 3962
55994c2c
MR		 3963 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3964 if (ret)
3965 return ret;
2d41c0b5 3966
03af79e0 3967 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3968 *changed = false;
3969 else
3970 *changed = true;
2d41c0b5 3971
55994c2c 3972 return 0;
2d41c0b5
PB		 3973}
3974
9b613022
MR		 3975static uint32_t
3976pipes_modified(struct drm_atomic_state *state)
3977{
3978 struct drm_crtc *crtc;
3979 struct drm_crtc_state *cstate;
3980 uint32_t i, ret = 0;
3981
3982 for_each_crtc_in_state(state, crtc, cstate, i)
3983 ret |= drm_crtc_mask(crtc);
3984
3985 return ret;
3986}
3987
bb7791bd 3988static int
7f60e200
PZ		 3989skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3990{
3991 struct drm_atomic_state *state = cstate->base.state;
3992 struct drm_device *dev = state->dev;
3993 struct drm_crtc *crtc = cstate->base.crtc;
3994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3995 struct drm_i915_private *dev_priv = to_i915(dev);
3996 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3997 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3998 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3999 struct drm_plane_state *plane_state;
4000 struct drm_plane *plane;
4001 enum pipe pipe = intel_crtc->pipe;
4002 int id;
4003
4004 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
4005
220b0965 4006 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
7f60e200
PZ		 4007 id = skl_wm_plane_id(to_intel_plane(plane));
4008
4009 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
4010 &new_ddb->plane[pipe][id]) &&
4011 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
4012 &new_ddb->y_plane[pipe][id]))
4013 continue;
4014
4015 plane_state = drm_atomic_get_plane_state(state, plane);
4016 if (IS_ERR(plane_state))
4017 return PTR_ERR(plane_state);
4018 }
4019
4020 return 0;
4021}
4022
98d39494
MR		 4023static int
4024skl_compute_ddb(struct drm_atomic_state *state)
4025{
4026 struct drm_device *dev = state->dev;
4027 struct drm_i915_private *dev_priv = to_i915(dev);
4028 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4029 struct intel_crtc *intel_crtc;
734fa01f 4030 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4031 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4032 int ret;
4033
4034 /*
4035 * If this is our first atomic update following hardware readout,
4036 * we can't trust the DDB that the BIOS programmed for us. Let's
4037 * pretend that all pipes switched active status so that we'll
4038 * ensure a full DDB recompute.
4039 */
1b54a880
MR		 4040 if (dev_priv->wm.distrust_bios_wm) {
4041 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4042 state->acquire_ctx);
4043 if (ret)
4044 return ret;
4045
98d39494
MR		 4046 intel_state->active_pipe_changes = ~0;
4047
1b54a880
MR		 4048 /*
4049 * We usually only initialize intel_state->active_crtcs if we
4050 * we're doing a modeset; make sure this field is always
4051 * initialized during the sanitization process that happens
4052 * on the first commit too.
4053 */
4054 if (!intel_state->modeset)
4055 intel_state->active_crtcs = dev_priv->active_crtcs;
4056 }
4057
98d39494
MR		 4058 /*
4059 * If the modeset changes which CRTC's are active, we need to
4060 * recompute the DDB allocation for *all* active pipes, even
4061 * those that weren't otherwise being modified in any way by this
4062 * atomic commit. Due to the shrinking of the per-pipe allocations
4063 * when new active CRTC's are added, it's possible for a pipe that
4064 * we were already using and aren't changing at all here to suddenly
4065 * become invalid if its DDB needs exceeds its new allocation.
4066 *
4067 * Note that if we wind up doing a full DDB recompute, we can't let
4068 * any other display updates race with this transaction, so we need
4069 * to grab the lock on *all* CRTC's.
4070 */
734fa01f 4071 if (intel_state->active_pipe_changes) {
98d39494 4072 realloc_pipes = ~0;
734fa01f
MR		 4073 intel_state->wm_results.dirty_pipes = ~0;
4074 }
98d39494 4075
5a920b85
PZ		 4076 /*
4077 * We're not recomputing for the pipes not included in the commit, so
4078 * make sure we start with the current state.
4079 */
4080 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4081
98d39494
MR		 4082 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4083 struct intel_crtc_state *cstate;
4084
4085 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4086 if (IS_ERR(cstate))
4087 return PTR_ERR(cstate);
4088
734fa01f 4089 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4090 if (ret)
4091 return ret;
05a76d3d 4092
7f60e200 4093 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4094 if (ret)
4095 return ret;
98d39494
MR		 4096 }
4097
4098 return 0;
4099}
4100
2722efb9
MR		 4101static void
4102skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4103 struct skl_wm_values *src,
4104 enum pipe pipe)
4105{
2722efb9
MR		 4106 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4107 sizeof(dst->ddb.y_plane[pipe]));
4108 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4109 sizeof(dst->ddb.plane[pipe]));
4110}
4111
413fc530 4112static void
4113skl_print_wm_changes(const struct drm_atomic_state *state)
4114{
4115 const struct drm_device *dev = state->dev;
4116 const struct drm_i915_private *dev_priv = to_i915(dev);
4117 const struct intel_atomic_state *intel_state =
4118 to_intel_atomic_state(state);
4119 const struct drm_crtc *crtc;
4120 const struct drm_crtc_state *cstate;
413fc530 4121 const struct intel_plane *intel_plane;
413fc530 4122 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4123 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
413fc530 4124 int id;
7570498e 4125 int i;
413fc530 4126
4127 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4128 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129 enum pipe pipe = intel_crtc->pipe;
413fc530 4130
7570498e 4131 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
413fc530 4132 const struct skl_ddb_entry *old, *new;
4133
413fc530 4134 id = skl_wm_plane_id(intel_plane);
4135 old = &old_ddb->plane[pipe][id];
4136 new = &new_ddb->plane[pipe][id];
4137
413fc530 4138 if (skl_ddb_entry_equal(old, new))
4139 continue;
4140
7570498e
ML		 4141 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4142 intel_plane->base.base.id,
4143 intel_plane->base.name,
4144 old->start, old->end,
4145 new->start, new->end);
413fc530 4146 }
4147 }
4148}
4149
98d39494
MR		 4150static int
4151skl_compute_wm(struct drm_atomic_state *state)
4152{
4153 struct drm_crtc *crtc;
4154 struct drm_crtc_state *cstate;
734fa01f
MR		 4155 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4156 struct skl_wm_values *results = &intel_state->wm_results;
4157 struct skl_pipe_wm *pipe_wm;
98d39494 4158 bool changed = false;
734fa01f 4159 int ret, i;
98d39494
MR		 4160
4161 /*
4162 * If this transaction isn't actually touching any CRTC's, don't
4163 * bother with watermark calculation. Note that if we pass this
4164 * test, we're guaranteed to hold at least one CRTC state mutex,
4165 * which means we can safely use values like dev_priv->active_crtcs
4166 * since any racing commits that want to update them would need to
4167 * hold _all_ CRTC state mutexes.
4168 */
4169 for_each_crtc_in_state(state, crtc, cstate, i)
4170 changed = true;
4171 if (!changed)
4172 return 0;
4173
734fa01f
MR		 4174 /* Clear all dirty flags */
4175 results->dirty_pipes = 0;
4176
98d39494
MR		 4177 ret = skl_compute_ddb(state);
4178 if (ret)
4179 return ret;
4180
734fa01f
MR		 4181 /*
4182 * Calculate WM's for all pipes that are part of this transaction.
4183 * Note that the DDB allocation above may have added more CRTC's that
4184 * weren't otherwise being modified (and set bits in dirty_pipes) if
4185 * pipe allocations had to change.
4186 *
4187 * FIXME: Now that we're doing this in the atomic check phase, we
4188 * should allow skl_update_pipe_wm() to return failure in cases where
4189 * no suitable watermark values can be found.
4190 */
4191 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4192 struct intel_crtc_state *intel_cstate =
4193 to_intel_crtc_state(cstate);
03af79e0
ML		 4194 const struct skl_pipe_wm *old_pipe_wm =
4195 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
734fa01f
MR		 4196
4197 pipe_wm = &intel_cstate->wm.skl.optimal;
03af79e0
ML		 4198 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4199 &results->ddb, &changed);
734fa01f
MR		 4200 if (ret)
4201 return ret;
4202
4203 if (changed)
4204 results->dirty_pipes |= drm_crtc_mask(crtc);
4205
4206 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4207 /* This pipe's WM's did not change */
4208 continue;
4209
4210 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4211 }
4212
413fc530 4213 skl_print_wm_changes(state);
4214
98d39494
MR		 4215 return 0;
4216}
4217
432081bc 4218static void skl_update_wm(struct intel_crtc *intel_crtc)
2d41c0b5 4219{
432081bc 4220 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4221 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4222 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4223 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
432081bc 4224 struct intel_crtc_state *cstate = to_intel_crtc_state(intel_crtc->base.state);
e8f1f02e 4225 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4226 enum pipe pipe = intel_crtc->pipe;
adda50b8 4227
432081bc 4228 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
2d41c0b5
PB		 4229 return;
4230
734fa01f 4231 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4232
2722efb9 4233 /*
27082493
L		 4234 * If this pipe isn't active already, we're going to be enabling it
4235 * very soon. Since it's safe to update a pipe's ddb allocation while
4236 * the pipe's shut off, just do so here. Already active pipes will have
4237 * their watermarks updated once we update their planes.
2722efb9 4238 */
432081bc 4239 if (intel_crtc->base.state->active_changed) {
27082493
L		 4240 int plane;
4241
2c4b49a0 4242 for_each_universal_plane(dev_priv, pipe, plane)
d8c0fafc 4243 skl_write_plane_wm(intel_crtc, &pipe_wm->planes[plane],
4244 &results->ddb, plane);
27082493 4245
d8c0fafc 4246 skl_write_cursor_wm(intel_crtc, &pipe_wm->planes[PLANE_CURSOR],
4247 &results->ddb);
27082493
L		 4248 }
4249
4250 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f 4251
ce0ba283
L		 4252 intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4253
734fa01f 4254 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4255}
4256
d890565c
VS		 4257static void ilk_compute_wm_config(struct drm_device *dev,
4258 struct intel_wm_config *config)
4259{
4260 struct intel_crtc *crtc;
4261
4262 /* Compute the currently _active_ config */
4263 for_each_intel_crtc(dev, crtc) {
4264 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4265
4266 if (!wm->pipe_enabled)
4267 continue;
4268
4269 config->sprites_enabled |= wm->sprites_enabled;
4270 config->sprites_scaled |= wm->sprites_scaled;
4271 config->num_pipes_active++;
4272 }
4273}
4274
ed4a6a7c 4275static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4276{
91c8a326 4277 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4278 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4279 struct ilk_wm_maximums max;
d890565c 4280 struct intel_wm_config config = {};
820c1980 4281 struct ilk_wm_values results = {};
77c122bc 4282 enum intel_ddb_partitioning partitioning;
261a27d1 4283
d890565c
VS		 4284 ilk_compute_wm_config(dev, &config);
4285
4286 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4287 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4288
4289 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4290 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4291 config.num_pipes_active == 1 && config.sprites_enabled) {
4292 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4293 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4294
820c1980 4295 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4296 } else {
198a1e9b 4297 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4298 }
4299
198a1e9b 4300 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4301 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4302
820c1980 4303 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4304
820c1980 4305 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4306}
4307
ed4a6a7c 4308static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4309{
ed4a6a7c
MR		 4310 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4311 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4312
ed4a6a7c 4313 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4314 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4315 ilk_program_watermarks(dev_priv);
4316 mutex_unlock(&dev_priv->wm.wm_mutex);
4317}
bf220452 4318
ed4a6a7c
MR		 4319static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4320{
4321 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4322 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4323
ed4a6a7c
MR		 4324 mutex_lock(&dev_priv->wm.wm_mutex);
4325 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4326 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4327 ilk_program_watermarks(dev_priv);
4328 }
4329 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4330}
4331
d8c0fafc 4332static inline void skl_wm_level_from_reg_val(uint32_t val,
4333 struct skl_wm_level *level)
3078999f 4334{
d8c0fafc 4335 level->plane_en = val & PLANE_WM_EN;
4336 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4337 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4338 PLANE_WM_LINES_MASK;
3078999f
PB		 4339}
4340
bf9d99ad 4341void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4342 struct skl_pipe_wm *out)
3078999f
PB		 4343{
4344 struct drm_device *dev = crtc->dev;
fac5e23e 4345 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f 4346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d8c0fafc 4347 struct intel_plane *intel_plane;
d8c0fafc 4348 struct skl_plane_wm *wm;
3078999f 4349 enum pipe pipe = intel_crtc->pipe;
d8c0fafc 4350 int level, id, max_level;
4351 uint32_t val;
3078999f 4352
5db94019 4353 max_level = ilk_wm_max_level(dev_priv);
3078999f 4354
d8c0fafc 4355 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4356 id = skl_wm_plane_id(intel_plane);
bf9d99ad 4357 wm = &out->planes[id];
3078999f 4358
d8c0fafc 4359 for (level = 0; level <= max_level; level++) {
4360 if (id != PLANE_CURSOR)
4361 val = I915_READ(PLANE_WM(pipe, id, level));
4362 else
4363 val = I915_READ(CUR_WM(pipe, level));
3078999f 4364
d8c0fafc 4365 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4366 }
3078999f 4367
d8c0fafc 4368 if (id != PLANE_CURSOR)
4369 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4370 else
4371 val = I915_READ(CUR_WM_TRANS(pipe));
4372
4373 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4374 }
4375
d8c0fafc 4376 if (!intel_crtc->active)
4377 return;
4e0963c7 4378
bf9d99ad 4379 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4380}
4381
4382void skl_wm_get_hw_state(struct drm_device *dev)
4383{
fac5e23e 4384 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4385 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4386 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4387 struct drm_crtc *crtc;
bf9d99ad 4388 struct intel_crtc *intel_crtc;
4389 struct intel_crtc_state *cstate;
3078999f 4390
a269c583 4391 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4392 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4393 intel_crtc = to_intel_crtc(crtc);
4394 cstate = to_intel_crtc_state(crtc->state);
4395
4396 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4397
03af79e0 4398 if (intel_crtc->active)
bf9d99ad 4399 hw->dirty_pipes |= drm_crtc_mask(crtc);
bf9d99ad 4400 }
a1de91e5 4401
279e99d7
MR		 4402 if (dev_priv->active_crtcs) {
4403 /* Fully recompute DDB on first atomic commit */
4404 dev_priv->wm.distrust_bios_wm = true;
4405 } else {
4406 /* Easy/common case; just sanitize DDB now if everything off */
4407 memset(ddb, 0, sizeof(*ddb));
4408 }
3078999f
PB		 4409}
4410
243e6a44
VS		 4411static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4412{
4413 struct drm_device *dev = crtc->dev;
fac5e23e 4414 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4415 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4417 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4418 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4419 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4420 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4421 [PIPE_A] = WM0_PIPEA_ILK,
4422 [PIPE_B] = WM0_PIPEB_ILK,
4423 [PIPE_C] = WM0_PIPEC_IVB,
4424 };
4425
4426 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4427 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4428 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4429
15606534
VS		 4430 memset(active, 0, sizeof(*active));
4431
3ef00284 4432 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4433
4434 if (active->pipe_enabled) {
243e6a44
VS		 4435 u32 tmp = hw->wm_pipe[pipe];
4436
4437 /*
4438 * For active pipes LP0 watermark is marked as
4439 * enabled, and LP1+ watermaks as disabled since
4440 * we can't really reverse compute them in case
4441 * multiple pipes are active.
4442 */
4443 active->wm[0].enable = true;
4444 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4445 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4446 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4447 active->linetime = hw->wm_linetime[pipe];
4448 } else {
5db94019 4449 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4450
4451 /*
4452 * For inactive pipes, all watermark levels
4453 * should be marked as enabled but zeroed,
4454 * which is what we'd compute them to.
4455 */
4456 for (level = 0; level <= max_level; level++)
4457 active->wm[level].enable = true;
4458 }
4e0963c7
MR		 4459
4460 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4461}
4462
6eb1a681
VS		 4463#define _FW_WM(value, plane) \
4464 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4465#define _FW_WM_VLV(value, plane) \
4466 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4467
4468static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4469 struct vlv_wm_values *wm)
4470{
4471 enum pipe pipe;
4472 uint32_t tmp;
4473
4474 for_each_pipe(dev_priv, pipe) {
4475 tmp = I915_READ(VLV_DDL(pipe));
4476
4477 wm->ddl[pipe].primary =
4478 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4479 wm->ddl[pipe].cursor =
4480 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4481 wm->ddl[pipe].sprite[0] =
4482 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4483 wm->ddl[pipe].sprite[1] =
4484 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4485 }
4486
4487 tmp = I915_READ(DSPFW1);
4488 wm->sr.plane = _FW_WM(tmp, SR);
4489 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4490 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4491 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4492
4493 tmp = I915_READ(DSPFW2);
4494 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4495 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4496 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4497
4498 tmp = I915_READ(DSPFW3);
4499 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4500
4501 if (IS_CHERRYVIEW(dev_priv)) {
4502 tmp = I915_READ(DSPFW7_CHV);
4503 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4504 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4505
4506 tmp = I915_READ(DSPFW8_CHV);
4507 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4508 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4509
4510 tmp = I915_READ(DSPFW9_CHV);
4511 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4512 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4513
4514 tmp = I915_READ(DSPHOWM);
4515 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4516 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4517 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4518 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4519 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4520 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4521 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4522 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4523 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4524 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4525 } else {
4526 tmp = I915_READ(DSPFW7);
4527 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4528 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4529
4530 tmp = I915_READ(DSPHOWM);
4531 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4532 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4533 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4534 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4535 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4536 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4537 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4538 }
4539}
4540
4541#undef _FW_WM
4542#undef _FW_WM_VLV
4543
4544void vlv_wm_get_hw_state(struct drm_device *dev)
4545{
4546 struct drm_i915_private *dev_priv = to_i915(dev);
4547 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4548 struct intel_plane *plane;
4549 enum pipe pipe;
4550 u32 val;
4551
4552 vlv_read_wm_values(dev_priv, wm);
4553
4554 for_each_intel_plane(dev, plane) {
4555 switch (plane->base.type) {
4556 int sprite;
4557 case DRM_PLANE_TYPE_CURSOR:
4558 plane->wm.fifo_size = 63;
4559 break;
4560 case DRM_PLANE_TYPE_PRIMARY:
4561 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4562 break;
4563 case DRM_PLANE_TYPE_OVERLAY:
4564 sprite = plane->plane;
4565 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4566 break;
4567 }
4568 }
4569
4570 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4571 wm->level = VLV_WM_LEVEL_PM2;
4572
4573 if (IS_CHERRYVIEW(dev_priv)) {
4574 mutex_lock(&dev_priv->rps.hw_lock);
4575
4576 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4577 if (val & DSP_MAXFIFO_PM5_ENABLE)
4578 wm->level = VLV_WM_LEVEL_PM5;
4579
58590c14
VS		 4580 /*
4581 * If DDR DVFS is disabled in the BIOS, Punit
4582 * will never ack the request. So if that happens
4583 * assume we don't have to enable/disable DDR DVFS
4584 * dynamically. To test that just set the REQ_ACK
4585 * bit to poke the Punit, but don't change the
4586 * HIGH/LOW bits so that we don't actually change
4587 * the current state.
4588 */
6eb1a681 4589 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4590 val |= FORCE_DDR_FREQ_REQ_ACK;
4591 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4592
4593 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4594 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4595 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4596 "assuming DDR DVFS is disabled\n");
4597 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4598 } else {
4599 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4600 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4601 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4602 }
6eb1a681
VS		 4603
4604 mutex_unlock(&dev_priv->rps.hw_lock);
4605 }
4606
4607 for_each_pipe(dev_priv, pipe)
4608 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4609 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4610 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4611
4612 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4613 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4614}
4615
243e6a44
VS		 4616void ilk_wm_get_hw_state(struct drm_device *dev)
4617{
fac5e23e 4618 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4619 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4620 struct drm_crtc *crtc;
4621
70e1e0ec 4622 for_each_crtc(dev, crtc)
243e6a44
VS		 4623 ilk_pipe_wm_get_hw_state(crtc);
4624
4625 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4626 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4627 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4628
4629 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4630 if (INTEL_INFO(dev)->gen >= 7) {
4631 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4632 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4633 }
243e6a44 4634
8652744b 4635 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4636 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4637 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4638 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4639 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4640 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4641
4642 hw->enable_fbc_wm =
4643 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4644}
4645
b445e3b0
ED		 4646/**
4647 * intel_update_watermarks - update FIFO watermark values based on current modes
4648 *
4649 * Calculate watermark values for the various WM regs based on current mode
4650 * and plane configuration.
4651 *
4652 * There are several cases to deal with here:
4653 * - normal (i.e. non-self-refresh)
4654 * - self-refresh (SR) mode
4655 * - lines are large relative to FIFO size (buffer can hold up to 2)
4656 * - lines are small relative to FIFO size (buffer can hold more than 2
4657 * lines), so need to account for TLB latency
4658 *
4659 * The normal calculation is:
4660 * watermark = dotclock * bytes per pixel * latency
4661 * where latency is platform & configuration dependent (we assume pessimal
4662 * values here).
4663 *
4664 * The SR calculation is:
4665 * watermark = (trunc(latency/line time)+1) * surface width *
4666 * bytes per pixel
4667 * where
4668 * line time = htotal / dotclock
4669 * surface width = hdisplay for normal plane and 64 for cursor
4670 * and latency is assumed to be high, as above.
4671 *
4672 * The final value programmed to the register should always be rounded up,
4673 * and include an extra 2 entries to account for clock crossings.
4674 *
4675 * We don't use the sprite, so we can ignore that. And on Crestline we have
4676 * to set the non-SR watermarks to 8.
4677 */
432081bc 4678void intel_update_watermarks(struct intel_crtc *crtc)
b445e3b0 4679{
432081bc 4680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0
ED		 4681
4682 if (dev_priv->display.update_wm)
46ba614c 4683 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4684}
4685
e2828914 4686/*
9270388e 4687 * Lock protecting IPS related data structures
9270388e
DV		 4688 */
4689DEFINE_SPINLOCK(mchdev_lock);
4690
4691/* Global for IPS driver to get at the current i915 device. Protected by
4692 * mchdev_lock. */
4693static struct drm_i915_private *i915_mch_dev;
4694
91d14251 4695bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4696{
2b4e57bd
ED		 4697 u16 rgvswctl;
4698
9270388e
DV		 4699 assert_spin_locked(&mchdev_lock);
4700
2b4e57bd
ED		 4701 rgvswctl = I915_READ16(MEMSWCTL);
4702 if (rgvswctl & MEMCTL_CMD_STS) {
4703 DRM_DEBUG("gpu busy, RCS change rejected\n");
4704 return false; /* still busy with another command */
4705 }
4706
4707 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4708 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4709 I915_WRITE16(MEMSWCTL, rgvswctl);
4710 POSTING_READ16(MEMSWCTL);
4711
4712 rgvswctl |= MEMCTL_CMD_STS;
4713 I915_WRITE16(MEMSWCTL, rgvswctl);
4714
4715 return true;
4716}
4717
91d14251 4718static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4719{
84f1b20f 4720 u32 rgvmodectl;
2b4e57bd
ED		 4721 u8 fmax, fmin, fstart, vstart;
4722
9270388e
DV		 4723 spin_lock_irq(&mchdev_lock);
4724
84f1b20f
TU		 4725 rgvmodectl = I915_READ(MEMMODECTL);
4726
2b4e57bd
ED		 4727 /* Enable temp reporting */
4728 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4729 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4730
4731 /* 100ms RC evaluation intervals */
4732 I915_WRITE(RCUPEI, 100000);
4733 I915_WRITE(RCDNEI, 100000);
4734
4735 /* Set max/min thresholds to 90ms and 80ms respectively */
4736 I915_WRITE(RCBMAXAVG, 90000);
4737 I915_WRITE(RCBMINAVG, 80000);
4738
4739 I915_WRITE(MEMIHYST, 1);
4740
4741 /* Set up min, max, and cur for interrupt handling */
4742 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4743 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4744 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4745 MEMMODE_FSTART_SHIFT;
4746
616847e7 4747 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4748 PXVFREQ_PX_SHIFT;
4749
20e4d407
DV		 4750 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4751 dev_priv->ips.fstart = fstart;
2b4e57bd 4752
20e4d407
DV		 4753 dev_priv->ips.max_delay = fstart;
4754 dev_priv->ips.min_delay = fmin;
4755 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4756
4757 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4758 fmax, fmin, fstart);
4759
4760 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4761
4762 /*
4763 * Interrupts will be enabled in ironlake_irq_postinstall
4764 */
4765
4766 I915_WRITE(VIDSTART, vstart);
4767 POSTING_READ(VIDSTART);
4768
4769 rgvmodectl |= MEMMODE_SWMODE_EN;
4770 I915_WRITE(MEMMODECTL, rgvmodectl);
4771
9270388e 4772 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4773 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4774 mdelay(1);
2b4e57bd 4775
91d14251 4776 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4777
7d81c3e0
VS		 4778 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4779 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4780 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4781 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4782 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4783
4784 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4785}
4786
91d14251 4787static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4788{
9270388e
DV		 4789 u16 rgvswctl;
4790
4791 spin_lock_irq(&mchdev_lock);
4792
4793 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4794
4795 /* Ack interrupts, disable EFC interrupt */
4796 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4797 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4798 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4799 I915_WRITE(DEIIR, DE_PCU_EVENT);
4800 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4801
4802 /* Go back to the starting frequency */
91d14251 4803 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4804 mdelay(1);
2b4e57bd
ED		 4805 rgvswctl |= MEMCTL_CMD_STS;
4806 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4807 mdelay(1);
2b4e57bd 4808
9270388e 4809 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4810}
4811
acbe9475
DV		 4812/* There's a funny hw issue where the hw returns all 0 when reading from
4813 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4814 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4815 * all limits and the gpu stuck at whatever frequency it is at atm).
4816 */
74ef1173 4817static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4818{
7b9e0ae6 4819 u32 limits;
2b4e57bd 4820
20b46e59
DV		 4821 /* Only set the down limit when we've reached the lowest level to avoid
4822 * getting more interrupts, otherwise leave this clear. This prevents a
4823 * race in the hw when coming out of rc6: There's a tiny window where
4824 * the hw runs at the minimal clock before selecting the desired
4825 * frequency, if the down threshold expires in that window we will not
4826 * receive a down interrupt. */
2d1fe073 4827 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4828 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4829 if (val <= dev_priv->rps.min_freq_softlimit)
4830 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4831 } else {
4832 limits = dev_priv->rps.max_freq_softlimit << 24;
4833 if (val <= dev_priv->rps.min_freq_softlimit)
4834 limits |= dev_priv->rps.min_freq_softlimit << 16;
4835 }
20b46e59
DV		 4836
4837 return limits;
4838}
4839
dd75fdc8
CW		 4840static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4841{
4842 int new_power;
8a586437
AG		 4843 u32 threshold_up = 0, threshold_down = 0; /* in % */
4844 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4845
4846 new_power = dev_priv->rps.power;
4847 switch (dev_priv->rps.power) {
4848 case LOW_POWER:
a72b5623
CW		 4849 if (val > dev_priv->rps.efficient_freq + 1 &&
4850 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4851 new_power = BETWEEN;
4852 break;
4853
4854 case BETWEEN:
a72b5623
CW		 4855 if (val <= dev_priv->rps.efficient_freq &&
4856 val < dev_priv->rps.cur_freq)
dd75fdc8 4857 new_power = LOW_POWER;
a72b5623
CW		 4858 else if (val >= dev_priv->rps.rp0_freq &&
4859 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4860 new_power = HIGH_POWER;
4861 break;
4862
4863 case HIGH_POWER:
a72b5623
CW		 4864 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4865 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4866 new_power = BETWEEN;
4867 break;
4868 }
4869 /* Max/min bins are special */
aed242ff 4870 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4871 new_power = LOW_POWER;
aed242ff 4872 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4873 new_power = HIGH_POWER;
4874 if (new_power == dev_priv->rps.power)
4875 return;
4876
4877 /* Note the units here are not exactly 1us, but 1280ns. */
4878 switch (new_power) {
4879 case LOW_POWER:
4880 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4881 ei_up = 16000;
4882 threshold_up = 95;
dd75fdc8
CW		 4883
4884 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4885 ei_down = 32000;
4886 threshold_down = 85;
dd75fdc8
CW		 4887 break;
4888
4889 case BETWEEN:
4890 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4891 ei_up = 13000;
4892 threshold_up = 90;
dd75fdc8
CW		 4893
4894 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4895 ei_down = 32000;
4896 threshold_down = 75;
dd75fdc8
CW		 4897 break;
4898
4899 case HIGH_POWER:
4900 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4901 ei_up = 10000;
4902 threshold_up = 85;
dd75fdc8
CW		 4903
4904 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4905 ei_down = 32000;
4906 threshold_down = 60;
dd75fdc8
CW		 4907 break;
4908 }
4909
8a586437 4910 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4911 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4912 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4913 GT_INTERVAL_FROM_US(dev_priv,
4914 ei_up * threshold_up / 100));
8a586437
AG		 4915
4916 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4917 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4918 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4919 GT_INTERVAL_FROM_US(dev_priv,
4920 ei_down * threshold_down / 100));
4921
4922 I915_WRITE(GEN6_RP_CONTROL,
4923 GEN6_RP_MEDIA_TURBO |
4924 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4925 GEN6_RP_MEDIA_IS_GFX |
4926 GEN6_RP_ENABLE |
4927 GEN6_RP_UP_BUSY_AVG |
4928 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4929
dd75fdc8 4930 dev_priv->rps.power = new_power;
8fb55197
CW		 4931 dev_priv->rps.up_threshold = threshold_up;
4932 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4933 dev_priv->rps.last_adj = 0;
4934}
4935
2876ce73
CW		 4936static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4937{
4938 u32 mask = 0;
4939
4940 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4941 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4942 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4943 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4944
7b3c29f6
CW		 4945 mask &= dev_priv->pm_rps_events;
4946
59d02a1f 4947 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4948}
4949
b8a5ff8d
JM		 4950/* gen6_set_rps is called to update the frequency request, but should also be
4951 * called when the range (min_delay and max_delay) is modified so that we can
4952 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4953static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4954{
23eafea6 4955 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4956 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4957 return;
4958
4fc688ce 4959 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4960 WARN_ON(val > dev_priv->rps.max_freq);
4961 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4962
eb64cad1
CW		 4963 /* min/max delay may still have been modified so be sure to
4964 * write the limits value.
4965 */
4966 if (val != dev_priv->rps.cur_freq) {
4967 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4968
dc97997a 4969 if (IS_GEN9(dev_priv))
5704195c
AG		 4970 I915_WRITE(GEN6_RPNSWREQ,
4971 GEN9_FREQUENCY(val));
dc97997a 4972 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4973 I915_WRITE(GEN6_RPNSWREQ,
4974 HSW_FREQUENCY(val));
4975 else
4976 I915_WRITE(GEN6_RPNSWREQ,
4977 GEN6_FREQUENCY(val) |
4978 GEN6_OFFSET(0) |
4979 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4980 }
7b9e0ae6 4981
7b9e0ae6
CW		 4982 /* Make sure we continue to get interrupts
4983 * until we hit the minimum or maximum frequencies.
4984 */
74ef1173 4985 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4986 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4987
d5570a72
BW		 4988 POSTING_READ(GEN6_RPNSWREQ);
4989
b39fb297 4990 dev_priv->rps.cur_freq = val;
0f94592e 4991 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4992}
4993
dc97997a 4994static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4995{
ffe02b40 4996 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4997 WARN_ON(val > dev_priv->rps.max_freq);
4998 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4999
dc97997a 5000 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 5001 "Odd GPU freq value\n"))
5002 val &= ~1;
5003
cd25dd5b
D		 5004 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
5005
8fb55197 5006 if (val != dev_priv->rps.cur_freq) {
ffe02b40 5007 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 5008 if (!IS_CHERRYVIEW(dev_priv))
5009 gen6_set_rps_thresholds(dev_priv, val);
5010 }
ffe02b40 5011
ffe02b40
VS		 5012 dev_priv->rps.cur_freq = val;
5013 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5014}
5015
a7f6e231 5016/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5017 *
5018 * * If Gfx is Idle, then
a7f6e231
D		 5019 * 1. Forcewake Media well.
5020 * 2. Request idle freq.
5021 * 3. Release Forcewake of Media well.
76c3552f
D		 5022*/
5023static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5024{
aed242ff 5025 u32 val = dev_priv->rps.idle_freq;
5549d25f 5026
aed242ff 5027 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5028 return;
5029
a7f6e231
D		 5030 /* Wake up the media well, as that takes a lot less
5031 * power than the Render well. */
5032 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5033 valleyview_set_rps(dev_priv, val);
a7f6e231 5034 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5035}
5036
43cf3bf0
CW		 5037void gen6_rps_busy(struct drm_i915_private *dev_priv)
5038{
5039 mutex_lock(&dev_priv->rps.hw_lock);
5040 if (dev_priv->rps.enabled) {
5041 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5042 gen6_rps_reset_ei(dev_priv);
5043 I915_WRITE(GEN6_PMINTRMSK,
5044 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5045
c33d247d
CW		 5046 gen6_enable_rps_interrupts(dev_priv);
5047
2b83c4c4
MW		 5048 /* Ensure we start at the user's desired frequency */
5049 intel_set_rps(dev_priv,
5050 clamp(dev_priv->rps.cur_freq,
5051 dev_priv->rps.min_freq_softlimit,
5052 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5053 }
5054 mutex_unlock(&dev_priv->rps.hw_lock);
5055}
5056
b29c19b6
CW		 5057void gen6_rps_idle(struct drm_i915_private *dev_priv)
5058{
c33d247d
CW		 5059 /* Flush our bottom-half so that it does not race with us
5060 * setting the idle frequency and so that it is bounded by
5061 * our rpm wakeref. And then disable the interrupts to stop any
5062 * futher RPS reclocking whilst we are asleep.
5063 */
5064 gen6_disable_rps_interrupts(dev_priv);
5065
b29c19b6 5066 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5067 if (dev_priv->rps.enabled) {
dc97997a 5068 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5069 vlv_set_rps_idle(dev_priv);
7526ed79 5070 else
dc97997a 5071 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5072 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5073 I915_WRITE(GEN6_PMINTRMSK,
5074 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5075 }
8d3afd7d 5076 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5077
8d3afd7d 5078 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5079 while (!list_empty(&dev_priv->rps.clients))
5080 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5081 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5082}
5083
1854d5ca 5084void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5085 struct intel_rps_client *rps,
5086 unsigned long submitted)
b29c19b6 5087{
8d3afd7d
CW		 5088 /* This is intentionally racy! We peek at the state here, then
5089 * validate inside the RPS worker.
5090 */
67d97da3 5091 if (!(dev_priv->gt.awake &&
8d3afd7d 5092 dev_priv->rps.enabled &&
29ecd78d 5093 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5094 return;
43cf3bf0 5095
e61b9958
CW		 5096 /* Force a RPS boost (and don't count it against the client) if
5097 * the GPU is severely congested.
5098 */
d0bc54f2 5099 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5100 rps = NULL;
5101
8d3afd7d
CW		 5102 spin_lock(&dev_priv->rps.client_lock);
5103 if (rps == NULL || list_empty(&rps->link)) {
5104 spin_lock_irq(&dev_priv->irq_lock);
5105 if (dev_priv->rps.interrupts_enabled) {
5106 dev_priv->rps.client_boost = true;
c33d247d 5107 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5108 }
5109 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5110
2e1b8730
CW		 5111 if (rps != NULL) {
5112 list_add(&rps->link, &dev_priv->rps.clients);
5113 rps->boosts++;
1854d5ca
CW		 5114 } else
5115 dev_priv->rps.boosts++;
c0951f0c 5116 }
8d3afd7d 5117 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5118}
5119
dc97997a 5120void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5121{
dc97997a
CW		 5122 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5123 valleyview_set_rps(dev_priv, val);
ffe02b40 5124 else
dc97997a 5125 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5126}
5127
dc97997a 5128static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5129{
20e49366 5130 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5131 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5132}
5133
dc97997a 5134static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5135{
2030d684
AG		 5136 I915_WRITE(GEN6_RP_CONTROL, 0);
5137}
5138
dc97997a 5139static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5140{
d20d4f0c 5141 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5142 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5143 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5144}
5145
dc97997a 5146static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5147{
38807746
D		 5148 I915_WRITE(GEN6_RC_CONTROL, 0);
5149}
5150
dc97997a 5151static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5152{
98a2e5f9
D		 5153 /* we're doing forcewake before Disabling RC6,
5154 * This what the BIOS expects when going into suspend */
59bad947 5155 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5156
44fc7d5c 5157 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5158
59bad947 5159 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5160}
5161
dc97997a 5162static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5163{
dc97997a 5164 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5165 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5166 mode = GEN6_RC_CTL_RC6_ENABLE;
5167 else
5168 mode = 0;
5169 }
dc97997a 5170 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5171 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5172 "RC6 %s RC6p %s RC6pp %s\n",
5173 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5174 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5175 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5176
5177 else
b99d49cc
ID		 5178 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5179 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5180}
5181
dc97997a 5182static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5183{
72e96d64 5184 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5185 bool enable_rc6 = true;
5186 unsigned long rc6_ctx_base;
fc619841
ID		 5187 u32 rc_ctl;
5188 int rc_sw_target;
5189
5190 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5191 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5192 RC_SW_TARGET_STATE_SHIFT;
5193 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5194 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5195 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5196 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5197 rc_sw_target);
274008e8
SAK		 5198
5199 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5200 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5201 enable_rc6 = false;
5202 }
5203
5204 /*
5205 * The exact context size is not known for BXT, so assume a page size
5206 * for this check.
5207 */
5208 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5209 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5210 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5211 ggtt->stolen_reserved_size))) {
b99d49cc 5212 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5213 enable_rc6 = false;
5214 }
5215
5216 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5217 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5218 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5219 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5220 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5221 enable_rc6 = false;
5222 }
5223
fc619841
ID		 5224 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5225 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5226 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5227 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5228 enable_rc6 = false;
5229 }
5230
5231 if (!I915_READ(GEN6_GFXPAUSE)) {
5232 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5233 enable_rc6 = false;
5234 }
5235
5236 if (!I915_READ(GEN8_MISC_CTRL0)) {
5237 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5238 enable_rc6 = false;
5239 }
5240
5241 return enable_rc6;
5242}
5243
dc97997a 5244int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5245{
e7d66d89 5246 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5247 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5248 return 0;
5249
274008e8
SAK		 5250 if (!enable_rc6)
5251 return 0;
5252
dc97997a 5253 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5254 DRM_INFO("RC6 disabled by BIOS\n");
5255 return 0;
5256 }
5257
456470eb 5258 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5259 if (enable_rc6 >= 0) {
5260 int mask;
5261
dc97997a 5262 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5263 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5264 INTEL_RC6pp_ENABLE;
5265 else
5266 mask = INTEL_RC6_ENABLE;
5267
5268 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5269 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5270 "(requested %d, valid %d)\n",
5271 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5272
5273 return enable_rc6 & mask;
5274 }
2b4e57bd 5275
dc97997a 5276 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5277 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5278
5279 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5280}
5281
dc97997a 5282static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5283{
5284 /* All of these values are in units of 50MHz */
773ea9a8 5285
93ee2920 5286 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5287 if (IS_BROXTON(dev_priv)) {
773ea9a8 5288 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5289 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5290 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5291 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5292 } else {
773ea9a8 5293 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5294 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5295 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5296 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5297 }
3280e8b0 5298 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5299 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5300
93ee2920 5301 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5302 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5303 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5304 u32 ddcc_status = 0;
5305
5306 if (sandybridge_pcode_read(dev_priv,
5307 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5308 &ddcc_status) == 0)
93ee2920 5309 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5310 clamp_t(u8,
5311 ((ddcc_status >> 8) & 0xff),
5312 dev_priv->rps.min_freq,
5313 dev_priv->rps.max_freq);
93ee2920
TR		 5314 }
5315
dc97997a 5316 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5317 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5318 * the natural hardware unit for SKL
5319 */
c5e0688c
AG		 5320 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5321 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5322 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5323 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5324 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5325 }
3280e8b0
BW		 5326}
5327
3a45b05c
CW		 5328static void reset_rps(struct drm_i915_private *dev_priv,
5329 void (*set)(struct drm_i915_private *, u8))
5330{
5331 u8 freq = dev_priv->rps.cur_freq;
5332
5333 /* force a reset */
5334 dev_priv->rps.power = -1;
5335 dev_priv->rps.cur_freq = -1;
5336
5337 set(dev_priv, freq);
5338}
5339
b6fef0ef 5340/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5341static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5342{
b6fef0ef
JB		 5343 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5344
23eafea6 5345 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5346 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5347 /*
5348 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5349 * clear out the Control register just to avoid inconsitency
5350 * with debugfs interface, which will show Turbo as enabled
5351 * only and that is not expected by the User after adding the
5352 * WaGsvDisableTurbo. Apart from this there is no problem even
5353 * if the Turbo is left enabled in the Control register, as the
5354 * Up/Down interrupts would remain masked.
5355 */
dc97997a 5356 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5357 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5358 return;
5359 }
5360
0beb059a
AG		 5361 /* Program defaults and thresholds for RPS*/
5362 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5363 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5364
5365 /* 1 second timeout*/
5366 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5367 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5368
b6fef0ef 5369 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5370
0beb059a
AG		 5371 /* Leaning on the below call to gen6_set_rps to program/setup the
5372 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5373 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5374 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5375
5376 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5377}
5378
dc97997a 5379static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5380{
e2f80391 5381 struct intel_engine_cs *engine;
3b3f1650 5382 enum intel_engine_id id;
20e49366 5383 uint32_t rc6_mask = 0;
20e49366
ZW		 5384
5385 /* 1a: Software RC state - RC0 */
5386 I915_WRITE(GEN6_RC_STATE, 0);
5387
5388 /* 1b: Get forcewake during program sequence. Although the driver
5389 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5390 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5391
5392 /* 2a: Disable RC states. */
5393 I915_WRITE(GEN6_RC_CONTROL, 0);
5394
5395 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5396
5397 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5398 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5399 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5400 else
5401 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5402 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5403 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5404 for_each_engine(engine, dev_priv, id)
e2f80391 5405 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5406
1a3d1898 5407 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5408 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5409
20e49366 5410 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5411
38c23527
ZW		 5412 /* 2c: Program Coarse Power Gating Policies. */
5413 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5414 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5415
20e49366 5416 /* 3a: Enable RC6 */
dc97997a 5417 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5418 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5419 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5420 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5421 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5422 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5423 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5424 GEN7_RC_CTL_TO_MODE |
5425 rc6_mask);
3e7732a0
SAK		 5426 } else {
5427 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5428 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5429 GEN6_RC_CTL_EI_MODE(1) |
5430 rc6_mask);
3e7732a0 5431 }
20e49366 5432
cb07bae0
SK		 5433 /*
5434 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5435 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5436 */
dc97997a 5437 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5438 I915_WRITE(GEN9_PG_ENABLE, 0);
5439 else
5440 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5441 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5442
59bad947 5443 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5444}
5445
dc97997a 5446static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5447{
e2f80391 5448 struct intel_engine_cs *engine;
3b3f1650 5449 enum intel_engine_id id;
93ee2920 5450 uint32_t rc6_mask = 0;
6edee7f3
BW		 5451
5452 /* 1a: Software RC state - RC0 */
5453 I915_WRITE(GEN6_RC_STATE, 0);
5454
5455 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5456 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5457 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5458
5459 /* 2a: Disable RC states. */
5460 I915_WRITE(GEN6_RC_CONTROL, 0);
5461
6edee7f3
BW		 5462 /* 2b: Program RC6 thresholds.*/
5463 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5464 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5465 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5466 for_each_engine(engine, dev_priv, id)
e2f80391 5467 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5468 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5469 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5470 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5471 else
5472 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5473
5474 /* 3: Enable RC6 */
dc97997a 5475 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5476 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5477 intel_print_rc6_info(dev_priv, rc6_mask);
5478 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5479 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5480 GEN7_RC_CTL_TO_MODE |
5481 rc6_mask);
5482 else
5483 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5484 GEN6_RC_CTL_EI_MODE(1) |
5485 rc6_mask);
6edee7f3
BW		 5486
5487 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5488 I915_WRITE(GEN6_RPNSWREQ,
5489 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5490 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5491 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5492 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5493 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5494
5495 /* Docs recommend 900MHz, and 300 MHz respectively */
5496 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5497 dev_priv->rps.max_freq_softlimit << 24 |
5498 dev_priv->rps.min_freq_softlimit << 16);
5499
5500 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5501 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5502 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5503 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5504
5505 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5506
5507 /* 5: Enable RPS */
7526ed79
DV		 5508 I915_WRITE(GEN6_RP_CONTROL,
5509 GEN6_RP_MEDIA_TURBO |
5510 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5511 GEN6_RP_MEDIA_IS_GFX |
5512 GEN6_RP_ENABLE |
5513 GEN6_RP_UP_BUSY_AVG |
5514 GEN6_RP_DOWN_IDLE_AVG);
5515
5516 /* 6: Ring frequency + overclocking (our driver does this later */
5517
3a45b05c 5518 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5519
59bad947 5520 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5521}
5522
dc97997a 5523static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5524{
e2f80391 5525 struct intel_engine_cs *engine;
3b3f1650 5526 enum intel_engine_id id;
99ac9612 5527 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5528 u32 gtfifodbg;
2b4e57bd 5529 int rc6_mode;
b4ac5afc 5530 int ret;
2b4e57bd 5531
4fc688ce 5532 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5533
2b4e57bd
ED		 5534 /* Here begins a magic sequence of register writes to enable
5535 * auto-downclocking.
5536 *
5537 * Perhaps there might be some value in exposing these to
5538 * userspace...
5539 */
5540 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5541
5542 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5543 gtfifodbg = I915_READ(GTFIFODBG);
5544 if (gtfifodbg) {
2b4e57bd
ED		 5545 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5546 I915_WRITE(GTFIFODBG, gtfifodbg);
5547 }
5548
59bad947 5549 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5550
5551 /* disable the counters and set deterministic thresholds */
5552 I915_WRITE(GEN6_RC_CONTROL, 0);
5553
5554 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5555 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5556 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5557 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5558 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5559
3b3f1650 5560 for_each_engine(engine, dev_priv, id)
e2f80391 5561 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5562
5563 I915_WRITE(GEN6_RC_SLEEP, 0);
5564 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5565 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5566 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5567 else
5568 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5569 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5570 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5571
5a7dc92a 5572 /* Check if we are enabling RC6 */
dc97997a 5573 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5574 if (rc6_mode & INTEL_RC6_ENABLE)
5575 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5576
5a7dc92a 5577 /* We don't use those on Haswell */
dc97997a 5578 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5579 if (rc6_mode & INTEL_RC6p_ENABLE)
5580 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5581
5a7dc92a
ED		 5582 if (rc6_mode & INTEL_RC6pp_ENABLE)
5583 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5584 }
2b4e57bd 5585
dc97997a 5586 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5587
5588 I915_WRITE(GEN6_RC_CONTROL,
5589 rc6_mask |
5590 GEN6_RC_CTL_EI_MODE(1) |
5591 GEN6_RC_CTL_HW_ENABLE);
5592
dd75fdc8
CW		 5593 /* Power down if completely idle for over 50ms */
5594 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5595 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5596
3a45b05c 5597 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5598
31643d54
BW		 5599 rc6vids = 0;
5600 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5601 if (IS_GEN6(dev_priv) && ret) {
31643d54 5602 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5603 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5604 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5605 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5606 rc6vids &= 0xffff00;
5607 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5608 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5609 if (ret)
5610 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5611 }
5612
59bad947 5613 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5614}
5615
fb7404e8 5616static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5617{
5618 int min_freq = 15;
3ebecd07
CW		 5619 unsigned int gpu_freq;
5620 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5621 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5622 int scaling_factor = 180;
eda79642 5623 struct cpufreq_policy *policy;
2b4e57bd 5624
4fc688ce 5625 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5626
eda79642
BW		 5627 policy = cpufreq_cpu_get(0);
5628 if (policy) {
5629 max_ia_freq = policy->cpuinfo.max_freq;
5630 cpufreq_cpu_put(policy);
5631 } else {
5632 /*
5633 * Default to measured freq if none found, PCU will ensure we
5634 * don't go over
5635 */
2b4e57bd 5636 max_ia_freq = tsc_khz;
eda79642 5637 }
2b4e57bd
ED		 5638
5639 /* Convert from kHz to MHz */
5640 max_ia_freq /= 1000;
5641
153b4b95 5642 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5643 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5644 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5645
dc97997a 5646 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5647 /* Convert GT frequency to 50 HZ units */
5648 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5649 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5650 } else {
5651 min_gpu_freq = dev_priv->rps.min_freq;
5652 max_gpu_freq = dev_priv->rps.max_freq;
5653 }
5654
2b4e57bd
ED		 5655 /*
5656 * For each potential GPU frequency, load a ring frequency we'd like
5657 * to use for memory access. We do this by specifying the IA frequency
5658 * the PCU should use as a reference to determine the ring frequency.
5659 */
4c8c7743
AG		 5660 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5661 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5662 unsigned int ia_freq = 0, ring_freq = 0;
5663
dc97997a 5664 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5665 /*
5666 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5667 * No floor required for ring frequency on SKL.
5668 */
5669 ring_freq = gpu_freq;
dc97997a 5670 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5671 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5672 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5673 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5674 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5675 ring_freq = max(min_ring_freq, ring_freq);
5676 /* leave ia_freq as the default, chosen by cpufreq */
5677 } else {
5678 /* On older processors, there is no separate ring
5679 * clock domain, so in order to boost the bandwidth
5680 * of the ring, we need to upclock the CPU (ia_freq).
5681 *
5682 * For GPU frequencies less than 750MHz,
5683 * just use the lowest ring freq.
5684 */
5685 if (gpu_freq < min_freq)
5686 ia_freq = 800;
5687 else
5688 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5689 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5690 }
2b4e57bd 5691
42c0526c
BW		 5692 sandybridge_pcode_write(dev_priv,
5693 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5694 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5695 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5696 gpu_freq);
2b4e57bd 5697 }
2b4e57bd
ED		 5698}
5699
03af2045 5700static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5701{
5702 u32 val, rp0;
5703
5b5929cb 5704 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5705
43b67998 5706 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5707 case 8:
5708 /* (2 * 4) config */
5709 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5710 break;
5711 case 12:
5712 /* (2 * 6) config */
5713 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5714 break;
5715 case 16:
5716 /* (2 * 8) config */
5717 default:
5718 /* Setting (2 * 8) Min RP0 for any other combination */
5719 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5720 break;
095acd5f 5721 }
5b5929cb
JN		 5722
5723 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5724
2b6b3a09
D		 5725 return rp0;
5726}
5727
5728static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5729{
5730 u32 val, rpe;
5731
5732 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5733 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5734
5735 return rpe;
5736}
5737
7707df4a
D		 5738static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5739{
5740 u32 val, rp1;
5741
5b5929cb
JN		 5742 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5743 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5744
7707df4a
D		 5745 return rp1;
5746}
5747
f8f2b001
D		 5748static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5749{
5750 u32 val, rp1;
5751
5752 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5753
5754 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5755
5756 return rp1;
5757}
5758
03af2045 5759static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5760{
5761 u32 val, rp0;
5762
64936258 5763 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5764
5765 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5766 /* Clamp to max */
5767 rp0 = min_t(u32, rp0, 0xea);
5768
5769 return rp0;
5770}
5771
5772static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5773{
5774 u32 val, rpe;
5775
64936258 5776 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5777 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5778 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5779 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5780
5781 return rpe;
5782}
5783
03af2045 5784static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5785{
36146035
ID		 5786 u32 val;
5787
5788 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5789 /*
5790 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5791 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5792 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5793 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5794 * to make sure it matches what Punit accepts.
5795 */
5796 return max_t(u32, val, 0xc0);
0a073b84
JB		 5797}
5798
ae48434c
ID		 5799/* Check that the pctx buffer wasn't move under us. */
5800static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5801{
5802 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5803
5804 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5805 dev_priv->vlv_pctx->stolen->start);
5806}
5807
38807746
D		 5808
5809/* Check that the pcbr address is not empty. */
5810static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5811{
5812 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5813
5814 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5815}
5816
dc97997a 5817static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5818{
62106b4f 5819 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5820 unsigned long pctx_paddr, paddr;
38807746
D		 5821 u32 pcbr;
5822 int pctx_size = 32*1024;
5823
38807746
D		 5824 pcbr = I915_READ(VLV_PCBR);
5825 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5826 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5827 paddr = (dev_priv->mm.stolen_base +
62106b4f 5828 (ggtt->stolen_size - pctx_size));
38807746
D		 5829
5830 pctx_paddr = (paddr & (~4095));
5831 I915_WRITE(VLV_PCBR, pctx_paddr);
5832 }
ce611ef8
VS		 5833
5834 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5835}
5836
dc97997a 5837static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5838{
c9cddffc
JB		 5839 struct drm_i915_gem_object *pctx;
5840 unsigned long pctx_paddr;
5841 u32 pcbr;
5842 int pctx_size = 24*1024;
5843
5844 pcbr = I915_READ(VLV_PCBR);
5845 if (pcbr) {
5846 /* BIOS set it up already, grab the pre-alloc'd space */
5847 int pcbr_offset;
5848
5849 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5850 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5851 pcbr_offset,
190d6cd5 5852 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5853 pctx_size);
5854 goto out;
5855 }
5856
ce611ef8
VS		 5857 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5858
c9cddffc
JB		 5859 /*
5860 * From the Gunit register HAS:
5861 * The Gfx driver is expected to program this register and ensure
5862 * proper allocation within Gfx stolen memory. For example, this
5863 * register should be programmed such than the PCBR range does not
5864 * overlap with other ranges, such as the frame buffer, protected
5865 * memory, or any other relevant ranges.
5866 */
91c8a326 5867 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5868 if (!pctx) {
5869 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5870 goto out;
c9cddffc
JB		 5871 }
5872
5873 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5874 I915_WRITE(VLV_PCBR, pctx_paddr);
5875
5876out:
ce611ef8 5877 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5878 dev_priv->vlv_pctx = pctx;
5879}
5880
dc97997a 5881static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5882{
ae48434c
ID		 5883 if (WARN_ON(!dev_priv->vlv_pctx))
5884 return;
5885
f0cd5182 5886 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5887 dev_priv->vlv_pctx = NULL;
5888}
5889
c30fec65
VS		 5890static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5891{
5892 dev_priv->rps.gpll_ref_freq =
5893 vlv_get_cck_clock(dev_priv, "GPLL ref",
5894 CCK_GPLL_CLOCK_CONTROL,
5895 dev_priv->czclk_freq);
5896
5897 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5898 dev_priv->rps.gpll_ref_freq);
5899}
5900
dc97997a 5901static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5902{
2bb25c17 5903 u32 val;
4e80519e 5904
dc97997a 5905 valleyview_setup_pctx(dev_priv);
4e80519e 5906
c30fec65
VS		 5907 vlv_init_gpll_ref_freq(dev_priv);
5908
2bb25c17
VS		 5909 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5910 switch ((val >> 6) & 3) {
5911 case 0:
5912 case 1:
5913 dev_priv->mem_freq = 800;
5914 break;
5915 case 2:
5916 dev_priv->mem_freq = 1066;
5917 break;
5918 case 3:
5919 dev_priv->mem_freq = 1333;
5920 break;
5921 }
80b83b62 5922 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5923
4e80519e
ID		 5924 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5925 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5926 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5927 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5928 dev_priv->rps.max_freq);
5929
5930 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5931 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5932 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5933 dev_priv->rps.efficient_freq);
5934
f8f2b001
D		 5935 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5936 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5937 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5938 dev_priv->rps.rp1_freq);
5939
4e80519e
ID		 5940 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5941 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5942 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5943 dev_priv->rps.min_freq);
4e80519e
ID		 5944}
5945
dc97997a 5946static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5947{
2bb25c17 5948 u32 val;
2b6b3a09 5949
dc97997a 5950 cherryview_setup_pctx(dev_priv);
2b6b3a09 5951
c30fec65
VS		 5952 vlv_init_gpll_ref_freq(dev_priv);
5953
a580516d 5954 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5955 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5956 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5957
2bb25c17 5958 switch ((val >> 2) & 0x7) {
2bb25c17 5959 case 3:
2bb25c17
VS		 5960 dev_priv->mem_freq = 2000;
5961 break;
bfa7df01 5962 default:
2bb25c17
VS		 5963 dev_priv->mem_freq = 1600;
5964 break;
5965 }
80b83b62 5966 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5967
2b6b3a09
D		 5968 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5969 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5970 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5971 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5972 dev_priv->rps.max_freq);
5973
5974 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5975 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5976 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5977 dev_priv->rps.efficient_freq);
5978
7707df4a
D		 5979 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5980 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5981 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5982 dev_priv->rps.rp1_freq);
5983
5b7c91b7
D		 5984 /* PUnit validated range is only [RPe, RP0] */
5985 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5986 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5987 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5988 dev_priv->rps.min_freq);
5989
1c14762d
VS		 5990 WARN_ONCE((dev_priv->rps.max_freq |
5991 dev_priv->rps.efficient_freq |
5992 dev_priv->rps.rp1_freq |
5993 dev_priv->rps.min_freq) & 1,
5994 "Odd GPU freq values\n");
38807746
D		 5995}
5996
dc97997a 5997static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5998{
dc97997a 5999 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 6000}
6001
dc97997a 6002static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 6003{
e2f80391 6004 struct intel_engine_cs *engine;
3b3f1650 6005 enum intel_engine_id id;
2b6b3a09 6006 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 6007
6008 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6009
297b32ec
VS		 6010 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6011 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 6012 if (gtfifodbg) {
6013 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6014 gtfifodbg);
6015 I915_WRITE(GTFIFODBG, gtfifodbg);
6016 }
6017
6018 cherryview_check_pctx(dev_priv);
6019
6020 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6021 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6022 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6023
160614a2
VS		 6024 /* Disable RC states. */
6025 I915_WRITE(GEN6_RC_CONTROL, 0);
6026
38807746
D		 6027 /* 2a: Program RC6 thresholds.*/
6028 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6029 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6030 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6031
3b3f1650 6032 for_each_engine(engine, dev_priv, id)
e2f80391 6033 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6034 I915_WRITE(GEN6_RC_SLEEP, 0);
6035
f4f71c7d
D		 6036 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6037 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6038
6039 /* allows RC6 residency counter to work */
6040 I915_WRITE(VLV_COUNTER_CONTROL,
6041 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6042 VLV_MEDIA_RC6_COUNT_EN |
6043 VLV_RENDER_RC6_COUNT_EN));
6044
6045 /* For now we assume BIOS is allocating and populating the PCBR */
6046 pcbr = I915_READ(VLV_PCBR);
6047
38807746 6048 /* 3: Enable RC6 */
dc97997a
CW		 6049 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6050 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6051 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6052
6053 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6054
2b6b3a09 6055 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6056 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6057 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6058 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6059 I915_WRITE(GEN6_RP_UP_EI, 66000);
6060 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6061
6062 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6063
6064 /* 5: Enable RPS */
6065 I915_WRITE(GEN6_RP_CONTROL,
6066 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6067 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6068 GEN6_RP_ENABLE |
6069 GEN6_RP_UP_BUSY_AVG |
6070 GEN6_RP_DOWN_IDLE_AVG);
6071
3ef62342
D		 6072 /* Setting Fixed Bias */
6073 val = VLV_OVERRIDE_EN |
6074 VLV_SOC_TDP_EN |
6075 CHV_BIAS_CPU_50_SOC_50;
6076 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6077
2b6b3a09
D		 6078 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6079
8d40c3ae
VS		 6080 /* RPS code assumes GPLL is used */
6081 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6082
742f491d 6083 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6084 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6085
3a45b05c 6086 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6087
59bad947 6088 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6089}
6090
dc97997a 6091static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6092{
e2f80391 6093 struct intel_engine_cs *engine;
3b3f1650 6094 enum intel_engine_id id;
2a5913a8 6095 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6096
6097 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6098
ae48434c
ID		 6099 valleyview_check_pctx(dev_priv);
6100
297b32ec
VS		 6101 gtfifodbg = I915_READ(GTFIFODBG);
6102 if (gtfifodbg) {
f7d85c1e
JB		 6103 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6104 gtfifodbg);
0a073b84
JB		 6105 I915_WRITE(GTFIFODBG, gtfifodbg);
6106 }
6107
c8d9a590 6108 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6109 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6110
160614a2
VS		 6111 /* Disable RC states. */
6112 I915_WRITE(GEN6_RC_CONTROL, 0);
6113
cad725fe 6114 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6115 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6116 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6117 I915_WRITE(GEN6_RP_UP_EI, 66000);
6118 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6119
6120 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6121
6122 I915_WRITE(GEN6_RP_CONTROL,
6123 GEN6_RP_MEDIA_TURBO |
6124 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6125 GEN6_RP_MEDIA_IS_GFX |
6126 GEN6_RP_ENABLE |
6127 GEN6_RP_UP_BUSY_AVG |
6128 GEN6_RP_DOWN_IDLE_CONT);
6129
6130 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6131 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6132 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6133
3b3f1650 6134 for_each_engine(engine, dev_priv, id)
e2f80391 6135 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6136
2f0aa304 6137 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6138
6139 /* allows RC6 residency counter to work */
49798eb2 6140 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6141 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6142 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6143 VLV_MEDIA_RC6_COUNT_EN |
6144 VLV_RENDER_RC6_COUNT_EN));
31685c25 6145
dc97997a 6146 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6147 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6148
dc97997a 6149 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6150
a2b23fe0 6151 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6152
3ef62342
D		 6153 /* Setting Fixed Bias */
6154 val = VLV_OVERRIDE_EN |
6155 VLV_SOC_TDP_EN |
6156 VLV_BIAS_CPU_125_SOC_875;
6157 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6158
64936258 6159 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6160
8d40c3ae
VS		 6161 /* RPS code assumes GPLL is used */
6162 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6163
742f491d 6164 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6165 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6166
3a45b05c 6167 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6168
59bad947 6169 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6170}
6171
dde18883
ED		 6172static unsigned long intel_pxfreq(u32 vidfreq)
6173{
6174 unsigned long freq;
6175 int div = (vidfreq & 0x3f0000) >> 16;
6176 int post = (vidfreq & 0x3000) >> 12;
6177 int pre = (vidfreq & 0x7);
6178
6179 if (!pre)
6180 return 0;
6181
6182 freq = ((div * 133333) / ((1<<post) * pre));
6183
6184 return freq;
6185}
6186
eb48eb00
DV		 6187static const struct cparams {
6188 u16 i;
6189 u16 t;
6190 u16 m;
6191 u16 c;
6192} cparams[] = {
6193 { 1, 1333, 301, 28664 },
6194 { 1, 1066, 294, 24460 },
6195 { 1, 800, 294, 25192 },
6196 { 0, 1333, 276, 27605 },
6197 { 0, 1066, 276, 27605 },
6198 { 0, 800, 231, 23784 },
6199};
6200
f531dcb2 6201static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6202{
6203 u64 total_count, diff, ret;
6204 u32 count1, count2, count3, m = 0, c = 0;
6205 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6206 int i;
6207
02d71956
DV		 6208 assert_spin_locked(&mchdev_lock);
6209
20e4d407 6210 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6211
6212 /* Prevent division-by-zero if we are asking too fast.
6213 * Also, we don't get interesting results if we are polling
6214 * faster than once in 10ms, so just return the saved value
6215 * in such cases.
6216 */
6217 if (diff1 <= 10)
20e4d407 6218 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6219
6220 count1 = I915_READ(DMIEC);
6221 count2 = I915_READ(DDREC);
6222 count3 = I915_READ(CSIEC);
6223
6224 total_count = count1 + count2 + count3;
6225
6226 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6227 if (total_count < dev_priv->ips.last_count1) {
6228 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6229 diff += total_count;
6230 } else {
20e4d407 6231 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6232 }
6233
6234 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6235 if (cparams[i].i == dev_priv->ips.c_m &&
6236 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6237 m = cparams[i].m;
6238 c = cparams[i].c;
6239 break;
6240 }
6241 }
6242
6243 diff = div_u64(diff, diff1);
6244 ret = ((m * diff) + c);
6245 ret = div_u64(ret, 10);
6246
20e4d407
DV		 6247 dev_priv->ips.last_count1 = total_count;
6248 dev_priv->ips.last_time1 = now;
eb48eb00 6249
20e4d407 6250 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6251
6252 return ret;
6253}
6254
f531dcb2
CW		 6255unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6256{
6257 unsigned long val;
6258
dc97997a 6259 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6260 return 0;
6261
6262 spin_lock_irq(&mchdev_lock);
6263
6264 val = __i915_chipset_val(dev_priv);
6265
6266 spin_unlock_irq(&mchdev_lock);
6267
6268 return val;
6269}
6270
eb48eb00
DV		 6271unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6272{
6273 unsigned long m, x, b;
6274 u32 tsfs;
6275
6276 tsfs = I915_READ(TSFS);
6277
6278 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6279 x = I915_READ8(TR1);
6280
6281 b = tsfs & TSFS_INTR_MASK;
6282
6283 return ((m * x) / 127) - b;
6284}
6285
d972d6ee
MK		 6286static int _pxvid_to_vd(u8 pxvid)
6287{
6288 if (pxvid == 0)
6289 return 0;
6290
6291 if (pxvid >= 8 && pxvid < 31)
6292 pxvid = 31;
6293
6294 return (pxvid + 2) * 125;
6295}
6296
6297static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6298{
d972d6ee
MK		 6299 const int vd = _pxvid_to_vd(pxvid);
6300 const int vm = vd - 1125;
6301
dc97997a 6302 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6303 return vm > 0 ? vm : 0;
6304
6305 return vd;
eb48eb00
DV		 6306}
6307
02d71956 6308static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6309{
5ed0bdf2 6310 u64 now, diff, diffms;
eb48eb00
DV		 6311 u32 count;
6312
02d71956 6313 assert_spin_locked(&mchdev_lock);
eb48eb00 6314
5ed0bdf2
TG		 6315 now = ktime_get_raw_ns();
6316 diffms = now - dev_priv->ips.last_time2;
6317 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6318
6319 /* Don't divide by 0 */
eb48eb00
DV		 6320 if (!diffms)
6321 return;
6322
6323 count = I915_READ(GFXEC);
6324
20e4d407
DV		 6325 if (count < dev_priv->ips.last_count2) {
6326 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6327 diff += count;
6328 } else {
20e4d407 6329 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6330 }
6331
20e4d407
DV		 6332 dev_priv->ips.last_count2 = count;
6333 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6334
6335 /* More magic constants... */
6336 diff = diff * 1181;
6337 diff = div_u64(diff, diffms * 10);
20e4d407 6338 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6339}
6340
02d71956
DV		 6341void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6342{
dc97997a 6343 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6344 return;
6345
9270388e 6346 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6347
6348 __i915_update_gfx_val(dev_priv);
6349
9270388e 6350 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6351}
6352
f531dcb2 6353static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6354{
6355 unsigned long t, corr, state1, corr2, state2;
6356 u32 pxvid, ext_v;
6357
02d71956
DV		 6358 assert_spin_locked(&mchdev_lock);
6359
616847e7 6360 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6361 pxvid = (pxvid >> 24) & 0x7f;
6362 ext_v = pvid_to_extvid(dev_priv, pxvid);
6363
6364 state1 = ext_v;
6365
6366 t = i915_mch_val(dev_priv);
6367
6368 /* Revel in the empirically derived constants */
6369
6370 /* Correction factor in 1/100000 units */
6371 if (t > 80)
6372 corr = ((t * 2349) + 135940);
6373 else if (t >= 50)
6374 corr = ((t * 964) + 29317);
6375 else /* < 50 */
6376 corr = ((t * 301) + 1004);
6377
6378 corr = corr * ((150142 * state1) / 10000 - 78642);
6379 corr /= 100000;
20e4d407 6380 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6381
6382 state2 = (corr2 * state1) / 10000;
6383 state2 /= 100; /* convert to mW */
6384
02d71956 6385 __i915_update_gfx_val(dev_priv);
eb48eb00 6386
20e4d407 6387 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6388}
6389
f531dcb2
CW		 6390unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6391{
6392 unsigned long val;
6393
dc97997a 6394 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6395 return 0;
6396
6397 spin_lock_irq(&mchdev_lock);
6398
6399 val = __i915_gfx_val(dev_priv);
6400
6401 spin_unlock_irq(&mchdev_lock);
6402
6403 return val;
6404}
6405
eb48eb00
DV		 6406/**
6407 * i915_read_mch_val - return value for IPS use
6408 *
6409 * Calculate and return a value for the IPS driver to use when deciding whether
6410 * we have thermal and power headroom to increase CPU or GPU power budget.
6411 */
6412unsigned long i915_read_mch_val(void)
6413{
6414 struct drm_i915_private *dev_priv;
6415 unsigned long chipset_val, graphics_val, ret = 0;
6416
9270388e 6417 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6418 if (!i915_mch_dev)
6419 goto out_unlock;
6420 dev_priv = i915_mch_dev;
6421
f531dcb2
CW		 6422 chipset_val = __i915_chipset_val(dev_priv);
6423 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6424
6425 ret = chipset_val + graphics_val;
6426
6427out_unlock:
9270388e 6428 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6429
6430 return ret;
6431}
6432EXPORT_SYMBOL_GPL(i915_read_mch_val);
6433
6434/**
6435 * i915_gpu_raise - raise GPU frequency limit
6436 *
6437 * Raise the limit; IPS indicates we have thermal headroom.
6438 */
6439bool i915_gpu_raise(void)
6440{
6441 struct drm_i915_private *dev_priv;
6442 bool ret = true;
6443
9270388e 6444 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6445 if (!i915_mch_dev) {
6446 ret = false;
6447 goto out_unlock;
6448 }
6449 dev_priv = i915_mch_dev;
6450
20e4d407
DV		 6451 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6452 dev_priv->ips.max_delay--;
eb48eb00
DV		 6453
6454out_unlock:
9270388e 6455 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6456
6457 return ret;
6458}
6459EXPORT_SYMBOL_GPL(i915_gpu_raise);
6460
6461/**
6462 * i915_gpu_lower - lower GPU frequency limit
6463 *
6464 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6465 * frequency maximum.
6466 */
6467bool i915_gpu_lower(void)
6468{
6469 struct drm_i915_private *dev_priv;
6470 bool ret = true;
6471
9270388e 6472 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6473 if (!i915_mch_dev) {
6474 ret = false;
6475 goto out_unlock;
6476 }
6477 dev_priv = i915_mch_dev;
6478
20e4d407
DV		 6479 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6480 dev_priv->ips.max_delay++;
eb48eb00
DV		 6481
6482out_unlock:
9270388e 6483 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6484
6485 return ret;
6486}
6487EXPORT_SYMBOL_GPL(i915_gpu_lower);
6488
6489/**
6490 * i915_gpu_busy - indicate GPU business to IPS
6491 *
6492 * Tell the IPS driver whether or not the GPU is busy.
6493 */
6494bool i915_gpu_busy(void)
6495{
eb48eb00
DV		 6496 bool ret = false;
6497
9270388e 6498 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6499 if (i915_mch_dev)
6500 ret = i915_mch_dev->gt.awake;
9270388e 6501 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6502
6503 return ret;
6504}
6505EXPORT_SYMBOL_GPL(i915_gpu_busy);
6506
6507/**
6508 * i915_gpu_turbo_disable - disable graphics turbo
6509 *
6510 * Disable graphics turbo by resetting the max frequency and setting the
6511 * current frequency to the default.
6512 */
6513bool i915_gpu_turbo_disable(void)
6514{
6515 struct drm_i915_private *dev_priv;
6516 bool ret = true;
6517
9270388e 6518 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6519 if (!i915_mch_dev) {
6520 ret = false;
6521 goto out_unlock;
6522 }
6523 dev_priv = i915_mch_dev;
6524
20e4d407 6525 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6526
91d14251 6527 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6528 ret = false;
6529
6530out_unlock:
9270388e 6531 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6532
6533 return ret;
6534}
6535EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6536
6537/**
6538 * Tells the intel_ips driver that the i915 driver is now loaded, if
6539 * IPS got loaded first.
6540 *
6541 * This awkward dance is so that neither module has to depend on the
6542 * other in order for IPS to do the appropriate communication of
6543 * GPU turbo limits to i915.
6544 */
6545static void
6546ips_ping_for_i915_load(void)
6547{
6548 void (*link)(void);
6549
6550 link = symbol_get(ips_link_to_i915_driver);
6551 if (link) {
6552 link();
6553 symbol_put(ips_link_to_i915_driver);
6554 }
6555}
6556
6557void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6558{
02d71956
DV		 6559 /* We only register the i915 ips part with intel-ips once everything is
6560 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6561 spin_lock_irq(&mchdev_lock);
eb48eb00 6562 i915_mch_dev = dev_priv;
9270388e 6563 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6564
6565 ips_ping_for_i915_load();
6566}
6567
6568void intel_gpu_ips_teardown(void)
6569{
9270388e 6570 spin_lock_irq(&mchdev_lock);
eb48eb00 6571 i915_mch_dev = NULL;
9270388e 6572 spin_unlock_irq(&mchdev_lock);
eb48eb00 6573}
76c3552f 6574
dc97997a 6575static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6576{
dde18883
ED		 6577 u32 lcfuse;
6578 u8 pxw[16];
6579 int i;
6580
6581 /* Disable to program */
6582 I915_WRITE(ECR, 0);
6583 POSTING_READ(ECR);
6584
6585 /* Program energy weights for various events */
6586 I915_WRITE(SDEW, 0x15040d00);
6587 I915_WRITE(CSIEW0, 0x007f0000);
6588 I915_WRITE(CSIEW1, 0x1e220004);
6589 I915_WRITE(CSIEW2, 0x04000004);
6590
6591 for (i = 0; i < 5; i++)
616847e7 6592 I915_WRITE(PEW(i), 0);
dde18883 6593 for (i = 0; i < 3; i++)
616847e7 6594 I915_WRITE(DEW(i), 0);
dde18883
ED		 6595
6596 /* Program P-state weights to account for frequency power adjustment */
6597 for (i = 0; i < 16; i++) {
616847e7 6598 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6599 unsigned long freq = intel_pxfreq(pxvidfreq);
6600 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6601 PXVFREQ_PX_SHIFT;
6602 unsigned long val;
6603
6604 val = vid * vid;
6605 val *= (freq / 1000);
6606 val *= 255;
6607 val /= (127*127*900);
6608 if (val > 0xff)
6609 DRM_ERROR("bad pxval: %ld\n", val);
6610 pxw[i] = val;
6611 }
6612 /* Render standby states get 0 weight */
6613 pxw[14] = 0;
6614 pxw[15] = 0;
6615
6616 for (i = 0; i < 4; i++) {
6617 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6618 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6619 I915_WRITE(PXW(i), val);
dde18883
ED		 6620 }
6621
6622 /* Adjust magic regs to magic values (more experimental results) */
6623 I915_WRITE(OGW0, 0);
6624 I915_WRITE(OGW1, 0);
6625 I915_WRITE(EG0, 0x00007f00);
6626 I915_WRITE(EG1, 0x0000000e);
6627 I915_WRITE(EG2, 0x000e0000);
6628 I915_WRITE(EG3, 0x68000300);
6629 I915_WRITE(EG4, 0x42000000);
6630 I915_WRITE(EG5, 0x00140031);
6631 I915_WRITE(EG6, 0);
6632 I915_WRITE(EG7, 0);
6633
6634 for (i = 0; i < 8; i++)
616847e7 6635 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6636
6637 /* Enable PMON + select events */
6638 I915_WRITE(ECR, 0x80000019);
6639
6640 lcfuse = I915_READ(LCFUSE02);
6641
20e4d407 6642 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6643}
6644
dc97997a 6645void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6646{
b268c699
ID		 6647 /*
6648 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6649 * requirement.
6650 */
6651 if (!i915.enable_rc6) {
6652 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6653 intel_runtime_pm_get(dev_priv);
6654 }
e6069ca8 6655
b5163dbb 6656 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6657 mutex_lock(&dev_priv->rps.hw_lock);
6658
6659 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6660 if (IS_CHERRYVIEW(dev_priv))
6661 cherryview_init_gt_powersave(dev_priv);
6662 else if (IS_VALLEYVIEW(dev_priv))
6663 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6664 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6665 gen6_init_rps_frequencies(dev_priv);
6666
6667 /* Derive initial user preferences/limits from the hardware limits */
6668 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6669 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6670
6671 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6672 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6673
6674 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6675 dev_priv->rps.min_freq_softlimit =
6676 max_t(int,
6677 dev_priv->rps.efficient_freq,
6678 intel_freq_opcode(dev_priv, 450));
6679
99ac9612
CW		 6680 /* After setting max-softlimit, find the overclock max freq */
6681 if (IS_GEN6(dev_priv) ||
6682 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6683 u32 params = 0;
6684
6685 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6686 if (params & BIT(31)) { /* OC supported */
6687 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6688 (dev_priv->rps.max_freq & 0xff) * 50,
6689 (params & 0xff) * 50);
6690 dev_priv->rps.max_freq = params & 0xff;
6691 }
6692 }
6693
29ecd78d
CW		 6694 /* Finally allow us to boost to max by default */
6695 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6696
773ea9a8 6697 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6698 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6699
6700 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6701}
6702
dc97997a 6703void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6704{
8dac1e1f 6705 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6706 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6707
6708 if (!i915.enable_rc6)
6709 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6710}
6711
54b4f68f
CW		 6712/**
6713 * intel_suspend_gt_powersave - suspend PM work and helper threads
6714 * @dev_priv: i915 device
6715 *
6716 * We don't want to disable RC6 or other features here, we just want
6717 * to make sure any work we've queued has finished and won't bother
6718 * us while we're suspended.
6719 */
6720void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6721{
6722 if (INTEL_GEN(dev_priv) < 6)
6723 return;
6724
6725 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6726 intel_runtime_pm_put(dev_priv);
6727
6728 /* gen6_rps_idle() will be called later to disable interrupts */
6729}
6730
b7137e0c
CW		 6731void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6732{
6733 dev_priv->rps.enabled = true; /* force disabling */
6734 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6735
6736 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6737}
6738
dc97997a 6739void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6740{
b7137e0c
CW		 6741 if (!READ_ONCE(dev_priv->rps.enabled))
6742 return;
e494837a 6743
b7137e0c 6744 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6745
b7137e0c
CW		 6746 if (INTEL_GEN(dev_priv) >= 9) {
6747 gen9_disable_rc6(dev_priv);
6748 gen9_disable_rps(dev_priv);
6749 } else if (IS_CHERRYVIEW(dev_priv)) {
6750 cherryview_disable_rps(dev_priv);
6751 } else if (IS_VALLEYVIEW(dev_priv)) {
6752 valleyview_disable_rps(dev_priv);
6753 } else if (INTEL_GEN(dev_priv) >= 6) {
6754 gen6_disable_rps(dev_priv);
6755 } else if (IS_IRONLAKE_M(dev_priv)) {
6756 ironlake_disable_drps(dev_priv);
930ebb46 6757 }
b7137e0c
CW		 6758
6759 dev_priv->rps.enabled = false;
6760 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6761}
6762
b7137e0c 6763void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6764{
54b4f68f
CW		 6765 /* We shouldn't be disabling as we submit, so this should be less
6766 * racy than it appears!
6767 */
b7137e0c
CW		 6768 if (READ_ONCE(dev_priv->rps.enabled))
6769 return;
1a01ab3b 6770
b7137e0c
CW		 6771 /* Powersaving is controlled by the host when inside a VM */
6772 if (intel_vgpu_active(dev_priv))
6773 return;
0a073b84 6774
b7137e0c 6775 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6776
6777 if (IS_CHERRYVIEW(dev_priv)) {
6778 cherryview_enable_rps(dev_priv);
6779 } else if (IS_VALLEYVIEW(dev_priv)) {
6780 valleyview_enable_rps(dev_priv);
b7137e0c 6781 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6782 gen9_enable_rc6(dev_priv);
6783 gen9_enable_rps(dev_priv);
6784 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6785 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6786 } else if (IS_BROADWELL(dev_priv)) {
6787 gen8_enable_rps(dev_priv);
fb7404e8 6788 gen6_update_ring_freq(dev_priv);
b7137e0c 6789 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6790 gen6_enable_rps(dev_priv);
fb7404e8 6791 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6792 } else if (IS_IRONLAKE_M(dev_priv)) {
6793 ironlake_enable_drps(dev_priv);
6794 intel_init_emon(dev_priv);
0a073b84 6795 }
aed242ff
CW		 6796
6797 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6798 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6799
6800 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6801 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6802
54b4f68f 6803 dev_priv->rps.enabled = true;
b7137e0c
CW		 6804 mutex_unlock(&dev_priv->rps.hw_lock);
6805}
3cc134e3 6806
54b4f68f
CW		 6807static void __intel_autoenable_gt_powersave(struct work_struct *work)
6808{
6809 struct drm_i915_private *dev_priv =
6810 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6811 struct intel_engine_cs *rcs;
6812 struct drm_i915_gem_request *req;
6813
6814 if (READ_ONCE(dev_priv->rps.enabled))
6815 goto out;
6816
3b3f1650 6817 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6818 if (rcs->last_context)
6819 goto out;
6820
6821 if (!rcs->init_context)
6822 goto out;
6823
6824 mutex_lock(&dev_priv->drm.struct_mutex);
6825
6826 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6827 if (IS_ERR(req))
6828 goto unlock;
6829
6830 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6831 rcs->init_context(req);
6832
6833 /* Mark the device busy, calling intel_enable_gt_powersave() */
6834 i915_add_request_no_flush(req);
6835
6836unlock:
6837 mutex_unlock(&dev_priv->drm.struct_mutex);
6838out:
6839 intel_runtime_pm_put(dev_priv);
6840}
6841
6842void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6843{
6844 if (READ_ONCE(dev_priv->rps.enabled))
6845 return;
6846
6847 if (IS_IRONLAKE_M(dev_priv)) {
6848 ironlake_enable_drps(dev_priv);
54b4f68f 6849 intel_init_emon(dev_priv);
54b4f68f
CW		 6850 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6851 /*
6852 * PCU communication is slow and this doesn't need to be
6853 * done at any specific time, so do this out of our fast path
6854 * to make resume and init faster.
6855 *
6856 * We depend on the HW RC6 power context save/restore
6857 * mechanism when entering D3 through runtime PM suspend. So
6858 * disable RPM until RPS/RC6 is properly setup. We can only
6859 * get here via the driver load/system resume/runtime resume
6860 * paths, so the _noresume version is enough (and in case of
6861 * runtime resume it's necessary).
6862 */
6863 if (queue_delayed_work(dev_priv->wq,
6864 &dev_priv->rps.autoenable_work,
6865 round_jiffies_up_relative(HZ)))
6866 intel_runtime_pm_get_noresume(dev_priv);
6867 }
6868}
6869
3107bd48
DV		 6870static void ibx_init_clock_gating(struct drm_device *dev)
6871{
fac5e23e 6872 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6873
6874 /*
6875 * On Ibex Peak and Cougar Point, we need to disable clock
6876 * gating for the panel power sequencer or it will fail to
6877 * start up when no ports are active.
6878 */
6879 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6880}
6881
0e088b8f
VS		 6882static void g4x_disable_trickle_feed(struct drm_device *dev)
6883{
fac5e23e 6884 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6885 enum pipe pipe;
0e088b8f 6886
055e393f 6887 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6888 I915_WRITE(DSPCNTR(pipe),
6889 I915_READ(DSPCNTR(pipe)) |
6890 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6891
6892 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6893 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6894 }
6895}
6896
017636cc
VS		 6897static void ilk_init_lp_watermarks(struct drm_device *dev)
6898{
fac5e23e 6899 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6900
6901 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6902 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6903 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6904
6905 /*
6906 * Don't touch WM1S_LP_EN here.
6907 * Doing so could cause underruns.
6908 */
6909}
6910
1fa61106 6911static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6912{
fac5e23e 6913 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6914 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6915
f1e8fa56
DL		 6916 /*
6917 * Required for FBC
6918 * WaFbcDisableDpfcClockGating:ilk
6919 */
4d47e4f5
DL		 6920 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6921 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6922 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6923
6924 I915_WRITE(PCH_3DCGDIS0,
6925 MARIUNIT_CLOCK_GATE_DISABLE |
6926 SVSMUNIT_CLOCK_GATE_DISABLE);
6927 I915_WRITE(PCH_3DCGDIS1,
6928 VFMUNIT_CLOCK_GATE_DISABLE);
6929
6f1d69b0
ED		 6930 /*
6931 * According to the spec the following bits should be set in
6932 * order to enable memory self-refresh
6933 * The bit 22/21 of 0x42004
6934 * The bit 5 of 0x42020
6935 * The bit 15 of 0x45000
6936 */
6937 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6938 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6939 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6940 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6941 I915_WRITE(DISP_ARB_CTL,
6942 (I915_READ(DISP_ARB_CTL) |
6943 DISP_FBC_WM_DIS));
017636cc
VS		 6944
6945 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6946
6947 /*
6948 * Based on the document from hardware guys the following bits
6949 * should be set unconditionally in order to enable FBC.
6950 * The bit 22 of 0x42000
6951 * The bit 22 of 0x42004
6952 * The bit 7,8,9 of 0x42020.
6953 */
50a0bc90 6954 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6955 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6956 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6957 I915_READ(ILK_DISPLAY_CHICKEN1) |
6958 ILK_FBCQ_DIS);
6959 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6960 I915_READ(ILK_DISPLAY_CHICKEN2) |
6961 ILK_DPARB_GATE);
6f1d69b0
ED		 6962 }
6963
4d47e4f5
DL		 6964 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6965
6f1d69b0
ED		 6966 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6967 I915_READ(ILK_DISPLAY_CHICKEN2) |
6968 ILK_ELPIN_409_SELECT);
6969 I915_WRITE(_3D_CHICKEN2,
6970 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6971 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6972
ecdb4eb7 6973 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6974 I915_WRITE(CACHE_MODE_0,
6975 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6976
4e04632e
AG		 6977 /* WaDisable_RenderCache_OperationalFlush:ilk */
6978 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6979
0e088b8f 6980 g4x_disable_trickle_feed(dev);
bdad2b2f 6981
3107bd48
DV		 6982 ibx_init_clock_gating(dev);
6983}
6984
6985static void cpt_init_clock_gating(struct drm_device *dev)
6986{
fac5e23e 6987 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6988 int pipe;
3f704fa2 6989 uint32_t val;
3107bd48
DV		 6990
6991 /*
6992 * On Ibex Peak and Cougar Point, we need to disable clock
6993 * gating for the panel power sequencer or it will fail to
6994 * start up when no ports are active.
6995 */
cd664078
JB		 6996 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6997 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6998 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6999 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7000 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 7001 /* The below fixes the weird display corruption, a few pixels shifted
7002 * downward, on (only) LVDS of some HP laptops with IVY.
7003 */
055e393f 7004 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 7005 val = I915_READ(TRANS_CHICKEN2(pipe));
7006 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7007 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 7008 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 7009 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 7010 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7011 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7012 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 7013 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7014 }
3107bd48 7015 /* WADP0ClockGatingDisable */
055e393f 7016 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7017 I915_WRITE(TRANS_CHICKEN1(pipe),
7018 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7019 }
6f1d69b0
ED		 7020}
7021
1d7aaa0c
DV		 7022static void gen6_check_mch_setup(struct drm_device *dev)
7023{
fac5e23e 7024 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7025 uint32_t tmp;
7026
7027 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7028 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7029 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7030 tmp);
1d7aaa0c
DV		 7031}
7032
1fa61106 7033static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7034{
fac5e23e 7035 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7036 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7037
231e54f6 7038 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7039
7040 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7041 I915_READ(ILK_DISPLAY_CHICKEN2) |
7042 ILK_ELPIN_409_SELECT);
7043
ecdb4eb7 7044 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7045 I915_WRITE(_3D_CHICKEN,
7046 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7047
4e04632e
AG		 7048 /* WaDisable_RenderCache_OperationalFlush:snb */
7049 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7050
8d85d272
VS		 7051 /*
7052 * BSpec recoomends 8x4 when MSAA is used,
7053 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7054 *
7055 * Note that PS/WM thread counts depend on the WIZ hashing
7056 * disable bit, which we don't touch here, but it's good
7057 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7058 */
7059 I915_WRITE(GEN6_GT_MODE,
98533251 7060 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7061
017636cc 7062 ilk_init_lp_watermarks(dev);
6f1d69b0 7063
6f1d69b0 7064 I915_WRITE(CACHE_MODE_0,
50743298 7065 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7066
7067 I915_WRITE(GEN6_UCGCTL1,
7068 I915_READ(GEN6_UCGCTL1) |
7069 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7070 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7071
7072 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7073 * gating disable must be set. Failure to set it results in
7074 * flickering pixels due to Z write ordering failures after
7075 * some amount of runtime in the Mesa "fire" demo, and Unigine
7076 * Sanctuary and Tropics, and apparently anything else with
7077 * alpha test or pixel discard.
7078 *
7079 * According to the spec, bit 11 (RCCUNIT) must also be set,
7080 * but we didn't debug actual testcases to find it out.
0f846f81 7081 *
ef59318c
VS		 7082 * WaDisableRCCUnitClockGating:snb
7083 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7084 */
7085 I915_WRITE(GEN6_UCGCTL2,
7086 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7087 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7088
5eb146dd 7089 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7090 I915_WRITE(_3D_CHICKEN3,
7091 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7092
e927ecde
VS		 7093 /*
7094 * Bspec says:
7095 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7096 * 3DSTATE_SF number of SF output attributes is more than 16."
7097 */
7098 I915_WRITE(_3D_CHICKEN3,
7099 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7100
6f1d69b0
ED		 7101 /*
7102 * According to the spec the following bits should be
7103 * set in order to enable memory self-refresh and fbc:
7104 * The bit21 and bit22 of 0x42000
7105 * The bit21 and bit22 of 0x42004
7106 * The bit5 and bit7 of 0x42020
7107 * The bit14 of 0x70180
7108 * The bit14 of 0x71180
4bb35334
DL		 7109 *
7110 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7111 */
7112 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7113 I915_READ(ILK_DISPLAY_CHICKEN1) |
7114 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7115 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7116 I915_READ(ILK_DISPLAY_CHICKEN2) |
7117 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7118 I915_WRITE(ILK_DSPCLK_GATE_D,
7119 I915_READ(ILK_DSPCLK_GATE_D) |
7120 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7121 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7122
0e088b8f 7123 g4x_disable_trickle_feed(dev);
f8f2ac9a 7124
3107bd48 7125 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7126
7127 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7128}
7129
7130static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7131{
7132 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7133
3aad9059 7134 /*
46680e0a 7135 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7136 *
7137 * This actually overrides the dispatch
7138 * mode for all thread types.
7139 */
6f1d69b0
ED		 7140 reg &= ~GEN7_FF_SCHED_MASK;
7141 reg |= GEN7_FF_TS_SCHED_HW;
7142 reg |= GEN7_FF_VS_SCHED_HW;
7143 reg |= GEN7_FF_DS_SCHED_HW;
7144
7145 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7146}
7147
17a303ec
PZ		 7148static void lpt_init_clock_gating(struct drm_device *dev)
7149{
fac5e23e 7150 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7151
7152 /*
7153 * TODO: this bit should only be enabled when really needed, then
7154 * disabled when not needed anymore in order to save power.
7155 */
4f8036a2 7156 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7157 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7158 I915_READ(SOUTH_DSPCLK_GATE_D) |
7159 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7160
7161 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7162 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7163 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7164 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7165}
7166
7d708ee4
ID		 7167static void lpt_suspend_hw(struct drm_device *dev)
7168{
fac5e23e 7169 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7170
4f8036a2 7171 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7172 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7173
7174 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7175 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7176 }
7177}
7178
450174fe
ID		 7179static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7180 int general_prio_credits,
7181 int high_prio_credits)
7182{
7183 u32 misccpctl;
7184
7185 /* WaTempDisableDOPClkGating:bdw */
7186 misccpctl = I915_READ(GEN7_MISCCPCTL);
7187 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7188
7189 I915_WRITE(GEN8_L3SQCREG1,
7190 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7191 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7192
7193 /*
7194 * Wait at least 100 clocks before re-enabling clock gating.
7195 * See the definition of L3SQCREG1 in BSpec.
7196 */
7197 POSTING_READ(GEN8_L3SQCREG1);
7198 udelay(1);
7199 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7200}
7201
9498dba7
MK		 7202static void kabylake_init_clock_gating(struct drm_device *dev)
7203{
9146f308 7204 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7205
b033bb6d 7206 gen9_init_clock_gating(dev);
9498dba7
MK		 7207
7208 /* WaDisableSDEUnitClockGating:kbl */
7209 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7210 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7211 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7212
7213 /* WaDisableGamClockGating:kbl */
7214 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7215 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7216 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7217
7218 /* WaFbcNukeOnHostModify:kbl */
7219 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7220 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7221}
7222
dc00b6a0
DV		 7223static void skylake_init_clock_gating(struct drm_device *dev)
7224{
c584e2d3 7225 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7226
b033bb6d 7227 gen9_init_clock_gating(dev);
44fff99f
MK		 7228
7229 /* WAC6entrylatency:skl */
7230 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7231 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7232
7233 /* WaFbcNukeOnHostModify:skl */
7234 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7235 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7236}
7237
47c2bd97 7238static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7239{
fac5e23e 7240 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7241 enum pipe pipe;
1020a5c2 7242
7ad0dbab 7243 ilk_init_lp_watermarks(dev);
50ed5fbd 7244
ab57fff1 7245 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7246 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7247
ab57fff1 7248 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7249 I915_WRITE(CHICKEN_PAR1_1,
7250 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7251
ab57fff1 7252 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7253 for_each_pipe(dev_priv, pipe) {
07d27e20 7254 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7255 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7256 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7257 }
63801f21 7258
ab57fff1
BW		 7259 /* WaVSRefCountFullforceMissDisable:bdw */
7260 /* WaDSRefCountFullforceMissDisable:bdw */
7261 I915_WRITE(GEN7_FF_THREAD_MODE,
7262 I915_READ(GEN7_FF_THREAD_MODE) &
7263 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7264
295e8bb7
VS		 7265 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7266 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7267
7268 /* WaDisableSDEUnitClockGating:bdw */
7269 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7270 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7271
450174fe
ID		 7272 /* WaProgramL3SqcReg1Default:bdw */
7273 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7274
6d50b065
VS		 7275 /*
7276 * WaGttCachingOffByDefault:bdw
7277 * GTT cache may not work with big pages, so if those
7278 * are ever enabled GTT cache may need to be disabled.
7279 */
7280 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7281
17e0adf0
MK		 7282 /* WaKVMNotificationOnConfigChange:bdw */
7283 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7284 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7285
89d6b2b8 7286 lpt_init_clock_gating(dev);
1020a5c2
BW		 7287}
7288
cad2a2d7
ED		 7289static void haswell_init_clock_gating(struct drm_device *dev)
7290{
fac5e23e 7291 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7292
017636cc 7293 ilk_init_lp_watermarks(dev);
cad2a2d7 7294
f3fc4884
FJ		 7295 /* L3 caching of data atomics doesn't work -- disable it. */
7296 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7297 I915_WRITE(HSW_ROW_CHICKEN3,
7298 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7299
ecdb4eb7 7300 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7301 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7302 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7303 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7304
e36ea7ff
VS		 7305 /* WaVSRefCountFullforceMissDisable:hsw */
7306 I915_WRITE(GEN7_FF_THREAD_MODE,
7307 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7308
4e04632e
AG		 7309 /* WaDisable_RenderCache_OperationalFlush:hsw */
7310 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7311
fe27c606
CW		 7312 /* enable HiZ Raw Stall Optimization */
7313 I915_WRITE(CACHE_MODE_0_GEN7,
7314 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7315
ecdb4eb7 7316 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7317 I915_WRITE(CACHE_MODE_1,
7318 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7319
a12c4967
VS		 7320 /*
7321 * BSpec recommends 8x4 when MSAA is used,
7322 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7323 *
7324 * Note that PS/WM thread counts depend on the WIZ hashing
7325 * disable bit, which we don't touch here, but it's good
7326 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7327 */
7328 I915_WRITE(GEN7_GT_MODE,
98533251 7329 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7330
94411593
KG		 7331 /* WaSampleCChickenBitEnable:hsw */
7332 I915_WRITE(HALF_SLICE_CHICKEN3,
7333 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7334
ecdb4eb7 7335 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7336 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7337
90a88643
PZ		 7338 /* WaRsPkgCStateDisplayPMReq:hsw */
7339 I915_WRITE(CHICKEN_PAR1_1,
7340 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7341
17a303ec 7342 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7343}
7344
1fa61106 7345static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7346{
fac5e23e 7347 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7348 uint32_t snpcr;
6f1d69b0 7349
017636cc 7350 ilk_init_lp_watermarks(dev);
6f1d69b0 7351
231e54f6 7352 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7353
ecdb4eb7 7354 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7355 I915_WRITE(_3D_CHICKEN3,
7356 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7357
ecdb4eb7 7358 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7359 I915_WRITE(IVB_CHICKEN3,
7360 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7361 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7362
ecdb4eb7 7363 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7364 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7365 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7366 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7367
4e04632e
AG		 7368 /* WaDisable_RenderCache_OperationalFlush:ivb */
7369 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7370
ecdb4eb7 7371 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7372 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7373 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7374
ecdb4eb7 7375 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7376 I915_WRITE(GEN7_L3CNTLREG1,
7377 GEN7_WA_FOR_GEN7_L3_CONTROL);
7378 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7379 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7380 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7381 I915_WRITE(GEN7_ROW_CHICKEN2,
7382 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7383 else {
7384 /* must write both registers */
7385 I915_WRITE(GEN7_ROW_CHICKEN2,
7386 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7387 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7388 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7389 }
6f1d69b0 7390
ecdb4eb7 7391 /* WaForceL3Serialization:ivb */
61939d97
JB		 7392 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7393 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7394
1b80a19a 7395 /*
0f846f81 7396 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7397 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7398 */
7399 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7400 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7401
ecdb4eb7 7402 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7403 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7404 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7405 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7406
0e088b8f 7407 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7408
7409 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7410
22721343
CW		 7411 if (0) { /* causes HiZ corruption on ivb:gt1 */
7412 /* enable HiZ Raw Stall Optimization */
7413 I915_WRITE(CACHE_MODE_0_GEN7,
7414 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7415 }
116f2b6d 7416
ecdb4eb7 7417 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7418 I915_WRITE(CACHE_MODE_1,
7419 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7420
a607c1a4
VS		 7421 /*
7422 * BSpec recommends 8x4 when MSAA is used,
7423 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7424 *
7425 * Note that PS/WM thread counts depend on the WIZ hashing
7426 * disable bit, which we don't touch here, but it's good
7427 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7428 */
7429 I915_WRITE(GEN7_GT_MODE,
98533251 7430 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7431
20848223
BW		 7432 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7433 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7434 snpcr |= GEN6_MBC_SNPCR_MED;
7435 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7436
6e266956 7437 if (!HAS_PCH_NOP(dev_priv))
ab5c608b 7438 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7439
7440 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7441}
7442
1fa61106 7443static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7444{
fac5e23e 7445 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7446
ecdb4eb7 7447 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7448 I915_WRITE(_3D_CHICKEN3,
7449 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7450
ecdb4eb7 7451 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7452 I915_WRITE(IVB_CHICKEN3,
7453 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7454 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7455
fad7d36e 7456 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7457 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7458 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7459 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7460 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7461
4e04632e
AG		 7462 /* WaDisable_RenderCache_OperationalFlush:vlv */
7463 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7464
ecdb4eb7 7465 /* WaForceL3Serialization:vlv */
61939d97
JB		 7466 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7467 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7468
ecdb4eb7 7469 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7470 I915_WRITE(GEN7_ROW_CHICKEN2,
7471 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7472
ecdb4eb7 7473 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7474 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7475 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7476 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7477
46680e0a
VS		 7478 gen7_setup_fixed_func_scheduler(dev_priv);
7479
3c0edaeb 7480 /*
0f846f81 7481 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7482 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7483 */
7484 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7485 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7486
c98f5062
AG		 7487 /* WaDisableL3Bank2xClockGate:vlv
7488 * Disabling L3 clock gating- MMIO 940c[25] = 1
7489 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7490 I915_WRITE(GEN7_UCGCTL4,
7491 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7492
afd58e79
VS		 7493 /*
7494 * BSpec says this must be set, even though
7495 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7496 */
6b26c86d
DV		 7497 I915_WRITE(CACHE_MODE_1,
7498 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7499
da2518f9
VS		 7500 /*
7501 * BSpec recommends 8x4 when MSAA is used,
7502 * however in practice 16x4 seems fastest.
7503 *
7504 * Note that PS/WM thread counts depend on the WIZ hashing
7505 * disable bit, which we don't touch here, but it's good
7506 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7507 */
7508 I915_WRITE(GEN7_GT_MODE,
7509 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7510
031994ee
VS		 7511 /*
7512 * WaIncreaseL3CreditsForVLVB0:vlv
7513 * This is the hardware default actually.
7514 */
7515 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7516
2d809570 7517 /*
ecdb4eb7 7518 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7519 * Disable clock gating on th GCFG unit to prevent a delay
7520 * in the reporting of vblank events.
7521 */
7a0d1eed 7522 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7523}
7524
a4565da8
VS		 7525static void cherryview_init_clock_gating(struct drm_device *dev)
7526{
fac5e23e 7527 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7528
232ce337
VS		 7529 /* WaVSRefCountFullforceMissDisable:chv */
7530 /* WaDSRefCountFullforceMissDisable:chv */
7531 I915_WRITE(GEN7_FF_THREAD_MODE,
7532 I915_READ(GEN7_FF_THREAD_MODE) &
7533 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7534
7535 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7536 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7537 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7538
7539 /* WaDisableCSUnitClockGating:chv */
7540 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7541 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7542
7543 /* WaDisableSDEUnitClockGating:chv */
7544 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7545 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7546
450174fe
ID		 7547 /*
7548 * WaProgramL3SqcReg1Default:chv
7549 * See gfxspecs/Related Documents/Performance Guide/
7550 * LSQC Setting Recommendations.
7551 */
7552 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7553
6d50b065
VS		 7554 /*
7555 * GTT cache may not work with big pages, so if those
7556 * are ever enabled GTT cache may need to be disabled.
7557 */
7558 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7559}
7560
1fa61106 7561static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7562{
fac5e23e 7563 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7564 uint32_t dspclk_gate;
7565
7566 I915_WRITE(RENCLK_GATE_D1, 0);
7567 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7568 GS_UNIT_CLOCK_GATE_DISABLE |
7569 CL_UNIT_CLOCK_GATE_DISABLE);
7570 I915_WRITE(RAMCLK_GATE_D, 0);
7571 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7572 OVRUNIT_CLOCK_GATE_DISABLE |
7573 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7574 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7575 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7576 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7577
7578 /* WaDisableRenderCachePipelinedFlush */
7579 I915_WRITE(CACHE_MODE_0,
7580 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7581
4e04632e
AG		 7582 /* WaDisable_RenderCache_OperationalFlush:g4x */
7583 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7584
0e088b8f 7585 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7586}
7587
1fa61106 7588static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7589{
fac5e23e 7590 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7591
7592 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7593 I915_WRITE(RENCLK_GATE_D2, 0);
7594 I915_WRITE(DSPCLK_GATE_D, 0);
7595 I915_WRITE(RAMCLK_GATE_D, 0);
7596 I915_WRITE16(DEUC, 0);
20f94967
VS		 7597 I915_WRITE(MI_ARB_STATE,
7598 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7599
7600 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7601 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7602}
7603
1fa61106 7604static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7605{
fac5e23e 7606 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7607
7608 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7609 I965_RCC_CLOCK_GATE_DISABLE |
7610 I965_RCPB_CLOCK_GATE_DISABLE |
7611 I965_ISC_CLOCK_GATE_DISABLE |
7612 I965_FBC_CLOCK_GATE_DISABLE);
7613 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7614 I915_WRITE(MI_ARB_STATE,
7615 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7616
7617 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7618 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7619}
7620
1fa61106 7621static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7622{
fac5e23e 7623 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7624 u32 dstate = I915_READ(D_STATE);
7625
7626 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7627 DSTATE_DOT_CLOCK_GATING;
7628 I915_WRITE(D_STATE, dstate);
13a86b85 7629
9b1e14f4 7630 if (IS_PINEVIEW(dev_priv))
13a86b85 7631 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7632
7633 /* IIR "flip pending" means done if this bit is set */
7634 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7635
7636 /* interrupts should cause a wake up from C3 */
3299254f 7637 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7638
7639 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7640 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7641
7642 I915_WRITE(MI_ARB_STATE,
7643 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7644}
7645
1fa61106 7646static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7647{
fac5e23e 7648 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7649
7650 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7651
7652 /* interrupts should cause a wake up from C3 */
7653 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7654 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7655
7656 I915_WRITE(MEM_MODE,
7657 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7658}
7659
1fa61106 7660static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7661{
fac5e23e 7662 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7663
7664 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7665
7666 I915_WRITE(MEM_MODE,
7667 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7668 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7669}
7670
6f1d69b0
ED		 7671void intel_init_clock_gating(struct drm_device *dev)
7672{
fac5e23e 7673 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7674
bb400da9 7675 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7676}
7677
7d708ee4
ID		 7678void intel_suspend_hw(struct drm_device *dev)
7679{
6e266956 7680 if (HAS_PCH_LPT(to_i915(dev)))
7d708ee4
ID		 7681 lpt_suspend_hw(dev);
7682}
7683
bb400da9
ID		 7684static void nop_init_clock_gating(struct drm_device *dev)
7685{
7686 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7687}
7688
7689/**
7690 * intel_init_clock_gating_hooks - setup the clock gating hooks
7691 * @dev_priv: device private
7692 *
7693 * Setup the hooks that configure which clocks of a given platform can be
7694 * gated and also apply various GT and display specific workarounds for these
7695 * platforms. Note that some GT specific workarounds are applied separately
7696 * when GPU contexts or batchbuffers start their execution.
7697 */
7698void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7699{
7700 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7701 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7702 else if (IS_KABYLAKE(dev_priv))
9498dba7 7703 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7704 else if (IS_BROXTON(dev_priv))
7705 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7706 else if (IS_BROADWELL(dev_priv))
7707 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7708 else if (IS_CHERRYVIEW(dev_priv))
7709 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7710 else if (IS_HASWELL(dev_priv))
7711 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7712 else if (IS_IVYBRIDGE(dev_priv))
7713 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7714 else if (IS_VALLEYVIEW(dev_priv))
7715 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7716 else if (IS_GEN6(dev_priv))
7717 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7718 else if (IS_GEN5(dev_priv))
7719 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7720 else if (IS_G4X(dev_priv))
7721 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7722 else if (IS_CRESTLINE(dev_priv))
7723 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7724 else if (IS_BROADWATER(dev_priv))
7725 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7726 else if (IS_GEN3(dev_priv))
7727 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7728 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7729 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7730 else if (IS_GEN2(dev_priv))
7731 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7732 else {
7733 MISSING_CASE(INTEL_DEVID(dev_priv));
7734 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7735 }
7736}
7737
1fa61106
ED		 7738/* Set up chip specific power management-related functions */
7739void intel_init_pm(struct drm_device *dev)
7740{
fac5e23e 7741 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7742
7ff0ebcc 7743 intel_fbc_init(dev_priv);
1fa61106 7744
c921aba8 7745 /* For cxsr */
9b1e14f4 7746 if (IS_PINEVIEW(dev_priv))
c921aba8 7747 i915_pineview_get_mem_freq(dev);
5db94019 7748 else if (IS_GEN5(dev_priv))
c921aba8
DV		 7749 i915_ironlake_get_mem_freq(dev);
7750
1fa61106 7751 /* For FIFO watermark updates */
f5ed50cb 7752 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7753 skl_setup_wm_latency(dev);
2d41c0b5 7754 dev_priv->display.update_wm = skl_update_wm;
98d39494 7755 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7756 } else if (HAS_PCH_SPLIT(dev_priv)) {
fa50ad61 7757 ilk_setup_wm_latency(dev);
53615a5e 7758
5db94019 7759 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7760 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7761 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7762 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7763 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7764 dev_priv->display.compute_intermediate_wm =
7765 ilk_compute_intermediate_wm;
7766 dev_priv->display.initial_watermarks =
7767 ilk_initial_watermarks;
7768 dev_priv->display.optimize_watermarks =
7769 ilk_optimize_watermarks;
bd602544
VS		 7770 } else {
7771 DRM_DEBUG_KMS("Failed to read display plane latency. "
7772 "Disable CxSR\n");
7773 }
920a14b2 7774 } else if (IS_CHERRYVIEW(dev_priv)) {
262cd2e1 7775 vlv_setup_wm_latency(dev);
262cd2e1 7776 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7777 } else if (IS_VALLEYVIEW(dev_priv)) {
26e1fe4f 7778 vlv_setup_wm_latency(dev);
26e1fe4f 7779 dev_priv->display.update_wm = vlv_update_wm;
9b1e14f4 7780 } else if (IS_PINEVIEW(dev_priv)) {
50a0bc90 7781 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7782 dev_priv->is_ddr3,
7783 dev_priv->fsb_freq,
7784 dev_priv->mem_freq)) {
7785 DRM_INFO("failed to find known CxSR latency "
7786 "(found ddr%s fsb freq %d, mem freq %d), "
7787 "disabling CxSR\n",
7788 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7789 dev_priv->fsb_freq, dev_priv->mem_freq);
7790 /* Disable CxSR and never update its watermark again */
5209b1f4 7791 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7792 dev_priv->display.update_wm = NULL;
7793 } else
7794 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7795 } else if (IS_G4X(dev_priv)) {
1fa61106 7796 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7797 } else if (IS_GEN4(dev_priv)) {
1fa61106 7798 dev_priv->display.update_wm = i965_update_wm;
5db94019 7799 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7800 dev_priv->display.update_wm = i9xx_update_wm;
7801 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7802 } else if (IS_GEN2(dev_priv)) {
feb56b93
DV		 7803 if (INTEL_INFO(dev)->num_pipes == 1) {
7804 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7805 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7806 } else {
7807 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7808 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7809 }
feb56b93
DV		 7810 } else {
7811 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7812 }
7813}
7814
87660502
L		 7815static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7816{
7817 uint32_t flags =
7818 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7819
7820 switch (flags) {
7821 case GEN6_PCODE_SUCCESS:
7822 return 0;
7823 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7824 case GEN6_PCODE_ILLEGAL_CMD:
7825 return -ENXIO;
7826 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7827 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7828 return -EOVERFLOW;
7829 case GEN6_PCODE_TIMEOUT:
7830 return -ETIMEDOUT;
7831 default:
7832 MISSING_CASE(flags)
7833 return 0;
7834 }
7835}
7836
7837static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7838{
7839 uint32_t flags =
7840 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7841
7842 switch (flags) {
7843 case GEN6_PCODE_SUCCESS:
7844 return 0;
7845 case GEN6_PCODE_ILLEGAL_CMD:
7846 return -ENXIO;
7847 case GEN7_PCODE_TIMEOUT:
7848 return -ETIMEDOUT;
7849 case GEN7_PCODE_ILLEGAL_DATA:
7850 return -EINVAL;
7851 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7852 return -EOVERFLOW;
7853 default:
7854 MISSING_CASE(flags);
7855 return 0;
7856 }
7857}
7858
151a49d0 7859int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7860{
87660502
L		 7861 int status;
7862
4fc688ce 7863 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7864
3f5582dd
CW		 7865 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7866 * use te fw I915_READ variants to reduce the amount of work
7867 * required when reading/writing.
7868 */
7869
7870 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7871 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7872 return -EAGAIN;
7873 }
7874
3f5582dd
CW		 7875 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7876 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7877 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7878
3f5582dd
CW		 7879 if (intel_wait_for_register_fw(dev_priv,
7880 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7881 500)) {
42c0526c
BW		 7882 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7883 return -ETIMEDOUT;
7884 }
7885
3f5582dd
CW		 7886 *val = I915_READ_FW(GEN6_PCODE_DATA);
7887 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7888
87660502
L		 7889 if (INTEL_GEN(dev_priv) > 6)
7890 status = gen7_check_mailbox_status(dev_priv);
7891 else
7892 status = gen6_check_mailbox_status(dev_priv);
7893
7894 if (status) {
7895 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7896 status);
7897 return status;
7898 }
7899
42c0526c
BW		 7900 return 0;
7901}
7902
3f5582dd 7903int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7904 u32 mbox, u32 val)
42c0526c 7905{
87660502
L		 7906 int status;
7907
4fc688ce 7908 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7909
3f5582dd
CW		 7910 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7911 * use te fw I915_READ variants to reduce the amount of work
7912 * required when reading/writing.
7913 */
7914
7915 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7916 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7917 return -EAGAIN;
7918 }
7919
3f5582dd
CW		 7920 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7921 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7922
3f5582dd
CW		 7923 if (intel_wait_for_register_fw(dev_priv,
7924 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7925 500)) {
42c0526c
BW		 7926 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7927 return -ETIMEDOUT;
7928 }
7929
3f5582dd 7930 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7931
87660502
L		 7932 if (INTEL_GEN(dev_priv) > 6)
7933 status = gen7_check_mailbox_status(dev_priv);
7934 else
7935 status = gen6_check_mailbox_status(dev_priv);
7936
7937 if (status) {
7938 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7939 status);
7940 return status;
7941 }
7942
42c0526c
BW		 7943 return 0;
7944}
a0e4e199 7945
dd06f88c
VS		 7946static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7947{
c30fec65
VS		 7948 /*
7949 * N = val - 0xb7
7950 * Slow = Fast = GPLL ref * N
7951 */
7952 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7953}
7954
b55dd647 7955static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7956{
c30fec65 7957 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7958}
7959
b55dd647 7960static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7961{
c30fec65
VS		 7962 /*
7963 * N = val / 2
7964 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7965 */
7966 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7967}
7968
b55dd647 7969static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7970{
1c14762d 7971 /* CHV needs even values */
c30fec65 7972 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7973}
7974
616bc820 7975int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7976{
2d1fe073 7977 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7978 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7979 GEN9_FREQ_SCALER);
2d1fe073 7980 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7981 return chv_gpu_freq(dev_priv, val);
2d1fe073 7982 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7983 return byt_gpu_freq(dev_priv, val);
7984 else
7985 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7986}
7987
616bc820
VS		 7988int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7989{
2d1fe073 7990 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7991 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7992 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7993 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7994 return chv_freq_opcode(dev_priv, val);
2d1fe073 7995 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7996 return byt_freq_opcode(dev_priv, val);
7997 else
500a3d2e 7998 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7999}
22b1b2f8 8000
6ad790c0
CW		 8001struct request_boost {
8002 struct work_struct work;
eed29a5b 8003 struct drm_i915_gem_request *req;
6ad790c0
CW		 8004};
8005
8006static void __intel_rps_boost_work(struct work_struct *work)
8007{
8008 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 8009 struct drm_i915_gem_request *req = boost->req;
6ad790c0 8010
f69a02c9 8011 if (!i915_gem_request_completed(req))
c033666a 8012 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 8013
e8a261ea 8014 i915_gem_request_put(req);
6ad790c0
CW		 8015 kfree(boost);
8016}
8017
91d14251 8018void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8019{
8020 struct request_boost *boost;
8021
91d14251 8022 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8023 return;
8024
f69a02c9 8025 if (i915_gem_request_completed(req))
e61b9958
CW		 8026 return;
8027
6ad790c0
CW		 8028 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8029 if (boost == NULL)
8030 return;
8031
e8a261ea 8032 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8033
8034 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8035 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8036}
8037
f742a552 8038void intel_pm_setup(struct drm_device *dev)
907b28c5 8039{
fac5e23e 8040 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8041
f742a552 8042 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8043 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8044
54b4f68f
CW		 8045 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8046 __intel_autoenable_gt_powersave);
1854d5ca 8047 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8048
33688d95 8049 dev_priv->pm.suspended = false;
1f814dac 8050 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 8051}
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