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drm/i915: Add missing ')' to SKL_PS_ECC_STAT define
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
a82abe43
ID		 55static void bxt_init_clock_gating(struct drm_device *dev)
56{
32608ca2
ID		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
a7546159
NH		 59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
32608ca2
ID		 63 /*
64 * FIXME:
868434c5 65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 66 */
32608ca2 67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
a82abe43
ID		 69}
70
c921aba8
DV		 71static void i915_pineview_get_mem_freq(struct drm_device *dev)
72{
50227e1c 73 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 74 u32 tmp;
75
76 tmp = I915_READ(CLKCFG);
77
78 switch (tmp & CLKCFG_FSB_MASK) {
79 case CLKCFG_FSB_533:
80 dev_priv->fsb_freq = 533; /* 133*4 */
81 break;
82 case CLKCFG_FSB_800:
83 dev_priv->fsb_freq = 800; /* 200*4 */
84 break;
85 case CLKCFG_FSB_667:
86 dev_priv->fsb_freq = 667; /* 167*4 */
87 break;
88 case CLKCFG_FSB_400:
89 dev_priv->fsb_freq = 400; /* 100*4 */
90 break;
91 }
92
93 switch (tmp & CLKCFG_MEM_MASK) {
94 case CLKCFG_MEM_533:
95 dev_priv->mem_freq = 533;
96 break;
97 case CLKCFG_MEM_667:
98 dev_priv->mem_freq = 667;
99 break;
100 case CLKCFG_MEM_800:
101 dev_priv->mem_freq = 800;
102 break;
103 }
104
105 /* detect pineview DDR3 setting */
106 tmp = I915_READ(CSHRDDR3CTL);
107 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
108}
109
110static void i915_ironlake_get_mem_freq(struct drm_device *dev)
111{
50227e1c 112 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 113 u16 ddrpll, csipll;
114
115 ddrpll = I915_READ16(DDRMPLL1);
116 csipll = I915_READ16(CSIPLL0);
117
118 switch (ddrpll & 0xff) {
119 case 0xc:
120 dev_priv->mem_freq = 800;
121 break;
122 case 0x10:
123 dev_priv->mem_freq = 1066;
124 break;
125 case 0x14:
126 dev_priv->mem_freq = 1333;
127 break;
128 case 0x18:
129 dev_priv->mem_freq = 1600;
130 break;
131 default:
132 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
133 ddrpll & 0xff);
134 dev_priv->mem_freq = 0;
135 break;
136 }
137
20e4d407 138 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 139
140 switch (csipll & 0x3ff) {
141 case 0x00c:
142 dev_priv->fsb_freq = 3200;
143 break;
144 case 0x00e:
145 dev_priv->fsb_freq = 3733;
146 break;
147 case 0x010:
148 dev_priv->fsb_freq = 4266;
149 break;
150 case 0x012:
151 dev_priv->fsb_freq = 4800;
152 break;
153 case 0x014:
154 dev_priv->fsb_freq = 5333;
155 break;
156 case 0x016:
157 dev_priv->fsb_freq = 5866;
158 break;
159 case 0x018:
160 dev_priv->fsb_freq = 6400;
161 break;
162 default:
163 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
164 csipll & 0x3ff);
165 dev_priv->fsb_freq = 0;
166 break;
167 }
168
169 if (dev_priv->fsb_freq == 3200) {
20e4d407 170 dev_priv->ips.c_m = 0;
c921aba8 171 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 172 dev_priv->ips.c_m = 1;
c921aba8 173 } else {
20e4d407 174 dev_priv->ips.c_m = 2;
c921aba8
DV		 175 }
176}
177
b445e3b0
ED		 178static const struct cxsr_latency cxsr_latency_table[] = {
179 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
180 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
181 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
182 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
183 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
184
185 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
186 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
187 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
188 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
189 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
190
191 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
192 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
193 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
194 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
195 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
196
197 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
198 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
199 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
200 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
201 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
202
203 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
204 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
205 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
206 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
207 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
208
209 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
210 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
211 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
212 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
213 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
214};
215
63c62275 216static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 217 int is_ddr3,
218 int fsb,
219 int mem)
220{
221 const struct cxsr_latency *latency;
222 int i;
223
224 if (fsb == 0 || mem == 0)
225 return NULL;
226
227 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
228 latency = &cxsr_latency_table[i];
229 if (is_desktop == latency->is_desktop &&
230 is_ddr3 == latency->is_ddr3 &&
231 fsb == latency->fsb_freq && mem == latency->mem_freq)
232 return latency;
233 }
234
235 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
236
237 return NULL;
238}
239
fc1ac8de
VS		 240static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
241{
242 u32 val;
243
244 mutex_lock(&dev_priv->rps.hw_lock);
245
246 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
247 if (enable)
248 val &= ~FORCE_DDR_HIGH_FREQ;
249 else
250 val |= FORCE_DDR_HIGH_FREQ;
251 val &= ~FORCE_DDR_LOW_FREQ;
252 val |= FORCE_DDR_FREQ_REQ_ACK;
253 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
254
255 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
256 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
257 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
258
259 mutex_unlock(&dev_priv->rps.hw_lock);
260}
261
cfb41411
VS		 262static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
263{
264 u32 val;
265
266 mutex_lock(&dev_priv->rps.hw_lock);
267
268 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
269 if (enable)
270 val |= DSP_MAXFIFO_PM5_ENABLE;
271 else
272 val &= ~DSP_MAXFIFO_PM5_ENABLE;
273 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
274
275 mutex_unlock(&dev_priv->rps.hw_lock);
276}
277
f4998963
VS		 278#define FW_WM(value, plane) \
279 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
280
5209b1f4 281void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 282{
5209b1f4
ID		 283 struct drm_device *dev = dev_priv->dev;
284 u32 val;
b445e3b0 285
5209b1f4
ID		 286 if (IS_VALLEYVIEW(dev)) {
287 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 288 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 289 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 290 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
291 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 292 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 293 } else if (IS_PINEVIEW(dev)) {
294 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
295 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
296 I915_WRITE(DSPFW3, val);
a7a6c498 297 POSTING_READ(DSPFW3);
5209b1f4
ID		 298 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
299 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
300 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
301 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_I915GM(dev)) {
304 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
305 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
306 I915_WRITE(INSTPM, val);
a7a6c498 307 POSTING_READ(INSTPM);
5209b1f4
ID		 308 } else {
309 return;
310 }
b445e3b0 311
5209b1f4
ID		 312 DRM_DEBUG_KMS("memory self-refresh is %s\n",
313 enable ? "enabled" : "disabled");
b445e3b0
ED		 314}
315
fc1ac8de 316
b445e3b0
ED		 317/*
318 * Latency for FIFO fetches is dependent on several factors:
319 * - memory configuration (speed, channels)
320 * - chipset
321 * - current MCH state
322 * It can be fairly high in some situations, so here we assume a fairly
323 * pessimal value. It's a tradeoff between extra memory fetches (if we
324 * set this value too high, the FIFO will fetch frequently to stay full)
325 * and power consumption (set it too low to save power and we might see
326 * FIFO underruns and display "flicker").
327 *
328 * A value of 5us seems to be a good balance; safe for very low end
329 * platforms but not overly aggressive on lower latency configs.
330 */
5aef6003 331static const int pessimal_latency_ns = 5000;
b445e3b0 332
b5004720
VS		 333#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
334 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
335
336static int vlv_get_fifo_size(struct drm_device *dev,
337 enum pipe pipe, int plane)
338{
339 struct drm_i915_private *dev_priv = dev->dev_private;
340 int sprite0_start, sprite1_start, size;
341
342 switch (pipe) {
343 uint32_t dsparb, dsparb2, dsparb3;
344 case PIPE_A:
345 dsparb = I915_READ(DSPARB);
346 dsparb2 = I915_READ(DSPARB2);
347 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
348 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
349 break;
350 case PIPE_B:
351 dsparb = I915_READ(DSPARB);
352 dsparb2 = I915_READ(DSPARB2);
353 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
354 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
355 break;
356 case PIPE_C:
357 dsparb2 = I915_READ(DSPARB2);
358 dsparb3 = I915_READ(DSPARB3);
359 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
360 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
361 break;
362 default:
363 return 0;
364 }
365
366 switch (plane) {
367 case 0:
368 size = sprite0_start;
369 break;
370 case 1:
371 size = sprite1_start - sprite0_start;
372 break;
373 case 2:
374 size = 512 - 1 - sprite1_start;
375 break;
376 default:
377 return 0;
378 }
379
380 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
381 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
382 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
383 size);
384
385 return size;
386}
387
1fa61106 388static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 389{
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 uint32_t dsparb = I915_READ(DSPARB);
392 int size;
393
394 size = dsparb & 0x7f;
395 if (plane)
396 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
397
398 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
399 plane ? "B" : "A", size);
400
401 return size;
402}
403
feb56b93 404static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 405{
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 uint32_t dsparb = I915_READ(DSPARB);
408 int size;
409
410 size = dsparb & 0x1ff;
411 if (plane)
412 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
413 size >>= 1; /* Convert to cachelines */
414
415 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
416 plane ? "B" : "A", size);
417
418 return size;
419}
420
1fa61106 421static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 422{
423 struct drm_i915_private *dev_priv = dev->dev_private;
424 uint32_t dsparb = I915_READ(DSPARB);
425 int size;
426
427 size = dsparb & 0x7f;
428 size >>= 2; /* Convert to cachelines */
429
430 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
431 plane ? "B" : "A",
432 size);
433
434 return size;
435}
436
b445e3b0
ED		 437/* Pineview has different values for various configs */
438static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 439 .fifo_size = PINEVIEW_DISPLAY_FIFO,
440 .max_wm = PINEVIEW_MAX_WM,
441 .default_wm = PINEVIEW_DFT_WM,
442 .guard_size = PINEVIEW_GUARD_WM,
443 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 444};
445static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 446 .fifo_size = PINEVIEW_DISPLAY_FIFO,
447 .max_wm = PINEVIEW_MAX_WM,
448 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
449 .guard_size = PINEVIEW_GUARD_WM,
450 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 451};
452static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 453 .fifo_size = PINEVIEW_CURSOR_FIFO,
454 .max_wm = PINEVIEW_CURSOR_MAX_WM,
455 .default_wm = PINEVIEW_CURSOR_DFT_WM,
456 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
457 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 458};
459static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 460 .fifo_size = PINEVIEW_CURSOR_FIFO,
461 .max_wm = PINEVIEW_CURSOR_MAX_WM,
462 .default_wm = PINEVIEW_CURSOR_DFT_WM,
463 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
464 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 465};
466static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 467 .fifo_size = G4X_FIFO_SIZE,
468 .max_wm = G4X_MAX_WM,
469 .default_wm = G4X_MAX_WM,
470 .guard_size = 2,
471 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 472};
473static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 474 .fifo_size = I965_CURSOR_FIFO,
475 .max_wm = I965_CURSOR_MAX_WM,
476 .default_wm = I965_CURSOR_DFT_WM,
477 .guard_size = 2,
478 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 479};
480static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 481 .fifo_size = VALLEYVIEW_FIFO_SIZE,
482 .max_wm = VALLEYVIEW_MAX_WM,
483 .default_wm = VALLEYVIEW_MAX_WM,
484 .guard_size = 2,
485 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 486};
487static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 488 .fifo_size = I965_CURSOR_FIFO,
489 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
490 .default_wm = I965_CURSOR_DFT_WM,
491 .guard_size = 2,
492 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 493};
494static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 495 .fifo_size = I965_CURSOR_FIFO,
496 .max_wm = I965_CURSOR_MAX_WM,
497 .default_wm = I965_CURSOR_DFT_WM,
498 .guard_size = 2,
499 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 500};
501static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 502 .fifo_size = I945_FIFO_SIZE,
503 .max_wm = I915_MAX_WM,
504 .default_wm = 1,
505 .guard_size = 2,
506 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 507};
508static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 509 .fifo_size = I915_FIFO_SIZE,
510 .max_wm = I915_MAX_WM,
511 .default_wm = 1,
512 .guard_size = 2,
513 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 514};
9d539105 515static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 516 .fifo_size = I855GM_FIFO_SIZE,
517 .max_wm = I915_MAX_WM,
518 .default_wm = 1,
519 .guard_size = 2,
520 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 521};
9d539105
VS		 522static const struct intel_watermark_params i830_bc_wm_info = {
523 .fifo_size = I855GM_FIFO_SIZE,
524 .max_wm = I915_MAX_WM/2,
525 .default_wm = 1,
526 .guard_size = 2,
527 .cacheline_size = I830_FIFO_LINE_SIZE,
528};
feb56b93 529static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 530 .fifo_size = I830_FIFO_SIZE,
531 .max_wm = I915_MAX_WM,
532 .default_wm = 1,
533 .guard_size = 2,
534 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 535};
536
b445e3b0
ED		 537/**
538 * intel_calculate_wm - calculate watermark level
539 * @clock_in_khz: pixel clock
540 * @wm: chip FIFO params
541 * @pixel_size: display pixel size
542 * @latency_ns: memory latency for the platform
543 *
544 * Calculate the watermark level (the level at which the display plane will
545 * start fetching from memory again). Each chip has a different display
546 * FIFO size and allocation, so the caller needs to figure that out and pass
547 * in the correct intel_watermark_params structure.
548 *
549 * As the pixel clock runs, the FIFO will be drained at a rate that depends
550 * on the pixel size. When it reaches the watermark level, it'll start
551 * fetching FIFO line sized based chunks from memory until the FIFO fills
552 * past the watermark point. If the FIFO drains completely, a FIFO underrun
553 * will occur, and a display engine hang could result.
554 */
555static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
556 const struct intel_watermark_params *wm,
557 int fifo_size,
558 int pixel_size,
559 unsigned long latency_ns)
560{
561 long entries_required, wm_size;
562
563 /*
564 * Note: we need to make sure we don't overflow for various clock &
565 * latency values.
566 * clocks go from a few thousand to several hundred thousand.
567 * latency is usually a few thousand
568 */
569 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
570 1000;
571 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
572
573 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
574
575 wm_size = fifo_size - (entries_required + wm->guard_size);
576
577 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
578
579 /* Don't promote wm_size to unsigned... */
580 if (wm_size > (long)wm->max_wm)
581 wm_size = wm->max_wm;
582 if (wm_size <= 0)
583 wm_size = wm->default_wm;
d6feb196
VS		 584
585 /*
586 * Bspec seems to indicate that the value shouldn't be lower than
587 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
588 * Lets go for 8 which is the burst size since certain platforms
589 * already use a hardcoded 8 (which is what the spec says should be
590 * done).
591 */
592 if (wm_size <= 8)
593 wm_size = 8;
594
b445e3b0
ED		 595 return wm_size;
596}
597
598static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
599{
600 struct drm_crtc *crtc, *enabled = NULL;
601
70e1e0ec 602 for_each_crtc(dev, crtc) {
3490ea5d 603 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 604 if (enabled)
605 return NULL;
606 enabled = crtc;
607 }
608 }
609
610 return enabled;
611}
612
46ba614c 613static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 614{
46ba614c 615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 616 struct drm_i915_private *dev_priv = dev->dev_private;
617 struct drm_crtc *crtc;
618 const struct cxsr_latency *latency;
619 u32 reg;
620 unsigned long wm;
621
622 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
623 dev_priv->fsb_freq, dev_priv->mem_freq);
624 if (!latency) {
625 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 626 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 627 return;
628 }
629
630 crtc = single_enabled_crtc(dev);
631 if (crtc) {
7c5f93b0 632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 633 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 634 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 635
636 /* Display SR */
637 wm = intel_calculate_wm(clock, &pineview_display_wm,
638 pineview_display_wm.fifo_size,
639 pixel_size, latency->display_sr);
640 reg = I915_READ(DSPFW1);
641 reg &= ~DSPFW_SR_MASK;
f4998963 642 reg |= FW_WM(wm, SR);
b445e3b0
ED		 643 I915_WRITE(DSPFW1, reg);
644 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
645
646 /* cursor SR */
647 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
648 pineview_display_wm.fifo_size,
649 pixel_size, latency->cursor_sr);
650 reg = I915_READ(DSPFW3);
651 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 652 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 653 I915_WRITE(DSPFW3, reg);
654
655 /* Display HPLL off SR */
656 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
657 pineview_display_hplloff_wm.fifo_size,
658 pixel_size, latency->display_hpll_disable);
659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 661 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 662 I915_WRITE(DSPFW3, reg);
663
664 /* cursor HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
667 pixel_size, latency->cursor_hpll_disable);
668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 670 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 671 I915_WRITE(DSPFW3, reg);
672 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
673
5209b1f4 674 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 675 } else {
5209b1f4 676 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 677 }
678}
679
680static bool g4x_compute_wm0(struct drm_device *dev,
681 int plane,
682 const struct intel_watermark_params *display,
683 int display_latency_ns,
684 const struct intel_watermark_params *cursor,
685 int cursor_latency_ns,
686 int *plane_wm,
687 int *cursor_wm)
688{
689 struct drm_crtc *crtc;
4fe8590a 690 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 691 int htotal, hdisplay, clock, pixel_size;
692 int line_time_us, line_count;
693 int entries, tlb_miss;
694
695 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 696 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 697 *cursor_wm = cursor->guard_size;
698 *plane_wm = display->guard_size;
699 return false;
700 }
701
6e3c9717 702 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 703 clock = adjusted_mode->crtc_clock;
fec8cba3 704 htotal = adjusted_mode->crtc_htotal;
6e3c9717 705 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 706 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 707
708 /* Use the small buffer method to calculate plane watermark */
709 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
710 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
711 if (tlb_miss > 0)
712 entries += tlb_miss;
713 entries = DIV_ROUND_UP(entries, display->cacheline_size);
714 *plane_wm = entries + display->guard_size;
715 if (*plane_wm > (int)display->max_wm)
716 *plane_wm = display->max_wm;
717
718 /* Use the large buffer method to calculate cursor watermark */
922044c9 719 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 720 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 721 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 722 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
723 if (tlb_miss > 0)
724 entries += tlb_miss;
725 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
726 *cursor_wm = entries + cursor->guard_size;
727 if (*cursor_wm > (int)cursor->max_wm)
728 *cursor_wm = (int)cursor->max_wm;
729
730 return true;
731}
732
733/*
734 * Check the wm result.
735 *
736 * If any calculated watermark values is larger than the maximum value that
737 * can be programmed into the associated watermark register, that watermark
738 * must be disabled.
739 */
740static bool g4x_check_srwm(struct drm_device *dev,
741 int display_wm, int cursor_wm,
742 const struct intel_watermark_params *display,
743 const struct intel_watermark_params *cursor)
744{
745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
746 display_wm, cursor_wm);
747
748 if (display_wm > display->max_wm) {
749 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
750 display_wm, display->max_wm);
751 return false;
752 }
753
754 if (cursor_wm > cursor->max_wm) {
755 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
756 cursor_wm, cursor->max_wm);
757 return false;
758 }
759
760 if (!(display_wm || cursor_wm)) {
761 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
762 return false;
763 }
764
765 return true;
766}
767
768static bool g4x_compute_srwm(struct drm_device *dev,
769 int plane,
770 int latency_ns,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor,
773 int *display_wm, int *cursor_wm)
774{
775 struct drm_crtc *crtc;
4fe8590a 776 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 777 int hdisplay, htotal, pixel_size, clock;
778 unsigned long line_time_us;
779 int line_count, line_size;
780 int small, large;
781 int entries;
782
783 if (!latency_ns) {
784 *display_wm = *cursor_wm = 0;
785 return false;
786 }
787
788 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 789 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 790 clock = adjusted_mode->crtc_clock;
fec8cba3 791 htotal = adjusted_mode->crtc_htotal;
6e3c9717 792 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 793 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 794
922044c9 795 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 796 line_count = (latency_ns / line_time_us + 1000) / 1000;
797 line_size = hdisplay * pixel_size;
798
799 /* Use the minimum of the small and large buffer method for primary */
800 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
801 large = line_count * line_size;
802
803 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
804 *display_wm = entries + display->guard_size;
805
806 /* calculate the self-refresh watermark for display cursor */
3dd512fb 807 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 808 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
809 *cursor_wm = entries + cursor->guard_size;
810
811 return g4x_check_srwm(dev,
812 *display_wm, *cursor_wm,
813 display, cursor);
814}
815
15665979
VS		 816#define FW_WM_VLV(value, plane) \
817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
818
0018fda1
VS		 819static void vlv_write_wm_values(struct intel_crtc *crtc,
820 const struct vlv_wm_values *wm)
821{
822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
823 enum pipe pipe = crtc->pipe;
824
825 I915_WRITE(VLV_DDL(pipe),
826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
830
ae80152d 831 I915_WRITE(DSPFW1,
15665979
VS		 832 FW_WM(wm->sr.plane, SR) |
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 836 I915_WRITE(DSPFW2,
15665979
VS		 837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 840 I915_WRITE(DSPFW3,
15665979 841 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 842
843 if (IS_CHERRYVIEW(dev_priv)) {
844 I915_WRITE(DSPFW7_CHV,
15665979
VS		 845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 847 I915_WRITE(DSPFW8_CHV,
15665979
VS		 848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 850 I915_WRITE(DSPFW9_CHV,
15665979
VS		 851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 853 I915_WRITE(DSPHOWM,
15665979
VS		 854 FW_WM(wm->sr.plane >> 9, SR_HI) |
855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 864 } else {
865 I915_WRITE(DSPFW7,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 868 I915_WRITE(DSPHOWM,
15665979
VS		 869 FW_WM(wm->sr.plane >> 9, SR_HI) |
870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 876 }
877
2cb389b7
VS		 878 /* zero (unused) WM1 watermarks */
879 I915_WRITE(DSPFW4, 0);
880 I915_WRITE(DSPFW5, 0);
881 I915_WRITE(DSPFW6, 0);
882 I915_WRITE(DSPHOWM1, 0);
883
ae80152d 884 POSTING_READ(DSPFW1);
0018fda1
VS		 885}
886
15665979
VS		 887#undef FW_WM_VLV
888
6eb1a681
VS		 889enum vlv_wm_level {
890 VLV_WM_LEVEL_PM2,
891 VLV_WM_LEVEL_PM5,
892 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 893};
894
262cd2e1
VS		 895/* latency must be in 0.1us units. */
896static unsigned int vlv_wm_method2(unsigned int pixel_rate,
897 unsigned int pipe_htotal,
898 unsigned int horiz_pixels,
899 unsigned int bytes_per_pixel,
900 unsigned int latency)
901{
902 unsigned int ret;
903
904 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
905 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
906 ret = DIV_ROUND_UP(ret, 64);
907
908 return ret;
909}
910
911static void vlv_setup_wm_latency(struct drm_device *dev)
912{
913 struct drm_i915_private *dev_priv = dev->dev_private;
914
915 /* all latencies in usec */
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
917
58590c14
VS		 918 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
919
262cd2e1
VS		 920 if (IS_CHERRYVIEW(dev_priv)) {
921 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
922 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 923
924 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 925 }
926}
927
928static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
929 struct intel_crtc *crtc,
930 const struct intel_plane_state *state,
931 int level)
932{
933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
934 int clock, htotal, pixel_size, width, wm;
935
936 if (dev_priv->wm.pri_latency[level] == 0)
937 return USHRT_MAX;
938
939 if (!state->visible)
940 return 0;
941
942 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
943 clock = crtc->config->base.adjusted_mode.crtc_clock;
944 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
945 width = crtc->config->pipe_src_w;
946 if (WARN_ON(htotal == 0))
947 htotal = 1;
948
949 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
950 /*
951 * FIXME the formula gives values that are
952 * too big for the cursor FIFO, and hence we
953 * would never be able to use cursors. For
954 * now just hardcode the watermark.
955 */
956 wm = 63;
957 } else {
958 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
959 dev_priv->wm.pri_latency[level] * 10);
960 }
961
962 return min_t(int, wm, USHRT_MAX);
963}
964
54f1b6e1
VS		 965static void vlv_compute_fifo(struct intel_crtc *crtc)
966{
967 struct drm_device *dev = crtc->base.dev;
968 struct vlv_wm_state *wm_state = &crtc->wm_state;
969 struct intel_plane *plane;
970 unsigned int total_rate = 0;
971 const int fifo_size = 512 - 1;
972 int fifo_extra, fifo_left = fifo_size;
973
974 for_each_intel_plane_on_crtc(dev, crtc, plane) {
975 struct intel_plane_state *state =
976 to_intel_plane_state(plane->base.state);
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
979 continue;
980
981 if (state->visible) {
982 wm_state->num_active_planes++;
983 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
984 }
985 }
986
987 for_each_intel_plane_on_crtc(dev, crtc, plane) {
988 struct intel_plane_state *state =
989 to_intel_plane_state(plane->base.state);
990 unsigned int rate;
991
992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
993 plane->wm.fifo_size = 63;
994 continue;
995 }
996
997 if (!state->visible) {
998 plane->wm.fifo_size = 0;
999 continue;
1000 }
1001
1002 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004 fifo_left -= plane->wm.fifo_size;
1005 }
1006
1007 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009 /* spread the remainder evenly */
1010 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011 int plane_extra;
1012
1013 if (fifo_left == 0)
1014 break;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017 continue;
1018
1019 /* give it all to the first plane if none are active */
1020 if (plane->wm.fifo_size == 0 &&
1021 wm_state->num_active_planes)
1022 continue;
1023
1024 plane_extra = min(fifo_extra, fifo_left);
1025 plane->wm.fifo_size += plane_extra;
1026 fifo_left -= plane_extra;
1027 }
1028
1029 WARN_ON(fifo_left != 0);
1030}
1031
262cd2e1
VS		 1032static void vlv_invert_wms(struct intel_crtc *crtc)
1033{
1034 struct vlv_wm_state *wm_state = &crtc->wm_state;
1035 int level;
1036
1037 for (level = 0; level < wm_state->num_levels; level++) {
1038 struct drm_device *dev = crtc->base.dev;
1039 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040 struct intel_plane *plane;
1041
1042 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046 switch (plane->base.type) {
1047 int sprite;
1048 case DRM_PLANE_TYPE_CURSOR:
1049 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050 wm_state->wm[level].cursor;
1051 break;
1052 case DRM_PLANE_TYPE_PRIMARY:
1053 wm_state->wm[level].primary = plane->wm.fifo_size -
1054 wm_state->wm[level].primary;
1055 break;
1056 case DRM_PLANE_TYPE_OVERLAY:
1057 sprite = plane->plane;
1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059 wm_state->wm[level].sprite[sprite];
1060 break;
1061 }
1062 }
1063 }
1064}
1065
26e1fe4f 1066static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1067{
1068 struct drm_device *dev = crtc->base.dev;
1069 struct vlv_wm_state *wm_state = &crtc->wm_state;
1070 struct intel_plane *plane;
1071 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072 int level;
1073
1074 memset(wm_state, 0, sizeof(*wm_state));
1075
852eb00d 1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1078
1079 wm_state->num_active_planes = 0;
262cd2e1 1080
54f1b6e1 1081 vlv_compute_fifo(crtc);
262cd2e1
VS		 1082
1083 if (wm_state->num_active_planes != 1)
1084 wm_state->cxsr = false;
1085
1086 if (wm_state->cxsr) {
1087 for (level = 0; level < wm_state->num_levels; level++) {
1088 wm_state->sr[level].plane = sr_fifo_size;
1089 wm_state->sr[level].cursor = 63;
1090 }
1091 }
1092
1093 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094 struct intel_plane_state *state =
1095 to_intel_plane_state(plane->base.state);
1096
1097 if (!state->visible)
1098 continue;
1099
1100 /* normal watermarks */
1101 for (level = 0; level < wm_state->num_levels; level++) {
1102 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105 /* hack */
1106 if (WARN_ON(level == 0 && wm > max_wm))
1107 wm = max_wm;
1108
1109 if (wm > plane->wm.fifo_size)
1110 break;
1111
1112 switch (plane->base.type) {
1113 int sprite;
1114 case DRM_PLANE_TYPE_CURSOR:
1115 wm_state->wm[level].cursor = wm;
1116 break;
1117 case DRM_PLANE_TYPE_PRIMARY:
1118 wm_state->wm[level].primary = wm;
1119 break;
1120 case DRM_PLANE_TYPE_OVERLAY:
1121 sprite = plane->plane;
1122 wm_state->wm[level].sprite[sprite] = wm;
1123 break;
1124 }
1125 }
1126
1127 wm_state->num_levels = level;
1128
1129 if (!wm_state->cxsr)
1130 continue;
1131
1132 /* maxfifo watermarks */
1133 switch (plane->base.type) {
1134 int sprite, level;
1135 case DRM_PLANE_TYPE_CURSOR:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].cursor =
1138 wm_state->sr[level].cursor;
1139 break;
1140 case DRM_PLANE_TYPE_PRIMARY:
1141 for (level = 0; level < wm_state->num_levels; level++)
1142 wm_state->sr[level].plane =
1143 min(wm_state->sr[level].plane,
1144 wm_state->wm[level].primary);
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 for (level = 0; level < wm_state->num_levels; level++)
1149 wm_state->sr[level].plane =
1150 min(wm_state->sr[level].plane,
1151 wm_state->wm[level].sprite[sprite]);
1152 break;
1153 }
1154 }
1155
1156 /* clear any (partially) filled invalid levels */
58590c14 1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1158 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160 }
1161
1162 vlv_invert_wms(crtc);
1163}
1164
54f1b6e1
VS		 1165#define VLV_FIFO(plane, value) \
1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169{
1170 struct drm_device *dev = crtc->base.dev;
1171 struct drm_i915_private *dev_priv = to_i915(dev);
1172 struct intel_plane *plane;
1173 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177 WARN_ON(plane->wm.fifo_size != 63);
1178 continue;
1179 }
1180
1181 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182 sprite0_start = plane->wm.fifo_size;
1183 else if (plane->plane == 0)
1184 sprite1_start = sprite0_start + plane->wm.fifo_size;
1185 else
1186 fifo_size = sprite1_start + plane->wm.fifo_size;
1187 }
1188
1189 WARN_ON(fifo_size != 512 - 1);
1190
1191 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192 pipe_name(crtc->pipe), sprite0_start,
1193 sprite1_start, fifo_size);
1194
1195 switch (crtc->pipe) {
1196 uint32_t dsparb, dsparb2, dsparb3;
1197 case PIPE_A:
1198 dsparb = I915_READ(DSPARB);
1199 dsparb2 = I915_READ(DSPARB2);
1200
1201 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202 VLV_FIFO(SPRITEB, 0xff));
1203 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204 VLV_FIFO(SPRITEB, sprite1_start));
1205
1206 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207 VLV_FIFO(SPRITEB_HI, 0x1));
1208 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211 I915_WRITE(DSPARB, dsparb);
1212 I915_WRITE(DSPARB2, dsparb2);
1213 break;
1214 case PIPE_B:
1215 dsparb = I915_READ(DSPARB);
1216 dsparb2 = I915_READ(DSPARB2);
1217
1218 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219 VLV_FIFO(SPRITED, 0xff));
1220 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221 VLV_FIFO(SPRITED, sprite1_start));
1222
1223 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224 VLV_FIFO(SPRITED_HI, 0xff));
1225 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228 I915_WRITE(DSPARB, dsparb);
1229 I915_WRITE(DSPARB2, dsparb2);
1230 break;
1231 case PIPE_C:
1232 dsparb3 = I915_READ(DSPARB3);
1233 dsparb2 = I915_READ(DSPARB2);
1234
1235 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236 VLV_FIFO(SPRITEF, 0xff));
1237 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238 VLV_FIFO(SPRITEF, sprite1_start));
1239
1240 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241 VLV_FIFO(SPRITEF_HI, 0xff));
1242 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245 I915_WRITE(DSPARB3, dsparb3);
1246 I915_WRITE(DSPARB2, dsparb2);
1247 break;
1248 default:
1249 break;
1250 }
1251}
1252
1253#undef VLV_FIFO
1254
262cd2e1
VS		 1255static void vlv_merge_wm(struct drm_device *dev,
1256 struct vlv_wm_values *wm)
1257{
1258 struct intel_crtc *crtc;
1259 int num_active_crtcs = 0;
1260
58590c14 1261 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1262 wm->cxsr = true;
1263
1264 for_each_intel_crtc(dev, crtc) {
1265 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267 if (!crtc->active)
1268 continue;
1269
1270 if (!wm_state->cxsr)
1271 wm->cxsr = false;
1272
1273 num_active_crtcs++;
1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275 }
1276
1277 if (num_active_crtcs != 1)
1278 wm->cxsr = false;
1279
6f9c784b
VS		 1280 if (num_active_crtcs > 1)
1281 wm->level = VLV_WM_LEVEL_PM2;
1282
262cd2e1
VS		 1283 for_each_intel_crtc(dev, crtc) {
1284 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285 enum pipe pipe = crtc->pipe;
1286
1287 if (!crtc->active)
1288 continue;
1289
1290 wm->pipe[pipe] = wm_state->wm[wm->level];
1291 if (wm->cxsr)
1292 wm->sr = wm_state->sr[wm->level];
1293
1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298 }
1299}
1300
1301static void vlv_update_wm(struct drm_crtc *crtc)
1302{
1303 struct drm_device *dev = crtc->dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306 enum pipe pipe = intel_crtc->pipe;
1307 struct vlv_wm_values wm = {};
1308
26e1fe4f 1309 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1310 vlv_merge_wm(dev, &wm);
1311
54f1b6e1
VS		 1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313 /* FIXME should be part of crtc atomic commit */
1314 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1315 return;
54f1b6e1 1316 }
262cd2e1
VS		 1317
1318 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320 chv_set_memory_dvfs(dev_priv, false);
1321
1322 if (wm.level < VLV_WM_LEVEL_PM5 &&
1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324 chv_set_memory_pm5(dev_priv, false);
1325
852eb00d 1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1327 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1328
54f1b6e1
VS		 1329 /* FIXME should be part of crtc atomic commit */
1330 vlv_pipe_set_fifo_size(intel_crtc);
1331
262cd2e1
VS		 1332 vlv_write_wm_values(intel_crtc, &wm);
1333
1334 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
852eb00d 1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1341 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1342
1343 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345 chv_set_memory_pm5(dev_priv, true);
1346
1347 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, true);
1350
1351 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1352}
1353
ae80152d
VS		 1354#define single_plane_enabled(mask) is_power_of_2(mask)
1355
46ba614c 1356static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1357{
46ba614c 1358 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1359 static const int sr_latency_ns = 12000;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362 int plane_sr, cursor_sr;
1363 unsigned int enabled = 0;
9858425c 1364 bool cxsr_enabled;
b445e3b0 1365
51cea1f4 1366 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1367 &g4x_wm_info, pessimal_latency_ns,
1368 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1369 &planea_wm, &cursora_wm))
51cea1f4 1370 enabled |= 1 << PIPE_A;
b445e3b0 1371
51cea1f4 1372 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1373 &g4x_wm_info, pessimal_latency_ns,
1374 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1375 &planeb_wm, &cursorb_wm))
51cea1f4 1376 enabled |= 1 << PIPE_B;
b445e3b0 1377
b445e3b0
ED		 1378 if (single_plane_enabled(enabled) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1380 sr_latency_ns,
1381 &g4x_wm_info,
1382 &g4x_cursor_wm_info,
52bd02d8 1383 &plane_sr, &cursor_sr)) {
9858425c 1384 cxsr_enabled = true;
52bd02d8 1385 } else {
9858425c 1386 cxsr_enabled = false;
5209b1f4 1387 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1388 plane_sr = cursor_sr = 0;
1389 }
b445e3b0 1390
a5043453
VS		 1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1393 planea_wm, cursora_wm,
1394 planeb_wm, cursorb_wm,
1395 plane_sr, cursor_sr);
1396
1397 I915_WRITE(DSPFW1,
f4998963
VS		 1398 FW_WM(plane_sr, SR) |
1399 FW_WM(cursorb_wm, CURSORB) |
1400 FW_WM(planeb_wm, PLANEB) |
1401 FW_WM(planea_wm, PLANEA));
b445e3b0 1402 I915_WRITE(DSPFW2,
8c919b28 1403 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1404 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1405 /* HPLL off in SR has some issues on G4x... disable it */
1406 I915_WRITE(DSPFW3,
8c919b28 1407 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1408 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1409
1410 if (cxsr_enabled)
1411 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1412}
1413
46ba614c 1414static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1415{
46ba614c 1416 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct drm_crtc *crtc;
1419 int srwm = 1;
1420 int cursor_sr = 16;
9858425c 1421 bool cxsr_enabled;
b445e3b0
ED		 1422
1423 /* Calc sr entries for one plane configs */
1424 crtc = single_enabled_crtc(dev);
1425 if (crtc) {
1426 /* self-refresh has much higher latency */
1427 static const int sr_latency_ns = 12000;
124abe07 1428 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1429 int clock = adjusted_mode->crtc_clock;
fec8cba3 1430 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1431 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1432 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1433 unsigned long line_time_us;
1434 int entries;
1435
922044c9 1436 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1437
1438 /* Use ns/us then divide to preserve precision */
1439 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440 pixel_size * hdisplay;
1441 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442 srwm = I965_FIFO_SIZE - entries;
1443 if (srwm < 0)
1444 srwm = 1;
1445 srwm &= 0x1ff;
1446 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447 entries, srwm);
1448
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1450 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1451 entries = DIV_ROUND_UP(entries,
1452 i965_cursor_wm_info.cacheline_size);
1453 cursor_sr = i965_cursor_wm_info.fifo_size -
1454 (entries + i965_cursor_wm_info.guard_size);
1455
1456 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457 cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460 "cursor %d\n", srwm, cursor_sr);
1461
9858425c 1462 cxsr_enabled = true;
b445e3b0 1463 } else {
9858425c 1464 cxsr_enabled = false;
b445e3b0 1465 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1466 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1467 }
1468
1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470 srwm);
1471
1472 /* 965 has limitations... */
f4998963
VS		 1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474 FW_WM(8, CURSORB) |
1475 FW_WM(8, PLANEB) |
1476 FW_WM(8, PLANEA));
1477 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478 FW_WM(8, PLANEC_OLD));
b445e3b0 1479 /* update cursor SR watermark */
f4998963 1480 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1481
1482 if (cxsr_enabled)
1483 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1484}
1485
f4998963
VS		 1486#undef FW_WM
1487
46ba614c 1488static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1489{
46ba614c 1490 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 const struct intel_watermark_params *wm_info;
1493 uint32_t fwater_lo;
1494 uint32_t fwater_hi;
1495 int cwm, srwm = 1;
1496 int fifo_size;
1497 int planea_wm, planeb_wm;
1498 struct drm_crtc *crtc, *enabled = NULL;
1499
1500 if (IS_I945GM(dev))
1501 wm_info = &i945_wm_info;
1502 else if (!IS_GEN2(dev))
1503 wm_info = &i915_wm_info;
1504 else
9d539105 1505 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1506
1507 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1509 if (intel_crtc_active(crtc)) {
241bfc38 1510 const struct drm_display_mode *adjusted_mode;
59bea882 1511 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1512 if (IS_GEN2(dev))
1513 cpp = 4;
1514
6e3c9717 1515 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1516 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1517 wm_info, fifo_size, cpp,
5aef6003 1518 pessimal_latency_ns);
b445e3b0 1519 enabled = crtc;
9d539105 1520 } else {
b445e3b0 1521 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1522 if (planea_wm > (long)wm_info->max_wm)
1523 planea_wm = wm_info->max_wm;
1524 }
1525
1526 if (IS_GEN2(dev))
1527 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1528
1529 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1531 if (intel_crtc_active(crtc)) {
241bfc38 1532 const struct drm_display_mode *adjusted_mode;
59bea882 1533 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1534 if (IS_GEN2(dev))
1535 cpp = 4;
1536
6e3c9717 1537 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1538 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1539 wm_info, fifo_size, cpp,
5aef6003 1540 pessimal_latency_ns);
b445e3b0
ED		 1541 if (enabled == NULL)
1542 enabled = crtc;
1543 else
1544 enabled = NULL;
9d539105 1545 } else {
b445e3b0 1546 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1547 if (planeb_wm > (long)wm_info->max_wm)
1548 planeb_wm = wm_info->max_wm;
1549 }
b445e3b0
ED		 1550
1551 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
2ab1bc9d 1553 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1554 struct drm_i915_gem_object *obj;
2ab1bc9d 1555
59bea882 1556 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1557
1558 /* self-refresh seems busted with untiled */
2ff8fde1 1559 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1560 enabled = NULL;
1561 }
1562
b445e3b0
ED		 1563 /*
1564 * Overlay gets an aggressive default since video jitter is bad.
1565 */
1566 cwm = 2;
1567
1568 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1569 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1570
1571 /* Calc sr entries for one plane configs */
1572 if (HAS_FW_BLC(dev) && enabled) {
1573 /* self-refresh has much higher latency */
1574 static const int sr_latency_ns = 6000;
124abe07 1575 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1576 int clock = adjusted_mode->crtc_clock;
fec8cba3 1577 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1578 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1579 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1580 unsigned long line_time_us;
1581 int entries;
1582
922044c9 1583 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1584
1585 /* Use ns/us then divide to preserve precision */
1586 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587 pixel_size * hdisplay;
1588 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590 srwm = wm_info->fifo_size - entries;
1591 if (srwm < 0)
1592 srwm = 1;
1593
1594 if (IS_I945G(dev) || IS_I945GM(dev))
1595 I915_WRITE(FW_BLC_SELF,
1596 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597 else if (IS_I915GM(dev))
1598 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599 }
1600
1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602 planea_wm, planeb_wm, cwm, srwm);
1603
1604 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605 fwater_hi = (cwm & 0x1f);
1606
1607 /* Set request length to 8 cachelines per fetch */
1608 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609 fwater_hi = fwater_hi | (1 << 8);
1610
1611 I915_WRITE(FW_BLC, fwater_lo);
1612 I915_WRITE(FW_BLC2, fwater_hi);
1613
5209b1f4
ID		 1614 if (enabled)
1615 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1616}
1617
feb56b93 1618static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1619{
46ba614c 1620 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 struct drm_crtc *crtc;
241bfc38 1623 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1624 uint32_t fwater_lo;
1625 int planea_wm;
1626
1627 crtc = single_enabled_crtc(dev);
1628 if (crtc == NULL)
1629 return;
1630
6e3c9717 1631 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1632 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1633 &i845_wm_info,
b445e3b0 1634 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1635 4, pessimal_latency_ns);
b445e3b0
ED		 1636 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637 fwater_lo |= (3<<8) | planea_wm;
1638
1639 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641 I915_WRITE(FW_BLC, fwater_lo);
1642}
1643
8cfb3407 1644uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1645{
fd4daa9c 1646 uint32_t pixel_rate;
801bcfff 1647
8cfb3407 1648 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1649
1650 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651 * adjust the pixel_rate here. */
1652
8cfb3407 1653 if (pipe_config->pch_pfit.enabled) {
801bcfff 1654 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1655 uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657 pipe_w = pipe_config->pipe_src_w;
1658 pipe_h = pipe_config->pipe_src_h;
801bcfff 1659
801bcfff
PZ		 1660 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661 pfit_h = pfit_size & 0xFFFF;
1662 if (pipe_w < pfit_w)
1663 pipe_w = pfit_w;
1664 if (pipe_h < pfit_h)
1665 pipe_h = pfit_h;
1666
1667 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1668 pfit_w * pfit_h);
1669 }
1670
1671 return pixel_rate;
1672}
1673
37126462 1674/* latency must be in 0.1us units. */
23297044 1675static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1676 uint32_t latency)
1677{
1678 uint64_t ret;
1679
3312ba65
VS		 1680 if (WARN(latency == 0, "Latency value missing\n"))
1681 return UINT_MAX;
1682
801bcfff
PZ		 1683 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1684 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1685
1686 return ret;
1687}
1688
37126462 1689/* latency must be in 0.1us units. */
23297044 1690static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1691 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1692 uint32_t latency)
1693{
1694 uint32_t ret;
1695
3312ba65
VS		 1696 if (WARN(latency == 0, "Latency value missing\n"))
1697 return UINT_MAX;
1698
801bcfff
PZ		 1699 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1700 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1701 ret = DIV_ROUND_UP(ret, 64) + 2;
1702 return ret;
1703}
1704
23297044 1705static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1706 uint8_t bytes_per_pixel)
1707{
1708 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1709}
1710
820c1980 1711struct ilk_wm_maximums {
cca32e9a
PZ		 1712 uint16_t pri;
1713 uint16_t spr;
1714 uint16_t cur;
1715 uint16_t fbc;
1716};
1717
37126462
VS		 1718/*
1719 * For both WM_PIPE and WM_LP.
1720 * mem_value must be in 0.1us units.
1721 */
7221fc33 1722static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1723 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1724 uint32_t mem_value,
1725 bool is_lp)
801bcfff 1726{
43d59eda 1727 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
cca32e9a
PZ		 1728 uint32_t method1, method2;
1729
7221fc33 1730 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1731 return 0;
1732
7221fc33 1733 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
cca32e9a
PZ		 1734
1735 if (!is_lp)
1736 return method1;
1737
7221fc33
MR		 1738 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1739 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1740 drm_rect_width(&pstate->dst),
1741 bpp,
cca32e9a
PZ		 1742 mem_value);
1743
1744 return min(method1, method2);
801bcfff
PZ		 1745}
1746
37126462
VS		 1747/*
1748 * For both WM_PIPE and WM_LP.
1749 * mem_value must be in 0.1us units.
1750 */
7221fc33 1751static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1752 const struct intel_plane_state *pstate,
801bcfff
PZ		 1753 uint32_t mem_value)
1754{
43d59eda 1755 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
801bcfff
PZ		 1756 uint32_t method1, method2;
1757
7221fc33 1758 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1759 return 0;
1760
7221fc33
MR		 1761 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1762 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1763 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1764 drm_rect_width(&pstate->dst),
1765 bpp,
801bcfff
PZ		 1766 mem_value);
1767 return min(method1, method2);
1768}
1769
37126462
VS		 1770/*
1771 * For both WM_PIPE and WM_LP.
1772 * mem_value must be in 0.1us units.
1773 */
7221fc33 1774static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1775 const struct intel_plane_state *pstate,
801bcfff
PZ		 1776 uint32_t mem_value)
1777{
43d59eda
MR		 1778 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1779
7221fc33 1780 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1781 return 0;
1782
7221fc33
MR		 1783 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1784 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1785 drm_rect_width(&pstate->dst),
1786 bpp,
801bcfff
PZ		 1787 mem_value);
1788}
1789
cca32e9a 1790/* Only for WM_LP. */
7221fc33 1791static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1792 const struct intel_plane_state *pstate,
1fda9882 1793 uint32_t pri_val)
cca32e9a 1794{
43d59eda
MR		 1795 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1796
7221fc33 1797 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1798 return 0;
1799
43d59eda 1800 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
cca32e9a
PZ		 1801}
1802
158ae64f
VS		 1803static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1804{
416f4727
VS		 1805 if (INTEL_INFO(dev)->gen >= 8)
1806 return 3072;
1807 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1808 return 768;
1809 else
1810 return 512;
1811}
1812
4e975081
VS		 1813static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1814 int level, bool is_sprite)
1815{
1816 if (INTEL_INFO(dev)->gen >= 8)
1817 /* BDW primary/sprite plane watermarks */
1818 return level == 0 ? 255 : 2047;
1819 else if (INTEL_INFO(dev)->gen >= 7)
1820 /* IVB/HSW primary/sprite plane watermarks */
1821 return level == 0 ? 127 : 1023;
1822 else if (!is_sprite)
1823 /* ILK/SNB primary plane watermarks */
1824 return level == 0 ? 127 : 511;
1825 else
1826 /* ILK/SNB sprite plane watermarks */
1827 return level == 0 ? 63 : 255;
1828}
1829
1830static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1831 int level)
1832{
1833 if (INTEL_INFO(dev)->gen >= 7)
1834 return level == 0 ? 63 : 255;
1835 else
1836 return level == 0 ? 31 : 63;
1837}
1838
1839static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1840{
1841 if (INTEL_INFO(dev)->gen >= 8)
1842 return 31;
1843 else
1844 return 15;
1845}
1846
158ae64f
VS		 1847/* Calculate the maximum primary/sprite plane watermark */
1848static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1849 int level,
240264f4 1850 const struct intel_wm_config *config,
158ae64f
VS		 1851 enum intel_ddb_partitioning ddb_partitioning,
1852 bool is_sprite)
1853{
1854 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1855
1856 /* if sprites aren't enabled, sprites get nothing */
240264f4 1857 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1858 return 0;
1859
1860 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1861 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1862 fifo_size /= INTEL_INFO(dev)->num_pipes;
1863
1864 /*
1865 * For some reason the non self refresh
1866 * FIFO size is only half of the self
1867 * refresh FIFO size on ILK/SNB.
1868 */
1869 if (INTEL_INFO(dev)->gen <= 6)
1870 fifo_size /= 2;
1871 }
1872
240264f4 1873 if (config->sprites_enabled) {
158ae64f
VS		 1874 /* level 0 is always calculated with 1:1 split */
1875 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1876 if (is_sprite)
1877 fifo_size *= 5;
1878 fifo_size /= 6;
1879 } else {
1880 fifo_size /= 2;
1881 }
1882 }
1883
1884 /* clamp to max that the registers can hold */
4e975081 1885 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1886}
1887
1888/* Calculate the maximum cursor plane watermark */
1889static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1890 int level,
1891 const struct intel_wm_config *config)
158ae64f
VS		 1892{
1893 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1894 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1895 return 64;
1896
1897 /* otherwise just report max that registers can hold */
4e975081 1898 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1899}
1900
d34ff9c6 1901static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1902 int level,
1903 const struct intel_wm_config *config,
1904 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1905 struct ilk_wm_maximums *max)
158ae64f 1906{
240264f4
VS		 1907 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1908 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1909 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1910 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1911}
1912
a3cb4048
VS		 1913static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1914 int level,
1915 struct ilk_wm_maximums *max)
1916{
1917 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1918 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1919 max->cur = ilk_cursor_wm_reg_max(dev, level);
1920 max->fbc = ilk_fbc_wm_reg_max(dev);
1921}
1922
d9395655 1923static bool ilk_validate_wm_level(int level,
820c1980 1924 const struct ilk_wm_maximums *max,
d9395655 1925 struct intel_wm_level *result)
a9786a11
VS		 1926{
1927 bool ret;
1928
1929 /* already determined to be invalid? */
1930 if (!result->enable)
1931 return false;
1932
1933 result->enable = result->pri_val <= max->pri &&
1934 result->spr_val <= max->spr &&
1935 result->cur_val <= max->cur;
1936
1937 ret = result->enable;
1938
1939 /*
1940 * HACK until we can pre-compute everything,
1941 * and thus fail gracefully if LP0 watermarks
1942 * are exceeded...
1943 */
1944 if (level == 0 && !result->enable) {
1945 if (result->pri_val > max->pri)
1946 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1947 level, result->pri_val, max->pri);
1948 if (result->spr_val > max->spr)
1949 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1950 level, result->spr_val, max->spr);
1951 if (result->cur_val > max->cur)
1952 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1953 level, result->cur_val, max->cur);
1954
1955 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1956 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1957 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1958 result->enable = true;
1959 }
1960
a9786a11
VS		 1961 return ret;
1962}
1963
d34ff9c6 1964static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1965 const struct intel_crtc *intel_crtc,
6f5ddd17 1966 int level,
7221fc33 1967 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1968 struct intel_plane_state *pristate,
1969 struct intel_plane_state *sprstate,
1970 struct intel_plane_state *curstate,
1fd527cc 1971 struct intel_wm_level *result)
6f5ddd17
VS		 1972{
1973 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1974 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1975 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1976
1977 /* WM1+ latency values stored in 0.5us units */
1978 if (level > 0) {
1979 pri_latency *= 5;
1980 spr_latency *= 5;
1981 cur_latency *= 5;
1982 }
1983
86c8bbbe
MR		 1984 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
1985 pri_latency, level);
1986 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
1987 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
1988 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 1989 result->enable = true;
1990}
1991
801bcfff
PZ		 1992static uint32_t
1993hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1994{
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7c5f93b0 1997 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1998 u32 linetime, ips_linetime;
1f8eeabf 1999
3ef00284 2000 if (!intel_crtc->active)
801bcfff 2001 return 0;
1011d8c4 2002
1f8eeabf
ED		 2003 /* The WM are computed with base on how long it takes to fill a single
2004 * row at the given clock rate, multiplied by 8.
2005 * */
124abe07
VS		 2006 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2007 adjusted_mode->crtc_clock);
2008 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2009 dev_priv->cdclk_freq);
1f8eeabf 2010
801bcfff
PZ		 2011 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2012 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2013}
2014
2af30a5c 2015static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2016{
2017 struct drm_i915_private *dev_priv = dev->dev_private;
2018
2af30a5c
PB		 2019 if (IS_GEN9(dev)) {
2020 uint32_t val;
4f947386 2021 int ret, i;
367294be 2022 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2023
2024 /* read the first set of memory latencies[0:3] */
2025 val = 0; /* data0 to be programmed to 0 for first set */
2026 mutex_lock(&dev_priv->rps.hw_lock);
2027 ret = sandybridge_pcode_read(dev_priv,
2028 GEN9_PCODE_READ_MEM_LATENCY,
2029 &val);
2030 mutex_unlock(&dev_priv->rps.hw_lock);
2031
2032 if (ret) {
2033 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2034 return;
2035 }
2036
2037 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2038 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2039 GEN9_MEM_LATENCY_LEVEL_MASK;
2040 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2041 GEN9_MEM_LATENCY_LEVEL_MASK;
2042 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2043 GEN9_MEM_LATENCY_LEVEL_MASK;
2044
2045 /* read the second set of memory latencies[4:7] */
2046 val = 1; /* data0 to be programmed to 1 for second set */
2047 mutex_lock(&dev_priv->rps.hw_lock);
2048 ret = sandybridge_pcode_read(dev_priv,
2049 GEN9_PCODE_READ_MEM_LATENCY,
2050 &val);
2051 mutex_unlock(&dev_priv->rps.hw_lock);
2052 if (ret) {
2053 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2054 return;
2055 }
2056
2057 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2058 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2059 GEN9_MEM_LATENCY_LEVEL_MASK;
2060 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2061 GEN9_MEM_LATENCY_LEVEL_MASK;
2062 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2063 GEN9_MEM_LATENCY_LEVEL_MASK;
2064
367294be 2065 /*
6f97235b
DL		 2066 * WaWmMemoryReadLatency:skl
2067 *
367294be
VK		 2068 * punit doesn't take into account the read latency so we need
2069 * to add 2us to the various latency levels we retrieve from
2070 * the punit.
2071 * - W0 is a bit special in that it's the only level that
2072 * can't be disabled if we want to have display working, so
2073 * we always add 2us there.
2074 * - For levels >=1, punit returns 0us latency when they are
2075 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2076 *
2077 * Additionally, if a level n (n > 1) has a 0us latency, all
2078 * levels m (m >= n) need to be disabled. We make sure to
2079 * sanitize the values out of the punit to satisfy this
2080 * requirement.
367294be
VK		 2081 */
2082 wm[0] += 2;
2083 for (level = 1; level <= max_level; level++)
2084 if (wm[level] != 0)
2085 wm[level] += 2;
4f947386
VK		 2086 else {
2087 for (i = level + 1; i <= max_level; i++)
2088 wm[i] = 0;
367294be 2089
4f947386
VK		 2090 break;
2091 }
2af30a5c 2092 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2093 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2094
2095 wm[0] = (sskpd >> 56) & 0xFF;
2096 if (wm[0] == 0)
2097 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2098 wm[1] = (sskpd >> 4) & 0xFF;
2099 wm[2] = (sskpd >> 12) & 0xFF;
2100 wm[3] = (sskpd >> 20) & 0x1FF;
2101 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2102 } else if (INTEL_INFO(dev)->gen >= 6) {
2103 uint32_t sskpd = I915_READ(MCH_SSKPD);
2104
2105 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2106 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2107 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2108 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2109 } else if (INTEL_INFO(dev)->gen >= 5) {
2110 uint32_t mltr = I915_READ(MLTR_ILK);
2111
2112 /* ILK primary LP0 latency is 700 ns */
2113 wm[0] = 7;
2114 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2115 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2116 }
2117}
2118
53615a5e
VS		 2119static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2120{
2121 /* ILK sprite LP0 latency is 1300 ns */
2122 if (INTEL_INFO(dev)->gen == 5)
2123 wm[0] = 13;
2124}
2125
2126static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2127{
2128 /* ILK cursor LP0 latency is 1300 ns */
2129 if (INTEL_INFO(dev)->gen == 5)
2130 wm[0] = 13;
2131
2132 /* WaDoubleCursorLP3Latency:ivb */
2133 if (IS_IVYBRIDGE(dev))
2134 wm[3] *= 2;
2135}
2136
546c81fd 2137int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2138{
26ec971e 2139 /* how many WM levels are we expecting */
b6e742f6 2140 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2141 return 7;
2142 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2143 return 4;
26ec971e 2144 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2145 return 3;
26ec971e 2146 else
ad0d6dc4
VS		 2147 return 2;
2148}
7526ed79 2149
ad0d6dc4
VS		 2150static void intel_print_wm_latency(struct drm_device *dev,
2151 const char *name,
2af30a5c 2152 const uint16_t wm[8])
ad0d6dc4
VS		 2153{
2154 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2155
2156 for (level = 0; level <= max_level; level++) {
2157 unsigned int latency = wm[level];
2158
2159 if (latency == 0) {
2160 DRM_ERROR("%s WM%d latency not provided\n",
2161 name, level);
2162 continue;
2163 }
2164
2af30a5c
PB		 2165 /*
2166 * - latencies are in us on gen9.
2167 * - before then, WM1+ latency values are in 0.5us units
2168 */
2169 if (IS_GEN9(dev))
2170 latency *= 10;
2171 else if (level > 0)
26ec971e
VS		 2172 latency *= 5;
2173
2174 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2175 name, level, wm[level],
2176 latency / 10, latency % 10);
2177 }
2178}
2179
e95a2f75
VS		 2180static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2181 uint16_t wm[5], uint16_t min)
2182{
2183 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2184
2185 if (wm[0] >= min)
2186 return false;
2187
2188 wm[0] = max(wm[0], min);
2189 for (level = 1; level <= max_level; level++)
2190 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2191
2192 return true;
2193}
2194
2195static void snb_wm_latency_quirk(struct drm_device *dev)
2196{
2197 struct drm_i915_private *dev_priv = dev->dev_private;
2198 bool changed;
2199
2200 /*
2201 * The BIOS provided WM memory latency values are often
2202 * inadequate for high resolution displays. Adjust them.
2203 */
2204 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2205 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2206 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2207
2208 if (!changed)
2209 return;
2210
2211 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2212 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2213 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2214 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2215}
2216
fa50ad61 2217static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2218{
2219 struct drm_i915_private *dev_priv = dev->dev_private;
2220
2221 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2222
2223 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2224 sizeof(dev_priv->wm.pri_latency));
2225 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2226 sizeof(dev_priv->wm.pri_latency));
2227
2228 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2229 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2230
2231 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2232 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2233 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2234
2235 if (IS_GEN6(dev))
2236 snb_wm_latency_quirk(dev);
53615a5e
VS		 2237}
2238
2af30a5c
PB		 2239static void skl_setup_wm_latency(struct drm_device *dev)
2240{
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242
2243 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2244 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2245}
2246
0b2ae6d7 2247/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2248static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2249 struct drm_atomic_state *state)
0b2ae6d7 2250{
86c8bbbe
MR		 2251 struct intel_pipe_wm *pipe_wm;
2252 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2253 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2254 struct intel_crtc_state *cstate = NULL;
43d59eda 2255 struct intel_plane *intel_plane;
86c8bbbe
MR		 2256 struct drm_plane_state *ps;
2257 struct intel_plane_state *pristate = NULL;
43d59eda 2258 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2259 struct intel_plane_state *curstate = NULL;
0b2ae6d7
VS		 2260 int level, max_level = ilk_wm_max_level(dev);
2261 /* LP0 watermark maximums depend on this pipe alone */
2262 struct intel_wm_config config = {
2263 .num_pipes_active = 1,
0b2ae6d7 2264 };
820c1980 2265 struct ilk_wm_maximums max;
0b2ae6d7 2266
86c8bbbe
MR		 2267 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2268 if (IS_ERR(cstate))
2269 return PTR_ERR(cstate);
2270
2271 pipe_wm = &cstate->wm.optimal.ilk;
2272
43d59eda 2273 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2274 ps = drm_atomic_get_plane_state(state,
2275 &intel_plane->base);
2276 if (IS_ERR(ps))
2277 return PTR_ERR(ps);
2278
2279 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2280 pristate = to_intel_plane_state(ps);
2281 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2282 sprstate = to_intel_plane_state(ps);
2283 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2284 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2285 }
2286
2287 config.sprites_enabled = sprstate->visible;
2288 config.sprites_scaled = sprstate->visible &&
2289 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2290 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2291
7221fc33 2292 pipe_wm->pipe_enabled = cstate->base.active;
86c8bbbe 2293 pipe_wm->sprites_enabled = config.sprites_enabled;
43d59eda 2294 pipe_wm->sprites_scaled = config.sprites_scaled;
2a44b76b 2295
7b39a0b7 2296 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2297 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2298 max_level = 1;
2299
2300 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
43d59eda 2301 if (config.sprites_scaled)
7b39a0b7
VS		 2302 max_level = 0;
2303
86c8bbbe
MR		 2304 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2305 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2306
a42a5719 2307 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
86c8bbbe
MR		 2308 pipe_wm->linetime = hsw_compute_linetime_wm(dev,
2309 &intel_crtc->base);
0b2ae6d7 2310
a3cb4048
VS		 2311 /* LP0 watermarks always use 1/2 DDB partitioning */
2312 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2313
0b2ae6d7 2314 /* At least LP0 must be valid */
a3cb4048 2315 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
86c8bbbe 2316 return -EINVAL;
a3cb4048
VS		 2317
2318 ilk_compute_wm_reg_maximums(dev, 1, &max);
2319
2320 for (level = 1; level <= max_level; level++) {
2321 struct intel_wm_level wm = {};
2322
86c8bbbe
MR		 2323 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2324 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2325
2326 /*
2327 * Disable any watermark level that exceeds the
2328 * register maximums since such watermarks are
2329 * always invalid.
2330 */
2331 if (!ilk_validate_wm_level(level, &max, &wm))
2332 break;
2333
2334 pipe_wm->wm[level] = wm;
2335 }
2336
86c8bbbe 2337 return 0;
0b2ae6d7
VS		 2338}
2339
2340/*
2341 * Merge the watermarks from all active pipes for a specific level.
2342 */
2343static void ilk_merge_wm_level(struct drm_device *dev,
2344 int level,
2345 struct intel_wm_level *ret_wm)
2346{
2347 const struct intel_crtc *intel_crtc;
2348
d52fea5b
VS		 2349 ret_wm->enable = true;
2350
d3fcc808 2351 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2352 const struct intel_crtc_state *cstate =
2353 to_intel_crtc_state(intel_crtc->base.state);
2354 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
fe392efd
VS		 2355 const struct intel_wm_level *wm = &active->wm[level];
2356
2357 if (!active->pipe_enabled)
2358 continue;
0b2ae6d7 2359
d52fea5b
VS		 2360 /*
2361 * The watermark values may have been used in the past,
2362 * so we must maintain them in the registers for some
2363 * time even if the level is now disabled.
2364 */
0b2ae6d7 2365 if (!wm->enable)
d52fea5b 2366 ret_wm->enable = false;
0b2ae6d7
VS		 2367
2368 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2369 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2370 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2371 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2372 }
0b2ae6d7
VS		 2373}
2374
2375/*
2376 * Merge all low power watermarks for all active pipes.
2377 */
2378static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2379 const struct intel_wm_config *config,
820c1980 2380 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2381 struct intel_pipe_wm *merged)
2382{
7733b49b 2383 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2384 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2385 int last_enabled_level = max_level;
0b2ae6d7 2386
0ba22e26
VS		 2387 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2388 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2389 config->num_pipes_active > 1)
2390 return;
2391
6c8b6c28
VS		 2392 /* ILK: FBC WM must be disabled always */
2393 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2394
2395 /* merge each WM1+ level */
2396 for (level = 1; level <= max_level; level++) {
2397 struct intel_wm_level *wm = &merged->wm[level];
2398
2399 ilk_merge_wm_level(dev, level, wm);
2400
d52fea5b
VS		 2401 if (level > last_enabled_level)
2402 wm->enable = false;
2403 else if (!ilk_validate_wm_level(level, max, wm))
2404 /* make sure all following levels get disabled */
2405 last_enabled_level = level - 1;
0b2ae6d7
VS		 2406
2407 /*
2408 * The spec says it is preferred to disable
2409 * FBC WMs instead of disabling a WM level.
2410 */
2411 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2412 if (wm->enable)
2413 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2414 wm->fbc_val = 0;
2415 }
2416 }
6c8b6c28
VS		 2417
2418 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2419 /*
2420 * FIXME this is racy. FBC might get enabled later.
2421 * What we should check here is whether FBC can be
2422 * enabled sometime later.
2423 */
7733b49b
PZ		 2424 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2425 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2426 for (level = 2; level <= max_level; level++) {
2427 struct intel_wm_level *wm = &merged->wm[level];
2428
2429 wm->enable = false;
2430 }
2431 }
0b2ae6d7
VS		 2432}
2433
b380ca3c
VS		 2434static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2435{
2436 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2437 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2438}
2439
a68d68ee
VS		 2440/* The value we need to program into the WM_LPx latency field */
2441static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2442{
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444
a42a5719 2445 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2446 return 2 * level;
2447 else
2448 return dev_priv->wm.pri_latency[level];
2449}
2450
820c1980 2451static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2452 const struct intel_pipe_wm *merged,
609cedef 2453 enum intel_ddb_partitioning partitioning,
820c1980 2454 struct ilk_wm_values *results)
801bcfff 2455{
0b2ae6d7
VS		 2456 struct intel_crtc *intel_crtc;
2457 int level, wm_lp;
cca32e9a 2458
0362c781 2459 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2460 results->partitioning = partitioning;
cca32e9a 2461
0b2ae6d7 2462 /* LP1+ register values */
cca32e9a 2463 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2464 const struct intel_wm_level *r;
801bcfff 2465
b380ca3c 2466 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2467
0362c781 2468 r = &merged->wm[level];
cca32e9a 2469
d52fea5b
VS		 2470 /*
2471 * Maintain the watermark values even if the level is
2472 * disabled. Doing otherwise could cause underruns.
2473 */
2474 results->wm_lp[wm_lp - 1] =
a68d68ee 2475 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2476 (r->pri_val << WM1_LP_SR_SHIFT) |
2477 r->cur_val;
2478
d52fea5b
VS		 2479 if (r->enable)
2480 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2481
416f4727
VS		 2482 if (INTEL_INFO(dev)->gen >= 8)
2483 results->wm_lp[wm_lp - 1] |=
2484 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2485 else
2486 results->wm_lp[wm_lp - 1] |=
2487 r->fbc_val << WM1_LP_FBC_SHIFT;
2488
d52fea5b
VS		 2489 /*
2490 * Always set WM1S_LP_EN when spr_val != 0, even if the
2491 * level is disabled. Doing otherwise could cause underruns.
2492 */
6cef2b8a
VS		 2493 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2494 WARN_ON(wm_lp != 1);
2495 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2496 } else
2497 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2498 }
801bcfff 2499
0b2ae6d7 2500 /* LP0 register values */
d3fcc808 2501 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2502 const struct intel_crtc_state *cstate =
2503 to_intel_crtc_state(intel_crtc->base.state);
0b2ae6d7 2504 enum pipe pipe = intel_crtc->pipe;
4e0963c7 2505 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
0b2ae6d7
VS		 2506
2507 if (WARN_ON(!r->enable))
2508 continue;
2509
4e0963c7 2510 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
1011d8c4 2511
0b2ae6d7
VS		 2512 results->wm_pipe[pipe] =
2513 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2514 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2515 r->cur_val;
801bcfff
PZ		 2516 }
2517}
2518
861f3389
PZ		 2519/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2520 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2521static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2522 struct intel_pipe_wm *r1,
2523 struct intel_pipe_wm *r2)
861f3389 2524{
198a1e9b
VS		 2525 int level, max_level = ilk_wm_max_level(dev);
2526 int level1 = 0, level2 = 0;
861f3389 2527
198a1e9b
VS		 2528 for (level = 1; level <= max_level; level++) {
2529 if (r1->wm[level].enable)
2530 level1 = level;
2531 if (r2->wm[level].enable)
2532 level2 = level;
861f3389
PZ		 2533 }
2534
198a1e9b
VS		 2535 if (level1 == level2) {
2536 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2537 return r2;
2538 else
2539 return r1;
198a1e9b 2540 } else if (level1 > level2) {
861f3389
PZ		 2541 return r1;
2542 } else {
2543 return r2;
2544 }
2545}
2546
49a687c4
VS		 2547/* dirty bits used to track which watermarks need changes */
2548#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2549#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2550#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2551#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2552#define WM_DIRTY_FBC (1 << 24)
2553#define WM_DIRTY_DDB (1 << 25)
2554
055e393f 2555static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2556 const struct ilk_wm_values *old,
2557 const struct ilk_wm_values *new)
49a687c4
VS		 2558{
2559 unsigned int dirty = 0;
2560 enum pipe pipe;
2561 int wm_lp;
2562
055e393f 2563 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2564 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2565 dirty |= WM_DIRTY_LINETIME(pipe);
2566 /* Must disable LP1+ watermarks too */
2567 dirty |= WM_DIRTY_LP_ALL;
2568 }
2569
2570 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2571 dirty |= WM_DIRTY_PIPE(pipe);
2572 /* Must disable LP1+ watermarks too */
2573 dirty |= WM_DIRTY_LP_ALL;
2574 }
2575 }
2576
2577 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2578 dirty |= WM_DIRTY_FBC;
2579 /* Must disable LP1+ watermarks too */
2580 dirty |= WM_DIRTY_LP_ALL;
2581 }
2582
2583 if (old->partitioning != new->partitioning) {
2584 dirty |= WM_DIRTY_DDB;
2585 /* Must disable LP1+ watermarks too */
2586 dirty |= WM_DIRTY_LP_ALL;
2587 }
2588
2589 /* LP1+ watermarks already deemed dirty, no need to continue */
2590 if (dirty & WM_DIRTY_LP_ALL)
2591 return dirty;
2592
2593 /* Find the lowest numbered LP1+ watermark in need of an update... */
2594 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2595 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2596 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2597 break;
2598 }
2599
2600 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2601 for (; wm_lp <= 3; wm_lp++)
2602 dirty |= WM_DIRTY_LP(wm_lp);
2603
2604 return dirty;
2605}
2606
8553c18e
VS		 2607static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2608 unsigned int dirty)
801bcfff 2609{
820c1980 2610 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2611 bool changed = false;
801bcfff 2612
facd619b
VS		 2613 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2614 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2615 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2616 changed = true;
facd619b
VS		 2617 }
2618 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2619 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2620 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2621 changed = true;
facd619b
VS		 2622 }
2623 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2624 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2625 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2626 changed = true;
facd619b 2627 }
801bcfff 2628
facd619b
VS		 2629 /*
2630 * Don't touch WM1S_LP_EN here.
2631 * Doing so could cause underruns.
2632 */
6cef2b8a 2633
8553c18e
VS		 2634 return changed;
2635}
2636
2637/*
2638 * The spec says we shouldn't write when we don't need, because every write
2639 * causes WMs to be re-evaluated, expending some power.
2640 */
820c1980
ID		 2641static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2642 struct ilk_wm_values *results)
8553c18e
VS		 2643{
2644 struct drm_device *dev = dev_priv->dev;
820c1980 2645 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2646 unsigned int dirty;
2647 uint32_t val;
2648
055e393f 2649 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2650 if (!dirty)
2651 return;
2652
2653 _ilk_disable_lp_wm(dev_priv, dirty);
2654
49a687c4 2655 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2656 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2657 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2658 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2659 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2660 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2661
49a687c4 2662 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2663 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2664 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2665 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2666 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2667 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2668
49a687c4 2669 if (dirty & WM_DIRTY_DDB) {
a42a5719 2670 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2671 val = I915_READ(WM_MISC);
2672 if (results->partitioning == INTEL_DDB_PART_1_2)
2673 val &= ~WM_MISC_DATA_PARTITION_5_6;
2674 else
2675 val |= WM_MISC_DATA_PARTITION_5_6;
2676 I915_WRITE(WM_MISC, val);
2677 } else {
2678 val = I915_READ(DISP_ARB_CTL2);
2679 if (results->partitioning == INTEL_DDB_PART_1_2)
2680 val &= ~DISP_DATA_PARTITION_5_6;
2681 else
2682 val |= DISP_DATA_PARTITION_5_6;
2683 I915_WRITE(DISP_ARB_CTL2, val);
2684 }
1011d8c4
PZ		 2685 }
2686
49a687c4 2687 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2688 val = I915_READ(DISP_ARB_CTL);
2689 if (results->enable_fbc_wm)
2690 val &= ~DISP_FBC_WM_DIS;
2691 else
2692 val |= DISP_FBC_WM_DIS;
2693 I915_WRITE(DISP_ARB_CTL, val);
2694 }
2695
954911eb
ID		 2696 if (dirty & WM_DIRTY_LP(1) &&
2697 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2698 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2699
2700 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2701 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2702 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2703 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2704 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2705 }
801bcfff 2706
facd619b 2707 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2708 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2709 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2710 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2711 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2712 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2713
2714 dev_priv->wm.hw = *results;
801bcfff
PZ		 2715}
2716
8553c18e
VS		 2717static bool ilk_disable_lp_wm(struct drm_device *dev)
2718{
2719 struct drm_i915_private *dev_priv = dev->dev_private;
2720
2721 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2722}
2723
b9cec075
DL		 2724/*
2725 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2726 * different active planes.
2727 */
2728
2729#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2730#define BXT_DDB_SIZE 512
b9cec075 2731
024c9045
MR		 2732/*
2733 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2734 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2735 * other universal planes are in indices 1..n. Note that this may leave unused
2736 * indices between the top "sprite" plane and the cursor.
2737 */
2738static int
2739skl_wm_plane_id(const struct intel_plane *plane)
2740{
2741 switch (plane->base.type) {
2742 case DRM_PLANE_TYPE_PRIMARY:
2743 return 0;
2744 case DRM_PLANE_TYPE_CURSOR:
2745 return PLANE_CURSOR;
2746 case DRM_PLANE_TYPE_OVERLAY:
2747 return plane->plane + 1;
2748 default:
2749 MISSING_CASE(plane->base.type);
2750 return plane->plane;
2751 }
2752}
2753
b9cec075
DL		 2754static void
2755skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2756 const struct intel_crtc_state *cstate,
b9cec075 2757 const struct intel_wm_config *config,
b9cec075
DL		 2758 struct skl_ddb_entry *alloc /* out */)
2759{
024c9045 2760 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2761 struct drm_crtc *crtc;
2762 unsigned int pipe_size, ddb_size;
2763 int nth_active_pipe;
2764
024c9045 2765 if (!cstate->base.active) {
b9cec075
DL		 2766 alloc->start = 0;
2767 alloc->end = 0;
2768 return;
2769 }
2770
43d735a6
DL		 2771 if (IS_BROXTON(dev))
2772 ddb_size = BXT_DDB_SIZE;
2773 else
2774 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2775
2776 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2777
2778 nth_active_pipe = 0;
2779 for_each_crtc(dev, crtc) {
3ef00284 2780 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2781 continue;
2782
2783 if (crtc == for_crtc)
2784 break;
2785
2786 nth_active_pipe++;
2787 }
2788
2789 pipe_size = ddb_size / config->num_pipes_active;
2790 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2791 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2792}
2793
2794static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2795{
2796 if (config->num_pipes_active == 1)
2797 return 32;
2798
2799 return 8;
2800}
2801
a269c583
DL		 2802static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2803{
2804 entry->start = reg & 0x3ff;
2805 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2806 if (entry->end)
2807 entry->end += 1;
a269c583
DL		 2808}
2809
08db6652
DL		 2810void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2811 struct skl_ddb_allocation *ddb /* out */)
a269c583 2812{
a269c583
DL		 2813 enum pipe pipe;
2814 int plane;
2815 u32 val;
2816
2817 for_each_pipe(dev_priv, pipe) {
dd740780 2818 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2819 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2820 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2821 val);
2822 }
2823
2824 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2825 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2826 val);
a269c583
DL		 2827 }
2828}
2829
b9cec075 2830static unsigned int
024c9045
MR		 2831skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2832 const struct drm_plane_state *pstate,
2833 int y)
b9cec075 2834{
024c9045
MR		 2835 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2836 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2837
2838 /* for planar format */
024c9045 2839 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2840 if (y) /* y-plane data rate */
024c9045
MR		 2841 return intel_crtc->config->pipe_src_w *
2842 intel_crtc->config->pipe_src_h *
2843 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2844 else /* uv-plane data rate */
024c9045
MR		 2845 return (intel_crtc->config->pipe_src_w/2) *
2846 (intel_crtc->config->pipe_src_h/2) *
2847 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2848 }
2849
2850 /* for packed formats */
024c9045
MR		 2851 return intel_crtc->config->pipe_src_w *
2852 intel_crtc->config->pipe_src_h *
2853 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2854}
2855
2856/*
2857 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2858 * a 8192x4096@32bpp framebuffer:
2859 * 3 * 4096 * 8192 * 4 < 2^32
2860 */
2861static unsigned int
024c9045 2862skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2863{
024c9045
MR		 2864 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2865 struct drm_device *dev = intel_crtc->base.dev;
2866 const struct intel_plane *intel_plane;
b9cec075 2867 unsigned int total_data_rate = 0;
b9cec075 2868
024c9045
MR		 2869 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2870 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2871
024c9045 2872 if (pstate->fb == NULL)
b9cec075
DL		 2873 continue;
2874
024c9045
MR		 2875 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2876 continue;
2877
2878 /* packed/uv */
2879 total_data_rate += skl_plane_relative_data_rate(cstate,
2880 pstate,
2881 0);
2882
2883 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2884 /* y-plane */
2885 total_data_rate += skl_plane_relative_data_rate(cstate,
2886 pstate,
2887 1);
b9cec075
DL		 2888 }
2889
2890 return total_data_rate;
2891}
2892
2893static void
024c9045 2894skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2895 struct skl_ddb_allocation *ddb /* out */)
2896{
024c9045 2897 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2898 struct drm_device *dev = crtc->dev;
aa363136
MR		 2899 struct drm_i915_private *dev_priv = to_i915(dev);
2900 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2902 struct intel_plane *intel_plane;
b9cec075 2903 enum pipe pipe = intel_crtc->pipe;
34bb56af 2904 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2905 uint16_t alloc_size, start, cursor_blocks;
80958155 2906 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2907 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2908 unsigned int total_data_rate;
b9cec075 2909
024c9045 2910 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2911 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2912 if (alloc_size == 0) {
2913 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2914 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2915 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2916 return;
2917 }
2918
2919 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2920 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2921 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2922
2923 alloc_size -= cursor_blocks;
34bb56af 2924 alloc->end -= cursor_blocks;
b9cec075 2925
80958155 2926 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 2927 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2928 struct drm_plane *plane = &intel_plane->base;
2929 struct drm_framebuffer *fb = plane->state->fb;
2930 int id = skl_wm_plane_id(intel_plane);
80958155 2931
024c9045
MR		 2932 if (fb == NULL)
2933 continue;
2934 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2935 continue;
2936
024c9045
MR		 2937 minimum[id] = 8;
2938 alloc_size -= minimum[id];
2939 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2940 alloc_size -= y_minimum[id];
80958155
DL		 2941 }
2942
b9cec075 2943 /*
80958155
DL		 2944 * 2. Distribute the remaining space in proportion to the amount of
2945 * data each plane needs to fetch from memory.
b9cec075
DL		 2946 *
2947 * FIXME: we may not allocate every single block here.
2948 */
024c9045 2949 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 2950
34bb56af 2951 start = alloc->start;
024c9045
MR		 2952 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2953 struct drm_plane *plane = &intel_plane->base;
2954 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 2955 unsigned int data_rate, y_data_rate;
2956 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 2957 int id = skl_wm_plane_id(intel_plane);
b9cec075 2958
024c9045
MR		 2959 if (pstate->fb == NULL)
2960 continue;
2961 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 2962 continue;
2963
024c9045 2964 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 2965
2966 /*
2cd601c6 2967 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 2968 * promote the expression to 64 bits to avoid overflowing, the
2969 * result is < available as data_rate / total_data_rate < 1
2970 */
024c9045 2971 plane_blocks = minimum[id];
80958155
DL		 2972 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2973 total_data_rate);
b9cec075 2974
024c9045
MR		 2975 ddb->plane[pipe][id].start = start;
2976 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 2977
2978 start += plane_blocks;
2cd601c6
CK		 2979
2980 /*
2981 * allocation for y_plane part of planar format:
2982 */
024c9045
MR		 2983 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
2984 y_data_rate = skl_plane_relative_data_rate(cstate,
2985 pstate,
2986 1);
2987 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 2988 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2989 total_data_rate);
2990
024c9045
MR		 2991 ddb->y_plane[pipe][id].start = start;
2992 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 2993
2994 start += y_plane_blocks;
2995 }
2996
b9cec075
DL		 2997 }
2998
2999}
3000
5cec258b 3001static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3002{
3003 /* TODO: Take into account the scalers once we support them */
2d112de7 3004 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3005}
3006
3007/*
3008 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3009 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3010 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3011 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3012*/
3013static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3014 uint32_t latency)
3015{
3016 uint32_t wm_intermediate_val, ret;
3017
3018 if (latency == 0)
3019 return UINT_MAX;
3020
d4c2aa60 3021 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3022 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3023
3024 return ret;
3025}
3026
3027static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3028 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3029 uint64_t tiling, uint32_t latency)
2d41c0b5 3030{
d4c2aa60
TU		 3031 uint32_t ret;
3032 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3033 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3034
3035 if (latency == 0)
3036 return UINT_MAX;
3037
3038 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3039
3040 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3041 tiling == I915_FORMAT_MOD_Yf_TILED) {
3042 plane_bytes_per_line *= 4;
3043 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3044 plane_blocks_per_line /= 4;
3045 } else {
3046 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3047 }
3048
2d41c0b5
PB		 3049 wm_intermediate_val = latency * pixel_rate;
3050 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3051 plane_blocks_per_line;
2d41c0b5
PB		 3052
3053 return ret;
3054}
3055
2d41c0b5
PB		 3056static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3057 const struct intel_crtc *intel_crtc)
3058{
3059 struct drm_device *dev = intel_crtc->base.dev;
3060 struct drm_i915_private *dev_priv = dev->dev_private;
3061 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3062
e6d90023
KM		 3063 /*
3064 * If ddb allocation of pipes changed, it may require recalculation of
3065 * watermarks
3066 */
3067 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3068 return true;
3069
3070 return false;
3071}
3072
d4c2aa60 3073static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3074 struct intel_crtc_state *cstate,
3075 struct intel_plane *intel_plane,
afb024aa 3076 uint16_t ddb_allocation,
d4c2aa60 3077 int level,
afb024aa
DL		 3078 uint16_t *out_blocks, /* out */
3079 uint8_t *out_lines /* out */)
2d41c0b5 3080{
024c9045
MR		 3081 struct drm_plane *plane = &intel_plane->base;
3082 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3083 uint32_t latency = dev_priv->wm.skl_latency[level];
3084 uint32_t method1, method2;
3085 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3086 uint32_t res_blocks, res_lines;
3087 uint32_t selected_result;
2cd601c6 3088 uint8_t bytes_per_pixel;
2d41c0b5 3089
024c9045 3090 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3091 return false;
3092
024c9045
MR		 3093 bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3094 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
2cd601c6 3095 bytes_per_pixel,
d4c2aa60 3096 latency);
024c9045
MR		 3097 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3098 cstate->base.adjusted_mode.crtc_htotal,
3099 cstate->pipe_src_w,
2cd601c6 3100 bytes_per_pixel,
024c9045 3101 fb->modifier[0],
d4c2aa60 3102 latency);
2d41c0b5 3103
024c9045 3104 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
d4c2aa60 3105 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3106
024c9045
MR		 3107 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3108 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3109 uint32_t min_scanlines = 4;
3110 uint32_t y_tile_minimum;
024c9045
MR		 3111 if (intel_rotation_90_or_270(plane->state->rotation)) {
3112 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3113 drm_format_plane_cpp(fb->pixel_format, 1) :
3114 drm_format_plane_cpp(fb->pixel_format, 0);
3115
3116 switch (bpp) {
1fc0a8f7
TU		 3117 case 1:
3118 min_scanlines = 16;
3119 break;
3120 case 2:
3121 min_scanlines = 8;
3122 break;
3123 case 8:
3124 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3125 }
1fc0a8f7
TU		 3126 }
3127 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3128 selected_result = max(method2, y_tile_minimum);
3129 } else {
3130 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3131 selected_result = min(method1, method2);
3132 else
3133 selected_result = method1;
3134 }
2d41c0b5 3135
d4c2aa60
TU		 3136 res_blocks = selected_result + 1;
3137 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3138
0fda6568 3139 if (level >= 1 && level <= 7) {
024c9045
MR		 3140 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3141 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3142 res_lines += 4;
3143 else
3144 res_blocks++;
3145 }
e6d66171 3146
d4c2aa60 3147 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3148 return false;
3149
3150 *out_blocks = res_blocks;
3151 *out_lines = res_lines;
2d41c0b5
PB		 3152
3153 return true;
3154}
3155
3156static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3157 struct skl_ddb_allocation *ddb,
024c9045 3158 struct intel_crtc_state *cstate,
2d41c0b5 3159 int level,
2d41c0b5
PB		 3160 struct skl_wm_level *result)
3161{
024c9045
MR		 3162 struct drm_device *dev = dev_priv->dev;
3163 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3164 struct intel_plane *intel_plane;
2d41c0b5 3165 uint16_t ddb_blocks;
024c9045
MR		 3166 enum pipe pipe = intel_crtc->pipe;
3167
3168 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3169 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3170
2d41c0b5
PB		 3171 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3172
d4c2aa60 3173 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3174 cstate,
3175 intel_plane,
2d41c0b5 3176 ddb_blocks,
d4c2aa60 3177 level,
2d41c0b5
PB		 3178 &result->plane_res_b[i],
3179 &result->plane_res_l[i]);
3180 }
2d41c0b5
PB		 3181}
3182
407b50f3 3183static uint32_t
024c9045 3184skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3185{
024c9045 3186 if (!cstate->base.active)
407b50f3
DL		 3187 return 0;
3188
024c9045 3189 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3190 return 0;
407b50f3 3191
024c9045
MR		 3192 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3193 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3194}
3195
024c9045 3196static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3197 struct skl_wm_level *trans_wm /* out */)
407b50f3 3198{
024c9045 3199 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3201 struct intel_plane *intel_plane;
9414f563 3202
024c9045 3203 if (!cstate->base.active)
407b50f3 3204 return;
9414f563
DL		 3205
3206 /* Until we know more, just disable transition WMs */
024c9045
MR		 3207 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3208 int i = skl_wm_plane_id(intel_plane);
3209
9414f563 3210 trans_wm->plane_en[i] = false;
024c9045 3211 }
407b50f3
DL		 3212}
3213
024c9045 3214static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3215 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3216 struct skl_pipe_wm *pipe_wm)
3217{
024c9045 3218 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3219 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3220 int level, max_level = ilk_wm_max_level(dev);
3221
3222 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3223 skl_compute_wm_level(dev_priv, ddb, cstate,
3224 level, &pipe_wm->wm[level]);
2d41c0b5 3225 }
024c9045 3226 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3227
024c9045 3228 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3229}
3230
3231static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3232 struct skl_pipe_wm *p_wm,
3233 struct skl_wm_values *r,
3234 struct intel_crtc *intel_crtc)
3235{
3236 int level, max_level = ilk_wm_max_level(dev);
3237 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3238 uint32_t temp;
3239 int i;
2d41c0b5
PB		 3240
3241 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3242 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3243 temp = 0;
2d41c0b5
PB		 3244
3245 temp |= p_wm->wm[level].plane_res_l[i] <<
3246 PLANE_WM_LINES_SHIFT;
3247 temp |= p_wm->wm[level].plane_res_b[i];
3248 if (p_wm->wm[level].plane_en[i])
3249 temp |= PLANE_WM_EN;
3250
3251 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3252 }
3253
3254 temp = 0;
2d41c0b5 3255
4969d33e
MR		 3256 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3257 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3258
4969d33e 3259 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3260 temp |= PLANE_WM_EN;
3261
4969d33e 3262 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3263
3264 }
3265
9414f563
DL		 3266 /* transition WMs */
3267 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3268 temp = 0;
3269 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3270 temp |= p_wm->trans_wm.plane_res_b[i];
3271 if (p_wm->trans_wm.plane_en[i])
3272 temp |= PLANE_WM_EN;
3273
3274 r->plane_trans[pipe][i] = temp;
3275 }
3276
3277 temp = 0;
4969d33e
MR		 3278 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3279 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3280 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3281 temp |= PLANE_WM_EN;
3282
4969d33e 3283 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3284
2d41c0b5
PB		 3285 r->wm_linetime[pipe] = p_wm->linetime;
3286}
3287
16160e3d
DL		 3288static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3289 const struct skl_ddb_entry *entry)
3290{
3291 if (entry->end)
3292 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3293 else
3294 I915_WRITE(reg, 0);
3295}
3296
2d41c0b5
PB		 3297static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3298 const struct skl_wm_values *new)
3299{
3300 struct drm_device *dev = dev_priv->dev;
3301 struct intel_crtc *crtc;
3302
3303 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3304 int i, level, max_level = ilk_wm_max_level(dev);
3305 enum pipe pipe = crtc->pipe;
3306
5d374d96
DL		 3307 if (!new->dirty[pipe])
3308 continue;
8211bd5b 3309
5d374d96 3310 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3311
5d374d96
DL		 3312 for (level = 0; level <= max_level; level++) {
3313 for (i = 0; i < intel_num_planes(crtc); i++)
3314 I915_WRITE(PLANE_WM(pipe, i, level),
3315 new->plane[pipe][i][level]);
3316 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3317 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3318 }
5d374d96
DL		 3319 for (i = 0; i < intel_num_planes(crtc); i++)
3320 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3321 new->plane_trans[pipe][i]);
4969d33e
MR		 3322 I915_WRITE(CUR_WM_TRANS(pipe),
3323 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3324
2cd601c6 3325 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3326 skl_ddb_entry_write(dev_priv,
3327 PLANE_BUF_CFG(pipe, i),
3328 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3329 skl_ddb_entry_write(dev_priv,
3330 PLANE_NV12_BUF_CFG(pipe, i),
3331 &new->ddb.y_plane[pipe][i]);
3332 }
5d374d96
DL		 3333
3334 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3335 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3336 }
2d41c0b5
PB		 3337}
3338
0e8fb7ba
DL		 3339/*
3340 * When setting up a new DDB allocation arrangement, we need to correctly
3341 * sequence the times at which the new allocations for the pipes are taken into
3342 * account or we'll have pipes fetching from space previously allocated to
3343 * another pipe.
3344 *
3345 * Roughly the sequence looks like:
3346 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3347 * overlapping with a previous light-up pipe (another way to put it is:
3348 * pipes with their new allocation strickly included into their old ones).
3349 * 2. re-allocate the other pipes that get their allocation reduced
3350 * 3. allocate the pipes having their allocation increased
3351 *
3352 * Steps 1. and 2. are here to take care of the following case:
3353 * - Initially DDB looks like this:
3354 * | B | C |
3355 * - enable pipe A.
3356 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3357 * allocation
3358 * | A | B | C |
3359 *
3360 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3361 */
3362
d21b795c
DL		 3363static void
3364skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3365{
0e8fb7ba
DL		 3366 int plane;
3367
d21b795c
DL		 3368 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3369
dd740780 3370 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3371 I915_WRITE(PLANE_SURF(pipe, plane),
3372 I915_READ(PLANE_SURF(pipe, plane)));
3373 }
3374 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3375}
3376
3377static bool
3378skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3379 const struct skl_ddb_allocation *new,
3380 enum pipe pipe)
3381{
3382 uint16_t old_size, new_size;
3383
3384 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3385 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3386
3387 return old_size != new_size &&
3388 new->pipe[pipe].start >= old->pipe[pipe].start &&
3389 new->pipe[pipe].end <= old->pipe[pipe].end;
3390}
3391
3392static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3393 struct skl_wm_values *new_values)
3394{
3395 struct drm_device *dev = dev_priv->dev;
3396 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3397 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3398 struct intel_crtc *crtc;
3399 enum pipe pipe;
3400
3401 new_ddb = &new_values->ddb;
3402 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3403
3404 /*
3405 * First pass: flush the pipes with the new allocation contained into
3406 * the old space.
3407 *
3408 * We'll wait for the vblank on those pipes to ensure we can safely
3409 * re-allocate the freed space without this pipe fetching from it.
3410 */
3411 for_each_intel_crtc(dev, crtc) {
3412 if (!crtc->active)
3413 continue;
3414
3415 pipe = crtc->pipe;
3416
3417 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3418 continue;
3419
d21b795c 3420 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3421 intel_wait_for_vblank(dev, pipe);
3422
3423 reallocated[pipe] = true;
3424 }
3425
3426
3427 /*
3428 * Second pass: flush the pipes that are having their allocation
3429 * reduced, but overlapping with a previous allocation.
3430 *
3431 * Here as well we need to wait for the vblank to make sure the freed
3432 * space is not used anymore.
3433 */
3434 for_each_intel_crtc(dev, crtc) {
3435 if (!crtc->active)
3436 continue;
3437
3438 pipe = crtc->pipe;
3439
3440 if (reallocated[pipe])
3441 continue;
3442
3443 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3444 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3445 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3446 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3447 reallocated[pipe] = true;
0e8fb7ba 3448 }
0e8fb7ba
DL		 3449 }
3450
3451 /*
3452 * Third pass: flush the pipes that got more space allocated.
3453 *
3454 * We don't need to actively wait for the update here, next vblank
3455 * will just get more DDB space with the correct WM values.
3456 */
3457 for_each_intel_crtc(dev, crtc) {
3458 if (!crtc->active)
3459 continue;
3460
3461 pipe = crtc->pipe;
3462
3463 /*
3464 * At this point, only the pipes more space than before are
3465 * left to re-allocate.
3466 */
3467 if (reallocated[pipe])
3468 continue;
3469
d21b795c 3470 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3471 }
3472}
3473
2d41c0b5 3474static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3475 struct skl_ddb_allocation *ddb, /* out */
3476 struct skl_pipe_wm *pipe_wm /* out */)
3477{
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3479 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3480
aa363136 3481 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3482 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3483
4e0963c7 3484 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3485 return false;
3486
4e0963c7 3487 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3488
2d41c0b5
PB		 3489 return true;
3490}
3491
3492static void skl_update_other_pipe_wm(struct drm_device *dev,
3493 struct drm_crtc *crtc,
2d41c0b5
PB		 3494 struct skl_wm_values *r)
3495{
3496 struct intel_crtc *intel_crtc;
3497 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3498
3499 /*
3500 * If the WM update hasn't changed the allocation for this_crtc (the
3501 * crtc we are currently computing the new WM values for), other
3502 * enabled crtcs will keep the same allocation and we don't need to
3503 * recompute anything for them.
3504 */
3505 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3506 return;
3507
3508 /*
3509 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3510 * other active pipes need new DDB allocation and WM values.
3511 */
3512 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3513 base.head) {
2d41c0b5
PB		 3514 struct skl_pipe_wm pipe_wm = {};
3515 bool wm_changed;
3516
3517 if (this_crtc->pipe == intel_crtc->pipe)
3518 continue;
3519
3520 if (!intel_crtc->active)
3521 continue;
3522
aa363136 3523 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3524 &r->ddb, &pipe_wm);
3525
3526 /*
3527 * If we end up re-computing the other pipe WM values, it's
3528 * because it was really needed, so we expect the WM values to
3529 * be different.
3530 */
3531 WARN_ON(!wm_changed);
3532
024c9045 3533 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3534 r->dirty[intel_crtc->pipe] = true;
3535 }
3536}
3537
adda50b8
BP		 3538static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3539{
3540 watermarks->wm_linetime[pipe] = 0;
3541 memset(watermarks->plane[pipe], 0,
3542 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3543 memset(watermarks->plane_trans[pipe],
3544 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3545 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3546
3547 /* Clear ddb entries for pipe */
3548 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3549 memset(&watermarks->ddb.plane[pipe], 0,
3550 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3551 memset(&watermarks->ddb.y_plane[pipe], 0,
3552 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3553 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3554 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3555
3556}
3557
2d41c0b5
PB		 3558static void skl_update_wm(struct drm_crtc *crtc)
3559{
3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561 struct drm_device *dev = crtc->dev;
3562 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3563 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3564 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3565 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3566
adda50b8
BP		 3567
3568 /* Clear all dirty flags */
3569 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3570
3571 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3572
aa363136 3573 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3574 return;
3575
4e0963c7 3576 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3577 results->dirty[intel_crtc->pipe] = true;
3578
aa363136 3579 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3580 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3581 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3582
3583 /* store the new configuration */
3584 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3585}
3586
b9d5c839 3587static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3588{
b9d5c839
VS		 3589 struct drm_device *dev = dev_priv->dev;
3590 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3591 struct ilk_wm_maximums max;
aa363136 3592 struct intel_wm_config *config = &dev_priv->wm.config;
820c1980 3593 struct ilk_wm_values results = {};
77c122bc 3594 enum intel_ddb_partitioning partitioning;
261a27d1 3595
aa363136
MR		 3596 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3597 ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
a485bfb8
VS		 3598
3599 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3600 if (INTEL_INFO(dev)->gen >= 7 &&
aa363136
MR		 3601 config->num_pipes_active == 1 && config->sprites_enabled) {
3602 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3603 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
0362c781 3604
820c1980 3605 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3606 } else {
198a1e9b 3607 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3608 }
3609
198a1e9b 3610 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3611 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3612
820c1980 3613 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3614
820c1980 3615 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3616}
3617
b9d5c839
VS		 3618static void ilk_update_wm(struct drm_crtc *crtc)
3619{
3620 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
b9d5c839
VS		 3623
3624 WARN_ON(cstate->base.active != intel_crtc->active);
3625
3626 /*
3627 * IVB workaround: must disable low power watermarks for at least
3628 * one frame before enabling scaling. LP watermarks can be re-enabled
3629 * when scaling is disabled.
3630 *
3631 * WaCxSRDisabledForSpriteScaling:ivb
3632 */
3633 if (cstate->disable_lp_wm) {
3634 ilk_disable_lp_wm(crtc->dev);
3635 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3636 }
3637
4e0963c7 3638 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
b9d5c839
VS		 3639
3640 ilk_program_watermarks(dev_priv);
3641}
3642
3078999f
PB		 3643static void skl_pipe_wm_active_state(uint32_t val,
3644 struct skl_pipe_wm *active,
3645 bool is_transwm,
3646 bool is_cursor,
3647 int i,
3648 int level)
3649{
3650 bool is_enabled = (val & PLANE_WM_EN) != 0;
3651
3652 if (!is_transwm) {
3653 if (!is_cursor) {
3654 active->wm[level].plane_en[i] = is_enabled;
3655 active->wm[level].plane_res_b[i] =
3656 val & PLANE_WM_BLOCKS_MASK;
3657 active->wm[level].plane_res_l[i] =
3658 (val >> PLANE_WM_LINES_SHIFT) &
3659 PLANE_WM_LINES_MASK;
3660 } else {
4969d33e
MR		 3661 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3662 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3663 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3664 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3665 (val >> PLANE_WM_LINES_SHIFT) &
3666 PLANE_WM_LINES_MASK;
3667 }
3668 } else {
3669 if (!is_cursor) {
3670 active->trans_wm.plane_en[i] = is_enabled;
3671 active->trans_wm.plane_res_b[i] =
3672 val & PLANE_WM_BLOCKS_MASK;
3673 active->trans_wm.plane_res_l[i] =
3674 (val >> PLANE_WM_LINES_SHIFT) &
3675 PLANE_WM_LINES_MASK;
3676 } else {
4969d33e
MR		 3677 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3678 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3679 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3680 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3681 (val >> PLANE_WM_LINES_SHIFT) &
3682 PLANE_WM_LINES_MASK;
3683 }
3684 }
3685}
3686
3687static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3688{
3689 struct drm_device *dev = crtc->dev;
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3693 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3694 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3695 enum pipe pipe = intel_crtc->pipe;
3696 int level, i, max_level;
3697 uint32_t temp;
3698
3699 max_level = ilk_wm_max_level(dev);
3700
3701 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3702
3703 for (level = 0; level <= max_level; level++) {
3704 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3705 hw->plane[pipe][i][level] =
3706 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3707 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3708 }
3709
3710 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3711 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3712 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3713
3ef00284 3714 if (!intel_crtc->active)
3078999f
PB		 3715 return;
3716
3717 hw->dirty[pipe] = true;
3718
3719 active->linetime = hw->wm_linetime[pipe];
3720
3721 for (level = 0; level <= max_level; level++) {
3722 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3723 temp = hw->plane[pipe][i][level];
3724 skl_pipe_wm_active_state(temp, active, false,
3725 false, i, level);
3726 }
4969d33e 3727 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3728 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3729 }
3730
3731 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3732 temp = hw->plane_trans[pipe][i];
3733 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3734 }
3735
4969d33e 3736 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3737 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3738
3739 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3740}
3741
3742void skl_wm_get_hw_state(struct drm_device *dev)
3743{
a269c583
DL		 3744 struct drm_i915_private *dev_priv = dev->dev_private;
3745 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3746 struct drm_crtc *crtc;
3747
a269c583 3748 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3749 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3750 skl_pipe_wm_get_hw_state(crtc);
3751}
3752
243e6a44
VS		 3753static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3754{
3755 struct drm_device *dev = crtc->dev;
3756 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3757 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3759 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3760 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44
VS		 3761 enum pipe pipe = intel_crtc->pipe;
3762 static const unsigned int wm0_pipe_reg[] = {
3763 [PIPE_A] = WM0_PIPEA_ILK,
3764 [PIPE_B] = WM0_PIPEB_ILK,
3765 [PIPE_C] = WM0_PIPEC_IVB,
3766 };
3767
3768 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3769 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3770 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3771
3ef00284 3772 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3773
3774 if (active->pipe_enabled) {
243e6a44
VS		 3775 u32 tmp = hw->wm_pipe[pipe];
3776
3777 /*
3778 * For active pipes LP0 watermark is marked as
3779 * enabled, and LP1+ watermaks as disabled since
3780 * we can't really reverse compute them in case
3781 * multiple pipes are active.
3782 */
3783 active->wm[0].enable = true;
3784 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3785 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3786 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3787 active->linetime = hw->wm_linetime[pipe];
3788 } else {
3789 int level, max_level = ilk_wm_max_level(dev);
3790
3791 /*
3792 * For inactive pipes, all watermark levels
3793 * should be marked as enabled but zeroed,
3794 * which is what we'd compute them to.
3795 */
3796 for (level = 0; level <= max_level; level++)
3797 active->wm[level].enable = true;
3798 }
4e0963c7
MR		 3799
3800 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3801}
3802
6eb1a681
VS		 3803#define _FW_WM(value, plane) \
3804 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3805#define _FW_WM_VLV(value, plane) \
3806 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3807
3808static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3809 struct vlv_wm_values *wm)
3810{
3811 enum pipe pipe;
3812 uint32_t tmp;
3813
3814 for_each_pipe(dev_priv, pipe) {
3815 tmp = I915_READ(VLV_DDL(pipe));
3816
3817 wm->ddl[pipe].primary =
3818 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3819 wm->ddl[pipe].cursor =
3820 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3821 wm->ddl[pipe].sprite[0] =
3822 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3823 wm->ddl[pipe].sprite[1] =
3824 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3825 }
3826
3827 tmp = I915_READ(DSPFW1);
3828 wm->sr.plane = _FW_WM(tmp, SR);
3829 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3830 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3831 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3832
3833 tmp = I915_READ(DSPFW2);
3834 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3835 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3836 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3837
3838 tmp = I915_READ(DSPFW3);
3839 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3840
3841 if (IS_CHERRYVIEW(dev_priv)) {
3842 tmp = I915_READ(DSPFW7_CHV);
3843 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3844 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3845
3846 tmp = I915_READ(DSPFW8_CHV);
3847 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3848 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3849
3850 tmp = I915_READ(DSPFW9_CHV);
3851 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3852 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3853
3854 tmp = I915_READ(DSPHOWM);
3855 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3856 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3857 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3858 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3859 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3860 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3861 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3862 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3863 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3864 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3865 } else {
3866 tmp = I915_READ(DSPFW7);
3867 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3868 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3869
3870 tmp = I915_READ(DSPHOWM);
3871 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3872 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3873 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3874 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3875 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3876 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3877 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3878 }
3879}
3880
3881#undef _FW_WM
3882#undef _FW_WM_VLV
3883
3884void vlv_wm_get_hw_state(struct drm_device *dev)
3885{
3886 struct drm_i915_private *dev_priv = to_i915(dev);
3887 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3888 struct intel_plane *plane;
3889 enum pipe pipe;
3890 u32 val;
3891
3892 vlv_read_wm_values(dev_priv, wm);
3893
3894 for_each_intel_plane(dev, plane) {
3895 switch (plane->base.type) {
3896 int sprite;
3897 case DRM_PLANE_TYPE_CURSOR:
3898 plane->wm.fifo_size = 63;
3899 break;
3900 case DRM_PLANE_TYPE_PRIMARY:
3901 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3902 break;
3903 case DRM_PLANE_TYPE_OVERLAY:
3904 sprite = plane->plane;
3905 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3906 break;
3907 }
3908 }
3909
3910 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3911 wm->level = VLV_WM_LEVEL_PM2;
3912
3913 if (IS_CHERRYVIEW(dev_priv)) {
3914 mutex_lock(&dev_priv->rps.hw_lock);
3915
3916 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3917 if (val & DSP_MAXFIFO_PM5_ENABLE)
3918 wm->level = VLV_WM_LEVEL_PM5;
3919
58590c14
VS		 3920 /*
3921 * If DDR DVFS is disabled in the BIOS, Punit
3922 * will never ack the request. So if that happens
3923 * assume we don't have to enable/disable DDR DVFS
3924 * dynamically. To test that just set the REQ_ACK
3925 * bit to poke the Punit, but don't change the
3926 * HIGH/LOW bits so that we don't actually change
3927 * the current state.
3928 */
6eb1a681 3929 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3930 val |= FORCE_DDR_FREQ_REQ_ACK;
3931 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3932
3933 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3934 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3935 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3936 "assuming DDR DVFS is disabled\n");
3937 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3938 } else {
3939 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3940 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3941 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3942 }
6eb1a681
VS		 3943
3944 mutex_unlock(&dev_priv->rps.hw_lock);
3945 }
3946
3947 for_each_pipe(dev_priv, pipe)
3948 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3949 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
3950 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
3951
3952 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3953 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3954}
3955
243e6a44
VS		 3956void ilk_wm_get_hw_state(struct drm_device *dev)
3957{
3958 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3959 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3960 struct drm_crtc *crtc;
3961
70e1e0ec 3962 for_each_crtc(dev, crtc)
243e6a44
VS		 3963 ilk_pipe_wm_get_hw_state(crtc);
3964
3965 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3966 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3967 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3968
3969 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3970 if (INTEL_INFO(dev)->gen >= 7) {
3971 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3972 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3973 }
243e6a44 3974
a42a5719 3975 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3976 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3977 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3978 else if (IS_IVYBRIDGE(dev))
3979 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3980 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3981
3982 hw->enable_fbc_wm =
3983 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3984}
3985
b445e3b0
ED		 3986/**
3987 * intel_update_watermarks - update FIFO watermark values based on current modes
3988 *
3989 * Calculate watermark values for the various WM regs based on current mode
3990 * and plane configuration.
3991 *
3992 * There are several cases to deal with here:
3993 * - normal (i.e. non-self-refresh)
3994 * - self-refresh (SR) mode
3995 * - lines are large relative to FIFO size (buffer can hold up to 2)
3996 * - lines are small relative to FIFO size (buffer can hold more than 2
3997 * lines), so need to account for TLB latency
3998 *
3999 * The normal calculation is:
4000 * watermark = dotclock * bytes per pixel * latency
4001 * where latency is platform & configuration dependent (we assume pessimal
4002 * values here).
4003 *
4004 * The SR calculation is:
4005 * watermark = (trunc(latency/line time)+1) * surface width *
4006 * bytes per pixel
4007 * where
4008 * line time = htotal / dotclock
4009 * surface width = hdisplay for normal plane and 64 for cursor
4010 * and latency is assumed to be high, as above.
4011 *
4012 * The final value programmed to the register should always be rounded up,
4013 * and include an extra 2 entries to account for clock crossings.
4014 *
4015 * We don't use the sprite, so we can ignore that. And on Crestline we have
4016 * to set the non-SR watermarks to 8.
4017 */
46ba614c 4018void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4019{
46ba614c 4020 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4021
4022 if (dev_priv->display.update_wm)
46ba614c 4023 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4024}
4025
9270388e
DV		 4026/**
4027 * Lock protecting IPS related data structures
9270388e
DV		 4028 */
4029DEFINE_SPINLOCK(mchdev_lock);
4030
4031/* Global for IPS driver to get at the current i915 device. Protected by
4032 * mchdev_lock. */
4033static struct drm_i915_private *i915_mch_dev;
4034
2b4e57bd
ED		 4035bool ironlake_set_drps(struct drm_device *dev, u8 val)
4036{
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 u16 rgvswctl;
4039
9270388e
DV		 4040 assert_spin_locked(&mchdev_lock);
4041
2b4e57bd
ED		 4042 rgvswctl = I915_READ16(MEMSWCTL);
4043 if (rgvswctl & MEMCTL_CMD_STS) {
4044 DRM_DEBUG("gpu busy, RCS change rejected\n");
4045 return false; /* still busy with another command */
4046 }
4047
4048 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4049 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4050 I915_WRITE16(MEMSWCTL, rgvswctl);
4051 POSTING_READ16(MEMSWCTL);
4052
4053 rgvswctl |= MEMCTL_CMD_STS;
4054 I915_WRITE16(MEMSWCTL, rgvswctl);
4055
4056 return true;
4057}
4058
8090c6b9 4059static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4060{
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 u32 rgvmodectl = I915_READ(MEMMODECTL);
4063 u8 fmax, fmin, fstart, vstart;
4064
9270388e
DV		 4065 spin_lock_irq(&mchdev_lock);
4066
2b4e57bd
ED		 4067 /* Enable temp reporting */
4068 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4069 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4070
4071 /* 100ms RC evaluation intervals */
4072 I915_WRITE(RCUPEI, 100000);
4073 I915_WRITE(RCDNEI, 100000);
4074
4075 /* Set max/min thresholds to 90ms and 80ms respectively */
4076 I915_WRITE(RCBMAXAVG, 90000);
4077 I915_WRITE(RCBMINAVG, 80000);
4078
4079 I915_WRITE(MEMIHYST, 1);
4080
4081 /* Set up min, max, and cur for interrupt handling */
4082 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4083 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4084 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4085 MEMMODE_FSTART_SHIFT;
4086
616847e7 4087 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4088 PXVFREQ_PX_SHIFT;
4089
20e4d407
DV		 4090 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4091 dev_priv->ips.fstart = fstart;
2b4e57bd 4092
20e4d407
DV		 4093 dev_priv->ips.max_delay = fstart;
4094 dev_priv->ips.min_delay = fmin;
4095 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4096
4097 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4098 fmax, fmin, fstart);
4099
4100 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4101
4102 /*
4103 * Interrupts will be enabled in ironlake_irq_postinstall
4104 */
4105
4106 I915_WRITE(VIDSTART, vstart);
4107 POSTING_READ(VIDSTART);
4108
4109 rgvmodectl |= MEMMODE_SWMODE_EN;
4110 I915_WRITE(MEMMODECTL, rgvmodectl);
4111
9270388e 4112 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4113 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4114 mdelay(1);
2b4e57bd
ED		 4115
4116 ironlake_set_drps(dev, fstart);
4117
7d81c3e0
VS		 4118 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4119 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4120 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4121 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4122 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4123
4124 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4125}
4126
8090c6b9 4127static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4128{
4129 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4130 u16 rgvswctl;
4131
4132 spin_lock_irq(&mchdev_lock);
4133
4134 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4135
4136 /* Ack interrupts, disable EFC interrupt */
4137 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4138 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4139 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4140 I915_WRITE(DEIIR, DE_PCU_EVENT);
4141 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4142
4143 /* Go back to the starting frequency */
20e4d407 4144 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4145 mdelay(1);
2b4e57bd
ED		 4146 rgvswctl |= MEMCTL_CMD_STS;
4147 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4148 mdelay(1);
2b4e57bd 4149
9270388e 4150 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4151}
4152
acbe9475
DV		 4153/* There's a funny hw issue where the hw returns all 0 when reading from
4154 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4155 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4156 * all limits and the gpu stuck at whatever frequency it is at atm).
4157 */
74ef1173 4158static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4159{
7b9e0ae6 4160 u32 limits;
2b4e57bd 4161
20b46e59
DV		 4162 /* Only set the down limit when we've reached the lowest level to avoid
4163 * getting more interrupts, otherwise leave this clear. This prevents a
4164 * race in the hw when coming out of rc6: There's a tiny window where
4165 * the hw runs at the minimal clock before selecting the desired
4166 * frequency, if the down threshold expires in that window we will not
4167 * receive a down interrupt. */
74ef1173
AG		 4168 if (IS_GEN9(dev_priv->dev)) {
4169 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4170 if (val <= dev_priv->rps.min_freq_softlimit)
4171 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4172 } else {
4173 limits = dev_priv->rps.max_freq_softlimit << 24;
4174 if (val <= dev_priv->rps.min_freq_softlimit)
4175 limits |= dev_priv->rps.min_freq_softlimit << 16;
4176 }
20b46e59
DV		 4177
4178 return limits;
4179}
4180
dd75fdc8
CW		 4181static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4182{
4183 int new_power;
8a586437
AG		 4184 u32 threshold_up = 0, threshold_down = 0; /* in % */
4185 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4186
4187 new_power = dev_priv->rps.power;
4188 switch (dev_priv->rps.power) {
4189 case LOW_POWER:
b39fb297 4190 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4191 new_power = BETWEEN;
4192 break;
4193
4194 case BETWEEN:
b39fb297 4195 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4196 new_power = LOW_POWER;
b39fb297 4197 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4198 new_power = HIGH_POWER;
4199 break;
4200
4201 case HIGH_POWER:
b39fb297 4202 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4203 new_power = BETWEEN;
4204 break;
4205 }
4206 /* Max/min bins are special */
aed242ff 4207 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4208 new_power = LOW_POWER;
aed242ff 4209 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4210 new_power = HIGH_POWER;
4211 if (new_power == dev_priv->rps.power)
4212 return;
4213
4214 /* Note the units here are not exactly 1us, but 1280ns. */
4215 switch (new_power) {
4216 case LOW_POWER:
4217 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4218 ei_up = 16000;
4219 threshold_up = 95;
dd75fdc8
CW		 4220
4221 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4222 ei_down = 32000;
4223 threshold_down = 85;
dd75fdc8
CW		 4224 break;
4225
4226 case BETWEEN:
4227 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4228 ei_up = 13000;
4229 threshold_up = 90;
dd75fdc8
CW		 4230
4231 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4232 ei_down = 32000;
4233 threshold_down = 75;
dd75fdc8
CW		 4234 break;
4235
4236 case HIGH_POWER:
4237 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4238 ei_up = 10000;
4239 threshold_up = 85;
dd75fdc8
CW		 4240
4241 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4242 ei_down = 32000;
4243 threshold_down = 60;
dd75fdc8
CW		 4244 break;
4245 }
4246
8a586437
AG		 4247 I915_WRITE(GEN6_RP_UP_EI,
4248 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4249 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4250 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4251
4252 I915_WRITE(GEN6_RP_DOWN_EI,
4253 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4254 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4255 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4256
4257 I915_WRITE(GEN6_RP_CONTROL,
4258 GEN6_RP_MEDIA_TURBO |
4259 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4260 GEN6_RP_MEDIA_IS_GFX |
4261 GEN6_RP_ENABLE |
4262 GEN6_RP_UP_BUSY_AVG |
4263 GEN6_RP_DOWN_IDLE_AVG);
4264
dd75fdc8 4265 dev_priv->rps.power = new_power;
8fb55197
CW		 4266 dev_priv->rps.up_threshold = threshold_up;
4267 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4268 dev_priv->rps.last_adj = 0;
4269}
4270
2876ce73
CW		 4271static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4272{
4273 u32 mask = 0;
4274
4275 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4276 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4277 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4278 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4279
7b3c29f6
CW		 4280 mask &= dev_priv->pm_rps_events;
4281
59d02a1f 4282 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4283}
4284
b8a5ff8d
JM		 4285/* gen6_set_rps is called to update the frequency request, but should also be
4286 * called when the range (min_delay and max_delay) is modified so that we can
4287 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4288static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4289{
4290 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4291
23eafea6 4292 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4293 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4294 return;
4295
4fc688ce 4296 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4297 WARN_ON(val > dev_priv->rps.max_freq);
4298 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4299
eb64cad1
CW		 4300 /* min/max delay may still have been modified so be sure to
4301 * write the limits value.
4302 */
4303 if (val != dev_priv->rps.cur_freq) {
4304 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4305
5704195c
AG		 4306 if (IS_GEN9(dev))
4307 I915_WRITE(GEN6_RPNSWREQ,
4308 GEN9_FREQUENCY(val));
4309 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4310 I915_WRITE(GEN6_RPNSWREQ,
4311 HSW_FREQUENCY(val));
4312 else
4313 I915_WRITE(GEN6_RPNSWREQ,
4314 GEN6_FREQUENCY(val) |
4315 GEN6_OFFSET(0) |
4316 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4317 }
7b9e0ae6 4318
7b9e0ae6
CW		 4319 /* Make sure we continue to get interrupts
4320 * until we hit the minimum or maximum frequencies.
4321 */
74ef1173 4322 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4323 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4324
d5570a72
BW		 4325 POSTING_READ(GEN6_RPNSWREQ);
4326
b39fb297 4327 dev_priv->rps.cur_freq = val;
be2cde9a 4328 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4329}
4330
ffe02b40
VS		 4331static void valleyview_set_rps(struct drm_device *dev, u8 val)
4332{
4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334
4335 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4336 WARN_ON(val > dev_priv->rps.max_freq);
4337 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4338
4339 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4340 "Odd GPU freq value\n"))
4341 val &= ~1;
4342
cd25dd5b
D		 4343 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4344
8fb55197 4345 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4346 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4347 if (!IS_CHERRYVIEW(dev_priv))
4348 gen6_set_rps_thresholds(dev_priv, val);
4349 }
ffe02b40 4350
ffe02b40
VS		 4351 dev_priv->rps.cur_freq = val;
4352 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4353}
4354
a7f6e231 4355/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4356 *
4357 * * If Gfx is Idle, then
a7f6e231
D		 4358 * 1. Forcewake Media well.
4359 * 2. Request idle freq.
4360 * 3. Release Forcewake of Media well.
76c3552f
D		 4361*/
4362static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4363{
aed242ff 4364 u32 val = dev_priv->rps.idle_freq;
5549d25f 4365
aed242ff 4366 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4367 return;
4368
a7f6e231
D		 4369 /* Wake up the media well, as that takes a lot less
4370 * power than the Render well. */
4371 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4372 valleyview_set_rps(dev_priv->dev, val);
4373 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4374}
4375
43cf3bf0
CW		 4376void gen6_rps_busy(struct drm_i915_private *dev_priv)
4377{
4378 mutex_lock(&dev_priv->rps.hw_lock);
4379 if (dev_priv->rps.enabled) {
4380 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4381 gen6_rps_reset_ei(dev_priv);
4382 I915_WRITE(GEN6_PMINTRMSK,
4383 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4384 }
4385 mutex_unlock(&dev_priv->rps.hw_lock);
4386}
4387
b29c19b6
CW		 4388void gen6_rps_idle(struct drm_i915_private *dev_priv)
4389{
691bb717
DL		 4390 struct drm_device *dev = dev_priv->dev;
4391
b29c19b6 4392 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4393 if (dev_priv->rps.enabled) {
21a11fff 4394 if (IS_VALLEYVIEW(dev))
76c3552f 4395 vlv_set_rps_idle(dev_priv);
7526ed79 4396 else
aed242ff 4397 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4398 dev_priv->rps.last_adj = 0;
43cf3bf0 4399 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4400 }
8d3afd7d 4401 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4402
8d3afd7d 4403 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4404 while (!list_empty(&dev_priv->rps.clients))
4405 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4406 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4407}
4408
1854d5ca 4409void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4410 struct intel_rps_client *rps,
4411 unsigned long submitted)
b29c19b6 4412{
8d3afd7d
CW		 4413 /* This is intentionally racy! We peek at the state here, then
4414 * validate inside the RPS worker.
4415 */
4416 if (!(dev_priv->mm.busy &&
4417 dev_priv->rps.enabled &&
4418 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4419 return;
43cf3bf0 4420
e61b9958
CW		 4421 /* Force a RPS boost (and don't count it against the client) if
4422 * the GPU is severely congested.
4423 */
d0bc54f2 4424 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4425 rps = NULL;
4426
8d3afd7d
CW		 4427 spin_lock(&dev_priv->rps.client_lock);
4428 if (rps == NULL || list_empty(&rps->link)) {
4429 spin_lock_irq(&dev_priv->irq_lock);
4430 if (dev_priv->rps.interrupts_enabled) {
4431 dev_priv->rps.client_boost = true;
4432 queue_work(dev_priv->wq, &dev_priv->rps.work);
4433 }
4434 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4435
2e1b8730
CW		 4436 if (rps != NULL) {
4437 list_add(&rps->link, &dev_priv->rps.clients);
4438 rps->boosts++;
1854d5ca
CW		 4439 } else
4440 dev_priv->rps.boosts++;
c0951f0c 4441 }
8d3afd7d 4442 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4443}
4444
ffe02b40 4445void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4446{
ffe02b40
VS		 4447 if (IS_VALLEYVIEW(dev))
4448 valleyview_set_rps(dev, val);
4449 else
4450 gen6_set_rps(dev, val);
0a073b84
JB		 4451}
4452
20e49366
ZW		 4453static void gen9_disable_rps(struct drm_device *dev)
4454{
4455 struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4458 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4459}
4460
44fc7d5c 4461static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4462{
4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464
4465 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4466 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4467}
4468
38807746
D		 4469static void cherryview_disable_rps(struct drm_device *dev)
4470{
4471 struct drm_i915_private *dev_priv = dev->dev_private;
4472
4473 I915_WRITE(GEN6_RC_CONTROL, 0);
4474}
4475
44fc7d5c
DV		 4476static void valleyview_disable_rps(struct drm_device *dev)
4477{
4478 struct drm_i915_private *dev_priv = dev->dev_private;
4479
98a2e5f9
D		 4480 /* we're doing forcewake before Disabling RC6,
4481 * This what the BIOS expects when going into suspend */
59bad947 4482 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4483
44fc7d5c 4484 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4485
59bad947 4486 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4487}
4488
dc39fff7
BW		 4489static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4490{
91ca689a
ID		 4491 if (IS_VALLEYVIEW(dev)) {
4492 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4493 mode = GEN6_RC_CTL_RC6_ENABLE;
4494 else
4495 mode = 0;
4496 }
58abf1da
RV		 4497 if (HAS_RC6p(dev))
4498 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4499 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4500 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4501 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4502
4503 else
4504 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4505 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4506}
4507
e6069ca8 4508static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4509{
e7d66d89
DV		 4510 /* No RC6 before Ironlake and code is gone for ilk. */
4511 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4512 return 0;
4513
456470eb 4514 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4515 if (enable_rc6 >= 0) {
4516 int mask;
4517
58abf1da 4518 if (HAS_RC6p(dev))
e6069ca8
ID		 4519 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4520 INTEL_RC6pp_ENABLE;
4521 else
4522 mask = INTEL_RC6_ENABLE;
4523
4524 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4525 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4526 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4527
4528 return enable_rc6 & mask;
4529 }
2b4e57bd 4530
8bade1ad 4531 if (IS_IVYBRIDGE(dev))
cca84a1f 4532 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4533
4534 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4535}
4536
e6069ca8
ID		 4537int intel_enable_rc6(const struct drm_device *dev)
4538{
4539 return i915.enable_rc6;
4540}
4541
93ee2920 4542static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4543{
93ee2920
TR		 4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 uint32_t rp_state_cap;
4546 u32 ddcc_status = 0;
4547 int ret;
4548
3280e8b0
BW		 4549 /* All of these values are in units of 50MHz */
4550 dev_priv->rps.cur_freq = 0;
93ee2920 4551 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4552 if (IS_BROXTON(dev)) {
4553 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4554 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4555 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4556 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4557 } else {
4558 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4559 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4560 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4561 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4562 }
4563
3280e8b0
BW		 4564 /* hw_max = RP0 until we check for overclocking */
4565 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4566
93ee2920 4567 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4568 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4569 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4570 ret = sandybridge_pcode_read(dev_priv,
4571 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4572 &ddcc_status);
4573 if (0 == ret)
4574 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4575 clamp_t(u8,
4576 ((ddcc_status >> 8) & 0xff),
4577 dev_priv->rps.min_freq,
4578 dev_priv->rps.max_freq);
93ee2920
TR		 4579 }
4580
ef11bdb3 4581 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4582 /* Store the frequency values in 16.66 MHZ units, which is
4583 the natural hardware unit for SKL */
4584 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4585 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4586 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4587 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4588 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4589 }
4590
aed242ff
CW		 4591 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4592
3280e8b0
BW		 4593 /* Preserve min/max settings in case of re-init */
4594 if (dev_priv->rps.max_freq_softlimit == 0)
4595 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4596
93ee2920
TR		 4597 if (dev_priv->rps.min_freq_softlimit == 0) {
4598 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4599 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4600 max_t(int, dev_priv->rps.efficient_freq,
4601 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4602 else
4603 dev_priv->rps.min_freq_softlimit =
4604 dev_priv->rps.min_freq;
4605 }
3280e8b0
BW		 4606}
4607
b6fef0ef 4608/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4609static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4610{
4611 struct drm_i915_private *dev_priv = dev->dev_private;
4612
4613 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4614
ba1c554c
DL		 4615 gen6_init_rps_frequencies(dev);
4616
23eafea6 4617 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4618 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4619 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4620 return;
4621 }
4622
0beb059a
AG		 4623 /* Program defaults and thresholds for RPS*/
4624 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4625 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4626
4627 /* 1 second timeout*/
4628 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4629 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4630
b6fef0ef 4631 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4632
0beb059a
AG		 4633 /* Leaning on the below call to gen6_set_rps to program/setup the
4634 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4635 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4636 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4637 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4638
4639 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4640}
4641
4642static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4643{
4644 struct drm_i915_private *dev_priv = dev->dev_private;
4645 struct intel_engine_cs *ring;
4646 uint32_t rc6_mask = 0;
4647 int unused;
4648
4649 /* 1a: Software RC state - RC0 */
4650 I915_WRITE(GEN6_RC_STATE, 0);
4651
4652 /* 1b: Get forcewake during program sequence. Although the driver
4653 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4654 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4655
4656 /* 2a: Disable RC states. */
4657 I915_WRITE(GEN6_RC_CONTROL, 0);
4658
4659 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4660
4661 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4662 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
e87a005d 4663 IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
63a4dec2
SAK		 4664 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4665 else
4666 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4667 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4668 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4669 for_each_ring(ring, dev_priv, unused)
4670 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4671
4672 if (HAS_GUC_UCODE(dev))
4673 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4674
20e49366 4675 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4676
38c23527
ZW		 4677 /* 2c: Program Coarse Power Gating Policies. */
4678 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4679 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4680
20e49366
ZW		 4681 /* 3a: Enable RC6 */
4682 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4683 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4684 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4685 "on" : "off");
3e7732a0 4686 /* WaRsUseTimeoutMode */
e87a005d 4687 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4688 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4689 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4690 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4691 GEN7_RC_CTL_TO_MODE |
4692 rc6_mask);
3e7732a0
SAK		 4693 } else {
4694 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4695 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4696 GEN6_RC_CTL_EI_MODE(1) |
4697 rc6_mask);
3e7732a0 4698 }
20e49366 4699
cb07bae0
SK		 4700 /*
4701 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4702 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4703 */
e87a005d
JN		 4704 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
4705 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4706 IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
f2d2fe95
SAK		 4707 I915_WRITE(GEN9_PG_ENABLE, 0);
4708 else
4709 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4710 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4711
59bad947 4712 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4713
4714}
4715
6edee7f3
BW		 4716static void gen8_enable_rps(struct drm_device *dev)
4717{
4718 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4719 struct intel_engine_cs *ring;
93ee2920 4720 uint32_t rc6_mask = 0;
6edee7f3
BW		 4721 int unused;
4722
4723 /* 1a: Software RC state - RC0 */
4724 I915_WRITE(GEN6_RC_STATE, 0);
4725
4726 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4727 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4728 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4729
4730 /* 2a: Disable RC states. */
4731 I915_WRITE(GEN6_RC_CONTROL, 0);
4732
93ee2920
TR		 4733 /* Initialize rps frequencies */
4734 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4735
4736 /* 2b: Program RC6 thresholds.*/
4737 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4738 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4739 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4740 for_each_ring(ring, dev_priv, unused)
4741 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4742 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4743 if (IS_BROADWELL(dev))
4744 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4745 else
4746 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4747
4748 /* 3: Enable RC6 */
4749 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4750 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4751 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4752 if (IS_BROADWELL(dev))
4753 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4754 GEN7_RC_CTL_TO_MODE |
4755 rc6_mask);
4756 else
4757 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4758 GEN6_RC_CTL_EI_MODE(1) |
4759 rc6_mask);
6edee7f3
BW		 4760
4761 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4762 I915_WRITE(GEN6_RPNSWREQ,
4763 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4764 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4765 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4766 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4767 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4768
4769 /* Docs recommend 900MHz, and 300 MHz respectively */
4770 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4771 dev_priv->rps.max_freq_softlimit << 24 |
4772 dev_priv->rps.min_freq_softlimit << 16);
4773
4774 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4775 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4776 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4777 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4778
4779 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4780
4781 /* 5: Enable RPS */
7526ed79
DV		 4782 I915_WRITE(GEN6_RP_CONTROL,
4783 GEN6_RP_MEDIA_TURBO |
4784 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4785 GEN6_RP_MEDIA_IS_GFX |
4786 GEN6_RP_ENABLE |
4787 GEN6_RP_UP_BUSY_AVG |
4788 GEN6_RP_DOWN_IDLE_AVG);
4789
4790 /* 6: Ring frequency + overclocking (our driver does this later */
4791
c7f3153a 4792 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4793 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4794
59bad947 4795 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4796}
4797
79f5b2c7 4798static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4799{
79f5b2c7 4800 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4801 struct intel_engine_cs *ring;
d060c169 4802 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4803 u32 gtfifodbg;
2b4e57bd 4804 int rc6_mode;
42c0526c 4805 int i, ret;
2b4e57bd 4806
4fc688ce 4807 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4808
2b4e57bd
ED		 4809 /* Here begins a magic sequence of register writes to enable
4810 * auto-downclocking.
4811 *
4812 * Perhaps there might be some value in exposing these to
4813 * userspace...
4814 */
4815 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4816
4817 /* Clear the DBG now so we don't confuse earlier errors */
4818 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4819 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4820 I915_WRITE(GTFIFODBG, gtfifodbg);
4821 }
4822
59bad947 4823 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4824
93ee2920
TR		 4825 /* Initialize rps frequencies */
4826 gen6_init_rps_frequencies(dev);
dd0a1aa1 4827
2b4e57bd
ED		 4828 /* disable the counters and set deterministic thresholds */
4829 I915_WRITE(GEN6_RC_CONTROL, 0);
4830
4831 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4832 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4833 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4834 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4835 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4836
b4519513
CW		 4837 for_each_ring(ring, dev_priv, i)
4838 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4839
4840 I915_WRITE(GEN6_RC_SLEEP, 0);
4841 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4842 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4843 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4844 else
4845 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4846 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4847 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4848
5a7dc92a 4849 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4850 rc6_mode = intel_enable_rc6(dev_priv->dev);
4851 if (rc6_mode & INTEL_RC6_ENABLE)
4852 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4853
5a7dc92a
ED		 4854 /* We don't use those on Haswell */
4855 if (!IS_HASWELL(dev)) {
4856 if (rc6_mode & INTEL_RC6p_ENABLE)
4857 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4858
5a7dc92a
ED		 4859 if (rc6_mode & INTEL_RC6pp_ENABLE)
4860 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4861 }
2b4e57bd 4862
dc39fff7 4863 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4864
4865 I915_WRITE(GEN6_RC_CONTROL,
4866 rc6_mask |
4867 GEN6_RC_CTL_EI_MODE(1) |
4868 GEN6_RC_CTL_HW_ENABLE);
4869
dd75fdc8
CW		 4870 /* Power down if completely idle for over 50ms */
4871 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4872 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4873
42c0526c 4874 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4875 if (ret)
42c0526c 4876 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4877
4878 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4879 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4880 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4881 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4882 (pcu_mbox & 0xff) * 50);
b39fb297 4883 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4884 }
4885
dd75fdc8 4886 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4887 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4888
31643d54
BW		 4889 rc6vids = 0;
4890 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4891 if (IS_GEN6(dev) && ret) {
4892 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4893 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4894 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4895 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4896 rc6vids &= 0xffff00;
4897 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4898 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4899 if (ret)
4900 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4901 }
4902
59bad947 4903 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4904}
4905
c2bc2fc5 4906static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4907{
79f5b2c7 4908 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4909 int min_freq = 15;
3ebecd07
CW		 4910 unsigned int gpu_freq;
4911 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 4912 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 4913 int scaling_factor = 180;
eda79642 4914 struct cpufreq_policy *policy;
2b4e57bd 4915
4fc688ce 4916 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4917
eda79642
BW		 4918 policy = cpufreq_cpu_get(0);
4919 if (policy) {
4920 max_ia_freq = policy->cpuinfo.max_freq;
4921 cpufreq_cpu_put(policy);
4922 } else {
4923 /*
4924 * Default to measured freq if none found, PCU will ensure we
4925 * don't go over
4926 */
2b4e57bd 4927 max_ia_freq = tsc_khz;
eda79642 4928 }
2b4e57bd
ED		 4929
4930 /* Convert from kHz to MHz */
4931 max_ia_freq /= 1000;
4932
153b4b95 4933 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4934 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4935 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4936
ef11bdb3 4937 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4938 /* Convert GT frequency to 50 HZ units */
4939 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4940 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4941 } else {
4942 min_gpu_freq = dev_priv->rps.min_freq;
4943 max_gpu_freq = dev_priv->rps.max_freq;
4944 }
4945
2b4e57bd
ED		 4946 /*
4947 * For each potential GPU frequency, load a ring frequency we'd like
4948 * to use for memory access. We do this by specifying the IA frequency
4949 * the PCU should use as a reference to determine the ring frequency.
4950 */
4c8c7743
AG		 4951 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
4952 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 4953 unsigned int ia_freq = 0, ring_freq = 0;
4954
ef11bdb3 4955 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4956 /*
4957 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4958 * No floor required for ring frequency on SKL.
4959 */
4960 ring_freq = gpu_freq;
4961 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 4962 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4963 ring_freq = max(min_ring_freq, gpu_freq);
4964 } else if (IS_HASWELL(dev)) {
f6aca45c 4965 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4966 ring_freq = max(min_ring_freq, ring_freq);
4967 /* leave ia_freq as the default, chosen by cpufreq */
4968 } else {
4969 /* On older processors, there is no separate ring
4970 * clock domain, so in order to boost the bandwidth
4971 * of the ring, we need to upclock the CPU (ia_freq).
4972 *
4973 * For GPU frequencies less than 750MHz,
4974 * just use the lowest ring freq.
4975 */
4976 if (gpu_freq < min_freq)
4977 ia_freq = 800;
4978 else
4979 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4980 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4981 }
2b4e57bd 4982
42c0526c
BW		 4983 sandybridge_pcode_write(dev_priv,
4984 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4985 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4986 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4987 gpu_freq);
2b4e57bd 4988 }
2b4e57bd
ED		 4989}
4990
c2bc2fc5
ID		 4991void gen6_update_ring_freq(struct drm_device *dev)
4992{
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994
97d3308a 4995 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 4996 return;
4997
4998 mutex_lock(&dev_priv->rps.hw_lock);
4999 __gen6_update_ring_freq(dev);
5000 mutex_unlock(&dev_priv->rps.hw_lock);
5001}
5002
03af2045 5003static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5004{
095acd5f 5005 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5006 u32 val, rp0;
5007
5b5929cb 5008 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5009
5b5929cb
JN		 5010 switch (INTEL_INFO(dev)->eu_total) {
5011 case 8:
5012 /* (2 * 4) config */
5013 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5014 break;
5015 case 12:
5016 /* (2 * 6) config */
5017 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5018 break;
5019 case 16:
5020 /* (2 * 8) config */
5021 default:
5022 /* Setting (2 * 8) Min RP0 for any other combination */
5023 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5024 break;
095acd5f 5025 }
5b5929cb
JN		 5026
5027 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5028
2b6b3a09
D		 5029 return rp0;
5030}
5031
5032static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5033{
5034 u32 val, rpe;
5035
5036 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5037 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5038
5039 return rpe;
5040}
5041
7707df4a
D		 5042static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5043{
5044 u32 val, rp1;
5045
5b5929cb
JN		 5046 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5047 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5048
7707df4a
D		 5049 return rp1;
5050}
5051
f8f2b001
D		 5052static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5053{
5054 u32 val, rp1;
5055
5056 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5057
5058 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5059
5060 return rp1;
5061}
5062
03af2045 5063static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5064{
5065 u32 val, rp0;
5066
64936258 5067 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5068
5069 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5070 /* Clamp to max */
5071 rp0 = min_t(u32, rp0, 0xea);
5072
5073 return rp0;
5074}
5075
5076static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5077{
5078 u32 val, rpe;
5079
64936258 5080 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5081 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5082 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5083 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5084
5085 return rpe;
5086}
5087
03af2045 5088static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5089{
64936258 5090 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5091}
5092
ae48434c
ID		 5093/* Check that the pctx buffer wasn't move under us. */
5094static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5095{
5096 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5097
5098 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5099 dev_priv->vlv_pctx->stolen->start);
5100}
5101
38807746
D		 5102
5103/* Check that the pcbr address is not empty. */
5104static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5105{
5106 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5107
5108 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5109}
5110
5111static void cherryview_setup_pctx(struct drm_device *dev)
5112{
5113 struct drm_i915_private *dev_priv = dev->dev_private;
5114 unsigned long pctx_paddr, paddr;
5115 struct i915_gtt *gtt = &dev_priv->gtt;
5116 u32 pcbr;
5117 int pctx_size = 32*1024;
5118
5119 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5120
5121 pcbr = I915_READ(VLV_PCBR);
5122 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5123 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5124 paddr = (dev_priv->mm.stolen_base +
5125 (gtt->stolen_size - pctx_size));
5126
5127 pctx_paddr = (paddr & (~4095));
5128 I915_WRITE(VLV_PCBR, pctx_paddr);
5129 }
ce611ef8
VS		 5130
5131 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5132}
5133
c9cddffc
JB		 5134static void valleyview_setup_pctx(struct drm_device *dev)
5135{
5136 struct drm_i915_private *dev_priv = dev->dev_private;
5137 struct drm_i915_gem_object *pctx;
5138 unsigned long pctx_paddr;
5139 u32 pcbr;
5140 int pctx_size = 24*1024;
5141
17b0c1f7
ID		 5142 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5143
c9cddffc
JB		 5144 pcbr = I915_READ(VLV_PCBR);
5145 if (pcbr) {
5146 /* BIOS set it up already, grab the pre-alloc'd space */
5147 int pcbr_offset;
5148
5149 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5150 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5151 pcbr_offset,
190d6cd5 5152 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5153 pctx_size);
5154 goto out;
5155 }
5156
ce611ef8
VS		 5157 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5158
c9cddffc
JB		 5159 /*
5160 * From the Gunit register HAS:
5161 * The Gfx driver is expected to program this register and ensure
5162 * proper allocation within Gfx stolen memory. For example, this
5163 * register should be programmed such than the PCBR range does not
5164 * overlap with other ranges, such as the frame buffer, protected
5165 * memory, or any other relevant ranges.
5166 */
5167 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5168 if (!pctx) {
5169 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5170 return;
5171 }
5172
5173 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5174 I915_WRITE(VLV_PCBR, pctx_paddr);
5175
5176out:
ce611ef8 5177 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5178 dev_priv->vlv_pctx = pctx;
5179}
5180
ae48434c
ID		 5181static void valleyview_cleanup_pctx(struct drm_device *dev)
5182{
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184
5185 if (WARN_ON(!dev_priv->vlv_pctx))
5186 return;
5187
5188 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5189 dev_priv->vlv_pctx = NULL;
5190}
5191
4e80519e
ID		 5192static void valleyview_init_gt_powersave(struct drm_device *dev)
5193{
5194 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5195 u32 val;
4e80519e
ID		 5196
5197 valleyview_setup_pctx(dev);
5198
5199 mutex_lock(&dev_priv->rps.hw_lock);
5200
2bb25c17
VS		 5201 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5202 switch ((val >> 6) & 3) {
5203 case 0:
5204 case 1:
5205 dev_priv->mem_freq = 800;
5206 break;
5207 case 2:
5208 dev_priv->mem_freq = 1066;
5209 break;
5210 case 3:
5211 dev_priv->mem_freq = 1333;
5212 break;
5213 }
80b83b62 5214 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5215
4e80519e
ID		 5216 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5217 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5218 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5219 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5220 dev_priv->rps.max_freq);
5221
5222 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5223 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5224 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5225 dev_priv->rps.efficient_freq);
5226
f8f2b001
D		 5227 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5228 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5229 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5230 dev_priv->rps.rp1_freq);
5231
4e80519e
ID		 5232 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5233 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5234 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5235 dev_priv->rps.min_freq);
5236
aed242ff
CW		 5237 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5238
4e80519e
ID		 5239 /* Preserve min/max settings in case of re-init */
5240 if (dev_priv->rps.max_freq_softlimit == 0)
5241 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5242
5243 if (dev_priv->rps.min_freq_softlimit == 0)
5244 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5245
5246 mutex_unlock(&dev_priv->rps.hw_lock);
5247}
5248
38807746
D		 5249static void cherryview_init_gt_powersave(struct drm_device *dev)
5250{
2b6b3a09 5251 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5252 u32 val;
2b6b3a09 5253
38807746 5254 cherryview_setup_pctx(dev);
2b6b3a09
D		 5255
5256 mutex_lock(&dev_priv->rps.hw_lock);
5257
a580516d 5258 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5259 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5260 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5261
2bb25c17 5262 switch ((val >> 2) & 0x7) {
2bb25c17 5263 case 3:
2bb25c17
VS		 5264 dev_priv->mem_freq = 2000;
5265 break;
bfa7df01 5266 default:
2bb25c17
VS		 5267 dev_priv->mem_freq = 1600;
5268 break;
5269 }
80b83b62 5270 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5271
2b6b3a09
D		 5272 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5273 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5274 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5275 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5276 dev_priv->rps.max_freq);
5277
5278 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5279 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5280 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5281 dev_priv->rps.efficient_freq);
5282
7707df4a
D		 5283 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5284 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5285 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5286 dev_priv->rps.rp1_freq);
5287
5b7c91b7
D		 5288 /* PUnit validated range is only [RPe, RP0] */
5289 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5290 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5291 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5292 dev_priv->rps.min_freq);
5293
1c14762d
VS		 5294 WARN_ONCE((dev_priv->rps.max_freq |
5295 dev_priv->rps.efficient_freq |
5296 dev_priv->rps.rp1_freq |
5297 dev_priv->rps.min_freq) & 1,
5298 "Odd GPU freq values\n");
5299
aed242ff
CW		 5300 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5301
2b6b3a09
D		 5302 /* Preserve min/max settings in case of re-init */
5303 if (dev_priv->rps.max_freq_softlimit == 0)
5304 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5305
5306 if (dev_priv->rps.min_freq_softlimit == 0)
5307 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5308
5309 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5310}
5311
4e80519e
ID		 5312static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5313{
5314 valleyview_cleanup_pctx(dev);
5315}
5316
38807746
D		 5317static void cherryview_enable_rps(struct drm_device *dev)
5318{
5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320 struct intel_engine_cs *ring;
2b6b3a09 5321 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5322 int i;
5323
5324 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5325
5326 gtfifodbg = I915_READ(GTFIFODBG);
5327 if (gtfifodbg) {
5328 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5329 gtfifodbg);
5330 I915_WRITE(GTFIFODBG, gtfifodbg);
5331 }
5332
5333 cherryview_check_pctx(dev_priv);
5334
5335 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5336 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5337 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5338
160614a2
VS		 5339 /* Disable RC states. */
5340 I915_WRITE(GEN6_RC_CONTROL, 0);
5341
38807746
D		 5342 /* 2a: Program RC6 thresholds.*/
5343 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5344 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5345 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5346
5347 for_each_ring(ring, dev_priv, i)
5348 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5349 I915_WRITE(GEN6_RC_SLEEP, 0);
5350
f4f71c7d
D		 5351 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5352 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5353
5354 /* allows RC6 residency counter to work */
5355 I915_WRITE(VLV_COUNTER_CONTROL,
5356 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5357 VLV_MEDIA_RC6_COUNT_EN |
5358 VLV_RENDER_RC6_COUNT_EN));
5359
5360 /* For now we assume BIOS is allocating and populating the PCBR */
5361 pcbr = I915_READ(VLV_PCBR);
5362
38807746
D		 5363 /* 3: Enable RC6 */
5364 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5365 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5366 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5367
5368 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5369
2b6b3a09 5370 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5371 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5372 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5373 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5374 I915_WRITE(GEN6_RP_UP_EI, 66000);
5375 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5376
5377 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5378
5379 /* 5: Enable RPS */
5380 I915_WRITE(GEN6_RP_CONTROL,
5381 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5382 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5383 GEN6_RP_ENABLE |
5384 GEN6_RP_UP_BUSY_AVG |
5385 GEN6_RP_DOWN_IDLE_AVG);
5386
3ef62342
D		 5387 /* Setting Fixed Bias */
5388 val = VLV_OVERRIDE_EN |
5389 VLV_SOC_TDP_EN |
5390 CHV_BIAS_CPU_50_SOC_50;
5391 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5392
2b6b3a09
D		 5393 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5394
8d40c3ae
VS		 5395 /* RPS code assumes GPLL is used */
5396 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5397
742f491d 5398 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5399 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5400
5401 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5402 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5403 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5404 dev_priv->rps.cur_freq);
5405
5406 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5407 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5408 dev_priv->rps.efficient_freq);
5409
5410 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5411
59bad947 5412 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5413}
5414
0a073b84
JB		 5415static void valleyview_enable_rps(struct drm_device *dev)
5416{
5417 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5418 struct intel_engine_cs *ring;
2a5913a8 5419 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5420 int i;
5421
5422 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5423
ae48434c
ID		 5424 valleyview_check_pctx(dev_priv);
5425
0a073b84 5426 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5427 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5428 gtfifodbg);
0a073b84
JB		 5429 I915_WRITE(GTFIFODBG, gtfifodbg);
5430 }
5431
c8d9a590 5432 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5433 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5434
160614a2
VS		 5435 /* Disable RC states. */
5436 I915_WRITE(GEN6_RC_CONTROL, 0);
5437
cad725fe 5438 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5439 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5440 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5441 I915_WRITE(GEN6_RP_UP_EI, 66000);
5442 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5443
5444 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5445
5446 I915_WRITE(GEN6_RP_CONTROL,
5447 GEN6_RP_MEDIA_TURBO |
5448 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5449 GEN6_RP_MEDIA_IS_GFX |
5450 GEN6_RP_ENABLE |
5451 GEN6_RP_UP_BUSY_AVG |
5452 GEN6_RP_DOWN_IDLE_CONT);
5453
5454 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5455 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5456 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5457
5458 for_each_ring(ring, dev_priv, i)
5459 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5460
2f0aa304 5461 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5462
5463 /* allows RC6 residency counter to work */
49798eb2 5464 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5465 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5466 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5467 VLV_MEDIA_RC6_COUNT_EN |
5468 VLV_RENDER_RC6_COUNT_EN));
31685c25 5469
a2b23fe0 5470 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5471 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5472
5473 intel_print_rc6_info(dev, rc6_mode);
5474
a2b23fe0 5475 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5476
3ef62342
D		 5477 /* Setting Fixed Bias */
5478 val = VLV_OVERRIDE_EN |
5479 VLV_SOC_TDP_EN |
5480 VLV_BIAS_CPU_125_SOC_875;
5481 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5482
64936258 5483 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5484
8d40c3ae
VS		 5485 /* RPS code assumes GPLL is used */
5486 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5487
742f491d 5488 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5489 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5490
b39fb297 5491 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5492 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5493 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5494 dev_priv->rps.cur_freq);
0a073b84 5495
73008b98 5496 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5497 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5498 dev_priv->rps.efficient_freq);
0a073b84 5499
b39fb297 5500 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5501
59bad947 5502 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5503}
5504
dde18883
ED		 5505static unsigned long intel_pxfreq(u32 vidfreq)
5506{
5507 unsigned long freq;
5508 int div = (vidfreq & 0x3f0000) >> 16;
5509 int post = (vidfreq & 0x3000) >> 12;
5510 int pre = (vidfreq & 0x7);
5511
5512 if (!pre)
5513 return 0;
5514
5515 freq = ((div * 133333) / ((1<<post) * pre));
5516
5517 return freq;
5518}
5519
eb48eb00
DV		 5520static const struct cparams {
5521 u16 i;
5522 u16 t;
5523 u16 m;
5524 u16 c;
5525} cparams[] = {
5526 { 1, 1333, 301, 28664 },
5527 { 1, 1066, 294, 24460 },
5528 { 1, 800, 294, 25192 },
5529 { 0, 1333, 276, 27605 },
5530 { 0, 1066, 276, 27605 },
5531 { 0, 800, 231, 23784 },
5532};
5533
f531dcb2 5534static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5535{
5536 u64 total_count, diff, ret;
5537 u32 count1, count2, count3, m = 0, c = 0;
5538 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5539 int i;
5540
02d71956
DV		 5541 assert_spin_locked(&mchdev_lock);
5542
20e4d407 5543 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5544
5545 /* Prevent division-by-zero if we are asking too fast.
5546 * Also, we don't get interesting results if we are polling
5547 * faster than once in 10ms, so just return the saved value
5548 * in such cases.
5549 */
5550 if (diff1 <= 10)
20e4d407 5551 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5552
5553 count1 = I915_READ(DMIEC);
5554 count2 = I915_READ(DDREC);
5555 count3 = I915_READ(CSIEC);
5556
5557 total_count = count1 + count2 + count3;
5558
5559 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5560 if (total_count < dev_priv->ips.last_count1) {
5561 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5562 diff += total_count;
5563 } else {
20e4d407 5564 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5565 }
5566
5567 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5568 if (cparams[i].i == dev_priv->ips.c_m &&
5569 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5570 m = cparams[i].m;
5571 c = cparams[i].c;
5572 break;
5573 }
5574 }
5575
5576 diff = div_u64(diff, diff1);
5577 ret = ((m * diff) + c);
5578 ret = div_u64(ret, 10);
5579
20e4d407
DV		 5580 dev_priv->ips.last_count1 = total_count;
5581 dev_priv->ips.last_time1 = now;
eb48eb00 5582
20e4d407 5583 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5584
5585 return ret;
5586}
5587
f531dcb2
CW		 5588unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5589{
3d13ef2e 5590 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5591 unsigned long val;
5592
3d13ef2e 5593 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5594 return 0;
5595
5596 spin_lock_irq(&mchdev_lock);
5597
5598 val = __i915_chipset_val(dev_priv);
5599
5600 spin_unlock_irq(&mchdev_lock);
5601
5602 return val;
5603}
5604
eb48eb00
DV		 5605unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5606{
5607 unsigned long m, x, b;
5608 u32 tsfs;
5609
5610 tsfs = I915_READ(TSFS);
5611
5612 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5613 x = I915_READ8(TR1);
5614
5615 b = tsfs & TSFS_INTR_MASK;
5616
5617 return ((m * x) / 127) - b;
5618}
5619
d972d6ee
MK		 5620static int _pxvid_to_vd(u8 pxvid)
5621{
5622 if (pxvid == 0)
5623 return 0;
5624
5625 if (pxvid >= 8 && pxvid < 31)
5626 pxvid = 31;
5627
5628 return (pxvid + 2) * 125;
5629}
5630
5631static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5632{
3d13ef2e 5633 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5634 const int vd = _pxvid_to_vd(pxvid);
5635 const int vm = vd - 1125;
5636
3d13ef2e 5637 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5638 return vm > 0 ? vm : 0;
5639
5640 return vd;
eb48eb00
DV		 5641}
5642
02d71956 5643static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5644{
5ed0bdf2 5645 u64 now, diff, diffms;
eb48eb00
DV		 5646 u32 count;
5647
02d71956 5648 assert_spin_locked(&mchdev_lock);
eb48eb00 5649
5ed0bdf2
TG		 5650 now = ktime_get_raw_ns();
5651 diffms = now - dev_priv->ips.last_time2;
5652 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5653
5654 /* Don't divide by 0 */
eb48eb00
DV		 5655 if (!diffms)
5656 return;
5657
5658 count = I915_READ(GFXEC);
5659
20e4d407
DV		 5660 if (count < dev_priv->ips.last_count2) {
5661 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5662 diff += count;
5663 } else {
20e4d407 5664 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5665 }
5666
20e4d407
DV		 5667 dev_priv->ips.last_count2 = count;
5668 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5669
5670 /* More magic constants... */
5671 diff = diff * 1181;
5672 diff = div_u64(diff, diffms * 10);
20e4d407 5673 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5674}
5675
02d71956
DV		 5676void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5677{
3d13ef2e
DL		 5678 struct drm_device *dev = dev_priv->dev;
5679
5680 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5681 return;
5682
9270388e 5683 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5684
5685 __i915_update_gfx_val(dev_priv);
5686
9270388e 5687 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5688}
5689
f531dcb2 5690static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5691{
5692 unsigned long t, corr, state1, corr2, state2;
5693 u32 pxvid, ext_v;
5694
02d71956
DV		 5695 assert_spin_locked(&mchdev_lock);
5696
616847e7 5697 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5698 pxvid = (pxvid >> 24) & 0x7f;
5699 ext_v = pvid_to_extvid(dev_priv, pxvid);
5700
5701 state1 = ext_v;
5702
5703 t = i915_mch_val(dev_priv);
5704
5705 /* Revel in the empirically derived constants */
5706
5707 /* Correction factor in 1/100000 units */
5708 if (t > 80)
5709 corr = ((t * 2349) + 135940);
5710 else if (t >= 50)
5711 corr = ((t * 964) + 29317);
5712 else /* < 50 */
5713 corr = ((t * 301) + 1004);
5714
5715 corr = corr * ((150142 * state1) / 10000 - 78642);
5716 corr /= 100000;
20e4d407 5717 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5718
5719 state2 = (corr2 * state1) / 10000;
5720 state2 /= 100; /* convert to mW */
5721
02d71956 5722 __i915_update_gfx_val(dev_priv);
eb48eb00 5723
20e4d407 5724 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5725}
5726
f531dcb2
CW		 5727unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5728{
3d13ef2e 5729 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5730 unsigned long val;
5731
3d13ef2e 5732 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5733 return 0;
5734
5735 spin_lock_irq(&mchdev_lock);
5736
5737 val = __i915_gfx_val(dev_priv);
5738
5739 spin_unlock_irq(&mchdev_lock);
5740
5741 return val;
5742}
5743
eb48eb00
DV		 5744/**
5745 * i915_read_mch_val - return value for IPS use
5746 *
5747 * Calculate and return a value for the IPS driver to use when deciding whether
5748 * we have thermal and power headroom to increase CPU or GPU power budget.
5749 */
5750unsigned long i915_read_mch_val(void)
5751{
5752 struct drm_i915_private *dev_priv;
5753 unsigned long chipset_val, graphics_val, ret = 0;
5754
9270388e 5755 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5756 if (!i915_mch_dev)
5757 goto out_unlock;
5758 dev_priv = i915_mch_dev;
5759
f531dcb2
CW		 5760 chipset_val = __i915_chipset_val(dev_priv);
5761 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5762
5763 ret = chipset_val + graphics_val;
5764
5765out_unlock:
9270388e 5766 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5767
5768 return ret;
5769}
5770EXPORT_SYMBOL_GPL(i915_read_mch_val);
5771
5772/**
5773 * i915_gpu_raise - raise GPU frequency limit
5774 *
5775 * Raise the limit; IPS indicates we have thermal headroom.
5776 */
5777bool i915_gpu_raise(void)
5778{
5779 struct drm_i915_private *dev_priv;
5780 bool ret = true;
5781
9270388e 5782 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5783 if (!i915_mch_dev) {
5784 ret = false;
5785 goto out_unlock;
5786 }
5787 dev_priv = i915_mch_dev;
5788
20e4d407
DV		 5789 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5790 dev_priv->ips.max_delay--;
eb48eb00
DV		 5791
5792out_unlock:
9270388e 5793 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5794
5795 return ret;
5796}
5797EXPORT_SYMBOL_GPL(i915_gpu_raise);
5798
5799/**
5800 * i915_gpu_lower - lower GPU frequency limit
5801 *
5802 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5803 * frequency maximum.
5804 */
5805bool i915_gpu_lower(void)
5806{
5807 struct drm_i915_private *dev_priv;
5808 bool ret = true;
5809
9270388e 5810 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5811 if (!i915_mch_dev) {
5812 ret = false;
5813 goto out_unlock;
5814 }
5815 dev_priv = i915_mch_dev;
5816
20e4d407
DV		 5817 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5818 dev_priv->ips.max_delay++;
eb48eb00
DV		 5819
5820out_unlock:
9270388e 5821 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5822
5823 return ret;
5824}
5825EXPORT_SYMBOL_GPL(i915_gpu_lower);
5826
5827/**
5828 * i915_gpu_busy - indicate GPU business to IPS
5829 *
5830 * Tell the IPS driver whether or not the GPU is busy.
5831 */
5832bool i915_gpu_busy(void)
5833{
5834 struct drm_i915_private *dev_priv;
a4872ba6 5835 struct intel_engine_cs *ring;
eb48eb00 5836 bool ret = false;
f047e395 5837 int i;
eb48eb00 5838
9270388e 5839 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5840 if (!i915_mch_dev)
5841 goto out_unlock;
5842 dev_priv = i915_mch_dev;
5843
f047e395
CW		 5844 for_each_ring(ring, dev_priv, i)
5845 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5846
5847out_unlock:
9270388e 5848 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5849
5850 return ret;
5851}
5852EXPORT_SYMBOL_GPL(i915_gpu_busy);
5853
5854/**
5855 * i915_gpu_turbo_disable - disable graphics turbo
5856 *
5857 * Disable graphics turbo by resetting the max frequency and setting the
5858 * current frequency to the default.
5859 */
5860bool i915_gpu_turbo_disable(void)
5861{
5862 struct drm_i915_private *dev_priv;
5863 bool ret = true;
5864
9270388e 5865 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5866 if (!i915_mch_dev) {
5867 ret = false;
5868 goto out_unlock;
5869 }
5870 dev_priv = i915_mch_dev;
5871
20e4d407 5872 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5873
20e4d407 5874 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5875 ret = false;
5876
5877out_unlock:
9270388e 5878 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5879
5880 return ret;
5881}
5882EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5883
5884/**
5885 * Tells the intel_ips driver that the i915 driver is now loaded, if
5886 * IPS got loaded first.
5887 *
5888 * This awkward dance is so that neither module has to depend on the
5889 * other in order for IPS to do the appropriate communication of
5890 * GPU turbo limits to i915.
5891 */
5892static void
5893ips_ping_for_i915_load(void)
5894{
5895 void (*link)(void);
5896
5897 link = symbol_get(ips_link_to_i915_driver);
5898 if (link) {
5899 link();
5900 symbol_put(ips_link_to_i915_driver);
5901 }
5902}
5903
5904void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5905{
02d71956
DV		 5906 /* We only register the i915 ips part with intel-ips once everything is
5907 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5908 spin_lock_irq(&mchdev_lock);
eb48eb00 5909 i915_mch_dev = dev_priv;
9270388e 5910 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5911
5912 ips_ping_for_i915_load();
5913}
5914
5915void intel_gpu_ips_teardown(void)
5916{
9270388e 5917 spin_lock_irq(&mchdev_lock);
eb48eb00 5918 i915_mch_dev = NULL;
9270388e 5919 spin_unlock_irq(&mchdev_lock);
eb48eb00 5920}
76c3552f 5921
8090c6b9 5922static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5923{
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 u32 lcfuse;
5926 u8 pxw[16];
5927 int i;
5928
5929 /* Disable to program */
5930 I915_WRITE(ECR, 0);
5931 POSTING_READ(ECR);
5932
5933 /* Program energy weights for various events */
5934 I915_WRITE(SDEW, 0x15040d00);
5935 I915_WRITE(CSIEW0, 0x007f0000);
5936 I915_WRITE(CSIEW1, 0x1e220004);
5937 I915_WRITE(CSIEW2, 0x04000004);
5938
5939 for (i = 0; i < 5; i++)
616847e7 5940 I915_WRITE(PEW(i), 0);
dde18883 5941 for (i = 0; i < 3; i++)
616847e7 5942 I915_WRITE(DEW(i), 0);
dde18883
ED		 5943
5944 /* Program P-state weights to account for frequency power adjustment */
5945 for (i = 0; i < 16; i++) {
616847e7 5946 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 5947 unsigned long freq = intel_pxfreq(pxvidfreq);
5948 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5949 PXVFREQ_PX_SHIFT;
5950 unsigned long val;
5951
5952 val = vid * vid;
5953 val *= (freq / 1000);
5954 val *= 255;
5955 val /= (127*127*900);
5956 if (val > 0xff)
5957 DRM_ERROR("bad pxval: %ld\n", val);
5958 pxw[i] = val;
5959 }
5960 /* Render standby states get 0 weight */
5961 pxw[14] = 0;
5962 pxw[15] = 0;
5963
5964 for (i = 0; i < 4; i++) {
5965 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5966 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 5967 I915_WRITE(PXW(i), val);
dde18883
ED		 5968 }
5969
5970 /* Adjust magic regs to magic values (more experimental results) */
5971 I915_WRITE(OGW0, 0);
5972 I915_WRITE(OGW1, 0);
5973 I915_WRITE(EG0, 0x00007f00);
5974 I915_WRITE(EG1, 0x0000000e);
5975 I915_WRITE(EG2, 0x000e0000);
5976 I915_WRITE(EG3, 0x68000300);
5977 I915_WRITE(EG4, 0x42000000);
5978 I915_WRITE(EG5, 0x00140031);
5979 I915_WRITE(EG6, 0);
5980 I915_WRITE(EG7, 0);
5981
5982 for (i = 0; i < 8; i++)
616847e7 5983 I915_WRITE(PXWL(i), 0);
dde18883
ED		 5984
5985 /* Enable PMON + select events */
5986 I915_WRITE(ECR, 0x80000019);
5987
5988 lcfuse = I915_READ(LCFUSE02);
5989
20e4d407 5990 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5991}
5992
ae48434c
ID		 5993void intel_init_gt_powersave(struct drm_device *dev)
5994{
e6069ca8
ID		 5995 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5996
38807746
D		 5997 if (IS_CHERRYVIEW(dev))
5998 cherryview_init_gt_powersave(dev);
5999 else if (IS_VALLEYVIEW(dev))
4e80519e 6000 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6001}
6002
6003void intel_cleanup_gt_powersave(struct drm_device *dev)
6004{
38807746
D		 6005 if (IS_CHERRYVIEW(dev))
6006 return;
6007 else if (IS_VALLEYVIEW(dev))
4e80519e 6008 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6009}
6010
dbea3cea
ID		 6011static void gen6_suspend_rps(struct drm_device *dev)
6012{
6013 struct drm_i915_private *dev_priv = dev->dev_private;
6014
6015 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6016
4c2a8897 6017 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6018}
6019
156c7ca0
JB		 6020/**
6021 * intel_suspend_gt_powersave - suspend PM work and helper threads
6022 * @dev: drm device
6023 *
6024 * We don't want to disable RC6 or other features here, we just want
6025 * to make sure any work we've queued has finished and won't bother
6026 * us while we're suspended.
6027 */
6028void intel_suspend_gt_powersave(struct drm_device *dev)
6029{
6030 struct drm_i915_private *dev_priv = dev->dev_private;
6031
d4d70aa5
ID		 6032 if (INTEL_INFO(dev)->gen < 6)
6033 return;
6034
dbea3cea 6035 gen6_suspend_rps(dev);
b47adc17
D		 6036
6037 /* Force GPU to min freq during suspend */
6038 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6039}
6040
8090c6b9
DV		 6041void intel_disable_gt_powersave(struct drm_device *dev)
6042{
1a01ab3b
JB		 6043 struct drm_i915_private *dev_priv = dev->dev_private;
6044
930ebb46 6045 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6046 ironlake_disable_drps(dev);
38807746 6047 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6048 intel_suspend_gt_powersave(dev);
e494837a 6049
4fc688ce 6050 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6051 if (INTEL_INFO(dev)->gen >= 9)
6052 gen9_disable_rps(dev);
6053 else if (IS_CHERRYVIEW(dev))
38807746
D		 6054 cherryview_disable_rps(dev);
6055 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6056 valleyview_disable_rps(dev);
6057 else
6058 gen6_disable_rps(dev);
e534770a 6059
c0951f0c 6060 dev_priv->rps.enabled = false;
4fc688ce 6061 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6062 }
8090c6b9
DV		 6063}
6064
1a01ab3b
JB		 6065static void intel_gen6_powersave_work(struct work_struct *work)
6066{
6067 struct drm_i915_private *dev_priv =
6068 container_of(work, struct drm_i915_private,
6069 rps.delayed_resume_work.work);
6070 struct drm_device *dev = dev_priv->dev;
6071
4fc688ce 6072 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6073
4c2a8897 6074 gen6_reset_rps_interrupts(dev);
3cc134e3 6075
38807746
D		 6076 if (IS_CHERRYVIEW(dev)) {
6077 cherryview_enable_rps(dev);
6078 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6079 valleyview_enable_rps(dev);
20e49366 6080 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6081 gen9_enable_rc6(dev);
20e49366 6082 gen9_enable_rps(dev);
ef11bdb3 6083 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6084 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6085 } else if (IS_BROADWELL(dev)) {
6086 gen8_enable_rps(dev);
c2bc2fc5 6087 __gen6_update_ring_freq(dev);
0a073b84
JB		 6088 } else {
6089 gen6_enable_rps(dev);
c2bc2fc5 6090 __gen6_update_ring_freq(dev);
0a073b84 6091 }
aed242ff
CW		 6092
6093 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6094 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6095
6096 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6097 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6098
c0951f0c 6099 dev_priv->rps.enabled = true;
3cc134e3 6100
4c2a8897 6101 gen6_enable_rps_interrupts(dev);
3cc134e3 6102
4fc688ce 6103 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6104
6105 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6106}
6107
8090c6b9
DV		 6108void intel_enable_gt_powersave(struct drm_device *dev)
6109{
1a01ab3b
JB		 6110 struct drm_i915_private *dev_priv = dev->dev_private;
6111
f61018b1
YZ		 6112 /* Powersaving is controlled by the host when inside a VM */
6113 if (intel_vgpu_active(dev))
6114 return;
6115
8090c6b9 6116 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6117 mutex_lock(&dev->struct_mutex);
8090c6b9 6118 ironlake_enable_drps(dev);
8090c6b9 6119 intel_init_emon(dev);
dc1d0136 6120 mutex_unlock(&dev->struct_mutex);
38807746 6121 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6122 /*
6123 * PCU communication is slow and this doesn't need to be
6124 * done at any specific time, so do this out of our fast path
6125 * to make resume and init faster.
c6df39b5
ID		 6126 *
6127 * We depend on the HW RC6 power context save/restore
6128 * mechanism when entering D3 through runtime PM suspend. So
6129 * disable RPM until RPS/RC6 is properly setup. We can only
6130 * get here via the driver load/system resume/runtime resume
6131 * paths, so the _noresume version is enough (and in case of
6132 * runtime resume it's necessary).
1a01ab3b 6133 */
c6df39b5
ID		 6134 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6135 round_jiffies_up_relative(HZ)))
6136 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6137 }
6138}
6139
c6df39b5
ID		 6140void intel_reset_gt_powersave(struct drm_device *dev)
6141{
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143
dbea3cea
ID		 6144 if (INTEL_INFO(dev)->gen < 6)
6145 return;
6146
6147 gen6_suspend_rps(dev);
c6df39b5 6148 dev_priv->rps.enabled = false;
c6df39b5
ID		 6149}
6150
3107bd48
DV		 6151static void ibx_init_clock_gating(struct drm_device *dev)
6152{
6153 struct drm_i915_private *dev_priv = dev->dev_private;
6154
6155 /*
6156 * On Ibex Peak and Cougar Point, we need to disable clock
6157 * gating for the panel power sequencer or it will fail to
6158 * start up when no ports are active.
6159 */
6160 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6161}
6162
0e088b8f
VS		 6163static void g4x_disable_trickle_feed(struct drm_device *dev)
6164{
6165 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6166 enum pipe pipe;
0e088b8f 6167
055e393f 6168 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6169 I915_WRITE(DSPCNTR(pipe),
6170 I915_READ(DSPCNTR(pipe)) |
6171 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6172
6173 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6174 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6175 }
6176}
6177
017636cc
VS		 6178static void ilk_init_lp_watermarks(struct drm_device *dev)
6179{
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181
6182 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6183 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6184 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6185
6186 /*
6187 * Don't touch WM1S_LP_EN here.
6188 * Doing so could cause underruns.
6189 */
6190}
6191
1fa61106 6192static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6193{
6194 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6195 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6196
f1e8fa56
DL		 6197 /*
6198 * Required for FBC
6199 * WaFbcDisableDpfcClockGating:ilk
6200 */
4d47e4f5
DL		 6201 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6202 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6203 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6204
6205 I915_WRITE(PCH_3DCGDIS0,
6206 MARIUNIT_CLOCK_GATE_DISABLE |
6207 SVSMUNIT_CLOCK_GATE_DISABLE);
6208 I915_WRITE(PCH_3DCGDIS1,
6209 VFMUNIT_CLOCK_GATE_DISABLE);
6210
6f1d69b0
ED		 6211 /*
6212 * According to the spec the following bits should be set in
6213 * order to enable memory self-refresh
6214 * The bit 22/21 of 0x42004
6215 * The bit 5 of 0x42020
6216 * The bit 15 of 0x45000
6217 */
6218 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6219 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6220 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6221 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6222 I915_WRITE(DISP_ARB_CTL,
6223 (I915_READ(DISP_ARB_CTL) |
6224 DISP_FBC_WM_DIS));
017636cc
VS		 6225
6226 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6227
6228 /*
6229 * Based on the document from hardware guys the following bits
6230 * should be set unconditionally in order to enable FBC.
6231 * The bit 22 of 0x42000
6232 * The bit 22 of 0x42004
6233 * The bit 7,8,9 of 0x42020.
6234 */
6235 if (IS_IRONLAKE_M(dev)) {
4bb35334 6236 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6237 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6238 I915_READ(ILK_DISPLAY_CHICKEN1) |
6239 ILK_FBCQ_DIS);
6240 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6241 I915_READ(ILK_DISPLAY_CHICKEN2) |
6242 ILK_DPARB_GATE);
6f1d69b0
ED		 6243 }
6244
4d47e4f5
DL		 6245 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6246
6f1d69b0
ED		 6247 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6248 I915_READ(ILK_DISPLAY_CHICKEN2) |
6249 ILK_ELPIN_409_SELECT);
6250 I915_WRITE(_3D_CHICKEN2,
6251 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6252 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6253
ecdb4eb7 6254 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6255 I915_WRITE(CACHE_MODE_0,
6256 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6257
4e04632e
AG		 6258 /* WaDisable_RenderCache_OperationalFlush:ilk */
6259 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6260
0e088b8f 6261 g4x_disable_trickle_feed(dev);
bdad2b2f 6262
3107bd48
DV		 6263 ibx_init_clock_gating(dev);
6264}
6265
6266static void cpt_init_clock_gating(struct drm_device *dev)
6267{
6268 struct drm_i915_private *dev_priv = dev->dev_private;
6269 int pipe;
3f704fa2 6270 uint32_t val;
3107bd48
DV		 6271
6272 /*
6273 * On Ibex Peak and Cougar Point, we need to disable clock
6274 * gating for the panel power sequencer or it will fail to
6275 * start up when no ports are active.
6276 */
cd664078
JB		 6277 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6278 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6279 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6280 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6281 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6282 /* The below fixes the weird display corruption, a few pixels shifted
6283 * downward, on (only) LVDS of some HP laptops with IVY.
6284 */
055e393f 6285 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6286 val = I915_READ(TRANS_CHICKEN2(pipe));
6287 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6288 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6289 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6290 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6291 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6292 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6293 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6294 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6295 }
3107bd48 6296 /* WADP0ClockGatingDisable */
055e393f 6297 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6298 I915_WRITE(TRANS_CHICKEN1(pipe),
6299 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6300 }
6f1d69b0
ED		 6301}
6302
1d7aaa0c
DV		 6303static void gen6_check_mch_setup(struct drm_device *dev)
6304{
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 uint32_t tmp;
6307
6308 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6309 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6310 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6311 tmp);
1d7aaa0c
DV		 6312}
6313
1fa61106 6314static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6315{
6316 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6317 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6318
231e54f6 6319 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6320
6321 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6322 I915_READ(ILK_DISPLAY_CHICKEN2) |
6323 ILK_ELPIN_409_SELECT);
6324
ecdb4eb7 6325 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6326 I915_WRITE(_3D_CHICKEN,
6327 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6328
4e04632e
AG		 6329 /* WaDisable_RenderCache_OperationalFlush:snb */
6330 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6331
8d85d272
VS		 6332 /*
6333 * BSpec recoomends 8x4 when MSAA is used,
6334 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6335 *
6336 * Note that PS/WM thread counts depend on the WIZ hashing
6337 * disable bit, which we don't touch here, but it's good
6338 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6339 */
6340 I915_WRITE(GEN6_GT_MODE,
98533251 6341 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6342
017636cc 6343 ilk_init_lp_watermarks(dev);
6f1d69b0 6344
6f1d69b0 6345 I915_WRITE(CACHE_MODE_0,
50743298 6346 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6347
6348 I915_WRITE(GEN6_UCGCTL1,
6349 I915_READ(GEN6_UCGCTL1) |
6350 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6351 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6352
6353 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6354 * gating disable must be set. Failure to set it results in
6355 * flickering pixels due to Z write ordering failures after
6356 * some amount of runtime in the Mesa "fire" demo, and Unigine
6357 * Sanctuary and Tropics, and apparently anything else with
6358 * alpha test or pixel discard.
6359 *
6360 * According to the spec, bit 11 (RCCUNIT) must also be set,
6361 * but we didn't debug actual testcases to find it out.
0f846f81 6362 *
ef59318c
VS		 6363 * WaDisableRCCUnitClockGating:snb
6364 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6365 */
6366 I915_WRITE(GEN6_UCGCTL2,
6367 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6368 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6369
5eb146dd 6370 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6371 I915_WRITE(_3D_CHICKEN3,
6372 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6373
e927ecde
VS		 6374 /*
6375 * Bspec says:
6376 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6377 * 3DSTATE_SF number of SF output attributes is more than 16."
6378 */
6379 I915_WRITE(_3D_CHICKEN3,
6380 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6381
6f1d69b0
ED		 6382 /*
6383 * According to the spec the following bits should be
6384 * set in order to enable memory self-refresh and fbc:
6385 * The bit21 and bit22 of 0x42000
6386 * The bit21 and bit22 of 0x42004
6387 * The bit5 and bit7 of 0x42020
6388 * The bit14 of 0x70180
6389 * The bit14 of 0x71180
4bb35334
DL		 6390 *
6391 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6392 */
6393 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6394 I915_READ(ILK_DISPLAY_CHICKEN1) |
6395 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6396 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6397 I915_READ(ILK_DISPLAY_CHICKEN2) |
6398 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6399 I915_WRITE(ILK_DSPCLK_GATE_D,
6400 I915_READ(ILK_DSPCLK_GATE_D) |
6401 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6402 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6403
0e088b8f 6404 g4x_disable_trickle_feed(dev);
f8f2ac9a 6405
3107bd48 6406 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6407
6408 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6409}
6410
6411static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6412{
6413 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6414
3aad9059 6415 /*
46680e0a 6416 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6417 *
6418 * This actually overrides the dispatch
6419 * mode for all thread types.
6420 */
6f1d69b0
ED		 6421 reg &= ~GEN7_FF_SCHED_MASK;
6422 reg |= GEN7_FF_TS_SCHED_HW;
6423 reg |= GEN7_FF_VS_SCHED_HW;
6424 reg |= GEN7_FF_DS_SCHED_HW;
6425
6426 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6427}
6428
17a303ec
PZ		 6429static void lpt_init_clock_gating(struct drm_device *dev)
6430{
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432
6433 /*
6434 * TODO: this bit should only be enabled when really needed, then
6435 * disabled when not needed anymore in order to save power.
6436 */
c2699524 6437 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6438 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6439 I915_READ(SOUTH_DSPCLK_GATE_D) |
6440 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6441
6442 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6443 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6444 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6445 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6446}
6447
7d708ee4
ID		 6448static void lpt_suspend_hw(struct drm_device *dev)
6449{
6450 struct drm_i915_private *dev_priv = dev->dev_private;
6451
c2699524 6452 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6453 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6454
6455 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6456 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6457 }
6458}
6459
47c2bd97 6460static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6461{
6462 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6463 enum pipe pipe;
4d487cff 6464 uint32_t misccpctl;
1020a5c2 6465
7ad0dbab 6466 ilk_init_lp_watermarks(dev);
50ed5fbd 6467
ab57fff1 6468 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6469 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6470
ab57fff1 6471 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6472 I915_WRITE(CHICKEN_PAR1_1,
6473 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6474
ab57fff1 6475 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6476 for_each_pipe(dev_priv, pipe) {
07d27e20 6477 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6478 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6479 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6480 }
63801f21 6481
ab57fff1
BW		 6482 /* WaVSRefCountFullforceMissDisable:bdw */
6483 /* WaDSRefCountFullforceMissDisable:bdw */
6484 I915_WRITE(GEN7_FF_THREAD_MODE,
6485 I915_READ(GEN7_FF_THREAD_MODE) &
6486 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6487
295e8bb7
VS		 6488 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6489 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6490
6491 /* WaDisableSDEUnitClockGating:bdw */
6492 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6493 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6494
4d487cff
VS		 6495 /*
6496 * WaProgramL3SqcReg1Default:bdw
6497 * WaTempDisableDOPClkGating:bdw
6498 */
6499 misccpctl = I915_READ(GEN7_MISCCPCTL);
6500 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6501 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6502 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6503
6d50b065
VS		 6504 /*
6505 * WaGttCachingOffByDefault:bdw
6506 * GTT cache may not work with big pages, so if those
6507 * are ever enabled GTT cache may need to be disabled.
6508 */
6509 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6510
89d6b2b8 6511 lpt_init_clock_gating(dev);
1020a5c2
BW		 6512}
6513
cad2a2d7
ED		 6514static void haswell_init_clock_gating(struct drm_device *dev)
6515{
6516 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6517
017636cc 6518 ilk_init_lp_watermarks(dev);
cad2a2d7 6519
f3fc4884
FJ		 6520 /* L3 caching of data atomics doesn't work -- disable it. */
6521 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6522 I915_WRITE(HSW_ROW_CHICKEN3,
6523 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6524
ecdb4eb7 6525 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6526 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6527 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6528 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6529
e36ea7ff
VS		 6530 /* WaVSRefCountFullforceMissDisable:hsw */
6531 I915_WRITE(GEN7_FF_THREAD_MODE,
6532 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6533
4e04632e
AG		 6534 /* WaDisable_RenderCache_OperationalFlush:hsw */
6535 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6536
fe27c606
CW		 6537 /* enable HiZ Raw Stall Optimization */
6538 I915_WRITE(CACHE_MODE_0_GEN7,
6539 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6540
ecdb4eb7 6541 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6542 I915_WRITE(CACHE_MODE_1,
6543 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6544
a12c4967
VS		 6545 /*
6546 * BSpec recommends 8x4 when MSAA is used,
6547 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6548 *
6549 * Note that PS/WM thread counts depend on the WIZ hashing
6550 * disable bit, which we don't touch here, but it's good
6551 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6552 */
6553 I915_WRITE(GEN7_GT_MODE,
98533251 6554 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6555
94411593
KG		 6556 /* WaSampleCChickenBitEnable:hsw */
6557 I915_WRITE(HALF_SLICE_CHICKEN3,
6558 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6559
ecdb4eb7 6560 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6561 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6562
90a88643
PZ		 6563 /* WaRsPkgCStateDisplayPMReq:hsw */
6564 I915_WRITE(CHICKEN_PAR1_1,
6565 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6566
17a303ec 6567 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6568}
6569
1fa61106 6570static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6571{
6572 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6573 uint32_t snpcr;
6f1d69b0 6574
017636cc 6575 ilk_init_lp_watermarks(dev);
6f1d69b0 6576
231e54f6 6577 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6578
ecdb4eb7 6579 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6580 I915_WRITE(_3D_CHICKEN3,
6581 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6582
ecdb4eb7 6583 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6584 I915_WRITE(IVB_CHICKEN3,
6585 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6586 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6587
ecdb4eb7 6588 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6589 if (IS_IVB_GT1(dev))
6590 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6591 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6592
4e04632e
AG		 6593 /* WaDisable_RenderCache_OperationalFlush:ivb */
6594 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6595
ecdb4eb7 6596 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6597 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6598 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6599
ecdb4eb7 6600 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6601 I915_WRITE(GEN7_L3CNTLREG1,
6602 GEN7_WA_FOR_GEN7_L3_CONTROL);
6603 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6604 GEN7_WA_L3_CHICKEN_MODE);
6605 if (IS_IVB_GT1(dev))
6606 I915_WRITE(GEN7_ROW_CHICKEN2,
6607 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6608 else {
6609 /* must write both registers */
6610 I915_WRITE(GEN7_ROW_CHICKEN2,
6611 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6612 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6613 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6614 }
6f1d69b0 6615
ecdb4eb7 6616 /* WaForceL3Serialization:ivb */
61939d97
JB		 6617 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6618 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6619
1b80a19a 6620 /*
0f846f81 6621 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6622 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6623 */
6624 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6625 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6626
ecdb4eb7 6627 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6628 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6629 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6630 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6631
0e088b8f 6632 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6633
6634 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6635
22721343
CW		 6636 if (0) { /* causes HiZ corruption on ivb:gt1 */
6637 /* enable HiZ Raw Stall Optimization */
6638 I915_WRITE(CACHE_MODE_0_GEN7,
6639 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6640 }
116f2b6d 6641
ecdb4eb7 6642 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6643 I915_WRITE(CACHE_MODE_1,
6644 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6645
a607c1a4
VS		 6646 /*
6647 * BSpec recommends 8x4 when MSAA is used,
6648 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6649 *
6650 * Note that PS/WM thread counts depend on the WIZ hashing
6651 * disable bit, which we don't touch here, but it's good
6652 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6653 */
6654 I915_WRITE(GEN7_GT_MODE,
98533251 6655 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6656
20848223
BW		 6657 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6658 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6659 snpcr |= GEN6_MBC_SNPCR_MED;
6660 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6661
ab5c608b
BW		 6662 if (!HAS_PCH_NOP(dev))
6663 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6664
6665 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6666}
6667
c6beb13e
VS		 6668static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6669{
6670 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6671
6672 /*
6673 * Disable trickle feed and enable pnd deadline calculation
6674 */
6675 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6676 I915_WRITE(CBR1_VLV, 0);
6677}
6678
1fa61106 6679static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6680{
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6682
c6beb13e 6683 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6684
ecdb4eb7 6685 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6686 I915_WRITE(_3D_CHICKEN3,
6687 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6688
ecdb4eb7 6689 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6690 I915_WRITE(IVB_CHICKEN3,
6691 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6692 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6693
fad7d36e 6694 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6695 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6696 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6697 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6698 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6699
4e04632e
AG		 6700 /* WaDisable_RenderCache_OperationalFlush:vlv */
6701 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6702
ecdb4eb7 6703 /* WaForceL3Serialization:vlv */
61939d97
JB		 6704 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6705 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6706
ecdb4eb7 6707 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6708 I915_WRITE(GEN7_ROW_CHICKEN2,
6709 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6710
ecdb4eb7 6711 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6712 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6713 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6714 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6715
46680e0a
VS		 6716 gen7_setup_fixed_func_scheduler(dev_priv);
6717
3c0edaeb 6718 /*
0f846f81 6719 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6720 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6721 */
6722 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6723 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6724
c98f5062
AG		 6725 /* WaDisableL3Bank2xClockGate:vlv
6726 * Disabling L3 clock gating- MMIO 940c[25] = 1
6727 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6728 I915_WRITE(GEN7_UCGCTL4,
6729 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6730
afd58e79
VS		 6731 /*
6732 * BSpec says this must be set, even though
6733 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6734 */
6b26c86d
DV		 6735 I915_WRITE(CACHE_MODE_1,
6736 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6737
da2518f9
VS		 6738 /*
6739 * BSpec recommends 8x4 when MSAA is used,
6740 * however in practice 16x4 seems fastest.
6741 *
6742 * Note that PS/WM thread counts depend on the WIZ hashing
6743 * disable bit, which we don't touch here, but it's good
6744 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6745 */
6746 I915_WRITE(GEN7_GT_MODE,
6747 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6748
031994ee
VS		 6749 /*
6750 * WaIncreaseL3CreditsForVLVB0:vlv
6751 * This is the hardware default actually.
6752 */
6753 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6754
2d809570 6755 /*
ecdb4eb7 6756 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6757 * Disable clock gating on th GCFG unit to prevent a delay
6758 * in the reporting of vblank events.
6759 */
7a0d1eed 6760 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6761}
6762
a4565da8
VS		 6763static void cherryview_init_clock_gating(struct drm_device *dev)
6764{
6765 struct drm_i915_private *dev_priv = dev->dev_private;
6766
c6beb13e 6767 vlv_init_display_clock_gating(dev_priv);
dd811e70 6768
232ce337
VS		 6769 /* WaVSRefCountFullforceMissDisable:chv */
6770 /* WaDSRefCountFullforceMissDisable:chv */
6771 I915_WRITE(GEN7_FF_THREAD_MODE,
6772 I915_READ(GEN7_FF_THREAD_MODE) &
6773 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6774
6775 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6776 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6777 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6778
6779 /* WaDisableCSUnitClockGating:chv */
6780 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6781 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6782
6783 /* WaDisableSDEUnitClockGating:chv */
6784 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6785 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6786
6787 /*
6788 * GTT cache may not work with big pages, so if those
6789 * are ever enabled GTT cache may need to be disabled.
6790 */
6791 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6792}
6793
1fa61106 6794static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6795{
6796 struct drm_i915_private *dev_priv = dev->dev_private;
6797 uint32_t dspclk_gate;
6798
6799 I915_WRITE(RENCLK_GATE_D1, 0);
6800 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6801 GS_UNIT_CLOCK_GATE_DISABLE |
6802 CL_UNIT_CLOCK_GATE_DISABLE);
6803 I915_WRITE(RAMCLK_GATE_D, 0);
6804 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6805 OVRUNIT_CLOCK_GATE_DISABLE |
6806 OVCUNIT_CLOCK_GATE_DISABLE;
6807 if (IS_GM45(dev))
6808 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6809 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6810
6811 /* WaDisableRenderCachePipelinedFlush */
6812 I915_WRITE(CACHE_MODE_0,
6813 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6814
4e04632e
AG		 6815 /* WaDisable_RenderCache_OperationalFlush:g4x */
6816 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6817
0e088b8f 6818 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6819}
6820
1fa61106 6821static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6822{
6823 struct drm_i915_private *dev_priv = dev->dev_private;
6824
6825 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6826 I915_WRITE(RENCLK_GATE_D2, 0);
6827 I915_WRITE(DSPCLK_GATE_D, 0);
6828 I915_WRITE(RAMCLK_GATE_D, 0);
6829 I915_WRITE16(DEUC, 0);
20f94967
VS		 6830 I915_WRITE(MI_ARB_STATE,
6831 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6832
6833 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6834 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6835}
6836
1fa61106 6837static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6838{
6839 struct drm_i915_private *dev_priv = dev->dev_private;
6840
6841 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6842 I965_RCC_CLOCK_GATE_DISABLE |
6843 I965_RCPB_CLOCK_GATE_DISABLE |
6844 I965_ISC_CLOCK_GATE_DISABLE |
6845 I965_FBC_CLOCK_GATE_DISABLE);
6846 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6847 I915_WRITE(MI_ARB_STATE,
6848 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6849
6850 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6851 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6852}
6853
1fa61106 6854static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6855{
6856 struct drm_i915_private *dev_priv = dev->dev_private;
6857 u32 dstate = I915_READ(D_STATE);
6858
6859 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6860 DSTATE_DOT_CLOCK_GATING;
6861 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6862
6863 if (IS_PINEVIEW(dev))
6864 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6865
6866 /* IIR "flip pending" means done if this bit is set */
6867 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6868
6869 /* interrupts should cause a wake up from C3 */
3299254f 6870 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6871
6872 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6873 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6874
6875 I915_WRITE(MI_ARB_STATE,
6876 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6877}
6878
1fa61106 6879static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6880{
6881 struct drm_i915_private *dev_priv = dev->dev_private;
6882
6883 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6884
6885 /* interrupts should cause a wake up from C3 */
6886 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6887 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6888
6889 I915_WRITE(MEM_MODE,
6890 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6891}
6892
1fa61106 6893static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6894{
6895 struct drm_i915_private *dev_priv = dev->dev_private;
6896
6897 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6898
6899 I915_WRITE(MEM_MODE,
6900 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6901 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6902}
6903
6f1d69b0
ED		 6904void intel_init_clock_gating(struct drm_device *dev)
6905{
6906 struct drm_i915_private *dev_priv = dev->dev_private;
6907
c57e3551
DL		 6908 if (dev_priv->display.init_clock_gating)
6909 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6910}
6911
7d708ee4
ID		 6912void intel_suspend_hw(struct drm_device *dev)
6913{
6914 if (HAS_PCH_LPT(dev))
6915 lpt_suspend_hw(dev);
6916}
6917
1fa61106
ED		 6918/* Set up chip specific power management-related functions */
6919void intel_init_pm(struct drm_device *dev)
6920{
6921 struct drm_i915_private *dev_priv = dev->dev_private;
6922
7ff0ebcc 6923 intel_fbc_init(dev_priv);
1fa61106 6924
c921aba8
DV		 6925 /* For cxsr */
6926 if (IS_PINEVIEW(dev))
6927 i915_pineview_get_mem_freq(dev);
6928 else if (IS_GEN5(dev))
6929 i915_ironlake_get_mem_freq(dev);
6930
1fa61106 6931 /* For FIFO watermark updates */
f5ed50cb 6932 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6933 skl_setup_wm_latency(dev);
6934
a82abe43
ID		 6935 if (IS_BROXTON(dev))
6936 dev_priv->display.init_clock_gating =
6937 bxt_init_clock_gating;
2d41c0b5 6938 dev_priv->display.update_wm = skl_update_wm;
c83155a6 6939 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6940 ilk_setup_wm_latency(dev);
53615a5e 6941
bd602544
VS		 6942 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6943 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6944 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6945 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6946 dev_priv->display.update_wm = ilk_update_wm;
86c8bbbe 6947 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
bd602544
VS		 6948 } else {
6949 DRM_DEBUG_KMS("Failed to read display plane latency. "
6950 "Disable CxSR\n");
6951 }
6952
6953 if (IS_GEN5(dev))
1fa61106 6954 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6955 else if (IS_GEN6(dev))
1fa61106 6956 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6957 else if (IS_IVYBRIDGE(dev))
1fa61106 6958 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6959 else if (IS_HASWELL(dev))
cad2a2d7 6960 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6961 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6962 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6963 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 6964 vlv_setup_wm_latency(dev);
6965
6966 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 6967 dev_priv->display.init_clock_gating =
6968 cherryview_init_clock_gating;
1fa61106 6969 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 6970 vlv_setup_wm_latency(dev);
6971
6972 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 6973 dev_priv->display.init_clock_gating =
6974 valleyview_init_clock_gating;
1fa61106
ED		 6975 } else if (IS_PINEVIEW(dev)) {
6976 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6977 dev_priv->is_ddr3,
6978 dev_priv->fsb_freq,
6979 dev_priv->mem_freq)) {
6980 DRM_INFO("failed to find known CxSR latency "
6981 "(found ddr%s fsb freq %d, mem freq %d), "
6982 "disabling CxSR\n",
6983 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6984 dev_priv->fsb_freq, dev_priv->mem_freq);
6985 /* Disable CxSR and never update its watermark again */
5209b1f4 6986 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6987 dev_priv->display.update_wm = NULL;
6988 } else
6989 dev_priv->display.update_wm = pineview_update_wm;
6990 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6991 } else if (IS_G4X(dev)) {
6992 dev_priv->display.update_wm = g4x_update_wm;
6993 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6994 } else if (IS_GEN4(dev)) {
6995 dev_priv->display.update_wm = i965_update_wm;
6996 if (IS_CRESTLINE(dev))
6997 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6998 else if (IS_BROADWATER(dev))
6999 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7000 } else if (IS_GEN3(dev)) {
7001 dev_priv->display.update_wm = i9xx_update_wm;
7002 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7003 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7004 } else if (IS_GEN2(dev)) {
7005 if (INTEL_INFO(dev)->num_pipes == 1) {
7006 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7007 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7008 } else {
7009 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7010 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7011 }
7012
7013 if (IS_I85X(dev) || IS_I865G(dev))
7014 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7015 else
7016 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7017 } else {
7018 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7019 }
7020}
7021
151a49d0 7022int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7023{
4fc688ce 7024 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7025
7026 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7027 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7028 return -EAGAIN;
7029 }
7030
7031 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7032 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7033 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7034
7035 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7036 500)) {
7037 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7038 return -ETIMEDOUT;
7039 }
7040
7041 *val = I915_READ(GEN6_PCODE_DATA);
7042 I915_WRITE(GEN6_PCODE_DATA, 0);
7043
7044 return 0;
7045}
7046
151a49d0 7047int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7048{
4fc688ce 7049 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7050
7051 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7052 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7053 return -EAGAIN;
7054 }
7055
7056 I915_WRITE(GEN6_PCODE_DATA, val);
7057 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7058
7059 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7060 500)) {
7061 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7062 return -ETIMEDOUT;
7063 }
7064
7065 I915_WRITE(GEN6_PCODE_DATA, 0);
7066
7067 return 0;
7068}
a0e4e199 7069
dd06f88c 7070static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7071{
dd06f88c
VS		 7072 switch (czclk_freq) {
7073 case 200:
7074 return 10;
7075 case 267:
7076 return 12;
7077 case 320:
7078 case 333:
dd06f88c 7079 return 16;
ab3fb157
VS		 7080 case 400:
7081 return 20;
855ba3be
JB		 7082 default:
7083 return -1;
7084 }
dd06f88c 7085}
855ba3be 7086
dd06f88c
VS		 7087static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7088{
bfa7df01 7089 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7090
7091 div = vlv_gpu_freq_div(czclk_freq);
7092 if (div < 0)
7093 return div;
7094
7095 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7096}
7097
b55dd647 7098static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7099{
bfa7df01 7100 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7101
dd06f88c
VS		 7102 mul = vlv_gpu_freq_div(czclk_freq);
7103 if (mul < 0)
7104 return mul;
855ba3be 7105
dd06f88c 7106 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7107}
7108
b55dd647 7109static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7110{
bfa7df01 7111 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7112
dd06f88c
VS		 7113 div = vlv_gpu_freq_div(czclk_freq) / 2;
7114 if (div < 0)
7115 return div;
22b1b2f8 7116
dd06f88c 7117 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7118}
7119
b55dd647 7120static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7121{
bfa7df01 7122 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7123
dd06f88c
VS		 7124 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7125 if (mul < 0)
7126 return mul;
22b1b2f8 7127
1c14762d 7128 /* CHV needs even values */
dd06f88c 7129 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7130}
7131
616bc820 7132int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7133{
80b6dda4
AG		 7134 if (IS_GEN9(dev_priv->dev))
7135 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7136 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7137 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7138 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7139 return byt_gpu_freq(dev_priv, val);
7140 else
7141 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7142}
7143
616bc820
VS		 7144int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7145{
80b6dda4
AG		 7146 if (IS_GEN9(dev_priv->dev))
7147 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7148 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7149 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7150 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7151 return byt_freq_opcode(dev_priv, val);
7152 else
7153 return val / GT_FREQUENCY_MULTIPLIER;
7154}
22b1b2f8 7155
6ad790c0
CW		 7156struct request_boost {
7157 struct work_struct work;
eed29a5b 7158 struct drm_i915_gem_request *req;
6ad790c0
CW		 7159};
7160
7161static void __intel_rps_boost_work(struct work_struct *work)
7162{
7163 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7164 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7165
e61b9958
CW		 7166 if (!i915_gem_request_completed(req, true))
7167 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7168 req->emitted_jiffies);
6ad790c0 7169
e61b9958 7170 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7171 kfree(boost);
7172}
7173
7174void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7175 struct drm_i915_gem_request *req)
6ad790c0
CW		 7176{
7177 struct request_boost *boost;
7178
eed29a5b 7179 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7180 return;
7181
e61b9958
CW		 7182 if (i915_gem_request_completed(req, true))
7183 return;
7184
6ad790c0
CW		 7185 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7186 if (boost == NULL)
7187 return;
7188
eed29a5b
DV		 7189 i915_gem_request_reference(req);
7190 boost->req = req;
6ad790c0
CW		 7191
7192 INIT_WORK(&boost->work, __intel_rps_boost_work);
7193 queue_work(to_i915(dev)->wq, &boost->work);
7194}
7195
f742a552 7196void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7197{
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199
f742a552 7200 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7201 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7202
907b28c5
CW		 7203 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7204 intel_gen6_powersave_work);
1854d5ca 7205 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7206 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7207 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7208
33688d95 7209 dev_priv->pm.suspended = false;
907b28c5 7210}
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