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drm/i915/skl+: calculate plane pixel rate (v4)
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
a82abe43
ID		 58static void bxt_init_clock_gating(struct drm_device *dev)
59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
dc00b6a0
DV		 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:bxt */
63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
a7546159
NH		 66 /* WaDisableSDEUnitClockGating:bxt */
67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
68 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
69
32608ca2
ID		 70 /*
71 * FIXME:
868434c5 72 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 73 */
32608ca2 74 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 75 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 76
77 /*
78 * Wa: Backlight PWM may stop in the asserted state, causing backlight
79 * to stay fully on.
80 */
81 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
82 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
83 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 84}
85
c921aba8
DV		 86static void i915_pineview_get_mem_freq(struct drm_device *dev)
87{
50227e1c 88 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 89 u32 tmp;
90
91 tmp = I915_READ(CLKCFG);
92
93 switch (tmp & CLKCFG_FSB_MASK) {
94 case CLKCFG_FSB_533:
95 dev_priv->fsb_freq = 533; /* 133*4 */
96 break;
97 case CLKCFG_FSB_800:
98 dev_priv->fsb_freq = 800; /* 200*4 */
99 break;
100 case CLKCFG_FSB_667:
101 dev_priv->fsb_freq = 667; /* 167*4 */
102 break;
103 case CLKCFG_FSB_400:
104 dev_priv->fsb_freq = 400; /* 100*4 */
105 break;
106 }
107
108 switch (tmp & CLKCFG_MEM_MASK) {
109 case CLKCFG_MEM_533:
110 dev_priv->mem_freq = 533;
111 break;
112 case CLKCFG_MEM_667:
113 dev_priv->mem_freq = 667;
114 break;
115 case CLKCFG_MEM_800:
116 dev_priv->mem_freq = 800;
117 break;
118 }
119
120 /* detect pineview DDR3 setting */
121 tmp = I915_READ(CSHRDDR3CTL);
122 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
123}
124
125static void i915_ironlake_get_mem_freq(struct drm_device *dev)
126{
50227e1c 127 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 128 u16 ddrpll, csipll;
129
130 ddrpll = I915_READ16(DDRMPLL1);
131 csipll = I915_READ16(CSIPLL0);
132
133 switch (ddrpll & 0xff) {
134 case 0xc:
135 dev_priv->mem_freq = 800;
136 break;
137 case 0x10:
138 dev_priv->mem_freq = 1066;
139 break;
140 case 0x14:
141 dev_priv->mem_freq = 1333;
142 break;
143 case 0x18:
144 dev_priv->mem_freq = 1600;
145 break;
146 default:
147 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
148 ddrpll & 0xff);
149 dev_priv->mem_freq = 0;
150 break;
151 }
152
20e4d407 153 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 154
155 switch (csipll & 0x3ff) {
156 case 0x00c:
157 dev_priv->fsb_freq = 3200;
158 break;
159 case 0x00e:
160 dev_priv->fsb_freq = 3733;
161 break;
162 case 0x010:
163 dev_priv->fsb_freq = 4266;
164 break;
165 case 0x012:
166 dev_priv->fsb_freq = 4800;
167 break;
168 case 0x014:
169 dev_priv->fsb_freq = 5333;
170 break;
171 case 0x016:
172 dev_priv->fsb_freq = 5866;
173 break;
174 case 0x018:
175 dev_priv->fsb_freq = 6400;
176 break;
177 default:
178 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
179 csipll & 0x3ff);
180 dev_priv->fsb_freq = 0;
181 break;
182 }
183
184 if (dev_priv->fsb_freq == 3200) {
20e4d407 185 dev_priv->ips.c_m = 0;
c921aba8 186 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 187 dev_priv->ips.c_m = 1;
c921aba8 188 } else {
20e4d407 189 dev_priv->ips.c_m = 2;
c921aba8
DV		 190 }
191}
192
b445e3b0
ED		 193static const struct cxsr_latency cxsr_latency_table[] = {
194 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
195 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
196 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
197 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
198 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
199
200 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
201 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
202 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
203 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
204 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
205
206 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
207 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
208 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
209 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
210 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
211
212 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
213 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
214 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
215 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
216 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
217
218 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
219 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
220 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
221 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
222 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
223
224 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
225 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
226 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
227 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
228 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
229};
230
63c62275 231static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 232 int is_ddr3,
233 int fsb,
234 int mem)
235{
236 const struct cxsr_latency *latency;
237 int i;
238
239 if (fsb == 0 || mem == 0)
240 return NULL;
241
242 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
243 latency = &cxsr_latency_table[i];
244 if (is_desktop == latency->is_desktop &&
245 is_ddr3 == latency->is_ddr3 &&
246 fsb == latency->fsb_freq && mem == latency->mem_freq)
247 return latency;
248 }
249
250 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
251
252 return NULL;
253}
254
fc1ac8de
VS		 255static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
256{
257 u32 val;
258
259 mutex_lock(&dev_priv->rps.hw_lock);
260
261 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
262 if (enable)
263 val &= ~FORCE_DDR_HIGH_FREQ;
264 else
265 val |= FORCE_DDR_HIGH_FREQ;
266 val &= ~FORCE_DDR_LOW_FREQ;
267 val |= FORCE_DDR_FREQ_REQ_ACK;
268 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
269
270 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
271 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
272 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
273
274 mutex_unlock(&dev_priv->rps.hw_lock);
275}
276
cfb41411
VS		 277static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
278{
279 u32 val;
280
281 mutex_lock(&dev_priv->rps.hw_lock);
282
283 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
284 if (enable)
285 val |= DSP_MAXFIFO_PM5_ENABLE;
286 else
287 val &= ~DSP_MAXFIFO_PM5_ENABLE;
288 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
289
290 mutex_unlock(&dev_priv->rps.hw_lock);
291}
292
f4998963
VS		 293#define FW_WM(value, plane) \
294 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
295
5209b1f4 296void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 297{
5209b1f4
ID		 298 struct drm_device *dev = dev_priv->dev;
299 u32 val;
b445e3b0 300
666a4537 301 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 302 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 303 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 304 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 305 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
306 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 307 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 308 } else if (IS_PINEVIEW(dev)) {
309 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
310 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
311 I915_WRITE(DSPFW3, val);
a7a6c498 312 POSTING_READ(DSPFW3);
5209b1f4
ID		 313 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
315 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
316 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 317 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 318 } else if (IS_I915GM(dev)) {
319 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
320 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
321 I915_WRITE(INSTPM, val);
a7a6c498 322 POSTING_READ(INSTPM);
5209b1f4
ID		 323 } else {
324 return;
325 }
b445e3b0 326
5209b1f4
ID		 327 DRM_DEBUG_KMS("memory self-refresh is %s\n",
328 enable ? "enabled" : "disabled");
b445e3b0
ED		 329}
330
fc1ac8de 331
b445e3b0
ED		 332/*
333 * Latency for FIFO fetches is dependent on several factors:
334 * - memory configuration (speed, channels)
335 * - chipset
336 * - current MCH state
337 * It can be fairly high in some situations, so here we assume a fairly
338 * pessimal value. It's a tradeoff between extra memory fetches (if we
339 * set this value too high, the FIFO will fetch frequently to stay full)
340 * and power consumption (set it too low to save power and we might see
341 * FIFO underruns and display "flicker").
342 *
343 * A value of 5us seems to be a good balance; safe for very low end
344 * platforms but not overly aggressive on lower latency configs.
345 */
5aef6003 346static const int pessimal_latency_ns = 5000;
b445e3b0 347
b5004720
VS		 348#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
349 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
350
351static int vlv_get_fifo_size(struct drm_device *dev,
352 enum pipe pipe, int plane)
353{
354 struct drm_i915_private *dev_priv = dev->dev_private;
355 int sprite0_start, sprite1_start, size;
356
357 switch (pipe) {
358 uint32_t dsparb, dsparb2, dsparb3;
359 case PIPE_A:
360 dsparb = I915_READ(DSPARB);
361 dsparb2 = I915_READ(DSPARB2);
362 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
363 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
364 break;
365 case PIPE_B:
366 dsparb = I915_READ(DSPARB);
367 dsparb2 = I915_READ(DSPARB2);
368 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
369 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
370 break;
371 case PIPE_C:
372 dsparb2 = I915_READ(DSPARB2);
373 dsparb3 = I915_READ(DSPARB3);
374 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
375 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
376 break;
377 default:
378 return 0;
379 }
380
381 switch (plane) {
382 case 0:
383 size = sprite0_start;
384 break;
385 case 1:
386 size = sprite1_start - sprite0_start;
387 break;
388 case 2:
389 size = 512 - 1 - sprite1_start;
390 break;
391 default:
392 return 0;
393 }
394
395 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
396 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
397 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
398 size);
399
400 return size;
401}
402
1fa61106 403static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 404{
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 uint32_t dsparb = I915_READ(DSPARB);
407 int size;
408
409 size = dsparb & 0x7f;
410 if (plane)
411 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
412
413 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
414 plane ? "B" : "A", size);
415
416 return size;
417}
418
feb56b93 419static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 420{
421 struct drm_i915_private *dev_priv = dev->dev_private;
422 uint32_t dsparb = I915_READ(DSPARB);
423 int size;
424
425 size = dsparb & 0x1ff;
426 if (plane)
427 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
428 size >>= 1; /* Convert to cachelines */
429
430 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
431 plane ? "B" : "A", size);
432
433 return size;
434}
435
1fa61106 436static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 437{
438 struct drm_i915_private *dev_priv = dev->dev_private;
439 uint32_t dsparb = I915_READ(DSPARB);
440 int size;
441
442 size = dsparb & 0x7f;
443 size >>= 2; /* Convert to cachelines */
444
445 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
446 plane ? "B" : "A",
447 size);
448
449 return size;
450}
451
b445e3b0
ED		 452/* Pineview has different values for various configs */
453static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 454 .fifo_size = PINEVIEW_DISPLAY_FIFO,
455 .max_wm = PINEVIEW_MAX_WM,
456 .default_wm = PINEVIEW_DFT_WM,
457 .guard_size = PINEVIEW_GUARD_WM,
458 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 459};
460static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 461 .fifo_size = PINEVIEW_DISPLAY_FIFO,
462 .max_wm = PINEVIEW_MAX_WM,
463 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
464 .guard_size = PINEVIEW_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 466};
467static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 468 .fifo_size = PINEVIEW_CURSOR_FIFO,
469 .max_wm = PINEVIEW_CURSOR_MAX_WM,
470 .default_wm = PINEVIEW_CURSOR_DFT_WM,
471 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 473};
474static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 475 .fifo_size = PINEVIEW_CURSOR_FIFO,
476 .max_wm = PINEVIEW_CURSOR_MAX_WM,
477 .default_wm = PINEVIEW_CURSOR_DFT_WM,
478 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
479 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 480};
481static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 482 .fifo_size = G4X_FIFO_SIZE,
483 .max_wm = G4X_MAX_WM,
484 .default_wm = G4X_MAX_WM,
485 .guard_size = 2,
486 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 487};
488static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 489 .fifo_size = I965_CURSOR_FIFO,
490 .max_wm = I965_CURSOR_MAX_WM,
491 .default_wm = I965_CURSOR_DFT_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 494};
b445e3b0 495static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = I965_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 503 .fifo_size = I945_FIFO_SIZE,
504 .max_wm = I915_MAX_WM,
505 .default_wm = 1,
506 .guard_size = 2,
507 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 510 .fifo_size = I915_FIFO_SIZE,
511 .max_wm = I915_MAX_WM,
512 .default_wm = 1,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 515};
9d539105 516static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 517 .fifo_size = I855GM_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 522};
9d539105
VS		 523static const struct intel_watermark_params i830_bc_wm_info = {
524 .fifo_size = I855GM_FIFO_SIZE,
525 .max_wm = I915_MAX_WM/2,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I830_FIFO_LINE_SIZE,
529};
feb56b93 530static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 531 .fifo_size = I830_FIFO_SIZE,
532 .max_wm = I915_MAX_WM,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 536};
537
b445e3b0
ED		 538/**
539 * intel_calculate_wm - calculate watermark level
540 * @clock_in_khz: pixel clock
541 * @wm: chip FIFO params
ac484963 542 * @cpp: bytes per pixel
b445e3b0
ED		 543 * @latency_ns: memory latency for the platform
544 *
545 * Calculate the watermark level (the level at which the display plane will
546 * start fetching from memory again). Each chip has a different display
547 * FIFO size and allocation, so the caller needs to figure that out and pass
548 * in the correct intel_watermark_params structure.
549 *
550 * As the pixel clock runs, the FIFO will be drained at a rate that depends
551 * on the pixel size. When it reaches the watermark level, it'll start
552 * fetching FIFO line sized based chunks from memory until the FIFO fills
553 * past the watermark point. If the FIFO drains completely, a FIFO underrun
554 * will occur, and a display engine hang could result.
555 */
556static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
557 const struct intel_watermark_params *wm,
ac484963 558 int fifo_size, int cpp,
b445e3b0
ED		 559 unsigned long latency_ns)
560{
561 long entries_required, wm_size;
562
563 /*
564 * Note: we need to make sure we don't overflow for various clock &
565 * latency values.
566 * clocks go from a few thousand to several hundred thousand.
567 * latency is usually a few thousand
568 */
ac484963 569 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 570 1000;
571 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
572
573 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
574
575 wm_size = fifo_size - (entries_required + wm->guard_size);
576
577 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
578
579 /* Don't promote wm_size to unsigned... */
580 if (wm_size > (long)wm->max_wm)
581 wm_size = wm->max_wm;
582 if (wm_size <= 0)
583 wm_size = wm->default_wm;
d6feb196
VS		 584
585 /*
586 * Bspec seems to indicate that the value shouldn't be lower than
587 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
588 * Lets go for 8 which is the burst size since certain platforms
589 * already use a hardcoded 8 (which is what the spec says should be
590 * done).
591 */
592 if (wm_size <= 8)
593 wm_size = 8;
594
b445e3b0
ED		 595 return wm_size;
596}
597
598static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
599{
600 struct drm_crtc *crtc, *enabled = NULL;
601
70e1e0ec 602 for_each_crtc(dev, crtc) {
3490ea5d 603 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 604 if (enabled)
605 return NULL;
606 enabled = crtc;
607 }
608 }
609
610 return enabled;
611}
612
46ba614c 613static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 614{
46ba614c 615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 616 struct drm_i915_private *dev_priv = dev->dev_private;
617 struct drm_crtc *crtc;
618 const struct cxsr_latency *latency;
619 u32 reg;
620 unsigned long wm;
621
622 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
623 dev_priv->fsb_freq, dev_priv->mem_freq);
624 if (!latency) {
625 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 626 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 627 return;
628 }
629
630 crtc = single_enabled_crtc(dev);
631 if (crtc) {
7c5f93b0 632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 633 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 634 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 635
636 /* Display SR */
637 wm = intel_calculate_wm(clock, &pineview_display_wm,
638 pineview_display_wm.fifo_size,
ac484963 639 cpp, latency->display_sr);
b445e3b0
ED		 640 reg = I915_READ(DSPFW1);
641 reg &= ~DSPFW_SR_MASK;
f4998963 642 reg |= FW_WM(wm, SR);
b445e3b0
ED		 643 I915_WRITE(DSPFW1, reg);
644 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
645
646 /* cursor SR */
647 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
648 pineview_display_wm.fifo_size,
ac484963 649 cpp, latency->cursor_sr);
b445e3b0
ED		 650 reg = I915_READ(DSPFW3);
651 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 652 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 653 I915_WRITE(DSPFW3, reg);
654
655 /* Display HPLL off SR */
656 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
657 pineview_display_hplloff_wm.fifo_size,
ac484963 658 cpp, latency->display_hpll_disable);
b445e3b0
ED		 659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 661 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 662 I915_WRITE(DSPFW3, reg);
663
664 /* cursor HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
ac484963 667 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 670 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 671 I915_WRITE(DSPFW3, reg);
672 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
673
5209b1f4 674 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 675 } else {
5209b1f4 676 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 677 }
678}
679
680static bool g4x_compute_wm0(struct drm_device *dev,
681 int plane,
682 const struct intel_watermark_params *display,
683 int display_latency_ns,
684 const struct intel_watermark_params *cursor,
685 int cursor_latency_ns,
686 int *plane_wm,
687 int *cursor_wm)
688{
689 struct drm_crtc *crtc;
4fe8590a 690 const struct drm_display_mode *adjusted_mode;
ac484963 691 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 692 int line_time_us, line_count;
693 int entries, tlb_miss;
694
695 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 696 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 697 *cursor_wm = cursor->guard_size;
698 *plane_wm = display->guard_size;
699 return false;
700 }
701
6e3c9717 702 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 703 clock = adjusted_mode->crtc_clock;
fec8cba3 704 htotal = adjusted_mode->crtc_htotal;
6e3c9717 705 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 706 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 707
708 /* Use the small buffer method to calculate plane watermark */
ac484963 709 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 710 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
711 if (tlb_miss > 0)
712 entries += tlb_miss;
713 entries = DIV_ROUND_UP(entries, display->cacheline_size);
714 *plane_wm = entries + display->guard_size;
715 if (*plane_wm > (int)display->max_wm)
716 *plane_wm = display->max_wm;
717
718 /* Use the large buffer method to calculate cursor watermark */
922044c9 719 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 720 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 721 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 722 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
723 if (tlb_miss > 0)
724 entries += tlb_miss;
725 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
726 *cursor_wm = entries + cursor->guard_size;
727 if (*cursor_wm > (int)cursor->max_wm)
728 *cursor_wm = (int)cursor->max_wm;
729
730 return true;
731}
732
733/*
734 * Check the wm result.
735 *
736 * If any calculated watermark values is larger than the maximum value that
737 * can be programmed into the associated watermark register, that watermark
738 * must be disabled.
739 */
740static bool g4x_check_srwm(struct drm_device *dev,
741 int display_wm, int cursor_wm,
742 const struct intel_watermark_params *display,
743 const struct intel_watermark_params *cursor)
744{
745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
746 display_wm, cursor_wm);
747
748 if (display_wm > display->max_wm) {
749 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
750 display_wm, display->max_wm);
751 return false;
752 }
753
754 if (cursor_wm > cursor->max_wm) {
755 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
756 cursor_wm, cursor->max_wm);
757 return false;
758 }
759
760 if (!(display_wm || cursor_wm)) {
761 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
762 return false;
763 }
764
765 return true;
766}
767
768static bool g4x_compute_srwm(struct drm_device *dev,
769 int plane,
770 int latency_ns,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor,
773 int *display_wm, int *cursor_wm)
774{
775 struct drm_crtc *crtc;
4fe8590a 776 const struct drm_display_mode *adjusted_mode;
ac484963 777 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 778 unsigned long line_time_us;
779 int line_count, line_size;
780 int small, large;
781 int entries;
782
783 if (!latency_ns) {
784 *display_wm = *cursor_wm = 0;
785 return false;
786 }
787
788 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 789 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 790 clock = adjusted_mode->crtc_clock;
fec8cba3 791 htotal = adjusted_mode->crtc_htotal;
6e3c9717 792 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 793 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 794
922044c9 795 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 796 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 797 line_size = hdisplay * cpp;
b445e3b0
ED		 798
799 /* Use the minimum of the small and large buffer method for primary */
ac484963 800 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 801 large = line_count * line_size;
802
803 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
804 *display_wm = entries + display->guard_size;
805
806 /* calculate the self-refresh watermark for display cursor */
ac484963 807 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 808 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
809 *cursor_wm = entries + cursor->guard_size;
810
811 return g4x_check_srwm(dev,
812 *display_wm, *cursor_wm,
813 display, cursor);
814}
815
15665979
VS		 816#define FW_WM_VLV(value, plane) \
817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
818
0018fda1
VS		 819static void vlv_write_wm_values(struct intel_crtc *crtc,
820 const struct vlv_wm_values *wm)
821{
822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
823 enum pipe pipe = crtc->pipe;
824
825 I915_WRITE(VLV_DDL(pipe),
826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
830
ae80152d 831 I915_WRITE(DSPFW1,
15665979
VS		 832 FW_WM(wm->sr.plane, SR) |
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 836 I915_WRITE(DSPFW2,
15665979
VS		 837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 840 I915_WRITE(DSPFW3,
15665979 841 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 842
843 if (IS_CHERRYVIEW(dev_priv)) {
844 I915_WRITE(DSPFW7_CHV,
15665979
VS		 845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 847 I915_WRITE(DSPFW8_CHV,
15665979
VS		 848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 850 I915_WRITE(DSPFW9_CHV,
15665979
VS		 851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 853 I915_WRITE(DSPHOWM,
15665979
VS		 854 FW_WM(wm->sr.plane >> 9, SR_HI) |
855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 864 } else {
865 I915_WRITE(DSPFW7,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 868 I915_WRITE(DSPHOWM,
15665979
VS		 869 FW_WM(wm->sr.plane >> 9, SR_HI) |
870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 876 }
877
2cb389b7
VS		 878 /* zero (unused) WM1 watermarks */
879 I915_WRITE(DSPFW4, 0);
880 I915_WRITE(DSPFW5, 0);
881 I915_WRITE(DSPFW6, 0);
882 I915_WRITE(DSPHOWM1, 0);
883
ae80152d 884 POSTING_READ(DSPFW1);
0018fda1
VS		 885}
886
15665979
VS		 887#undef FW_WM_VLV
888
6eb1a681
VS		 889enum vlv_wm_level {
890 VLV_WM_LEVEL_PM2,
891 VLV_WM_LEVEL_PM5,
892 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 893};
894
262cd2e1
VS		 895/* latency must be in 0.1us units. */
896static unsigned int vlv_wm_method2(unsigned int pixel_rate,
897 unsigned int pipe_htotal,
898 unsigned int horiz_pixels,
ac484963 899 unsigned int cpp,
262cd2e1
VS		 900 unsigned int latency)
901{
902 unsigned int ret;
903
904 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 905 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 906 ret = DIV_ROUND_UP(ret, 64);
907
908 return ret;
909}
910
911static void vlv_setup_wm_latency(struct drm_device *dev)
912{
913 struct drm_i915_private *dev_priv = dev->dev_private;
914
915 /* all latencies in usec */
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
917
58590c14
VS		 918 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
919
262cd2e1
VS		 920 if (IS_CHERRYVIEW(dev_priv)) {
921 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
922 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 923
924 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 925 }
926}
927
928static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
929 struct intel_crtc *crtc,
930 const struct intel_plane_state *state,
931 int level)
932{
933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 934 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 935
936 if (dev_priv->wm.pri_latency[level] == 0)
937 return USHRT_MAX;
938
939 if (!state->visible)
940 return 0;
941
ac484963 942 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 943 clock = crtc->config->base.adjusted_mode.crtc_clock;
944 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
945 width = crtc->config->pipe_src_w;
946 if (WARN_ON(htotal == 0))
947 htotal = 1;
948
949 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
950 /*
951 * FIXME the formula gives values that are
952 * too big for the cursor FIFO, and hence we
953 * would never be able to use cursors. For
954 * now just hardcode the watermark.
955 */
956 wm = 63;
957 } else {
ac484963 958 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 959 dev_priv->wm.pri_latency[level] * 10);
960 }
961
962 return min_t(int, wm, USHRT_MAX);
963}
964
54f1b6e1
VS		 965static void vlv_compute_fifo(struct intel_crtc *crtc)
966{
967 struct drm_device *dev = crtc->base.dev;
968 struct vlv_wm_state *wm_state = &crtc->wm_state;
969 struct intel_plane *plane;
970 unsigned int total_rate = 0;
971 const int fifo_size = 512 - 1;
972 int fifo_extra, fifo_left = fifo_size;
973
974 for_each_intel_plane_on_crtc(dev, crtc, plane) {
975 struct intel_plane_state *state =
976 to_intel_plane_state(plane->base.state);
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
979 continue;
980
981 if (state->visible) {
982 wm_state->num_active_planes++;
983 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
984 }
985 }
986
987 for_each_intel_plane_on_crtc(dev, crtc, plane) {
988 struct intel_plane_state *state =
989 to_intel_plane_state(plane->base.state);
990 unsigned int rate;
991
992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
993 plane->wm.fifo_size = 63;
994 continue;
995 }
996
997 if (!state->visible) {
998 plane->wm.fifo_size = 0;
999 continue;
1000 }
1001
1002 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004 fifo_left -= plane->wm.fifo_size;
1005 }
1006
1007 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009 /* spread the remainder evenly */
1010 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011 int plane_extra;
1012
1013 if (fifo_left == 0)
1014 break;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017 continue;
1018
1019 /* give it all to the first plane if none are active */
1020 if (plane->wm.fifo_size == 0 &&
1021 wm_state->num_active_planes)
1022 continue;
1023
1024 plane_extra = min(fifo_extra, fifo_left);
1025 plane->wm.fifo_size += plane_extra;
1026 fifo_left -= plane_extra;
1027 }
1028
1029 WARN_ON(fifo_left != 0);
1030}
1031
262cd2e1
VS		 1032static void vlv_invert_wms(struct intel_crtc *crtc)
1033{
1034 struct vlv_wm_state *wm_state = &crtc->wm_state;
1035 int level;
1036
1037 for (level = 0; level < wm_state->num_levels; level++) {
1038 struct drm_device *dev = crtc->base.dev;
1039 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040 struct intel_plane *plane;
1041
1042 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046 switch (plane->base.type) {
1047 int sprite;
1048 case DRM_PLANE_TYPE_CURSOR:
1049 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050 wm_state->wm[level].cursor;
1051 break;
1052 case DRM_PLANE_TYPE_PRIMARY:
1053 wm_state->wm[level].primary = plane->wm.fifo_size -
1054 wm_state->wm[level].primary;
1055 break;
1056 case DRM_PLANE_TYPE_OVERLAY:
1057 sprite = plane->plane;
1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059 wm_state->wm[level].sprite[sprite];
1060 break;
1061 }
1062 }
1063 }
1064}
1065
26e1fe4f 1066static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1067{
1068 struct drm_device *dev = crtc->base.dev;
1069 struct vlv_wm_state *wm_state = &crtc->wm_state;
1070 struct intel_plane *plane;
1071 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072 int level;
1073
1074 memset(wm_state, 0, sizeof(*wm_state));
1075
852eb00d 1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1078
1079 wm_state->num_active_planes = 0;
262cd2e1 1080
54f1b6e1 1081 vlv_compute_fifo(crtc);
262cd2e1
VS		 1082
1083 if (wm_state->num_active_planes != 1)
1084 wm_state->cxsr = false;
1085
1086 if (wm_state->cxsr) {
1087 for (level = 0; level < wm_state->num_levels; level++) {
1088 wm_state->sr[level].plane = sr_fifo_size;
1089 wm_state->sr[level].cursor = 63;
1090 }
1091 }
1092
1093 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094 struct intel_plane_state *state =
1095 to_intel_plane_state(plane->base.state);
1096
1097 if (!state->visible)
1098 continue;
1099
1100 /* normal watermarks */
1101 for (level = 0; level < wm_state->num_levels; level++) {
1102 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105 /* hack */
1106 if (WARN_ON(level == 0 && wm > max_wm))
1107 wm = max_wm;
1108
1109 if (wm > plane->wm.fifo_size)
1110 break;
1111
1112 switch (plane->base.type) {
1113 int sprite;
1114 case DRM_PLANE_TYPE_CURSOR:
1115 wm_state->wm[level].cursor = wm;
1116 break;
1117 case DRM_PLANE_TYPE_PRIMARY:
1118 wm_state->wm[level].primary = wm;
1119 break;
1120 case DRM_PLANE_TYPE_OVERLAY:
1121 sprite = plane->plane;
1122 wm_state->wm[level].sprite[sprite] = wm;
1123 break;
1124 }
1125 }
1126
1127 wm_state->num_levels = level;
1128
1129 if (!wm_state->cxsr)
1130 continue;
1131
1132 /* maxfifo watermarks */
1133 switch (plane->base.type) {
1134 int sprite, level;
1135 case DRM_PLANE_TYPE_CURSOR:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].cursor =
5a37ed0a 1138 wm_state->wm[level].cursor;
262cd2e1
VS		 1139 break;
1140 case DRM_PLANE_TYPE_PRIMARY:
1141 for (level = 0; level < wm_state->num_levels; level++)
1142 wm_state->sr[level].plane =
1143 min(wm_state->sr[level].plane,
1144 wm_state->wm[level].primary);
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 for (level = 0; level < wm_state->num_levels; level++)
1149 wm_state->sr[level].plane =
1150 min(wm_state->sr[level].plane,
1151 wm_state->wm[level].sprite[sprite]);
1152 break;
1153 }
1154 }
1155
1156 /* clear any (partially) filled invalid levels */
58590c14 1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1158 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160 }
1161
1162 vlv_invert_wms(crtc);
1163}
1164
54f1b6e1
VS		 1165#define VLV_FIFO(plane, value) \
1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169{
1170 struct drm_device *dev = crtc->base.dev;
1171 struct drm_i915_private *dev_priv = to_i915(dev);
1172 struct intel_plane *plane;
1173 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177 WARN_ON(plane->wm.fifo_size != 63);
1178 continue;
1179 }
1180
1181 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182 sprite0_start = plane->wm.fifo_size;
1183 else if (plane->plane == 0)
1184 sprite1_start = sprite0_start + plane->wm.fifo_size;
1185 else
1186 fifo_size = sprite1_start + plane->wm.fifo_size;
1187 }
1188
1189 WARN_ON(fifo_size != 512 - 1);
1190
1191 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192 pipe_name(crtc->pipe), sprite0_start,
1193 sprite1_start, fifo_size);
1194
1195 switch (crtc->pipe) {
1196 uint32_t dsparb, dsparb2, dsparb3;
1197 case PIPE_A:
1198 dsparb = I915_READ(DSPARB);
1199 dsparb2 = I915_READ(DSPARB2);
1200
1201 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202 VLV_FIFO(SPRITEB, 0xff));
1203 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204 VLV_FIFO(SPRITEB, sprite1_start));
1205
1206 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207 VLV_FIFO(SPRITEB_HI, 0x1));
1208 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211 I915_WRITE(DSPARB, dsparb);
1212 I915_WRITE(DSPARB2, dsparb2);
1213 break;
1214 case PIPE_B:
1215 dsparb = I915_READ(DSPARB);
1216 dsparb2 = I915_READ(DSPARB2);
1217
1218 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219 VLV_FIFO(SPRITED, 0xff));
1220 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221 VLV_FIFO(SPRITED, sprite1_start));
1222
1223 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224 VLV_FIFO(SPRITED_HI, 0xff));
1225 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228 I915_WRITE(DSPARB, dsparb);
1229 I915_WRITE(DSPARB2, dsparb2);
1230 break;
1231 case PIPE_C:
1232 dsparb3 = I915_READ(DSPARB3);
1233 dsparb2 = I915_READ(DSPARB2);
1234
1235 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236 VLV_FIFO(SPRITEF, 0xff));
1237 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238 VLV_FIFO(SPRITEF, sprite1_start));
1239
1240 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241 VLV_FIFO(SPRITEF_HI, 0xff));
1242 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245 I915_WRITE(DSPARB3, dsparb3);
1246 I915_WRITE(DSPARB2, dsparb2);
1247 break;
1248 default:
1249 break;
1250 }
1251}
1252
1253#undef VLV_FIFO
1254
262cd2e1
VS		 1255static void vlv_merge_wm(struct drm_device *dev,
1256 struct vlv_wm_values *wm)
1257{
1258 struct intel_crtc *crtc;
1259 int num_active_crtcs = 0;
1260
58590c14 1261 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1262 wm->cxsr = true;
1263
1264 for_each_intel_crtc(dev, crtc) {
1265 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267 if (!crtc->active)
1268 continue;
1269
1270 if (!wm_state->cxsr)
1271 wm->cxsr = false;
1272
1273 num_active_crtcs++;
1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275 }
1276
1277 if (num_active_crtcs != 1)
1278 wm->cxsr = false;
1279
6f9c784b
VS		 1280 if (num_active_crtcs > 1)
1281 wm->level = VLV_WM_LEVEL_PM2;
1282
262cd2e1
VS		 1283 for_each_intel_crtc(dev, crtc) {
1284 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285 enum pipe pipe = crtc->pipe;
1286
1287 if (!crtc->active)
1288 continue;
1289
1290 wm->pipe[pipe] = wm_state->wm[wm->level];
1291 if (wm->cxsr)
1292 wm->sr = wm_state->sr[wm->level];
1293
1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298 }
1299}
1300
1301static void vlv_update_wm(struct drm_crtc *crtc)
1302{
1303 struct drm_device *dev = crtc->dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306 enum pipe pipe = intel_crtc->pipe;
1307 struct vlv_wm_values wm = {};
1308
26e1fe4f 1309 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1310 vlv_merge_wm(dev, &wm);
1311
54f1b6e1
VS		 1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313 /* FIXME should be part of crtc atomic commit */
1314 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1315 return;
54f1b6e1 1316 }
262cd2e1
VS		 1317
1318 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320 chv_set_memory_dvfs(dev_priv, false);
1321
1322 if (wm.level < VLV_WM_LEVEL_PM5 &&
1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324 chv_set_memory_pm5(dev_priv, false);
1325
852eb00d 1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1327 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1328
54f1b6e1
VS		 1329 /* FIXME should be part of crtc atomic commit */
1330 vlv_pipe_set_fifo_size(intel_crtc);
1331
262cd2e1
VS		 1332 vlv_write_wm_values(intel_crtc, &wm);
1333
1334 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
852eb00d 1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1341 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1342
1343 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345 chv_set_memory_pm5(dev_priv, true);
1346
1347 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, true);
1350
1351 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1352}
1353
ae80152d
VS		 1354#define single_plane_enabled(mask) is_power_of_2(mask)
1355
46ba614c 1356static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1357{
46ba614c 1358 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1359 static const int sr_latency_ns = 12000;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362 int plane_sr, cursor_sr;
1363 unsigned int enabled = 0;
9858425c 1364 bool cxsr_enabled;
b445e3b0 1365
51cea1f4 1366 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1367 &g4x_wm_info, pessimal_latency_ns,
1368 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1369 &planea_wm, &cursora_wm))
51cea1f4 1370 enabled |= 1 << PIPE_A;
b445e3b0 1371
51cea1f4 1372 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1373 &g4x_wm_info, pessimal_latency_ns,
1374 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1375 &planeb_wm, &cursorb_wm))
51cea1f4 1376 enabled |= 1 << PIPE_B;
b445e3b0 1377
b445e3b0
ED		 1378 if (single_plane_enabled(enabled) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1380 sr_latency_ns,
1381 &g4x_wm_info,
1382 &g4x_cursor_wm_info,
52bd02d8 1383 &plane_sr, &cursor_sr)) {
9858425c 1384 cxsr_enabled = true;
52bd02d8 1385 } else {
9858425c 1386 cxsr_enabled = false;
5209b1f4 1387 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1388 plane_sr = cursor_sr = 0;
1389 }
b445e3b0 1390
a5043453
VS		 1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1393 planea_wm, cursora_wm,
1394 planeb_wm, cursorb_wm,
1395 plane_sr, cursor_sr);
1396
1397 I915_WRITE(DSPFW1,
f4998963
VS		 1398 FW_WM(plane_sr, SR) |
1399 FW_WM(cursorb_wm, CURSORB) |
1400 FW_WM(planeb_wm, PLANEB) |
1401 FW_WM(planea_wm, PLANEA));
b445e3b0 1402 I915_WRITE(DSPFW2,
8c919b28 1403 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1404 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1405 /* HPLL off in SR has some issues on G4x... disable it */
1406 I915_WRITE(DSPFW3,
8c919b28 1407 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1408 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1409
1410 if (cxsr_enabled)
1411 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1412}
1413
46ba614c 1414static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1415{
46ba614c 1416 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct drm_crtc *crtc;
1419 int srwm = 1;
1420 int cursor_sr = 16;
9858425c 1421 bool cxsr_enabled;
b445e3b0
ED		 1422
1423 /* Calc sr entries for one plane configs */
1424 crtc = single_enabled_crtc(dev);
1425 if (crtc) {
1426 /* self-refresh has much higher latency */
1427 static const int sr_latency_ns = 12000;
124abe07 1428 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1429 int clock = adjusted_mode->crtc_clock;
fec8cba3 1430 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1431 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1432 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1433 unsigned long line_time_us;
1434 int entries;
1435
922044c9 1436 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1437
1438 /* Use ns/us then divide to preserve precision */
1439 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1440 cpp * hdisplay;
b445e3b0
ED		 1441 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442 srwm = I965_FIFO_SIZE - entries;
1443 if (srwm < 0)
1444 srwm = 1;
1445 srwm &= 0x1ff;
1446 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447 entries, srwm);
1448
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1450 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1451 entries = DIV_ROUND_UP(entries,
1452 i965_cursor_wm_info.cacheline_size);
1453 cursor_sr = i965_cursor_wm_info.fifo_size -
1454 (entries + i965_cursor_wm_info.guard_size);
1455
1456 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457 cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460 "cursor %d\n", srwm, cursor_sr);
1461
9858425c 1462 cxsr_enabled = true;
b445e3b0 1463 } else {
9858425c 1464 cxsr_enabled = false;
b445e3b0 1465 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1466 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1467 }
1468
1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470 srwm);
1471
1472 /* 965 has limitations... */
f4998963
VS		 1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474 FW_WM(8, CURSORB) |
1475 FW_WM(8, PLANEB) |
1476 FW_WM(8, PLANEA));
1477 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478 FW_WM(8, PLANEC_OLD));
b445e3b0 1479 /* update cursor SR watermark */
f4998963 1480 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1481
1482 if (cxsr_enabled)
1483 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1484}
1485
f4998963
VS		 1486#undef FW_WM
1487
46ba614c 1488static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1489{
46ba614c 1490 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 const struct intel_watermark_params *wm_info;
1493 uint32_t fwater_lo;
1494 uint32_t fwater_hi;
1495 int cwm, srwm = 1;
1496 int fifo_size;
1497 int planea_wm, planeb_wm;
1498 struct drm_crtc *crtc, *enabled = NULL;
1499
1500 if (IS_I945GM(dev))
1501 wm_info = &i945_wm_info;
1502 else if (!IS_GEN2(dev))
1503 wm_info = &i915_wm_info;
1504 else
9d539105 1505 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1506
1507 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1509 if (intel_crtc_active(crtc)) {
241bfc38 1510 const struct drm_display_mode *adjusted_mode;
ac484963 1511 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1512 if (IS_GEN2(dev))
1513 cpp = 4;
1514
6e3c9717 1515 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1516 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1517 wm_info, fifo_size, cpp,
5aef6003 1518 pessimal_latency_ns);
b445e3b0 1519 enabled = crtc;
9d539105 1520 } else {
b445e3b0 1521 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1522 if (planea_wm > (long)wm_info->max_wm)
1523 planea_wm = wm_info->max_wm;
1524 }
1525
1526 if (IS_GEN2(dev))
1527 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1528
1529 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1531 if (intel_crtc_active(crtc)) {
241bfc38 1532 const struct drm_display_mode *adjusted_mode;
ac484963 1533 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1534 if (IS_GEN2(dev))
1535 cpp = 4;
1536
6e3c9717 1537 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1538 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1539 wm_info, fifo_size, cpp,
5aef6003 1540 pessimal_latency_ns);
b445e3b0
ED		 1541 if (enabled == NULL)
1542 enabled = crtc;
1543 else
1544 enabled = NULL;
9d539105 1545 } else {
b445e3b0 1546 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1547 if (planeb_wm > (long)wm_info->max_wm)
1548 planeb_wm = wm_info->max_wm;
1549 }
b445e3b0
ED		 1550
1551 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
2ab1bc9d 1553 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1554 struct drm_i915_gem_object *obj;
2ab1bc9d 1555
59bea882 1556 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1557
1558 /* self-refresh seems busted with untiled */
2ff8fde1 1559 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1560 enabled = NULL;
1561 }
1562
b445e3b0
ED		 1563 /*
1564 * Overlay gets an aggressive default since video jitter is bad.
1565 */
1566 cwm = 2;
1567
1568 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1569 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1570
1571 /* Calc sr entries for one plane configs */
1572 if (HAS_FW_BLC(dev) && enabled) {
1573 /* self-refresh has much higher latency */
1574 static const int sr_latency_ns = 6000;
124abe07 1575 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1576 int clock = adjusted_mode->crtc_clock;
fec8cba3 1577 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1578 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1579 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1580 unsigned long line_time_us;
1581 int entries;
1582
922044c9 1583 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1584
1585 /* Use ns/us then divide to preserve precision */
1586 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1587 cpp * hdisplay;
b445e3b0
ED		 1588 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590 srwm = wm_info->fifo_size - entries;
1591 if (srwm < 0)
1592 srwm = 1;
1593
1594 if (IS_I945G(dev) || IS_I945GM(dev))
1595 I915_WRITE(FW_BLC_SELF,
1596 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597 else if (IS_I915GM(dev))
1598 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599 }
1600
1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602 planea_wm, planeb_wm, cwm, srwm);
1603
1604 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605 fwater_hi = (cwm & 0x1f);
1606
1607 /* Set request length to 8 cachelines per fetch */
1608 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609 fwater_hi = fwater_hi | (1 << 8);
1610
1611 I915_WRITE(FW_BLC, fwater_lo);
1612 I915_WRITE(FW_BLC2, fwater_hi);
1613
5209b1f4
ID		 1614 if (enabled)
1615 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1616}
1617
feb56b93 1618static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1619{
46ba614c 1620 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 struct drm_crtc *crtc;
241bfc38 1623 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1624 uint32_t fwater_lo;
1625 int planea_wm;
1626
1627 crtc = single_enabled_crtc(dev);
1628 if (crtc == NULL)
1629 return;
1630
6e3c9717 1631 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1632 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1633 &i845_wm_info,
b445e3b0 1634 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1635 4, pessimal_latency_ns);
b445e3b0
ED		 1636 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637 fwater_lo |= (3<<8) | planea_wm;
1638
1639 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641 I915_WRITE(FW_BLC, fwater_lo);
1642}
1643
8cfb3407 1644uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1645{
fd4daa9c 1646 uint32_t pixel_rate;
801bcfff 1647
8cfb3407 1648 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1649
1650 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651 * adjust the pixel_rate here. */
1652
8cfb3407 1653 if (pipe_config->pch_pfit.enabled) {
801bcfff 1654 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1655 uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657 pipe_w = pipe_config->pipe_src_w;
1658 pipe_h = pipe_config->pipe_src_h;
801bcfff 1659
801bcfff
PZ		 1660 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661 pfit_h = pfit_size & 0xFFFF;
1662 if (pipe_w < pfit_w)
1663 pipe_w = pfit_w;
1664 if (pipe_h < pfit_h)
1665 pipe_h = pfit_h;
1666
15126882
MR		 1667 if (WARN_ON(!pfit_w || !pfit_h))
1668 return pixel_rate;
1669
801bcfff
PZ		 1670 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1671 pfit_w * pfit_h);
1672 }
1673
1674 return pixel_rate;
1675}
1676
37126462 1677/* latency must be in 0.1us units. */
ac484963 1678static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1679{
1680 uint64_t ret;
1681
3312ba65
VS		 1682 if (WARN(latency == 0, "Latency value missing\n"))
1683 return UINT_MAX;
1684
ac484963 1685 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1686 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1687
1688 return ret;
1689}
1690
37126462 1691/* latency must be in 0.1us units. */
23297044 1692static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1693 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1694 uint32_t latency)
1695{
1696 uint32_t ret;
1697
3312ba65
VS		 1698 if (WARN(latency == 0, "Latency value missing\n"))
1699 return UINT_MAX;
15126882
MR		 1700 if (WARN_ON(!pipe_htotal))
1701 return UINT_MAX;
3312ba65 1702
801bcfff 1703 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1704 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1705 ret = DIV_ROUND_UP(ret, 64) + 2;
1706 return ret;
1707}
1708
23297044 1709static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1710 uint8_t cpp)
cca32e9a 1711{
15126882
MR		 1712 /*
1713 * Neither of these should be possible since this function shouldn't be
1714 * called if the CRTC is off or the plane is invisible. But let's be
1715 * extra paranoid to avoid a potential divide-by-zero if we screw up
1716 * elsewhere in the driver.
1717 */
ac484963 1718 if (WARN_ON(!cpp))
15126882
MR		 1719 return 0;
1720 if (WARN_ON(!horiz_pixels))
1721 return 0;
1722
ac484963 1723 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1724}
1725
820c1980 1726struct ilk_wm_maximums {
cca32e9a
PZ		 1727 uint16_t pri;
1728 uint16_t spr;
1729 uint16_t cur;
1730 uint16_t fbc;
1731};
1732
37126462
VS		 1733/*
1734 * For both WM_PIPE and WM_LP.
1735 * mem_value must be in 0.1us units.
1736 */
7221fc33 1737static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1738 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1739 uint32_t mem_value,
1740 bool is_lp)
801bcfff 1741{
ac484963
VS		 1742 int cpp = pstate->base.fb ?
1743 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1744 uint32_t method1, method2;
1745
7221fc33 1746 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1747 return 0;
1748
ac484963 1749 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1750
1751 if (!is_lp)
1752 return method1;
1753
7221fc33
MR		 1754 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1755 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1756 drm_rect_width(&pstate->dst),
ac484963 1757 cpp, mem_value);
cca32e9a
PZ		 1758
1759 return min(method1, method2);
801bcfff
PZ		 1760}
1761
37126462
VS		 1762/*
1763 * For both WM_PIPE and WM_LP.
1764 * mem_value must be in 0.1us units.
1765 */
7221fc33 1766static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1767 const struct intel_plane_state *pstate,
801bcfff
PZ		 1768 uint32_t mem_value)
1769{
ac484963
VS		 1770 int cpp = pstate->base.fb ?
1771 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1772 uint32_t method1, method2;
1773
7221fc33 1774 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1775 return 0;
1776
ac484963 1777 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1778 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1779 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1780 drm_rect_width(&pstate->dst),
ac484963 1781 cpp, mem_value);
801bcfff
PZ		 1782 return min(method1, method2);
1783}
1784
37126462
VS		 1785/*
1786 * For both WM_PIPE and WM_LP.
1787 * mem_value must be in 0.1us units.
1788 */
7221fc33 1789static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1790 const struct intel_plane_state *pstate,
801bcfff
PZ		 1791 uint32_t mem_value)
1792{
b2435692
MR		 1793 /*
1794 * We treat the cursor plane as always-on for the purposes of watermark
1795 * calculation. Until we have two-stage watermark programming merged,
1796 * this is necessary to avoid flickering.
1797 */
1798 int cpp = 4;
1799 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1800
b2435692 1801 if (!cstate->base.active)
801bcfff
PZ		 1802 return 0;
1803
7221fc33
MR		 1804 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1805 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1806 width, cpp, mem_value);
801bcfff
PZ		 1807}
1808
cca32e9a 1809/* Only for WM_LP. */
7221fc33 1810static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1811 const struct intel_plane_state *pstate,
1fda9882 1812 uint32_t pri_val)
cca32e9a 1813{
ac484963
VS		 1814 int cpp = pstate->base.fb ?
1815 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1816
7221fc33 1817 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1818 return 0;
1819
ac484963 1820 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1821}
1822
158ae64f
VS		 1823static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1824{
416f4727
VS		 1825 if (INTEL_INFO(dev)->gen >= 8)
1826 return 3072;
1827 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1828 return 768;
1829 else
1830 return 512;
1831}
1832
4e975081
VS		 1833static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1834 int level, bool is_sprite)
1835{
1836 if (INTEL_INFO(dev)->gen >= 8)
1837 /* BDW primary/sprite plane watermarks */
1838 return level == 0 ? 255 : 2047;
1839 else if (INTEL_INFO(dev)->gen >= 7)
1840 /* IVB/HSW primary/sprite plane watermarks */
1841 return level == 0 ? 127 : 1023;
1842 else if (!is_sprite)
1843 /* ILK/SNB primary plane watermarks */
1844 return level == 0 ? 127 : 511;
1845 else
1846 /* ILK/SNB sprite plane watermarks */
1847 return level == 0 ? 63 : 255;
1848}
1849
1850static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1851 int level)
1852{
1853 if (INTEL_INFO(dev)->gen >= 7)
1854 return level == 0 ? 63 : 255;
1855 else
1856 return level == 0 ? 31 : 63;
1857}
1858
1859static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1860{
1861 if (INTEL_INFO(dev)->gen >= 8)
1862 return 31;
1863 else
1864 return 15;
1865}
1866
158ae64f
VS		 1867/* Calculate the maximum primary/sprite plane watermark */
1868static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1869 int level,
240264f4 1870 const struct intel_wm_config *config,
158ae64f
VS		 1871 enum intel_ddb_partitioning ddb_partitioning,
1872 bool is_sprite)
1873{
1874 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1875
1876 /* if sprites aren't enabled, sprites get nothing */
240264f4 1877 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1878 return 0;
1879
1880 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1881 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1882 fifo_size /= INTEL_INFO(dev)->num_pipes;
1883
1884 /*
1885 * For some reason the non self refresh
1886 * FIFO size is only half of the self
1887 * refresh FIFO size on ILK/SNB.
1888 */
1889 if (INTEL_INFO(dev)->gen <= 6)
1890 fifo_size /= 2;
1891 }
1892
240264f4 1893 if (config->sprites_enabled) {
158ae64f
VS		 1894 /* level 0 is always calculated with 1:1 split */
1895 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1896 if (is_sprite)
1897 fifo_size *= 5;
1898 fifo_size /= 6;
1899 } else {
1900 fifo_size /= 2;
1901 }
1902 }
1903
1904 /* clamp to max that the registers can hold */
4e975081 1905 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1906}
1907
1908/* Calculate the maximum cursor plane watermark */
1909static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1910 int level,
1911 const struct intel_wm_config *config)
158ae64f
VS		 1912{
1913 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1914 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1915 return 64;
1916
1917 /* otherwise just report max that registers can hold */
4e975081 1918 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1919}
1920
d34ff9c6 1921static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1922 int level,
1923 const struct intel_wm_config *config,
1924 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1925 struct ilk_wm_maximums *max)
158ae64f 1926{
240264f4
VS		 1927 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1928 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1929 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1930 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1931}
1932
a3cb4048
VS		 1933static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1934 int level,
1935 struct ilk_wm_maximums *max)
1936{
1937 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1938 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1939 max->cur = ilk_cursor_wm_reg_max(dev, level);
1940 max->fbc = ilk_fbc_wm_reg_max(dev);
1941}
1942
d9395655 1943static bool ilk_validate_wm_level(int level,
820c1980 1944 const struct ilk_wm_maximums *max,
d9395655 1945 struct intel_wm_level *result)
a9786a11
VS		 1946{
1947 bool ret;
1948
1949 /* already determined to be invalid? */
1950 if (!result->enable)
1951 return false;
1952
1953 result->enable = result->pri_val <= max->pri &&
1954 result->spr_val <= max->spr &&
1955 result->cur_val <= max->cur;
1956
1957 ret = result->enable;
1958
1959 /*
1960 * HACK until we can pre-compute everything,
1961 * and thus fail gracefully if LP0 watermarks
1962 * are exceeded...
1963 */
1964 if (level == 0 && !result->enable) {
1965 if (result->pri_val > max->pri)
1966 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1967 level, result->pri_val, max->pri);
1968 if (result->spr_val > max->spr)
1969 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1970 level, result->spr_val, max->spr);
1971 if (result->cur_val > max->cur)
1972 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1973 level, result->cur_val, max->cur);
1974
1975 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1976 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1977 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1978 result->enable = true;
1979 }
1980
a9786a11
VS		 1981 return ret;
1982}
1983
d34ff9c6 1984static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1985 const struct intel_crtc *intel_crtc,
6f5ddd17 1986 int level,
7221fc33 1987 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1988 struct intel_plane_state *pristate,
1989 struct intel_plane_state *sprstate,
1990 struct intel_plane_state *curstate,
1fd527cc 1991 struct intel_wm_level *result)
6f5ddd17
VS		 1992{
1993 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1994 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1995 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1996
1997 /* WM1+ latency values stored in 0.5us units */
1998 if (level > 0) {
1999 pri_latency *= 5;
2000 spr_latency *= 5;
2001 cur_latency *= 5;
2002 }
2003
e3bddded
ML		 2004 if (pristate) {
2005 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2006 pri_latency, level);
2007 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2008 }
2009
2010 if (sprstate)
2011 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2012
2013 if (curstate)
2014 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2015
6f5ddd17
VS		 2016 result->enable = true;
2017}
2018
801bcfff 2019static uint32_t
532f7a7f 2020hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2021{
532f7a7f
VS		 2022 const struct intel_atomic_state *intel_state =
2023 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2024 const struct drm_display_mode *adjusted_mode =
2025 &cstate->base.adjusted_mode;
85a02deb 2026 u32 linetime, ips_linetime;
1f8eeabf 2027
ee91a159
MR		 2028 if (!cstate->base.active)
2029 return 0;
2030 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2031 return 0;
532f7a7f 2032 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2033 return 0;
1011d8c4 2034
1f8eeabf
ED		 2035 /* The WM are computed with base on how long it takes to fill a single
2036 * row at the given clock rate, multiplied by 8.
2037 * */
124abe07
VS		 2038 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2039 adjusted_mode->crtc_clock);
2040 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2041 intel_state->cdclk);
1f8eeabf 2042
801bcfff
PZ		 2043 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2044 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2045}
2046
2af30a5c 2047static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2048{
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050
2af30a5c
PB		 2051 if (IS_GEN9(dev)) {
2052 uint32_t val;
4f947386 2053 int ret, i;
367294be 2054 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2055
2056 /* read the first set of memory latencies[0:3] */
2057 val = 0; /* data0 to be programmed to 0 for first set */
2058 mutex_lock(&dev_priv->rps.hw_lock);
2059 ret = sandybridge_pcode_read(dev_priv,
2060 GEN9_PCODE_READ_MEM_LATENCY,
2061 &val);
2062 mutex_unlock(&dev_priv->rps.hw_lock);
2063
2064 if (ret) {
2065 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2066 return;
2067 }
2068
2069 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2070 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK;
2072 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2073 GEN9_MEM_LATENCY_LEVEL_MASK;
2074 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2075 GEN9_MEM_LATENCY_LEVEL_MASK;
2076
2077 /* read the second set of memory latencies[4:7] */
2078 val = 1; /* data0 to be programmed to 1 for second set */
2079 mutex_lock(&dev_priv->rps.hw_lock);
2080 ret = sandybridge_pcode_read(dev_priv,
2081 GEN9_PCODE_READ_MEM_LATENCY,
2082 &val);
2083 mutex_unlock(&dev_priv->rps.hw_lock);
2084 if (ret) {
2085 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2086 return;
2087 }
2088
2089 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2090 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2091 GEN9_MEM_LATENCY_LEVEL_MASK;
2092 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2093 GEN9_MEM_LATENCY_LEVEL_MASK;
2094 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2095 GEN9_MEM_LATENCY_LEVEL_MASK;
2096
367294be 2097 /*
6f97235b
DL		 2098 * WaWmMemoryReadLatency:skl
2099 *
367294be
VK		 2100 * punit doesn't take into account the read latency so we need
2101 * to add 2us to the various latency levels we retrieve from
2102 * the punit.
2103 * - W0 is a bit special in that it's the only level that
2104 * can't be disabled if we want to have display working, so
2105 * we always add 2us there.
2106 * - For levels >=1, punit returns 0us latency when they are
2107 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2108 *
2109 * Additionally, if a level n (n > 1) has a 0us latency, all
2110 * levels m (m >= n) need to be disabled. We make sure to
2111 * sanitize the values out of the punit to satisfy this
2112 * requirement.
367294be
VK		 2113 */
2114 wm[0] += 2;
2115 for (level = 1; level <= max_level; level++)
2116 if (wm[level] != 0)
2117 wm[level] += 2;
4f947386
VK		 2118 else {
2119 for (i = level + 1; i <= max_level; i++)
2120 wm[i] = 0;
367294be 2121
4f947386
VK		 2122 break;
2123 }
2af30a5c 2124 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2125 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2126
2127 wm[0] = (sskpd >> 56) & 0xFF;
2128 if (wm[0] == 0)
2129 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2130 wm[1] = (sskpd >> 4) & 0xFF;
2131 wm[2] = (sskpd >> 12) & 0xFF;
2132 wm[3] = (sskpd >> 20) & 0x1FF;
2133 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2134 } else if (INTEL_INFO(dev)->gen >= 6) {
2135 uint32_t sskpd = I915_READ(MCH_SSKPD);
2136
2137 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2138 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2139 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2140 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2141 } else if (INTEL_INFO(dev)->gen >= 5) {
2142 uint32_t mltr = I915_READ(MLTR_ILK);
2143
2144 /* ILK primary LP0 latency is 700 ns */
2145 wm[0] = 7;
2146 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2147 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2148 }
2149}
2150
53615a5e
VS		 2151static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2152{
2153 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2154 if (IS_GEN5(dev))
53615a5e
VS		 2155 wm[0] = 13;
2156}
2157
2158static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2159{
2160 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2161 if (IS_GEN5(dev))
53615a5e
VS		 2162 wm[0] = 13;
2163
2164 /* WaDoubleCursorLP3Latency:ivb */
2165 if (IS_IVYBRIDGE(dev))
2166 wm[3] *= 2;
2167}
2168
546c81fd 2169int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2170{
26ec971e 2171 /* how many WM levels are we expecting */
b6e742f6 2172 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2173 return 7;
2174 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2175 return 4;
26ec971e 2176 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2177 return 3;
26ec971e 2178 else
ad0d6dc4
VS		 2179 return 2;
2180}
7526ed79 2181
ad0d6dc4
VS		 2182static void intel_print_wm_latency(struct drm_device *dev,
2183 const char *name,
2af30a5c 2184 const uint16_t wm[8])
ad0d6dc4
VS		 2185{
2186 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2187
2188 for (level = 0; level <= max_level; level++) {
2189 unsigned int latency = wm[level];
2190
2191 if (latency == 0) {
2192 DRM_ERROR("%s WM%d latency not provided\n",
2193 name, level);
2194 continue;
2195 }
2196
2af30a5c
PB		 2197 /*
2198 * - latencies are in us on gen9.
2199 * - before then, WM1+ latency values are in 0.5us units
2200 */
2201 if (IS_GEN9(dev))
2202 latency *= 10;
2203 else if (level > 0)
26ec971e
VS		 2204 latency *= 5;
2205
2206 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2207 name, level, wm[level],
2208 latency / 10, latency % 10);
2209 }
2210}
2211
e95a2f75
VS		 2212static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2213 uint16_t wm[5], uint16_t min)
2214{
2215 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2216
2217 if (wm[0] >= min)
2218 return false;
2219
2220 wm[0] = max(wm[0], min);
2221 for (level = 1; level <= max_level; level++)
2222 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2223
2224 return true;
2225}
2226
2227static void snb_wm_latency_quirk(struct drm_device *dev)
2228{
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 bool changed;
2231
2232 /*
2233 * The BIOS provided WM memory latency values are often
2234 * inadequate for high resolution displays. Adjust them.
2235 */
2236 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2237 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2238 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2239
2240 if (!changed)
2241 return;
2242
2243 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2244 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2245 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2246 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2247}
2248
fa50ad61 2249static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2250{
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252
2253 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2254
2255 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2256 sizeof(dev_priv->wm.pri_latency));
2257 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2258 sizeof(dev_priv->wm.pri_latency));
2259
2260 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2261 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2262
2263 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2264 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2265 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2266
2267 if (IS_GEN6(dev))
2268 snb_wm_latency_quirk(dev);
53615a5e
VS		 2269}
2270
2af30a5c
PB		 2271static void skl_setup_wm_latency(struct drm_device *dev)
2272{
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274
2275 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2276 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2277}
2278
ed4a6a7c
MR		 2279static bool ilk_validate_pipe_wm(struct drm_device *dev,
2280 struct intel_pipe_wm *pipe_wm)
2281{
2282 /* LP0 watermark maximums depend on this pipe alone */
2283 const struct intel_wm_config config = {
2284 .num_pipes_active = 1,
2285 .sprites_enabled = pipe_wm->sprites_enabled,
2286 .sprites_scaled = pipe_wm->sprites_scaled,
2287 };
2288 struct ilk_wm_maximums max;
2289
2290 /* LP0 watermarks always use 1/2 DDB partitioning */
2291 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2292
2293 /* At least LP0 must be valid */
2294 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2295 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2296 return false;
2297 }
2298
2299 return true;
2300}
2301
0b2ae6d7 2302/* Compute new watermarks for the pipe */
e3bddded 2303static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2304{
e3bddded
ML		 2305 struct drm_atomic_state *state = cstate->base.state;
2306 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2307 struct intel_pipe_wm *pipe_wm;
e3bddded 2308 struct drm_device *dev = state->dev;
d34ff9c6 2309 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2310 struct intel_plane *intel_plane;
86c8bbbe 2311 struct intel_plane_state *pristate = NULL;
43d59eda 2312 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2313 struct intel_plane_state *curstate = NULL;
d81f04c5 2314 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2315 struct ilk_wm_maximums max;
0b2ae6d7 2316
e8f1f02e 2317 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2318
43d59eda 2319 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2320 struct intel_plane_state *ps;
2321
2322 ps = intel_atomic_get_existing_plane_state(state,
2323 intel_plane);
2324 if (!ps)
2325 continue;
86c8bbbe
MR		 2326
2327 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2328 pristate = ps;
86c8bbbe 2329 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2330 sprstate = ps;
86c8bbbe 2331 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2332 curstate = ps;
43d59eda
MR		 2333 }
2334
ed4a6a7c 2335 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2336 if (sprstate) {
2337 pipe_wm->sprites_enabled = sprstate->visible;
2338 pipe_wm->sprites_scaled = sprstate->visible &&
2339 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2340 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2341 }
2342
d81f04c5
ML		 2343 usable_level = max_level;
2344
7b39a0b7 2345 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2346 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2347 usable_level = 1;
7b39a0b7
VS		 2348
2349 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2350 if (pipe_wm->sprites_scaled)
d81f04c5 2351 usable_level = 0;
7b39a0b7 2352
86c8bbbe 2353 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2354 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2355
2356 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2357 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2358
a42a5719 2359 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2360 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2361
ed4a6a7c 2362 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2363 return -EINVAL;
a3cb4048
VS		 2364
2365 ilk_compute_wm_reg_maximums(dev, 1, &max);
2366
2367 for (level = 1; level <= max_level; level++) {
71f0a626 2368 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2369
86c8bbbe 2370 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2371 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2372
2373 /*
2374 * Disable any watermark level that exceeds the
2375 * register maximums since such watermarks are
2376 * always invalid.
2377 */
71f0a626
ML		 2378 if (level > usable_level)
2379 continue;
2380
2381 if (ilk_validate_wm_level(level, &max, wm))
2382 pipe_wm->wm[level] = *wm;
2383 else
d81f04c5 2384 usable_level = level;
a3cb4048
VS		 2385 }
2386
86c8bbbe 2387 return 0;
0b2ae6d7
VS		 2388}
2389
ed4a6a7c
MR		 2390/*
2391 * Build a set of 'intermediate' watermark values that satisfy both the old
2392 * state and the new state. These can be programmed to the hardware
2393 * immediately.
2394 */
2395static int ilk_compute_intermediate_wm(struct drm_device *dev,
2396 struct intel_crtc *intel_crtc,
2397 struct intel_crtc_state *newstate)
2398{
e8f1f02e 2399 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2400 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2401 int level, max_level = ilk_wm_max_level(dev);
2402
2403 /*
2404 * Start with the final, target watermarks, then combine with the
2405 * currently active watermarks to get values that are safe both before
2406 * and after the vblank.
2407 */
e8f1f02e 2408 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2409 a->pipe_enabled |= b->pipe_enabled;
2410 a->sprites_enabled |= b->sprites_enabled;
2411 a->sprites_scaled |= b->sprites_scaled;
2412
2413 for (level = 0; level <= max_level; level++) {
2414 struct intel_wm_level *a_wm = &a->wm[level];
2415 const struct intel_wm_level *b_wm = &b->wm[level];
2416
2417 a_wm->enable &= b_wm->enable;
2418 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2419 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2420 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2421 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2422 }
2423
2424 /*
2425 * We need to make sure that these merged watermark values are
2426 * actually a valid configuration themselves. If they're not,
2427 * there's no safe way to transition from the old state to
2428 * the new state, so we need to fail the atomic transaction.
2429 */
2430 if (!ilk_validate_pipe_wm(dev, a))
2431 return -EINVAL;
2432
2433 /*
2434 * If our intermediate WM are identical to the final WM, then we can
2435 * omit the post-vblank programming; only update if it's different.
2436 */
e8f1f02e 2437 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2438 newstate->wm.need_postvbl_update = false;
2439
2440 return 0;
2441}
2442
0b2ae6d7
VS		 2443/*
2444 * Merge the watermarks from all active pipes for a specific level.
2445 */
2446static void ilk_merge_wm_level(struct drm_device *dev,
2447 int level,
2448 struct intel_wm_level *ret_wm)
2449{
2450 const struct intel_crtc *intel_crtc;
2451
d52fea5b
VS		 2452 ret_wm->enable = true;
2453
d3fcc808 2454 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2455 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2456 const struct intel_wm_level *wm = &active->wm[level];
2457
2458 if (!active->pipe_enabled)
2459 continue;
0b2ae6d7 2460
d52fea5b
VS		 2461 /*
2462 * The watermark values may have been used in the past,
2463 * so we must maintain them in the registers for some
2464 * time even if the level is now disabled.
2465 */
0b2ae6d7 2466 if (!wm->enable)
d52fea5b 2467 ret_wm->enable = false;
0b2ae6d7
VS		 2468
2469 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2470 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2471 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2472 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2473 }
0b2ae6d7
VS		 2474}
2475
2476/*
2477 * Merge all low power watermarks for all active pipes.
2478 */
2479static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2480 const struct intel_wm_config *config,
820c1980 2481 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2482 struct intel_pipe_wm *merged)
2483{
7733b49b 2484 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2485 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2486 int last_enabled_level = max_level;
0b2ae6d7 2487
0ba22e26
VS		 2488 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2489 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2490 config->num_pipes_active > 1)
1204d5ba 2491 last_enabled_level = 0;
0ba22e26 2492
6c8b6c28
VS		 2493 /* ILK: FBC WM must be disabled always */
2494 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2495
2496 /* merge each WM1+ level */
2497 for (level = 1; level <= max_level; level++) {
2498 struct intel_wm_level *wm = &merged->wm[level];
2499
2500 ilk_merge_wm_level(dev, level, wm);
2501
d52fea5b
VS		 2502 if (level > last_enabled_level)
2503 wm->enable = false;
2504 else if (!ilk_validate_wm_level(level, max, wm))
2505 /* make sure all following levels get disabled */
2506 last_enabled_level = level - 1;
0b2ae6d7
VS		 2507
2508 /*
2509 * The spec says it is preferred to disable
2510 * FBC WMs instead of disabling a WM level.
2511 */
2512 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2513 if (wm->enable)
2514 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2515 wm->fbc_val = 0;
2516 }
2517 }
6c8b6c28
VS		 2518
2519 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2520 /*
2521 * FIXME this is racy. FBC might get enabled later.
2522 * What we should check here is whether FBC can be
2523 * enabled sometime later.
2524 */
7733b49b 2525 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2526 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2527 for (level = 2; level <= max_level; level++) {
2528 struct intel_wm_level *wm = &merged->wm[level];
2529
2530 wm->enable = false;
2531 }
2532 }
0b2ae6d7
VS		 2533}
2534
b380ca3c
VS		 2535static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2536{
2537 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2538 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2539}
2540
a68d68ee
VS		 2541/* The value we need to program into the WM_LPx latency field */
2542static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2543{
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545
a42a5719 2546 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2547 return 2 * level;
2548 else
2549 return dev_priv->wm.pri_latency[level];
2550}
2551
820c1980 2552static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2553 const struct intel_pipe_wm *merged,
609cedef 2554 enum intel_ddb_partitioning partitioning,
820c1980 2555 struct ilk_wm_values *results)
801bcfff 2556{
0b2ae6d7
VS		 2557 struct intel_crtc *intel_crtc;
2558 int level, wm_lp;
cca32e9a 2559
0362c781 2560 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2561 results->partitioning = partitioning;
cca32e9a 2562
0b2ae6d7 2563 /* LP1+ register values */
cca32e9a 2564 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2565 const struct intel_wm_level *r;
801bcfff 2566
b380ca3c 2567 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2568
0362c781 2569 r = &merged->wm[level];
cca32e9a 2570
d52fea5b
VS		 2571 /*
2572 * Maintain the watermark values even if the level is
2573 * disabled. Doing otherwise could cause underruns.
2574 */
2575 results->wm_lp[wm_lp - 1] =
a68d68ee 2576 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2577 (r->pri_val << WM1_LP_SR_SHIFT) |
2578 r->cur_val;
2579
d52fea5b
VS		 2580 if (r->enable)
2581 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2582
416f4727
VS		 2583 if (INTEL_INFO(dev)->gen >= 8)
2584 results->wm_lp[wm_lp - 1] |=
2585 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2586 else
2587 results->wm_lp[wm_lp - 1] |=
2588 r->fbc_val << WM1_LP_FBC_SHIFT;
2589
d52fea5b
VS		 2590 /*
2591 * Always set WM1S_LP_EN when spr_val != 0, even if the
2592 * level is disabled. Doing otherwise could cause underruns.
2593 */
6cef2b8a
VS		 2594 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2595 WARN_ON(wm_lp != 1);
2596 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2597 } else
2598 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2599 }
801bcfff 2600
0b2ae6d7 2601 /* LP0 register values */
d3fcc808 2602 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2603 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2604 const struct intel_wm_level *r =
2605 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2606
2607 if (WARN_ON(!r->enable))
2608 continue;
2609
ed4a6a7c 2610 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2611
0b2ae6d7
VS		 2612 results->wm_pipe[pipe] =
2613 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2614 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2615 r->cur_val;
801bcfff
PZ		 2616 }
2617}
2618
861f3389
PZ		 2619/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2620 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2621static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2622 struct intel_pipe_wm *r1,
2623 struct intel_pipe_wm *r2)
861f3389 2624{
198a1e9b
VS		 2625 int level, max_level = ilk_wm_max_level(dev);
2626 int level1 = 0, level2 = 0;
861f3389 2627
198a1e9b
VS		 2628 for (level = 1; level <= max_level; level++) {
2629 if (r1->wm[level].enable)
2630 level1 = level;
2631 if (r2->wm[level].enable)
2632 level2 = level;
861f3389
PZ		 2633 }
2634
198a1e9b
VS		 2635 if (level1 == level2) {
2636 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2637 return r2;
2638 else
2639 return r1;
198a1e9b 2640 } else if (level1 > level2) {
861f3389
PZ		 2641 return r1;
2642 } else {
2643 return r2;
2644 }
2645}
2646
49a687c4
VS		 2647/* dirty bits used to track which watermarks need changes */
2648#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2649#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2650#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2651#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2652#define WM_DIRTY_FBC (1 << 24)
2653#define WM_DIRTY_DDB (1 << 25)
2654
055e393f 2655static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2656 const struct ilk_wm_values *old,
2657 const struct ilk_wm_values *new)
49a687c4
VS		 2658{
2659 unsigned int dirty = 0;
2660 enum pipe pipe;
2661 int wm_lp;
2662
055e393f 2663 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2664 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2665 dirty |= WM_DIRTY_LINETIME(pipe);
2666 /* Must disable LP1+ watermarks too */
2667 dirty |= WM_DIRTY_LP_ALL;
2668 }
2669
2670 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2671 dirty |= WM_DIRTY_PIPE(pipe);
2672 /* Must disable LP1+ watermarks too */
2673 dirty |= WM_DIRTY_LP_ALL;
2674 }
2675 }
2676
2677 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2678 dirty |= WM_DIRTY_FBC;
2679 /* Must disable LP1+ watermarks too */
2680 dirty |= WM_DIRTY_LP_ALL;
2681 }
2682
2683 if (old->partitioning != new->partitioning) {
2684 dirty |= WM_DIRTY_DDB;
2685 /* Must disable LP1+ watermarks too */
2686 dirty |= WM_DIRTY_LP_ALL;
2687 }
2688
2689 /* LP1+ watermarks already deemed dirty, no need to continue */
2690 if (dirty & WM_DIRTY_LP_ALL)
2691 return dirty;
2692
2693 /* Find the lowest numbered LP1+ watermark in need of an update... */
2694 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2695 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2696 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2697 break;
2698 }
2699
2700 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2701 for (; wm_lp <= 3; wm_lp++)
2702 dirty |= WM_DIRTY_LP(wm_lp);
2703
2704 return dirty;
2705}
2706
8553c18e
VS		 2707static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2708 unsigned int dirty)
801bcfff 2709{
820c1980 2710 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2711 bool changed = false;
801bcfff 2712
facd619b
VS		 2713 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2714 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2716 changed = true;
facd619b
VS		 2717 }
2718 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2719 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2721 changed = true;
facd619b
VS		 2722 }
2723 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2724 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2725 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2726 changed = true;
facd619b 2727 }
801bcfff 2728
facd619b
VS		 2729 /*
2730 * Don't touch WM1S_LP_EN here.
2731 * Doing so could cause underruns.
2732 */
6cef2b8a 2733
8553c18e
VS		 2734 return changed;
2735}
2736
2737/*
2738 * The spec says we shouldn't write when we don't need, because every write
2739 * causes WMs to be re-evaluated, expending some power.
2740 */
820c1980
ID		 2741static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2742 struct ilk_wm_values *results)
8553c18e
VS		 2743{
2744 struct drm_device *dev = dev_priv->dev;
820c1980 2745 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2746 unsigned int dirty;
2747 uint32_t val;
2748
055e393f 2749 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2750 if (!dirty)
2751 return;
2752
2753 _ilk_disable_lp_wm(dev_priv, dirty);
2754
49a687c4 2755 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2756 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2757 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2758 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2759 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2760 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2761
49a687c4 2762 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2763 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2764 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2765 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2766 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2767 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2768
49a687c4 2769 if (dirty & WM_DIRTY_DDB) {
a42a5719 2770 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2771 val = I915_READ(WM_MISC);
2772 if (results->partitioning == INTEL_DDB_PART_1_2)
2773 val &= ~WM_MISC_DATA_PARTITION_5_6;
2774 else
2775 val |= WM_MISC_DATA_PARTITION_5_6;
2776 I915_WRITE(WM_MISC, val);
2777 } else {
2778 val = I915_READ(DISP_ARB_CTL2);
2779 if (results->partitioning == INTEL_DDB_PART_1_2)
2780 val &= ~DISP_DATA_PARTITION_5_6;
2781 else
2782 val |= DISP_DATA_PARTITION_5_6;
2783 I915_WRITE(DISP_ARB_CTL2, val);
2784 }
1011d8c4
PZ		 2785 }
2786
49a687c4 2787 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2788 val = I915_READ(DISP_ARB_CTL);
2789 if (results->enable_fbc_wm)
2790 val &= ~DISP_FBC_WM_DIS;
2791 else
2792 val |= DISP_FBC_WM_DIS;
2793 I915_WRITE(DISP_ARB_CTL, val);
2794 }
2795
954911eb
ID		 2796 if (dirty & WM_DIRTY_LP(1) &&
2797 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2798 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2799
2800 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2801 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2802 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2803 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2804 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2805 }
801bcfff 2806
facd619b 2807 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2808 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2809 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2810 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2811 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2812 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2813
2814 dev_priv->wm.hw = *results;
801bcfff
PZ		 2815}
2816
ed4a6a7c 2817bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2818{
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820
2821 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2822}
2823
b9cec075
DL		 2824/*
2825 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2826 * different active planes.
2827 */
2828
2829#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2830#define BXT_DDB_SIZE 512
b9cec075 2831
024c9045
MR		 2832/*
2833 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2834 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2835 * other universal planes are in indices 1..n. Note that this may leave unused
2836 * indices between the top "sprite" plane and the cursor.
2837 */
2838static int
2839skl_wm_plane_id(const struct intel_plane *plane)
2840{
2841 switch (plane->base.type) {
2842 case DRM_PLANE_TYPE_PRIMARY:
2843 return 0;
2844 case DRM_PLANE_TYPE_CURSOR:
2845 return PLANE_CURSOR;
2846 case DRM_PLANE_TYPE_OVERLAY:
2847 return plane->plane + 1;
2848 default:
2849 MISSING_CASE(plane->base.type);
2850 return plane->plane;
2851 }
2852}
2853
b9cec075
DL		 2854static void
2855skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2856 const struct intel_crtc_state *cstate,
c107acfe
MR		 2857 struct skl_ddb_entry *alloc, /* out */
2858 int *num_active /* out */)
b9cec075 2859{
c107acfe
MR		 2860 struct drm_atomic_state *state = cstate->base.state;
2861 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2862 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 2863 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2864 unsigned int pipe_size, ddb_size;
2865 int nth_active_pipe;
c107acfe
MR		 2866 int pipe = to_intel_crtc(for_crtc)->pipe;
2867
a6d3460e 2868 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 2869 alloc->start = 0;
2870 alloc->end = 0;
a6d3460e 2871 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 2872 return;
2873 }
2874
a6d3460e
MR		 2875 if (intel_state->active_pipe_changes)
2876 *num_active = hweight32(intel_state->active_crtcs);
2877 else
2878 *num_active = hweight32(dev_priv->active_crtcs);
2879
43d735a6
DL		 2880 if (IS_BROXTON(dev))
2881 ddb_size = BXT_DDB_SIZE;
2882 else
2883 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2884
2885 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2886
c107acfe 2887 /*
a6d3460e
MR		 2888 * If the state doesn't change the active CRTC's, then there's
2889 * no need to recalculate; the existing pipe allocation limits
2890 * should remain unchanged. Note that we're safe from racing
2891 * commits since any racing commit that changes the active CRTC
2892 * list would need to grab _all_ crtc locks, including the one
2893 * we currently hold.
c107acfe 2894 */
a6d3460e
MR		 2895 if (!intel_state->active_pipe_changes) {
2896 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2897 return;
c107acfe 2898 }
a6d3460e
MR		 2899
2900 nth_active_pipe = hweight32(intel_state->active_crtcs &
2901 (drm_crtc_mask(for_crtc) - 1));
2902 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2903 alloc->start = nth_active_pipe * ddb_size / *num_active;
2904 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2905}
2906
c107acfe 2907static unsigned int skl_cursor_allocation(int num_active)
b9cec075 2908{
c107acfe 2909 if (num_active == 1)
b9cec075
DL		 2910 return 32;
2911
2912 return 8;
2913}
2914
a269c583
DL		 2915static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2916{
2917 entry->start = reg & 0x3ff;
2918 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2919 if (entry->end)
2920 entry->end += 1;
a269c583
DL		 2921}
2922
08db6652
DL		 2923void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2924 struct skl_ddb_allocation *ddb /* out */)
a269c583 2925{
a269c583
DL		 2926 enum pipe pipe;
2927 int plane;
2928 u32 val;
2929
b10f1b20
ML		 2930 memset(ddb, 0, sizeof(*ddb));
2931
a269c583 2932 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2933 enum intel_display_power_domain power_domain;
2934
2935 power_domain = POWER_DOMAIN_PIPE(pipe);
2936 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2937 continue;
2938
dd740780 2939 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2940 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2941 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2942 val);
2943 }
2944
2945 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2946 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2947 val);
4d800030
ID		 2948
2949 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2950 }
2951}
2952
9c2f7a9d
KM		 2953/*
2954 * Determines the downscale amount of a plane for the purposes of watermark calculations.
2955 * The bspec defines downscale amount as:
2956 *
2957 * """
2958 * Horizontal down scale amount = maximum[1, Horizontal source size /
2959 * Horizontal destination size]
2960 * Vertical down scale amount = maximum[1, Vertical source size /
2961 * Vertical destination size]
2962 * Total down scale amount = Horizontal down scale amount *
2963 * Vertical down scale amount
2964 * """
2965 *
2966 * Return value is provided in 16.16 fixed point form to retain fractional part.
2967 * Caller should take care of dividing & rounding off the value.
2968 */
2969static uint32_t
2970skl_plane_downscale_amount(const struct intel_plane_state *pstate)
2971{
2972 uint32_t downscale_h, downscale_w;
2973 uint32_t src_w, src_h, dst_w, dst_h;
2974
2975 if (WARN_ON(!pstate->visible))
2976 return DRM_PLANE_HELPER_NO_SCALING;
2977
2978 /* n.b., src is 16.16 fixed point, dst is whole integer */
2979 src_w = drm_rect_width(&pstate->src);
2980 src_h = drm_rect_height(&pstate->src);
2981 dst_w = drm_rect_width(&pstate->dst);
2982 dst_h = drm_rect_height(&pstate->dst);
2983 if (intel_rotation_90_or_270(pstate->base.rotation))
2984 swap(dst_w, dst_h);
2985
2986 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
2987 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
2988
2989 /* Provide result in 16.16 fixed point */
2990 return (uint64_t)downscale_w * downscale_h >> 16;
2991}
2992
b9cec075 2993static unsigned int
024c9045
MR		 2994skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2995 const struct drm_plane_state *pstate,
2996 int y)
b9cec075 2997{
a280f7dd 2998 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 2999 struct drm_framebuffer *fb = pstate->fb;
a280f7dd 3000 uint32_t width = 0, height = 0;
a1de91e5
MR		 3001 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3002
3003 if (!intel_pstate->visible)
3004 return 0;
3005 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3006 return 0;
3007 if (y && format != DRM_FORMAT_NV12)
3008 return 0;
a280f7dd
KM		 3009
3010 width = drm_rect_width(&intel_pstate->src) >> 16;
3011 height = drm_rect_height(&intel_pstate->src) >> 16;
3012
3013 if (intel_rotation_90_or_270(pstate->rotation))
3014 swap(width, height);
2cd601c6
CK		 3015
3016 /* for planar format */
a1de91e5 3017 if (format == DRM_FORMAT_NV12) {
2cd601c6 3018 if (y) /* y-plane data rate */
a280f7dd 3019 return width * height *
a1de91e5 3020 drm_format_plane_cpp(format, 0);
2cd601c6 3021 else /* uv-plane data rate */
a280f7dd 3022 return (width / 2) * (height / 2) *
a1de91e5 3023 drm_format_plane_cpp(format, 1);
2cd601c6
CK		 3024 }
3025
3026 /* for packed formats */
a1de91e5 3027 return width * height * drm_format_plane_cpp(format, 0);
b9cec075
DL		 3028}
3029
3030/*
3031 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3032 * a 8192x4096@32bpp framebuffer:
3033 * 3 * 4096 * 8192 * 4 < 2^32
3034 */
3035static unsigned int
9c74d826 3036skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3037{
9c74d826
MR		 3038 struct drm_crtc_state *cstate = &intel_cstate->base;
3039 struct drm_atomic_state *state = cstate->state;
3040 struct drm_crtc *crtc = cstate->crtc;
3041 struct drm_device *dev = crtc->dev;
3042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3043 const struct drm_plane *plane;
024c9045 3044 const struct intel_plane *intel_plane;
a6d3460e 3045 struct drm_plane_state *pstate;
a1de91e5 3046 unsigned int rate, total_data_rate = 0;
9c74d826 3047 int id;
a6d3460e
MR		 3048 int i;
3049
3050 if (WARN_ON(!state))
3051 return 0;
b9cec075 3052
a1de91e5 3053 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3054 for_each_plane_in_state(state, plane, pstate, i) {
3055 id = skl_wm_plane_id(to_intel_plane(plane));
3056 intel_plane = to_intel_plane(plane);
3057
3058 if (intel_plane->pipe != intel_crtc->pipe)
3059 continue;
3060
3061 /* packed/uv */
3062 rate = skl_plane_relative_data_rate(intel_cstate,
3063 pstate, 0);
3064 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3065
3066 /* y-plane */
3067 rate = skl_plane_relative_data_rate(intel_cstate,
3068 pstate, 1);
3069 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3070 }
024c9045 3071
a1de91e5
MR		 3072 /* Calculate CRTC's total data rate from cached values */
3073 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3074 int id = skl_wm_plane_id(intel_plane);
024c9045 3075
a1de91e5 3076 /* packed/uv */
9c74d826
MR		 3077 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3078 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3079 }
3080
9c74d826
MR		 3081 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3082
b9cec075
DL		 3083 return total_data_rate;
3084}
3085
cbcfd14b
KM		 3086static uint16_t
3087skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3088 const int y)
3089{
3090 struct drm_framebuffer *fb = pstate->fb;
3091 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3092 uint32_t src_w, src_h;
3093 uint32_t min_scanlines = 8;
3094 uint8_t plane_bpp;
3095
3096 if (WARN_ON(!fb))
3097 return 0;
3098
3099 /* For packed formats, no y-plane, return 0 */
3100 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3101 return 0;
3102
3103 /* For Non Y-tile return 8-blocks */
3104 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3105 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3106 return 8;
3107
3108 src_w = drm_rect_width(&intel_pstate->src) >> 16;
3109 src_h = drm_rect_height(&intel_pstate->src) >> 16;
3110
3111 if (intel_rotation_90_or_270(pstate->rotation))
3112 swap(src_w, src_h);
3113
3114 /* Halve UV plane width and height for NV12 */
3115 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3116 src_w /= 2;
3117 src_h /= 2;
3118 }
3119
3120 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3121 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3122 else
3123 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3124
3125 if (intel_rotation_90_or_270(pstate->rotation)) {
3126 switch (plane_bpp) {
3127 case 1:
3128 min_scanlines = 32;
3129 break;
3130 case 2:
3131 min_scanlines = 16;
3132 break;
3133 case 4:
3134 min_scanlines = 8;
3135 break;
3136 case 8:
3137 min_scanlines = 4;
3138 break;
3139 default:
3140 WARN(1, "Unsupported pixel depth %u for rotation",
3141 plane_bpp);
3142 min_scanlines = 32;
3143 }
3144 }
3145
3146 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3147}
3148
c107acfe 3149static int
024c9045 3150skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3151 struct skl_ddb_allocation *ddb /* out */)
3152{
c107acfe 3153 struct drm_atomic_state *state = cstate->base.state;
024c9045 3154 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3155 struct drm_device *dev = crtc->dev;
3156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3157 struct intel_plane *intel_plane;
c107acfe
MR		 3158 struct drm_plane *plane;
3159 struct drm_plane_state *pstate;
b9cec075 3160 enum pipe pipe = intel_crtc->pipe;
34bb56af 3161 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3162 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3163 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3164 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3165 unsigned int total_data_rate;
c107acfe
MR		 3166 int num_active;
3167 int id, i;
b9cec075 3168
a6d3460e
MR		 3169 if (WARN_ON(!state))
3170 return 0;
3171
c107acfe
MR		 3172 if (!cstate->base.active) {
3173 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3174 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3175 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3176 return 0;
3177 }
3178
a6d3460e 3179 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3180 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3181 if (alloc_size == 0) {
3182 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3183 return 0;
b9cec075
DL		 3184 }
3185
c107acfe 3186 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3187 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3188 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3189
3190 alloc_size -= cursor_blocks;
b9cec075 3191
80958155 3192 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3193 for_each_plane_in_state(state, plane, pstate, i) {
3194 intel_plane = to_intel_plane(plane);
3195 id = skl_wm_plane_id(intel_plane);
c107acfe 3196
a6d3460e
MR		 3197 if (intel_plane->pipe != pipe)
3198 continue;
c107acfe 3199
a6d3460e
MR		 3200 if (!to_intel_plane_state(pstate)->visible) {
3201 minimum[id] = 0;
3202 y_minimum[id] = 0;
3203 continue;
3204 }
3205 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3206 minimum[id] = 0;
3207 y_minimum[id] = 0;
3208 continue;
c107acfe 3209 }
a6d3460e 3210
cbcfd14b
KM		 3211 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3212 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3213 }
80958155 3214
c107acfe
MR		 3215 for (i = 0; i < PLANE_CURSOR; i++) {
3216 alloc_size -= minimum[i];
3217 alloc_size -= y_minimum[i];
80958155
DL		 3218 }
3219
b9cec075 3220 /*
80958155
DL		 3221 * 2. Distribute the remaining space in proportion to the amount of
3222 * data each plane needs to fetch from memory.
b9cec075
DL		 3223 *
3224 * FIXME: we may not allocate every single block here.
3225 */
024c9045 3226 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3227 if (total_data_rate == 0)
c107acfe 3228 return 0;
b9cec075 3229
34bb56af 3230 start = alloc->start;
024c9045 3231 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3232 unsigned int data_rate, y_data_rate;
3233 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3234 int id = skl_wm_plane_id(intel_plane);
b9cec075 3235
a1de91e5 3236 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3237
3238 /*
2cd601c6 3239 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3240 * promote the expression to 64 bits to avoid overflowing, the
3241 * result is < available as data_rate / total_data_rate < 1
3242 */
024c9045 3243 plane_blocks = minimum[id];
80958155
DL		 3244 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3245 total_data_rate);
b9cec075 3246
c107acfe
MR		 3247 /* Leave disabled planes at (0,0) */
3248 if (data_rate) {
3249 ddb->plane[pipe][id].start = start;
3250 ddb->plane[pipe][id].end = start + plane_blocks;
3251 }
b9cec075
DL		 3252
3253 start += plane_blocks;
2cd601c6
CK		 3254
3255 /*
3256 * allocation for y_plane part of planar format:
3257 */
a1de91e5
MR		 3258 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3259
3260 y_plane_blocks = y_minimum[id];
3261 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3262 total_data_rate);
2cd601c6 3263
c107acfe
MR		 3264 if (y_data_rate) {
3265 ddb->y_plane[pipe][id].start = start;
3266 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3267 }
a1de91e5
MR		 3268
3269 start += y_plane_blocks;
b9cec075
DL		 3270 }
3271
c107acfe 3272 return 0;
b9cec075
DL		 3273}
3274
5cec258b 3275static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3276{
3277 /* TODO: Take into account the scalers once we support them */
2d112de7 3278 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3279}
3280
3281/*
3282 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3283 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3284 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3285 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3286*/
ac484963 3287static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3288{
3289 uint32_t wm_intermediate_val, ret;
3290
3291 if (latency == 0)
3292 return UINT_MAX;
3293
ac484963 3294 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3295 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3296
3297 return ret;
3298}
3299
3300static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3301 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3302 uint64_t tiling, uint32_t latency)
2d41c0b5 3303{
d4c2aa60
TU		 3304 uint32_t ret;
3305 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3306 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3307
3308 if (latency == 0)
3309 return UINT_MAX;
3310
ac484963 3311 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3312
3313 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3314 tiling == I915_FORMAT_MOD_Yf_TILED) {
3315 plane_bytes_per_line *= 4;
3316 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3317 plane_blocks_per_line /= 4;
3318 } else {
3319 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3320 }
3321
2d41c0b5
PB		 3322 wm_intermediate_val = latency * pixel_rate;
3323 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3324 plane_blocks_per_line;
2d41c0b5
PB		 3325
3326 return ret;
3327}
3328
9c2f7a9d
KM		 3329static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3330 struct intel_plane_state *pstate)
3331{
3332 uint64_t adjusted_pixel_rate;
3333 uint64_t downscale_amount;
3334 uint64_t pixel_rate;
3335
3336 /* Shouldn't reach here on disabled planes... */
3337 if (WARN_ON(!pstate->visible))
3338 return 0;
3339
3340 /*
3341 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3342 * with additional adjustments for plane-specific scaling.
3343 */
3344 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3345 downscale_amount = skl_plane_downscale_amount(pstate);
3346
3347 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3348 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3349
3350 return pixel_rate;
3351}
3352
55994c2c
MR		 3353static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3354 struct intel_crtc_state *cstate,
3355 struct intel_plane_state *intel_pstate,
3356 uint16_t ddb_allocation,
3357 int level,
3358 uint16_t *out_blocks, /* out */
3359 uint8_t *out_lines, /* out */
3360 bool *enabled /* out */)
2d41c0b5 3361{
33815fa5
MR		 3362 struct drm_plane_state *pstate = &intel_pstate->base;
3363 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3364 uint32_t latency = dev_priv->wm.skl_latency[level];
3365 uint32_t method1, method2;
3366 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3367 uint32_t res_blocks, res_lines;
3368 uint32_t selected_result;
ac484963 3369 uint8_t cpp;
a280f7dd 3370 uint32_t width = 0, height = 0;
9c2f7a9d 3371 uint32_t plane_pixel_rate;
2d41c0b5 3372
55994c2c
MR		 3373 if (latency == 0 || !cstate->base.active || !intel_pstate->visible) {
3374 *enabled = false;
3375 return 0;
3376 }
2d41c0b5 3377
a280f7dd
KM		 3378 width = drm_rect_width(&intel_pstate->src) >> 16;
3379 height = drm_rect_height(&intel_pstate->src) >> 16;
3380
33815fa5 3381 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3382 swap(width, height);
3383
ac484963 3384 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3385 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3386
3387 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3388 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3389 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3390 width,
3391 cpp,
3392 fb->modifier[0],
d4c2aa60 3393 latency);
2d41c0b5 3394
a280f7dd 3395 plane_bytes_per_line = width * cpp;
d4c2aa60 3396 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3397
024c9045
MR		 3398 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3399 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3400 uint32_t min_scanlines = 4;
3401 uint32_t y_tile_minimum;
33815fa5 3402 if (intel_rotation_90_or_270(pstate->rotation)) {
ac484963 3403 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3404 drm_format_plane_cpp(fb->pixel_format, 1) :
3405 drm_format_plane_cpp(fb->pixel_format, 0);
3406
ac484963 3407 switch (cpp) {
1fc0a8f7
TU		 3408 case 1:
3409 min_scanlines = 16;
3410 break;
3411 case 2:
3412 min_scanlines = 8;
3413 break;
3414 case 8:
3415 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3416 }
1fc0a8f7
TU		 3417 }
3418 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3419 selected_result = max(method2, y_tile_minimum);
3420 } else {
3421 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3422 selected_result = min(method1, method2);
3423 else
3424 selected_result = method1;
3425 }
2d41c0b5 3426
d4c2aa60
TU		 3427 res_blocks = selected_result + 1;
3428 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3429
0fda6568 3430 if (level >= 1 && level <= 7) {
024c9045
MR		 3431 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3432 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3433 res_lines += 4;
3434 else
3435 res_blocks++;
3436 }
e6d66171 3437
55994c2c
MR		 3438 if (res_blocks >= ddb_allocation || res_lines > 31) {
3439 *enabled = false;
6b6bada7
MR		 3440
3441 /*
3442 * If there are no valid level 0 watermarks, then we can't
3443 * support this display configuration.
3444 */
3445 if (level) {
3446 return 0;
3447 } else {
3448 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3449 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3450 to_intel_crtc(cstate->base.crtc)->pipe,
3451 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3452 res_blocks, ddb_allocation, res_lines);
3453
3454 return -EINVAL;
3455 }
55994c2c 3456 }
e6d66171
DL		 3457
3458 *out_blocks = res_blocks;
3459 *out_lines = res_lines;
55994c2c 3460 *enabled = true;
2d41c0b5 3461
55994c2c 3462 return 0;
2d41c0b5
PB		 3463}
3464
f4a96752
MR		 3465static int
3466skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3467 struct skl_ddb_allocation *ddb,
3468 struct intel_crtc_state *cstate,
3469 int level,
3470 struct skl_wm_level *result)
2d41c0b5 3471{
024c9045 3472 struct drm_device *dev = dev_priv->dev;
f4a96752 3473 struct drm_atomic_state *state = cstate->base.state;
024c9045 3474 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3475 struct drm_plane *plane;
024c9045 3476 struct intel_plane *intel_plane;
33815fa5 3477 struct intel_plane_state *intel_pstate;
2d41c0b5 3478 uint16_t ddb_blocks;
024c9045 3479 enum pipe pipe = intel_crtc->pipe;
55994c2c 3480 int ret;
024c9045 3481
f4a96752
MR		 3482 /*
3483 * We'll only calculate watermarks for planes that are actually
3484 * enabled, so make sure all other planes are set as disabled.
3485 */
3486 memset(result, 0, sizeof(*result));
3487
3488 for_each_intel_plane_mask(dev, intel_plane, cstate->base.plane_mask) {
024c9045 3489 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3490
f4a96752
MR		 3491 plane = &intel_plane->base;
3492 intel_pstate = NULL;
3493 if (state)
3494 intel_pstate =
3495 intel_atomic_get_existing_plane_state(state,
3496 intel_plane);
3497
3498 /*
3499 * Note: If we start supporting multiple pending atomic commits
3500 * against the same planes/CRTC's in the future, plane->state
3501 * will no longer be the correct pre-state to use for the
3502 * calculations here and we'll need to change where we get the
3503 * 'unchanged' plane data from.
3504 *
3505 * For now this is fine because we only allow one queued commit
3506 * against a CRTC. Even if the plane isn't modified by this
3507 * transaction and we don't have a plane lock, we still have
3508 * the CRTC's lock, so we know that no other transactions are
3509 * racing with us to update it.
3510 */
3511 if (!intel_pstate)
3512 intel_pstate = to_intel_plane_state(plane->state);
3513
3514 WARN_ON(!intel_pstate->base.fb);
3515
2d41c0b5
PB		 3516 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3517
55994c2c
MR		 3518 ret = skl_compute_plane_wm(dev_priv,
3519 cstate,
3520 intel_pstate,
3521 ddb_blocks,
3522 level,
3523 &result->plane_res_b[i],
3524 &result->plane_res_l[i],
3525 &result->plane_en[i]);
3526 if (ret)
3527 return ret;
2d41c0b5 3528 }
f4a96752
MR		 3529
3530 return 0;
2d41c0b5
PB		 3531}
3532
407b50f3 3533static uint32_t
024c9045 3534skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3535{
024c9045 3536 if (!cstate->base.active)
407b50f3
DL		 3537 return 0;
3538
024c9045 3539 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3540 return 0;
407b50f3 3541
024c9045
MR		 3542 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3543 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3544}
3545
024c9045 3546static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3547 struct skl_wm_level *trans_wm /* out */)
407b50f3 3548{
024c9045 3549 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3551 struct intel_plane *intel_plane;
9414f563 3552
024c9045 3553 if (!cstate->base.active)
407b50f3 3554 return;
9414f563
DL		 3555
3556 /* Until we know more, just disable transition WMs */
024c9045
MR		 3557 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3558 int i = skl_wm_plane_id(intel_plane);
3559
9414f563 3560 trans_wm->plane_en[i] = false;
024c9045 3561 }
407b50f3
DL		 3562}
3563
55994c2c
MR		 3564static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3565 struct skl_ddb_allocation *ddb,
3566 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3567{
024c9045 3568 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3569 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3570 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3571 int ret;
2d41c0b5
PB		 3572
3573 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3574 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3575 level, &pipe_wm->wm[level]);
3576 if (ret)
3577 return ret;
2d41c0b5 3578 }
024c9045 3579 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3580
024c9045 3581 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3582
3583 return 0;
2d41c0b5
PB		 3584}
3585
3586static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3587 struct skl_pipe_wm *p_wm,
3588 struct skl_wm_values *r,
3589 struct intel_crtc *intel_crtc)
3590{
3591 int level, max_level = ilk_wm_max_level(dev);
3592 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3593 uint32_t temp;
3594 int i;
2d41c0b5
PB		 3595
3596 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3597 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3598 temp = 0;
2d41c0b5
PB		 3599
3600 temp |= p_wm->wm[level].plane_res_l[i] <<
3601 PLANE_WM_LINES_SHIFT;
3602 temp |= p_wm->wm[level].plane_res_b[i];
3603 if (p_wm->wm[level].plane_en[i])
3604 temp |= PLANE_WM_EN;
3605
3606 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3607 }
3608
3609 temp = 0;
2d41c0b5 3610
4969d33e
MR		 3611 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3612 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3613
4969d33e 3614 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3615 temp |= PLANE_WM_EN;
3616
4969d33e 3617 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3618
3619 }
3620
9414f563
DL		 3621 /* transition WMs */
3622 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3623 temp = 0;
3624 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3625 temp |= p_wm->trans_wm.plane_res_b[i];
3626 if (p_wm->trans_wm.plane_en[i])
3627 temp |= PLANE_WM_EN;
3628
3629 r->plane_trans[pipe][i] = temp;
3630 }
3631
3632 temp = 0;
4969d33e
MR		 3633 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3634 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3635 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3636 temp |= PLANE_WM_EN;
3637
4969d33e 3638 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3639
2d41c0b5
PB		 3640 r->wm_linetime[pipe] = p_wm->linetime;
3641}
3642
f0f59a00
VS		 3643static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3644 i915_reg_t reg,
16160e3d
DL		 3645 const struct skl_ddb_entry *entry)
3646{
3647 if (entry->end)
3648 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3649 else
3650 I915_WRITE(reg, 0);
3651}
3652
2d41c0b5
PB		 3653static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3654 const struct skl_wm_values *new)
3655{
3656 struct drm_device *dev = dev_priv->dev;
3657 struct intel_crtc *crtc;
3658
19c8054c 3659 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3660 int i, level, max_level = ilk_wm_max_level(dev);
3661 enum pipe pipe = crtc->pipe;
3662
2b4b9f35 3663 if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0)
5d374d96 3664 continue;
734fa01f
MR		 3665 if (!crtc->active)
3666 continue;
8211bd5b 3667
5d374d96 3668 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3669
5d374d96
DL		 3670 for (level = 0; level <= max_level; level++) {
3671 for (i = 0; i < intel_num_planes(crtc); i++)
3672 I915_WRITE(PLANE_WM(pipe, i, level),
3673 new->plane[pipe][i][level]);
3674 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3675 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3676 }
5d374d96
DL		 3677 for (i = 0; i < intel_num_planes(crtc); i++)
3678 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3679 new->plane_trans[pipe][i]);
4969d33e
MR		 3680 I915_WRITE(CUR_WM_TRANS(pipe),
3681 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3682
2cd601c6 3683 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3684 skl_ddb_entry_write(dev_priv,
3685 PLANE_BUF_CFG(pipe, i),
3686 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3687 skl_ddb_entry_write(dev_priv,
3688 PLANE_NV12_BUF_CFG(pipe, i),
3689 &new->ddb.y_plane[pipe][i]);
3690 }
5d374d96
DL		 3691
3692 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3693 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3694 }
2d41c0b5
PB		 3695}
3696
0e8fb7ba
DL		 3697/*
3698 * When setting up a new DDB allocation arrangement, we need to correctly
3699 * sequence the times at which the new allocations for the pipes are taken into
3700 * account or we'll have pipes fetching from space previously allocated to
3701 * another pipe.
3702 *
3703 * Roughly the sequence looks like:
3704 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3705 * overlapping with a previous light-up pipe (another way to put it is:
3706 * pipes with their new allocation strickly included into their old ones).
3707 * 2. re-allocate the other pipes that get their allocation reduced
3708 * 3. allocate the pipes having their allocation increased
3709 *
3710 * Steps 1. and 2. are here to take care of the following case:
3711 * - Initially DDB looks like this:
3712 * | B | C |
3713 * - enable pipe A.
3714 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3715 * allocation
3716 * | A | B | C |
3717 *
3718 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3719 */
3720
d21b795c
DL		 3721static void
3722skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3723{
0e8fb7ba
DL		 3724 int plane;
3725
d21b795c
DL		 3726 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3727
dd740780 3728 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3729 I915_WRITE(PLANE_SURF(pipe, plane),
3730 I915_READ(PLANE_SURF(pipe, plane)));
3731 }
3732 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3733}
3734
3735static bool
3736skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3737 const struct skl_ddb_allocation *new,
3738 enum pipe pipe)
3739{
3740 uint16_t old_size, new_size;
3741
3742 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3743 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3744
3745 return old_size != new_size &&
3746 new->pipe[pipe].start >= old->pipe[pipe].start &&
3747 new->pipe[pipe].end <= old->pipe[pipe].end;
3748}
3749
3750static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3751 struct skl_wm_values *new_values)
3752{
3753 struct drm_device *dev = dev_priv->dev;
3754 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3755 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3756 struct intel_crtc *crtc;
3757 enum pipe pipe;
3758
3759 new_ddb = &new_values->ddb;
3760 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3761
3762 /*
3763 * First pass: flush the pipes with the new allocation contained into
3764 * the old space.
3765 *
3766 * We'll wait for the vblank on those pipes to ensure we can safely
3767 * re-allocate the freed space without this pipe fetching from it.
3768 */
3769 for_each_intel_crtc(dev, crtc) {
3770 if (!crtc->active)
3771 continue;
3772
3773 pipe = crtc->pipe;
3774
3775 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3776 continue;
3777
d21b795c 3778 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3779 intel_wait_for_vblank(dev, pipe);
3780
3781 reallocated[pipe] = true;
3782 }
3783
3784
3785 /*
3786 * Second pass: flush the pipes that are having their allocation
3787 * reduced, but overlapping with a previous allocation.
3788 *
3789 * Here as well we need to wait for the vblank to make sure the freed
3790 * space is not used anymore.
3791 */
3792 for_each_intel_crtc(dev, crtc) {
3793 if (!crtc->active)
3794 continue;
3795
3796 pipe = crtc->pipe;
3797
3798 if (reallocated[pipe])
3799 continue;
3800
3801 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3802 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3803 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3804 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3805 reallocated[pipe] = true;
0e8fb7ba 3806 }
0e8fb7ba
DL		 3807 }
3808
3809 /*
3810 * Third pass: flush the pipes that got more space allocated.
3811 *
3812 * We don't need to actively wait for the update here, next vblank
3813 * will just get more DDB space with the correct WM values.
3814 */
3815 for_each_intel_crtc(dev, crtc) {
3816 if (!crtc->active)
3817 continue;
3818
3819 pipe = crtc->pipe;
3820
3821 /*
3822 * At this point, only the pipes more space than before are
3823 * left to re-allocate.
3824 */
3825 if (reallocated[pipe])
3826 continue;
3827
d21b795c 3828 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3829 }
3830}
3831
55994c2c
MR		 3832static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3833 struct skl_ddb_allocation *ddb, /* out */
3834 struct skl_pipe_wm *pipe_wm, /* out */
3835 bool *changed /* out */)
2d41c0b5 3836{
f4a96752
MR		 3837 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3838 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3839 int ret;
2d41c0b5 3840
55994c2c
MR		 3841 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3842 if (ret)
3843 return ret;
2d41c0b5 3844
4e0963c7 3845 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3846 *changed = false;
3847 else
3848 *changed = true;
2d41c0b5 3849
55994c2c 3850 return 0;
2d41c0b5
PB		 3851}
3852
98d39494
MR		 3853static int
3854skl_compute_ddb(struct drm_atomic_state *state)
3855{
3856 struct drm_device *dev = state->dev;
3857 struct drm_i915_private *dev_priv = to_i915(dev);
3858 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3859 struct intel_crtc *intel_crtc;
734fa01f 3860 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
98d39494
MR		 3861 unsigned realloc_pipes = dev_priv->active_crtcs;
3862 int ret;
3863
3864 /*
3865 * If this is our first atomic update following hardware readout,
3866 * we can't trust the DDB that the BIOS programmed for us. Let's
3867 * pretend that all pipes switched active status so that we'll
3868 * ensure a full DDB recompute.
3869 */
3870 if (dev_priv->wm.distrust_bios_wm)
3871 intel_state->active_pipe_changes = ~0;
3872
3873 /*
3874 * If the modeset changes which CRTC's are active, we need to
3875 * recompute the DDB allocation for *all* active pipes, even
3876 * those that weren't otherwise being modified in any way by this
3877 * atomic commit. Due to the shrinking of the per-pipe allocations
3878 * when new active CRTC's are added, it's possible for a pipe that
3879 * we were already using and aren't changing at all here to suddenly
3880 * become invalid if its DDB needs exceeds its new allocation.
3881 *
3882 * Note that if we wind up doing a full DDB recompute, we can't let
3883 * any other display updates race with this transaction, so we need
3884 * to grab the lock on *all* CRTC's.
3885 */
734fa01f 3886 if (intel_state->active_pipe_changes) {
98d39494 3887 realloc_pipes = ~0;
734fa01f
MR		 3888 intel_state->wm_results.dirty_pipes = ~0;
3889 }
98d39494
MR		 3890
3891 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3892 struct intel_crtc_state *cstate;
3893
3894 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3895 if (IS_ERR(cstate))
3896 return PTR_ERR(cstate);
3897
734fa01f 3898 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 3899 if (ret)
3900 return ret;
3901 }
3902
3903 return 0;
3904}
3905
3906static int
3907skl_compute_wm(struct drm_atomic_state *state)
3908{
3909 struct drm_crtc *crtc;
3910 struct drm_crtc_state *cstate;
734fa01f
MR		 3911 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3912 struct skl_wm_values *results = &intel_state->wm_results;
3913 struct skl_pipe_wm *pipe_wm;
98d39494 3914 bool changed = false;
734fa01f 3915 int ret, i;
98d39494
MR		 3916
3917 /*
3918 * If this transaction isn't actually touching any CRTC's, don't
3919 * bother with watermark calculation. Note that if we pass this
3920 * test, we're guaranteed to hold at least one CRTC state mutex,
3921 * which means we can safely use values like dev_priv->active_crtcs
3922 * since any racing commits that want to update them would need to
3923 * hold _all_ CRTC state mutexes.
3924 */
3925 for_each_crtc_in_state(state, crtc, cstate, i)
3926 changed = true;
3927 if (!changed)
3928 return 0;
3929
734fa01f
MR		 3930 /* Clear all dirty flags */
3931 results->dirty_pipes = 0;
3932
98d39494
MR		 3933 ret = skl_compute_ddb(state);
3934 if (ret)
3935 return ret;
3936
734fa01f
MR		 3937 /*
3938 * Calculate WM's for all pipes that are part of this transaction.
3939 * Note that the DDB allocation above may have added more CRTC's that
3940 * weren't otherwise being modified (and set bits in dirty_pipes) if
3941 * pipe allocations had to change.
3942 *
3943 * FIXME: Now that we're doing this in the atomic check phase, we
3944 * should allow skl_update_pipe_wm() to return failure in cases where
3945 * no suitable watermark values can be found.
3946 */
3947 for_each_crtc_in_state(state, crtc, cstate, i) {
3948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3949 struct intel_crtc_state *intel_cstate =
3950 to_intel_crtc_state(cstate);
3951
3952 pipe_wm = &intel_cstate->wm.skl.optimal;
3953 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
3954 &changed);
3955 if (ret)
3956 return ret;
3957
3958 if (changed)
3959 results->dirty_pipes |= drm_crtc_mask(crtc);
3960
3961 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
3962 /* This pipe's WM's did not change */
3963 continue;
3964
3965 intel_cstate->update_wm_pre = true;
3966 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
3967 }
3968
98d39494
MR		 3969 return 0;
3970}
3971
2d41c0b5
PB		 3972static void skl_update_wm(struct drm_crtc *crtc)
3973{
3974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3975 struct drm_device *dev = crtc->dev;
3976 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3977 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7 3978 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 3979 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
adda50b8 3980
734fa01f 3981 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 3982 return;
3983
734fa01f
MR		 3984 intel_crtc->wm.active.skl = *pipe_wm;
3985
3986 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 3987
2d41c0b5 3988 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3989 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3990
3991 /* store the new configuration */
3992 dev_priv->wm.skl_hw = *results;
734fa01f
MR		 3993
3994 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 3995}
3996
d890565c
VS		 3997static void ilk_compute_wm_config(struct drm_device *dev,
3998 struct intel_wm_config *config)
3999{
4000 struct intel_crtc *crtc;
4001
4002 /* Compute the currently _active_ config */
4003 for_each_intel_crtc(dev, crtc) {
4004 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4005
4006 if (!wm->pipe_enabled)
4007 continue;
4008
4009 config->sprites_enabled |= wm->sprites_enabled;
4010 config->sprites_scaled |= wm->sprites_scaled;
4011 config->num_pipes_active++;
4012 }
4013}
4014
ed4a6a7c 4015static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4016{
ed4a6a7c 4017 struct drm_device *dev = dev_priv->dev;
b9d5c839 4018 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4019 struct ilk_wm_maximums max;
d890565c 4020 struct intel_wm_config config = {};
820c1980 4021 struct ilk_wm_values results = {};
77c122bc 4022 enum intel_ddb_partitioning partitioning;
261a27d1 4023
d890565c
VS		 4024 ilk_compute_wm_config(dev, &config);
4025
4026 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4027 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4028
4029 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4030 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4031 config.num_pipes_active == 1 && config.sprites_enabled) {
4032 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4033 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4034
820c1980 4035 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4036 } else {
198a1e9b 4037 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4038 }
4039
198a1e9b 4040 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4041 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4042
820c1980 4043 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4044
820c1980 4045 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4046}
4047
ed4a6a7c 4048static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4049{
ed4a6a7c
MR		 4050 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4051 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4052
ed4a6a7c 4053 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4054 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4055 ilk_program_watermarks(dev_priv);
4056 mutex_unlock(&dev_priv->wm.wm_mutex);
4057}
bf220452 4058
ed4a6a7c
MR		 4059static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4060{
4061 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4062 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4063
ed4a6a7c
MR		 4064 mutex_lock(&dev_priv->wm.wm_mutex);
4065 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4066 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4067 ilk_program_watermarks(dev_priv);
4068 }
4069 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4070}
4071
3078999f
PB		 4072static void skl_pipe_wm_active_state(uint32_t val,
4073 struct skl_pipe_wm *active,
4074 bool is_transwm,
4075 bool is_cursor,
4076 int i,
4077 int level)
4078{
4079 bool is_enabled = (val & PLANE_WM_EN) != 0;
4080
4081 if (!is_transwm) {
4082 if (!is_cursor) {
4083 active->wm[level].plane_en[i] = is_enabled;
4084 active->wm[level].plane_res_b[i] =
4085 val & PLANE_WM_BLOCKS_MASK;
4086 active->wm[level].plane_res_l[i] =
4087 (val >> PLANE_WM_LINES_SHIFT) &
4088 PLANE_WM_LINES_MASK;
4089 } else {
4969d33e
MR		 4090 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4091 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4092 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4093 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4094 (val >> PLANE_WM_LINES_SHIFT) &
4095 PLANE_WM_LINES_MASK;
4096 }
4097 } else {
4098 if (!is_cursor) {
4099 active->trans_wm.plane_en[i] = is_enabled;
4100 active->trans_wm.plane_res_b[i] =
4101 val & PLANE_WM_BLOCKS_MASK;
4102 active->trans_wm.plane_res_l[i] =
4103 (val >> PLANE_WM_LINES_SHIFT) &
4104 PLANE_WM_LINES_MASK;
4105 } else {
4969d33e
MR		 4106 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4107 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4108 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4109 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4110 (val >> PLANE_WM_LINES_SHIFT) &
4111 PLANE_WM_LINES_MASK;
4112 }
4113 }
4114}
4115
4116static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4117{
4118 struct drm_device *dev = crtc->dev;
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4122 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4123 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4124 enum pipe pipe = intel_crtc->pipe;
4125 int level, i, max_level;
4126 uint32_t temp;
4127
4128 max_level = ilk_wm_max_level(dev);
4129
4130 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4131
4132 for (level = 0; level <= max_level; level++) {
4133 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4134 hw->plane[pipe][i][level] =
4135 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4136 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4137 }
4138
4139 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4140 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4141 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4142
3ef00284 4143 if (!intel_crtc->active)
3078999f
PB		 4144 return;
4145
2b4b9f35 4146 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4147
4148 active->linetime = hw->wm_linetime[pipe];
4149
4150 for (level = 0; level <= max_level; level++) {
4151 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4152 temp = hw->plane[pipe][i][level];
4153 skl_pipe_wm_active_state(temp, active, false,
4154 false, i, level);
4155 }
4969d33e 4156 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4157 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4158 }
4159
4160 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4161 temp = hw->plane_trans[pipe][i];
4162 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4163 }
4164
4969d33e 4165 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4166 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4167
4168 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4169}
4170
4171void skl_wm_get_hw_state(struct drm_device *dev)
4172{
a269c583
DL		 4173 struct drm_i915_private *dev_priv = dev->dev_private;
4174 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4175 struct drm_crtc *crtc;
4176
a269c583 4177 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4178 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4179 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4180
279e99d7
MR		 4181 if (dev_priv->active_crtcs) {
4182 /* Fully recompute DDB on first atomic commit */
4183 dev_priv->wm.distrust_bios_wm = true;
4184 } else {
4185 /* Easy/common case; just sanitize DDB now if everything off */
4186 memset(ddb, 0, sizeof(*ddb));
4187 }
3078999f
PB		 4188}
4189
243e6a44
VS		 4190static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4191{
4192 struct drm_device *dev = crtc->dev;
4193 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4194 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4196 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4197 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4198 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4199 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4200 [PIPE_A] = WM0_PIPEA_ILK,
4201 [PIPE_B] = WM0_PIPEB_ILK,
4202 [PIPE_C] = WM0_PIPEC_IVB,
4203 };
4204
4205 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4206 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4207 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4208
15606534
VS		 4209 memset(active, 0, sizeof(*active));
4210
3ef00284 4211 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4212
4213 if (active->pipe_enabled) {
243e6a44
VS		 4214 u32 tmp = hw->wm_pipe[pipe];
4215
4216 /*
4217 * For active pipes LP0 watermark is marked as
4218 * enabled, and LP1+ watermaks as disabled since
4219 * we can't really reverse compute them in case
4220 * multiple pipes are active.
4221 */
4222 active->wm[0].enable = true;
4223 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4224 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4225 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4226 active->linetime = hw->wm_linetime[pipe];
4227 } else {
4228 int level, max_level = ilk_wm_max_level(dev);
4229
4230 /*
4231 * For inactive pipes, all watermark levels
4232 * should be marked as enabled but zeroed,
4233 * which is what we'd compute them to.
4234 */
4235 for (level = 0; level <= max_level; level++)
4236 active->wm[level].enable = true;
4237 }
4e0963c7
MR		 4238
4239 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4240}
4241
6eb1a681
VS		 4242#define _FW_WM(value, plane) \
4243 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4244#define _FW_WM_VLV(value, plane) \
4245 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4246
4247static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4248 struct vlv_wm_values *wm)
4249{
4250 enum pipe pipe;
4251 uint32_t tmp;
4252
4253 for_each_pipe(dev_priv, pipe) {
4254 tmp = I915_READ(VLV_DDL(pipe));
4255
4256 wm->ddl[pipe].primary =
4257 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4258 wm->ddl[pipe].cursor =
4259 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4260 wm->ddl[pipe].sprite[0] =
4261 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4262 wm->ddl[pipe].sprite[1] =
4263 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4264 }
4265
4266 tmp = I915_READ(DSPFW1);
4267 wm->sr.plane = _FW_WM(tmp, SR);
4268 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4269 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4270 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4271
4272 tmp = I915_READ(DSPFW2);
4273 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4274 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4275 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4276
4277 tmp = I915_READ(DSPFW3);
4278 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4279
4280 if (IS_CHERRYVIEW(dev_priv)) {
4281 tmp = I915_READ(DSPFW7_CHV);
4282 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4283 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4284
4285 tmp = I915_READ(DSPFW8_CHV);
4286 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4287 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4288
4289 tmp = I915_READ(DSPFW9_CHV);
4290 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4291 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4292
4293 tmp = I915_READ(DSPHOWM);
4294 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4295 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4296 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4297 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4298 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4299 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4300 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4301 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4302 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4303 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4304 } else {
4305 tmp = I915_READ(DSPFW7);
4306 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4307 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4308
4309 tmp = I915_READ(DSPHOWM);
4310 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4311 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4312 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4313 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4314 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4315 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4316 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4317 }
4318}
4319
4320#undef _FW_WM
4321#undef _FW_WM_VLV
4322
4323void vlv_wm_get_hw_state(struct drm_device *dev)
4324{
4325 struct drm_i915_private *dev_priv = to_i915(dev);
4326 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4327 struct intel_plane *plane;
4328 enum pipe pipe;
4329 u32 val;
4330
4331 vlv_read_wm_values(dev_priv, wm);
4332
4333 for_each_intel_plane(dev, plane) {
4334 switch (plane->base.type) {
4335 int sprite;
4336 case DRM_PLANE_TYPE_CURSOR:
4337 plane->wm.fifo_size = 63;
4338 break;
4339 case DRM_PLANE_TYPE_PRIMARY:
4340 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4341 break;
4342 case DRM_PLANE_TYPE_OVERLAY:
4343 sprite = plane->plane;
4344 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4345 break;
4346 }
4347 }
4348
4349 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4350 wm->level = VLV_WM_LEVEL_PM2;
4351
4352 if (IS_CHERRYVIEW(dev_priv)) {
4353 mutex_lock(&dev_priv->rps.hw_lock);
4354
4355 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4356 if (val & DSP_MAXFIFO_PM5_ENABLE)
4357 wm->level = VLV_WM_LEVEL_PM5;
4358
58590c14
VS		 4359 /*
4360 * If DDR DVFS is disabled in the BIOS, Punit
4361 * will never ack the request. So if that happens
4362 * assume we don't have to enable/disable DDR DVFS
4363 * dynamically. To test that just set the REQ_ACK
4364 * bit to poke the Punit, but don't change the
4365 * HIGH/LOW bits so that we don't actually change
4366 * the current state.
4367 */
6eb1a681 4368 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4369 val |= FORCE_DDR_FREQ_REQ_ACK;
4370 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4371
4372 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4373 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4374 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4375 "assuming DDR DVFS is disabled\n");
4376 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4377 } else {
4378 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4379 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4380 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4381 }
6eb1a681
VS		 4382
4383 mutex_unlock(&dev_priv->rps.hw_lock);
4384 }
4385
4386 for_each_pipe(dev_priv, pipe)
4387 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4388 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4389 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4390
4391 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4392 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4393}
4394
243e6a44
VS		 4395void ilk_wm_get_hw_state(struct drm_device *dev)
4396{
4397 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4398 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4399 struct drm_crtc *crtc;
4400
70e1e0ec 4401 for_each_crtc(dev, crtc)
243e6a44
VS		 4402 ilk_pipe_wm_get_hw_state(crtc);
4403
4404 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4405 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4406 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4407
4408 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4409 if (INTEL_INFO(dev)->gen >= 7) {
4410 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4411 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4412 }
243e6a44 4413
a42a5719 4414 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4415 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4416 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4417 else if (IS_IVYBRIDGE(dev))
4418 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4419 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4420
4421 hw->enable_fbc_wm =
4422 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4423}
4424
b445e3b0
ED		 4425/**
4426 * intel_update_watermarks - update FIFO watermark values based on current modes
4427 *
4428 * Calculate watermark values for the various WM regs based on current mode
4429 * and plane configuration.
4430 *
4431 * There are several cases to deal with here:
4432 * - normal (i.e. non-self-refresh)
4433 * - self-refresh (SR) mode
4434 * - lines are large relative to FIFO size (buffer can hold up to 2)
4435 * - lines are small relative to FIFO size (buffer can hold more than 2
4436 * lines), so need to account for TLB latency
4437 *
4438 * The normal calculation is:
4439 * watermark = dotclock * bytes per pixel * latency
4440 * where latency is platform & configuration dependent (we assume pessimal
4441 * values here).
4442 *
4443 * The SR calculation is:
4444 * watermark = (trunc(latency/line time)+1) * surface width *
4445 * bytes per pixel
4446 * where
4447 * line time = htotal / dotclock
4448 * surface width = hdisplay for normal plane and 64 for cursor
4449 * and latency is assumed to be high, as above.
4450 *
4451 * The final value programmed to the register should always be rounded up,
4452 * and include an extra 2 entries to account for clock crossings.
4453 *
4454 * We don't use the sprite, so we can ignore that. And on Crestline we have
4455 * to set the non-SR watermarks to 8.
4456 */
46ba614c 4457void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4458{
46ba614c 4459 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4460
4461 if (dev_priv->display.update_wm)
46ba614c 4462 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4463}
4464
e2828914 4465/*
9270388e 4466 * Lock protecting IPS related data structures
9270388e
DV		 4467 */
4468DEFINE_SPINLOCK(mchdev_lock);
4469
4470/* Global for IPS driver to get at the current i915 device. Protected by
4471 * mchdev_lock. */
4472static struct drm_i915_private *i915_mch_dev;
4473
91d14251 4474bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4475{
2b4e57bd
ED		 4476 u16 rgvswctl;
4477
9270388e
DV		 4478 assert_spin_locked(&mchdev_lock);
4479
2b4e57bd
ED		 4480 rgvswctl = I915_READ16(MEMSWCTL);
4481 if (rgvswctl & MEMCTL_CMD_STS) {
4482 DRM_DEBUG("gpu busy, RCS change rejected\n");
4483 return false; /* still busy with another command */
4484 }
4485
4486 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4487 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4488 I915_WRITE16(MEMSWCTL, rgvswctl);
4489 POSTING_READ16(MEMSWCTL);
4490
4491 rgvswctl |= MEMCTL_CMD_STS;
4492 I915_WRITE16(MEMSWCTL, rgvswctl);
4493
4494 return true;
4495}
4496
91d14251 4497static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4498{
84f1b20f 4499 u32 rgvmodectl;
2b4e57bd
ED		 4500 u8 fmax, fmin, fstart, vstart;
4501
9270388e
DV		 4502 spin_lock_irq(&mchdev_lock);
4503
84f1b20f
TU		 4504 rgvmodectl = I915_READ(MEMMODECTL);
4505
2b4e57bd
ED		 4506 /* Enable temp reporting */
4507 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4508 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4509
4510 /* 100ms RC evaluation intervals */
4511 I915_WRITE(RCUPEI, 100000);
4512 I915_WRITE(RCDNEI, 100000);
4513
4514 /* Set max/min thresholds to 90ms and 80ms respectively */
4515 I915_WRITE(RCBMAXAVG, 90000);
4516 I915_WRITE(RCBMINAVG, 80000);
4517
4518 I915_WRITE(MEMIHYST, 1);
4519
4520 /* Set up min, max, and cur for interrupt handling */
4521 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4522 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4523 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4524 MEMMODE_FSTART_SHIFT;
4525
616847e7 4526 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4527 PXVFREQ_PX_SHIFT;
4528
20e4d407
DV		 4529 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4530 dev_priv->ips.fstart = fstart;
2b4e57bd 4531
20e4d407
DV		 4532 dev_priv->ips.max_delay = fstart;
4533 dev_priv->ips.min_delay = fmin;
4534 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4535
4536 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4537 fmax, fmin, fstart);
4538
4539 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4540
4541 /*
4542 * Interrupts will be enabled in ironlake_irq_postinstall
4543 */
4544
4545 I915_WRITE(VIDSTART, vstart);
4546 POSTING_READ(VIDSTART);
4547
4548 rgvmodectl |= MEMMODE_SWMODE_EN;
4549 I915_WRITE(MEMMODECTL, rgvmodectl);
4550
9270388e 4551 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4552 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4553 mdelay(1);
2b4e57bd 4554
91d14251 4555 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4556
7d81c3e0
VS		 4557 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4558 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4559 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4560 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4561 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4562
4563 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4564}
4565
91d14251 4566static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4567{
9270388e
DV		 4568 u16 rgvswctl;
4569
4570 spin_lock_irq(&mchdev_lock);
4571
4572 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4573
4574 /* Ack interrupts, disable EFC interrupt */
4575 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4576 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4577 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4578 I915_WRITE(DEIIR, DE_PCU_EVENT);
4579 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4580
4581 /* Go back to the starting frequency */
91d14251 4582 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4583 mdelay(1);
2b4e57bd
ED		 4584 rgvswctl |= MEMCTL_CMD_STS;
4585 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4586 mdelay(1);
2b4e57bd 4587
9270388e 4588 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4589}
4590
acbe9475
DV		 4591/* There's a funny hw issue where the hw returns all 0 when reading from
4592 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4593 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4594 * all limits and the gpu stuck at whatever frequency it is at atm).
4595 */
74ef1173 4596static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4597{
7b9e0ae6 4598 u32 limits;
2b4e57bd 4599
20b46e59
DV		 4600 /* Only set the down limit when we've reached the lowest level to avoid
4601 * getting more interrupts, otherwise leave this clear. This prevents a
4602 * race in the hw when coming out of rc6: There's a tiny window where
4603 * the hw runs at the minimal clock before selecting the desired
4604 * frequency, if the down threshold expires in that window we will not
4605 * receive a down interrupt. */
2d1fe073 4606 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4607 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4608 if (val <= dev_priv->rps.min_freq_softlimit)
4609 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4610 } else {
4611 limits = dev_priv->rps.max_freq_softlimit << 24;
4612 if (val <= dev_priv->rps.min_freq_softlimit)
4613 limits |= dev_priv->rps.min_freq_softlimit << 16;
4614 }
20b46e59
DV		 4615
4616 return limits;
4617}
4618
dd75fdc8
CW		 4619static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4620{
4621 int new_power;
8a586437
AG		 4622 u32 threshold_up = 0, threshold_down = 0; /* in % */
4623 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4624
4625 new_power = dev_priv->rps.power;
4626 switch (dev_priv->rps.power) {
4627 case LOW_POWER:
b39fb297 4628 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4629 new_power = BETWEEN;
4630 break;
4631
4632 case BETWEEN:
b39fb297 4633 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4634 new_power = LOW_POWER;
b39fb297 4635 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4636 new_power = HIGH_POWER;
4637 break;
4638
4639 case HIGH_POWER:
b39fb297 4640 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4641 new_power = BETWEEN;
4642 break;
4643 }
4644 /* Max/min bins are special */
aed242ff 4645 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4646 new_power = LOW_POWER;
aed242ff 4647 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4648 new_power = HIGH_POWER;
4649 if (new_power == dev_priv->rps.power)
4650 return;
4651
4652 /* Note the units here are not exactly 1us, but 1280ns. */
4653 switch (new_power) {
4654 case LOW_POWER:
4655 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4656 ei_up = 16000;
4657 threshold_up = 95;
dd75fdc8
CW		 4658
4659 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4660 ei_down = 32000;
4661 threshold_down = 85;
dd75fdc8
CW		 4662 break;
4663
4664 case BETWEEN:
4665 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4666 ei_up = 13000;
4667 threshold_up = 90;
dd75fdc8
CW		 4668
4669 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4670 ei_down = 32000;
4671 threshold_down = 75;
dd75fdc8
CW		 4672 break;
4673
4674 case HIGH_POWER:
4675 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4676 ei_up = 10000;
4677 threshold_up = 85;
dd75fdc8
CW		 4678
4679 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4680 ei_down = 32000;
4681 threshold_down = 60;
dd75fdc8
CW		 4682 break;
4683 }
4684
8a586437
AG		 4685 I915_WRITE(GEN6_RP_UP_EI,
4686 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4687 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4688 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4689
4690 I915_WRITE(GEN6_RP_DOWN_EI,
4691 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4692 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4693 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4694
4695 I915_WRITE(GEN6_RP_CONTROL,
4696 GEN6_RP_MEDIA_TURBO |
4697 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4698 GEN6_RP_MEDIA_IS_GFX |
4699 GEN6_RP_ENABLE |
4700 GEN6_RP_UP_BUSY_AVG |
4701 GEN6_RP_DOWN_IDLE_AVG);
4702
dd75fdc8 4703 dev_priv->rps.power = new_power;
8fb55197
CW		 4704 dev_priv->rps.up_threshold = threshold_up;
4705 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4706 dev_priv->rps.last_adj = 0;
4707}
4708
2876ce73
CW		 4709static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4710{
4711 u32 mask = 0;
4712
4713 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4714 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4715 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4716 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4717
7b3c29f6
CW		 4718 mask &= dev_priv->pm_rps_events;
4719
59d02a1f 4720 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4721}
4722
b8a5ff8d
JM		 4723/* gen6_set_rps is called to update the frequency request, but should also be
4724 * called when the range (min_delay and max_delay) is modified so that we can
4725 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4726static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4727{
23eafea6 4728 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4729 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4730 return;
4731
4fc688ce 4732 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4733 WARN_ON(val > dev_priv->rps.max_freq);
4734 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4735
eb64cad1
CW		 4736 /* min/max delay may still have been modified so be sure to
4737 * write the limits value.
4738 */
4739 if (val != dev_priv->rps.cur_freq) {
4740 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4741
dc97997a 4742 if (IS_GEN9(dev_priv))
5704195c
AG		 4743 I915_WRITE(GEN6_RPNSWREQ,
4744 GEN9_FREQUENCY(val));
dc97997a 4745 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4746 I915_WRITE(GEN6_RPNSWREQ,
4747 HSW_FREQUENCY(val));
4748 else
4749 I915_WRITE(GEN6_RPNSWREQ,
4750 GEN6_FREQUENCY(val) |
4751 GEN6_OFFSET(0) |
4752 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4753 }
7b9e0ae6 4754
7b9e0ae6
CW		 4755 /* Make sure we continue to get interrupts
4756 * until we hit the minimum or maximum frequencies.
4757 */
74ef1173 4758 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4759 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4760
d5570a72
BW		 4761 POSTING_READ(GEN6_RPNSWREQ);
4762
b39fb297 4763 dev_priv->rps.cur_freq = val;
0f94592e 4764 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4765}
4766
dc97997a 4767static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4768{
ffe02b40 4769 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4770 WARN_ON(val > dev_priv->rps.max_freq);
4771 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4772
dc97997a 4773 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4774 "Odd GPU freq value\n"))
4775 val &= ~1;
4776
cd25dd5b
D		 4777 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4778
8fb55197 4779 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4780 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4781 if (!IS_CHERRYVIEW(dev_priv))
4782 gen6_set_rps_thresholds(dev_priv, val);
4783 }
ffe02b40 4784
ffe02b40
VS		 4785 dev_priv->rps.cur_freq = val;
4786 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4787}
4788
a7f6e231 4789/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4790 *
4791 * * If Gfx is Idle, then
a7f6e231
D		 4792 * 1. Forcewake Media well.
4793 * 2. Request idle freq.
4794 * 3. Release Forcewake of Media well.
76c3552f
D		 4795*/
4796static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4797{
aed242ff 4798 u32 val = dev_priv->rps.idle_freq;
5549d25f 4799
aed242ff 4800 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4801 return;
4802
a7f6e231
D		 4803 /* Wake up the media well, as that takes a lot less
4804 * power than the Render well. */
4805 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4806 valleyview_set_rps(dev_priv, val);
a7f6e231 4807 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4808}
4809
43cf3bf0
CW		 4810void gen6_rps_busy(struct drm_i915_private *dev_priv)
4811{
4812 mutex_lock(&dev_priv->rps.hw_lock);
4813 if (dev_priv->rps.enabled) {
4814 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4815 gen6_rps_reset_ei(dev_priv);
4816 I915_WRITE(GEN6_PMINTRMSK,
4817 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4818 }
4819 mutex_unlock(&dev_priv->rps.hw_lock);
4820}
4821
b29c19b6
CW		 4822void gen6_rps_idle(struct drm_i915_private *dev_priv)
4823{
4824 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4825 if (dev_priv->rps.enabled) {
dc97997a 4826 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 4827 vlv_set_rps_idle(dev_priv);
7526ed79 4828 else
dc97997a 4829 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 4830 dev_priv->rps.last_adj = 0;
43cf3bf0 4831 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4832 }
8d3afd7d 4833 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4834
8d3afd7d 4835 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4836 while (!list_empty(&dev_priv->rps.clients))
4837 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4838 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4839}
4840
1854d5ca 4841void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4842 struct intel_rps_client *rps,
4843 unsigned long submitted)
b29c19b6 4844{
8d3afd7d
CW		 4845 /* This is intentionally racy! We peek at the state here, then
4846 * validate inside the RPS worker.
4847 */
4848 if (!(dev_priv->mm.busy &&
4849 dev_priv->rps.enabled &&
4850 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4851 return;
43cf3bf0 4852
e61b9958
CW		 4853 /* Force a RPS boost (and don't count it against the client) if
4854 * the GPU is severely congested.
4855 */
d0bc54f2 4856 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4857 rps = NULL;
4858
8d3afd7d
CW		 4859 spin_lock(&dev_priv->rps.client_lock);
4860 if (rps == NULL || list_empty(&rps->link)) {
4861 spin_lock_irq(&dev_priv->irq_lock);
4862 if (dev_priv->rps.interrupts_enabled) {
4863 dev_priv->rps.client_boost = true;
4864 queue_work(dev_priv->wq, &dev_priv->rps.work);
4865 }
4866 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4867
2e1b8730
CW		 4868 if (rps != NULL) {
4869 list_add(&rps->link, &dev_priv->rps.clients);
4870 rps->boosts++;
1854d5ca
CW		 4871 } else
4872 dev_priv->rps.boosts++;
c0951f0c 4873 }
8d3afd7d 4874 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4875}
4876
dc97997a 4877void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 4878{
dc97997a
CW		 4879 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4880 valleyview_set_rps(dev_priv, val);
ffe02b40 4881 else
dc97997a 4882 gen6_set_rps(dev_priv, val);
0a073b84
JB		 4883}
4884
dc97997a 4885static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 4886{
20e49366 4887 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4888 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4889}
4890
dc97997a 4891static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 4892{
2030d684
AG		 4893 I915_WRITE(GEN6_RP_CONTROL, 0);
4894}
4895
dc97997a 4896static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 4897{
d20d4f0c 4898 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4899 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4900 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4901}
4902
dc97997a 4903static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 4904{
38807746
D		 4905 I915_WRITE(GEN6_RC_CONTROL, 0);
4906}
4907
dc97997a 4908static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 4909{
98a2e5f9
D		 4910 /* we're doing forcewake before Disabling RC6,
4911 * This what the BIOS expects when going into suspend */
59bad947 4912 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4913
44fc7d5c 4914 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4915
59bad947 4916 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4917}
4918
dc97997a 4919static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 4920{
dc97997a 4921 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 4922 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4923 mode = GEN6_RC_CTL_RC6_ENABLE;
4924 else
4925 mode = 0;
4926 }
dc97997a 4927 if (HAS_RC6p(dev_priv))
58abf1da 4928 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4929 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4930 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4931 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4932
4933 else
4934 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4935 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4936}
4937
dc97997a 4938static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 4939{
72e96d64 4940 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 4941 bool enable_rc6 = true;
4942 unsigned long rc6_ctx_base;
4943
4944 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4945 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4946 enable_rc6 = false;
4947 }
4948
4949 /*
4950 * The exact context size is not known for BXT, so assume a page size
4951 * for this check.
4952 */
4953 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 4954 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4955 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4956 ggtt->stolen_reserved_size))) {
274008e8
SAK		 4957 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4958 enable_rc6 = false;
4959 }
4960
4961 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4962 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4963 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4964 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4965 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4966 enable_rc6 = false;
4967 }
4968
4969 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4970 GEN6_RC_CTL_HW_ENABLE)) &&
4971 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4972 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4973 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4974 enable_rc6 = false;
4975 }
4976
4977 return enable_rc6;
4978}
4979
dc97997a 4980int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 4981{
e7d66d89 4982 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 4983 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 4984 return 0;
4985
274008e8
SAK		 4986 if (!enable_rc6)
4987 return 0;
4988
dc97997a 4989 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 4990 DRM_INFO("RC6 disabled by BIOS\n");
4991 return 0;
4992 }
4993
456470eb 4994 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4995 if (enable_rc6 >= 0) {
4996 int mask;
4997
dc97997a 4998 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 4999 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5000 INTEL_RC6pp_ENABLE;
5001 else
5002 mask = INTEL_RC6_ENABLE;
5003
5004 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 5005 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
5006 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5007
5008 return enable_rc6 & mask;
5009 }
2b4e57bd 5010
dc97997a 5011 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5012 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5013
5014 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5015}
5016
dc97997a 5017static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0 5018{
93ee2920
TR		 5019 uint32_t rp_state_cap;
5020 u32 ddcc_status = 0;
5021 int ret;
5022
3280e8b0
BW		 5023 /* All of these values are in units of 50MHz */
5024 dev_priv->rps.cur_freq = 0;
93ee2920 5025 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5026 if (IS_BROXTON(dev_priv)) {
35040562
BP		 5027 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5028 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5029 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5030 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5031 } else {
5032 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5033 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5034 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5035 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5036 }
5037
3280e8b0
BW		 5038 /* hw_max = RP0 until we check for overclocking */
5039 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5040
93ee2920 5041 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5042 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5043 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
93ee2920
TR		 5044 ret = sandybridge_pcode_read(dev_priv,
5045 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5046 &ddcc_status);
5047 if (0 == ret)
5048 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5049 clamp_t(u8,
5050 ((ddcc_status >> 8) & 0xff),
5051 dev_priv->rps.min_freq,
5052 dev_priv->rps.max_freq);
93ee2920
TR		 5053 }
5054
dc97997a 5055 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c
AG		 5056 /* Store the frequency values in 16.66 MHZ units, which is
5057 the natural hardware unit for SKL */
5058 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5059 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5060 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5061 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5062 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5063 }
5064
aed242ff
CW		 5065 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5066
3280e8b0
BW		 5067 /* Preserve min/max settings in case of re-init */
5068 if (dev_priv->rps.max_freq_softlimit == 0)
5069 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5070
93ee2920 5071 if (dev_priv->rps.min_freq_softlimit == 0) {
dc97997a 5072 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
93ee2920 5073 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 5074 max_t(int, dev_priv->rps.efficient_freq,
5075 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 5076 else
5077 dev_priv->rps.min_freq_softlimit =
5078 dev_priv->rps.min_freq;
5079 }
3280e8b0
BW		 5080}
5081
b6fef0ef 5082/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5083static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5084{
b6fef0ef
JB		 5085 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5086
dc97997a 5087 gen6_init_rps_frequencies(dev_priv);
ba1c554c 5088
23eafea6 5089 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5090 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5091 /*
5092 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5093 * clear out the Control register just to avoid inconsitency
5094 * with debugfs interface, which will show Turbo as enabled
5095 * only and that is not expected by the User after adding the
5096 * WaGsvDisableTurbo. Apart from this there is no problem even
5097 * if the Turbo is left enabled in the Control register, as the
5098 * Up/Down interrupts would remain masked.
5099 */
dc97997a 5100 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5101 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5102 return;
5103 }
5104
0beb059a
AG		 5105 /* Program defaults and thresholds for RPS*/
5106 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5107 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5108
5109 /* 1 second timeout*/
5110 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5111 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5112
b6fef0ef 5113 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5114
0beb059a
AG		 5115 /* Leaning on the below call to gen6_set_rps to program/setup the
5116 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5117 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5118 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5119 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
b6fef0ef
JB		 5120
5121 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5122}
5123
dc97997a 5124static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5125{
e2f80391 5126 struct intel_engine_cs *engine;
20e49366 5127 uint32_t rc6_mask = 0;
20e49366
ZW		 5128
5129 /* 1a: Software RC state - RC0 */
5130 I915_WRITE(GEN6_RC_STATE, 0);
5131
5132 /* 1b: Get forcewake during program sequence. Although the driver
5133 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5134 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5135
5136 /* 2a: Disable RC states. */
5137 I915_WRITE(GEN6_RC_CONTROL, 0);
5138
5139 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5140
5141 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5142 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5143 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5144 else
5145 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5146 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5147 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5148 for_each_engine(engine, dev_priv)
e2f80391 5149 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5150
1a3d1898 5151 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5152 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5153
20e49366 5154 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5155
38c23527
ZW		 5156 /* 2c: Program Coarse Power Gating Policies. */
5157 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5158 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5159
20e49366 5160 /* 3a: Enable RC6 */
dc97997a 5161 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5162 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5163 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5164 /* WaRsUseTimeoutMode */
dc97997a
CW		 5165 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5166 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5167 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5168 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5169 GEN7_RC_CTL_TO_MODE |
5170 rc6_mask);
3e7732a0
SAK		 5171 } else {
5172 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5173 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5174 GEN6_RC_CTL_EI_MODE(1) |
5175 rc6_mask);
3e7732a0 5176 }
20e49366 5177
cb07bae0
SK		 5178 /*
5179 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5180 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5181 */
dc97997a 5182 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5183 I915_WRITE(GEN9_PG_ENABLE, 0);
5184 else
5185 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5186 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5187
59bad947 5188 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5189}
5190
dc97997a 5191static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5192{
e2f80391 5193 struct intel_engine_cs *engine;
93ee2920 5194 uint32_t rc6_mask = 0;
6edee7f3
BW		 5195
5196 /* 1a: Software RC state - RC0 */
5197 I915_WRITE(GEN6_RC_STATE, 0);
5198
5199 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5200 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5201 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5202
5203 /* 2a: Disable RC states. */
5204 I915_WRITE(GEN6_RC_CONTROL, 0);
5205
93ee2920 5206 /* Initialize rps frequencies */
dc97997a 5207 gen6_init_rps_frequencies(dev_priv);
6edee7f3
BW		 5208
5209 /* 2b: Program RC6 thresholds.*/
5210 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5211 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5212 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5213 for_each_engine(engine, dev_priv)
e2f80391 5214 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5215 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5216 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5217 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5218 else
5219 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5220
5221 /* 3: Enable RC6 */
dc97997a 5222 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5223 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5224 intel_print_rc6_info(dev_priv, rc6_mask);
5225 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5226 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5227 GEN7_RC_CTL_TO_MODE |
5228 rc6_mask);
5229 else
5230 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5231 GEN6_RC_CTL_EI_MODE(1) |
5232 rc6_mask);
6edee7f3
BW		 5233
5234 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5235 I915_WRITE(GEN6_RPNSWREQ,
5236 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5237 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5238 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5239 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5240 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5241
5242 /* Docs recommend 900MHz, and 300 MHz respectively */
5243 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5244 dev_priv->rps.max_freq_softlimit << 24 |
5245 dev_priv->rps.min_freq_softlimit << 16);
5246
5247 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5248 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5249 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5250 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5251
5252 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5253
5254 /* 5: Enable RPS */
7526ed79
DV		 5255 I915_WRITE(GEN6_RP_CONTROL,
5256 GEN6_RP_MEDIA_TURBO |
5257 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5258 GEN6_RP_MEDIA_IS_GFX |
5259 GEN6_RP_ENABLE |
5260 GEN6_RP_UP_BUSY_AVG |
5261 GEN6_RP_DOWN_IDLE_AVG);
5262
5263 /* 6: Ring frequency + overclocking (our driver does this later */
5264
c7f3153a 5265 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5266 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
7526ed79 5267
59bad947 5268 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5269}
5270
dc97997a 5271static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5272{
e2f80391 5273 struct intel_engine_cs *engine;
d060c169 5274 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5275 u32 gtfifodbg;
2b4e57bd 5276 int rc6_mode;
b4ac5afc 5277 int ret;
2b4e57bd 5278
4fc688ce 5279 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5280
2b4e57bd
ED		 5281 /* Here begins a magic sequence of register writes to enable
5282 * auto-downclocking.
5283 *
5284 * Perhaps there might be some value in exposing these to
5285 * userspace...
5286 */
5287 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5288
5289 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5290 gtfifodbg = I915_READ(GTFIFODBG);
5291 if (gtfifodbg) {
2b4e57bd
ED		 5292 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5293 I915_WRITE(GTFIFODBG, gtfifodbg);
5294 }
5295
59bad947 5296 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5297
93ee2920 5298 /* Initialize rps frequencies */
dc97997a 5299 gen6_init_rps_frequencies(dev_priv);
dd0a1aa1 5300
2b4e57bd
ED		 5301 /* disable the counters and set deterministic thresholds */
5302 I915_WRITE(GEN6_RC_CONTROL, 0);
5303
5304 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5305 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5306 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5307 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5308 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5309
b4ac5afc 5310 for_each_engine(engine, dev_priv)
e2f80391 5311 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5312
5313 I915_WRITE(GEN6_RC_SLEEP, 0);
5314 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5315 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5316 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5317 else
5318 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5319 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5320 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5321
5a7dc92a 5322 /* Check if we are enabling RC6 */
dc97997a 5323 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5324 if (rc6_mode & INTEL_RC6_ENABLE)
5325 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5326
5a7dc92a 5327 /* We don't use those on Haswell */
dc97997a 5328 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5329 if (rc6_mode & INTEL_RC6p_ENABLE)
5330 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5331
5a7dc92a
ED		 5332 if (rc6_mode & INTEL_RC6pp_ENABLE)
5333 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5334 }
2b4e57bd 5335
dc97997a 5336 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5337
5338 I915_WRITE(GEN6_RC_CONTROL,
5339 rc6_mask |
5340 GEN6_RC_CTL_EI_MODE(1) |
5341 GEN6_RC_CTL_HW_ENABLE);
5342
dd75fdc8
CW		 5343 /* Power down if completely idle for over 50ms */
5344 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5345 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5346
42c0526c 5347 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5348 if (ret)
42c0526c 5349 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5350
5351 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5352 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5353 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5354 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5355 (pcu_mbox & 0xff) * 50);
b39fb297 5356 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5357 }
5358
dd75fdc8 5359 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5360 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b4e57bd 5361
31643d54
BW		 5362 rc6vids = 0;
5363 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5364 if (IS_GEN6(dev_priv) && ret) {
31643d54 5365 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5366 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5367 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5368 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5369 rc6vids &= 0xffff00;
5370 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5371 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5372 if (ret)
5373 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5374 }
5375
59bad947 5376 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5377}
5378
dc97997a 5379static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5380{
5381 int min_freq = 15;
3ebecd07
CW		 5382 unsigned int gpu_freq;
5383 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5384 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5385 int scaling_factor = 180;
eda79642 5386 struct cpufreq_policy *policy;
2b4e57bd 5387
4fc688ce 5388 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5389
eda79642
BW		 5390 policy = cpufreq_cpu_get(0);
5391 if (policy) {
5392 max_ia_freq = policy->cpuinfo.max_freq;
5393 cpufreq_cpu_put(policy);
5394 } else {
5395 /*
5396 * Default to measured freq if none found, PCU will ensure we
5397 * don't go over
5398 */
2b4e57bd 5399 max_ia_freq = tsc_khz;
eda79642 5400 }
2b4e57bd
ED		 5401
5402 /* Convert from kHz to MHz */
5403 max_ia_freq /= 1000;
5404
153b4b95 5405 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5406 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5407 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5408
dc97997a 5409 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5410 /* Convert GT frequency to 50 HZ units */
5411 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5412 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5413 } else {
5414 min_gpu_freq = dev_priv->rps.min_freq;
5415 max_gpu_freq = dev_priv->rps.max_freq;
5416 }
5417
2b4e57bd
ED		 5418 /*
5419 * For each potential GPU frequency, load a ring frequency we'd like
5420 * to use for memory access. We do this by specifying the IA frequency
5421 * the PCU should use as a reference to determine the ring frequency.
5422 */
4c8c7743
AG		 5423 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5424 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5425 unsigned int ia_freq = 0, ring_freq = 0;
5426
dc97997a 5427 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5428 /*
5429 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5430 * No floor required for ring frequency on SKL.
5431 */
5432 ring_freq = gpu_freq;
dc97997a 5433 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5434 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5435 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5436 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5437 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5438 ring_freq = max(min_ring_freq, ring_freq);
5439 /* leave ia_freq as the default, chosen by cpufreq */
5440 } else {
5441 /* On older processors, there is no separate ring
5442 * clock domain, so in order to boost the bandwidth
5443 * of the ring, we need to upclock the CPU (ia_freq).
5444 *
5445 * For GPU frequencies less than 750MHz,
5446 * just use the lowest ring freq.
5447 */
5448 if (gpu_freq < min_freq)
5449 ia_freq = 800;
5450 else
5451 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5452 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5453 }
2b4e57bd 5454
42c0526c
BW		 5455 sandybridge_pcode_write(dev_priv,
5456 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5457 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5458 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5459 gpu_freq);
2b4e57bd 5460 }
2b4e57bd
ED		 5461}
5462
dc97997a 5463void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
c2bc2fc5 5464{
dc97997a 5465 if (!HAS_CORE_RING_FREQ(dev_priv))
c2bc2fc5
ID		 5466 return;
5467
5468 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a 5469 __gen6_update_ring_freq(dev_priv);
c2bc2fc5
ID		 5470 mutex_unlock(&dev_priv->rps.hw_lock);
5471}
5472
03af2045 5473static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5474{
5475 u32 val, rp0;
5476
5b5929cb 5477 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5478
dc97997a 5479 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5480 case 8:
5481 /* (2 * 4) config */
5482 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5483 break;
5484 case 12:
5485 /* (2 * 6) config */
5486 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5487 break;
5488 case 16:
5489 /* (2 * 8) config */
5490 default:
5491 /* Setting (2 * 8) Min RP0 for any other combination */
5492 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5493 break;
095acd5f 5494 }
5b5929cb
JN		 5495
5496 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5497
2b6b3a09
D		 5498 return rp0;
5499}
5500
5501static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5502{
5503 u32 val, rpe;
5504
5505 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5506 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5507
5508 return rpe;
5509}
5510
7707df4a
D		 5511static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5512{
5513 u32 val, rp1;
5514
5b5929cb
JN		 5515 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5516 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5517
7707df4a
D		 5518 return rp1;
5519}
5520
f8f2b001
D		 5521static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5522{
5523 u32 val, rp1;
5524
5525 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5526
5527 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5528
5529 return rp1;
5530}
5531
03af2045 5532static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5533{
5534 u32 val, rp0;
5535
64936258 5536 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5537
5538 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5539 /* Clamp to max */
5540 rp0 = min_t(u32, rp0, 0xea);
5541
5542 return rp0;
5543}
5544
5545static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5546{
5547 u32 val, rpe;
5548
64936258 5549 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5550 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5551 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5552 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5553
5554 return rpe;
5555}
5556
03af2045 5557static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5558{
36146035
ID		 5559 u32 val;
5560
5561 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5562 /*
5563 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5564 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5565 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5566 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5567 * to make sure it matches what Punit accepts.
5568 */
5569 return max_t(u32, val, 0xc0);
0a073b84
JB		 5570}
5571
ae48434c
ID		 5572/* Check that the pctx buffer wasn't move under us. */
5573static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5574{
5575 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5576
5577 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5578 dev_priv->vlv_pctx->stolen->start);
5579}
5580
38807746
D		 5581
5582/* Check that the pcbr address is not empty. */
5583static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5584{
5585 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5586
5587 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5588}
5589
dc97997a 5590static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5591{
62106b4f 5592 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5593 unsigned long pctx_paddr, paddr;
38807746
D		 5594 u32 pcbr;
5595 int pctx_size = 32*1024;
5596
38807746
D		 5597 pcbr = I915_READ(VLV_PCBR);
5598 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5599 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5600 paddr = (dev_priv->mm.stolen_base +
62106b4f 5601 (ggtt->stolen_size - pctx_size));
38807746
D		 5602
5603 pctx_paddr = (paddr & (~4095));
5604 I915_WRITE(VLV_PCBR, pctx_paddr);
5605 }
ce611ef8
VS		 5606
5607 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5608}
5609
dc97997a 5610static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5611{
c9cddffc
JB		 5612 struct drm_i915_gem_object *pctx;
5613 unsigned long pctx_paddr;
5614 u32 pcbr;
5615 int pctx_size = 24*1024;
5616
dc97997a 5617 mutex_lock(&dev_priv->dev->struct_mutex);
17b0c1f7 5618
c9cddffc
JB		 5619 pcbr = I915_READ(VLV_PCBR);
5620 if (pcbr) {
5621 /* BIOS set it up already, grab the pre-alloc'd space */
5622 int pcbr_offset;
5623
5624 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5625 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5626 pcbr_offset,
190d6cd5 5627 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5628 pctx_size);
5629 goto out;
5630 }
5631
ce611ef8
VS		 5632 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5633
c9cddffc
JB		 5634 /*
5635 * From the Gunit register HAS:
5636 * The Gfx driver is expected to program this register and ensure
5637 * proper allocation within Gfx stolen memory. For example, this
5638 * register should be programmed such than the PCBR range does not
5639 * overlap with other ranges, such as the frame buffer, protected
5640 * memory, or any other relevant ranges.
5641 */
dc97997a 5642 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
c9cddffc
JB		 5643 if (!pctx) {
5644 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5645 goto out;
c9cddffc
JB		 5646 }
5647
5648 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5649 I915_WRITE(VLV_PCBR, pctx_paddr);
5650
5651out:
ce611ef8 5652 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5653 dev_priv->vlv_pctx = pctx;
dc97997a 5654 mutex_unlock(&dev_priv->dev->struct_mutex);
c9cddffc
JB		 5655}
5656
dc97997a 5657static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5658{
ae48434c
ID		 5659 if (WARN_ON(!dev_priv->vlv_pctx))
5660 return;
5661
ee504898 5662 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5663 dev_priv->vlv_pctx = NULL;
5664}
5665
c30fec65
VS		 5666static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5667{
5668 dev_priv->rps.gpll_ref_freq =
5669 vlv_get_cck_clock(dev_priv, "GPLL ref",
5670 CCK_GPLL_CLOCK_CONTROL,
5671 dev_priv->czclk_freq);
5672
5673 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5674 dev_priv->rps.gpll_ref_freq);
5675}
5676
dc97997a 5677static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5678{
2bb25c17 5679 u32 val;
4e80519e 5680
dc97997a 5681 valleyview_setup_pctx(dev_priv);
4e80519e 5682
c30fec65
VS		 5683 vlv_init_gpll_ref_freq(dev_priv);
5684
4e80519e
ID		 5685 mutex_lock(&dev_priv->rps.hw_lock);
5686
2bb25c17
VS		 5687 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5688 switch ((val >> 6) & 3) {
5689 case 0:
5690 case 1:
5691 dev_priv->mem_freq = 800;
5692 break;
5693 case 2:
5694 dev_priv->mem_freq = 1066;
5695 break;
5696 case 3:
5697 dev_priv->mem_freq = 1333;
5698 break;
5699 }
80b83b62 5700 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5701
4e80519e
ID		 5702 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5703 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5704 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5705 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5706 dev_priv->rps.max_freq);
5707
5708 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5709 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5710 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5711 dev_priv->rps.efficient_freq);
5712
f8f2b001
D		 5713 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5714 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5715 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5716 dev_priv->rps.rp1_freq);
5717
4e80519e
ID		 5718 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5719 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5720 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5721 dev_priv->rps.min_freq);
5722
aed242ff
CW		 5723 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5724
4e80519e
ID		 5725 /* Preserve min/max settings in case of re-init */
5726 if (dev_priv->rps.max_freq_softlimit == 0)
5727 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5728
5729 if (dev_priv->rps.min_freq_softlimit == 0)
5730 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5731
5732 mutex_unlock(&dev_priv->rps.hw_lock);
5733}
5734
dc97997a 5735static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5736{
2bb25c17 5737 u32 val;
2b6b3a09 5738
dc97997a 5739 cherryview_setup_pctx(dev_priv);
2b6b3a09 5740
c30fec65
VS		 5741 vlv_init_gpll_ref_freq(dev_priv);
5742
2b6b3a09
D		 5743 mutex_lock(&dev_priv->rps.hw_lock);
5744
a580516d 5745 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5746 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5747 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5748
2bb25c17 5749 switch ((val >> 2) & 0x7) {
2bb25c17 5750 case 3:
2bb25c17
VS		 5751 dev_priv->mem_freq = 2000;
5752 break;
bfa7df01 5753 default:
2bb25c17
VS		 5754 dev_priv->mem_freq = 1600;
5755 break;
5756 }
80b83b62 5757 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5758
2b6b3a09
D		 5759 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5760 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5761 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5762 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5763 dev_priv->rps.max_freq);
5764
5765 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5766 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5767 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5768 dev_priv->rps.efficient_freq);
5769
7707df4a
D		 5770 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5771 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5772 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5773 dev_priv->rps.rp1_freq);
5774
5b7c91b7
D		 5775 /* PUnit validated range is only [RPe, RP0] */
5776 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5777 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5778 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5779 dev_priv->rps.min_freq);
5780
1c14762d
VS		 5781 WARN_ONCE((dev_priv->rps.max_freq |
5782 dev_priv->rps.efficient_freq |
5783 dev_priv->rps.rp1_freq |
5784 dev_priv->rps.min_freq) & 1,
5785 "Odd GPU freq values\n");
5786
aed242ff
CW		 5787 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5788
2b6b3a09
D		 5789 /* Preserve min/max settings in case of re-init */
5790 if (dev_priv->rps.max_freq_softlimit == 0)
5791 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5792
5793 if (dev_priv->rps.min_freq_softlimit == 0)
5794 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5795
5796 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5797}
5798
dc97997a 5799static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5800{
dc97997a 5801 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5802}
5803
dc97997a 5804static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5805{
e2f80391 5806 struct intel_engine_cs *engine;
2b6b3a09 5807 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5808
5809 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5810
297b32ec
VS		 5811 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5812 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5813 if (gtfifodbg) {
5814 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5815 gtfifodbg);
5816 I915_WRITE(GTFIFODBG, gtfifodbg);
5817 }
5818
5819 cherryview_check_pctx(dev_priv);
5820
5821 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5822 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5823 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5824
160614a2
VS		 5825 /* Disable RC states. */
5826 I915_WRITE(GEN6_RC_CONTROL, 0);
5827
38807746
D		 5828 /* 2a: Program RC6 thresholds.*/
5829 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5830 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5831 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5832
b4ac5afc 5833 for_each_engine(engine, dev_priv)
e2f80391 5834 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5835 I915_WRITE(GEN6_RC_SLEEP, 0);
5836
f4f71c7d
D		 5837 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5838 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5839
5840 /* allows RC6 residency counter to work */
5841 I915_WRITE(VLV_COUNTER_CONTROL,
5842 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5843 VLV_MEDIA_RC6_COUNT_EN |
5844 VLV_RENDER_RC6_COUNT_EN));
5845
5846 /* For now we assume BIOS is allocating and populating the PCBR */
5847 pcbr = I915_READ(VLV_PCBR);
5848
38807746 5849 /* 3: Enable RC6 */
dc97997a
CW		 5850 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5851 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5852 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5853
5854 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5855
2b6b3a09 5856 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5857 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5858 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5859 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5860 I915_WRITE(GEN6_RP_UP_EI, 66000);
5861 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5862
5863 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5864
5865 /* 5: Enable RPS */
5866 I915_WRITE(GEN6_RP_CONTROL,
5867 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5868 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5869 GEN6_RP_ENABLE |
5870 GEN6_RP_UP_BUSY_AVG |
5871 GEN6_RP_DOWN_IDLE_AVG);
5872
3ef62342
D		 5873 /* Setting Fixed Bias */
5874 val = VLV_OVERRIDE_EN |
5875 VLV_SOC_TDP_EN |
5876 CHV_BIAS_CPU_50_SOC_50;
5877 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5878
2b6b3a09
D		 5879 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5880
8d40c3ae
VS		 5881 /* RPS code assumes GPLL is used */
5882 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5883
742f491d 5884 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5885 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5886
5887 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5888 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5889 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5890 dev_priv->rps.cur_freq);
5891
5892 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5893 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5894 dev_priv->rps.idle_freq);
2b6b3a09 5895
dc97997a 5896 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b6b3a09 5897
59bad947 5898 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5899}
5900
dc97997a 5901static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 5902{
e2f80391 5903 struct intel_engine_cs *engine;
2a5913a8 5904 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5905
5906 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5907
ae48434c
ID		 5908 valleyview_check_pctx(dev_priv);
5909
297b32ec
VS		 5910 gtfifodbg = I915_READ(GTFIFODBG);
5911 if (gtfifodbg) {
f7d85c1e
JB		 5912 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5913 gtfifodbg);
0a073b84
JB		 5914 I915_WRITE(GTFIFODBG, gtfifodbg);
5915 }
5916
c8d9a590 5917 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5918 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5919
160614a2
VS		 5920 /* Disable RC states. */
5921 I915_WRITE(GEN6_RC_CONTROL, 0);
5922
cad725fe 5923 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5924 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5925 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5926 I915_WRITE(GEN6_RP_UP_EI, 66000);
5927 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5928
5929 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5930
5931 I915_WRITE(GEN6_RP_CONTROL,
5932 GEN6_RP_MEDIA_TURBO |
5933 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5934 GEN6_RP_MEDIA_IS_GFX |
5935 GEN6_RP_ENABLE |
5936 GEN6_RP_UP_BUSY_AVG |
5937 GEN6_RP_DOWN_IDLE_CONT);
5938
5939 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5940 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5941 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5942
b4ac5afc 5943 for_each_engine(engine, dev_priv)
e2f80391 5944 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5945
2f0aa304 5946 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5947
5948 /* allows RC6 residency counter to work */
49798eb2 5949 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5950 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5951 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5952 VLV_MEDIA_RC6_COUNT_EN |
5953 VLV_RENDER_RC6_COUNT_EN));
31685c25 5954
dc97997a 5955 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 5956 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 5957
dc97997a 5958 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 5959
a2b23fe0 5960 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5961
3ef62342
D		 5962 /* Setting Fixed Bias */
5963 val = VLV_OVERRIDE_EN |
5964 VLV_SOC_TDP_EN |
5965 VLV_BIAS_CPU_125_SOC_875;
5966 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5967
64936258 5968 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5969
8d40c3ae
VS		 5970 /* RPS code assumes GPLL is used */
5971 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5972
742f491d 5973 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5974 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5975
b39fb297 5976 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5977 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5978 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5979 dev_priv->rps.cur_freq);
0a073b84 5980
73008b98 5981 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5982 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5983 dev_priv->rps.idle_freq);
0a073b84 5984
dc97997a 5985 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
0a073b84 5986
59bad947 5987 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5988}
5989
dde18883
ED		 5990static unsigned long intel_pxfreq(u32 vidfreq)
5991{
5992 unsigned long freq;
5993 int div = (vidfreq & 0x3f0000) >> 16;
5994 int post = (vidfreq & 0x3000) >> 12;
5995 int pre = (vidfreq & 0x7);
5996
5997 if (!pre)
5998 return 0;
5999
6000 freq = ((div * 133333) / ((1<<post) * pre));
6001
6002 return freq;
6003}
6004
eb48eb00
DV		 6005static const struct cparams {
6006 u16 i;
6007 u16 t;
6008 u16 m;
6009 u16 c;
6010} cparams[] = {
6011 { 1, 1333, 301, 28664 },
6012 { 1, 1066, 294, 24460 },
6013 { 1, 800, 294, 25192 },
6014 { 0, 1333, 276, 27605 },
6015 { 0, 1066, 276, 27605 },
6016 { 0, 800, 231, 23784 },
6017};
6018
f531dcb2 6019static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6020{
6021 u64 total_count, diff, ret;
6022 u32 count1, count2, count3, m = 0, c = 0;
6023 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6024 int i;
6025
02d71956
DV		 6026 assert_spin_locked(&mchdev_lock);
6027
20e4d407 6028 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6029
6030 /* Prevent division-by-zero if we are asking too fast.
6031 * Also, we don't get interesting results if we are polling
6032 * faster than once in 10ms, so just return the saved value
6033 * in such cases.
6034 */
6035 if (diff1 <= 10)
20e4d407 6036 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6037
6038 count1 = I915_READ(DMIEC);
6039 count2 = I915_READ(DDREC);
6040 count3 = I915_READ(CSIEC);
6041
6042 total_count = count1 + count2 + count3;
6043
6044 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6045 if (total_count < dev_priv->ips.last_count1) {
6046 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6047 diff += total_count;
6048 } else {
20e4d407 6049 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6050 }
6051
6052 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6053 if (cparams[i].i == dev_priv->ips.c_m &&
6054 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6055 m = cparams[i].m;
6056 c = cparams[i].c;
6057 break;
6058 }
6059 }
6060
6061 diff = div_u64(diff, diff1);
6062 ret = ((m * diff) + c);
6063 ret = div_u64(ret, 10);
6064
20e4d407
DV		 6065 dev_priv->ips.last_count1 = total_count;
6066 dev_priv->ips.last_time1 = now;
eb48eb00 6067
20e4d407 6068 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6069
6070 return ret;
6071}
6072
f531dcb2
CW		 6073unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6074{
6075 unsigned long val;
6076
dc97997a 6077 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6078 return 0;
6079
6080 spin_lock_irq(&mchdev_lock);
6081
6082 val = __i915_chipset_val(dev_priv);
6083
6084 spin_unlock_irq(&mchdev_lock);
6085
6086 return val;
6087}
6088
eb48eb00
DV		 6089unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6090{
6091 unsigned long m, x, b;
6092 u32 tsfs;
6093
6094 tsfs = I915_READ(TSFS);
6095
6096 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6097 x = I915_READ8(TR1);
6098
6099 b = tsfs & TSFS_INTR_MASK;
6100
6101 return ((m * x) / 127) - b;
6102}
6103
d972d6ee
MK		 6104static int _pxvid_to_vd(u8 pxvid)
6105{
6106 if (pxvid == 0)
6107 return 0;
6108
6109 if (pxvid >= 8 && pxvid < 31)
6110 pxvid = 31;
6111
6112 return (pxvid + 2) * 125;
6113}
6114
6115static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6116{
d972d6ee
MK		 6117 const int vd = _pxvid_to_vd(pxvid);
6118 const int vm = vd - 1125;
6119
dc97997a 6120 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6121 return vm > 0 ? vm : 0;
6122
6123 return vd;
eb48eb00
DV		 6124}
6125
02d71956 6126static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6127{
5ed0bdf2 6128 u64 now, diff, diffms;
eb48eb00
DV		 6129 u32 count;
6130
02d71956 6131 assert_spin_locked(&mchdev_lock);
eb48eb00 6132
5ed0bdf2
TG		 6133 now = ktime_get_raw_ns();
6134 diffms = now - dev_priv->ips.last_time2;
6135 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6136
6137 /* Don't divide by 0 */
eb48eb00
DV		 6138 if (!diffms)
6139 return;
6140
6141 count = I915_READ(GFXEC);
6142
20e4d407
DV		 6143 if (count < dev_priv->ips.last_count2) {
6144 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6145 diff += count;
6146 } else {
20e4d407 6147 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6148 }
6149
20e4d407
DV		 6150 dev_priv->ips.last_count2 = count;
6151 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6152
6153 /* More magic constants... */
6154 diff = diff * 1181;
6155 diff = div_u64(diff, diffms * 10);
20e4d407 6156 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6157}
6158
02d71956
DV		 6159void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6160{
dc97997a 6161 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6162 return;
6163
9270388e 6164 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6165
6166 __i915_update_gfx_val(dev_priv);
6167
9270388e 6168 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6169}
6170
f531dcb2 6171static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6172{
6173 unsigned long t, corr, state1, corr2, state2;
6174 u32 pxvid, ext_v;
6175
02d71956
DV		 6176 assert_spin_locked(&mchdev_lock);
6177
616847e7 6178 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6179 pxvid = (pxvid >> 24) & 0x7f;
6180 ext_v = pvid_to_extvid(dev_priv, pxvid);
6181
6182 state1 = ext_v;
6183
6184 t = i915_mch_val(dev_priv);
6185
6186 /* Revel in the empirically derived constants */
6187
6188 /* Correction factor in 1/100000 units */
6189 if (t > 80)
6190 corr = ((t * 2349) + 135940);
6191 else if (t >= 50)
6192 corr = ((t * 964) + 29317);
6193 else /* < 50 */
6194 corr = ((t * 301) + 1004);
6195
6196 corr = corr * ((150142 * state1) / 10000 - 78642);
6197 corr /= 100000;
20e4d407 6198 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6199
6200 state2 = (corr2 * state1) / 10000;
6201 state2 /= 100; /* convert to mW */
6202
02d71956 6203 __i915_update_gfx_val(dev_priv);
eb48eb00 6204
20e4d407 6205 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6206}
6207
f531dcb2
CW		 6208unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6209{
6210 unsigned long val;
6211
dc97997a 6212 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6213 return 0;
6214
6215 spin_lock_irq(&mchdev_lock);
6216
6217 val = __i915_gfx_val(dev_priv);
6218
6219 spin_unlock_irq(&mchdev_lock);
6220
6221 return val;
6222}
6223
eb48eb00
DV		 6224/**
6225 * i915_read_mch_val - return value for IPS use
6226 *
6227 * Calculate and return a value for the IPS driver to use when deciding whether
6228 * we have thermal and power headroom to increase CPU or GPU power budget.
6229 */
6230unsigned long i915_read_mch_val(void)
6231{
6232 struct drm_i915_private *dev_priv;
6233 unsigned long chipset_val, graphics_val, ret = 0;
6234
9270388e 6235 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6236 if (!i915_mch_dev)
6237 goto out_unlock;
6238 dev_priv = i915_mch_dev;
6239
f531dcb2
CW		 6240 chipset_val = __i915_chipset_val(dev_priv);
6241 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6242
6243 ret = chipset_val + graphics_val;
6244
6245out_unlock:
9270388e 6246 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6247
6248 return ret;
6249}
6250EXPORT_SYMBOL_GPL(i915_read_mch_val);
6251
6252/**
6253 * i915_gpu_raise - raise GPU frequency limit
6254 *
6255 * Raise the limit; IPS indicates we have thermal headroom.
6256 */
6257bool i915_gpu_raise(void)
6258{
6259 struct drm_i915_private *dev_priv;
6260 bool ret = true;
6261
9270388e 6262 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6263 if (!i915_mch_dev) {
6264 ret = false;
6265 goto out_unlock;
6266 }
6267 dev_priv = i915_mch_dev;
6268
20e4d407
DV		 6269 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6270 dev_priv->ips.max_delay--;
eb48eb00
DV		 6271
6272out_unlock:
9270388e 6273 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6274
6275 return ret;
6276}
6277EXPORT_SYMBOL_GPL(i915_gpu_raise);
6278
6279/**
6280 * i915_gpu_lower - lower GPU frequency limit
6281 *
6282 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6283 * frequency maximum.
6284 */
6285bool i915_gpu_lower(void)
6286{
6287 struct drm_i915_private *dev_priv;
6288 bool ret = true;
6289
9270388e 6290 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6291 if (!i915_mch_dev) {
6292 ret = false;
6293 goto out_unlock;
6294 }
6295 dev_priv = i915_mch_dev;
6296
20e4d407
DV		 6297 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6298 dev_priv->ips.max_delay++;
eb48eb00
DV		 6299
6300out_unlock:
9270388e 6301 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6302
6303 return ret;
6304}
6305EXPORT_SYMBOL_GPL(i915_gpu_lower);
6306
6307/**
6308 * i915_gpu_busy - indicate GPU business to IPS
6309 *
6310 * Tell the IPS driver whether or not the GPU is busy.
6311 */
6312bool i915_gpu_busy(void)
6313{
6314 struct drm_i915_private *dev_priv;
e2f80391 6315 struct intel_engine_cs *engine;
eb48eb00
DV		 6316 bool ret = false;
6317
9270388e 6318 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6319 if (!i915_mch_dev)
6320 goto out_unlock;
6321 dev_priv = i915_mch_dev;
6322
b4ac5afc 6323 for_each_engine(engine, dev_priv)
e2f80391 6324 ret |= !list_empty(&engine->request_list);
eb48eb00
DV		 6325
6326out_unlock:
9270388e 6327 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6328
6329 return ret;
6330}
6331EXPORT_SYMBOL_GPL(i915_gpu_busy);
6332
6333/**
6334 * i915_gpu_turbo_disable - disable graphics turbo
6335 *
6336 * Disable graphics turbo by resetting the max frequency and setting the
6337 * current frequency to the default.
6338 */
6339bool i915_gpu_turbo_disable(void)
6340{
6341 struct drm_i915_private *dev_priv;
6342 bool ret = true;
6343
9270388e 6344 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6345 if (!i915_mch_dev) {
6346 ret = false;
6347 goto out_unlock;
6348 }
6349 dev_priv = i915_mch_dev;
6350
20e4d407 6351 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6352
91d14251 6353 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6354 ret = false;
6355
6356out_unlock:
9270388e 6357 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6358
6359 return ret;
6360}
6361EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6362
6363/**
6364 * Tells the intel_ips driver that the i915 driver is now loaded, if
6365 * IPS got loaded first.
6366 *
6367 * This awkward dance is so that neither module has to depend on the
6368 * other in order for IPS to do the appropriate communication of
6369 * GPU turbo limits to i915.
6370 */
6371static void
6372ips_ping_for_i915_load(void)
6373{
6374 void (*link)(void);
6375
6376 link = symbol_get(ips_link_to_i915_driver);
6377 if (link) {
6378 link();
6379 symbol_put(ips_link_to_i915_driver);
6380 }
6381}
6382
6383void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6384{
02d71956
DV		 6385 /* We only register the i915 ips part with intel-ips once everything is
6386 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6387 spin_lock_irq(&mchdev_lock);
eb48eb00 6388 i915_mch_dev = dev_priv;
9270388e 6389 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6390
6391 ips_ping_for_i915_load();
6392}
6393
6394void intel_gpu_ips_teardown(void)
6395{
9270388e 6396 spin_lock_irq(&mchdev_lock);
eb48eb00 6397 i915_mch_dev = NULL;
9270388e 6398 spin_unlock_irq(&mchdev_lock);
eb48eb00 6399}
76c3552f 6400
dc97997a 6401static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6402{
dde18883
ED		 6403 u32 lcfuse;
6404 u8 pxw[16];
6405 int i;
6406
6407 /* Disable to program */
6408 I915_WRITE(ECR, 0);
6409 POSTING_READ(ECR);
6410
6411 /* Program energy weights for various events */
6412 I915_WRITE(SDEW, 0x15040d00);
6413 I915_WRITE(CSIEW0, 0x007f0000);
6414 I915_WRITE(CSIEW1, 0x1e220004);
6415 I915_WRITE(CSIEW2, 0x04000004);
6416
6417 for (i = 0; i < 5; i++)
616847e7 6418 I915_WRITE(PEW(i), 0);
dde18883 6419 for (i = 0; i < 3; i++)
616847e7 6420 I915_WRITE(DEW(i), 0);
dde18883
ED		 6421
6422 /* Program P-state weights to account for frequency power adjustment */
6423 for (i = 0; i < 16; i++) {
616847e7 6424 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6425 unsigned long freq = intel_pxfreq(pxvidfreq);
6426 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6427 PXVFREQ_PX_SHIFT;
6428 unsigned long val;
6429
6430 val = vid * vid;
6431 val *= (freq / 1000);
6432 val *= 255;
6433 val /= (127*127*900);
6434 if (val > 0xff)
6435 DRM_ERROR("bad pxval: %ld\n", val);
6436 pxw[i] = val;
6437 }
6438 /* Render standby states get 0 weight */
6439 pxw[14] = 0;
6440 pxw[15] = 0;
6441
6442 for (i = 0; i < 4; i++) {
6443 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6444 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6445 I915_WRITE(PXW(i), val);
dde18883
ED		 6446 }
6447
6448 /* Adjust magic regs to magic values (more experimental results) */
6449 I915_WRITE(OGW0, 0);
6450 I915_WRITE(OGW1, 0);
6451 I915_WRITE(EG0, 0x00007f00);
6452 I915_WRITE(EG1, 0x0000000e);
6453 I915_WRITE(EG2, 0x000e0000);
6454 I915_WRITE(EG3, 0x68000300);
6455 I915_WRITE(EG4, 0x42000000);
6456 I915_WRITE(EG5, 0x00140031);
6457 I915_WRITE(EG6, 0);
6458 I915_WRITE(EG7, 0);
6459
6460 for (i = 0; i < 8; i++)
616847e7 6461 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6462
6463 /* Enable PMON + select events */
6464 I915_WRITE(ECR, 0x80000019);
6465
6466 lcfuse = I915_READ(LCFUSE02);
6467
20e4d407 6468 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6469}
6470
dc97997a 6471void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6472{
b268c699
ID		 6473 /*
6474 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6475 * requirement.
6476 */
6477 if (!i915.enable_rc6) {
6478 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6479 intel_runtime_pm_get(dev_priv);
6480 }
e6069ca8 6481
dc97997a
CW		 6482 if (IS_CHERRYVIEW(dev_priv))
6483 cherryview_init_gt_powersave(dev_priv);
6484 else if (IS_VALLEYVIEW(dev_priv))
6485 valleyview_init_gt_powersave(dev_priv);
ae48434c
ID		 6486}
6487
dc97997a 6488void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6489{
dc97997a 6490 if (IS_CHERRYVIEW(dev_priv))
38807746 6491 return;
dc97997a
CW		 6492 else if (IS_VALLEYVIEW(dev_priv))
6493 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6494
6495 if (!i915.enable_rc6)
6496 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6497}
6498
91d14251 6499static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
dbea3cea 6500{
dbea3cea
ID		 6501 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6502
91d14251 6503 gen6_disable_rps_interrupts(dev_priv);
dbea3cea
ID		 6504}
6505
156c7ca0
JB		 6506/**
6507 * intel_suspend_gt_powersave - suspend PM work and helper threads
dc97997a 6508 * @dev_priv: i915 device
156c7ca0
JB		 6509 *
6510 * We don't want to disable RC6 or other features here, we just want
6511 * to make sure any work we've queued has finished and won't bother
6512 * us while we're suspended.
6513 */
dc97997a 6514void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
156c7ca0 6515{
91d14251 6516 if (INTEL_GEN(dev_priv) < 6)
d4d70aa5
ID		 6517 return;
6518
91d14251 6519 gen6_suspend_rps(dev_priv);
b47adc17
D		 6520
6521 /* Force GPU to min freq during suspend */
6522 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6523}
6524
dc97997a 6525void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6526{
dc97997a 6527 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6528 ironlake_disable_drps(dev_priv);
dc97997a
CW		 6529 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6530 intel_suspend_gt_powersave(dev_priv);
e494837a 6531
4fc688ce 6532 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6533 if (INTEL_INFO(dev_priv)->gen >= 9) {
6534 gen9_disable_rc6(dev_priv);
6535 gen9_disable_rps(dev_priv);
6536 } else if (IS_CHERRYVIEW(dev_priv))
6537 cherryview_disable_rps(dev_priv);
6538 else if (IS_VALLEYVIEW(dev_priv))
6539 valleyview_disable_rps(dev_priv);
d20d4f0c 6540 else
dc97997a 6541 gen6_disable_rps(dev_priv);
e534770a 6542
c0951f0c 6543 dev_priv->rps.enabled = false;
4fc688ce 6544 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6545 }
8090c6b9
DV		 6546}
6547
1a01ab3b
JB		 6548static void intel_gen6_powersave_work(struct work_struct *work)
6549{
6550 struct drm_i915_private *dev_priv =
6551 container_of(work, struct drm_i915_private,
6552 rps.delayed_resume_work.work);
1a01ab3b 6553
4fc688ce 6554 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6555
dc97997a
CW		 6556 gen6_reset_rps_interrupts(dev_priv);
6557
6558 if (IS_CHERRYVIEW(dev_priv)) {
6559 cherryview_enable_rps(dev_priv);
6560 } else if (IS_VALLEYVIEW(dev_priv)) {
6561 valleyview_enable_rps(dev_priv);
6562 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6563 gen9_enable_rc6(dev_priv);
6564 gen9_enable_rps(dev_priv);
6565 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6566 __gen6_update_ring_freq(dev_priv);
6567 } else if (IS_BROADWELL(dev_priv)) {
6568 gen8_enable_rps(dev_priv);
6569 __gen6_update_ring_freq(dev_priv);
0a073b84 6570 } else {
dc97997a
CW		 6571 gen6_enable_rps(dev_priv);
6572 __gen6_update_ring_freq(dev_priv);
0a073b84 6573 }
aed242ff
CW		 6574
6575 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6576 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6577
6578 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6579 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6580
c0951f0c 6581 dev_priv->rps.enabled = true;
3cc134e3 6582
91d14251 6583 gen6_enable_rps_interrupts(dev_priv);
3cc134e3 6584
4fc688ce 6585 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6586
6587 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6588}
6589
dc97997a 6590void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6591{
f61018b1 6592 /* Powersaving is controlled by the host when inside a VM */
c033666a 6593 if (intel_vgpu_active(dev_priv))
f61018b1
YZ		 6594 return;
6595
dc97997a 6596 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6597 ironlake_enable_drps(dev_priv);
dc97997a
CW		 6598 mutex_lock(&dev_priv->dev->struct_mutex);
6599 intel_init_emon(dev_priv);
6600 mutex_unlock(&dev_priv->dev->struct_mutex);
6601 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
1a01ab3b
JB		 6602 /*
6603 * PCU communication is slow and this doesn't need to be
6604 * done at any specific time, so do this out of our fast path
6605 * to make resume and init faster.
c6df39b5
ID		 6606 *
6607 * We depend on the HW RC6 power context save/restore
6608 * mechanism when entering D3 through runtime PM suspend. So
6609 * disable RPM until RPS/RC6 is properly setup. We can only
6610 * get here via the driver load/system resume/runtime resume
6611 * paths, so the _noresume version is enough (and in case of
6612 * runtime resume it's necessary).
1a01ab3b 6613 */
c6df39b5
ID		 6614 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6615 round_jiffies_up_relative(HZ)))
6616 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6617 }
6618}
6619
dc97997a 6620void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
c6df39b5 6621{
dc97997a 6622 if (INTEL_INFO(dev_priv)->gen < 6)
dbea3cea
ID		 6623 return;
6624
91d14251 6625 gen6_suspend_rps(dev_priv);
c6df39b5 6626 dev_priv->rps.enabled = false;
c6df39b5
ID		 6627}
6628
3107bd48
DV		 6629static void ibx_init_clock_gating(struct drm_device *dev)
6630{
6631 struct drm_i915_private *dev_priv = dev->dev_private;
6632
6633 /*
6634 * On Ibex Peak and Cougar Point, we need to disable clock
6635 * gating for the panel power sequencer or it will fail to
6636 * start up when no ports are active.
6637 */
6638 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6639}
6640
0e088b8f
VS		 6641static void g4x_disable_trickle_feed(struct drm_device *dev)
6642{
6643 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6644 enum pipe pipe;
0e088b8f 6645
055e393f 6646 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6647 I915_WRITE(DSPCNTR(pipe),
6648 I915_READ(DSPCNTR(pipe)) |
6649 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6650
6651 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6652 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6653 }
6654}
6655
017636cc
VS		 6656static void ilk_init_lp_watermarks(struct drm_device *dev)
6657{
6658 struct drm_i915_private *dev_priv = dev->dev_private;
6659
6660 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6661 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6662 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6663
6664 /*
6665 * Don't touch WM1S_LP_EN here.
6666 * Doing so could cause underruns.
6667 */
6668}
6669
1fa61106 6670static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6671{
6672 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6673 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6674
f1e8fa56
DL		 6675 /*
6676 * Required for FBC
6677 * WaFbcDisableDpfcClockGating:ilk
6678 */
4d47e4f5
DL		 6679 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6680 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6681 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6682
6683 I915_WRITE(PCH_3DCGDIS0,
6684 MARIUNIT_CLOCK_GATE_DISABLE |
6685 SVSMUNIT_CLOCK_GATE_DISABLE);
6686 I915_WRITE(PCH_3DCGDIS1,
6687 VFMUNIT_CLOCK_GATE_DISABLE);
6688
6f1d69b0
ED		 6689 /*
6690 * According to the spec the following bits should be set in
6691 * order to enable memory self-refresh
6692 * The bit 22/21 of 0x42004
6693 * The bit 5 of 0x42020
6694 * The bit 15 of 0x45000
6695 */
6696 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6697 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6698 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6699 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6700 I915_WRITE(DISP_ARB_CTL,
6701 (I915_READ(DISP_ARB_CTL) |
6702 DISP_FBC_WM_DIS));
017636cc
VS		 6703
6704 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6705
6706 /*
6707 * Based on the document from hardware guys the following bits
6708 * should be set unconditionally in order to enable FBC.
6709 * The bit 22 of 0x42000
6710 * The bit 22 of 0x42004
6711 * The bit 7,8,9 of 0x42020.
6712 */
6713 if (IS_IRONLAKE_M(dev)) {
4bb35334 6714 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6715 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6716 I915_READ(ILK_DISPLAY_CHICKEN1) |
6717 ILK_FBCQ_DIS);
6718 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6719 I915_READ(ILK_DISPLAY_CHICKEN2) |
6720 ILK_DPARB_GATE);
6f1d69b0
ED		 6721 }
6722
4d47e4f5
DL		 6723 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6724
6f1d69b0
ED		 6725 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6726 I915_READ(ILK_DISPLAY_CHICKEN2) |
6727 ILK_ELPIN_409_SELECT);
6728 I915_WRITE(_3D_CHICKEN2,
6729 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6730 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6731
ecdb4eb7 6732 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6733 I915_WRITE(CACHE_MODE_0,
6734 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6735
4e04632e
AG		 6736 /* WaDisable_RenderCache_OperationalFlush:ilk */
6737 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6738
0e088b8f 6739 g4x_disable_trickle_feed(dev);
bdad2b2f 6740
3107bd48
DV		 6741 ibx_init_clock_gating(dev);
6742}
6743
6744static void cpt_init_clock_gating(struct drm_device *dev)
6745{
6746 struct drm_i915_private *dev_priv = dev->dev_private;
6747 int pipe;
3f704fa2 6748 uint32_t val;
3107bd48
DV		 6749
6750 /*
6751 * On Ibex Peak and Cougar Point, we need to disable clock
6752 * gating for the panel power sequencer or it will fail to
6753 * start up when no ports are active.
6754 */
cd664078
JB		 6755 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6756 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6757 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6758 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6759 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6760 /* The below fixes the weird display corruption, a few pixels shifted
6761 * downward, on (only) LVDS of some HP laptops with IVY.
6762 */
055e393f 6763 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6764 val = I915_READ(TRANS_CHICKEN2(pipe));
6765 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6766 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6767 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6768 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6769 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6770 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6771 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6772 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6773 }
3107bd48 6774 /* WADP0ClockGatingDisable */
055e393f 6775 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6776 I915_WRITE(TRANS_CHICKEN1(pipe),
6777 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6778 }
6f1d69b0
ED		 6779}
6780
1d7aaa0c
DV		 6781static void gen6_check_mch_setup(struct drm_device *dev)
6782{
6783 struct drm_i915_private *dev_priv = dev->dev_private;
6784 uint32_t tmp;
6785
6786 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6787 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6788 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6789 tmp);
1d7aaa0c
DV		 6790}
6791
1fa61106 6792static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6793{
6794 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6795 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6796
231e54f6 6797 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6798
6799 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6800 I915_READ(ILK_DISPLAY_CHICKEN2) |
6801 ILK_ELPIN_409_SELECT);
6802
ecdb4eb7 6803 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6804 I915_WRITE(_3D_CHICKEN,
6805 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6806
4e04632e
AG		 6807 /* WaDisable_RenderCache_OperationalFlush:snb */
6808 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6809
8d85d272
VS		 6810 /*
6811 * BSpec recoomends 8x4 when MSAA is used,
6812 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6813 *
6814 * Note that PS/WM thread counts depend on the WIZ hashing
6815 * disable bit, which we don't touch here, but it's good
6816 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6817 */
6818 I915_WRITE(GEN6_GT_MODE,
98533251 6819 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6820
017636cc 6821 ilk_init_lp_watermarks(dev);
6f1d69b0 6822
6f1d69b0 6823 I915_WRITE(CACHE_MODE_0,
50743298 6824 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6825
6826 I915_WRITE(GEN6_UCGCTL1,
6827 I915_READ(GEN6_UCGCTL1) |
6828 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6829 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6830
6831 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6832 * gating disable must be set. Failure to set it results in
6833 * flickering pixels due to Z write ordering failures after
6834 * some amount of runtime in the Mesa "fire" demo, and Unigine
6835 * Sanctuary and Tropics, and apparently anything else with
6836 * alpha test or pixel discard.
6837 *
6838 * According to the spec, bit 11 (RCCUNIT) must also be set,
6839 * but we didn't debug actual testcases to find it out.
0f846f81 6840 *
ef59318c
VS		 6841 * WaDisableRCCUnitClockGating:snb
6842 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6843 */
6844 I915_WRITE(GEN6_UCGCTL2,
6845 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6846 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6847
5eb146dd 6848 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6849 I915_WRITE(_3D_CHICKEN3,
6850 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6851
e927ecde
VS		 6852 /*
6853 * Bspec says:
6854 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6855 * 3DSTATE_SF number of SF output attributes is more than 16."
6856 */
6857 I915_WRITE(_3D_CHICKEN3,
6858 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6859
6f1d69b0
ED		 6860 /*
6861 * According to the spec the following bits should be
6862 * set in order to enable memory self-refresh and fbc:
6863 * The bit21 and bit22 of 0x42000
6864 * The bit21 and bit22 of 0x42004
6865 * The bit5 and bit7 of 0x42020
6866 * The bit14 of 0x70180
6867 * The bit14 of 0x71180
4bb35334
DL		 6868 *
6869 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6870 */
6871 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6872 I915_READ(ILK_DISPLAY_CHICKEN1) |
6873 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6874 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6875 I915_READ(ILK_DISPLAY_CHICKEN2) |
6876 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6877 I915_WRITE(ILK_DSPCLK_GATE_D,
6878 I915_READ(ILK_DSPCLK_GATE_D) |
6879 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6880 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6881
0e088b8f 6882 g4x_disable_trickle_feed(dev);
f8f2ac9a 6883
3107bd48 6884 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6885
6886 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6887}
6888
6889static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6890{
6891 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6892
3aad9059 6893 /*
46680e0a 6894 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6895 *
6896 * This actually overrides the dispatch
6897 * mode for all thread types.
6898 */
6f1d69b0
ED		 6899 reg &= ~GEN7_FF_SCHED_MASK;
6900 reg |= GEN7_FF_TS_SCHED_HW;
6901 reg |= GEN7_FF_VS_SCHED_HW;
6902 reg |= GEN7_FF_DS_SCHED_HW;
6903
6904 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6905}
6906
17a303ec
PZ		 6907static void lpt_init_clock_gating(struct drm_device *dev)
6908{
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910
6911 /*
6912 * TODO: this bit should only be enabled when really needed, then
6913 * disabled when not needed anymore in order to save power.
6914 */
c2699524 6915 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6916 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6917 I915_READ(SOUTH_DSPCLK_GATE_D) |
6918 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6919
6920 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6921 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6922 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6923 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6924}
6925
7d708ee4
ID		 6926static void lpt_suspend_hw(struct drm_device *dev)
6927{
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6929
c2699524 6930 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6931 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6932
6933 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6934 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6935 }
6936}
6937
450174fe
ID		 6938static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6939 int general_prio_credits,
6940 int high_prio_credits)
6941{
6942 u32 misccpctl;
6943
6944 /* WaTempDisableDOPClkGating:bdw */
6945 misccpctl = I915_READ(GEN7_MISCCPCTL);
6946 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6947
6948 I915_WRITE(GEN8_L3SQCREG1,
6949 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6950 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6951
6952 /*
6953 * Wait at least 100 clocks before re-enabling clock gating.
6954 * See the definition of L3SQCREG1 in BSpec.
6955 */
6956 POSTING_READ(GEN8_L3SQCREG1);
6957 udelay(1);
6958 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6959}
6960
dc00b6a0
DV		 6961static void skylake_init_clock_gating(struct drm_device *dev)
6962{
6963 struct drm_i915_private *dev_priv = dev->dev_private;
6964
6965 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */
6966 I915_WRITE(CHICKEN_PAR1_1,
6967 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
6968}
6969
47c2bd97 6970static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6971{
6972 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6973 enum pipe pipe;
1020a5c2 6974
7ad0dbab 6975 ilk_init_lp_watermarks(dev);
50ed5fbd 6976
ab57fff1 6977 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6978 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6979
ab57fff1 6980 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6981 I915_WRITE(CHICKEN_PAR1_1,
6982 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6983
ab57fff1 6984 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6985 for_each_pipe(dev_priv, pipe) {
07d27e20 6986 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6987 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6988 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6989 }
63801f21 6990
ab57fff1
BW		 6991 /* WaVSRefCountFullforceMissDisable:bdw */
6992 /* WaDSRefCountFullforceMissDisable:bdw */
6993 I915_WRITE(GEN7_FF_THREAD_MODE,
6994 I915_READ(GEN7_FF_THREAD_MODE) &
6995 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6996
295e8bb7
VS		 6997 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6998 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6999
7000 /* WaDisableSDEUnitClockGating:bdw */
7001 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7002 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7003
450174fe
ID		 7004 /* WaProgramL3SqcReg1Default:bdw */
7005 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7006
6d50b065
VS		 7007 /*
7008 * WaGttCachingOffByDefault:bdw
7009 * GTT cache may not work with big pages, so if those
7010 * are ever enabled GTT cache may need to be disabled.
7011 */
7012 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7013
89d6b2b8 7014 lpt_init_clock_gating(dev);
1020a5c2
BW		 7015}
7016
cad2a2d7
ED		 7017static void haswell_init_clock_gating(struct drm_device *dev)
7018{
7019 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 7020
017636cc 7021 ilk_init_lp_watermarks(dev);
cad2a2d7 7022
f3fc4884
FJ		 7023 /* L3 caching of data atomics doesn't work -- disable it. */
7024 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7025 I915_WRITE(HSW_ROW_CHICKEN3,
7026 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7027
ecdb4eb7 7028 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7029 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7030 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7031 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7032
e36ea7ff
VS		 7033 /* WaVSRefCountFullforceMissDisable:hsw */
7034 I915_WRITE(GEN7_FF_THREAD_MODE,
7035 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7036
4e04632e
AG		 7037 /* WaDisable_RenderCache_OperationalFlush:hsw */
7038 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7039
fe27c606
CW		 7040 /* enable HiZ Raw Stall Optimization */
7041 I915_WRITE(CACHE_MODE_0_GEN7,
7042 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7043
ecdb4eb7 7044 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7045 I915_WRITE(CACHE_MODE_1,
7046 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7047
a12c4967
VS		 7048 /*
7049 * BSpec recommends 8x4 when MSAA is used,
7050 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7051 *
7052 * Note that PS/WM thread counts depend on the WIZ hashing
7053 * disable bit, which we don't touch here, but it's good
7054 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7055 */
7056 I915_WRITE(GEN7_GT_MODE,
98533251 7057 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7058
94411593
KG		 7059 /* WaSampleCChickenBitEnable:hsw */
7060 I915_WRITE(HALF_SLICE_CHICKEN3,
7061 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7062
ecdb4eb7 7063 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7064 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7065
90a88643
PZ		 7066 /* WaRsPkgCStateDisplayPMReq:hsw */
7067 I915_WRITE(CHICKEN_PAR1_1,
7068 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7069
17a303ec 7070 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7071}
7072
1fa61106 7073static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7074{
7075 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 7076 uint32_t snpcr;
6f1d69b0 7077
017636cc 7078 ilk_init_lp_watermarks(dev);
6f1d69b0 7079
231e54f6 7080 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7081
ecdb4eb7 7082 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7083 I915_WRITE(_3D_CHICKEN3,
7084 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7085
ecdb4eb7 7086 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7087 I915_WRITE(IVB_CHICKEN3,
7088 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7089 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7090
ecdb4eb7 7091 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7092 if (IS_IVB_GT1(dev))
7093 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7094 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7095
4e04632e
AG		 7096 /* WaDisable_RenderCache_OperationalFlush:ivb */
7097 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7098
ecdb4eb7 7099 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7100 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7101 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7102
ecdb4eb7 7103 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7104 I915_WRITE(GEN7_L3CNTLREG1,
7105 GEN7_WA_FOR_GEN7_L3_CONTROL);
7106 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7107 GEN7_WA_L3_CHICKEN_MODE);
7108 if (IS_IVB_GT1(dev))
7109 I915_WRITE(GEN7_ROW_CHICKEN2,
7110 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7111 else {
7112 /* must write both registers */
7113 I915_WRITE(GEN7_ROW_CHICKEN2,
7114 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7115 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7116 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7117 }
6f1d69b0 7118
ecdb4eb7 7119 /* WaForceL3Serialization:ivb */
61939d97
JB		 7120 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7121 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7122
1b80a19a 7123 /*
0f846f81 7124 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7125 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7126 */
7127 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7128 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7129
ecdb4eb7 7130 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7131 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7132 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7133 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7134
0e088b8f 7135 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7136
7137 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7138
22721343
CW		 7139 if (0) { /* causes HiZ corruption on ivb:gt1 */
7140 /* enable HiZ Raw Stall Optimization */
7141 I915_WRITE(CACHE_MODE_0_GEN7,
7142 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7143 }
116f2b6d 7144
ecdb4eb7 7145 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7146 I915_WRITE(CACHE_MODE_1,
7147 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7148
a607c1a4
VS		 7149 /*
7150 * BSpec recommends 8x4 when MSAA is used,
7151 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7152 *
7153 * Note that PS/WM thread counts depend on the WIZ hashing
7154 * disable bit, which we don't touch here, but it's good
7155 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7156 */
7157 I915_WRITE(GEN7_GT_MODE,
98533251 7158 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7159
20848223
BW		 7160 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7161 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7162 snpcr |= GEN6_MBC_SNPCR_MED;
7163 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7164
ab5c608b
BW		 7165 if (!HAS_PCH_NOP(dev))
7166 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7167
7168 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7169}
7170
1fa61106 7171static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7172{
7173 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 7174
ecdb4eb7 7175 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7176 I915_WRITE(_3D_CHICKEN3,
7177 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7178
ecdb4eb7 7179 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7180 I915_WRITE(IVB_CHICKEN3,
7181 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7182 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7183
fad7d36e 7184 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7185 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7186 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7187 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7188 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7189
4e04632e
AG		 7190 /* WaDisable_RenderCache_OperationalFlush:vlv */
7191 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7192
ecdb4eb7 7193 /* WaForceL3Serialization:vlv */
61939d97
JB		 7194 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7195 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7196
ecdb4eb7 7197 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7198 I915_WRITE(GEN7_ROW_CHICKEN2,
7199 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7200
ecdb4eb7 7201 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7202 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7203 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7204 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7205
46680e0a
VS		 7206 gen7_setup_fixed_func_scheduler(dev_priv);
7207
3c0edaeb 7208 /*
0f846f81 7209 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7210 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7211 */
7212 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7213 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7214
c98f5062
AG		 7215 /* WaDisableL3Bank2xClockGate:vlv
7216 * Disabling L3 clock gating- MMIO 940c[25] = 1
7217 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7218 I915_WRITE(GEN7_UCGCTL4,
7219 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7220
afd58e79
VS		 7221 /*
7222 * BSpec says this must be set, even though
7223 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7224 */
6b26c86d
DV		 7225 I915_WRITE(CACHE_MODE_1,
7226 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7227
da2518f9
VS		 7228 /*
7229 * BSpec recommends 8x4 when MSAA is used,
7230 * however in practice 16x4 seems fastest.
7231 *
7232 * Note that PS/WM thread counts depend on the WIZ hashing
7233 * disable bit, which we don't touch here, but it's good
7234 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7235 */
7236 I915_WRITE(GEN7_GT_MODE,
7237 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7238
031994ee
VS		 7239 /*
7240 * WaIncreaseL3CreditsForVLVB0:vlv
7241 * This is the hardware default actually.
7242 */
7243 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7244
2d809570 7245 /*
ecdb4eb7 7246 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7247 * Disable clock gating on th GCFG unit to prevent a delay
7248 * in the reporting of vblank events.
7249 */
7a0d1eed 7250 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7251}
7252
a4565da8
VS		 7253static void cherryview_init_clock_gating(struct drm_device *dev)
7254{
7255 struct drm_i915_private *dev_priv = dev->dev_private;
7256
232ce337
VS		 7257 /* WaVSRefCountFullforceMissDisable:chv */
7258 /* WaDSRefCountFullforceMissDisable:chv */
7259 I915_WRITE(GEN7_FF_THREAD_MODE,
7260 I915_READ(GEN7_FF_THREAD_MODE) &
7261 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7262
7263 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7264 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7265 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7266
7267 /* WaDisableCSUnitClockGating:chv */
7268 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7269 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7270
7271 /* WaDisableSDEUnitClockGating:chv */
7272 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7273 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7274
450174fe
ID		 7275 /*
7276 * WaProgramL3SqcReg1Default:chv
7277 * See gfxspecs/Related Documents/Performance Guide/
7278 * LSQC Setting Recommendations.
7279 */
7280 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7281
6d50b065
VS		 7282 /*
7283 * GTT cache may not work with big pages, so if those
7284 * are ever enabled GTT cache may need to be disabled.
7285 */
7286 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7287}
7288
1fa61106 7289static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7290{
7291 struct drm_i915_private *dev_priv = dev->dev_private;
7292 uint32_t dspclk_gate;
7293
7294 I915_WRITE(RENCLK_GATE_D1, 0);
7295 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7296 GS_UNIT_CLOCK_GATE_DISABLE |
7297 CL_UNIT_CLOCK_GATE_DISABLE);
7298 I915_WRITE(RAMCLK_GATE_D, 0);
7299 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7300 OVRUNIT_CLOCK_GATE_DISABLE |
7301 OVCUNIT_CLOCK_GATE_DISABLE;
7302 if (IS_GM45(dev))
7303 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7304 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7305
7306 /* WaDisableRenderCachePipelinedFlush */
7307 I915_WRITE(CACHE_MODE_0,
7308 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7309
4e04632e
AG		 7310 /* WaDisable_RenderCache_OperationalFlush:g4x */
7311 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7312
0e088b8f 7313 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7314}
7315
1fa61106 7316static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7317{
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319
7320 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7321 I915_WRITE(RENCLK_GATE_D2, 0);
7322 I915_WRITE(DSPCLK_GATE_D, 0);
7323 I915_WRITE(RAMCLK_GATE_D, 0);
7324 I915_WRITE16(DEUC, 0);
20f94967
VS		 7325 I915_WRITE(MI_ARB_STATE,
7326 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7327
7328 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7329 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7330}
7331
1fa61106 7332static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7333{
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335
7336 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7337 I965_RCC_CLOCK_GATE_DISABLE |
7338 I965_RCPB_CLOCK_GATE_DISABLE |
7339 I965_ISC_CLOCK_GATE_DISABLE |
7340 I965_FBC_CLOCK_GATE_DISABLE);
7341 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7342 I915_WRITE(MI_ARB_STATE,
7343 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7344
7345 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7346 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7347}
7348
1fa61106 7349static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7350{
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 u32 dstate = I915_READ(D_STATE);
7353
7354 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7355 DSTATE_DOT_CLOCK_GATING;
7356 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7357
7358 if (IS_PINEVIEW(dev))
7359 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7360
7361 /* IIR "flip pending" means done if this bit is set */
7362 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7363
7364 /* interrupts should cause a wake up from C3 */
3299254f 7365 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7366
7367 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7368 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7369
7370 I915_WRITE(MI_ARB_STATE,
7371 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7372}
7373
1fa61106 7374static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7375{
7376 struct drm_i915_private *dev_priv = dev->dev_private;
7377
7378 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7379
7380 /* interrupts should cause a wake up from C3 */
7381 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7382 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7383
7384 I915_WRITE(MEM_MODE,
7385 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7386}
7387
1fa61106 7388static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7389{
7390 struct drm_i915_private *dev_priv = dev->dev_private;
7391
7392 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7393
7394 I915_WRITE(MEM_MODE,
7395 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7396 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7397}
7398
6f1d69b0
ED		 7399void intel_init_clock_gating(struct drm_device *dev)
7400{
7401 struct drm_i915_private *dev_priv = dev->dev_private;
7402
bb400da9 7403 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7404}
7405
7d708ee4
ID		 7406void intel_suspend_hw(struct drm_device *dev)
7407{
7408 if (HAS_PCH_LPT(dev))
7409 lpt_suspend_hw(dev);
7410}
7411
bb400da9
ID		 7412static void nop_init_clock_gating(struct drm_device *dev)
7413{
7414 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7415}
7416
7417/**
7418 * intel_init_clock_gating_hooks - setup the clock gating hooks
7419 * @dev_priv: device private
7420 *
7421 * Setup the hooks that configure which clocks of a given platform can be
7422 * gated and also apply various GT and display specific workarounds for these
7423 * platforms. Note that some GT specific workarounds are applied separately
7424 * when GPU contexts or batchbuffers start their execution.
7425 */
7426void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7427{
7428 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7429 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7430 else if (IS_KABYLAKE(dev_priv))
dc00b6a0 7431 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9
ID		 7432 else if (IS_BROXTON(dev_priv))
7433 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7434 else if (IS_BROADWELL(dev_priv))
7435 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7436 else if (IS_CHERRYVIEW(dev_priv))
7437 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7438 else if (IS_HASWELL(dev_priv))
7439 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7440 else if (IS_IVYBRIDGE(dev_priv))
7441 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7442 else if (IS_VALLEYVIEW(dev_priv))
7443 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7444 else if (IS_GEN6(dev_priv))
7445 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7446 else if (IS_GEN5(dev_priv))
7447 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7448 else if (IS_G4X(dev_priv))
7449 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7450 else if (IS_CRESTLINE(dev_priv))
7451 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7452 else if (IS_BROADWATER(dev_priv))
7453 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7454 else if (IS_GEN3(dev_priv))
7455 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7456 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7457 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7458 else if (IS_GEN2(dev_priv))
7459 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7460 else {
7461 MISSING_CASE(INTEL_DEVID(dev_priv));
7462 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7463 }
7464}
7465
1fa61106
ED		 7466/* Set up chip specific power management-related functions */
7467void intel_init_pm(struct drm_device *dev)
7468{
7469 struct drm_i915_private *dev_priv = dev->dev_private;
7470
7ff0ebcc 7471 intel_fbc_init(dev_priv);
1fa61106 7472
c921aba8
DV		 7473 /* For cxsr */
7474 if (IS_PINEVIEW(dev))
7475 i915_pineview_get_mem_freq(dev);
7476 else if (IS_GEN5(dev))
7477 i915_ironlake_get_mem_freq(dev);
7478
1fa61106 7479 /* For FIFO watermark updates */
f5ed50cb 7480 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7481 skl_setup_wm_latency(dev);
2d41c0b5 7482 dev_priv->display.update_wm = skl_update_wm;
98d39494 7483 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7484 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7485 ilk_setup_wm_latency(dev);
53615a5e 7486
bd602544
VS		 7487 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7488 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7489 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7490 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7491 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7492 dev_priv->display.compute_intermediate_wm =
7493 ilk_compute_intermediate_wm;
7494 dev_priv->display.initial_watermarks =
7495 ilk_initial_watermarks;
7496 dev_priv->display.optimize_watermarks =
7497 ilk_optimize_watermarks;
bd602544
VS		 7498 } else {
7499 DRM_DEBUG_KMS("Failed to read display plane latency. "
7500 "Disable CxSR\n");
7501 }
a4565da8 7502 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7503 vlv_setup_wm_latency(dev);
262cd2e1 7504 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7505 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7506 vlv_setup_wm_latency(dev);
26e1fe4f 7507 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7508 } else if (IS_PINEVIEW(dev)) {
7509 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7510 dev_priv->is_ddr3,
7511 dev_priv->fsb_freq,
7512 dev_priv->mem_freq)) {
7513 DRM_INFO("failed to find known CxSR latency "
7514 "(found ddr%s fsb freq %d, mem freq %d), "
7515 "disabling CxSR\n",
7516 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7517 dev_priv->fsb_freq, dev_priv->mem_freq);
7518 /* Disable CxSR and never update its watermark again */
5209b1f4 7519 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7520 dev_priv->display.update_wm = NULL;
7521 } else
7522 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7523 } else if (IS_G4X(dev)) {
7524 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7525 } else if (IS_GEN4(dev)) {
7526 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7527 } else if (IS_GEN3(dev)) {
7528 dev_priv->display.update_wm = i9xx_update_wm;
7529 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7530 } else if (IS_GEN2(dev)) {
7531 if (INTEL_INFO(dev)->num_pipes == 1) {
7532 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7533 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7534 } else {
7535 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7536 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7537 }
feb56b93
DV		 7538 } else {
7539 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7540 }
7541}
7542
151a49d0 7543int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7544{
4fc688ce 7545 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7546
7547 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7548 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7549 return -EAGAIN;
7550 }
7551
7552 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7553 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7554 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7555
7556 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7557 500)) {
7558 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7559 return -ETIMEDOUT;
7560 }
7561
7562 *val = I915_READ(GEN6_PCODE_DATA);
7563 I915_WRITE(GEN6_PCODE_DATA, 0);
7564
7565 return 0;
7566}
7567
151a49d0 7568int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7569{
4fc688ce 7570 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7571
7572 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7573 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7574 return -EAGAIN;
7575 }
7576
7577 I915_WRITE(GEN6_PCODE_DATA, val);
7578 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7579
7580 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7581 500)) {
7582 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7583 return -ETIMEDOUT;
7584 }
7585
7586 I915_WRITE(GEN6_PCODE_DATA, 0);
7587
7588 return 0;
7589}
a0e4e199 7590
dd06f88c
VS		 7591static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7592{
c30fec65
VS		 7593 /*
7594 * N = val - 0xb7
7595 * Slow = Fast = GPLL ref * N
7596 */
7597 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7598}
7599
b55dd647 7600static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7601{
c30fec65 7602 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7603}
7604
b55dd647 7605static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7606{
c30fec65
VS		 7607 /*
7608 * N = val / 2
7609 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7610 */
7611 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7612}
7613
b55dd647 7614static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7615{
1c14762d 7616 /* CHV needs even values */
c30fec65 7617 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7618}
7619
616bc820 7620int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7621{
2d1fe073 7622 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7623 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7624 GEN9_FREQ_SCALER);
2d1fe073 7625 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7626 return chv_gpu_freq(dev_priv, val);
2d1fe073 7627 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7628 return byt_gpu_freq(dev_priv, val);
7629 else
7630 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7631}
7632
616bc820
VS		 7633int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7634{
2d1fe073 7635 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7636 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7637 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7638 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7639 return chv_freq_opcode(dev_priv, val);
2d1fe073 7640 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7641 return byt_freq_opcode(dev_priv, val);
7642 else
500a3d2e 7643 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7644}
22b1b2f8 7645
6ad790c0
CW		 7646struct request_boost {
7647 struct work_struct work;
eed29a5b 7648 struct drm_i915_gem_request *req;
6ad790c0
CW		 7649};
7650
7651static void __intel_rps_boost_work(struct work_struct *work)
7652{
7653 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7654 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7655
e61b9958 7656 if (!i915_gem_request_completed(req, true))
c033666a 7657 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7658
73db04cf 7659 i915_gem_request_unreference(req);
6ad790c0
CW		 7660 kfree(boost);
7661}
7662
91d14251 7663void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7664{
7665 struct request_boost *boost;
7666
91d14251 7667 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7668 return;
7669
e61b9958
CW		 7670 if (i915_gem_request_completed(req, true))
7671 return;
7672
6ad790c0
CW		 7673 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7674 if (boost == NULL)
7675 return;
7676
eed29a5b
DV		 7677 i915_gem_request_reference(req);
7678 boost->req = req;
6ad790c0
CW		 7679
7680 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7681 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7682}
7683
f742a552 7684void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7685{
7686 struct drm_i915_private *dev_priv = dev->dev_private;
7687
f742a552 7688 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7689 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7690
907b28c5
CW		 7691 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7692 intel_gen6_powersave_work);
1854d5ca 7693 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7694 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7695 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7696
33688d95 7697 dev_priv->pm.suspended = false;
1f814dac 7698 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7699 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7700}
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