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drm/i915/guc: Add host2guc notification for suspend and resume
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
6381b550
NH		 62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
77719d28 66}
91e41d16 67
45db2194 68static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 69{
acd5c346 70 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 71
77719d28
DL		 72 gen9_init_clock_gating(dev);
73
2caa3b26 74 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 75 /* WaDisableHDCInvalidation:skl */
76 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
77 BDW_DISABLE_HDC_INVALIDATION);
78
2caa3b26
DL		 79 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
80 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 81 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 82 }
81e231af 83
a4106a78
AS		 84 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
85 * involving this register should also be added to WA batch as required.
86 */
8bc0ccf6
DL		 87 if (INTEL_REVID(dev) <= SKL_REVID_E0)
88 /* WaDisableLSQCROPERFforOCL:skl */
89 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
90 GEN8_LQSC_RO_PERF_DIS);
245d9667
AS		 91
92 /* WaEnableGapsTsvCreditFix:skl */
93 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) {
94 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
95 GEN9_GAPS_TSV_CREDIT_DISABLE));
96 }
da2078cd
DL		 97}
98
a82abe43
ID		 99static void bxt_init_clock_gating(struct drm_device *dev)
100{
32608ca2
ID		 101 struct drm_i915_private *dev_priv = dev->dev_private;
102
a82abe43 103 gen9_init_clock_gating(dev);
32608ca2 104
a7546159
NH		 105 /* WaDisableSDEUnitClockGating:bxt */
106 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
107 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
108
32608ca2
ID		 109 /*
110 * FIXME:
868434c5 111 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 112 */
32608ca2 113 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 115
aa66c506
AS		 116 /* WaStoreMultiplePTEenable:bxt */
117 /* This is a requirement according to Hardware specification */
118 if (INTEL_REVID(dev) == BXT_REVID_A0)
a7546159 119 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
5b88abac
AS		 120
121 /* WaSetClckGatingDisableMedia:bxt */
122 if (INTEL_REVID(dev) == BXT_REVID_A0) {
123 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
124 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
125 }
a82abe43
ID		 126}
127
c921aba8
DV		 128static void i915_pineview_get_mem_freq(struct drm_device *dev)
129{
50227e1c 130 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 131 u32 tmp;
132
133 tmp = I915_READ(CLKCFG);
134
135 switch (tmp & CLKCFG_FSB_MASK) {
136 case CLKCFG_FSB_533:
137 dev_priv->fsb_freq = 533; /* 133*4 */
138 break;
139 case CLKCFG_FSB_800:
140 dev_priv->fsb_freq = 800; /* 200*4 */
141 break;
142 case CLKCFG_FSB_667:
143 dev_priv->fsb_freq = 667; /* 167*4 */
144 break;
145 case CLKCFG_FSB_400:
146 dev_priv->fsb_freq = 400; /* 100*4 */
147 break;
148 }
149
150 switch (tmp & CLKCFG_MEM_MASK) {
151 case CLKCFG_MEM_533:
152 dev_priv->mem_freq = 533;
153 break;
154 case CLKCFG_MEM_667:
155 dev_priv->mem_freq = 667;
156 break;
157 case CLKCFG_MEM_800:
158 dev_priv->mem_freq = 800;
159 break;
160 }
161
162 /* detect pineview DDR3 setting */
163 tmp = I915_READ(CSHRDDR3CTL);
164 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
165}
166
167static void i915_ironlake_get_mem_freq(struct drm_device *dev)
168{
50227e1c 169 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 170 u16 ddrpll, csipll;
171
172 ddrpll = I915_READ16(DDRMPLL1);
173 csipll = I915_READ16(CSIPLL0);
174
175 switch (ddrpll & 0xff) {
176 case 0xc:
177 dev_priv->mem_freq = 800;
178 break;
179 case 0x10:
180 dev_priv->mem_freq = 1066;
181 break;
182 case 0x14:
183 dev_priv->mem_freq = 1333;
184 break;
185 case 0x18:
186 dev_priv->mem_freq = 1600;
187 break;
188 default:
189 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
190 ddrpll & 0xff);
191 dev_priv->mem_freq = 0;
192 break;
193 }
194
20e4d407 195 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 196
197 switch (csipll & 0x3ff) {
198 case 0x00c:
199 dev_priv->fsb_freq = 3200;
200 break;
201 case 0x00e:
202 dev_priv->fsb_freq = 3733;
203 break;
204 case 0x010:
205 dev_priv->fsb_freq = 4266;
206 break;
207 case 0x012:
208 dev_priv->fsb_freq = 4800;
209 break;
210 case 0x014:
211 dev_priv->fsb_freq = 5333;
212 break;
213 case 0x016:
214 dev_priv->fsb_freq = 5866;
215 break;
216 case 0x018:
217 dev_priv->fsb_freq = 6400;
218 break;
219 default:
220 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
221 csipll & 0x3ff);
222 dev_priv->fsb_freq = 0;
223 break;
224 }
225
226 if (dev_priv->fsb_freq == 3200) {
20e4d407 227 dev_priv->ips.c_m = 0;
c921aba8 228 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 229 dev_priv->ips.c_m = 1;
c921aba8 230 } else {
20e4d407 231 dev_priv->ips.c_m = 2;
c921aba8
DV		 232 }
233}
234
b445e3b0
ED		 235static const struct cxsr_latency cxsr_latency_table[] = {
236 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
237 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
238 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
239 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
240 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
241
242 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
243 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
244 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
245 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
246 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
247
248 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
249 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
250 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
251 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
252 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
253
254 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
255 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
256 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
257 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
258 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
259
260 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
261 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
262 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
263 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
264 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
265
266 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
267 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
268 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
269 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
270 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
271};
272
63c62275 273static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 274 int is_ddr3,
275 int fsb,
276 int mem)
277{
278 const struct cxsr_latency *latency;
279 int i;
280
281 if (fsb == 0 || mem == 0)
282 return NULL;
283
284 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
285 latency = &cxsr_latency_table[i];
286 if (is_desktop == latency->is_desktop &&
287 is_ddr3 == latency->is_ddr3 &&
288 fsb == latency->fsb_freq && mem == latency->mem_freq)
289 return latency;
290 }
291
292 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
293
294 return NULL;
295}
296
fc1ac8de
VS		 297static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
298{
299 u32 val;
300
301 mutex_lock(&dev_priv->rps.hw_lock);
302
303 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
304 if (enable)
305 val &= ~FORCE_DDR_HIGH_FREQ;
306 else
307 val |= FORCE_DDR_HIGH_FREQ;
308 val &= ~FORCE_DDR_LOW_FREQ;
309 val |= FORCE_DDR_FREQ_REQ_ACK;
310 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
311
312 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
313 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
314 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
315
316 mutex_unlock(&dev_priv->rps.hw_lock);
317}
318
cfb41411
VS		 319static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
320{
321 u32 val;
322
323 mutex_lock(&dev_priv->rps.hw_lock);
324
325 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
326 if (enable)
327 val |= DSP_MAXFIFO_PM5_ENABLE;
328 else
329 val &= ~DSP_MAXFIFO_PM5_ENABLE;
330 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
331
332 mutex_unlock(&dev_priv->rps.hw_lock);
333}
334
f4998963
VS		 335#define FW_WM(value, plane) \
336 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
337
5209b1f4 338void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 339{
5209b1f4
ID		 340 struct drm_device *dev = dev_priv->dev;
341 u32 val;
b445e3b0 342
5209b1f4
ID		 343 if (IS_VALLEYVIEW(dev)) {
344 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 345 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 346 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 347 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
348 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 349 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 350 } else if (IS_PINEVIEW(dev)) {
351 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
352 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
353 I915_WRITE(DSPFW3, val);
a7a6c498 354 POSTING_READ(DSPFW3);
5209b1f4
ID		 355 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
356 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
357 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
358 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 359 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 360 } else if (IS_I915GM(dev)) {
361 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
362 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
363 I915_WRITE(INSTPM, val);
a7a6c498 364 POSTING_READ(INSTPM);
5209b1f4
ID		 365 } else {
366 return;
367 }
b445e3b0 368
5209b1f4
ID		 369 DRM_DEBUG_KMS("memory self-refresh is %s\n",
370 enable ? "enabled" : "disabled");
b445e3b0
ED		 371}
372
fc1ac8de 373
b445e3b0
ED		 374/*
375 * Latency for FIFO fetches is dependent on several factors:
376 * - memory configuration (speed, channels)
377 * - chipset
378 * - current MCH state
379 * It can be fairly high in some situations, so here we assume a fairly
380 * pessimal value. It's a tradeoff between extra memory fetches (if we
381 * set this value too high, the FIFO will fetch frequently to stay full)
382 * and power consumption (set it too low to save power and we might see
383 * FIFO underruns and display "flicker").
384 *
385 * A value of 5us seems to be a good balance; safe for very low end
386 * platforms but not overly aggressive on lower latency configs.
387 */
5aef6003 388static const int pessimal_latency_ns = 5000;
b445e3b0 389
b5004720
VS		 390#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
391 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
392
393static int vlv_get_fifo_size(struct drm_device *dev,
394 enum pipe pipe, int plane)
395{
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 int sprite0_start, sprite1_start, size;
398
399 switch (pipe) {
400 uint32_t dsparb, dsparb2, dsparb3;
401 case PIPE_A:
402 dsparb = I915_READ(DSPARB);
403 dsparb2 = I915_READ(DSPARB2);
404 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
405 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
406 break;
407 case PIPE_B:
408 dsparb = I915_READ(DSPARB);
409 dsparb2 = I915_READ(DSPARB2);
410 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
411 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
412 break;
413 case PIPE_C:
414 dsparb2 = I915_READ(DSPARB2);
415 dsparb3 = I915_READ(DSPARB3);
416 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
417 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
418 break;
419 default:
420 return 0;
421 }
422
423 switch (plane) {
424 case 0:
425 size = sprite0_start;
426 break;
427 case 1:
428 size = sprite1_start - sprite0_start;
429 break;
430 case 2:
431 size = 512 - 1 - sprite1_start;
432 break;
433 default:
434 return 0;
435 }
436
437 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
438 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
439 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
440 size);
441
442 return size;
443}
444
1fa61106 445static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 uint32_t dsparb = I915_READ(DSPARB);
449 int size;
450
451 size = dsparb & 0x7f;
452 if (plane)
453 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
454
455 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
456 plane ? "B" : "A", size);
457
458 return size;
459}
460
feb56b93 461static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 462{
463 struct drm_i915_private *dev_priv = dev->dev_private;
464 uint32_t dsparb = I915_READ(DSPARB);
465 int size;
466
467 size = dsparb & 0x1ff;
468 if (plane)
469 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
470 size >>= 1; /* Convert to cachelines */
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476}
477
1fa61106 478static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 479{
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 uint32_t dsparb = I915_READ(DSPARB);
482 int size;
483
484 size = dsparb & 0x7f;
485 size >>= 2; /* Convert to cachelines */
486
487 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
488 plane ? "B" : "A",
489 size);
490
491 return size;
492}
493
b445e3b0
ED		 494/* Pineview has different values for various configs */
495static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 496 .fifo_size = PINEVIEW_DISPLAY_FIFO,
497 .max_wm = PINEVIEW_MAX_WM,
498 .default_wm = PINEVIEW_DFT_WM,
499 .guard_size = PINEVIEW_GUARD_WM,
500 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 503 .fifo_size = PINEVIEW_DISPLAY_FIFO,
504 .max_wm = PINEVIEW_MAX_WM,
505 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
506 .guard_size = PINEVIEW_GUARD_WM,
507 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 510 .fifo_size = PINEVIEW_CURSOR_FIFO,
511 .max_wm = PINEVIEW_CURSOR_MAX_WM,
512 .default_wm = PINEVIEW_CURSOR_DFT_WM,
513 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
514 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 517 .fifo_size = PINEVIEW_CURSOR_FIFO,
518 .max_wm = PINEVIEW_CURSOR_MAX_WM,
519 .default_wm = PINEVIEW_CURSOR_DFT_WM,
520 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
521 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 522};
523static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 524 .fifo_size = G4X_FIFO_SIZE,
525 .max_wm = G4X_MAX_WM,
526 .default_wm = G4X_MAX_WM,
527 .guard_size = 2,
528 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 529};
530static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 531 .fifo_size = I965_CURSOR_FIFO,
532 .max_wm = I965_CURSOR_MAX_WM,
533 .default_wm = I965_CURSOR_DFT_WM,
534 .guard_size = 2,
535 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 536};
537static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 538 .fifo_size = VALLEYVIEW_FIFO_SIZE,
539 .max_wm = VALLEYVIEW_MAX_WM,
540 .default_wm = VALLEYVIEW_MAX_WM,
541 .guard_size = 2,
542 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 543};
544static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 545 .fifo_size = I965_CURSOR_FIFO,
546 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
547 .default_wm = I965_CURSOR_DFT_WM,
548 .guard_size = 2,
549 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 550};
551static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 552 .fifo_size = I965_CURSOR_FIFO,
553 .max_wm = I965_CURSOR_MAX_WM,
554 .default_wm = I965_CURSOR_DFT_WM,
555 .guard_size = 2,
556 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 557};
558static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 559 .fifo_size = I945_FIFO_SIZE,
560 .max_wm = I915_MAX_WM,
561 .default_wm = 1,
562 .guard_size = 2,
563 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 564};
565static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 566 .fifo_size = I915_FIFO_SIZE,
567 .max_wm = I915_MAX_WM,
568 .default_wm = 1,
569 .guard_size = 2,
570 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 571};
9d539105 572static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 573 .fifo_size = I855GM_FIFO_SIZE,
574 .max_wm = I915_MAX_WM,
575 .default_wm = 1,
576 .guard_size = 2,
577 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 578};
9d539105
VS		 579static const struct intel_watermark_params i830_bc_wm_info = {
580 .fifo_size = I855GM_FIFO_SIZE,
581 .max_wm = I915_MAX_WM/2,
582 .default_wm = 1,
583 .guard_size = 2,
584 .cacheline_size = I830_FIFO_LINE_SIZE,
585};
feb56b93 586static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 587 .fifo_size = I830_FIFO_SIZE,
588 .max_wm = I915_MAX_WM,
589 .default_wm = 1,
590 .guard_size = 2,
591 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 592};
593
b445e3b0
ED		 594/**
595 * intel_calculate_wm - calculate watermark level
596 * @clock_in_khz: pixel clock
597 * @wm: chip FIFO params
598 * @pixel_size: display pixel size
599 * @latency_ns: memory latency for the platform
600 *
601 * Calculate the watermark level (the level at which the display plane will
602 * start fetching from memory again). Each chip has a different display
603 * FIFO size and allocation, so the caller needs to figure that out and pass
604 * in the correct intel_watermark_params structure.
605 *
606 * As the pixel clock runs, the FIFO will be drained at a rate that depends
607 * on the pixel size. When it reaches the watermark level, it'll start
608 * fetching FIFO line sized based chunks from memory until the FIFO fills
609 * past the watermark point. If the FIFO drains completely, a FIFO underrun
610 * will occur, and a display engine hang could result.
611 */
612static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
613 const struct intel_watermark_params *wm,
614 int fifo_size,
615 int pixel_size,
616 unsigned long latency_ns)
617{
618 long entries_required, wm_size;
619
620 /*
621 * Note: we need to make sure we don't overflow for various clock &
622 * latency values.
623 * clocks go from a few thousand to several hundred thousand.
624 * latency is usually a few thousand
625 */
626 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
627 1000;
628 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
629
630 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
631
632 wm_size = fifo_size - (entries_required + wm->guard_size);
633
634 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
635
636 /* Don't promote wm_size to unsigned... */
637 if (wm_size > (long)wm->max_wm)
638 wm_size = wm->max_wm;
639 if (wm_size <= 0)
640 wm_size = wm->default_wm;
d6feb196
VS		 641
642 /*
643 * Bspec seems to indicate that the value shouldn't be lower than
644 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
645 * Lets go for 8 which is the burst size since certain platforms
646 * already use a hardcoded 8 (which is what the spec says should be
647 * done).
648 */
649 if (wm_size <= 8)
650 wm_size = 8;
651
b445e3b0
ED		 652 return wm_size;
653}
654
655static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
656{
657 struct drm_crtc *crtc, *enabled = NULL;
658
70e1e0ec 659 for_each_crtc(dev, crtc) {
3490ea5d 660 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 661 if (enabled)
662 return NULL;
663 enabled = crtc;
664 }
665 }
666
667 return enabled;
668}
669
46ba614c 670static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 671{
46ba614c 672 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 673 struct drm_i915_private *dev_priv = dev->dev_private;
674 struct drm_crtc *crtc;
675 const struct cxsr_latency *latency;
676 u32 reg;
677 unsigned long wm;
678
679 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
680 dev_priv->fsb_freq, dev_priv->mem_freq);
681 if (!latency) {
682 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 683 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 684 return;
685 }
686
687 crtc = single_enabled_crtc(dev);
688 if (crtc) {
7c5f93b0 689 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 690 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 691 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 692
693 /* Display SR */
694 wm = intel_calculate_wm(clock, &pineview_display_wm,
695 pineview_display_wm.fifo_size,
696 pixel_size, latency->display_sr);
697 reg = I915_READ(DSPFW1);
698 reg &= ~DSPFW_SR_MASK;
f4998963 699 reg |= FW_WM(wm, SR);
b445e3b0
ED		 700 I915_WRITE(DSPFW1, reg);
701 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
702
703 /* cursor SR */
704 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
705 pineview_display_wm.fifo_size,
706 pixel_size, latency->cursor_sr);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 709 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 710 I915_WRITE(DSPFW3, reg);
711
712 /* Display HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 pixel_size, latency->display_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 718 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 719 I915_WRITE(DSPFW3, reg);
720
721 /* cursor HPLL off SR */
722 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
723 pineview_display_hplloff_wm.fifo_size,
724 pixel_size, latency->cursor_hpll_disable);
725 reg = I915_READ(DSPFW3);
726 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 727 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 728 I915_WRITE(DSPFW3, reg);
729 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
730
5209b1f4 731 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 732 } else {
5209b1f4 733 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 734 }
735}
736
737static bool g4x_compute_wm0(struct drm_device *dev,
738 int plane,
739 const struct intel_watermark_params *display,
740 int display_latency_ns,
741 const struct intel_watermark_params *cursor,
742 int cursor_latency_ns,
743 int *plane_wm,
744 int *cursor_wm)
745{
746 struct drm_crtc *crtc;
4fe8590a 747 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 748 int htotal, hdisplay, clock, pixel_size;
749 int line_time_us, line_count;
750 int entries, tlb_miss;
751
752 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 753 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 754 *cursor_wm = cursor->guard_size;
755 *plane_wm = display->guard_size;
756 return false;
757 }
758
6e3c9717 759 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 760 clock = adjusted_mode->crtc_clock;
fec8cba3 761 htotal = adjusted_mode->crtc_htotal;
6e3c9717 762 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 763 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 764
765 /* Use the small buffer method to calculate plane watermark */
766 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
767 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
768 if (tlb_miss > 0)
769 entries += tlb_miss;
770 entries = DIV_ROUND_UP(entries, display->cacheline_size);
771 *plane_wm = entries + display->guard_size;
772 if (*plane_wm > (int)display->max_wm)
773 *plane_wm = display->max_wm;
774
775 /* Use the large buffer method to calculate cursor watermark */
922044c9 776 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 777 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 778 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 779 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
780 if (tlb_miss > 0)
781 entries += tlb_miss;
782 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
783 *cursor_wm = entries + cursor->guard_size;
784 if (*cursor_wm > (int)cursor->max_wm)
785 *cursor_wm = (int)cursor->max_wm;
786
787 return true;
788}
789
790/*
791 * Check the wm result.
792 *
793 * If any calculated watermark values is larger than the maximum value that
794 * can be programmed into the associated watermark register, that watermark
795 * must be disabled.
796 */
797static bool g4x_check_srwm(struct drm_device *dev,
798 int display_wm, int cursor_wm,
799 const struct intel_watermark_params *display,
800 const struct intel_watermark_params *cursor)
801{
802 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
803 display_wm, cursor_wm);
804
805 if (display_wm > display->max_wm) {
806 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
807 display_wm, display->max_wm);
808 return false;
809 }
810
811 if (cursor_wm > cursor->max_wm) {
812 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
813 cursor_wm, cursor->max_wm);
814 return false;
815 }
816
817 if (!(display_wm || cursor_wm)) {
818 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
819 return false;
820 }
821
822 return true;
823}
824
825static bool g4x_compute_srwm(struct drm_device *dev,
826 int plane,
827 int latency_ns,
828 const struct intel_watermark_params *display,
829 const struct intel_watermark_params *cursor,
830 int *display_wm, int *cursor_wm)
831{
832 struct drm_crtc *crtc;
4fe8590a 833 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 834 int hdisplay, htotal, pixel_size, clock;
835 unsigned long line_time_us;
836 int line_count, line_size;
837 int small, large;
838 int entries;
839
840 if (!latency_ns) {
841 *display_wm = *cursor_wm = 0;
842 return false;
843 }
844
845 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 846 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 847 clock = adjusted_mode->crtc_clock;
fec8cba3 848 htotal = adjusted_mode->crtc_htotal;
6e3c9717 849 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 850 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 851
922044c9 852 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 853 line_count = (latency_ns / line_time_us + 1000) / 1000;
854 line_size = hdisplay * pixel_size;
855
856 /* Use the minimum of the small and large buffer method for primary */
857 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
858 large = line_count * line_size;
859
860 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
861 *display_wm = entries + display->guard_size;
862
863 /* calculate the self-refresh watermark for display cursor */
3dd512fb 864 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 865 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
866 *cursor_wm = entries + cursor->guard_size;
867
868 return g4x_check_srwm(dev,
869 *display_wm, *cursor_wm,
870 display, cursor);
871}
872
15665979
VS		 873#define FW_WM_VLV(value, plane) \
874 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
875
0018fda1
VS		 876static void vlv_write_wm_values(struct intel_crtc *crtc,
877 const struct vlv_wm_values *wm)
878{
879 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
880 enum pipe pipe = crtc->pipe;
881
882 I915_WRITE(VLV_DDL(pipe),
883 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
884 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
885 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
886 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
887
ae80152d 888 I915_WRITE(DSPFW1,
15665979
VS		 889 FW_WM(wm->sr.plane, SR) |
890 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
891 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
892 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 893 I915_WRITE(DSPFW2,
15665979
VS		 894 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
895 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
896 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 897 I915_WRITE(DSPFW3,
15665979 898 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 899
900 if (IS_CHERRYVIEW(dev_priv)) {
901 I915_WRITE(DSPFW7_CHV,
15665979
VS		 902 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
903 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 904 I915_WRITE(DSPFW8_CHV,
15665979
VS		 905 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
906 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 907 I915_WRITE(DSPFW9_CHV,
15665979
VS		 908 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
909 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 910 I915_WRITE(DSPHOWM,
15665979
VS		 911 FW_WM(wm->sr.plane >> 9, SR_HI) |
912 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
913 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
914 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
915 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
916 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
917 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
918 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
919 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
920 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 921 } else {
922 I915_WRITE(DSPFW7,
15665979
VS		 923 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
924 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 925 I915_WRITE(DSPHOWM,
15665979
VS		 926 FW_WM(wm->sr.plane >> 9, SR_HI) |
927 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
928 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
929 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
930 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
931 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
932 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 933 }
934
2cb389b7
VS		 935 /* zero (unused) WM1 watermarks */
936 I915_WRITE(DSPFW4, 0);
937 I915_WRITE(DSPFW5, 0);
938 I915_WRITE(DSPFW6, 0);
939 I915_WRITE(DSPHOWM1, 0);
940
ae80152d 941 POSTING_READ(DSPFW1);
0018fda1
VS		 942}
943
15665979
VS		 944#undef FW_WM_VLV
945
6eb1a681
VS		 946enum vlv_wm_level {
947 VLV_WM_LEVEL_PM2,
948 VLV_WM_LEVEL_PM5,
949 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 950};
951
262cd2e1
VS		 952/* latency must be in 0.1us units. */
953static unsigned int vlv_wm_method2(unsigned int pixel_rate,
954 unsigned int pipe_htotal,
955 unsigned int horiz_pixels,
956 unsigned int bytes_per_pixel,
957 unsigned int latency)
958{
959 unsigned int ret;
960
961 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
962 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
963 ret = DIV_ROUND_UP(ret, 64);
964
965 return ret;
966}
967
968static void vlv_setup_wm_latency(struct drm_device *dev)
969{
970 struct drm_i915_private *dev_priv = dev->dev_private;
971
972 /* all latencies in usec */
973 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
974
58590c14
VS		 975 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
976
262cd2e1
VS		 977 if (IS_CHERRYVIEW(dev_priv)) {
978 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
979 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 980
981 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 982 }
983}
984
985static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
986 struct intel_crtc *crtc,
987 const struct intel_plane_state *state,
988 int level)
989{
990 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
991 int clock, htotal, pixel_size, width, wm;
992
993 if (dev_priv->wm.pri_latency[level] == 0)
994 return USHRT_MAX;
995
996 if (!state->visible)
997 return 0;
998
999 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1000 clock = crtc->config->base.adjusted_mode.crtc_clock;
1001 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1002 width = crtc->config->pipe_src_w;
1003 if (WARN_ON(htotal == 0))
1004 htotal = 1;
1005
1006 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007 /*
1008 * FIXME the formula gives values that are
1009 * too big for the cursor FIFO, and hence we
1010 * would never be able to use cursors. For
1011 * now just hardcode the watermark.
1012 */
1013 wm = 63;
1014 } else {
1015 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1016 dev_priv->wm.pri_latency[level] * 10);
1017 }
1018
1019 return min_t(int, wm, USHRT_MAX);
1020}
1021
54f1b6e1
VS		 1022static void vlv_compute_fifo(struct intel_crtc *crtc)
1023{
1024 struct drm_device *dev = crtc->base.dev;
1025 struct vlv_wm_state *wm_state = &crtc->wm_state;
1026 struct intel_plane *plane;
1027 unsigned int total_rate = 0;
1028 const int fifo_size = 512 - 1;
1029 int fifo_extra, fifo_left = fifo_size;
1030
1031 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1032 struct intel_plane_state *state =
1033 to_intel_plane_state(plane->base.state);
1034
1035 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036 continue;
1037
1038 if (state->visible) {
1039 wm_state->num_active_planes++;
1040 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041 }
1042 }
1043
1044 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045 struct intel_plane_state *state =
1046 to_intel_plane_state(plane->base.state);
1047 unsigned int rate;
1048
1049 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1050 plane->wm.fifo_size = 63;
1051 continue;
1052 }
1053
1054 if (!state->visible) {
1055 plane->wm.fifo_size = 0;
1056 continue;
1057 }
1058
1059 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1060 plane->wm.fifo_size = fifo_size * rate / total_rate;
1061 fifo_left -= plane->wm.fifo_size;
1062 }
1063
1064 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1065
1066 /* spread the remainder evenly */
1067 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1068 int plane_extra;
1069
1070 if (fifo_left == 0)
1071 break;
1072
1073 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1074 continue;
1075
1076 /* give it all to the first plane if none are active */
1077 if (plane->wm.fifo_size == 0 &&
1078 wm_state->num_active_planes)
1079 continue;
1080
1081 plane_extra = min(fifo_extra, fifo_left);
1082 plane->wm.fifo_size += plane_extra;
1083 fifo_left -= plane_extra;
1084 }
1085
1086 WARN_ON(fifo_left != 0);
1087}
1088
262cd2e1
VS		 1089static void vlv_invert_wms(struct intel_crtc *crtc)
1090{
1091 struct vlv_wm_state *wm_state = &crtc->wm_state;
1092 int level;
1093
1094 for (level = 0; level < wm_state->num_levels; level++) {
1095 struct drm_device *dev = crtc->base.dev;
1096 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097 struct intel_plane *plane;
1098
1099 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1100 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 switch (plane->base.type) {
1104 int sprite;
1105 case DRM_PLANE_TYPE_CURSOR:
1106 wm_state->wm[level].cursor = plane->wm.fifo_size -
1107 wm_state->wm[level].cursor;
1108 break;
1109 case DRM_PLANE_TYPE_PRIMARY:
1110 wm_state->wm[level].primary = plane->wm.fifo_size -
1111 wm_state->wm[level].primary;
1112 break;
1113 case DRM_PLANE_TYPE_OVERLAY:
1114 sprite = plane->plane;
1115 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1116 wm_state->wm[level].sprite[sprite];
1117 break;
1118 }
1119 }
1120 }
1121}
1122
26e1fe4f 1123static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1124{
1125 struct drm_device *dev = crtc->base.dev;
1126 struct vlv_wm_state *wm_state = &crtc->wm_state;
1127 struct intel_plane *plane;
1128 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1129 int level;
1130
1131 memset(wm_state, 0, sizeof(*wm_state));
1132
852eb00d 1133 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1134 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1135
1136 wm_state->num_active_planes = 0;
262cd2e1 1137
54f1b6e1 1138 vlv_compute_fifo(crtc);
262cd2e1
VS		 1139
1140 if (wm_state->num_active_planes != 1)
1141 wm_state->cxsr = false;
1142
1143 if (wm_state->cxsr) {
1144 for (level = 0; level < wm_state->num_levels; level++) {
1145 wm_state->sr[level].plane = sr_fifo_size;
1146 wm_state->sr[level].cursor = 63;
1147 }
1148 }
1149
1150 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1151 struct intel_plane_state *state =
1152 to_intel_plane_state(plane->base.state);
1153
1154 if (!state->visible)
1155 continue;
1156
1157 /* normal watermarks */
1158 for (level = 0; level < wm_state->num_levels; level++) {
1159 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1160 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1161
1162 /* hack */
1163 if (WARN_ON(level == 0 && wm > max_wm))
1164 wm = max_wm;
1165
1166 if (wm > plane->wm.fifo_size)
1167 break;
1168
1169 switch (plane->base.type) {
1170 int sprite;
1171 case DRM_PLANE_TYPE_CURSOR:
1172 wm_state->wm[level].cursor = wm;
1173 break;
1174 case DRM_PLANE_TYPE_PRIMARY:
1175 wm_state->wm[level].primary = wm;
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 wm_state->wm[level].sprite[sprite] = wm;
1180 break;
1181 }
1182 }
1183
1184 wm_state->num_levels = level;
1185
1186 if (!wm_state->cxsr)
1187 continue;
1188
1189 /* maxfifo watermarks */
1190 switch (plane->base.type) {
1191 int sprite, level;
1192 case DRM_PLANE_TYPE_CURSOR:
1193 for (level = 0; level < wm_state->num_levels; level++)
1194 wm_state->sr[level].cursor =
1195 wm_state->sr[level].cursor;
1196 break;
1197 case DRM_PLANE_TYPE_PRIMARY:
1198 for (level = 0; level < wm_state->num_levels; level++)
1199 wm_state->sr[level].plane =
1200 min(wm_state->sr[level].plane,
1201 wm_state->wm[level].primary);
1202 break;
1203 case DRM_PLANE_TYPE_OVERLAY:
1204 sprite = plane->plane;
1205 for (level = 0; level < wm_state->num_levels; level++)
1206 wm_state->sr[level].plane =
1207 min(wm_state->sr[level].plane,
1208 wm_state->wm[level].sprite[sprite]);
1209 break;
1210 }
1211 }
1212
1213 /* clear any (partially) filled invalid levels */
58590c14 1214 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1215 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1216 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1217 }
1218
1219 vlv_invert_wms(crtc);
1220}
1221
54f1b6e1
VS		 1222#define VLV_FIFO(plane, value) \
1223 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1224
1225static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1226{
1227 struct drm_device *dev = crtc->base.dev;
1228 struct drm_i915_private *dev_priv = to_i915(dev);
1229 struct intel_plane *plane;
1230 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1231
1232 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1233 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1234 WARN_ON(plane->wm.fifo_size != 63);
1235 continue;
1236 }
1237
1238 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1239 sprite0_start = plane->wm.fifo_size;
1240 else if (plane->plane == 0)
1241 sprite1_start = sprite0_start + plane->wm.fifo_size;
1242 else
1243 fifo_size = sprite1_start + plane->wm.fifo_size;
1244 }
1245
1246 WARN_ON(fifo_size != 512 - 1);
1247
1248 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1249 pipe_name(crtc->pipe), sprite0_start,
1250 sprite1_start, fifo_size);
1251
1252 switch (crtc->pipe) {
1253 uint32_t dsparb, dsparb2, dsparb3;
1254 case PIPE_A:
1255 dsparb = I915_READ(DSPARB);
1256 dsparb2 = I915_READ(DSPARB2);
1257
1258 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1259 VLV_FIFO(SPRITEB, 0xff));
1260 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1261 VLV_FIFO(SPRITEB, sprite1_start));
1262
1263 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1264 VLV_FIFO(SPRITEB_HI, 0x1));
1265 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1266 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1267
1268 I915_WRITE(DSPARB, dsparb);
1269 I915_WRITE(DSPARB2, dsparb2);
1270 break;
1271 case PIPE_B:
1272 dsparb = I915_READ(DSPARB);
1273 dsparb2 = I915_READ(DSPARB2);
1274
1275 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1276 VLV_FIFO(SPRITED, 0xff));
1277 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1278 VLV_FIFO(SPRITED, sprite1_start));
1279
1280 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1281 VLV_FIFO(SPRITED_HI, 0xff));
1282 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1283 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1284
1285 I915_WRITE(DSPARB, dsparb);
1286 I915_WRITE(DSPARB2, dsparb2);
1287 break;
1288 case PIPE_C:
1289 dsparb3 = I915_READ(DSPARB3);
1290 dsparb2 = I915_READ(DSPARB2);
1291
1292 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1293 VLV_FIFO(SPRITEF, 0xff));
1294 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1295 VLV_FIFO(SPRITEF, sprite1_start));
1296
1297 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1298 VLV_FIFO(SPRITEF_HI, 0xff));
1299 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1300 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1301
1302 I915_WRITE(DSPARB3, dsparb3);
1303 I915_WRITE(DSPARB2, dsparb2);
1304 break;
1305 default:
1306 break;
1307 }
1308}
1309
1310#undef VLV_FIFO
1311
262cd2e1
VS		 1312static void vlv_merge_wm(struct drm_device *dev,
1313 struct vlv_wm_values *wm)
1314{
1315 struct intel_crtc *crtc;
1316 int num_active_crtcs = 0;
1317
58590c14 1318 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1319 wm->cxsr = true;
1320
1321 for_each_intel_crtc(dev, crtc) {
1322 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1323
1324 if (!crtc->active)
1325 continue;
1326
1327 if (!wm_state->cxsr)
1328 wm->cxsr = false;
1329
1330 num_active_crtcs++;
1331 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1332 }
1333
1334 if (num_active_crtcs != 1)
1335 wm->cxsr = false;
1336
6f9c784b
VS		 1337 if (num_active_crtcs > 1)
1338 wm->level = VLV_WM_LEVEL_PM2;
1339
262cd2e1
VS		 1340 for_each_intel_crtc(dev, crtc) {
1341 struct vlv_wm_state *wm_state = &crtc->wm_state;
1342 enum pipe pipe = crtc->pipe;
1343
1344 if (!crtc->active)
1345 continue;
1346
1347 wm->pipe[pipe] = wm_state->wm[wm->level];
1348 if (wm->cxsr)
1349 wm->sr = wm_state->sr[wm->level];
1350
1351 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1352 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1353 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1354 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1355 }
1356}
1357
1358static void vlv_update_wm(struct drm_crtc *crtc)
1359{
1360 struct drm_device *dev = crtc->dev;
1361 struct drm_i915_private *dev_priv = dev->dev_private;
1362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1363 enum pipe pipe = intel_crtc->pipe;
1364 struct vlv_wm_values wm = {};
1365
26e1fe4f 1366 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1367 vlv_merge_wm(dev, &wm);
1368
54f1b6e1
VS		 1369 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1370 /* FIXME should be part of crtc atomic commit */
1371 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1372 return;
54f1b6e1 1373 }
262cd2e1
VS		 1374
1375 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1376 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1377 chv_set_memory_dvfs(dev_priv, false);
1378
1379 if (wm.level < VLV_WM_LEVEL_PM5 &&
1380 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1381 chv_set_memory_pm5(dev_priv, false);
1382
852eb00d 1383 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1384 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1385
54f1b6e1
VS		 1386 /* FIXME should be part of crtc atomic commit */
1387 vlv_pipe_set_fifo_size(intel_crtc);
1388
262cd2e1
VS		 1389 vlv_write_wm_values(intel_crtc, &wm);
1390
1391 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1392 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1393 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1394 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1395 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1396
852eb00d 1397 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1398 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1399
1400 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1401 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1402 chv_set_memory_pm5(dev_priv, true);
1403
1404 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1405 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1406 chv_set_memory_dvfs(dev_priv, true);
1407
1408 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1409}
1410
ae80152d
VS		 1411#define single_plane_enabled(mask) is_power_of_2(mask)
1412
46ba614c 1413static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1414{
46ba614c 1415 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1416 static const int sr_latency_ns = 12000;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1419 int plane_sr, cursor_sr;
1420 unsigned int enabled = 0;
9858425c 1421 bool cxsr_enabled;
b445e3b0 1422
51cea1f4 1423 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1424 &g4x_wm_info, pessimal_latency_ns,
1425 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1426 &planea_wm, &cursora_wm))
51cea1f4 1427 enabled |= 1 << PIPE_A;
b445e3b0 1428
51cea1f4 1429 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1430 &g4x_wm_info, pessimal_latency_ns,
1431 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1432 &planeb_wm, &cursorb_wm))
51cea1f4 1433 enabled |= 1 << PIPE_B;
b445e3b0 1434
b445e3b0
ED		 1435 if (single_plane_enabled(enabled) &&
1436 g4x_compute_srwm(dev, ffs(enabled) - 1,
1437 sr_latency_ns,
1438 &g4x_wm_info,
1439 &g4x_cursor_wm_info,
52bd02d8 1440 &plane_sr, &cursor_sr)) {
9858425c 1441 cxsr_enabled = true;
52bd02d8 1442 } else {
9858425c 1443 cxsr_enabled = false;
5209b1f4 1444 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1445 plane_sr = cursor_sr = 0;
1446 }
b445e3b0 1447
a5043453
VS		 1448 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1449 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1450 planea_wm, cursora_wm,
1451 planeb_wm, cursorb_wm,
1452 plane_sr, cursor_sr);
1453
1454 I915_WRITE(DSPFW1,
f4998963
VS		 1455 FW_WM(plane_sr, SR) |
1456 FW_WM(cursorb_wm, CURSORB) |
1457 FW_WM(planeb_wm, PLANEB) |
1458 FW_WM(planea_wm, PLANEA));
b445e3b0 1459 I915_WRITE(DSPFW2,
8c919b28 1460 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1461 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1462 /* HPLL off in SR has some issues on G4x... disable it */
1463 I915_WRITE(DSPFW3,
8c919b28 1464 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1465 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1466
1467 if (cxsr_enabled)
1468 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1469}
1470
46ba614c 1471static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1472{
46ba614c 1473 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_crtc *crtc;
1476 int srwm = 1;
1477 int cursor_sr = 16;
9858425c 1478 bool cxsr_enabled;
b445e3b0
ED		 1479
1480 /* Calc sr entries for one plane configs */
1481 crtc = single_enabled_crtc(dev);
1482 if (crtc) {
1483 /* self-refresh has much higher latency */
1484 static const int sr_latency_ns = 12000;
124abe07 1485 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1486 int clock = adjusted_mode->crtc_clock;
fec8cba3 1487 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1488 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1489 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1490 unsigned long line_time_us;
1491 int entries;
1492
922044c9 1493 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1494
1495 /* Use ns/us then divide to preserve precision */
1496 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497 pixel_size * hdisplay;
1498 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1499 srwm = I965_FIFO_SIZE - entries;
1500 if (srwm < 0)
1501 srwm = 1;
1502 srwm &= 0x1ff;
1503 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1504 entries, srwm);
1505
1506 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1507 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1508 entries = DIV_ROUND_UP(entries,
1509 i965_cursor_wm_info.cacheline_size);
1510 cursor_sr = i965_cursor_wm_info.fifo_size -
1511 (entries + i965_cursor_wm_info.guard_size);
1512
1513 if (cursor_sr > i965_cursor_wm_info.max_wm)
1514 cursor_sr = i965_cursor_wm_info.max_wm;
1515
1516 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1517 "cursor %d\n", srwm, cursor_sr);
1518
9858425c 1519 cxsr_enabled = true;
b445e3b0 1520 } else {
9858425c 1521 cxsr_enabled = false;
b445e3b0 1522 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1523 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1524 }
1525
1526 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1527 srwm);
1528
1529 /* 965 has limitations... */
f4998963
VS		 1530 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1531 FW_WM(8, CURSORB) |
1532 FW_WM(8, PLANEB) |
1533 FW_WM(8, PLANEA));
1534 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1535 FW_WM(8, PLANEC_OLD));
b445e3b0 1536 /* update cursor SR watermark */
f4998963 1537 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1538
1539 if (cxsr_enabled)
1540 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1541}
1542
f4998963
VS		 1543#undef FW_WM
1544
46ba614c 1545static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1546{
46ba614c 1547 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1548 struct drm_i915_private *dev_priv = dev->dev_private;
1549 const struct intel_watermark_params *wm_info;
1550 uint32_t fwater_lo;
1551 uint32_t fwater_hi;
1552 int cwm, srwm = 1;
1553 int fifo_size;
1554 int planea_wm, planeb_wm;
1555 struct drm_crtc *crtc, *enabled = NULL;
1556
1557 if (IS_I945GM(dev))
1558 wm_info = &i945_wm_info;
1559 else if (!IS_GEN2(dev))
1560 wm_info = &i915_wm_info;
1561 else
9d539105 1562 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1563
1564 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1565 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1566 if (intel_crtc_active(crtc)) {
241bfc38 1567 const struct drm_display_mode *adjusted_mode;
59bea882 1568 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1569 if (IS_GEN2(dev))
1570 cpp = 4;
1571
6e3c9717 1572 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1573 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1574 wm_info, fifo_size, cpp,
5aef6003 1575 pessimal_latency_ns);
b445e3b0 1576 enabled = crtc;
9d539105 1577 } else {
b445e3b0 1578 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1579 if (planea_wm > (long)wm_info->max_wm)
1580 planea_wm = wm_info->max_wm;
1581 }
1582
1583 if (IS_GEN2(dev))
1584 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1585
1586 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1587 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1588 if (intel_crtc_active(crtc)) {
241bfc38 1589 const struct drm_display_mode *adjusted_mode;
59bea882 1590 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1591 if (IS_GEN2(dev))
1592 cpp = 4;
1593
6e3c9717 1594 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1595 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1596 wm_info, fifo_size, cpp,
5aef6003 1597 pessimal_latency_ns);
b445e3b0
ED		 1598 if (enabled == NULL)
1599 enabled = crtc;
1600 else
1601 enabled = NULL;
9d539105 1602 } else {
b445e3b0 1603 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1604 if (planeb_wm > (long)wm_info->max_wm)
1605 planeb_wm = wm_info->max_wm;
1606 }
b445e3b0
ED		 1607
1608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1609
2ab1bc9d 1610 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1611 struct drm_i915_gem_object *obj;
2ab1bc9d 1612
59bea882 1613 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1614
1615 /* self-refresh seems busted with untiled */
2ff8fde1 1616 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1617 enabled = NULL;
1618 }
1619
b445e3b0
ED		 1620 /*
1621 * Overlay gets an aggressive default since video jitter is bad.
1622 */
1623 cwm = 2;
1624
1625 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1626 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1627
1628 /* Calc sr entries for one plane configs */
1629 if (HAS_FW_BLC(dev) && enabled) {
1630 /* self-refresh has much higher latency */
1631 static const int sr_latency_ns = 6000;
124abe07 1632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1633 int clock = adjusted_mode->crtc_clock;
fec8cba3 1634 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1635 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1636 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1637 unsigned long line_time_us;
1638 int entries;
1639
922044c9 1640 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644 pixel_size * hdisplay;
1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
1651 if (IS_I945G(dev) || IS_I945GM(dev))
1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654 else if (IS_I915GM(dev))
1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
5209b1f4
ID		 1671 if (enabled)
1672 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1673}
1674
feb56b93 1675static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1676{
46ba614c 1677 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1678 struct drm_i915_private *dev_priv = dev->dev_private;
1679 struct drm_crtc *crtc;
241bfc38 1680 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1681 uint32_t fwater_lo;
1682 int planea_wm;
1683
1684 crtc = single_enabled_crtc(dev);
1685 if (crtc == NULL)
1686 return;
1687
6e3c9717 1688 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1689 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1690 &i845_wm_info,
b445e3b0 1691 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1692 4, pessimal_latency_ns);
b445e3b0
ED		 1693 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1694 fwater_lo |= (3<<8) | planea_wm;
1695
1696 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1697
1698 I915_WRITE(FW_BLC, fwater_lo);
1699}
1700
8cfb3407 1701uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1702{
fd4daa9c 1703 uint32_t pixel_rate;
801bcfff 1704
8cfb3407 1705 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1706
1707 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1708 * adjust the pixel_rate here. */
1709
8cfb3407 1710 if (pipe_config->pch_pfit.enabled) {
801bcfff 1711 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1712 uint32_t pfit_size = pipe_config->pch_pfit.size;
1713
1714 pipe_w = pipe_config->pipe_src_w;
1715 pipe_h = pipe_config->pipe_src_h;
801bcfff 1716
801bcfff
PZ		 1717 pfit_w = (pfit_size >> 16) & 0xFFFF;
1718 pfit_h = pfit_size & 0xFFFF;
1719 if (pipe_w < pfit_w)
1720 pipe_w = pfit_w;
1721 if (pipe_h < pfit_h)
1722 pipe_h = pfit_h;
1723
1724 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1725 pfit_w * pfit_h);
1726 }
1727
1728 return pixel_rate;
1729}
1730
37126462 1731/* latency must be in 0.1us units. */
23297044 1732static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1733 uint32_t latency)
1734{
1735 uint64_t ret;
1736
3312ba65
VS		 1737 if (WARN(latency == 0, "Latency value missing\n"))
1738 return UINT_MAX;
1739
801bcfff
PZ		 1740 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1741 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1742
1743 return ret;
1744}
1745
37126462 1746/* latency must be in 0.1us units. */
23297044 1747static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1748 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1749 uint32_t latency)
1750{
1751 uint32_t ret;
1752
3312ba65
VS		 1753 if (WARN(latency == 0, "Latency value missing\n"))
1754 return UINT_MAX;
1755
801bcfff
PZ		 1756 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1757 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1758 ret = DIV_ROUND_UP(ret, 64) + 2;
1759 return ret;
1760}
1761
23297044 1762static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1763 uint8_t bytes_per_pixel)
1764{
1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1766}
1767
820c1980 1768struct ilk_wm_maximums {
cca32e9a
PZ		 1769 uint16_t pri;
1770 uint16_t spr;
1771 uint16_t cur;
1772 uint16_t fbc;
1773};
1774
37126462
VS		 1775/*
1776 * For both WM_PIPE and WM_LP.
1777 * mem_value must be in 0.1us units.
1778 */
7221fc33 1779static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1780 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1781 uint32_t mem_value,
1782 bool is_lp)
801bcfff 1783{
43d59eda 1784 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
cca32e9a
PZ		 1785 uint32_t method1, method2;
1786
7221fc33 1787 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1788 return 0;
1789
7221fc33 1790 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
cca32e9a
PZ		 1791
1792 if (!is_lp)
1793 return method1;
1794
7221fc33
MR		 1795 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1796 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1797 drm_rect_width(&pstate->dst),
1798 bpp,
cca32e9a
PZ		 1799 mem_value);
1800
1801 return min(method1, method2);
801bcfff
PZ		 1802}
1803
37126462
VS		 1804/*
1805 * For both WM_PIPE and WM_LP.
1806 * mem_value must be in 0.1us units.
1807 */
7221fc33 1808static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1809 const struct intel_plane_state *pstate,
801bcfff
PZ		 1810 uint32_t mem_value)
1811{
43d59eda 1812 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
801bcfff
PZ		 1813 uint32_t method1, method2;
1814
7221fc33 1815 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1816 return 0;
1817
7221fc33
MR		 1818 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1819 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1820 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1821 drm_rect_width(&pstate->dst),
1822 bpp,
801bcfff
PZ		 1823 mem_value);
1824 return min(method1, method2);
1825}
1826
37126462
VS		 1827/*
1828 * For both WM_PIPE and WM_LP.
1829 * mem_value must be in 0.1us units.
1830 */
7221fc33 1831static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1832 const struct intel_plane_state *pstate,
801bcfff
PZ		 1833 uint32_t mem_value)
1834{
43d59eda
MR		 1835 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1836
7221fc33 1837 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1838 return 0;
1839
7221fc33
MR		 1840 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1841 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1842 drm_rect_width(&pstate->dst),
1843 bpp,
801bcfff
PZ		 1844 mem_value);
1845}
1846
cca32e9a 1847/* Only for WM_LP. */
7221fc33 1848static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1849 const struct intel_plane_state *pstate,
1fda9882 1850 uint32_t pri_val)
cca32e9a 1851{
43d59eda
MR		 1852 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1853
7221fc33 1854 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1855 return 0;
1856
43d59eda 1857 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
cca32e9a
PZ		 1858}
1859
158ae64f
VS		 1860static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1861{
416f4727
VS		 1862 if (INTEL_INFO(dev)->gen >= 8)
1863 return 3072;
1864 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1865 return 768;
1866 else
1867 return 512;
1868}
1869
4e975081
VS		 1870static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1871 int level, bool is_sprite)
1872{
1873 if (INTEL_INFO(dev)->gen >= 8)
1874 /* BDW primary/sprite plane watermarks */
1875 return level == 0 ? 255 : 2047;
1876 else if (INTEL_INFO(dev)->gen >= 7)
1877 /* IVB/HSW primary/sprite plane watermarks */
1878 return level == 0 ? 127 : 1023;
1879 else if (!is_sprite)
1880 /* ILK/SNB primary plane watermarks */
1881 return level == 0 ? 127 : 511;
1882 else
1883 /* ILK/SNB sprite plane watermarks */
1884 return level == 0 ? 63 : 255;
1885}
1886
1887static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1888 int level)
1889{
1890 if (INTEL_INFO(dev)->gen >= 7)
1891 return level == 0 ? 63 : 255;
1892 else
1893 return level == 0 ? 31 : 63;
1894}
1895
1896static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1897{
1898 if (INTEL_INFO(dev)->gen >= 8)
1899 return 31;
1900 else
1901 return 15;
1902}
1903
158ae64f
VS		 1904/* Calculate the maximum primary/sprite plane watermark */
1905static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1906 int level,
240264f4 1907 const struct intel_wm_config *config,
158ae64f
VS		 1908 enum intel_ddb_partitioning ddb_partitioning,
1909 bool is_sprite)
1910{
1911 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1912
1913 /* if sprites aren't enabled, sprites get nothing */
240264f4 1914 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1915 return 0;
1916
1917 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1918 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1919 fifo_size /= INTEL_INFO(dev)->num_pipes;
1920
1921 /*
1922 * For some reason the non self refresh
1923 * FIFO size is only half of the self
1924 * refresh FIFO size on ILK/SNB.
1925 */
1926 if (INTEL_INFO(dev)->gen <= 6)
1927 fifo_size /= 2;
1928 }
1929
240264f4 1930 if (config->sprites_enabled) {
158ae64f
VS		 1931 /* level 0 is always calculated with 1:1 split */
1932 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1933 if (is_sprite)
1934 fifo_size *= 5;
1935 fifo_size /= 6;
1936 } else {
1937 fifo_size /= 2;
1938 }
1939 }
1940
1941 /* clamp to max that the registers can hold */
4e975081 1942 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1943}
1944
1945/* Calculate the maximum cursor plane watermark */
1946static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1947 int level,
1948 const struct intel_wm_config *config)
158ae64f
VS		 1949{
1950 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1951 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1952 return 64;
1953
1954 /* otherwise just report max that registers can hold */
4e975081 1955 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1956}
1957
d34ff9c6 1958static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1959 int level,
1960 const struct intel_wm_config *config,
1961 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1962 struct ilk_wm_maximums *max)
158ae64f 1963{
240264f4
VS		 1964 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1965 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1966 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1967 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1968}
1969
a3cb4048
VS		 1970static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1971 int level,
1972 struct ilk_wm_maximums *max)
1973{
1974 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1975 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1976 max->cur = ilk_cursor_wm_reg_max(dev, level);
1977 max->fbc = ilk_fbc_wm_reg_max(dev);
1978}
1979
d9395655 1980static bool ilk_validate_wm_level(int level,
820c1980 1981 const struct ilk_wm_maximums *max,
d9395655 1982 struct intel_wm_level *result)
a9786a11
VS		 1983{
1984 bool ret;
1985
1986 /* already determined to be invalid? */
1987 if (!result->enable)
1988 return false;
1989
1990 result->enable = result->pri_val <= max->pri &&
1991 result->spr_val <= max->spr &&
1992 result->cur_val <= max->cur;
1993
1994 ret = result->enable;
1995
1996 /*
1997 * HACK until we can pre-compute everything,
1998 * and thus fail gracefully if LP0 watermarks
1999 * are exceeded...
2000 */
2001 if (level == 0 && !result->enable) {
2002 if (result->pri_val > max->pri)
2003 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2004 level, result->pri_val, max->pri);
2005 if (result->spr_val > max->spr)
2006 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2007 level, result->spr_val, max->spr);
2008 if (result->cur_val > max->cur)
2009 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2010 level, result->cur_val, max->cur);
2011
2012 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2013 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2014 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2015 result->enable = true;
2016 }
2017
a9786a11
VS		 2018 return ret;
2019}
2020
d34ff9c6 2021static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2022 const struct intel_crtc *intel_crtc,
6f5ddd17 2023 int level,
7221fc33 2024 struct intel_crtc_state *cstate,
a28170f3
MR		 2025 struct intel_plane_state *pristate,
2026 struct intel_plane_state *sprstate,
2027 struct intel_plane_state *curstate,
1fd527cc 2028 struct intel_wm_level *result)
6f5ddd17
VS		 2029{
2030 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2031 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2032 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2033
2034 /* WM1+ latency values stored in 0.5us units */
2035 if (level > 0) {
2036 pri_latency *= 5;
2037 spr_latency *= 5;
2038 cur_latency *= 5;
2039 }
2040
a28170f3
MR		 2041 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2042 pri_latency, level);
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2045 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 2046 result->enable = true;
2047}
2048
801bcfff
PZ		 2049static uint32_t
2050hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2051{
2052 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7c5f93b0 2054 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2055 u32 linetime, ips_linetime;
1f8eeabf 2056
3ef00284 2057 if (!intel_crtc->active)
801bcfff 2058 return 0;
1011d8c4 2059
1f8eeabf
ED		 2060 /* The WM are computed with base on how long it takes to fill a single
2061 * row at the given clock rate, multiplied by 8.
2062 * */
124abe07
VS		 2063 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2064 adjusted_mode->crtc_clock);
2065 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2066 dev_priv->cdclk_freq);
1f8eeabf 2067
801bcfff
PZ		 2068 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2069 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2070}
2071
2af30a5c 2072static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2073{
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075
2af30a5c
PB		 2076 if (IS_GEN9(dev)) {
2077 uint32_t val;
4f947386 2078 int ret, i;
367294be 2079 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2080
2081 /* read the first set of memory latencies[0:3] */
2082 val = 0; /* data0 to be programmed to 0 for first set */
2083 mutex_lock(&dev_priv->rps.hw_lock);
2084 ret = sandybridge_pcode_read(dev_priv,
2085 GEN9_PCODE_READ_MEM_LATENCY,
2086 &val);
2087 mutex_unlock(&dev_priv->rps.hw_lock);
2088
2089 if (ret) {
2090 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2091 return;
2092 }
2093
2094 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2095 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2096 GEN9_MEM_LATENCY_LEVEL_MASK;
2097 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2098 GEN9_MEM_LATENCY_LEVEL_MASK;
2099 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2100 GEN9_MEM_LATENCY_LEVEL_MASK;
2101
2102 /* read the second set of memory latencies[4:7] */
2103 val = 1; /* data0 to be programmed to 1 for second set */
2104 mutex_lock(&dev_priv->rps.hw_lock);
2105 ret = sandybridge_pcode_read(dev_priv,
2106 GEN9_PCODE_READ_MEM_LATENCY,
2107 &val);
2108 mutex_unlock(&dev_priv->rps.hw_lock);
2109 if (ret) {
2110 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2111 return;
2112 }
2113
2114 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2115 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2116 GEN9_MEM_LATENCY_LEVEL_MASK;
2117 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2118 GEN9_MEM_LATENCY_LEVEL_MASK;
2119 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2120 GEN9_MEM_LATENCY_LEVEL_MASK;
2121
367294be 2122 /*
6f97235b
DL		 2123 * WaWmMemoryReadLatency:skl
2124 *
367294be
VK		 2125 * punit doesn't take into account the read latency so we need
2126 * to add 2us to the various latency levels we retrieve from
2127 * the punit.
2128 * - W0 is a bit special in that it's the only level that
2129 * can't be disabled if we want to have display working, so
2130 * we always add 2us there.
2131 * - For levels >=1, punit returns 0us latency when they are
2132 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2133 *
2134 * Additionally, if a level n (n > 1) has a 0us latency, all
2135 * levels m (m >= n) need to be disabled. We make sure to
2136 * sanitize the values out of the punit to satisfy this
2137 * requirement.
367294be
VK		 2138 */
2139 wm[0] += 2;
2140 for (level = 1; level <= max_level; level++)
2141 if (wm[level] != 0)
2142 wm[level] += 2;
4f947386
VK		 2143 else {
2144 for (i = level + 1; i <= max_level; i++)
2145 wm[i] = 0;
367294be 2146
4f947386
VK		 2147 break;
2148 }
2af30a5c 2149 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2150 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2151
2152 wm[0] = (sskpd >> 56) & 0xFF;
2153 if (wm[0] == 0)
2154 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2155 wm[1] = (sskpd >> 4) & 0xFF;
2156 wm[2] = (sskpd >> 12) & 0xFF;
2157 wm[3] = (sskpd >> 20) & 0x1FF;
2158 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2159 } else if (INTEL_INFO(dev)->gen >= 6) {
2160 uint32_t sskpd = I915_READ(MCH_SSKPD);
2161
2162 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2163 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2164 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2165 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2166 } else if (INTEL_INFO(dev)->gen >= 5) {
2167 uint32_t mltr = I915_READ(MLTR_ILK);
2168
2169 /* ILK primary LP0 latency is 700 ns */
2170 wm[0] = 7;
2171 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2172 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2173 }
2174}
2175
53615a5e
VS		 2176static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2177{
2178 /* ILK sprite LP0 latency is 1300 ns */
2179 if (INTEL_INFO(dev)->gen == 5)
2180 wm[0] = 13;
2181}
2182
2183static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184{
2185 /* ILK cursor LP0 latency is 1300 ns */
2186 if (INTEL_INFO(dev)->gen == 5)
2187 wm[0] = 13;
2188
2189 /* WaDoubleCursorLP3Latency:ivb */
2190 if (IS_IVYBRIDGE(dev))
2191 wm[3] *= 2;
2192}
2193
546c81fd 2194int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2195{
26ec971e 2196 /* how many WM levels are we expecting */
b6e742f6 2197 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2198 return 7;
2199 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2200 return 4;
26ec971e 2201 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2202 return 3;
26ec971e 2203 else
ad0d6dc4
VS		 2204 return 2;
2205}
7526ed79 2206
ad0d6dc4
VS		 2207static void intel_print_wm_latency(struct drm_device *dev,
2208 const char *name,
2af30a5c 2209 const uint16_t wm[8])
ad0d6dc4
VS		 2210{
2211 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2212
2213 for (level = 0; level <= max_level; level++) {
2214 unsigned int latency = wm[level];
2215
2216 if (latency == 0) {
2217 DRM_ERROR("%s WM%d latency not provided\n",
2218 name, level);
2219 continue;
2220 }
2221
2af30a5c
PB		 2222 /*
2223 * - latencies are in us on gen9.
2224 * - before then, WM1+ latency values are in 0.5us units
2225 */
2226 if (IS_GEN9(dev))
2227 latency *= 10;
2228 else if (level > 0)
26ec971e
VS		 2229 latency *= 5;
2230
2231 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2232 name, level, wm[level],
2233 latency / 10, latency % 10);
2234 }
2235}
2236
e95a2f75
VS		 2237static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2238 uint16_t wm[5], uint16_t min)
2239{
2240 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2241
2242 if (wm[0] >= min)
2243 return false;
2244
2245 wm[0] = max(wm[0], min);
2246 for (level = 1; level <= max_level; level++)
2247 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2248
2249 return true;
2250}
2251
2252static void snb_wm_latency_quirk(struct drm_device *dev)
2253{
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 bool changed;
2256
2257 /*
2258 * The BIOS provided WM memory latency values are often
2259 * inadequate for high resolution displays. Adjust them.
2260 */
2261 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2262 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2263 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2264
2265 if (!changed)
2266 return;
2267
2268 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2269 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2270 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2271 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2272}
2273
fa50ad61 2274static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2275{
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277
2278 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2279
2280 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2281 sizeof(dev_priv->wm.pri_latency));
2282 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2283 sizeof(dev_priv->wm.pri_latency));
2284
2285 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2286 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2287
2288 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2289 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2290 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2291
2292 if (IS_GEN6(dev))
2293 snb_wm_latency_quirk(dev);
53615a5e
VS		 2294}
2295
2af30a5c
PB		 2296static void skl_setup_wm_latency(struct drm_device *dev)
2297{
2298 struct drm_i915_private *dev_priv = dev->dev_private;
2299
2300 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2301 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2302}
2303
0b2ae6d7 2304/* Compute new watermarks for the pipe */
a28170f3
MR		 2305static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2306 struct drm_atomic_state *state)
0b2ae6d7 2307{
a28170f3
MR		 2308 struct intel_pipe_wm *pipe_wm;
2309 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2310 const struct drm_i915_private *dev_priv = dev->dev_private;
a28170f3 2311 struct intel_crtc_state *cstate = NULL;
43d59eda 2312 struct intel_plane *intel_plane;
a28170f3
MR		 2313 struct drm_plane_state *ps;
2314 struct intel_plane_state *pristate = NULL;
43d59eda 2315 struct intel_plane_state *sprstate = NULL;
a28170f3 2316 struct intel_plane_state *curstate = NULL;
0b2ae6d7
VS		 2317 int level, max_level = ilk_wm_max_level(dev);
2318 /* LP0 watermark maximums depend on this pipe alone */
2319 struct intel_wm_config config = {
2320 .num_pipes_active = 1,
0b2ae6d7 2321 };
820c1980 2322 struct ilk_wm_maximums max;
0b2ae6d7 2323
a28170f3
MR		 2324 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2325 if (IS_ERR(cstate))
2326 return PTR_ERR(cstate);
2327
2328 pipe_wm = &cstate->wm.optimal.ilk;
2329
43d59eda 2330 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
a28170f3
MR		 2331 ps = drm_atomic_get_plane_state(state,
2332 &intel_plane->base);
2333 if (IS_ERR(ps))
2334 return PTR_ERR(ps);
2335
2336 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2337 pristate = to_intel_plane_state(ps);
2338 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2339 sprstate = to_intel_plane_state(ps);
2340 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2341 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2342 }
2343
2344 config.sprites_enabled = sprstate->visible;
2345 config.sprites_scaled = sprstate->visible &&
2346 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2347 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2348
7221fc33 2349 pipe_wm->pipe_enabled = cstate->base.active;
a28170f3 2350 pipe_wm->sprites_enabled = config.sprites_enabled;
43d59eda 2351 pipe_wm->sprites_scaled = config.sprites_scaled;
2a44b76b 2352
7b39a0b7 2353 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2354 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2355 max_level = 1;
2356
2357 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
43d59eda 2358 if (config.sprites_scaled)
7b39a0b7
VS		 2359 max_level = 0;
2360
a28170f3
MR		 2361 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2362 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2363
a42a5719 2364 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a28170f3
MR		 2365 pipe_wm->linetime = hsw_compute_linetime_wm(dev,
2366 &intel_crtc->base);
0b2ae6d7 2367
a3cb4048
VS		 2368 /* LP0 watermarks always use 1/2 DDB partitioning */
2369 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2370
0b2ae6d7 2371 /* At least LP0 must be valid */
a3cb4048 2372 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
a28170f3 2373 return -EINVAL;
a3cb4048
VS		 2374
2375 ilk_compute_wm_reg_maximums(dev, 1, &max);
2376
2377 for (level = 1; level <= max_level; level++) {
2378 struct intel_wm_level wm = {};
2379
a28170f3
MR		 2380 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2381 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2382
2383 /*
2384 * Disable any watermark level that exceeds the
2385 * register maximums since such watermarks are
2386 * always invalid.
2387 */
2388 if (!ilk_validate_wm_level(level, &max, &wm))
2389 break;
2390
2391 pipe_wm->wm[level] = wm;
2392 }
2393
a28170f3 2394 return 0;
0b2ae6d7
VS		 2395}
2396
2397/*
2398 * Merge the watermarks from all active pipes for a specific level.
2399 */
2400static void ilk_merge_wm_level(struct drm_device *dev,
2401 int level,
2402 struct intel_wm_level *ret_wm)
2403{
2404 const struct intel_crtc *intel_crtc;
2405
d52fea5b
VS		 2406 ret_wm->enable = true;
2407
d3fcc808 2408 for_each_intel_crtc(dev, intel_crtc) {
de4a9f83
MR		 2409 const struct intel_crtc_state *cstate =
2410 to_intel_crtc_state(intel_crtc->base.state);
2411 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
fe392efd
VS		 2412 const struct intel_wm_level *wm = &active->wm[level];
2413
2414 if (!active->pipe_enabled)
2415 continue;
0b2ae6d7 2416
d52fea5b
VS		 2417 /*
2418 * The watermark values may have been used in the past,
2419 * so we must maintain them in the registers for some
2420 * time even if the level is now disabled.
2421 */
0b2ae6d7 2422 if (!wm->enable)
d52fea5b 2423 ret_wm->enable = false;
0b2ae6d7
VS		 2424
2425 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2426 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2427 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2428 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2429 }
0b2ae6d7
VS		 2430}
2431
2432/*
2433 * Merge all low power watermarks for all active pipes.
2434 */
2435static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2436 const struct intel_wm_config *config,
820c1980 2437 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2438 struct intel_pipe_wm *merged)
2439{
7733b49b 2440 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2441 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2442 int last_enabled_level = max_level;
0b2ae6d7 2443
0ba22e26
VS		 2444 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2445 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2446 config->num_pipes_active > 1)
2447 return;
2448
6c8b6c28
VS		 2449 /* ILK: FBC WM must be disabled always */
2450 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2451
2452 /* merge each WM1+ level */
2453 for (level = 1; level <= max_level; level++) {
2454 struct intel_wm_level *wm = &merged->wm[level];
2455
2456 ilk_merge_wm_level(dev, level, wm);
2457
d52fea5b
VS		 2458 if (level > last_enabled_level)
2459 wm->enable = false;
2460 else if (!ilk_validate_wm_level(level, max, wm))
2461 /* make sure all following levels get disabled */
2462 last_enabled_level = level - 1;
0b2ae6d7
VS		 2463
2464 /*
2465 * The spec says it is preferred to disable
2466 * FBC WMs instead of disabling a WM level.
2467 */
2468 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2469 if (wm->enable)
2470 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2471 wm->fbc_val = 0;
2472 }
2473 }
6c8b6c28
VS		 2474
2475 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2476 /*
2477 * FIXME this is racy. FBC might get enabled later.
2478 * What we should check here is whether FBC can be
2479 * enabled sometime later.
2480 */
7733b49b
PZ		 2481 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2482 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2483 for (level = 2; level <= max_level; level++) {
2484 struct intel_wm_level *wm = &merged->wm[level];
2485
2486 wm->enable = false;
2487 }
2488 }
0b2ae6d7
VS		 2489}
2490
b380ca3c
VS		 2491static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2492{
2493 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2494 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2495}
2496
a68d68ee
VS		 2497/* The value we need to program into the WM_LPx latency field */
2498static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2499{
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2501
a42a5719 2502 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2503 return 2 * level;
2504 else
2505 return dev_priv->wm.pri_latency[level];
2506}
2507
820c1980 2508static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2509 const struct intel_pipe_wm *merged,
609cedef 2510 enum intel_ddb_partitioning partitioning,
820c1980 2511 struct ilk_wm_values *results)
801bcfff 2512{
0b2ae6d7
VS		 2513 struct intel_crtc *intel_crtc;
2514 int level, wm_lp;
cca32e9a 2515
0362c781 2516 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2517 results->partitioning = partitioning;
cca32e9a 2518
0b2ae6d7 2519 /* LP1+ register values */
cca32e9a 2520 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2521 const struct intel_wm_level *r;
801bcfff 2522
b380ca3c 2523 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2524
0362c781 2525 r = &merged->wm[level];
cca32e9a 2526
d52fea5b
VS		 2527 /*
2528 * Maintain the watermark values even if the level is
2529 * disabled. Doing otherwise could cause underruns.
2530 */
2531 results->wm_lp[wm_lp - 1] =
a68d68ee 2532 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2533 (r->pri_val << WM1_LP_SR_SHIFT) |
2534 r->cur_val;
2535
d52fea5b
VS		 2536 if (r->enable)
2537 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2538
416f4727
VS		 2539 if (INTEL_INFO(dev)->gen >= 8)
2540 results->wm_lp[wm_lp - 1] |=
2541 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2542 else
2543 results->wm_lp[wm_lp - 1] |=
2544 r->fbc_val << WM1_LP_FBC_SHIFT;
2545
d52fea5b
VS		 2546 /*
2547 * Always set WM1S_LP_EN when spr_val != 0, even if the
2548 * level is disabled. Doing otherwise could cause underruns.
2549 */
6cef2b8a
VS		 2550 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2551 WARN_ON(wm_lp != 1);
2552 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2553 } else
2554 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2555 }
801bcfff 2556
0b2ae6d7 2557 /* LP0 register values */
d3fcc808 2558 for_each_intel_crtc(dev, intel_crtc) {
de4a9f83
MR		 2559 const struct intel_crtc_state *cstate =
2560 to_intel_crtc_state(intel_crtc->base.state);
0b2ae6d7 2561 enum pipe pipe = intel_crtc->pipe;
de4a9f83 2562 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
0b2ae6d7
VS		 2563
2564 if (WARN_ON(!r->enable))
2565 continue;
2566
de4a9f83 2567 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
1011d8c4 2568
0b2ae6d7
VS		 2569 results->wm_pipe[pipe] =
2570 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2571 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2572 r->cur_val;
801bcfff
PZ		 2573 }
2574}
2575
861f3389
PZ		 2576/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2577 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2578static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2579 struct intel_pipe_wm *r1,
2580 struct intel_pipe_wm *r2)
861f3389 2581{
198a1e9b
VS		 2582 int level, max_level = ilk_wm_max_level(dev);
2583 int level1 = 0, level2 = 0;
861f3389 2584
198a1e9b
VS		 2585 for (level = 1; level <= max_level; level++) {
2586 if (r1->wm[level].enable)
2587 level1 = level;
2588 if (r2->wm[level].enable)
2589 level2 = level;
861f3389
PZ		 2590 }
2591
198a1e9b
VS		 2592 if (level1 == level2) {
2593 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2594 return r2;
2595 else
2596 return r1;
198a1e9b 2597 } else if (level1 > level2) {
861f3389
PZ		 2598 return r1;
2599 } else {
2600 return r2;
2601 }
2602}
2603
49a687c4
VS		 2604/* dirty bits used to track which watermarks need changes */
2605#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2606#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2607#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2608#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2609#define WM_DIRTY_FBC (1 << 24)
2610#define WM_DIRTY_DDB (1 << 25)
2611
055e393f 2612static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2613 const struct ilk_wm_values *old,
2614 const struct ilk_wm_values *new)
49a687c4
VS		 2615{
2616 unsigned int dirty = 0;
2617 enum pipe pipe;
2618 int wm_lp;
2619
055e393f 2620 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2621 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2622 dirty |= WM_DIRTY_LINETIME(pipe);
2623 /* Must disable LP1+ watermarks too */
2624 dirty |= WM_DIRTY_LP_ALL;
2625 }
2626
2627 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2628 dirty |= WM_DIRTY_PIPE(pipe);
2629 /* Must disable LP1+ watermarks too */
2630 dirty |= WM_DIRTY_LP_ALL;
2631 }
2632 }
2633
2634 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2635 dirty |= WM_DIRTY_FBC;
2636 /* Must disable LP1+ watermarks too */
2637 dirty |= WM_DIRTY_LP_ALL;
2638 }
2639
2640 if (old->partitioning != new->partitioning) {
2641 dirty |= WM_DIRTY_DDB;
2642 /* Must disable LP1+ watermarks too */
2643 dirty |= WM_DIRTY_LP_ALL;
2644 }
2645
2646 /* LP1+ watermarks already deemed dirty, no need to continue */
2647 if (dirty & WM_DIRTY_LP_ALL)
2648 return dirty;
2649
2650 /* Find the lowest numbered LP1+ watermark in need of an update... */
2651 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2652 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2653 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2654 break;
2655 }
2656
2657 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2658 for (; wm_lp <= 3; wm_lp++)
2659 dirty |= WM_DIRTY_LP(wm_lp);
2660
2661 return dirty;
2662}
2663
8553c18e
VS		 2664static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2665 unsigned int dirty)
801bcfff 2666{
820c1980 2667 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2668 bool changed = false;
801bcfff 2669
facd619b
VS		 2670 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2671 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2672 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2673 changed = true;
facd619b
VS		 2674 }
2675 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2676 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2677 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2678 changed = true;
facd619b
VS		 2679 }
2680 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2681 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2682 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2683 changed = true;
facd619b 2684 }
801bcfff 2685
facd619b
VS		 2686 /*
2687 * Don't touch WM1S_LP_EN here.
2688 * Doing so could cause underruns.
2689 */
6cef2b8a 2690
8553c18e
VS		 2691 return changed;
2692}
2693
2694/*
2695 * The spec says we shouldn't write when we don't need, because every write
2696 * causes WMs to be re-evaluated, expending some power.
2697 */
820c1980
ID		 2698static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2699 struct ilk_wm_values *results)
8553c18e
VS		 2700{
2701 struct drm_device *dev = dev_priv->dev;
820c1980 2702 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2703 unsigned int dirty;
2704 uint32_t val;
2705
055e393f 2706 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2707 if (!dirty)
2708 return;
2709
2710 _ilk_disable_lp_wm(dev_priv, dirty);
2711
49a687c4 2712 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2713 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2714 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2715 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2716 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2717 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2718
49a687c4 2719 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2720 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2721 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2722 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2723 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2724 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2725
49a687c4 2726 if (dirty & WM_DIRTY_DDB) {
a42a5719 2727 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2728 val = I915_READ(WM_MISC);
2729 if (results->partitioning == INTEL_DDB_PART_1_2)
2730 val &= ~WM_MISC_DATA_PARTITION_5_6;
2731 else
2732 val |= WM_MISC_DATA_PARTITION_5_6;
2733 I915_WRITE(WM_MISC, val);
2734 } else {
2735 val = I915_READ(DISP_ARB_CTL2);
2736 if (results->partitioning == INTEL_DDB_PART_1_2)
2737 val &= ~DISP_DATA_PARTITION_5_6;
2738 else
2739 val |= DISP_DATA_PARTITION_5_6;
2740 I915_WRITE(DISP_ARB_CTL2, val);
2741 }
1011d8c4
PZ		 2742 }
2743
49a687c4 2744 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2745 val = I915_READ(DISP_ARB_CTL);
2746 if (results->enable_fbc_wm)
2747 val &= ~DISP_FBC_WM_DIS;
2748 else
2749 val |= DISP_FBC_WM_DIS;
2750 I915_WRITE(DISP_ARB_CTL, val);
2751 }
2752
954911eb
ID		 2753 if (dirty & WM_DIRTY_LP(1) &&
2754 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2755 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2756
2757 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2758 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2759 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2760 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2761 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2762 }
801bcfff 2763
facd619b 2764 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2765 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2766 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2767 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2768 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2769 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2770
2771 dev_priv->wm.hw = *results;
801bcfff
PZ		 2772}
2773
8553c18e
VS		 2774static bool ilk_disable_lp_wm(struct drm_device *dev)
2775{
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777
2778 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2779}
2780
b9cec075
DL		 2781/*
2782 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2783 * different active planes.
2784 */
2785
2786#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2787#define BXT_DDB_SIZE 512
b9cec075 2788
3a05f5e2
MR		 2789/*
2790 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2791 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2792 * other universal planes are in indices 1..n. Note that this may leave unused
2793 * indices between the top "sprite" plane and the cursor.
2794 */
2795static int
2796skl_wm_plane_id(const struct intel_plane *plane)
2797{
2798 switch (plane->base.type) {
2799 case DRM_PLANE_TYPE_PRIMARY:
2800 return 0;
2801 case DRM_PLANE_TYPE_CURSOR:
2802 return PLANE_CURSOR;
2803 case DRM_PLANE_TYPE_OVERLAY:
2804 return plane->plane + 1;
2805 default:
2806 MISSING_CASE(plane->base.type);
2807 return plane->plane;
2808 }
2809}
2810
b9cec075
DL		 2811static void
2812skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3a05f5e2 2813 const struct intel_crtc_state *cstate,
b9cec075 2814 const struct intel_wm_config *config,
b9cec075
DL		 2815 struct skl_ddb_entry *alloc /* out */)
2816{
3a05f5e2 2817 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2818 struct drm_crtc *crtc;
2819 unsigned int pipe_size, ddb_size;
2820 int nth_active_pipe;
2821
3a05f5e2 2822 if (!cstate->base.active) {
b9cec075
DL		 2823 alloc->start = 0;
2824 alloc->end = 0;
2825 return;
2826 }
2827
43d735a6
DL		 2828 if (IS_BROXTON(dev))
2829 ddb_size = BXT_DDB_SIZE;
2830 else
2831 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2832
2833 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2834
2835 nth_active_pipe = 0;
2836 for_each_crtc(dev, crtc) {
3ef00284 2837 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2838 continue;
2839
2840 if (crtc == for_crtc)
2841 break;
2842
2843 nth_active_pipe++;
2844 }
2845
2846 pipe_size = ddb_size / config->num_pipes_active;
2847 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2848 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2849}
2850
2851static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2852{
2853 if (config->num_pipes_active == 1)
2854 return 32;
2855
2856 return 8;
2857}
2858
a269c583
DL		 2859static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2860{
2861 entry->start = reg & 0x3ff;
2862 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2863 if (entry->end)
2864 entry->end += 1;
a269c583
DL		 2865}
2866
08db6652
DL		 2867void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2868 struct skl_ddb_allocation *ddb /* out */)
a269c583 2869{
a269c583
DL		 2870 enum pipe pipe;
2871 int plane;
2872 u32 val;
2873
2874 for_each_pipe(dev_priv, pipe) {
dd740780 2875 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2876 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2877 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2878 val);
2879 }
2880
2881 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2882 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2883 val);
a269c583
DL		 2884 }
2885}
2886
b9cec075 2887static unsigned int
3a05f5e2
MR		 2888skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2889 const struct drm_plane_state *pstate,
2890 int y)
b9cec075 2891{
3a05f5e2
MR		 2892 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2893 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2894
2895 /* for planar format */
3a05f5e2 2896 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2897 if (y) /* y-plane data rate */
3a05f5e2
MR		 2898 return intel_crtc->config->pipe_src_w *
2899 intel_crtc->config->pipe_src_h *
2900 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2901 else /* uv-plane data rate */
3a05f5e2
MR		 2902 return (intel_crtc->config->pipe_src_w/2) *
2903 (intel_crtc->config->pipe_src_h/2) *
2904 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2905 }
2906
2907 /* for packed formats */
3a05f5e2
MR		 2908 return intel_crtc->config->pipe_src_w *
2909 intel_crtc->config->pipe_src_h *
2910 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2911}
2912
2913/*
2914 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2915 * a 8192x4096@32bpp framebuffer:
2916 * 3 * 4096 * 8192 * 4 < 2^32
2917 */
2918static unsigned int
3a05f5e2 2919skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2920{
3a05f5e2
MR		 2921 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2922 struct drm_device *dev = intel_crtc->base.dev;
2923 const struct intel_plane *intel_plane;
b9cec075 2924 unsigned int total_data_rate = 0;
b9cec075 2925
3a05f5e2
MR		 2926 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2927 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2928
3a05f5e2 2929 if (pstate->fb == NULL)
b9cec075
DL		 2930 continue;
2931
3a05f5e2
MR		 2932 /* packed/uv */
2933 total_data_rate += skl_plane_relative_data_rate(cstate,
2934 pstate,
2935 0);
2936
2937 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2938 /* y-plane */
2939 total_data_rate += skl_plane_relative_data_rate(cstate,
2940 pstate,
2941 1);
b9cec075
DL		 2942 }
2943
2944 return total_data_rate;
2945}
2946
2947static void
3a05f5e2 2948skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2949 struct skl_ddb_allocation *ddb /* out */)
2950{
3a05f5e2 2951 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2952 struct drm_device *dev = crtc->dev;
76305b1a
MR		 2953 struct drm_i915_private *dev_priv = to_i915(dev);
2954 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3a05f5e2 2956 struct intel_plane *intel_plane;
b9cec075 2957 enum pipe pipe = intel_crtc->pipe;
34bb56af 2958 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2959 uint16_t alloc_size, start, cursor_blocks;
80958155 2960 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2961 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2962 unsigned int total_data_rate;
b9cec075 2963
3a05f5e2 2964 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2965 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2966 if (alloc_size == 0) {
2967 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2968 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2969 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2970 return;
2971 }
2972
2973 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2974 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2975 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2976
2977 alloc_size -= cursor_blocks;
34bb56af 2978 alloc->end -= cursor_blocks;
b9cec075 2979
80958155 2980 /* 1. Allocate the mininum required blocks for each active plane */
3a05f5e2
MR		 2981 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2982 struct drm_plane *plane = &intel_plane->base;
2983 struct drm_framebuffer *fb = plane->fb;
2984 int id = skl_wm_plane_id(intel_plane);
80958155 2985
3a05f5e2
MR		 2986 if (fb == NULL)
2987 continue;
2988 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2989 continue;
2990
3a05f5e2
MR		 2991 minimum[id] = 8;
2992 alloc_size -= minimum[id];
2993 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2994 alloc_size -= y_minimum[id];
80958155
DL		 2995 }
2996
b9cec075 2997 /*
80958155
DL		 2998 * 2. Distribute the remaining space in proportion to the amount of
2999 * data each plane needs to fetch from memory.
b9cec075
DL		 3000 *
3001 * FIXME: we may not allocate every single block here.
3002 */
3a05f5e2 3003 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 3004
34bb56af 3005 start = alloc->start;
3a05f5e2
MR		 3006 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3007 struct drm_plane *plane = &intel_plane->base;
3008 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 3009 unsigned int data_rate, y_data_rate;
3010 uint16_t plane_blocks, y_plane_blocks = 0;
3a05f5e2 3011 int id = skl_wm_plane_id(intel_plane);
b9cec075 3012
3a05f5e2
MR		 3013 if (pstate->fb == NULL)
3014 continue;
3015 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 3016 continue;
3017
3a05f5e2 3018 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3019
3020 /*
2cd601c6 3021 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3022 * promote the expression to 64 bits to avoid overflowing, the
3023 * result is < available as data_rate / total_data_rate < 1
3024 */
3a05f5e2 3025 plane_blocks = minimum[id];
80958155
DL		 3026 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3027 total_data_rate);
b9cec075 3028
3a05f5e2
MR		 3029 ddb->plane[pipe][id].start = start;
3030 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3031
3032 start += plane_blocks;
2cd601c6
CK		 3033
3034 /*
3035 * allocation for y_plane part of planar format:
3036 */
3a05f5e2
MR		 3037 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3038 y_data_rate = skl_plane_relative_data_rate(cstate,
3039 pstate,
3040 1);
3041 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3042 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3043 total_data_rate);
3044
3a05f5e2
MR		 3045 ddb->y_plane[pipe][id].start = start;
3046 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3047
3048 start += y_plane_blocks;
3049 }
3050
b9cec075
DL		 3051 }
3052
3053}
3054
5cec258b 3055static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3056{
3057 /* TODO: Take into account the scalers once we support them */
2d112de7 3058 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3059}
3060
3061/*
3062 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3063 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3064 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3065 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3066*/
3067static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3068 uint32_t latency)
3069{
3070 uint32_t wm_intermediate_val, ret;
3071
3072 if (latency == 0)
3073 return UINT_MAX;
3074
d4c2aa60 3075 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3076 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3077
3078 return ret;
3079}
3080
3081static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3082 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3083 uint64_t tiling, uint32_t latency)
2d41c0b5 3084{
d4c2aa60
TU		 3085 uint32_t ret;
3086 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3087 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3088
3089 if (latency == 0)
3090 return UINT_MAX;
3091
3092 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3093
3094 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3095 tiling == I915_FORMAT_MOD_Yf_TILED) {
3096 plane_bytes_per_line *= 4;
3097 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3098 plane_blocks_per_line /= 4;
3099 } else {
3100 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3101 }
3102
2d41c0b5
PB		 3103 wm_intermediate_val = latency * pixel_rate;
3104 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3105 plane_blocks_per_line;
2d41c0b5
PB		 3106
3107 return ret;
3108}
3109
2d41c0b5
PB		 3110static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3111 const struct intel_crtc *intel_crtc)
3112{
3113 struct drm_device *dev = intel_crtc->base.dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3116 enum pipe pipe = intel_crtc->pipe;
3117
3118 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3119 sizeof(new_ddb->plane[pipe])))
3120 return true;
3121
4969d33e
MR		 3122 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3123 sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
2d41c0b5
PB		 3124 return true;
3125
3126 return false;
3127}
3128
d4c2aa60 3129static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3a05f5e2
MR		 3130 struct intel_crtc_state *cstate,
3131 struct intel_plane *intel_plane,
afb024aa 3132 uint16_t ddb_allocation,
d4c2aa60 3133 int level,
afb024aa
DL		 3134 uint16_t *out_blocks, /* out */
3135 uint8_t *out_lines /* out */)
2d41c0b5 3136{
3a05f5e2
MR		 3137 struct drm_plane *plane = &intel_plane->base;
3138 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3139 uint32_t latency = dev_priv->wm.skl_latency[level];
3140 uint32_t method1, method2;
3141 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3142 uint32_t res_blocks, res_lines;
3143 uint32_t selected_result;
2cd601c6 3144 uint8_t bytes_per_pixel;
2d41c0b5 3145
3a05f5e2 3146 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3147 return false;
3148
3a05f5e2
MR		 3149 bytes_per_pixel = (fb->pixel_format == DRM_FORMAT_NV12) ?
3150 drm_format_plane_cpp(DRM_FORMAT_NV12, 0) :
3151 drm_format_plane_cpp(DRM_FORMAT_NV12, 1);
3152 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
2cd601c6 3153 bytes_per_pixel,
d4c2aa60 3154 latency);
3a05f5e2
MR		 3155 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3156 cstate->base.adjusted_mode.crtc_htotal,
3157 cstate->pipe_src_w,
2cd601c6 3158 bytes_per_pixel,
3a05f5e2 3159 fb->modifier[0],
d4c2aa60 3160 latency);
2d41c0b5 3161
3a05f5e2 3162 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
d4c2aa60 3163 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3164
3a05f5e2
MR		 3165 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3166 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3167 uint32_t min_scanlines = 4;
3168 uint32_t y_tile_minimum;
3a05f5e2
MR		 3169 if (intel_rotation_90_or_270(plane->state->rotation)) {
3170 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3171 drm_format_plane_cpp(fb->pixel_format, 1) :
3172 drm_format_plane_cpp(fb->pixel_format, 0);
3173
3174 switch (bpp) {
1fc0a8f7
TU		 3175 case 1:
3176 min_scanlines = 16;
3177 break;
3178 case 2:
3179 min_scanlines = 8;
3180 break;
3181 case 8:
3182 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3183 }
1fc0a8f7
TU		 3184 }
3185 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3186 selected_result = max(method2, y_tile_minimum);
3187 } else {
3188 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3189 selected_result = min(method1, method2);
3190 else
3191 selected_result = method1;
3192 }
2d41c0b5 3193
d4c2aa60
TU		 3194 res_blocks = selected_result + 1;
3195 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3196
0fda6568 3197 if (level >= 1 && level <= 7) {
3a05f5e2
MR		 3198 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3199 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3200 res_lines += 4;
3201 else
3202 res_blocks++;
3203 }
e6d66171 3204
d4c2aa60 3205 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3206 return false;
3207
3208 *out_blocks = res_blocks;
3209 *out_lines = res_lines;
2d41c0b5
PB		 3210
3211 return true;
3212}
3213
3214static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3215 struct skl_ddb_allocation *ddb,
3a05f5e2 3216 struct intel_crtc_state *cstate,
2d41c0b5 3217 int level,
2d41c0b5
PB		 3218 struct skl_wm_level *result)
3219{
3a05f5e2
MR		 3220 struct drm_device *dev = dev_priv->dev;
3221 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3222 struct intel_plane *intel_plane;
2d41c0b5 3223 uint16_t ddb_blocks;
3a05f5e2
MR		 3224 enum pipe pipe = intel_crtc->pipe;
3225
3226 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3227 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3228
2d41c0b5
PB		 3229 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3230
d4c2aa60 3231 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3a05f5e2
MR		 3232 cstate,
3233 intel_plane,
2d41c0b5 3234 ddb_blocks,
d4c2aa60 3235 level,
2d41c0b5
PB		 3236 &result->plane_res_b[i],
3237 &result->plane_res_l[i]);
3238 }
2d41c0b5
PB		 3239}
3240
407b50f3 3241static uint32_t
3a05f5e2 3242skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3243{
3a05f5e2 3244 if (!cstate->base.active)
407b50f3
DL		 3245 return 0;
3246
3a05f5e2 3247 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3248 return 0;
407b50f3 3249
3a05f5e2
MR		 3250 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3251 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3252}
3253
3a05f5e2 3254static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3255 struct skl_wm_level *trans_wm /* out */)
407b50f3 3256{
3a05f5e2 3257 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3a05f5e2 3259 struct intel_plane *intel_plane;
9414f563 3260
3a05f5e2 3261 if (!cstate->base.active)
407b50f3 3262 return;
9414f563
DL		 3263
3264 /* Until we know more, just disable transition WMs */
3a05f5e2
MR		 3265 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3266 int i = skl_wm_plane_id(intel_plane);
3267
9414f563 3268 trans_wm->plane_en[i] = false;
3a05f5e2 3269 }
407b50f3
DL		 3270}
3271
3a05f5e2 3272static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3273 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3274 struct skl_pipe_wm *pipe_wm)
3275{
3a05f5e2 3276 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3277 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3278 int level, max_level = ilk_wm_max_level(dev);
3279
3280 for (level = 0; level <= max_level; level++) {
3a05f5e2
MR		 3281 skl_compute_wm_level(dev_priv, ddb, cstate,
3282 level, &pipe_wm->wm[level]);
2d41c0b5 3283 }
3a05f5e2 3284 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3285
3a05f5e2 3286 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3287}
3288
3289static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3290 struct skl_pipe_wm *p_wm,
3291 struct skl_wm_values *r,
3292 struct intel_crtc *intel_crtc)
3293{
3294 int level, max_level = ilk_wm_max_level(dev);
3295 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3296 uint32_t temp;
3297 int i;
2d41c0b5
PB		 3298
3299 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3300 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3301 temp = 0;
2d41c0b5
PB		 3302
3303 temp |= p_wm->wm[level].plane_res_l[i] <<
3304 PLANE_WM_LINES_SHIFT;
3305 temp |= p_wm->wm[level].plane_res_b[i];
3306 if (p_wm->wm[level].plane_en[i])
3307 temp |= PLANE_WM_EN;
3308
3309 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3310 }
3311
3312 temp = 0;
2d41c0b5 3313
4969d33e
MR		 3314 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3315 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3316
4969d33e 3317 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3318 temp |= PLANE_WM_EN;
3319
4969d33e 3320 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3321
3322 }
3323
9414f563
DL		 3324 /* transition WMs */
3325 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3326 temp = 0;
3327 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3328 temp |= p_wm->trans_wm.plane_res_b[i];
3329 if (p_wm->trans_wm.plane_en[i])
3330 temp |= PLANE_WM_EN;
3331
3332 r->plane_trans[pipe][i] = temp;
3333 }
3334
3335 temp = 0;
4969d33e
MR		 3336 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3337 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3338 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3339 temp |= PLANE_WM_EN;
3340
4969d33e 3341 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3342
2d41c0b5
PB		 3343 r->wm_linetime[pipe] = p_wm->linetime;
3344}
3345
16160e3d
DL		 3346static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3347 const struct skl_ddb_entry *entry)
3348{
3349 if (entry->end)
3350 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3351 else
3352 I915_WRITE(reg, 0);
3353}
3354
2d41c0b5
PB		 3355static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3356 const struct skl_wm_values *new)
3357{
3358 struct drm_device *dev = dev_priv->dev;
3359 struct intel_crtc *crtc;
3360
3361 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3362 int i, level, max_level = ilk_wm_max_level(dev);
3363 enum pipe pipe = crtc->pipe;
3364
5d374d96
DL		 3365 if (!new->dirty[pipe])
3366 continue;
8211bd5b 3367
5d374d96 3368 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3369
5d374d96
DL		 3370 for (level = 0; level <= max_level; level++) {
3371 for (i = 0; i < intel_num_planes(crtc); i++)
3372 I915_WRITE(PLANE_WM(pipe, i, level),
3373 new->plane[pipe][i][level]);
3374 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3375 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3376 }
5d374d96
DL		 3377 for (i = 0; i < intel_num_planes(crtc); i++)
3378 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3379 new->plane_trans[pipe][i]);
4969d33e
MR		 3380 I915_WRITE(CUR_WM_TRANS(pipe),
3381 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3382
2cd601c6 3383 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3384 skl_ddb_entry_write(dev_priv,
3385 PLANE_BUF_CFG(pipe, i),
3386 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3387 skl_ddb_entry_write(dev_priv,
3388 PLANE_NV12_BUF_CFG(pipe, i),
3389 &new->ddb.y_plane[pipe][i]);
3390 }
5d374d96
DL		 3391
3392 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3393 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3394 }
2d41c0b5
PB		 3395}
3396
0e8fb7ba
DL		 3397/*
3398 * When setting up a new DDB allocation arrangement, we need to correctly
3399 * sequence the times at which the new allocations for the pipes are taken into
3400 * account or we'll have pipes fetching from space previously allocated to
3401 * another pipe.
3402 *
3403 * Roughly the sequence looks like:
3404 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3405 * overlapping with a previous light-up pipe (another way to put it is:
3406 * pipes with their new allocation strickly included into their old ones).
3407 * 2. re-allocate the other pipes that get their allocation reduced
3408 * 3. allocate the pipes having their allocation increased
3409 *
3410 * Steps 1. and 2. are here to take care of the following case:
3411 * - Initially DDB looks like this:
3412 * | B | C |
3413 * - enable pipe A.
3414 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3415 * allocation
3416 * | A | B | C |
3417 *
3418 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3419 */
3420
d21b795c
DL		 3421static void
3422skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3423{
0e8fb7ba
DL		 3424 int plane;
3425
d21b795c
DL		 3426 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3427
dd740780 3428 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3429 I915_WRITE(PLANE_SURF(pipe, plane),
3430 I915_READ(PLANE_SURF(pipe, plane)));
3431 }
3432 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3433}
3434
3435static bool
3436skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3437 const struct skl_ddb_allocation *new,
3438 enum pipe pipe)
3439{
3440 uint16_t old_size, new_size;
3441
3442 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3443 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3444
3445 return old_size != new_size &&
3446 new->pipe[pipe].start >= old->pipe[pipe].start &&
3447 new->pipe[pipe].end <= old->pipe[pipe].end;
3448}
3449
3450static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3451 struct skl_wm_values *new_values)
3452{
3453 struct drm_device *dev = dev_priv->dev;
3454 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3455 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3456 struct intel_crtc *crtc;
3457 enum pipe pipe;
3458
3459 new_ddb = &new_values->ddb;
3460 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3461
3462 /*
3463 * First pass: flush the pipes with the new allocation contained into
3464 * the old space.
3465 *
3466 * We'll wait for the vblank on those pipes to ensure we can safely
3467 * re-allocate the freed space without this pipe fetching from it.
3468 */
3469 for_each_intel_crtc(dev, crtc) {
3470 if (!crtc->active)
3471 continue;
3472
3473 pipe = crtc->pipe;
3474
3475 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3476 continue;
3477
d21b795c 3478 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3479 intel_wait_for_vblank(dev, pipe);
3480
3481 reallocated[pipe] = true;
3482 }
3483
3484
3485 /*
3486 * Second pass: flush the pipes that are having their allocation
3487 * reduced, but overlapping with a previous allocation.
3488 *
3489 * Here as well we need to wait for the vblank to make sure the freed
3490 * space is not used anymore.
3491 */
3492 for_each_intel_crtc(dev, crtc) {
3493 if (!crtc->active)
3494 continue;
3495
3496 pipe = crtc->pipe;
3497
3498 if (reallocated[pipe])
3499 continue;
3500
3501 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3502 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3503 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3504 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3505 reallocated[pipe] = true;
0e8fb7ba 3506 }
0e8fb7ba
DL		 3507 }
3508
3509 /*
3510 * Third pass: flush the pipes that got more space allocated.
3511 *
3512 * We don't need to actively wait for the update here, next vblank
3513 * will just get more DDB space with the correct WM values.
3514 */
3515 for_each_intel_crtc(dev, crtc) {
3516 if (!crtc->active)
3517 continue;
3518
3519 pipe = crtc->pipe;
3520
3521 /*
3522 * At this point, only the pipes more space than before are
3523 * left to re-allocate.
3524 */
3525 if (reallocated[pipe])
3526 continue;
3527
d21b795c 3528 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3529 }
3530}
3531
2d41c0b5 3532static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3533 struct skl_ddb_allocation *ddb, /* out */
3534 struct skl_pipe_wm *pipe_wm /* out */)
3535{
3536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3a05f5e2 3537 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3538
76305b1a 3539 skl_allocate_pipe_ddb(cstate, ddb);
3a05f5e2 3540 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3541
de4a9f83 3542 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3543 return false;
3544
de4a9f83 3545 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3546
2d41c0b5
PB		 3547 return true;
3548}
3549
3550static void skl_update_other_pipe_wm(struct drm_device *dev,
3551 struct drm_crtc *crtc,
2d41c0b5
PB		 3552 struct skl_wm_values *r)
3553{
3554 struct intel_crtc *intel_crtc;
3555 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3556
3557 /*
3558 * If the WM update hasn't changed the allocation for this_crtc (the
3559 * crtc we are currently computing the new WM values for), other
3560 * enabled crtcs will keep the same allocation and we don't need to
3561 * recompute anything for them.
3562 */
3563 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3564 return;
3565
3566 /*
3567 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3568 * other active pipes need new DDB allocation and WM values.
3569 */
3570 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3571 base.head) {
2d41c0b5
PB		 3572 struct skl_pipe_wm pipe_wm = {};
3573 bool wm_changed;
3574
3575 if (this_crtc->pipe == intel_crtc->pipe)
3576 continue;
3577
3578 if (!intel_crtc->active)
3579 continue;
3580
76305b1a 3581 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3582 &r->ddb, &pipe_wm);
3583
3584 /*
3585 * If we end up re-computing the other pipe WM values, it's
3586 * because it was really needed, so we expect the WM values to
3587 * be different.
3588 */
3589 WARN_ON(!wm_changed);
3590
3a05f5e2 3591 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3592 r->dirty[intel_crtc->pipe] = true;
3593 }
3594}
3595
adda50b8
BP		 3596static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3597{
3598 watermarks->wm_linetime[pipe] = 0;
3599 memset(watermarks->plane[pipe], 0,
3600 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3601 memset(watermarks->plane_trans[pipe],
3602 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3603 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3604
3605 /* Clear ddb entries for pipe */
3606 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3607 memset(&watermarks->ddb.plane[pipe], 0,
3608 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3609 memset(&watermarks->ddb.y_plane[pipe], 0,
3610 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3611 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3612 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3613
3614}
3615
2d41c0b5
PB		 3616static void skl_update_wm(struct drm_crtc *crtc)
3617{
3618 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3621 struct skl_wm_values *results = &dev_priv->wm.skl_results;
de4a9f83
MR		 3622 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3623 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3624
adda50b8
BP		 3625
3626 /* Clear all dirty flags */
3627 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3628
3629 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3630
76305b1a 3631 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3632 return;
3633
de4a9f83 3634 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3635 results->dirty[intel_crtc->pipe] = true;
3636
76305b1a 3637 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3638 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3639 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3640
3641 /* store the new configuration */
3642 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3643}
3644
de165e0b 3645static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3646{
de165e0b
VS		 3647 struct drm_device *dev = dev_priv->dev;
3648 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3649 struct ilk_wm_maximums max;
76305b1a 3650 struct intel_wm_config *config = &dev_priv->wm.config;
820c1980 3651 struct ilk_wm_values results = {};
77c122bc 3652 enum intel_ddb_partitioning partitioning;
861f3389 3653
76305b1a
MR		 3654 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3655 ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
a485bfb8
VS		 3656
3657 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3658 if (INTEL_INFO(dev)->gen >= 7 &&
76305b1a
MR		 3659 config->num_pipes_active == 1 && config->sprites_enabled) {
3660 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3661 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
0362c781 3662
820c1980 3663 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3664 } else {
198a1e9b 3665 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3666 }
3667
198a1e9b 3668 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3669 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3670
820c1980 3671 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3672
820c1980 3673 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3674}
3675
de165e0b
VS		 3676static void ilk_update_wm(struct drm_crtc *crtc)
3677{
3678 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3680 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
de165e0b
VS		 3681
3682 WARN_ON(cstate->base.active != intel_crtc->active);
3683
3684 /*
3685 * IVB workaround: must disable low power watermarks for at least
3686 * one frame before enabling scaling. LP watermarks can be re-enabled
3687 * when scaling is disabled.
3688 *
3689 * WaCxSRDisabledForSpriteScaling:ivb
3690 */
3691 if (cstate->disable_lp_wm) {
3692 ilk_disable_lp_wm(crtc->dev);
3693 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3694 }
3695
de4a9f83 3696 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
de165e0b
VS		 3697
3698 ilk_program_watermarks(dev_priv);
3699}
3700
3078999f
PB		 3701static void skl_pipe_wm_active_state(uint32_t val,
3702 struct skl_pipe_wm *active,
3703 bool is_transwm,
3704 bool is_cursor,
3705 int i,
3706 int level)
3707{
3708 bool is_enabled = (val & PLANE_WM_EN) != 0;
3709
3710 if (!is_transwm) {
3711 if (!is_cursor) {
3712 active->wm[level].plane_en[i] = is_enabled;
3713 active->wm[level].plane_res_b[i] =
3714 val & PLANE_WM_BLOCKS_MASK;
3715 active->wm[level].plane_res_l[i] =
3716 (val >> PLANE_WM_LINES_SHIFT) &
3717 PLANE_WM_LINES_MASK;
3718 } else {
4969d33e
MR		 3719 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3720 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3721 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3722 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3723 (val >> PLANE_WM_LINES_SHIFT) &
3724 PLANE_WM_LINES_MASK;
3725 }
3726 } else {
3727 if (!is_cursor) {
3728 active->trans_wm.plane_en[i] = is_enabled;
3729 active->trans_wm.plane_res_b[i] =
3730 val & PLANE_WM_BLOCKS_MASK;
3731 active->trans_wm.plane_res_l[i] =
3732 (val >> PLANE_WM_LINES_SHIFT) &
3733 PLANE_WM_LINES_MASK;
3734 } else {
4969d33e
MR		 3735 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3736 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3737 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3738 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3739 (val >> PLANE_WM_LINES_SHIFT) &
3740 PLANE_WM_LINES_MASK;
3741 }
3742 }
3743}
3744
3745static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3746{
3747 struct drm_device *dev = crtc->dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
de4a9f83
MR		 3751 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3752 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3753 enum pipe pipe = intel_crtc->pipe;
3754 int level, i, max_level;
3755 uint32_t temp;
3756
3757 max_level = ilk_wm_max_level(dev);
3758
3759 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3760
3761 for (level = 0; level <= max_level; level++) {
3762 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3763 hw->plane[pipe][i][level] =
3764 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3765 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3766 }
3767
3768 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3769 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3770 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3771
3ef00284 3772 if (!intel_crtc->active)
3078999f
PB		 3773 return;
3774
3775 hw->dirty[pipe] = true;
3776
3777 active->linetime = hw->wm_linetime[pipe];
3778
3779 for (level = 0; level <= max_level; level++) {
3780 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3781 temp = hw->plane[pipe][i][level];
3782 skl_pipe_wm_active_state(temp, active, false,
3783 false, i, level);
3784 }
4969d33e 3785 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3786 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3787 }
3788
3789 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3790 temp = hw->plane_trans[pipe][i];
3791 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3792 }
3793
4969d33e 3794 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3795 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
de4a9f83
MR		 3796
3797 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3798}
3799
3800void skl_wm_get_hw_state(struct drm_device *dev)
3801{
a269c583
DL		 3802 struct drm_i915_private *dev_priv = dev->dev_private;
3803 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3804 struct drm_crtc *crtc;
3805
a269c583 3806 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3807 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3808 skl_pipe_wm_get_hw_state(crtc);
3809}
3810
243e6a44
VS		 3811static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3812{
3813 struct drm_device *dev = crtc->dev;
3814 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3815 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
de4a9f83
MR		 3817 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3818 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44
VS		 3819 enum pipe pipe = intel_crtc->pipe;
3820 static const unsigned int wm0_pipe_reg[] = {
3821 [PIPE_A] = WM0_PIPEA_ILK,
3822 [PIPE_B] = WM0_PIPEB_ILK,
3823 [PIPE_C] = WM0_PIPEC_IVB,
3824 };
3825
3826 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3827 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3828 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3829
3ef00284 3830 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3831
3832 if (active->pipe_enabled) {
243e6a44
VS		 3833 u32 tmp = hw->wm_pipe[pipe];
3834
3835 /*
3836 * For active pipes LP0 watermark is marked as
3837 * enabled, and LP1+ watermaks as disabled since
3838 * we can't really reverse compute them in case
3839 * multiple pipes are active.
3840 */
3841 active->wm[0].enable = true;
3842 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3843 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3844 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3845 active->linetime = hw->wm_linetime[pipe];
3846 } else {
3847 int level, max_level = ilk_wm_max_level(dev);
3848
3849 /*
3850 * For inactive pipes, all watermark levels
3851 * should be marked as enabled but zeroed,
3852 * which is what we'd compute them to.
3853 */
3854 for (level = 0; level <= max_level; level++)
3855 active->wm[level].enable = true;
3856 }
de4a9f83
MR		 3857
3858 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3859}
3860
6eb1a681
VS		 3861#define _FW_WM(value, plane) \
3862 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3863#define _FW_WM_VLV(value, plane) \
3864 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3865
3866static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3867 struct vlv_wm_values *wm)
3868{
3869 enum pipe pipe;
3870 uint32_t tmp;
3871
3872 for_each_pipe(dev_priv, pipe) {
3873 tmp = I915_READ(VLV_DDL(pipe));
3874
3875 wm->ddl[pipe].primary =
3876 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3877 wm->ddl[pipe].cursor =
3878 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3879 wm->ddl[pipe].sprite[0] =
3880 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3881 wm->ddl[pipe].sprite[1] =
3882 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3883 }
3884
3885 tmp = I915_READ(DSPFW1);
3886 wm->sr.plane = _FW_WM(tmp, SR);
3887 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3888 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3889 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3890
3891 tmp = I915_READ(DSPFW2);
3892 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3893 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3894 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3895
3896 tmp = I915_READ(DSPFW3);
3897 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3898
3899 if (IS_CHERRYVIEW(dev_priv)) {
3900 tmp = I915_READ(DSPFW7_CHV);
3901 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3902 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3903
3904 tmp = I915_READ(DSPFW8_CHV);
3905 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3906 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3907
3908 tmp = I915_READ(DSPFW9_CHV);
3909 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3910 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3911
3912 tmp = I915_READ(DSPHOWM);
3913 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3914 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3915 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3916 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3917 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3918 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3919 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3920 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3921 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3922 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3923 } else {
3924 tmp = I915_READ(DSPFW7);
3925 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3926 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3927
3928 tmp = I915_READ(DSPHOWM);
3929 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3930 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3931 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3932 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3933 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3934 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3935 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3936 }
3937}
3938
3939#undef _FW_WM
3940#undef _FW_WM_VLV
3941
3942void vlv_wm_get_hw_state(struct drm_device *dev)
3943{
3944 struct drm_i915_private *dev_priv = to_i915(dev);
3945 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3946 struct intel_plane *plane;
3947 enum pipe pipe;
3948 u32 val;
3949
3950 vlv_read_wm_values(dev_priv, wm);
3951
3952 for_each_intel_plane(dev, plane) {
3953 switch (plane->base.type) {
3954 int sprite;
3955 case DRM_PLANE_TYPE_CURSOR:
3956 plane->wm.fifo_size = 63;
3957 break;
3958 case DRM_PLANE_TYPE_PRIMARY:
3959 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3960 break;
3961 case DRM_PLANE_TYPE_OVERLAY:
3962 sprite = plane->plane;
3963 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3964 break;
3965 }
3966 }
3967
3968 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3969 wm->level = VLV_WM_LEVEL_PM2;
3970
3971 if (IS_CHERRYVIEW(dev_priv)) {
3972 mutex_lock(&dev_priv->rps.hw_lock);
3973
3974 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3975 if (val & DSP_MAXFIFO_PM5_ENABLE)
3976 wm->level = VLV_WM_LEVEL_PM5;
3977
58590c14
VS		 3978 /*
3979 * If DDR DVFS is disabled in the BIOS, Punit
3980 * will never ack the request. So if that happens
3981 * assume we don't have to enable/disable DDR DVFS
3982 * dynamically. To test that just set the REQ_ACK
3983 * bit to poke the Punit, but don't change the
3984 * HIGH/LOW bits so that we don't actually change
3985 * the current state.
3986 */
6eb1a681 3987 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3988 val |= FORCE_DDR_FREQ_REQ_ACK;
3989 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3990
3991 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3992 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3993 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3994 "assuming DDR DVFS is disabled\n");
3995 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3996 } else {
3997 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3998 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3999 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4000 }
6eb1a681
VS		 4001
4002 mutex_unlock(&dev_priv->rps.hw_lock);
4003 }
4004
4005 for_each_pipe(dev_priv, pipe)
4006 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4007 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4008 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4009
4010 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4011 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4012}
4013
243e6a44
VS		 4014void ilk_wm_get_hw_state(struct drm_device *dev)
4015{
4016 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4017 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4018 struct drm_crtc *crtc;
4019
70e1e0ec 4020 for_each_crtc(dev, crtc)
243e6a44
VS		 4021 ilk_pipe_wm_get_hw_state(crtc);
4022
4023 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4024 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4025 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4026
4027 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4028 if (INTEL_INFO(dev)->gen >= 7) {
4029 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4030 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4031 }
243e6a44 4032
a42a5719 4033 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4034 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4035 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4036 else if (IS_IVYBRIDGE(dev))
4037 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4038 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4039
4040 hw->enable_fbc_wm =
4041 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4042}
4043
b445e3b0
ED		 4044/**
4045 * intel_update_watermarks - update FIFO watermark values based on current modes
4046 *
4047 * Calculate watermark values for the various WM regs based on current mode
4048 * and plane configuration.
4049 *
4050 * There are several cases to deal with here:
4051 * - normal (i.e. non-self-refresh)
4052 * - self-refresh (SR) mode
4053 * - lines are large relative to FIFO size (buffer can hold up to 2)
4054 * - lines are small relative to FIFO size (buffer can hold more than 2
4055 * lines), so need to account for TLB latency
4056 *
4057 * The normal calculation is:
4058 * watermark = dotclock * bytes per pixel * latency
4059 * where latency is platform & configuration dependent (we assume pessimal
4060 * values here).
4061 *
4062 * The SR calculation is:
4063 * watermark = (trunc(latency/line time)+1) * surface width *
4064 * bytes per pixel
4065 * where
4066 * line time = htotal / dotclock
4067 * surface width = hdisplay for normal plane and 64 for cursor
4068 * and latency is assumed to be high, as above.
4069 *
4070 * The final value programmed to the register should always be rounded up,
4071 * and include an extra 2 entries to account for clock crossings.
4072 *
4073 * We don't use the sprite, so we can ignore that. And on Crestline we have
4074 * to set the non-SR watermarks to 8.
4075 */
46ba614c 4076void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4077{
46ba614c 4078 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4079
4080 if (dev_priv->display.update_wm)
46ba614c 4081 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4082}
4083
9270388e
DV		 4084/**
4085 * Lock protecting IPS related data structures
9270388e
DV		 4086 */
4087DEFINE_SPINLOCK(mchdev_lock);
4088
4089/* Global for IPS driver to get at the current i915 device. Protected by
4090 * mchdev_lock. */
4091static struct drm_i915_private *i915_mch_dev;
4092
2b4e57bd
ED		 4093bool ironlake_set_drps(struct drm_device *dev, u8 val)
4094{
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096 u16 rgvswctl;
4097
9270388e
DV		 4098 assert_spin_locked(&mchdev_lock);
4099
2b4e57bd
ED		 4100 rgvswctl = I915_READ16(MEMSWCTL);
4101 if (rgvswctl & MEMCTL_CMD_STS) {
4102 DRM_DEBUG("gpu busy, RCS change rejected\n");
4103 return false; /* still busy with another command */
4104 }
4105
4106 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4107 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4108 I915_WRITE16(MEMSWCTL, rgvswctl);
4109 POSTING_READ16(MEMSWCTL);
4110
4111 rgvswctl |= MEMCTL_CMD_STS;
4112 I915_WRITE16(MEMSWCTL, rgvswctl);
4113
4114 return true;
4115}
4116
8090c6b9 4117static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4118{
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 u32 rgvmodectl = I915_READ(MEMMODECTL);
4121 u8 fmax, fmin, fstart, vstart;
4122
9270388e
DV		 4123 spin_lock_irq(&mchdev_lock);
4124
2b4e57bd
ED		 4125 /* Enable temp reporting */
4126 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4127 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4128
4129 /* 100ms RC evaluation intervals */
4130 I915_WRITE(RCUPEI, 100000);
4131 I915_WRITE(RCDNEI, 100000);
4132
4133 /* Set max/min thresholds to 90ms and 80ms respectively */
4134 I915_WRITE(RCBMAXAVG, 90000);
4135 I915_WRITE(RCBMINAVG, 80000);
4136
4137 I915_WRITE(MEMIHYST, 1);
4138
4139 /* Set up min, max, and cur for interrupt handling */
4140 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4141 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4142 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4143 MEMMODE_FSTART_SHIFT;
4144
616847e7 4145 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4146 PXVFREQ_PX_SHIFT;
4147
20e4d407
DV		 4148 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4149 dev_priv->ips.fstart = fstart;
2b4e57bd 4150
20e4d407
DV		 4151 dev_priv->ips.max_delay = fstart;
4152 dev_priv->ips.min_delay = fmin;
4153 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4154
4155 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4156 fmax, fmin, fstart);
4157
4158 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4159
4160 /*
4161 * Interrupts will be enabled in ironlake_irq_postinstall
4162 */
4163
4164 I915_WRITE(VIDSTART, vstart);
4165 POSTING_READ(VIDSTART);
4166
4167 rgvmodectl |= MEMMODE_SWMODE_EN;
4168 I915_WRITE(MEMMODECTL, rgvmodectl);
4169
9270388e 4170 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4171 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4172 mdelay(1);
2b4e57bd
ED		 4173
4174 ironlake_set_drps(dev, fstart);
4175
7d81c3e0
VS		 4176 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4177 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4178 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4179 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4180 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4181
4182 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4183}
4184
8090c6b9 4185static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4186{
4187 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4188 u16 rgvswctl;
4189
4190 spin_lock_irq(&mchdev_lock);
4191
4192 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4193
4194 /* Ack interrupts, disable EFC interrupt */
4195 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4196 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4197 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4198 I915_WRITE(DEIIR, DE_PCU_EVENT);
4199 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4200
4201 /* Go back to the starting frequency */
20e4d407 4202 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4203 mdelay(1);
2b4e57bd
ED		 4204 rgvswctl |= MEMCTL_CMD_STS;
4205 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4206 mdelay(1);
2b4e57bd 4207
9270388e 4208 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4209}
4210
acbe9475
DV		 4211/* There's a funny hw issue where the hw returns all 0 when reading from
4212 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4213 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4214 * all limits and the gpu stuck at whatever frequency it is at atm).
4215 */
74ef1173 4216static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4217{
7b9e0ae6 4218 u32 limits;
2b4e57bd 4219
20b46e59
DV		 4220 /* Only set the down limit when we've reached the lowest level to avoid
4221 * getting more interrupts, otherwise leave this clear. This prevents a
4222 * race in the hw when coming out of rc6: There's a tiny window where
4223 * the hw runs at the minimal clock before selecting the desired
4224 * frequency, if the down threshold expires in that window we will not
4225 * receive a down interrupt. */
74ef1173
AG		 4226 if (IS_GEN9(dev_priv->dev)) {
4227 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4228 if (val <= dev_priv->rps.min_freq_softlimit)
4229 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4230 } else {
4231 limits = dev_priv->rps.max_freq_softlimit << 24;
4232 if (val <= dev_priv->rps.min_freq_softlimit)
4233 limits |= dev_priv->rps.min_freq_softlimit << 16;
4234 }
20b46e59
DV		 4235
4236 return limits;
4237}
4238
dd75fdc8
CW		 4239static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4240{
4241 int new_power;
8a586437
AG		 4242 u32 threshold_up = 0, threshold_down = 0; /* in % */
4243 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4244
4245 new_power = dev_priv->rps.power;
4246 switch (dev_priv->rps.power) {
4247 case LOW_POWER:
b39fb297 4248 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4249 new_power = BETWEEN;
4250 break;
4251
4252 case BETWEEN:
b39fb297 4253 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4254 new_power = LOW_POWER;
b39fb297 4255 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4256 new_power = HIGH_POWER;
4257 break;
4258
4259 case HIGH_POWER:
b39fb297 4260 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4261 new_power = BETWEEN;
4262 break;
4263 }
4264 /* Max/min bins are special */
aed242ff 4265 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4266 new_power = LOW_POWER;
aed242ff 4267 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4268 new_power = HIGH_POWER;
4269 if (new_power == dev_priv->rps.power)
4270 return;
4271
4272 /* Note the units here are not exactly 1us, but 1280ns. */
4273 switch (new_power) {
4274 case LOW_POWER:
4275 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4276 ei_up = 16000;
4277 threshold_up = 95;
dd75fdc8
CW		 4278
4279 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4280 ei_down = 32000;
4281 threshold_down = 85;
dd75fdc8
CW		 4282 break;
4283
4284 case BETWEEN:
4285 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4286 ei_up = 13000;
4287 threshold_up = 90;
dd75fdc8
CW		 4288
4289 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4290 ei_down = 32000;
4291 threshold_down = 75;
dd75fdc8
CW		 4292 break;
4293
4294 case HIGH_POWER:
4295 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4296 ei_up = 10000;
4297 threshold_up = 85;
dd75fdc8
CW		 4298
4299 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4300 ei_down = 32000;
4301 threshold_down = 60;
dd75fdc8
CW		 4302 break;
4303 }
4304
8a586437
AG		 4305 I915_WRITE(GEN6_RP_UP_EI,
4306 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4307 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4308 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4309
4310 I915_WRITE(GEN6_RP_DOWN_EI,
4311 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4312 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4313 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4314
4315 I915_WRITE(GEN6_RP_CONTROL,
4316 GEN6_RP_MEDIA_TURBO |
4317 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4318 GEN6_RP_MEDIA_IS_GFX |
4319 GEN6_RP_ENABLE |
4320 GEN6_RP_UP_BUSY_AVG |
4321 GEN6_RP_DOWN_IDLE_AVG);
4322
dd75fdc8 4323 dev_priv->rps.power = new_power;
8fb55197
CW		 4324 dev_priv->rps.up_threshold = threshold_up;
4325 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4326 dev_priv->rps.last_adj = 0;
4327}
4328
2876ce73
CW		 4329static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4330{
4331 u32 mask = 0;
4332
4333 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4334 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4335 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4336 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4337
7b3c29f6
CW		 4338 mask &= dev_priv->pm_rps_events;
4339
59d02a1f 4340 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4341}
4342
b8a5ff8d
JM		 4343/* gen6_set_rps is called to update the frequency request, but should also be
4344 * called when the range (min_delay and max_delay) is modified so that we can
4345 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4346static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4347{
4348 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4349
23eafea6
SAK		 4350 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4351 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4352 return;
4353
4fc688ce 4354 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4355 WARN_ON(val > dev_priv->rps.max_freq);
4356 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4357
eb64cad1
CW		 4358 /* min/max delay may still have been modified so be sure to
4359 * write the limits value.
4360 */
4361 if (val != dev_priv->rps.cur_freq) {
4362 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4363
5704195c
AG		 4364 if (IS_GEN9(dev))
4365 I915_WRITE(GEN6_RPNSWREQ,
4366 GEN9_FREQUENCY(val));
4367 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4368 I915_WRITE(GEN6_RPNSWREQ,
4369 HSW_FREQUENCY(val));
4370 else
4371 I915_WRITE(GEN6_RPNSWREQ,
4372 GEN6_FREQUENCY(val) |
4373 GEN6_OFFSET(0) |
4374 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4375 }
7b9e0ae6 4376
7b9e0ae6
CW		 4377 /* Make sure we continue to get interrupts
4378 * until we hit the minimum or maximum frequencies.
4379 */
74ef1173 4380 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4381 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4382
d5570a72
BW		 4383 POSTING_READ(GEN6_RPNSWREQ);
4384
b39fb297 4385 dev_priv->rps.cur_freq = val;
be2cde9a 4386 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4387}
4388
ffe02b40
VS		 4389static void valleyview_set_rps(struct drm_device *dev, u8 val)
4390{
4391 struct drm_i915_private *dev_priv = dev->dev_private;
4392
4393 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4394 WARN_ON(val > dev_priv->rps.max_freq);
4395 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4396
4397 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4398 "Odd GPU freq value\n"))
4399 val &= ~1;
4400
cd25dd5b
D		 4401 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4402
8fb55197 4403 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4404 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4405 if (!IS_CHERRYVIEW(dev_priv))
4406 gen6_set_rps_thresholds(dev_priv, val);
4407 }
ffe02b40 4408
ffe02b40
VS		 4409 dev_priv->rps.cur_freq = val;
4410 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4411}
4412
a7f6e231 4413/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4414 *
4415 * * If Gfx is Idle, then
a7f6e231
D		 4416 * 1. Forcewake Media well.
4417 * 2. Request idle freq.
4418 * 3. Release Forcewake of Media well.
76c3552f
D		 4419*/
4420static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4421{
aed242ff 4422 u32 val = dev_priv->rps.idle_freq;
5549d25f 4423
aed242ff 4424 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4425 return;
4426
a7f6e231
D		 4427 /* Wake up the media well, as that takes a lot less
4428 * power than the Render well. */
4429 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4430 valleyview_set_rps(dev_priv->dev, val);
4431 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4432}
4433
43cf3bf0
CW		 4434void gen6_rps_busy(struct drm_i915_private *dev_priv)
4435{
4436 mutex_lock(&dev_priv->rps.hw_lock);
4437 if (dev_priv->rps.enabled) {
4438 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4439 gen6_rps_reset_ei(dev_priv);
4440 I915_WRITE(GEN6_PMINTRMSK,
4441 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4442 }
4443 mutex_unlock(&dev_priv->rps.hw_lock);
4444}
4445
b29c19b6
CW		 4446void gen6_rps_idle(struct drm_i915_private *dev_priv)
4447{
691bb717
DL		 4448 struct drm_device *dev = dev_priv->dev;
4449
b29c19b6 4450 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4451 if (dev_priv->rps.enabled) {
21a11fff 4452 if (IS_VALLEYVIEW(dev))
76c3552f 4453 vlv_set_rps_idle(dev_priv);
7526ed79 4454 else
aed242ff 4455 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4456 dev_priv->rps.last_adj = 0;
43cf3bf0 4457 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4458 }
8d3afd7d 4459 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4460
8d3afd7d 4461 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4462 while (!list_empty(&dev_priv->rps.clients))
4463 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4464 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4465}
4466
1854d5ca 4467void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4468 struct intel_rps_client *rps,
4469 unsigned long submitted)
b29c19b6 4470{
8d3afd7d
CW		 4471 /* This is intentionally racy! We peek at the state here, then
4472 * validate inside the RPS worker.
4473 */
4474 if (!(dev_priv->mm.busy &&
4475 dev_priv->rps.enabled &&
4476 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4477 return;
43cf3bf0 4478
e61b9958
CW		 4479 /* Force a RPS boost (and don't count it against the client) if
4480 * the GPU is severely congested.
4481 */
d0bc54f2 4482 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4483 rps = NULL;
4484
8d3afd7d
CW		 4485 spin_lock(&dev_priv->rps.client_lock);
4486 if (rps == NULL || list_empty(&rps->link)) {
4487 spin_lock_irq(&dev_priv->irq_lock);
4488 if (dev_priv->rps.interrupts_enabled) {
4489 dev_priv->rps.client_boost = true;
4490 queue_work(dev_priv->wq, &dev_priv->rps.work);
4491 }
4492 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4493
2e1b8730
CW		 4494 if (rps != NULL) {
4495 list_add(&rps->link, &dev_priv->rps.clients);
4496 rps->boosts++;
1854d5ca
CW		 4497 } else
4498 dev_priv->rps.boosts++;
c0951f0c 4499 }
8d3afd7d 4500 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4501}
4502
ffe02b40 4503void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4504{
ffe02b40
VS		 4505 if (IS_VALLEYVIEW(dev))
4506 valleyview_set_rps(dev, val);
4507 else
4508 gen6_set_rps(dev, val);
0a073b84
JB		 4509}
4510
20e49366
ZW		 4511static void gen9_disable_rps(struct drm_device *dev)
4512{
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514
4515 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4516 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4517}
4518
44fc7d5c 4519static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4520{
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522
4523 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4524 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4525}
4526
38807746
D		 4527static void cherryview_disable_rps(struct drm_device *dev)
4528{
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530
4531 I915_WRITE(GEN6_RC_CONTROL, 0);
4532}
4533
44fc7d5c
DV		 4534static void valleyview_disable_rps(struct drm_device *dev)
4535{
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537
98a2e5f9
D		 4538 /* we're doing forcewake before Disabling RC6,
4539 * This what the BIOS expects when going into suspend */
59bad947 4540 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4541
44fc7d5c 4542 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4543
59bad947 4544 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4545}
4546
dc39fff7
BW		 4547static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4548{
91ca689a
ID		 4549 if (IS_VALLEYVIEW(dev)) {
4550 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4551 mode = GEN6_RC_CTL_RC6_ENABLE;
4552 else
4553 mode = 0;
4554 }
58abf1da
RV		 4555 if (HAS_RC6p(dev))
4556 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4557 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4558 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4559 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4560
4561 else
4562 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4563 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4564}
4565
e6069ca8 4566static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4567{
e7d66d89
DV		 4568 /* No RC6 before Ironlake and code is gone for ilk. */
4569 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4570 return 0;
4571
456470eb 4572 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4573 if (enable_rc6 >= 0) {
4574 int mask;
4575
58abf1da 4576 if (HAS_RC6p(dev))
e6069ca8
ID		 4577 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4578 INTEL_RC6pp_ENABLE;
4579 else
4580 mask = INTEL_RC6_ENABLE;
4581
4582 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4583 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4584 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4585
4586 return enable_rc6 & mask;
4587 }
2b4e57bd 4588
8bade1ad 4589 if (IS_IVYBRIDGE(dev))
cca84a1f 4590 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4591
4592 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4593}
4594
e6069ca8
ID		 4595int intel_enable_rc6(const struct drm_device *dev)
4596{
4597 return i915.enable_rc6;
4598}
4599
93ee2920 4600static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4601{
93ee2920
TR		 4602 struct drm_i915_private *dev_priv = dev->dev_private;
4603 uint32_t rp_state_cap;
4604 u32 ddcc_status = 0;
4605 int ret;
4606
3280e8b0
BW		 4607 /* All of these values are in units of 50MHz */
4608 dev_priv->rps.cur_freq = 0;
93ee2920 4609 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4610 if (IS_BROXTON(dev)) {
4611 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4612 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4613 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4614 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4615 } else {
4616 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4617 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4618 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4619 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4620 }
4621
3280e8b0
BW		 4622 /* hw_max = RP0 until we check for overclocking */
4623 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4624
93ee2920 4625 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4626 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4627 ret = sandybridge_pcode_read(dev_priv,
4628 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4629 &ddcc_status);
4630 if (0 == ret)
4631 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4632 clamp_t(u8,
4633 ((ddcc_status >> 8) & 0xff),
4634 dev_priv->rps.min_freq,
4635 dev_priv->rps.max_freq);
93ee2920
TR		 4636 }
4637
c5e0688c
AG		 4638 if (IS_SKYLAKE(dev)) {
4639 /* Store the frequency values in 16.66 MHZ units, which is
4640 the natural hardware unit for SKL */
4641 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4642 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4643 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4644 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4645 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4646 }
4647
aed242ff
CW		 4648 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4649
3280e8b0
BW		 4650 /* Preserve min/max settings in case of re-init */
4651 if (dev_priv->rps.max_freq_softlimit == 0)
4652 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4653
93ee2920
TR		 4654 if (dev_priv->rps.min_freq_softlimit == 0) {
4655 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4656 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4657 max_t(int, dev_priv->rps.efficient_freq,
4658 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4659 else
4660 dev_priv->rps.min_freq_softlimit =
4661 dev_priv->rps.min_freq;
4662 }
3280e8b0
BW		 4663}
4664
b6fef0ef 4665/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4666static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4667{
4668 struct drm_i915_private *dev_priv = dev->dev_private;
4669
4670 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4671
ba1c554c
DL		 4672 gen6_init_rps_frequencies(dev);
4673
23eafea6
SAK		 4674 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4675 if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4676 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4677 return;
4678 }
4679
0beb059a
AG		 4680 /* Program defaults and thresholds for RPS*/
4681 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4682 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4683
4684 /* 1 second timeout*/
4685 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4686 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4687
b6fef0ef 4688 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4689
0beb059a
AG		 4690 /* Leaning on the below call to gen6_set_rps to program/setup the
4691 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4692 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4693 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4694 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4695
4696 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4697}
4698
4699static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4700{
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 struct intel_engine_cs *ring;
4703 uint32_t rc6_mask = 0;
4704 int unused;
4705
4706 /* 1a: Software RC state - RC0 */
4707 I915_WRITE(GEN6_RC_STATE, 0);
4708
4709 /* 1b: Get forcewake during program sequence. Although the driver
4710 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4711 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4712
4713 /* 2a: Disable RC states. */
4714 I915_WRITE(GEN6_RC_CONTROL, 0);
4715
4716 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4717
4718 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4719 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4720 (INTEL_REVID(dev) <= SKL_REVID_E0)))
4721 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4722 else
4723 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4724 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4725 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4726 for_each_ring(ring, dev_priv, unused)
4727 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4728
4729 if (HAS_GUC_UCODE(dev))
4730 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4731
20e49366
ZW		 4732 I915_WRITE(GEN6_RC_SLEEP, 0);
4733 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4734
38c23527
ZW		 4735 /* 2c: Program Coarse Power Gating Policies. */
4736 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4737 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4738
20e49366
ZW		 4739 /* 3a: Enable RC6 */
4740 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4741 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4742 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4743 "on" : "off");
e3429cd2
SAK		 4744
4745 if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4746 (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0))
4747 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4748 GEN7_RC_CTL_TO_MODE |
4749 rc6_mask);
4750 else
4751 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4752 GEN6_RC_CTL_EI_MODE(1) |
4753 rc6_mask);
20e49366 4754
cb07bae0
SK		 4755 /*
4756 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4757 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4758 */
f2d2fe95
SAK		 4759 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4760 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
4761 I915_WRITE(GEN9_PG_ENABLE, 0);
4762 else
4763 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4764 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4765
59bad947 4766 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4767
4768}
4769
6edee7f3
BW		 4770static void gen8_enable_rps(struct drm_device *dev)
4771{
4772 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4773 struct intel_engine_cs *ring;
93ee2920 4774 uint32_t rc6_mask = 0;
6edee7f3
BW		 4775 int unused;
4776
4777 /* 1a: Software RC state - RC0 */
4778 I915_WRITE(GEN6_RC_STATE, 0);
4779
4780 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4781 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4782 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4783
4784 /* 2a: Disable RC states. */
4785 I915_WRITE(GEN6_RC_CONTROL, 0);
4786
93ee2920
TR		 4787 /* Initialize rps frequencies */
4788 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4789
4790 /* 2b: Program RC6 thresholds.*/
4791 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4792 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4793 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4794 for_each_ring(ring, dev_priv, unused)
4795 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4796 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4797 if (IS_BROADWELL(dev))
4798 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4799 else
4800 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4801
4802 /* 3: Enable RC6 */
4803 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4804 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4805 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4806 if (IS_BROADWELL(dev))
4807 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4808 GEN7_RC_CTL_TO_MODE |
4809 rc6_mask);
4810 else
4811 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4812 GEN6_RC_CTL_EI_MODE(1) |
4813 rc6_mask);
6edee7f3
BW		 4814
4815 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4816 I915_WRITE(GEN6_RPNSWREQ,
4817 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4818 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4819 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4820 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4821 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4822
4823 /* Docs recommend 900MHz, and 300 MHz respectively */
4824 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4825 dev_priv->rps.max_freq_softlimit << 24 |
4826 dev_priv->rps.min_freq_softlimit << 16);
4827
4828 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4829 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4830 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4831 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4832
4833 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4834
4835 /* 5: Enable RPS */
7526ed79
DV		 4836 I915_WRITE(GEN6_RP_CONTROL,
4837 GEN6_RP_MEDIA_TURBO |
4838 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4839 GEN6_RP_MEDIA_IS_GFX |
4840 GEN6_RP_ENABLE |
4841 GEN6_RP_UP_BUSY_AVG |
4842 GEN6_RP_DOWN_IDLE_AVG);
4843
4844 /* 6: Ring frequency + overclocking (our driver does this later */
4845
c7f3153a 4846 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4847 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4848
59bad947 4849 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4850}
4851
79f5b2c7 4852static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4853{
79f5b2c7 4854 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4855 struct intel_engine_cs *ring;
d060c169 4856 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4857 u32 gtfifodbg;
2b4e57bd 4858 int rc6_mode;
42c0526c 4859 int i, ret;
2b4e57bd 4860
4fc688ce 4861 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4862
2b4e57bd
ED		 4863 /* Here begins a magic sequence of register writes to enable
4864 * auto-downclocking.
4865 *
4866 * Perhaps there might be some value in exposing these to
4867 * userspace...
4868 */
4869 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4870
4871 /* Clear the DBG now so we don't confuse earlier errors */
4872 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4873 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4874 I915_WRITE(GTFIFODBG, gtfifodbg);
4875 }
4876
59bad947 4877 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4878
93ee2920
TR		 4879 /* Initialize rps frequencies */
4880 gen6_init_rps_frequencies(dev);
dd0a1aa1 4881
2b4e57bd
ED		 4882 /* disable the counters and set deterministic thresholds */
4883 I915_WRITE(GEN6_RC_CONTROL, 0);
4884
4885 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4886 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4887 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4888 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4889 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4890
b4519513
CW		 4891 for_each_ring(ring, dev_priv, i)
4892 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4893
4894 I915_WRITE(GEN6_RC_SLEEP, 0);
4895 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4896 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4897 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4898 else
4899 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4900 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4901 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4902
5a7dc92a 4903 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4904 rc6_mode = intel_enable_rc6(dev_priv->dev);
4905 if (rc6_mode & INTEL_RC6_ENABLE)
4906 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4907
5a7dc92a
ED		 4908 /* We don't use those on Haswell */
4909 if (!IS_HASWELL(dev)) {
4910 if (rc6_mode & INTEL_RC6p_ENABLE)
4911 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4912
5a7dc92a
ED		 4913 if (rc6_mode & INTEL_RC6pp_ENABLE)
4914 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4915 }
2b4e57bd 4916
dc39fff7 4917 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4918
4919 I915_WRITE(GEN6_RC_CONTROL,
4920 rc6_mask |
4921 GEN6_RC_CTL_EI_MODE(1) |
4922 GEN6_RC_CTL_HW_ENABLE);
4923
dd75fdc8
CW		 4924 /* Power down if completely idle for over 50ms */
4925 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4926 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4927
42c0526c 4928 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4929 if (ret)
42c0526c 4930 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4931
4932 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4933 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4934 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4935 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4936 (pcu_mbox & 0xff) * 50);
b39fb297 4937 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4938 }
4939
dd75fdc8 4940 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4941 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4942
31643d54
BW		 4943 rc6vids = 0;
4944 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4945 if (IS_GEN6(dev) && ret) {
4946 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4947 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4948 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4949 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4950 rc6vids &= 0xffff00;
4951 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4952 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4953 if (ret)
4954 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4955 }
4956
59bad947 4957 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4958}
4959
c2bc2fc5 4960static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4961{
79f5b2c7 4962 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4963 int min_freq = 15;
3ebecd07
CW		 4964 unsigned int gpu_freq;
4965 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 4966 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 4967 int scaling_factor = 180;
eda79642 4968 struct cpufreq_policy *policy;
2b4e57bd 4969
4fc688ce 4970 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4971
eda79642
BW		 4972 policy = cpufreq_cpu_get(0);
4973 if (policy) {
4974 max_ia_freq = policy->cpuinfo.max_freq;
4975 cpufreq_cpu_put(policy);
4976 } else {
4977 /*
4978 * Default to measured freq if none found, PCU will ensure we
4979 * don't go over
4980 */
2b4e57bd 4981 max_ia_freq = tsc_khz;
eda79642 4982 }
2b4e57bd
ED		 4983
4984 /* Convert from kHz to MHz */
4985 max_ia_freq /= 1000;
4986
153b4b95 4987 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4988 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4989 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4990
4c8c7743
AG		 4991 if (IS_SKYLAKE(dev)) {
4992 /* Convert GT frequency to 50 HZ units */
4993 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4994 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4995 } else {
4996 min_gpu_freq = dev_priv->rps.min_freq;
4997 max_gpu_freq = dev_priv->rps.max_freq;
4998 }
4999
2b4e57bd
ED		 5000 /*
5001 * For each potential GPU frequency, load a ring frequency we'd like
5002 * to use for memory access. We do this by specifying the IA frequency
5003 * the PCU should use as a reference to determine the ring frequency.
5004 */
4c8c7743
AG		 5005 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5006 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5007 unsigned int ia_freq = 0, ring_freq = 0;
5008
4c8c7743
AG		 5009 if (IS_SKYLAKE(dev)) {
5010 /*
5011 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5012 * No floor required for ring frequency on SKL.
5013 */
5014 ring_freq = gpu_freq;
5015 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5016 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5017 ring_freq = max(min_ring_freq, gpu_freq);
5018 } else if (IS_HASWELL(dev)) {
f6aca45c 5019 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5020 ring_freq = max(min_ring_freq, ring_freq);
5021 /* leave ia_freq as the default, chosen by cpufreq */
5022 } else {
5023 /* On older processors, there is no separate ring
5024 * clock domain, so in order to boost the bandwidth
5025 * of the ring, we need to upclock the CPU (ia_freq).
5026 *
5027 * For GPU frequencies less than 750MHz,
5028 * just use the lowest ring freq.
5029 */
5030 if (gpu_freq < min_freq)
5031 ia_freq = 800;
5032 else
5033 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5034 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5035 }
2b4e57bd 5036
42c0526c
BW		 5037 sandybridge_pcode_write(dev_priv,
5038 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5039 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5040 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5041 gpu_freq);
2b4e57bd 5042 }
2b4e57bd
ED		 5043}
5044
c2bc2fc5
ID		 5045void gen6_update_ring_freq(struct drm_device *dev)
5046{
5047 struct drm_i915_private *dev_priv = dev->dev_private;
5048
97d3308a 5049 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5050 return;
5051
5052 mutex_lock(&dev_priv->rps.hw_lock);
5053 __gen6_update_ring_freq(dev);
5054 mutex_unlock(&dev_priv->rps.hw_lock);
5055}
5056
03af2045 5057static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5058{
095acd5f 5059 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5060 u32 val, rp0;
5061
095acd5f
D		 5062 if (dev->pdev->revision >= 0x20) {
5063 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5064
095acd5f
D		 5065 switch (INTEL_INFO(dev)->eu_total) {
5066 case 8:
5067 /* (2 * 4) config */
5068 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5069 break;
5070 case 12:
5071 /* (2 * 6) config */
5072 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5073 break;
5074 case 16:
5075 /* (2 * 8) config */
5076 default:
5077 /* Setting (2 * 8) Min RP0 for any other combination */
5078 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5079 break;
5080 }
5081 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5082 } else {
5083 /* For pre-production hardware */
5084 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5085 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5086 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5087 }
2b6b3a09
D		 5088 return rp0;
5089}
5090
5091static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5092{
5093 u32 val, rpe;
5094
5095 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5096 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5097
5098 return rpe;
5099}
5100
7707df4a
D		 5101static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5102{
095acd5f 5103 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5104 u32 val, rp1;
5105
095acd5f
D		 5106 if (dev->pdev->revision >= 0x20) {
5107 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5108 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5109 } else {
5110 /* For pre-production hardware */
5111 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5112 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5113 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5114 }
7707df4a
D		 5115 return rp1;
5116}
5117
f8f2b001
D		 5118static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5119{
5120 u32 val, rp1;
5121
5122 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5123
5124 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5125
5126 return rp1;
5127}
5128
03af2045 5129static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5130{
5131 u32 val, rp0;
5132
64936258 5133 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5134
5135 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5136 /* Clamp to max */
5137 rp0 = min_t(u32, rp0, 0xea);
5138
5139 return rp0;
5140}
5141
5142static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5143{
5144 u32 val, rpe;
5145
64936258 5146 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5147 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5148 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5149 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5150
5151 return rpe;
5152}
5153
03af2045 5154static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5155{
64936258 5156 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5157}
5158
ae48434c
ID		 5159/* Check that the pctx buffer wasn't move under us. */
5160static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5161{
5162 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5163
5164 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5165 dev_priv->vlv_pctx->stolen->start);
5166}
5167
38807746
D		 5168
5169/* Check that the pcbr address is not empty. */
5170static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5171{
5172 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5173
5174 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5175}
5176
5177static void cherryview_setup_pctx(struct drm_device *dev)
5178{
5179 struct drm_i915_private *dev_priv = dev->dev_private;
5180 unsigned long pctx_paddr, paddr;
5181 struct i915_gtt *gtt = &dev_priv->gtt;
5182 u32 pcbr;
5183 int pctx_size = 32*1024;
5184
5185 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5186
5187 pcbr = I915_READ(VLV_PCBR);
5188 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5189 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5190 paddr = (dev_priv->mm.stolen_base +
5191 (gtt->stolen_size - pctx_size));
5192
5193 pctx_paddr = (paddr & (~4095));
5194 I915_WRITE(VLV_PCBR, pctx_paddr);
5195 }
ce611ef8
VS		 5196
5197 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5198}
5199
c9cddffc
JB		 5200static void valleyview_setup_pctx(struct drm_device *dev)
5201{
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct drm_i915_gem_object *pctx;
5204 unsigned long pctx_paddr;
5205 u32 pcbr;
5206 int pctx_size = 24*1024;
5207
17b0c1f7
ID		 5208 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5209
c9cddffc
JB		 5210 pcbr = I915_READ(VLV_PCBR);
5211 if (pcbr) {
5212 /* BIOS set it up already, grab the pre-alloc'd space */
5213 int pcbr_offset;
5214
5215 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5216 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5217 pcbr_offset,
190d6cd5 5218 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5219 pctx_size);
5220 goto out;
5221 }
5222
ce611ef8
VS		 5223 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5224
c9cddffc
JB		 5225 /*
5226 * From the Gunit register HAS:
5227 * The Gfx driver is expected to program this register and ensure
5228 * proper allocation within Gfx stolen memory. For example, this
5229 * register should be programmed such than the PCBR range does not
5230 * overlap with other ranges, such as the frame buffer, protected
5231 * memory, or any other relevant ranges.
5232 */
5233 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5234 if (!pctx) {
5235 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5236 return;
5237 }
5238
5239 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5240 I915_WRITE(VLV_PCBR, pctx_paddr);
5241
5242out:
ce611ef8 5243 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5244 dev_priv->vlv_pctx = pctx;
5245}
5246
ae48434c
ID		 5247static void valleyview_cleanup_pctx(struct drm_device *dev)
5248{
5249 struct drm_i915_private *dev_priv = dev->dev_private;
5250
5251 if (WARN_ON(!dev_priv->vlv_pctx))
5252 return;
5253
5254 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5255 dev_priv->vlv_pctx = NULL;
5256}
5257
4e80519e
ID		 5258static void valleyview_init_gt_powersave(struct drm_device *dev)
5259{
5260 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5261 u32 val;
4e80519e
ID		 5262
5263 valleyview_setup_pctx(dev);
5264
5265 mutex_lock(&dev_priv->rps.hw_lock);
5266
2bb25c17
VS		 5267 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5268 switch ((val >> 6) & 3) {
5269 case 0:
5270 case 1:
5271 dev_priv->mem_freq = 800;
5272 break;
5273 case 2:
5274 dev_priv->mem_freq = 1066;
5275 break;
5276 case 3:
5277 dev_priv->mem_freq = 1333;
5278 break;
5279 }
80b83b62 5280 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5281
4e80519e
ID		 5282 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5283 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5284 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5285 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5286 dev_priv->rps.max_freq);
5287
5288 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5289 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5290 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5291 dev_priv->rps.efficient_freq);
5292
f8f2b001
D		 5293 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5294 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5295 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5296 dev_priv->rps.rp1_freq);
5297
4e80519e
ID		 5298 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5299 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5300 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5301 dev_priv->rps.min_freq);
5302
aed242ff
CW		 5303 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5304
4e80519e
ID		 5305 /* Preserve min/max settings in case of re-init */
5306 if (dev_priv->rps.max_freq_softlimit == 0)
5307 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5308
5309 if (dev_priv->rps.min_freq_softlimit == 0)
5310 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5311
5312 mutex_unlock(&dev_priv->rps.hw_lock);
5313}
5314
38807746
D		 5315static void cherryview_init_gt_powersave(struct drm_device *dev)
5316{
2b6b3a09 5317 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5318 u32 val;
2b6b3a09 5319
38807746 5320 cherryview_setup_pctx(dev);
2b6b3a09
D		 5321
5322 mutex_lock(&dev_priv->rps.hw_lock);
5323
a580516d 5324 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5325 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5326 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5327
2bb25c17 5328 switch ((val >> 2) & 0x7) {
2bb25c17 5329 case 3:
2bb25c17
VS		 5330 dev_priv->mem_freq = 2000;
5331 break;
bfa7df01 5332 default:
2bb25c17
VS		 5333 dev_priv->mem_freq = 1600;
5334 break;
5335 }
80b83b62 5336 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5337
2b6b3a09
D		 5338 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5339 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5340 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5341 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5342 dev_priv->rps.max_freq);
5343
5344 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5345 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5346 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5347 dev_priv->rps.efficient_freq);
5348
7707df4a
D		 5349 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5350 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5351 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5352 dev_priv->rps.rp1_freq);
5353
5b7c91b7
D		 5354 /* PUnit validated range is only [RPe, RP0] */
5355 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5356 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5357 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5358 dev_priv->rps.min_freq);
5359
1c14762d
VS		 5360 WARN_ONCE((dev_priv->rps.max_freq |
5361 dev_priv->rps.efficient_freq |
5362 dev_priv->rps.rp1_freq |
5363 dev_priv->rps.min_freq) & 1,
5364 "Odd GPU freq values\n");
5365
aed242ff
CW		 5366 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5367
2b6b3a09
D		 5368 /* Preserve min/max settings in case of re-init */
5369 if (dev_priv->rps.max_freq_softlimit == 0)
5370 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5371
5372 if (dev_priv->rps.min_freq_softlimit == 0)
5373 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5374
5375 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5376}
5377
4e80519e
ID		 5378static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5379{
5380 valleyview_cleanup_pctx(dev);
5381}
5382
38807746
D		 5383static void cherryview_enable_rps(struct drm_device *dev)
5384{
5385 struct drm_i915_private *dev_priv = dev->dev_private;
5386 struct intel_engine_cs *ring;
2b6b3a09 5387 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5388 int i;
5389
5390 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5391
5392 gtfifodbg = I915_READ(GTFIFODBG);
5393 if (gtfifodbg) {
5394 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5395 gtfifodbg);
5396 I915_WRITE(GTFIFODBG, gtfifodbg);
5397 }
5398
5399 cherryview_check_pctx(dev_priv);
5400
5401 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5402 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5403 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5404
160614a2
VS		 5405 /* Disable RC states. */
5406 I915_WRITE(GEN6_RC_CONTROL, 0);
5407
38807746
D		 5408 /* 2a: Program RC6 thresholds.*/
5409 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5410 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5411 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5412
5413 for_each_ring(ring, dev_priv, i)
5414 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5415 I915_WRITE(GEN6_RC_SLEEP, 0);
5416
f4f71c7d
D		 5417 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5418 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5419
5420 /* allows RC6 residency counter to work */
5421 I915_WRITE(VLV_COUNTER_CONTROL,
5422 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5423 VLV_MEDIA_RC6_COUNT_EN |
5424 VLV_RENDER_RC6_COUNT_EN));
5425
5426 /* For now we assume BIOS is allocating and populating the PCBR */
5427 pcbr = I915_READ(VLV_PCBR);
5428
38807746
D		 5429 /* 3: Enable RC6 */
5430 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5431 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5432 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5433
5434 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5435
2b6b3a09 5436 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5437 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5438 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5439 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5440 I915_WRITE(GEN6_RP_UP_EI, 66000);
5441 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5442
5443 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5444
5445 /* 5: Enable RPS */
5446 I915_WRITE(GEN6_RP_CONTROL,
5447 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5448 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5449 GEN6_RP_ENABLE |
5450 GEN6_RP_UP_BUSY_AVG |
5451 GEN6_RP_DOWN_IDLE_AVG);
5452
3ef62342
D		 5453 /* Setting Fixed Bias */
5454 val = VLV_OVERRIDE_EN |
5455 VLV_SOC_TDP_EN |
5456 CHV_BIAS_CPU_50_SOC_50;
5457 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5458
2b6b3a09
D		 5459 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5460
8d40c3ae
VS		 5461 /* RPS code assumes GPLL is used */
5462 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5463
742f491d 5464 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5465 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5466
5467 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5468 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5469 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5470 dev_priv->rps.cur_freq);
5471
5472 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5473 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5474 dev_priv->rps.efficient_freq);
5475
5476 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5477
59bad947 5478 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5479}
5480
0a073b84
JB		 5481static void valleyview_enable_rps(struct drm_device *dev)
5482{
5483 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5484 struct intel_engine_cs *ring;
2a5913a8 5485 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5486 int i;
5487
5488 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5489
ae48434c
ID		 5490 valleyview_check_pctx(dev_priv);
5491
0a073b84 5492 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5493 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5494 gtfifodbg);
0a073b84
JB		 5495 I915_WRITE(GTFIFODBG, gtfifodbg);
5496 }
5497
c8d9a590 5498 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5499 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5500
160614a2
VS		 5501 /* Disable RC states. */
5502 I915_WRITE(GEN6_RC_CONTROL, 0);
5503
cad725fe 5504 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5505 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5506 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5507 I915_WRITE(GEN6_RP_UP_EI, 66000);
5508 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5509
5510 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5511
5512 I915_WRITE(GEN6_RP_CONTROL,
5513 GEN6_RP_MEDIA_TURBO |
5514 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5515 GEN6_RP_MEDIA_IS_GFX |
5516 GEN6_RP_ENABLE |
5517 GEN6_RP_UP_BUSY_AVG |
5518 GEN6_RP_DOWN_IDLE_CONT);
5519
5520 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5521 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5522 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5523
5524 for_each_ring(ring, dev_priv, i)
5525 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5526
2f0aa304 5527 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5528
5529 /* allows RC6 residency counter to work */
49798eb2 5530 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5531 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5532 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5533 VLV_MEDIA_RC6_COUNT_EN |
5534 VLV_RENDER_RC6_COUNT_EN));
31685c25 5535
a2b23fe0 5536 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5537 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5538
5539 intel_print_rc6_info(dev, rc6_mode);
5540
a2b23fe0 5541 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5542
3ef62342
D		 5543 /* Setting Fixed Bias */
5544 val = VLV_OVERRIDE_EN |
5545 VLV_SOC_TDP_EN |
5546 VLV_BIAS_CPU_125_SOC_875;
5547 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5548
64936258 5549 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5550
8d40c3ae
VS		 5551 /* RPS code assumes GPLL is used */
5552 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5553
742f491d 5554 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5555 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5556
b39fb297 5557 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5558 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5559 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5560 dev_priv->rps.cur_freq);
0a073b84 5561
73008b98 5562 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5563 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5564 dev_priv->rps.efficient_freq);
0a073b84 5565
b39fb297 5566 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5567
59bad947 5568 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5569}
5570
dde18883
ED		 5571static unsigned long intel_pxfreq(u32 vidfreq)
5572{
5573 unsigned long freq;
5574 int div = (vidfreq & 0x3f0000) >> 16;
5575 int post = (vidfreq & 0x3000) >> 12;
5576 int pre = (vidfreq & 0x7);
5577
5578 if (!pre)
5579 return 0;
5580
5581 freq = ((div * 133333) / ((1<<post) * pre));
5582
5583 return freq;
5584}
5585
eb48eb00
DV		 5586static const struct cparams {
5587 u16 i;
5588 u16 t;
5589 u16 m;
5590 u16 c;
5591} cparams[] = {
5592 { 1, 1333, 301, 28664 },
5593 { 1, 1066, 294, 24460 },
5594 { 1, 800, 294, 25192 },
5595 { 0, 1333, 276, 27605 },
5596 { 0, 1066, 276, 27605 },
5597 { 0, 800, 231, 23784 },
5598};
5599
f531dcb2 5600static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5601{
5602 u64 total_count, diff, ret;
5603 u32 count1, count2, count3, m = 0, c = 0;
5604 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5605 int i;
5606
02d71956
DV		 5607 assert_spin_locked(&mchdev_lock);
5608
20e4d407 5609 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5610
5611 /* Prevent division-by-zero if we are asking too fast.
5612 * Also, we don't get interesting results if we are polling
5613 * faster than once in 10ms, so just return the saved value
5614 * in such cases.
5615 */
5616 if (diff1 <= 10)
20e4d407 5617 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5618
5619 count1 = I915_READ(DMIEC);
5620 count2 = I915_READ(DDREC);
5621 count3 = I915_READ(CSIEC);
5622
5623 total_count = count1 + count2 + count3;
5624
5625 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5626 if (total_count < dev_priv->ips.last_count1) {
5627 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5628 diff += total_count;
5629 } else {
20e4d407 5630 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5631 }
5632
5633 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5634 if (cparams[i].i == dev_priv->ips.c_m &&
5635 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5636 m = cparams[i].m;
5637 c = cparams[i].c;
5638 break;
5639 }
5640 }
5641
5642 diff = div_u64(diff, diff1);
5643 ret = ((m * diff) + c);
5644 ret = div_u64(ret, 10);
5645
20e4d407
DV		 5646 dev_priv->ips.last_count1 = total_count;
5647 dev_priv->ips.last_time1 = now;
eb48eb00 5648
20e4d407 5649 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5650
5651 return ret;
5652}
5653
f531dcb2
CW		 5654unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5655{
3d13ef2e 5656 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5657 unsigned long val;
5658
3d13ef2e 5659 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5660 return 0;
5661
5662 spin_lock_irq(&mchdev_lock);
5663
5664 val = __i915_chipset_val(dev_priv);
5665
5666 spin_unlock_irq(&mchdev_lock);
5667
5668 return val;
5669}
5670
eb48eb00
DV		 5671unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5672{
5673 unsigned long m, x, b;
5674 u32 tsfs;
5675
5676 tsfs = I915_READ(TSFS);
5677
5678 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5679 x = I915_READ8(TR1);
5680
5681 b = tsfs & TSFS_INTR_MASK;
5682
5683 return ((m * x) / 127) - b;
5684}
5685
d972d6ee
MK		 5686static int _pxvid_to_vd(u8 pxvid)
5687{
5688 if (pxvid == 0)
5689 return 0;
5690
5691 if (pxvid >= 8 && pxvid < 31)
5692 pxvid = 31;
5693
5694 return (pxvid + 2) * 125;
5695}
5696
5697static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5698{
3d13ef2e 5699 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5700 const int vd = _pxvid_to_vd(pxvid);
5701 const int vm = vd - 1125;
5702
3d13ef2e 5703 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5704 return vm > 0 ? vm : 0;
5705
5706 return vd;
eb48eb00
DV		 5707}
5708
02d71956 5709static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5710{
5ed0bdf2 5711 u64 now, diff, diffms;
eb48eb00
DV		 5712 u32 count;
5713
02d71956 5714 assert_spin_locked(&mchdev_lock);
eb48eb00 5715
5ed0bdf2
TG		 5716 now = ktime_get_raw_ns();
5717 diffms = now - dev_priv->ips.last_time2;
5718 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5719
5720 /* Don't divide by 0 */
eb48eb00
DV		 5721 if (!diffms)
5722 return;
5723
5724 count = I915_READ(GFXEC);
5725
20e4d407
DV		 5726 if (count < dev_priv->ips.last_count2) {
5727 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5728 diff += count;
5729 } else {
20e4d407 5730 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5731 }
5732
20e4d407
DV		 5733 dev_priv->ips.last_count2 = count;
5734 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5735
5736 /* More magic constants... */
5737 diff = diff * 1181;
5738 diff = div_u64(diff, diffms * 10);
20e4d407 5739 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5740}
5741
02d71956
DV		 5742void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5743{
3d13ef2e
DL		 5744 struct drm_device *dev = dev_priv->dev;
5745
5746 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5747 return;
5748
9270388e 5749 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5750
5751 __i915_update_gfx_val(dev_priv);
5752
9270388e 5753 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5754}
5755
f531dcb2 5756static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5757{
5758 unsigned long t, corr, state1, corr2, state2;
5759 u32 pxvid, ext_v;
5760
02d71956
DV		 5761 assert_spin_locked(&mchdev_lock);
5762
616847e7 5763 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5764 pxvid = (pxvid >> 24) & 0x7f;
5765 ext_v = pvid_to_extvid(dev_priv, pxvid);
5766
5767 state1 = ext_v;
5768
5769 t = i915_mch_val(dev_priv);
5770
5771 /* Revel in the empirically derived constants */
5772
5773 /* Correction factor in 1/100000 units */
5774 if (t > 80)
5775 corr = ((t * 2349) + 135940);
5776 else if (t >= 50)
5777 corr = ((t * 964) + 29317);
5778 else /* < 50 */
5779 corr = ((t * 301) + 1004);
5780
5781 corr = corr * ((150142 * state1) / 10000 - 78642);
5782 corr /= 100000;
20e4d407 5783 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5784
5785 state2 = (corr2 * state1) / 10000;
5786 state2 /= 100; /* convert to mW */
5787
02d71956 5788 __i915_update_gfx_val(dev_priv);
eb48eb00 5789
20e4d407 5790 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5791}
5792
f531dcb2
CW		 5793unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5794{
3d13ef2e 5795 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5796 unsigned long val;
5797
3d13ef2e 5798 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5799 return 0;
5800
5801 spin_lock_irq(&mchdev_lock);
5802
5803 val = __i915_gfx_val(dev_priv);
5804
5805 spin_unlock_irq(&mchdev_lock);
5806
5807 return val;
5808}
5809
eb48eb00
DV		 5810/**
5811 * i915_read_mch_val - return value for IPS use
5812 *
5813 * Calculate and return a value for the IPS driver to use when deciding whether
5814 * we have thermal and power headroom to increase CPU or GPU power budget.
5815 */
5816unsigned long i915_read_mch_val(void)
5817{
5818 struct drm_i915_private *dev_priv;
5819 unsigned long chipset_val, graphics_val, ret = 0;
5820
9270388e 5821 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5822 if (!i915_mch_dev)
5823 goto out_unlock;
5824 dev_priv = i915_mch_dev;
5825
f531dcb2
CW		 5826 chipset_val = __i915_chipset_val(dev_priv);
5827 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5828
5829 ret = chipset_val + graphics_val;
5830
5831out_unlock:
9270388e 5832 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5833
5834 return ret;
5835}
5836EXPORT_SYMBOL_GPL(i915_read_mch_val);
5837
5838/**
5839 * i915_gpu_raise - raise GPU frequency limit
5840 *
5841 * Raise the limit; IPS indicates we have thermal headroom.
5842 */
5843bool i915_gpu_raise(void)
5844{
5845 struct drm_i915_private *dev_priv;
5846 bool ret = true;
5847
9270388e 5848 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5849 if (!i915_mch_dev) {
5850 ret = false;
5851 goto out_unlock;
5852 }
5853 dev_priv = i915_mch_dev;
5854
20e4d407
DV		 5855 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5856 dev_priv->ips.max_delay--;
eb48eb00
DV		 5857
5858out_unlock:
9270388e 5859 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5860
5861 return ret;
5862}
5863EXPORT_SYMBOL_GPL(i915_gpu_raise);
5864
5865/**
5866 * i915_gpu_lower - lower GPU frequency limit
5867 *
5868 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5869 * frequency maximum.
5870 */
5871bool i915_gpu_lower(void)
5872{
5873 struct drm_i915_private *dev_priv;
5874 bool ret = true;
5875
9270388e 5876 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5877 if (!i915_mch_dev) {
5878 ret = false;
5879 goto out_unlock;
5880 }
5881 dev_priv = i915_mch_dev;
5882
20e4d407
DV		 5883 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5884 dev_priv->ips.max_delay++;
eb48eb00
DV		 5885
5886out_unlock:
9270388e 5887 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5888
5889 return ret;
5890}
5891EXPORT_SYMBOL_GPL(i915_gpu_lower);
5892
5893/**
5894 * i915_gpu_busy - indicate GPU business to IPS
5895 *
5896 * Tell the IPS driver whether or not the GPU is busy.
5897 */
5898bool i915_gpu_busy(void)
5899{
5900 struct drm_i915_private *dev_priv;
a4872ba6 5901 struct intel_engine_cs *ring;
eb48eb00 5902 bool ret = false;
f047e395 5903 int i;
eb48eb00 5904
9270388e 5905 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5906 if (!i915_mch_dev)
5907 goto out_unlock;
5908 dev_priv = i915_mch_dev;
5909
f047e395
CW		 5910 for_each_ring(ring, dev_priv, i)
5911 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5912
5913out_unlock:
9270388e 5914 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5915
5916 return ret;
5917}
5918EXPORT_SYMBOL_GPL(i915_gpu_busy);
5919
5920/**
5921 * i915_gpu_turbo_disable - disable graphics turbo
5922 *
5923 * Disable graphics turbo by resetting the max frequency and setting the
5924 * current frequency to the default.
5925 */
5926bool i915_gpu_turbo_disable(void)
5927{
5928 struct drm_i915_private *dev_priv;
5929 bool ret = true;
5930
9270388e 5931 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5932 if (!i915_mch_dev) {
5933 ret = false;
5934 goto out_unlock;
5935 }
5936 dev_priv = i915_mch_dev;
5937
20e4d407 5938 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5939
20e4d407 5940 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5941 ret = false;
5942
5943out_unlock:
9270388e 5944 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5945
5946 return ret;
5947}
5948EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5949
5950/**
5951 * Tells the intel_ips driver that the i915 driver is now loaded, if
5952 * IPS got loaded first.
5953 *
5954 * This awkward dance is so that neither module has to depend on the
5955 * other in order for IPS to do the appropriate communication of
5956 * GPU turbo limits to i915.
5957 */
5958static void
5959ips_ping_for_i915_load(void)
5960{
5961 void (*link)(void);
5962
5963 link = symbol_get(ips_link_to_i915_driver);
5964 if (link) {
5965 link();
5966 symbol_put(ips_link_to_i915_driver);
5967 }
5968}
5969
5970void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5971{
02d71956
DV		 5972 /* We only register the i915 ips part with intel-ips once everything is
5973 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5974 spin_lock_irq(&mchdev_lock);
eb48eb00 5975 i915_mch_dev = dev_priv;
9270388e 5976 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5977
5978 ips_ping_for_i915_load();
5979}
5980
5981void intel_gpu_ips_teardown(void)
5982{
9270388e 5983 spin_lock_irq(&mchdev_lock);
eb48eb00 5984 i915_mch_dev = NULL;
9270388e 5985 spin_unlock_irq(&mchdev_lock);
eb48eb00 5986}
76c3552f 5987
8090c6b9 5988static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5989{
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 u32 lcfuse;
5992 u8 pxw[16];
5993 int i;
5994
5995 /* Disable to program */
5996 I915_WRITE(ECR, 0);
5997 POSTING_READ(ECR);
5998
5999 /* Program energy weights for various events */
6000 I915_WRITE(SDEW, 0x15040d00);
6001 I915_WRITE(CSIEW0, 0x007f0000);
6002 I915_WRITE(CSIEW1, 0x1e220004);
6003 I915_WRITE(CSIEW2, 0x04000004);
6004
6005 for (i = 0; i < 5; i++)
616847e7 6006 I915_WRITE(PEW(i), 0);
dde18883 6007 for (i = 0; i < 3; i++)
616847e7 6008 I915_WRITE(DEW(i), 0);
dde18883
ED		 6009
6010 /* Program P-state weights to account for frequency power adjustment */
6011 for (i = 0; i < 16; i++) {
616847e7 6012 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6013 unsigned long freq = intel_pxfreq(pxvidfreq);
6014 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6015 PXVFREQ_PX_SHIFT;
6016 unsigned long val;
6017
6018 val = vid * vid;
6019 val *= (freq / 1000);
6020 val *= 255;
6021 val /= (127*127*900);
6022 if (val > 0xff)
6023 DRM_ERROR("bad pxval: %ld\n", val);
6024 pxw[i] = val;
6025 }
6026 /* Render standby states get 0 weight */
6027 pxw[14] = 0;
6028 pxw[15] = 0;
6029
6030 for (i = 0; i < 4; i++) {
6031 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6032 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6033 I915_WRITE(PXW(i), val);
dde18883
ED		 6034 }
6035
6036 /* Adjust magic regs to magic values (more experimental results) */
6037 I915_WRITE(OGW0, 0);
6038 I915_WRITE(OGW1, 0);
6039 I915_WRITE(EG0, 0x00007f00);
6040 I915_WRITE(EG1, 0x0000000e);
6041 I915_WRITE(EG2, 0x000e0000);
6042 I915_WRITE(EG3, 0x68000300);
6043 I915_WRITE(EG4, 0x42000000);
6044 I915_WRITE(EG5, 0x00140031);
6045 I915_WRITE(EG6, 0);
6046 I915_WRITE(EG7, 0);
6047
6048 for (i = 0; i < 8; i++)
616847e7 6049 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6050
6051 /* Enable PMON + select events */
6052 I915_WRITE(ECR, 0x80000019);
6053
6054 lcfuse = I915_READ(LCFUSE02);
6055
20e4d407 6056 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6057}
6058
ae48434c
ID		 6059void intel_init_gt_powersave(struct drm_device *dev)
6060{
e6069ca8
ID		 6061 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6062
38807746
D		 6063 if (IS_CHERRYVIEW(dev))
6064 cherryview_init_gt_powersave(dev);
6065 else if (IS_VALLEYVIEW(dev))
4e80519e 6066 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6067}
6068
6069void intel_cleanup_gt_powersave(struct drm_device *dev)
6070{
38807746
D		 6071 if (IS_CHERRYVIEW(dev))
6072 return;
6073 else if (IS_VALLEYVIEW(dev))
4e80519e 6074 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6075}
6076
dbea3cea
ID		 6077static void gen6_suspend_rps(struct drm_device *dev)
6078{
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080
6081 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6082
4c2a8897 6083 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6084}
6085
156c7ca0
JB		 6086/**
6087 * intel_suspend_gt_powersave - suspend PM work and helper threads
6088 * @dev: drm device
6089 *
6090 * We don't want to disable RC6 or other features here, we just want
6091 * to make sure any work we've queued has finished and won't bother
6092 * us while we're suspended.
6093 */
6094void intel_suspend_gt_powersave(struct drm_device *dev)
6095{
6096 struct drm_i915_private *dev_priv = dev->dev_private;
6097
d4d70aa5
ID		 6098 if (INTEL_INFO(dev)->gen < 6)
6099 return;
6100
dbea3cea 6101 gen6_suspend_rps(dev);
b47adc17
D		 6102
6103 /* Force GPU to min freq during suspend */
6104 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6105}
6106
8090c6b9
DV		 6107void intel_disable_gt_powersave(struct drm_device *dev)
6108{
1a01ab3b
JB		 6109 struct drm_i915_private *dev_priv = dev->dev_private;
6110
930ebb46 6111 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6112 ironlake_disable_drps(dev);
38807746 6113 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6114 intel_suspend_gt_powersave(dev);
e494837a 6115
4fc688ce 6116 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6117 if (INTEL_INFO(dev)->gen >= 9)
6118 gen9_disable_rps(dev);
6119 else if (IS_CHERRYVIEW(dev))
38807746
D		 6120 cherryview_disable_rps(dev);
6121 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6122 valleyview_disable_rps(dev);
6123 else
6124 gen6_disable_rps(dev);
e534770a 6125
c0951f0c 6126 dev_priv->rps.enabled = false;
4fc688ce 6127 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6128 }
8090c6b9
DV		 6129}
6130
1a01ab3b
JB		 6131static void intel_gen6_powersave_work(struct work_struct *work)
6132{
6133 struct drm_i915_private *dev_priv =
6134 container_of(work, struct drm_i915_private,
6135 rps.delayed_resume_work.work);
6136 struct drm_device *dev = dev_priv->dev;
6137
4fc688ce 6138 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6139
4c2a8897 6140 gen6_reset_rps_interrupts(dev);
3cc134e3 6141
38807746
D		 6142 if (IS_CHERRYVIEW(dev)) {
6143 cherryview_enable_rps(dev);
6144 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6145 valleyview_enable_rps(dev);
20e49366 6146 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6147 gen9_enable_rc6(dev);
20e49366 6148 gen9_enable_rps(dev);
cc017fb4
AG		 6149 if (IS_SKYLAKE(dev))
6150 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6151 } else if (IS_BROADWELL(dev)) {
6152 gen8_enable_rps(dev);
c2bc2fc5 6153 __gen6_update_ring_freq(dev);
0a073b84
JB		 6154 } else {
6155 gen6_enable_rps(dev);
c2bc2fc5 6156 __gen6_update_ring_freq(dev);
0a073b84 6157 }
aed242ff
CW		 6158
6159 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6160 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6161
6162 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6163 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6164
c0951f0c 6165 dev_priv->rps.enabled = true;
3cc134e3 6166
4c2a8897 6167 gen6_enable_rps_interrupts(dev);
3cc134e3 6168
4fc688ce 6169 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6170
6171 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6172}
6173
8090c6b9
DV		 6174void intel_enable_gt_powersave(struct drm_device *dev)
6175{
1a01ab3b
JB		 6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177
f61018b1
YZ		 6178 /* Powersaving is controlled by the host when inside a VM */
6179 if (intel_vgpu_active(dev))
6180 return;
6181
8090c6b9 6182 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6183 mutex_lock(&dev->struct_mutex);
8090c6b9 6184 ironlake_enable_drps(dev);
8090c6b9 6185 intel_init_emon(dev);
dc1d0136 6186 mutex_unlock(&dev->struct_mutex);
38807746 6187 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6188 /*
6189 * PCU communication is slow and this doesn't need to be
6190 * done at any specific time, so do this out of our fast path
6191 * to make resume and init faster.
c6df39b5
ID		 6192 *
6193 * We depend on the HW RC6 power context save/restore
6194 * mechanism when entering D3 through runtime PM suspend. So
6195 * disable RPM until RPS/RC6 is properly setup. We can only
6196 * get here via the driver load/system resume/runtime resume
6197 * paths, so the _noresume version is enough (and in case of
6198 * runtime resume it's necessary).
1a01ab3b 6199 */
c6df39b5
ID		 6200 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6201 round_jiffies_up_relative(HZ)))
6202 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6203 }
6204}
6205
c6df39b5
ID		 6206void intel_reset_gt_powersave(struct drm_device *dev)
6207{
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209
dbea3cea
ID		 6210 if (INTEL_INFO(dev)->gen < 6)
6211 return;
6212
6213 gen6_suspend_rps(dev);
c6df39b5 6214 dev_priv->rps.enabled = false;
c6df39b5
ID		 6215}
6216
3107bd48
DV		 6217static void ibx_init_clock_gating(struct drm_device *dev)
6218{
6219 struct drm_i915_private *dev_priv = dev->dev_private;
6220
6221 /*
6222 * On Ibex Peak and Cougar Point, we need to disable clock
6223 * gating for the panel power sequencer or it will fail to
6224 * start up when no ports are active.
6225 */
6226 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6227}
6228
0e088b8f
VS		 6229static void g4x_disable_trickle_feed(struct drm_device *dev)
6230{
6231 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6232 enum pipe pipe;
0e088b8f 6233
055e393f 6234 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6235 I915_WRITE(DSPCNTR(pipe),
6236 I915_READ(DSPCNTR(pipe)) |
6237 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6238
6239 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6240 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6241 }
6242}
6243
017636cc
VS		 6244static void ilk_init_lp_watermarks(struct drm_device *dev)
6245{
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247
6248 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6249 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6250 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6251
6252 /*
6253 * Don't touch WM1S_LP_EN here.
6254 * Doing so could cause underruns.
6255 */
6256}
6257
1fa61106 6258static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6259{
6260 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6261 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6262
f1e8fa56
DL		 6263 /*
6264 * Required for FBC
6265 * WaFbcDisableDpfcClockGating:ilk
6266 */
4d47e4f5
DL		 6267 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6268 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6269 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6270
6271 I915_WRITE(PCH_3DCGDIS0,
6272 MARIUNIT_CLOCK_GATE_DISABLE |
6273 SVSMUNIT_CLOCK_GATE_DISABLE);
6274 I915_WRITE(PCH_3DCGDIS1,
6275 VFMUNIT_CLOCK_GATE_DISABLE);
6276
6f1d69b0
ED		 6277 /*
6278 * According to the spec the following bits should be set in
6279 * order to enable memory self-refresh
6280 * The bit 22/21 of 0x42004
6281 * The bit 5 of 0x42020
6282 * The bit 15 of 0x45000
6283 */
6284 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6285 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6286 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6287 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6288 I915_WRITE(DISP_ARB_CTL,
6289 (I915_READ(DISP_ARB_CTL) |
6290 DISP_FBC_WM_DIS));
017636cc
VS		 6291
6292 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6293
6294 /*
6295 * Based on the document from hardware guys the following bits
6296 * should be set unconditionally in order to enable FBC.
6297 * The bit 22 of 0x42000
6298 * The bit 22 of 0x42004
6299 * The bit 7,8,9 of 0x42020.
6300 */
6301 if (IS_IRONLAKE_M(dev)) {
4bb35334 6302 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6303 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6304 I915_READ(ILK_DISPLAY_CHICKEN1) |
6305 ILK_FBCQ_DIS);
6306 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6307 I915_READ(ILK_DISPLAY_CHICKEN2) |
6308 ILK_DPARB_GATE);
6f1d69b0
ED		 6309 }
6310
4d47e4f5
DL		 6311 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6312
6f1d69b0
ED		 6313 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6314 I915_READ(ILK_DISPLAY_CHICKEN2) |
6315 ILK_ELPIN_409_SELECT);
6316 I915_WRITE(_3D_CHICKEN2,
6317 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6318 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6319
ecdb4eb7 6320 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6321 I915_WRITE(CACHE_MODE_0,
6322 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6323
4e04632e
AG		 6324 /* WaDisable_RenderCache_OperationalFlush:ilk */
6325 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6326
0e088b8f 6327 g4x_disable_trickle_feed(dev);
bdad2b2f 6328
3107bd48
DV		 6329 ibx_init_clock_gating(dev);
6330}
6331
6332static void cpt_init_clock_gating(struct drm_device *dev)
6333{
6334 struct drm_i915_private *dev_priv = dev->dev_private;
6335 int pipe;
3f704fa2 6336 uint32_t val;
3107bd48
DV		 6337
6338 /*
6339 * On Ibex Peak and Cougar Point, we need to disable clock
6340 * gating for the panel power sequencer or it will fail to
6341 * start up when no ports are active.
6342 */
cd664078
JB		 6343 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6344 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6345 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6346 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6347 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6348 /* The below fixes the weird display corruption, a few pixels shifted
6349 * downward, on (only) LVDS of some HP laptops with IVY.
6350 */
055e393f 6351 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6352 val = I915_READ(TRANS_CHICKEN2(pipe));
6353 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6354 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6355 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6356 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6357 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6358 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6359 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6360 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6361 }
3107bd48 6362 /* WADP0ClockGatingDisable */
055e393f 6363 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6364 I915_WRITE(TRANS_CHICKEN1(pipe),
6365 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6366 }
6f1d69b0
ED		 6367}
6368
1d7aaa0c
DV		 6369static void gen6_check_mch_setup(struct drm_device *dev)
6370{
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 uint32_t tmp;
6373
6374 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6375 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6376 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6377 tmp);
1d7aaa0c
DV		 6378}
6379
1fa61106 6380static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6381{
6382 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6383 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6384
231e54f6 6385 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6386
6387 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6388 I915_READ(ILK_DISPLAY_CHICKEN2) |
6389 ILK_ELPIN_409_SELECT);
6390
ecdb4eb7 6391 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6392 I915_WRITE(_3D_CHICKEN,
6393 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6394
4e04632e
AG		 6395 /* WaDisable_RenderCache_OperationalFlush:snb */
6396 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6397
8d85d272
VS		 6398 /*
6399 * BSpec recoomends 8x4 when MSAA is used,
6400 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6401 *
6402 * Note that PS/WM thread counts depend on the WIZ hashing
6403 * disable bit, which we don't touch here, but it's good
6404 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6405 */
6406 I915_WRITE(GEN6_GT_MODE,
98533251 6407 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6408
017636cc 6409 ilk_init_lp_watermarks(dev);
6f1d69b0 6410
6f1d69b0 6411 I915_WRITE(CACHE_MODE_0,
50743298 6412 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6413
6414 I915_WRITE(GEN6_UCGCTL1,
6415 I915_READ(GEN6_UCGCTL1) |
6416 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6417 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6418
6419 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6420 * gating disable must be set. Failure to set it results in
6421 * flickering pixels due to Z write ordering failures after
6422 * some amount of runtime in the Mesa "fire" demo, and Unigine
6423 * Sanctuary and Tropics, and apparently anything else with
6424 * alpha test or pixel discard.
6425 *
6426 * According to the spec, bit 11 (RCCUNIT) must also be set,
6427 * but we didn't debug actual testcases to find it out.
0f846f81 6428 *
ef59318c
VS		 6429 * WaDisableRCCUnitClockGating:snb
6430 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6431 */
6432 I915_WRITE(GEN6_UCGCTL2,
6433 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6434 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6435
5eb146dd 6436 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6437 I915_WRITE(_3D_CHICKEN3,
6438 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6439
e927ecde
VS		 6440 /*
6441 * Bspec says:
6442 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6443 * 3DSTATE_SF number of SF output attributes is more than 16."
6444 */
6445 I915_WRITE(_3D_CHICKEN3,
6446 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6447
6f1d69b0
ED		 6448 /*
6449 * According to the spec the following bits should be
6450 * set in order to enable memory self-refresh and fbc:
6451 * The bit21 and bit22 of 0x42000
6452 * The bit21 and bit22 of 0x42004
6453 * The bit5 and bit7 of 0x42020
6454 * The bit14 of 0x70180
6455 * The bit14 of 0x71180
4bb35334
DL		 6456 *
6457 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6458 */
6459 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6460 I915_READ(ILK_DISPLAY_CHICKEN1) |
6461 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6462 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6463 I915_READ(ILK_DISPLAY_CHICKEN2) |
6464 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6465 I915_WRITE(ILK_DSPCLK_GATE_D,
6466 I915_READ(ILK_DSPCLK_GATE_D) |
6467 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6468 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6469
0e088b8f 6470 g4x_disable_trickle_feed(dev);
f8f2ac9a 6471
3107bd48 6472 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6473
6474 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6475}
6476
6477static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6478{
6479 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6480
3aad9059 6481 /*
46680e0a 6482 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6483 *
6484 * This actually overrides the dispatch
6485 * mode for all thread types.
6486 */
6f1d69b0
ED		 6487 reg &= ~GEN7_FF_SCHED_MASK;
6488 reg |= GEN7_FF_TS_SCHED_HW;
6489 reg |= GEN7_FF_VS_SCHED_HW;
6490 reg |= GEN7_FF_DS_SCHED_HW;
6491
6492 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6493}
6494
17a303ec
PZ		 6495static void lpt_init_clock_gating(struct drm_device *dev)
6496{
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498
6499 /*
6500 * TODO: this bit should only be enabled when really needed, then
6501 * disabled when not needed anymore in order to save power.
6502 */
c2699524 6503 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6504 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6505 I915_READ(SOUTH_DSPCLK_GATE_D) |
6506 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6507
6508 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6509 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6510 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6511 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6512}
6513
7d708ee4
ID		 6514static void lpt_suspend_hw(struct drm_device *dev)
6515{
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517
c2699524 6518 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6519 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6520
6521 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6522 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6523 }
6524}
6525
47c2bd97 6526static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6527{
6528 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6529 enum pipe pipe;
4d487cff 6530 uint32_t misccpctl;
1020a5c2 6531
7ad0dbab 6532 ilk_init_lp_watermarks(dev);
50ed5fbd 6533
ab57fff1 6534 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6535 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6536
ab57fff1 6537 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6538 I915_WRITE(CHICKEN_PAR1_1,
6539 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6540
ab57fff1 6541 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6542 for_each_pipe(dev_priv, pipe) {
07d27e20 6543 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6544 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6545 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6546 }
63801f21 6547
ab57fff1
BW		 6548 /* WaVSRefCountFullforceMissDisable:bdw */
6549 /* WaDSRefCountFullforceMissDisable:bdw */
6550 I915_WRITE(GEN7_FF_THREAD_MODE,
6551 I915_READ(GEN7_FF_THREAD_MODE) &
6552 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6553
295e8bb7
VS		 6554 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6555 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6556
6557 /* WaDisableSDEUnitClockGating:bdw */
6558 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6559 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6560
4d487cff
VS		 6561 /*
6562 * WaProgramL3SqcReg1Default:bdw
6563 * WaTempDisableDOPClkGating:bdw
6564 */
6565 misccpctl = I915_READ(GEN7_MISCCPCTL);
6566 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6567 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6568 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6569
6d50b065
VS		 6570 /*
6571 * WaGttCachingOffByDefault:bdw
6572 * GTT cache may not work with big pages, so if those
6573 * are ever enabled GTT cache may need to be disabled.
6574 */
6575 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6576
89d6b2b8 6577 lpt_init_clock_gating(dev);
1020a5c2
BW		 6578}
6579
cad2a2d7
ED		 6580static void haswell_init_clock_gating(struct drm_device *dev)
6581{
6582 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6583
017636cc 6584 ilk_init_lp_watermarks(dev);
cad2a2d7 6585
f3fc4884
FJ		 6586 /* L3 caching of data atomics doesn't work -- disable it. */
6587 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6588 I915_WRITE(HSW_ROW_CHICKEN3,
6589 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6590
ecdb4eb7 6591 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6592 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6593 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6594 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6595
e36ea7ff
VS		 6596 /* WaVSRefCountFullforceMissDisable:hsw */
6597 I915_WRITE(GEN7_FF_THREAD_MODE,
6598 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6599
4e04632e
AG		 6600 /* WaDisable_RenderCache_OperationalFlush:hsw */
6601 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6602
fe27c606
CW		 6603 /* enable HiZ Raw Stall Optimization */
6604 I915_WRITE(CACHE_MODE_0_GEN7,
6605 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6606
ecdb4eb7 6607 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6608 I915_WRITE(CACHE_MODE_1,
6609 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6610
a12c4967
VS		 6611 /*
6612 * BSpec recommends 8x4 when MSAA is used,
6613 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6614 *
6615 * Note that PS/WM thread counts depend on the WIZ hashing
6616 * disable bit, which we don't touch here, but it's good
6617 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6618 */
6619 I915_WRITE(GEN7_GT_MODE,
98533251 6620 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6621
94411593
KG		 6622 /* WaSampleCChickenBitEnable:hsw */
6623 I915_WRITE(HALF_SLICE_CHICKEN3,
6624 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6625
ecdb4eb7 6626 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6627 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6628
90a88643
PZ		 6629 /* WaRsPkgCStateDisplayPMReq:hsw */
6630 I915_WRITE(CHICKEN_PAR1_1,
6631 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6632
17a303ec 6633 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6634}
6635
1fa61106 6636static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6637{
6638 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6639 uint32_t snpcr;
6f1d69b0 6640
017636cc 6641 ilk_init_lp_watermarks(dev);
6f1d69b0 6642
231e54f6 6643 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6644
ecdb4eb7 6645 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6646 I915_WRITE(_3D_CHICKEN3,
6647 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6648
ecdb4eb7 6649 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6650 I915_WRITE(IVB_CHICKEN3,
6651 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6652 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6653
ecdb4eb7 6654 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6655 if (IS_IVB_GT1(dev))
6656 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6657 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6658
4e04632e
AG		 6659 /* WaDisable_RenderCache_OperationalFlush:ivb */
6660 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6661
ecdb4eb7 6662 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6663 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6664 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6665
ecdb4eb7 6666 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6667 I915_WRITE(GEN7_L3CNTLREG1,
6668 GEN7_WA_FOR_GEN7_L3_CONTROL);
6669 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6670 GEN7_WA_L3_CHICKEN_MODE);
6671 if (IS_IVB_GT1(dev))
6672 I915_WRITE(GEN7_ROW_CHICKEN2,
6673 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6674 else {
6675 /* must write both registers */
6676 I915_WRITE(GEN7_ROW_CHICKEN2,
6677 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6678 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6679 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6680 }
6f1d69b0 6681
ecdb4eb7 6682 /* WaForceL3Serialization:ivb */
61939d97
JB		 6683 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6684 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6685
1b80a19a 6686 /*
0f846f81 6687 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6688 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6689 */
6690 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6691 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6692
ecdb4eb7 6693 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6694 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6695 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6696 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6697
0e088b8f 6698 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6699
6700 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6701
22721343
CW		 6702 if (0) { /* causes HiZ corruption on ivb:gt1 */
6703 /* enable HiZ Raw Stall Optimization */
6704 I915_WRITE(CACHE_MODE_0_GEN7,
6705 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6706 }
116f2b6d 6707
ecdb4eb7 6708 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6709 I915_WRITE(CACHE_MODE_1,
6710 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6711
a607c1a4
VS		 6712 /*
6713 * BSpec recommends 8x4 when MSAA is used,
6714 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6715 *
6716 * Note that PS/WM thread counts depend on the WIZ hashing
6717 * disable bit, which we don't touch here, but it's good
6718 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6719 */
6720 I915_WRITE(GEN7_GT_MODE,
98533251 6721 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6722
20848223
BW		 6723 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6724 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6725 snpcr |= GEN6_MBC_SNPCR_MED;
6726 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6727
ab5c608b
BW		 6728 if (!HAS_PCH_NOP(dev))
6729 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6730
6731 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6732}
6733
c6beb13e
VS		 6734static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6735{
6736 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6737
6738 /*
6739 * Disable trickle feed and enable pnd deadline calculation
6740 */
6741 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6742 I915_WRITE(CBR1_VLV, 0);
6743}
6744
1fa61106 6745static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6746{
6747 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6748
c6beb13e 6749 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6750
ecdb4eb7 6751 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6752 I915_WRITE(_3D_CHICKEN3,
6753 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6754
ecdb4eb7 6755 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6756 I915_WRITE(IVB_CHICKEN3,
6757 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6758 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6759
fad7d36e 6760 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6761 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6762 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6763 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6764 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6765
4e04632e
AG		 6766 /* WaDisable_RenderCache_OperationalFlush:vlv */
6767 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6768
ecdb4eb7 6769 /* WaForceL3Serialization:vlv */
61939d97
JB		 6770 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6771 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6772
ecdb4eb7 6773 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6774 I915_WRITE(GEN7_ROW_CHICKEN2,
6775 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6776
ecdb4eb7 6777 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6778 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6779 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6780 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6781
46680e0a
VS		 6782 gen7_setup_fixed_func_scheduler(dev_priv);
6783
3c0edaeb 6784 /*
0f846f81 6785 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6786 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6787 */
6788 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6789 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6790
c98f5062
AG		 6791 /* WaDisableL3Bank2xClockGate:vlv
6792 * Disabling L3 clock gating- MMIO 940c[25] = 1
6793 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6794 I915_WRITE(GEN7_UCGCTL4,
6795 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6796
afd58e79
VS		 6797 /*
6798 * BSpec says this must be set, even though
6799 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6800 */
6b26c86d
DV		 6801 I915_WRITE(CACHE_MODE_1,
6802 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6803
da2518f9
VS		 6804 /*
6805 * BSpec recommends 8x4 when MSAA is used,
6806 * however in practice 16x4 seems fastest.
6807 *
6808 * Note that PS/WM thread counts depend on the WIZ hashing
6809 * disable bit, which we don't touch here, but it's good
6810 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6811 */
6812 I915_WRITE(GEN7_GT_MODE,
6813 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6814
031994ee
VS		 6815 /*
6816 * WaIncreaseL3CreditsForVLVB0:vlv
6817 * This is the hardware default actually.
6818 */
6819 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6820
2d809570 6821 /*
ecdb4eb7 6822 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6823 * Disable clock gating on th GCFG unit to prevent a delay
6824 * in the reporting of vblank events.
6825 */
7a0d1eed 6826 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6827}
6828
a4565da8
VS		 6829static void cherryview_init_clock_gating(struct drm_device *dev)
6830{
6831 struct drm_i915_private *dev_priv = dev->dev_private;
6832
c6beb13e 6833 vlv_init_display_clock_gating(dev_priv);
dd811e70 6834
232ce337
VS		 6835 /* WaVSRefCountFullforceMissDisable:chv */
6836 /* WaDSRefCountFullforceMissDisable:chv */
6837 I915_WRITE(GEN7_FF_THREAD_MODE,
6838 I915_READ(GEN7_FF_THREAD_MODE) &
6839 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6840
6841 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6842 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6843 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6844
6845 /* WaDisableCSUnitClockGating:chv */
6846 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6847 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6848
6849 /* WaDisableSDEUnitClockGating:chv */
6850 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6851 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6852
6853 /*
6854 * GTT cache may not work with big pages, so if those
6855 * are ever enabled GTT cache may need to be disabled.
6856 */
6857 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6858}
6859
1fa61106 6860static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6861{
6862 struct drm_i915_private *dev_priv = dev->dev_private;
6863 uint32_t dspclk_gate;
6864
6865 I915_WRITE(RENCLK_GATE_D1, 0);
6866 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6867 GS_UNIT_CLOCK_GATE_DISABLE |
6868 CL_UNIT_CLOCK_GATE_DISABLE);
6869 I915_WRITE(RAMCLK_GATE_D, 0);
6870 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6871 OVRUNIT_CLOCK_GATE_DISABLE |
6872 OVCUNIT_CLOCK_GATE_DISABLE;
6873 if (IS_GM45(dev))
6874 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6875 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6876
6877 /* WaDisableRenderCachePipelinedFlush */
6878 I915_WRITE(CACHE_MODE_0,
6879 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6880
4e04632e
AG		 6881 /* WaDisable_RenderCache_OperationalFlush:g4x */
6882 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6883
0e088b8f 6884 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6885}
6886
1fa61106 6887static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6888{
6889 struct drm_i915_private *dev_priv = dev->dev_private;
6890
6891 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6892 I915_WRITE(RENCLK_GATE_D2, 0);
6893 I915_WRITE(DSPCLK_GATE_D, 0);
6894 I915_WRITE(RAMCLK_GATE_D, 0);
6895 I915_WRITE16(DEUC, 0);
20f94967
VS		 6896 I915_WRITE(MI_ARB_STATE,
6897 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6898
6899 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6900 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6901}
6902
1fa61106 6903static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6904{
6905 struct drm_i915_private *dev_priv = dev->dev_private;
6906
6907 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6908 I965_RCC_CLOCK_GATE_DISABLE |
6909 I965_RCPB_CLOCK_GATE_DISABLE |
6910 I965_ISC_CLOCK_GATE_DISABLE |
6911 I965_FBC_CLOCK_GATE_DISABLE);
6912 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6913 I915_WRITE(MI_ARB_STATE,
6914 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6915
6916 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6917 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6918}
6919
1fa61106 6920static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6921{
6922 struct drm_i915_private *dev_priv = dev->dev_private;
6923 u32 dstate = I915_READ(D_STATE);
6924
6925 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6926 DSTATE_DOT_CLOCK_GATING;
6927 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6928
6929 if (IS_PINEVIEW(dev))
6930 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6931
6932 /* IIR "flip pending" means done if this bit is set */
6933 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6934
6935 /* interrupts should cause a wake up from C3 */
3299254f 6936 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6937
6938 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6939 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6940
6941 I915_WRITE(MI_ARB_STATE,
6942 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6943}
6944
1fa61106 6945static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6946{
6947 struct drm_i915_private *dev_priv = dev->dev_private;
6948
6949 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6950
6951 /* interrupts should cause a wake up from C3 */
6952 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6953 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6954
6955 I915_WRITE(MEM_MODE,
6956 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6957}
6958
1fa61106 6959static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6960{
6961 struct drm_i915_private *dev_priv = dev->dev_private;
6962
6963 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6964
6965 I915_WRITE(MEM_MODE,
6966 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6967 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6968}
6969
6f1d69b0
ED		 6970void intel_init_clock_gating(struct drm_device *dev)
6971{
6972 struct drm_i915_private *dev_priv = dev->dev_private;
6973
c57e3551
DL		 6974 if (dev_priv->display.init_clock_gating)
6975 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6976}
6977
7d708ee4
ID		 6978void intel_suspend_hw(struct drm_device *dev)
6979{
6980 if (HAS_PCH_LPT(dev))
6981 lpt_suspend_hw(dev);
6982}
6983
1fa61106
ED		 6984/* Set up chip specific power management-related functions */
6985void intel_init_pm(struct drm_device *dev)
6986{
6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988
7ff0ebcc 6989 intel_fbc_init(dev_priv);
1fa61106 6990
c921aba8
DV		 6991 /* For cxsr */
6992 if (IS_PINEVIEW(dev))
6993 i915_pineview_get_mem_freq(dev);
6994 else if (IS_GEN5(dev))
6995 i915_ironlake_get_mem_freq(dev);
6996
1fa61106 6997 /* For FIFO watermark updates */
f5ed50cb 6998 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6999 skl_setup_wm_latency(dev);
7000
a82abe43
ID		 7001 if (IS_BROXTON(dev))
7002 dev_priv->display.init_clock_gating =
7003 bxt_init_clock_gating;
7004 else if (IS_SKYLAKE(dev))
7005 dev_priv->display.init_clock_gating =
7006 skl_init_clock_gating;
2d41c0b5 7007 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7008 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7009 ilk_setup_wm_latency(dev);
53615a5e 7010
bd602544
VS		 7011 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7012 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7013 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7014 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7015 dev_priv->display.update_wm = ilk_update_wm;
a28170f3 7016 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
bd602544
VS		 7017 } else {
7018 DRM_DEBUG_KMS("Failed to read display plane latency. "
7019 "Disable CxSR\n");
7020 }
7021
7022 if (IS_GEN5(dev))
1fa61106 7023 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7024 else if (IS_GEN6(dev))
1fa61106 7025 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7026 else if (IS_IVYBRIDGE(dev))
1fa61106 7027 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7028 else if (IS_HASWELL(dev))
cad2a2d7 7029 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7030 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7031 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7032 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7033 vlv_setup_wm_latency(dev);
7034
7035 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7036 dev_priv->display.init_clock_gating =
7037 cherryview_init_clock_gating;
1fa61106 7038 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7039 vlv_setup_wm_latency(dev);
7040
7041 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7042 dev_priv->display.init_clock_gating =
7043 valleyview_init_clock_gating;
1fa61106
ED		 7044 } else if (IS_PINEVIEW(dev)) {
7045 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7046 dev_priv->is_ddr3,
7047 dev_priv->fsb_freq,
7048 dev_priv->mem_freq)) {
7049 DRM_INFO("failed to find known CxSR latency "
7050 "(found ddr%s fsb freq %d, mem freq %d), "
7051 "disabling CxSR\n",
7052 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7053 dev_priv->fsb_freq, dev_priv->mem_freq);
7054 /* Disable CxSR and never update its watermark again */
5209b1f4 7055 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7056 dev_priv->display.update_wm = NULL;
7057 } else
7058 dev_priv->display.update_wm = pineview_update_wm;
7059 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7060 } else if (IS_G4X(dev)) {
7061 dev_priv->display.update_wm = g4x_update_wm;
7062 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7063 } else if (IS_GEN4(dev)) {
7064 dev_priv->display.update_wm = i965_update_wm;
7065 if (IS_CRESTLINE(dev))
7066 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7067 else if (IS_BROADWATER(dev))
7068 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7069 } else if (IS_GEN3(dev)) {
7070 dev_priv->display.update_wm = i9xx_update_wm;
7071 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7072 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7073 } else if (IS_GEN2(dev)) {
7074 if (INTEL_INFO(dev)->num_pipes == 1) {
7075 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7076 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7077 } else {
7078 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7079 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7080 }
7081
7082 if (IS_I85X(dev) || IS_I865G(dev))
7083 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7084 else
7085 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7086 } else {
7087 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7088 }
7089}
7090
151a49d0 7091int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7092{
4fc688ce 7093 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7094
7095 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7096 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7097 return -EAGAIN;
7098 }
7099
7100 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7101 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7102 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7103
7104 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7105 500)) {
7106 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7107 return -ETIMEDOUT;
7108 }
7109
7110 *val = I915_READ(GEN6_PCODE_DATA);
7111 I915_WRITE(GEN6_PCODE_DATA, 0);
7112
7113 return 0;
7114}
7115
151a49d0 7116int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7117{
4fc688ce 7118 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7119
7120 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7121 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7122 return -EAGAIN;
7123 }
7124
7125 I915_WRITE(GEN6_PCODE_DATA, val);
7126 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7127
7128 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7129 500)) {
7130 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7131 return -ETIMEDOUT;
7132 }
7133
7134 I915_WRITE(GEN6_PCODE_DATA, 0);
7135
7136 return 0;
7137}
a0e4e199 7138
dd06f88c 7139static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7140{
dd06f88c
VS		 7141 switch (czclk_freq) {
7142 case 200:
7143 return 10;
7144 case 267:
7145 return 12;
7146 case 320:
7147 case 333:
dd06f88c 7148 return 16;
ab3fb157
VS		 7149 case 400:
7150 return 20;
855ba3be
JB		 7151 default:
7152 return -1;
7153 }
dd06f88c 7154}
855ba3be 7155
dd06f88c
VS		 7156static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7157{
bfa7df01 7158 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7159
7160 div = vlv_gpu_freq_div(czclk_freq);
7161 if (div < 0)
7162 return div;
7163
7164 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7165}
7166
b55dd647 7167static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7168{
bfa7df01 7169 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7170
dd06f88c
VS		 7171 mul = vlv_gpu_freq_div(czclk_freq);
7172 if (mul < 0)
7173 return mul;
855ba3be 7174
dd06f88c 7175 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7176}
7177
b55dd647 7178static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7179{
bfa7df01 7180 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7181
dd06f88c
VS		 7182 div = vlv_gpu_freq_div(czclk_freq) / 2;
7183 if (div < 0)
7184 return div;
22b1b2f8 7185
dd06f88c 7186 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7187}
7188
b55dd647 7189static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7190{
bfa7df01 7191 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7192
dd06f88c
VS		 7193 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7194 if (mul < 0)
7195 return mul;
22b1b2f8 7196
1c14762d 7197 /* CHV needs even values */
dd06f88c 7198 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7199}
7200
616bc820 7201int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7202{
80b6dda4
AG		 7203 if (IS_GEN9(dev_priv->dev))
7204 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7205 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7206 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7207 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7208 return byt_gpu_freq(dev_priv, val);
7209 else
7210 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7211}
7212
616bc820
VS		 7213int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7214{
80b6dda4
AG		 7215 if (IS_GEN9(dev_priv->dev))
7216 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7217 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7218 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7219 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7220 return byt_freq_opcode(dev_priv, val);
7221 else
7222 return val / GT_FREQUENCY_MULTIPLIER;
7223}
22b1b2f8 7224
6ad790c0
CW		 7225struct request_boost {
7226 struct work_struct work;
eed29a5b 7227 struct drm_i915_gem_request *req;
6ad790c0
CW		 7228};
7229
7230static void __intel_rps_boost_work(struct work_struct *work)
7231{
7232 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7233 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7234
e61b9958
CW		 7235 if (!i915_gem_request_completed(req, true))
7236 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7237 req->emitted_jiffies);
6ad790c0 7238
e61b9958 7239 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7240 kfree(boost);
7241}
7242
7243void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7244 struct drm_i915_gem_request *req)
6ad790c0
CW		 7245{
7246 struct request_boost *boost;
7247
eed29a5b 7248 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7249 return;
7250
e61b9958
CW		 7251 if (i915_gem_request_completed(req, true))
7252 return;
7253
6ad790c0
CW		 7254 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7255 if (boost == NULL)
7256 return;
7257
eed29a5b
DV		 7258 i915_gem_request_reference(req);
7259 boost->req = req;
6ad790c0
CW		 7260
7261 INIT_WORK(&boost->work, __intel_rps_boost_work);
7262 queue_work(to_i915(dev)->wq, &boost->work);
7263}
7264
f742a552 7265void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7266{
7267 struct drm_i915_private *dev_priv = dev->dev_private;
7268
f742a552 7269 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7270 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7271
907b28c5
CW		 7272 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7273 intel_gen6_powersave_work);
1854d5ca 7274 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7275 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7276 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7277
33688d95 7278 dev_priv->pm.suspended = false;
907b28c5 7279}
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