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drm/i915: keep intel device info structs in gen based order
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
46f16e63 59static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
a82abe43 60{
b033bb6d 61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
b033bb6d
MK		 65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 67
68 /* WaEnableChickenDCPR:skl,bxt,kbl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 73 /* WaFbcWakeMemOn:skl,bxt,kbl */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 81}
82
46f16e63 83static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
b033bb6d 84{
46f16e63 85 gen9_init_clock_gating(dev_priv);
b033bb6d 86
a7546159
NH		 87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
32608ca2
ID		 91 /*
92 * FIXME:
868434c5 93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 94 */
32608ca2 95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
102 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
103 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
104 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 105}
106
148ac1f3 107static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 108{
c921aba8
DV		 109 u32 tmp;
110
111 tmp = I915_READ(CLKCFG);
112
113 switch (tmp & CLKCFG_FSB_MASK) {
114 case CLKCFG_FSB_533:
115 dev_priv->fsb_freq = 533; /* 133*4 */
116 break;
117 case CLKCFG_FSB_800:
118 dev_priv->fsb_freq = 800; /* 200*4 */
119 break;
120 case CLKCFG_FSB_667:
121 dev_priv->fsb_freq = 667; /* 167*4 */
122 break;
123 case CLKCFG_FSB_400:
124 dev_priv->fsb_freq = 400; /* 100*4 */
125 break;
126 }
127
128 switch (tmp & CLKCFG_MEM_MASK) {
129 case CLKCFG_MEM_533:
130 dev_priv->mem_freq = 533;
131 break;
132 case CLKCFG_MEM_667:
133 dev_priv->mem_freq = 667;
134 break;
135 case CLKCFG_MEM_800:
136 dev_priv->mem_freq = 800;
137 break;
138 }
139
140 /* detect pineview DDR3 setting */
141 tmp = I915_READ(CSHRDDR3CTL);
142 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
143}
144
148ac1f3 145static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 146{
c921aba8
DV		 147 u16 ddrpll, csipll;
148
149 ddrpll = I915_READ16(DDRMPLL1);
150 csipll = I915_READ16(CSIPLL0);
151
152 switch (ddrpll & 0xff) {
153 case 0xc:
154 dev_priv->mem_freq = 800;
155 break;
156 case 0x10:
157 dev_priv->mem_freq = 1066;
158 break;
159 case 0x14:
160 dev_priv->mem_freq = 1333;
161 break;
162 case 0x18:
163 dev_priv->mem_freq = 1600;
164 break;
165 default:
166 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
167 ddrpll & 0xff);
168 dev_priv->mem_freq = 0;
169 break;
170 }
171
20e4d407 172 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 173
174 switch (csipll & 0x3ff) {
175 case 0x00c:
176 dev_priv->fsb_freq = 3200;
177 break;
178 case 0x00e:
179 dev_priv->fsb_freq = 3733;
180 break;
181 case 0x010:
182 dev_priv->fsb_freq = 4266;
183 break;
184 case 0x012:
185 dev_priv->fsb_freq = 4800;
186 break;
187 case 0x014:
188 dev_priv->fsb_freq = 5333;
189 break;
190 case 0x016:
191 dev_priv->fsb_freq = 5866;
192 break;
193 case 0x018:
194 dev_priv->fsb_freq = 6400;
195 break;
196 default:
197 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
198 csipll & 0x3ff);
199 dev_priv->fsb_freq = 0;
200 break;
201 }
202
203 if (dev_priv->fsb_freq == 3200) {
20e4d407 204 dev_priv->ips.c_m = 0;
c921aba8 205 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 206 dev_priv->ips.c_m = 1;
c921aba8 207 } else {
20e4d407 208 dev_priv->ips.c_m = 2;
c921aba8
DV		 209 }
210}
211
b445e3b0
ED		 212static const struct cxsr_latency cxsr_latency_table[] = {
213 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
214 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
215 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
216 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
217 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
218
219 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
220 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
221 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
222 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
223 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
224
225 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
226 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
227 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
228 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
229 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
230
231 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
232 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
233 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
234 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
235 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
236
237 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
238 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
239 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
240 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
241 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
242
243 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
244 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
245 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
246 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
247 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
248};
249
44a655ca
TU		 250static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
251 bool is_ddr3,
b445e3b0
ED		 252 int fsb,
253 int mem)
254{
255 const struct cxsr_latency *latency;
256 int i;
257
258 if (fsb == 0 || mem == 0)
259 return NULL;
260
261 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
262 latency = &cxsr_latency_table[i];
263 if (is_desktop == latency->is_desktop &&
264 is_ddr3 == latency->is_ddr3 &&
265 fsb == latency->fsb_freq && mem == latency->mem_freq)
266 return latency;
267 }
268
269 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
270
271 return NULL;
272}
273
fc1ac8de
VS		 274static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
275{
276 u32 val;
277
278 mutex_lock(&dev_priv->rps.hw_lock);
279
280 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
281 if (enable)
282 val &= ~FORCE_DDR_HIGH_FREQ;
283 else
284 val |= FORCE_DDR_HIGH_FREQ;
285 val &= ~FORCE_DDR_LOW_FREQ;
286 val |= FORCE_DDR_FREQ_REQ_ACK;
287 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
288
289 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
290 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
291 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
292
293 mutex_unlock(&dev_priv->rps.hw_lock);
294}
295
cfb41411
VS		 296static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
297{
298 u32 val;
299
300 mutex_lock(&dev_priv->rps.hw_lock);
301
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
303 if (enable)
304 val |= DSP_MAXFIFO_PM5_ENABLE;
305 else
306 val &= ~DSP_MAXFIFO_PM5_ENABLE;
307 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
308
309 mutex_unlock(&dev_priv->rps.hw_lock);
310}
311
f4998963
VS		 312#define FW_WM(value, plane) \
313 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
314
11a85d6a 315static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 316{
11a85d6a 317 bool was_enabled;
5209b1f4 318 u32 val;
b445e3b0 319
920a14b2 320 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
11a85d6a 321 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
5209b1f4 322 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 323 POSTING_READ(FW_BLC_SELF_VLV);
9beb5fea 324 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
11a85d6a 325 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5209b1f4 326 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF);
9b1e14f4 328 } else if (IS_PINEVIEW(dev_priv)) {
11a85d6a
VS		 329 val = I915_READ(DSPFW3);
330 was_enabled = val & PINEVIEW_SELF_REFRESH_EN;
331 if (enable)
332 val |= PINEVIEW_SELF_REFRESH_EN;
333 else
334 val &= ~PINEVIEW_SELF_REFRESH_EN;
5209b1f4 335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
50a0bc90 337 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
11a85d6a 338 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
5209b1f4
ID		 339 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
340 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
341 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 342 POSTING_READ(FW_BLC_SELF);
50a0bc90 343 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 344 /*
345 * FIXME can't find a bit like this for 915G, and
346 * and yet it does have the related watermark in
347 * FW_BLC_SELF. What's going on?
348 */
11a85d6a 349 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
5209b1f4
ID		 350 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
351 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
352 I915_WRITE(INSTPM, val);
a7a6c498 353 POSTING_READ(INSTPM);
5209b1f4 354 } else {
11a85d6a 355 return false;
5209b1f4 356 }
b445e3b0 357
11a85d6a
VS		 358 DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n",
359 enableddisabled(enable),
360 enableddisabled(was_enabled));
361
362 return was_enabled;
b445e3b0
ED		 363}
364
11a85d6a 365bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
3d90e649 366{
11a85d6a
VS		 367 bool ret;
368
3d90e649 369 mutex_lock(&dev_priv->wm.wm_mutex);
11a85d6a 370 ret = _intel_set_memory_cxsr(dev_priv, enable);
3d90e649
VS		 371 dev_priv->wm.vlv.cxsr = enable;
372 mutex_unlock(&dev_priv->wm.wm_mutex);
11a85d6a
VS		 373
374 return ret;
3d90e649 375}
fc1ac8de 376
b445e3b0
ED		 377/*
378 * Latency for FIFO fetches is dependent on several factors:
379 * - memory configuration (speed, channels)
380 * - chipset
381 * - current MCH state
382 * It can be fairly high in some situations, so here we assume a fairly
383 * pessimal value. It's a tradeoff between extra memory fetches (if we
384 * set this value too high, the FIFO will fetch frequently to stay full)
385 * and power consumption (set it too low to save power and we might see
386 * FIFO underruns and display "flicker").
387 *
388 * A value of 5us seems to be a good balance; safe for very low end
389 * platforms but not overly aggressive on lower latency configs.
390 */
5aef6003 391static const int pessimal_latency_ns = 5000;
b445e3b0 392
b5004720
VS		 393#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
394 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
395
49845a23 396static int vlv_get_fifo_size(struct intel_plane *plane)
b5004720 397{
49845a23 398 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
b5004720
VS		 399 int sprite0_start, sprite1_start, size;
400
49845a23
VS		 401 if (plane->id == PLANE_CURSOR)
402 return 63;
403
404 switch (plane->pipe) {
b5004720
VS		 405 uint32_t dsparb, dsparb2, dsparb3;
406 case PIPE_A:
407 dsparb = I915_READ(DSPARB);
408 dsparb2 = I915_READ(DSPARB2);
409 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
410 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
411 break;
412 case PIPE_B:
413 dsparb = I915_READ(DSPARB);
414 dsparb2 = I915_READ(DSPARB2);
415 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
416 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
417 break;
418 case PIPE_C:
419 dsparb2 = I915_READ(DSPARB2);
420 dsparb3 = I915_READ(DSPARB3);
421 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
422 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
423 break;
424 default:
425 return 0;
426 }
427
49845a23
VS		 428 switch (plane->id) {
429 case PLANE_PRIMARY:
b5004720
VS		 430 size = sprite0_start;
431 break;
49845a23 432 case PLANE_SPRITE0:
b5004720
VS		 433 size = sprite1_start - sprite0_start;
434 break;
49845a23 435 case PLANE_SPRITE1:
b5004720
VS		 436 size = 512 - 1 - sprite1_start;
437 break;
438 default:
439 return 0;
440 }
441
49845a23 442 DRM_DEBUG_KMS("%s FIFO size: %d\n", plane->base.name, size);
b5004720
VS		 443
444 return size;
445}
446
ef0f5e93 447static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 448{
b445e3b0
ED		 449 uint32_t dsparb = I915_READ(DSPARB);
450 int size;
451
452 size = dsparb & 0x7f;
453 if (plane)
454 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
455
456 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
457 plane ? "B" : "A", size);
458
459 return size;
460}
461
ef0f5e93 462static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 463{
b445e3b0
ED		 464 uint32_t dsparb = I915_READ(DSPARB);
465 int size;
466
467 size = dsparb & 0x1ff;
468 if (plane)
469 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
470 size >>= 1; /* Convert to cachelines */
471
472 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
473 plane ? "B" : "A", size);
474
475 return size;
476}
477
ef0f5e93 478static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 479{
b445e3b0
ED		 480 uint32_t dsparb = I915_READ(DSPARB);
481 int size;
482
483 size = dsparb & 0x7f;
484 size >>= 2; /* Convert to cachelines */
485
486 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
487 plane ? "B" : "A",
488 size);
489
490 return size;
491}
492
b445e3b0
ED		 493/* Pineview has different values for various configs */
494static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 495 .fifo_size = PINEVIEW_DISPLAY_FIFO,
496 .max_wm = PINEVIEW_MAX_WM,
497 .default_wm = PINEVIEW_DFT_WM,
498 .guard_size = PINEVIEW_GUARD_WM,
499 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 500};
501static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 502 .fifo_size = PINEVIEW_DISPLAY_FIFO,
503 .max_wm = PINEVIEW_MAX_WM,
504 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
505 .guard_size = PINEVIEW_GUARD_WM,
506 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 507};
508static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 509 .fifo_size = PINEVIEW_CURSOR_FIFO,
510 .max_wm = PINEVIEW_CURSOR_MAX_WM,
511 .default_wm = PINEVIEW_CURSOR_DFT_WM,
512 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
513 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 514};
515static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 516 .fifo_size = PINEVIEW_CURSOR_FIFO,
517 .max_wm = PINEVIEW_CURSOR_MAX_WM,
518 .default_wm = PINEVIEW_CURSOR_DFT_WM,
519 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
520 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 521};
522static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 523 .fifo_size = G4X_FIFO_SIZE,
524 .max_wm = G4X_MAX_WM,
525 .default_wm = G4X_MAX_WM,
526 .guard_size = 2,
527 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 528};
529static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 530 .fifo_size = I965_CURSOR_FIFO,
531 .max_wm = I965_CURSOR_MAX_WM,
532 .default_wm = I965_CURSOR_DFT_WM,
533 .guard_size = 2,
534 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 535};
b445e3b0 536static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 537 .fifo_size = I965_CURSOR_FIFO,
538 .max_wm = I965_CURSOR_MAX_WM,
539 .default_wm = I965_CURSOR_DFT_WM,
540 .guard_size = 2,
541 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 542};
543static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 544 .fifo_size = I945_FIFO_SIZE,
545 .max_wm = I915_MAX_WM,
546 .default_wm = 1,
547 .guard_size = 2,
548 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 549};
550static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 551 .fifo_size = I915_FIFO_SIZE,
552 .max_wm = I915_MAX_WM,
553 .default_wm = 1,
554 .guard_size = 2,
555 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 556};
9d539105 557static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 558 .fifo_size = I855GM_FIFO_SIZE,
559 .max_wm = I915_MAX_WM,
560 .default_wm = 1,
561 .guard_size = 2,
562 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 563};
9d539105
VS		 564static const struct intel_watermark_params i830_bc_wm_info = {
565 .fifo_size = I855GM_FIFO_SIZE,
566 .max_wm = I915_MAX_WM/2,
567 .default_wm = 1,
568 .guard_size = 2,
569 .cacheline_size = I830_FIFO_LINE_SIZE,
570};
feb56b93 571static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 572 .fifo_size = I830_FIFO_SIZE,
573 .max_wm = I915_MAX_WM,
574 .default_wm = 1,
575 .guard_size = 2,
576 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 577};
578
b445e3b0
ED		 579/**
580 * intel_calculate_wm - calculate watermark level
581 * @clock_in_khz: pixel clock
582 * @wm: chip FIFO params
ac484963 583 * @cpp: bytes per pixel
b445e3b0
ED		 584 * @latency_ns: memory latency for the platform
585 *
586 * Calculate the watermark level (the level at which the display plane will
587 * start fetching from memory again). Each chip has a different display
588 * FIFO size and allocation, so the caller needs to figure that out and pass
589 * in the correct intel_watermark_params structure.
590 *
591 * As the pixel clock runs, the FIFO will be drained at a rate that depends
592 * on the pixel size. When it reaches the watermark level, it'll start
593 * fetching FIFO line sized based chunks from memory until the FIFO fills
594 * past the watermark point. If the FIFO drains completely, a FIFO underrun
595 * will occur, and a display engine hang could result.
596 */
597static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
598 const struct intel_watermark_params *wm,
ac484963 599 int fifo_size, int cpp,
b445e3b0
ED		 600 unsigned long latency_ns)
601{
602 long entries_required, wm_size;
603
604 /*
605 * Note: we need to make sure we don't overflow for various clock &
606 * latency values.
607 * clocks go from a few thousand to several hundred thousand.
608 * latency is usually a few thousand
609 */
ac484963 610 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 611 1000;
612 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
613
614 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
615
616 wm_size = fifo_size - (entries_required + wm->guard_size);
617
618 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
619
620 /* Don't promote wm_size to unsigned... */
621 if (wm_size > (long)wm->max_wm)
622 wm_size = wm->max_wm;
623 if (wm_size <= 0)
624 wm_size = wm->default_wm;
d6feb196
VS		 625
626 /*
627 * Bspec seems to indicate that the value shouldn't be lower than
628 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
629 * Lets go for 8 which is the burst size since certain platforms
630 * already use a hardcoded 8 (which is what the spec says should be
631 * done).
632 */
633 if (wm_size <= 8)
634 wm_size = 8;
635
b445e3b0
ED		 636 return wm_size;
637}
638
ffc7a76b 639static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
b445e3b0 640{
efc2611e 641 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 642
ffc7a76b 643 for_each_intel_crtc(&dev_priv->drm, crtc) {
efc2611e 644 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 645 if (enabled)
646 return NULL;
647 enabled = crtc;
648 }
649 }
650
651 return enabled;
652}
653
432081bc 654static void pineview_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 655{
ffc7a76b 656 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 657 struct intel_crtc *crtc;
b445e3b0
ED		 658 const struct cxsr_latency *latency;
659 u32 reg;
660 unsigned long wm;
661
50a0bc90
TU		 662 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
663 dev_priv->is_ddr3,
664 dev_priv->fsb_freq,
665 dev_priv->mem_freq);
b445e3b0
ED		 666 if (!latency) {
667 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 668 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 669 return;
670 }
671
ffc7a76b 672 crtc = single_enabled_crtc(dev_priv);
b445e3b0 673 if (crtc) {
efc2611e
VS		 674 const struct drm_display_mode *adjusted_mode =
675 &crtc->config->base.adjusted_mode;
676 const struct drm_framebuffer *fb =
677 crtc->base.primary->state->fb;
678 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
7c5f93b0 679 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 680
681 /* Display SR */
682 wm = intel_calculate_wm(clock, &pineview_display_wm,
683 pineview_display_wm.fifo_size,
ac484963 684 cpp, latency->display_sr);
b445e3b0
ED		 685 reg = I915_READ(DSPFW1);
686 reg &= ~DSPFW_SR_MASK;
f4998963 687 reg |= FW_WM(wm, SR);
b445e3b0
ED		 688 I915_WRITE(DSPFW1, reg);
689 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
690
691 /* cursor SR */
692 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
693 pineview_display_wm.fifo_size,
ac484963 694 cpp, latency->cursor_sr);
b445e3b0
ED		 695 reg = I915_READ(DSPFW3);
696 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 697 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 698 I915_WRITE(DSPFW3, reg);
699
700 /* Display HPLL off SR */
701 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
702 pineview_display_hplloff_wm.fifo_size,
ac484963 703 cpp, latency->display_hpll_disable);
b445e3b0
ED		 704 reg = I915_READ(DSPFW3);
705 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 706 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 707 I915_WRITE(DSPFW3, reg);
708
709 /* cursor HPLL off SR */
710 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
711 pineview_display_hplloff_wm.fifo_size,
ac484963 712 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 713 reg = I915_READ(DSPFW3);
714 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 715 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 716 I915_WRITE(DSPFW3, reg);
717 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
718
5209b1f4 719 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 720 } else {
5209b1f4 721 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 722 }
723}
724
f0ce2310 725static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
b445e3b0
ED		 726 int plane,
727 const struct intel_watermark_params *display,
728 int display_latency_ns,
729 const struct intel_watermark_params *cursor,
730 int cursor_latency_ns,
731 int *plane_wm,
732 int *cursor_wm)
733{
efc2611e 734 struct intel_crtc *crtc;
4fe8590a 735 const struct drm_display_mode *adjusted_mode;
efc2611e 736 const struct drm_framebuffer *fb;
ac484963 737 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 738 int line_time_us, line_count;
739 int entries, tlb_miss;
740
b91eb5cc 741 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e 742 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 743 *cursor_wm = cursor->guard_size;
744 *plane_wm = display->guard_size;
745 return false;
746 }
747
efc2611e
VS		 748 adjusted_mode = &crtc->config->base.adjusted_mode;
749 fb = crtc->base.primary->state->fb;
241bfc38 750 clock = adjusted_mode->crtc_clock;
fec8cba3 751 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 752 hdisplay = crtc->config->pipe_src_w;
753 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 754
755 /* Use the small buffer method to calculate plane watermark */
ac484963 756 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 757 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
758 if (tlb_miss > 0)
759 entries += tlb_miss;
760 entries = DIV_ROUND_UP(entries, display->cacheline_size);
761 *plane_wm = entries + display->guard_size;
762 if (*plane_wm > (int)display->max_wm)
763 *plane_wm = display->max_wm;
764
765 /* Use the large buffer method to calculate cursor watermark */
922044c9 766 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 767 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
efc2611e 768 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
b445e3b0
ED		 769 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
770 if (tlb_miss > 0)
771 entries += tlb_miss;
772 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
773 *cursor_wm = entries + cursor->guard_size;
774 if (*cursor_wm > (int)cursor->max_wm)
775 *cursor_wm = (int)cursor->max_wm;
776
777 return true;
778}
779
780/*
781 * Check the wm result.
782 *
783 * If any calculated watermark values is larger than the maximum value that
784 * can be programmed into the associated watermark register, that watermark
785 * must be disabled.
786 */
f0ce2310 787static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 788 int display_wm, int cursor_wm,
789 const struct intel_watermark_params *display,
790 const struct intel_watermark_params *cursor)
791{
792 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
793 display_wm, cursor_wm);
794
795 if (display_wm > display->max_wm) {
ae9400ca 796 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 797 display_wm, display->max_wm);
798 return false;
799 }
800
801 if (cursor_wm > cursor->max_wm) {
ae9400ca 802 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 803 cursor_wm, cursor->max_wm);
804 return false;
805 }
806
807 if (!(display_wm || cursor_wm)) {
808 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
809 return false;
810 }
811
812 return true;
813}
814
f0ce2310 815static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 816 int plane,
817 int latency_ns,
818 const struct intel_watermark_params *display,
819 const struct intel_watermark_params *cursor,
820 int *display_wm, int *cursor_wm)
821{
efc2611e 822 struct intel_crtc *crtc;
4fe8590a 823 const struct drm_display_mode *adjusted_mode;
efc2611e 824 const struct drm_framebuffer *fb;
ac484963 825 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 826 unsigned long line_time_us;
827 int line_count, line_size;
828 int small, large;
829 int entries;
830
831 if (!latency_ns) {
832 *display_wm = *cursor_wm = 0;
833 return false;
834 }
835
b91eb5cc 836 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e
VS		 837 adjusted_mode = &crtc->config->base.adjusted_mode;
838 fb = crtc->base.primary->state->fb;
241bfc38 839 clock = adjusted_mode->crtc_clock;
fec8cba3 840 htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 841 hdisplay = crtc->config->pipe_src_w;
842 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0 843
922044c9 844 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 845 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 846 line_size = hdisplay * cpp;
b445e3b0
ED		 847
848 /* Use the minimum of the small and large buffer method for primary */
ac484963 849 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 850 large = line_count * line_size;
851
852 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
853 *display_wm = entries + display->guard_size;
854
855 /* calculate the self-refresh watermark for display cursor */
efc2611e 856 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 857 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
858 *cursor_wm = entries + cursor->guard_size;
859
f0ce2310 860 return g4x_check_srwm(dev_priv,
b445e3b0
ED		 861 *display_wm, *cursor_wm,
862 display, cursor);
863}
864
15665979
VS		 865#define FW_WM_VLV(value, plane) \
866 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
867
50f4caef 868static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
0018fda1
VS		 869 const struct vlv_wm_values *wm)
870{
50f4caef
VS		 871 enum pipe pipe;
872
873 for_each_pipe(dev_priv, pipe) {
874 I915_WRITE(VLV_DDL(pipe),
875 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
876 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
877 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
878 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
879 }
0018fda1 880
6fe6a7ff
VS		 881 /*
882 * Zero the (unused) WM1 watermarks, and also clear all the
883 * high order bits so that there are no out of bounds values
884 * present in the registers during the reprogramming.
885 */
886 I915_WRITE(DSPHOWM, 0);
887 I915_WRITE(DSPHOWM1, 0);
888 I915_WRITE(DSPFW4, 0);
889 I915_WRITE(DSPFW5, 0);
890 I915_WRITE(DSPFW6, 0);
891
ae80152d 892 I915_WRITE(DSPFW1,
15665979 893 FW_WM(wm->sr.plane, SR) |
1b31389c
VS		 894 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
895 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
896 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
ae80152d 897 I915_WRITE(DSPFW2,
1b31389c
VS		 898 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
899 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
900 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
ae80152d 901 I915_WRITE(DSPFW3,
15665979 902 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 903
904 if (IS_CHERRYVIEW(dev_priv)) {
905 I915_WRITE(DSPFW7_CHV,
1b31389c
VS		 906 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
907 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
ae80152d 908 I915_WRITE(DSPFW8_CHV,
1b31389c
VS		 909 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
910 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
ae80152d 911 I915_WRITE(DSPFW9_CHV,
1b31389c
VS		 912 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
913 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
ae80152d 914 I915_WRITE(DSPHOWM,
15665979 915 FW_WM(wm->sr.plane >> 9, SR_HI) |
1b31389c
VS		 916 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
917 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
918 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
919 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
920 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
921 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
922 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
923 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
924 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
ae80152d
VS		 925 } else {
926 I915_WRITE(DSPFW7,
1b31389c
VS		 927 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
928 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
ae80152d 929 I915_WRITE(DSPHOWM,
15665979 930 FW_WM(wm->sr.plane >> 9, SR_HI) |
1b31389c
VS		 931 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
932 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
933 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
934 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
935 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
936 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
ae80152d
VS		 937 }
938
939 POSTING_READ(DSPFW1);
0018fda1
VS		 940}
941
15665979
VS		 942#undef FW_WM_VLV
943
6eb1a681
VS		 944enum vlv_wm_level {
945 VLV_WM_LEVEL_PM2,
946 VLV_WM_LEVEL_PM5,
947 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 948};
949
262cd2e1
VS		 950/* latency must be in 0.1us units. */
951static unsigned int vlv_wm_method2(unsigned int pixel_rate,
952 unsigned int pipe_htotal,
953 unsigned int horiz_pixels,
ac484963 954 unsigned int cpp,
262cd2e1
VS		 955 unsigned int latency)
956{
957 unsigned int ret;
958
959 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 960 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 961 ret = DIV_ROUND_UP(ret, 64);
962
963 return ret;
964}
965
bb726519 966static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
262cd2e1 967{
262cd2e1
VS		 968 /* all latencies in usec */
969 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
970
58590c14
VS		 971 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
972
262cd2e1
VS		 973 if (IS_CHERRYVIEW(dev_priv)) {
974 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
975 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 976
977 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 978 }
979}
980
e339d67e
VS		 981static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
982 const struct intel_plane_state *plane_state,
262cd2e1
VS		 983 int level)
984{
e339d67e 985 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
262cd2e1 986 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
e339d67e
VS		 987 const struct drm_display_mode *adjusted_mode =
988 &crtc_state->base.adjusted_mode;
ac484963 989 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 990
991 if (dev_priv->wm.pri_latency[level] == 0)
992 return USHRT_MAX;
993
e339d67e 994 if (!plane_state->base.visible)
262cd2e1
VS		 995 return 0;
996
e339d67e
VS		 997 cpp = drm_format_plane_cpp(plane_state->base.fb->pixel_format, 0);
998 clock = adjusted_mode->crtc_clock;
999 htotal = adjusted_mode->crtc_htotal;
1000 width = crtc_state->pipe_src_w;
262cd2e1
VS		 1001 if (WARN_ON(htotal == 0))
1002 htotal = 1;
1003
1004 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1005 /*
1006 * FIXME the formula gives values that are
1007 * too big for the cursor FIFO, and hence we
1008 * would never be able to use cursors. For
1009 * now just hardcode the watermark.
1010 */
1011 wm = 63;
1012 } else {
ac484963 1013 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 1014 dev_priv->wm.pri_latency[level] * 10);
1015 }
1016
1017 return min_t(int, wm, USHRT_MAX);
1018}
1019
54f1b6e1
VS		 1020static void vlv_compute_fifo(struct intel_crtc *crtc)
1021{
1022 struct drm_device *dev = crtc->base.dev;
1023 struct vlv_wm_state *wm_state = &crtc->wm_state;
1024 struct intel_plane *plane;
1025 unsigned int total_rate = 0;
1026 const int fifo_size = 512 - 1;
1027 int fifo_extra, fifo_left = fifo_size;
1028
1029 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1030 struct intel_plane_state *state =
1031 to_intel_plane_state(plane->base.state);
1032
1033 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1034 continue;
1035
936e71e3 1036 if (state->base.visible) {
54f1b6e1
VS		 1037 wm_state->num_active_planes++;
1038 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1039 }
1040 }
1041
1042 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1043 struct intel_plane_state *state =
1044 to_intel_plane_state(plane->base.state);
1045 unsigned int rate;
1046
1047 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1048 plane->wm.fifo_size = 63;
1049 continue;
1050 }
1051
936e71e3 1052 if (!state->base.visible) {
54f1b6e1
VS		 1053 plane->wm.fifo_size = 0;
1054 continue;
1055 }
1056
1057 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1058 plane->wm.fifo_size = fifo_size * rate / total_rate;
1059 fifo_left -= plane->wm.fifo_size;
1060 }
1061
1062 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1063
1064 /* spread the remainder evenly */
1065 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1066 int plane_extra;
1067
1068 if (fifo_left == 0)
1069 break;
1070
1071 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1072 continue;
1073
1074 /* give it all to the first plane if none are active */
1075 if (plane->wm.fifo_size == 0 &&
1076 wm_state->num_active_planes)
1077 continue;
1078
1079 plane_extra = min(fifo_extra, fifo_left);
1080 plane->wm.fifo_size += plane_extra;
1081 fifo_left -= plane_extra;
1082 }
1083
1084 WARN_ON(fifo_left != 0);
1085}
1086
26cca0e5
VS		 1087static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1088{
1089 if (wm > fifo_size)
1090 return USHRT_MAX;
1091 else
1092 return fifo_size - wm;
1093}
1094
262cd2e1
VS		 1095static void vlv_invert_wms(struct intel_crtc *crtc)
1096{
1097 struct vlv_wm_state *wm_state = &crtc->wm_state;
1098 int level;
1099
1100 for (level = 0; level < wm_state->num_levels; level++) {
7c951c00 1101 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b7f05d4a 1102 const int sr_fifo_size =
7c951c00 1103 INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
262cd2e1
VS		 1104 struct intel_plane *plane;
1105
26cca0e5
VS		 1106 wm_state->sr[level].plane =
1107 vlv_invert_wm_value(wm_state->sr[level].plane,
1108 sr_fifo_size);
1109 wm_state->sr[level].cursor =
1110 vlv_invert_wm_value(wm_state->sr[level].cursor,
1111 63);
262cd2e1 1112
7c951c00 1113 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
26cca0e5
VS		 1114 wm_state->wm[level].plane[plane->id] =
1115 vlv_invert_wm_value(wm_state->wm[level].plane[plane->id],
1116 plane->wm.fifo_size);
262cd2e1
VS		 1117 }
1118 }
1119}
1120
26e1fe4f 1121static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1 1122{
7c951c00 1123 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
262cd2e1
VS		 1124 struct vlv_wm_state *wm_state = &crtc->wm_state;
1125 struct intel_plane *plane;
262cd2e1
VS		 1126 int level;
1127
1128 memset(wm_state, 0, sizeof(*wm_state));
1129
852eb00d 1130 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
b7f05d4a 1131 wm_state->num_levels = dev_priv->wm.max_level + 1;
262cd2e1
VS		 1132
1133 wm_state->num_active_planes = 0;
262cd2e1 1134
54f1b6e1 1135 vlv_compute_fifo(crtc);
262cd2e1
VS		 1136
1137 if (wm_state->num_active_planes != 1)
1138 wm_state->cxsr = false;
1139
7c951c00 1140 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
262cd2e1
VS		 1141 struct intel_plane_state *state =
1142 to_intel_plane_state(plane->base.state);
1b31389c 1143 int level;
262cd2e1 1144
936e71e3 1145 if (!state->base.visible)
262cd2e1
VS		 1146 continue;
1147
1148 /* normal watermarks */
1149 for (level = 0; level < wm_state->num_levels; level++) {
e339d67e 1150 int wm = vlv_compute_wm_level(crtc->config, state, level);
1be4d379 1151 int max_wm = plane->wm.fifo_size;
262cd2e1
VS		 1152
1153 /* hack */
1154 if (WARN_ON(level == 0 && wm > max_wm))
1155 wm = max_wm;
1156
1be4d379 1157 if (wm > max_wm)
262cd2e1
VS		 1158 break;
1159
1b31389c 1160 wm_state->wm[level].plane[plane->id] = wm;
262cd2e1
VS		 1161 }
1162
1163 wm_state->num_levels = level;
1164
1165 if (!wm_state->cxsr)
1166 continue;
1167
1168 /* maxfifo watermarks */
1b31389c 1169 if (plane->id == PLANE_CURSOR) {
262cd2e1
VS		 1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].cursor =
1b31389c
VS		 1172 wm_state->wm[level].plane[PLANE_CURSOR];
1173 } else {
262cd2e1
VS		 1174 for (level = 0; level < wm_state->num_levels; level++)
1175 wm_state->sr[level].plane =
50a9dd3f 1176 max(wm_state->sr[level].plane,
1b31389c 1177 wm_state->wm[level].plane[plane->id]);
262cd2e1
VS		 1178 }
1179 }
1180
1181 /* clear any (partially) filled invalid levels */
b7f05d4a 1182 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
262cd2e1
VS		 1183 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1184 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1185 }
1186
1187 vlv_invert_wms(crtc);
1188}
1189
54f1b6e1
VS		 1190#define VLV_FIFO(plane, value) \
1191 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1192
1193static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1194{
1195 struct drm_device *dev = crtc->base.dev;
1196 struct drm_i915_private *dev_priv = to_i915(dev);
1197 struct intel_plane *plane;
1198 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1199
1200 for_each_intel_plane_on_crtc(dev, crtc, plane) {
49845a23
VS		 1201 switch (plane->id) {
1202 case PLANE_PRIMARY:
54f1b6e1 1203 sprite0_start = plane->wm.fifo_size;
49845a23
VS		 1204 break;
1205 case PLANE_SPRITE0:
54f1b6e1 1206 sprite1_start = sprite0_start + plane->wm.fifo_size;
49845a23
VS		 1207 break;
1208 case PLANE_SPRITE1:
54f1b6e1 1209 fifo_size = sprite1_start + plane->wm.fifo_size;
49845a23
VS		 1210 break;
1211 case PLANE_CURSOR:
1212 WARN_ON(plane->wm.fifo_size != 63);
1213 break;
1214 default:
1215 MISSING_CASE(plane->id);
1216 break;
1217 }
54f1b6e1
VS		 1218 }
1219
1220 WARN_ON(fifo_size != 512 - 1);
1221
1222 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223 pipe_name(crtc->pipe), sprite0_start,
1224 sprite1_start, fifo_size);
1225
1226 switch (crtc->pipe) {
1227 uint32_t dsparb, dsparb2, dsparb3;
1228 case PIPE_A:
1229 dsparb = I915_READ(DSPARB);
1230 dsparb2 = I915_READ(DSPARB2);
1231
1232 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1233 VLV_FIFO(SPRITEB, 0xff));
1234 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1235 VLV_FIFO(SPRITEB, sprite1_start));
1236
1237 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1238 VLV_FIFO(SPRITEB_HI, 0x1));
1239 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1240 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1241
1242 I915_WRITE(DSPARB, dsparb);
1243 I915_WRITE(DSPARB2, dsparb2);
1244 break;
1245 case PIPE_B:
1246 dsparb = I915_READ(DSPARB);
1247 dsparb2 = I915_READ(DSPARB2);
1248
1249 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1250 VLV_FIFO(SPRITED, 0xff));
1251 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1252 VLV_FIFO(SPRITED, sprite1_start));
1253
1254 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1255 VLV_FIFO(SPRITED_HI, 0xff));
1256 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1257 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1258
1259 I915_WRITE(DSPARB, dsparb);
1260 I915_WRITE(DSPARB2, dsparb2);
1261 break;
1262 case PIPE_C:
1263 dsparb3 = I915_READ(DSPARB3);
1264 dsparb2 = I915_READ(DSPARB2);
1265
1266 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1267 VLV_FIFO(SPRITEF, 0xff));
1268 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1269 VLV_FIFO(SPRITEF, sprite1_start));
1270
1271 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1272 VLV_FIFO(SPRITEF_HI, 0xff));
1273 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1274 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1275
1276 I915_WRITE(DSPARB3, dsparb3);
1277 I915_WRITE(DSPARB2, dsparb2);
1278 break;
1279 default:
1280 break;
1281 }
1282}
1283
1284#undef VLV_FIFO
1285
7c951c00 1286static void vlv_merge_wm(struct drm_i915_private *dev_priv,
262cd2e1
VS		 1287 struct vlv_wm_values *wm)
1288{
1289 struct intel_crtc *crtc;
1290 int num_active_crtcs = 0;
1291
7c951c00 1292 wm->level = dev_priv->wm.max_level;
262cd2e1
VS		 1293 wm->cxsr = true;
1294
7c951c00 1295 for_each_intel_crtc(&dev_priv->drm, crtc) {
262cd2e1
VS		 1296 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1297
1298 if (!crtc->active)
1299 continue;
1300
1301 if (!wm_state->cxsr)
1302 wm->cxsr = false;
1303
1304 num_active_crtcs++;
1305 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1306 }
1307
1308 if (num_active_crtcs != 1)
1309 wm->cxsr = false;
1310
6f9c784b
VS		 1311 if (num_active_crtcs > 1)
1312 wm->level = VLV_WM_LEVEL_PM2;
1313
7c951c00 1314 for_each_intel_crtc(&dev_priv->drm, crtc) {
262cd2e1
VS		 1315 struct vlv_wm_state *wm_state = &crtc->wm_state;
1316 enum pipe pipe = crtc->pipe;
1317
1318 if (!crtc->active)
1319 continue;
1320
1321 wm->pipe[pipe] = wm_state->wm[wm->level];
1322 if (wm->cxsr)
1323 wm->sr = wm_state->sr[wm->level];
1324
1b31389c
VS		 1325 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
1327 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
1328 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
262cd2e1
VS		 1329 }
1330}
1331
fa292a4b
VS		 1332static bool is_disabling(int old, int new, int threshold)
1333{
1334 return old >= threshold && new < threshold;
1335}
1336
1337static bool is_enabling(int old, int new, int threshold)
1338{
1339 return old < threshold && new >= threshold;
1340}
1341
432081bc 1342static void vlv_update_wm(struct intel_crtc *crtc)
262cd2e1 1343{
7c951c00 1344 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
432081bc 1345 enum pipe pipe = crtc->pipe;
fa292a4b
VS		 1346 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
1347 struct vlv_wm_values new_wm = {};
262cd2e1 1348
432081bc 1349 vlv_compute_wm(crtc);
fa292a4b 1350 vlv_merge_wm(dev_priv, &new_wm);
262cd2e1 1351
fa292a4b 1352 if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) {
54f1b6e1 1353 /* FIXME should be part of crtc atomic commit */
432081bc 1354 vlv_pipe_set_fifo_size(crtc);
fa292a4b 1355
262cd2e1 1356 return;
54f1b6e1 1357 }
262cd2e1 1358
fa292a4b 1359 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
262cd2e1
VS		 1360 chv_set_memory_dvfs(dev_priv, false);
1361
fa292a4b 1362 if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
262cd2e1
VS		 1363 chv_set_memory_pm5(dev_priv, false);
1364
fa292a4b 1365 if (is_disabling(old_wm->cxsr, new_wm.cxsr, true))
3d90e649 1366 _intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1367
54f1b6e1 1368 /* FIXME should be part of crtc atomic commit */
432081bc 1369 vlv_pipe_set_fifo_size(crtc);
54f1b6e1 1370
fa292a4b 1371 vlv_write_wm_values(dev_priv, &new_wm);
262cd2e1
VS		 1372
1373 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1374 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
fa292a4b
VS		 1375 pipe_name(pipe), new_wm.pipe[pipe].plane[PLANE_PRIMARY], new_wm.pipe[pipe].plane[PLANE_CURSOR],
1376 new_wm.pipe[pipe].plane[PLANE_SPRITE0], new_wm.pipe[pipe].plane[PLANE_SPRITE1],
1377 new_wm.sr.plane, new_wm.sr.cursor, new_wm.level, new_wm.cxsr);
262cd2e1 1378
fa292a4b 1379 if (is_enabling(old_wm->cxsr, new_wm.cxsr, true))
3d90e649 1380 _intel_set_memory_cxsr(dev_priv, true);
262cd2e1 1381
fa292a4b 1382 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5))
262cd2e1
VS		 1383 chv_set_memory_pm5(dev_priv, true);
1384
fa292a4b 1385 if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS))
262cd2e1
VS		 1386 chv_set_memory_dvfs(dev_priv, true);
1387
fa292a4b 1388 *old_wm = new_wm;
3c2777fd
VS		 1389}
1390
ae80152d
VS		 1391#define single_plane_enabled(mask) is_power_of_2(mask)
1392
432081bc 1393static void g4x_update_wm(struct intel_crtc *crtc)
b445e3b0 1394{
b91eb5cc 1395 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0 1396 static const int sr_latency_ns = 12000;
b445e3b0
ED		 1397 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1398 int plane_sr, cursor_sr;
1399 unsigned int enabled = 0;
9858425c 1400 bool cxsr_enabled;
b445e3b0 1401
f0ce2310 1402 if (g4x_compute_wm0(dev_priv, PIPE_A,
5aef6003
CW		 1403 &g4x_wm_info, pessimal_latency_ns,
1404 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1405 &planea_wm, &cursora_wm))
51cea1f4 1406 enabled |= 1 << PIPE_A;
b445e3b0 1407
f0ce2310 1408 if (g4x_compute_wm0(dev_priv, PIPE_B,
5aef6003
CW		 1409 &g4x_wm_info, pessimal_latency_ns,
1410 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1411 &planeb_wm, &cursorb_wm))
51cea1f4 1412 enabled |= 1 << PIPE_B;
b445e3b0 1413
b445e3b0 1414 if (single_plane_enabled(enabled) &&
f0ce2310 1415 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
b445e3b0
ED		 1416 sr_latency_ns,
1417 &g4x_wm_info,
1418 &g4x_cursor_wm_info,
52bd02d8 1419 &plane_sr, &cursor_sr)) {
9858425c 1420 cxsr_enabled = true;
52bd02d8 1421 } else {
9858425c 1422 cxsr_enabled = false;
5209b1f4 1423 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1424 plane_sr = cursor_sr = 0;
1425 }
b445e3b0 1426
a5043453
VS		 1427 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1428 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1429 planea_wm, cursora_wm,
1430 planeb_wm, cursorb_wm,
1431 plane_sr, cursor_sr);
1432
1433 I915_WRITE(DSPFW1,
f4998963
VS		 1434 FW_WM(plane_sr, SR) |
1435 FW_WM(cursorb_wm, CURSORB) |
1436 FW_WM(planeb_wm, PLANEB) |
1437 FW_WM(planea_wm, PLANEA));
b445e3b0 1438 I915_WRITE(DSPFW2,
8c919b28 1439 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1440 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1441 /* HPLL off in SR has some issues on G4x... disable it */
1442 I915_WRITE(DSPFW3,
8c919b28 1443 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1444 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1445
1446 if (cxsr_enabled)
1447 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1448}
1449
432081bc 1450static void i965_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1451{
ffc7a76b 1452 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1453 struct intel_crtc *crtc;
b445e3b0
ED		 1454 int srwm = 1;
1455 int cursor_sr = 16;
9858425c 1456 bool cxsr_enabled;
b445e3b0
ED		 1457
1458 /* Calc sr entries for one plane configs */
ffc7a76b 1459 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1460 if (crtc) {
1461 /* self-refresh has much higher latency */
1462 static const int sr_latency_ns = 12000;
efc2611e
VS		 1463 const struct drm_display_mode *adjusted_mode =
1464 &crtc->config->base.adjusted_mode;
1465 const struct drm_framebuffer *fb =
1466 crtc->base.primary->state->fb;
241bfc38 1467 int clock = adjusted_mode->crtc_clock;
fec8cba3 1468 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1469 int hdisplay = crtc->config->pipe_src_w;
1470 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b445e3b0
ED		 1471 unsigned long line_time_us;
1472 int entries;
1473
922044c9 1474 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1475
1476 /* Use ns/us then divide to preserve precision */
1477 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1478 cpp * hdisplay;
b445e3b0
ED		 1479 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1480 srwm = I965_FIFO_SIZE - entries;
1481 if (srwm < 0)
1482 srwm = 1;
1483 srwm &= 0x1ff;
1484 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1485 entries, srwm);
1486
1487 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
efc2611e 1488 cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 1489 entries = DIV_ROUND_UP(entries,
1490 i965_cursor_wm_info.cacheline_size);
1491 cursor_sr = i965_cursor_wm_info.fifo_size -
1492 (entries + i965_cursor_wm_info.guard_size);
1493
1494 if (cursor_sr > i965_cursor_wm_info.max_wm)
1495 cursor_sr = i965_cursor_wm_info.max_wm;
1496
1497 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1498 "cursor %d\n", srwm, cursor_sr);
1499
9858425c 1500 cxsr_enabled = true;
b445e3b0 1501 } else {
9858425c 1502 cxsr_enabled = false;
b445e3b0 1503 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1504 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1505 }
1506
1507 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1508 srwm);
1509
1510 /* 965 has limitations... */
f4998963
VS		 1511 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1512 FW_WM(8, CURSORB) |
1513 FW_WM(8, PLANEB) |
1514 FW_WM(8, PLANEA));
1515 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1516 FW_WM(8, PLANEC_OLD));
b445e3b0 1517 /* update cursor SR watermark */
f4998963 1518 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1519
1520 if (cxsr_enabled)
1521 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1522}
1523
f4998963
VS		 1524#undef FW_WM
1525
432081bc 1526static void i9xx_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1527{
ffc7a76b 1528 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
b445e3b0
ED		 1529 const struct intel_watermark_params *wm_info;
1530 uint32_t fwater_lo;
1531 uint32_t fwater_hi;
1532 int cwm, srwm = 1;
1533 int fifo_size;
1534 int planea_wm, planeb_wm;
efc2611e 1535 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 1536
a9097be4 1537 if (IS_I945GM(dev_priv))
b445e3b0 1538 wm_info = &i945_wm_info;
5db94019 1539 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1540 wm_info = &i915_wm_info;
1541 else
9d539105 1542 wm_info = &i830_a_wm_info;
b445e3b0 1543
ef0f5e93 1544 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
b91eb5cc 1545 crtc = intel_get_crtc_for_plane(dev_priv, 0);
efc2611e
VS		 1546 if (intel_crtc_active(crtc)) {
1547 const struct drm_display_mode *adjusted_mode =
1548 &crtc->config->base.adjusted_mode;
1549 const struct drm_framebuffer *fb =
1550 crtc->base.primary->state->fb;
1551 int cpp;
1552
5db94019 1553 if (IS_GEN2(dev_priv))
b9e0bda3 1554 cpp = 4;
efc2611e
VS		 1555 else
1556 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1557
241bfc38 1558 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1559 wm_info, fifo_size, cpp,
5aef6003 1560 pessimal_latency_ns);
b445e3b0 1561 enabled = crtc;
9d539105 1562 } else {
b445e3b0 1563 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1564 if (planea_wm > (long)wm_info->max_wm)
1565 planea_wm = wm_info->max_wm;
1566 }
1567
5db94019 1568 if (IS_GEN2(dev_priv))
9d539105 1569 wm_info = &i830_bc_wm_info;
b445e3b0 1570
ef0f5e93 1571 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
b91eb5cc 1572 crtc = intel_get_crtc_for_plane(dev_priv, 1);
efc2611e
VS		 1573 if (intel_crtc_active(crtc)) {
1574 const struct drm_display_mode *adjusted_mode =
1575 &crtc->config->base.adjusted_mode;
1576 const struct drm_framebuffer *fb =
1577 crtc->base.primary->state->fb;
1578 int cpp;
1579
5db94019 1580 if (IS_GEN2(dev_priv))
b9e0bda3 1581 cpp = 4;
efc2611e
VS		 1582 else
1583 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
b9e0bda3 1584
241bfc38 1585 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1586 wm_info, fifo_size, cpp,
5aef6003 1587 pessimal_latency_ns);
b445e3b0
ED		 1588 if (enabled == NULL)
1589 enabled = crtc;
1590 else
1591 enabled = NULL;
9d539105 1592 } else {
b445e3b0 1593 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1594 if (planeb_wm > (long)wm_info->max_wm)
1595 planeb_wm = wm_info->max_wm;
1596 }
b445e3b0
ED		 1597
1598 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1599
50a0bc90 1600 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1601 struct drm_i915_gem_object *obj;
2ab1bc9d 1602
efc2611e 1603 obj = intel_fb_obj(enabled->base.primary->state->fb);
2ab1bc9d
DV		 1604
1605 /* self-refresh seems busted with untiled */
3e510a8e 1606 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1607 enabled = NULL;
1608 }
1609
b445e3b0
ED		 1610 /*
1611 * Overlay gets an aggressive default since video jitter is bad.
1612 */
1613 cwm = 2;
1614
1615 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1616 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1617
1618 /* Calc sr entries for one plane configs */
03427fcb 1619 if (HAS_FW_BLC(dev_priv) && enabled) {
b445e3b0
ED		 1620 /* self-refresh has much higher latency */
1621 static const int sr_latency_ns = 6000;
efc2611e
VS		 1622 const struct drm_display_mode *adjusted_mode =
1623 &enabled->config->base.adjusted_mode;
1624 const struct drm_framebuffer *fb =
1625 enabled->base.primary->state->fb;
241bfc38 1626 int clock = adjusted_mode->crtc_clock;
fec8cba3 1627 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1628 int hdisplay = enabled->config->pipe_src_w;
1629 int cpp;
b445e3b0
ED		 1630 unsigned long line_time_us;
1631 int entries;
1632
50a0bc90 1633 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056 1634 cpp = 4;
efc2611e
VS		 1635 else
1636 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2d1b5056 1637
922044c9 1638 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1639
1640 /* Use ns/us then divide to preserve precision */
1641 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1642 cpp * hdisplay;
b445e3b0
ED		 1643 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1644 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1645 srwm = wm_info->fifo_size - entries;
1646 if (srwm < 0)
1647 srwm = 1;
1648
50a0bc90 1649 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1650 I915_WRITE(FW_BLC_SELF,
1651 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1652 else
b445e3b0
ED		 1653 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1654 }
1655
1656 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1657 planea_wm, planeb_wm, cwm, srwm);
1658
1659 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1660 fwater_hi = (cwm & 0x1f);
1661
1662 /* Set request length to 8 cachelines per fetch */
1663 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1664 fwater_hi = fwater_hi | (1 << 8);
1665
1666 I915_WRITE(FW_BLC, fwater_lo);
1667 I915_WRITE(FW_BLC2, fwater_hi);
1668
5209b1f4
ID		 1669 if (enabled)
1670 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1671}
1672
432081bc 1673static void i845_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1674{
ffc7a76b 1675 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1676 struct intel_crtc *crtc;
241bfc38 1677 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1678 uint32_t fwater_lo;
1679 int planea_wm;
1680
ffc7a76b 1681 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1682 if (crtc == NULL)
1683 return;
1684
efc2611e 1685 adjusted_mode = &crtc->config->base.adjusted_mode;
241bfc38 1686 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1687 &i845_wm_info,
ef0f5e93 1688 dev_priv->display.get_fifo_size(dev_priv, 0),
5aef6003 1689 4, pessimal_latency_ns);
b445e3b0
ED		 1690 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1691 fwater_lo |= (3<<8) | planea_wm;
1692
1693 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1694
1695 I915_WRITE(FW_BLC, fwater_lo);
1696}
1697
8cfb3407 1698uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1699{
fd4daa9c 1700 uint32_t pixel_rate;
801bcfff 1701
8cfb3407 1702 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1703
1704 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1705 * adjust the pixel_rate here. */
1706
8cfb3407 1707 if (pipe_config->pch_pfit.enabled) {
801bcfff 1708 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1709 uint32_t pfit_size = pipe_config->pch_pfit.size;
1710
1711 pipe_w = pipe_config->pipe_src_w;
1712 pipe_h = pipe_config->pipe_src_h;
801bcfff 1713
801bcfff
PZ		 1714 pfit_w = (pfit_size >> 16) & 0xFFFF;
1715 pfit_h = pfit_size & 0xFFFF;
1716 if (pipe_w < pfit_w)
1717 pipe_w = pfit_w;
1718 if (pipe_h < pfit_h)
1719 pipe_h = pfit_h;
1720
15126882
MR		 1721 if (WARN_ON(!pfit_w || !pfit_h))
1722 return pixel_rate;
1723
801bcfff
PZ		 1724 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1725 pfit_w * pfit_h);
1726 }
1727
1728 return pixel_rate;
1729}
1730
37126462 1731/* latency must be in 0.1us units. */
ac484963 1732static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1733{
1734 uint64_t ret;
1735
3312ba65
VS		 1736 if (WARN(latency == 0, "Latency value missing\n"))
1737 return UINT_MAX;
1738
ac484963 1739 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1740 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1741
1742 return ret;
1743}
1744
37126462 1745/* latency must be in 0.1us units. */
23297044 1746static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1747 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1748 uint32_t latency)
1749{
1750 uint32_t ret;
1751
3312ba65
VS		 1752 if (WARN(latency == 0, "Latency value missing\n"))
1753 return UINT_MAX;
15126882
MR		 1754 if (WARN_ON(!pipe_htotal))
1755 return UINT_MAX;
3312ba65 1756
801bcfff 1757 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1758 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1759 ret = DIV_ROUND_UP(ret, 64) + 2;
1760 return ret;
1761}
1762
23297044 1763static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1764 uint8_t cpp)
cca32e9a 1765{
15126882
MR		 1766 /*
1767 * Neither of these should be possible since this function shouldn't be
1768 * called if the CRTC is off or the plane is invisible. But let's be
1769 * extra paranoid to avoid a potential divide-by-zero if we screw up
1770 * elsewhere in the driver.
1771 */
ac484963 1772 if (WARN_ON(!cpp))
15126882
MR		 1773 return 0;
1774 if (WARN_ON(!horiz_pixels))
1775 return 0;
1776
ac484963 1777 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1778}
1779
820c1980 1780struct ilk_wm_maximums {
cca32e9a
PZ		 1781 uint16_t pri;
1782 uint16_t spr;
1783 uint16_t cur;
1784 uint16_t fbc;
1785};
1786
37126462
VS		 1787/*
1788 * For both WM_PIPE and WM_LP.
1789 * mem_value must be in 0.1us units.
1790 */
7221fc33 1791static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1792 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1793 uint32_t mem_value,
1794 bool is_lp)
801bcfff 1795{
ac484963
VS		 1796 int cpp = pstate->base.fb ?
1797 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1798 uint32_t method1, method2;
1799
936e71e3 1800 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1801 return 0;
1802
ac484963 1803 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1804
1805 if (!is_lp)
1806 return method1;
1807
7221fc33
MR		 1808 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1809 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1810 drm_rect_width(&pstate->base.dst),
ac484963 1811 cpp, mem_value);
cca32e9a
PZ		 1812
1813 return min(method1, method2);
801bcfff
PZ		 1814}
1815
37126462
VS		 1816/*
1817 * For both WM_PIPE and WM_LP.
1818 * mem_value must be in 0.1us units.
1819 */
7221fc33 1820static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1821 const struct intel_plane_state *pstate,
801bcfff
PZ		 1822 uint32_t mem_value)
1823{
ac484963
VS		 1824 int cpp = pstate->base.fb ?
1825 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1826 uint32_t method1, method2;
1827
936e71e3 1828 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1829 return 0;
1830
ac484963 1831 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1832 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1833 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1834 drm_rect_width(&pstate->base.dst),
ac484963 1835 cpp, mem_value);
801bcfff
PZ		 1836 return min(method1, method2);
1837}
1838
37126462
VS		 1839/*
1840 * For both WM_PIPE and WM_LP.
1841 * mem_value must be in 0.1us units.
1842 */
7221fc33 1843static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1844 const struct intel_plane_state *pstate,
801bcfff
PZ		 1845 uint32_t mem_value)
1846{
b2435692
MR		 1847 /*
1848 * We treat the cursor plane as always-on for the purposes of watermark
1849 * calculation. Until we have two-stage watermark programming merged,
1850 * this is necessary to avoid flickering.
1851 */
1852 int cpp = 4;
936e71e3 1853 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1854
b2435692 1855 if (!cstate->base.active)
801bcfff
PZ		 1856 return 0;
1857
7221fc33
MR		 1858 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1859 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1860 width, cpp, mem_value);
801bcfff
PZ		 1861}
1862
cca32e9a 1863/* Only for WM_LP. */
7221fc33 1864static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1865 const struct intel_plane_state *pstate,
1fda9882 1866 uint32_t pri_val)
cca32e9a 1867{
ac484963
VS		 1868 int cpp = pstate->base.fb ?
1869 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1870
936e71e3 1871 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1872 return 0;
1873
936e71e3 1874 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1875}
1876
175fded1
TU		 1877static unsigned int
1878ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
158ae64f 1879{
175fded1 1880 if (INTEL_GEN(dev_priv) >= 8)
416f4727 1881 return 3072;
175fded1 1882 else if (INTEL_GEN(dev_priv) >= 7)
158ae64f
VS		 1883 return 768;
1884 else
1885 return 512;
1886}
1887
175fded1
TU		 1888static unsigned int
1889ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1890 int level, bool is_sprite)
4e975081 1891{
175fded1 1892 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1893 /* BDW primary/sprite plane watermarks */
1894 return level == 0 ? 255 : 2047;
175fded1 1895 else if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1896 /* IVB/HSW primary/sprite plane watermarks */
1897 return level == 0 ? 127 : 1023;
1898 else if (!is_sprite)
1899 /* ILK/SNB primary plane watermarks */
1900 return level == 0 ? 127 : 511;
1901 else
1902 /* ILK/SNB sprite plane watermarks */
1903 return level == 0 ? 63 : 255;
1904}
1905
175fded1
TU		 1906static unsigned int
1907ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
4e975081 1908{
175fded1 1909 if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1910 return level == 0 ? 63 : 255;
1911 else
1912 return level == 0 ? 31 : 63;
1913}
1914
175fded1 1915static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
4e975081 1916{
175fded1 1917 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1918 return 31;
1919 else
1920 return 15;
1921}
1922
158ae64f
VS		 1923/* Calculate the maximum primary/sprite plane watermark */
1924static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1925 int level,
240264f4 1926 const struct intel_wm_config *config,
158ae64f
VS		 1927 enum intel_ddb_partitioning ddb_partitioning,
1928 bool is_sprite)
1929{
175fded1
TU		 1930 struct drm_i915_private *dev_priv = to_i915(dev);
1931 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
158ae64f
VS		 1932
1933 /* if sprites aren't enabled, sprites get nothing */
240264f4 1934 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1935 return 0;
1936
1937 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1938 if (level == 0 || config->num_pipes_active > 1) {
175fded1 1939 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
158ae64f
VS		 1940
1941 /*
1942 * For some reason the non self refresh
1943 * FIFO size is only half of the self
1944 * refresh FIFO size on ILK/SNB.
1945 */
175fded1 1946 if (INTEL_GEN(dev_priv) <= 6)
158ae64f
VS		 1947 fifo_size /= 2;
1948 }
1949
240264f4 1950 if (config->sprites_enabled) {
158ae64f
VS		 1951 /* level 0 is always calculated with 1:1 split */
1952 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1953 if (is_sprite)
1954 fifo_size *= 5;
1955 fifo_size /= 6;
1956 } else {
1957 fifo_size /= 2;
1958 }
1959 }
1960
1961 /* clamp to max that the registers can hold */
175fded1 1962 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
158ae64f
VS		 1963}
1964
1965/* Calculate the maximum cursor plane watermark */
1966static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1967 int level,
1968 const struct intel_wm_config *config)
158ae64f
VS		 1969{
1970 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1971 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1972 return 64;
1973
1974 /* otherwise just report max that registers can hold */
175fded1 1975 return ilk_cursor_wm_reg_max(to_i915(dev), level);
158ae64f
VS		 1976}
1977
d34ff9c6 1978static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1979 int level,
1980 const struct intel_wm_config *config,
1981 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1982 struct ilk_wm_maximums *max)
158ae64f 1983{
240264f4
VS		 1984 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1985 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1986 max->cur = ilk_cursor_wm_max(dev, level, config);
175fded1 1987 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
158ae64f
VS		 1988}
1989
175fded1 1990static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
a3cb4048
VS		 1991 int level,
1992 struct ilk_wm_maximums *max)
1993{
175fded1
TU		 1994 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1995 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1996 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1997 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
a3cb4048
VS		 1998}
1999
d9395655 2000static bool ilk_validate_wm_level(int level,
820c1980 2001 const struct ilk_wm_maximums *max,
d9395655 2002 struct intel_wm_level *result)
a9786a11
VS		 2003{
2004 bool ret;
2005
2006 /* already determined to be invalid? */
2007 if (!result->enable)
2008 return false;
2009
2010 result->enable = result->pri_val <= max->pri &&
2011 result->spr_val <= max->spr &&
2012 result->cur_val <= max->cur;
2013
2014 ret = result->enable;
2015
2016 /*
2017 * HACK until we can pre-compute everything,
2018 * and thus fail gracefully if LP0 watermarks
2019 * are exceeded...
2020 */
2021 if (level == 0 && !result->enable) {
2022 if (result->pri_val > max->pri)
2023 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2024 level, result->pri_val, max->pri);
2025 if (result->spr_val > max->spr)
2026 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2027 level, result->spr_val, max->spr);
2028 if (result->cur_val > max->cur)
2029 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2030 level, result->cur_val, max->cur);
2031
2032 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2033 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2034 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2035 result->enable = true;
2036 }
2037
a9786a11
VS		 2038 return ret;
2039}
2040
d34ff9c6 2041static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2042 const struct intel_crtc *intel_crtc,
6f5ddd17 2043 int level,
7221fc33 2044 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2045 struct intel_plane_state *pristate,
2046 struct intel_plane_state *sprstate,
2047 struct intel_plane_state *curstate,
1fd527cc 2048 struct intel_wm_level *result)
6f5ddd17
VS		 2049{
2050 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2051 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2052 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2053
2054 /* WM1+ latency values stored in 0.5us units */
2055 if (level > 0) {
2056 pri_latency *= 5;
2057 spr_latency *= 5;
2058 cur_latency *= 5;
2059 }
2060
e3bddded
ML		 2061 if (pristate) {
2062 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2063 pri_latency, level);
2064 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2065 }
2066
2067 if (sprstate)
2068 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2069
2070 if (curstate)
2071 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2072
6f5ddd17
VS		 2073 result->enable = true;
2074}
2075
801bcfff 2076static uint32_t
532f7a7f 2077hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2078{
532f7a7f
VS		 2079 const struct intel_atomic_state *intel_state =
2080 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2081 const struct drm_display_mode *adjusted_mode =
2082 &cstate->base.adjusted_mode;
85a02deb 2083 u32 linetime, ips_linetime;
1f8eeabf 2084
ee91a159
MR		 2085 if (!cstate->base.active)
2086 return 0;
2087 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2088 return 0;
532f7a7f 2089 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2090 return 0;
1011d8c4 2091
1f8eeabf
ED		 2092 /* The WM are computed with base on how long it takes to fill a single
2093 * row at the given clock rate, multiplied by 8.
2094 * */
124abe07
VS		 2095 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2096 adjusted_mode->crtc_clock);
2097 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2098 intel_state->cdclk);
1f8eeabf 2099
801bcfff
PZ		 2100 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2101 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2102}
2103
bb726519
VS		 2104static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2105 uint16_t wm[8])
12b134df 2106{
5db94019 2107 if (IS_GEN9(dev_priv)) {
2af30a5c 2108 uint32_t val;
4f947386 2109 int ret, i;
5db94019 2110 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2111
2112 /* read the first set of memory latencies[0:3] */
2113 val = 0; /* data0 to be programmed to 0 for first set */
2114 mutex_lock(&dev_priv->rps.hw_lock);
2115 ret = sandybridge_pcode_read(dev_priv,
2116 GEN9_PCODE_READ_MEM_LATENCY,
2117 &val);
2118 mutex_unlock(&dev_priv->rps.hw_lock);
2119
2120 if (ret) {
2121 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2122 return;
2123 }
2124
2125 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2131 GEN9_MEM_LATENCY_LEVEL_MASK;
2132
2133 /* read the second set of memory latencies[4:7] */
2134 val = 1; /* data0 to be programmed to 1 for second set */
2135 mutex_lock(&dev_priv->rps.hw_lock);
2136 ret = sandybridge_pcode_read(dev_priv,
2137 GEN9_PCODE_READ_MEM_LATENCY,
2138 &val);
2139 mutex_unlock(&dev_priv->rps.hw_lock);
2140 if (ret) {
2141 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2142 return;
2143 }
2144
2145 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2146 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2147 GEN9_MEM_LATENCY_LEVEL_MASK;
2148 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2149 GEN9_MEM_LATENCY_LEVEL_MASK;
2150 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2151 GEN9_MEM_LATENCY_LEVEL_MASK;
2152
0727e40a
PZ		 2153 /*
2154 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2155 * need to be disabled. We make sure to sanitize the values out
2156 * of the punit to satisfy this requirement.
2157 */
2158 for (level = 1; level <= max_level; level++) {
2159 if (wm[level] == 0) {
2160 for (i = level + 1; i <= max_level; i++)
2161 wm[i] = 0;
2162 break;
2163 }
2164 }
2165
367294be 2166 /*
6f97235b
DL		 2167 * WaWmMemoryReadLatency:skl
2168 *
367294be 2169 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2170 * to add 2us to the various latency levels we retrieve from the
2171 * punit when level 0 response data us 0us.
367294be 2172 */
0727e40a
PZ		 2173 if (wm[0] == 0) {
2174 wm[0] += 2;
2175 for (level = 1; level <= max_level; level++) {
2176 if (wm[level] == 0)
2177 break;
367294be 2178 wm[level] += 2;
4f947386 2179 }
0727e40a
PZ		 2180 }
2181
8652744b 2182 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2183 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2184
2185 wm[0] = (sskpd >> 56) & 0xFF;
2186 if (wm[0] == 0)
2187 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2188 wm[1] = (sskpd >> 4) & 0xFF;
2189 wm[2] = (sskpd >> 12) & 0xFF;
2190 wm[3] = (sskpd >> 20) & 0x1FF;
2191 wm[4] = (sskpd >> 32) & 0x1FF;
bb726519 2192 } else if (INTEL_GEN(dev_priv) >= 6) {
63cf9a13
VS		 2193 uint32_t sskpd = I915_READ(MCH_SSKPD);
2194
2195 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2196 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2197 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2198 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
bb726519 2199 } else if (INTEL_GEN(dev_priv) >= 5) {
3a88d0ac
VS		 2200 uint32_t mltr = I915_READ(MLTR_ILK);
2201
2202 /* ILK primary LP0 latency is 700 ns */
2203 wm[0] = 7;
2204 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2205 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2206 }
2207}
2208
5db94019
TU		 2209static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2210 uint16_t wm[5])
53615a5e
VS		 2211{
2212 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2213 if (IS_GEN5(dev_priv))
53615a5e
VS		 2214 wm[0] = 13;
2215}
2216
fd6b8f43
TU		 2217static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2218 uint16_t wm[5])
53615a5e
VS		 2219{
2220 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2221 if (IS_GEN5(dev_priv))
53615a5e
VS		 2222 wm[0] = 13;
2223
2224 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2225 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2226 wm[3] *= 2;
2227}
2228
5db94019 2229int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2230{
26ec971e 2231 /* how many WM levels are we expecting */
8652744b 2232 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2233 return 7;
8652744b 2234 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2235 return 4;
8652744b 2236 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2237 return 3;
26ec971e 2238 else
ad0d6dc4
VS		 2239 return 2;
2240}
7526ed79 2241
5db94019 2242static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2243 const char *name,
2af30a5c 2244 const uint16_t wm[8])
ad0d6dc4 2245{
5db94019 2246 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2247
2248 for (level = 0; level <= max_level; level++) {
2249 unsigned int latency = wm[level];
2250
2251 if (latency == 0) {
2252 DRM_ERROR("%s WM%d latency not provided\n",
2253 name, level);
2254 continue;
2255 }
2256
2af30a5c
PB		 2257 /*
2258 * - latencies are in us on gen9.
2259 * - before then, WM1+ latency values are in 0.5us units
2260 */
5db94019 2261 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2262 latency *= 10;
2263 else if (level > 0)
26ec971e
VS		 2264 latency *= 5;
2265
2266 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2267 name, level, wm[level],
2268 latency / 10, latency % 10);
2269 }
2270}
2271
e95a2f75
VS		 2272static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2273 uint16_t wm[5], uint16_t min)
2274{
5db94019 2275 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2276
2277 if (wm[0] >= min)
2278 return false;
2279
2280 wm[0] = max(wm[0], min);
2281 for (level = 1; level <= max_level; level++)
2282 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2283
2284 return true;
2285}
2286
bb726519 2287static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
e95a2f75 2288{
e95a2f75
VS		 2289 bool changed;
2290
2291 /*
2292 * The BIOS provided WM memory latency values are often
2293 * inadequate for high resolution displays. Adjust them.
2294 */
2295 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2296 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2297 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2298
2299 if (!changed)
2300 return;
2301
2302 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2303 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2304 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2305 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2306}
2307
bb726519 2308static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
53615a5e 2309{
bb726519 2310 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
53615a5e
VS		 2311
2312 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2313 sizeof(dev_priv->wm.pri_latency));
2314 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2315 sizeof(dev_priv->wm.pri_latency));
2316
5db94019 2317 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2318 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2319
5db94019
TU		 2320 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2321 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2322 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2323
5db94019 2324 if (IS_GEN6(dev_priv))
bb726519 2325 snb_wm_latency_quirk(dev_priv);
53615a5e
VS		 2326}
2327
bb726519 2328static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2af30a5c 2329{
bb726519 2330 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
5db94019 2331 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2332}
2333
ed4a6a7c
MR		 2334static bool ilk_validate_pipe_wm(struct drm_device *dev,
2335 struct intel_pipe_wm *pipe_wm)
2336{
2337 /* LP0 watermark maximums depend on this pipe alone */
2338 const struct intel_wm_config config = {
2339 .num_pipes_active = 1,
2340 .sprites_enabled = pipe_wm->sprites_enabled,
2341 .sprites_scaled = pipe_wm->sprites_scaled,
2342 };
2343 struct ilk_wm_maximums max;
2344
2345 /* LP0 watermarks always use 1/2 DDB partitioning */
2346 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2347
2348 /* At least LP0 must be valid */
2349 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2350 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2351 return false;
2352 }
2353
2354 return true;
2355}
2356
0b2ae6d7 2357/* Compute new watermarks for the pipe */
e3bddded 2358static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2359{
e3bddded
ML		 2360 struct drm_atomic_state *state = cstate->base.state;
2361 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2362 struct intel_pipe_wm *pipe_wm;
e3bddded 2363 struct drm_device *dev = state->dev;
fac5e23e 2364 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2365 struct intel_plane *intel_plane;
86c8bbbe 2366 struct intel_plane_state *pristate = NULL;
43d59eda 2367 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2368 struct intel_plane_state *curstate = NULL;
5db94019 2369 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2370 struct ilk_wm_maximums max;
0b2ae6d7 2371
e8f1f02e 2372 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2373
43d59eda 2374 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2375 struct intel_plane_state *ps;
2376
2377 ps = intel_atomic_get_existing_plane_state(state,
2378 intel_plane);
2379 if (!ps)
2380 continue;
86c8bbbe
MR		 2381
2382 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2383 pristate = ps;
86c8bbbe 2384 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2385 sprstate = ps;
86c8bbbe 2386 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2387 curstate = ps;
43d59eda
MR		 2388 }
2389
ed4a6a7c 2390 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2391 if (sprstate) {
936e71e3
VS		 2392 pipe_wm->sprites_enabled = sprstate->base.visible;
2393 pipe_wm->sprites_scaled = sprstate->base.visible &&
2394 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2395 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2396 }
2397
d81f04c5
ML		 2398 usable_level = max_level;
2399
7b39a0b7 2400 /* ILK/SNB: LP2+ watermarks only w/o sprites */
175fded1 2401 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2402 usable_level = 1;
7b39a0b7
VS		 2403
2404 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2405 if (pipe_wm->sprites_scaled)
d81f04c5 2406 usable_level = 0;
7b39a0b7 2407
86c8bbbe 2408 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2409 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2410
2411 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2412 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2413
8652744b 2414 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2415 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2416
ed4a6a7c 2417 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2418 return -EINVAL;
a3cb4048 2419
175fded1 2420 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
a3cb4048
VS		 2421
2422 for (level = 1; level <= max_level; level++) {
71f0a626 2423 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2424
86c8bbbe 2425 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2426 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2427
2428 /*
2429 * Disable any watermark level that exceeds the
2430 * register maximums since such watermarks are
2431 * always invalid.
2432 */
71f0a626
ML		 2433 if (level > usable_level)
2434 continue;
2435
2436 if (ilk_validate_wm_level(level, &max, wm))
2437 pipe_wm->wm[level] = *wm;
2438 else
d81f04c5 2439 usable_level = level;
a3cb4048
VS		 2440 }
2441
86c8bbbe 2442 return 0;
0b2ae6d7
VS		 2443}
2444
ed4a6a7c
MR		 2445/*
2446 * Build a set of 'intermediate' watermark values that satisfy both the old
2447 * state and the new state. These can be programmed to the hardware
2448 * immediately.
2449 */
2450static int ilk_compute_intermediate_wm(struct drm_device *dev,
2451 struct intel_crtc *intel_crtc,
2452 struct intel_crtc_state *newstate)
2453{
e8f1f02e 2454 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2455 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2456 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2457
2458 /*
2459 * Start with the final, target watermarks, then combine with the
2460 * currently active watermarks to get values that are safe both before
2461 * and after the vblank.
2462 */
e8f1f02e 2463 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2464 a->pipe_enabled |= b->pipe_enabled;
2465 a->sprites_enabled |= b->sprites_enabled;
2466 a->sprites_scaled |= b->sprites_scaled;
2467
2468 for (level = 0; level <= max_level; level++) {
2469 struct intel_wm_level *a_wm = &a->wm[level];
2470 const struct intel_wm_level *b_wm = &b->wm[level];
2471
2472 a_wm->enable &= b_wm->enable;
2473 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2474 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2475 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2476 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2477 }
2478
2479 /*
2480 * We need to make sure that these merged watermark values are
2481 * actually a valid configuration themselves. If they're not,
2482 * there's no safe way to transition from the old state to
2483 * the new state, so we need to fail the atomic transaction.
2484 */
2485 if (!ilk_validate_pipe_wm(dev, a))
2486 return -EINVAL;
2487
2488 /*
2489 * If our intermediate WM are identical to the final WM, then we can
2490 * omit the post-vblank programming; only update if it's different.
2491 */
e8f1f02e 2492 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2493 newstate->wm.need_postvbl_update = false;
2494
2495 return 0;
2496}
2497
0b2ae6d7
VS		 2498/*
2499 * Merge the watermarks from all active pipes for a specific level.
2500 */
2501static void ilk_merge_wm_level(struct drm_device *dev,
2502 int level,
2503 struct intel_wm_level *ret_wm)
2504{
2505 const struct intel_crtc *intel_crtc;
2506
d52fea5b
VS		 2507 ret_wm->enable = true;
2508
d3fcc808 2509 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2510 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2511 const struct intel_wm_level *wm = &active->wm[level];
2512
2513 if (!active->pipe_enabled)
2514 continue;
0b2ae6d7 2515
d52fea5b
VS		 2516 /*
2517 * The watermark values may have been used in the past,
2518 * so we must maintain them in the registers for some
2519 * time even if the level is now disabled.
2520 */
0b2ae6d7 2521 if (!wm->enable)
d52fea5b 2522 ret_wm->enable = false;
0b2ae6d7
VS		 2523
2524 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2525 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2526 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2527 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2528 }
0b2ae6d7
VS		 2529}
2530
2531/*
2532 * Merge all low power watermarks for all active pipes.
2533 */
2534static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2535 const struct intel_wm_config *config,
820c1980 2536 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2537 struct intel_pipe_wm *merged)
2538{
fac5e23e 2539 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2540 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2541 int last_enabled_level = max_level;
0b2ae6d7 2542
0ba22e26 2543 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2544 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2545 config->num_pipes_active > 1)
1204d5ba 2546 last_enabled_level = 0;
0ba22e26 2547
6c8b6c28 2548 /* ILK: FBC WM must be disabled always */
175fded1 2549 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
0b2ae6d7
VS		 2550
2551 /* merge each WM1+ level */
2552 for (level = 1; level <= max_level; level++) {
2553 struct intel_wm_level *wm = &merged->wm[level];
2554
2555 ilk_merge_wm_level(dev, level, wm);
2556
d52fea5b
VS		 2557 if (level > last_enabled_level)
2558 wm->enable = false;
2559 else if (!ilk_validate_wm_level(level, max, wm))
2560 /* make sure all following levels get disabled */
2561 last_enabled_level = level - 1;
0b2ae6d7
VS		 2562
2563 /*
2564 * The spec says it is preferred to disable
2565 * FBC WMs instead of disabling a WM level.
2566 */
2567 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2568 if (wm->enable)
2569 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2570 wm->fbc_val = 0;
2571 }
2572 }
6c8b6c28
VS		 2573
2574 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2575 /*
2576 * FIXME this is racy. FBC might get enabled later.
2577 * What we should check here is whether FBC can be
2578 * enabled sometime later.
2579 */
5db94019 2580 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2581 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2582 for (level = 2; level <= max_level; level++) {
2583 struct intel_wm_level *wm = &merged->wm[level];
2584
2585 wm->enable = false;
2586 }
2587 }
0b2ae6d7
VS		 2588}
2589
b380ca3c
VS		 2590static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2591{
2592 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2593 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2594}
2595
a68d68ee
VS		 2596/* The value we need to program into the WM_LPx latency field */
2597static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2598{
fac5e23e 2599 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2600
8652744b 2601 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2602 return 2 * level;
2603 else
2604 return dev_priv->wm.pri_latency[level];
2605}
2606
820c1980 2607static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2608 const struct intel_pipe_wm *merged,
609cedef 2609 enum intel_ddb_partitioning partitioning,
820c1980 2610 struct ilk_wm_values *results)
801bcfff 2611{
175fded1 2612 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7
VS		 2613 struct intel_crtc *intel_crtc;
2614 int level, wm_lp;
cca32e9a 2615
0362c781 2616 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2617 results->partitioning = partitioning;
cca32e9a 2618
0b2ae6d7 2619 /* LP1+ register values */
cca32e9a 2620 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2621 const struct intel_wm_level *r;
801bcfff 2622
b380ca3c 2623 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2624
0362c781 2625 r = &merged->wm[level];
cca32e9a 2626
d52fea5b
VS		 2627 /*
2628 * Maintain the watermark values even if the level is
2629 * disabled. Doing otherwise could cause underruns.
2630 */
2631 results->wm_lp[wm_lp - 1] =
a68d68ee 2632 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2633 (r->pri_val << WM1_LP_SR_SHIFT) |
2634 r->cur_val;
2635
d52fea5b
VS		 2636 if (r->enable)
2637 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2638
175fded1 2639 if (INTEL_GEN(dev_priv) >= 8)
416f4727
VS		 2640 results->wm_lp[wm_lp - 1] |=
2641 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2642 else
2643 results->wm_lp[wm_lp - 1] |=
2644 r->fbc_val << WM1_LP_FBC_SHIFT;
2645
d52fea5b
VS		 2646 /*
2647 * Always set WM1S_LP_EN when spr_val != 0, even if the
2648 * level is disabled. Doing otherwise could cause underruns.
2649 */
175fded1 2650 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
6cef2b8a
VS		 2651 WARN_ON(wm_lp != 1);
2652 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2653 } else
2654 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2655 }
801bcfff 2656
0b2ae6d7 2657 /* LP0 register values */
d3fcc808 2658 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2659 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2660 const struct intel_wm_level *r =
2661 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2662
2663 if (WARN_ON(!r->enable))
2664 continue;
2665
ed4a6a7c 2666 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2667
0b2ae6d7
VS		 2668 results->wm_pipe[pipe] =
2669 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2670 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2671 r->cur_val;
801bcfff
PZ		 2672 }
2673}
2674
861f3389
PZ		 2675/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2676 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2677static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2678 struct intel_pipe_wm *r1,
2679 struct intel_pipe_wm *r2)
861f3389 2680{
5db94019 2681 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2682 int level1 = 0, level2 = 0;
861f3389 2683
198a1e9b
VS		 2684 for (level = 1; level <= max_level; level++) {
2685 if (r1->wm[level].enable)
2686 level1 = level;
2687 if (r2->wm[level].enable)
2688 level2 = level;
861f3389
PZ		 2689 }
2690
198a1e9b
VS		 2691 if (level1 == level2) {
2692 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2693 return r2;
2694 else
2695 return r1;
198a1e9b 2696 } else if (level1 > level2) {
861f3389
PZ		 2697 return r1;
2698 } else {
2699 return r2;
2700 }
2701}
2702
49a687c4
VS		 2703/* dirty bits used to track which watermarks need changes */
2704#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2705#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2706#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2707#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2708#define WM_DIRTY_FBC (1 << 24)
2709#define WM_DIRTY_DDB (1 << 25)
2710
055e393f 2711static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2712 const struct ilk_wm_values *old,
2713 const struct ilk_wm_values *new)
49a687c4
VS		 2714{
2715 unsigned int dirty = 0;
2716 enum pipe pipe;
2717 int wm_lp;
2718
055e393f 2719 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2720 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2721 dirty |= WM_DIRTY_LINETIME(pipe);
2722 /* Must disable LP1+ watermarks too */
2723 dirty |= WM_DIRTY_LP_ALL;
2724 }
2725
2726 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2727 dirty |= WM_DIRTY_PIPE(pipe);
2728 /* Must disable LP1+ watermarks too */
2729 dirty |= WM_DIRTY_LP_ALL;
2730 }
2731 }
2732
2733 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2734 dirty |= WM_DIRTY_FBC;
2735 /* Must disable LP1+ watermarks too */
2736 dirty |= WM_DIRTY_LP_ALL;
2737 }
2738
2739 if (old->partitioning != new->partitioning) {
2740 dirty |= WM_DIRTY_DDB;
2741 /* Must disable LP1+ watermarks too */
2742 dirty |= WM_DIRTY_LP_ALL;
2743 }
2744
2745 /* LP1+ watermarks already deemed dirty, no need to continue */
2746 if (dirty & WM_DIRTY_LP_ALL)
2747 return dirty;
2748
2749 /* Find the lowest numbered LP1+ watermark in need of an update... */
2750 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2751 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2752 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2753 break;
2754 }
2755
2756 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2757 for (; wm_lp <= 3; wm_lp++)
2758 dirty |= WM_DIRTY_LP(wm_lp);
2759
2760 return dirty;
2761}
2762
8553c18e
VS		 2763static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2764 unsigned int dirty)
801bcfff 2765{
820c1980 2766 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2767 bool changed = false;
801bcfff 2768
facd619b
VS		 2769 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2770 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2771 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2772 changed = true;
facd619b
VS		 2773 }
2774 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2775 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2776 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2777 changed = true;
facd619b
VS		 2778 }
2779 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2780 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2781 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2782 changed = true;
facd619b 2783 }
801bcfff 2784
facd619b
VS		 2785 /*
2786 * Don't touch WM1S_LP_EN here.
2787 * Doing so could cause underruns.
2788 */
6cef2b8a 2789
8553c18e
VS		 2790 return changed;
2791}
2792
2793/*
2794 * The spec says we shouldn't write when we don't need, because every write
2795 * causes WMs to be re-evaluated, expending some power.
2796 */
820c1980
ID		 2797static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2798 struct ilk_wm_values *results)
8553c18e 2799{
820c1980 2800 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2801 unsigned int dirty;
2802 uint32_t val;
2803
055e393f 2804 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2805 if (!dirty)
2806 return;
2807
2808 _ilk_disable_lp_wm(dev_priv, dirty);
2809
49a687c4 2810 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2811 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2812 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2813 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2814 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2815 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2816
49a687c4 2817 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2818 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2819 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2820 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2821 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2822 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2823
49a687c4 2824 if (dirty & WM_DIRTY_DDB) {
8652744b 2825 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2826 val = I915_READ(WM_MISC);
2827 if (results->partitioning == INTEL_DDB_PART_1_2)
2828 val &= ~WM_MISC_DATA_PARTITION_5_6;
2829 else
2830 val |= WM_MISC_DATA_PARTITION_5_6;
2831 I915_WRITE(WM_MISC, val);
2832 } else {
2833 val = I915_READ(DISP_ARB_CTL2);
2834 if (results->partitioning == INTEL_DDB_PART_1_2)
2835 val &= ~DISP_DATA_PARTITION_5_6;
2836 else
2837 val |= DISP_DATA_PARTITION_5_6;
2838 I915_WRITE(DISP_ARB_CTL2, val);
2839 }
1011d8c4
PZ		 2840 }
2841
49a687c4 2842 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2843 val = I915_READ(DISP_ARB_CTL);
2844 if (results->enable_fbc_wm)
2845 val &= ~DISP_FBC_WM_DIS;
2846 else
2847 val |= DISP_FBC_WM_DIS;
2848 I915_WRITE(DISP_ARB_CTL, val);
2849 }
2850
954911eb
ID		 2851 if (dirty & WM_DIRTY_LP(1) &&
2852 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2853 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2854
175fded1 2855 if (INTEL_GEN(dev_priv) >= 7) {
6cef2b8a
VS		 2856 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2857 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2858 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2859 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2860 }
801bcfff 2861
facd619b 2862 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2863 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2864 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2865 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2866 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2867 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2868
2869 dev_priv->wm.hw = *results;
801bcfff
PZ		 2870}
2871
ed4a6a7c 2872bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2873{
fac5e23e 2874 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2875
2876 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2877}
2878
656d1b89 2879#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2880
ee3d532f
PZ		 2881/*
2882 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2883 * so assume we'll always need it in order to avoid underruns.
2884 */
2885static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2886{
2887 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2888
2889 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2890 IS_KABYLAKE(dev_priv))
2891 return true;
2892
2893 return false;
2894}
2895
56feca91
PZ		 2896static bool
2897intel_has_sagv(struct drm_i915_private *dev_priv)
2898{
6e3100ec
PZ		 2899 if (IS_KABYLAKE(dev_priv))
2900 return true;
2901
2902 if (IS_SKYLAKE(dev_priv) &&
2903 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2904 return true;
2905
2906 return false;
56feca91
PZ		 2907}
2908
656d1b89
L		 2909/*
2910 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2911 * depending on power and performance requirements. The display engine access
2912 * to system memory is blocked during the adjustment time. Because of the
2913 * blocking time, having this enabled can cause full system hangs and/or pipe
2914 * underruns if we don't meet all of the following requirements:
2915 *
2916 * - <= 1 pipe enabled
2917 * - All planes can enable watermarks for latencies >= SAGV engine block time
2918 * - We're not using an interlaced display configuration
2919 */
2920int
16dcdc4e 2921intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2922{
2923 int ret;
2924
56feca91
PZ		 2925 if (!intel_has_sagv(dev_priv))
2926 return 0;
2927
2928 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2929 return 0;
2930
2931 DRM_DEBUG_KMS("Enabling the SAGV\n");
2932 mutex_lock(&dev_priv->rps.hw_lock);
2933
2934 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2935 GEN9_SAGV_ENABLE);
2936
2937 /* We don't need to wait for the SAGV when enabling */
2938 mutex_unlock(&dev_priv->rps.hw_lock);
2939
2940 /*
2941 * Some skl systems, pre-release machines in particular,
2942 * don't actually have an SAGV.
2943 */
6e3100ec 2944 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2945 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2946 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2947 return 0;
2948 } else if (ret < 0) {
2949 DRM_ERROR("Failed to enable the SAGV\n");
2950 return ret;
2951 }
2952
16dcdc4e 2953 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2954 return 0;
2955}
2956
2957static int
16dcdc4e 2958intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2959{
2960 int ret;
2961 uint32_t temp = GEN9_SAGV_DISABLE;
2962
2963 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2964 &temp);
2965 if (ret)
2966 return ret;
2967 else
2968 return temp & GEN9_SAGV_IS_DISABLED;
2969}
2970
2971int
16dcdc4e 2972intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2973{
2974 int ret, result;
2975
56feca91
PZ		 2976 if (!intel_has_sagv(dev_priv))
2977 return 0;
2978
2979 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2980 return 0;
2981
2982 DRM_DEBUG_KMS("Disabling the SAGV\n");
2983 mutex_lock(&dev_priv->rps.hw_lock);
2984
2985 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2986 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2987 mutex_unlock(&dev_priv->rps.hw_lock);
2988
2989 if (ret == -ETIMEDOUT) {
2990 DRM_ERROR("Request to disable SAGV timed out\n");
2991 return -ETIMEDOUT;
2992 }
2993
2994 /*
2995 * Some skl systems, pre-release machines in particular,
2996 * don't actually have an SAGV.
2997 */
6e3100ec 2998 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 2999 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3000 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3001 return 0;
3002 } else if (result < 0) {
3003 DRM_ERROR("Failed to disable the SAGV\n");
3004 return result;
3005 }
3006
16dcdc4e 3007 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3008 return 0;
3009}
3010
16dcdc4e 3011bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3012{
3013 struct drm_device *dev = state->dev;
3014 struct drm_i915_private *dev_priv = to_i915(dev);
3015 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3016 struct intel_crtc *crtc;
3017 struct intel_plane *plane;
d8c0fafc 3018 struct intel_crtc_state *cstate;
656d1b89 3019 enum pipe pipe;
d8c0fafc 3020 int level, latency;
656d1b89 3021
56feca91
PZ		 3022 if (!intel_has_sagv(dev_priv))
3023 return false;
3024
656d1b89
L		 3025 /*
3026 * SKL workaround: bspec recommends we disable the SAGV when we have
3027 * more then one pipe enabled
3028 *
3029 * If there are no active CRTCs, no additional checks need be performed
3030 */
3031 if (hweight32(intel_state->active_crtcs) == 0)
3032 return true;
3033 else if (hweight32(intel_state->active_crtcs) > 1)
3034 return false;
3035
3036 /* Since we're now guaranteed to only have one active CRTC... */
3037 pipe = ffs(intel_state->active_crtcs) - 1;
98187836 3038 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
d8c0fafc 3039 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3040
c89cadd5 3041 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3042 return false;
3043
ee3d532f 3044 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d5cdfdf5
VS		 3045 struct skl_plane_wm *wm =
3046 &cstate->wm.skl.optimal.planes[plane->id];
ee3d532f 3047
656d1b89 3048 /* Skip this plane if it's not enabled */
d8c0fafc 3049 if (!wm->wm[0].plane_en)
656d1b89
L		 3050 continue;
3051
3052 /* Find the highest enabled wm level for this plane */
5db94019 3053 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3054 !wm->wm[level].plane_en; --level)
656d1b89
L		 3055 { }
3056
ee3d532f
PZ		 3057 latency = dev_priv->wm.skl_latency[level];
3058
3059 if (skl_needs_memory_bw_wa(intel_state) &&
bae781b2 3060 plane->base.state->fb->modifier ==
ee3d532f
PZ		 3061 I915_FORMAT_MOD_X_TILED)
3062 latency += 15;
3063
656d1b89
L		 3064 /*
3065 * If any of the planes on this pipe don't enable wm levels
3066 * that incur memory latencies higher then 30µs we can't enable
3067 * the SAGV
3068 */
ee3d532f 3069 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3070 return false;
3071 }
3072
3073 return true;
3074}
3075
b9cec075
DL		 3076static void
3077skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3078 const struct intel_crtc_state *cstate,
c107acfe
MR		 3079 struct skl_ddb_entry *alloc, /* out */
3080 int *num_active /* out */)
b9cec075 3081{
c107acfe
MR		 3082 struct drm_atomic_state *state = cstate->base.state;
3083 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3084 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3085 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3086 unsigned int pipe_size, ddb_size;
3087 int nth_active_pipe;
c107acfe 3088
a6d3460e 3089 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3090 alloc->start = 0;
3091 alloc->end = 0;
a6d3460e 3092 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3093 return;
3094 }
3095
a6d3460e
MR		 3096 if (intel_state->active_pipe_changes)
3097 *num_active = hweight32(intel_state->active_crtcs);
3098 else
3099 *num_active = hweight32(dev_priv->active_crtcs);
3100
6f3fff60
D		 3101 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3102 WARN_ON(ddb_size == 0);
b9cec075
DL		 3103
3104 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3105
c107acfe 3106 /*
a6d3460e
MR		 3107 * If the state doesn't change the active CRTC's, then there's
3108 * no need to recalculate; the existing pipe allocation limits
3109 * should remain unchanged. Note that we're safe from racing
3110 * commits since any racing commit that changes the active CRTC
3111 * list would need to grab _all_ crtc locks, including the one
3112 * we currently hold.
c107acfe 3113 */
a6d3460e 3114 if (!intel_state->active_pipe_changes) {
512b5527
ML		 3115 /*
3116 * alloc may be cleared by clear_intel_crtc_state,
3117 * copy from old state to be sure
3118 */
3119 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
a6d3460e 3120 return;
c107acfe 3121 }
a6d3460e
MR		 3122
3123 nth_active_pipe = hweight32(intel_state->active_crtcs &
3124 (drm_crtc_mask(for_crtc) - 1));
3125 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3126 alloc->start = nth_active_pipe * ddb_size / *num_active;
3127 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3128}
3129
c107acfe 3130static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3131{
c107acfe 3132 if (num_active == 1)
b9cec075
DL		 3133 return 32;
3134
3135 return 8;
3136}
3137
a269c583
DL		 3138static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3139{
3140 entry->start = reg & 0x3ff;
3141 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3142 if (entry->end)
3143 entry->end += 1;
a269c583
DL		 3144}
3145
08db6652
DL		 3146void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3147 struct skl_ddb_allocation *ddb /* out */)
a269c583 3148{
d5cdfdf5 3149 struct intel_crtc *crtc;
a269c583 3150
b10f1b20
ML		 3151 memset(ddb, 0, sizeof(*ddb));
3152
d5cdfdf5 3153 for_each_intel_crtc(&dev_priv->drm, crtc) {
4d800030 3154 enum intel_display_power_domain power_domain;
d5cdfdf5
VS		 3155 enum plane_id plane_id;
3156 enum pipe pipe = crtc->pipe;
4d800030
ID		 3157
3158 power_domain = POWER_DOMAIN_PIPE(pipe);
3159 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3160 continue;
3161
d5cdfdf5
VS		 3162 for_each_plane_id_on_crtc(crtc, plane_id) {
3163 u32 val;
3164
3165 if (plane_id != PLANE_CURSOR)
3166 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
3167 else
3168 val = I915_READ(CUR_BUF_CFG(pipe));
a269c583 3169
d5cdfdf5
VS		 3170 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
3171 }
4d800030
ID		 3172
3173 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3174 }
3175}
3176
9c2f7a9d
KM		 3177/*
3178 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3179 * The bspec defines downscale amount as:
3180 *
3181 * """
3182 * Horizontal down scale amount = maximum[1, Horizontal source size /
3183 * Horizontal destination size]
3184 * Vertical down scale amount = maximum[1, Vertical source size /
3185 * Vertical destination size]
3186 * Total down scale amount = Horizontal down scale amount *
3187 * Vertical down scale amount
3188 * """
3189 *
3190 * Return value is provided in 16.16 fixed point form to retain fractional part.
3191 * Caller should take care of dividing & rounding off the value.
3192 */
3193static uint32_t
3194skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3195{
3196 uint32_t downscale_h, downscale_w;
3197 uint32_t src_w, src_h, dst_w, dst_h;
3198
936e71e3 3199 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3200 return DRM_PLANE_HELPER_NO_SCALING;
3201
3202 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3203 src_w = drm_rect_width(&pstate->base.src);
3204 src_h = drm_rect_height(&pstate->base.src);
3205 dst_w = drm_rect_width(&pstate->base.dst);
3206 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3207 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3208 swap(dst_w, dst_h);
3209
3210 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3211 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3212
3213 /* Provide result in 16.16 fixed point */
3214 return (uint64_t)downscale_w * downscale_h >> 16;
3215}
3216
b9cec075 3217static unsigned int
024c9045
MR		 3218skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3219 const struct drm_plane_state *pstate,
3220 int y)
b9cec075 3221{
a280f7dd 3222 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3223 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3224 uint32_t down_scale_amount, data_rate;
a280f7dd 3225 uint32_t width = 0, height = 0;
a1de91e5
MR		 3226 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3227
936e71e3 3228 if (!intel_pstate->base.visible)
a1de91e5
MR		 3229 return 0;
3230 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3231 return 0;
3232 if (y && format != DRM_FORMAT_NV12)
3233 return 0;
a280f7dd 3234
936e71e3
VS		 3235 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3236 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3237
bd2ef25d 3238 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3239 swap(width, height);
2cd601c6
CK		 3240
3241 /* for planar format */
a1de91e5 3242 if (format == DRM_FORMAT_NV12) {
2cd601c6 3243 if (y) /* y-plane data rate */
8d19d7d9 3244 data_rate = width * height *
a1de91e5 3245 drm_format_plane_cpp(format, 0);
2cd601c6 3246 else /* uv-plane data rate */
8d19d7d9 3247 data_rate = (width / 2) * (height / 2) *
a1de91e5 3248 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3249 } else {
3250 /* for packed formats */
3251 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3252 }
3253
8d19d7d9
KM		 3254 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3255
3256 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3257}
3258
3259/*
3260 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3261 * a 8192x4096@32bpp framebuffer:
3262 * 3 * 4096 * 8192 * 4 < 2^32
3263 */
3264static unsigned int
1e6ee542
ML		 3265skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3266 unsigned *plane_data_rate,
3267 unsigned *plane_y_data_rate)
b9cec075 3268{
9c74d826
MR		 3269 struct drm_crtc_state *cstate = &intel_cstate->base;
3270 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3271 struct drm_plane *plane;
c8fe32c1 3272 const struct drm_plane_state *pstate;
d5cdfdf5 3273 unsigned int total_data_rate = 0;
a6d3460e
MR		 3274
3275 if (WARN_ON(!state))
3276 return 0;
b9cec075 3277
a1de91e5 3278 /* Calculate and cache data rate for each plane */
c8fe32c1 3279 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
d5cdfdf5
VS		 3280 enum plane_id plane_id = to_intel_plane(plane)->id;
3281 unsigned int rate;
a6d3460e 3282
a6d3460e
MR		 3283 /* packed/uv */
3284 rate = skl_plane_relative_data_rate(intel_cstate,
3285 pstate, 0);
d5cdfdf5 3286 plane_data_rate[plane_id] = rate;
1e6ee542
ML		 3287
3288 total_data_rate += rate;
a6d3460e
MR		 3289
3290 /* y-plane */
3291 rate = skl_plane_relative_data_rate(intel_cstate,
3292 pstate, 1);
d5cdfdf5 3293 plane_y_data_rate[plane_id] = rate;
024c9045 3294
1e6ee542 3295 total_data_rate += rate;
b9cec075
DL		 3296 }
3297
3298 return total_data_rate;
3299}
3300
cbcfd14b
KM		 3301static uint16_t
3302skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3303 const int y)
3304{
3305 struct drm_framebuffer *fb = pstate->fb;
3306 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3307 uint32_t src_w, src_h;
3308 uint32_t min_scanlines = 8;
3309 uint8_t plane_bpp;
3310
3311 if (WARN_ON(!fb))
3312 return 0;
3313
3314 /* For packed formats, no y-plane, return 0 */
3315 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3316 return 0;
3317
3318 /* For Non Y-tile return 8-blocks */
bae781b2
VS		 3319 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3320 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
cbcfd14b
KM		 3321 return 8;
3322
936e71e3
VS		 3323 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3324 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3325
bd2ef25d 3326 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3327 swap(src_w, src_h);
3328
3329 /* Halve UV plane width and height for NV12 */
3330 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3331 src_w /= 2;
3332 src_h /= 2;
3333 }
3334
3335 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3336 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3337 else
3338 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3339
bd2ef25d 3340 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3341 switch (plane_bpp) {
3342 case 1:
3343 min_scanlines = 32;
3344 break;
3345 case 2:
3346 min_scanlines = 16;
3347 break;
3348 case 4:
3349 min_scanlines = 8;
3350 break;
3351 case 8:
3352 min_scanlines = 4;
3353 break;
3354 default:
3355 WARN(1, "Unsupported pixel depth %u for rotation",
3356 plane_bpp);
3357 min_scanlines = 32;
3358 }
3359 }
3360
3361 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3362}
3363
49845a7a
ML		 3364static void
3365skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3366 uint16_t *minimum, uint16_t *y_minimum)
3367{
3368 const struct drm_plane_state *pstate;
3369 struct drm_plane *plane;
3370
3371 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
d5cdfdf5 3372 enum plane_id plane_id = to_intel_plane(plane)->id;
49845a7a 3373
d5cdfdf5 3374 if (plane_id == PLANE_CURSOR)
49845a7a
ML		 3375 continue;
3376
3377 if (!pstate->visible)
3378 continue;
3379
d5cdfdf5
VS		 3380 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
3381 y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
49845a7a
ML		 3382 }
3383
3384 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3385}
3386
c107acfe 3387static int
024c9045 3388skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3389 struct skl_ddb_allocation *ddb /* out */)
3390{
c107acfe 3391 struct drm_atomic_state *state = cstate->base.state;
024c9045 3392 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3393 struct drm_device *dev = crtc->dev;
3394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3395 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3396 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
49845a7a 3397 uint16_t alloc_size, start;
fefdd810
ML		 3398 uint16_t minimum[I915_MAX_PLANES] = {};
3399 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3400 unsigned int total_data_rate;
d5cdfdf5 3401 enum plane_id plane_id;
c107acfe 3402 int num_active;
1e6ee542
ML		 3403 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3404 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3405
5a920b85
PZ		 3406 /* Clear the partitioning for disabled planes. */
3407 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3408 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3409
a6d3460e
MR		 3410 if (WARN_ON(!state))
3411 return 0;
3412
c107acfe 3413 if (!cstate->base.active) {
ce0ba283 3414 alloc->start = alloc->end = 0;
c107acfe
MR		 3415 return 0;
3416 }
3417
a6d3460e 3418 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3419 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3420 if (alloc_size == 0) {
3421 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3422 return 0;
b9cec075
DL		 3423 }
3424
49845a7a 3425 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
a6d3460e 3426
49845a7a
ML		 3427 /*
3428 * 1. Allocate the mininum required blocks for each active plane
3429 * and allocate the cursor, it doesn't require extra allocation
3430 * proportional to the data rate.
3431 */
80958155 3432
d5cdfdf5
VS		 3433 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
3434 alloc_size -= minimum[plane_id];
3435 alloc_size -= y_minimum[plane_id];
80958155
DL		 3436 }
3437
49845a7a
ML		 3438 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3439 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3440
b9cec075 3441 /*
80958155
DL		 3442 * 2. Distribute the remaining space in proportion to the amount of
3443 * data each plane needs to fetch from memory.
b9cec075
DL		 3444 *
3445 * FIXME: we may not allocate every single block here.
3446 */
1e6ee542
ML		 3447 total_data_rate = skl_get_total_relative_data_rate(cstate,
3448 plane_data_rate,
3449 plane_y_data_rate);
a1de91e5 3450 if (total_data_rate == 0)
c107acfe 3451 return 0;
b9cec075 3452
34bb56af 3453 start = alloc->start;
d5cdfdf5 3454 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
2cd601c6
CK		 3455 unsigned int data_rate, y_data_rate;
3456 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3457
d5cdfdf5 3458 if (plane_id == PLANE_CURSOR)
49845a7a
ML		 3459 continue;
3460
d5cdfdf5 3461 data_rate = plane_data_rate[plane_id];
b9cec075
DL		 3462
3463 /*
2cd601c6 3464 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3465 * promote the expression to 64 bits to avoid overflowing, the
3466 * result is < available as data_rate / total_data_rate < 1
3467 */
d5cdfdf5 3468 plane_blocks = minimum[plane_id];
80958155
DL		 3469 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3470 total_data_rate);
b9cec075 3471
c107acfe
MR		 3472 /* Leave disabled planes at (0,0) */
3473 if (data_rate) {
d5cdfdf5
VS		 3474 ddb->plane[pipe][plane_id].start = start;
3475 ddb->plane[pipe][plane_id].end = start + plane_blocks;
c107acfe 3476 }
b9cec075
DL		 3477
3478 start += plane_blocks;
2cd601c6
CK		 3479
3480 /*
3481 * allocation for y_plane part of planar format:
3482 */
d5cdfdf5 3483 y_data_rate = plane_y_data_rate[plane_id];
a1de91e5 3484
d5cdfdf5 3485 y_plane_blocks = y_minimum[plane_id];
a1de91e5
MR		 3486 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3487 total_data_rate);
2cd601c6 3488
c107acfe 3489 if (y_data_rate) {
d5cdfdf5
VS		 3490 ddb->y_plane[pipe][plane_id].start = start;
3491 ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
c107acfe 3492 }
a1de91e5
MR		 3493
3494 start += y_plane_blocks;
b9cec075
DL		 3495 }
3496
c107acfe 3497 return 0;
b9cec075
DL		 3498}
3499
2d41c0b5
PB		 3500/*
3501 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3502 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3503 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3504 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3505*/
ac484963 3506static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3507{
3508 uint32_t wm_intermediate_val, ret;
3509
3510 if (latency == 0)
3511 return UINT_MAX;
3512
ac484963 3513 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3514 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3515
3516 return ret;
3517}
3518
3519static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3520 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3521{
d4c2aa60 3522 uint32_t ret;
d4c2aa60 3523 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3524
3525 if (latency == 0)
3526 return UINT_MAX;
3527
2d41c0b5
PB		 3528 wm_intermediate_val = latency * pixel_rate;
3529 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3530 plane_blocks_per_line;
2d41c0b5
PB		 3531
3532 return ret;
3533}
3534
9c2f7a9d
KM		 3535static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3536 struct intel_plane_state *pstate)
3537{
3538 uint64_t adjusted_pixel_rate;
3539 uint64_t downscale_amount;
3540 uint64_t pixel_rate;
3541
3542 /* Shouldn't reach here on disabled planes... */
936e71e3 3543 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3544 return 0;
3545
3546 /*
3547 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3548 * with additional adjustments for plane-specific scaling.
3549 */
cfd7e3a2 3550 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
9c2f7a9d
KM		 3551 downscale_amount = skl_plane_downscale_amount(pstate);
3552
3553 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3554 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3555
3556 return pixel_rate;
3557}
3558
55994c2c
MR		 3559static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3560 struct intel_crtc_state *cstate,
3561 struct intel_plane_state *intel_pstate,
3562 uint16_t ddb_allocation,
3563 int level,
3564 uint16_t *out_blocks, /* out */
3565 uint8_t *out_lines, /* out */
3566 bool *enabled /* out */)
2d41c0b5 3567{
33815fa5
MR		 3568 struct drm_plane_state *pstate = &intel_pstate->base;
3569 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3570 uint32_t latency = dev_priv->wm.skl_latency[level];
3571 uint32_t method1, method2;
3572 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3573 uint32_t res_blocks, res_lines;
3574 uint32_t selected_result;
ac484963 3575 uint8_t cpp;
a280f7dd 3576 uint32_t width = 0, height = 0;
9c2f7a9d 3577 uint32_t plane_pixel_rate;
75676ed4 3578 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3579 struct intel_atomic_state *state =
3580 to_intel_atomic_state(cstate->base.state);
3581 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3582
936e71e3 3583 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3584 *enabled = false;
3585 return 0;
3586 }
2d41c0b5 3587
bae781b2 3588 if (apply_memory_bw_wa && fb->modifier == I915_FORMAT_MOD_X_TILED)
ee3d532f
PZ		 3589 latency += 15;
3590
936e71e3
VS		 3591 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3592 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3593
bd2ef25d 3594 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3595 swap(width, height);
3596
ac484963 3597 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3598 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3599
61d0a04d 3600 if (drm_rotation_90_or_270(pstate->rotation)) {
1186fa85
PZ		 3601 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3602 drm_format_plane_cpp(fb->pixel_format, 1) :
3603 drm_format_plane_cpp(fb->pixel_format, 0);
3604
3605 switch (cpp) {
3606 case 1:
3607 y_min_scanlines = 16;
3608 break;
3609 case 2:
3610 y_min_scanlines = 8;
3611 break;
1186fa85
PZ		 3612 case 4:
3613 y_min_scanlines = 4;
3614 break;
86a462bc
PZ		 3615 default:
3616 MISSING_CASE(cpp);
3617 return -EINVAL;
1186fa85
PZ		 3618 }
3619 } else {
3620 y_min_scanlines = 4;
3621 }
3622
2ef32dee
PZ		 3623 if (apply_memory_bw_wa)
3624 y_min_scanlines *= 2;
3625
7a1a8aed 3626 plane_bytes_per_line = width * cpp;
bae781b2
VS		 3627 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3628 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
7a1a8aed
PZ		 3629 plane_blocks_per_line =
3630 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3631 plane_blocks_per_line /= y_min_scanlines;
bae781b2 3632 } else if (fb->modifier == DRM_FORMAT_MOD_NONE) {
7a1a8aed
PZ		 3633 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3634 + 1;
3635 } else {
3636 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3637 }
3638
9c2f7a9d
KM		 3639 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3640 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3641 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3642 latency,
7a1a8aed 3643 plane_blocks_per_line);
2d41c0b5 3644
75676ed4
PZ		 3645 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3646
bae781b2
VS		 3647 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3648 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3649 selected_result = max(method2, y_tile_minimum);
3650 } else {
f1db3eaf
PZ		 3651 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3652 (plane_bytes_per_line / 512 < 1))
3653 selected_result = method2;
3654 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3655 selected_result = min(method1, method2);
3656 else
3657 selected_result = method1;
3658 }
2d41c0b5 3659
d4c2aa60
TU		 3660 res_blocks = selected_result + 1;
3661 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3662
0fda6568 3663 if (level >= 1 && level <= 7) {
bae781b2
VS		 3664 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3665 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
75676ed4 3666 res_blocks += y_tile_minimum;
1186fa85 3667 res_lines += y_min_scanlines;
75676ed4 3668 } else {
0fda6568 3669 res_blocks++;
75676ed4 3670 }
0fda6568 3671 }
e6d66171 3672
55994c2c
MR		 3673 if (res_blocks >= ddb_allocation || res_lines > 31) {
3674 *enabled = false;
6b6bada7
MR		 3675
3676 /*
3677 * If there are no valid level 0 watermarks, then we can't
3678 * support this display configuration.
3679 */
3680 if (level) {
3681 return 0;
3682 } else {
d5cdfdf5
VS		 3683 struct drm_plane *plane = pstate->plane;
3684
6b6bada7 3685 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
d5cdfdf5
VS		 3686 DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n",
3687 plane->base.id, plane->name,
6b6bada7 3688 res_blocks, ddb_allocation, res_lines);
6b6bada7
MR		 3689 return -EINVAL;
3690 }
55994c2c 3691 }
e6d66171
DL		 3692
3693 *out_blocks = res_blocks;
3694 *out_lines = res_lines;
55994c2c 3695 *enabled = true;
2d41c0b5 3696
55994c2c 3697 return 0;
2d41c0b5
PB		 3698}
3699
f4a96752
MR		 3700static int
3701skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3702 struct skl_ddb_allocation *ddb,
3703 struct intel_crtc_state *cstate,
a62163e9 3704 struct intel_plane *intel_plane,
f4a96752
MR		 3705 int level,
3706 struct skl_wm_level *result)
2d41c0b5 3707{
f4a96752 3708 struct drm_atomic_state *state = cstate->base.state;
024c9045 3709 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3710 struct drm_plane *plane = &intel_plane->base;
3711 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3712 uint16_t ddb_blocks;
024c9045 3713 enum pipe pipe = intel_crtc->pipe;
55994c2c 3714 int ret;
a62163e9
L		 3715
3716 if (state)
3717 intel_pstate =
3718 intel_atomic_get_existing_plane_state(state,
3719 intel_plane);
024c9045 3720
f4a96752 3721 /*
a62163e9
L		 3722 * Note: If we start supporting multiple pending atomic commits against
3723 * the same planes/CRTC's in the future, plane->state will no longer be
3724 * the correct pre-state to use for the calculations here and we'll
3725 * need to change where we get the 'unchanged' plane data from.
3726 *
3727 * For now this is fine because we only allow one queued commit against
3728 * a CRTC. Even if the plane isn't modified by this transaction and we
3729 * don't have a plane lock, we still have the CRTC's lock, so we know
3730 * that no other transactions are racing with us to update it.
f4a96752 3731 */
a62163e9
L		 3732 if (!intel_pstate)
3733 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3734
a62163e9 3735 WARN_ON(!intel_pstate->base.fb);
f4a96752 3736
d5cdfdf5 3737 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
2d41c0b5 3738
a62163e9
L		 3739 ret = skl_compute_plane_wm(dev_priv,
3740 cstate,
3741 intel_pstate,
3742 ddb_blocks,
3743 level,
3744 &result->plane_res_b,
3745 &result->plane_res_l,
3746 &result->plane_en);
3747 if (ret)
3748 return ret;
f4a96752
MR		 3749
3750 return 0;
2d41c0b5
PB		 3751}
3752
407b50f3 3753static uint32_t
024c9045 3754skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3755{
30d1b5fe
PZ		 3756 uint32_t pixel_rate;
3757
024c9045 3758 if (!cstate->base.active)
407b50f3
DL		 3759 return 0;
3760
30d1b5fe
PZ		 3761 pixel_rate = ilk_pipe_pixel_rate(cstate);
3762
3763 if (WARN_ON(pixel_rate == 0))
661abfc0 3764 return 0;
407b50f3 3765
024c9045 3766 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
30d1b5fe 3767 pixel_rate);
407b50f3
DL		 3768}
3769
024c9045 3770static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3771 struct skl_wm_level *trans_wm /* out */)
407b50f3 3772{
024c9045 3773 if (!cstate->base.active)
407b50f3 3774 return;
9414f563
DL		 3775
3776 /* Until we know more, just disable transition WMs */
a62163e9 3777 trans_wm->plane_en = false;
407b50f3
DL		 3778}
3779
55994c2c
MR		 3780static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3781 struct skl_ddb_allocation *ddb,
3782 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3783{
024c9045 3784 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3785 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3786 struct intel_plane *intel_plane;
3787 struct skl_plane_wm *wm;
5db94019 3788 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3789 int ret;
2d41c0b5 3790
a62163e9
L		 3791 /*
3792 * We'll only calculate watermarks for planes that are actually
3793 * enabled, so make sure all other planes are set as disabled.
3794 */
3795 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3796
3797 for_each_intel_plane_mask(&dev_priv->drm,
3798 intel_plane,
3799 cstate->base.plane_mask) {
d5cdfdf5 3800 wm = &pipe_wm->planes[intel_plane->id];
a62163e9
L		 3801
3802 for (level = 0; level <= max_level; level++) {
3803 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3804 intel_plane, level,
3805 &wm->wm[level]);
3806 if (ret)
3807 return ret;
3808 }
3809 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3810 }
024c9045 3811 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3812
55994c2c 3813 return 0;
2d41c0b5
PB		 3814}
3815
f0f59a00
VS		 3816static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3817 i915_reg_t reg,
16160e3d
DL		 3818 const struct skl_ddb_entry *entry)
3819{
3820 if (entry->end)
3821 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3822 else
3823 I915_WRITE(reg, 0);
3824}
3825
d8c0fafc 3826static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3827 i915_reg_t reg,
3828 const struct skl_wm_level *level)
3829{
3830 uint32_t val = 0;
3831
3832 if (level->plane_en) {
3833 val |= PLANE_WM_EN;
3834 val |= level->plane_res_b;
3835 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3836 }
3837
3838 I915_WRITE(reg, val);
3839}
3840
d9348dec
VS		 3841static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3842 const struct skl_plane_wm *wm,
3843 const struct skl_ddb_allocation *ddb,
d5cdfdf5 3844 enum plane_id plane_id)
62e0fb88
L		 3845{
3846 struct drm_crtc *crtc = &intel_crtc->base;
3847 struct drm_device *dev = crtc->dev;
3848 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3849 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3850 enum pipe pipe = intel_crtc->pipe;
3851
3852 for (level = 0; level <= max_level; level++) {
d5cdfdf5 3853 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
d8c0fafc 3854 &wm->wm[level]);
62e0fb88 3855 }
d5cdfdf5 3856 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
d8c0fafc 3857 &wm->trans_wm);
27082493 3858
d5cdfdf5
VS		 3859 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
3860 &ddb->plane[pipe][plane_id]);
3861 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
3862 &ddb->y_plane[pipe][plane_id]);
62e0fb88
L		 3863}
3864
d9348dec
VS		 3865static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3866 const struct skl_plane_wm *wm,
3867 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3868{
3869 struct drm_crtc *crtc = &intel_crtc->base;
3870 struct drm_device *dev = crtc->dev;
3871 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3872 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3873 enum pipe pipe = intel_crtc->pipe;
3874
3875 for (level = 0; level <= max_level; level++) {
d8c0fafc 3876 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3877 &wm->wm[level]);
62e0fb88 3878 }
d8c0fafc 3879 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3880
27082493 3881 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3882 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3883}
3884
45ece230 3885bool skl_wm_level_equals(const struct skl_wm_level *l1,
3886 const struct skl_wm_level *l2)
3887{
3888 if (l1->plane_en != l2->plane_en)
3889 return false;
3890
3891 /* If both planes aren't enabled, the rest shouldn't matter */
3892 if (!l1->plane_en)
3893 return true;
3894
3895 return (l1->plane_res_l == l2->plane_res_l &&
3896 l1->plane_res_b == l2->plane_res_b);
3897}
3898
27082493
L		 3899static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3900 const struct skl_ddb_entry *b)
0e8fb7ba 3901{
27082493 3902 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3903}
3904
5eff503b
ML		 3905bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3906 const struct skl_ddb_entry *ddb,
3907 int ignore)
0e8fb7ba 3908{
ce0ba283 3909 int i;
0e8fb7ba 3910
5eff503b
ML		 3911 for (i = 0; i < I915_MAX_PIPES; i++)
3912 if (i != ignore && entries[i] &&
3913 skl_ddb_entries_overlap(ddb, entries[i]))
27082493 3914 return true;
0e8fb7ba 3915
27082493 3916 return false;
0e8fb7ba
DL		 3917}
3918
55994c2c 3919static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
03af79e0 3920 const struct skl_pipe_wm *old_pipe_wm,
55994c2c 3921 struct skl_pipe_wm *pipe_wm, /* out */
03af79e0 3922 struct skl_ddb_allocation *ddb, /* out */
55994c2c 3923 bool *changed /* out */)
2d41c0b5 3924{
f4a96752 3925 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3926 int ret;
2d41c0b5 3927
55994c2c
MR		 3928 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3929 if (ret)
3930 return ret;
2d41c0b5 3931
03af79e0 3932 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3933 *changed = false;
3934 else
3935 *changed = true;
2d41c0b5 3936
55994c2c 3937 return 0;
2d41c0b5
PB		 3938}
3939
9b613022
MR		 3940static uint32_t
3941pipes_modified(struct drm_atomic_state *state)
3942{
3943 struct drm_crtc *crtc;
3944 struct drm_crtc_state *cstate;
3945 uint32_t i, ret = 0;
3946
3947 for_each_crtc_in_state(state, crtc, cstate, i)
3948 ret |= drm_crtc_mask(crtc);
3949
3950 return ret;
3951}
3952
bb7791bd 3953static int
7f60e200
PZ		 3954skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3955{
3956 struct drm_atomic_state *state = cstate->base.state;
3957 struct drm_device *dev = state->dev;
3958 struct drm_crtc *crtc = cstate->base.crtc;
3959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960 struct drm_i915_private *dev_priv = to_i915(dev);
3961 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3962 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3963 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3964 struct drm_plane_state *plane_state;
3965 struct drm_plane *plane;
3966 enum pipe pipe = intel_crtc->pipe;
7f60e200
PZ		 3967
3968 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3969
220b0965 3970 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
d5cdfdf5 3971 enum plane_id plane_id = to_intel_plane(plane)->id;
7f60e200 3972
d5cdfdf5
VS		 3973 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
3974 &new_ddb->plane[pipe][plane_id]) &&
3975 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
3976 &new_ddb->y_plane[pipe][plane_id]))
7f60e200
PZ		 3977 continue;
3978
3979 plane_state = drm_atomic_get_plane_state(state, plane);
3980 if (IS_ERR(plane_state))
3981 return PTR_ERR(plane_state);
3982 }
3983
3984 return 0;
3985}
3986
98d39494
MR		 3987static int
3988skl_compute_ddb(struct drm_atomic_state *state)
3989{
3990 struct drm_device *dev = state->dev;
3991 struct drm_i915_private *dev_priv = to_i915(dev);
3992 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3993 struct intel_crtc *intel_crtc;
734fa01f 3994 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3995 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3996 int ret;
3997
3998 /*
3999 * If this is our first atomic update following hardware readout,
4000 * we can't trust the DDB that the BIOS programmed for us. Let's
4001 * pretend that all pipes switched active status so that we'll
4002 * ensure a full DDB recompute.
4003 */
1b54a880
MR		 4004 if (dev_priv->wm.distrust_bios_wm) {
4005 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4006 state->acquire_ctx);
4007 if (ret)
4008 return ret;
4009
98d39494
MR		 4010 intel_state->active_pipe_changes = ~0;
4011
1b54a880
MR		 4012 /*
4013 * We usually only initialize intel_state->active_crtcs if we
4014 * we're doing a modeset; make sure this field is always
4015 * initialized during the sanitization process that happens
4016 * on the first commit too.
4017 */
4018 if (!intel_state->modeset)
4019 intel_state->active_crtcs = dev_priv->active_crtcs;
4020 }
4021
98d39494
MR		 4022 /*
4023 * If the modeset changes which CRTC's are active, we need to
4024 * recompute the DDB allocation for *all* active pipes, even
4025 * those that weren't otherwise being modified in any way by this
4026 * atomic commit. Due to the shrinking of the per-pipe allocations
4027 * when new active CRTC's are added, it's possible for a pipe that
4028 * we were already using and aren't changing at all here to suddenly
4029 * become invalid if its DDB needs exceeds its new allocation.
4030 *
4031 * Note that if we wind up doing a full DDB recompute, we can't let
4032 * any other display updates race with this transaction, so we need
4033 * to grab the lock on *all* CRTC's.
4034 */
734fa01f 4035 if (intel_state->active_pipe_changes) {
98d39494 4036 realloc_pipes = ~0;
734fa01f
MR		 4037 intel_state->wm_results.dirty_pipes = ~0;
4038 }
98d39494 4039
5a920b85
PZ		 4040 /*
4041 * We're not recomputing for the pipes not included in the commit, so
4042 * make sure we start with the current state.
4043 */
4044 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4045
98d39494
MR		 4046 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4047 struct intel_crtc_state *cstate;
4048
4049 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4050 if (IS_ERR(cstate))
4051 return PTR_ERR(cstate);
4052
734fa01f 4053 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4054 if (ret)
4055 return ret;
05a76d3d 4056
7f60e200 4057 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4058 if (ret)
4059 return ret;
98d39494
MR		 4060 }
4061
4062 return 0;
4063}
4064
2722efb9
MR		 4065static void
4066skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4067 struct skl_wm_values *src,
4068 enum pipe pipe)
4069{
2722efb9
MR		 4070 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4071 sizeof(dst->ddb.y_plane[pipe]));
4072 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4073 sizeof(dst->ddb.plane[pipe]));
4074}
4075
413fc530 4076static void
4077skl_print_wm_changes(const struct drm_atomic_state *state)
4078{
4079 const struct drm_device *dev = state->dev;
4080 const struct drm_i915_private *dev_priv = to_i915(dev);
4081 const struct intel_atomic_state *intel_state =
4082 to_intel_atomic_state(state);
4083 const struct drm_crtc *crtc;
4084 const struct drm_crtc_state *cstate;
413fc530 4085 const struct intel_plane *intel_plane;
413fc530 4086 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4087 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
7570498e 4088 int i;
413fc530 4089
4090 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4091 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4092 enum pipe pipe = intel_crtc->pipe;
413fc530 4093
7570498e 4094 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
d5cdfdf5 4095 enum plane_id plane_id = intel_plane->id;
413fc530 4096 const struct skl_ddb_entry *old, *new;
4097
d5cdfdf5
VS		 4098 old = &old_ddb->plane[pipe][plane_id];
4099 new = &new_ddb->plane[pipe][plane_id];
413fc530 4100
413fc530 4101 if (skl_ddb_entry_equal(old, new))
4102 continue;
4103
7570498e
ML		 4104 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4105 intel_plane->base.base.id,
4106 intel_plane->base.name,
4107 old->start, old->end,
4108 new->start, new->end);
413fc530 4109 }
4110 }
4111}
4112
98d39494
MR		 4113static int
4114skl_compute_wm(struct drm_atomic_state *state)
4115{
4116 struct drm_crtc *crtc;
4117 struct drm_crtc_state *cstate;
734fa01f
MR		 4118 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4119 struct skl_wm_values *results = &intel_state->wm_results;
4120 struct skl_pipe_wm *pipe_wm;
98d39494 4121 bool changed = false;
734fa01f 4122 int ret, i;
98d39494
MR		 4123
4124 /*
4125 * If this transaction isn't actually touching any CRTC's, don't
4126 * bother with watermark calculation. Note that if we pass this
4127 * test, we're guaranteed to hold at least one CRTC state mutex,
4128 * which means we can safely use values like dev_priv->active_crtcs
4129 * since any racing commits that want to update them would need to
4130 * hold _all_ CRTC state mutexes.
4131 */
4132 for_each_crtc_in_state(state, crtc, cstate, i)
4133 changed = true;
4134 if (!changed)
4135 return 0;
4136
734fa01f
MR		 4137 /* Clear all dirty flags */
4138 results->dirty_pipes = 0;
4139
98d39494
MR		 4140 ret = skl_compute_ddb(state);
4141 if (ret)
4142 return ret;
4143
734fa01f
MR		 4144 /*
4145 * Calculate WM's for all pipes that are part of this transaction.
4146 * Note that the DDB allocation above may have added more CRTC's that
4147 * weren't otherwise being modified (and set bits in dirty_pipes) if
4148 * pipe allocations had to change.
4149 *
4150 * FIXME: Now that we're doing this in the atomic check phase, we
4151 * should allow skl_update_pipe_wm() to return failure in cases where
4152 * no suitable watermark values can be found.
4153 */
4154 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4155 struct intel_crtc_state *intel_cstate =
4156 to_intel_crtc_state(cstate);
03af79e0
ML		 4157 const struct skl_pipe_wm *old_pipe_wm =
4158 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
734fa01f
MR		 4159
4160 pipe_wm = &intel_cstate->wm.skl.optimal;
03af79e0
ML		 4161 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4162 &results->ddb, &changed);
734fa01f
MR		 4163 if (ret)
4164 return ret;
4165
4166 if (changed)
4167 results->dirty_pipes |= drm_crtc_mask(crtc);
4168
4169 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4170 /* This pipe's WM's did not change */
4171 continue;
4172
4173 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4174 }
4175
413fc530 4176 skl_print_wm_changes(state);
4177
98d39494
MR		 4178 return 0;
4179}
4180
ccf010fb
ML		 4181static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4182 struct intel_crtc_state *cstate)
4183{
4184 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4185 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4186 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
e62929b3 4187 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
ccf010fb 4188 enum pipe pipe = crtc->pipe;
d5cdfdf5 4189 enum plane_id plane_id;
e62929b3
ML		 4190
4191 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4192 return;
ccf010fb
ML		 4193
4194 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
e62929b3 4195
d5cdfdf5
VS		 4196 for_each_plane_id_on_crtc(crtc, plane_id) {
4197 if (plane_id != PLANE_CURSOR)
4198 skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id],
4199 ddb, plane_id);
4200 else
4201 skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id],
4202 ddb);
4203 }
ccf010fb
ML		 4204}
4205
e62929b3
ML		 4206static void skl_initial_wm(struct intel_atomic_state *state,
4207 struct intel_crtc_state *cstate)
2d41c0b5 4208{
e62929b3 4209 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
432081bc 4210 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4211 struct drm_i915_private *dev_priv = to_i915(dev);
e62929b3 4212 struct skl_wm_values *results = &state->wm_results;
2722efb9 4213 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
27082493 4214 enum pipe pipe = intel_crtc->pipe;
adda50b8 4215
432081bc 4216 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
2d41c0b5
PB		 4217 return;
4218
734fa01f 4219 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4220
e62929b3
ML		 4221 if (cstate->base.active_changed)
4222 skl_atomic_update_crtc_wm(state, cstate);
27082493
L		 4223
4224 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4225
4226 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4227}
4228
d890565c
VS		 4229static void ilk_compute_wm_config(struct drm_device *dev,
4230 struct intel_wm_config *config)
4231{
4232 struct intel_crtc *crtc;
4233
4234 /* Compute the currently _active_ config */
4235 for_each_intel_crtc(dev, crtc) {
4236 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4237
4238 if (!wm->pipe_enabled)
4239 continue;
4240
4241 config->sprites_enabled |= wm->sprites_enabled;
4242 config->sprites_scaled |= wm->sprites_scaled;
4243 config->num_pipes_active++;
4244 }
4245}
4246
ed4a6a7c 4247static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4248{
91c8a326 4249 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4250 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4251 struct ilk_wm_maximums max;
d890565c 4252 struct intel_wm_config config = {};
820c1980 4253 struct ilk_wm_values results = {};
77c122bc 4254 enum intel_ddb_partitioning partitioning;
261a27d1 4255
d890565c
VS		 4256 ilk_compute_wm_config(dev, &config);
4257
4258 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4259 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4260
4261 /* 5/6 split only in single pipe config on IVB+ */
175fded1 4262 if (INTEL_GEN(dev_priv) >= 7 &&
d890565c
VS		 4263 config.num_pipes_active == 1 && config.sprites_enabled) {
4264 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4265 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4266
820c1980 4267 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4268 } else {
198a1e9b 4269 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4270 }
4271
198a1e9b 4272 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4273 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4274
820c1980 4275 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4276
820c1980 4277 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4278}
4279
ccf010fb
ML		 4280static void ilk_initial_watermarks(struct intel_atomic_state *state,
4281 struct intel_crtc_state *cstate)
b9d5c839 4282{
ed4a6a7c
MR		 4283 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4284 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4285
ed4a6a7c 4286 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4287 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4288 ilk_program_watermarks(dev_priv);
4289 mutex_unlock(&dev_priv->wm.wm_mutex);
4290}
bf220452 4291
ccf010fb
ML		 4292static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4293 struct intel_crtc_state *cstate)
ed4a6a7c
MR		 4294{
4295 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4296 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4297
ed4a6a7c
MR		 4298 mutex_lock(&dev_priv->wm.wm_mutex);
4299 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4300 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4301 ilk_program_watermarks(dev_priv);
4302 }
4303 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4304}
4305
d8c0fafc 4306static inline void skl_wm_level_from_reg_val(uint32_t val,
4307 struct skl_wm_level *level)
3078999f 4308{
d8c0fafc 4309 level->plane_en = val & PLANE_WM_EN;
4310 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4311 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4312 PLANE_WM_LINES_MASK;
3078999f
PB		 4313}
4314
bf9d99ad 4315void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4316 struct skl_pipe_wm *out)
3078999f 4317{
d5cdfdf5 4318 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3078999f 4319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3078999f 4320 enum pipe pipe = intel_crtc->pipe;
d5cdfdf5
VS		 4321 int level, max_level;
4322 enum plane_id plane_id;
d8c0fafc 4323 uint32_t val;
3078999f 4324
5db94019 4325 max_level = ilk_wm_max_level(dev_priv);
3078999f 4326
d5cdfdf5
VS		 4327 for_each_plane_id_on_crtc(intel_crtc, plane_id) {
4328 struct skl_plane_wm *wm = &out->planes[plane_id];
3078999f 4329
d8c0fafc 4330 for (level = 0; level <= max_level; level++) {
d5cdfdf5
VS		 4331 if (plane_id != PLANE_CURSOR)
4332 val = I915_READ(PLANE_WM(pipe, plane_id, level));
d8c0fafc 4333 else
4334 val = I915_READ(CUR_WM(pipe, level));
3078999f 4335
d8c0fafc 4336 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4337 }
3078999f 4338
d5cdfdf5
VS		 4339 if (plane_id != PLANE_CURSOR)
4340 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
d8c0fafc 4341 else
4342 val = I915_READ(CUR_WM_TRANS(pipe));
4343
4344 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4345 }
4346
d8c0fafc 4347 if (!intel_crtc->active)
4348 return;
4e0963c7 4349
bf9d99ad 4350 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4351}
4352
4353void skl_wm_get_hw_state(struct drm_device *dev)
4354{
fac5e23e 4355 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4356 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4357 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4358 struct drm_crtc *crtc;
bf9d99ad 4359 struct intel_crtc *intel_crtc;
4360 struct intel_crtc_state *cstate;
3078999f 4361
a269c583 4362 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4363 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4364 intel_crtc = to_intel_crtc(crtc);
4365 cstate = to_intel_crtc_state(crtc->state);
4366
4367 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4368
03af79e0 4369 if (intel_crtc->active)
bf9d99ad 4370 hw->dirty_pipes |= drm_crtc_mask(crtc);
bf9d99ad 4371 }
a1de91e5 4372
279e99d7
MR		 4373 if (dev_priv->active_crtcs) {
4374 /* Fully recompute DDB on first atomic commit */
4375 dev_priv->wm.distrust_bios_wm = true;
4376 } else {
4377 /* Easy/common case; just sanitize DDB now if everything off */
4378 memset(ddb, 0, sizeof(*ddb));
4379 }
3078999f
PB		 4380}
4381
243e6a44
VS		 4382static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4383{
4384 struct drm_device *dev = crtc->dev;
fac5e23e 4385 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4386 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4388 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4389 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4390 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4391 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4392 [PIPE_A] = WM0_PIPEA_ILK,
4393 [PIPE_B] = WM0_PIPEB_ILK,
4394 [PIPE_C] = WM0_PIPEC_IVB,
4395 };
4396
4397 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4398 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4399 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4400
15606534
VS		 4401 memset(active, 0, sizeof(*active));
4402
3ef00284 4403 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4404
4405 if (active->pipe_enabled) {
243e6a44
VS		 4406 u32 tmp = hw->wm_pipe[pipe];
4407
4408 /*
4409 * For active pipes LP0 watermark is marked as
4410 * enabled, and LP1+ watermaks as disabled since
4411 * we can't really reverse compute them in case
4412 * multiple pipes are active.
4413 */
4414 active->wm[0].enable = true;
4415 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4416 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4417 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4418 active->linetime = hw->wm_linetime[pipe];
4419 } else {
5db94019 4420 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4421
4422 /*
4423 * For inactive pipes, all watermark levels
4424 * should be marked as enabled but zeroed,
4425 * which is what we'd compute them to.
4426 */
4427 for (level = 0; level <= max_level; level++)
4428 active->wm[level].enable = true;
4429 }
4e0963c7
MR		 4430
4431 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4432}
4433
6eb1a681
VS		 4434#define _FW_WM(value, plane) \
4435 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4436#define _FW_WM_VLV(value, plane) \
4437 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4438
4439static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4440 struct vlv_wm_values *wm)
4441{
4442 enum pipe pipe;
4443 uint32_t tmp;
4444
4445 for_each_pipe(dev_priv, pipe) {
4446 tmp = I915_READ(VLV_DDL(pipe));
4447
1b31389c 4448 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6eb1a681 4449 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
1b31389c 4450 wm->ddl[pipe].plane[PLANE_CURSOR] =
6eb1a681 4451 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
1b31389c 4452 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6eb1a681 4453 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
1b31389c 4454 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6eb1a681
VS		 4455 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4456 }
4457
4458 tmp = I915_READ(DSPFW1);
4459 wm->sr.plane = _FW_WM(tmp, SR);
1b31389c
VS		 4460 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
4461 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
4462 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6eb1a681
VS		 4463
4464 tmp = I915_READ(DSPFW2);
1b31389c
VS		 4465 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
4466 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
4467 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6eb1a681
VS		 4468
4469 tmp = I915_READ(DSPFW3);
4470 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4471
4472 if (IS_CHERRYVIEW(dev_priv)) {
4473 tmp = I915_READ(DSPFW7_CHV);
1b31389c
VS		 4474 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4475 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6eb1a681
VS		 4476
4477 tmp = I915_READ(DSPFW8_CHV);
1b31389c
VS		 4478 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
4479 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6eb1a681
VS		 4480
4481 tmp = I915_READ(DSPFW9_CHV);
1b31389c
VS		 4482 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
4483 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6eb1a681
VS		 4484
4485 tmp = I915_READ(DSPHOWM);
4486 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
1b31389c
VS		 4487 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4488 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4489 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
4490 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4491 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4492 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4493 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4494 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4495 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6eb1a681
VS		 4496 } else {
4497 tmp = I915_READ(DSPFW7);
1b31389c
VS		 4498 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
4499 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6eb1a681
VS		 4500
4501 tmp = I915_READ(DSPHOWM);
4502 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
1b31389c
VS		 4503 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4504 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4505 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
4506 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4507 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4508 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6eb1a681
VS		 4509 }
4510}
4511
4512#undef _FW_WM
4513#undef _FW_WM_VLV
4514
4515void vlv_wm_get_hw_state(struct drm_device *dev)
4516{
4517 struct drm_i915_private *dev_priv = to_i915(dev);
4518 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4519 struct intel_plane *plane;
4520 enum pipe pipe;
4521 u32 val;
4522
4523 vlv_read_wm_values(dev_priv, wm);
4524
49845a23
VS		 4525 for_each_intel_plane(dev, plane)
4526 plane->wm.fifo_size = vlv_get_fifo_size(plane);
6eb1a681
VS		 4527
4528 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4529 wm->level = VLV_WM_LEVEL_PM2;
4530
4531 if (IS_CHERRYVIEW(dev_priv)) {
4532 mutex_lock(&dev_priv->rps.hw_lock);
4533
4534 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4535 if (val & DSP_MAXFIFO_PM5_ENABLE)
4536 wm->level = VLV_WM_LEVEL_PM5;
4537
58590c14
VS		 4538 /*
4539 * If DDR DVFS is disabled in the BIOS, Punit
4540 * will never ack the request. So if that happens
4541 * assume we don't have to enable/disable DDR DVFS
4542 * dynamically. To test that just set the REQ_ACK
4543 * bit to poke the Punit, but don't change the
4544 * HIGH/LOW bits so that we don't actually change
4545 * the current state.
4546 */
6eb1a681 4547 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4548 val |= FORCE_DDR_FREQ_REQ_ACK;
4549 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4550
4551 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4552 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4553 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4554 "assuming DDR DVFS is disabled\n");
4555 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4556 } else {
4557 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4558 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4559 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4560 }
6eb1a681
VS		 4561
4562 mutex_unlock(&dev_priv->rps.hw_lock);
4563 }
4564
4565 for_each_pipe(dev_priv, pipe)
4566 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
1b31389c
VS		 4567 pipe_name(pipe),
4568 wm->pipe[pipe].plane[PLANE_PRIMARY],
4569 wm->pipe[pipe].plane[PLANE_CURSOR],
4570 wm->pipe[pipe].plane[PLANE_SPRITE0],
4571 wm->pipe[pipe].plane[PLANE_SPRITE1]);
6eb1a681
VS		 4572
4573 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4574 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4575}
4576
243e6a44
VS		 4577void ilk_wm_get_hw_state(struct drm_device *dev)
4578{
fac5e23e 4579 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4580 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4581 struct drm_crtc *crtc;
4582
70e1e0ec 4583 for_each_crtc(dev, crtc)
243e6a44
VS		 4584 ilk_pipe_wm_get_hw_state(crtc);
4585
4586 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4587 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4588 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4589
4590 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
175fded1 4591 if (INTEL_GEN(dev_priv) >= 7) {
cfa7698b
VS		 4592 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4593 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4594 }
243e6a44 4595
8652744b 4596 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4597 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4598 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4599 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4600 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4601 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4602
4603 hw->enable_fbc_wm =
4604 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4605}
4606
b445e3b0
ED		 4607/**
4608 * intel_update_watermarks - update FIFO watermark values based on current modes
4609 *
4610 * Calculate watermark values for the various WM regs based on current mode
4611 * and plane configuration.
4612 *
4613 * There are several cases to deal with here:
4614 * - normal (i.e. non-self-refresh)
4615 * - self-refresh (SR) mode
4616 * - lines are large relative to FIFO size (buffer can hold up to 2)
4617 * - lines are small relative to FIFO size (buffer can hold more than 2
4618 * lines), so need to account for TLB latency
4619 *
4620 * The normal calculation is:
4621 * watermark = dotclock * bytes per pixel * latency
4622 * where latency is platform & configuration dependent (we assume pessimal
4623 * values here).
4624 *
4625 * The SR calculation is:
4626 * watermark = (trunc(latency/line time)+1) * surface width *
4627 * bytes per pixel
4628 * where
4629 * line time = htotal / dotclock
4630 * surface width = hdisplay for normal plane and 64 for cursor
4631 * and latency is assumed to be high, as above.
4632 *
4633 * The final value programmed to the register should always be rounded up,
4634 * and include an extra 2 entries to account for clock crossings.
4635 *
4636 * We don't use the sprite, so we can ignore that. And on Crestline we have
4637 * to set the non-SR watermarks to 8.
4638 */
432081bc 4639void intel_update_watermarks(struct intel_crtc *crtc)
b445e3b0 4640{
432081bc 4641 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0
ED		 4642
4643 if (dev_priv->display.update_wm)
46ba614c 4644 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4645}
4646
e2828914 4647/*
9270388e 4648 * Lock protecting IPS related data structures
9270388e
DV		 4649 */
4650DEFINE_SPINLOCK(mchdev_lock);
4651
4652/* Global for IPS driver to get at the current i915 device. Protected by
4653 * mchdev_lock. */
4654static struct drm_i915_private *i915_mch_dev;
4655
91d14251 4656bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4657{
2b4e57bd
ED		 4658 u16 rgvswctl;
4659
9270388e
DV		 4660 assert_spin_locked(&mchdev_lock);
4661
2b4e57bd
ED		 4662 rgvswctl = I915_READ16(MEMSWCTL);
4663 if (rgvswctl & MEMCTL_CMD_STS) {
4664 DRM_DEBUG("gpu busy, RCS change rejected\n");
4665 return false; /* still busy with another command */
4666 }
4667
4668 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4669 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4670 I915_WRITE16(MEMSWCTL, rgvswctl);
4671 POSTING_READ16(MEMSWCTL);
4672
4673 rgvswctl |= MEMCTL_CMD_STS;
4674 I915_WRITE16(MEMSWCTL, rgvswctl);
4675
4676 return true;
4677}
4678
91d14251 4679static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4680{
84f1b20f 4681 u32 rgvmodectl;
2b4e57bd
ED		 4682 u8 fmax, fmin, fstart, vstart;
4683
9270388e
DV		 4684 spin_lock_irq(&mchdev_lock);
4685
84f1b20f
TU		 4686 rgvmodectl = I915_READ(MEMMODECTL);
4687
2b4e57bd
ED		 4688 /* Enable temp reporting */
4689 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4690 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4691
4692 /* 100ms RC evaluation intervals */
4693 I915_WRITE(RCUPEI, 100000);
4694 I915_WRITE(RCDNEI, 100000);
4695
4696 /* Set max/min thresholds to 90ms and 80ms respectively */
4697 I915_WRITE(RCBMAXAVG, 90000);
4698 I915_WRITE(RCBMINAVG, 80000);
4699
4700 I915_WRITE(MEMIHYST, 1);
4701
4702 /* Set up min, max, and cur for interrupt handling */
4703 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4704 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4705 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4706 MEMMODE_FSTART_SHIFT;
4707
616847e7 4708 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4709 PXVFREQ_PX_SHIFT;
4710
20e4d407
DV		 4711 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4712 dev_priv->ips.fstart = fstart;
2b4e57bd 4713
20e4d407
DV		 4714 dev_priv->ips.max_delay = fstart;
4715 dev_priv->ips.min_delay = fmin;
4716 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4717
4718 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4719 fmax, fmin, fstart);
4720
4721 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4722
4723 /*
4724 * Interrupts will be enabled in ironlake_irq_postinstall
4725 */
4726
4727 I915_WRITE(VIDSTART, vstart);
4728 POSTING_READ(VIDSTART);
4729
4730 rgvmodectl |= MEMMODE_SWMODE_EN;
4731 I915_WRITE(MEMMODECTL, rgvmodectl);
4732
9270388e 4733 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4734 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4735 mdelay(1);
2b4e57bd 4736
91d14251 4737 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4738
7d81c3e0
VS		 4739 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4740 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4741 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4742 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4743 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4744
4745 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4746}
4747
91d14251 4748static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4749{
9270388e
DV		 4750 u16 rgvswctl;
4751
4752 spin_lock_irq(&mchdev_lock);
4753
4754 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4755
4756 /* Ack interrupts, disable EFC interrupt */
4757 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4758 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4759 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4760 I915_WRITE(DEIIR, DE_PCU_EVENT);
4761 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4762
4763 /* Go back to the starting frequency */
91d14251 4764 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4765 mdelay(1);
2b4e57bd
ED		 4766 rgvswctl |= MEMCTL_CMD_STS;
4767 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4768 mdelay(1);
2b4e57bd 4769
9270388e 4770 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4771}
4772
acbe9475
DV		 4773/* There's a funny hw issue where the hw returns all 0 when reading from
4774 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4775 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4776 * all limits and the gpu stuck at whatever frequency it is at atm).
4777 */
74ef1173 4778static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4779{
7b9e0ae6 4780 u32 limits;
2b4e57bd 4781
20b46e59
DV		 4782 /* Only set the down limit when we've reached the lowest level to avoid
4783 * getting more interrupts, otherwise leave this clear. This prevents a
4784 * race in the hw when coming out of rc6: There's a tiny window where
4785 * the hw runs at the minimal clock before selecting the desired
4786 * frequency, if the down threshold expires in that window we will not
4787 * receive a down interrupt. */
2d1fe073 4788 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4789 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4790 if (val <= dev_priv->rps.min_freq_softlimit)
4791 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4792 } else {
4793 limits = dev_priv->rps.max_freq_softlimit << 24;
4794 if (val <= dev_priv->rps.min_freq_softlimit)
4795 limits |= dev_priv->rps.min_freq_softlimit << 16;
4796 }
20b46e59
DV		 4797
4798 return limits;
4799}
4800
dd75fdc8
CW		 4801static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4802{
4803 int new_power;
8a586437
AG		 4804 u32 threshold_up = 0, threshold_down = 0; /* in % */
4805 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4806
4807 new_power = dev_priv->rps.power;
4808 switch (dev_priv->rps.power) {
4809 case LOW_POWER:
a72b5623
CW		 4810 if (val > dev_priv->rps.efficient_freq + 1 &&
4811 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4812 new_power = BETWEEN;
4813 break;
4814
4815 case BETWEEN:
a72b5623
CW		 4816 if (val <= dev_priv->rps.efficient_freq &&
4817 val < dev_priv->rps.cur_freq)
dd75fdc8 4818 new_power = LOW_POWER;
a72b5623
CW		 4819 else if (val >= dev_priv->rps.rp0_freq &&
4820 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4821 new_power = HIGH_POWER;
4822 break;
4823
4824 case HIGH_POWER:
a72b5623
CW		 4825 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4826 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4827 new_power = BETWEEN;
4828 break;
4829 }
4830 /* Max/min bins are special */
aed242ff 4831 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4832 new_power = LOW_POWER;
aed242ff 4833 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4834 new_power = HIGH_POWER;
4835 if (new_power == dev_priv->rps.power)
4836 return;
4837
4838 /* Note the units here are not exactly 1us, but 1280ns. */
4839 switch (new_power) {
4840 case LOW_POWER:
4841 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4842 ei_up = 16000;
4843 threshold_up = 95;
dd75fdc8
CW		 4844
4845 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4846 ei_down = 32000;
4847 threshold_down = 85;
dd75fdc8
CW		 4848 break;
4849
4850 case BETWEEN:
4851 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4852 ei_up = 13000;
4853 threshold_up = 90;
dd75fdc8
CW		 4854
4855 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4856 ei_down = 32000;
4857 threshold_down = 75;
dd75fdc8
CW		 4858 break;
4859
4860 case HIGH_POWER:
4861 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4862 ei_up = 10000;
4863 threshold_up = 85;
dd75fdc8
CW		 4864
4865 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4866 ei_down = 32000;
4867 threshold_down = 60;
dd75fdc8
CW		 4868 break;
4869 }
4870
8a586437 4871 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4872 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4873 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4874 GT_INTERVAL_FROM_US(dev_priv,
4875 ei_up * threshold_up / 100));
8a586437
AG		 4876
4877 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4878 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4879 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4880 GT_INTERVAL_FROM_US(dev_priv,
4881 ei_down * threshold_down / 100));
4882
4883 I915_WRITE(GEN6_RP_CONTROL,
4884 GEN6_RP_MEDIA_TURBO |
4885 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4886 GEN6_RP_MEDIA_IS_GFX |
4887 GEN6_RP_ENABLE |
4888 GEN6_RP_UP_BUSY_AVG |
4889 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4890
dd75fdc8 4891 dev_priv->rps.power = new_power;
8fb55197
CW		 4892 dev_priv->rps.up_threshold = threshold_up;
4893 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4894 dev_priv->rps.last_adj = 0;
4895}
4896
2876ce73
CW		 4897static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4898{
4899 u32 mask = 0;
4900
4901 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4902 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4903 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4904 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4905
7b3c29f6
CW		 4906 mask &= dev_priv->pm_rps_events;
4907
59d02a1f 4908 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4909}
4910
b8a5ff8d
JM		 4911/* gen6_set_rps is called to update the frequency request, but should also be
4912 * called when the range (min_delay and max_delay) is modified so that we can
4913 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4914static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4915{
23eafea6 4916 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4917 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4918 return;
4919
4fc688ce 4920 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4921 WARN_ON(val > dev_priv->rps.max_freq);
4922 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4923
eb64cad1
CW		 4924 /* min/max delay may still have been modified so be sure to
4925 * write the limits value.
4926 */
4927 if (val != dev_priv->rps.cur_freq) {
4928 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4929
dc97997a 4930 if (IS_GEN9(dev_priv))
5704195c
AG		 4931 I915_WRITE(GEN6_RPNSWREQ,
4932 GEN9_FREQUENCY(val));
dc97997a 4933 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4934 I915_WRITE(GEN6_RPNSWREQ,
4935 HSW_FREQUENCY(val));
4936 else
4937 I915_WRITE(GEN6_RPNSWREQ,
4938 GEN6_FREQUENCY(val) |
4939 GEN6_OFFSET(0) |
4940 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4941 }
7b9e0ae6 4942
7b9e0ae6
CW		 4943 /* Make sure we continue to get interrupts
4944 * until we hit the minimum or maximum frequencies.
4945 */
74ef1173 4946 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4947 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4948
d5570a72
BW		 4949 POSTING_READ(GEN6_RPNSWREQ);
4950
b39fb297 4951 dev_priv->rps.cur_freq = val;
0f94592e 4952 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4953}
4954
dc97997a 4955static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4956{
ffe02b40 4957 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4958 WARN_ON(val > dev_priv->rps.max_freq);
4959 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4960
dc97997a 4961 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4962 "Odd GPU freq value\n"))
4963 val &= ~1;
4964
cd25dd5b
D		 4965 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4966
8fb55197 4967 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4968 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4969 if (!IS_CHERRYVIEW(dev_priv))
4970 gen6_set_rps_thresholds(dev_priv, val);
4971 }
ffe02b40 4972
ffe02b40
VS		 4973 dev_priv->rps.cur_freq = val;
4974 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4975}
4976
a7f6e231 4977/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4978 *
4979 * * If Gfx is Idle, then
a7f6e231
D		 4980 * 1. Forcewake Media well.
4981 * 2. Request idle freq.
4982 * 3. Release Forcewake of Media well.
76c3552f
D		 4983*/
4984static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4985{
aed242ff 4986 u32 val = dev_priv->rps.idle_freq;
5549d25f 4987
aed242ff 4988 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4989 return;
4990
a7f6e231
D		 4991 /* Wake up the media well, as that takes a lot less
4992 * power than the Render well. */
4993 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4994 valleyview_set_rps(dev_priv, val);
a7f6e231 4995 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4996}
4997
43cf3bf0
CW		 4998void gen6_rps_busy(struct drm_i915_private *dev_priv)
4999{
5000 mutex_lock(&dev_priv->rps.hw_lock);
5001 if (dev_priv->rps.enabled) {
5002 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5003 gen6_rps_reset_ei(dev_priv);
5004 I915_WRITE(GEN6_PMINTRMSK,
5005 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5006
c33d247d
CW		 5007 gen6_enable_rps_interrupts(dev_priv);
5008
2b83c4c4
MW		 5009 /* Ensure we start at the user's desired frequency */
5010 intel_set_rps(dev_priv,
5011 clamp(dev_priv->rps.cur_freq,
5012 dev_priv->rps.min_freq_softlimit,
5013 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5014 }
5015 mutex_unlock(&dev_priv->rps.hw_lock);
5016}
5017
b29c19b6
CW		 5018void gen6_rps_idle(struct drm_i915_private *dev_priv)
5019{
c33d247d
CW		 5020 /* Flush our bottom-half so that it does not race with us
5021 * setting the idle frequency and so that it is bounded by
5022 * our rpm wakeref. And then disable the interrupts to stop any
5023 * futher RPS reclocking whilst we are asleep.
5024 */
5025 gen6_disable_rps_interrupts(dev_priv);
5026
b29c19b6 5027 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5028 if (dev_priv->rps.enabled) {
dc97997a 5029 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5030 vlv_set_rps_idle(dev_priv);
7526ed79 5031 else
dc97997a 5032 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5033 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5034 I915_WRITE(GEN6_PMINTRMSK,
5035 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5036 }
8d3afd7d 5037 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5038
8d3afd7d 5039 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5040 while (!list_empty(&dev_priv->rps.clients))
5041 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5042 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5043}
5044
1854d5ca 5045void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5046 struct intel_rps_client *rps,
5047 unsigned long submitted)
b29c19b6 5048{
8d3afd7d
CW		 5049 /* This is intentionally racy! We peek at the state here, then
5050 * validate inside the RPS worker.
5051 */
67d97da3 5052 if (!(dev_priv->gt.awake &&
8d3afd7d 5053 dev_priv->rps.enabled &&
29ecd78d 5054 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5055 return;
43cf3bf0 5056
e61b9958
CW		 5057 /* Force a RPS boost (and don't count it against the client) if
5058 * the GPU is severely congested.
5059 */
d0bc54f2 5060 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5061 rps = NULL;
5062
8d3afd7d
CW		 5063 spin_lock(&dev_priv->rps.client_lock);
5064 if (rps == NULL || list_empty(&rps->link)) {
5065 spin_lock_irq(&dev_priv->irq_lock);
5066 if (dev_priv->rps.interrupts_enabled) {
5067 dev_priv->rps.client_boost = true;
c33d247d 5068 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5069 }
5070 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5071
2e1b8730
CW		 5072 if (rps != NULL) {
5073 list_add(&rps->link, &dev_priv->rps.clients);
5074 rps->boosts++;
1854d5ca
CW		 5075 } else
5076 dev_priv->rps.boosts++;
c0951f0c 5077 }
8d3afd7d 5078 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5079}
5080
dc97997a 5081void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5082{
dc97997a
CW		 5083 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5084 valleyview_set_rps(dev_priv, val);
ffe02b40 5085 else
dc97997a 5086 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5087}
5088
dc97997a 5089static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5090{
20e49366 5091 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5092 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5093}
5094
dc97997a 5095static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5096{
2030d684
AG		 5097 I915_WRITE(GEN6_RP_CONTROL, 0);
5098}
5099
dc97997a 5100static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5101{
d20d4f0c 5102 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5103 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5104 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5105}
5106
dc97997a 5107static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5108{
38807746
D		 5109 I915_WRITE(GEN6_RC_CONTROL, 0);
5110}
5111
dc97997a 5112static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5113{
98a2e5f9
D		 5114 /* we're doing forcewake before Disabling RC6,
5115 * This what the BIOS expects when going into suspend */
59bad947 5116 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5117
44fc7d5c 5118 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5119
59bad947 5120 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5121}
5122
dc97997a 5123static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5124{
dc97997a 5125 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5126 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5127 mode = GEN6_RC_CTL_RC6_ENABLE;
5128 else
5129 mode = 0;
5130 }
dc97997a 5131 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5132 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5133 "RC6 %s RC6p %s RC6pp %s\n",
5134 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5135 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5136 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5137
5138 else
b99d49cc
ID		 5139 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5140 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5141}
5142
dc97997a 5143static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5144{
72e96d64 5145 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5146 bool enable_rc6 = true;
5147 unsigned long rc6_ctx_base;
fc619841
ID		 5148 u32 rc_ctl;
5149 int rc_sw_target;
5150
5151 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5152 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5153 RC_SW_TARGET_STATE_SHIFT;
5154 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5155 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5156 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5157 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5158 rc_sw_target);
274008e8
SAK		 5159
5160 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5161 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5162 enable_rc6 = false;
5163 }
5164
5165 /*
5166 * The exact context size is not known for BXT, so assume a page size
5167 * for this check.
5168 */
5169 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5170 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5171 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5172 ggtt->stolen_reserved_size))) {
b99d49cc 5173 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5174 enable_rc6 = false;
5175 }
5176
5177 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5178 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5179 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5180 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5181 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5182 enable_rc6 = false;
5183 }
5184
fc619841
ID		 5185 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5186 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5187 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5188 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5189 enable_rc6 = false;
5190 }
5191
5192 if (!I915_READ(GEN6_GFXPAUSE)) {
5193 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5194 enable_rc6 = false;
5195 }
5196
5197 if (!I915_READ(GEN8_MISC_CTRL0)) {
5198 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5199 enable_rc6 = false;
5200 }
5201
5202 return enable_rc6;
5203}
5204
dc97997a 5205int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5206{
e7d66d89 5207 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5208 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5209 return 0;
5210
274008e8
SAK		 5211 if (!enable_rc6)
5212 return 0;
5213
cc3f90f0 5214 if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5215 DRM_INFO("RC6 disabled by BIOS\n");
5216 return 0;
5217 }
5218
456470eb 5219 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5220 if (enable_rc6 >= 0) {
5221 int mask;
5222
dc97997a 5223 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5224 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5225 INTEL_RC6pp_ENABLE;
5226 else
5227 mask = INTEL_RC6_ENABLE;
5228
5229 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5230 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5231 "(requested %d, valid %d)\n",
5232 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5233
5234 return enable_rc6 & mask;
5235 }
2b4e57bd 5236
dc97997a 5237 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5238 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5239
5240 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5241}
5242
dc97997a 5243static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5244{
5245 /* All of these values are in units of 50MHz */
773ea9a8 5246
93ee2920 5247 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
cc3f90f0 5248 if (IS_GEN9_LP(dev_priv)) {
773ea9a8 5249 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5250 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5251 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5252 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5253 } else {
773ea9a8 5254 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5255 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5256 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5257 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5258 }
3280e8b0 5259 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5260 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5261
93ee2920 5262 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5263 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5264 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5265 u32 ddcc_status = 0;
5266
5267 if (sandybridge_pcode_read(dev_priv,
5268 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5269 &ddcc_status) == 0)
93ee2920 5270 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5271 clamp_t(u8,
5272 ((ddcc_status >> 8) & 0xff),
5273 dev_priv->rps.min_freq,
5274 dev_priv->rps.max_freq);
93ee2920
TR		 5275 }
5276
dc97997a 5277 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5278 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5279 * the natural hardware unit for SKL
5280 */
c5e0688c
AG		 5281 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5282 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5283 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5284 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5285 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5286 }
3280e8b0
BW		 5287}
5288
3a45b05c
CW		 5289static void reset_rps(struct drm_i915_private *dev_priv,
5290 void (*set)(struct drm_i915_private *, u8))
5291{
5292 u8 freq = dev_priv->rps.cur_freq;
5293
5294 /* force a reset */
5295 dev_priv->rps.power = -1;
5296 dev_priv->rps.cur_freq = -1;
5297
5298 set(dev_priv, freq);
5299}
5300
b6fef0ef 5301/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5302static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5303{
b6fef0ef
JB		 5304 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5305
23eafea6 5306 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5307 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5308 /*
5309 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5310 * clear out the Control register just to avoid inconsitency
5311 * with debugfs interface, which will show Turbo as enabled
5312 * only and that is not expected by the User after adding the
5313 * WaGsvDisableTurbo. Apart from this there is no problem even
5314 * if the Turbo is left enabled in the Control register, as the
5315 * Up/Down interrupts would remain masked.
5316 */
dc97997a 5317 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5318 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5319 return;
5320 }
5321
0beb059a
AG		 5322 /* Program defaults and thresholds for RPS*/
5323 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5324 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5325
5326 /* 1 second timeout*/
5327 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5328 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5329
b6fef0ef 5330 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5331
0beb059a
AG		 5332 /* Leaning on the below call to gen6_set_rps to program/setup the
5333 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5334 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5335 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5336
5337 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5338}
5339
dc97997a 5340static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5341{
e2f80391 5342 struct intel_engine_cs *engine;
3b3f1650 5343 enum intel_engine_id id;
20e49366 5344 uint32_t rc6_mask = 0;
20e49366
ZW		 5345
5346 /* 1a: Software RC state - RC0 */
5347 I915_WRITE(GEN6_RC_STATE, 0);
5348
5349 /* 1b: Get forcewake during program sequence. Although the driver
5350 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5351 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5352
5353 /* 2a: Disable RC states. */
5354 I915_WRITE(GEN6_RC_CONTROL, 0);
5355
5356 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5357
5358 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5359 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5360 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5361 else
5362 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5363 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5364 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5365 for_each_engine(engine, dev_priv, id)
e2f80391 5366 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5367
1a3d1898 5368 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5369 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5370
20e49366 5371 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5372
38c23527
ZW		 5373 /* 2c: Program Coarse Power Gating Policies. */
5374 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5375 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5376
20e49366 5377 /* 3a: Enable RC6 */
dc97997a 5378 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5379 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5380 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5381 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5382 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5383 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5384 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5385 GEN7_RC_CTL_TO_MODE |
5386 rc6_mask);
3e7732a0
SAK		 5387 } else {
5388 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5389 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5390 GEN6_RC_CTL_EI_MODE(1) |
5391 rc6_mask);
3e7732a0 5392 }
20e49366 5393
cb07bae0
SK		 5394 /*
5395 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5396 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5397 */
dc97997a 5398 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5399 I915_WRITE(GEN9_PG_ENABLE, 0);
5400 else
5401 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5402 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5403
59bad947 5404 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5405}
5406
dc97997a 5407static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5408{
e2f80391 5409 struct intel_engine_cs *engine;
3b3f1650 5410 enum intel_engine_id id;
93ee2920 5411 uint32_t rc6_mask = 0;
6edee7f3
BW		 5412
5413 /* 1a: Software RC state - RC0 */
5414 I915_WRITE(GEN6_RC_STATE, 0);
5415
5416 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5417 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5418 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5419
5420 /* 2a: Disable RC states. */
5421 I915_WRITE(GEN6_RC_CONTROL, 0);
5422
6edee7f3
BW		 5423 /* 2b: Program RC6 thresholds.*/
5424 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5425 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5426 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5427 for_each_engine(engine, dev_priv, id)
e2f80391 5428 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5429 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5430 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5431 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5432 else
5433 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5434
5435 /* 3: Enable RC6 */
dc97997a 5436 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5437 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5438 intel_print_rc6_info(dev_priv, rc6_mask);
5439 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5440 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5441 GEN7_RC_CTL_TO_MODE |
5442 rc6_mask);
5443 else
5444 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5445 GEN6_RC_CTL_EI_MODE(1) |
5446 rc6_mask);
6edee7f3
BW		 5447
5448 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5449 I915_WRITE(GEN6_RPNSWREQ,
5450 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5451 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5452 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5453 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5454 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5455
5456 /* Docs recommend 900MHz, and 300 MHz respectively */
5457 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5458 dev_priv->rps.max_freq_softlimit << 24 |
5459 dev_priv->rps.min_freq_softlimit << 16);
5460
5461 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5462 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5463 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5464 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5465
5466 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5467
5468 /* 5: Enable RPS */
7526ed79
DV		 5469 I915_WRITE(GEN6_RP_CONTROL,
5470 GEN6_RP_MEDIA_TURBO |
5471 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5472 GEN6_RP_MEDIA_IS_GFX |
5473 GEN6_RP_ENABLE |
5474 GEN6_RP_UP_BUSY_AVG |
5475 GEN6_RP_DOWN_IDLE_AVG);
5476
5477 /* 6: Ring frequency + overclocking (our driver does this later */
5478
3a45b05c 5479 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5480
59bad947 5481 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5482}
5483
dc97997a 5484static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5485{
e2f80391 5486 struct intel_engine_cs *engine;
3b3f1650 5487 enum intel_engine_id id;
99ac9612 5488 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5489 u32 gtfifodbg;
2b4e57bd 5490 int rc6_mode;
b4ac5afc 5491 int ret;
2b4e57bd 5492
4fc688ce 5493 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5494
2b4e57bd
ED		 5495 /* Here begins a magic sequence of register writes to enable
5496 * auto-downclocking.
5497 *
5498 * Perhaps there might be some value in exposing these to
5499 * userspace...
5500 */
5501 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5502
5503 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5504 gtfifodbg = I915_READ(GTFIFODBG);
5505 if (gtfifodbg) {
2b4e57bd
ED		 5506 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5507 I915_WRITE(GTFIFODBG, gtfifodbg);
5508 }
5509
59bad947 5510 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5511
5512 /* disable the counters and set deterministic thresholds */
5513 I915_WRITE(GEN6_RC_CONTROL, 0);
5514
5515 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5516 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5517 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5518 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5519 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5520
3b3f1650 5521 for_each_engine(engine, dev_priv, id)
e2f80391 5522 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5523
5524 I915_WRITE(GEN6_RC_SLEEP, 0);
5525 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5526 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5527 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5528 else
5529 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5530 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5531 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5532
5a7dc92a 5533 /* Check if we are enabling RC6 */
dc97997a 5534 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5535 if (rc6_mode & INTEL_RC6_ENABLE)
5536 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5537
5a7dc92a 5538 /* We don't use those on Haswell */
dc97997a 5539 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5540 if (rc6_mode & INTEL_RC6p_ENABLE)
5541 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5542
5a7dc92a
ED		 5543 if (rc6_mode & INTEL_RC6pp_ENABLE)
5544 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5545 }
2b4e57bd 5546
dc97997a 5547 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5548
5549 I915_WRITE(GEN6_RC_CONTROL,
5550 rc6_mask |
5551 GEN6_RC_CTL_EI_MODE(1) |
5552 GEN6_RC_CTL_HW_ENABLE);
5553
dd75fdc8
CW		 5554 /* Power down if completely idle for over 50ms */
5555 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5556 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5557
3a45b05c 5558 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5559
31643d54
BW		 5560 rc6vids = 0;
5561 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5562 if (IS_GEN6(dev_priv) && ret) {
31643d54 5563 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5564 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5565 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5566 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5567 rc6vids &= 0xffff00;
5568 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5569 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5570 if (ret)
5571 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5572 }
5573
59bad947 5574 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5575}
5576
fb7404e8 5577static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5578{
5579 int min_freq = 15;
3ebecd07
CW		 5580 unsigned int gpu_freq;
5581 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5582 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5583 int scaling_factor = 180;
eda79642 5584 struct cpufreq_policy *policy;
2b4e57bd 5585
4fc688ce 5586 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5587
eda79642
BW		 5588 policy = cpufreq_cpu_get(0);
5589 if (policy) {
5590 max_ia_freq = policy->cpuinfo.max_freq;
5591 cpufreq_cpu_put(policy);
5592 } else {
5593 /*
5594 * Default to measured freq if none found, PCU will ensure we
5595 * don't go over
5596 */
2b4e57bd 5597 max_ia_freq = tsc_khz;
eda79642 5598 }
2b4e57bd
ED		 5599
5600 /* Convert from kHz to MHz */
5601 max_ia_freq /= 1000;
5602
153b4b95 5603 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5604 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5605 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5606
dc97997a 5607 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5608 /* Convert GT frequency to 50 HZ units */
5609 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5610 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5611 } else {
5612 min_gpu_freq = dev_priv->rps.min_freq;
5613 max_gpu_freq = dev_priv->rps.max_freq;
5614 }
5615
2b4e57bd
ED		 5616 /*
5617 * For each potential GPU frequency, load a ring frequency we'd like
5618 * to use for memory access. We do this by specifying the IA frequency
5619 * the PCU should use as a reference to determine the ring frequency.
5620 */
4c8c7743
AG		 5621 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5622 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5623 unsigned int ia_freq = 0, ring_freq = 0;
5624
dc97997a 5625 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5626 /*
5627 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5628 * No floor required for ring frequency on SKL.
5629 */
5630 ring_freq = gpu_freq;
dc97997a 5631 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5632 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5633 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5634 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5635 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5636 ring_freq = max(min_ring_freq, ring_freq);
5637 /* leave ia_freq as the default, chosen by cpufreq */
5638 } else {
5639 /* On older processors, there is no separate ring
5640 * clock domain, so in order to boost the bandwidth
5641 * of the ring, we need to upclock the CPU (ia_freq).
5642 *
5643 * For GPU frequencies less than 750MHz,
5644 * just use the lowest ring freq.
5645 */
5646 if (gpu_freq < min_freq)
5647 ia_freq = 800;
5648 else
5649 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5650 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5651 }
2b4e57bd 5652
42c0526c
BW		 5653 sandybridge_pcode_write(dev_priv,
5654 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5655 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5656 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5657 gpu_freq);
2b4e57bd 5658 }
2b4e57bd
ED		 5659}
5660
03af2045 5661static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5662{
5663 u32 val, rp0;
5664
5b5929cb 5665 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5666
43b67998 5667 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5668 case 8:
5669 /* (2 * 4) config */
5670 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5671 break;
5672 case 12:
5673 /* (2 * 6) config */
5674 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5675 break;
5676 case 16:
5677 /* (2 * 8) config */
5678 default:
5679 /* Setting (2 * 8) Min RP0 for any other combination */
5680 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5681 break;
095acd5f 5682 }
5b5929cb
JN		 5683
5684 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5685
2b6b3a09
D		 5686 return rp0;
5687}
5688
5689static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5690{
5691 u32 val, rpe;
5692
5693 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5694 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5695
5696 return rpe;
5697}
5698
7707df4a
D		 5699static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5700{
5701 u32 val, rp1;
5702
5b5929cb
JN		 5703 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5704 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5705
7707df4a
D		 5706 return rp1;
5707}
5708
f8f2b001
D		 5709static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5710{
5711 u32 val, rp1;
5712
5713 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5714
5715 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5716
5717 return rp1;
5718}
5719
03af2045 5720static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5721{
5722 u32 val, rp0;
5723
64936258 5724 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5725
5726 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5727 /* Clamp to max */
5728 rp0 = min_t(u32, rp0, 0xea);
5729
5730 return rp0;
5731}
5732
5733static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5734{
5735 u32 val, rpe;
5736
64936258 5737 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5738 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5739 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5740 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5741
5742 return rpe;
5743}
5744
03af2045 5745static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5746{
36146035
ID		 5747 u32 val;
5748
5749 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5750 /*
5751 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5752 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5753 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5754 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5755 * to make sure it matches what Punit accepts.
5756 */
5757 return max_t(u32, val, 0xc0);
0a073b84
JB		 5758}
5759
ae48434c
ID		 5760/* Check that the pctx buffer wasn't move under us. */
5761static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5762{
5763 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5764
5765 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5766 dev_priv->vlv_pctx->stolen->start);
5767}
5768
38807746
D		 5769
5770/* Check that the pcbr address is not empty. */
5771static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5772{
5773 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5774
5775 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5776}
5777
dc97997a 5778static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5779{
62106b4f 5780 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5781 unsigned long pctx_paddr, paddr;
38807746
D		 5782 u32 pcbr;
5783 int pctx_size = 32*1024;
5784
38807746
D		 5785 pcbr = I915_READ(VLV_PCBR);
5786 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5787 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5788 paddr = (dev_priv->mm.stolen_base +
62106b4f 5789 (ggtt->stolen_size - pctx_size));
38807746
D		 5790
5791 pctx_paddr = (paddr & (~4095));
5792 I915_WRITE(VLV_PCBR, pctx_paddr);
5793 }
ce611ef8
VS		 5794
5795 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5796}
5797
dc97997a 5798static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5799{
c9cddffc
JB		 5800 struct drm_i915_gem_object *pctx;
5801 unsigned long pctx_paddr;
5802 u32 pcbr;
5803 int pctx_size = 24*1024;
5804
5805 pcbr = I915_READ(VLV_PCBR);
5806 if (pcbr) {
5807 /* BIOS set it up already, grab the pre-alloc'd space */
5808 int pcbr_offset;
5809
5810 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
187685cb 5811 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv,
c9cddffc 5812 pcbr_offset,
190d6cd5 5813 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5814 pctx_size);
5815 goto out;
5816 }
5817
ce611ef8
VS		 5818 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5819
c9cddffc
JB		 5820 /*
5821 * From the Gunit register HAS:
5822 * The Gfx driver is expected to program this register and ensure
5823 * proper allocation within Gfx stolen memory. For example, this
5824 * register should be programmed such than the PCBR range does not
5825 * overlap with other ranges, such as the frame buffer, protected
5826 * memory, or any other relevant ranges.
5827 */
187685cb 5828 pctx = i915_gem_object_create_stolen(dev_priv, pctx_size);
c9cddffc
JB		 5829 if (!pctx) {
5830 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5831 goto out;
c9cddffc
JB		 5832 }
5833
5834 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5835 I915_WRITE(VLV_PCBR, pctx_paddr);
5836
5837out:
ce611ef8 5838 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5839 dev_priv->vlv_pctx = pctx;
5840}
5841
dc97997a 5842static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5843{
ae48434c
ID		 5844 if (WARN_ON(!dev_priv->vlv_pctx))
5845 return;
5846
f0cd5182 5847 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5848 dev_priv->vlv_pctx = NULL;
5849}
5850
c30fec65
VS		 5851static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5852{
5853 dev_priv->rps.gpll_ref_freq =
5854 vlv_get_cck_clock(dev_priv, "GPLL ref",
5855 CCK_GPLL_CLOCK_CONTROL,
5856 dev_priv->czclk_freq);
5857
5858 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5859 dev_priv->rps.gpll_ref_freq);
5860}
5861
dc97997a 5862static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5863{
2bb25c17 5864 u32 val;
4e80519e 5865
dc97997a 5866 valleyview_setup_pctx(dev_priv);
4e80519e 5867
c30fec65
VS		 5868 vlv_init_gpll_ref_freq(dev_priv);
5869
2bb25c17
VS		 5870 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5871 switch ((val >> 6) & 3) {
5872 case 0:
5873 case 1:
5874 dev_priv->mem_freq = 800;
5875 break;
5876 case 2:
5877 dev_priv->mem_freq = 1066;
5878 break;
5879 case 3:
5880 dev_priv->mem_freq = 1333;
5881 break;
5882 }
80b83b62 5883 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5884
4e80519e
ID		 5885 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5886 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5887 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5888 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5889 dev_priv->rps.max_freq);
5890
5891 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5892 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5893 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5894 dev_priv->rps.efficient_freq);
5895
f8f2b001
D		 5896 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5897 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5898 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5899 dev_priv->rps.rp1_freq);
5900
4e80519e
ID		 5901 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5902 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5903 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5904 dev_priv->rps.min_freq);
4e80519e
ID		 5905}
5906
dc97997a 5907static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5908{
2bb25c17 5909 u32 val;
2b6b3a09 5910
dc97997a 5911 cherryview_setup_pctx(dev_priv);
2b6b3a09 5912
c30fec65
VS		 5913 vlv_init_gpll_ref_freq(dev_priv);
5914
a580516d 5915 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5916 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5917 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5918
2bb25c17 5919 switch ((val >> 2) & 0x7) {
2bb25c17 5920 case 3:
2bb25c17
VS		 5921 dev_priv->mem_freq = 2000;
5922 break;
bfa7df01 5923 default:
2bb25c17
VS		 5924 dev_priv->mem_freq = 1600;
5925 break;
5926 }
80b83b62 5927 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5928
2b6b3a09
D		 5929 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5930 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5931 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5932 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5933 dev_priv->rps.max_freq);
5934
5935 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5936 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5937 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5938 dev_priv->rps.efficient_freq);
5939
7707df4a
D		 5940 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5941 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5942 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5943 dev_priv->rps.rp1_freq);
5944
5b7c91b7
D		 5945 /* PUnit validated range is only [RPe, RP0] */
5946 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5947 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5948 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5949 dev_priv->rps.min_freq);
5950
1c14762d
VS		 5951 WARN_ONCE((dev_priv->rps.max_freq |
5952 dev_priv->rps.efficient_freq |
5953 dev_priv->rps.rp1_freq |
5954 dev_priv->rps.min_freq) & 1,
5955 "Odd GPU freq values\n");
38807746
D		 5956}
5957
dc97997a 5958static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5959{
dc97997a 5960 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5961}
5962
dc97997a 5963static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5964{
e2f80391 5965 struct intel_engine_cs *engine;
3b3f1650 5966 enum intel_engine_id id;
2b6b3a09 5967 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5968
5969 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5970
297b32ec
VS		 5971 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5972 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5973 if (gtfifodbg) {
5974 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5975 gtfifodbg);
5976 I915_WRITE(GTFIFODBG, gtfifodbg);
5977 }
5978
5979 cherryview_check_pctx(dev_priv);
5980
5981 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5982 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5983 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5984
160614a2
VS		 5985 /* Disable RC states. */
5986 I915_WRITE(GEN6_RC_CONTROL, 0);
5987
38807746
D		 5988 /* 2a: Program RC6 thresholds.*/
5989 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5990 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5991 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5992
3b3f1650 5993 for_each_engine(engine, dev_priv, id)
e2f80391 5994 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5995 I915_WRITE(GEN6_RC_SLEEP, 0);
5996
f4f71c7d
D		 5997 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5998 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5999
6000 /* allows RC6 residency counter to work */
6001 I915_WRITE(VLV_COUNTER_CONTROL,
6002 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6003 VLV_MEDIA_RC6_COUNT_EN |
6004 VLV_RENDER_RC6_COUNT_EN));
6005
6006 /* For now we assume BIOS is allocating and populating the PCBR */
6007 pcbr = I915_READ(VLV_PCBR);
6008
38807746 6009 /* 3: Enable RC6 */
dc97997a
CW		 6010 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6011 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6012 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6013
6014 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6015
2b6b3a09 6016 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6017 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6018 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6019 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6020 I915_WRITE(GEN6_RP_UP_EI, 66000);
6021 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6022
6023 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6024
6025 /* 5: Enable RPS */
6026 I915_WRITE(GEN6_RP_CONTROL,
6027 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6028 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6029 GEN6_RP_ENABLE |
6030 GEN6_RP_UP_BUSY_AVG |
6031 GEN6_RP_DOWN_IDLE_AVG);
6032
3ef62342
D		 6033 /* Setting Fixed Bias */
6034 val = VLV_OVERRIDE_EN |
6035 VLV_SOC_TDP_EN |
6036 CHV_BIAS_CPU_50_SOC_50;
6037 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6038
2b6b3a09
D		 6039 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6040
8d40c3ae
VS		 6041 /* RPS code assumes GPLL is used */
6042 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6043
742f491d 6044 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6045 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6046
3a45b05c 6047 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6048
59bad947 6049 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6050}
6051
dc97997a 6052static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6053{
e2f80391 6054 struct intel_engine_cs *engine;
3b3f1650 6055 enum intel_engine_id id;
2a5913a8 6056 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6057
6058 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6059
ae48434c
ID		 6060 valleyview_check_pctx(dev_priv);
6061
297b32ec
VS		 6062 gtfifodbg = I915_READ(GTFIFODBG);
6063 if (gtfifodbg) {
f7d85c1e
JB		 6064 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6065 gtfifodbg);
0a073b84
JB		 6066 I915_WRITE(GTFIFODBG, gtfifodbg);
6067 }
6068
c8d9a590 6069 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6070 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6071
160614a2
VS		 6072 /* Disable RC states. */
6073 I915_WRITE(GEN6_RC_CONTROL, 0);
6074
cad725fe 6075 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6076 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6077 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6078 I915_WRITE(GEN6_RP_UP_EI, 66000);
6079 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6080
6081 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6082
6083 I915_WRITE(GEN6_RP_CONTROL,
6084 GEN6_RP_MEDIA_TURBO |
6085 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6086 GEN6_RP_MEDIA_IS_GFX |
6087 GEN6_RP_ENABLE |
6088 GEN6_RP_UP_BUSY_AVG |
6089 GEN6_RP_DOWN_IDLE_CONT);
6090
6091 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6092 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6093 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6094
3b3f1650 6095 for_each_engine(engine, dev_priv, id)
e2f80391 6096 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6097
2f0aa304 6098 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6099
6100 /* allows RC6 residency counter to work */
49798eb2 6101 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6102 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6103 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6104 VLV_MEDIA_RC6_COUNT_EN |
6105 VLV_RENDER_RC6_COUNT_EN));
31685c25 6106
dc97997a 6107 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6108 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6109
dc97997a 6110 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6111
a2b23fe0 6112 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6113
3ef62342
D		 6114 /* Setting Fixed Bias */
6115 val = VLV_OVERRIDE_EN |
6116 VLV_SOC_TDP_EN |
6117 VLV_BIAS_CPU_125_SOC_875;
6118 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6119
64936258 6120 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6121
8d40c3ae
VS		 6122 /* RPS code assumes GPLL is used */
6123 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6124
742f491d 6125 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6126 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6127
3a45b05c 6128 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6129
59bad947 6130 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6131}
6132
dde18883
ED		 6133static unsigned long intel_pxfreq(u32 vidfreq)
6134{
6135 unsigned long freq;
6136 int div = (vidfreq & 0x3f0000) >> 16;
6137 int post = (vidfreq & 0x3000) >> 12;
6138 int pre = (vidfreq & 0x7);
6139
6140 if (!pre)
6141 return 0;
6142
6143 freq = ((div * 133333) / ((1<<post) * pre));
6144
6145 return freq;
6146}
6147
eb48eb00
DV		 6148static const struct cparams {
6149 u16 i;
6150 u16 t;
6151 u16 m;
6152 u16 c;
6153} cparams[] = {
6154 { 1, 1333, 301, 28664 },
6155 { 1, 1066, 294, 24460 },
6156 { 1, 800, 294, 25192 },
6157 { 0, 1333, 276, 27605 },
6158 { 0, 1066, 276, 27605 },
6159 { 0, 800, 231, 23784 },
6160};
6161
f531dcb2 6162static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6163{
6164 u64 total_count, diff, ret;
6165 u32 count1, count2, count3, m = 0, c = 0;
6166 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6167 int i;
6168
02d71956
DV		 6169 assert_spin_locked(&mchdev_lock);
6170
20e4d407 6171 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6172
6173 /* Prevent division-by-zero if we are asking too fast.
6174 * Also, we don't get interesting results if we are polling
6175 * faster than once in 10ms, so just return the saved value
6176 * in such cases.
6177 */
6178 if (diff1 <= 10)
20e4d407 6179 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6180
6181 count1 = I915_READ(DMIEC);
6182 count2 = I915_READ(DDREC);
6183 count3 = I915_READ(CSIEC);
6184
6185 total_count = count1 + count2 + count3;
6186
6187 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6188 if (total_count < dev_priv->ips.last_count1) {
6189 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6190 diff += total_count;
6191 } else {
20e4d407 6192 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6193 }
6194
6195 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6196 if (cparams[i].i == dev_priv->ips.c_m &&
6197 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6198 m = cparams[i].m;
6199 c = cparams[i].c;
6200 break;
6201 }
6202 }
6203
6204 diff = div_u64(diff, diff1);
6205 ret = ((m * diff) + c);
6206 ret = div_u64(ret, 10);
6207
20e4d407
DV		 6208 dev_priv->ips.last_count1 = total_count;
6209 dev_priv->ips.last_time1 = now;
eb48eb00 6210
20e4d407 6211 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6212
6213 return ret;
6214}
6215
f531dcb2
CW		 6216unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6217{
6218 unsigned long val;
6219
dc97997a 6220 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6221 return 0;
6222
6223 spin_lock_irq(&mchdev_lock);
6224
6225 val = __i915_chipset_val(dev_priv);
6226
6227 spin_unlock_irq(&mchdev_lock);
6228
6229 return val;
6230}
6231
eb48eb00
DV		 6232unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6233{
6234 unsigned long m, x, b;
6235 u32 tsfs;
6236
6237 tsfs = I915_READ(TSFS);
6238
6239 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6240 x = I915_READ8(TR1);
6241
6242 b = tsfs & TSFS_INTR_MASK;
6243
6244 return ((m * x) / 127) - b;
6245}
6246
d972d6ee
MK		 6247static int _pxvid_to_vd(u8 pxvid)
6248{
6249 if (pxvid == 0)
6250 return 0;
6251
6252 if (pxvid >= 8 && pxvid < 31)
6253 pxvid = 31;
6254
6255 return (pxvid + 2) * 125;
6256}
6257
6258static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6259{
d972d6ee
MK		 6260 const int vd = _pxvid_to_vd(pxvid);
6261 const int vm = vd - 1125;
6262
dc97997a 6263 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6264 return vm > 0 ? vm : 0;
6265
6266 return vd;
eb48eb00
DV		 6267}
6268
02d71956 6269static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6270{
5ed0bdf2 6271 u64 now, diff, diffms;
eb48eb00
DV		 6272 u32 count;
6273
02d71956 6274 assert_spin_locked(&mchdev_lock);
eb48eb00 6275
5ed0bdf2
TG		 6276 now = ktime_get_raw_ns();
6277 diffms = now - dev_priv->ips.last_time2;
6278 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6279
6280 /* Don't divide by 0 */
eb48eb00
DV		 6281 if (!diffms)
6282 return;
6283
6284 count = I915_READ(GFXEC);
6285
20e4d407
DV		 6286 if (count < dev_priv->ips.last_count2) {
6287 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6288 diff += count;
6289 } else {
20e4d407 6290 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6291 }
6292
20e4d407
DV		 6293 dev_priv->ips.last_count2 = count;
6294 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6295
6296 /* More magic constants... */
6297 diff = diff * 1181;
6298 diff = div_u64(diff, diffms * 10);
20e4d407 6299 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6300}
6301
02d71956
DV		 6302void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6303{
dc97997a 6304 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6305 return;
6306
9270388e 6307 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6308
6309 __i915_update_gfx_val(dev_priv);
6310
9270388e 6311 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6312}
6313
f531dcb2 6314static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6315{
6316 unsigned long t, corr, state1, corr2, state2;
6317 u32 pxvid, ext_v;
6318
02d71956
DV		 6319 assert_spin_locked(&mchdev_lock);
6320
616847e7 6321 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6322 pxvid = (pxvid >> 24) & 0x7f;
6323 ext_v = pvid_to_extvid(dev_priv, pxvid);
6324
6325 state1 = ext_v;
6326
6327 t = i915_mch_val(dev_priv);
6328
6329 /* Revel in the empirically derived constants */
6330
6331 /* Correction factor in 1/100000 units */
6332 if (t > 80)
6333 corr = ((t * 2349) + 135940);
6334 else if (t >= 50)
6335 corr = ((t * 964) + 29317);
6336 else /* < 50 */
6337 corr = ((t * 301) + 1004);
6338
6339 corr = corr * ((150142 * state1) / 10000 - 78642);
6340 corr /= 100000;
20e4d407 6341 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6342
6343 state2 = (corr2 * state1) / 10000;
6344 state2 /= 100; /* convert to mW */
6345
02d71956 6346 __i915_update_gfx_val(dev_priv);
eb48eb00 6347
20e4d407 6348 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6349}
6350
f531dcb2
CW		 6351unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6352{
6353 unsigned long val;
6354
dc97997a 6355 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6356 return 0;
6357
6358 spin_lock_irq(&mchdev_lock);
6359
6360 val = __i915_gfx_val(dev_priv);
6361
6362 spin_unlock_irq(&mchdev_lock);
6363
6364 return val;
6365}
6366
eb48eb00
DV		 6367/**
6368 * i915_read_mch_val - return value for IPS use
6369 *
6370 * Calculate and return a value for the IPS driver to use when deciding whether
6371 * we have thermal and power headroom to increase CPU or GPU power budget.
6372 */
6373unsigned long i915_read_mch_val(void)
6374{
6375 struct drm_i915_private *dev_priv;
6376 unsigned long chipset_val, graphics_val, ret = 0;
6377
9270388e 6378 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6379 if (!i915_mch_dev)
6380 goto out_unlock;
6381 dev_priv = i915_mch_dev;
6382
f531dcb2
CW		 6383 chipset_val = __i915_chipset_val(dev_priv);
6384 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6385
6386 ret = chipset_val + graphics_val;
6387
6388out_unlock:
9270388e 6389 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6390
6391 return ret;
6392}
6393EXPORT_SYMBOL_GPL(i915_read_mch_val);
6394
6395/**
6396 * i915_gpu_raise - raise GPU frequency limit
6397 *
6398 * Raise the limit; IPS indicates we have thermal headroom.
6399 */
6400bool i915_gpu_raise(void)
6401{
6402 struct drm_i915_private *dev_priv;
6403 bool ret = true;
6404
9270388e 6405 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6406 if (!i915_mch_dev) {
6407 ret = false;
6408 goto out_unlock;
6409 }
6410 dev_priv = i915_mch_dev;
6411
20e4d407
DV		 6412 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6413 dev_priv->ips.max_delay--;
eb48eb00
DV		 6414
6415out_unlock:
9270388e 6416 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6417
6418 return ret;
6419}
6420EXPORT_SYMBOL_GPL(i915_gpu_raise);
6421
6422/**
6423 * i915_gpu_lower - lower GPU frequency limit
6424 *
6425 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6426 * frequency maximum.
6427 */
6428bool i915_gpu_lower(void)
6429{
6430 struct drm_i915_private *dev_priv;
6431 bool ret = true;
6432
9270388e 6433 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6434 if (!i915_mch_dev) {
6435 ret = false;
6436 goto out_unlock;
6437 }
6438 dev_priv = i915_mch_dev;
6439
20e4d407
DV		 6440 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6441 dev_priv->ips.max_delay++;
eb48eb00
DV		 6442
6443out_unlock:
9270388e 6444 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6445
6446 return ret;
6447}
6448EXPORT_SYMBOL_GPL(i915_gpu_lower);
6449
6450/**
6451 * i915_gpu_busy - indicate GPU business to IPS
6452 *
6453 * Tell the IPS driver whether or not the GPU is busy.
6454 */
6455bool i915_gpu_busy(void)
6456{
eb48eb00
DV		 6457 bool ret = false;
6458
9270388e 6459 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6460 if (i915_mch_dev)
6461 ret = i915_mch_dev->gt.awake;
9270388e 6462 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6463
6464 return ret;
6465}
6466EXPORT_SYMBOL_GPL(i915_gpu_busy);
6467
6468/**
6469 * i915_gpu_turbo_disable - disable graphics turbo
6470 *
6471 * Disable graphics turbo by resetting the max frequency and setting the
6472 * current frequency to the default.
6473 */
6474bool i915_gpu_turbo_disable(void)
6475{
6476 struct drm_i915_private *dev_priv;
6477 bool ret = true;
6478
9270388e 6479 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6480 if (!i915_mch_dev) {
6481 ret = false;
6482 goto out_unlock;
6483 }
6484 dev_priv = i915_mch_dev;
6485
20e4d407 6486 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6487
91d14251 6488 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6489 ret = false;
6490
6491out_unlock:
9270388e 6492 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6493
6494 return ret;
6495}
6496EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6497
6498/**
6499 * Tells the intel_ips driver that the i915 driver is now loaded, if
6500 * IPS got loaded first.
6501 *
6502 * This awkward dance is so that neither module has to depend on the
6503 * other in order for IPS to do the appropriate communication of
6504 * GPU turbo limits to i915.
6505 */
6506static void
6507ips_ping_for_i915_load(void)
6508{
6509 void (*link)(void);
6510
6511 link = symbol_get(ips_link_to_i915_driver);
6512 if (link) {
6513 link();
6514 symbol_put(ips_link_to_i915_driver);
6515 }
6516}
6517
6518void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6519{
02d71956
DV		 6520 /* We only register the i915 ips part with intel-ips once everything is
6521 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6522 spin_lock_irq(&mchdev_lock);
eb48eb00 6523 i915_mch_dev = dev_priv;
9270388e 6524 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6525
6526 ips_ping_for_i915_load();
6527}
6528
6529void intel_gpu_ips_teardown(void)
6530{
9270388e 6531 spin_lock_irq(&mchdev_lock);
eb48eb00 6532 i915_mch_dev = NULL;
9270388e 6533 spin_unlock_irq(&mchdev_lock);
eb48eb00 6534}
76c3552f 6535
dc97997a 6536static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6537{
dde18883
ED		 6538 u32 lcfuse;
6539 u8 pxw[16];
6540 int i;
6541
6542 /* Disable to program */
6543 I915_WRITE(ECR, 0);
6544 POSTING_READ(ECR);
6545
6546 /* Program energy weights for various events */
6547 I915_WRITE(SDEW, 0x15040d00);
6548 I915_WRITE(CSIEW0, 0x007f0000);
6549 I915_WRITE(CSIEW1, 0x1e220004);
6550 I915_WRITE(CSIEW2, 0x04000004);
6551
6552 for (i = 0; i < 5; i++)
616847e7 6553 I915_WRITE(PEW(i), 0);
dde18883 6554 for (i = 0; i < 3; i++)
616847e7 6555 I915_WRITE(DEW(i), 0);
dde18883
ED		 6556
6557 /* Program P-state weights to account for frequency power adjustment */
6558 for (i = 0; i < 16; i++) {
616847e7 6559 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6560 unsigned long freq = intel_pxfreq(pxvidfreq);
6561 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6562 PXVFREQ_PX_SHIFT;
6563 unsigned long val;
6564
6565 val = vid * vid;
6566 val *= (freq / 1000);
6567 val *= 255;
6568 val /= (127*127*900);
6569 if (val > 0xff)
6570 DRM_ERROR("bad pxval: %ld\n", val);
6571 pxw[i] = val;
6572 }
6573 /* Render standby states get 0 weight */
6574 pxw[14] = 0;
6575 pxw[15] = 0;
6576
6577 for (i = 0; i < 4; i++) {
6578 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6579 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6580 I915_WRITE(PXW(i), val);
dde18883
ED		 6581 }
6582
6583 /* Adjust magic regs to magic values (more experimental results) */
6584 I915_WRITE(OGW0, 0);
6585 I915_WRITE(OGW1, 0);
6586 I915_WRITE(EG0, 0x00007f00);
6587 I915_WRITE(EG1, 0x0000000e);
6588 I915_WRITE(EG2, 0x000e0000);
6589 I915_WRITE(EG3, 0x68000300);
6590 I915_WRITE(EG4, 0x42000000);
6591 I915_WRITE(EG5, 0x00140031);
6592 I915_WRITE(EG6, 0);
6593 I915_WRITE(EG7, 0);
6594
6595 for (i = 0; i < 8; i++)
616847e7 6596 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6597
6598 /* Enable PMON + select events */
6599 I915_WRITE(ECR, 0x80000019);
6600
6601 lcfuse = I915_READ(LCFUSE02);
6602
20e4d407 6603 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6604}
6605
dc97997a 6606void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6607{
b268c699
ID		 6608 /*
6609 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6610 * requirement.
6611 */
6612 if (!i915.enable_rc6) {
6613 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6614 intel_runtime_pm_get(dev_priv);
6615 }
e6069ca8 6616
b5163dbb 6617 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6618 mutex_lock(&dev_priv->rps.hw_lock);
6619
6620 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6621 if (IS_CHERRYVIEW(dev_priv))
6622 cherryview_init_gt_powersave(dev_priv);
6623 else if (IS_VALLEYVIEW(dev_priv))
6624 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6625 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6626 gen6_init_rps_frequencies(dev_priv);
6627
6628 /* Derive initial user preferences/limits from the hardware limits */
6629 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6630 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6631
6632 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6633 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6634
6635 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6636 dev_priv->rps.min_freq_softlimit =
6637 max_t(int,
6638 dev_priv->rps.efficient_freq,
6639 intel_freq_opcode(dev_priv, 450));
6640
99ac9612
CW		 6641 /* After setting max-softlimit, find the overclock max freq */
6642 if (IS_GEN6(dev_priv) ||
6643 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6644 u32 params = 0;
6645
6646 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6647 if (params & BIT(31)) { /* OC supported */
6648 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6649 (dev_priv->rps.max_freq & 0xff) * 50,
6650 (params & 0xff) * 50);
6651 dev_priv->rps.max_freq = params & 0xff;
6652 }
6653 }
6654
29ecd78d
CW		 6655 /* Finally allow us to boost to max by default */
6656 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6657
773ea9a8 6658 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6659 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6660
6661 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6662}
6663
dc97997a 6664void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6665{
8dac1e1f 6666 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6667 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6668
6669 if (!i915.enable_rc6)
6670 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6671}
6672
54b4f68f
CW		 6673/**
6674 * intel_suspend_gt_powersave - suspend PM work and helper threads
6675 * @dev_priv: i915 device
6676 *
6677 * We don't want to disable RC6 or other features here, we just want
6678 * to make sure any work we've queued has finished and won't bother
6679 * us while we're suspended.
6680 */
6681void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6682{
6683 if (INTEL_GEN(dev_priv) < 6)
6684 return;
6685
6686 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6687 intel_runtime_pm_put(dev_priv);
6688
6689 /* gen6_rps_idle() will be called later to disable interrupts */
6690}
6691
b7137e0c
CW		 6692void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6693{
6694 dev_priv->rps.enabled = true; /* force disabling */
6695 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6696
6697 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6698}
6699
dc97997a 6700void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6701{
b7137e0c
CW		 6702 if (!READ_ONCE(dev_priv->rps.enabled))
6703 return;
e494837a 6704
b7137e0c 6705 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6706
b7137e0c
CW		 6707 if (INTEL_GEN(dev_priv) >= 9) {
6708 gen9_disable_rc6(dev_priv);
6709 gen9_disable_rps(dev_priv);
6710 } else if (IS_CHERRYVIEW(dev_priv)) {
6711 cherryview_disable_rps(dev_priv);
6712 } else if (IS_VALLEYVIEW(dev_priv)) {
6713 valleyview_disable_rps(dev_priv);
6714 } else if (INTEL_GEN(dev_priv) >= 6) {
6715 gen6_disable_rps(dev_priv);
6716 } else if (IS_IRONLAKE_M(dev_priv)) {
6717 ironlake_disable_drps(dev_priv);
930ebb46 6718 }
b7137e0c
CW		 6719
6720 dev_priv->rps.enabled = false;
6721 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6722}
6723
b7137e0c 6724void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6725{
54b4f68f
CW		 6726 /* We shouldn't be disabling as we submit, so this should be less
6727 * racy than it appears!
6728 */
b7137e0c
CW		 6729 if (READ_ONCE(dev_priv->rps.enabled))
6730 return;
1a01ab3b 6731
b7137e0c
CW		 6732 /* Powersaving is controlled by the host when inside a VM */
6733 if (intel_vgpu_active(dev_priv))
6734 return;
0a073b84 6735
b7137e0c 6736 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6737
6738 if (IS_CHERRYVIEW(dev_priv)) {
6739 cherryview_enable_rps(dev_priv);
6740 } else if (IS_VALLEYVIEW(dev_priv)) {
6741 valleyview_enable_rps(dev_priv);
b7137e0c 6742 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6743 gen9_enable_rc6(dev_priv);
6744 gen9_enable_rps(dev_priv);
6745 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6746 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6747 } else if (IS_BROADWELL(dev_priv)) {
6748 gen8_enable_rps(dev_priv);
fb7404e8 6749 gen6_update_ring_freq(dev_priv);
b7137e0c 6750 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6751 gen6_enable_rps(dev_priv);
fb7404e8 6752 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6753 } else if (IS_IRONLAKE_M(dev_priv)) {
6754 ironlake_enable_drps(dev_priv);
6755 intel_init_emon(dev_priv);
0a073b84 6756 }
aed242ff
CW		 6757
6758 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6759 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6760
6761 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6762 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6763
54b4f68f 6764 dev_priv->rps.enabled = true;
b7137e0c
CW		 6765 mutex_unlock(&dev_priv->rps.hw_lock);
6766}
3cc134e3 6767
54b4f68f
CW		 6768static void __intel_autoenable_gt_powersave(struct work_struct *work)
6769{
6770 struct drm_i915_private *dev_priv =
6771 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6772 struct intel_engine_cs *rcs;
6773 struct drm_i915_gem_request *req;
6774
6775 if (READ_ONCE(dev_priv->rps.enabled))
6776 goto out;
6777
3b3f1650 6778 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6779 if (rcs->last_context)
6780 goto out;
6781
6782 if (!rcs->init_context)
6783 goto out;
6784
6785 mutex_lock(&dev_priv->drm.struct_mutex);
6786
6787 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6788 if (IS_ERR(req))
6789 goto unlock;
6790
6791 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6792 rcs->init_context(req);
6793
6794 /* Mark the device busy, calling intel_enable_gt_powersave() */
6795 i915_add_request_no_flush(req);
6796
6797unlock:
6798 mutex_unlock(&dev_priv->drm.struct_mutex);
6799out:
6800 intel_runtime_pm_put(dev_priv);
6801}
6802
6803void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6804{
6805 if (READ_ONCE(dev_priv->rps.enabled))
6806 return;
6807
6808 if (IS_IRONLAKE_M(dev_priv)) {
6809 ironlake_enable_drps(dev_priv);
54b4f68f 6810 intel_init_emon(dev_priv);
54b4f68f
CW		 6811 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6812 /*
6813 * PCU communication is slow and this doesn't need to be
6814 * done at any specific time, so do this out of our fast path
6815 * to make resume and init faster.
6816 *
6817 * We depend on the HW RC6 power context save/restore
6818 * mechanism when entering D3 through runtime PM suspend. So
6819 * disable RPM until RPS/RC6 is properly setup. We can only
6820 * get here via the driver load/system resume/runtime resume
6821 * paths, so the _noresume version is enough (and in case of
6822 * runtime resume it's necessary).
6823 */
6824 if (queue_delayed_work(dev_priv->wq,
6825 &dev_priv->rps.autoenable_work,
6826 round_jiffies_up_relative(HZ)))
6827 intel_runtime_pm_get_noresume(dev_priv);
6828 }
6829}
6830
46f16e63 6831static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6832{
3107bd48
DV		 6833 /*
6834 * On Ibex Peak and Cougar Point, we need to disable clock
6835 * gating for the panel power sequencer or it will fail to
6836 * start up when no ports are active.
6837 */
6838 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6839}
6840
46f16e63 6841static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
0e088b8f 6842{
b12ce1d8 6843 enum pipe pipe;
0e088b8f 6844
055e393f 6845 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6846 I915_WRITE(DSPCNTR(pipe),
6847 I915_READ(DSPCNTR(pipe)) |
6848 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6849
6850 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6851 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6852 }
6853}
6854
46f16e63 6855static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
017636cc 6856{
017636cc
VS		 6857 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6858 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6859 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6860
6861 /*
6862 * Don't touch WM1S_LP_EN here.
6863 * Doing so could cause underruns.
6864 */
6865}
6866
46f16e63 6867static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 6868{
231e54f6 6869 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6870
f1e8fa56
DL		 6871 /*
6872 * Required for FBC
6873 * WaFbcDisableDpfcClockGating:ilk
6874 */
4d47e4f5
DL		 6875 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6876 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6877 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6878
6879 I915_WRITE(PCH_3DCGDIS0,
6880 MARIUNIT_CLOCK_GATE_DISABLE |
6881 SVSMUNIT_CLOCK_GATE_DISABLE);
6882 I915_WRITE(PCH_3DCGDIS1,
6883 VFMUNIT_CLOCK_GATE_DISABLE);
6884
6f1d69b0
ED		 6885 /*
6886 * According to the spec the following bits should be set in
6887 * order to enable memory self-refresh
6888 * The bit 22/21 of 0x42004
6889 * The bit 5 of 0x42020
6890 * The bit 15 of 0x45000
6891 */
6892 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6893 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6894 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6895 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6896 I915_WRITE(DISP_ARB_CTL,
6897 (I915_READ(DISP_ARB_CTL) |
6898 DISP_FBC_WM_DIS));
017636cc 6899
46f16e63 6900 ilk_init_lp_watermarks(dev_priv);
6f1d69b0
ED		 6901
6902 /*
6903 * Based on the document from hardware guys the following bits
6904 * should be set unconditionally in order to enable FBC.
6905 * The bit 22 of 0x42000
6906 * The bit 22 of 0x42004
6907 * The bit 7,8,9 of 0x42020.
6908 */
50a0bc90 6909 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6910 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6911 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6912 I915_READ(ILK_DISPLAY_CHICKEN1) |
6913 ILK_FBCQ_DIS);
6914 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6915 I915_READ(ILK_DISPLAY_CHICKEN2) |
6916 ILK_DPARB_GATE);
6f1d69b0
ED		 6917 }
6918
4d47e4f5
DL		 6919 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6920
6f1d69b0
ED		 6921 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6922 I915_READ(ILK_DISPLAY_CHICKEN2) |
6923 ILK_ELPIN_409_SELECT);
6924 I915_WRITE(_3D_CHICKEN2,
6925 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6926 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6927
ecdb4eb7 6928 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6929 I915_WRITE(CACHE_MODE_0,
6930 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6931
4e04632e
AG		 6932 /* WaDisable_RenderCache_OperationalFlush:ilk */
6933 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6934
46f16e63 6935 g4x_disable_trickle_feed(dev_priv);
bdad2b2f 6936
46f16e63 6937 ibx_init_clock_gating(dev_priv);
3107bd48
DV		 6938}
6939
46f16e63 6940static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6941{
3107bd48 6942 int pipe;
3f704fa2 6943 uint32_t val;
3107bd48
DV		 6944
6945 /*
6946 * On Ibex Peak and Cougar Point, we need to disable clock
6947 * gating for the panel power sequencer or it will fail to
6948 * start up when no ports are active.
6949 */
cd664078
JB		 6950 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6951 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6952 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6953 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6954 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6955 /* The below fixes the weird display corruption, a few pixels shifted
6956 * downward, on (only) LVDS of some HP laptops with IVY.
6957 */
055e393f 6958 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6959 val = I915_READ(TRANS_CHICKEN2(pipe));
6960 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6961 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6962 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6963 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6964 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6965 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6966 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6967 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6968 }
3107bd48 6969 /* WADP0ClockGatingDisable */
055e393f 6970 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6971 I915_WRITE(TRANS_CHICKEN1(pipe),
6972 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6973 }
6f1d69b0
ED		 6974}
6975
46f16e63 6976static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
1d7aaa0c 6977{
1d7aaa0c
DV		 6978 uint32_t tmp;
6979
6980 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6981 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6982 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6983 tmp);
1d7aaa0c
DV		 6984}
6985
46f16e63 6986static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 6987{
231e54f6 6988 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6989
231e54f6 6990 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6991
6992 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6993 I915_READ(ILK_DISPLAY_CHICKEN2) |
6994 ILK_ELPIN_409_SELECT);
6995
ecdb4eb7 6996 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6997 I915_WRITE(_3D_CHICKEN,
6998 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6999
4e04632e
AG		 7000 /* WaDisable_RenderCache_OperationalFlush:snb */
7001 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7002
8d85d272
VS		 7003 /*
7004 * BSpec recoomends 8x4 when MSAA is used,
7005 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7006 *
7007 * Note that PS/WM thread counts depend on the WIZ hashing
7008 * disable bit, which we don't touch here, but it's good
7009 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7010 */
7011 I915_WRITE(GEN6_GT_MODE,
98533251 7012 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7013
46f16e63 7014 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7015
6f1d69b0 7016 I915_WRITE(CACHE_MODE_0,
50743298 7017 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7018
7019 I915_WRITE(GEN6_UCGCTL1,
7020 I915_READ(GEN6_UCGCTL1) |
7021 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7022 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7023
7024 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7025 * gating disable must be set. Failure to set it results in
7026 * flickering pixels due to Z write ordering failures after
7027 * some amount of runtime in the Mesa "fire" demo, and Unigine
7028 * Sanctuary and Tropics, and apparently anything else with
7029 * alpha test or pixel discard.
7030 *
7031 * According to the spec, bit 11 (RCCUNIT) must also be set,
7032 * but we didn't debug actual testcases to find it out.
0f846f81 7033 *
ef59318c
VS		 7034 * WaDisableRCCUnitClockGating:snb
7035 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7036 */
7037 I915_WRITE(GEN6_UCGCTL2,
7038 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7039 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7040
5eb146dd 7041 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7042 I915_WRITE(_3D_CHICKEN3,
7043 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7044
e927ecde
VS		 7045 /*
7046 * Bspec says:
7047 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7048 * 3DSTATE_SF number of SF output attributes is more than 16."
7049 */
7050 I915_WRITE(_3D_CHICKEN3,
7051 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7052
6f1d69b0
ED		 7053 /*
7054 * According to the spec the following bits should be
7055 * set in order to enable memory self-refresh and fbc:
7056 * The bit21 and bit22 of 0x42000
7057 * The bit21 and bit22 of 0x42004
7058 * The bit5 and bit7 of 0x42020
7059 * The bit14 of 0x70180
7060 * The bit14 of 0x71180
4bb35334
DL		 7061 *
7062 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7063 */
7064 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7065 I915_READ(ILK_DISPLAY_CHICKEN1) |
7066 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7067 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7068 I915_READ(ILK_DISPLAY_CHICKEN2) |
7069 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7070 I915_WRITE(ILK_DSPCLK_GATE_D,
7071 I915_READ(ILK_DSPCLK_GATE_D) |
7072 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7073 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7074
46f16e63 7075 g4x_disable_trickle_feed(dev_priv);
f8f2ac9a 7076
46f16e63 7077 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7078
46f16e63 7079 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7080}
7081
7082static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7083{
7084 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7085
3aad9059 7086 /*
46680e0a 7087 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7088 *
7089 * This actually overrides the dispatch
7090 * mode for all thread types.
7091 */
6f1d69b0
ED		 7092 reg &= ~GEN7_FF_SCHED_MASK;
7093 reg |= GEN7_FF_TS_SCHED_HW;
7094 reg |= GEN7_FF_VS_SCHED_HW;
7095 reg |= GEN7_FF_DS_SCHED_HW;
7096
7097 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7098}
7099
46f16e63 7100static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
17a303ec 7101{
17a303ec
PZ		 7102 /*
7103 * TODO: this bit should only be enabled when really needed, then
7104 * disabled when not needed anymore in order to save power.
7105 */
4f8036a2 7106 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7107 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7108 I915_READ(SOUTH_DSPCLK_GATE_D) |
7109 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7110
7111 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7112 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7113 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7114 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7115}
7116
712bf364 7117static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7118{
4f8036a2 7119 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7120 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7121
7122 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7123 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7124 }
7125}
7126
450174fe
ID		 7127static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7128 int general_prio_credits,
7129 int high_prio_credits)
7130{
7131 u32 misccpctl;
7132
7133 /* WaTempDisableDOPClkGating:bdw */
7134 misccpctl = I915_READ(GEN7_MISCCPCTL);
7135 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7136
7137 I915_WRITE(GEN8_L3SQCREG1,
7138 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7139 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7140
7141 /*
7142 * Wait at least 100 clocks before re-enabling clock gating.
7143 * See the definition of L3SQCREG1 in BSpec.
7144 */
7145 POSTING_READ(GEN8_L3SQCREG1);
7146 udelay(1);
7147 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7148}
7149
46f16e63 7150static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
9498dba7 7151{
46f16e63 7152 gen9_init_clock_gating(dev_priv);
9498dba7
MK		 7153
7154 /* WaDisableSDEUnitClockGating:kbl */
7155 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7156 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7157 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7158
7159 /* WaDisableGamClockGating:kbl */
7160 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7161 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7162 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7163
7164 /* WaFbcNukeOnHostModify:kbl */
7165 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7166 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7167}
7168
46f16e63 7169static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
dc00b6a0 7170{
46f16e63 7171 gen9_init_clock_gating(dev_priv);
44fff99f
MK		 7172
7173 /* WAC6entrylatency:skl */
7174 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7175 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7176
7177 /* WaFbcNukeOnHostModify:skl */
7178 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7179 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7180}
7181
46f16e63 7182static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
1020a5c2 7183{
07d27e20 7184 enum pipe pipe;
1020a5c2 7185
46f16e63 7186 ilk_init_lp_watermarks(dev_priv);
50ed5fbd 7187
ab57fff1 7188 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7189 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7190
ab57fff1 7191 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7192 I915_WRITE(CHICKEN_PAR1_1,
7193 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7194
ab57fff1 7195 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7196 for_each_pipe(dev_priv, pipe) {
07d27e20 7197 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7198 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7199 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7200 }
63801f21 7201
ab57fff1
BW		 7202 /* WaVSRefCountFullforceMissDisable:bdw */
7203 /* WaDSRefCountFullforceMissDisable:bdw */
7204 I915_WRITE(GEN7_FF_THREAD_MODE,
7205 I915_READ(GEN7_FF_THREAD_MODE) &
7206 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7207
295e8bb7
VS		 7208 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7209 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7210
7211 /* WaDisableSDEUnitClockGating:bdw */
7212 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7213 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7214
450174fe
ID		 7215 /* WaProgramL3SqcReg1Default:bdw */
7216 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7217
6d50b065
VS		 7218 /*
7219 * WaGttCachingOffByDefault:bdw
7220 * GTT cache may not work with big pages, so if those
7221 * are ever enabled GTT cache may need to be disabled.
7222 */
7223 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7224
17e0adf0
MK		 7225 /* WaKVMNotificationOnConfigChange:bdw */
7226 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7227 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7228
46f16e63 7229 lpt_init_clock_gating(dev_priv);
1020a5c2
BW		 7230}
7231
46f16e63 7232static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
cad2a2d7 7233{
46f16e63 7234 ilk_init_lp_watermarks(dev_priv);
cad2a2d7 7235
f3fc4884
FJ		 7236 /* L3 caching of data atomics doesn't work -- disable it. */
7237 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7238 I915_WRITE(HSW_ROW_CHICKEN3,
7239 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7240
ecdb4eb7 7241 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7242 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7243 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7244 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7245
e36ea7ff
VS		 7246 /* WaVSRefCountFullforceMissDisable:hsw */
7247 I915_WRITE(GEN7_FF_THREAD_MODE,
7248 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7249
4e04632e
AG		 7250 /* WaDisable_RenderCache_OperationalFlush:hsw */
7251 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7252
fe27c606
CW		 7253 /* enable HiZ Raw Stall Optimization */
7254 I915_WRITE(CACHE_MODE_0_GEN7,
7255 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7256
ecdb4eb7 7257 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7258 I915_WRITE(CACHE_MODE_1,
7259 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7260
a12c4967
VS		 7261 /*
7262 * BSpec recommends 8x4 when MSAA is used,
7263 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7264 *
7265 * Note that PS/WM thread counts depend on the WIZ hashing
7266 * disable bit, which we don't touch here, but it's good
7267 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7268 */
7269 I915_WRITE(GEN7_GT_MODE,
98533251 7270 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7271
94411593
KG		 7272 /* WaSampleCChickenBitEnable:hsw */
7273 I915_WRITE(HALF_SLICE_CHICKEN3,
7274 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7275
ecdb4eb7 7276 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7277 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7278
90a88643
PZ		 7279 /* WaRsPkgCStateDisplayPMReq:hsw */
7280 I915_WRITE(CHICKEN_PAR1_1,
7281 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7282
46f16e63 7283 lpt_init_clock_gating(dev_priv);
cad2a2d7
ED		 7284}
7285
46f16e63 7286static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7287{
20848223 7288 uint32_t snpcr;
6f1d69b0 7289
46f16e63 7290 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7291
231e54f6 7292 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7293
ecdb4eb7 7294 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7295 I915_WRITE(_3D_CHICKEN3,
7296 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7297
ecdb4eb7 7298 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7299 I915_WRITE(IVB_CHICKEN3,
7300 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7301 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7302
ecdb4eb7 7303 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7304 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7305 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7306 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7307
4e04632e
AG		 7308 /* WaDisable_RenderCache_OperationalFlush:ivb */
7309 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7310
ecdb4eb7 7311 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7312 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7313 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7314
ecdb4eb7 7315 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7316 I915_WRITE(GEN7_L3CNTLREG1,
7317 GEN7_WA_FOR_GEN7_L3_CONTROL);
7318 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7319 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7320 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7321 I915_WRITE(GEN7_ROW_CHICKEN2,
7322 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7323 else {
7324 /* must write both registers */
7325 I915_WRITE(GEN7_ROW_CHICKEN2,
7326 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7327 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7328 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7329 }
6f1d69b0 7330
ecdb4eb7 7331 /* WaForceL3Serialization:ivb */
61939d97
JB		 7332 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7333 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7334
1b80a19a 7335 /*
0f846f81 7336 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7337 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7338 */
7339 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7340 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7341
ecdb4eb7 7342 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7343 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7344 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7345 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7346
46f16e63 7347 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7348
7349 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7350
22721343
CW		 7351 if (0) { /* causes HiZ corruption on ivb:gt1 */
7352 /* enable HiZ Raw Stall Optimization */
7353 I915_WRITE(CACHE_MODE_0_GEN7,
7354 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7355 }
116f2b6d 7356
ecdb4eb7 7357 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7358 I915_WRITE(CACHE_MODE_1,
7359 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7360
a607c1a4
VS		 7361 /*
7362 * BSpec recommends 8x4 when MSAA is used,
7363 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7364 *
7365 * Note that PS/WM thread counts depend on the WIZ hashing
7366 * disable bit, which we don't touch here, but it's good
7367 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7368 */
7369 I915_WRITE(GEN7_GT_MODE,
98533251 7370 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7371
20848223
BW		 7372 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7373 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7374 snpcr |= GEN6_MBC_SNPCR_MED;
7375 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7376
6e266956 7377 if (!HAS_PCH_NOP(dev_priv))
46f16e63 7378 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7379
46f16e63 7380 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7381}
7382
46f16e63 7383static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7384{
ecdb4eb7 7385 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7386 I915_WRITE(_3D_CHICKEN3,
7387 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7388
ecdb4eb7 7389 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7390 I915_WRITE(IVB_CHICKEN3,
7391 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7392 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7393
fad7d36e 7394 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7395 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7396 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7397 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7398 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7399
4e04632e
AG		 7400 /* WaDisable_RenderCache_OperationalFlush:vlv */
7401 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7402
ecdb4eb7 7403 /* WaForceL3Serialization:vlv */
61939d97
JB		 7404 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7405 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7406
ecdb4eb7 7407 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7408 I915_WRITE(GEN7_ROW_CHICKEN2,
7409 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7410
ecdb4eb7 7411 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7412 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7413 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7414 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7415
46680e0a
VS		 7416 gen7_setup_fixed_func_scheduler(dev_priv);
7417
3c0edaeb 7418 /*
0f846f81 7419 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7420 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7421 */
7422 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7423 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7424
c98f5062
AG		 7425 /* WaDisableL3Bank2xClockGate:vlv
7426 * Disabling L3 clock gating- MMIO 940c[25] = 1
7427 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7428 I915_WRITE(GEN7_UCGCTL4,
7429 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7430
afd58e79
VS		 7431 /*
7432 * BSpec says this must be set, even though
7433 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7434 */
6b26c86d
DV		 7435 I915_WRITE(CACHE_MODE_1,
7436 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7437
da2518f9
VS		 7438 /*
7439 * BSpec recommends 8x4 when MSAA is used,
7440 * however in practice 16x4 seems fastest.
7441 *
7442 * Note that PS/WM thread counts depend on the WIZ hashing
7443 * disable bit, which we don't touch here, but it's good
7444 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7445 */
7446 I915_WRITE(GEN7_GT_MODE,
7447 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7448
031994ee
VS		 7449 /*
7450 * WaIncreaseL3CreditsForVLVB0:vlv
7451 * This is the hardware default actually.
7452 */
7453 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7454
2d809570 7455 /*
ecdb4eb7 7456 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7457 * Disable clock gating on th GCFG unit to prevent a delay
7458 * in the reporting of vblank events.
7459 */
7a0d1eed 7460 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7461}
7462
46f16e63 7463static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
a4565da8 7464{
232ce337
VS		 7465 /* WaVSRefCountFullforceMissDisable:chv */
7466 /* WaDSRefCountFullforceMissDisable:chv */
7467 I915_WRITE(GEN7_FF_THREAD_MODE,
7468 I915_READ(GEN7_FF_THREAD_MODE) &
7469 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7470
7471 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7472 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7473 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7474
7475 /* WaDisableCSUnitClockGating:chv */
7476 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7477 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7478
7479 /* WaDisableSDEUnitClockGating:chv */
7480 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7481 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7482
450174fe
ID		 7483 /*
7484 * WaProgramL3SqcReg1Default:chv
7485 * See gfxspecs/Related Documents/Performance Guide/
7486 * LSQC Setting Recommendations.
7487 */
7488 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7489
6d50b065
VS		 7490 /*
7491 * GTT cache may not work with big pages, so if those
7492 * are ever enabled GTT cache may need to be disabled.
7493 */
7494 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7495}
7496
46f16e63 7497static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7498{
6f1d69b0
ED		 7499 uint32_t dspclk_gate;
7500
7501 I915_WRITE(RENCLK_GATE_D1, 0);
7502 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7503 GS_UNIT_CLOCK_GATE_DISABLE |
7504 CL_UNIT_CLOCK_GATE_DISABLE);
7505 I915_WRITE(RAMCLK_GATE_D, 0);
7506 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7507 OVRUNIT_CLOCK_GATE_DISABLE |
7508 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7509 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7510 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7511 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7512
7513 /* WaDisableRenderCachePipelinedFlush */
7514 I915_WRITE(CACHE_MODE_0,
7515 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7516
4e04632e
AG		 7517 /* WaDisable_RenderCache_OperationalFlush:g4x */
7518 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7519
46f16e63 7520 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7521}
7522
46f16e63 7523static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7524{
6f1d69b0
ED		 7525 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7526 I915_WRITE(RENCLK_GATE_D2, 0);
7527 I915_WRITE(DSPCLK_GATE_D, 0);
7528 I915_WRITE(RAMCLK_GATE_D, 0);
7529 I915_WRITE16(DEUC, 0);
20f94967
VS		 7530 I915_WRITE(MI_ARB_STATE,
7531 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7532
7533 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7534 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7535}
7536
46f16e63 7537static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7538{
6f1d69b0
ED		 7539 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7540 I965_RCC_CLOCK_GATE_DISABLE |
7541 I965_RCPB_CLOCK_GATE_DISABLE |
7542 I965_ISC_CLOCK_GATE_DISABLE |
7543 I965_FBC_CLOCK_GATE_DISABLE);
7544 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7545 I915_WRITE(MI_ARB_STATE,
7546 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7547
7548 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7549 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7550}
7551
46f16e63 7552static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7553{
6f1d69b0
ED		 7554 u32 dstate = I915_READ(D_STATE);
7555
7556 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7557 DSTATE_DOT_CLOCK_GATING;
7558 I915_WRITE(D_STATE, dstate);
13a86b85 7559
9b1e14f4 7560 if (IS_PINEVIEW(dev_priv))
13a86b85 7561 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7562
7563 /* IIR "flip pending" means done if this bit is set */
7564 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7565
7566 /* interrupts should cause a wake up from C3 */
3299254f 7567 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7568
7569 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7570 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7571
7572 I915_WRITE(MI_ARB_STATE,
7573 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7574}
7575
46f16e63 7576static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7577{
6f1d69b0 7578 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7579
7580 /* interrupts should cause a wake up from C3 */
7581 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7582 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7583
7584 I915_WRITE(MEM_MODE,
7585 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7586}
7587
46f16e63 7588static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7589{
6f1d69b0 7590 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7591
7592 I915_WRITE(MEM_MODE,
7593 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7594 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7595}
7596
46f16e63 7597void intel_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7598{
46f16e63 7599 dev_priv->display.init_clock_gating(dev_priv);
6f1d69b0
ED		 7600}
7601
712bf364 7602void intel_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7603{
712bf364
VS		 7604 if (HAS_PCH_LPT(dev_priv))
7605 lpt_suspend_hw(dev_priv);
7d708ee4
ID		 7606}
7607
46f16e63 7608static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
bb400da9
ID		 7609{
7610 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7611}
7612
7613/**
7614 * intel_init_clock_gating_hooks - setup the clock gating hooks
7615 * @dev_priv: device private
7616 *
7617 * Setup the hooks that configure which clocks of a given platform can be
7618 * gated and also apply various GT and display specific workarounds for these
7619 * platforms. Note that some GT specific workarounds are applied separately
7620 * when GPU contexts or batchbuffers start their execution.
7621 */
7622void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7623{
7624 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7625 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7626 else if (IS_KABYLAKE(dev_priv))
9498dba7 7627 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
cc3f90f0 7628 else if (IS_GEN9_LP(dev_priv))
bb400da9
ID		 7629 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7630 else if (IS_BROADWELL(dev_priv))
7631 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7632 else if (IS_CHERRYVIEW(dev_priv))
7633 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7634 else if (IS_HASWELL(dev_priv))
7635 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7636 else if (IS_IVYBRIDGE(dev_priv))
7637 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7638 else if (IS_VALLEYVIEW(dev_priv))
7639 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7640 else if (IS_GEN6(dev_priv))
7641 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7642 else if (IS_GEN5(dev_priv))
7643 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7644 else if (IS_G4X(dev_priv))
7645 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7646 else if (IS_CRESTLINE(dev_priv))
7647 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7648 else if (IS_BROADWATER(dev_priv))
7649 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7650 else if (IS_GEN3(dev_priv))
7651 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7652 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7653 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7654 else if (IS_GEN2(dev_priv))
7655 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7656 else {
7657 MISSING_CASE(INTEL_DEVID(dev_priv));
7658 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7659 }
7660}
7661
1fa61106 7662/* Set up chip specific power management-related functions */
62d75df7 7663void intel_init_pm(struct drm_i915_private *dev_priv)
1fa61106 7664{
7ff0ebcc 7665 intel_fbc_init(dev_priv);
1fa61106 7666
c921aba8 7667 /* For cxsr */
9b1e14f4 7668 if (IS_PINEVIEW(dev_priv))
148ac1f3 7669 i915_pineview_get_mem_freq(dev_priv);
5db94019 7670 else if (IS_GEN5(dev_priv))
148ac1f3 7671 i915_ironlake_get_mem_freq(dev_priv);
c921aba8 7672
1fa61106 7673 /* For FIFO watermark updates */
62d75df7 7674 if (INTEL_GEN(dev_priv) >= 9) {
bb726519 7675 skl_setup_wm_latency(dev_priv);
e62929b3 7676 dev_priv->display.initial_watermarks = skl_initial_wm;
ccf010fb 7677 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
98d39494 7678 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7679 } else if (HAS_PCH_SPLIT(dev_priv)) {
bb726519 7680 ilk_setup_wm_latency(dev_priv);
53615a5e 7681
5db94019 7682 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7683 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7684 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7685 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7686 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7687 dev_priv->display.compute_intermediate_wm =
7688 ilk_compute_intermediate_wm;
7689 dev_priv->display.initial_watermarks =
7690 ilk_initial_watermarks;
7691 dev_priv->display.optimize_watermarks =
7692 ilk_optimize_watermarks;
bd602544
VS		 7693 } else {
7694 DRM_DEBUG_KMS("Failed to read display plane latency. "
7695 "Disable CxSR\n");
7696 }
6b6b3eef 7697 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
bb726519 7698 vlv_setup_wm_latency(dev_priv);
26e1fe4f 7699 dev_priv->display.update_wm = vlv_update_wm;
9b1e14f4 7700 } else if (IS_PINEVIEW(dev_priv)) {
50a0bc90 7701 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7702 dev_priv->is_ddr3,
7703 dev_priv->fsb_freq,
7704 dev_priv->mem_freq)) {
7705 DRM_INFO("failed to find known CxSR latency "
7706 "(found ddr%s fsb freq %d, mem freq %d), "
7707 "disabling CxSR\n",
7708 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7709 dev_priv->fsb_freq, dev_priv->mem_freq);
7710 /* Disable CxSR and never update its watermark again */
5209b1f4 7711 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7712 dev_priv->display.update_wm = NULL;
7713 } else
7714 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7715 } else if (IS_G4X(dev_priv)) {
1fa61106 7716 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7717 } else if (IS_GEN4(dev_priv)) {
1fa61106 7718 dev_priv->display.update_wm = i965_update_wm;
5db94019 7719 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7720 dev_priv->display.update_wm = i9xx_update_wm;
7721 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7722 } else if (IS_GEN2(dev_priv)) {
62d75df7 7723 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
feb56b93 7724 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7725 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7726 } else {
7727 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7728 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7729 }
feb56b93
DV		 7730 } else {
7731 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7732 }
7733}
7734
87660502
L		 7735static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7736{
7737 uint32_t flags =
7738 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7739
7740 switch (flags) {
7741 case GEN6_PCODE_SUCCESS:
7742 return 0;
7743 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7744 case GEN6_PCODE_ILLEGAL_CMD:
7745 return -ENXIO;
7746 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7747 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7748 return -EOVERFLOW;
7749 case GEN6_PCODE_TIMEOUT:
7750 return -ETIMEDOUT;
7751 default:
7752 MISSING_CASE(flags)
7753 return 0;
7754 }
7755}
7756
7757static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7758{
7759 uint32_t flags =
7760 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7761
7762 switch (flags) {
7763 case GEN6_PCODE_SUCCESS:
7764 return 0;
7765 case GEN6_PCODE_ILLEGAL_CMD:
7766 return -ENXIO;
7767 case GEN7_PCODE_TIMEOUT:
7768 return -ETIMEDOUT;
7769 case GEN7_PCODE_ILLEGAL_DATA:
7770 return -EINVAL;
7771 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7772 return -EOVERFLOW;
7773 default:
7774 MISSING_CASE(flags);
7775 return 0;
7776 }
7777}
7778
151a49d0 7779int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7780{
87660502
L		 7781 int status;
7782
4fc688ce 7783 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7784
3f5582dd
CW		 7785 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7786 * use te fw I915_READ variants to reduce the amount of work
7787 * required when reading/writing.
7788 */
7789
7790 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7791 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7792 return -EAGAIN;
7793 }
7794
3f5582dd
CW		 7795 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7796 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7797 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7798
3f5582dd
CW		 7799 if (intel_wait_for_register_fw(dev_priv,
7800 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7801 500)) {
42c0526c
BW		 7802 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7803 return -ETIMEDOUT;
7804 }
7805
3f5582dd
CW		 7806 *val = I915_READ_FW(GEN6_PCODE_DATA);
7807 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7808
87660502
L		 7809 if (INTEL_GEN(dev_priv) > 6)
7810 status = gen7_check_mailbox_status(dev_priv);
7811 else
7812 status = gen6_check_mailbox_status(dev_priv);
7813
7814 if (status) {
7815 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7816 status);
7817 return status;
7818 }
7819
42c0526c
BW		 7820 return 0;
7821}
7822
3f5582dd 7823int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7824 u32 mbox, u32 val)
42c0526c 7825{
87660502
L		 7826 int status;
7827
4fc688ce 7828 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7829
3f5582dd
CW		 7830 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7831 * use te fw I915_READ variants to reduce the amount of work
7832 * required when reading/writing.
7833 */
7834
7835 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7836 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7837 return -EAGAIN;
7838 }
7839
3f5582dd 7840 I915_WRITE_FW(GEN6_PCODE_DATA, val);
8bf41b72 7841 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
3f5582dd 7842 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7843
3f5582dd
CW		 7844 if (intel_wait_for_register_fw(dev_priv,
7845 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7846 500)) {
42c0526c
BW		 7847 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7848 return -ETIMEDOUT;
7849 }
7850
3f5582dd 7851 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7852
87660502
L		 7853 if (INTEL_GEN(dev_priv) > 6)
7854 status = gen7_check_mailbox_status(dev_priv);
7855 else
7856 status = gen6_check_mailbox_status(dev_priv);
7857
7858 if (status) {
7859 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7860 status);
7861 return status;
7862 }
7863
42c0526c
BW		 7864 return 0;
7865}
a0e4e199 7866
dd06f88c
VS		 7867static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7868{
c30fec65
VS		 7869 /*
7870 * N = val - 0xb7
7871 * Slow = Fast = GPLL ref * N
7872 */
7873 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7874}
7875
b55dd647 7876static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7877{
c30fec65 7878 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7879}
7880
b55dd647 7881static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7882{
c30fec65
VS		 7883 /*
7884 * N = val / 2
7885 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7886 */
7887 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7888}
7889
b55dd647 7890static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7891{
1c14762d 7892 /* CHV needs even values */
c30fec65 7893 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7894}
7895
616bc820 7896int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7897{
2d1fe073 7898 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7899 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7900 GEN9_FREQ_SCALER);
2d1fe073 7901 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7902 return chv_gpu_freq(dev_priv, val);
2d1fe073 7903 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7904 return byt_gpu_freq(dev_priv, val);
7905 else
7906 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7907}
7908
616bc820
VS		 7909int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7910{
2d1fe073 7911 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7912 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7913 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7914 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7915 return chv_freq_opcode(dev_priv, val);
2d1fe073 7916 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7917 return byt_freq_opcode(dev_priv, val);
7918 else
500a3d2e 7919 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7920}
22b1b2f8 7921
6ad790c0
CW		 7922struct request_boost {
7923 struct work_struct work;
eed29a5b 7924 struct drm_i915_gem_request *req;
6ad790c0
CW		 7925};
7926
7927static void __intel_rps_boost_work(struct work_struct *work)
7928{
7929 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7930 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7931
f69a02c9 7932 if (!i915_gem_request_completed(req))
c033666a 7933 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7934
e8a261ea 7935 i915_gem_request_put(req);
6ad790c0
CW		 7936 kfree(boost);
7937}
7938
91d14251 7939void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7940{
7941 struct request_boost *boost;
7942
91d14251 7943 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7944 return;
7945
f69a02c9 7946 if (i915_gem_request_completed(req))
e61b9958
CW		 7947 return;
7948
6ad790c0
CW		 7949 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7950 if (boost == NULL)
7951 return;
7952
e8a261ea 7953 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7954
7955 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7956 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7957}
7958
192aa181 7959void intel_pm_setup(struct drm_i915_private *dev_priv)
907b28c5 7960{
f742a552 7961 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7962 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7963
54b4f68f
CW		 7964 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7965 __intel_autoenable_gt_powersave);
1854d5ca 7966 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 7967
33688d95 7968 dev_priv->pm.suspended = false;
1f814dac 7969 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 7970}
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