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drm/i915/gen9: Drop re-allocation of DDB at atomic commit (v2)
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
a82abe43
ID		 57static void bxt_init_clock_gating(struct drm_device *dev)
58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
a7546159
NH		 61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
32608ca2
ID		 65 /*
66 * FIXME:
868434c5 67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 68 */
32608ca2 69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 79}
80
c921aba8
DV		 81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
50227e1c 83 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
20e4d407 148 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
20e4d407 180 dev_priv->ips.c_m = 0;
c921aba8 181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 182 dev_priv->ips.c_m = 1;
c921aba8 183 } else {
20e4d407 184 dev_priv->ips.c_m = 2;
c921aba8
DV		 185 }
186}
187
b445e3b0
ED		 188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
63c62275 226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
fc1ac8de
VS		 250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
cfb41411
VS		 272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
f4998963
VS		 288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
5209b1f4 291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 292{
5209b1f4
ID		 293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
b445e3b0 295
666a4537 296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 298 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 299 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
a7a6c498 307 POSTING_READ(DSPFW3);
5209b1f4
ID		 308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 312 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
a7a6c498 317 POSTING_READ(INSTPM);
5209b1f4
ID		 318 } else {
319 return;
320 }
b445e3b0 321
5209b1f4
ID		 322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
b445e3b0
ED		 324}
325
fc1ac8de 326
b445e3b0
ED		 327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
5aef6003 341static const int pessimal_latency_ns = 5000;
b445e3b0 342
b5004720
VS		 343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
1fa61106 398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
feb56b93 414static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
1fa61106 431static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
b445e3b0
ED		 447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 461};
462static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 489};
b445e3b0 490static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 491 .fifo_size = I965_CURSOR_FIFO,
492 .max_wm = I965_CURSOR_MAX_WM,
493 .default_wm = I965_CURSOR_DFT_WM,
494 .guard_size = 2,
495 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 498 .fifo_size = I945_FIFO_SIZE,
499 .max_wm = I915_MAX_WM,
500 .default_wm = 1,
501 .guard_size = 2,
502 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 505 .fifo_size = I915_FIFO_SIZE,
506 .max_wm = I915_MAX_WM,
507 .default_wm = 1,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 510};
9d539105 511static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 512 .fifo_size = I855GM_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 517};
9d539105
VS		 518static const struct intel_watermark_params i830_bc_wm_info = {
519 .fifo_size = I855GM_FIFO_SIZE,
520 .max_wm = I915_MAX_WM/2,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I830_FIFO_LINE_SIZE,
524};
feb56b93 525static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 526 .fifo_size = I830_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532
b445e3b0
ED		 533/**
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
ac484963 537 * @cpp: bytes per pixel
b445e3b0
ED		 538 * @latency_ns: memory latency for the platform
539 *
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
544 *
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
550 */
551static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
552 const struct intel_watermark_params *wm,
ac484963 553 int fifo_size, int cpp,
b445e3b0
ED		 554 unsigned long latency_ns)
555{
556 long entries_required, wm_size;
557
558 /*
559 * Note: we need to make sure we don't overflow for various clock &
560 * latency values.
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
563 */
ac484963 564 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 565 1000;
566 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
567
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
569
570 wm_size = fifo_size - (entries_required + wm->guard_size);
571
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
573
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size > (long)wm->max_wm)
576 wm_size = wm->max_wm;
577 if (wm_size <= 0)
578 wm_size = wm->default_wm;
d6feb196
VS		 579
580 /*
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
585 * done).
586 */
587 if (wm_size <= 8)
588 wm_size = 8;
589
b445e3b0
ED		 590 return wm_size;
591}
592
593static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
594{
595 struct drm_crtc *crtc, *enabled = NULL;
596
70e1e0ec 597 for_each_crtc(dev, crtc) {
3490ea5d 598 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 599 if (enabled)
600 return NULL;
601 enabled = crtc;
602 }
603 }
604
605 return enabled;
606}
607
46ba614c 608static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 609{
46ba614c 610 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct drm_crtc *crtc;
613 const struct cxsr_latency *latency;
614 u32 reg;
615 unsigned long wm;
616
617 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
618 dev_priv->fsb_freq, dev_priv->mem_freq);
619 if (!latency) {
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 621 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 622 return;
623 }
624
625 crtc = single_enabled_crtc(dev);
626 if (crtc) {
7c5f93b0 627 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 628 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 629 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 630
631 /* Display SR */
632 wm = intel_calculate_wm(clock, &pineview_display_wm,
633 pineview_display_wm.fifo_size,
ac484963 634 cpp, latency->display_sr);
b445e3b0
ED		 635 reg = I915_READ(DSPFW1);
636 reg &= ~DSPFW_SR_MASK;
f4998963 637 reg |= FW_WM(wm, SR);
b445e3b0
ED		 638 I915_WRITE(DSPFW1, reg);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
640
641 /* cursor SR */
642 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
643 pineview_display_wm.fifo_size,
ac484963 644 cpp, latency->cursor_sr);
b445e3b0
ED		 645 reg = I915_READ(DSPFW3);
646 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 647 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 648 I915_WRITE(DSPFW3, reg);
649
650 /* Display HPLL off SR */
651 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
652 pineview_display_hplloff_wm.fifo_size,
ac484963 653 cpp, latency->display_hpll_disable);
b445e3b0
ED		 654 reg = I915_READ(DSPFW3);
655 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 656 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 657 I915_WRITE(DSPFW3, reg);
658
659 /* cursor HPLL off SR */
660 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
661 pineview_display_hplloff_wm.fifo_size,
ac484963 662 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 663 reg = I915_READ(DSPFW3);
664 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 665 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 666 I915_WRITE(DSPFW3, reg);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
668
5209b1f4 669 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 670 } else {
5209b1f4 671 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 672 }
673}
674
675static bool g4x_compute_wm0(struct drm_device *dev,
676 int plane,
677 const struct intel_watermark_params *display,
678 int display_latency_ns,
679 const struct intel_watermark_params *cursor,
680 int cursor_latency_ns,
681 int *plane_wm,
682 int *cursor_wm)
683{
684 struct drm_crtc *crtc;
4fe8590a 685 const struct drm_display_mode *adjusted_mode;
ac484963 686 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 687 int line_time_us, line_count;
688 int entries, tlb_miss;
689
690 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 691 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 692 *cursor_wm = cursor->guard_size;
693 *plane_wm = display->guard_size;
694 return false;
695 }
696
6e3c9717 697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 698 clock = adjusted_mode->crtc_clock;
fec8cba3 699 htotal = adjusted_mode->crtc_htotal;
6e3c9717 700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 701 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 702
703 /* Use the small buffer method to calculate plane watermark */
ac484963 704 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 705 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
706 if (tlb_miss > 0)
707 entries += tlb_miss;
708 entries = DIV_ROUND_UP(entries, display->cacheline_size);
709 *plane_wm = entries + display->guard_size;
710 if (*plane_wm > (int)display->max_wm)
711 *plane_wm = display->max_wm;
712
713 /* Use the large buffer method to calculate cursor watermark */
922044c9 714 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 715 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 716 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 717 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
718 if (tlb_miss > 0)
719 entries += tlb_miss;
720 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
721 *cursor_wm = entries + cursor->guard_size;
722 if (*cursor_wm > (int)cursor->max_wm)
723 *cursor_wm = (int)cursor->max_wm;
724
725 return true;
726}
727
728/*
729 * Check the wm result.
730 *
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
733 * must be disabled.
734 */
735static bool g4x_check_srwm(struct drm_device *dev,
736 int display_wm, int cursor_wm,
737 const struct intel_watermark_params *display,
738 const struct intel_watermark_params *cursor)
739{
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm, cursor_wm);
742
743 if (display_wm > display->max_wm) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm, display->max_wm);
746 return false;
747 }
748
749 if (cursor_wm > cursor->max_wm) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm, cursor->max_wm);
752 return false;
753 }
754
755 if (!(display_wm || cursor_wm)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
757 return false;
758 }
759
760 return true;
761}
762
763static bool g4x_compute_srwm(struct drm_device *dev,
764 int plane,
765 int latency_ns,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor,
768 int *display_wm, int *cursor_wm)
769{
770 struct drm_crtc *crtc;
4fe8590a 771 const struct drm_display_mode *adjusted_mode;
ac484963 772 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 773 unsigned long line_time_us;
774 int line_count, line_size;
775 int small, large;
776 int entries;
777
778 if (!latency_ns) {
779 *display_wm = *cursor_wm = 0;
780 return false;
781 }
782
783 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 784 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 785 clock = adjusted_mode->crtc_clock;
fec8cba3 786 htotal = adjusted_mode->crtc_htotal;
6e3c9717 787 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 788 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 789
922044c9 790 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 791 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 792 line_size = hdisplay * cpp;
b445e3b0
ED		 793
794 /* Use the minimum of the small and large buffer method for primary */
ac484963 795 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 796 large = line_count * line_size;
797
798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
799 *display_wm = entries + display->guard_size;
800
801 /* calculate the self-refresh watermark for display cursor */
ac484963 802 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
804 *cursor_wm = entries + cursor->guard_size;
805
806 return g4x_check_srwm(dev,
807 *display_wm, *cursor_wm,
808 display, cursor);
809}
810
15665979
VS		 811#define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
813
0018fda1
VS		 814static void vlv_write_wm_values(struct intel_crtc *crtc,
815 const struct vlv_wm_values *wm)
816{
817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
818 enum pipe pipe = crtc->pipe;
819
820 I915_WRITE(VLV_DDL(pipe),
821 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
822 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
825
ae80152d 826 I915_WRITE(DSPFW1,
15665979
VS		 827 FW_WM(wm->sr.plane, SR) |
828 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
829 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
830 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 831 I915_WRITE(DSPFW2,
15665979
VS		 832 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
833 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
834 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 835 I915_WRITE(DSPFW3,
15665979 836 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 837
838 if (IS_CHERRYVIEW(dev_priv)) {
839 I915_WRITE(DSPFW7_CHV,
15665979
VS		 840 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
841 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 842 I915_WRITE(DSPFW8_CHV,
15665979
VS		 843 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
844 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 845 I915_WRITE(DSPFW9_CHV,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
847 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 848 I915_WRITE(DSPHOWM,
15665979
VS		 849 FW_WM(wm->sr.plane >> 9, SR_HI) |
850 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
851 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
852 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
853 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
854 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
855 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
856 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
857 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
858 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 859 } else {
860 I915_WRITE(DSPFW7,
15665979
VS		 861 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
862 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 863 I915_WRITE(DSPHOWM,
15665979
VS		 864 FW_WM(wm->sr.plane >> 9, SR_HI) |
865 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
868 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
870 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 871 }
872
2cb389b7
VS		 873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4, 0);
875 I915_WRITE(DSPFW5, 0);
876 I915_WRITE(DSPFW6, 0);
877 I915_WRITE(DSPHOWM1, 0);
878
ae80152d 879 POSTING_READ(DSPFW1);
0018fda1
VS		 880}
881
15665979
VS		 882#undef FW_WM_VLV
883
6eb1a681
VS		 884enum vlv_wm_level {
885 VLV_WM_LEVEL_PM2,
886 VLV_WM_LEVEL_PM5,
887 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 888};
889
262cd2e1
VS		 890/* latency must be in 0.1us units. */
891static unsigned int vlv_wm_method2(unsigned int pixel_rate,
892 unsigned int pipe_htotal,
893 unsigned int horiz_pixels,
ac484963 894 unsigned int cpp,
262cd2e1
VS		 895 unsigned int latency)
896{
897 unsigned int ret;
898
899 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 900 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 901 ret = DIV_ROUND_UP(ret, 64);
902
903 return ret;
904}
905
906static void vlv_setup_wm_latency(struct drm_device *dev)
907{
908 struct drm_i915_private *dev_priv = dev->dev_private;
909
910 /* all latencies in usec */
911 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
912
58590c14
VS		 913 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
914
262cd2e1
VS		 915 if (IS_CHERRYVIEW(dev_priv)) {
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
917 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 918
919 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 920 }
921}
922
923static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
924 struct intel_crtc *crtc,
925 const struct intel_plane_state *state,
926 int level)
927{
928 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 929 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 930
931 if (dev_priv->wm.pri_latency[level] == 0)
932 return USHRT_MAX;
933
934 if (!state->visible)
935 return 0;
936
ac484963 937 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 938 clock = crtc->config->base.adjusted_mode.crtc_clock;
939 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
940 width = crtc->config->pipe_src_w;
941 if (WARN_ON(htotal == 0))
942 htotal = 1;
943
944 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
945 /*
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
950 */
951 wm = 63;
952 } else {
ac484963 953 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 954 dev_priv->wm.pri_latency[level] * 10);
955 }
956
957 return min_t(int, wm, USHRT_MAX);
958}
959
54f1b6e1
VS		 960static void vlv_compute_fifo(struct intel_crtc *crtc)
961{
962 struct drm_device *dev = crtc->base.dev;
963 struct vlv_wm_state *wm_state = &crtc->wm_state;
964 struct intel_plane *plane;
965 unsigned int total_rate = 0;
966 const int fifo_size = 512 - 1;
967 int fifo_extra, fifo_left = fifo_size;
968
969 for_each_intel_plane_on_crtc(dev, crtc, plane) {
970 struct intel_plane_state *state =
971 to_intel_plane_state(plane->base.state);
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
974 continue;
975
976 if (state->visible) {
977 wm_state->num_active_planes++;
978 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
979 }
980 }
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985 unsigned int rate;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 plane->wm.fifo_size = 63;
989 continue;
990 }
991
992 if (!state->visible) {
993 plane->wm.fifo_size = 0;
994 continue;
995 }
996
997 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 plane->wm.fifo_size = fifo_size * rate / total_rate;
999 fifo_left -= plane->wm.fifo_size;
1000 }
1001
1002 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 int plane_extra;
1007
1008 if (fifo_left == 0)
1009 break;
1010
1011 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012 continue;
1013
1014 /* give it all to the first plane if none are active */
1015 if (plane->wm.fifo_size == 0 &&
1016 wm_state->num_active_planes)
1017 continue;
1018
1019 plane_extra = min(fifo_extra, fifo_left);
1020 plane->wm.fifo_size += plane_extra;
1021 fifo_left -= plane_extra;
1022 }
1023
1024 WARN_ON(fifo_left != 0);
1025}
1026
262cd2e1
VS		 1027static void vlv_invert_wms(struct intel_crtc *crtc)
1028{
1029 struct vlv_wm_state *wm_state = &crtc->wm_state;
1030 int level;
1031
1032 for (level = 0; level < wm_state->num_levels; level++) {
1033 struct drm_device *dev = crtc->base.dev;
1034 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035 struct intel_plane *plane;
1036
1037 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041 switch (plane->base.type) {
1042 int sprite;
1043 case DRM_PLANE_TYPE_CURSOR:
1044 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045 wm_state->wm[level].cursor;
1046 break;
1047 case DRM_PLANE_TYPE_PRIMARY:
1048 wm_state->wm[level].primary = plane->wm.fifo_size -
1049 wm_state->wm[level].primary;
1050 break;
1051 case DRM_PLANE_TYPE_OVERLAY:
1052 sprite = plane->plane;
1053 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054 wm_state->wm[level].sprite[sprite];
1055 break;
1056 }
1057 }
1058 }
1059}
1060
26e1fe4f 1061static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1062{
1063 struct drm_device *dev = crtc->base.dev;
1064 struct vlv_wm_state *wm_state = &crtc->wm_state;
1065 struct intel_plane *plane;
1066 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067 int level;
1068
1069 memset(wm_state, 0, sizeof(*wm_state));
1070
852eb00d 1071 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1072 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1073
1074 wm_state->num_active_planes = 0;
262cd2e1 1075
54f1b6e1 1076 vlv_compute_fifo(crtc);
262cd2e1
VS		 1077
1078 if (wm_state->num_active_planes != 1)
1079 wm_state->cxsr = false;
1080
1081 if (wm_state->cxsr) {
1082 for (level = 0; level < wm_state->num_levels; level++) {
1083 wm_state->sr[level].plane = sr_fifo_size;
1084 wm_state->sr[level].cursor = 63;
1085 }
1086 }
1087
1088 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089 struct intel_plane_state *state =
1090 to_intel_plane_state(plane->base.state);
1091
1092 if (!state->visible)
1093 continue;
1094
1095 /* normal watermarks */
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100 /* hack */
1101 if (WARN_ON(level == 0 && wm > max_wm))
1102 wm = max_wm;
1103
1104 if (wm > plane->wm.fifo_size)
1105 break;
1106
1107 switch (plane->base.type) {
1108 int sprite;
1109 case DRM_PLANE_TYPE_CURSOR:
1110 wm_state->wm[level].cursor = wm;
1111 break;
1112 case DRM_PLANE_TYPE_PRIMARY:
1113 wm_state->wm[level].primary = wm;
1114 break;
1115 case DRM_PLANE_TYPE_OVERLAY:
1116 sprite = plane->plane;
1117 wm_state->wm[level].sprite[sprite] = wm;
1118 break;
1119 }
1120 }
1121
1122 wm_state->num_levels = level;
1123
1124 if (!wm_state->cxsr)
1125 continue;
1126
1127 /* maxfifo watermarks */
1128 switch (plane->base.type) {
1129 int sprite, level;
1130 case DRM_PLANE_TYPE_CURSOR:
1131 for (level = 0; level < wm_state->num_levels; level++)
1132 wm_state->sr[level].cursor =
5a37ed0a 1133 wm_state->wm[level].cursor;
262cd2e1
VS		 1134 break;
1135 case DRM_PLANE_TYPE_PRIMARY:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].plane =
1138 min(wm_state->sr[level].plane,
1139 wm_state->wm[level].primary);
1140 break;
1141 case DRM_PLANE_TYPE_OVERLAY:
1142 sprite = plane->plane;
1143 for (level = 0; level < wm_state->num_levels; level++)
1144 wm_state->sr[level].plane =
1145 min(wm_state->sr[level].plane,
1146 wm_state->wm[level].sprite[sprite]);
1147 break;
1148 }
1149 }
1150
1151 /* clear any (partially) filled invalid levels */
58590c14 1152 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1153 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155 }
1156
1157 vlv_invert_wms(crtc);
1158}
1159
54f1b6e1
VS		 1160#define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164{
1165 struct drm_device *dev = crtc->base.dev;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 struct intel_plane *plane;
1168 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172 WARN_ON(plane->wm.fifo_size != 63);
1173 continue;
1174 }
1175
1176 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177 sprite0_start = plane->wm.fifo_size;
1178 else if (plane->plane == 0)
1179 sprite1_start = sprite0_start + plane->wm.fifo_size;
1180 else
1181 fifo_size = sprite1_start + plane->wm.fifo_size;
1182 }
1183
1184 WARN_ON(fifo_size != 512 - 1);
1185
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc->pipe), sprite0_start,
1188 sprite1_start, fifo_size);
1189
1190 switch (crtc->pipe) {
1191 uint32_t dsparb, dsparb2, dsparb3;
1192 case PIPE_A:
1193 dsparb = I915_READ(DSPARB);
1194 dsparb2 = I915_READ(DSPARB2);
1195
1196 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197 VLV_FIFO(SPRITEB, 0xff));
1198 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199 VLV_FIFO(SPRITEB, sprite1_start));
1200
1201 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202 VLV_FIFO(SPRITEB_HI, 0x1));
1203 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206 I915_WRITE(DSPARB, dsparb);
1207 I915_WRITE(DSPARB2, dsparb2);
1208 break;
1209 case PIPE_B:
1210 dsparb = I915_READ(DSPARB);
1211 dsparb2 = I915_READ(DSPARB2);
1212
1213 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214 VLV_FIFO(SPRITED, 0xff));
1215 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216 VLV_FIFO(SPRITED, sprite1_start));
1217
1218 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219 VLV_FIFO(SPRITED_HI, 0xff));
1220 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223 I915_WRITE(DSPARB, dsparb);
1224 I915_WRITE(DSPARB2, dsparb2);
1225 break;
1226 case PIPE_C:
1227 dsparb3 = I915_READ(DSPARB3);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231 VLV_FIFO(SPRITEF, 0xff));
1232 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233 VLV_FIFO(SPRITEF, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236 VLV_FIFO(SPRITEF_HI, 0xff));
1237 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB3, dsparb3);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 default:
1244 break;
1245 }
1246}
1247
1248#undef VLV_FIFO
1249
262cd2e1
VS		 1250static void vlv_merge_wm(struct drm_device *dev,
1251 struct vlv_wm_values *wm)
1252{
1253 struct intel_crtc *crtc;
1254 int num_active_crtcs = 0;
1255
58590c14 1256 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1257 wm->cxsr = true;
1258
1259 for_each_intel_crtc(dev, crtc) {
1260 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262 if (!crtc->active)
1263 continue;
1264
1265 if (!wm_state->cxsr)
1266 wm->cxsr = false;
1267
1268 num_active_crtcs++;
1269 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270 }
1271
1272 if (num_active_crtcs != 1)
1273 wm->cxsr = false;
1274
6f9c784b
VS		 1275 if (num_active_crtcs > 1)
1276 wm->level = VLV_WM_LEVEL_PM2;
1277
262cd2e1
VS		 1278 for_each_intel_crtc(dev, crtc) {
1279 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280 enum pipe pipe = crtc->pipe;
1281
1282 if (!crtc->active)
1283 continue;
1284
1285 wm->pipe[pipe] = wm_state->wm[wm->level];
1286 if (wm->cxsr)
1287 wm->sr = wm_state->sr[wm->level];
1288
1289 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293 }
1294}
1295
1296static void vlv_update_wm(struct drm_crtc *crtc)
1297{
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301 enum pipe pipe = intel_crtc->pipe;
1302 struct vlv_wm_values wm = {};
1303
26e1fe4f 1304 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1305 vlv_merge_wm(dev, &wm);
1306
54f1b6e1
VS		 1307 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1310 return;
54f1b6e1 1311 }
262cd2e1
VS		 1312
1313 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315 chv_set_memory_dvfs(dev_priv, false);
1316
1317 if (wm.level < VLV_WM_LEVEL_PM5 &&
1318 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319 chv_set_memory_pm5(dev_priv, false);
1320
852eb00d 1321 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1322 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1323
54f1b6e1
VS		 1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc);
1326
262cd2e1
VS		 1327 vlv_write_wm_values(intel_crtc, &wm);
1328
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
852eb00d 1335 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1337
1338 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340 chv_set_memory_pm5(dev_priv, true);
1341
1342 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, true);
1345
1346 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1347}
1348
ae80152d
VS		 1349#define single_plane_enabled(mask) is_power_of_2(mask)
1350
46ba614c 1351static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1352{
46ba614c 1353 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
9858425c 1359 bool cxsr_enabled;
b445e3b0 1360
51cea1f4 1361 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1362 &g4x_wm_info, pessimal_latency_ns,
1363 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1364 &planea_wm, &cursora_wm))
51cea1f4 1365 enabled |= 1 << PIPE_A;
b445e3b0 1366
51cea1f4 1367 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1368 &g4x_wm_info, pessimal_latency_ns,
1369 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1370 &planeb_wm, &cursorb_wm))
51cea1f4 1371 enabled |= 1 << PIPE_B;
b445e3b0 1372
b445e3b0
ED		 1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
52bd02d8 1378 &plane_sr, &cursor_sr)) {
9858425c 1379 cxsr_enabled = true;
52bd02d8 1380 } else {
9858425c 1381 cxsr_enabled = false;
5209b1f4 1382 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1383 plane_sr = cursor_sr = 0;
1384 }
b445e3b0 1385
a5043453
VS		 1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1388 planea_wm, cursora_wm,
1389 planeb_wm, cursorb_wm,
1390 plane_sr, cursor_sr);
1391
1392 I915_WRITE(DSPFW1,
f4998963
VS		 1393 FW_WM(plane_sr, SR) |
1394 FW_WM(cursorb_wm, CURSORB) |
1395 FW_WM(planeb_wm, PLANEB) |
1396 FW_WM(planea_wm, PLANEA));
b445e3b0 1397 I915_WRITE(DSPFW2,
8c919b28 1398 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1399 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1400 /* HPLL off in SR has some issues on G4x... disable it */
1401 I915_WRITE(DSPFW3,
8c919b28 1402 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1403 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1407}
1408
46ba614c 1409static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1410{
46ba614c 1411 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc;
1414 int srwm = 1;
1415 int cursor_sr = 16;
9858425c 1416 bool cxsr_enabled;
b445e3b0
ED		 1417
1418 /* Calc sr entries for one plane configs */
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc) {
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns = 12000;
124abe07 1423 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1424 int clock = adjusted_mode->crtc_clock;
fec8cba3 1425 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1426 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1427 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1428 unsigned long line_time_us;
1429 int entries;
1430
922044c9 1431 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1432
1433 /* Use ns/us then divide to preserve precision */
1434 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1435 cpp * hdisplay;
b445e3b0
ED		 1436 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437 srwm = I965_FIFO_SIZE - entries;
1438 if (srwm < 0)
1439 srwm = 1;
1440 srwm &= 0x1ff;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442 entries, srwm);
1443
1444 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1445 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1446 entries = DIV_ROUND_UP(entries,
1447 i965_cursor_wm_info.cacheline_size);
1448 cursor_sr = i965_cursor_wm_info.fifo_size -
1449 (entries + i965_cursor_wm_info.guard_size);
1450
1451 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452 cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm, cursor_sr);
1456
9858425c 1457 cxsr_enabled = true;
b445e3b0 1458 } else {
9858425c 1459 cxsr_enabled = false;
b445e3b0 1460 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1461 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1462 }
1463
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465 srwm);
1466
1467 /* 965 has limitations... */
f4998963
VS		 1468 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469 FW_WM(8, CURSORB) |
1470 FW_WM(8, PLANEB) |
1471 FW_WM(8, PLANEA));
1472 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473 FW_WM(8, PLANEC_OLD));
b445e3b0 1474 /* update cursor SR watermark */
f4998963 1475 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1479}
1480
f4998963
VS		 1481#undef FW_WM
1482
46ba614c 1483static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1484{
46ba614c 1485 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 const struct intel_watermark_params *wm_info;
1488 uint32_t fwater_lo;
1489 uint32_t fwater_hi;
1490 int cwm, srwm = 1;
1491 int fifo_size;
1492 int planea_wm, planeb_wm;
1493 struct drm_crtc *crtc, *enabled = NULL;
1494
1495 if (IS_I945GM(dev))
1496 wm_info = &i945_wm_info;
1497 else if (!IS_GEN2(dev))
1498 wm_info = &i915_wm_info;
1499 else
9d539105 1500 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1504 if (intel_crtc_active(crtc)) {
241bfc38 1505 const struct drm_display_mode *adjusted_mode;
ac484963 1506 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1507 if (IS_GEN2(dev))
1508 cpp = 4;
1509
6e3c9717 1510 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1511 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1512 wm_info, fifo_size, cpp,
5aef6003 1513 pessimal_latency_ns);
b445e3b0 1514 enabled = crtc;
9d539105 1515 } else {
b445e3b0 1516 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1517 if (planea_wm > (long)wm_info->max_wm)
1518 planea_wm = wm_info->max_wm;
1519 }
1520
1521 if (IS_GEN2(dev))
1522 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1526 if (intel_crtc_active(crtc)) {
241bfc38 1527 const struct drm_display_mode *adjusted_mode;
ac484963 1528 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
6e3c9717 1532 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1534 wm_info, fifo_size, cpp,
5aef6003 1535 pessimal_latency_ns);
b445e3b0
ED		 1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
9d539105 1540 } else {
b445e3b0 1541 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1542 if (planeb_wm > (long)wm_info->max_wm)
1543 planeb_wm = wm_info->max_wm;
1544 }
b445e3b0
ED		 1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d 1548 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1549 struct drm_i915_gem_object *obj;
2ab1bc9d 1550
59bea882 1551 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1552
1553 /* self-refresh seems busted with untiled */
2ff8fde1 1554 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1564 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
124abe07 1570 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1571 int clock = adjusted_mode->crtc_clock;
fec8cba3 1572 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1573 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1574 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1575 unsigned long line_time_us;
1576 int entries;
1577
922044c9 1578 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1579
1580 /* Use ns/us then divide to preserve precision */
1581 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1582 cpp * hdisplay;
b445e3b0
ED		 1583 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585 srwm = wm_info->fifo_size - entries;
1586 if (srwm < 0)
1587 srwm = 1;
1588
1589 if (IS_I945G(dev) || IS_I945GM(dev))
1590 I915_WRITE(FW_BLC_SELF,
1591 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594 }
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm, planeb_wm, cwm, srwm);
1598
1599 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600 fwater_hi = (cwm & 0x1f);
1601
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604 fwater_hi = fwater_hi | (1 << 8);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 I915_WRITE(FW_BLC2, fwater_hi);
1608
5209b1f4
ID		 1609 if (enabled)
1610 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1611}
1612
feb56b93 1613static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1614{
46ba614c 1615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
241bfc38 1618 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
6e3c9717 1626 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1628 &i845_wm_info,
b445e3b0 1629 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1630 4, pessimal_latency_ns);
b445e3b0
ED		 1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637}
1638
8cfb3407 1639uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1640{
fd4daa9c 1641 uint32_t pixel_rate;
801bcfff 1642
8cfb3407 1643 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1644
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1647
8cfb3407 1648 if (pipe_config->pch_pfit.enabled) {
801bcfff 1649 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1650 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652 pipe_w = pipe_config->pipe_src_w;
1653 pipe_h = pipe_config->pipe_src_h;
801bcfff 1654
801bcfff
PZ		 1655 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656 pfit_h = pfit_size & 0xFFFF;
1657 if (pipe_w < pfit_w)
1658 pipe_w = pfit_w;
1659 if (pipe_h < pfit_h)
1660 pipe_h = pfit_h;
1661
15126882
MR		 1662 if (WARN_ON(!pfit_w || !pfit_h))
1663 return pixel_rate;
1664
801bcfff
PZ		 1665 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666 pfit_w * pfit_h);
1667 }
1668
1669 return pixel_rate;
1670}
1671
37126462 1672/* latency must be in 0.1us units. */
ac484963 1673static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1674{
1675 uint64_t ret;
1676
3312ba65
VS		 1677 if (WARN(latency == 0, "Latency value missing\n"))
1678 return UINT_MAX;
1679
ac484963 1680 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1681 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683 return ret;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
23297044 1687static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1688 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1689 uint32_t latency)
1690{
1691 uint32_t ret;
1692
3312ba65
VS		 1693 if (WARN(latency == 0, "Latency value missing\n"))
1694 return UINT_MAX;
15126882
MR		 1695 if (WARN_ON(!pipe_htotal))
1696 return UINT_MAX;
3312ba65 1697
801bcfff 1698 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1699 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1700 ret = DIV_ROUND_UP(ret, 64) + 2;
1701 return ret;
1702}
1703
23297044 1704static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1705 uint8_t cpp)
cca32e9a 1706{
15126882
MR		 1707 /*
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1712 */
ac484963 1713 if (WARN_ON(!cpp))
15126882
MR		 1714 return 0;
1715 if (WARN_ON(!horiz_pixels))
1716 return 0;
1717
ac484963 1718 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1719}
1720
820c1980 1721struct ilk_wm_maximums {
cca32e9a
PZ		 1722 uint16_t pri;
1723 uint16_t spr;
1724 uint16_t cur;
1725 uint16_t fbc;
1726};
1727
37126462
VS		 1728/*
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1731 */
7221fc33 1732static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1733 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1734 uint32_t mem_value,
1735 bool is_lp)
801bcfff 1736{
ac484963
VS		 1737 int cpp = pstate->base.fb ?
1738 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1739 uint32_t method1, method2;
1740
7221fc33 1741 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1742 return 0;
1743
ac484963 1744 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1745
1746 if (!is_lp)
1747 return method1;
1748
7221fc33
MR		 1749 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1751 drm_rect_width(&pstate->dst),
ac484963 1752 cpp, mem_value);
cca32e9a
PZ		 1753
1754 return min(method1, method2);
801bcfff
PZ		 1755}
1756
37126462
VS		 1757/*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
7221fc33 1761static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1762 const struct intel_plane_state *pstate,
801bcfff
PZ		 1763 uint32_t mem_value)
1764{
ac484963
VS		 1765 int cpp = pstate->base.fb ?
1766 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1767 uint32_t method1, method2;
1768
7221fc33 1769 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1770 return 0;
1771
ac484963 1772 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1775 drm_rect_width(&pstate->dst),
ac484963 1776 cpp, mem_value);
801bcfff
PZ		 1777 return min(method1, method2);
1778}
1779
37126462
VS		 1780/*
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1783 */
7221fc33 1784static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1785 const struct intel_plane_state *pstate,
801bcfff
PZ		 1786 uint32_t mem_value)
1787{
b2435692
MR		 1788 /*
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1792 */
1793 int cpp = 4;
1794 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1795
b2435692 1796 if (!cstate->base.active)
801bcfff
PZ		 1797 return 0;
1798
7221fc33
MR		 1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1801 width, cpp, mem_value);
801bcfff
PZ		 1802}
1803
cca32e9a 1804/* Only for WM_LP. */
7221fc33 1805static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1806 const struct intel_plane_state *pstate,
1fda9882 1807 uint32_t pri_val)
cca32e9a 1808{
ac484963
VS		 1809 int cpp = pstate->base.fb ?
1810 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1811
7221fc33 1812 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1813 return 0;
1814
ac484963 1815 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1816}
1817
158ae64f
VS		 1818static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819{
416f4727
VS		 1820 if (INTEL_INFO(dev)->gen >= 8)
1821 return 3072;
1822 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1823 return 768;
1824 else
1825 return 512;
1826}
1827
4e975081
VS		 1828static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829 int level, bool is_sprite)
1830{
1831 if (INTEL_INFO(dev)->gen >= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level == 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev)->gen >= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level == 0 ? 127 : 1023;
1837 else if (!is_sprite)
1838 /* ILK/SNB primary plane watermarks */
1839 return level == 0 ? 127 : 511;
1840 else
1841 /* ILK/SNB sprite plane watermarks */
1842 return level == 0 ? 63 : 255;
1843}
1844
1845static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846 int level)
1847{
1848 if (INTEL_INFO(dev)->gen >= 7)
1849 return level == 0 ? 63 : 255;
1850 else
1851 return level == 0 ? 31 : 63;
1852}
1853
1854static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855{
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 return 31;
1858 else
1859 return 15;
1860}
1861
158ae64f
VS		 1862/* Calculate the maximum primary/sprite plane watermark */
1863static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 int level,
240264f4 1865 const struct intel_wm_config *config,
158ae64f
VS		 1866 enum intel_ddb_partitioning ddb_partitioning,
1867 bool is_sprite)
1868{
1869 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1870
1871 /* if sprites aren't enabled, sprites get nothing */
240264f4 1872 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1873 return 0;
1874
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1876 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1877 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879 /*
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1883 */
1884 if (INTEL_INFO(dev)->gen <= 6)
1885 fifo_size /= 2;
1886 }
1887
240264f4 1888 if (config->sprites_enabled) {
158ae64f
VS		 1889 /* level 0 is always calculated with 1:1 split */
1890 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891 if (is_sprite)
1892 fifo_size *= 5;
1893 fifo_size /= 6;
1894 } else {
1895 fifo_size /= 2;
1896 }
1897 }
1898
1899 /* clamp to max that the registers can hold */
4e975081 1900 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1901}
1902
1903/* Calculate the maximum cursor plane watermark */
1904static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1905 int level,
1906 const struct intel_wm_config *config)
158ae64f
VS		 1907{
1908 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1909 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1910 return 64;
1911
1912 /* otherwise just report max that registers can hold */
4e975081 1913 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1914}
1915
d34ff9c6 1916static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1917 int level,
1918 const struct intel_wm_config *config,
1919 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1920 struct ilk_wm_maximums *max)
158ae64f 1921{
240264f4
VS		 1922 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1925 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1926}
1927
a3cb4048
VS		 1928static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 int level,
1930 struct ilk_wm_maximums *max)
1931{
1932 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934 max->cur = ilk_cursor_wm_reg_max(dev, level);
1935 max->fbc = ilk_fbc_wm_reg_max(dev);
1936}
1937
d9395655 1938static bool ilk_validate_wm_level(int level,
820c1980 1939 const struct ilk_wm_maximums *max,
d9395655 1940 struct intel_wm_level *result)
a9786a11
VS		 1941{
1942 bool ret;
1943
1944 /* already determined to be invalid? */
1945 if (!result->enable)
1946 return false;
1947
1948 result->enable = result->pri_val <= max->pri &&
1949 result->spr_val <= max->spr &&
1950 result->cur_val <= max->cur;
1951
1952 ret = result->enable;
1953
1954 /*
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1957 * are exceeded...
1958 */
1959 if (level == 0 && !result->enable) {
1960 if (result->pri_val > max->pri)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level, result->pri_val, max->pri);
1963 if (result->spr_val > max->spr)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level, result->spr_val, max->spr);
1966 if (result->cur_val > max->cur)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level, result->cur_val, max->cur);
1969
1970 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973 result->enable = true;
1974 }
1975
a9786a11
VS		 1976 return ret;
1977}
1978
d34ff9c6 1979static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1980 const struct intel_crtc *intel_crtc,
6f5ddd17 1981 int level,
7221fc33 1982 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1983 struct intel_plane_state *pristate,
1984 struct intel_plane_state *sprstate,
1985 struct intel_plane_state *curstate,
1fd527cc 1986 struct intel_wm_level *result)
6f5ddd17
VS		 1987{
1988 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992 /* WM1+ latency values stored in 0.5us units */
1993 if (level > 0) {
1994 pri_latency *= 5;
1995 spr_latency *= 5;
1996 cur_latency *= 5;
1997 }
1998
e3bddded
ML		 1999 if (pristate) {
2000 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001 pri_latency, level);
2002 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003 }
2004
2005 if (sprstate)
2006 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008 if (curstate)
2009 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
6f5ddd17
VS		 2011 result->enable = true;
2012}
2013
801bcfff 2014static uint32_t
532f7a7f 2015hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2016{
532f7a7f
VS		 2017 const struct intel_atomic_state *intel_state =
2018 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2019 const struct drm_display_mode *adjusted_mode =
2020 &cstate->base.adjusted_mode;
85a02deb 2021 u32 linetime, ips_linetime;
1f8eeabf 2022
ee91a159
MR		 2023 if (!cstate->base.active)
2024 return 0;
2025 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026 return 0;
532f7a7f 2027 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2028 return 0;
1011d8c4 2029
1f8eeabf
ED		 2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2032 * */
124abe07
VS		 2033 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034 adjusted_mode->crtc_clock);
2035 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2036 intel_state->cdclk);
1f8eeabf 2037
801bcfff
PZ		 2038 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2040}
2041
2af30a5c 2042static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2043{
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045
2af30a5c
PB		 2046 if (IS_GEN9(dev)) {
2047 uint32_t val;
4f947386 2048 int ret, i;
367294be 2049 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2050
2051 /* read the first set of memory latencies[0:3] */
2052 val = 0; /* data0 to be programmed to 0 for first set */
2053 mutex_lock(&dev_priv->rps.hw_lock);
2054 ret = sandybridge_pcode_read(dev_priv,
2055 GEN9_PCODE_READ_MEM_LATENCY,
2056 &val);
2057 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059 if (ret) {
2060 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061 return;
2062 }
2063
2064 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072 /* read the second set of memory latencies[4:7] */
2073 val = 1; /* data0 to be programmed to 1 for second set */
2074 mutex_lock(&dev_priv->rps.hw_lock);
2075 ret = sandybridge_pcode_read(dev_priv,
2076 GEN9_PCODE_READ_MEM_LATENCY,
2077 &val);
2078 mutex_unlock(&dev_priv->rps.hw_lock);
2079 if (ret) {
2080 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081 return;
2082 }
2083
2084 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
367294be 2092 /*
6f97235b
DL		 2093 * WaWmMemoryReadLatency:skl
2094 *
367294be
VK		 2095 * punit doesn't take into account the read latency so we need
2096 * to add 2us to the various latency levels we retrieve from
2097 * the punit.
2098 * - W0 is a bit special in that it's the only level that
2099 * can't be disabled if we want to have display working, so
2100 * we always add 2us there.
2101 * - For levels >=1, punit returns 0us latency when they are
2102 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2103 *
2104 * Additionally, if a level n (n > 1) has a 0us latency, all
2105 * levels m (m >= n) need to be disabled. We make sure to
2106 * sanitize the values out of the punit to satisfy this
2107 * requirement.
367294be
VK		 2108 */
2109 wm[0] += 2;
2110 for (level = 1; level <= max_level; level++)
2111 if (wm[level] != 0)
2112 wm[level] += 2;
4f947386
VK		 2113 else {
2114 for (i = level + 1; i <= max_level; i++)
2115 wm[i] = 0;
367294be 2116
4f947386
VK		 2117 break;
2118 }
2af30a5c 2119 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2120 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122 wm[0] = (sskpd >> 56) & 0xFF;
2123 if (wm[0] == 0)
2124 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2125 wm[1] = (sskpd >> 4) & 0xFF;
2126 wm[2] = (sskpd >> 12) & 0xFF;
2127 wm[3] = (sskpd >> 20) & 0x1FF;
2128 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2129 } else if (INTEL_INFO(dev)->gen >= 6) {
2130 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2136 } else if (INTEL_INFO(dev)->gen >= 5) {
2137 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139 /* ILK primary LP0 latency is 700 ns */
2140 wm[0] = 7;
2141 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2143 }
2144}
2145
53615a5e
VS		 2146static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147{
2148 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2149 if (IS_GEN5(dev))
53615a5e
VS		 2150 wm[0] = 13;
2151}
2152
2153static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154{
2155 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2156 if (IS_GEN5(dev))
53615a5e
VS		 2157 wm[0] = 13;
2158
2159 /* WaDoubleCursorLP3Latency:ivb */
2160 if (IS_IVYBRIDGE(dev))
2161 wm[3] *= 2;
2162}
2163
546c81fd 2164int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2165{
26ec971e 2166 /* how many WM levels are we expecting */
b6e742f6 2167 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2168 return 7;
2169 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2170 return 4;
26ec971e 2171 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2172 return 3;
26ec971e 2173 else
ad0d6dc4
VS		 2174 return 2;
2175}
7526ed79 2176
ad0d6dc4
VS		 2177static void intel_print_wm_latency(struct drm_device *dev,
2178 const char *name,
2af30a5c 2179 const uint16_t wm[8])
ad0d6dc4
VS		 2180{
2181 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2182
2183 for (level = 0; level <= max_level; level++) {
2184 unsigned int latency = wm[level];
2185
2186 if (latency == 0) {
2187 DRM_ERROR("%s WM%d latency not provided\n",
2188 name, level);
2189 continue;
2190 }
2191
2af30a5c
PB		 2192 /*
2193 * - latencies are in us on gen9.
2194 * - before then, WM1+ latency values are in 0.5us units
2195 */
2196 if (IS_GEN9(dev))
2197 latency *= 10;
2198 else if (level > 0)
26ec971e
VS		 2199 latency *= 5;
2200
2201 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202 name, level, wm[level],
2203 latency / 10, latency % 10);
2204 }
2205}
2206
e95a2f75
VS		 2207static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208 uint16_t wm[5], uint16_t min)
2209{
2210 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212 if (wm[0] >= min)
2213 return false;
2214
2215 wm[0] = max(wm[0], min);
2216 for (level = 1; level <= max_level; level++)
2217 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219 return true;
2220}
2221
2222static void snb_wm_latency_quirk(struct drm_device *dev)
2223{
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 bool changed;
2226
2227 /*
2228 * The BIOS provided WM memory latency values are often
2229 * inadequate for high resolution displays. Adjust them.
2230 */
2231 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235 if (!changed)
2236 return;
2237
2238 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242}
2243
fa50ad61 2244static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2245{
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251 sizeof(dev_priv->wm.pri_latency));
2252 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254
2255 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2257
2258 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2261
2262 if (IS_GEN6(dev))
2263 snb_wm_latency_quirk(dev);
53615a5e
VS		 2264}
2265
2af30a5c
PB		 2266static void skl_setup_wm_latency(struct drm_device *dev)
2267{
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272}
2273
ed4a6a7c
MR		 2274static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275 struct intel_pipe_wm *pipe_wm)
2276{
2277 /* LP0 watermark maximums depend on this pipe alone */
2278 const struct intel_wm_config config = {
2279 .num_pipes_active = 1,
2280 .sprites_enabled = pipe_wm->sprites_enabled,
2281 .sprites_scaled = pipe_wm->sprites_scaled,
2282 };
2283 struct ilk_wm_maximums max;
2284
2285 /* LP0 watermarks always use 1/2 DDB partitioning */
2286 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288 /* At least LP0 must be valid */
2289 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291 return false;
2292 }
2293
2294 return true;
2295}
2296
0b2ae6d7 2297/* Compute new watermarks for the pipe */
e3bddded 2298static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2299{
e3bddded
ML		 2300 struct drm_atomic_state *state = cstate->base.state;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2302 struct intel_pipe_wm *pipe_wm;
e3bddded 2303 struct drm_device *dev = state->dev;
d34ff9c6 2304 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2305 struct intel_plane *intel_plane;
86c8bbbe 2306 struct intel_plane_state *pristate = NULL;
43d59eda 2307 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2308 struct intel_plane_state *curstate = NULL;
d81f04c5 2309 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2310 struct ilk_wm_maximums max;
0b2ae6d7 2311
e8f1f02e 2312 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2313
43d59eda 2314 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2315 struct intel_plane_state *ps;
2316
2317 ps = intel_atomic_get_existing_plane_state(state,
2318 intel_plane);
2319 if (!ps)
2320 continue;
86c8bbbe
MR		 2321
2322 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2323 pristate = ps;
86c8bbbe 2324 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2325 sprstate = ps;
86c8bbbe 2326 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2327 curstate = ps;
43d59eda
MR		 2328 }
2329
ed4a6a7c 2330 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2331 if (sprstate) {
2332 pipe_wm->sprites_enabled = sprstate->visible;
2333 pipe_wm->sprites_scaled = sprstate->visible &&
2334 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336 }
2337
d81f04c5
ML		 2338 usable_level = max_level;
2339
7b39a0b7 2340 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2341 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2342 usable_level = 1;
7b39a0b7
VS		 2343
2344 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2345 if (pipe_wm->sprites_scaled)
d81f04c5 2346 usable_level = 0;
7b39a0b7 2347
86c8bbbe 2348 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2349 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2353
a42a5719 2354 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2355 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2356
ed4a6a7c 2357 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2358 return -EINVAL;
a3cb4048
VS		 2359
2360 ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362 for (level = 1; level <= max_level; level++) {
71f0a626 2363 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2364
86c8bbbe 2365 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2366 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2367
2368 /*
2369 * Disable any watermark level that exceeds the
2370 * register maximums since such watermarks are
2371 * always invalid.
2372 */
71f0a626
ML		 2373 if (level > usable_level)
2374 continue;
2375
2376 if (ilk_validate_wm_level(level, &max, wm))
2377 pipe_wm->wm[level] = *wm;
2378 else
d81f04c5 2379 usable_level = level;
a3cb4048
VS		 2380 }
2381
86c8bbbe 2382 return 0;
0b2ae6d7
VS		 2383}
2384
ed4a6a7c
MR		 2385/*
2386 * Build a set of 'intermediate' watermark values that satisfy both the old
2387 * state and the new state. These can be programmed to the hardware
2388 * immediately.
2389 */
2390static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391 struct intel_crtc *intel_crtc,
2392 struct intel_crtc_state *newstate)
2393{
e8f1f02e 2394 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2395 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396 int level, max_level = ilk_wm_max_level(dev);
2397
2398 /*
2399 * Start with the final, target watermarks, then combine with the
2400 * currently active watermarks to get values that are safe both before
2401 * and after the vblank.
2402 */
e8f1f02e 2403 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2404 a->pipe_enabled |= b->pipe_enabled;
2405 a->sprites_enabled |= b->sprites_enabled;
2406 a->sprites_scaled |= b->sprites_scaled;
2407
2408 for (level = 0; level <= max_level; level++) {
2409 struct intel_wm_level *a_wm = &a->wm[level];
2410 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412 a_wm->enable &= b_wm->enable;
2413 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417 }
2418
2419 /*
2420 * We need to make sure that these merged watermark values are
2421 * actually a valid configuration themselves. If they're not,
2422 * there's no safe way to transition from the old state to
2423 * the new state, so we need to fail the atomic transaction.
2424 */
2425 if (!ilk_validate_pipe_wm(dev, a))
2426 return -EINVAL;
2427
2428 /*
2429 * If our intermediate WM are identical to the final WM, then we can
2430 * omit the post-vblank programming; only update if it's different.
2431 */
e8f1f02e 2432 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2433 newstate->wm.need_postvbl_update = false;
2434
2435 return 0;
2436}
2437
0b2ae6d7
VS		 2438/*
2439 * Merge the watermarks from all active pipes for a specific level.
2440 */
2441static void ilk_merge_wm_level(struct drm_device *dev,
2442 int level,
2443 struct intel_wm_level *ret_wm)
2444{
2445 const struct intel_crtc *intel_crtc;
2446
d52fea5b
VS		 2447 ret_wm->enable = true;
2448
d3fcc808 2449 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2450 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2451 const struct intel_wm_level *wm = &active->wm[level];
2452
2453 if (!active->pipe_enabled)
2454 continue;
0b2ae6d7 2455
d52fea5b
VS		 2456 /*
2457 * The watermark values may have been used in the past,
2458 * so we must maintain them in the registers for some
2459 * time even if the level is now disabled.
2460 */
0b2ae6d7 2461 if (!wm->enable)
d52fea5b 2462 ret_wm->enable = false;
0b2ae6d7
VS		 2463
2464 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468 }
0b2ae6d7
VS		 2469}
2470
2471/*
2472 * Merge all low power watermarks for all active pipes.
2473 */
2474static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2475 const struct intel_wm_config *config,
820c1980 2476 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2477 struct intel_pipe_wm *merged)
2478{
7733b49b 2479 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2480 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2481 int last_enabled_level = max_level;
0b2ae6d7 2482
0ba22e26
VS		 2483 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485 config->num_pipes_active > 1)
1204d5ba 2486 last_enabled_level = 0;
0ba22e26 2487
6c8b6c28
VS		 2488 /* ILK: FBC WM must be disabled always */
2489 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2490
2491 /* merge each WM1+ level */
2492 for (level = 1; level <= max_level; level++) {
2493 struct intel_wm_level *wm = &merged->wm[level];
2494
2495 ilk_merge_wm_level(dev, level, wm);
2496
d52fea5b
VS		 2497 if (level > last_enabled_level)
2498 wm->enable = false;
2499 else if (!ilk_validate_wm_level(level, max, wm))
2500 /* make sure all following levels get disabled */
2501 last_enabled_level = level - 1;
0b2ae6d7
VS		 2502
2503 /*
2504 * The spec says it is preferred to disable
2505 * FBC WMs instead of disabling a WM level.
2506 */
2507 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2508 if (wm->enable)
2509 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2510 wm->fbc_val = 0;
2511 }
2512 }
6c8b6c28
VS		 2513
2514 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515 /*
2516 * FIXME this is racy. FBC might get enabled later.
2517 * What we should check here is whether FBC can be
2518 * enabled sometime later.
2519 */
7733b49b 2520 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2521 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2522 for (level = 2; level <= max_level; level++) {
2523 struct intel_wm_level *wm = &merged->wm[level];
2524
2525 wm->enable = false;
2526 }
2527 }
0b2ae6d7
VS		 2528}
2529
b380ca3c
VS		 2530static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531{
2532 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534}
2535
a68d68ee
VS		 2536/* The value we need to program into the WM_LPx latency field */
2537static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538{
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540
a42a5719 2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2542 return 2 * level;
2543 else
2544 return dev_priv->wm.pri_latency[level];
2545}
2546
820c1980 2547static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2548 const struct intel_pipe_wm *merged,
609cedef 2549 enum intel_ddb_partitioning partitioning,
820c1980 2550 struct ilk_wm_values *results)
801bcfff 2551{
0b2ae6d7
VS		 2552 struct intel_crtc *intel_crtc;
2553 int level, wm_lp;
cca32e9a 2554
0362c781 2555 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2556 results->partitioning = partitioning;
cca32e9a 2557
0b2ae6d7 2558 /* LP1+ register values */
cca32e9a 2559 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2560 const struct intel_wm_level *r;
801bcfff 2561
b380ca3c 2562 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2563
0362c781 2564 r = &merged->wm[level];
cca32e9a 2565
d52fea5b
VS		 2566 /*
2567 * Maintain the watermark values even if the level is
2568 * disabled. Doing otherwise could cause underruns.
2569 */
2570 results->wm_lp[wm_lp - 1] =
a68d68ee 2571 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2572 (r->pri_val << WM1_LP_SR_SHIFT) |
2573 r->cur_val;
2574
d52fea5b
VS		 2575 if (r->enable)
2576 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
416f4727
VS		 2578 if (INTEL_INFO(dev)->gen >= 8)
2579 results->wm_lp[wm_lp - 1] |=
2580 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581 else
2582 results->wm_lp[wm_lp - 1] |=
2583 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
d52fea5b
VS		 2585 /*
2586 * Always set WM1S_LP_EN when spr_val != 0, even if the
2587 * level is disabled. Doing otherwise could cause underruns.
2588 */
6cef2b8a
VS		 2589 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590 WARN_ON(wm_lp != 1);
2591 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592 } else
2593 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2594 }
801bcfff 2595
0b2ae6d7 2596 /* LP0 register values */
d3fcc808 2597 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2598 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2599 const struct intel_wm_level *r =
2600 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2601
2602 if (WARN_ON(!r->enable))
2603 continue;
2604
ed4a6a7c 2605 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2606
0b2ae6d7
VS		 2607 results->wm_pipe[pipe] =
2608 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610 r->cur_val;
801bcfff
PZ		 2611 }
2612}
2613
861f3389
PZ		 2614/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2616static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2617 struct intel_pipe_wm *r1,
2618 struct intel_pipe_wm *r2)
861f3389 2619{
198a1e9b
VS		 2620 int level, max_level = ilk_wm_max_level(dev);
2621 int level1 = 0, level2 = 0;
861f3389 2622
198a1e9b
VS		 2623 for (level = 1; level <= max_level; level++) {
2624 if (r1->wm[level].enable)
2625 level1 = level;
2626 if (r2->wm[level].enable)
2627 level2 = level;
861f3389
PZ		 2628 }
2629
198a1e9b
VS		 2630 if (level1 == level2) {
2631 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2632 return r2;
2633 else
2634 return r1;
198a1e9b 2635 } else if (level1 > level2) {
861f3389
PZ		 2636 return r1;
2637 } else {
2638 return r2;
2639 }
2640}
2641
49a687c4
VS		 2642/* dirty bits used to track which watermarks need changes */
2643#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647#define WM_DIRTY_FBC (1 << 24)
2648#define WM_DIRTY_DDB (1 << 25)
2649
055e393f 2650static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2651 const struct ilk_wm_values *old,
2652 const struct ilk_wm_values *new)
49a687c4
VS		 2653{
2654 unsigned int dirty = 0;
2655 enum pipe pipe;
2656 int wm_lp;
2657
055e393f 2658 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2659 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660 dirty |= WM_DIRTY_LINETIME(pipe);
2661 /* Must disable LP1+ watermarks too */
2662 dirty |= WM_DIRTY_LP_ALL;
2663 }
2664
2665 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666 dirty |= WM_DIRTY_PIPE(pipe);
2667 /* Must disable LP1+ watermarks too */
2668 dirty |= WM_DIRTY_LP_ALL;
2669 }
2670 }
2671
2672 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673 dirty |= WM_DIRTY_FBC;
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677
2678 if (old->partitioning != new->partitioning) {
2679 dirty |= WM_DIRTY_DDB;
2680 /* Must disable LP1+ watermarks too */
2681 dirty |= WM_DIRTY_LP_ALL;
2682 }
2683
2684 /* LP1+ watermarks already deemed dirty, no need to continue */
2685 if (dirty & WM_DIRTY_LP_ALL)
2686 return dirty;
2687
2688 /* Find the lowest numbered LP1+ watermark in need of an update... */
2689 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692 break;
2693 }
2694
2695 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696 for (; wm_lp <= 3; wm_lp++)
2697 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699 return dirty;
2700}
2701
8553c18e
VS		 2702static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703 unsigned int dirty)
801bcfff 2704{
820c1980 2705 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2706 bool changed = false;
801bcfff 2707
facd619b
VS		 2708 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2711 changed = true;
facd619b
VS		 2712 }
2713 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2716 changed = true;
facd619b
VS		 2717 }
2718 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2721 changed = true;
facd619b 2722 }
801bcfff 2723
facd619b
VS		 2724 /*
2725 * Don't touch WM1S_LP_EN here.
2726 * Doing so could cause underruns.
2727 */
6cef2b8a 2728
8553c18e
VS		 2729 return changed;
2730}
2731
2732/*
2733 * The spec says we shouldn't write when we don't need, because every write
2734 * causes WMs to be re-evaluated, expending some power.
2735 */
820c1980
ID		 2736static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737 struct ilk_wm_values *results)
8553c18e
VS		 2738{
2739 struct drm_device *dev = dev_priv->dev;
820c1980 2740 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2741 unsigned int dirty;
2742 uint32_t val;
2743
055e393f 2744 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2745 if (!dirty)
2746 return;
2747
2748 _ilk_disable_lp_wm(dev_priv, dirty);
2749
49a687c4 2750 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2751 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2752 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2753 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2754 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2755 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
49a687c4 2757 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2758 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2759 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2761 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
49a687c4 2764 if (dirty & WM_DIRTY_DDB) {
a42a5719 2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2766 val = I915_READ(WM_MISC);
2767 if (results->partitioning == INTEL_DDB_PART_1_2)
2768 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769 else
2770 val |= WM_MISC_DATA_PARTITION_5_6;
2771 I915_WRITE(WM_MISC, val);
2772 } else {
2773 val = I915_READ(DISP_ARB_CTL2);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~DISP_DATA_PARTITION_5_6;
2776 else
2777 val |= DISP_DATA_PARTITION_5_6;
2778 I915_WRITE(DISP_ARB_CTL2, val);
2779 }
1011d8c4
PZ		 2780 }
2781
49a687c4 2782 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2783 val = I915_READ(DISP_ARB_CTL);
2784 if (results->enable_fbc_wm)
2785 val &= ~DISP_FBC_WM_DIS;
2786 else
2787 val |= DISP_FBC_WM_DIS;
2788 I915_WRITE(DISP_ARB_CTL, val);
2789 }
2790
954911eb
ID		 2791 if (dirty & WM_DIRTY_LP(1) &&
2792 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2796 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800 }
801bcfff 2801
facd619b 2802 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2803 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2804 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2805 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2806 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2807 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2808
2809 dev_priv->wm.hw = *results;
801bcfff
PZ		 2810}
2811
ed4a6a7c 2812bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2813{
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817}
2818
b9cec075
DL		 2819/*
2820 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821 * different active planes.
2822 */
2823
2824#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2825#define BXT_DDB_SIZE 512
b9cec075 2826
024c9045
MR		 2827/*
2828 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2829 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830 * other universal planes are in indices 1..n. Note that this may leave unused
2831 * indices between the top "sprite" plane and the cursor.
2832 */
2833static int
2834skl_wm_plane_id(const struct intel_plane *plane)
2835{
2836 switch (plane->base.type) {
2837 case DRM_PLANE_TYPE_PRIMARY:
2838 return 0;
2839 case DRM_PLANE_TYPE_CURSOR:
2840 return PLANE_CURSOR;
2841 case DRM_PLANE_TYPE_OVERLAY:
2842 return plane->plane + 1;
2843 default:
2844 MISSING_CASE(plane->base.type);
2845 return plane->plane;
2846 }
2847}
2848
b9cec075
DL		 2849static void
2850skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2851 const struct intel_crtc_state *cstate,
c107acfe
MR		 2852 struct skl_ddb_entry *alloc, /* out */
2853 int *num_active /* out */)
b9cec075 2854{
c107acfe
MR		 2855 struct drm_atomic_state *state = cstate->base.state;
2856 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2857 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 2858 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2859 unsigned int pipe_size, ddb_size;
2860 int nth_active_pipe;
c107acfe
MR		 2861 int pipe = to_intel_crtc(for_crtc)->pipe;
2862
a6d3460e 2863 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 2864 alloc->start = 0;
2865 alloc->end = 0;
a6d3460e 2866 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 2867 return;
2868 }
2869
a6d3460e
MR		 2870 if (intel_state->active_pipe_changes)
2871 *num_active = hweight32(intel_state->active_crtcs);
2872 else
2873 *num_active = hweight32(dev_priv->active_crtcs);
2874
43d735a6
DL		 2875 if (IS_BROXTON(dev))
2876 ddb_size = BXT_DDB_SIZE;
2877 else
2878 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2879
2880 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2881
c107acfe 2882 /*
a6d3460e
MR		 2883 * If the state doesn't change the active CRTC's, then there's
2884 * no need to recalculate; the existing pipe allocation limits
2885 * should remain unchanged. Note that we're safe from racing
2886 * commits since any racing commit that changes the active CRTC
2887 * list would need to grab _all_ crtc locks, including the one
2888 * we currently hold.
c107acfe 2889 */
a6d3460e
MR		 2890 if (!intel_state->active_pipe_changes) {
2891 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2892 return;
c107acfe 2893 }
a6d3460e
MR		 2894
2895 nth_active_pipe = hweight32(intel_state->active_crtcs &
2896 (drm_crtc_mask(for_crtc) - 1));
2897 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2898 alloc->start = nth_active_pipe * ddb_size / *num_active;
2899 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2900}
2901
c107acfe 2902static unsigned int skl_cursor_allocation(int num_active)
b9cec075 2903{
c107acfe 2904 if (num_active == 1)
b9cec075
DL		 2905 return 32;
2906
2907 return 8;
2908}
2909
a269c583
DL		 2910static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2911{
2912 entry->start = reg & 0x3ff;
2913 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2914 if (entry->end)
2915 entry->end += 1;
a269c583
DL		 2916}
2917
08db6652
DL		 2918void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2919 struct skl_ddb_allocation *ddb /* out */)
a269c583 2920{
a269c583
DL		 2921 enum pipe pipe;
2922 int plane;
2923 u32 val;
2924
b10f1b20
ML		 2925 memset(ddb, 0, sizeof(*ddb));
2926
a269c583 2927 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2928 enum intel_display_power_domain power_domain;
2929
2930 power_domain = POWER_DOMAIN_PIPE(pipe);
2931 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2932 continue;
2933
dd740780 2934 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2935 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2936 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2937 val);
2938 }
2939
2940 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2941 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2942 val);
4d800030
ID		 2943
2944 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2945 }
2946}
2947
b9cec075 2948static unsigned int
024c9045
MR		 2949skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2950 const struct drm_plane_state *pstate,
2951 int y)
b9cec075 2952{
a280f7dd 2953 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 2954 struct drm_framebuffer *fb = pstate->fb;
a280f7dd 2955 uint32_t width = 0, height = 0;
a1de91e5
MR		 2956 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
2957
2958 if (!intel_pstate->visible)
2959 return 0;
2960 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
2961 return 0;
2962 if (y && format != DRM_FORMAT_NV12)
2963 return 0;
a280f7dd
KM		 2964
2965 width = drm_rect_width(&intel_pstate->src) >> 16;
2966 height = drm_rect_height(&intel_pstate->src) >> 16;
2967
2968 if (intel_rotation_90_or_270(pstate->rotation))
2969 swap(width, height);
2cd601c6
CK		 2970
2971 /* for planar format */
a1de91e5 2972 if (format == DRM_FORMAT_NV12) {
2cd601c6 2973 if (y) /* y-plane data rate */
a280f7dd 2974 return width * height *
a1de91e5 2975 drm_format_plane_cpp(format, 0);
2cd601c6 2976 else /* uv-plane data rate */
a280f7dd 2977 return (width / 2) * (height / 2) *
a1de91e5 2978 drm_format_plane_cpp(format, 1);
2cd601c6
CK		 2979 }
2980
2981 /* for packed formats */
a1de91e5 2982 return width * height * drm_format_plane_cpp(format, 0);
b9cec075
DL		 2983}
2984
2985/*
2986 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2987 * a 8192x4096@32bpp framebuffer:
2988 * 3 * 4096 * 8192 * 4 < 2^32
2989 */
2990static unsigned int
9c74d826 2991skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 2992{
9c74d826
MR		 2993 struct drm_crtc_state *cstate = &intel_cstate->base;
2994 struct drm_atomic_state *state = cstate->state;
2995 struct drm_crtc *crtc = cstate->crtc;
2996 struct drm_device *dev = crtc->dev;
2997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 2998 const struct drm_plane *plane;
024c9045 2999 const struct intel_plane *intel_plane;
a6d3460e 3000 struct drm_plane_state *pstate;
a1de91e5 3001 unsigned int rate, total_data_rate = 0;
9c74d826 3002 int id;
a6d3460e
MR		 3003 int i;
3004
3005 if (WARN_ON(!state))
3006 return 0;
b9cec075 3007
a1de91e5 3008 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3009 for_each_plane_in_state(state, plane, pstate, i) {
3010 id = skl_wm_plane_id(to_intel_plane(plane));
3011 intel_plane = to_intel_plane(plane);
3012
3013 if (intel_plane->pipe != intel_crtc->pipe)
3014 continue;
3015
3016 /* packed/uv */
3017 rate = skl_plane_relative_data_rate(intel_cstate,
3018 pstate, 0);
3019 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3020
3021 /* y-plane */
3022 rate = skl_plane_relative_data_rate(intel_cstate,
3023 pstate, 1);
3024 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3025 }
024c9045 3026
a1de91e5
MR		 3027 /* Calculate CRTC's total data rate from cached values */
3028 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3029 int id = skl_wm_plane_id(intel_plane);
024c9045 3030
a1de91e5 3031 /* packed/uv */
9c74d826
MR		 3032 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3033 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3034 }
3035
9c74d826
MR		 3036 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3037
b9cec075
DL		 3038 return total_data_rate;
3039}
3040
c107acfe 3041static int
024c9045 3042skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3043 struct skl_ddb_allocation *ddb /* out */)
3044{
c107acfe 3045 struct drm_atomic_state *state = cstate->base.state;
024c9045 3046 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3047 struct drm_device *dev = crtc->dev;
3048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3049 struct intel_plane *intel_plane;
c107acfe
MR		 3050 struct drm_plane *plane;
3051 struct drm_plane_state *pstate;
b9cec075 3052 enum pipe pipe = intel_crtc->pipe;
34bb56af 3053 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3054 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3055 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3056 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3057 unsigned int total_data_rate;
c107acfe
MR		 3058 int num_active;
3059 int id, i;
b9cec075 3060
a6d3460e
MR		 3061 if (WARN_ON(!state))
3062 return 0;
3063
c107acfe
MR		 3064 if (!cstate->base.active) {
3065 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3066 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3067 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3068 return 0;
3069 }
3070
a6d3460e 3071 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3072 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3073 if (alloc_size == 0) {
3074 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3075 return 0;
b9cec075
DL		 3076 }
3077
c107acfe 3078 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3079 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3080 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3081
3082 alloc_size -= cursor_blocks;
b9cec075 3083
80958155 3084 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3085 for_each_plane_in_state(state, plane, pstate, i) {
3086 intel_plane = to_intel_plane(plane);
3087 id = skl_wm_plane_id(intel_plane);
c107acfe 3088
a6d3460e
MR		 3089 if (intel_plane->pipe != pipe)
3090 continue;
c107acfe 3091
a6d3460e
MR		 3092 if (!to_intel_plane_state(pstate)->visible) {
3093 minimum[id] = 0;
3094 y_minimum[id] = 0;
3095 continue;
3096 }
3097 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3098 minimum[id] = 0;
3099 y_minimum[id] = 0;
3100 continue;
c107acfe 3101 }
a6d3460e
MR		 3102
3103 minimum[id] = 8;
3104 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
3105 y_minimum[id] = 8;
3106 else
3107 y_minimum[id] = 0;
c107acfe 3108 }
80958155 3109
c107acfe
MR		 3110 for (i = 0; i < PLANE_CURSOR; i++) {
3111 alloc_size -= minimum[i];
3112 alloc_size -= y_minimum[i];
80958155
DL		 3113 }
3114
b9cec075 3115 /*
80958155
DL		 3116 * 2. Distribute the remaining space in proportion to the amount of
3117 * data each plane needs to fetch from memory.
b9cec075
DL		 3118 *
3119 * FIXME: we may not allocate every single block here.
3120 */
024c9045 3121 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3122 if (total_data_rate == 0)
c107acfe 3123 return 0;
b9cec075 3124
34bb56af 3125 start = alloc->start;
024c9045 3126 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3127 unsigned int data_rate, y_data_rate;
3128 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3129 int id = skl_wm_plane_id(intel_plane);
b9cec075 3130
a1de91e5 3131 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3132
3133 /*
2cd601c6 3134 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3135 * promote the expression to 64 bits to avoid overflowing, the
3136 * result is < available as data_rate / total_data_rate < 1
3137 */
024c9045 3138 plane_blocks = minimum[id];
80958155
DL		 3139 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3140 total_data_rate);
b9cec075 3141
c107acfe
MR		 3142 /* Leave disabled planes at (0,0) */
3143 if (data_rate) {
3144 ddb->plane[pipe][id].start = start;
3145 ddb->plane[pipe][id].end = start + plane_blocks;
3146 }
b9cec075
DL		 3147
3148 start += plane_blocks;
2cd601c6
CK		 3149
3150 /*
3151 * allocation for y_plane part of planar format:
3152 */
a1de91e5
MR		 3153 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3154
3155 y_plane_blocks = y_minimum[id];
3156 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3157 total_data_rate);
2cd601c6 3158
c107acfe
MR		 3159 if (y_data_rate) {
3160 ddb->y_plane[pipe][id].start = start;
3161 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3162 }
a1de91e5
MR		 3163
3164 start += y_plane_blocks;
b9cec075
DL		 3165 }
3166
c107acfe 3167 return 0;
b9cec075
DL		 3168}
3169
5cec258b 3170static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3171{
3172 /* TODO: Take into account the scalers once we support them */
2d112de7 3173 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3174}
3175
3176/*
3177 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3178 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3179 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3180 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3181*/
ac484963 3182static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3183{
3184 uint32_t wm_intermediate_val, ret;
3185
3186 if (latency == 0)
3187 return UINT_MAX;
3188
ac484963 3189 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3190 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3191
3192 return ret;
3193}
3194
3195static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3196 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3197 uint64_t tiling, uint32_t latency)
2d41c0b5 3198{
d4c2aa60
TU		 3199 uint32_t ret;
3200 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3201 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3202
3203 if (latency == 0)
3204 return UINT_MAX;
3205
ac484963 3206 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3207
3208 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3209 tiling == I915_FORMAT_MOD_Yf_TILED) {
3210 plane_bytes_per_line *= 4;
3211 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3212 plane_blocks_per_line /= 4;
3213 } else {
3214 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3215 }
3216
2d41c0b5
PB		 3217 wm_intermediate_val = latency * pixel_rate;
3218 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3219 plane_blocks_per_line;
2d41c0b5
PB		 3220
3221 return ret;
3222}
3223
2d41c0b5
PB		 3224static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3225 const struct intel_crtc *intel_crtc)
3226{
3227 struct drm_device *dev = intel_crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3230
e6d90023
KM		 3231 /*
3232 * If ddb allocation of pipes changed, it may require recalculation of
3233 * watermarks
3234 */
3235 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3236 return true;
3237
3238 return false;
3239}
3240
d4c2aa60 3241static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3242 struct intel_crtc_state *cstate,
3243 struct intel_plane *intel_plane,
afb024aa 3244 uint16_t ddb_allocation,
d4c2aa60 3245 int level,
afb024aa
DL		 3246 uint16_t *out_blocks, /* out */
3247 uint8_t *out_lines /* out */)
2d41c0b5 3248{
024c9045
MR		 3249 struct drm_plane *plane = &intel_plane->base;
3250 struct drm_framebuffer *fb = plane->state->fb;
a280f7dd
KM		 3251 struct intel_plane_state *intel_pstate =
3252 to_intel_plane_state(plane->state);
d4c2aa60
TU		 3253 uint32_t latency = dev_priv->wm.skl_latency[level];
3254 uint32_t method1, method2;
3255 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3256 uint32_t res_blocks, res_lines;
3257 uint32_t selected_result;
ac484963 3258 uint8_t cpp;
a280f7dd 3259 uint32_t width = 0, height = 0;
2d41c0b5 3260
a280f7dd 3261 if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
2d41c0b5
PB		 3262 return false;
3263
a280f7dd
KM		 3264 width = drm_rect_width(&intel_pstate->src) >> 16;
3265 height = drm_rect_height(&intel_pstate->src) >> 16;
3266
3267 if (intel_rotation_90_or_270(plane->state->rotation))
3268 swap(width, height);
3269
ac484963 3270 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3271 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3272 cpp, latency);
024c9045
MR		 3273 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3274 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3275 width,
3276 cpp,
3277 fb->modifier[0],
d4c2aa60 3278 latency);
2d41c0b5 3279
a280f7dd 3280 plane_bytes_per_line = width * cpp;
d4c2aa60 3281 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3282
024c9045
MR		 3283 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3284 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3285 uint32_t min_scanlines = 4;
3286 uint32_t y_tile_minimum;
024c9045 3287 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3288 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3289 drm_format_plane_cpp(fb->pixel_format, 1) :
3290 drm_format_plane_cpp(fb->pixel_format, 0);
3291
ac484963 3292 switch (cpp) {
1fc0a8f7
TU		 3293 case 1:
3294 min_scanlines = 16;
3295 break;
3296 case 2:
3297 min_scanlines = 8;
3298 break;
3299 case 8:
3300 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3301 }
1fc0a8f7
TU		 3302 }
3303 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3304 selected_result = max(method2, y_tile_minimum);
3305 } else {
3306 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3307 selected_result = min(method1, method2);
3308 else
3309 selected_result = method1;
3310 }
2d41c0b5 3311
d4c2aa60
TU		 3312 res_blocks = selected_result + 1;
3313 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3314
0fda6568 3315 if (level >= 1 && level <= 7) {
024c9045
MR		 3316 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3317 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3318 res_lines += 4;
3319 else
3320 res_blocks++;
3321 }
e6d66171 3322
d4c2aa60 3323 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3324 return false;
3325
3326 *out_blocks = res_blocks;
3327 *out_lines = res_lines;
2d41c0b5
PB		 3328
3329 return true;
3330}
3331
3332static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3333 struct skl_ddb_allocation *ddb,
024c9045 3334 struct intel_crtc_state *cstate,
2d41c0b5 3335 int level,
2d41c0b5
PB		 3336 struct skl_wm_level *result)
3337{
024c9045
MR		 3338 struct drm_device *dev = dev_priv->dev;
3339 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3340 struct intel_plane *intel_plane;
2d41c0b5 3341 uint16_t ddb_blocks;
024c9045
MR		 3342 enum pipe pipe = intel_crtc->pipe;
3343
3344 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3345 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3346
2d41c0b5
PB		 3347 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3348
d4c2aa60 3349 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3350 cstate,
3351 intel_plane,
2d41c0b5 3352 ddb_blocks,
d4c2aa60 3353 level,
2d41c0b5
PB		 3354 &result->plane_res_b[i],
3355 &result->plane_res_l[i]);
3356 }
2d41c0b5
PB		 3357}
3358
407b50f3 3359static uint32_t
024c9045 3360skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3361{
024c9045 3362 if (!cstate->base.active)
407b50f3
DL		 3363 return 0;
3364
024c9045 3365 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3366 return 0;
407b50f3 3367
024c9045
MR		 3368 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3369 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3370}
3371
024c9045 3372static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3373 struct skl_wm_level *trans_wm /* out */)
407b50f3 3374{
024c9045 3375 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3377 struct intel_plane *intel_plane;
9414f563 3378
024c9045 3379 if (!cstate->base.active)
407b50f3 3380 return;
9414f563
DL		 3381
3382 /* Until we know more, just disable transition WMs */
024c9045
MR		 3383 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3384 int i = skl_wm_plane_id(intel_plane);
3385
9414f563 3386 trans_wm->plane_en[i] = false;
024c9045 3387 }
407b50f3
DL		 3388}
3389
e7649b54
MR		 3390static void skl_build_pipe_wm(struct intel_crtc_state *cstate,
3391 struct skl_ddb_allocation *ddb,
3392 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3393{
024c9045 3394 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3395 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3396 int level, max_level = ilk_wm_max_level(dev);
3397
3398 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3399 skl_compute_wm_level(dev_priv, ddb, cstate,
3400 level, &pipe_wm->wm[level]);
2d41c0b5 3401 }
024c9045 3402 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3403
024c9045 3404 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3405}
3406
3407static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3408 struct skl_pipe_wm *p_wm,
3409 struct skl_wm_values *r,
3410 struct intel_crtc *intel_crtc)
3411{
3412 int level, max_level = ilk_wm_max_level(dev);
3413 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3414 uint32_t temp;
3415 int i;
2d41c0b5
PB		 3416
3417 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3418 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3419 temp = 0;
2d41c0b5
PB		 3420
3421 temp |= p_wm->wm[level].plane_res_l[i] <<
3422 PLANE_WM_LINES_SHIFT;
3423 temp |= p_wm->wm[level].plane_res_b[i];
3424 if (p_wm->wm[level].plane_en[i])
3425 temp |= PLANE_WM_EN;
3426
3427 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3428 }
3429
3430 temp = 0;
2d41c0b5 3431
4969d33e
MR		 3432 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3433 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3434
4969d33e 3435 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3436 temp |= PLANE_WM_EN;
3437
4969d33e 3438 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3439
3440 }
3441
9414f563
DL		 3442 /* transition WMs */
3443 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3444 temp = 0;
3445 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3446 temp |= p_wm->trans_wm.plane_res_b[i];
3447 if (p_wm->trans_wm.plane_en[i])
3448 temp |= PLANE_WM_EN;
3449
3450 r->plane_trans[pipe][i] = temp;
3451 }
3452
3453 temp = 0;
4969d33e
MR		 3454 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3455 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3456 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3457 temp |= PLANE_WM_EN;
3458
4969d33e 3459 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3460
2d41c0b5
PB		 3461 r->wm_linetime[pipe] = p_wm->linetime;
3462}
3463
f0f59a00
VS		 3464static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3465 i915_reg_t reg,
16160e3d
DL		 3466 const struct skl_ddb_entry *entry)
3467{
3468 if (entry->end)
3469 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3470 else
3471 I915_WRITE(reg, 0);
3472}
3473
2d41c0b5
PB		 3474static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3475 const struct skl_wm_values *new)
3476{
3477 struct drm_device *dev = dev_priv->dev;
3478 struct intel_crtc *crtc;
3479
19c8054c 3480 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3481 int i, level, max_level = ilk_wm_max_level(dev);
3482 enum pipe pipe = crtc->pipe;
3483
5d374d96
DL		 3484 if (!new->dirty[pipe])
3485 continue;
8211bd5b 3486
5d374d96 3487 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3488
5d374d96
DL		 3489 for (level = 0; level <= max_level; level++) {
3490 for (i = 0; i < intel_num_planes(crtc); i++)
3491 I915_WRITE(PLANE_WM(pipe, i, level),
3492 new->plane[pipe][i][level]);
3493 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3494 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3495 }
5d374d96
DL		 3496 for (i = 0; i < intel_num_planes(crtc); i++)
3497 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3498 new->plane_trans[pipe][i]);
4969d33e
MR		 3499 I915_WRITE(CUR_WM_TRANS(pipe),
3500 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3501
2cd601c6 3502 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3503 skl_ddb_entry_write(dev_priv,
3504 PLANE_BUF_CFG(pipe, i),
3505 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3506 skl_ddb_entry_write(dev_priv,
3507 PLANE_NV12_BUF_CFG(pipe, i),
3508 &new->ddb.y_plane[pipe][i]);
3509 }
5d374d96
DL		 3510
3511 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3512 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3513 }
2d41c0b5
PB		 3514}
3515
0e8fb7ba
DL		 3516/*
3517 * When setting up a new DDB allocation arrangement, we need to correctly
3518 * sequence the times at which the new allocations for the pipes are taken into
3519 * account or we'll have pipes fetching from space previously allocated to
3520 * another pipe.
3521 *
3522 * Roughly the sequence looks like:
3523 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3524 * overlapping with a previous light-up pipe (another way to put it is:
3525 * pipes with their new allocation strickly included into their old ones).
3526 * 2. re-allocate the other pipes that get their allocation reduced
3527 * 3. allocate the pipes having their allocation increased
3528 *
3529 * Steps 1. and 2. are here to take care of the following case:
3530 * - Initially DDB looks like this:
3531 * | B | C |
3532 * - enable pipe A.
3533 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3534 * allocation
3535 * | A | B | C |
3536 *
3537 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3538 */
3539
d21b795c
DL		 3540static void
3541skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3542{
0e8fb7ba
DL		 3543 int plane;
3544
d21b795c
DL		 3545 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3546
dd740780 3547 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3548 I915_WRITE(PLANE_SURF(pipe, plane),
3549 I915_READ(PLANE_SURF(pipe, plane)));
3550 }
3551 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3552}
3553
3554static bool
3555skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3556 const struct skl_ddb_allocation *new,
3557 enum pipe pipe)
3558{
3559 uint16_t old_size, new_size;
3560
3561 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3562 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3563
3564 return old_size != new_size &&
3565 new->pipe[pipe].start >= old->pipe[pipe].start &&
3566 new->pipe[pipe].end <= old->pipe[pipe].end;
3567}
3568
3569static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3570 struct skl_wm_values *new_values)
3571{
3572 struct drm_device *dev = dev_priv->dev;
3573 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3574 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3575 struct intel_crtc *crtc;
3576 enum pipe pipe;
3577
3578 new_ddb = &new_values->ddb;
3579 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3580
3581 /*
3582 * First pass: flush the pipes with the new allocation contained into
3583 * the old space.
3584 *
3585 * We'll wait for the vblank on those pipes to ensure we can safely
3586 * re-allocate the freed space without this pipe fetching from it.
3587 */
3588 for_each_intel_crtc(dev, crtc) {
3589 if (!crtc->active)
3590 continue;
3591
3592 pipe = crtc->pipe;
3593
3594 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3595 continue;
3596
d21b795c 3597 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3598 intel_wait_for_vblank(dev, pipe);
3599
3600 reallocated[pipe] = true;
3601 }
3602
3603
3604 /*
3605 * Second pass: flush the pipes that are having their allocation
3606 * reduced, but overlapping with a previous allocation.
3607 *
3608 * Here as well we need to wait for the vblank to make sure the freed
3609 * space is not used anymore.
3610 */
3611 for_each_intel_crtc(dev, crtc) {
3612 if (!crtc->active)
3613 continue;
3614
3615 pipe = crtc->pipe;
3616
3617 if (reallocated[pipe])
3618 continue;
3619
3620 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3621 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3622 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3623 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3624 reallocated[pipe] = true;
0e8fb7ba 3625 }
0e8fb7ba
DL		 3626 }
3627
3628 /*
3629 * Third pass: flush the pipes that got more space allocated.
3630 *
3631 * We don't need to actively wait for the update here, next vblank
3632 * will just get more DDB space with the correct WM values.
3633 */
3634 for_each_intel_crtc(dev, crtc) {
3635 if (!crtc->active)
3636 continue;
3637
3638 pipe = crtc->pipe;
3639
3640 /*
3641 * At this point, only the pipes more space than before are
3642 * left to re-allocate.
3643 */
3644 if (reallocated[pipe])
3645 continue;
3646
d21b795c 3647 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3648 }
3649}
3650
2d41c0b5 3651static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3652 struct skl_ddb_allocation *ddb, /* out */
3653 struct skl_pipe_wm *pipe_wm /* out */)
3654{
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3656 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3657
e7649b54 3658 skl_build_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3659
4e0963c7 3660 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3661 return false;
3662
4e0963c7 3663 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3664
2d41c0b5
PB		 3665 return true;
3666}
3667
3668static void skl_update_other_pipe_wm(struct drm_device *dev,
3669 struct drm_crtc *crtc,
2d41c0b5
PB		 3670 struct skl_wm_values *r)
3671{
3672 struct intel_crtc *intel_crtc;
3673 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3674
3675 /*
3676 * If the WM update hasn't changed the allocation for this_crtc (the
3677 * crtc we are currently computing the new WM values for), other
3678 * enabled crtcs will keep the same allocation and we don't need to
3679 * recompute anything for them.
3680 */
3681 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3682 return;
3683
3684 /*
3685 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3686 * other active pipes need new DDB allocation and WM values.
3687 */
19c8054c 3688 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3689 struct skl_pipe_wm pipe_wm = {};
3690 bool wm_changed;
3691
3692 if (this_crtc->pipe == intel_crtc->pipe)
3693 continue;
3694
3695 if (!intel_crtc->active)
3696 continue;
3697
aa363136 3698 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3699 &r->ddb, &pipe_wm);
3700
3701 /*
3702 * If we end up re-computing the other pipe WM values, it's
3703 * because it was really needed, so we expect the WM values to
3704 * be different.
3705 */
3706 WARN_ON(!wm_changed);
3707
024c9045 3708 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3709 r->dirty[intel_crtc->pipe] = true;
3710 }
3711}
3712
adda50b8
BP		 3713static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3714{
3715 watermarks->wm_linetime[pipe] = 0;
3716 memset(watermarks->plane[pipe], 0,
3717 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3718 memset(watermarks->plane_trans[pipe],
3719 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3720 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3721}
3722
98d39494
MR		 3723static int
3724skl_compute_ddb(struct drm_atomic_state *state)
3725{
3726 struct drm_device *dev = state->dev;
3727 struct drm_i915_private *dev_priv = to_i915(dev);
3728 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3729 struct intel_crtc *intel_crtc;
3730 unsigned realloc_pipes = dev_priv->active_crtcs;
3731 int ret;
3732
3733 /*
3734 * If this is our first atomic update following hardware readout,
3735 * we can't trust the DDB that the BIOS programmed for us. Let's
3736 * pretend that all pipes switched active status so that we'll
3737 * ensure a full DDB recompute.
3738 */
3739 if (dev_priv->wm.distrust_bios_wm)
3740 intel_state->active_pipe_changes = ~0;
3741
3742 /*
3743 * If the modeset changes which CRTC's are active, we need to
3744 * recompute the DDB allocation for *all* active pipes, even
3745 * those that weren't otherwise being modified in any way by this
3746 * atomic commit. Due to the shrinking of the per-pipe allocations
3747 * when new active CRTC's are added, it's possible for a pipe that
3748 * we were already using and aren't changing at all here to suddenly
3749 * become invalid if its DDB needs exceeds its new allocation.
3750 *
3751 * Note that if we wind up doing a full DDB recompute, we can't let
3752 * any other display updates race with this transaction, so we need
3753 * to grab the lock on *all* CRTC's.
3754 */
3755 if (intel_state->active_pipe_changes)
3756 realloc_pipes = ~0;
3757
3758 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3759 struct intel_crtc_state *cstate;
3760
3761 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3762 if (IS_ERR(cstate))
3763 return PTR_ERR(cstate);
3764
3765 ret = skl_allocate_pipe_ddb(cstate, &intel_state->ddb);
3766 if (ret)
3767 return ret;
3768 }
3769
3770 return 0;
3771}
3772
3773static int
3774skl_compute_wm(struct drm_atomic_state *state)
3775{
3776 struct drm_crtc *crtc;
3777 struct drm_crtc_state *cstate;
3778 int ret, i;
3779 bool changed = false;
3780
3781 /*
3782 * If this transaction isn't actually touching any CRTC's, don't
3783 * bother with watermark calculation. Note that if we pass this
3784 * test, we're guaranteed to hold at least one CRTC state mutex,
3785 * which means we can safely use values like dev_priv->active_crtcs
3786 * since any racing commits that want to update them would need to
3787 * hold _all_ CRTC state mutexes.
3788 */
3789 for_each_crtc_in_state(state, crtc, cstate, i)
3790 changed = true;
3791 if (!changed)
3792 return 0;
3793
3794 ret = skl_compute_ddb(state);
3795 if (ret)
3796 return ret;
3797
3798 return 0;
3799}
3800
2d41c0b5
PB		 3801static void skl_update_wm(struct drm_crtc *crtc)
3802{
3803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3806 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7 3807 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 3808 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
2d41c0b5 3809
adda50b8
BP		 3810
3811 /* Clear all dirty flags */
3812 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3813
3814 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3815
aa363136 3816 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3817 return;
3818
4e0963c7 3819 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3820 results->dirty[intel_crtc->pipe] = true;
3821
aa363136 3822 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3823 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3824 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3825
3826 /* store the new configuration */
3827 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3828}
3829
d890565c
VS		 3830static void ilk_compute_wm_config(struct drm_device *dev,
3831 struct intel_wm_config *config)
3832{
3833 struct intel_crtc *crtc;
3834
3835 /* Compute the currently _active_ config */
3836 for_each_intel_crtc(dev, crtc) {
3837 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3838
3839 if (!wm->pipe_enabled)
3840 continue;
3841
3842 config->sprites_enabled |= wm->sprites_enabled;
3843 config->sprites_scaled |= wm->sprites_scaled;
3844 config->num_pipes_active++;
3845 }
3846}
3847
ed4a6a7c 3848static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3849{
ed4a6a7c 3850 struct drm_device *dev = dev_priv->dev;
b9d5c839 3851 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3852 struct ilk_wm_maximums max;
d890565c 3853 struct intel_wm_config config = {};
820c1980 3854 struct ilk_wm_values results = {};
77c122bc 3855 enum intel_ddb_partitioning partitioning;
261a27d1 3856
d890565c
VS		 3857 ilk_compute_wm_config(dev, &config);
3858
3859 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3860 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3861
3862 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3863 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3864 config.num_pipes_active == 1 && config.sprites_enabled) {
3865 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3866 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3867
820c1980 3868 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3869 } else {
198a1e9b 3870 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3871 }
3872
198a1e9b 3873 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3874 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3875
820c1980 3876 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3877
820c1980 3878 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3879}
3880
ed4a6a7c 3881static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 3882{
ed4a6a7c
MR		 3883 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3884 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3885
ed4a6a7c 3886 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 3887 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 3888 ilk_program_watermarks(dev_priv);
3889 mutex_unlock(&dev_priv->wm.wm_mutex);
3890}
bf220452 3891
ed4a6a7c
MR		 3892static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3893{
3894 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3895 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 3896
ed4a6a7c
MR		 3897 mutex_lock(&dev_priv->wm.wm_mutex);
3898 if (cstate->wm.need_postvbl_update) {
e8f1f02e 3899 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 3900 ilk_program_watermarks(dev_priv);
3901 }
3902 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 3903}
3904
3078999f
PB		 3905static void skl_pipe_wm_active_state(uint32_t val,
3906 struct skl_pipe_wm *active,
3907 bool is_transwm,
3908 bool is_cursor,
3909 int i,
3910 int level)
3911{
3912 bool is_enabled = (val & PLANE_WM_EN) != 0;
3913
3914 if (!is_transwm) {
3915 if (!is_cursor) {
3916 active->wm[level].plane_en[i] = is_enabled;
3917 active->wm[level].plane_res_b[i] =
3918 val & PLANE_WM_BLOCKS_MASK;
3919 active->wm[level].plane_res_l[i] =
3920 (val >> PLANE_WM_LINES_SHIFT) &
3921 PLANE_WM_LINES_MASK;
3922 } else {
4969d33e
MR		 3923 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3924 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3925 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3926 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3927 (val >> PLANE_WM_LINES_SHIFT) &
3928 PLANE_WM_LINES_MASK;
3929 }
3930 } else {
3931 if (!is_cursor) {
3932 active->trans_wm.plane_en[i] = is_enabled;
3933 active->trans_wm.plane_res_b[i] =
3934 val & PLANE_WM_BLOCKS_MASK;
3935 active->trans_wm.plane_res_l[i] =
3936 (val >> PLANE_WM_LINES_SHIFT) &
3937 PLANE_WM_LINES_MASK;
3938 } else {
4969d33e
MR		 3939 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3940 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3941 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3942 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3943 (val >> PLANE_WM_LINES_SHIFT) &
3944 PLANE_WM_LINES_MASK;
3945 }
3946 }
3947}
3948
3949static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3950{
3951 struct drm_device *dev = crtc->dev;
3952 struct drm_i915_private *dev_priv = dev->dev_private;
3953 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 3955 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 3956 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 3957 enum pipe pipe = intel_crtc->pipe;
3958 int level, i, max_level;
3959 uint32_t temp;
3960
3961 max_level = ilk_wm_max_level(dev);
3962
3963 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3964
3965 for (level = 0; level <= max_level; level++) {
3966 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3967 hw->plane[pipe][i][level] =
3968 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3969 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3970 }
3971
3972 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3973 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3974 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3975
3ef00284 3976 if (!intel_crtc->active)
3078999f
PB		 3977 return;
3978
3979 hw->dirty[pipe] = true;
3980
3981 active->linetime = hw->wm_linetime[pipe];
3982
3983 for (level = 0; level <= max_level; level++) {
3984 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3985 temp = hw->plane[pipe][i][level];
3986 skl_pipe_wm_active_state(temp, active, false,
3987 false, i, level);
3988 }
4969d33e 3989 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3990 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3991 }
3992
3993 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3994 temp = hw->plane_trans[pipe][i];
3995 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3996 }
3997
4969d33e 3998 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3999 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4000
4001 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4002}
4003
4004void skl_wm_get_hw_state(struct drm_device *dev)
4005{
a269c583
DL		 4006 struct drm_i915_private *dev_priv = dev->dev_private;
4007 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4008 struct drm_crtc *crtc;
a1de91e5 4009 struct intel_crtc *intel_crtc;
3078999f 4010
a269c583 4011 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4012 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4013 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4014
279e99d7
MR		 4015 if (dev_priv->active_crtcs) {
4016 /* Fully recompute DDB on first atomic commit */
4017 dev_priv->wm.distrust_bios_wm = true;
4018 } else {
4019 /* Easy/common case; just sanitize DDB now if everything off */
4020 memset(ddb, 0, sizeof(*ddb));
4021 }
4022
a1de91e5
MR		 4023 /* Calculate plane data rates */
4024 for_each_intel_crtc(dev, intel_crtc) {
4025 struct intel_crtc_state *cstate = intel_crtc->config;
4026 struct intel_plane *intel_plane;
4027
4028 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4029 const struct drm_plane_state *pstate =
4030 intel_plane->base.state;
4031 int id = skl_wm_plane_id(intel_plane);
4032
4033 cstate->wm.skl.plane_data_rate[id] =
4034 skl_plane_relative_data_rate(cstate, pstate, 0);
4035 cstate->wm.skl.plane_y_data_rate[id] =
4036 skl_plane_relative_data_rate(cstate, pstate, 1);
4037 }
4038 }
3078999f
PB		 4039}
4040
243e6a44
VS		 4041static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4042{
4043 struct drm_device *dev = crtc->dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4045 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4047 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4048 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4049 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4050 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4051 [PIPE_A] = WM0_PIPEA_ILK,
4052 [PIPE_B] = WM0_PIPEB_ILK,
4053 [PIPE_C] = WM0_PIPEC_IVB,
4054 };
4055
4056 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4057 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4058 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4059
3ef00284 4060 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4061
4062 if (active->pipe_enabled) {
243e6a44
VS		 4063 u32 tmp = hw->wm_pipe[pipe];
4064
4065 /*
4066 * For active pipes LP0 watermark is marked as
4067 * enabled, and LP1+ watermaks as disabled since
4068 * we can't really reverse compute them in case
4069 * multiple pipes are active.
4070 */
4071 active->wm[0].enable = true;
4072 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4073 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4074 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4075 active->linetime = hw->wm_linetime[pipe];
4076 } else {
4077 int level, max_level = ilk_wm_max_level(dev);
4078
4079 /*
4080 * For inactive pipes, all watermark levels
4081 * should be marked as enabled but zeroed,
4082 * which is what we'd compute them to.
4083 */
4084 for (level = 0; level <= max_level; level++)
4085 active->wm[level].enable = true;
4086 }
4e0963c7
MR		 4087
4088 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4089}
4090
6eb1a681
VS		 4091#define _FW_WM(value, plane) \
4092 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4093#define _FW_WM_VLV(value, plane) \
4094 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4095
4096static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4097 struct vlv_wm_values *wm)
4098{
4099 enum pipe pipe;
4100 uint32_t tmp;
4101
4102 for_each_pipe(dev_priv, pipe) {
4103 tmp = I915_READ(VLV_DDL(pipe));
4104
4105 wm->ddl[pipe].primary =
4106 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4107 wm->ddl[pipe].cursor =
4108 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4109 wm->ddl[pipe].sprite[0] =
4110 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4111 wm->ddl[pipe].sprite[1] =
4112 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4113 }
4114
4115 tmp = I915_READ(DSPFW1);
4116 wm->sr.plane = _FW_WM(tmp, SR);
4117 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4118 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4119 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4120
4121 tmp = I915_READ(DSPFW2);
4122 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4123 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4124 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4125
4126 tmp = I915_READ(DSPFW3);
4127 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4128
4129 if (IS_CHERRYVIEW(dev_priv)) {
4130 tmp = I915_READ(DSPFW7_CHV);
4131 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4132 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4133
4134 tmp = I915_READ(DSPFW8_CHV);
4135 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4136 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4137
4138 tmp = I915_READ(DSPFW9_CHV);
4139 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4140 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4141
4142 tmp = I915_READ(DSPHOWM);
4143 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4144 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4145 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4146 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4147 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4148 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4149 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4150 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4151 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4152 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4153 } else {
4154 tmp = I915_READ(DSPFW7);
4155 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4156 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4157
4158 tmp = I915_READ(DSPHOWM);
4159 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4160 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4161 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4162 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4163 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4164 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4165 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4166 }
4167}
4168
4169#undef _FW_WM
4170#undef _FW_WM_VLV
4171
4172void vlv_wm_get_hw_state(struct drm_device *dev)
4173{
4174 struct drm_i915_private *dev_priv = to_i915(dev);
4175 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4176 struct intel_plane *plane;
4177 enum pipe pipe;
4178 u32 val;
4179
4180 vlv_read_wm_values(dev_priv, wm);
4181
4182 for_each_intel_plane(dev, plane) {
4183 switch (plane->base.type) {
4184 int sprite;
4185 case DRM_PLANE_TYPE_CURSOR:
4186 plane->wm.fifo_size = 63;
4187 break;
4188 case DRM_PLANE_TYPE_PRIMARY:
4189 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4190 break;
4191 case DRM_PLANE_TYPE_OVERLAY:
4192 sprite = plane->plane;
4193 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4194 break;
4195 }
4196 }
4197
4198 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4199 wm->level = VLV_WM_LEVEL_PM2;
4200
4201 if (IS_CHERRYVIEW(dev_priv)) {
4202 mutex_lock(&dev_priv->rps.hw_lock);
4203
4204 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4205 if (val & DSP_MAXFIFO_PM5_ENABLE)
4206 wm->level = VLV_WM_LEVEL_PM5;
4207
58590c14
VS		 4208 /*
4209 * If DDR DVFS is disabled in the BIOS, Punit
4210 * will never ack the request. So if that happens
4211 * assume we don't have to enable/disable DDR DVFS
4212 * dynamically. To test that just set the REQ_ACK
4213 * bit to poke the Punit, but don't change the
4214 * HIGH/LOW bits so that we don't actually change
4215 * the current state.
4216 */
6eb1a681 4217 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4218 val |= FORCE_DDR_FREQ_REQ_ACK;
4219 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4220
4221 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4222 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4223 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4224 "assuming DDR DVFS is disabled\n");
4225 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4226 } else {
4227 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4228 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4229 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4230 }
6eb1a681
VS		 4231
4232 mutex_unlock(&dev_priv->rps.hw_lock);
4233 }
4234
4235 for_each_pipe(dev_priv, pipe)
4236 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4237 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4238 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4239
4240 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4241 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4242}
4243
243e6a44
VS		 4244void ilk_wm_get_hw_state(struct drm_device *dev)
4245{
4246 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4247 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4248 struct drm_crtc *crtc;
4249
70e1e0ec 4250 for_each_crtc(dev, crtc)
243e6a44
VS		 4251 ilk_pipe_wm_get_hw_state(crtc);
4252
4253 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4254 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4255 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4256
4257 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4258 if (INTEL_INFO(dev)->gen >= 7) {
4259 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4260 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4261 }
243e6a44 4262
a42a5719 4263 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4264 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4265 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4266 else if (IS_IVYBRIDGE(dev))
4267 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4268 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4269
4270 hw->enable_fbc_wm =
4271 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4272}
4273
b445e3b0
ED		 4274/**
4275 * intel_update_watermarks - update FIFO watermark values based on current modes
4276 *
4277 * Calculate watermark values for the various WM regs based on current mode
4278 * and plane configuration.
4279 *
4280 * There are several cases to deal with here:
4281 * - normal (i.e. non-self-refresh)
4282 * - self-refresh (SR) mode
4283 * - lines are large relative to FIFO size (buffer can hold up to 2)
4284 * - lines are small relative to FIFO size (buffer can hold more than 2
4285 * lines), so need to account for TLB latency
4286 *
4287 * The normal calculation is:
4288 * watermark = dotclock * bytes per pixel * latency
4289 * where latency is platform & configuration dependent (we assume pessimal
4290 * values here).
4291 *
4292 * The SR calculation is:
4293 * watermark = (trunc(latency/line time)+1) * surface width *
4294 * bytes per pixel
4295 * where
4296 * line time = htotal / dotclock
4297 * surface width = hdisplay for normal plane and 64 for cursor
4298 * and latency is assumed to be high, as above.
4299 *
4300 * The final value programmed to the register should always be rounded up,
4301 * and include an extra 2 entries to account for clock crossings.
4302 *
4303 * We don't use the sprite, so we can ignore that. And on Crestline we have
4304 * to set the non-SR watermarks to 8.
4305 */
46ba614c 4306void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4307{
46ba614c 4308 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4309
4310 if (dev_priv->display.update_wm)
46ba614c 4311 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4312}
4313
e2828914 4314/*
9270388e 4315 * Lock protecting IPS related data structures
9270388e
DV		 4316 */
4317DEFINE_SPINLOCK(mchdev_lock);
4318
4319/* Global for IPS driver to get at the current i915 device. Protected by
4320 * mchdev_lock. */
4321static struct drm_i915_private *i915_mch_dev;
4322
91d14251 4323bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4324{
2b4e57bd
ED		 4325 u16 rgvswctl;
4326
9270388e
DV		 4327 assert_spin_locked(&mchdev_lock);
4328
2b4e57bd
ED		 4329 rgvswctl = I915_READ16(MEMSWCTL);
4330 if (rgvswctl & MEMCTL_CMD_STS) {
4331 DRM_DEBUG("gpu busy, RCS change rejected\n");
4332 return false; /* still busy with another command */
4333 }
4334
4335 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4336 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4337 I915_WRITE16(MEMSWCTL, rgvswctl);
4338 POSTING_READ16(MEMSWCTL);
4339
4340 rgvswctl |= MEMCTL_CMD_STS;
4341 I915_WRITE16(MEMSWCTL, rgvswctl);
4342
4343 return true;
4344}
4345
91d14251 4346static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4347{
84f1b20f 4348 u32 rgvmodectl;
2b4e57bd
ED		 4349 u8 fmax, fmin, fstart, vstart;
4350
9270388e
DV		 4351 spin_lock_irq(&mchdev_lock);
4352
84f1b20f
TU		 4353 rgvmodectl = I915_READ(MEMMODECTL);
4354
2b4e57bd
ED		 4355 /* Enable temp reporting */
4356 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4357 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4358
4359 /* 100ms RC evaluation intervals */
4360 I915_WRITE(RCUPEI, 100000);
4361 I915_WRITE(RCDNEI, 100000);
4362
4363 /* Set max/min thresholds to 90ms and 80ms respectively */
4364 I915_WRITE(RCBMAXAVG, 90000);
4365 I915_WRITE(RCBMINAVG, 80000);
4366
4367 I915_WRITE(MEMIHYST, 1);
4368
4369 /* Set up min, max, and cur for interrupt handling */
4370 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4371 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4372 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4373 MEMMODE_FSTART_SHIFT;
4374
616847e7 4375 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4376 PXVFREQ_PX_SHIFT;
4377
20e4d407
DV		 4378 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4379 dev_priv->ips.fstart = fstart;
2b4e57bd 4380
20e4d407
DV		 4381 dev_priv->ips.max_delay = fstart;
4382 dev_priv->ips.min_delay = fmin;
4383 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4384
4385 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4386 fmax, fmin, fstart);
4387
4388 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4389
4390 /*
4391 * Interrupts will be enabled in ironlake_irq_postinstall
4392 */
4393
4394 I915_WRITE(VIDSTART, vstart);
4395 POSTING_READ(VIDSTART);
4396
4397 rgvmodectl |= MEMMODE_SWMODE_EN;
4398 I915_WRITE(MEMMODECTL, rgvmodectl);
4399
9270388e 4400 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4401 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4402 mdelay(1);
2b4e57bd 4403
91d14251 4404 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4405
7d81c3e0
VS		 4406 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4407 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4408 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4409 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4410 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4411
4412 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4413}
4414
91d14251 4415static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4416{
9270388e
DV		 4417 u16 rgvswctl;
4418
4419 spin_lock_irq(&mchdev_lock);
4420
4421 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4422
4423 /* Ack interrupts, disable EFC interrupt */
4424 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4425 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4426 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4427 I915_WRITE(DEIIR, DE_PCU_EVENT);
4428 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4429
4430 /* Go back to the starting frequency */
91d14251 4431 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4432 mdelay(1);
2b4e57bd
ED		 4433 rgvswctl |= MEMCTL_CMD_STS;
4434 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4435 mdelay(1);
2b4e57bd 4436
9270388e 4437 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4438}
4439
acbe9475
DV		 4440/* There's a funny hw issue where the hw returns all 0 when reading from
4441 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4442 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4443 * all limits and the gpu stuck at whatever frequency it is at atm).
4444 */
74ef1173 4445static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4446{
7b9e0ae6 4447 u32 limits;
2b4e57bd 4448
20b46e59
DV		 4449 /* Only set the down limit when we've reached the lowest level to avoid
4450 * getting more interrupts, otherwise leave this clear. This prevents a
4451 * race in the hw when coming out of rc6: There's a tiny window where
4452 * the hw runs at the minimal clock before selecting the desired
4453 * frequency, if the down threshold expires in that window we will not
4454 * receive a down interrupt. */
2d1fe073 4455 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4456 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4457 if (val <= dev_priv->rps.min_freq_softlimit)
4458 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4459 } else {
4460 limits = dev_priv->rps.max_freq_softlimit << 24;
4461 if (val <= dev_priv->rps.min_freq_softlimit)
4462 limits |= dev_priv->rps.min_freq_softlimit << 16;
4463 }
20b46e59
DV		 4464
4465 return limits;
4466}
4467
dd75fdc8
CW		 4468static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4469{
4470 int new_power;
8a586437
AG		 4471 u32 threshold_up = 0, threshold_down = 0; /* in % */
4472 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4473
4474 new_power = dev_priv->rps.power;
4475 switch (dev_priv->rps.power) {
4476 case LOW_POWER:
b39fb297 4477 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4478 new_power = BETWEEN;
4479 break;
4480
4481 case BETWEEN:
b39fb297 4482 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4483 new_power = LOW_POWER;
b39fb297 4484 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4485 new_power = HIGH_POWER;
4486 break;
4487
4488 case HIGH_POWER:
b39fb297 4489 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4490 new_power = BETWEEN;
4491 break;
4492 }
4493 /* Max/min bins are special */
aed242ff 4494 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4495 new_power = LOW_POWER;
aed242ff 4496 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4497 new_power = HIGH_POWER;
4498 if (new_power == dev_priv->rps.power)
4499 return;
4500
4501 /* Note the units here are not exactly 1us, but 1280ns. */
4502 switch (new_power) {
4503 case LOW_POWER:
4504 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4505 ei_up = 16000;
4506 threshold_up = 95;
dd75fdc8
CW		 4507
4508 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4509 ei_down = 32000;
4510 threshold_down = 85;
dd75fdc8
CW		 4511 break;
4512
4513 case BETWEEN:
4514 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4515 ei_up = 13000;
4516 threshold_up = 90;
dd75fdc8
CW		 4517
4518 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4519 ei_down = 32000;
4520 threshold_down = 75;
dd75fdc8
CW		 4521 break;
4522
4523 case HIGH_POWER:
4524 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4525 ei_up = 10000;
4526 threshold_up = 85;
dd75fdc8
CW		 4527
4528 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4529 ei_down = 32000;
4530 threshold_down = 60;
dd75fdc8
CW		 4531 break;
4532 }
4533
8a586437
AG		 4534 I915_WRITE(GEN6_RP_UP_EI,
4535 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4536 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4537 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4538
4539 I915_WRITE(GEN6_RP_DOWN_EI,
4540 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4541 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4542 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4543
4544 I915_WRITE(GEN6_RP_CONTROL,
4545 GEN6_RP_MEDIA_TURBO |
4546 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4547 GEN6_RP_MEDIA_IS_GFX |
4548 GEN6_RP_ENABLE |
4549 GEN6_RP_UP_BUSY_AVG |
4550 GEN6_RP_DOWN_IDLE_AVG);
4551
dd75fdc8 4552 dev_priv->rps.power = new_power;
8fb55197
CW		 4553 dev_priv->rps.up_threshold = threshold_up;
4554 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4555 dev_priv->rps.last_adj = 0;
4556}
4557
2876ce73
CW		 4558static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4559{
4560 u32 mask = 0;
4561
4562 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4563 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4564 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4565 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4566
7b3c29f6
CW		 4567 mask &= dev_priv->pm_rps_events;
4568
59d02a1f 4569 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4570}
4571
b8a5ff8d
JM		 4572/* gen6_set_rps is called to update the frequency request, but should also be
4573 * called when the range (min_delay and max_delay) is modified so that we can
4574 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4575static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4576{
23eafea6 4577 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4578 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4579 return;
4580
4fc688ce 4581 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4582 WARN_ON(val > dev_priv->rps.max_freq);
4583 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4584
eb64cad1
CW		 4585 /* min/max delay may still have been modified so be sure to
4586 * write the limits value.
4587 */
4588 if (val != dev_priv->rps.cur_freq) {
4589 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4590
dc97997a 4591 if (IS_GEN9(dev_priv))
5704195c
AG		 4592 I915_WRITE(GEN6_RPNSWREQ,
4593 GEN9_FREQUENCY(val));
dc97997a 4594 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4595 I915_WRITE(GEN6_RPNSWREQ,
4596 HSW_FREQUENCY(val));
4597 else
4598 I915_WRITE(GEN6_RPNSWREQ,
4599 GEN6_FREQUENCY(val) |
4600 GEN6_OFFSET(0) |
4601 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4602 }
7b9e0ae6 4603
7b9e0ae6
CW		 4604 /* Make sure we continue to get interrupts
4605 * until we hit the minimum or maximum frequencies.
4606 */
74ef1173 4607 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4608 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4609
d5570a72
BW		 4610 POSTING_READ(GEN6_RPNSWREQ);
4611
b39fb297 4612 dev_priv->rps.cur_freq = val;
0f94592e 4613 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4614}
4615
dc97997a 4616static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4617{
ffe02b40 4618 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4619 WARN_ON(val > dev_priv->rps.max_freq);
4620 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4621
dc97997a 4622 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4623 "Odd GPU freq value\n"))
4624 val &= ~1;
4625
cd25dd5b
D		 4626 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4627
8fb55197 4628 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4629 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4630 if (!IS_CHERRYVIEW(dev_priv))
4631 gen6_set_rps_thresholds(dev_priv, val);
4632 }
ffe02b40 4633
ffe02b40
VS		 4634 dev_priv->rps.cur_freq = val;
4635 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4636}
4637
a7f6e231 4638/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4639 *
4640 * * If Gfx is Idle, then
a7f6e231
D		 4641 * 1. Forcewake Media well.
4642 * 2. Request idle freq.
4643 * 3. Release Forcewake of Media well.
76c3552f
D		 4644*/
4645static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4646{
aed242ff 4647 u32 val = dev_priv->rps.idle_freq;
5549d25f 4648
aed242ff 4649 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4650 return;
4651
a7f6e231
D		 4652 /* Wake up the media well, as that takes a lot less
4653 * power than the Render well. */
4654 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4655 valleyview_set_rps(dev_priv, val);
a7f6e231 4656 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4657}
4658
43cf3bf0
CW		 4659void gen6_rps_busy(struct drm_i915_private *dev_priv)
4660{
4661 mutex_lock(&dev_priv->rps.hw_lock);
4662 if (dev_priv->rps.enabled) {
4663 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4664 gen6_rps_reset_ei(dev_priv);
4665 I915_WRITE(GEN6_PMINTRMSK,
4666 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4667 }
4668 mutex_unlock(&dev_priv->rps.hw_lock);
4669}
4670
b29c19b6
CW		 4671void gen6_rps_idle(struct drm_i915_private *dev_priv)
4672{
4673 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4674 if (dev_priv->rps.enabled) {
dc97997a 4675 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 4676 vlv_set_rps_idle(dev_priv);
7526ed79 4677 else
dc97997a 4678 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 4679 dev_priv->rps.last_adj = 0;
43cf3bf0 4680 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4681 }
8d3afd7d 4682 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4683
8d3afd7d 4684 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4685 while (!list_empty(&dev_priv->rps.clients))
4686 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4687 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4688}
4689
1854d5ca 4690void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4691 struct intel_rps_client *rps,
4692 unsigned long submitted)
b29c19b6 4693{
8d3afd7d
CW		 4694 /* This is intentionally racy! We peek at the state here, then
4695 * validate inside the RPS worker.
4696 */
4697 if (!(dev_priv->mm.busy &&
4698 dev_priv->rps.enabled &&
4699 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4700 return;
43cf3bf0 4701
e61b9958
CW		 4702 /* Force a RPS boost (and don't count it against the client) if
4703 * the GPU is severely congested.
4704 */
d0bc54f2 4705 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4706 rps = NULL;
4707
8d3afd7d
CW		 4708 spin_lock(&dev_priv->rps.client_lock);
4709 if (rps == NULL || list_empty(&rps->link)) {
4710 spin_lock_irq(&dev_priv->irq_lock);
4711 if (dev_priv->rps.interrupts_enabled) {
4712 dev_priv->rps.client_boost = true;
4713 queue_work(dev_priv->wq, &dev_priv->rps.work);
4714 }
4715 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4716
2e1b8730
CW		 4717 if (rps != NULL) {
4718 list_add(&rps->link, &dev_priv->rps.clients);
4719 rps->boosts++;
1854d5ca
CW		 4720 } else
4721 dev_priv->rps.boosts++;
c0951f0c 4722 }
8d3afd7d 4723 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4724}
4725
dc97997a 4726void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 4727{
dc97997a
CW		 4728 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4729 valleyview_set_rps(dev_priv, val);
ffe02b40 4730 else
dc97997a 4731 gen6_set_rps(dev_priv, val);
0a073b84
JB		 4732}
4733
dc97997a 4734static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 4735{
20e49366 4736 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4737 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4738}
4739
dc97997a 4740static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 4741{
2030d684
AG		 4742 I915_WRITE(GEN6_RP_CONTROL, 0);
4743}
4744
dc97997a 4745static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 4746{
d20d4f0c 4747 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4748 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4749 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4750}
4751
dc97997a 4752static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 4753{
38807746
D		 4754 I915_WRITE(GEN6_RC_CONTROL, 0);
4755}
4756
dc97997a 4757static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 4758{
98a2e5f9
D		 4759 /* we're doing forcewake before Disabling RC6,
4760 * This what the BIOS expects when going into suspend */
59bad947 4761 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4762
44fc7d5c 4763 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4764
59bad947 4765 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4766}
4767
dc97997a 4768static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 4769{
dc97997a 4770 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 4771 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4772 mode = GEN6_RC_CTL_RC6_ENABLE;
4773 else
4774 mode = 0;
4775 }
dc97997a 4776 if (HAS_RC6p(dev_priv))
58abf1da 4777 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4778 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4779 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4780 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4781
4782 else
4783 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4784 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4785}
4786
dc97997a 4787static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 4788{
72e96d64 4789 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 4790 bool enable_rc6 = true;
4791 unsigned long rc6_ctx_base;
4792
4793 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4794 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4795 enable_rc6 = false;
4796 }
4797
4798 /*
4799 * The exact context size is not known for BXT, so assume a page size
4800 * for this check.
4801 */
4802 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 4803 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4804 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4805 ggtt->stolen_reserved_size))) {
274008e8
SAK		 4806 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4807 enable_rc6 = false;
4808 }
4809
4810 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4811 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4812 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4813 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4814 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4815 enable_rc6 = false;
4816 }
4817
4818 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4819 GEN6_RC_CTL_HW_ENABLE)) &&
4820 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4821 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4822 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4823 enable_rc6 = false;
4824 }
4825
4826 return enable_rc6;
4827}
4828
dc97997a 4829int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 4830{
e7d66d89 4831 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 4832 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 4833 return 0;
4834
274008e8
SAK		 4835 if (!enable_rc6)
4836 return 0;
4837
dc97997a 4838 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 4839 DRM_INFO("RC6 disabled by BIOS\n");
4840 return 0;
4841 }
4842
456470eb 4843 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4844 if (enable_rc6 >= 0) {
4845 int mask;
4846
dc97997a 4847 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 4848 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4849 INTEL_RC6pp_ENABLE;
4850 else
4851 mask = INTEL_RC6_ENABLE;
4852
4853 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4854 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4855 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4856
4857 return enable_rc6 & mask;
4858 }
2b4e57bd 4859
dc97997a 4860 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 4861 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4862
4863 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4864}
4865
dc97997a 4866static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0 4867{
93ee2920
TR		 4868 uint32_t rp_state_cap;
4869 u32 ddcc_status = 0;
4870 int ret;
4871
3280e8b0
BW		 4872 /* All of these values are in units of 50MHz */
4873 dev_priv->rps.cur_freq = 0;
93ee2920 4874 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 4875 if (IS_BROXTON(dev_priv)) {
35040562
BP		 4876 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4877 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4878 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4879 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4880 } else {
4881 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4882 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4883 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4884 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4885 }
4886
3280e8b0
BW		 4887 /* hw_max = RP0 until we check for overclocking */
4888 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4889
93ee2920 4890 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 4891 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
4892 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
93ee2920
TR		 4893 ret = sandybridge_pcode_read(dev_priv,
4894 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4895 &ddcc_status);
4896 if (0 == ret)
4897 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4898 clamp_t(u8,
4899 ((ddcc_status >> 8) & 0xff),
4900 dev_priv->rps.min_freq,
4901 dev_priv->rps.max_freq);
93ee2920
TR		 4902 }
4903
dc97997a 4904 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c
AG		 4905 /* Store the frequency values in 16.66 MHZ units, which is
4906 the natural hardware unit for SKL */
4907 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4908 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4909 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4910 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4911 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4912 }
4913
aed242ff
CW		 4914 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4915
3280e8b0
BW		 4916 /* Preserve min/max settings in case of re-init */
4917 if (dev_priv->rps.max_freq_softlimit == 0)
4918 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4919
93ee2920 4920 if (dev_priv->rps.min_freq_softlimit == 0) {
dc97997a 4921 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
93ee2920 4922 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4923 max_t(int, dev_priv->rps.efficient_freq,
4924 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4925 else
4926 dev_priv->rps.min_freq_softlimit =
4927 dev_priv->rps.min_freq;
4928 }
3280e8b0
BW		 4929}
4930
b6fef0ef 4931/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 4932static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 4933{
b6fef0ef
JB		 4934 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4935
dc97997a 4936 gen6_init_rps_frequencies(dev_priv);
ba1c554c 4937
23eafea6 4938 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4939 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 4940 /*
4941 * BIOS could leave the Hw Turbo enabled, so need to explicitly
4942 * clear out the Control register just to avoid inconsitency
4943 * with debugfs interface, which will show Turbo as enabled
4944 * only and that is not expected by the User after adding the
4945 * WaGsvDisableTurbo. Apart from this there is no problem even
4946 * if the Turbo is left enabled in the Control register, as the
4947 * Up/Down interrupts would remain masked.
4948 */
dc97997a 4949 gen9_disable_rps(dev_priv);
23eafea6
SAK		 4950 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4951 return;
4952 }
4953
0beb059a
AG		 4954 /* Program defaults and thresholds for RPS*/
4955 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4956 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4957
4958 /* 1 second timeout*/
4959 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4960 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4961
b6fef0ef 4962 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4963
0beb059a
AG		 4964 /* Leaning on the below call to gen6_set_rps to program/setup the
4965 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4966 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4967 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 4968 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
b6fef0ef
JB		 4969
4970 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4971}
4972
dc97997a 4973static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 4974{
e2f80391 4975 struct intel_engine_cs *engine;
20e49366 4976 uint32_t rc6_mask = 0;
20e49366
ZW		 4977
4978 /* 1a: Software RC state - RC0 */
4979 I915_WRITE(GEN6_RC_STATE, 0);
4980
4981 /* 1b: Get forcewake during program sequence. Although the driver
4982 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4983 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4984
4985 /* 2a: Disable RC states. */
4986 I915_WRITE(GEN6_RC_CONTROL, 0);
4987
4988 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4989
4990 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 4991 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 4992 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4993 else
4994 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4995 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4996 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 4997 for_each_engine(engine, dev_priv)
e2f80391 4998 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 4999
dc97997a 5000 if (HAS_GUC_UCODE(dev_priv))
97c322e7
SAK		 5001 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5002
20e49366 5003 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5004
38c23527
ZW		 5005 /* 2c: Program Coarse Power Gating Policies. */
5006 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5007 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5008
20e49366 5009 /* 3a: Enable RC6 */
dc97997a 5010 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5011 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5012 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5013 /* WaRsUseTimeoutMode */
dc97997a
CW		 5014 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5015 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5016 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5017 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5018 GEN7_RC_CTL_TO_MODE |
5019 rc6_mask);
3e7732a0
SAK		 5020 } else {
5021 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5022 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5023 GEN6_RC_CTL_EI_MODE(1) |
5024 rc6_mask);
3e7732a0 5025 }
20e49366 5026
cb07bae0
SK		 5027 /*
5028 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5029 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5030 */
dc97997a 5031 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5032 I915_WRITE(GEN9_PG_ENABLE, 0);
5033 else
5034 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5035 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5036
59bad947 5037 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5038}
5039
dc97997a 5040static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5041{
e2f80391 5042 struct intel_engine_cs *engine;
93ee2920 5043 uint32_t rc6_mask = 0;
6edee7f3
BW		 5044
5045 /* 1a: Software RC state - RC0 */
5046 I915_WRITE(GEN6_RC_STATE, 0);
5047
5048 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5049 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5050 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5051
5052 /* 2a: Disable RC states. */
5053 I915_WRITE(GEN6_RC_CONTROL, 0);
5054
93ee2920 5055 /* Initialize rps frequencies */
dc97997a 5056 gen6_init_rps_frequencies(dev_priv);
6edee7f3
BW		 5057
5058 /* 2b: Program RC6 thresholds.*/
5059 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5060 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5061 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5062 for_each_engine(engine, dev_priv)
e2f80391 5063 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5064 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5065 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5066 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5067 else
5068 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5069
5070 /* 3: Enable RC6 */
dc97997a 5071 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5072 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5073 intel_print_rc6_info(dev_priv, rc6_mask);
5074 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5075 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5076 GEN7_RC_CTL_TO_MODE |
5077 rc6_mask);
5078 else
5079 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5080 GEN6_RC_CTL_EI_MODE(1) |
5081 rc6_mask);
6edee7f3
BW		 5082
5083 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5084 I915_WRITE(GEN6_RPNSWREQ,
5085 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5086 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5087 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5088 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5089 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5090
5091 /* Docs recommend 900MHz, and 300 MHz respectively */
5092 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5093 dev_priv->rps.max_freq_softlimit << 24 |
5094 dev_priv->rps.min_freq_softlimit << 16);
5095
5096 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5097 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5098 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5099 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5100
5101 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5102
5103 /* 5: Enable RPS */
7526ed79
DV		 5104 I915_WRITE(GEN6_RP_CONTROL,
5105 GEN6_RP_MEDIA_TURBO |
5106 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5107 GEN6_RP_MEDIA_IS_GFX |
5108 GEN6_RP_ENABLE |
5109 GEN6_RP_UP_BUSY_AVG |
5110 GEN6_RP_DOWN_IDLE_AVG);
5111
5112 /* 6: Ring frequency + overclocking (our driver does this later */
5113
c7f3153a 5114 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5115 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
7526ed79 5116
59bad947 5117 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5118}
5119
dc97997a 5120static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5121{
e2f80391 5122 struct intel_engine_cs *engine;
d060c169 5123 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5124 u32 gtfifodbg;
2b4e57bd 5125 int rc6_mode;
b4ac5afc 5126 int ret;
2b4e57bd 5127
4fc688ce 5128 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5129
2b4e57bd
ED		 5130 /* Here begins a magic sequence of register writes to enable
5131 * auto-downclocking.
5132 *
5133 * Perhaps there might be some value in exposing these to
5134 * userspace...
5135 */
5136 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5137
5138 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5139 gtfifodbg = I915_READ(GTFIFODBG);
5140 if (gtfifodbg) {
2b4e57bd
ED		 5141 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5142 I915_WRITE(GTFIFODBG, gtfifodbg);
5143 }
5144
59bad947 5145 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5146
93ee2920 5147 /* Initialize rps frequencies */
dc97997a 5148 gen6_init_rps_frequencies(dev_priv);
dd0a1aa1 5149
2b4e57bd
ED		 5150 /* disable the counters and set deterministic thresholds */
5151 I915_WRITE(GEN6_RC_CONTROL, 0);
5152
5153 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5154 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5155 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5156 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5157 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5158
b4ac5afc 5159 for_each_engine(engine, dev_priv)
e2f80391 5160 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5161
5162 I915_WRITE(GEN6_RC_SLEEP, 0);
5163 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5164 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5165 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5166 else
5167 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5168 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5169 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5170
5a7dc92a 5171 /* Check if we are enabling RC6 */
dc97997a 5172 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5173 if (rc6_mode & INTEL_RC6_ENABLE)
5174 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5175
5a7dc92a 5176 /* We don't use those on Haswell */
dc97997a 5177 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5178 if (rc6_mode & INTEL_RC6p_ENABLE)
5179 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5180
5a7dc92a
ED		 5181 if (rc6_mode & INTEL_RC6pp_ENABLE)
5182 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5183 }
2b4e57bd 5184
dc97997a 5185 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5186
5187 I915_WRITE(GEN6_RC_CONTROL,
5188 rc6_mask |
5189 GEN6_RC_CTL_EI_MODE(1) |
5190 GEN6_RC_CTL_HW_ENABLE);
5191
dd75fdc8
CW		 5192 /* Power down if completely idle for over 50ms */
5193 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5194 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5195
42c0526c 5196 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5197 if (ret)
42c0526c 5198 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5199
5200 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5201 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5202 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5203 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5204 (pcu_mbox & 0xff) * 50);
b39fb297 5205 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5206 }
5207
dd75fdc8 5208 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5209 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b4e57bd 5210
31643d54
BW		 5211 rc6vids = 0;
5212 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5213 if (IS_GEN6(dev_priv) && ret) {
31643d54 5214 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5215 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5216 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5217 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5218 rc6vids &= 0xffff00;
5219 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5220 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5221 if (ret)
5222 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5223 }
5224
59bad947 5225 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5226}
5227
dc97997a 5228static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5229{
5230 int min_freq = 15;
3ebecd07
CW		 5231 unsigned int gpu_freq;
5232 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5233 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5234 int scaling_factor = 180;
eda79642 5235 struct cpufreq_policy *policy;
2b4e57bd 5236
4fc688ce 5237 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5238
eda79642
BW		 5239 policy = cpufreq_cpu_get(0);
5240 if (policy) {
5241 max_ia_freq = policy->cpuinfo.max_freq;
5242 cpufreq_cpu_put(policy);
5243 } else {
5244 /*
5245 * Default to measured freq if none found, PCU will ensure we
5246 * don't go over
5247 */
2b4e57bd 5248 max_ia_freq = tsc_khz;
eda79642 5249 }
2b4e57bd
ED		 5250
5251 /* Convert from kHz to MHz */
5252 max_ia_freq /= 1000;
5253
153b4b95 5254 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5255 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5256 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5257
dc97997a 5258 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5259 /* Convert GT frequency to 50 HZ units */
5260 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5261 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5262 } else {
5263 min_gpu_freq = dev_priv->rps.min_freq;
5264 max_gpu_freq = dev_priv->rps.max_freq;
5265 }
5266
2b4e57bd
ED		 5267 /*
5268 * For each potential GPU frequency, load a ring frequency we'd like
5269 * to use for memory access. We do this by specifying the IA frequency
5270 * the PCU should use as a reference to determine the ring frequency.
5271 */
4c8c7743
AG		 5272 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5273 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5274 unsigned int ia_freq = 0, ring_freq = 0;
5275
dc97997a 5276 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5277 /*
5278 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5279 * No floor required for ring frequency on SKL.
5280 */
5281 ring_freq = gpu_freq;
dc97997a 5282 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5283 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5284 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5285 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5286 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5287 ring_freq = max(min_ring_freq, ring_freq);
5288 /* leave ia_freq as the default, chosen by cpufreq */
5289 } else {
5290 /* On older processors, there is no separate ring
5291 * clock domain, so in order to boost the bandwidth
5292 * of the ring, we need to upclock the CPU (ia_freq).
5293 *
5294 * For GPU frequencies less than 750MHz,
5295 * just use the lowest ring freq.
5296 */
5297 if (gpu_freq < min_freq)
5298 ia_freq = 800;
5299 else
5300 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5301 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5302 }
2b4e57bd 5303
42c0526c
BW		 5304 sandybridge_pcode_write(dev_priv,
5305 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5306 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5307 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5308 gpu_freq);
2b4e57bd 5309 }
2b4e57bd
ED		 5310}
5311
dc97997a 5312void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
c2bc2fc5 5313{
dc97997a 5314 if (!HAS_CORE_RING_FREQ(dev_priv))
c2bc2fc5
ID		 5315 return;
5316
5317 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a 5318 __gen6_update_ring_freq(dev_priv);
c2bc2fc5
ID		 5319 mutex_unlock(&dev_priv->rps.hw_lock);
5320}
5321
03af2045 5322static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5323{
5324 u32 val, rp0;
5325
5b5929cb 5326 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5327
dc97997a 5328 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5329 case 8:
5330 /* (2 * 4) config */
5331 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5332 break;
5333 case 12:
5334 /* (2 * 6) config */
5335 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5336 break;
5337 case 16:
5338 /* (2 * 8) config */
5339 default:
5340 /* Setting (2 * 8) Min RP0 for any other combination */
5341 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5342 break;
095acd5f 5343 }
5b5929cb
JN		 5344
5345 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5346
2b6b3a09
D		 5347 return rp0;
5348}
5349
5350static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5351{
5352 u32 val, rpe;
5353
5354 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5355 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5356
5357 return rpe;
5358}
5359
7707df4a
D		 5360static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5361{
5362 u32 val, rp1;
5363
5b5929cb
JN		 5364 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5365 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5366
7707df4a
D		 5367 return rp1;
5368}
5369
f8f2b001
D		 5370static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5371{
5372 u32 val, rp1;
5373
5374 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5375
5376 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5377
5378 return rp1;
5379}
5380
03af2045 5381static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5382{
5383 u32 val, rp0;
5384
64936258 5385 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5386
5387 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5388 /* Clamp to max */
5389 rp0 = min_t(u32, rp0, 0xea);
5390
5391 return rp0;
5392}
5393
5394static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5395{
5396 u32 val, rpe;
5397
64936258 5398 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5399 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5400 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5401 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5402
5403 return rpe;
5404}
5405
03af2045 5406static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5407{
36146035
ID		 5408 u32 val;
5409
5410 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5411 /*
5412 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5413 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5414 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5415 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5416 * to make sure it matches what Punit accepts.
5417 */
5418 return max_t(u32, val, 0xc0);
0a073b84
JB		 5419}
5420
ae48434c
ID		 5421/* Check that the pctx buffer wasn't move under us. */
5422static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5423{
5424 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5425
5426 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5427 dev_priv->vlv_pctx->stolen->start);
5428}
5429
38807746
D		 5430
5431/* Check that the pcbr address is not empty. */
5432static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5433{
5434 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5435
5436 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5437}
5438
dc97997a 5439static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5440{
62106b4f 5441 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5442 unsigned long pctx_paddr, paddr;
38807746
D		 5443 u32 pcbr;
5444 int pctx_size = 32*1024;
5445
38807746
D		 5446 pcbr = I915_READ(VLV_PCBR);
5447 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5448 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5449 paddr = (dev_priv->mm.stolen_base +
62106b4f 5450 (ggtt->stolen_size - pctx_size));
38807746
D		 5451
5452 pctx_paddr = (paddr & (~4095));
5453 I915_WRITE(VLV_PCBR, pctx_paddr);
5454 }
ce611ef8
VS		 5455
5456 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5457}
5458
dc97997a 5459static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5460{
c9cddffc
JB		 5461 struct drm_i915_gem_object *pctx;
5462 unsigned long pctx_paddr;
5463 u32 pcbr;
5464 int pctx_size = 24*1024;
5465
dc97997a 5466 mutex_lock(&dev_priv->dev->struct_mutex);
17b0c1f7 5467
c9cddffc
JB		 5468 pcbr = I915_READ(VLV_PCBR);
5469 if (pcbr) {
5470 /* BIOS set it up already, grab the pre-alloc'd space */
5471 int pcbr_offset;
5472
5473 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5474 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5475 pcbr_offset,
190d6cd5 5476 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5477 pctx_size);
5478 goto out;
5479 }
5480
ce611ef8
VS		 5481 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5482
c9cddffc
JB		 5483 /*
5484 * From the Gunit register HAS:
5485 * The Gfx driver is expected to program this register and ensure
5486 * proper allocation within Gfx stolen memory. For example, this
5487 * register should be programmed such than the PCBR range does not
5488 * overlap with other ranges, such as the frame buffer, protected
5489 * memory, or any other relevant ranges.
5490 */
dc97997a 5491 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
c9cddffc
JB		 5492 if (!pctx) {
5493 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5494 goto out;
c9cddffc
JB		 5495 }
5496
5497 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5498 I915_WRITE(VLV_PCBR, pctx_paddr);
5499
5500out:
ce611ef8 5501 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5502 dev_priv->vlv_pctx = pctx;
dc97997a 5503 mutex_unlock(&dev_priv->dev->struct_mutex);
c9cddffc
JB		 5504}
5505
dc97997a 5506static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5507{
ae48434c
ID		 5508 if (WARN_ON(!dev_priv->vlv_pctx))
5509 return;
5510
ee504898 5511 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5512 dev_priv->vlv_pctx = NULL;
5513}
5514
c30fec65
VS		 5515static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5516{
5517 dev_priv->rps.gpll_ref_freq =
5518 vlv_get_cck_clock(dev_priv, "GPLL ref",
5519 CCK_GPLL_CLOCK_CONTROL,
5520 dev_priv->czclk_freq);
5521
5522 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5523 dev_priv->rps.gpll_ref_freq);
5524}
5525
dc97997a 5526static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5527{
2bb25c17 5528 u32 val;
4e80519e 5529
dc97997a 5530 valleyview_setup_pctx(dev_priv);
4e80519e 5531
c30fec65
VS		 5532 vlv_init_gpll_ref_freq(dev_priv);
5533
4e80519e
ID		 5534 mutex_lock(&dev_priv->rps.hw_lock);
5535
2bb25c17
VS		 5536 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5537 switch ((val >> 6) & 3) {
5538 case 0:
5539 case 1:
5540 dev_priv->mem_freq = 800;
5541 break;
5542 case 2:
5543 dev_priv->mem_freq = 1066;
5544 break;
5545 case 3:
5546 dev_priv->mem_freq = 1333;
5547 break;
5548 }
80b83b62 5549 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5550
4e80519e
ID		 5551 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5552 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5553 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5554 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5555 dev_priv->rps.max_freq);
5556
5557 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5558 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5559 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5560 dev_priv->rps.efficient_freq);
5561
f8f2b001
D		 5562 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5563 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5564 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5565 dev_priv->rps.rp1_freq);
5566
4e80519e
ID		 5567 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5568 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5569 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5570 dev_priv->rps.min_freq);
5571
aed242ff
CW		 5572 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5573
4e80519e
ID		 5574 /* Preserve min/max settings in case of re-init */
5575 if (dev_priv->rps.max_freq_softlimit == 0)
5576 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5577
5578 if (dev_priv->rps.min_freq_softlimit == 0)
5579 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5580
5581 mutex_unlock(&dev_priv->rps.hw_lock);
5582}
5583
dc97997a 5584static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5585{
2bb25c17 5586 u32 val;
2b6b3a09 5587
dc97997a 5588 cherryview_setup_pctx(dev_priv);
2b6b3a09 5589
c30fec65
VS		 5590 vlv_init_gpll_ref_freq(dev_priv);
5591
2b6b3a09
D		 5592 mutex_lock(&dev_priv->rps.hw_lock);
5593
a580516d 5594 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5595 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5596 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5597
2bb25c17 5598 switch ((val >> 2) & 0x7) {
2bb25c17 5599 case 3:
2bb25c17
VS		 5600 dev_priv->mem_freq = 2000;
5601 break;
bfa7df01 5602 default:
2bb25c17
VS		 5603 dev_priv->mem_freq = 1600;
5604 break;
5605 }
80b83b62 5606 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5607
2b6b3a09
D		 5608 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5609 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5610 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5611 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5612 dev_priv->rps.max_freq);
5613
5614 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5615 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5616 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5617 dev_priv->rps.efficient_freq);
5618
7707df4a
D		 5619 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5620 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5621 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5622 dev_priv->rps.rp1_freq);
5623
5b7c91b7
D		 5624 /* PUnit validated range is only [RPe, RP0] */
5625 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5626 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5627 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5628 dev_priv->rps.min_freq);
5629
1c14762d
VS		 5630 WARN_ONCE((dev_priv->rps.max_freq |
5631 dev_priv->rps.efficient_freq |
5632 dev_priv->rps.rp1_freq |
5633 dev_priv->rps.min_freq) & 1,
5634 "Odd GPU freq values\n");
5635
aed242ff
CW		 5636 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5637
2b6b3a09
D		 5638 /* Preserve min/max settings in case of re-init */
5639 if (dev_priv->rps.max_freq_softlimit == 0)
5640 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5641
5642 if (dev_priv->rps.min_freq_softlimit == 0)
5643 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5644
5645 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5646}
5647
dc97997a 5648static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5649{
dc97997a 5650 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5651}
5652
dc97997a 5653static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5654{
e2f80391 5655 struct intel_engine_cs *engine;
2b6b3a09 5656 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5657
5658 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5659
297b32ec
VS		 5660 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5661 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5662 if (gtfifodbg) {
5663 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5664 gtfifodbg);
5665 I915_WRITE(GTFIFODBG, gtfifodbg);
5666 }
5667
5668 cherryview_check_pctx(dev_priv);
5669
5670 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5671 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5672 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5673
160614a2
VS		 5674 /* Disable RC states. */
5675 I915_WRITE(GEN6_RC_CONTROL, 0);
5676
38807746
D		 5677 /* 2a: Program RC6 thresholds.*/
5678 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5679 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5680 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5681
b4ac5afc 5682 for_each_engine(engine, dev_priv)
e2f80391 5683 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5684 I915_WRITE(GEN6_RC_SLEEP, 0);
5685
f4f71c7d
D		 5686 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5687 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5688
5689 /* allows RC6 residency counter to work */
5690 I915_WRITE(VLV_COUNTER_CONTROL,
5691 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5692 VLV_MEDIA_RC6_COUNT_EN |
5693 VLV_RENDER_RC6_COUNT_EN));
5694
5695 /* For now we assume BIOS is allocating and populating the PCBR */
5696 pcbr = I915_READ(VLV_PCBR);
5697
38807746 5698 /* 3: Enable RC6 */
dc97997a
CW		 5699 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5700 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5701 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5702
5703 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5704
2b6b3a09 5705 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5706 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5707 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5708 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5709 I915_WRITE(GEN6_RP_UP_EI, 66000);
5710 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5711
5712 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5713
5714 /* 5: Enable RPS */
5715 I915_WRITE(GEN6_RP_CONTROL,
5716 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5717 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5718 GEN6_RP_ENABLE |
5719 GEN6_RP_UP_BUSY_AVG |
5720 GEN6_RP_DOWN_IDLE_AVG);
5721
3ef62342
D		 5722 /* Setting Fixed Bias */
5723 val = VLV_OVERRIDE_EN |
5724 VLV_SOC_TDP_EN |
5725 CHV_BIAS_CPU_50_SOC_50;
5726 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5727
2b6b3a09
D		 5728 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5729
8d40c3ae
VS		 5730 /* RPS code assumes GPLL is used */
5731 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5732
742f491d 5733 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5734 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5735
5736 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5737 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5738 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5739 dev_priv->rps.cur_freq);
5740
5741 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5742 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5743 dev_priv->rps.idle_freq);
2b6b3a09 5744
dc97997a 5745 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b6b3a09 5746
59bad947 5747 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5748}
5749
dc97997a 5750static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 5751{
e2f80391 5752 struct intel_engine_cs *engine;
2a5913a8 5753 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5754
5755 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5756
ae48434c
ID		 5757 valleyview_check_pctx(dev_priv);
5758
297b32ec
VS		 5759 gtfifodbg = I915_READ(GTFIFODBG);
5760 if (gtfifodbg) {
f7d85c1e
JB		 5761 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5762 gtfifodbg);
0a073b84
JB		 5763 I915_WRITE(GTFIFODBG, gtfifodbg);
5764 }
5765
c8d9a590 5766 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5767 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5768
160614a2
VS		 5769 /* Disable RC states. */
5770 I915_WRITE(GEN6_RC_CONTROL, 0);
5771
cad725fe 5772 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5773 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5774 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5775 I915_WRITE(GEN6_RP_UP_EI, 66000);
5776 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5777
5778 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5779
5780 I915_WRITE(GEN6_RP_CONTROL,
5781 GEN6_RP_MEDIA_TURBO |
5782 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5783 GEN6_RP_MEDIA_IS_GFX |
5784 GEN6_RP_ENABLE |
5785 GEN6_RP_UP_BUSY_AVG |
5786 GEN6_RP_DOWN_IDLE_CONT);
5787
5788 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5789 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5790 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5791
b4ac5afc 5792 for_each_engine(engine, dev_priv)
e2f80391 5793 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5794
2f0aa304 5795 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5796
5797 /* allows RC6 residency counter to work */
49798eb2 5798 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5799 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5800 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5801 VLV_MEDIA_RC6_COUNT_EN |
5802 VLV_RENDER_RC6_COUNT_EN));
31685c25 5803
dc97997a 5804 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 5805 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 5806
dc97997a 5807 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 5808
a2b23fe0 5809 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5810
3ef62342
D		 5811 /* Setting Fixed Bias */
5812 val = VLV_OVERRIDE_EN |
5813 VLV_SOC_TDP_EN |
5814 VLV_BIAS_CPU_125_SOC_875;
5815 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5816
64936258 5817 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5818
8d40c3ae
VS		 5819 /* RPS code assumes GPLL is used */
5820 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5821
742f491d 5822 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5823 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5824
b39fb297 5825 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5826 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5827 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5828 dev_priv->rps.cur_freq);
0a073b84 5829
73008b98 5830 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5831 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5832 dev_priv->rps.idle_freq);
0a073b84 5833
dc97997a 5834 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
0a073b84 5835
59bad947 5836 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5837}
5838
dde18883
ED		 5839static unsigned long intel_pxfreq(u32 vidfreq)
5840{
5841 unsigned long freq;
5842 int div = (vidfreq & 0x3f0000) >> 16;
5843 int post = (vidfreq & 0x3000) >> 12;
5844 int pre = (vidfreq & 0x7);
5845
5846 if (!pre)
5847 return 0;
5848
5849 freq = ((div * 133333) / ((1<<post) * pre));
5850
5851 return freq;
5852}
5853
eb48eb00
DV		 5854static const struct cparams {
5855 u16 i;
5856 u16 t;
5857 u16 m;
5858 u16 c;
5859} cparams[] = {
5860 { 1, 1333, 301, 28664 },
5861 { 1, 1066, 294, 24460 },
5862 { 1, 800, 294, 25192 },
5863 { 0, 1333, 276, 27605 },
5864 { 0, 1066, 276, 27605 },
5865 { 0, 800, 231, 23784 },
5866};
5867
f531dcb2 5868static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5869{
5870 u64 total_count, diff, ret;
5871 u32 count1, count2, count3, m = 0, c = 0;
5872 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5873 int i;
5874
02d71956
DV		 5875 assert_spin_locked(&mchdev_lock);
5876
20e4d407 5877 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5878
5879 /* Prevent division-by-zero if we are asking too fast.
5880 * Also, we don't get interesting results if we are polling
5881 * faster than once in 10ms, so just return the saved value
5882 * in such cases.
5883 */
5884 if (diff1 <= 10)
20e4d407 5885 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5886
5887 count1 = I915_READ(DMIEC);
5888 count2 = I915_READ(DDREC);
5889 count3 = I915_READ(CSIEC);
5890
5891 total_count = count1 + count2 + count3;
5892
5893 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5894 if (total_count < dev_priv->ips.last_count1) {
5895 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5896 diff += total_count;
5897 } else {
20e4d407 5898 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5899 }
5900
5901 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5902 if (cparams[i].i == dev_priv->ips.c_m &&
5903 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5904 m = cparams[i].m;
5905 c = cparams[i].c;
5906 break;
5907 }
5908 }
5909
5910 diff = div_u64(diff, diff1);
5911 ret = ((m * diff) + c);
5912 ret = div_u64(ret, 10);
5913
20e4d407
DV		 5914 dev_priv->ips.last_count1 = total_count;
5915 dev_priv->ips.last_time1 = now;
eb48eb00 5916
20e4d407 5917 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5918
5919 return ret;
5920}
5921
f531dcb2
CW		 5922unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5923{
5924 unsigned long val;
5925
dc97997a 5926 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 5927 return 0;
5928
5929 spin_lock_irq(&mchdev_lock);
5930
5931 val = __i915_chipset_val(dev_priv);
5932
5933 spin_unlock_irq(&mchdev_lock);
5934
5935 return val;
5936}
5937
eb48eb00
DV		 5938unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5939{
5940 unsigned long m, x, b;
5941 u32 tsfs;
5942
5943 tsfs = I915_READ(TSFS);
5944
5945 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5946 x = I915_READ8(TR1);
5947
5948 b = tsfs & TSFS_INTR_MASK;
5949
5950 return ((m * x) / 127) - b;
5951}
5952
d972d6ee
MK		 5953static int _pxvid_to_vd(u8 pxvid)
5954{
5955 if (pxvid == 0)
5956 return 0;
5957
5958 if (pxvid >= 8 && pxvid < 31)
5959 pxvid = 31;
5960
5961 return (pxvid + 2) * 125;
5962}
5963
5964static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5965{
d972d6ee
MK		 5966 const int vd = _pxvid_to_vd(pxvid);
5967 const int vm = vd - 1125;
5968
dc97997a 5969 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 5970 return vm > 0 ? vm : 0;
5971
5972 return vd;
eb48eb00
DV		 5973}
5974
02d71956 5975static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5976{
5ed0bdf2 5977 u64 now, diff, diffms;
eb48eb00
DV		 5978 u32 count;
5979
02d71956 5980 assert_spin_locked(&mchdev_lock);
eb48eb00 5981
5ed0bdf2
TG		 5982 now = ktime_get_raw_ns();
5983 diffms = now - dev_priv->ips.last_time2;
5984 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5985
5986 /* Don't divide by 0 */
eb48eb00
DV		 5987 if (!diffms)
5988 return;
5989
5990 count = I915_READ(GFXEC);
5991
20e4d407
DV		 5992 if (count < dev_priv->ips.last_count2) {
5993 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5994 diff += count;
5995 } else {
20e4d407 5996 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5997 }
5998
20e4d407
DV		 5999 dev_priv->ips.last_count2 = count;
6000 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6001
6002 /* More magic constants... */
6003 diff = diff * 1181;
6004 diff = div_u64(diff, diffms * 10);
20e4d407 6005 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6006}
6007
02d71956
DV		 6008void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6009{
dc97997a 6010 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6011 return;
6012
9270388e 6013 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6014
6015 __i915_update_gfx_val(dev_priv);
6016
9270388e 6017 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6018}
6019
f531dcb2 6020static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6021{
6022 unsigned long t, corr, state1, corr2, state2;
6023 u32 pxvid, ext_v;
6024
02d71956
DV		 6025 assert_spin_locked(&mchdev_lock);
6026
616847e7 6027 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6028 pxvid = (pxvid >> 24) & 0x7f;
6029 ext_v = pvid_to_extvid(dev_priv, pxvid);
6030
6031 state1 = ext_v;
6032
6033 t = i915_mch_val(dev_priv);
6034
6035 /* Revel in the empirically derived constants */
6036
6037 /* Correction factor in 1/100000 units */
6038 if (t > 80)
6039 corr = ((t * 2349) + 135940);
6040 else if (t >= 50)
6041 corr = ((t * 964) + 29317);
6042 else /* < 50 */
6043 corr = ((t * 301) + 1004);
6044
6045 corr = corr * ((150142 * state1) / 10000 - 78642);
6046 corr /= 100000;
20e4d407 6047 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6048
6049 state2 = (corr2 * state1) / 10000;
6050 state2 /= 100; /* convert to mW */
6051
02d71956 6052 __i915_update_gfx_val(dev_priv);
eb48eb00 6053
20e4d407 6054 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6055}
6056
f531dcb2
CW		 6057unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6058{
6059 unsigned long val;
6060
dc97997a 6061 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6062 return 0;
6063
6064 spin_lock_irq(&mchdev_lock);
6065
6066 val = __i915_gfx_val(dev_priv);
6067
6068 spin_unlock_irq(&mchdev_lock);
6069
6070 return val;
6071}
6072
eb48eb00
DV		 6073/**
6074 * i915_read_mch_val - return value for IPS use
6075 *
6076 * Calculate and return a value for the IPS driver to use when deciding whether
6077 * we have thermal and power headroom to increase CPU or GPU power budget.
6078 */
6079unsigned long i915_read_mch_val(void)
6080{
6081 struct drm_i915_private *dev_priv;
6082 unsigned long chipset_val, graphics_val, ret = 0;
6083
9270388e 6084 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6085 if (!i915_mch_dev)
6086 goto out_unlock;
6087 dev_priv = i915_mch_dev;
6088
f531dcb2
CW		 6089 chipset_val = __i915_chipset_val(dev_priv);
6090 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6091
6092 ret = chipset_val + graphics_val;
6093
6094out_unlock:
9270388e 6095 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6096
6097 return ret;
6098}
6099EXPORT_SYMBOL_GPL(i915_read_mch_val);
6100
6101/**
6102 * i915_gpu_raise - raise GPU frequency limit
6103 *
6104 * Raise the limit; IPS indicates we have thermal headroom.
6105 */
6106bool i915_gpu_raise(void)
6107{
6108 struct drm_i915_private *dev_priv;
6109 bool ret = true;
6110
9270388e 6111 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6112 if (!i915_mch_dev) {
6113 ret = false;
6114 goto out_unlock;
6115 }
6116 dev_priv = i915_mch_dev;
6117
20e4d407
DV		 6118 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6119 dev_priv->ips.max_delay--;
eb48eb00
DV		 6120
6121out_unlock:
9270388e 6122 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6123
6124 return ret;
6125}
6126EXPORT_SYMBOL_GPL(i915_gpu_raise);
6127
6128/**
6129 * i915_gpu_lower - lower GPU frequency limit
6130 *
6131 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6132 * frequency maximum.
6133 */
6134bool i915_gpu_lower(void)
6135{
6136 struct drm_i915_private *dev_priv;
6137 bool ret = true;
6138
9270388e 6139 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6140 if (!i915_mch_dev) {
6141 ret = false;
6142 goto out_unlock;
6143 }
6144 dev_priv = i915_mch_dev;
6145
20e4d407
DV		 6146 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6147 dev_priv->ips.max_delay++;
eb48eb00
DV		 6148
6149out_unlock:
9270388e 6150 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6151
6152 return ret;
6153}
6154EXPORT_SYMBOL_GPL(i915_gpu_lower);
6155
6156/**
6157 * i915_gpu_busy - indicate GPU business to IPS
6158 *
6159 * Tell the IPS driver whether or not the GPU is busy.
6160 */
6161bool i915_gpu_busy(void)
6162{
6163 struct drm_i915_private *dev_priv;
e2f80391 6164 struct intel_engine_cs *engine;
eb48eb00
DV		 6165 bool ret = false;
6166
9270388e 6167 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6168 if (!i915_mch_dev)
6169 goto out_unlock;
6170 dev_priv = i915_mch_dev;
6171
b4ac5afc 6172 for_each_engine(engine, dev_priv)
e2f80391 6173 ret |= !list_empty(&engine->request_list);
eb48eb00
DV		 6174
6175out_unlock:
9270388e 6176 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6177
6178 return ret;
6179}
6180EXPORT_SYMBOL_GPL(i915_gpu_busy);
6181
6182/**
6183 * i915_gpu_turbo_disable - disable graphics turbo
6184 *
6185 * Disable graphics turbo by resetting the max frequency and setting the
6186 * current frequency to the default.
6187 */
6188bool i915_gpu_turbo_disable(void)
6189{
6190 struct drm_i915_private *dev_priv;
6191 bool ret = true;
6192
9270388e 6193 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6194 if (!i915_mch_dev) {
6195 ret = false;
6196 goto out_unlock;
6197 }
6198 dev_priv = i915_mch_dev;
6199
20e4d407 6200 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6201
91d14251 6202 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6203 ret = false;
6204
6205out_unlock:
9270388e 6206 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6207
6208 return ret;
6209}
6210EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6211
6212/**
6213 * Tells the intel_ips driver that the i915 driver is now loaded, if
6214 * IPS got loaded first.
6215 *
6216 * This awkward dance is so that neither module has to depend on the
6217 * other in order for IPS to do the appropriate communication of
6218 * GPU turbo limits to i915.
6219 */
6220static void
6221ips_ping_for_i915_load(void)
6222{
6223 void (*link)(void);
6224
6225 link = symbol_get(ips_link_to_i915_driver);
6226 if (link) {
6227 link();
6228 symbol_put(ips_link_to_i915_driver);
6229 }
6230}
6231
6232void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6233{
02d71956
DV		 6234 /* We only register the i915 ips part with intel-ips once everything is
6235 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6236 spin_lock_irq(&mchdev_lock);
eb48eb00 6237 i915_mch_dev = dev_priv;
9270388e 6238 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6239
6240 ips_ping_for_i915_load();
6241}
6242
6243void intel_gpu_ips_teardown(void)
6244{
9270388e 6245 spin_lock_irq(&mchdev_lock);
eb48eb00 6246 i915_mch_dev = NULL;
9270388e 6247 spin_unlock_irq(&mchdev_lock);
eb48eb00 6248}
76c3552f 6249
dc97997a 6250static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6251{
dde18883
ED		 6252 u32 lcfuse;
6253 u8 pxw[16];
6254 int i;
6255
6256 /* Disable to program */
6257 I915_WRITE(ECR, 0);
6258 POSTING_READ(ECR);
6259
6260 /* Program energy weights for various events */
6261 I915_WRITE(SDEW, 0x15040d00);
6262 I915_WRITE(CSIEW0, 0x007f0000);
6263 I915_WRITE(CSIEW1, 0x1e220004);
6264 I915_WRITE(CSIEW2, 0x04000004);
6265
6266 for (i = 0; i < 5; i++)
616847e7 6267 I915_WRITE(PEW(i), 0);
dde18883 6268 for (i = 0; i < 3; i++)
616847e7 6269 I915_WRITE(DEW(i), 0);
dde18883
ED		 6270
6271 /* Program P-state weights to account for frequency power adjustment */
6272 for (i = 0; i < 16; i++) {
616847e7 6273 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6274 unsigned long freq = intel_pxfreq(pxvidfreq);
6275 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6276 PXVFREQ_PX_SHIFT;
6277 unsigned long val;
6278
6279 val = vid * vid;
6280 val *= (freq / 1000);
6281 val *= 255;
6282 val /= (127*127*900);
6283 if (val > 0xff)
6284 DRM_ERROR("bad pxval: %ld\n", val);
6285 pxw[i] = val;
6286 }
6287 /* Render standby states get 0 weight */
6288 pxw[14] = 0;
6289 pxw[15] = 0;
6290
6291 for (i = 0; i < 4; i++) {
6292 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6293 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6294 I915_WRITE(PXW(i), val);
dde18883
ED		 6295 }
6296
6297 /* Adjust magic regs to magic values (more experimental results) */
6298 I915_WRITE(OGW0, 0);
6299 I915_WRITE(OGW1, 0);
6300 I915_WRITE(EG0, 0x00007f00);
6301 I915_WRITE(EG1, 0x0000000e);
6302 I915_WRITE(EG2, 0x000e0000);
6303 I915_WRITE(EG3, 0x68000300);
6304 I915_WRITE(EG4, 0x42000000);
6305 I915_WRITE(EG5, 0x00140031);
6306 I915_WRITE(EG6, 0);
6307 I915_WRITE(EG7, 0);
6308
6309 for (i = 0; i < 8; i++)
616847e7 6310 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6311
6312 /* Enable PMON + select events */
6313 I915_WRITE(ECR, 0x80000019);
6314
6315 lcfuse = I915_READ(LCFUSE02);
6316
20e4d407 6317 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6318}
6319
dc97997a 6320void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6321{
b268c699
ID		 6322 /*
6323 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6324 * requirement.
6325 */
6326 if (!i915.enable_rc6) {
6327 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6328 intel_runtime_pm_get(dev_priv);
6329 }
e6069ca8 6330
dc97997a
CW		 6331 if (IS_CHERRYVIEW(dev_priv))
6332 cherryview_init_gt_powersave(dev_priv);
6333 else if (IS_VALLEYVIEW(dev_priv))
6334 valleyview_init_gt_powersave(dev_priv);
ae48434c
ID		 6335}
6336
dc97997a 6337void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6338{
dc97997a 6339 if (IS_CHERRYVIEW(dev_priv))
38807746 6340 return;
dc97997a
CW		 6341 else if (IS_VALLEYVIEW(dev_priv))
6342 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6343
6344 if (!i915.enable_rc6)
6345 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6346}
6347
91d14251 6348static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
dbea3cea 6349{
dbea3cea
ID		 6350 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6351
91d14251 6352 gen6_disable_rps_interrupts(dev_priv);
dbea3cea
ID		 6353}
6354
156c7ca0
JB		 6355/**
6356 * intel_suspend_gt_powersave - suspend PM work and helper threads
dc97997a 6357 * @dev_priv: i915 device
156c7ca0
JB		 6358 *
6359 * We don't want to disable RC6 or other features here, we just want
6360 * to make sure any work we've queued has finished and won't bother
6361 * us while we're suspended.
6362 */
dc97997a 6363void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
156c7ca0 6364{
91d14251 6365 if (INTEL_GEN(dev_priv) < 6)
d4d70aa5
ID		 6366 return;
6367
91d14251 6368 gen6_suspend_rps(dev_priv);
b47adc17
D		 6369
6370 /* Force GPU to min freq during suspend */
6371 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6372}
6373
dc97997a 6374void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6375{
dc97997a 6376 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6377 ironlake_disable_drps(dev_priv);
dc97997a
CW		 6378 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6379 intel_suspend_gt_powersave(dev_priv);
e494837a 6380
4fc688ce 6381 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6382 if (INTEL_INFO(dev_priv)->gen >= 9) {
6383 gen9_disable_rc6(dev_priv);
6384 gen9_disable_rps(dev_priv);
6385 } else if (IS_CHERRYVIEW(dev_priv))
6386 cherryview_disable_rps(dev_priv);
6387 else if (IS_VALLEYVIEW(dev_priv))
6388 valleyview_disable_rps(dev_priv);
d20d4f0c 6389 else
dc97997a 6390 gen6_disable_rps(dev_priv);
e534770a 6391
c0951f0c 6392 dev_priv->rps.enabled = false;
4fc688ce 6393 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6394 }
8090c6b9
DV		 6395}
6396
1a01ab3b
JB		 6397static void intel_gen6_powersave_work(struct work_struct *work)
6398{
6399 struct drm_i915_private *dev_priv =
6400 container_of(work, struct drm_i915_private,
6401 rps.delayed_resume_work.work);
1a01ab3b 6402
4fc688ce 6403 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6404
dc97997a
CW		 6405 gen6_reset_rps_interrupts(dev_priv);
6406
6407 if (IS_CHERRYVIEW(dev_priv)) {
6408 cherryview_enable_rps(dev_priv);
6409 } else if (IS_VALLEYVIEW(dev_priv)) {
6410 valleyview_enable_rps(dev_priv);
6411 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6412 gen9_enable_rc6(dev_priv);
6413 gen9_enable_rps(dev_priv);
6414 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6415 __gen6_update_ring_freq(dev_priv);
6416 } else if (IS_BROADWELL(dev_priv)) {
6417 gen8_enable_rps(dev_priv);
6418 __gen6_update_ring_freq(dev_priv);
0a073b84 6419 } else {
dc97997a
CW		 6420 gen6_enable_rps(dev_priv);
6421 __gen6_update_ring_freq(dev_priv);
0a073b84 6422 }
aed242ff
CW		 6423
6424 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6425 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6426
6427 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6428 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6429
c0951f0c 6430 dev_priv->rps.enabled = true;
3cc134e3 6431
91d14251 6432 gen6_enable_rps_interrupts(dev_priv);
3cc134e3 6433
4fc688ce 6434 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6435
6436 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6437}
6438
dc97997a 6439void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6440{
f61018b1 6441 /* Powersaving is controlled by the host when inside a VM */
c033666a 6442 if (intel_vgpu_active(dev_priv))
f61018b1
YZ		 6443 return;
6444
dc97997a 6445 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6446 ironlake_enable_drps(dev_priv);
dc97997a
CW		 6447 mutex_lock(&dev_priv->dev->struct_mutex);
6448 intel_init_emon(dev_priv);
6449 mutex_unlock(&dev_priv->dev->struct_mutex);
6450 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
1a01ab3b
JB		 6451 /*
6452 * PCU communication is slow and this doesn't need to be
6453 * done at any specific time, so do this out of our fast path
6454 * to make resume and init faster.
c6df39b5
ID		 6455 *
6456 * We depend on the HW RC6 power context save/restore
6457 * mechanism when entering D3 through runtime PM suspend. So
6458 * disable RPM until RPS/RC6 is properly setup. We can only
6459 * get here via the driver load/system resume/runtime resume
6460 * paths, so the _noresume version is enough (and in case of
6461 * runtime resume it's necessary).
1a01ab3b 6462 */
c6df39b5
ID		 6463 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6464 round_jiffies_up_relative(HZ)))
6465 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6466 }
6467}
6468
dc97997a 6469void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
c6df39b5 6470{
dc97997a 6471 if (INTEL_INFO(dev_priv)->gen < 6)
dbea3cea
ID		 6472 return;
6473
91d14251 6474 gen6_suspend_rps(dev_priv);
c6df39b5 6475 dev_priv->rps.enabled = false;
c6df39b5
ID		 6476}
6477
3107bd48
DV		 6478static void ibx_init_clock_gating(struct drm_device *dev)
6479{
6480 struct drm_i915_private *dev_priv = dev->dev_private;
6481
6482 /*
6483 * On Ibex Peak and Cougar Point, we need to disable clock
6484 * gating for the panel power sequencer or it will fail to
6485 * start up when no ports are active.
6486 */
6487 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6488}
6489
0e088b8f
VS		 6490static void g4x_disable_trickle_feed(struct drm_device *dev)
6491{
6492 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6493 enum pipe pipe;
0e088b8f 6494
055e393f 6495 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6496 I915_WRITE(DSPCNTR(pipe),
6497 I915_READ(DSPCNTR(pipe)) |
6498 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6499
6500 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6501 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6502 }
6503}
6504
017636cc
VS		 6505static void ilk_init_lp_watermarks(struct drm_device *dev)
6506{
6507 struct drm_i915_private *dev_priv = dev->dev_private;
6508
6509 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6510 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6511 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6512
6513 /*
6514 * Don't touch WM1S_LP_EN here.
6515 * Doing so could cause underruns.
6516 */
6517}
6518
1fa61106 6519static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6520{
6521 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6522 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6523
f1e8fa56
DL		 6524 /*
6525 * Required for FBC
6526 * WaFbcDisableDpfcClockGating:ilk
6527 */
4d47e4f5
DL		 6528 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6529 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6530 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6531
6532 I915_WRITE(PCH_3DCGDIS0,
6533 MARIUNIT_CLOCK_GATE_DISABLE |
6534 SVSMUNIT_CLOCK_GATE_DISABLE);
6535 I915_WRITE(PCH_3DCGDIS1,
6536 VFMUNIT_CLOCK_GATE_DISABLE);
6537
6f1d69b0
ED		 6538 /*
6539 * According to the spec the following bits should be set in
6540 * order to enable memory self-refresh
6541 * The bit 22/21 of 0x42004
6542 * The bit 5 of 0x42020
6543 * The bit 15 of 0x45000
6544 */
6545 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6546 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6547 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6548 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6549 I915_WRITE(DISP_ARB_CTL,
6550 (I915_READ(DISP_ARB_CTL) |
6551 DISP_FBC_WM_DIS));
017636cc
VS		 6552
6553 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6554
6555 /*
6556 * Based on the document from hardware guys the following bits
6557 * should be set unconditionally in order to enable FBC.
6558 * The bit 22 of 0x42000
6559 * The bit 22 of 0x42004
6560 * The bit 7,8,9 of 0x42020.
6561 */
6562 if (IS_IRONLAKE_M(dev)) {
4bb35334 6563 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6564 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6565 I915_READ(ILK_DISPLAY_CHICKEN1) |
6566 ILK_FBCQ_DIS);
6567 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6568 I915_READ(ILK_DISPLAY_CHICKEN2) |
6569 ILK_DPARB_GATE);
6f1d69b0
ED		 6570 }
6571
4d47e4f5
DL		 6572 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6573
6f1d69b0
ED		 6574 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6575 I915_READ(ILK_DISPLAY_CHICKEN2) |
6576 ILK_ELPIN_409_SELECT);
6577 I915_WRITE(_3D_CHICKEN2,
6578 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6579 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6580
ecdb4eb7 6581 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6582 I915_WRITE(CACHE_MODE_0,
6583 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6584
4e04632e
AG		 6585 /* WaDisable_RenderCache_OperationalFlush:ilk */
6586 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6587
0e088b8f 6588 g4x_disable_trickle_feed(dev);
bdad2b2f 6589
3107bd48
DV		 6590 ibx_init_clock_gating(dev);
6591}
6592
6593static void cpt_init_clock_gating(struct drm_device *dev)
6594{
6595 struct drm_i915_private *dev_priv = dev->dev_private;
6596 int pipe;
3f704fa2 6597 uint32_t val;
3107bd48
DV		 6598
6599 /*
6600 * On Ibex Peak and Cougar Point, we need to disable clock
6601 * gating for the panel power sequencer or it will fail to
6602 * start up when no ports are active.
6603 */
cd664078
JB		 6604 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6605 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6606 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6607 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6608 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6609 /* The below fixes the weird display corruption, a few pixels shifted
6610 * downward, on (only) LVDS of some HP laptops with IVY.
6611 */
055e393f 6612 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6613 val = I915_READ(TRANS_CHICKEN2(pipe));
6614 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6615 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6616 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6617 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6618 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6619 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6620 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6621 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6622 }
3107bd48 6623 /* WADP0ClockGatingDisable */
055e393f 6624 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6625 I915_WRITE(TRANS_CHICKEN1(pipe),
6626 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6627 }
6f1d69b0
ED		 6628}
6629
1d7aaa0c
DV		 6630static void gen6_check_mch_setup(struct drm_device *dev)
6631{
6632 struct drm_i915_private *dev_priv = dev->dev_private;
6633 uint32_t tmp;
6634
6635 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6636 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6637 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6638 tmp);
1d7aaa0c
DV		 6639}
6640
1fa61106 6641static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6642{
6643 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6644 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6645
231e54f6 6646 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6647
6648 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6649 I915_READ(ILK_DISPLAY_CHICKEN2) |
6650 ILK_ELPIN_409_SELECT);
6651
ecdb4eb7 6652 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6653 I915_WRITE(_3D_CHICKEN,
6654 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6655
4e04632e
AG		 6656 /* WaDisable_RenderCache_OperationalFlush:snb */
6657 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6658
8d85d272
VS		 6659 /*
6660 * BSpec recoomends 8x4 when MSAA is used,
6661 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6662 *
6663 * Note that PS/WM thread counts depend on the WIZ hashing
6664 * disable bit, which we don't touch here, but it's good
6665 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6666 */
6667 I915_WRITE(GEN6_GT_MODE,
98533251 6668 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6669
017636cc 6670 ilk_init_lp_watermarks(dev);
6f1d69b0 6671
6f1d69b0 6672 I915_WRITE(CACHE_MODE_0,
50743298 6673 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6674
6675 I915_WRITE(GEN6_UCGCTL1,
6676 I915_READ(GEN6_UCGCTL1) |
6677 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6678 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6679
6680 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6681 * gating disable must be set. Failure to set it results in
6682 * flickering pixels due to Z write ordering failures after
6683 * some amount of runtime in the Mesa "fire" demo, and Unigine
6684 * Sanctuary and Tropics, and apparently anything else with
6685 * alpha test or pixel discard.
6686 *
6687 * According to the spec, bit 11 (RCCUNIT) must also be set,
6688 * but we didn't debug actual testcases to find it out.
0f846f81 6689 *
ef59318c
VS		 6690 * WaDisableRCCUnitClockGating:snb
6691 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6692 */
6693 I915_WRITE(GEN6_UCGCTL2,
6694 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6695 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6696
5eb146dd 6697 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6698 I915_WRITE(_3D_CHICKEN3,
6699 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6700
e927ecde
VS		 6701 /*
6702 * Bspec says:
6703 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6704 * 3DSTATE_SF number of SF output attributes is more than 16."
6705 */
6706 I915_WRITE(_3D_CHICKEN3,
6707 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6708
6f1d69b0
ED		 6709 /*
6710 * According to the spec the following bits should be
6711 * set in order to enable memory self-refresh and fbc:
6712 * The bit21 and bit22 of 0x42000
6713 * The bit21 and bit22 of 0x42004
6714 * The bit5 and bit7 of 0x42020
6715 * The bit14 of 0x70180
6716 * The bit14 of 0x71180
4bb35334
DL		 6717 *
6718 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6719 */
6720 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6721 I915_READ(ILK_DISPLAY_CHICKEN1) |
6722 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6723 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6724 I915_READ(ILK_DISPLAY_CHICKEN2) |
6725 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6726 I915_WRITE(ILK_DSPCLK_GATE_D,
6727 I915_READ(ILK_DSPCLK_GATE_D) |
6728 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6729 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6730
0e088b8f 6731 g4x_disable_trickle_feed(dev);
f8f2ac9a 6732
3107bd48 6733 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6734
6735 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6736}
6737
6738static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6739{
6740 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6741
3aad9059 6742 /*
46680e0a 6743 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6744 *
6745 * This actually overrides the dispatch
6746 * mode for all thread types.
6747 */
6f1d69b0
ED		 6748 reg &= ~GEN7_FF_SCHED_MASK;
6749 reg |= GEN7_FF_TS_SCHED_HW;
6750 reg |= GEN7_FF_VS_SCHED_HW;
6751 reg |= GEN7_FF_DS_SCHED_HW;
6752
6753 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6754}
6755
17a303ec
PZ		 6756static void lpt_init_clock_gating(struct drm_device *dev)
6757{
6758 struct drm_i915_private *dev_priv = dev->dev_private;
6759
6760 /*
6761 * TODO: this bit should only be enabled when really needed, then
6762 * disabled when not needed anymore in order to save power.
6763 */
c2699524 6764 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6765 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6766 I915_READ(SOUTH_DSPCLK_GATE_D) |
6767 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6768
6769 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6770 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6771 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6772 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6773}
6774
7d708ee4
ID		 6775static void lpt_suspend_hw(struct drm_device *dev)
6776{
6777 struct drm_i915_private *dev_priv = dev->dev_private;
6778
c2699524 6779 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6780 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6781
6782 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6783 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6784 }
6785}
6786
450174fe
ID		 6787static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6788 int general_prio_credits,
6789 int high_prio_credits)
6790{
6791 u32 misccpctl;
6792
6793 /* WaTempDisableDOPClkGating:bdw */
6794 misccpctl = I915_READ(GEN7_MISCCPCTL);
6795 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6796
6797 I915_WRITE(GEN8_L3SQCREG1,
6798 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6799 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6800
6801 /*
6802 * Wait at least 100 clocks before re-enabling clock gating.
6803 * See the definition of L3SQCREG1 in BSpec.
6804 */
6805 POSTING_READ(GEN8_L3SQCREG1);
6806 udelay(1);
6807 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6808}
6809
47c2bd97 6810static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6811{
6812 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6813 enum pipe pipe;
1020a5c2 6814
7ad0dbab 6815 ilk_init_lp_watermarks(dev);
50ed5fbd 6816
ab57fff1 6817 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6818 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6819
ab57fff1 6820 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6821 I915_WRITE(CHICKEN_PAR1_1,
6822 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6823
ab57fff1 6824 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6825 for_each_pipe(dev_priv, pipe) {
07d27e20 6826 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6827 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6828 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6829 }
63801f21 6830
ab57fff1
BW		 6831 /* WaVSRefCountFullforceMissDisable:bdw */
6832 /* WaDSRefCountFullforceMissDisable:bdw */
6833 I915_WRITE(GEN7_FF_THREAD_MODE,
6834 I915_READ(GEN7_FF_THREAD_MODE) &
6835 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6836
295e8bb7
VS		 6837 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6838 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6839
6840 /* WaDisableSDEUnitClockGating:bdw */
6841 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6842 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6843
450174fe
ID		 6844 /* WaProgramL3SqcReg1Default:bdw */
6845 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 6846
6d50b065
VS		 6847 /*
6848 * WaGttCachingOffByDefault:bdw
6849 * GTT cache may not work with big pages, so if those
6850 * are ever enabled GTT cache may need to be disabled.
6851 */
6852 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6853
89d6b2b8 6854 lpt_init_clock_gating(dev);
1020a5c2
BW		 6855}
6856
cad2a2d7
ED		 6857static void haswell_init_clock_gating(struct drm_device *dev)
6858{
6859 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6860
017636cc 6861 ilk_init_lp_watermarks(dev);
cad2a2d7 6862
f3fc4884
FJ		 6863 /* L3 caching of data atomics doesn't work -- disable it. */
6864 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6865 I915_WRITE(HSW_ROW_CHICKEN3,
6866 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6867
ecdb4eb7 6868 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6869 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6870 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6871 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6872
e36ea7ff
VS		 6873 /* WaVSRefCountFullforceMissDisable:hsw */
6874 I915_WRITE(GEN7_FF_THREAD_MODE,
6875 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6876
4e04632e
AG		 6877 /* WaDisable_RenderCache_OperationalFlush:hsw */
6878 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6879
fe27c606
CW		 6880 /* enable HiZ Raw Stall Optimization */
6881 I915_WRITE(CACHE_MODE_0_GEN7,
6882 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6883
ecdb4eb7 6884 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6885 I915_WRITE(CACHE_MODE_1,
6886 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6887
a12c4967
VS		 6888 /*
6889 * BSpec recommends 8x4 when MSAA is used,
6890 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6891 *
6892 * Note that PS/WM thread counts depend on the WIZ hashing
6893 * disable bit, which we don't touch here, but it's good
6894 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6895 */
6896 I915_WRITE(GEN7_GT_MODE,
98533251 6897 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6898
94411593
KG		 6899 /* WaSampleCChickenBitEnable:hsw */
6900 I915_WRITE(HALF_SLICE_CHICKEN3,
6901 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6902
ecdb4eb7 6903 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6904 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6905
90a88643
PZ		 6906 /* WaRsPkgCStateDisplayPMReq:hsw */
6907 I915_WRITE(CHICKEN_PAR1_1,
6908 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6909
17a303ec 6910 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6911}
6912
1fa61106 6913static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6914{
6915 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6916 uint32_t snpcr;
6f1d69b0 6917
017636cc 6918 ilk_init_lp_watermarks(dev);
6f1d69b0 6919
231e54f6 6920 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6921
ecdb4eb7 6922 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6923 I915_WRITE(_3D_CHICKEN3,
6924 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6925
ecdb4eb7 6926 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6927 I915_WRITE(IVB_CHICKEN3,
6928 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6929 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6930
ecdb4eb7 6931 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6932 if (IS_IVB_GT1(dev))
6933 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6934 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6935
4e04632e
AG		 6936 /* WaDisable_RenderCache_OperationalFlush:ivb */
6937 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6938
ecdb4eb7 6939 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6940 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6941 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6942
ecdb4eb7 6943 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6944 I915_WRITE(GEN7_L3CNTLREG1,
6945 GEN7_WA_FOR_GEN7_L3_CONTROL);
6946 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6947 GEN7_WA_L3_CHICKEN_MODE);
6948 if (IS_IVB_GT1(dev))
6949 I915_WRITE(GEN7_ROW_CHICKEN2,
6950 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6951 else {
6952 /* must write both registers */
6953 I915_WRITE(GEN7_ROW_CHICKEN2,
6954 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6955 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6956 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6957 }
6f1d69b0 6958
ecdb4eb7 6959 /* WaForceL3Serialization:ivb */
61939d97
JB		 6960 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6961 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6962
1b80a19a 6963 /*
0f846f81 6964 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6965 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6966 */
6967 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6968 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6969
ecdb4eb7 6970 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6971 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6972 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6973 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6974
0e088b8f 6975 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6976
6977 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6978
22721343
CW		 6979 if (0) { /* causes HiZ corruption on ivb:gt1 */
6980 /* enable HiZ Raw Stall Optimization */
6981 I915_WRITE(CACHE_MODE_0_GEN7,
6982 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6983 }
116f2b6d 6984
ecdb4eb7 6985 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6986 I915_WRITE(CACHE_MODE_1,
6987 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6988
a607c1a4
VS		 6989 /*
6990 * BSpec recommends 8x4 when MSAA is used,
6991 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6992 *
6993 * Note that PS/WM thread counts depend on the WIZ hashing
6994 * disable bit, which we don't touch here, but it's good
6995 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6996 */
6997 I915_WRITE(GEN7_GT_MODE,
98533251 6998 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6999
20848223
BW		 7000 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7001 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7002 snpcr |= GEN6_MBC_SNPCR_MED;
7003 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7004
ab5c608b
BW		 7005 if (!HAS_PCH_NOP(dev))
7006 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7007
7008 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7009}
7010
1fa61106 7011static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7012{
7013 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 7014
ecdb4eb7 7015 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7016 I915_WRITE(_3D_CHICKEN3,
7017 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7018
ecdb4eb7 7019 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7020 I915_WRITE(IVB_CHICKEN3,
7021 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7022 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7023
fad7d36e 7024 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7025 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7026 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7027 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7028 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7029
4e04632e
AG		 7030 /* WaDisable_RenderCache_OperationalFlush:vlv */
7031 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7032
ecdb4eb7 7033 /* WaForceL3Serialization:vlv */
61939d97
JB		 7034 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7035 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7036
ecdb4eb7 7037 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7038 I915_WRITE(GEN7_ROW_CHICKEN2,
7039 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7040
ecdb4eb7 7041 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7042 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7043 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7044 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7045
46680e0a
VS		 7046 gen7_setup_fixed_func_scheduler(dev_priv);
7047
3c0edaeb 7048 /*
0f846f81 7049 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7050 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7051 */
7052 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7053 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7054
c98f5062
AG		 7055 /* WaDisableL3Bank2xClockGate:vlv
7056 * Disabling L3 clock gating- MMIO 940c[25] = 1
7057 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7058 I915_WRITE(GEN7_UCGCTL4,
7059 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7060
afd58e79
VS		 7061 /*
7062 * BSpec says this must be set, even though
7063 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7064 */
6b26c86d
DV		 7065 I915_WRITE(CACHE_MODE_1,
7066 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7067
da2518f9
VS		 7068 /*
7069 * BSpec recommends 8x4 when MSAA is used,
7070 * however in practice 16x4 seems fastest.
7071 *
7072 * Note that PS/WM thread counts depend on the WIZ hashing
7073 * disable bit, which we don't touch here, but it's good
7074 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7075 */
7076 I915_WRITE(GEN7_GT_MODE,
7077 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7078
031994ee
VS		 7079 /*
7080 * WaIncreaseL3CreditsForVLVB0:vlv
7081 * This is the hardware default actually.
7082 */
7083 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7084
2d809570 7085 /*
ecdb4eb7 7086 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7087 * Disable clock gating on th GCFG unit to prevent a delay
7088 * in the reporting of vblank events.
7089 */
7a0d1eed 7090 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7091}
7092
a4565da8
VS		 7093static void cherryview_init_clock_gating(struct drm_device *dev)
7094{
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096
232ce337
VS		 7097 /* WaVSRefCountFullforceMissDisable:chv */
7098 /* WaDSRefCountFullforceMissDisable:chv */
7099 I915_WRITE(GEN7_FF_THREAD_MODE,
7100 I915_READ(GEN7_FF_THREAD_MODE) &
7101 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7102
7103 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7104 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7105 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7106
7107 /* WaDisableCSUnitClockGating:chv */
7108 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7109 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7110
7111 /* WaDisableSDEUnitClockGating:chv */
7112 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7114
450174fe
ID		 7115 /*
7116 * WaProgramL3SqcReg1Default:chv
7117 * See gfxspecs/Related Documents/Performance Guide/
7118 * LSQC Setting Recommendations.
7119 */
7120 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7121
6d50b065
VS		 7122 /*
7123 * GTT cache may not work with big pages, so if those
7124 * are ever enabled GTT cache may need to be disabled.
7125 */
7126 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7127}
7128
1fa61106 7129static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7130{
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 uint32_t dspclk_gate;
7133
7134 I915_WRITE(RENCLK_GATE_D1, 0);
7135 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7136 GS_UNIT_CLOCK_GATE_DISABLE |
7137 CL_UNIT_CLOCK_GATE_DISABLE);
7138 I915_WRITE(RAMCLK_GATE_D, 0);
7139 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7140 OVRUNIT_CLOCK_GATE_DISABLE |
7141 OVCUNIT_CLOCK_GATE_DISABLE;
7142 if (IS_GM45(dev))
7143 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7144 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7145
7146 /* WaDisableRenderCachePipelinedFlush */
7147 I915_WRITE(CACHE_MODE_0,
7148 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7149
4e04632e
AG		 7150 /* WaDisable_RenderCache_OperationalFlush:g4x */
7151 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7152
0e088b8f 7153 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7154}
7155
1fa61106 7156static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7157{
7158 struct drm_i915_private *dev_priv = dev->dev_private;
7159
7160 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7161 I915_WRITE(RENCLK_GATE_D2, 0);
7162 I915_WRITE(DSPCLK_GATE_D, 0);
7163 I915_WRITE(RAMCLK_GATE_D, 0);
7164 I915_WRITE16(DEUC, 0);
20f94967
VS		 7165 I915_WRITE(MI_ARB_STATE,
7166 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7167
7168 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7169 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7170}
7171
1fa61106 7172static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7173{
7174 struct drm_i915_private *dev_priv = dev->dev_private;
7175
7176 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7177 I965_RCC_CLOCK_GATE_DISABLE |
7178 I965_RCPB_CLOCK_GATE_DISABLE |
7179 I965_ISC_CLOCK_GATE_DISABLE |
7180 I965_FBC_CLOCK_GATE_DISABLE);
7181 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7182 I915_WRITE(MI_ARB_STATE,
7183 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7184
7185 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7186 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7187}
7188
1fa61106 7189static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7190{
7191 struct drm_i915_private *dev_priv = dev->dev_private;
7192 u32 dstate = I915_READ(D_STATE);
7193
7194 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7195 DSTATE_DOT_CLOCK_GATING;
7196 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7197
7198 if (IS_PINEVIEW(dev))
7199 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7200
7201 /* IIR "flip pending" means done if this bit is set */
7202 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7203
7204 /* interrupts should cause a wake up from C3 */
3299254f 7205 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7206
7207 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7208 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7209
7210 I915_WRITE(MI_ARB_STATE,
7211 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7212}
7213
1fa61106 7214static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7215{
7216 struct drm_i915_private *dev_priv = dev->dev_private;
7217
7218 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7219
7220 /* interrupts should cause a wake up from C3 */
7221 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7222 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7223
7224 I915_WRITE(MEM_MODE,
7225 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7226}
7227
1fa61106 7228static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7229{
7230 struct drm_i915_private *dev_priv = dev->dev_private;
7231
7232 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7233
7234 I915_WRITE(MEM_MODE,
7235 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7236 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7237}
7238
6f1d69b0
ED		 7239void intel_init_clock_gating(struct drm_device *dev)
7240{
7241 struct drm_i915_private *dev_priv = dev->dev_private;
7242
bb400da9 7243 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7244}
7245
7d708ee4
ID		 7246void intel_suspend_hw(struct drm_device *dev)
7247{
7248 if (HAS_PCH_LPT(dev))
7249 lpt_suspend_hw(dev);
7250}
7251
bb400da9
ID		 7252static void nop_init_clock_gating(struct drm_device *dev)
7253{
7254 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7255}
7256
7257/**
7258 * intel_init_clock_gating_hooks - setup the clock gating hooks
7259 * @dev_priv: device private
7260 *
7261 * Setup the hooks that configure which clocks of a given platform can be
7262 * gated and also apply various GT and display specific workarounds for these
7263 * platforms. Note that some GT specific workarounds are applied separately
7264 * when GPU contexts or batchbuffers start their execution.
7265 */
7266void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7267{
7268 if (IS_SKYLAKE(dev_priv))
7269 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7270 else if (IS_KABYLAKE(dev_priv))
7271 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7272 else if (IS_BROXTON(dev_priv))
7273 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7274 else if (IS_BROADWELL(dev_priv))
7275 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7276 else if (IS_CHERRYVIEW(dev_priv))
7277 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7278 else if (IS_HASWELL(dev_priv))
7279 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7280 else if (IS_IVYBRIDGE(dev_priv))
7281 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7282 else if (IS_VALLEYVIEW(dev_priv))
7283 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7284 else if (IS_GEN6(dev_priv))
7285 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7286 else if (IS_GEN5(dev_priv))
7287 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7288 else if (IS_G4X(dev_priv))
7289 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7290 else if (IS_CRESTLINE(dev_priv))
7291 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7292 else if (IS_BROADWATER(dev_priv))
7293 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7294 else if (IS_GEN3(dev_priv))
7295 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7296 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7297 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7298 else if (IS_GEN2(dev_priv))
7299 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7300 else {
7301 MISSING_CASE(INTEL_DEVID(dev_priv));
7302 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7303 }
7304}
7305
1fa61106
ED		 7306/* Set up chip specific power management-related functions */
7307void intel_init_pm(struct drm_device *dev)
7308{
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310
7ff0ebcc 7311 intel_fbc_init(dev_priv);
1fa61106 7312
c921aba8
DV		 7313 /* For cxsr */
7314 if (IS_PINEVIEW(dev))
7315 i915_pineview_get_mem_freq(dev);
7316 else if (IS_GEN5(dev))
7317 i915_ironlake_get_mem_freq(dev);
7318
1fa61106 7319 /* For FIFO watermark updates */
f5ed50cb 7320 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7321 skl_setup_wm_latency(dev);
2d41c0b5 7322 dev_priv->display.update_wm = skl_update_wm;
98d39494 7323 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7324 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7325 ilk_setup_wm_latency(dev);
53615a5e 7326
bd602544
VS		 7327 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7328 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7329 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7330 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7331 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7332 dev_priv->display.compute_intermediate_wm =
7333 ilk_compute_intermediate_wm;
7334 dev_priv->display.initial_watermarks =
7335 ilk_initial_watermarks;
7336 dev_priv->display.optimize_watermarks =
7337 ilk_optimize_watermarks;
bd602544
VS		 7338 } else {
7339 DRM_DEBUG_KMS("Failed to read display plane latency. "
7340 "Disable CxSR\n");
7341 }
a4565da8 7342 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7343 vlv_setup_wm_latency(dev);
262cd2e1 7344 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7345 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7346 vlv_setup_wm_latency(dev);
26e1fe4f 7347 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7348 } else if (IS_PINEVIEW(dev)) {
7349 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7350 dev_priv->is_ddr3,
7351 dev_priv->fsb_freq,
7352 dev_priv->mem_freq)) {
7353 DRM_INFO("failed to find known CxSR latency "
7354 "(found ddr%s fsb freq %d, mem freq %d), "
7355 "disabling CxSR\n",
7356 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7357 dev_priv->fsb_freq, dev_priv->mem_freq);
7358 /* Disable CxSR and never update its watermark again */
5209b1f4 7359 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7360 dev_priv->display.update_wm = NULL;
7361 } else
7362 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7363 } else if (IS_G4X(dev)) {
7364 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7365 } else if (IS_GEN4(dev)) {
7366 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7367 } else if (IS_GEN3(dev)) {
7368 dev_priv->display.update_wm = i9xx_update_wm;
7369 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7370 } else if (IS_GEN2(dev)) {
7371 if (INTEL_INFO(dev)->num_pipes == 1) {
7372 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7373 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7374 } else {
7375 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7376 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7377 }
feb56b93
DV		 7378 } else {
7379 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7380 }
7381}
7382
151a49d0 7383int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7384{
4fc688ce 7385 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7386
7387 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7388 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7389 return -EAGAIN;
7390 }
7391
7392 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7393 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7394 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7395
7396 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7397 500)) {
7398 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7399 return -ETIMEDOUT;
7400 }
7401
7402 *val = I915_READ(GEN6_PCODE_DATA);
7403 I915_WRITE(GEN6_PCODE_DATA, 0);
7404
7405 return 0;
7406}
7407
151a49d0 7408int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7409{
4fc688ce 7410 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7411
7412 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7413 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7414 return -EAGAIN;
7415 }
7416
7417 I915_WRITE(GEN6_PCODE_DATA, val);
7418 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7419
7420 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7421 500)) {
7422 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7423 return -ETIMEDOUT;
7424 }
7425
7426 I915_WRITE(GEN6_PCODE_DATA, 0);
7427
7428 return 0;
7429}
a0e4e199 7430
dd06f88c
VS		 7431static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7432{
c30fec65
VS		 7433 /*
7434 * N = val - 0xb7
7435 * Slow = Fast = GPLL ref * N
7436 */
7437 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7438}
7439
b55dd647 7440static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7441{
c30fec65 7442 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7443}
7444
b55dd647 7445static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7446{
c30fec65
VS		 7447 /*
7448 * N = val / 2
7449 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7450 */
7451 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7452}
7453
b55dd647 7454static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7455{
1c14762d 7456 /* CHV needs even values */
c30fec65 7457 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7458}
7459
616bc820 7460int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7461{
2d1fe073 7462 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7463 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7464 GEN9_FREQ_SCALER);
2d1fe073 7465 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7466 return chv_gpu_freq(dev_priv, val);
2d1fe073 7467 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7468 return byt_gpu_freq(dev_priv, val);
7469 else
7470 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7471}
7472
616bc820
VS		 7473int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7474{
2d1fe073 7475 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7476 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7477 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7478 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7479 return chv_freq_opcode(dev_priv, val);
2d1fe073 7480 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7481 return byt_freq_opcode(dev_priv, val);
7482 else
500a3d2e 7483 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7484}
22b1b2f8 7485
6ad790c0
CW		 7486struct request_boost {
7487 struct work_struct work;
eed29a5b 7488 struct drm_i915_gem_request *req;
6ad790c0
CW		 7489};
7490
7491static void __intel_rps_boost_work(struct work_struct *work)
7492{
7493 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7494 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7495
e61b9958 7496 if (!i915_gem_request_completed(req, true))
c033666a 7497 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7498
73db04cf 7499 i915_gem_request_unreference(req);
6ad790c0
CW		 7500 kfree(boost);
7501}
7502
91d14251 7503void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7504{
7505 struct request_boost *boost;
7506
91d14251 7507 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7508 return;
7509
e61b9958
CW		 7510 if (i915_gem_request_completed(req, true))
7511 return;
7512
6ad790c0
CW		 7513 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7514 if (boost == NULL)
7515 return;
7516
eed29a5b
DV		 7517 i915_gem_request_reference(req);
7518 boost->req = req;
6ad790c0
CW		 7519
7520 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7521 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7522}
7523
f742a552 7524void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7525{
7526 struct drm_i915_private *dev_priv = dev->dev_private;
7527
f742a552 7528 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7529 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7530
907b28c5
CW		 7531 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7532 intel_gen6_powersave_work);
1854d5ca 7533 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7534 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7535 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7536
33688d95 7537 dev_priv->pm.suspended = false;
1f814dac 7538 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7539 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7540}
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