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drm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 95 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
7f2cf220 100 int i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112
113 /* Clear old tags */
114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
115 I915_WRITE(FBC_TAG + (i * 4), 0);
116
159f9875
VS		 117 if (IS_GEN4(dev)) {
118 u32 fbc_ctl2;
119
120 /* Set it up... */
121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
7f2cf220 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
159f9875
VS		 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
125 }
85208be0
ED		 126
127 /* enable it... */
993495ae
VS		 128 fbc_ctl = I915_READ(FBC_CONTROL);
129 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
130 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 131 if (IS_I945GM(dev))
132 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
133 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 134 fbc_ctl |= obj->fence_reg;
135 I915_WRITE(FBC_CONTROL, fbc_ctl);
136
5cd5410e 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
84f44ce7 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 139}
140
1fa61106 141static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 142{
143 struct drm_i915_private *dev_priv = dev->dev_private;
144
145 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
146}
147
993495ae 148static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 149{
150 struct drm_device *dev = crtc->dev;
151 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 152 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
154 struct drm_i915_gem_object *obj = intel_fb->obj;
155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 156 u32 dpfc_ctl;
157
3fa2e0ee
VS		 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
85208be0 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
85208be0 164
85208be0
ED		 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
166
167 /* enable it... */
fe74c1a5 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
85208be0 169
84f44ce7 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 171}
172
1fa61106 173static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 174{
175 struct drm_i915_private *dev_priv = dev->dev_private;
176 u32 dpfc_ctl;
177
178 /* Disable compression */
179 dpfc_ctl = I915_READ(DPFC_CONTROL);
180 if (dpfc_ctl & DPFC_CTL_EN) {
181 dpfc_ctl &= ~DPFC_CTL_EN;
182 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
183
184 DRM_DEBUG_KMS("disabled FBC\n");
185 }
186}
187
1fa61106 188static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191
192 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
193}
194
195static void sandybridge_blit_fbc_update(struct drm_device *dev)
196{
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 u32 blt_ecoskpd;
199
200 /* Make sure blitter notifies FBC of writes */
940aece4
D		 201
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 205
85208be0
ED		 206 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
207 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
208 GEN6_BLITTER_LOCK_SHIFT;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
210 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
212 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
213 GEN6_BLITTER_LOCK_SHIFT);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 216
940aece4 217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 218}
219
993495ae 220static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 221{
222 struct drm_device *dev = crtc->dev;
223 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 224 struct drm_framebuffer *fb = crtc->primary->fb;
85208be0
ED		 225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
226 struct drm_i915_gem_object *obj = intel_fb->obj;
227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85208be0
ED		 228 u32 dpfc_ctl;
229
46f3dab9 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
3fa2e0ee
VS		 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 else
234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0 238
85208be0 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 241 /* enable it... */
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
243
244 if (IS_GEN6(dev)) {
245 I915_WRITE(SNB_DPFC_CTL_SA,
246 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
248 sandybridge_blit_fbc_update(dev);
249 }
250
84f44ce7 251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 252}
253
1fa61106 254static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 255{
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 u32 dpfc_ctl;
258
259 /* Disable compression */
260 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
261 if (dpfc_ctl & DPFC_CTL_EN) {
262 dpfc_ctl &= ~DPFC_CTL_EN;
263 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
264
265 DRM_DEBUG_KMS("disabled FBC\n");
266 }
267}
268
1fa61106 269static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 270{
271 struct drm_i915_private *dev_priv = dev->dev_private;
272
273 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
274}
275
993495ae 276static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 277{
278 struct drm_device *dev = crtc->dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 280 struct drm_framebuffer *fb = crtc->primary->fb;
abe959c7
RV		 281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
282 struct drm_i915_gem_object *obj = intel_fb->obj;
283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3fa2e0ee 284 u32 dpfc_ctl;
abe959c7 285
3fa2e0ee
VS		 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
292
293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
abe959c7 294
891348b2 295 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
2adb6db8
VS		 297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
299 ILK_FBCQ_DIS);
28554164 300 } else {
2adb6db8 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
8f670bb1
VS		 302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
304 HSW_FBCQ_DIS);
891348b2 305 }
b74ea102 306
abe959c7
RV		 307 I915_WRITE(SNB_DPFC_CTL_SA,
308 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
310
311 sandybridge_blit_fbc_update(dev);
312
b19870ee 313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 314}
315
85208be0
ED		 316bool intel_fbc_enabled(struct drm_device *dev)
317{
318 struct drm_i915_private *dev_priv = dev->dev_private;
319
320 if (!dev_priv->display.fbc_enabled)
321 return false;
322
323 return dev_priv->display.fbc_enabled(dev);
324}
325
326static void intel_fbc_work_fn(struct work_struct *__work)
327{
328 struct intel_fbc_work *work =
329 container_of(to_delayed_work(__work),
330 struct intel_fbc_work, work);
331 struct drm_device *dev = work->crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333
334 mutex_lock(&dev->struct_mutex);
5c3fe8b0 335 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 336 /* Double check that we haven't switched fb without cancelling
337 * the prior work.
338 */
f4510a27 339 if (work->crtc->primary->fb == work->fb) {
993495ae 340 dev_priv->display.enable_fbc(work->crtc);
85208be0 341
5c3fe8b0 342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
f4510a27 343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
5c3fe8b0 344 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 345 }
346
5c3fe8b0 347 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 348 }
349 mutex_unlock(&dev->struct_mutex);
350
351 kfree(work);
352}
353
354static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
355{
5c3fe8b0 356 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 357 return;
358
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
360
361 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 363 * entirely asynchronously.
364 */
5c3fe8b0 365 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 366 /* tasklet was killed before being run, clean up */
5c3fe8b0 367 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 368
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
372 * necessary to run.
373 */
5c3fe8b0 374 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 375}
376
993495ae 377static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 378{
379 struct intel_fbc_work *work;
380 struct drm_device *dev = crtc->dev;
381 struct drm_i915_private *dev_priv = dev->dev_private;
382
383 if (!dev_priv->display.enable_fbc)
384 return;
385
386 intel_cancel_fbc_work(dev_priv);
387
b14c5679 388 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 389 if (work == NULL) {
6cdcb5e7 390 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 391 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 392 return;
393 }
394
395 work->crtc = crtc;
f4510a27 396 work->fb = crtc->primary->fb;
85208be0
ED		 397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
398
5c3fe8b0 399 dev_priv->fbc.fbc_work = work;
85208be0 400
85208be0
ED		 401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
406 *
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
7457d617
DL		 411 *
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 413 */
414 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
415}
416
417void intel_disable_fbc(struct drm_device *dev)
418{
419 struct drm_i915_private *dev_priv = dev->dev_private;
420
421 intel_cancel_fbc_work(dev_priv);
422
423 if (!dev_priv->display.disable_fbc)
424 return;
425
426 dev_priv->display.disable_fbc(dev);
5c3fe8b0 427 dev_priv->fbc.plane = -1;
85208be0
ED		 428}
429
29ebf90f
CW		 430static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
431 enum no_fbc_reason reason)
432{
433 if (dev_priv->fbc.no_fbc_reason == reason)
434 return false;
435
436 dev_priv->fbc.no_fbc_reason = reason;
437 return true;
438}
439
85208be0
ED		 440/**
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
443 *
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
449 * - no dual wide
f85da868 450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 451 *
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
455 * stolen memory.
456 *
457 * We need to enable/disable FBC on a global basis.
458 */
459void intel_update_fbc(struct drm_device *dev)
460{
461 struct drm_i915_private *dev_priv = dev->dev_private;
462 struct drm_crtc *crtc = NULL, *tmp_crtc;
463 struct intel_crtc *intel_crtc;
464 struct drm_framebuffer *fb;
465 struct intel_framebuffer *intel_fb;
466 struct drm_i915_gem_object *obj;
ef644fda 467 const struct drm_display_mode *adjusted_mode;
37327abd 468 unsigned int max_width, max_height;
85208be0 469
3a77c4c4 470 if (!HAS_FBC(dev)) {
29ebf90f 471 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 472 return;
29ebf90f 473 }
85208be0 474
d330a953 475 if (!i915.powersave) {
29ebf90f
CW		 476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 478 return;
29ebf90f 479 }
85208be0
ED		 480
481 /*
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
489 */
70e1e0ec 490 for_each_crtc(dev, tmp_crtc) {
3490ea5d 491 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 492 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 493 if (crtc) {
29ebf90f
CW		 494 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 496 goto out_disable;
497 }
498 crtc = tmp_crtc;
499 }
500 }
501
f4510a27 502 if (!crtc || crtc->primary->fb == NULL) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
504 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 505 goto out_disable;
506 }
507
508 intel_crtc = to_intel_crtc(crtc);
f4510a27 509 fb = crtc->primary->fb;
85208be0
ED		 510 intel_fb = to_intel_framebuffer(fb);
511 obj = intel_fb->obj;
ef644fda 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 513
d330a953 514 if (i915.enable_fbc < 0 &&
8a5729a3 515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 518 goto out_disable;
85208be0 519 }
d330a953 520 if (!i915.enable_fbc) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 523 goto out_disable;
524 }
ef644fda
VS		 525 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
526 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 527 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
529 "disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
f85da868
PZ		 532
533 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 534 max_width = 4096;
535 max_height = 2048;
f85da868 536 } else {
37327abd
VS		 537 max_width = 2048;
538 max_height = 1536;
f85da868 539 }
37327abd
VS		 540 if (intel_crtc->config.pipe_src_w > max_width ||
541 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 542 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 544 goto out_disable;
545 }
8f94d24b 546 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
c5a44aa0 547 intel_crtc->plane != PLANE_A) {
29ebf90f 548 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 550 goto out_disable;
551 }
552
553 /* The use of a CPU fence is mandatory in order to detect writes
554 * by the CPU to the scanout and trigger updates to the FBC.
555 */
556 if (obj->tiling_mode != I915_TILING_X ||
557 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 558 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
559 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 560 goto out_disable;
561 }
562
563 /* If the kernel debugger is active, always disable compression */
564 if (in_dbg_master())
565 goto out_disable;
566
11be49eb 567 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 568 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
569 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 570 goto out_disable;
571 }
572
85208be0
ED		 573 /* If the scanout has not changed, don't modify the FBC settings.
574 * Note that we make the fundamental assumption that the fb->obj
575 * cannot be unpinned (and have its GTT offset and fence revoked)
576 * without first being decoupled from the scanout and FBC disabled.
577 */
5c3fe8b0
BW		 578 if (dev_priv->fbc.plane == intel_crtc->plane &&
579 dev_priv->fbc.fb_id == fb->base.id &&
580 dev_priv->fbc.y == crtc->y)
85208be0
ED		 581 return;
582
583 if (intel_fbc_enabled(dev)) {
584 /* We update FBC along two paths, after changing fb/crtc
585 * configuration (modeswitching) and after page-flipping
586 * finishes. For the latter, we know that not only did
587 * we disable the FBC at the start of the page-flip
588 * sequence, but also more than one vblank has passed.
589 *
590 * For the former case of modeswitching, it is possible
591 * to switch between two FBC valid configurations
592 * instantaneously so we do need to disable the FBC
593 * before we can modify its control registers. We also
594 * have to wait for the next vblank for that to take
595 * effect. However, since we delay enabling FBC we can
596 * assume that a vblank has passed since disabling and
597 * that we can safely alter the registers in the deferred
598 * callback.
599 *
600 * In the scenario that we go from a valid to invalid
601 * and then back to valid FBC configuration we have
602 * no strict enforcement that a vblank occurred since
603 * disabling the FBC. However, along all current pipe
604 * disabling paths we do need to wait for a vblank at
605 * some point. And we wait before enabling FBC anyway.
606 */
607 DRM_DEBUG_KMS("disabling active FBC for update\n");
608 intel_disable_fbc(dev);
609 }
610
993495ae 611 intel_enable_fbc(crtc);
29ebf90f 612 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 613 return;
614
615out_disable:
616 /* Multiple disables should be harmless */
617 if (intel_fbc_enabled(dev)) {
618 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
619 intel_disable_fbc(dev);
620 }
11be49eb 621 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 622}
623
c921aba8
DV		 624static void i915_pineview_get_mem_freq(struct drm_device *dev)
625{
50227e1c 626 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 627 u32 tmp;
628
629 tmp = I915_READ(CLKCFG);
630
631 switch (tmp & CLKCFG_FSB_MASK) {
632 case CLKCFG_FSB_533:
633 dev_priv->fsb_freq = 533; /* 133*4 */
634 break;
635 case CLKCFG_FSB_800:
636 dev_priv->fsb_freq = 800; /* 200*4 */
637 break;
638 case CLKCFG_FSB_667:
639 dev_priv->fsb_freq = 667; /* 167*4 */
640 break;
641 case CLKCFG_FSB_400:
642 dev_priv->fsb_freq = 400; /* 100*4 */
643 break;
644 }
645
646 switch (tmp & CLKCFG_MEM_MASK) {
647 case CLKCFG_MEM_533:
648 dev_priv->mem_freq = 533;
649 break;
650 case CLKCFG_MEM_667:
651 dev_priv->mem_freq = 667;
652 break;
653 case CLKCFG_MEM_800:
654 dev_priv->mem_freq = 800;
655 break;
656 }
657
658 /* detect pineview DDR3 setting */
659 tmp = I915_READ(CSHRDDR3CTL);
660 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
661}
662
663static void i915_ironlake_get_mem_freq(struct drm_device *dev)
664{
50227e1c 665 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 666 u16 ddrpll, csipll;
667
668 ddrpll = I915_READ16(DDRMPLL1);
669 csipll = I915_READ16(CSIPLL0);
670
671 switch (ddrpll & 0xff) {
672 case 0xc:
673 dev_priv->mem_freq = 800;
674 break;
675 case 0x10:
676 dev_priv->mem_freq = 1066;
677 break;
678 case 0x14:
679 dev_priv->mem_freq = 1333;
680 break;
681 case 0x18:
682 dev_priv->mem_freq = 1600;
683 break;
684 default:
685 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
686 ddrpll & 0xff);
687 dev_priv->mem_freq = 0;
688 break;
689 }
690
20e4d407 691 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 692
693 switch (csipll & 0x3ff) {
694 case 0x00c:
695 dev_priv->fsb_freq = 3200;
696 break;
697 case 0x00e:
698 dev_priv->fsb_freq = 3733;
699 break;
700 case 0x010:
701 dev_priv->fsb_freq = 4266;
702 break;
703 case 0x012:
704 dev_priv->fsb_freq = 4800;
705 break;
706 case 0x014:
707 dev_priv->fsb_freq = 5333;
708 break;
709 case 0x016:
710 dev_priv->fsb_freq = 5866;
711 break;
712 case 0x018:
713 dev_priv->fsb_freq = 6400;
714 break;
715 default:
716 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
717 csipll & 0x3ff);
718 dev_priv->fsb_freq = 0;
719 break;
720 }
721
722 if (dev_priv->fsb_freq == 3200) {
20e4d407 723 dev_priv->ips.c_m = 0;
c921aba8 724 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 725 dev_priv->ips.c_m = 1;
c921aba8 726 } else {
20e4d407 727 dev_priv->ips.c_m = 2;
c921aba8
DV		 728 }
729}
730
b445e3b0
ED		 731static const struct cxsr_latency cxsr_latency_table[] = {
732 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
733 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
734 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
735 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
736 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
737
738 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
739 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
740 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
741 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
742 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
743
744 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
745 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
746 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
747 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
748 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
749
750 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
751 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
752 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
753 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
754 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
755
756 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
757 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
758 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
759 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
760 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
761
762 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
763 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
764 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
765 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
766 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
767};
768
63c62275 769static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 770 int is_ddr3,
771 int fsb,
772 int mem)
773{
774 const struct cxsr_latency *latency;
775 int i;
776
777 if (fsb == 0 || mem == 0)
778 return NULL;
779
780 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
781 latency = &cxsr_latency_table[i];
782 if (is_desktop == latency->is_desktop &&
783 is_ddr3 == latency->is_ddr3 &&
784 fsb == latency->fsb_freq && mem == latency->mem_freq)
785 return latency;
786 }
787
788 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
789
790 return NULL;
791}
792
1fa61106 793static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
796
797 /* deactivate cxsr */
798 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
799}
800
801/*
802 * Latency for FIFO fetches is dependent on several factors:
803 * - memory configuration (speed, channels)
804 * - chipset
805 * - current MCH state
806 * It can be fairly high in some situations, so here we assume a fairly
807 * pessimal value. It's a tradeoff between extra memory fetches (if we
808 * set this value too high, the FIFO will fetch frequently to stay full)
809 * and power consumption (set it too low to save power and we might see
810 * FIFO underruns and display "flicker").
811 *
812 * A value of 5us seems to be a good balance; safe for very low end
813 * platforms but not overly aggressive on lower latency configs.
814 */
815static const int latency_ns = 5000;
816
1fa61106 817static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 818{
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 uint32_t dsparb = I915_READ(DSPARB);
821 int size;
822
823 size = dsparb & 0x7f;
824 if (plane)
825 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
826
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
828 plane ? "B" : "A", size);
829
830 return size;
831}
832
feb56b93 833static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 834{
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 uint32_t dsparb = I915_READ(DSPARB);
837 int size;
838
839 size = dsparb & 0x1ff;
840 if (plane)
841 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
842 size >>= 1; /* Convert to cachelines */
843
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
845 plane ? "B" : "A", size);
846
847 return size;
848}
849
1fa61106 850static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
853 uint32_t dsparb = I915_READ(DSPARB);
854 int size;
855
856 size = dsparb & 0x7f;
857 size >>= 2; /* Convert to cachelines */
858
859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
860 plane ? "B" : "A",
861 size);
862
863 return size;
864}
865
b445e3b0
ED		 866/* Pineview has different values for various configs */
867static const struct intel_watermark_params pineview_display_wm = {
868 PINEVIEW_DISPLAY_FIFO,
869 PINEVIEW_MAX_WM,
870 PINEVIEW_DFT_WM,
871 PINEVIEW_GUARD_WM,
872 PINEVIEW_FIFO_LINE_SIZE
873};
874static const struct intel_watermark_params pineview_display_hplloff_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_HPLLOFF_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_cursor_wm = {
882 PINEVIEW_CURSOR_FIFO,
883 PINEVIEW_CURSOR_MAX_WM,
884 PINEVIEW_CURSOR_DFT_WM,
885 PINEVIEW_CURSOR_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE,
887};
888static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params g4x_wm_info = {
896 G4X_FIFO_SIZE,
897 G4X_MAX_WM,
898 G4X_MAX_WM,
899 2,
900 G4X_FIFO_LINE_SIZE,
901};
902static const struct intel_watermark_params g4x_cursor_wm_info = {
903 I965_CURSOR_FIFO,
904 I965_CURSOR_MAX_WM,
905 I965_CURSOR_DFT_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params valleyview_wm_info = {
910 VALLEYVIEW_FIFO_SIZE,
911 VALLEYVIEW_MAX_WM,
912 VALLEYVIEW_MAX_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_cursor_wm_info = {
917 I965_CURSOR_FIFO,
918 VALLEYVIEW_CURSOR_MAX_WM,
919 I965_CURSOR_DFT_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params i965_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 I965_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 I915_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i945_wm_info = {
931 I945_FIFO_SIZE,
932 I915_MAX_WM,
933 1,
934 2,
935 I915_FIFO_LINE_SIZE
936};
937static const struct intel_watermark_params i915_wm_info = {
938 I915_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
feb56b93 944static const struct intel_watermark_params i830_wm_info = {
b445e3b0
ED		 945 I855GM_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I830_FIFO_LINE_SIZE
950};
feb56b93 951static const struct intel_watermark_params i845_wm_info = {
b445e3b0
ED		 952 I830_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958
b445e3b0
ED		 959/**
960 * intel_calculate_wm - calculate watermark level
961 * @clock_in_khz: pixel clock
962 * @wm: chip FIFO params
963 * @pixel_size: display pixel size
964 * @latency_ns: memory latency for the platform
965 *
966 * Calculate the watermark level (the level at which the display plane will
967 * start fetching from memory again). Each chip has a different display
968 * FIFO size and allocation, so the caller needs to figure that out and pass
969 * in the correct intel_watermark_params structure.
970 *
971 * As the pixel clock runs, the FIFO will be drained at a rate that depends
972 * on the pixel size. When it reaches the watermark level, it'll start
973 * fetching FIFO line sized based chunks from memory until the FIFO fills
974 * past the watermark point. If the FIFO drains completely, a FIFO underrun
975 * will occur, and a display engine hang could result.
976 */
977static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
978 const struct intel_watermark_params *wm,
979 int fifo_size,
980 int pixel_size,
981 unsigned long latency_ns)
982{
983 long entries_required, wm_size;
984
985 /*
986 * Note: we need to make sure we don't overflow for various clock &
987 * latency values.
988 * clocks go from a few thousand to several hundred thousand.
989 * latency is usually a few thousand
990 */
991 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
992 1000;
993 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
994
995 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
996
997 wm_size = fifo_size - (entries_required + wm->guard_size);
998
999 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1000
1001 /* Don't promote wm_size to unsigned... */
1002 if (wm_size > (long)wm->max_wm)
1003 wm_size = wm->max_wm;
1004 if (wm_size <= 0)
1005 wm_size = wm->default_wm;
1006 return wm_size;
1007}
1008
1009static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1010{
1011 struct drm_crtc *crtc, *enabled = NULL;
1012
70e1e0ec 1013 for_each_crtc(dev, crtc) {
3490ea5d 1014 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1015 if (enabled)
1016 return NULL;
1017 enabled = crtc;
1018 }
1019 }
1020
1021 return enabled;
1022}
1023
46ba614c 1024static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1025{
46ba614c 1026 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 struct drm_crtc *crtc;
1029 const struct cxsr_latency *latency;
1030 u32 reg;
1031 unsigned long wm;
1032
1033 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1034 dev_priv->fsb_freq, dev_priv->mem_freq);
1035 if (!latency) {
1036 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037 pineview_disable_cxsr(dev);
1038 return;
1039 }
1040
1041 crtc = single_enabled_crtc(dev);
1042 if (crtc) {
241bfc38 1043 const struct drm_display_mode *adjusted_mode;
f4510a27 1044 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
241bfc38
DL		 1045 int clock;
1046
1047 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1048 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1049
1050 /* Display SR */
1051 wm = intel_calculate_wm(clock, &pineview_display_wm,
1052 pineview_display_wm.fifo_size,
1053 pixel_size, latency->display_sr);
1054 reg = I915_READ(DSPFW1);
1055 reg &= ~DSPFW_SR_MASK;
1056 reg |= wm << DSPFW_SR_SHIFT;
1057 I915_WRITE(DSPFW1, reg);
1058 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1059
1060 /* cursor SR */
1061 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1062 pineview_display_wm.fifo_size,
1063 pixel_size, latency->cursor_sr);
1064 reg = I915_READ(DSPFW3);
1065 reg &= ~DSPFW_CURSOR_SR_MASK;
1066 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1067 I915_WRITE(DSPFW3, reg);
1068
1069 /* Display HPLL off SR */
1070 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1071 pineview_display_hplloff_wm.fifo_size,
1072 pixel_size, latency->display_hpll_disable);
1073 reg = I915_READ(DSPFW3);
1074 reg &= ~DSPFW_HPLL_SR_MASK;
1075 reg |= wm & DSPFW_HPLL_SR_MASK;
1076 I915_WRITE(DSPFW3, reg);
1077
1078 /* cursor HPLL off SR */
1079 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1080 pineview_display_hplloff_wm.fifo_size,
1081 pixel_size, latency->cursor_hpll_disable);
1082 reg = I915_READ(DSPFW3);
1083 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1084 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1085 I915_WRITE(DSPFW3, reg);
1086 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1087
1088 /* activate cxsr */
1089 I915_WRITE(DSPFW3,
1090 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1091 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1092 } else {
1093 pineview_disable_cxsr(dev);
1094 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1095 }
1096}
1097
1098static bool g4x_compute_wm0(struct drm_device *dev,
1099 int plane,
1100 const struct intel_watermark_params *display,
1101 int display_latency_ns,
1102 const struct intel_watermark_params *cursor,
1103 int cursor_latency_ns,
1104 int *plane_wm,
1105 int *cursor_wm)
1106{
1107 struct drm_crtc *crtc;
4fe8590a 1108 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1109 int htotal, hdisplay, clock, pixel_size;
1110 int line_time_us, line_count;
1111 int entries, tlb_miss;
1112
1113 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1114 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1115 *cursor_wm = cursor->guard_size;
1116 *plane_wm = display->guard_size;
1117 return false;
1118 }
1119
4fe8590a 1120 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1121 clock = adjusted_mode->crtc_clock;
fec8cba3 1122 htotal = adjusted_mode->crtc_htotal;
37327abd 1123 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1124 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1125
1126 /* Use the small buffer method to calculate plane watermark */
1127 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1128 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1129 if (tlb_miss > 0)
1130 entries += tlb_miss;
1131 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1132 *plane_wm = entries + display->guard_size;
1133 if (*plane_wm > (int)display->max_wm)
1134 *plane_wm = display->max_wm;
1135
1136 /* Use the large buffer method to calculate cursor watermark */
922044c9 1137 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
7bb836dd 1139 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
b445e3b0
ED		 1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1141 if (tlb_miss > 0)
1142 entries += tlb_miss;
1143 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1144 *cursor_wm = entries + cursor->guard_size;
1145 if (*cursor_wm > (int)cursor->max_wm)
1146 *cursor_wm = (int)cursor->max_wm;
1147
1148 return true;
1149}
1150
1151/*
1152 * Check the wm result.
1153 *
1154 * If any calculated watermark values is larger than the maximum value that
1155 * can be programmed into the associated watermark register, that watermark
1156 * must be disabled.
1157 */
1158static bool g4x_check_srwm(struct drm_device *dev,
1159 int display_wm, int cursor_wm,
1160 const struct intel_watermark_params *display,
1161 const struct intel_watermark_params *cursor)
1162{
1163 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164 display_wm, cursor_wm);
1165
1166 if (display_wm > display->max_wm) {
1167 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168 display_wm, display->max_wm);
1169 return false;
1170 }
1171
1172 if (cursor_wm > cursor->max_wm) {
1173 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174 cursor_wm, cursor->max_wm);
1175 return false;
1176 }
1177
1178 if (!(display_wm || cursor_wm)) {
1179 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1180 return false;
1181 }
1182
1183 return true;
1184}
1185
1186static bool g4x_compute_srwm(struct drm_device *dev,
1187 int plane,
1188 int latency_ns,
1189 const struct intel_watermark_params *display,
1190 const struct intel_watermark_params *cursor,
1191 int *display_wm, int *cursor_wm)
1192{
1193 struct drm_crtc *crtc;
4fe8590a 1194 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1195 int hdisplay, htotal, pixel_size, clock;
1196 unsigned long line_time_us;
1197 int line_count, line_size;
1198 int small, large;
1199 int entries;
1200
1201 if (!latency_ns) {
1202 *display_wm = *cursor_wm = 0;
1203 return false;
1204 }
1205
1206 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1207 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1208 clock = adjusted_mode->crtc_clock;
fec8cba3 1209 htotal = adjusted_mode->crtc_htotal;
37327abd 1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1211 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0 1212
922044c9 1213 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1215 line_size = hdisplay * pixel_size;
1216
1217 /* Use the minimum of the small and large buffer method for primary */
1218 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1219 large = line_count * line_size;
1220
1221 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1222 *display_wm = entries + display->guard_size;
1223
1224 /* calculate the self-refresh watermark for display cursor */
7bb836dd 1225 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1226 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1227 *cursor_wm = entries + cursor->guard_size;
1228
1229 return g4x_check_srwm(dev,
1230 *display_wm, *cursor_wm,
1231 display, cursor);
1232}
1233
1234static bool vlv_compute_drain_latency(struct drm_device *dev,
1235 int plane,
1236 int *plane_prec_mult,
1237 int *plane_dl,
1238 int *cursor_prec_mult,
1239 int *cursor_dl)
1240{
1241 struct drm_crtc *crtc;
1242 int clock, pixel_size;
1243 int entries;
1244
1245 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1246 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1247 return false;
1248
241bfc38 1249 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
f4510a27 1250 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
b445e3b0
ED		 1251
1252 entries = (clock / 1000) * pixel_size;
1253 *plane_prec_mult = (entries > 256) ?
1254 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1255 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1256 pixel_size);
1257
1258 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1259 *cursor_prec_mult = (entries > 256) ?
1260 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1261 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1262
1263 return true;
1264}
1265
1266/*
1267 * Update drain latency registers of memory arbiter
1268 *
1269 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270 * to be programmed. Each plane has a drain latency multiplier and a drain
1271 * latency value.
1272 */
1273
1274static void vlv_update_drain_latency(struct drm_device *dev)
1275{
1276 struct drm_i915_private *dev_priv = dev->dev_private;
1277 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1278 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1279 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1280 either 16 or 32 */
1281
1282 /* For plane A, Cursor A */
1283 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1284 &cursor_prec_mult, &cursora_dl)) {
1285 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1287 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1288 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1289
1290 I915_WRITE(VLV_DDL1, cursora_prec |
1291 (cursora_dl << DDL_CURSORA_SHIFT) |
1292 planea_prec | planea_dl);
1293 }
1294
1295 /* For plane B, Cursor B */
1296 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1297 &cursor_prec_mult, &cursorb_dl)) {
1298 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1300 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1301 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1302
1303 I915_WRITE(VLV_DDL2, cursorb_prec |
1304 (cursorb_dl << DDL_CURSORB_SHIFT) |
1305 planeb_prec | planeb_dl);
1306 }
1307}
1308
1309#define single_plane_enabled(mask) is_power_of_2(mask)
1310
46ba614c 1311static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1312{
46ba614c 1313 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1314 static const int sr_latency_ns = 12000;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1317 int plane_sr, cursor_sr;
af6c4575 1318 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1319 unsigned int enabled = 0;
1320
1321 vlv_update_drain_latency(dev);
1322
51cea1f4 1323 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1324 &valleyview_wm_info, latency_ns,
1325 &valleyview_cursor_wm_info, latency_ns,
1326 &planea_wm, &cursora_wm))
51cea1f4 1327 enabled |= 1 << PIPE_A;
b445e3b0 1328
51cea1f4 1329 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1330 &valleyview_wm_info, latency_ns,
1331 &valleyview_cursor_wm_info, latency_ns,
1332 &planeb_wm, &cursorb_wm))
51cea1f4 1333 enabled |= 1 << PIPE_B;
b445e3b0 1334
b445e3b0
ED		 1335 if (single_plane_enabled(enabled) &&
1336 g4x_compute_srwm(dev, ffs(enabled) - 1,
1337 sr_latency_ns,
1338 &valleyview_wm_info,
1339 &valleyview_cursor_wm_info,
af6c4575
CW		 1340 &plane_sr, &ignore_cursor_sr) &&
1341 g4x_compute_srwm(dev, ffs(enabled) - 1,
1342 2*sr_latency_ns,
1343 &valleyview_wm_info,
1344 &valleyview_cursor_wm_info,
52bd02d8 1345 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1346 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1347 } else {
b445e3b0
ED		 1348 I915_WRITE(FW_BLC_SELF_VLV,
1349 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1350 plane_sr = cursor_sr = 0;
1351 }
b445e3b0
ED		 1352
1353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354 planea_wm, cursora_wm,
1355 planeb_wm, cursorb_wm,
1356 plane_sr, cursor_sr);
1357
1358 I915_WRITE(DSPFW1,
1359 (plane_sr << DSPFW_SR_SHIFT) |
1360 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1361 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1362 planea_wm);
1363 I915_WRITE(DSPFW2,
8c919b28 1364 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1365 (cursora_wm << DSPFW_CURSORA_SHIFT));
1366 I915_WRITE(DSPFW3,
8c919b28
CW		 1367 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1368 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1369}
1370
46ba614c 1371static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1372{
46ba614c 1373 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
1378 unsigned int enabled = 0;
1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1381 &g4x_wm_info, latency_ns,
1382 &g4x_cursor_wm_info, latency_ns,
1383 &planea_wm, &cursora_wm))
51cea1f4 1384 enabled |= 1 << PIPE_A;
b445e3b0 1385
51cea1f4 1386 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1387 &g4x_wm_info, latency_ns,
1388 &g4x_cursor_wm_info, latency_ns,
1389 &planeb_wm, &cursorb_wm))
51cea1f4 1390 enabled |= 1 << PIPE_B;
b445e3b0 1391
b445e3b0
ED		 1392 if (single_plane_enabled(enabled) &&
1393 g4x_compute_srwm(dev, ffs(enabled) - 1,
1394 sr_latency_ns,
1395 &g4x_wm_info,
1396 &g4x_cursor_wm_info,
52bd02d8 1397 &plane_sr, &cursor_sr)) {
b445e3b0 1398 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1399 } else {
b445e3b0
ED		 1400 I915_WRITE(FW_BLC_SELF,
1401 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1402 plane_sr = cursor_sr = 0;
1403 }
b445e3b0
ED		 1404
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406 planea_wm, cursora_wm,
1407 planeb_wm, cursorb_wm,
1408 plane_sr, cursor_sr);
1409
1410 I915_WRITE(DSPFW1,
1411 (plane_sr << DSPFW_SR_SHIFT) |
1412 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1413 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1414 planea_wm);
1415 I915_WRITE(DSPFW2,
8c919b28 1416 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1417 (cursora_wm << DSPFW_CURSORA_SHIFT));
1418 /* HPLL off in SR has some issues on G4x... disable it */
1419 I915_WRITE(DSPFW3,
8c919b28 1420 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1421 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1422}
1423
46ba614c 1424static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1425{
46ba614c 1426 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct drm_crtc *crtc;
1429 int srwm = 1;
1430 int cursor_sr = 16;
1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1437 const struct drm_display_mode *adjusted_mode =
1438 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1439 int clock = adjusted_mode->crtc_clock;
fec8cba3 1440 int htotal = adjusted_mode->crtc_htotal;
37327abd 1441 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
f4510a27 1442 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1443 unsigned long line_time_us;
1444 int entries;
1445
922044c9 1446 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1447
1448 /* Use ns/us then divide to preserve precision */
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450 pixel_size * hdisplay;
1451 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452 srwm = I965_FIFO_SIZE - entries;
1453 if (srwm < 0)
1454 srwm = 1;
1455 srwm &= 0x1ff;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457 entries, srwm);
1458
1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
7bb836dd 1460 pixel_size * to_intel_crtc(crtc)->cursor_width;
b445e3b0
ED		 1461 entries = DIV_ROUND_UP(entries,
1462 i965_cursor_wm_info.cacheline_size);
1463 cursor_sr = i965_cursor_wm_info.fifo_size -
1464 (entries + i965_cursor_wm_info.guard_size);
1465
1466 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467 cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm, cursor_sr);
1471
1472 if (IS_CRESTLINE(dev))
1473 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1474 } else {
1475 /* Turn off self refresh if both pipes are enabled */
1476 if (IS_CRESTLINE(dev))
1477 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1478 & ~FW_BLC_SELF_EN);
1479 }
1480
1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1482 srwm);
1483
1484 /* 965 has limitations... */
1485 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1486 (8 << 16) | (8 << 8) | (8 << 0));
1487 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490}
1491
46ba614c 1492static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1493{
46ba614c 1494 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 const struct intel_watermark_params *wm_info;
1497 uint32_t fwater_lo;
1498 uint32_t fwater_hi;
1499 int cwm, srwm = 1;
1500 int fifo_size;
1501 int planea_wm, planeb_wm;
1502 struct drm_crtc *crtc, *enabled = NULL;
1503
1504 if (IS_I945GM(dev))
1505 wm_info = &i945_wm_info;
1506 else if (!IS_GEN2(dev))
1507 wm_info = &i915_wm_info;
1508 else
feb56b93 1509 wm_info = &i830_wm_info;
b445e3b0
ED		 1510
1511 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1512 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1513 if (intel_crtc_active(crtc)) {
241bfc38 1514 const struct drm_display_mode *adjusted_mode;
f4510a27 1515 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1516 if (IS_GEN2(dev))
1517 cpp = 4;
1518
241bfc38
DL		 1519 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1520 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1521 wm_info, fifo_size, cpp,
b445e3b0
ED		 1522 latency_ns);
1523 enabled = crtc;
1524 } else
1525 planea_wm = fifo_size - wm_info->guard_size;
1526
1527 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1528 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1529 if (intel_crtc_active(crtc)) {
241bfc38 1530 const struct drm_display_mode *adjusted_mode;
f4510a27 1531 int cpp = crtc->primary->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1532 if (IS_GEN2(dev))
1533 cpp = 4;
1534
241bfc38
DL		 1535 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1536 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1537 wm_info, fifo_size, cpp,
b445e3b0
ED		 1538 latency_ns);
1539 if (enabled == NULL)
1540 enabled = crtc;
1541 else
1542 enabled = NULL;
1543 } else
1544 planeb_wm = fifo_size - wm_info->guard_size;
1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d
DV		 1548 if (IS_I915GM(dev) && enabled) {
1549 struct intel_framebuffer *fb;
1550
1551 fb = to_intel_framebuffer(enabled->primary->fb);
1552
1553 /* self-refresh seems busted with untiled */
1554 if (fb->obj->tiling_mode == I915_TILING_NONE)
1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 if (IS_I945G(dev) || IS_I945GM(dev))
1565 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1566 else if (IS_I915GM(dev))
3f2dc5ac 1567 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1568
1569 /* Calc sr entries for one plane configs */
1570 if (HAS_FW_BLC(dev) && enabled) {
1571 /* self-refresh has much higher latency */
1572 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1573 const struct drm_display_mode *adjusted_mode =
1574 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1575 int clock = adjusted_mode->crtc_clock;
fec8cba3 1576 int htotal = adjusted_mode->crtc_htotal;
f727b490 1577 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
f4510a27 1578 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
b445e3b0
ED		 1579 unsigned long line_time_us;
1580 int entries;
1581
922044c9 1582 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1583
1584 /* Use ns/us then divide to preserve precision */
1585 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1586 pixel_size * hdisplay;
1587 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1588 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1589 srwm = wm_info->fifo_size - entries;
1590 if (srwm < 0)
1591 srwm = 1;
1592
1593 if (IS_I945G(dev) || IS_I945GM(dev))
1594 I915_WRITE(FW_BLC_SELF,
1595 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1596 else if (IS_I915GM(dev))
1597 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1598 }
1599
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601 planea_wm, planeb_wm, cwm, srwm);
1602
1603 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1604 fwater_hi = (cwm & 0x1f);
1605
1606 /* Set request length to 8 cachelines per fetch */
1607 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1608 fwater_hi = fwater_hi | (1 << 8);
1609
1610 I915_WRITE(FW_BLC, fwater_lo);
1611 I915_WRITE(FW_BLC2, fwater_hi);
1612
1613 if (HAS_FW_BLC(dev)) {
1614 if (enabled) {
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF,
1617 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1618 else if (IS_I915GM(dev))
3f2dc5ac 1619 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
b445e3b0
ED		 1620 DRM_DEBUG_KMS("memory self refresh enabled\n");
1621 } else
1622 DRM_DEBUG_KMS("memory self refresh disabled\n");
1623 }
1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
241bfc38
DL		 1639 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1643 4, latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
3658729a
VS		 1652static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1653 struct drm_crtc *crtc)
801bcfff
PZ		 1654{
1655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1656 uint32_t pixel_rate;
801bcfff 1657
241bfc38 1658 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 1659
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1662
fd4daa9c 1663 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 1664 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 1665 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 1666
37327abd
VS		 1667 pipe_w = intel_crtc->config.pipe_src_w;
1668 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
1676 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1677 pfit_w * pfit_h);
1678 }
1679
1680 return pixel_rate;
1681}
1682
37126462 1683/* latency must be in 0.1us units. */
23297044 1684static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1685 uint32_t latency)
1686{
1687 uint64_t ret;
1688
3312ba65
VS		 1689 if (WARN(latency == 0, "Latency value missing\n"))
1690 return UINT_MAX;
1691
801bcfff
PZ		 1692 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1693 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1694
1695 return ret;
1696}
1697
37126462 1698/* latency must be in 0.1us units. */
23297044 1699static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1700 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1701 uint32_t latency)
1702{
1703 uint32_t ret;
1704
3312ba65
VS		 1705 if (WARN(latency == 0, "Latency value missing\n"))
1706 return UINT_MAX;
1707
801bcfff
PZ		 1708 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1709 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1710 ret = DIV_ROUND_UP(ret, 64) + 2;
1711 return ret;
1712}
1713
23297044 1714static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1715 uint8_t bytes_per_pixel)
1716{
1717 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1718}
1719
820c1980 1720struct ilk_pipe_wm_parameters {
801bcfff 1721 bool active;
801bcfff
PZ		 1722 uint32_t pipe_htotal;
1723 uint32_t pixel_rate;
c35426d2
VS		 1724 struct intel_plane_wm_parameters pri;
1725 struct intel_plane_wm_parameters spr;
1726 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1727};
1728
820c1980 1729struct ilk_wm_maximums {
cca32e9a
PZ		 1730 uint16_t pri;
1731 uint16_t spr;
1732 uint16_t cur;
1733 uint16_t fbc;
1734};
1735
240264f4
VS		 1736/* used in computing the new watermarks state */
1737struct intel_wm_config {
1738 unsigned int num_pipes_active;
1739 bool sprites_enabled;
1740 bool sprites_scaled;
240264f4
VS		 1741};
1742
37126462
VS		 1743/*
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1746 */
820c1980 1747static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
cca32e9a
PZ		 1751 uint32_t method1, method2;
1752
c35426d2 1753 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1754 return 0;
1755
23297044 1756 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1757 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1758 mem_value);
1759
1760 if (!is_lp)
1761 return method1;
1762
23297044 1763 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1764 params->pipe_htotal,
c35426d2
VS		 1765 params->pri.horiz_pixels,
1766 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1767 mem_value);
1768
1769 return min(method1, method2);
801bcfff
PZ		 1770}
1771
37126462
VS		 1772/*
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1775 */
820c1980 1776static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
1779 uint32_t method1, method2;
1780
c35426d2 1781 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1782 return 0;
1783
23297044 1784 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1785 params->spr.bytes_per_pixel,
801bcfff 1786 mem_value);
23297044 1787 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1788 params->pipe_htotal,
c35426d2
VS		 1789 params->spr.horiz_pixels,
1790 params->spr.bytes_per_pixel,
801bcfff
PZ		 1791 mem_value);
1792 return min(method1, method2);
1793}
1794
37126462
VS		 1795/*
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1798 */
820c1980 1799static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
c35426d2 1802 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1803 return 0;
1804
23297044 1805 return ilk_wm_method2(params->pixel_rate,
801bcfff 1806 params->pipe_htotal,
c35426d2
VS		 1807 params->cur.horiz_pixels,
1808 params->cur.bytes_per_pixel,
801bcfff
PZ		 1809 mem_value);
1810}
1811
cca32e9a 1812/* Only for WM_LP. */
820c1980 1813static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1814 uint32_t pri_val)
cca32e9a 1815{
c35426d2 1816 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1817 return 0;
1818
23297044 1819 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1820 params->pri.horiz_pixels,
1821 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1822}
1823
158ae64f
VS		 1824static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1825{
416f4727
VS		 1826 if (INTEL_INFO(dev)->gen >= 8)
1827 return 3072;
1828 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1829 return 768;
1830 else
1831 return 512;
1832}
1833
4e975081
VS		 1834static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1835 int level, bool is_sprite)
1836{
1837 if (INTEL_INFO(dev)->gen >= 8)
1838 /* BDW primary/sprite plane watermarks */
1839 return level == 0 ? 255 : 2047;
1840 else if (INTEL_INFO(dev)->gen >= 7)
1841 /* IVB/HSW primary/sprite plane watermarks */
1842 return level == 0 ? 127 : 1023;
1843 else if (!is_sprite)
1844 /* ILK/SNB primary plane watermarks */
1845 return level == 0 ? 127 : 511;
1846 else
1847 /* ILK/SNB sprite plane watermarks */
1848 return level == 0 ? 63 : 255;
1849}
1850
1851static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1852 int level)
1853{
1854 if (INTEL_INFO(dev)->gen >= 7)
1855 return level == 0 ? 63 : 255;
1856 else
1857 return level == 0 ? 31 : 63;
1858}
1859
1860static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1861{
1862 if (INTEL_INFO(dev)->gen >= 8)
1863 return 31;
1864 else
1865 return 15;
1866}
1867
158ae64f
VS		 1868/* Calculate the maximum primary/sprite plane watermark */
1869static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1870 int level,
240264f4 1871 const struct intel_wm_config *config,
158ae64f
VS		 1872 enum intel_ddb_partitioning ddb_partitioning,
1873 bool is_sprite)
1874{
1875 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1876
1877 /* if sprites aren't enabled, sprites get nothing */
240264f4 1878 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1879 return 0;
1880
1881 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1882 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1883 fifo_size /= INTEL_INFO(dev)->num_pipes;
1884
1885 /*
1886 * For some reason the non self refresh
1887 * FIFO size is only half of the self
1888 * refresh FIFO size on ILK/SNB.
1889 */
1890 if (INTEL_INFO(dev)->gen <= 6)
1891 fifo_size /= 2;
1892 }
1893
240264f4 1894 if (config->sprites_enabled) {
158ae64f
VS		 1895 /* level 0 is always calculated with 1:1 split */
1896 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1897 if (is_sprite)
1898 fifo_size *= 5;
1899 fifo_size /= 6;
1900 } else {
1901 fifo_size /= 2;
1902 }
1903 }
1904
1905 /* clamp to max that the registers can hold */
4e975081 1906 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1907}
1908
1909/* Calculate the maximum cursor plane watermark */
1910static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1911 int level,
1912 const struct intel_wm_config *config)
158ae64f
VS		 1913{
1914 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1915 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1916 return 64;
1917
1918 /* otherwise just report max that registers can hold */
4e975081 1919 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1920}
1921
d34ff9c6 1922static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1923 int level,
1924 const struct intel_wm_config *config,
1925 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1926 struct ilk_wm_maximums *max)
158ae64f 1927{
240264f4
VS		 1928 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1929 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1930 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1931 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1932}
1933
a3cb4048
VS		 1934static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1935 int level,
1936 struct ilk_wm_maximums *max)
1937{
1938 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1939 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1940 max->cur = ilk_cursor_wm_reg_max(dev, level);
1941 max->fbc = ilk_fbc_wm_reg_max(dev);
1942}
1943
d9395655 1944static bool ilk_validate_wm_level(int level,
820c1980 1945 const struct ilk_wm_maximums *max,
d9395655 1946 struct intel_wm_level *result)
a9786a11
VS		 1947{
1948 bool ret;
1949
1950 /* already determined to be invalid? */
1951 if (!result->enable)
1952 return false;
1953
1954 result->enable = result->pri_val <= max->pri &&
1955 result->spr_val <= max->spr &&
1956 result->cur_val <= max->cur;
1957
1958 ret = result->enable;
1959
1960 /*
1961 * HACK until we can pre-compute everything,
1962 * and thus fail gracefully if LP0 watermarks
1963 * are exceeded...
1964 */
1965 if (level == 0 && !result->enable) {
1966 if (result->pri_val > max->pri)
1967 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1968 level, result->pri_val, max->pri);
1969 if (result->spr_val > max->spr)
1970 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1971 level, result->spr_val, max->spr);
1972 if (result->cur_val > max->cur)
1973 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1974 level, result->cur_val, max->cur);
1975
1976 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1977 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1978 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1979 result->enable = true;
1980 }
1981
a9786a11
VS		 1982 return ret;
1983}
1984
d34ff9c6 1985static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1986 int level,
820c1980 1987 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1988 struct intel_wm_level *result)
6f5ddd17
VS		 1989{
1990 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1991 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1992 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1993
1994 /* WM1+ latency values stored in 0.5us units */
1995 if (level > 0) {
1996 pri_latency *= 5;
1997 spr_latency *= 5;
1998 cur_latency *= 5;
1999 }
2000
2001 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2002 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2003 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2004 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2005 result->enable = true;
2006}
2007
801bcfff
PZ		 2008static uint32_t
2009hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2010{
2011 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2013 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2014 u32 linetime, ips_linetime;
1f8eeabf 2015
801bcfff
PZ		 2016 if (!intel_crtc_active(crtc))
2017 return 0;
1011d8c4 2018
1f8eeabf
ED		 2019 /* The WM are computed with base on how long it takes to fill a single
2020 * row at the given clock rate, multiplied by 8.
2021 * */
fec8cba3
JB		 2022 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2023 mode->crtc_clock);
2024 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 2025 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2026
801bcfff
PZ		 2027 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2028 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2029}
2030
12b134df
VS		 2031static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2032{
2033 struct drm_i915_private *dev_priv = dev->dev_private;
2034
a42a5719 2035 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2036 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2037
2038 wm[0] = (sskpd >> 56) & 0xFF;
2039 if (wm[0] == 0)
2040 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2041 wm[1] = (sskpd >> 4) & 0xFF;
2042 wm[2] = (sskpd >> 12) & 0xFF;
2043 wm[3] = (sskpd >> 20) & 0x1FF;
2044 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2045 } else if (INTEL_INFO(dev)->gen >= 6) {
2046 uint32_t sskpd = I915_READ(MCH_SSKPD);
2047
2048 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2049 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2050 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2051 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2052 } else if (INTEL_INFO(dev)->gen >= 5) {
2053 uint32_t mltr = I915_READ(MLTR_ILK);
2054
2055 /* ILK primary LP0 latency is 700 ns */
2056 wm[0] = 7;
2057 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2058 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2059 }
2060}
2061
53615a5e
VS		 2062static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2063{
2064 /* ILK sprite LP0 latency is 1300 ns */
2065 if (INTEL_INFO(dev)->gen == 5)
2066 wm[0] = 13;
2067}
2068
2069static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2070{
2071 /* ILK cursor LP0 latency is 1300 ns */
2072 if (INTEL_INFO(dev)->gen == 5)
2073 wm[0] = 13;
2074
2075 /* WaDoubleCursorLP3Latency:ivb */
2076 if (IS_IVYBRIDGE(dev))
2077 wm[3] *= 2;
2078}
2079
546c81fd 2080int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2081{
26ec971e 2082 /* how many WM levels are we expecting */
a42a5719 2083 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2084 return 4;
26ec971e 2085 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2086 return 3;
26ec971e 2087 else
ad0d6dc4
VS		 2088 return 2;
2089}
2090
2091static void intel_print_wm_latency(struct drm_device *dev,
2092 const char *name,
2093 const uint16_t wm[5])
2094{
2095 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2096
2097 for (level = 0; level <= max_level; level++) {
2098 unsigned int latency = wm[level];
2099
2100 if (latency == 0) {
2101 DRM_ERROR("%s WM%d latency not provided\n",
2102 name, level);
2103 continue;
2104 }
2105
2106 /* WM1+ latency values in 0.5us units */
2107 if (level > 0)
2108 latency *= 5;
2109
2110 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2111 name, level, wm[level],
2112 latency / 10, latency % 10);
2113 }
2114}
2115
fa50ad61 2116static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2117{
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119
2120 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2121
2122 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2123 sizeof(dev_priv->wm.pri_latency));
2124 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2125 sizeof(dev_priv->wm.pri_latency));
2126
2127 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2128 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2129
2130 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2131 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2132 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2133}
2134
820c1980 2135static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2136 struct ilk_pipe_wm_parameters *p)
1011d8c4 2137{
7c4a395f
VS		 2138 struct drm_device *dev = crtc->dev;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2141 struct drm_plane *plane;
1011d8c4 2142
2a44b76b
VS		 2143 if (!intel_crtc_active(crtc))
2144 return;
801bcfff 2145
2a44b76b
VS		 2146 p->active = true;
2147 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2148 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2149 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2150 p->cur.bytes_per_pixel = 4;
2151 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2152 p->cur.horiz_pixels = intel_crtc->cursor_width;
2153 /* TODO: for now, assume primary and cursor planes are always enabled. */
2154 p->pri.enabled = true;
2155 p->cur.enabled = true;
7c4a395f 2156
af2b653b 2157 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2158 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2159
2a44b76b 2160 if (intel_plane->pipe == pipe) {
7c4a395f 2161 p->spr = intel_plane->wm;
2a44b76b
VS		 2162 break;
2163 }
2164 }
2165}
2166
2167static void ilk_compute_wm_config(struct drm_device *dev,
2168 struct intel_wm_config *config)
2169{
2170 struct intel_crtc *intel_crtc;
2171
2172 /* Compute the currently _active_ config */
d3fcc808 2173 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2174 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2175
2a44b76b
VS		 2176 if (!wm->pipe_enabled)
2177 continue;
cca32e9a 2178
2a44b76b
VS		 2179 config->sprites_enabled |= wm->sprites_enabled;
2180 config->sprites_scaled |= wm->sprites_scaled;
2181 config->num_pipes_active++;
cca32e9a 2182 }
801bcfff
PZ		 2183}
2184
0b2ae6d7
VS		 2185/* Compute new watermarks for the pipe */
2186static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2187 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2188 struct intel_pipe_wm *pipe_wm)
2189{
2190 struct drm_device *dev = crtc->dev;
d34ff9c6 2191 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2192 int level, max_level = ilk_wm_max_level(dev);
2193 /* LP0 watermark maximums depend on this pipe alone */
2194 struct intel_wm_config config = {
2195 .num_pipes_active = 1,
2196 .sprites_enabled = params->spr.enabled,
2197 .sprites_scaled = params->spr.scaled,
2198 };
820c1980 2199 struct ilk_wm_maximums max;
0b2ae6d7 2200
2a44b76b
VS		 2201 pipe_wm->pipe_enabled = params->active;
2202 pipe_wm->sprites_enabled = params->spr.enabled;
2203 pipe_wm->sprites_scaled = params->spr.scaled;
2204
7b39a0b7
VS		 2205 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2206 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2207 max_level = 1;
2208
2209 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2210 if (params->spr.scaled)
2211 max_level = 0;
2212
a3cb4048 2213 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2214
a42a5719 2215 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2216 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2217
a3cb4048
VS		 2218 /* LP0 watermarks always use 1/2 DDB partitioning */
2219 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2220
0b2ae6d7 2221 /* At least LP0 must be valid */
a3cb4048
VS		 2222 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2223 return false;
2224
2225 ilk_compute_wm_reg_maximums(dev, 1, &max);
2226
2227 for (level = 1; level <= max_level; level++) {
2228 struct intel_wm_level wm = {};
2229
2230 ilk_compute_wm_level(dev_priv, level, params, &wm);
2231
2232 /*
2233 * Disable any watermark level that exceeds the
2234 * register maximums since such watermarks are
2235 * always invalid.
2236 */
2237 if (!ilk_validate_wm_level(level, &max, &wm))
2238 break;
2239
2240 pipe_wm->wm[level] = wm;
2241 }
2242
2243 return true;
0b2ae6d7
VS		 2244}
2245
2246/*
2247 * Merge the watermarks from all active pipes for a specific level.
2248 */
2249static void ilk_merge_wm_level(struct drm_device *dev,
2250 int level,
2251 struct intel_wm_level *ret_wm)
2252{
2253 const struct intel_crtc *intel_crtc;
2254
d52fea5b
VS		 2255 ret_wm->enable = true;
2256
d3fcc808 2257 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2258 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2259 const struct intel_wm_level *wm = &active->wm[level];
2260
2261 if (!active->pipe_enabled)
2262 continue;
0b2ae6d7 2263
d52fea5b
VS		 2264 /*
2265 * The watermark values may have been used in the past,
2266 * so we must maintain them in the registers for some
2267 * time even if the level is now disabled.
2268 */
0b2ae6d7 2269 if (!wm->enable)
d52fea5b 2270 ret_wm->enable = false;
0b2ae6d7
VS		 2271
2272 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2273 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2274 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2275 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2276 }
0b2ae6d7
VS		 2277}
2278
2279/*
2280 * Merge all low power watermarks for all active pipes.
2281 */
2282static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2283 const struct intel_wm_config *config,
820c1980 2284 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2285 struct intel_pipe_wm *merged)
2286{
2287 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2288 int last_enabled_level = max_level;
0b2ae6d7 2289
0ba22e26
VS		 2290 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2291 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2292 config->num_pipes_active > 1)
2293 return;
2294
6c8b6c28
VS		 2295 /* ILK: FBC WM must be disabled always */
2296 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2297
2298 /* merge each WM1+ level */
2299 for (level = 1; level <= max_level; level++) {
2300 struct intel_wm_level *wm = &merged->wm[level];
2301
2302 ilk_merge_wm_level(dev, level, wm);
2303
d52fea5b
VS		 2304 if (level > last_enabled_level)
2305 wm->enable = false;
2306 else if (!ilk_validate_wm_level(level, max, wm))
2307 /* make sure all following levels get disabled */
2308 last_enabled_level = level - 1;
0b2ae6d7
VS		 2309
2310 /*
2311 * The spec says it is preferred to disable
2312 * FBC WMs instead of disabling a WM level.
2313 */
2314 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2315 if (wm->enable)
2316 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2317 wm->fbc_val = 0;
2318 }
2319 }
6c8b6c28
VS		 2320
2321 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2322 /*
2323 * FIXME this is racy. FBC might get enabled later.
2324 * What we should check here is whether FBC can be
2325 * enabled sometime later.
2326 */
2327 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2328 for (level = 2; level <= max_level; level++) {
2329 struct intel_wm_level *wm = &merged->wm[level];
2330
2331 wm->enable = false;
2332 }
2333 }
0b2ae6d7
VS		 2334}
2335
b380ca3c
VS		 2336static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2337{
2338 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2339 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2340}
2341
a68d68ee
VS		 2342/* The value we need to program into the WM_LPx latency field */
2343static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2344{
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2346
a42a5719 2347 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2348 return 2 * level;
2349 else
2350 return dev_priv->wm.pri_latency[level];
2351}
2352
820c1980 2353static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2354 const struct intel_pipe_wm *merged,
609cedef 2355 enum intel_ddb_partitioning partitioning,
820c1980 2356 struct ilk_wm_values *results)
801bcfff 2357{
0b2ae6d7
VS		 2358 struct intel_crtc *intel_crtc;
2359 int level, wm_lp;
cca32e9a 2360
0362c781 2361 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2362 results->partitioning = partitioning;
cca32e9a 2363
0b2ae6d7 2364 /* LP1+ register values */
cca32e9a 2365 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2366 const struct intel_wm_level *r;
801bcfff 2367
b380ca3c 2368 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2369
0362c781 2370 r = &merged->wm[level];
cca32e9a 2371
d52fea5b
VS		 2372 /*
2373 * Maintain the watermark values even if the level is
2374 * disabled. Doing otherwise could cause underruns.
2375 */
2376 results->wm_lp[wm_lp - 1] =
a68d68ee 2377 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2378 (r->pri_val << WM1_LP_SR_SHIFT) |
2379 r->cur_val;
2380
d52fea5b
VS		 2381 if (r->enable)
2382 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2383
416f4727
VS		 2384 if (INTEL_INFO(dev)->gen >= 8)
2385 results->wm_lp[wm_lp - 1] |=
2386 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2387 else
2388 results->wm_lp[wm_lp - 1] |=
2389 r->fbc_val << WM1_LP_FBC_SHIFT;
2390
d52fea5b
VS		 2391 /*
2392 * Always set WM1S_LP_EN when spr_val != 0, even if the
2393 * level is disabled. Doing otherwise could cause underruns.
2394 */
6cef2b8a
VS		 2395 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2396 WARN_ON(wm_lp != 1);
2397 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2398 } else
2399 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2400 }
801bcfff 2401
0b2ae6d7 2402 /* LP0 register values */
d3fcc808 2403 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2404 enum pipe pipe = intel_crtc->pipe;
2405 const struct intel_wm_level *r =
2406 &intel_crtc->wm.active.wm[0];
2407
2408 if (WARN_ON(!r->enable))
2409 continue;
2410
2411 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2412
0b2ae6d7
VS		 2413 results->wm_pipe[pipe] =
2414 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2415 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2416 r->cur_val;
801bcfff
PZ		 2417 }
2418}
2419
861f3389
PZ		 2420/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2421 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2422static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2423 struct intel_pipe_wm *r1,
2424 struct intel_pipe_wm *r2)
861f3389 2425{
198a1e9b
VS		 2426 int level, max_level = ilk_wm_max_level(dev);
2427 int level1 = 0, level2 = 0;
861f3389 2428
198a1e9b
VS		 2429 for (level = 1; level <= max_level; level++) {
2430 if (r1->wm[level].enable)
2431 level1 = level;
2432 if (r2->wm[level].enable)
2433 level2 = level;
861f3389
PZ		 2434 }
2435
198a1e9b
VS		 2436 if (level1 == level2) {
2437 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2438 return r2;
2439 else
2440 return r1;
198a1e9b 2441 } else if (level1 > level2) {
861f3389
PZ		 2442 return r1;
2443 } else {
2444 return r2;
2445 }
2446}
2447
49a687c4
VS		 2448/* dirty bits used to track which watermarks need changes */
2449#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2450#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2451#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2452#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2453#define WM_DIRTY_FBC (1 << 24)
2454#define WM_DIRTY_DDB (1 << 25)
2455
2456static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
820c1980
ID		 2457 const struct ilk_wm_values *old,
2458 const struct ilk_wm_values *new)
49a687c4
VS		 2459{
2460 unsigned int dirty = 0;
2461 enum pipe pipe;
2462 int wm_lp;
2463
2464 for_each_pipe(pipe) {
2465 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2466 dirty |= WM_DIRTY_LINETIME(pipe);
2467 /* Must disable LP1+ watermarks too */
2468 dirty |= WM_DIRTY_LP_ALL;
2469 }
2470
2471 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2472 dirty |= WM_DIRTY_PIPE(pipe);
2473 /* Must disable LP1+ watermarks too */
2474 dirty |= WM_DIRTY_LP_ALL;
2475 }
2476 }
2477
2478 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2479 dirty |= WM_DIRTY_FBC;
2480 /* Must disable LP1+ watermarks too */
2481 dirty |= WM_DIRTY_LP_ALL;
2482 }
2483
2484 if (old->partitioning != new->partitioning) {
2485 dirty |= WM_DIRTY_DDB;
2486 /* Must disable LP1+ watermarks too */
2487 dirty |= WM_DIRTY_LP_ALL;
2488 }
2489
2490 /* LP1+ watermarks already deemed dirty, no need to continue */
2491 if (dirty & WM_DIRTY_LP_ALL)
2492 return dirty;
2493
2494 /* Find the lowest numbered LP1+ watermark in need of an update... */
2495 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2496 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2497 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2498 break;
2499 }
2500
2501 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2502 for (; wm_lp <= 3; wm_lp++)
2503 dirty |= WM_DIRTY_LP(wm_lp);
2504
2505 return dirty;
2506}
2507
8553c18e
VS		 2508static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2509 unsigned int dirty)
801bcfff 2510{
820c1980 2511 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2512 bool changed = false;
801bcfff 2513
facd619b
VS		 2514 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2515 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2516 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2517 changed = true;
facd619b
VS		 2518 }
2519 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2520 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2521 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2522 changed = true;
facd619b
VS		 2523 }
2524 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2525 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2526 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2527 changed = true;
facd619b 2528 }
801bcfff 2529
facd619b
VS		 2530 /*
2531 * Don't touch WM1S_LP_EN here.
2532 * Doing so could cause underruns.
2533 */
6cef2b8a 2534
8553c18e
VS		 2535 return changed;
2536}
2537
2538/*
2539 * The spec says we shouldn't write when we don't need, because every write
2540 * causes WMs to be re-evaluated, expending some power.
2541 */
820c1980
ID		 2542static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2543 struct ilk_wm_values *results)
8553c18e
VS		 2544{
2545 struct drm_device *dev = dev_priv->dev;
820c1980 2546 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2547 unsigned int dirty;
2548 uint32_t val;
2549
2550 dirty = ilk_compute_wm_dirty(dev, previous, results);
2551 if (!dirty)
2552 return;
2553
2554 _ilk_disable_lp_wm(dev_priv, dirty);
2555
49a687c4 2556 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2557 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2558 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2559 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2560 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2561 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2562
49a687c4 2563 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2564 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2565 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2566 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2567 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2568 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2569
49a687c4 2570 if (dirty & WM_DIRTY_DDB) {
a42a5719 2571 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2572 val = I915_READ(WM_MISC);
2573 if (results->partitioning == INTEL_DDB_PART_1_2)
2574 val &= ~WM_MISC_DATA_PARTITION_5_6;
2575 else
2576 val |= WM_MISC_DATA_PARTITION_5_6;
2577 I915_WRITE(WM_MISC, val);
2578 } else {
2579 val = I915_READ(DISP_ARB_CTL2);
2580 if (results->partitioning == INTEL_DDB_PART_1_2)
2581 val &= ~DISP_DATA_PARTITION_5_6;
2582 else
2583 val |= DISP_DATA_PARTITION_5_6;
2584 I915_WRITE(DISP_ARB_CTL2, val);
2585 }
1011d8c4
PZ		 2586 }
2587
49a687c4 2588 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2589 val = I915_READ(DISP_ARB_CTL);
2590 if (results->enable_fbc_wm)
2591 val &= ~DISP_FBC_WM_DIS;
2592 else
2593 val |= DISP_FBC_WM_DIS;
2594 I915_WRITE(DISP_ARB_CTL, val);
2595 }
2596
954911eb
ID		 2597 if (dirty & WM_DIRTY_LP(1) &&
2598 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2599 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2600
2601 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2602 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2603 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2604 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2605 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2606 }
801bcfff 2607
facd619b 2608 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2609 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2610 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2611 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2612 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2613 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2614
2615 dev_priv->wm.hw = *results;
801bcfff
PZ		 2616}
2617
8553c18e
VS		 2618static bool ilk_disable_lp_wm(struct drm_device *dev)
2619{
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621
2622 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2623}
2624
820c1980 2625static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 2626{
7c4a395f 2627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2628 struct drm_device *dev = crtc->dev;
801bcfff 2629 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 2630 struct ilk_wm_maximums max;
2631 struct ilk_pipe_wm_parameters params = {};
2632 struct ilk_wm_values results = {};
77c122bc 2633 enum intel_ddb_partitioning partitioning;
7c4a395f 2634 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2635 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2636 struct intel_wm_config config = {};
7c4a395f 2637
2a44b76b 2638 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 2639
2640 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2641
2642 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2643 return;
861f3389 2644
7c4a395f 2645 intel_crtc->wm.active = pipe_wm;
861f3389 2646
2a44b76b
VS		 2647 ilk_compute_wm_config(dev, &config);
2648
34982fe1 2649 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 2650 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 2651
2652 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2653 if (INTEL_INFO(dev)->gen >= 7 &&
2654 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2655 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 2656 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 2657
820c1980 2658 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2659 } else {
198a1e9b 2660 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2661 }
2662
198a1e9b 2663 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2664 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2665
820c1980 2666 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 2667
820c1980 2668 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2669}
2670
820c1980 2671static void ilk_update_sprite_wm(struct drm_plane *plane,
adf3d35e 2672 struct drm_crtc *crtc,
526682e9 2673 uint32_t sprite_width, int pixel_size,
bdd57d03 2674 bool enabled, bool scaled)
526682e9 2675{
8553c18e 2676 struct drm_device *dev = plane->dev;
adf3d35e 2677 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2678
adf3d35e
VS		 2679 intel_plane->wm.enabled = enabled;
2680 intel_plane->wm.scaled = scaled;
2681 intel_plane->wm.horiz_pixels = sprite_width;
2682 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2683
8553c18e
VS		 2684 /*
2685 * IVB workaround: must disable low power watermarks for at least
2686 * one frame before enabling scaling. LP watermarks can be re-enabled
2687 * when scaling is disabled.
2688 *
2689 * WaCxSRDisabledForSpriteScaling:ivb
2690 */
2691 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2692 intel_wait_for_vblank(dev, intel_plane->pipe);
2693
820c1980 2694 ilk_update_wm(crtc);
526682e9
PZ		 2695}
2696
243e6a44
VS		 2697static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2698{
2699 struct drm_device *dev = crtc->dev;
2700 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2701 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2703 struct intel_pipe_wm *active = &intel_crtc->wm.active;
2704 enum pipe pipe = intel_crtc->pipe;
2705 static const unsigned int wm0_pipe_reg[] = {
2706 [PIPE_A] = WM0_PIPEA_ILK,
2707 [PIPE_B] = WM0_PIPEB_ILK,
2708 [PIPE_C] = WM0_PIPEC_IVB,
2709 };
2710
2711 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 2712 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2713 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 2714
2a44b76b
VS		 2715 active->pipe_enabled = intel_crtc_active(crtc);
2716
2717 if (active->pipe_enabled) {
243e6a44
VS		 2718 u32 tmp = hw->wm_pipe[pipe];
2719
2720 /*
2721 * For active pipes LP0 watermark is marked as
2722 * enabled, and LP1+ watermaks as disabled since
2723 * we can't really reverse compute them in case
2724 * multiple pipes are active.
2725 */
2726 active->wm[0].enable = true;
2727 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2728 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2729 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2730 active->linetime = hw->wm_linetime[pipe];
2731 } else {
2732 int level, max_level = ilk_wm_max_level(dev);
2733
2734 /*
2735 * For inactive pipes, all watermark levels
2736 * should be marked as enabled but zeroed,
2737 * which is what we'd compute them to.
2738 */
2739 for (level = 0; level <= max_level; level++)
2740 active->wm[level].enable = true;
2741 }
2742}
2743
2744void ilk_wm_get_hw_state(struct drm_device *dev)
2745{
2746 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 2747 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 2748 struct drm_crtc *crtc;
2749
70e1e0ec 2750 for_each_crtc(dev, crtc)
243e6a44
VS		 2751 ilk_pipe_wm_get_hw_state(crtc);
2752
2753 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2754 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2755 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2756
2757 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 2758 if (INTEL_INFO(dev)->gen >= 7) {
2759 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2760 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2761 }
243e6a44 2762
a42a5719 2763 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 2764 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2765 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2766 else if (IS_IVYBRIDGE(dev))
2767 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2768 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 2769
2770 hw->enable_fbc_wm =
2771 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2772}
2773
b445e3b0
ED		 2774/**
2775 * intel_update_watermarks - update FIFO watermark values based on current modes
2776 *
2777 * Calculate watermark values for the various WM regs based on current mode
2778 * and plane configuration.
2779 *
2780 * There are several cases to deal with here:
2781 * - normal (i.e. non-self-refresh)
2782 * - self-refresh (SR) mode
2783 * - lines are large relative to FIFO size (buffer can hold up to 2)
2784 * - lines are small relative to FIFO size (buffer can hold more than 2
2785 * lines), so need to account for TLB latency
2786 *
2787 * The normal calculation is:
2788 * watermark = dotclock * bytes per pixel * latency
2789 * where latency is platform & configuration dependent (we assume pessimal
2790 * values here).
2791 *
2792 * The SR calculation is:
2793 * watermark = (trunc(latency/line time)+1) * surface width *
2794 * bytes per pixel
2795 * where
2796 * line time = htotal / dotclock
2797 * surface width = hdisplay for normal plane and 64 for cursor
2798 * and latency is assumed to be high, as above.
2799 *
2800 * The final value programmed to the register should always be rounded up,
2801 * and include an extra 2 entries to account for clock crossings.
2802 *
2803 * We don't use the sprite, so we can ignore that. And on Crestline we have
2804 * to set the non-SR watermarks to 8.
2805 */
46ba614c 2806void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 2807{
46ba614c 2808 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 2809
2810 if (dev_priv->display.update_wm)
46ba614c 2811 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 2812}
2813
adf3d35e
VS		 2814void intel_update_sprite_watermarks(struct drm_plane *plane,
2815 struct drm_crtc *crtc,
4c4ff43a 2816 uint32_t sprite_width, int pixel_size,
39db4a4d 2817 bool enabled, bool scaled)
b445e3b0 2818{
adf3d35e 2819 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 2820
2821 if (dev_priv->display.update_sprite_wm)
adf3d35e 2822 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 2823 pixel_size, enabled, scaled);
b445e3b0
ED		 2824}
2825
2b4e57bd
ED		 2826static struct drm_i915_gem_object *
2827intel_alloc_context_page(struct drm_device *dev)
2828{
2829 struct drm_i915_gem_object *ctx;
2830 int ret;
2831
2832 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2833
2834 ctx = i915_gem_alloc_object(dev, 4096);
2835 if (!ctx) {
2836 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2837 return NULL;
2838 }
2839
c69766f2 2840 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2b4e57bd
ED		 2841 if (ret) {
2842 DRM_ERROR("failed to pin power context: %d\n", ret);
2843 goto err_unref;
2844 }
2845
2846 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2847 if (ret) {
2848 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2849 goto err_unpin;
2850 }
2851
2852 return ctx;
2853
2854err_unpin:
d7f46fc4 2855 i915_gem_object_ggtt_unpin(ctx);
2b4e57bd
ED		 2856err_unref:
2857 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2858 return NULL;
2859}
2860
9270388e
DV		 2861/**
2862 * Lock protecting IPS related data structures
9270388e
DV		 2863 */
2864DEFINE_SPINLOCK(mchdev_lock);
2865
2866/* Global for IPS driver to get at the current i915 device. Protected by
2867 * mchdev_lock. */
2868static struct drm_i915_private *i915_mch_dev;
2869
2b4e57bd
ED		 2870bool ironlake_set_drps(struct drm_device *dev, u8 val)
2871{
2872 struct drm_i915_private *dev_priv = dev->dev_private;
2873 u16 rgvswctl;
2874
9270388e
DV		 2875 assert_spin_locked(&mchdev_lock);
2876
2b4e57bd
ED		 2877 rgvswctl = I915_READ16(MEMSWCTL);
2878 if (rgvswctl & MEMCTL_CMD_STS) {
2879 DRM_DEBUG("gpu busy, RCS change rejected\n");
2880 return false; /* still busy with another command */
2881 }
2882
2883 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2884 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2885 I915_WRITE16(MEMSWCTL, rgvswctl);
2886 POSTING_READ16(MEMSWCTL);
2887
2888 rgvswctl |= MEMCTL_CMD_STS;
2889 I915_WRITE16(MEMSWCTL, rgvswctl);
2890
2891 return true;
2892}
2893
8090c6b9 2894static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2895{
2896 struct drm_i915_private *dev_priv = dev->dev_private;
2897 u32 rgvmodectl = I915_READ(MEMMODECTL);
2898 u8 fmax, fmin, fstart, vstart;
2899
9270388e
DV		 2900 spin_lock_irq(&mchdev_lock);
2901
2b4e57bd
ED		 2902 /* Enable temp reporting */
2903 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2904 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2905
2906 /* 100ms RC evaluation intervals */
2907 I915_WRITE(RCUPEI, 100000);
2908 I915_WRITE(RCDNEI, 100000);
2909
2910 /* Set max/min thresholds to 90ms and 80ms respectively */
2911 I915_WRITE(RCBMAXAVG, 90000);
2912 I915_WRITE(RCBMINAVG, 80000);
2913
2914 I915_WRITE(MEMIHYST, 1);
2915
2916 /* Set up min, max, and cur for interrupt handling */
2917 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2918 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2919 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2920 MEMMODE_FSTART_SHIFT;
2921
2922 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2923 PXVFREQ_PX_SHIFT;
2924
20e4d407
DV		 2925 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2926 dev_priv->ips.fstart = fstart;
2b4e57bd 2927
20e4d407
DV		 2928 dev_priv->ips.max_delay = fstart;
2929 dev_priv->ips.min_delay = fmin;
2930 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2931
2932 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2933 fmax, fmin, fstart);
2934
2935 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2936
2937 /*
2938 * Interrupts will be enabled in ironlake_irq_postinstall
2939 */
2940
2941 I915_WRITE(VIDSTART, vstart);
2942 POSTING_READ(VIDSTART);
2943
2944 rgvmodectl |= MEMMODE_SWMODE_EN;
2945 I915_WRITE(MEMMODECTL, rgvmodectl);
2946
9270388e 2947 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2948 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2949 mdelay(1);
2b4e57bd
ED		 2950
2951 ironlake_set_drps(dev, fstart);
2952
20e4d407 2953 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2954 I915_READ(0x112e0);
20e4d407
DV		 2955 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2956 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2957 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2958
2959 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2960}
2961
8090c6b9 2962static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2963{
2964 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2965 u16 rgvswctl;
2966
2967 spin_lock_irq(&mchdev_lock);
2968
2969 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2970
2971 /* Ack interrupts, disable EFC interrupt */
2972 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2973 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2974 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2975 I915_WRITE(DEIIR, DE_PCU_EVENT);
2976 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2977
2978 /* Go back to the starting frequency */
20e4d407 2979 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2980 mdelay(1);
2b4e57bd
ED		 2981 rgvswctl |= MEMCTL_CMD_STS;
2982 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2983 mdelay(1);
2b4e57bd 2984
9270388e 2985 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2986}
2987
acbe9475
DV		 2988/* There's a funny hw issue where the hw returns all 0 when reading from
2989 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2990 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2991 * all limits and the gpu stuck at whatever frequency it is at atm).
2992 */
6917c7b9 2993static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 2994{
7b9e0ae6 2995 u32 limits;
2b4e57bd 2996
20b46e59
DV		 2997 /* Only set the down limit when we've reached the lowest level to avoid
2998 * getting more interrupts, otherwise leave this clear. This prevents a
2999 * race in the hw when coming out of rc6: There's a tiny window where
3000 * the hw runs at the minimal clock before selecting the desired
3001 * frequency, if the down threshold expires in that window we will not
3002 * receive a down interrupt. */
b39fb297
BW		 3003 limits = dev_priv->rps.max_freq_softlimit << 24;
3004 if (val <= dev_priv->rps.min_freq_softlimit)
3005 limits |= dev_priv->rps.min_freq_softlimit << 16;
20b46e59
DV		 3006
3007 return limits;
3008}
3009
dd75fdc8
CW		 3010static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3011{
3012 int new_power;
3013
3014 new_power = dev_priv->rps.power;
3015 switch (dev_priv->rps.power) {
3016 case LOW_POWER:
b39fb297 3017 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3018 new_power = BETWEEN;
3019 break;
3020
3021 case BETWEEN:
b39fb297 3022 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3023 new_power = LOW_POWER;
b39fb297 3024 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3025 new_power = HIGH_POWER;
3026 break;
3027
3028 case HIGH_POWER:
b39fb297 3029 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3030 new_power = BETWEEN;
3031 break;
3032 }
3033 /* Max/min bins are special */
b39fb297 3034 if (val == dev_priv->rps.min_freq_softlimit)
dd75fdc8 3035 new_power = LOW_POWER;
b39fb297 3036 if (val == dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3037 new_power = HIGH_POWER;
3038 if (new_power == dev_priv->rps.power)
3039 return;
3040
3041 /* Note the units here are not exactly 1us, but 1280ns. */
3042 switch (new_power) {
3043 case LOW_POWER:
3044 /* Upclock if more than 95% busy over 16ms */
3045 I915_WRITE(GEN6_RP_UP_EI, 12500);
3046 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3047
3048 /* Downclock if less than 85% busy over 32ms */
3049 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3050 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3051
3052 I915_WRITE(GEN6_RP_CONTROL,
3053 GEN6_RP_MEDIA_TURBO |
3054 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3055 GEN6_RP_MEDIA_IS_GFX |
3056 GEN6_RP_ENABLE |
3057 GEN6_RP_UP_BUSY_AVG |
3058 GEN6_RP_DOWN_IDLE_AVG);
3059 break;
3060
3061 case BETWEEN:
3062 /* Upclock if more than 90% busy over 13ms */
3063 I915_WRITE(GEN6_RP_UP_EI, 10250);
3064 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3065
3066 /* Downclock if less than 75% busy over 32ms */
3067 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3068 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3069
3070 I915_WRITE(GEN6_RP_CONTROL,
3071 GEN6_RP_MEDIA_TURBO |
3072 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3073 GEN6_RP_MEDIA_IS_GFX |
3074 GEN6_RP_ENABLE |
3075 GEN6_RP_UP_BUSY_AVG |
3076 GEN6_RP_DOWN_IDLE_AVG);
3077 break;
3078
3079 case HIGH_POWER:
3080 /* Upclock if more than 85% busy over 10ms */
3081 I915_WRITE(GEN6_RP_UP_EI, 8000);
3082 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3083
3084 /* Downclock if less than 60% busy over 32ms */
3085 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3086 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3087
3088 I915_WRITE(GEN6_RP_CONTROL,
3089 GEN6_RP_MEDIA_TURBO |
3090 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3091 GEN6_RP_MEDIA_IS_GFX |
3092 GEN6_RP_ENABLE |
3093 GEN6_RP_UP_BUSY_AVG |
3094 GEN6_RP_DOWN_IDLE_AVG);
3095 break;
3096 }
3097
3098 dev_priv->rps.power = new_power;
3099 dev_priv->rps.last_adj = 0;
3100}
3101
2876ce73
CW		 3102static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3103{
3104 u32 mask = 0;
3105
3106 if (val > dev_priv->rps.min_freq_softlimit)
3107 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3108 if (val < dev_priv->rps.max_freq_softlimit)
3109 mask |= GEN6_PM_RP_UP_THRESHOLD;
3110
3111 /* IVB and SNB hard hangs on looping batchbuffer
3112 * if GEN6_PM_UP_EI_EXPIRED is masked.
3113 */
3114 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3115 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3116
baccd458
D		 3117 if (IS_GEN8(dev_priv->dev))
3118 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3119
2876ce73
CW		 3120 return ~mask;
3121}
3122
b8a5ff8d
JM		 3123/* gen6_set_rps is called to update the frequency request, but should also be
3124 * called when the range (min_delay and max_delay) is modified so that we can
3125 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
20b46e59
DV		 3126void gen6_set_rps(struct drm_device *dev, u8 val)
3127{
3128 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3129
4fc688ce 3130 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3131 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3132 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
004777cb 3133
eb64cad1
CW		 3134 /* min/max delay may still have been modified so be sure to
3135 * write the limits value.
3136 */
3137 if (val != dev_priv->rps.cur_freq) {
3138 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3139
50e6a2a7 3140 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3141 I915_WRITE(GEN6_RPNSWREQ,
3142 HSW_FREQUENCY(val));
3143 else
3144 I915_WRITE(GEN6_RPNSWREQ,
3145 GEN6_FREQUENCY(val) |
3146 GEN6_OFFSET(0) |
3147 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3148 }
7b9e0ae6 3149
7b9e0ae6
CW		 3150 /* Make sure we continue to get interrupts
3151 * until we hit the minimum or maximum frequencies.
3152 */
eb64cad1 3153 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
2876ce73 3154 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3155
d5570a72
BW		 3156 POSTING_READ(GEN6_RPNSWREQ);
3157
b39fb297 3158 dev_priv->rps.cur_freq = val;
be2cde9a 3159 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3160}
3161
76c3552f
D		 3162/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3163 *
3164 * * If Gfx is Idle, then
3165 * 1. Mask Turbo interrupts
3166 * 2. Bring up Gfx clock
3167 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3168 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3169 * 5. Unmask Turbo interrupts
3170*/
3171static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3172{
3173 /*
3174 * When we are idle. Drop to min voltage state.
3175 */
3176
b39fb297 3177 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
76c3552f
D		 3178 return;
3179
3180 /* Mask turbo interrupt so that they will not come in between */
3181 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3182
650ad970 3183 vlv_force_gfx_clock(dev_priv, true);
76c3552f 3184
b39fb297 3185 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
76c3552f
D		 3186
3187 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
b39fb297 3188 dev_priv->rps.min_freq_softlimit);
76c3552f
D		 3189
3190 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3191 & GENFREQSTATUS) == 0, 5))
3192 DRM_ERROR("timed out waiting for Punit\n");
3193
650ad970 3194 vlv_force_gfx_clock(dev_priv, false);
76c3552f 3195
2876ce73
CW		 3196 I915_WRITE(GEN6_PMINTRMSK,
3197 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
76c3552f
D		 3198}
3199
b29c19b6
CW		 3200void gen6_rps_idle(struct drm_i915_private *dev_priv)
3201{
691bb717
DL		 3202 struct drm_device *dev = dev_priv->dev;
3203
b29c19b6 3204 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3205 if (dev_priv->rps.enabled) {
691bb717 3206 if (IS_VALLEYVIEW(dev))
76c3552f 3207 vlv_set_rps_idle(dev_priv);
c0951f0c 3208 else
b39fb297 3209 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
c0951f0c
CW		 3210 dev_priv->rps.last_adj = 0;
3211 }
b29c19b6
CW		 3212 mutex_unlock(&dev_priv->rps.hw_lock);
3213}
3214
3215void gen6_rps_boost(struct drm_i915_private *dev_priv)
3216{
691bb717
DL		 3217 struct drm_device *dev = dev_priv->dev;
3218
b29c19b6 3219 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3220 if (dev_priv->rps.enabled) {
691bb717 3221 if (IS_VALLEYVIEW(dev))
b39fb297 3222 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c 3223 else
b39fb297 3224 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 3225 dev_priv->rps.last_adj = 0;
3226 }
b29c19b6
CW		 3227 mutex_unlock(&dev_priv->rps.hw_lock);
3228}
3229
0a073b84
JB		 3230void valleyview_set_rps(struct drm_device *dev, u8 val)
3231{
3232 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3233
0a073b84 3234 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
b39fb297
BW		 3235 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3236 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
0a073b84 3237
73008b98 3238 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
b39fb297
BW		 3239 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3240 dev_priv->rps.cur_freq,
2ec3815f 3241 vlv_gpu_freq(dev_priv, val), val);
0a073b84 3242
2876ce73
CW		 3243 if (val != dev_priv->rps.cur_freq)
3244 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3245
09c87db8 3246 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
0a073b84 3247
b39fb297 3248 dev_priv->rps.cur_freq = val;
2ec3815f 3249 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3250}
3251
0961021a
BW		 3252static void gen8_disable_rps_interrupts(struct drm_device *dev)
3253{
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255
992f191f 3256 I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
0961021a
BW		 3257 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3258 ~dev_priv->pm_rps_events);
3259 /* Complete PM interrupt masking here doesn't race with the rps work
3260 * item again unmasking PM interrupts because that is using a different
3261 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3262 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3263 * gen8_enable_rps will clean up. */
3264
3265 spin_lock_irq(&dev_priv->irq_lock);
3266 dev_priv->rps.pm_iir = 0;
3267 spin_unlock_irq(&dev_priv->irq_lock);
3268
3269 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3270}
3271
44fc7d5c 3272static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3273{
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275
2b4e57bd 3276 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
a6706b45
D		 3277 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3278 ~dev_priv->pm_rps_events);
2b4e57bd
ED		 3279 /* Complete PM interrupt masking here doesn't race with the rps work
3280 * item again unmasking PM interrupts because that is using a different
3281 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3282 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3283
59cdb63d 3284 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3285 dev_priv->rps.pm_iir = 0;
59cdb63d 3286 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3287
a6706b45 3288 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
2b4e57bd
ED		 3289}
3290
44fc7d5c 3291static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3292{
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294
3295 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3296 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3297
0961021a
BW		 3298 if (IS_BROADWELL(dev))
3299 gen8_disable_rps_interrupts(dev);
3300 else
3301 gen6_disable_rps_interrupts(dev);
44fc7d5c
DV		 3302}
3303
3304static void valleyview_disable_rps(struct drm_device *dev)
3305{
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307
3308 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3309
44fc7d5c 3310 gen6_disable_rps_interrupts(dev);
d20d4f0c
JB		 3311}
3312
dc39fff7
BW		 3313static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3314{
91ca689a
ID		 3315 if (IS_VALLEYVIEW(dev)) {
3316 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3317 mode = GEN6_RC_CTL_RC6_ENABLE;
3318 else
3319 mode = 0;
3320 }
dc39fff7 3321 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
1c79b42f
BW		 3322 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3323 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3324 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
dc39fff7
BW		 3325}
3326
e6069ca8 3327static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 3328{
eb4926e4
DL		 3329 /* No RC6 before Ironlake */
3330 if (INTEL_INFO(dev)->gen < 5)
3331 return 0;
3332
e6069ca8
ID		 3333 /* RC6 is only on Ironlake mobile not on desktop */
3334 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3335 return 0;
3336
456470eb 3337 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 3338 if (enable_rc6 >= 0) {
3339 int mask;
3340
3341 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3342 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3343 INTEL_RC6pp_ENABLE;
3344 else
3345 mask = INTEL_RC6_ENABLE;
3346
3347 if ((enable_rc6 & mask) != enable_rc6)
3348 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
8fd9c1a9 3349 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 3350
3351 return enable_rc6 & mask;
3352 }
2b4e57bd 3353
6567d748
CW		 3354 /* Disable RC6 on Ironlake */
3355 if (INTEL_INFO(dev)->gen == 5)
3356 return 0;
2b4e57bd 3357
8bade1ad 3358 if (IS_IVYBRIDGE(dev))
cca84a1f 3359 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 3360
3361 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 3362}
3363
e6069ca8
ID		 3364int intel_enable_rc6(const struct drm_device *dev)
3365{
3366 return i915.enable_rc6;
3367}
3368
0961021a
BW		 3369static void gen8_enable_rps_interrupts(struct drm_device *dev)
3370{
3371 struct drm_i915_private *dev_priv = dev->dev_private;
3372
3373 spin_lock_irq(&dev_priv->irq_lock);
3374 WARN_ON(dev_priv->rps.pm_iir);
3375 bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3376 I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3377 spin_unlock_irq(&dev_priv->irq_lock);
3378}
3379
44fc7d5c
DV		 3380static void gen6_enable_rps_interrupts(struct drm_device *dev)
3381{
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3385 WARN_ON(dev_priv->rps.pm_iir);
a6706b45
D		 3386 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3387 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
44fc7d5c 3388 spin_unlock_irq(&dev_priv->irq_lock);
44fc7d5c
DV		 3389}
3390
3280e8b0
BW		 3391static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3392{
3393 /* All of these values are in units of 50MHz */
3394 dev_priv->rps.cur_freq = 0;
3395 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3396 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3397 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3398 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3399 /* XXX: only BYT has a special efficient freq */
3400 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3401 /* hw_max = RP0 until we check for overclocking */
3402 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3403
3404 /* Preserve min/max settings in case of re-init */
3405 if (dev_priv->rps.max_freq_softlimit == 0)
3406 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3407
3408 if (dev_priv->rps.min_freq_softlimit == 0)
3409 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3410}
3411
6edee7f3
BW		 3412static void gen8_enable_rps(struct drm_device *dev)
3413{
3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415 struct intel_ring_buffer *ring;
3416 uint32_t rc6_mask = 0, rp_state_cap;
3417 int unused;
3418
3419 /* 1a: Software RC state - RC0 */
3420 I915_WRITE(GEN6_RC_STATE, 0);
3421
3422 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3423 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3424 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3425
3426 /* 2a: Disable RC states. */
3427 I915_WRITE(GEN6_RC_CONTROL, 0);
3428
3429 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0 3430 parse_rp_state_cap(dev_priv, rp_state_cap);
6edee7f3
BW		 3431
3432 /* 2b: Program RC6 thresholds.*/
3433 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3434 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3435 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3436 for_each_ring(ring, dev_priv, unused)
3437 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3438 I915_WRITE(GEN6_RC_SLEEP, 0);
3439 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3440
3441 /* 3: Enable RC6 */
3442 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3443 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 3444 intel_print_rc6_info(dev, rc6_mask);
6edee7f3 3445 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
abbf9d2c
BW		 3446 GEN6_RC_CTL_EI_MODE(1) |
3447 rc6_mask);
6edee7f3
BW		 3448
3449 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 3450 I915_WRITE(GEN6_RPNSWREQ,
3451 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3452 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3453 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
6edee7f3
BW		 3454 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3455 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3456
3457 /* Docs recommend 900MHz, and 300 MHz respectively */
3458 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
b39fb297
BW		 3459 dev_priv->rps.max_freq_softlimit << 24 |
3460 dev_priv->rps.min_freq_softlimit << 16);
6edee7f3
BW		 3461
3462 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3463 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3464 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3465 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3466
3467 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3468
3469 /* 5: Enable RPS */
3470 I915_WRITE(GEN6_RP_CONTROL,
3471 GEN6_RP_MEDIA_TURBO |
3472 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3473 GEN6_RP_MEDIA_IS_GFX |
3474 GEN6_RP_ENABLE |
3475 GEN6_RP_UP_BUSY_AVG |
3476 GEN6_RP_DOWN_IDLE_AVG);
3477
3478 /* 6: Ring frequency + overclocking (our driver does this later */
3479
3480 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3481
0961021a 3482 gen8_enable_rps_interrupts(dev);
6edee7f3 3483
c8d9a590 3484 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3485}
3486
79f5b2c7 3487static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3488{
79f5b2c7 3489 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3490 struct intel_ring_buffer *ring;
2a5913a8 3491 u32 rp_state_cap;
7b9e0ae6 3492 u32 gt_perf_status;
d060c169 3493 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 3494 u32 gtfifodbg;
2b4e57bd 3495 int rc6_mode;
42c0526c 3496 int i, ret;
2b4e57bd 3497
4fc688ce 3498 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3499
2b4e57bd
ED		 3500 /* Here begins a magic sequence of register writes to enable
3501 * auto-downclocking.
3502 *
3503 * Perhaps there might be some value in exposing these to
3504 * userspace...
3505 */
3506 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3507
3508 /* Clear the DBG now so we don't confuse earlier errors */
3509 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3510 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3511 I915_WRITE(GTFIFODBG, gtfifodbg);
3512 }
3513
c8d9a590 3514 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3515
7b9e0ae6
CW		 3516 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3517 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3518
3280e8b0 3519 parse_rp_state_cap(dev_priv, rp_state_cap);
dd0a1aa1 3520
2b4e57bd
ED		 3521 /* disable the counters and set deterministic thresholds */
3522 I915_WRITE(GEN6_RC_CONTROL, 0);
3523
3524 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3525 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3526 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3527 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3528 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3529
b4519513
CW		 3530 for_each_ring(ring, dev_priv, i)
3531 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3532
3533 I915_WRITE(GEN6_RC_SLEEP, 0);
3534 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3535 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3536 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3537 else
3538 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3539 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3540 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3541
5a7dc92a 3542 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3543 rc6_mode = intel_enable_rc6(dev_priv->dev);
3544 if (rc6_mode & INTEL_RC6_ENABLE)
3545 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3546
5a7dc92a
ED		 3547 /* We don't use those on Haswell */
3548 if (!IS_HASWELL(dev)) {
3549 if (rc6_mode & INTEL_RC6p_ENABLE)
3550 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3551
5a7dc92a
ED		 3552 if (rc6_mode & INTEL_RC6pp_ENABLE)
3553 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3554 }
2b4e57bd 3555
dc39fff7 3556 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3557
3558 I915_WRITE(GEN6_RC_CONTROL,
3559 rc6_mask |
3560 GEN6_RC_CTL_EI_MODE(1) |
3561 GEN6_RC_CTL_HW_ENABLE);
3562
dd75fdc8
CW		 3563 /* Power down if completely idle for over 50ms */
3564 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3565 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3566
42c0526c 3567 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 3568 if (ret)
42c0526c 3569 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 3570
3571 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3572 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3573 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 3574 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 3575 (pcu_mbox & 0xff) * 50);
b39fb297 3576 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 3577 }
3578
dd75fdc8 3579 dev_priv->rps.power = HIGH_POWER; /* force a reset */
b39fb297 3580 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
2b4e57bd 3581
44fc7d5c 3582 gen6_enable_rps_interrupts(dev);
2b4e57bd 3583
31643d54
BW		 3584 rc6vids = 0;
3585 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3586 if (IS_GEN6(dev) && ret) {
3587 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3588 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3589 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3590 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3591 rc6vids &= 0xffff00;
3592 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3593 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3594 if (ret)
3595 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3596 }
3597
c8d9a590 3598 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 3599}
3600
c2bc2fc5 3601static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3602{
79f5b2c7 3603 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3604 int min_freq = 15;
3ebecd07
CW		 3605 unsigned int gpu_freq;
3606 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3607 int scaling_factor = 180;
eda79642 3608 struct cpufreq_policy *policy;
2b4e57bd 3609
4fc688ce 3610 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3611
eda79642
BW		 3612 policy = cpufreq_cpu_get(0);
3613 if (policy) {
3614 max_ia_freq = policy->cpuinfo.max_freq;
3615 cpufreq_cpu_put(policy);
3616 } else {
3617 /*
3618 * Default to measured freq if none found, PCU will ensure we
3619 * don't go over
3620 */
2b4e57bd 3621 max_ia_freq = tsc_khz;
eda79642 3622 }
2b4e57bd
ED		 3623
3624 /* Convert from kHz to MHz */
3625 max_ia_freq /= 1000;
3626
153b4b95 3627 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3628 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3629 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3630
2b4e57bd
ED		 3631 /*
3632 * For each potential GPU frequency, load a ring frequency we'd like
3633 * to use for memory access. We do this by specifying the IA frequency
3634 * the PCU should use as a reference to determine the ring frequency.
3635 */
b39fb297 3636 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
2b4e57bd 3637 gpu_freq--) {
b39fb297 3638 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3ebecd07
CW		 3639 unsigned int ia_freq = 0, ring_freq = 0;
3640
46c764d4
BW		 3641 if (INTEL_INFO(dev)->gen >= 8) {
3642 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3643 ring_freq = max(min_ring_freq, gpu_freq);
3644 } else if (IS_HASWELL(dev)) {
f6aca45c 3645 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3646 ring_freq = max(min_ring_freq, ring_freq);
3647 /* leave ia_freq as the default, chosen by cpufreq */
3648 } else {
3649 /* On older processors, there is no separate ring
3650 * clock domain, so in order to boost the bandwidth
3651 * of the ring, we need to upclock the CPU (ia_freq).
3652 *
3653 * For GPU frequencies less than 750MHz,
3654 * just use the lowest ring freq.
3655 */
3656 if (gpu_freq < min_freq)
3657 ia_freq = 800;
3658 else
3659 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3660 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3661 }
2b4e57bd 3662
42c0526c
BW		 3663 sandybridge_pcode_write(dev_priv,
3664 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3665 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3666 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3667 gpu_freq);
2b4e57bd 3668 }
2b4e57bd
ED		 3669}
3670
c2bc2fc5
ID		 3671void gen6_update_ring_freq(struct drm_device *dev)
3672{
3673 struct drm_i915_private *dev_priv = dev->dev_private;
3674
3675 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3676 return;
3677
3678 mutex_lock(&dev_priv->rps.hw_lock);
3679 __gen6_update_ring_freq(dev);
3680 mutex_unlock(&dev_priv->rps.hw_lock);
3681}
3682
0a073b84
JB		 3683int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3684{
3685 u32 val, rp0;
3686
64936258 3687 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3688
3689 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3690 /* Clamp to max */
3691 rp0 = min_t(u32, rp0, 0xea);
3692
3693 return rp0;
3694}
3695
3696static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3697{
3698 u32 val, rpe;
3699
64936258 3700 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3701 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3702 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3703 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3704
3705 return rpe;
3706}
3707
3708int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3709{
64936258 3710 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3711}
3712
ae48434c
ID		 3713/* Check that the pctx buffer wasn't move under us. */
3714static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3715{
3716 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3717
3718 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3719 dev_priv->vlv_pctx->stolen->start);
3720}
3721
c9cddffc
JB		 3722static void valleyview_setup_pctx(struct drm_device *dev)
3723{
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct drm_i915_gem_object *pctx;
3726 unsigned long pctx_paddr;
3727 u32 pcbr;
3728 int pctx_size = 24*1024;
3729
17b0c1f7
ID		 3730 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3731
c9cddffc
JB		 3732 pcbr = I915_READ(VLV_PCBR);
3733 if (pcbr) {
3734 /* BIOS set it up already, grab the pre-alloc'd space */
3735 int pcbr_offset;
3736
3737 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3738 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3739 pcbr_offset,
190d6cd5 3740 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3741 pctx_size);
3742 goto out;
3743 }
3744
3745 /*
3746 * From the Gunit register HAS:
3747 * The Gfx driver is expected to program this register and ensure
3748 * proper allocation within Gfx stolen memory. For example, this
3749 * register should be programmed such than the PCBR range does not
3750 * overlap with other ranges, such as the frame buffer, protected
3751 * memory, or any other relevant ranges.
3752 */
3753 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3754 if (!pctx) {
3755 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3756 return;
3757 }
3758
3759 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3760 I915_WRITE(VLV_PCBR, pctx_paddr);
3761
3762out:
3763 dev_priv->vlv_pctx = pctx;
3764}
3765
ae48434c
ID		 3766static void valleyview_cleanup_pctx(struct drm_device *dev)
3767{
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769
3770 if (WARN_ON(!dev_priv->vlv_pctx))
3771 return;
3772
3773 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3774 dev_priv->vlv_pctx = NULL;
3775}
3776
4e80519e
ID		 3777static void valleyview_init_gt_powersave(struct drm_device *dev)
3778{
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780
3781 valleyview_setup_pctx(dev);
3782
3783 mutex_lock(&dev_priv->rps.hw_lock);
3784
3785 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3786 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3787 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3788 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3789 dev_priv->rps.max_freq);
3790
3791 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3792 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3793 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3794 dev_priv->rps.efficient_freq);
3795
3796 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3797 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3798 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3799 dev_priv->rps.min_freq);
3800
3801 /* Preserve min/max settings in case of re-init */
3802 if (dev_priv->rps.max_freq_softlimit == 0)
3803 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3804
3805 if (dev_priv->rps.min_freq_softlimit == 0)
3806 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3807
3808 mutex_unlock(&dev_priv->rps.hw_lock);
3809}
3810
3811static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3812{
3813 valleyview_cleanup_pctx(dev);
3814}
3815
0a073b84
JB		 3816static void valleyview_enable_rps(struct drm_device *dev)
3817{
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 struct intel_ring_buffer *ring;
2a5913a8 3820 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3821 int i;
3822
3823 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3824
ae48434c
ID		 3825 valleyview_check_pctx(dev_priv);
3826
0a073b84 3827 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3828 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3829 gtfifodbg);
0a073b84
JB		 3830 I915_WRITE(GTFIFODBG, gtfifodbg);
3831 }
3832
c8d9a590
D		 3833 /* If VLV, Forcewake all wells, else re-direct to regular path */
3834 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3835
3836 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3837 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3838 I915_WRITE(GEN6_RP_UP_EI, 66000);
3839 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3840
3841 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3842
3843 I915_WRITE(GEN6_RP_CONTROL,
3844 GEN6_RP_MEDIA_TURBO |
3845 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3846 GEN6_RP_MEDIA_IS_GFX |
3847 GEN6_RP_ENABLE |
3848 GEN6_RP_UP_BUSY_AVG |
3849 GEN6_RP_DOWN_IDLE_CONT);
3850
3851 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3852 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3853 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3854
3855 for_each_ring(ring, dev_priv, i)
3856 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3857
2f0aa304 3858 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 3859
3860 /* allows RC6 residency counter to work */
49798eb2
JB		 3861 I915_WRITE(VLV_COUNTER_CONTROL,
3862 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3863 VLV_MEDIA_RC6_COUNT_EN |
3864 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 3865 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 3866 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 3867
3868 intel_print_rc6_info(dev, rc6_mode);
3869
a2b23fe0 3870 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3871
64936258 3872 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 3873
3874 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3875 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3876
b39fb297 3877 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 3878 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
b39fb297
BW		 3879 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3880 dev_priv->rps.cur_freq);
0a073b84 3881
73008b98 3882 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
b39fb297
BW		 3883 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3884 dev_priv->rps.efficient_freq);
0a073b84 3885
b39fb297 3886 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 3887
44fc7d5c 3888 gen6_enable_rps_interrupts(dev);
0a073b84 3889
c8d9a590 3890 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 3891}
3892
930ebb46 3893void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3894{
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896
3e373948 3897 if (dev_priv->ips.renderctx) {
d7f46fc4 3898 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3e373948
DV		 3899 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3900 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3901 }
3902
3e373948 3903 if (dev_priv->ips.pwrctx) {
d7f46fc4 3904 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3e373948
DV		 3905 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3906 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3907 }
3908}
3909
930ebb46 3910static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3911{
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913
3914 if (I915_READ(PWRCTXA)) {
3915 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3916 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3917 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3918 50);
3919
3920 I915_WRITE(PWRCTXA, 0);
3921 POSTING_READ(PWRCTXA);
3922
3923 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3924 POSTING_READ(RSTDBYCTL);
3925 }
2b4e57bd
ED		 3926}
3927
3928static int ironlake_setup_rc6(struct drm_device *dev)
3929{
3930 struct drm_i915_private *dev_priv = dev->dev_private;
3931
3e373948
DV		 3932 if (dev_priv->ips.renderctx == NULL)
3933 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3934 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3935 return -ENOMEM;
3936
3e373948
DV		 3937 if (dev_priv->ips.pwrctx == NULL)
3938 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3939 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3940 ironlake_teardown_rc6(dev);
3941 return -ENOMEM;
3942 }
3943
3944 return 0;
3945}
3946
930ebb46 3947static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3948{
3949 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3950 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3951 bool was_interruptible;
2b4e57bd
ED		 3952 int ret;
3953
3954 /* rc6 disabled by default due to repeated reports of hanging during
3955 * boot and resume.
3956 */
3957 if (!intel_enable_rc6(dev))
3958 return;
3959
79f5b2c7
DV		 3960 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3961
2b4e57bd 3962 ret = ironlake_setup_rc6(dev);
79f5b2c7 3963 if (ret)
2b4e57bd 3964 return;
2b4e57bd 3965
3e960501
CW		 3966 was_interruptible = dev_priv->mm.interruptible;
3967 dev_priv->mm.interruptible = false;
3968
2b4e57bd
ED		 3969 /*
3970 * GPU can automatically power down the render unit if given a page
3971 * to save state.
3972 */
6d90c952 3973 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3974 if (ret) {
3975 ironlake_teardown_rc6(dev);
3e960501 3976 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3977 return;
3978 }
3979
6d90c952
DV		 3980 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3981 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3982 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3983 MI_MM_SPACE_GTT |
3984 MI_SAVE_EXT_STATE_EN |
3985 MI_RESTORE_EXT_STATE_EN |
3986 MI_RESTORE_INHIBIT);
3987 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3988 intel_ring_emit(ring, MI_NOOP);
3989 intel_ring_emit(ring, MI_FLUSH);
3990 intel_ring_advance(ring);
2b4e57bd
ED		 3991
3992 /*
3993 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3994 * does an implicit flush, combined with MI_FLUSH above, it should be
3995 * safe to assume that renderctx is valid
3996 */
3e960501
CW		 3997 ret = intel_ring_idle(ring);
3998 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3999 if (ret) {
def27a58 4000 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4001 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4002 return;
4003 }
4004
f343c5f6 4005 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4006 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7 4007
91ca689a 4008 intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
2b4e57bd
ED		 4009}
4010
dde18883
ED		 4011static unsigned long intel_pxfreq(u32 vidfreq)
4012{
4013 unsigned long freq;
4014 int div = (vidfreq & 0x3f0000) >> 16;
4015 int post = (vidfreq & 0x3000) >> 12;
4016 int pre = (vidfreq & 0x7);
4017
4018 if (!pre)
4019 return 0;
4020
4021 freq = ((div * 133333) / ((1<<post) * pre));
4022
4023 return freq;
4024}
4025
eb48eb00
DV		 4026static const struct cparams {
4027 u16 i;
4028 u16 t;
4029 u16 m;
4030 u16 c;
4031} cparams[] = {
4032 { 1, 1333, 301, 28664 },
4033 { 1, 1066, 294, 24460 },
4034 { 1, 800, 294, 25192 },
4035 { 0, 1333, 276, 27605 },
4036 { 0, 1066, 276, 27605 },
4037 { 0, 800, 231, 23784 },
4038};
4039
f531dcb2 4040static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4041{
4042 u64 total_count, diff, ret;
4043 u32 count1, count2, count3, m = 0, c = 0;
4044 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4045 int i;
4046
02d71956
DV		 4047 assert_spin_locked(&mchdev_lock);
4048
20e4d407 4049 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4050
4051 /* Prevent division-by-zero if we are asking too fast.
4052 * Also, we don't get interesting results if we are polling
4053 * faster than once in 10ms, so just return the saved value
4054 * in such cases.
4055 */
4056 if (diff1 <= 10)
20e4d407 4057 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4058
4059 count1 = I915_READ(DMIEC);
4060 count2 = I915_READ(DDREC);
4061 count3 = I915_READ(CSIEC);
4062
4063 total_count = count1 + count2 + count3;
4064
4065 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4066 if (total_count < dev_priv->ips.last_count1) {
4067 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4068 diff += total_count;
4069 } else {
20e4d407 4070 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4071 }
4072
4073 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4074 if (cparams[i].i == dev_priv->ips.c_m &&
4075 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4076 m = cparams[i].m;
4077 c = cparams[i].c;
4078 break;
4079 }
4080 }
4081
4082 diff = div_u64(diff, diff1);
4083 ret = ((m * diff) + c);
4084 ret = div_u64(ret, 10);
4085
20e4d407
DV		 4086 dev_priv->ips.last_count1 = total_count;
4087 dev_priv->ips.last_time1 = now;
eb48eb00 4088
20e4d407 4089 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4090
4091 return ret;
4092}
4093
f531dcb2
CW		 4094unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4095{
3d13ef2e 4096 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4097 unsigned long val;
4098
3d13ef2e 4099 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4100 return 0;
4101
4102 spin_lock_irq(&mchdev_lock);
4103
4104 val = __i915_chipset_val(dev_priv);
4105
4106 spin_unlock_irq(&mchdev_lock);
4107
4108 return val;
4109}
4110
eb48eb00
DV		 4111unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4112{
4113 unsigned long m, x, b;
4114 u32 tsfs;
4115
4116 tsfs = I915_READ(TSFS);
4117
4118 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4119 x = I915_READ8(TR1);
4120
4121 b = tsfs & TSFS_INTR_MASK;
4122
4123 return ((m * x) / 127) - b;
4124}
4125
4126static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4127{
3d13ef2e 4128 struct drm_device *dev = dev_priv->dev;
eb48eb00
DV		 4129 static const struct v_table {
4130 u16 vd; /* in .1 mil */
4131 u16 vm; /* in .1 mil */
4132 } v_table[] = {
4133 { 0, 0, },
4134 { 375, 0, },
4135 { 500, 0, },
4136 { 625, 0, },
4137 { 750, 0, },
4138 { 875, 0, },
4139 { 1000, 0, },
4140 { 1125, 0, },
4141 { 4125, 3000, },
4142 { 4125, 3000, },
4143 { 4125, 3000, },
4144 { 4125, 3000, },
4145 { 4125, 3000, },
4146 { 4125, 3000, },
4147 { 4125, 3000, },
4148 { 4125, 3000, },
4149 { 4125, 3000, },
4150 { 4125, 3000, },
4151 { 4125, 3000, },
4152 { 4125, 3000, },
4153 { 4125, 3000, },
4154 { 4125, 3000, },
4155 { 4125, 3000, },
4156 { 4125, 3000, },
4157 { 4125, 3000, },
4158 { 4125, 3000, },
4159 { 4125, 3000, },
4160 { 4125, 3000, },
4161 { 4125, 3000, },
4162 { 4125, 3000, },
4163 { 4125, 3000, },
4164 { 4125, 3000, },
4165 { 4250, 3125, },
4166 { 4375, 3250, },
4167 { 4500, 3375, },
4168 { 4625, 3500, },
4169 { 4750, 3625, },
4170 { 4875, 3750, },
4171 { 5000, 3875, },
4172 { 5125, 4000, },
4173 { 5250, 4125, },
4174 { 5375, 4250, },
4175 { 5500, 4375, },
4176 { 5625, 4500, },
4177 { 5750, 4625, },
4178 { 5875, 4750, },
4179 { 6000, 4875, },
4180 { 6125, 5000, },
4181 { 6250, 5125, },
4182 { 6375, 5250, },
4183 { 6500, 5375, },
4184 { 6625, 5500, },
4185 { 6750, 5625, },
4186 { 6875, 5750, },
4187 { 7000, 5875, },
4188 { 7125, 6000, },
4189 { 7250, 6125, },
4190 { 7375, 6250, },
4191 { 7500, 6375, },
4192 { 7625, 6500, },
4193 { 7750, 6625, },
4194 { 7875, 6750, },
4195 { 8000, 6875, },
4196 { 8125, 7000, },
4197 { 8250, 7125, },
4198 { 8375, 7250, },
4199 { 8500, 7375, },
4200 { 8625, 7500, },
4201 { 8750, 7625, },
4202 { 8875, 7750, },
4203 { 9000, 7875, },
4204 { 9125, 8000, },
4205 { 9250, 8125, },
4206 { 9375, 8250, },
4207 { 9500, 8375, },
4208 { 9625, 8500, },
4209 { 9750, 8625, },
4210 { 9875, 8750, },
4211 { 10000, 8875, },
4212 { 10125, 9000, },
4213 { 10250, 9125, },
4214 { 10375, 9250, },
4215 { 10500, 9375, },
4216 { 10625, 9500, },
4217 { 10750, 9625, },
4218 { 10875, 9750, },
4219 { 11000, 9875, },
4220 { 11125, 10000, },
4221 { 11250, 10125, },
4222 { 11375, 10250, },
4223 { 11500, 10375, },
4224 { 11625, 10500, },
4225 { 11750, 10625, },
4226 { 11875, 10750, },
4227 { 12000, 10875, },
4228 { 12125, 11000, },
4229 { 12250, 11125, },
4230 { 12375, 11250, },
4231 { 12500, 11375, },
4232 { 12625, 11500, },
4233 { 12750, 11625, },
4234 { 12875, 11750, },
4235 { 13000, 11875, },
4236 { 13125, 12000, },
4237 { 13250, 12125, },
4238 { 13375, 12250, },
4239 { 13500, 12375, },
4240 { 13625, 12500, },
4241 { 13750, 12625, },
4242 { 13875, 12750, },
4243 { 14000, 12875, },
4244 { 14125, 13000, },
4245 { 14250, 13125, },
4246 { 14375, 13250, },
4247 { 14500, 13375, },
4248 { 14625, 13500, },
4249 { 14750, 13625, },
4250 { 14875, 13750, },
4251 { 15000, 13875, },
4252 { 15125, 14000, },
4253 { 15250, 14125, },
4254 { 15375, 14250, },
4255 { 15500, 14375, },
4256 { 15625, 14500, },
4257 { 15750, 14625, },
4258 { 15875, 14750, },
4259 { 16000, 14875, },
4260 { 16125, 15000, },
4261 };
3d13ef2e 4262 if (INTEL_INFO(dev)->is_mobile)
eb48eb00
DV		 4263 return v_table[pxvid].vm;
4264 else
4265 return v_table[pxvid].vd;
4266}
4267
02d71956 4268static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4269{
4270 struct timespec now, diff1;
4271 u64 diff;
4272 unsigned long diffms;
4273 u32 count;
4274
02d71956 4275 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4276
4277 getrawmonotonic(&now);
20e4d407 4278 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4279
4280 /* Don't divide by 0 */
4281 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4282 if (!diffms)
4283 return;
4284
4285 count = I915_READ(GFXEC);
4286
20e4d407
DV		 4287 if (count < dev_priv->ips.last_count2) {
4288 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4289 diff += count;
4290 } else {
20e4d407 4291 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4292 }
4293
20e4d407
DV		 4294 dev_priv->ips.last_count2 = count;
4295 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4296
4297 /* More magic constants... */
4298 diff = diff * 1181;
4299 diff = div_u64(diff, diffms * 10);
20e4d407 4300 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4301}
4302
02d71956
DV		 4303void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4304{
3d13ef2e
DL		 4305 struct drm_device *dev = dev_priv->dev;
4306
4307 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 4308 return;
4309
9270388e 4310 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4311
4312 __i915_update_gfx_val(dev_priv);
4313
9270388e 4314 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4315}
4316
f531dcb2 4317static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4318{
4319 unsigned long t, corr, state1, corr2, state2;
4320 u32 pxvid, ext_v;
4321
02d71956
DV		 4322 assert_spin_locked(&mchdev_lock);
4323
b39fb297 4324 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 4325 pxvid = (pxvid >> 24) & 0x7f;
4326 ext_v = pvid_to_extvid(dev_priv, pxvid);
4327
4328 state1 = ext_v;
4329
4330 t = i915_mch_val(dev_priv);
4331
4332 /* Revel in the empirically derived constants */
4333
4334 /* Correction factor in 1/100000 units */
4335 if (t > 80)
4336 corr = ((t * 2349) + 135940);
4337 else if (t >= 50)
4338 corr = ((t * 964) + 29317);
4339 else /* < 50 */
4340 corr = ((t * 301) + 1004);
4341
4342 corr = corr * ((150142 * state1) / 10000 - 78642);
4343 corr /= 100000;
20e4d407 4344 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4345
4346 state2 = (corr2 * state1) / 10000;
4347 state2 /= 100; /* convert to mW */
4348
02d71956 4349 __i915_update_gfx_val(dev_priv);
eb48eb00 4350
20e4d407 4351 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4352}
4353
f531dcb2
CW		 4354unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4355{
3d13ef2e 4356 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 4357 unsigned long val;
4358
3d13ef2e 4359 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 4360 return 0;
4361
4362 spin_lock_irq(&mchdev_lock);
4363
4364 val = __i915_gfx_val(dev_priv);
4365
4366 spin_unlock_irq(&mchdev_lock);
4367
4368 return val;
4369}
4370
eb48eb00
DV		 4371/**
4372 * i915_read_mch_val - return value for IPS use
4373 *
4374 * Calculate and return a value for the IPS driver to use when deciding whether
4375 * we have thermal and power headroom to increase CPU or GPU power budget.
4376 */
4377unsigned long i915_read_mch_val(void)
4378{
4379 struct drm_i915_private *dev_priv;
4380 unsigned long chipset_val, graphics_val, ret = 0;
4381
9270388e 4382 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4383 if (!i915_mch_dev)
4384 goto out_unlock;
4385 dev_priv = i915_mch_dev;
4386
f531dcb2
CW		 4387 chipset_val = __i915_chipset_val(dev_priv);
4388 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4389
4390 ret = chipset_val + graphics_val;
4391
4392out_unlock:
9270388e 4393 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4394
4395 return ret;
4396}
4397EXPORT_SYMBOL_GPL(i915_read_mch_val);
4398
4399/**
4400 * i915_gpu_raise - raise GPU frequency limit
4401 *
4402 * Raise the limit; IPS indicates we have thermal headroom.
4403 */
4404bool i915_gpu_raise(void)
4405{
4406 struct drm_i915_private *dev_priv;
4407 bool ret = true;
4408
9270388e 4409 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4410 if (!i915_mch_dev) {
4411 ret = false;
4412 goto out_unlock;
4413 }
4414 dev_priv = i915_mch_dev;
4415
20e4d407
DV		 4416 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4417 dev_priv->ips.max_delay--;
eb48eb00
DV		 4418
4419out_unlock:
9270388e 4420 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4421
4422 return ret;
4423}
4424EXPORT_SYMBOL_GPL(i915_gpu_raise);
4425
4426/**
4427 * i915_gpu_lower - lower GPU frequency limit
4428 *
4429 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4430 * frequency maximum.
4431 */
4432bool i915_gpu_lower(void)
4433{
4434 struct drm_i915_private *dev_priv;
4435 bool ret = true;
4436
9270388e 4437 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4438 if (!i915_mch_dev) {
4439 ret = false;
4440 goto out_unlock;
4441 }
4442 dev_priv = i915_mch_dev;
4443
20e4d407
DV		 4444 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4445 dev_priv->ips.max_delay++;
eb48eb00
DV		 4446
4447out_unlock:
9270388e 4448 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4449
4450 return ret;
4451}
4452EXPORT_SYMBOL_GPL(i915_gpu_lower);
4453
4454/**
4455 * i915_gpu_busy - indicate GPU business to IPS
4456 *
4457 * Tell the IPS driver whether or not the GPU is busy.
4458 */
4459bool i915_gpu_busy(void)
4460{
4461 struct drm_i915_private *dev_priv;
f047e395 4462 struct intel_ring_buffer *ring;
eb48eb00 4463 bool ret = false;
f047e395 4464 int i;
eb48eb00 4465
9270388e 4466 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4467 if (!i915_mch_dev)
4468 goto out_unlock;
4469 dev_priv = i915_mch_dev;
4470
f047e395
CW		 4471 for_each_ring(ring, dev_priv, i)
4472 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4473
4474out_unlock:
9270388e 4475 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4476
4477 return ret;
4478}
4479EXPORT_SYMBOL_GPL(i915_gpu_busy);
4480
4481/**
4482 * i915_gpu_turbo_disable - disable graphics turbo
4483 *
4484 * Disable graphics turbo by resetting the max frequency and setting the
4485 * current frequency to the default.
4486 */
4487bool i915_gpu_turbo_disable(void)
4488{
4489 struct drm_i915_private *dev_priv;
4490 bool ret = true;
4491
9270388e 4492 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4493 if (!i915_mch_dev) {
4494 ret = false;
4495 goto out_unlock;
4496 }
4497 dev_priv = i915_mch_dev;
4498
20e4d407 4499 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4500
20e4d407 4501 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4502 ret = false;
4503
4504out_unlock:
9270388e 4505 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4506
4507 return ret;
4508}
4509EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4510
4511/**
4512 * Tells the intel_ips driver that the i915 driver is now loaded, if
4513 * IPS got loaded first.
4514 *
4515 * This awkward dance is so that neither module has to depend on the
4516 * other in order for IPS to do the appropriate communication of
4517 * GPU turbo limits to i915.
4518 */
4519static void
4520ips_ping_for_i915_load(void)
4521{
4522 void (*link)(void);
4523
4524 link = symbol_get(ips_link_to_i915_driver);
4525 if (link) {
4526 link();
4527 symbol_put(ips_link_to_i915_driver);
4528 }
4529}
4530
4531void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4532{
02d71956
DV		 4533 /* We only register the i915 ips part with intel-ips once everything is
4534 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4535 spin_lock_irq(&mchdev_lock);
eb48eb00 4536 i915_mch_dev = dev_priv;
9270388e 4537 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4538
4539 ips_ping_for_i915_load();
4540}
4541
4542void intel_gpu_ips_teardown(void)
4543{
9270388e 4544 spin_lock_irq(&mchdev_lock);
eb48eb00 4545 i915_mch_dev = NULL;
9270388e 4546 spin_unlock_irq(&mchdev_lock);
eb48eb00 4547}
76c3552f 4548
8090c6b9 4549static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4550{
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 u32 lcfuse;
4553 u8 pxw[16];
4554 int i;
4555
4556 /* Disable to program */
4557 I915_WRITE(ECR, 0);
4558 POSTING_READ(ECR);
4559
4560 /* Program energy weights for various events */
4561 I915_WRITE(SDEW, 0x15040d00);
4562 I915_WRITE(CSIEW0, 0x007f0000);
4563 I915_WRITE(CSIEW1, 0x1e220004);
4564 I915_WRITE(CSIEW2, 0x04000004);
4565
4566 for (i = 0; i < 5; i++)
4567 I915_WRITE(PEW + (i * 4), 0);
4568 for (i = 0; i < 3; i++)
4569 I915_WRITE(DEW + (i * 4), 0);
4570
4571 /* Program P-state weights to account for frequency power adjustment */
4572 for (i = 0; i < 16; i++) {
4573 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4574 unsigned long freq = intel_pxfreq(pxvidfreq);
4575 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4576 PXVFREQ_PX_SHIFT;
4577 unsigned long val;
4578
4579 val = vid * vid;
4580 val *= (freq / 1000);
4581 val *= 255;
4582 val /= (127*127*900);
4583 if (val > 0xff)
4584 DRM_ERROR("bad pxval: %ld\n", val);
4585 pxw[i] = val;
4586 }
4587 /* Render standby states get 0 weight */
4588 pxw[14] = 0;
4589 pxw[15] = 0;
4590
4591 for (i = 0; i < 4; i++) {
4592 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4593 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4594 I915_WRITE(PXW + (i * 4), val);
4595 }
4596
4597 /* Adjust magic regs to magic values (more experimental results) */
4598 I915_WRITE(OGW0, 0);
4599 I915_WRITE(OGW1, 0);
4600 I915_WRITE(EG0, 0x00007f00);
4601 I915_WRITE(EG1, 0x0000000e);
4602 I915_WRITE(EG2, 0x000e0000);
4603 I915_WRITE(EG3, 0x68000300);
4604 I915_WRITE(EG4, 0x42000000);
4605 I915_WRITE(EG5, 0x00140031);
4606 I915_WRITE(EG6, 0);
4607 I915_WRITE(EG7, 0);
4608
4609 for (i = 0; i < 8; i++)
4610 I915_WRITE(PXWL + (i * 4), 0);
4611
4612 /* Enable PMON + select events */
4613 I915_WRITE(ECR, 0x80000019);
4614
4615 lcfuse = I915_READ(LCFUSE02);
4616
20e4d407 4617 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4618}
4619
ae48434c
ID		 4620void intel_init_gt_powersave(struct drm_device *dev)
4621{
e6069ca8
ID		 4622 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4623
ae48434c 4624 if (IS_VALLEYVIEW(dev))
4e80519e 4625 valleyview_init_gt_powersave(dev);
ae48434c
ID		 4626}
4627
4628void intel_cleanup_gt_powersave(struct drm_device *dev)
4629{
4630 if (IS_VALLEYVIEW(dev))
4e80519e 4631 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 4632}
4633
8090c6b9
DV		 4634void intel_disable_gt_powersave(struct drm_device *dev)
4635{
1a01ab3b
JB		 4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637
fd0c0642
DV		 4638 /* Interrupts should be disabled already to avoid re-arming. */
4639 WARN_ON(dev->irq_enabled);
4640
930ebb46 4641 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4642 ironlake_disable_drps(dev);
930ebb46 4643 ironlake_disable_rc6(dev);
b7bb2439 4644 } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
1a01ab3b 4645 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4646 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4647 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4648 if (IS_VALLEYVIEW(dev))
4649 valleyview_disable_rps(dev);
4650 else
4651 gen6_disable_rps(dev);
c0951f0c 4652 dev_priv->rps.enabled = false;
4fc688ce 4653 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4654 }
8090c6b9
DV		 4655}
4656
1a01ab3b
JB		 4657static void intel_gen6_powersave_work(struct work_struct *work)
4658{
4659 struct drm_i915_private *dev_priv =
4660 container_of(work, struct drm_i915_private,
4661 rps.delayed_resume_work.work);
4662 struct drm_device *dev = dev_priv->dev;
4663
4fc688ce 4664 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4665
4666 if (IS_VALLEYVIEW(dev)) {
4667 valleyview_enable_rps(dev);
6edee7f3
BW		 4668 } else if (IS_BROADWELL(dev)) {
4669 gen8_enable_rps(dev);
c2bc2fc5 4670 __gen6_update_ring_freq(dev);
0a073b84
JB		 4671 } else {
4672 gen6_enable_rps(dev);
c2bc2fc5 4673 __gen6_update_ring_freq(dev);
0a073b84 4674 }
c0951f0c 4675 dev_priv->rps.enabled = true;
4fc688ce 4676 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 4677
4678 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 4679}
4680
8090c6b9
DV		 4681void intel_enable_gt_powersave(struct drm_device *dev)
4682{
1a01ab3b
JB		 4683 struct drm_i915_private *dev_priv = dev->dev_private;
4684
8090c6b9 4685 if (IS_IRONLAKE_M(dev)) {
dc1d0136 4686 mutex_lock(&dev->struct_mutex);
8090c6b9
DV		 4687 ironlake_enable_drps(dev);
4688 ironlake_enable_rc6(dev);
4689 intel_init_emon(dev);
dc1d0136 4690 mutex_unlock(&dev->struct_mutex);
b7bb2439 4691 } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
1a01ab3b
JB		 4692 /*
4693 * PCU communication is slow and this doesn't need to be
4694 * done at any specific time, so do this out of our fast path
4695 * to make resume and init faster.
c6df39b5
ID		 4696 *
4697 * We depend on the HW RC6 power context save/restore
4698 * mechanism when entering D3 through runtime PM suspend. So
4699 * disable RPM until RPS/RC6 is properly setup. We can only
4700 * get here via the driver load/system resume/runtime resume
4701 * paths, so the _noresume version is enough (and in case of
4702 * runtime resume it's necessary).
1a01ab3b 4703 */
c6df39b5
ID		 4704 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4705 round_jiffies_up_relative(HZ)))
4706 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 4707 }
4708}
4709
c6df39b5
ID		 4710void intel_reset_gt_powersave(struct drm_device *dev)
4711{
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4713
4714 dev_priv->rps.enabled = false;
4715 intel_enable_gt_powersave(dev);
4716}
4717
3107bd48
DV		 4718static void ibx_init_clock_gating(struct drm_device *dev)
4719{
4720 struct drm_i915_private *dev_priv = dev->dev_private;
4721
4722 /*
4723 * On Ibex Peak and Cougar Point, we need to disable clock
4724 * gating for the panel power sequencer or it will fail to
4725 * start up when no ports are active.
4726 */
4727 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4728}
4729
0e088b8f
VS		 4730static void g4x_disable_trickle_feed(struct drm_device *dev)
4731{
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 int pipe;
4734
4735 for_each_pipe(pipe) {
4736 I915_WRITE(DSPCNTR(pipe),
4737 I915_READ(DSPCNTR(pipe)) |
4738 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4739 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4740 }
4741}
4742
017636cc
VS		 4743static void ilk_init_lp_watermarks(struct drm_device *dev)
4744{
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746
4747 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4748 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4749 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4750
4751 /*
4752 * Don't touch WM1S_LP_EN here.
4753 * Doing so could cause underruns.
4754 */
4755}
4756
1fa61106 4757static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4758{
4759 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4760 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4761
f1e8fa56
DL		 4762 /*
4763 * Required for FBC
4764 * WaFbcDisableDpfcClockGating:ilk
4765 */
4d47e4f5
DL		 4766 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4767 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4768 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4769
4770 I915_WRITE(PCH_3DCGDIS0,
4771 MARIUNIT_CLOCK_GATE_DISABLE |
4772 SVSMUNIT_CLOCK_GATE_DISABLE);
4773 I915_WRITE(PCH_3DCGDIS1,
4774 VFMUNIT_CLOCK_GATE_DISABLE);
4775
6f1d69b0
ED		 4776 /*
4777 * According to the spec the following bits should be set in
4778 * order to enable memory self-refresh
4779 * The bit 22/21 of 0x42004
4780 * The bit 5 of 0x42020
4781 * The bit 15 of 0x45000
4782 */
4783 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4784 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4785 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4786 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4787 I915_WRITE(DISP_ARB_CTL,
4788 (I915_READ(DISP_ARB_CTL) |
4789 DISP_FBC_WM_DIS));
017636cc
VS		 4790
4791 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 4792
4793 /*
4794 * Based on the document from hardware guys the following bits
4795 * should be set unconditionally in order to enable FBC.
4796 * The bit 22 of 0x42000
4797 * The bit 22 of 0x42004
4798 * The bit 7,8,9 of 0x42020.
4799 */
4800 if (IS_IRONLAKE_M(dev)) {
4bb35334 4801 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4802 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4803 I915_READ(ILK_DISPLAY_CHICKEN1) |
4804 ILK_FBCQ_DIS);
4805 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4806 I915_READ(ILK_DISPLAY_CHICKEN2) |
4807 ILK_DPARB_GATE);
6f1d69b0
ED		 4808 }
4809
4d47e4f5
DL		 4810 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4811
6f1d69b0
ED		 4812 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4813 I915_READ(ILK_DISPLAY_CHICKEN2) |
4814 ILK_ELPIN_409_SELECT);
4815 I915_WRITE(_3D_CHICKEN2,
4816 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4817 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4818
ecdb4eb7 4819 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4820 I915_WRITE(CACHE_MODE_0,
4821 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4822
4e04632e
AG		 4823 /* WaDisable_RenderCache_OperationalFlush:ilk */
4824 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4825
0e088b8f 4826 g4x_disable_trickle_feed(dev);
bdad2b2f 4827
3107bd48
DV		 4828 ibx_init_clock_gating(dev);
4829}
4830
4831static void cpt_init_clock_gating(struct drm_device *dev)
4832{
4833 struct drm_i915_private *dev_priv = dev->dev_private;
4834 int pipe;
3f704fa2 4835 uint32_t val;
3107bd48
DV		 4836
4837 /*
4838 * On Ibex Peak and Cougar Point, we need to disable clock
4839 * gating for the panel power sequencer or it will fail to
4840 * start up when no ports are active.
4841 */
cd664078
JB		 4842 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4843 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4844 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 4845 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4846 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4847 /* The below fixes the weird display corruption, a few pixels shifted
4848 * downward, on (only) LVDS of some HP laptops with IVY.
4849 */
3f704fa2 4850 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4851 val = I915_READ(TRANS_CHICKEN2(pipe));
4852 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4853 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4854 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4855 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4856 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4857 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4858 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4859 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4860 }
3107bd48
DV		 4861 /* WADP0ClockGatingDisable */
4862 for_each_pipe(pipe) {
4863 I915_WRITE(TRANS_CHICKEN1(pipe),
4864 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4865 }
6f1d69b0
ED		 4866}
4867
1d7aaa0c
DV		 4868static void gen6_check_mch_setup(struct drm_device *dev)
4869{
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 uint32_t tmp;
4872
4873 tmp = I915_READ(MCH_SSKPD);
4874 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4875 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4876 DRM_INFO("This can cause pipe underruns and display issues.\n");
4877 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4878 }
4879}
4880
1fa61106 4881static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4882{
4883 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4884 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4885
231e54f6 4886 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4887
4888 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4889 I915_READ(ILK_DISPLAY_CHICKEN2) |
4890 ILK_ELPIN_409_SELECT);
4891
ecdb4eb7 4892 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4893 I915_WRITE(_3D_CHICKEN,
4894 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4895
ecdb4eb7 4896 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4897 if (IS_SNB_GT1(dev))
4898 I915_WRITE(GEN6_GT_MODE,
4899 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4900
4e04632e
AG		 4901 /* WaDisable_RenderCache_OperationalFlush:snb */
4902 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4903
8d85d272
VS		 4904 /*
4905 * BSpec recoomends 8x4 when MSAA is used,
4906 * however in practice 16x4 seems fastest.
c5c98a58
VS		 4907 *
4908 * Note that PS/WM thread counts depend on the WIZ hashing
4909 * disable bit, which we don't touch here, but it's good
4910 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 4911 */
4912 I915_WRITE(GEN6_GT_MODE,
4913 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4914
017636cc 4915 ilk_init_lp_watermarks(dev);
6f1d69b0 4916
6f1d69b0 4917 I915_WRITE(CACHE_MODE_0,
50743298 4918 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4919
4920 I915_WRITE(GEN6_UCGCTL1,
4921 I915_READ(GEN6_UCGCTL1) |
4922 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4923 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4924
4925 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4926 * gating disable must be set. Failure to set it results in
4927 * flickering pixels due to Z write ordering failures after
4928 * some amount of runtime in the Mesa "fire" demo, and Unigine
4929 * Sanctuary and Tropics, and apparently anything else with
4930 * alpha test or pixel discard.
4931 *
4932 * According to the spec, bit 11 (RCCUNIT) must also be set,
4933 * but we didn't debug actual testcases to find it out.
0f846f81 4934 *
ef59318c
VS		 4935 * WaDisableRCCUnitClockGating:snb
4936 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 4937 */
4938 I915_WRITE(GEN6_UCGCTL2,
4939 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4940 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4941
5eb146dd 4942 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 4943 I915_WRITE(_3D_CHICKEN3,
4944 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 4945
e927ecde
VS		 4946 /*
4947 * Bspec says:
4948 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4949 * 3DSTATE_SF number of SF output attributes is more than 16."
4950 */
4951 I915_WRITE(_3D_CHICKEN3,
4952 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4953
6f1d69b0
ED		 4954 /*
4955 * According to the spec the following bits should be
4956 * set in order to enable memory self-refresh and fbc:
4957 * The bit21 and bit22 of 0x42000
4958 * The bit21 and bit22 of 0x42004
4959 * The bit5 and bit7 of 0x42020
4960 * The bit14 of 0x70180
4961 * The bit14 of 0x71180
4bb35334
DL		 4962 *
4963 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4964 */
4965 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4966 I915_READ(ILK_DISPLAY_CHICKEN1) |
4967 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4968 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4969 I915_READ(ILK_DISPLAY_CHICKEN2) |
4970 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4971 I915_WRITE(ILK_DSPCLK_GATE_D,
4972 I915_READ(ILK_DSPCLK_GATE_D) |
4973 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4974 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4975
0e088b8f 4976 g4x_disable_trickle_feed(dev);
f8f2ac9a 4977
3107bd48 4978 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4979
4980 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4981}
4982
4983static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4984{
4985 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4986
3aad9059 4987 /*
46680e0a 4988 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 4989 *
4990 * This actually overrides the dispatch
4991 * mode for all thread types.
4992 */
6f1d69b0
ED		 4993 reg &= ~GEN7_FF_SCHED_MASK;
4994 reg |= GEN7_FF_TS_SCHED_HW;
4995 reg |= GEN7_FF_VS_SCHED_HW;
4996 reg |= GEN7_FF_DS_SCHED_HW;
4997
4998 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4999}
5000
17a303ec
PZ		 5001static void lpt_init_clock_gating(struct drm_device *dev)
5002{
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004
5005 /*
5006 * TODO: this bit should only be enabled when really needed, then
5007 * disabled when not needed anymore in order to save power.
5008 */
5009 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5010 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5011 I915_READ(SOUTH_DSPCLK_GATE_D) |
5012 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5013
5014 /* WADPOClockGatingDisable:hsw */
5015 I915_WRITE(_TRANSA_CHICKEN1,
5016 I915_READ(_TRANSA_CHICKEN1) |
5017 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5018}
5019
7d708ee4
ID		 5020static void lpt_suspend_hw(struct drm_device *dev)
5021{
5022 struct drm_i915_private *dev_priv = dev->dev_private;
5023
5024 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5025 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5026
5027 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5028 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5029 }
5030}
5031
1020a5c2
BW		 5032static void gen8_init_clock_gating(struct drm_device *dev)
5033{
5034 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 5035 enum pipe pipe;
1020a5c2
BW		 5036
5037 I915_WRITE(WM3_LP_ILK, 0);
5038 I915_WRITE(WM2_LP_ILK, 0);
5039 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5040
5041 /* FIXME(BDW): Check all the w/a, some might only apply to
5042 * pre-production hw. */
5043
c8966e10
KG		 5044 /* WaDisablePartialInstShootdown:bdw */
5045 I915_WRITE(GEN8_ROW_CHICKEN,
5046 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5047
1411e6a5
KG		 5048 /* WaDisableThreadStallDopClockGating:bdw */
5049 /* FIXME: Unclear whether we really need this on production bdw. */
5050 I915_WRITE(GEN8_ROW_CHICKEN,
5051 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5052
4167e32c
DL		 5053 /*
5054 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5055 * pre-production hardware
5056 */
fd392b60
BW		 5057 I915_WRITE(HALF_SLICE_CHICKEN3,
5058 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5059 I915_WRITE(HALF_SLICE_CHICKEN3,
5060 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5061 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5062
7f88da0c
BW		 5063 I915_WRITE(_3D_CHICKEN3,
5064 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5065
a75f3628
BW		 5066 I915_WRITE(COMMON_SLICE_CHICKEN2,
5067 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5068
4c2e7a5f
BW		 5069 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5070 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5071
242a4018
BW		 5072 /* WaDisableDopClockGating:bdw May not be needed for production */
5073 I915_WRITE(GEN7_ROW_CHICKEN2,
5074 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5075
ab57fff1 5076 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5077 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5078
ab57fff1 5079 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5080 I915_WRITE(CHICKEN_PAR1_1,
5081 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5082
ab57fff1 5083 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
07d27e20
DL		 5084 for_each_pipe(pipe) {
5085 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 5086 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 5087 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 5088 }
63801f21
BW		 5089
5090 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5091 * workaround for for a possible hang in the unlikely event a TLB
5092 * invalidation occurs during a PSD flush.
5093 */
5094 I915_WRITE(HDC_CHICKEN0,
5095 I915_READ(HDC_CHICKEN0) |
5096 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5097
5098 /* WaVSRefCountFullforceMissDisable:bdw */
5099 /* WaDSRefCountFullforceMissDisable:bdw */
5100 I915_WRITE(GEN7_FF_THREAD_MODE,
5101 I915_READ(GEN7_FF_THREAD_MODE) &
5102 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c
VS		 5103
5104 /*
5105 * BSpec recommends 8x4 when MSAA is used,
5106 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5107 *
5108 * Note that PS/WM thread counts depend on the WIZ hashing
5109 * disable bit, which we don't touch here, but it's good
5110 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
36075a4c
VS		 5111 */
5112 I915_WRITE(GEN7_GT_MODE,
5113 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
295e8bb7
VS		 5114
5115 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5116 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 5117
5118 /* WaDisableSDEUnitClockGating:bdw */
5119 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5120 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680
DL		 5121
5122 /* Wa4x4STCOptimizationDisable:bdw */
5123 I915_WRITE(CACHE_MODE_1,
5124 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
1020a5c2
BW		 5125}
5126
cad2a2d7
ED		 5127static void haswell_init_clock_gating(struct drm_device *dev)
5128{
5129 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 5130
017636cc 5131 ilk_init_lp_watermarks(dev);
cad2a2d7 5132
f3fc4884
FJ		 5133 /* L3 caching of data atomics doesn't work -- disable it. */
5134 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5135 I915_WRITE(HSW_ROW_CHICKEN3,
5136 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5137
ecdb4eb7 5138 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5139 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5140 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5141 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5142
e36ea7ff
VS		 5143 /* WaVSRefCountFullforceMissDisable:hsw */
5144 I915_WRITE(GEN7_FF_THREAD_MODE,
5145 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 5146
4e04632e
AG		 5147 /* WaDisable_RenderCache_OperationalFlush:hsw */
5148 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5149
fe27c606
CW		 5150 /* enable HiZ Raw Stall Optimization */
5151 I915_WRITE(CACHE_MODE_0_GEN7,
5152 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5153
ecdb4eb7 5154 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5155 I915_WRITE(CACHE_MODE_1,
5156 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5157
a12c4967
VS		 5158 /*
5159 * BSpec recommends 8x4 when MSAA is used,
5160 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5161 *
5162 * Note that PS/WM thread counts depend on the WIZ hashing
5163 * disable bit, which we don't touch here, but it's good
5164 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 5165 */
5166 I915_WRITE(GEN7_GT_MODE,
5167 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5168
ecdb4eb7 5169 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5170 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5171
90a88643
PZ		 5172 /* WaRsPkgCStateDisplayPMReq:hsw */
5173 I915_WRITE(CHICKEN_PAR1_1,
5174 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5175
17a303ec 5176 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5177}
5178
1fa61106 5179static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5180{
5181 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5182 uint32_t snpcr;
6f1d69b0 5183
017636cc 5184 ilk_init_lp_watermarks(dev);
6f1d69b0 5185
231e54f6 5186 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5187
ecdb4eb7 5188 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5189 I915_WRITE(_3D_CHICKEN3,
5190 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5191
ecdb4eb7 5192 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5193 I915_WRITE(IVB_CHICKEN3,
5194 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5195 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5196
ecdb4eb7 5197 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5198 if (IS_IVB_GT1(dev))
5199 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5200 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5201
4e04632e
AG		 5202 /* WaDisable_RenderCache_OperationalFlush:ivb */
5203 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5204
ecdb4eb7 5205 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5206 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5207 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5208
ecdb4eb7 5209 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5210 I915_WRITE(GEN7_L3CNTLREG1,
5211 GEN7_WA_FOR_GEN7_L3_CONTROL);
5212 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5213 GEN7_WA_L3_CHICKEN_MODE);
5214 if (IS_IVB_GT1(dev))
5215 I915_WRITE(GEN7_ROW_CHICKEN2,
5216 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 5217 else {
5218 /* must write both registers */
5219 I915_WRITE(GEN7_ROW_CHICKEN2,
5220 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 5221 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5222 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 5223 }
6f1d69b0 5224
ecdb4eb7 5225 /* WaForceL3Serialization:ivb */
61939d97
JB		 5226 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5227 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5228
1b80a19a 5229 /*
0f846f81 5230 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5231 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5232 */
5233 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 5234 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5235
ecdb4eb7 5236 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5237 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5238 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5239 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5240
0e088b8f 5241 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5242
5243 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5244
22721343
CW		 5245 if (0) { /* causes HiZ corruption on ivb:gt1 */
5246 /* enable HiZ Raw Stall Optimization */
5247 I915_WRITE(CACHE_MODE_0_GEN7,
5248 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5249 }
116f2b6d 5250
ecdb4eb7 5251 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5252 I915_WRITE(CACHE_MODE_1,
5253 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 5254
a607c1a4
VS		 5255 /*
5256 * BSpec recommends 8x4 when MSAA is used,
5257 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5258 *
5259 * Note that PS/WM thread counts depend on the WIZ hashing
5260 * disable bit, which we don't touch here, but it's good
5261 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 5262 */
5263 I915_WRITE(GEN7_GT_MODE,
5264 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5265
20848223
BW		 5266 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5267 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5268 snpcr |= GEN6_MBC_SNPCR_MED;
5269 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5270
ab5c608b
BW		 5271 if (!HAS_PCH_NOP(dev))
5272 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5273
5274 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5275}
5276
1fa61106 5277static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5278{
5279 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5280 u32 val;
5281
5282 mutex_lock(&dev_priv->rps.hw_lock);
5283 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5284 mutex_unlock(&dev_priv->rps.hw_lock);
5285 switch ((val >> 6) & 3) {
5286 case 0:
f64a28a7 5287 case 1:
f6d51948 5288 dev_priv->mem_freq = 800;
85b1d7b3 5289 break;
f64a28a7 5290 case 2:
f6d51948 5291 dev_priv->mem_freq = 1066;
85b1d7b3 5292 break;
f64a28a7 5293 case 3:
2325991e 5294 dev_priv->mem_freq = 1333;
f64a28a7 5295 break;
85b1d7b3
JB		 5296 }
5297 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5298
d60c4473
ID		 5299 dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5300 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5301 dev_priv->vlv_cdclk_freq);
5302
d7fe0cc0 5303 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5304
ecdb4eb7 5305 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5306 I915_WRITE(_3D_CHICKEN3,
5307 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5308
ecdb4eb7 5309 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5310 I915_WRITE(IVB_CHICKEN3,
5311 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5312 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5313
fad7d36e 5314 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 5315 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5316 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5317 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5318 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5319
4e04632e
AG		 5320 /* WaDisable_RenderCache_OperationalFlush:vlv */
5321 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5322
ecdb4eb7 5323 /* WaForceL3Serialization:vlv */
61939d97
JB		 5324 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5325 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5326
ecdb4eb7 5327 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5328 I915_WRITE(GEN7_ROW_CHICKEN2,
5329 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5330
ecdb4eb7 5331 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5332 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5333 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5334 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5335
46680e0a
VS		 5336 gen7_setup_fixed_func_scheduler(dev_priv);
5337
3c0edaeb 5338 /*
0f846f81 5339 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5340 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 5341 */
5342 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 5343 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 5344
c5c32cda 5345 /* WaDisableL3Bank2xClockGate:vlv */
e3f33d46
JB		 5346 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5347
e0d8d59b 5348 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5349
afd58e79
VS		 5350 /*
5351 * BSpec says this must be set, even though
5352 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5353 */
6b26c86d
DV		 5354 I915_WRITE(CACHE_MODE_1,
5355 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5356
031994ee
VS		 5357 /*
5358 * WaIncreaseL3CreditsForVLVB0:vlv
5359 * This is the hardware default actually.
5360 */
5361 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5362
2d809570 5363 /*
ecdb4eb7 5364 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5365 * Disable clock gating on th GCFG unit to prevent a delay
5366 * in the reporting of vblank events.
5367 */
7a0d1eed 5368 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 5369}
5370
a4565da8
VS		 5371static void cherryview_init_clock_gating(struct drm_device *dev)
5372{
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374
5375 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5376
5377 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
dd811e70
VS		 5378
5379 /* WaDisablePartialInstShootdown:chv */
5380 I915_WRITE(GEN8_ROW_CHICKEN,
5381 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
a7068025
VS		 5382
5383 /* WaDisableThreadStallDopClockGating:chv */
5384 I915_WRITE(GEN8_ROW_CHICKEN,
5385 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
a4565da8
VS		 5386}
5387
1fa61106 5388static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5389{
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391 uint32_t dspclk_gate;
5392
5393 I915_WRITE(RENCLK_GATE_D1, 0);
5394 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5395 GS_UNIT_CLOCK_GATE_DISABLE |
5396 CL_UNIT_CLOCK_GATE_DISABLE);
5397 I915_WRITE(RAMCLK_GATE_D, 0);
5398 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5399 OVRUNIT_CLOCK_GATE_DISABLE |
5400 OVCUNIT_CLOCK_GATE_DISABLE;
5401 if (IS_GM45(dev))
5402 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5403 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5404
5405 /* WaDisableRenderCachePipelinedFlush */
5406 I915_WRITE(CACHE_MODE_0,
5407 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5408
4e04632e
AG		 5409 /* WaDisable_RenderCache_OperationalFlush:g4x */
5410 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5411
0e088b8f 5412 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5413}
5414
1fa61106 5415static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5416{
5417 struct drm_i915_private *dev_priv = dev->dev_private;
5418
5419 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5420 I915_WRITE(RENCLK_GATE_D2, 0);
5421 I915_WRITE(DSPCLK_GATE_D, 0);
5422 I915_WRITE(RAMCLK_GATE_D, 0);
5423 I915_WRITE16(DEUC, 0);
20f94967
VS		 5424 I915_WRITE(MI_ARB_STATE,
5425 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5426
5427 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5428 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5429}
5430
1fa61106 5431static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5432{
5433 struct drm_i915_private *dev_priv = dev->dev_private;
5434
5435 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5436 I965_RCC_CLOCK_GATE_DISABLE |
5437 I965_RCPB_CLOCK_GATE_DISABLE |
5438 I965_ISC_CLOCK_GATE_DISABLE |
5439 I965_FBC_CLOCK_GATE_DISABLE);
5440 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5441 I915_WRITE(MI_ARB_STATE,
5442 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 5443
5444 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5445 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 5446}
5447
1fa61106 5448static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5449{
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 u32 dstate = I915_READ(D_STATE);
5452
5453 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5454 DSTATE_DOT_CLOCK_GATING;
5455 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5456
5457 if (IS_PINEVIEW(dev))
5458 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5459
5460 /* IIR "flip pending" means done if this bit is set */
5461 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5462}
5463
1fa61106 5464static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5465{
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467
5468 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5469}
5470
1fa61106 5471static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5472{
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474
5475 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5476}
5477
6f1d69b0
ED		 5478void intel_init_clock_gating(struct drm_device *dev)
5479{
5480 struct drm_i915_private *dev_priv = dev->dev_private;
5481
5482 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5483}
5484
7d708ee4
ID		 5485void intel_suspend_hw(struct drm_device *dev)
5486{
5487 if (HAS_PCH_LPT(dev))
5488 lpt_suspend_hw(dev);
5489}
5490
c1ca727f
ID		 5491#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5492 for (i = 0; \
5493 i < (power_domains)->power_well_count && \
5494 ((power_well) = &(power_domains)->power_wells[i]); \
5495 i++) \
5496 if ((power_well)->domains & (domain_mask))
5497
5498#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5499 for (i = (power_domains)->power_well_count - 1; \
5500 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5501 i--) \
5502 if ((power_well)->domains & (domain_mask))
5503
15d199ea
PZ		 5504/**
5505 * We should only use the power well if we explicitly asked the hardware to
5506 * enable it, so check if it's enabled and also check if we've requested it to
5507 * be enabled.
5508 */
da7e29bd 5509static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
c1ca727f
ID		 5510 struct i915_power_well *power_well)
5511{
c1ca727f
ID		 5512 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5513 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5514}
5515
da7e29bd 5516bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
ddf9c536
ID		 5517 enum intel_display_power_domain domain)
5518{
ddf9c536
ID		 5519 struct i915_power_domains *power_domains;
5520
5521 power_domains = &dev_priv->power_domains;
5522
5523 return power_domains->domain_use_count[domain];
5524}
5525
da7e29bd 5526bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
b97186f0 5527 enum intel_display_power_domain domain)
15d199ea 5528{
c1ca727f
ID		 5529 struct i915_power_domains *power_domains;
5530 struct i915_power_well *power_well;
5531 bool is_enabled;
5532 int i;
15d199ea 5533
882244a3
PZ		 5534 if (dev_priv->pm.suspended)
5535 return false;
5536
c1ca727f
ID		 5537 power_domains = &dev_priv->power_domains;
5538
5539 is_enabled = true;
5540
5541 mutex_lock(&power_domains->lock);
5542 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5543 if (power_well->always_on)
5544 continue;
5545
c6cb582e 5546 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
c1ca727f
ID		 5547 is_enabled = false;
5548 break;
5549 }
5550 }
5551 mutex_unlock(&power_domains->lock);
5552
5553 return is_enabled;
15d199ea
PZ		 5554}
5555
93c73e8c
ID		 5556/*
5557 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5558 * when not needed anymore. We have 4 registers that can request the power well
5559 * to be enabled, and it will only be disabled if none of the registers is
5560 * requesting it to be enabled.
5561 */
d5e8fdc8
PZ		 5562static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5563{
5564 struct drm_device *dev = dev_priv->dev;
5565 unsigned long irqflags;
5566
f9dcb0df
PZ		 5567 /*
5568 * After we re-enable the power well, if we touch VGA register 0x3d5
5569 * we'll get unclaimed register interrupts. This stops after we write
5570 * anything to the VGA MSR register. The vgacon module uses this
5571 * register all the time, so if we unbind our driver and, as a
5572 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5573 * console_unlock(). So make here we touch the VGA MSR register, making
5574 * sure vgacon can keep working normally without triggering interrupts
5575 * and error messages.
5576 */
5577 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5578 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5579 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5580
d5e8fdc8
PZ		 5581 if (IS_BROADWELL(dev)) {
5582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5583 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5584 dev_priv->de_irq_mask[PIPE_B]);
5585 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5586 ~dev_priv->de_irq_mask[PIPE_B] |
5587 GEN8_PIPE_VBLANK);
5588 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5589 dev_priv->de_irq_mask[PIPE_C]);
5590 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5591 ~dev_priv->de_irq_mask[PIPE_C] |
5592 GEN8_PIPE_VBLANK);
5593 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5594 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5595 }
5596}
5597
dd7c0b66
ID		 5598static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5599{
5600 assert_spin_locked(&dev->vbl_lock);
5601
5602 dev->vblank[pipe].last = 0;
5603}
5604
d5e8fdc8
PZ		 5605static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5606{
5607 struct drm_device *dev = dev_priv->dev;
07d27e20 5608 enum pipe pipe;
d5e8fdc8
PZ		 5609 unsigned long irqflags;
5610
5611 /*
5612 * After this, the registers on the pipes that are part of the power
5613 * well will become zero, so we have to adjust our counters according to
5614 * that.
5615 *
5616 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5617 */
5618 spin_lock_irqsave(&dev->vbl_lock, irqflags);
07d27e20
DL		 5619 for_each_pipe(pipe)
5620 if (pipe != PIPE_A)
dd7c0b66 5621 reset_vblank_counter(dev, pipe);
d5e8fdc8
PZ		 5622 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5623}
5624
da7e29bd 5625static void hsw_set_power_well(struct drm_i915_private *dev_priv,
c1ca727f 5626 struct i915_power_well *power_well, bool enable)
d0d3e513 5627{
fa42e23c
PZ		 5628 bool is_enabled, enable_requested;
5629 uint32_t tmp;
d0d3e513 5630
fa42e23c 5631 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5632 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5633 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5634
fa42e23c
PZ		 5635 if (enable) {
5636 if (!enable_requested)
6aedd1f5
PZ		 5637 I915_WRITE(HSW_PWR_WELL_DRIVER,
5638 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5639
fa42e23c
PZ		 5640 if (!is_enabled) {
5641 DRM_DEBUG_KMS("Enabling power well\n");
5642 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5643 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5644 DRM_ERROR("Timeout enabling power well\n");
5645 }
596cc11e 5646
d5e8fdc8 5647 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5648 } else {
5649 if (enable_requested) {
5650 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5651 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5652 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5653
d5e8fdc8 5654 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5655 }
5656 }
fa42e23c 5657}
d0d3e513 5658
c6cb582e
ID		 5659static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5660 struct i915_power_well *power_well)
5661{
5662 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5663
5664 /*
5665 * We're taking over the BIOS, so clear any requests made by it since
5666 * the driver is in charge now.
5667 */
5668 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5669 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5670}
5671
5672static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5673 struct i915_power_well *power_well)
5674{
c6cb582e
ID		 5675 hsw_set_power_well(dev_priv, power_well, true);
5676}
5677
5678static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5679 struct i915_power_well *power_well)
5680{
5681 hsw_set_power_well(dev_priv, power_well, false);
c6cb582e
ID		 5682}
5683
a45f4466
ID		 5684static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5685 struct i915_power_well *power_well)
5686{
5687}
5688
5689static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5690 struct i915_power_well *power_well)
5691{
5692 return true;
5693}
5694
77961eb9
ID		 5695static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5696 struct i915_power_well *power_well, bool enable)
5697{
5698 enum punit_power_well power_well_id = power_well->data;
5699 u32 mask;
5700 u32 state;
5701 u32 ctrl;
5702
5703 mask = PUNIT_PWRGT_MASK(power_well_id);
5704 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5705 PUNIT_PWRGT_PWR_GATE(power_well_id);
5706
5707 mutex_lock(&dev_priv->rps.hw_lock);
5708
5709#define COND \
5710 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5711
5712 if (COND)
5713 goto out;
5714
5715 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5716 ctrl &= ~mask;
5717 ctrl |= state;
5718 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5719
5720 if (wait_for(COND, 100))
5721 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5722 state,
5723 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5724
5725#undef COND
5726
5727out:
5728 mutex_unlock(&dev_priv->rps.hw_lock);
5729}
5730
5731static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5732 struct i915_power_well *power_well)
5733{
5734 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5735}
5736
5737static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5738 struct i915_power_well *power_well)
5739{
5740 vlv_set_power_well(dev_priv, power_well, true);
5741}
5742
5743static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5744 struct i915_power_well *power_well)
5745{
5746 vlv_set_power_well(dev_priv, power_well, false);
5747}
5748
5749static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5750 struct i915_power_well *power_well)
5751{
5752 int power_well_id = power_well->data;
5753 bool enabled = false;
5754 u32 mask;
5755 u32 state;
5756 u32 ctrl;
5757
5758 mask = PUNIT_PWRGT_MASK(power_well_id);
5759 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5760
5761 mutex_lock(&dev_priv->rps.hw_lock);
5762
5763 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5764 /*
5765 * We only ever set the power-on and power-gate states, anything
5766 * else is unexpected.
5767 */
5768 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5769 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5770 if (state == ctrl)
5771 enabled = true;
5772
5773 /*
5774 * A transient state at this point would mean some unexpected party
5775 * is poking at the power controls too.
5776 */
5777 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5778 WARN_ON(ctrl != state);
5779
5780 mutex_unlock(&dev_priv->rps.hw_lock);
5781
5782 return enabled;
5783}
5784
5785static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5786 struct i915_power_well *power_well)
5787{
5788 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5789
5790 vlv_set_power_well(dev_priv, power_well, true);
5791
5792 spin_lock_irq(&dev_priv->irq_lock);
5793 valleyview_enable_display_irqs(dev_priv);
5794 spin_unlock_irq(&dev_priv->irq_lock);
5795
5796 /*
0d116a29
ID		 5797 * During driver initialization/resume we can avoid restoring the
5798 * part of the HW/SW state that will be inited anyway explicitly.
77961eb9 5799 */
0d116a29
ID		 5800 if (dev_priv->power_domains.initializing)
5801 return;
5802
5803 intel_hpd_init(dev_priv->dev);
77961eb9
ID		 5804
5805 i915_redisable_vga_power_on(dev_priv->dev);
5806}
5807
5808static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5809 struct i915_power_well *power_well)
5810{
5811 struct drm_device *dev = dev_priv->dev;
5812 enum pipe pipe;
5813
5814 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5815
5816 spin_lock_irq(&dev_priv->irq_lock);
5817 for_each_pipe(pipe)
5818 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5819
5820 valleyview_disable_display_irqs(dev_priv);
5821 spin_unlock_irq(&dev_priv->irq_lock);
5822
5823 spin_lock_irq(&dev->vbl_lock);
5824 for_each_pipe(pipe)
5825 reset_vblank_counter(dev, pipe);
5826 spin_unlock_irq(&dev->vbl_lock);
5827
5828 vlv_set_power_well(dev_priv, power_well, false);
5829}
5830
25eaa003
ID		 5831static void check_power_well_state(struct drm_i915_private *dev_priv,
5832 struct i915_power_well *power_well)
5833{
5834 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5835
5836 if (power_well->always_on || !i915.disable_power_well) {
5837 if (!enabled)
5838 goto mismatch;
5839
5840 return;
5841 }
5842
5843 if (enabled != (power_well->count > 0))
5844 goto mismatch;
5845
5846 return;
5847
5848mismatch:
5849 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5850 power_well->name, power_well->always_on, enabled,
5851 power_well->count, i915.disable_power_well);
5852}
5853
da7e29bd 5854void intel_display_power_get(struct drm_i915_private *dev_priv,
6765625e
VS		 5855 enum intel_display_power_domain domain)
5856{
83c00f55 5857 struct i915_power_domains *power_domains;
c1ca727f
ID		 5858 struct i915_power_well *power_well;
5859 int i;
6765625e 5860
9e6ea71a
PZ		 5861 intel_runtime_pm_get(dev_priv);
5862
83c00f55
ID		 5863 power_domains = &dev_priv->power_domains;
5864
5865 mutex_lock(&power_domains->lock);
1da51581 5866
25eaa003
ID		 5867 for_each_power_well(i, power_well, BIT(domain), power_domains) {
5868 if (!power_well->count++) {
5869 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
c6cb582e 5870 power_well->ops->enable(dev_priv, power_well);
25eaa003
ID		 5871 }
5872
5873 check_power_well_state(dev_priv, power_well);
5874 }
1da51581 5875
ddf9c536
ID		 5876 power_domains->domain_use_count[domain]++;
5877
83c00f55 5878 mutex_unlock(&power_domains->lock);
6765625e
VS		 5879}
5880
da7e29bd 5881void intel_display_power_put(struct drm_i915_private *dev_priv,
6765625e
VS		 5882 enum intel_display_power_domain domain)
5883{
83c00f55 5884 struct i915_power_domains *power_domains;
c1ca727f
ID		 5885 struct i915_power_well *power_well;
5886 int i;
6765625e 5887
83c00f55
ID		 5888 power_domains = &dev_priv->power_domains;
5889
5890 mutex_lock(&power_domains->lock);
1da51581 5891
1da51581
ID		 5892 WARN_ON(!power_domains->domain_use_count[domain]);
5893 power_domains->domain_use_count[domain]--;
ddf9c536 5894
70bf407c
ID		 5895 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5896 WARN_ON(!power_well->count);
5897
25eaa003
ID		 5898 if (!--power_well->count && i915.disable_power_well) {
5899 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
c6cb582e 5900 power_well->ops->disable(dev_priv, power_well);
25eaa003
ID		 5901 }
5902
5903 check_power_well_state(dev_priv, power_well);
70bf407c 5904 }
1da51581 5905
83c00f55 5906 mutex_unlock(&power_domains->lock);
9e6ea71a
PZ		 5907
5908 intel_runtime_pm_put(dev_priv);
6765625e
VS		 5909}
5910
83c00f55 5911static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5912
5913/* Display audio driver power well request */
5914void i915_request_power_well(void)
5915{
b4ed4484
ID		 5916 struct drm_i915_private *dev_priv;
5917
a38911a3
WX		 5918 if (WARN_ON(!hsw_pwr))
5919 return;
5920
b4ed4484
ID		 5921 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5922 power_domains);
da7e29bd 5923 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5924}
5925EXPORT_SYMBOL_GPL(i915_request_power_well);
5926
5927/* Display audio driver power well release */
5928void i915_release_power_well(void)
5929{
b4ed4484
ID		 5930 struct drm_i915_private *dev_priv;
5931
a38911a3
WX		 5932 if (WARN_ON(!hsw_pwr))
5933 return;
5934
b4ed4484
ID		 5935 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5936 power_domains);
da7e29bd 5937 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5938}
5939EXPORT_SYMBOL_GPL(i915_release_power_well);
5940
efcad917
ID		 5941#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5942
5943#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
5944 BIT(POWER_DOMAIN_PIPE_A) | \
f5938f36 5945 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
319be8ae
ID		 5946 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
5947 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
5948 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5949 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5950 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5951 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5952 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
5953 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
5954 BIT(POWER_DOMAIN_PORT_CRT) | \
f5938f36 5955 BIT(POWER_DOMAIN_INIT))
efcad917
ID		 5956#define HSW_DISPLAY_POWER_DOMAINS ( \
5957 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
5958 BIT(POWER_DOMAIN_INIT))
5959
5960#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
5961 HSW_ALWAYS_ON_POWER_DOMAINS | \
5962 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5963#define BDW_DISPLAY_POWER_DOMAINS ( \
5964 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
5965 BIT(POWER_DOMAIN_INIT))
5966
77961eb9
ID		 5967#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
5968#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
5969
5970#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
5971 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5972 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5973 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5974 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5975 BIT(POWER_DOMAIN_PORT_CRT) | \
5976 BIT(POWER_DOMAIN_INIT))
5977
5978#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
5979 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5980 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5981 BIT(POWER_DOMAIN_INIT))
5982
5983#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
5984 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5985 BIT(POWER_DOMAIN_INIT))
5986
5987#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
5988 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5989 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5990 BIT(POWER_DOMAIN_INIT))
5991
5992#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
5993 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5994 BIT(POWER_DOMAIN_INIT))
5995
a45f4466
ID		 5996static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5997 .sync_hw = i9xx_always_on_power_well_noop,
5998 .enable = i9xx_always_on_power_well_noop,
5999 .disable = i9xx_always_on_power_well_noop,
6000 .is_enabled = i9xx_always_on_power_well_enabled,
6001};
c6cb582e 6002
1c2256df
ID		 6003static struct i915_power_well i9xx_always_on_power_well[] = {
6004 {
6005 .name = "always-on",
6006 .always_on = 1,
6007 .domains = POWER_DOMAIN_MASK,
c6cb582e 6008 .ops = &i9xx_always_on_power_well_ops,
1c2256df
ID		 6009 },
6010};
6011
c6cb582e
ID		 6012static const struct i915_power_well_ops hsw_power_well_ops = {
6013 .sync_hw = hsw_power_well_sync_hw,
6014 .enable = hsw_power_well_enable,
6015 .disable = hsw_power_well_disable,
6016 .is_enabled = hsw_power_well_enabled,
6017};
6018
c1ca727f 6019static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 6020 {
6021 .name = "always-on",
6022 .always_on = 1,
6023 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6024 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6025 },
c1ca727f
ID		 6026 {
6027 .name = "display",
efcad917 6028 .domains = HSW_DISPLAY_POWER_DOMAINS,
c6cb582e 6029 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6030 },
6031};
6032
6033static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 6034 {
6035 .name = "always-on",
6036 .always_on = 1,
6037 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
c6cb582e 6038 .ops = &i9xx_always_on_power_well_ops,
6f3ef5dd 6039 },
c1ca727f
ID		 6040 {
6041 .name = "display",
efcad917 6042 .domains = BDW_DISPLAY_POWER_DOMAINS,
c6cb582e 6043 .ops = &hsw_power_well_ops,
c1ca727f
ID		 6044 },
6045};
6046
77961eb9
ID		 6047static const struct i915_power_well_ops vlv_display_power_well_ops = {
6048 .sync_hw = vlv_power_well_sync_hw,
6049 .enable = vlv_display_power_well_enable,
6050 .disable = vlv_display_power_well_disable,
6051 .is_enabled = vlv_power_well_enabled,
6052};
6053
6054static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6055 .sync_hw = vlv_power_well_sync_hw,
6056 .enable = vlv_power_well_enable,
6057 .disable = vlv_power_well_disable,
6058 .is_enabled = vlv_power_well_enabled,
6059};
6060
6061static struct i915_power_well vlv_power_wells[] = {
6062 {
6063 .name = "always-on",
6064 .always_on = 1,
6065 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6066 .ops = &i9xx_always_on_power_well_ops,
6067 },
6068 {
6069 .name = "display",
6070 .domains = VLV_DISPLAY_POWER_DOMAINS,
6071 .data = PUNIT_POWER_WELL_DISP2D,
6072 .ops = &vlv_display_power_well_ops,
6073 },
6074 {
6075 .name = "dpio-common",
6076 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6077 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6078 .ops = &vlv_dpio_power_well_ops,
6079 },
6080 {
6081 .name = "dpio-tx-b-01",
6082 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6083 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6084 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6085 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6086 .ops = &vlv_dpio_power_well_ops,
6087 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6088 },
6089 {
6090 .name = "dpio-tx-b-23",
6091 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6092 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6093 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6094 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6095 .ops = &vlv_dpio_power_well_ops,
6096 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6097 },
6098 {
6099 .name = "dpio-tx-c-01",
6100 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6101 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6102 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6103 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6104 .ops = &vlv_dpio_power_well_ops,
6105 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6106 },
6107 {
6108 .name = "dpio-tx-c-23",
6109 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6110 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6111 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6112 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6113 .ops = &vlv_dpio_power_well_ops,
6114 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6115 },
6116};
6117
c1ca727f
ID		 6118#define set_power_wells(power_domains, __power_wells) ({ \
6119 (power_domains)->power_wells = (__power_wells); \
6120 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6121})
6122
da7e29bd 6123int intel_power_domains_init(struct drm_i915_private *dev_priv)
a38911a3 6124{
83c00f55 6125 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6126
83c00f55 6127 mutex_init(&power_domains->lock);
a38911a3 6128
c1ca727f
ID		 6129 /*
6130 * The enabling order will be from lower to higher indexed wells,
6131 * the disabling order is reversed.
6132 */
da7e29bd 6133 if (IS_HASWELL(dev_priv->dev)) {
c1ca727f
ID		 6134 set_power_wells(power_domains, hsw_power_wells);
6135 hsw_pwr = power_domains;
da7e29bd 6136 } else if (IS_BROADWELL(dev_priv->dev)) {
c1ca727f
ID		 6137 set_power_wells(power_domains, bdw_power_wells);
6138 hsw_pwr = power_domains;
77961eb9
ID		 6139 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6140 set_power_wells(power_domains, vlv_power_wells);
c1ca727f 6141 } else {
1c2256df 6142 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6143 }
a38911a3
WX		 6144
6145 return 0;
6146}
6147
da7e29bd 6148void intel_power_domains_remove(struct drm_i915_private *dev_priv)
a38911a3
WX		 6149{
6150 hsw_pwr = NULL;
6151}
6152
da7e29bd 6153static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
9cdb826c 6154{
83c00f55
ID		 6155 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6156 struct i915_power_well *power_well;
c1ca727f 6157 int i;
9cdb826c 6158
83c00f55 6159 mutex_lock(&power_domains->lock);
a45f4466
ID		 6160 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
6161 power_well->ops->sync_hw(dev_priv, power_well);
83c00f55 6162 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6163}
6164
da7e29bd 6165void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
d0d3e513 6166{
0d116a29
ID		 6167 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6168
6169 power_domains->initializing = true;
fa42e23c 6170 /* For now, we need the power well to be always enabled. */
da7e29bd
ID		 6171 intel_display_set_init_power(dev_priv, true);
6172 intel_power_domains_resume(dev_priv);
0d116a29 6173 power_domains->initializing = false;
d0d3e513
ED		 6174}
6175
c67a470b
PZ		 6176void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6177{
d361ae26 6178 intel_runtime_pm_get(dev_priv);
c67a470b
PZ		 6179}
6180
6181void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6182{
d361ae26 6183 intel_runtime_pm_put(dev_priv);
c67a470b
PZ		 6184}
6185
8a187455
PZ		 6186void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6187{
6188 struct drm_device *dev = dev_priv->dev;
6189 struct device *device = &dev->pdev->dev;
6190
6191 if (!HAS_RUNTIME_PM(dev))
6192 return;
6193
6194 pm_runtime_get_sync(device);
6195 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6196}
6197
c6df39b5
ID		 6198void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6199{
6200 struct drm_device *dev = dev_priv->dev;
6201 struct device *device = &dev->pdev->dev;
6202
6203 if (!HAS_RUNTIME_PM(dev))
6204 return;
6205
6206 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6207 pm_runtime_get_noresume(device);
6208}
6209
8a187455
PZ		 6210void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6211{
6212 struct drm_device *dev = dev_priv->dev;
6213 struct device *device = &dev->pdev->dev;
6214
6215 if (!HAS_RUNTIME_PM(dev))
6216 return;
6217
6218 pm_runtime_mark_last_busy(device);
6219 pm_runtime_put_autosuspend(device);
6220}
6221
6222void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6223{
6224 struct drm_device *dev = dev_priv->dev;
6225 struct device *device = &dev->pdev->dev;
6226
8a187455
PZ		 6227 if (!HAS_RUNTIME_PM(dev))
6228 return;
6229
6230 pm_runtime_set_active(device);
6231
aeab0b5a
ID		 6232 /*
6233 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6234 * requirement.
6235 */
6236 if (!intel_enable_rc6(dev)) {
6237 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6238 return;
6239 }
6240
8a187455
PZ		 6241 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6242 pm_runtime_mark_last_busy(device);
6243 pm_runtime_use_autosuspend(device);
ba0239e0
PZ		 6244
6245 pm_runtime_put_autosuspend(device);
8a187455
PZ		 6246}
6247
6248void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6249{
6250 struct drm_device *dev = dev_priv->dev;
6251 struct device *device = &dev->pdev->dev;
6252
6253 if (!HAS_RUNTIME_PM(dev))
6254 return;
6255
aeab0b5a
ID		 6256 if (!intel_enable_rc6(dev))
6257 return;
6258
8a187455
PZ		 6259 /* Make sure we're not suspended first. */
6260 pm_runtime_get_sync(device);
6261 pm_runtime_disable(device);
6262}
6263
1fa61106
ED		 6264/* Set up chip specific power management-related functions */
6265void intel_init_pm(struct drm_device *dev)
6266{
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268
3a77c4c4 6269 if (HAS_FBC(dev)) {
40045465 6270 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6271 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6272 dev_priv->display.enable_fbc = gen7_enable_fbc;
6273 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6274 } else if (INTEL_INFO(dev)->gen >= 5) {
6275 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6276 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6277 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6278 } else if (IS_GM45(dev)) {
6279 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6280 dev_priv->display.enable_fbc = g4x_enable_fbc;
6281 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6282 } else {
1fa61106
ED		 6283 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6284 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6285 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6286
6287 /* This value was pulled out of someone's hat */
6288 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6289 }
1fa61106
ED		 6290 }
6291
c921aba8
DV		 6292 /* For cxsr */
6293 if (IS_PINEVIEW(dev))
6294 i915_pineview_get_mem_freq(dev);
6295 else if (IS_GEN5(dev))
6296 i915_ironlake_get_mem_freq(dev);
6297
1fa61106
ED		 6298 /* For FIFO watermark updates */
6299 if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6300 ilk_setup_wm_latency(dev);
53615a5e 6301
bd602544
VS		 6302 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6303 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6304 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6305 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6306 dev_priv->display.update_wm = ilk_update_wm;
6307 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6308 } else {
6309 DRM_DEBUG_KMS("Failed to read display plane latency. "
6310 "Disable CxSR\n");
6311 }
6312
6313 if (IS_GEN5(dev))
1fa61106 6314 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6315 else if (IS_GEN6(dev))
1fa61106 6316 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6317 else if (IS_IVYBRIDGE(dev))
1fa61106 6318 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6319 else if (IS_HASWELL(dev))
cad2a2d7 6320 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6321 else if (INTEL_INFO(dev)->gen == 8)
1020a5c2 6322 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
a4565da8
VS		 6323 } else if (IS_CHERRYVIEW(dev)) {
6324 dev_priv->display.update_wm = valleyview_update_wm;
6325 dev_priv->display.init_clock_gating =
6326 cherryview_init_clock_gating;
1fa61106
ED		 6327 } else if (IS_VALLEYVIEW(dev)) {
6328 dev_priv->display.update_wm = valleyview_update_wm;
6329 dev_priv->display.init_clock_gating =
6330 valleyview_init_clock_gating;
1fa61106
ED		 6331 } else if (IS_PINEVIEW(dev)) {
6332 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6333 dev_priv->is_ddr3,
6334 dev_priv->fsb_freq,
6335 dev_priv->mem_freq)) {
6336 DRM_INFO("failed to find known CxSR latency "
6337 "(found ddr%s fsb freq %d, mem freq %d), "
6338 "disabling CxSR\n",
6339 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6340 dev_priv->fsb_freq, dev_priv->mem_freq);
6341 /* Disable CxSR and never update its watermark again */
6342 pineview_disable_cxsr(dev);
6343 dev_priv->display.update_wm = NULL;
6344 } else
6345 dev_priv->display.update_wm = pineview_update_wm;
6346 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6347 } else if (IS_G4X(dev)) {
6348 dev_priv->display.update_wm = g4x_update_wm;
6349 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6350 } else if (IS_GEN4(dev)) {
6351 dev_priv->display.update_wm = i965_update_wm;
6352 if (IS_CRESTLINE(dev))
6353 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6354 else if (IS_BROADWATER(dev))
6355 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6356 } else if (IS_GEN3(dev)) {
6357 dev_priv->display.update_wm = i9xx_update_wm;
6358 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6359 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6360 } else if (IS_GEN2(dev)) {
6361 if (INTEL_INFO(dev)->num_pipes == 1) {
6362 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6363 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6364 } else {
6365 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6366 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6367 }
6368
6369 if (IS_I85X(dev) || IS_I865G(dev))
6370 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6371 else
6372 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6373 } else {
6374 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6375 }
6376}
6377
42c0526c
BW		 6378int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6379{
4fc688ce 6380 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6381
6382 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6383 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6384 return -EAGAIN;
6385 }
6386
6387 I915_WRITE(GEN6_PCODE_DATA, *val);
6388 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6389
6390 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6391 500)) {
6392 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6393 return -ETIMEDOUT;
6394 }
6395
6396 *val = I915_READ(GEN6_PCODE_DATA);
6397 I915_WRITE(GEN6_PCODE_DATA, 0);
6398
6399 return 0;
6400}
6401
6402int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6403{
4fc688ce 6404 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6405
6406 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6407 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6408 return -EAGAIN;
6409 }
6410
6411 I915_WRITE(GEN6_PCODE_DATA, val);
6412 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6413
6414 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6415 500)) {
6416 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6417 return -ETIMEDOUT;
6418 }
6419
6420 I915_WRITE(GEN6_PCODE_DATA, 0);
6421
6422 return 0;
6423}
a0e4e199 6424
2ec3815f 6425int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6426{
07ab118b 6427 int div;
855ba3be 6428
07ab118b 6429 /* 4 x czclk */
2ec3815f 6430 switch (dev_priv->mem_freq) {
855ba3be 6431 case 800:
07ab118b 6432 div = 10;
855ba3be
JB		 6433 break;
6434 case 1066:
07ab118b 6435 div = 12;
855ba3be
JB		 6436 break;
6437 case 1333:
07ab118b 6438 div = 16;
855ba3be
JB		 6439 break;
6440 default:
6441 return -1;
6442 }
6443
2ec3815f 6444 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6445}
6446
2ec3815f 6447int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6448{
07ab118b 6449 int mul;
855ba3be 6450
07ab118b 6451 /* 4 x czclk */
2ec3815f 6452 switch (dev_priv->mem_freq) {
855ba3be 6453 case 800:
07ab118b 6454 mul = 10;
855ba3be
JB		 6455 break;
6456 case 1066:
07ab118b 6457 mul = 12;
855ba3be
JB		 6458 break;
6459 case 1333:
07ab118b 6460 mul = 16;
855ba3be
JB		 6461 break;
6462 default:
6463 return -1;
6464 }
6465
2ec3815f 6466 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6467}
6468
f742a552 6469void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6470{
6471 struct drm_i915_private *dev_priv = dev->dev_private;
6472
f742a552
DV		 6473 mutex_init(&dev_priv->rps.hw_lock);
6474
907b28c5
CW		 6475 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6476 intel_gen6_powersave_work);
5d584b2e 6477
33688d95 6478 dev_priv->pm.suspended = false;
5d584b2e 6479 dev_priv->pm.irqs_disabled = false;
907b28c5 6480}
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