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drm/i915/bxt: add bxt_init_clock_gating
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
3dcd020a
HN		 70 if (INTEL_REVID(dev) == SKL_REVID_A0) {
71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a
HN		 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
78 }
8bc0ccf6 79
2caa3b26 80 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 81 /* WaDisableHDCInvalidation:skl */
82 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
83 BDW_DISABLE_HDC_INVALIDATION);
84
2caa3b26
DL		 85 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
86 I915_WRITE(FF_SLICE_CS_CHICKEN2,
87 I915_READ(FF_SLICE_CS_CHICKEN2) |
88 GEN9_TSG_BARRIER_ACK_DISABLE);
89 }
81e231af 90
8bc0ccf6
DL		 91 if (INTEL_REVID(dev) <= SKL_REVID_E0)
92 /* WaDisableLSQCROPERFforOCL:skl */
93 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
94 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 95}
96
a82abe43
ID		 97static void bxt_init_clock_gating(struct drm_device *dev)
98{
99 gen9_init_clock_gating(dev);
100}
101
c921aba8
DV		 102static void i915_pineview_get_mem_freq(struct drm_device *dev)
103{
50227e1c 104 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 105 u32 tmp;
106
107 tmp = I915_READ(CLKCFG);
108
109 switch (tmp & CLKCFG_FSB_MASK) {
110 case CLKCFG_FSB_533:
111 dev_priv->fsb_freq = 533; /* 133*4 */
112 break;
113 case CLKCFG_FSB_800:
114 dev_priv->fsb_freq = 800; /* 200*4 */
115 break;
116 case CLKCFG_FSB_667:
117 dev_priv->fsb_freq = 667; /* 167*4 */
118 break;
119 case CLKCFG_FSB_400:
120 dev_priv->fsb_freq = 400; /* 100*4 */
121 break;
122 }
123
124 switch (tmp & CLKCFG_MEM_MASK) {
125 case CLKCFG_MEM_533:
126 dev_priv->mem_freq = 533;
127 break;
128 case CLKCFG_MEM_667:
129 dev_priv->mem_freq = 667;
130 break;
131 case CLKCFG_MEM_800:
132 dev_priv->mem_freq = 800;
133 break;
134 }
135
136 /* detect pineview DDR3 setting */
137 tmp = I915_READ(CSHRDDR3CTL);
138 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
139}
140
141static void i915_ironlake_get_mem_freq(struct drm_device *dev)
142{
50227e1c 143 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 144 u16 ddrpll, csipll;
145
146 ddrpll = I915_READ16(DDRMPLL1);
147 csipll = I915_READ16(CSIPLL0);
148
149 switch (ddrpll & 0xff) {
150 case 0xc:
151 dev_priv->mem_freq = 800;
152 break;
153 case 0x10:
154 dev_priv->mem_freq = 1066;
155 break;
156 case 0x14:
157 dev_priv->mem_freq = 1333;
158 break;
159 case 0x18:
160 dev_priv->mem_freq = 1600;
161 break;
162 default:
163 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
164 ddrpll & 0xff);
165 dev_priv->mem_freq = 0;
166 break;
167 }
168
20e4d407 169 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 170
171 switch (csipll & 0x3ff) {
172 case 0x00c:
173 dev_priv->fsb_freq = 3200;
174 break;
175 case 0x00e:
176 dev_priv->fsb_freq = 3733;
177 break;
178 case 0x010:
179 dev_priv->fsb_freq = 4266;
180 break;
181 case 0x012:
182 dev_priv->fsb_freq = 4800;
183 break;
184 case 0x014:
185 dev_priv->fsb_freq = 5333;
186 break;
187 case 0x016:
188 dev_priv->fsb_freq = 5866;
189 break;
190 case 0x018:
191 dev_priv->fsb_freq = 6400;
192 break;
193 default:
194 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
195 csipll & 0x3ff);
196 dev_priv->fsb_freq = 0;
197 break;
198 }
199
200 if (dev_priv->fsb_freq == 3200) {
20e4d407 201 dev_priv->ips.c_m = 0;
c921aba8 202 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 203 dev_priv->ips.c_m = 1;
c921aba8 204 } else {
20e4d407 205 dev_priv->ips.c_m = 2;
c921aba8
DV		 206 }
207}
208
b445e3b0
ED		 209static const struct cxsr_latency cxsr_latency_table[] = {
210 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
211 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
212 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
213 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
214 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
215
216 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
217 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
218 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
219 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
220 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
221
222 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
223 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
224 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
225 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
226 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
227
228 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
229 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
230 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
231 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
232 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
233
234 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
235 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
236 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
237 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
238 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
239
240 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
241 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
242 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
243 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
244 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
245};
246
63c62275 247static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 248 int is_ddr3,
249 int fsb,
250 int mem)
251{
252 const struct cxsr_latency *latency;
253 int i;
254
255 if (fsb == 0 || mem == 0)
256 return NULL;
257
258 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
259 latency = &cxsr_latency_table[i];
260 if (is_desktop == latency->is_desktop &&
261 is_ddr3 == latency->is_ddr3 &&
262 fsb == latency->fsb_freq && mem == latency->mem_freq)
263 return latency;
264 }
265
266 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
267
268 return NULL;
269}
270
fc1ac8de
VS		 271static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
272{
273 u32 val;
274
275 mutex_lock(&dev_priv->rps.hw_lock);
276
277 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
278 if (enable)
279 val &= ~FORCE_DDR_HIGH_FREQ;
280 else
281 val |= FORCE_DDR_HIGH_FREQ;
282 val &= ~FORCE_DDR_LOW_FREQ;
283 val |= FORCE_DDR_FREQ_REQ_ACK;
284 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
285
286 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
287 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
288 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
289
290 mutex_unlock(&dev_priv->rps.hw_lock);
291}
292
cfb41411
VS		 293static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
294{
295 u32 val;
296
297 mutex_lock(&dev_priv->rps.hw_lock);
298
299 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
300 if (enable)
301 val |= DSP_MAXFIFO_PM5_ENABLE;
302 else
303 val &= ~DSP_MAXFIFO_PM5_ENABLE;
304 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
305
306 mutex_unlock(&dev_priv->rps.hw_lock);
307}
308
f4998963
VS		 309#define FW_WM(value, plane) \
310 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
311
5209b1f4 312void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 313{
5209b1f4
ID		 314 struct drm_device *dev = dev_priv->dev;
315 u32 val;
b445e3b0 316
5209b1f4
ID		 317 if (IS_VALLEYVIEW(dev)) {
318 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
cfb41411
VS		 319 if (IS_CHERRYVIEW(dev))
320 chv_set_memory_pm5(dev_priv, enable);
5209b1f4
ID		 321 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
322 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
323 } else if (IS_PINEVIEW(dev)) {
324 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
325 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
326 I915_WRITE(DSPFW3, val);
327 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
328 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
329 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
330 I915_WRITE(FW_BLC_SELF, val);
331 } else if (IS_I915GM(dev)) {
332 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
333 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
334 I915_WRITE(INSTPM, val);
335 } else {
336 return;
337 }
b445e3b0 338
5209b1f4
ID		 339 DRM_DEBUG_KMS("memory self-refresh is %s\n",
340 enable ? "enabled" : "disabled");
b445e3b0
ED		 341}
342
fc1ac8de 343
b445e3b0
ED		 344/*
345 * Latency for FIFO fetches is dependent on several factors:
346 * - memory configuration (speed, channels)
347 * - chipset
348 * - current MCH state
349 * It can be fairly high in some situations, so here we assume a fairly
350 * pessimal value. It's a tradeoff between extra memory fetches (if we
351 * set this value too high, the FIFO will fetch frequently to stay full)
352 * and power consumption (set it too low to save power and we might see
353 * FIFO underruns and display "flicker").
354 *
355 * A value of 5us seems to be a good balance; safe for very low end
356 * platforms but not overly aggressive on lower latency configs.
357 */
5aef6003 358static const int pessimal_latency_ns = 5000;
b445e3b0 359
b5004720
VS		 360#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
361 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
362
363static int vlv_get_fifo_size(struct drm_device *dev,
364 enum pipe pipe, int plane)
365{
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 int sprite0_start, sprite1_start, size;
368
369 switch (pipe) {
370 uint32_t dsparb, dsparb2, dsparb3;
371 case PIPE_A:
372 dsparb = I915_READ(DSPARB);
373 dsparb2 = I915_READ(DSPARB2);
374 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
375 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
376 break;
377 case PIPE_B:
378 dsparb = I915_READ(DSPARB);
379 dsparb2 = I915_READ(DSPARB2);
380 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
381 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
382 break;
383 case PIPE_C:
384 dsparb2 = I915_READ(DSPARB2);
385 dsparb3 = I915_READ(DSPARB3);
386 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
387 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
388 break;
389 default:
390 return 0;
391 }
392
393 switch (plane) {
394 case 0:
395 size = sprite0_start;
396 break;
397 case 1:
398 size = sprite1_start - sprite0_start;
399 break;
400 case 2:
401 size = 512 - 1 - sprite1_start;
402 break;
403 default:
404 return 0;
405 }
406
407 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
408 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
409 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
410 size);
411
412 return size;
413}
414
1fa61106 415static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 416{
417 struct drm_i915_private *dev_priv = dev->dev_private;
418 uint32_t dsparb = I915_READ(DSPARB);
419 int size;
420
421 size = dsparb & 0x7f;
422 if (plane)
423 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
feb56b93 431static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x1ff;
438 if (plane)
439 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
440 size >>= 1; /* Convert to cachelines */
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
1fa61106 448static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 449{
450 struct drm_i915_private *dev_priv = dev->dev_private;
451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x7f;
455 size >>= 2; /* Convert to cachelines */
456
457 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
458 plane ? "B" : "A",
459 size);
460
461 return size;
462}
463
b445e3b0
ED		 464/* Pineview has different values for various configs */
465static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 466 .fifo_size = PINEVIEW_DISPLAY_FIFO,
467 .max_wm = PINEVIEW_MAX_WM,
468 .default_wm = PINEVIEW_DFT_WM,
469 .guard_size = PINEVIEW_GUARD_WM,
470 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 471};
472static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 473 .fifo_size = PINEVIEW_DISPLAY_FIFO,
474 .max_wm = PINEVIEW_MAX_WM,
475 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
476 .guard_size = PINEVIEW_GUARD_WM,
477 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 478};
479static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 480 .fifo_size = PINEVIEW_CURSOR_FIFO,
481 .max_wm = PINEVIEW_CURSOR_MAX_WM,
482 .default_wm = PINEVIEW_CURSOR_DFT_WM,
483 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
484 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 485};
486static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 487 .fifo_size = PINEVIEW_CURSOR_FIFO,
488 .max_wm = PINEVIEW_CURSOR_MAX_WM,
489 .default_wm = PINEVIEW_CURSOR_DFT_WM,
490 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
491 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 492};
493static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 494 .fifo_size = G4X_FIFO_SIZE,
495 .max_wm = G4X_MAX_WM,
496 .default_wm = G4X_MAX_WM,
497 .guard_size = 2,
498 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 499};
500static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 501 .fifo_size = I965_CURSOR_FIFO,
502 .max_wm = I965_CURSOR_MAX_WM,
503 .default_wm = I965_CURSOR_DFT_WM,
504 .guard_size = 2,
505 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 506};
507static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 508 .fifo_size = VALLEYVIEW_FIFO_SIZE,
509 .max_wm = VALLEYVIEW_MAX_WM,
510 .default_wm = VALLEYVIEW_MAX_WM,
511 .guard_size = 2,
512 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 513};
514static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 515 .fifo_size = I965_CURSOR_FIFO,
516 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
517 .default_wm = I965_CURSOR_DFT_WM,
518 .guard_size = 2,
519 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 520};
521static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 522 .fifo_size = I965_CURSOR_FIFO,
523 .max_wm = I965_CURSOR_MAX_WM,
524 .default_wm = I965_CURSOR_DFT_WM,
525 .guard_size = 2,
526 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 527};
528static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 529 .fifo_size = I945_FIFO_SIZE,
530 .max_wm = I915_MAX_WM,
531 .default_wm = 1,
532 .guard_size = 2,
533 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 534};
535static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 536 .fifo_size = I915_FIFO_SIZE,
537 .max_wm = I915_MAX_WM,
538 .default_wm = 1,
539 .guard_size = 2,
540 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 541};
9d539105 542static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 543 .fifo_size = I855GM_FIFO_SIZE,
544 .max_wm = I915_MAX_WM,
545 .default_wm = 1,
546 .guard_size = 2,
547 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 548};
9d539105
VS		 549static const struct intel_watermark_params i830_bc_wm_info = {
550 .fifo_size = I855GM_FIFO_SIZE,
551 .max_wm = I915_MAX_WM/2,
552 .default_wm = 1,
553 .guard_size = 2,
554 .cacheline_size = I830_FIFO_LINE_SIZE,
555};
feb56b93 556static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 557 .fifo_size = I830_FIFO_SIZE,
558 .max_wm = I915_MAX_WM,
559 .default_wm = 1,
560 .guard_size = 2,
561 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 562};
563
b445e3b0
ED		 564/**
565 * intel_calculate_wm - calculate watermark level
566 * @clock_in_khz: pixel clock
567 * @wm: chip FIFO params
568 * @pixel_size: display pixel size
569 * @latency_ns: memory latency for the platform
570 *
571 * Calculate the watermark level (the level at which the display plane will
572 * start fetching from memory again). Each chip has a different display
573 * FIFO size and allocation, so the caller needs to figure that out and pass
574 * in the correct intel_watermark_params structure.
575 *
576 * As the pixel clock runs, the FIFO will be drained at a rate that depends
577 * on the pixel size. When it reaches the watermark level, it'll start
578 * fetching FIFO line sized based chunks from memory until the FIFO fills
579 * past the watermark point. If the FIFO drains completely, a FIFO underrun
580 * will occur, and a display engine hang could result.
581 */
582static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
583 const struct intel_watermark_params *wm,
584 int fifo_size,
585 int pixel_size,
586 unsigned long latency_ns)
587{
588 long entries_required, wm_size;
589
590 /*
591 * Note: we need to make sure we don't overflow for various clock &
592 * latency values.
593 * clocks go from a few thousand to several hundred thousand.
594 * latency is usually a few thousand
595 */
596 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
597 1000;
598 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
599
600 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
601
602 wm_size = fifo_size - (entries_required + wm->guard_size);
603
604 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
605
606 /* Don't promote wm_size to unsigned... */
607 if (wm_size > (long)wm->max_wm)
608 wm_size = wm->max_wm;
609 if (wm_size <= 0)
610 wm_size = wm->default_wm;
d6feb196
VS		 611
612 /*
613 * Bspec seems to indicate that the value shouldn't be lower than
614 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
615 * Lets go for 8 which is the burst size since certain platforms
616 * already use a hardcoded 8 (which is what the spec says should be
617 * done).
618 */
619 if (wm_size <= 8)
620 wm_size = 8;
621
b445e3b0
ED		 622 return wm_size;
623}
624
625static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
626{
627 struct drm_crtc *crtc, *enabled = NULL;
628
70e1e0ec 629 for_each_crtc(dev, crtc) {
3490ea5d 630 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 631 if (enabled)
632 return NULL;
633 enabled = crtc;
634 }
635 }
636
637 return enabled;
638}
639
46ba614c 640static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 641{
46ba614c 642 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 643 struct drm_i915_private *dev_priv = dev->dev_private;
644 struct drm_crtc *crtc;
645 const struct cxsr_latency *latency;
646 u32 reg;
647 unsigned long wm;
648
649 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
650 dev_priv->fsb_freq, dev_priv->mem_freq);
651 if (!latency) {
652 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 653 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 654 return;
655 }
656
657 crtc = single_enabled_crtc(dev);
658 if (crtc) {
241bfc38 659 const struct drm_display_mode *adjusted_mode;
59bea882 660 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 661 int clock;
662
6e3c9717 663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 664 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 665
666 /* Display SR */
667 wm = intel_calculate_wm(clock, &pineview_display_wm,
668 pineview_display_wm.fifo_size,
669 pixel_size, latency->display_sr);
670 reg = I915_READ(DSPFW1);
671 reg &= ~DSPFW_SR_MASK;
f4998963 672 reg |= FW_WM(wm, SR);
b445e3b0
ED		 673 I915_WRITE(DSPFW1, reg);
674 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
675
676 /* cursor SR */
677 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
678 pineview_display_wm.fifo_size,
679 pixel_size, latency->cursor_sr);
680 reg = I915_READ(DSPFW3);
681 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 682 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 683 I915_WRITE(DSPFW3, reg);
684
685 /* Display HPLL off SR */
686 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
687 pineview_display_hplloff_wm.fifo_size,
688 pixel_size, latency->display_hpll_disable);
689 reg = I915_READ(DSPFW3);
690 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 691 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 692 I915_WRITE(DSPFW3, reg);
693
694 /* cursor HPLL off SR */
695 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
696 pineview_display_hplloff_wm.fifo_size,
697 pixel_size, latency->cursor_hpll_disable);
698 reg = I915_READ(DSPFW3);
699 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 700 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 701 I915_WRITE(DSPFW3, reg);
702 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
703
5209b1f4 704 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 705 } else {
5209b1f4 706 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 707 }
708}
709
710static bool g4x_compute_wm0(struct drm_device *dev,
711 int plane,
712 const struct intel_watermark_params *display,
713 int display_latency_ns,
714 const struct intel_watermark_params *cursor,
715 int cursor_latency_ns,
716 int *plane_wm,
717 int *cursor_wm)
718{
719 struct drm_crtc *crtc;
4fe8590a 720 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 721 int htotal, hdisplay, clock, pixel_size;
722 int line_time_us, line_count;
723 int entries, tlb_miss;
724
725 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 726 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 727 *cursor_wm = cursor->guard_size;
728 *plane_wm = display->guard_size;
729 return false;
730 }
731
6e3c9717 732 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 733 clock = adjusted_mode->crtc_clock;
fec8cba3 734 htotal = adjusted_mode->crtc_htotal;
6e3c9717 735 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 736 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 737
738 /* Use the small buffer method to calculate plane watermark */
739 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
740 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
741 if (tlb_miss > 0)
742 entries += tlb_miss;
743 entries = DIV_ROUND_UP(entries, display->cacheline_size);
744 *plane_wm = entries + display->guard_size;
745 if (*plane_wm > (int)display->max_wm)
746 *plane_wm = display->max_wm;
747
748 /* Use the large buffer method to calculate cursor watermark */
922044c9 749 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 750 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 751 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 752 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
753 if (tlb_miss > 0)
754 entries += tlb_miss;
755 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
756 *cursor_wm = entries + cursor->guard_size;
757 if (*cursor_wm > (int)cursor->max_wm)
758 *cursor_wm = (int)cursor->max_wm;
759
760 return true;
761}
762
763/*
764 * Check the wm result.
765 *
766 * If any calculated watermark values is larger than the maximum value that
767 * can be programmed into the associated watermark register, that watermark
768 * must be disabled.
769 */
770static bool g4x_check_srwm(struct drm_device *dev,
771 int display_wm, int cursor_wm,
772 const struct intel_watermark_params *display,
773 const struct intel_watermark_params *cursor)
774{
775 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
776 display_wm, cursor_wm);
777
778 if (display_wm > display->max_wm) {
779 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
780 display_wm, display->max_wm);
781 return false;
782 }
783
784 if (cursor_wm > cursor->max_wm) {
785 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
786 cursor_wm, cursor->max_wm);
787 return false;
788 }
789
790 if (!(display_wm || cursor_wm)) {
791 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
792 return false;
793 }
794
795 return true;
796}
797
798static bool g4x_compute_srwm(struct drm_device *dev,
799 int plane,
800 int latency_ns,
801 const struct intel_watermark_params *display,
802 const struct intel_watermark_params *cursor,
803 int *display_wm, int *cursor_wm)
804{
805 struct drm_crtc *crtc;
4fe8590a 806 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 807 int hdisplay, htotal, pixel_size, clock;
808 unsigned long line_time_us;
809 int line_count, line_size;
810 int small, large;
811 int entries;
812
813 if (!latency_ns) {
814 *display_wm = *cursor_wm = 0;
815 return false;
816 }
817
818 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 819 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 820 clock = adjusted_mode->crtc_clock;
fec8cba3 821 htotal = adjusted_mode->crtc_htotal;
6e3c9717 822 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 823 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 824
922044c9 825 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 826 line_count = (latency_ns / line_time_us + 1000) / 1000;
827 line_size = hdisplay * pixel_size;
828
829 /* Use the minimum of the small and large buffer method for primary */
830 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
831 large = line_count * line_size;
832
833 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
834 *display_wm = entries + display->guard_size;
835
836 /* calculate the self-refresh watermark for display cursor */
3dd512fb 837 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 838 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
839 *cursor_wm = entries + cursor->guard_size;
840
841 return g4x_check_srwm(dev,
842 *display_wm, *cursor_wm,
843 display, cursor);
844}
845
15665979
VS		 846#define FW_WM_VLV(value, plane) \
847 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
848
0018fda1
VS		 849static void vlv_write_wm_values(struct intel_crtc *crtc,
850 const struct vlv_wm_values *wm)
851{
852 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
853 enum pipe pipe = crtc->pipe;
854
855 I915_WRITE(VLV_DDL(pipe),
856 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
857 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
858 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
859 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
860
ae80152d 861 I915_WRITE(DSPFW1,
15665979
VS		 862 FW_WM(wm->sr.plane, SR) |
863 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
864 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
865 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 866 I915_WRITE(DSPFW2,
15665979
VS		 867 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
868 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
869 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 870 I915_WRITE(DSPFW3,
15665979 871 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 872
873 if (IS_CHERRYVIEW(dev_priv)) {
874 I915_WRITE(DSPFW7_CHV,
15665979
VS		 875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 877 I915_WRITE(DSPFW8_CHV,
15665979
VS		 878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
879 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 880 I915_WRITE(DSPFW9_CHV,
15665979
VS		 881 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
882 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 883 I915_WRITE(DSPHOWM,
15665979
VS		 884 FW_WM(wm->sr.plane >> 9, SR_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
886 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
887 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
889 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
890 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
892 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
893 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 894 } else {
895 I915_WRITE(DSPFW7,
15665979
VS		 896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
897 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 898 I915_WRITE(DSPHOWM,
15665979
VS		 899 FW_WM(wm->sr.plane >> 9, SR_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
901 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
902 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
904 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
905 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 906 }
907
908 POSTING_READ(DSPFW1);
909
0018fda1
VS		 910 dev_priv->wm.vlv = *wm;
911}
912
15665979
VS		 913#undef FW_WM_VLV
914
341c526f 915static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
883a3d2f 916 struct drm_plane *plane)
b445e3b0 917{
5e56ba45 918 struct drm_device *dev = crtc->dev;
883a3d2f
VS		 919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
920 int entries, prec_mult, drain_latency, pixel_size;
921 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
341c526f 922 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
b445e3b0 923
883a3d2f
VS		 924 /*
925 * FIXME the plane might have an fb
926 * but be invisible (eg. due to clipping)
927 */
928 if (!intel_crtc->active || !plane->state->fb)
929 return 0;
930
0948c265 931 if (WARN(clock == 0, "Pixel clock is zero!\n"))
341c526f 932 return 0;
b445e3b0 933
883a3d2f
VS		 934 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
935
0948c265 936 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
341c526f 937 return 0;
b445e3b0 938
a398e9c7 939 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
abfc00b5 940
341c526f
VS		 941 prec_mult = high_precision;
942 drain_latency = 64 * prec_mult * 4 / entries;
b445e3b0 943
341c526f
VS		 944 if (drain_latency > DRAIN_LATENCY_MASK) {
945 prec_mult /= 2;
946 drain_latency = 64 * prec_mult * 4 / entries;
abfc00b5
VS		 947 }
948
341c526f
VS		 949 if (drain_latency > DRAIN_LATENCY_MASK)
950 drain_latency = DRAIN_LATENCY_MASK;
b445e3b0 951
341c526f
VS		 952 return drain_latency | (prec_mult == high_precision ?
953 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
b445e3b0
ED		 954}
955
ae80152d
VS		 956static int vlv_compute_wm(struct intel_crtc *crtc,
957 struct intel_plane *plane,
958 int fifo_size)
b445e3b0 959{
ae80152d 960 int clock, entries, pixel_size;
b445e3b0 961
ae80152d
VS		 962 /*
963 * FIXME the plane might have an fb
964 * but be invisible (eg. due to clipping)
965 */
966 if (!crtc->active || !plane->base.state->fb)
967 return 0;
0948c265 968
ae80152d
VS		 969 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
970 clock = crtc->config->base.adjusted_mode.crtc_clock;
b445e3b0 971
ae80152d 972 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
b445e3b0 973
ae80152d
VS		 974 /*
975 * Set up the watermark such that we don't start issuing memory
976 * requests until we are within PND's max deadline value (256us).
977 * Idea being to be idle as long as possible while still taking
978 * advatange of PND's deadline scheduling. The limit of 8
979 * cachelines (used when the FIFO will anyway drain in less time
980 * than 256us) should match what we would be done if trickle
981 * feed were enabled.
982 */
983 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
984}
985
986static bool vlv_compute_sr_wm(struct drm_device *dev,
987 struct vlv_wm_values *wm)
b445e3b0 988{
ae80152d
VS		 989 struct drm_i915_private *dev_priv = to_i915(dev);
990 struct drm_crtc *crtc;
991 enum pipe pipe = INVALID_PIPE;
992 int num_planes = 0;
993 int fifo_size = 0;
994 struct intel_plane *plane;
b445e3b0 995
ae80152d 996 wm->sr.cursor = wm->sr.plane = 0;
b445e3b0 997
ae80152d
VS		 998 crtc = single_enabled_crtc(dev);
999 /* maxfifo not supported on pipe C */
1000 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1001 pipe = to_intel_crtc(crtc)->pipe;
1002 num_planes = !!wm->pipe[pipe].primary +
1003 !!wm->pipe[pipe].sprite[0] +
1004 !!wm->pipe[pipe].sprite[1];
1005 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1006 }
b445e3b0 1007
ae80152d
VS		 1008 if (fifo_size == 0 || num_planes > 1)
1009 return false;
b445e3b0 1010
ae80152d
VS		 1011 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1012 to_intel_plane(crtc->cursor), 0x3f);
b445e3b0 1013
ae80152d
VS		 1014 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1015 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1016 continue;
b445e3b0 1017
ae80152d
VS		 1018 if (plane->pipe != pipe)
1019 continue;
9858425c 1020
ae80152d
VS		 1021 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1022 plane, fifo_size);
1023 if (wm->sr.plane != 0)
1024 break;
1025 }
1026
1027 return true;
b445e3b0
ED		 1028}
1029
ae80152d 1030static void valleyview_update_wm(struct drm_crtc *crtc)
3c2777fd
VS		 1031{
1032 struct drm_device *dev = crtc->dev;
3c2777fd 1033 struct drm_i915_private *dev_priv = dev->dev_private;
ae80152d
VS		 1034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1035 enum pipe pipe = intel_crtc->pipe;
3c2777fd 1036 bool cxsr_enabled;
ae80152d 1037 struct vlv_wm_values wm = dev_priv->wm.vlv;
3c2777fd 1038
ae80152d
VS		 1039 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1040 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1041 to_intel_plane(crtc->primary),
1042 vlv_get_fifo_size(dev, pipe, 0));
3c2777fd 1043
ae80152d
VS		 1044 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1045 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1046 to_intel_plane(crtc->cursor),
1047 0x3f);
3c2777fd 1048
ae80152d 1049 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
3c2777fd 1050
ae80152d
VS		 1051 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1052 return;
3c2777fd 1053
ae80152d
VS		 1054 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1055 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1056 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1057 wm.sr.plane, wm.sr.cursor);
3c2777fd 1058
fc1ac8de
VS		 1059 /*
1060 * FIXME DDR DVFS introduces massive memory latencies which
1061 * are not known to system agent so any deadline specified
1062 * by the display may not be respected. To support DDR DVFS
1063 * the watermark code needs to be rewritten to essentially
1064 * bypass deadline mechanism and rely solely on the
1065 * watermarks. For now disable DDR DVFS.
1066 */
1067 if (IS_CHERRYVIEW(dev_priv))
1068 chv_set_memory_dvfs(dev_priv, false);
1069
ae80152d
VS		 1070 if (!cxsr_enabled)
1071 intel_set_memory_cxsr(dev_priv, false);
3c2777fd 1072
ae80152d 1073 vlv_write_wm_values(intel_crtc, &wm);
3c2777fd
VS		 1074
1075 if (cxsr_enabled)
1076 intel_set_memory_cxsr(dev_priv, true);
1077}
1078
01e184cc
GB		 1079static void valleyview_update_sprite_wm(struct drm_plane *plane,
1080 struct drm_crtc *crtc,
1081 uint32_t sprite_width,
1082 uint32_t sprite_height,
1083 int pixel_size,
1084 bool enabled, bool scaled)
1085{
1086 struct drm_device *dev = crtc->dev;
1087 struct drm_i915_private *dev_priv = dev->dev_private;
0018fda1
VS		 1088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1089 enum pipe pipe = intel_crtc->pipe;
01e184cc 1090 int sprite = to_intel_plane(plane)->plane;
ae80152d 1091 bool cxsr_enabled;
0018fda1 1092 struct vlv_wm_values wm = dev_priv->wm.vlv;
01e184cc 1093
ae80152d 1094 if (enabled) {
0018fda1 1095 wm.ddl[pipe].sprite[sprite] =
883a3d2f 1096 vlv_compute_drain_latency(crtc, plane);
ae80152d
VS		 1097
1098 wm.pipe[pipe].sprite[sprite] =
1099 vlv_compute_wm(intel_crtc,
1100 to_intel_plane(plane),
1101 vlv_get_fifo_size(dev, pipe, sprite+1));
1102 } else {
0018fda1 1103 wm.ddl[pipe].sprite[sprite] = 0;
ae80152d
VS		 1104 wm.pipe[pipe].sprite[sprite] = 0;
1105 }
1106
1107 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1108
1109 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1110 return;
1111
1112 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1113 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1114 sprite_name(pipe, sprite),
1115 wm.pipe[pipe].sprite[sprite],
1116 wm.sr.plane, wm.sr.cursor);
1117
1118 if (!cxsr_enabled)
1119 intel_set_memory_cxsr(dev_priv, false);
01e184cc 1120
0018fda1 1121 vlv_write_wm_values(intel_crtc, &wm);
ae80152d
VS		 1122
1123 if (cxsr_enabled)
1124 intel_set_memory_cxsr(dev_priv, true);
01e184cc
GB		 1125}
1126
ae80152d
VS		 1127#define single_plane_enabled(mask) is_power_of_2(mask)
1128
46ba614c 1129static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1130{
46ba614c 1131 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1132 static const int sr_latency_ns = 12000;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1135 int plane_sr, cursor_sr;
1136 unsigned int enabled = 0;
9858425c 1137 bool cxsr_enabled;
b445e3b0 1138
51cea1f4 1139 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1140 &g4x_wm_info, pessimal_latency_ns,
1141 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1142 &planea_wm, &cursora_wm))
51cea1f4 1143 enabled |= 1 << PIPE_A;
b445e3b0 1144
51cea1f4 1145 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1146 &g4x_wm_info, pessimal_latency_ns,
1147 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1148 &planeb_wm, &cursorb_wm))
51cea1f4 1149 enabled |= 1 << PIPE_B;
b445e3b0 1150
b445e3b0
ED		 1151 if (single_plane_enabled(enabled) &&
1152 g4x_compute_srwm(dev, ffs(enabled) - 1,
1153 sr_latency_ns,
1154 &g4x_wm_info,
1155 &g4x_cursor_wm_info,
52bd02d8 1156 &plane_sr, &cursor_sr)) {
9858425c 1157 cxsr_enabled = true;
52bd02d8 1158 } else {
9858425c 1159 cxsr_enabled = false;
5209b1f4 1160 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1161 plane_sr = cursor_sr = 0;
1162 }
b445e3b0 1163
a5043453
VS		 1164 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1165 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1166 planea_wm, cursora_wm,
1167 planeb_wm, cursorb_wm,
1168 plane_sr, cursor_sr);
1169
1170 I915_WRITE(DSPFW1,
f4998963
VS		 1171 FW_WM(plane_sr, SR) |
1172 FW_WM(cursorb_wm, CURSORB) |
1173 FW_WM(planeb_wm, PLANEB) |
1174 FW_WM(planea_wm, PLANEA));
b445e3b0 1175 I915_WRITE(DSPFW2,
8c919b28 1176 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1177 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1178 /* HPLL off in SR has some issues on G4x... disable it */
1179 I915_WRITE(DSPFW3,
8c919b28 1180 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1181 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1182
1183 if (cxsr_enabled)
1184 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1185}
1186
46ba614c 1187static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1188{
46ba614c 1189 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 struct drm_crtc *crtc;
1192 int srwm = 1;
1193 int cursor_sr = 16;
9858425c 1194 bool cxsr_enabled;
b445e3b0
ED		 1195
1196 /* Calc sr entries for one plane configs */
1197 crtc = single_enabled_crtc(dev);
1198 if (crtc) {
1199 /* self-refresh has much higher latency */
1200 static const int sr_latency_ns = 12000;
4fe8590a 1201 const struct drm_display_mode *adjusted_mode =
6e3c9717 1202 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1203 int clock = adjusted_mode->crtc_clock;
fec8cba3 1204 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1205 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1206 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1207 unsigned long line_time_us;
1208 int entries;
1209
922044c9 1210 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1211
1212 /* Use ns/us then divide to preserve precision */
1213 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1214 pixel_size * hdisplay;
1215 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1216 srwm = I965_FIFO_SIZE - entries;
1217 if (srwm < 0)
1218 srwm = 1;
1219 srwm &= 0x1ff;
1220 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1221 entries, srwm);
1222
1223 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1224 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1225 entries = DIV_ROUND_UP(entries,
1226 i965_cursor_wm_info.cacheline_size);
1227 cursor_sr = i965_cursor_wm_info.fifo_size -
1228 (entries + i965_cursor_wm_info.guard_size);
1229
1230 if (cursor_sr > i965_cursor_wm_info.max_wm)
1231 cursor_sr = i965_cursor_wm_info.max_wm;
1232
1233 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1234 "cursor %d\n", srwm, cursor_sr);
1235
9858425c 1236 cxsr_enabled = true;
b445e3b0 1237 } else {
9858425c 1238 cxsr_enabled = false;
b445e3b0 1239 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1240 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1241 }
1242
1243 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1244 srwm);
1245
1246 /* 965 has limitations... */
f4998963
VS		 1247 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1248 FW_WM(8, CURSORB) |
1249 FW_WM(8, PLANEB) |
1250 FW_WM(8, PLANEA));
1251 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1252 FW_WM(8, PLANEC_OLD));
b445e3b0 1253 /* update cursor SR watermark */
f4998963 1254 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1255
1256 if (cxsr_enabled)
1257 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1258}
1259
f4998963
VS		 1260#undef FW_WM
1261
46ba614c 1262static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1263{
46ba614c 1264 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1265 struct drm_i915_private *dev_priv = dev->dev_private;
1266 const struct intel_watermark_params *wm_info;
1267 uint32_t fwater_lo;
1268 uint32_t fwater_hi;
1269 int cwm, srwm = 1;
1270 int fifo_size;
1271 int planea_wm, planeb_wm;
1272 struct drm_crtc *crtc, *enabled = NULL;
1273
1274 if (IS_I945GM(dev))
1275 wm_info = &i945_wm_info;
1276 else if (!IS_GEN2(dev))
1277 wm_info = &i915_wm_info;
1278 else
9d539105 1279 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1280
1281 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1282 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1283 if (intel_crtc_active(crtc)) {
241bfc38 1284 const struct drm_display_mode *adjusted_mode;
59bea882 1285 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1286 if (IS_GEN2(dev))
1287 cpp = 4;
1288
6e3c9717 1289 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1290 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1291 wm_info, fifo_size, cpp,
5aef6003 1292 pessimal_latency_ns);
b445e3b0 1293 enabled = crtc;
9d539105 1294 } else {
b445e3b0 1295 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1296 if (planea_wm > (long)wm_info->max_wm)
1297 planea_wm = wm_info->max_wm;
1298 }
1299
1300 if (IS_GEN2(dev))
1301 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1302
1303 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1304 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1305 if (intel_crtc_active(crtc)) {
241bfc38 1306 const struct drm_display_mode *adjusted_mode;
59bea882 1307 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1308 if (IS_GEN2(dev))
1309 cpp = 4;
1310
6e3c9717 1311 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1312 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1313 wm_info, fifo_size, cpp,
5aef6003 1314 pessimal_latency_ns);
b445e3b0
ED		 1315 if (enabled == NULL)
1316 enabled = crtc;
1317 else
1318 enabled = NULL;
9d539105 1319 } else {
b445e3b0 1320 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1321 if (planeb_wm > (long)wm_info->max_wm)
1322 planeb_wm = wm_info->max_wm;
1323 }
b445e3b0
ED		 1324
1325 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1326
2ab1bc9d 1327 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1328 struct drm_i915_gem_object *obj;
2ab1bc9d 1329
59bea882 1330 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1331
1332 /* self-refresh seems busted with untiled */
2ff8fde1 1333 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1334 enabled = NULL;
1335 }
1336
b445e3b0
ED		 1337 /*
1338 * Overlay gets an aggressive default since video jitter is bad.
1339 */
1340 cwm = 2;
1341
1342 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1343 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1344
1345 /* Calc sr entries for one plane configs */
1346 if (HAS_FW_BLC(dev) && enabled) {
1347 /* self-refresh has much higher latency */
1348 static const int sr_latency_ns = 6000;
4fe8590a 1349 const struct drm_display_mode *adjusted_mode =
6e3c9717 1350 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1351 int clock = adjusted_mode->crtc_clock;
fec8cba3 1352 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1353 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1354 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1355 unsigned long line_time_us;
1356 int entries;
1357
922044c9 1358 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1359
1360 /* Use ns/us then divide to preserve precision */
1361 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1362 pixel_size * hdisplay;
1363 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1364 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1365 srwm = wm_info->fifo_size - entries;
1366 if (srwm < 0)
1367 srwm = 1;
1368
1369 if (IS_I945G(dev) || IS_I945GM(dev))
1370 I915_WRITE(FW_BLC_SELF,
1371 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1372 else if (IS_I915GM(dev))
1373 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1374 }
1375
1376 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1377 planea_wm, planeb_wm, cwm, srwm);
1378
1379 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1380 fwater_hi = (cwm & 0x1f);
1381
1382 /* Set request length to 8 cachelines per fetch */
1383 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1384 fwater_hi = fwater_hi | (1 << 8);
1385
1386 I915_WRITE(FW_BLC, fwater_lo);
1387 I915_WRITE(FW_BLC2, fwater_hi);
1388
5209b1f4
ID		 1389 if (enabled)
1390 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1391}
1392
feb56b93 1393static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1394{
46ba614c 1395 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 struct drm_crtc *crtc;
241bfc38 1398 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1399 uint32_t fwater_lo;
1400 int planea_wm;
1401
1402 crtc = single_enabled_crtc(dev);
1403 if (crtc == NULL)
1404 return;
1405
6e3c9717 1406 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1407 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1408 &i845_wm_info,
b445e3b0 1409 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1410 4, pessimal_latency_ns);
b445e3b0
ED		 1411 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1412 fwater_lo |= (3<<8) | planea_wm;
1413
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1415
1416 I915_WRITE(FW_BLC, fwater_lo);
1417}
1418
3658729a
VS		 1419static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1420 struct drm_crtc *crtc)
801bcfff
PZ		 1421{
1422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1423 uint32_t pixel_rate;
801bcfff 1424
6e3c9717 1425 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1426
1427 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1428 * adjust the pixel_rate here. */
1429
6e3c9717 1430 if (intel_crtc->config->pch_pfit.enabled) {
801bcfff 1431 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6e3c9717 1432 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
801bcfff 1433
6e3c9717
ACO		 1434 pipe_w = intel_crtc->config->pipe_src_w;
1435 pipe_h = intel_crtc->config->pipe_src_h;
801bcfff
PZ		 1436 pfit_w = (pfit_size >> 16) & 0xFFFF;
1437 pfit_h = pfit_size & 0xFFFF;
1438 if (pipe_w < pfit_w)
1439 pipe_w = pfit_w;
1440 if (pipe_h < pfit_h)
1441 pipe_h = pfit_h;
1442
1443 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1444 pfit_w * pfit_h);
1445 }
1446
1447 return pixel_rate;
1448}
1449
37126462 1450/* latency must be in 0.1us units. */
23297044 1451static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1452 uint32_t latency)
1453{
1454 uint64_t ret;
1455
3312ba65
VS		 1456 if (WARN(latency == 0, "Latency value missing\n"))
1457 return UINT_MAX;
1458
801bcfff
PZ		 1459 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1460 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1461
1462 return ret;
1463}
1464
37126462 1465/* latency must be in 0.1us units. */
23297044 1466static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1467 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1468 uint32_t latency)
1469{
1470 uint32_t ret;
1471
3312ba65
VS		 1472 if (WARN(latency == 0, "Latency value missing\n"))
1473 return UINT_MAX;
1474
801bcfff
PZ		 1475 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1476 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1477 ret = DIV_ROUND_UP(ret, 64) + 2;
1478 return ret;
1479}
1480
23297044 1481static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1482 uint8_t bytes_per_pixel)
1483{
1484 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1485}
1486
2ac96d2a
PB		 1487struct skl_pipe_wm_parameters {
1488 bool active;
1489 uint32_t pipe_htotal;
1490 uint32_t pixel_rate; /* in KHz */
1491 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1492 struct intel_plane_wm_parameters cursor;
1493};
1494
820c1980 1495struct ilk_pipe_wm_parameters {
801bcfff 1496 bool active;
801bcfff
PZ		 1497 uint32_t pipe_htotal;
1498 uint32_t pixel_rate;
c35426d2
VS		 1499 struct intel_plane_wm_parameters pri;
1500 struct intel_plane_wm_parameters spr;
1501 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1502};
1503
820c1980 1504struct ilk_wm_maximums {
cca32e9a
PZ		 1505 uint16_t pri;
1506 uint16_t spr;
1507 uint16_t cur;
1508 uint16_t fbc;
1509};
1510
240264f4
VS		 1511/* used in computing the new watermarks state */
1512struct intel_wm_config {
1513 unsigned int num_pipes_active;
1514 bool sprites_enabled;
1515 bool sprites_scaled;
240264f4
VS		 1516};
1517
37126462
VS		 1518/*
1519 * For both WM_PIPE and WM_LP.
1520 * mem_value must be in 0.1us units.
1521 */
820c1980 1522static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1523 uint32_t mem_value,
1524 bool is_lp)
801bcfff 1525{
cca32e9a
PZ		 1526 uint32_t method1, method2;
1527
c35426d2 1528 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1529 return 0;
1530
23297044 1531 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1532 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1533 mem_value);
1534
1535 if (!is_lp)
1536 return method1;
1537
23297044 1538 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1539 params->pipe_htotal,
c35426d2
VS		 1540 params->pri.horiz_pixels,
1541 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1542 mem_value);
1543
1544 return min(method1, method2);
801bcfff
PZ		 1545}
1546
37126462
VS		 1547/*
1548 * For both WM_PIPE and WM_LP.
1549 * mem_value must be in 0.1us units.
1550 */
820c1980 1551static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1552 uint32_t mem_value)
1553{
1554 uint32_t method1, method2;
1555
c35426d2 1556 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1557 return 0;
1558
23297044 1559 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1560 params->spr.bytes_per_pixel,
801bcfff 1561 mem_value);
23297044 1562 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1563 params->pipe_htotal,
c35426d2
VS		 1564 params->spr.horiz_pixels,
1565 params->spr.bytes_per_pixel,
801bcfff
PZ		 1566 mem_value);
1567 return min(method1, method2);
1568}
1569
37126462
VS		 1570/*
1571 * For both WM_PIPE and WM_LP.
1572 * mem_value must be in 0.1us units.
1573 */
820c1980 1574static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1575 uint32_t mem_value)
1576{
c35426d2 1577 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1578 return 0;
1579
23297044 1580 return ilk_wm_method2(params->pixel_rate,
801bcfff 1581 params->pipe_htotal,
c35426d2
VS		 1582 params->cur.horiz_pixels,
1583 params->cur.bytes_per_pixel,
801bcfff
PZ		 1584 mem_value);
1585}
1586
cca32e9a 1587/* Only for WM_LP. */
820c1980 1588static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1589 uint32_t pri_val)
cca32e9a 1590{
c35426d2 1591 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1592 return 0;
1593
23297044 1594 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1595 params->pri.horiz_pixels,
1596 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1597}
1598
158ae64f
VS		 1599static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1600{
416f4727
VS		 1601 if (INTEL_INFO(dev)->gen >= 8)
1602 return 3072;
1603 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1604 return 768;
1605 else
1606 return 512;
1607}
1608
4e975081
VS		 1609static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1610 int level, bool is_sprite)
1611{
1612 if (INTEL_INFO(dev)->gen >= 8)
1613 /* BDW primary/sprite plane watermarks */
1614 return level == 0 ? 255 : 2047;
1615 else if (INTEL_INFO(dev)->gen >= 7)
1616 /* IVB/HSW primary/sprite plane watermarks */
1617 return level == 0 ? 127 : 1023;
1618 else if (!is_sprite)
1619 /* ILK/SNB primary plane watermarks */
1620 return level == 0 ? 127 : 511;
1621 else
1622 /* ILK/SNB sprite plane watermarks */
1623 return level == 0 ? 63 : 255;
1624}
1625
1626static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1627 int level)
1628{
1629 if (INTEL_INFO(dev)->gen >= 7)
1630 return level == 0 ? 63 : 255;
1631 else
1632 return level == 0 ? 31 : 63;
1633}
1634
1635static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1636{
1637 if (INTEL_INFO(dev)->gen >= 8)
1638 return 31;
1639 else
1640 return 15;
1641}
1642
158ae64f
VS		 1643/* Calculate the maximum primary/sprite plane watermark */
1644static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1645 int level,
240264f4 1646 const struct intel_wm_config *config,
158ae64f
VS		 1647 enum intel_ddb_partitioning ddb_partitioning,
1648 bool is_sprite)
1649{
1650 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1651
1652 /* if sprites aren't enabled, sprites get nothing */
240264f4 1653 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1654 return 0;
1655
1656 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1657 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1658 fifo_size /= INTEL_INFO(dev)->num_pipes;
1659
1660 /*
1661 * For some reason the non self refresh
1662 * FIFO size is only half of the self
1663 * refresh FIFO size on ILK/SNB.
1664 */
1665 if (INTEL_INFO(dev)->gen <= 6)
1666 fifo_size /= 2;
1667 }
1668
240264f4 1669 if (config->sprites_enabled) {
158ae64f
VS		 1670 /* level 0 is always calculated with 1:1 split */
1671 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1672 if (is_sprite)
1673 fifo_size *= 5;
1674 fifo_size /= 6;
1675 } else {
1676 fifo_size /= 2;
1677 }
1678 }
1679
1680 /* clamp to max that the registers can hold */
4e975081 1681 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1682}
1683
1684/* Calculate the maximum cursor plane watermark */
1685static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1686 int level,
1687 const struct intel_wm_config *config)
158ae64f
VS		 1688{
1689 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1690 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1691 return 64;
1692
1693 /* otherwise just report max that registers can hold */
4e975081 1694 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1695}
1696
d34ff9c6 1697static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1698 int level,
1699 const struct intel_wm_config *config,
1700 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1701 struct ilk_wm_maximums *max)
158ae64f 1702{
240264f4
VS		 1703 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1704 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1705 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1706 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1707}
1708
a3cb4048
VS		 1709static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1710 int level,
1711 struct ilk_wm_maximums *max)
1712{
1713 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1714 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1715 max->cur = ilk_cursor_wm_reg_max(dev, level);
1716 max->fbc = ilk_fbc_wm_reg_max(dev);
1717}
1718
d9395655 1719static bool ilk_validate_wm_level(int level,
820c1980 1720 const struct ilk_wm_maximums *max,
d9395655 1721 struct intel_wm_level *result)
a9786a11
VS		 1722{
1723 bool ret;
1724
1725 /* already determined to be invalid? */
1726 if (!result->enable)
1727 return false;
1728
1729 result->enable = result->pri_val <= max->pri &&
1730 result->spr_val <= max->spr &&
1731 result->cur_val <= max->cur;
1732
1733 ret = result->enable;
1734
1735 /*
1736 * HACK until we can pre-compute everything,
1737 * and thus fail gracefully if LP0 watermarks
1738 * are exceeded...
1739 */
1740 if (level == 0 && !result->enable) {
1741 if (result->pri_val > max->pri)
1742 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1743 level, result->pri_val, max->pri);
1744 if (result->spr_val > max->spr)
1745 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1746 level, result->spr_val, max->spr);
1747 if (result->cur_val > max->cur)
1748 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1749 level, result->cur_val, max->cur);
1750
1751 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1752 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1753 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1754 result->enable = true;
1755 }
1756
a9786a11
VS		 1757 return ret;
1758}
1759
d34ff9c6 1760static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1761 int level,
820c1980 1762 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1763 struct intel_wm_level *result)
6f5ddd17
VS		 1764{
1765 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1766 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1767 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1768
1769 /* WM1+ latency values stored in 0.5us units */
1770 if (level > 0) {
1771 pri_latency *= 5;
1772 spr_latency *= 5;
1773 cur_latency *= 5;
1774 }
1775
1776 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1777 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1778 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1779 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1780 result->enable = true;
1781}
1782
801bcfff
PZ		 1783static uint32_t
1784hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1785{
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1788 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1789 u32 linetime, ips_linetime;
1f8eeabf 1790
3ef00284 1791 if (!intel_crtc->active)
801bcfff 1792 return 0;
1011d8c4 1793
1f8eeabf
ED		 1794 /* The WM are computed with base on how long it takes to fill a single
1795 * row at the given clock rate, multiplied by 8.
1796 * */
fec8cba3
JB		 1797 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1798 mode->crtc_clock);
1799 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 1800 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 1801
801bcfff
PZ		 1802 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1803 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1804}
1805
2af30a5c 1806static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 1807{
1808 struct drm_i915_private *dev_priv = dev->dev_private;
1809
2af30a5c
PB		 1810 if (IS_GEN9(dev)) {
1811 uint32_t val;
4f947386 1812 int ret, i;
367294be 1813 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 1814
1815 /* read the first set of memory latencies[0:3] */
1816 val = 0; /* data0 to be programmed to 0 for first set */
1817 mutex_lock(&dev_priv->rps.hw_lock);
1818 ret = sandybridge_pcode_read(dev_priv,
1819 GEN9_PCODE_READ_MEM_LATENCY,
1820 &val);
1821 mutex_unlock(&dev_priv->rps.hw_lock);
1822
1823 if (ret) {
1824 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1825 return;
1826 }
1827
1828 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1829 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1830 GEN9_MEM_LATENCY_LEVEL_MASK;
1831 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1832 GEN9_MEM_LATENCY_LEVEL_MASK;
1833 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1834 GEN9_MEM_LATENCY_LEVEL_MASK;
1835
1836 /* read the second set of memory latencies[4:7] */
1837 val = 1; /* data0 to be programmed to 1 for second set */
1838 mutex_lock(&dev_priv->rps.hw_lock);
1839 ret = sandybridge_pcode_read(dev_priv,
1840 GEN9_PCODE_READ_MEM_LATENCY,
1841 &val);
1842 mutex_unlock(&dev_priv->rps.hw_lock);
1843 if (ret) {
1844 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1845 return;
1846 }
1847
1848 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1849 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1850 GEN9_MEM_LATENCY_LEVEL_MASK;
1851 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1852 GEN9_MEM_LATENCY_LEVEL_MASK;
1853 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1854 GEN9_MEM_LATENCY_LEVEL_MASK;
1855
367294be 1856 /*
6f97235b
DL		 1857 * WaWmMemoryReadLatency:skl
1858 *
367294be
VK		 1859 * punit doesn't take into account the read latency so we need
1860 * to add 2us to the various latency levels we retrieve from
1861 * the punit.
1862 * - W0 is a bit special in that it's the only level that
1863 * can't be disabled if we want to have display working, so
1864 * we always add 2us there.
1865 * - For levels >=1, punit returns 0us latency when they are
1866 * disabled, so we respect that and don't add 2us then
4f947386
VK		 1867 *
1868 * Additionally, if a level n (n > 1) has a 0us latency, all
1869 * levels m (m >= n) need to be disabled. We make sure to
1870 * sanitize the values out of the punit to satisfy this
1871 * requirement.
367294be
VK		 1872 */
1873 wm[0] += 2;
1874 for (level = 1; level <= max_level; level++)
1875 if (wm[level] != 0)
1876 wm[level] += 2;
4f947386
VK		 1877 else {
1878 for (i = level + 1; i <= max_level; i++)
1879 wm[i] = 0;
367294be 1880
4f947386
VK		 1881 break;
1882 }
2af30a5c 1883 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 1884 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1885
1886 wm[0] = (sskpd >> 56) & 0xFF;
1887 if (wm[0] == 0)
1888 wm[0] = sskpd & 0xF;
e5d5019e
VS		 1889 wm[1] = (sskpd >> 4) & 0xFF;
1890 wm[2] = (sskpd >> 12) & 0xFF;
1891 wm[3] = (sskpd >> 20) & 0x1FF;
1892 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 1893 } else if (INTEL_INFO(dev)->gen >= 6) {
1894 uint32_t sskpd = I915_READ(MCH_SSKPD);
1895
1896 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1897 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1898 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1899 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 1900 } else if (INTEL_INFO(dev)->gen >= 5) {
1901 uint32_t mltr = I915_READ(MLTR_ILK);
1902
1903 /* ILK primary LP0 latency is 700 ns */
1904 wm[0] = 7;
1905 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1906 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 1907 }
1908}
1909
53615a5e
VS		 1910static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1911{
1912 /* ILK sprite LP0 latency is 1300 ns */
1913 if (INTEL_INFO(dev)->gen == 5)
1914 wm[0] = 13;
1915}
1916
1917static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1918{
1919 /* ILK cursor LP0 latency is 1300 ns */
1920 if (INTEL_INFO(dev)->gen == 5)
1921 wm[0] = 13;
1922
1923 /* WaDoubleCursorLP3Latency:ivb */
1924 if (IS_IVYBRIDGE(dev))
1925 wm[3] *= 2;
1926}
1927
546c81fd 1928int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1929{
26ec971e 1930 /* how many WM levels are we expecting */
2af30a5c
PB		 1931 if (IS_GEN9(dev))
1932 return 7;
1933 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1934 return 4;
26ec971e 1935 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1936 return 3;
26ec971e 1937 else
ad0d6dc4
VS		 1938 return 2;
1939}
7526ed79 1940
ad0d6dc4
VS		 1941static void intel_print_wm_latency(struct drm_device *dev,
1942 const char *name,
2af30a5c 1943 const uint16_t wm[8])
ad0d6dc4
VS		 1944{
1945 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 1946
1947 for (level = 0; level <= max_level; level++) {
1948 unsigned int latency = wm[level];
1949
1950 if (latency == 0) {
1951 DRM_ERROR("%s WM%d latency not provided\n",
1952 name, level);
1953 continue;
1954 }
1955
2af30a5c
PB		 1956 /*
1957 * - latencies are in us on gen9.
1958 * - before then, WM1+ latency values are in 0.5us units
1959 */
1960 if (IS_GEN9(dev))
1961 latency *= 10;
1962 else if (level > 0)
26ec971e
VS		 1963 latency *= 5;
1964
1965 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1966 name, level, wm[level],
1967 latency / 10, latency % 10);
1968 }
1969}
1970
e95a2f75
VS		 1971static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1972 uint16_t wm[5], uint16_t min)
1973{
1974 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1975
1976 if (wm[0] >= min)
1977 return false;
1978
1979 wm[0] = max(wm[0], min);
1980 for (level = 1; level <= max_level; level++)
1981 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1982
1983 return true;
1984}
1985
1986static void snb_wm_latency_quirk(struct drm_device *dev)
1987{
1988 struct drm_i915_private *dev_priv = dev->dev_private;
1989 bool changed;
1990
1991 /*
1992 * The BIOS provided WM memory latency values are often
1993 * inadequate for high resolution displays. Adjust them.
1994 */
1995 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1996 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1997 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1998
1999 if (!changed)
2000 return;
2001
2002 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2003 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2004 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2005 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2006}
2007
fa50ad61 2008static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2009{
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011
2012 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2013
2014 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2015 sizeof(dev_priv->wm.pri_latency));
2016 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2017 sizeof(dev_priv->wm.pri_latency));
2018
2019 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2020 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2021
2022 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2023 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2024 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2025
2026 if (IS_GEN6(dev))
2027 snb_wm_latency_quirk(dev);
53615a5e
VS		 2028}
2029
2af30a5c
PB		 2030static void skl_setup_wm_latency(struct drm_device *dev)
2031{
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2033
2034 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2035 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2036}
2037
820c1980 2038static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2039 struct ilk_pipe_wm_parameters *p)
1011d8c4 2040{
7c4a395f
VS		 2041 struct drm_device *dev = crtc->dev;
2042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2043 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2044 struct drm_plane *plane;
1011d8c4 2045
3ef00284 2046 if (!intel_crtc->active)
2a44b76b 2047 return;
801bcfff 2048
2a44b76b 2049 p->active = true;
6e3c9717 2050 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2a44b76b 2051 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c9f038a1
MR		 2052
2053 if (crtc->primary->state->fb) {
2054 p->pri.enabled = true;
2055 p->pri.bytes_per_pixel =
2056 crtc->primary->state->fb->bits_per_pixel / 8;
2057 } else {
2058 p->pri.enabled = false;
2059 p->pri.bytes_per_pixel = 0;
2060 }
2061
2062 if (crtc->cursor->state->fb) {
2063 p->cur.enabled = true;
2064 p->cur.bytes_per_pixel = 4;
2065 } else {
2066 p->cur.enabled = false;
2067 p->cur.bytes_per_pixel = 0;
2068 }
6e3c9717 2069 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2070 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2071
af2b653b 2072 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2073 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2074
2a44b76b 2075 if (intel_plane->pipe == pipe) {
7c4a395f 2076 p->spr = intel_plane->wm;
2a44b76b
VS		 2077 break;
2078 }
2079 }
2080}
2081
2082static void ilk_compute_wm_config(struct drm_device *dev,
2083 struct intel_wm_config *config)
2084{
2085 struct intel_crtc *intel_crtc;
2086
2087 /* Compute the currently _active_ config */
d3fcc808 2088 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2089 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2090
2a44b76b
VS		 2091 if (!wm->pipe_enabled)
2092 continue;
cca32e9a 2093
2a44b76b
VS		 2094 config->sprites_enabled |= wm->sprites_enabled;
2095 config->sprites_scaled |= wm->sprites_scaled;
2096 config->num_pipes_active++;
cca32e9a 2097 }
801bcfff
PZ		 2098}
2099
0b2ae6d7
VS		 2100/* Compute new watermarks for the pipe */
2101static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2102 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2103 struct intel_pipe_wm *pipe_wm)
2104{
2105 struct drm_device *dev = crtc->dev;
d34ff9c6 2106 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2107 int level, max_level = ilk_wm_max_level(dev);
2108 /* LP0 watermark maximums depend on this pipe alone */
2109 struct intel_wm_config config = {
2110 .num_pipes_active = 1,
2111 .sprites_enabled = params->spr.enabled,
2112 .sprites_scaled = params->spr.scaled,
2113 };
820c1980 2114 struct ilk_wm_maximums max;
0b2ae6d7 2115
2a44b76b
VS		 2116 pipe_wm->pipe_enabled = params->active;
2117 pipe_wm->sprites_enabled = params->spr.enabled;
2118 pipe_wm->sprites_scaled = params->spr.scaled;
2119
7b39a0b7
VS		 2120 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2121 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2122 max_level = 1;
2123
2124 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2125 if (params->spr.scaled)
2126 max_level = 0;
2127
a3cb4048 2128 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2129
a42a5719 2130 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2131 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2132
a3cb4048
VS		 2133 /* LP0 watermarks always use 1/2 DDB partitioning */
2134 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2135
0b2ae6d7 2136 /* At least LP0 must be valid */
a3cb4048
VS		 2137 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2138 return false;
2139
2140 ilk_compute_wm_reg_maximums(dev, 1, &max);
2141
2142 for (level = 1; level <= max_level; level++) {
2143 struct intel_wm_level wm = {};
2144
2145 ilk_compute_wm_level(dev_priv, level, params, &wm);
2146
2147 /*
2148 * Disable any watermark level that exceeds the
2149 * register maximums since such watermarks are
2150 * always invalid.
2151 */
2152 if (!ilk_validate_wm_level(level, &max, &wm))
2153 break;
2154
2155 pipe_wm->wm[level] = wm;
2156 }
2157
2158 return true;
0b2ae6d7
VS		 2159}
2160
2161/*
2162 * Merge the watermarks from all active pipes for a specific level.
2163 */
2164static void ilk_merge_wm_level(struct drm_device *dev,
2165 int level,
2166 struct intel_wm_level *ret_wm)
2167{
2168 const struct intel_crtc *intel_crtc;
2169
d52fea5b
VS		 2170 ret_wm->enable = true;
2171
d3fcc808 2172 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2173 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2174 const struct intel_wm_level *wm = &active->wm[level];
2175
2176 if (!active->pipe_enabled)
2177 continue;
0b2ae6d7 2178
d52fea5b
VS		 2179 /*
2180 * The watermark values may have been used in the past,
2181 * so we must maintain them in the registers for some
2182 * time even if the level is now disabled.
2183 */
0b2ae6d7 2184 if (!wm->enable)
d52fea5b 2185 ret_wm->enable = false;
0b2ae6d7
VS		 2186
2187 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2188 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2189 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2190 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2191 }
0b2ae6d7
VS		 2192}
2193
2194/*
2195 * Merge all low power watermarks for all active pipes.
2196 */
2197static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2198 const struct intel_wm_config *config,
820c1980 2199 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2200 struct intel_pipe_wm *merged)
2201{
2202 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2203 int last_enabled_level = max_level;
0b2ae6d7 2204
0ba22e26
VS		 2205 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2206 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2207 config->num_pipes_active > 1)
2208 return;
2209
6c8b6c28
VS		 2210 /* ILK: FBC WM must be disabled always */
2211 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2212
2213 /* merge each WM1+ level */
2214 for (level = 1; level <= max_level; level++) {
2215 struct intel_wm_level *wm = &merged->wm[level];
2216
2217 ilk_merge_wm_level(dev, level, wm);
2218
d52fea5b
VS		 2219 if (level > last_enabled_level)
2220 wm->enable = false;
2221 else if (!ilk_validate_wm_level(level, max, wm))
2222 /* make sure all following levels get disabled */
2223 last_enabled_level = level - 1;
0b2ae6d7
VS		 2224
2225 /*
2226 * The spec says it is preferred to disable
2227 * FBC WMs instead of disabling a WM level.
2228 */
2229 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2230 if (wm->enable)
2231 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2232 wm->fbc_val = 0;
2233 }
2234 }
6c8b6c28
VS		 2235
2236 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2237 /*
2238 * FIXME this is racy. FBC might get enabled later.
2239 * What we should check here is whether FBC can be
2240 * enabled sometime later.
2241 */
2242 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2243 for (level = 2; level <= max_level; level++) {
2244 struct intel_wm_level *wm = &merged->wm[level];
2245
2246 wm->enable = false;
2247 }
2248 }
0b2ae6d7
VS		 2249}
2250
b380ca3c
VS		 2251static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2252{
2253 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2254 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2255}
2256
a68d68ee
VS		 2257/* The value we need to program into the WM_LPx latency field */
2258static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2259{
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2261
a42a5719 2262 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2263 return 2 * level;
2264 else
2265 return dev_priv->wm.pri_latency[level];
2266}
2267
820c1980 2268static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2269 const struct intel_pipe_wm *merged,
609cedef 2270 enum intel_ddb_partitioning partitioning,
820c1980 2271 struct ilk_wm_values *results)
801bcfff 2272{
0b2ae6d7
VS		 2273 struct intel_crtc *intel_crtc;
2274 int level, wm_lp;
cca32e9a 2275
0362c781 2276 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2277 results->partitioning = partitioning;
cca32e9a 2278
0b2ae6d7 2279 /* LP1+ register values */
cca32e9a 2280 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2281 const struct intel_wm_level *r;
801bcfff 2282
b380ca3c 2283 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2284
0362c781 2285 r = &merged->wm[level];
cca32e9a 2286
d52fea5b
VS		 2287 /*
2288 * Maintain the watermark values even if the level is
2289 * disabled. Doing otherwise could cause underruns.
2290 */
2291 results->wm_lp[wm_lp - 1] =
a68d68ee 2292 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2293 (r->pri_val << WM1_LP_SR_SHIFT) |
2294 r->cur_val;
2295
d52fea5b
VS		 2296 if (r->enable)
2297 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2298
416f4727
VS		 2299 if (INTEL_INFO(dev)->gen >= 8)
2300 results->wm_lp[wm_lp - 1] |=
2301 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2302 else
2303 results->wm_lp[wm_lp - 1] |=
2304 r->fbc_val << WM1_LP_FBC_SHIFT;
2305
d52fea5b
VS		 2306 /*
2307 * Always set WM1S_LP_EN when spr_val != 0, even if the
2308 * level is disabled. Doing otherwise could cause underruns.
2309 */
6cef2b8a
VS		 2310 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2311 WARN_ON(wm_lp != 1);
2312 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2313 } else
2314 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2315 }
801bcfff 2316
0b2ae6d7 2317 /* LP0 register values */
d3fcc808 2318 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2319 enum pipe pipe = intel_crtc->pipe;
2320 const struct intel_wm_level *r =
2321 &intel_crtc->wm.active.wm[0];
2322
2323 if (WARN_ON(!r->enable))
2324 continue;
2325
2326 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2327
0b2ae6d7
VS		 2328 results->wm_pipe[pipe] =
2329 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2330 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2331 r->cur_val;
801bcfff
PZ		 2332 }
2333}
2334
861f3389
PZ		 2335/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2336 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2337static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2338 struct intel_pipe_wm *r1,
2339 struct intel_pipe_wm *r2)
861f3389 2340{
198a1e9b
VS		 2341 int level, max_level = ilk_wm_max_level(dev);
2342 int level1 = 0, level2 = 0;
861f3389 2343
198a1e9b
VS		 2344 for (level = 1; level <= max_level; level++) {
2345 if (r1->wm[level].enable)
2346 level1 = level;
2347 if (r2->wm[level].enable)
2348 level2 = level;
861f3389
PZ		 2349 }
2350
198a1e9b
VS		 2351 if (level1 == level2) {
2352 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2353 return r2;
2354 else
2355 return r1;
198a1e9b 2356 } else if (level1 > level2) {
861f3389
PZ		 2357 return r1;
2358 } else {
2359 return r2;
2360 }
2361}
2362
49a687c4
VS		 2363/* dirty bits used to track which watermarks need changes */
2364#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2365#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2366#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2367#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2368#define WM_DIRTY_FBC (1 << 24)
2369#define WM_DIRTY_DDB (1 << 25)
2370
055e393f 2371static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2372 const struct ilk_wm_values *old,
2373 const struct ilk_wm_values *new)
49a687c4
VS		 2374{
2375 unsigned int dirty = 0;
2376 enum pipe pipe;
2377 int wm_lp;
2378
055e393f 2379 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2380 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2381 dirty |= WM_DIRTY_LINETIME(pipe);
2382 /* Must disable LP1+ watermarks too */
2383 dirty |= WM_DIRTY_LP_ALL;
2384 }
2385
2386 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2387 dirty |= WM_DIRTY_PIPE(pipe);
2388 /* Must disable LP1+ watermarks too */
2389 dirty |= WM_DIRTY_LP_ALL;
2390 }
2391 }
2392
2393 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2394 dirty |= WM_DIRTY_FBC;
2395 /* Must disable LP1+ watermarks too */
2396 dirty |= WM_DIRTY_LP_ALL;
2397 }
2398
2399 if (old->partitioning != new->partitioning) {
2400 dirty |= WM_DIRTY_DDB;
2401 /* Must disable LP1+ watermarks too */
2402 dirty |= WM_DIRTY_LP_ALL;
2403 }
2404
2405 /* LP1+ watermarks already deemed dirty, no need to continue */
2406 if (dirty & WM_DIRTY_LP_ALL)
2407 return dirty;
2408
2409 /* Find the lowest numbered LP1+ watermark in need of an update... */
2410 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2411 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2412 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2413 break;
2414 }
2415
2416 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2417 for (; wm_lp <= 3; wm_lp++)
2418 dirty |= WM_DIRTY_LP(wm_lp);
2419
2420 return dirty;
2421}
2422
8553c18e
VS		 2423static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2424 unsigned int dirty)
801bcfff 2425{
820c1980 2426 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2427 bool changed = false;
801bcfff 2428
facd619b
VS		 2429 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2430 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2431 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2432 changed = true;
facd619b
VS		 2433 }
2434 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2435 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2436 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2437 changed = true;
facd619b
VS		 2438 }
2439 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2440 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2441 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2442 changed = true;
facd619b 2443 }
801bcfff 2444
facd619b
VS		 2445 /*
2446 * Don't touch WM1S_LP_EN here.
2447 * Doing so could cause underruns.
2448 */
6cef2b8a 2449
8553c18e
VS		 2450 return changed;
2451}
2452
2453/*
2454 * The spec says we shouldn't write when we don't need, because every write
2455 * causes WMs to be re-evaluated, expending some power.
2456 */
820c1980
ID		 2457static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2458 struct ilk_wm_values *results)
8553c18e
VS		 2459{
2460 struct drm_device *dev = dev_priv->dev;
820c1980 2461 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2462 unsigned int dirty;
2463 uint32_t val;
2464
055e393f 2465 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2466 if (!dirty)
2467 return;
2468
2469 _ilk_disable_lp_wm(dev_priv, dirty);
2470
49a687c4 2471 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2472 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2473 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2474 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2475 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2476 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2477
49a687c4 2478 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2479 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2480 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2481 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2482 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2483 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2484
49a687c4 2485 if (dirty & WM_DIRTY_DDB) {
a42a5719 2486 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2487 val = I915_READ(WM_MISC);
2488 if (results->partitioning == INTEL_DDB_PART_1_2)
2489 val &= ~WM_MISC_DATA_PARTITION_5_6;
2490 else
2491 val |= WM_MISC_DATA_PARTITION_5_6;
2492 I915_WRITE(WM_MISC, val);
2493 } else {
2494 val = I915_READ(DISP_ARB_CTL2);
2495 if (results->partitioning == INTEL_DDB_PART_1_2)
2496 val &= ~DISP_DATA_PARTITION_5_6;
2497 else
2498 val |= DISP_DATA_PARTITION_5_6;
2499 I915_WRITE(DISP_ARB_CTL2, val);
2500 }
1011d8c4
PZ		 2501 }
2502
49a687c4 2503 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2504 val = I915_READ(DISP_ARB_CTL);
2505 if (results->enable_fbc_wm)
2506 val &= ~DISP_FBC_WM_DIS;
2507 else
2508 val |= DISP_FBC_WM_DIS;
2509 I915_WRITE(DISP_ARB_CTL, val);
2510 }
2511
954911eb
ID		 2512 if (dirty & WM_DIRTY_LP(1) &&
2513 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2514 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2515
2516 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2517 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2518 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2519 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2520 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2521 }
801bcfff 2522
facd619b 2523 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2524 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2525 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2526 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2527 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2528 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2529
2530 dev_priv->wm.hw = *results;
801bcfff
PZ		 2531}
2532
8553c18e
VS		 2533static bool ilk_disable_lp_wm(struct drm_device *dev)
2534{
2535 struct drm_i915_private *dev_priv = dev->dev_private;
2536
2537 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2538}
2539
b9cec075
DL		 2540/*
2541 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2542 * different active planes.
2543 */
2544
2545#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2546#define BXT_DDB_SIZE 512
b9cec075
DL		 2547
2548static void
2549skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2550 struct drm_crtc *for_crtc,
2551 const struct intel_wm_config *config,
2552 const struct skl_pipe_wm_parameters *params,
2553 struct skl_ddb_entry *alloc /* out */)
2554{
2555 struct drm_crtc *crtc;
2556 unsigned int pipe_size, ddb_size;
2557 int nth_active_pipe;
2558
2559 if (!params->active) {
2560 alloc->start = 0;
2561 alloc->end = 0;
2562 return;
2563 }
2564
43d735a6
DL		 2565 if (IS_BROXTON(dev))
2566 ddb_size = BXT_DDB_SIZE;
2567 else
2568 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2569
2570 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2571
2572 nth_active_pipe = 0;
2573 for_each_crtc(dev, crtc) {
3ef00284 2574 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2575 continue;
2576
2577 if (crtc == for_crtc)
2578 break;
2579
2580 nth_active_pipe++;
2581 }
2582
2583 pipe_size = ddb_size / config->num_pipes_active;
2584 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2585 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2586}
2587
2588static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2589{
2590 if (config->num_pipes_active == 1)
2591 return 32;
2592
2593 return 8;
2594}
2595
a269c583
DL		 2596static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2597{
2598 entry->start = reg & 0x3ff;
2599 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2600 if (entry->end)
2601 entry->end += 1;
a269c583
DL		 2602}
2603
08db6652
DL		 2604void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2605 struct skl_ddb_allocation *ddb /* out */)
a269c583 2606{
a269c583
DL		 2607 enum pipe pipe;
2608 int plane;
2609 u32 val;
2610
2611 for_each_pipe(dev_priv, pipe) {
dd740780 2612 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2613 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2614 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2615 val);
2616 }
2617
2618 val = I915_READ(CUR_BUF_CFG(pipe));
2619 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2620 }
2621}
2622
b9cec075
DL		 2623static unsigned int
2624skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2625{
2626 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2627}
2628
2629/*
2630 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2631 * a 8192x4096@32bpp framebuffer:
2632 * 3 * 4096 * 8192 * 4 < 2^32
2633 */
2634static unsigned int
2635skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2636 const struct skl_pipe_wm_parameters *params)
2637{
2638 unsigned int total_data_rate = 0;
2639 int plane;
2640
2641 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2642 const struct intel_plane_wm_parameters *p;
2643
2644 p = &params->plane[plane];
2645 if (!p->enabled)
2646 continue;
2647
2648 total_data_rate += skl_plane_relative_data_rate(p);
2649 }
2650
2651 return total_data_rate;
2652}
2653
2654static void
2655skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2656 const struct intel_wm_config *config,
2657 const struct skl_pipe_wm_parameters *params,
2658 struct skl_ddb_allocation *ddb /* out */)
2659{
2660 struct drm_device *dev = crtc->dev;
dd740780 2661 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2663 enum pipe pipe = intel_crtc->pipe;
34bb56af 2664 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2665 uint16_t alloc_size, start, cursor_blocks;
80958155 2666 uint16_t minimum[I915_MAX_PLANES];
b9cec075
DL		 2667 unsigned int total_data_rate;
2668 int plane;
2669
34bb56af
DL		 2670 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2671 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2672 if (alloc_size == 0) {
2673 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2674 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2675 return;
2676 }
2677
2678 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2679 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2680 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2681
2682 alloc_size -= cursor_blocks;
34bb56af 2683 alloc->end -= cursor_blocks;
b9cec075 2684
80958155 2685 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2686 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2687 const struct intel_plane_wm_parameters *p;
2688
2689 p = &params->plane[plane];
2690 if (!p->enabled)
2691 continue;
2692
2693 minimum[plane] = 8;
2694 alloc_size -= minimum[plane];
2695 }
2696
b9cec075 2697 /*
80958155
DL		 2698 * 2. Distribute the remaining space in proportion to the amount of
2699 * data each plane needs to fetch from memory.
b9cec075
DL		 2700 *
2701 * FIXME: we may not allocate every single block here.
2702 */
2703 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2704
34bb56af 2705 start = alloc->start;
b9cec075
DL		 2706 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2707 const struct intel_plane_wm_parameters *p;
2708 unsigned int data_rate;
2709 uint16_t plane_blocks;
2710
2711 p = &params->plane[plane];
2712 if (!p->enabled)
2713 continue;
2714
2715 data_rate = skl_plane_relative_data_rate(p);
2716
2717 /*
2718 * promote the expression to 64 bits to avoid overflowing, the
2719 * result is < available as data_rate / total_data_rate < 1
2720 */
80958155
DL		 2721 plane_blocks = minimum[plane];
2722 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2723 total_data_rate);
b9cec075
DL		 2724
2725 ddb->plane[pipe][plane].start = start;
16160e3d 2726 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 2727
2728 start += plane_blocks;
2729 }
2730
2731}
2732
5cec258b 2733static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 2734{
2735 /* TODO: Take into account the scalers once we support them */
2d112de7 2736 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 2737}
2738
2739/*
2740 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2741 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2742 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2743 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2744*/
2745static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2746 uint32_t latency)
2747{
2748 uint32_t wm_intermediate_val, ret;
2749
2750 if (latency == 0)
2751 return UINT_MAX;
2752
d4c2aa60 2753 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 2754 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2755
2756 return ret;
2757}
2758
2759static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2760 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 2761 uint64_t tiling, uint32_t latency)
2d41c0b5 2762{
d4c2aa60
TU		 2763 uint32_t ret;
2764 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2765 uint32_t wm_intermediate_val;
2d41c0b5
PB		 2766
2767 if (latency == 0)
2768 return UINT_MAX;
2769
2770 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 2771
2772 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2773 tiling == I915_FORMAT_MOD_Yf_TILED) {
2774 plane_bytes_per_line *= 4;
2775 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2776 plane_blocks_per_line /= 4;
2777 } else {
2778 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2779 }
2780
2d41c0b5
PB		 2781 wm_intermediate_val = latency * pixel_rate;
2782 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 2783 plane_blocks_per_line;
2d41c0b5
PB		 2784
2785 return ret;
2786}
2787
2d41c0b5
PB		 2788static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2789 const struct intel_crtc *intel_crtc)
2790{
2791 struct drm_device *dev = intel_crtc->base.dev;
2792 struct drm_i915_private *dev_priv = dev->dev_private;
2793 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2794 enum pipe pipe = intel_crtc->pipe;
2795
2796 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2797 sizeof(new_ddb->plane[pipe])))
2798 return true;
2799
2800 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2801 sizeof(new_ddb->cursor[pipe])))
2802 return true;
2803
2804 return false;
2805}
2806
2807static void skl_compute_wm_global_parameters(struct drm_device *dev,
2808 struct intel_wm_config *config)
2809{
2810 struct drm_crtc *crtc;
2811 struct drm_plane *plane;
2812
2813 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 2814 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 2815
2816 /* FIXME: I don't think we need those two global parameters on SKL */
2817 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2818 struct intel_plane *intel_plane = to_intel_plane(plane);
2819
2820 config->sprites_enabled |= intel_plane->wm.enabled;
2821 config->sprites_scaled |= intel_plane->wm.scaled;
2822 }
2823}
2824
2825static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2826 struct skl_pipe_wm_parameters *p)
2827{
2828 struct drm_device *dev = crtc->dev;
2829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2830 enum pipe pipe = intel_crtc->pipe;
2831 struct drm_plane *plane;
0fda6568 2832 struct drm_framebuffer *fb;
2d41c0b5
PB		 2833 int i = 1; /* Index for sprite planes start */
2834
3ef00284 2835 p->active = intel_crtc->active;
2d41c0b5 2836 if (p->active) {
6e3c9717
ACO		 2837 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2838 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 2839
0fda6568 2840 fb = crtc->primary->state->fb;
c9f038a1
MR		 2841 if (fb) {
2842 p->plane[0].enabled = true;
2843 p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8;
0fda6568 2844 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 2845 } else {
2846 p->plane[0].enabled = false;
2847 p->plane[0].bytes_per_pixel = 0;
2848 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2849 }
2850 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2851 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 2852 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 2853
c9f038a1
MR		 2854 fb = crtc->cursor->state->fb;
2855 if (fb) {
2856 p->cursor.enabled = true;
2857 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2858 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2859 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2860 } else {
2861 p->cursor.enabled = false;
2862 p->cursor.bytes_per_pixel = 0;
2863 p->cursor.horiz_pixels = 64;
2864 p->cursor.vert_pixels = 64;
2865 }
2d41c0b5
PB		 2866 }
2867
2868 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2869 struct intel_plane *intel_plane = to_intel_plane(plane);
2870
a712f8eb
SJ		 2871 if (intel_plane->pipe == pipe &&
2872 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 2873 p->plane[i++] = intel_plane->wm;
2874 }
2875}
2876
d4c2aa60
TU		 2877static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2878 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 2879 struct intel_plane_wm_parameters *p_params,
2880 uint16_t ddb_allocation,
d4c2aa60 2881 int level,
afb024aa
DL		 2882 uint16_t *out_blocks, /* out */
2883 uint8_t *out_lines /* out */)
2d41c0b5 2884{
d4c2aa60
TU		 2885 uint32_t latency = dev_priv->wm.skl_latency[level];
2886 uint32_t method1, method2;
2887 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2888 uint32_t res_blocks, res_lines;
2889 uint32_t selected_result;
2d41c0b5 2890
d4c2aa60 2891 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 2892 return false;
2893
2894 method1 = skl_wm_method1(p->pixel_rate,
2895 p_params->bytes_per_pixel,
d4c2aa60 2896 latency);
2d41c0b5
PB		 2897 method2 = skl_wm_method2(p->pixel_rate,
2898 p->pipe_htotal,
2899 p_params->horiz_pixels,
2900 p_params->bytes_per_pixel,
0fda6568 2901 p_params->tiling,
d4c2aa60 2902 latency);
2d41c0b5
PB		 2903
2904 plane_bytes_per_line = p_params->horiz_pixels *
2905 p_params->bytes_per_pixel;
d4c2aa60 2906 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 2907
0fda6568
TU		 2908 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2909 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 2910 uint32_t min_scanlines = 4;
2911 uint32_t y_tile_minimum;
2912 if (intel_rotation_90_or_270(p_params->rotation)) {
2913 switch (p_params->bytes_per_pixel) {
2914 case 1:
2915 min_scanlines = 16;
2916 break;
2917 case 2:
2918 min_scanlines = 8;
2919 break;
2920 case 8:
2921 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 2922 }
1fc0a8f7
TU		 2923 }
2924 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 2925 selected_result = max(method2, y_tile_minimum);
2926 } else {
2927 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2928 selected_result = min(method1, method2);
2929 else
2930 selected_result = method1;
2931 }
2d41c0b5 2932
d4c2aa60
TU		 2933 res_blocks = selected_result + 1;
2934 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 2935
0fda6568
TU		 2936 if (level >= 1 && level <= 7) {
2937 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2938 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2939 res_lines += 4;
2940 else
2941 res_blocks++;
2942 }
e6d66171 2943
d4c2aa60 2944 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 2945 return false;
2946
2947 *out_blocks = res_blocks;
2948 *out_lines = res_lines;
2d41c0b5
PB		 2949
2950 return true;
2951}
2952
2953static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2954 struct skl_ddb_allocation *ddb,
2955 struct skl_pipe_wm_parameters *p,
2956 enum pipe pipe,
2957 int level,
2958 int num_planes,
2959 struct skl_wm_level *result)
2960{
2d41c0b5
PB		 2961 uint16_t ddb_blocks;
2962 int i;
2963
2964 for (i = 0; i < num_planes; i++) {
2965 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2966
d4c2aa60
TU		 2967 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
2968 p, &p->plane[i],
2d41c0b5 2969 ddb_blocks,
d4c2aa60 2970 level,
2d41c0b5
PB		 2971 &result->plane_res_b[i],
2972 &result->plane_res_l[i]);
2973 }
2974
2975 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 2976 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
2977 ddb_blocks, level,
2978 &result->cursor_res_b,
2d41c0b5
PB		 2979 &result->cursor_res_l);
2980}
2981
407b50f3
DL		 2982static uint32_t
2983skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2984{
3ef00284 2985 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 2986 return 0;
2987
2988 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2989
2990}
2991
2992static void skl_compute_transition_wm(struct drm_crtc *crtc,
2993 struct skl_pipe_wm_parameters *params,
9414f563 2994 struct skl_wm_level *trans_wm /* out */)
407b50f3 2995{
9414f563
DL		 2996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2997 int i;
2998
407b50f3
DL		 2999 if (!params->active)
3000 return;
9414f563
DL		 3001
3002 /* Until we know more, just disable transition WMs */
3003 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3004 trans_wm->plane_en[i] = false;
3005 trans_wm->cursor_en = false;
407b50f3
DL		 3006}
3007
2d41c0b5
PB		 3008static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3009 struct skl_ddb_allocation *ddb,
3010 struct skl_pipe_wm_parameters *params,
3011 struct skl_pipe_wm *pipe_wm)
3012{
3013 struct drm_device *dev = crtc->dev;
3014 const struct drm_i915_private *dev_priv = dev->dev_private;
3015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3016 int level, max_level = ilk_wm_max_level(dev);
3017
3018 for (level = 0; level <= max_level; level++) {
3019 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3020 level, intel_num_planes(intel_crtc),
3021 &pipe_wm->wm[level]);
3022 }
3023 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3024
9414f563 3025 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3026}
3027
3028static void skl_compute_wm_results(struct drm_device *dev,
3029 struct skl_pipe_wm_parameters *p,
3030 struct skl_pipe_wm *p_wm,
3031 struct skl_wm_values *r,
3032 struct intel_crtc *intel_crtc)
3033{
3034 int level, max_level = ilk_wm_max_level(dev);
3035 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3036 uint32_t temp;
3037 int i;
2d41c0b5
PB		 3038
3039 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3040 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3041 temp = 0;
2d41c0b5
PB		 3042
3043 temp |= p_wm->wm[level].plane_res_l[i] <<
3044 PLANE_WM_LINES_SHIFT;
3045 temp |= p_wm->wm[level].plane_res_b[i];
3046 if (p_wm->wm[level].plane_en[i])
3047 temp |= PLANE_WM_EN;
3048
3049 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3050 }
3051
3052 temp = 0;
2d41c0b5
PB		 3053
3054 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3055 temp |= p_wm->wm[level].cursor_res_b;
3056
3057 if (p_wm->wm[level].cursor_en)
3058 temp |= PLANE_WM_EN;
3059
3060 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3061
3062 }
3063
9414f563
DL		 3064 /* transition WMs */
3065 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3066 temp = 0;
3067 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3068 temp |= p_wm->trans_wm.plane_res_b[i];
3069 if (p_wm->trans_wm.plane_en[i])
3070 temp |= PLANE_WM_EN;
3071
3072 r->plane_trans[pipe][i] = temp;
3073 }
3074
3075 temp = 0;
3076 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3077 temp |= p_wm->trans_wm.cursor_res_b;
3078 if (p_wm->trans_wm.cursor_en)
3079 temp |= PLANE_WM_EN;
3080
3081 r->cursor_trans[pipe] = temp;
3082
2d41c0b5
PB		 3083 r->wm_linetime[pipe] = p_wm->linetime;
3084}
3085
16160e3d
DL		 3086static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3087 const struct skl_ddb_entry *entry)
3088{
3089 if (entry->end)
3090 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3091 else
3092 I915_WRITE(reg, 0);
3093}
3094
2d41c0b5
PB		 3095static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3096 const struct skl_wm_values *new)
3097{
3098 struct drm_device *dev = dev_priv->dev;
3099 struct intel_crtc *crtc;
3100
3101 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3102 int i, level, max_level = ilk_wm_max_level(dev);
3103 enum pipe pipe = crtc->pipe;
3104
5d374d96
DL		 3105 if (!new->dirty[pipe])
3106 continue;
8211bd5b 3107
5d374d96 3108 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3109
5d374d96
DL		 3110 for (level = 0; level <= max_level; level++) {
3111 for (i = 0; i < intel_num_planes(crtc); i++)
3112 I915_WRITE(PLANE_WM(pipe, i, level),
3113 new->plane[pipe][i][level]);
3114 I915_WRITE(CUR_WM(pipe, level),
3115 new->cursor[pipe][level]);
2d41c0b5 3116 }
5d374d96
DL		 3117 for (i = 0; i < intel_num_planes(crtc); i++)
3118 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3119 new->plane_trans[pipe][i]);
3120 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3121
3122 for (i = 0; i < intel_num_planes(crtc); i++)
3123 skl_ddb_entry_write(dev_priv,
3124 PLANE_BUF_CFG(pipe, i),
3125 &new->ddb.plane[pipe][i]);
3126
3127 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3128 &new->ddb.cursor[pipe]);
2d41c0b5 3129 }
2d41c0b5
PB		 3130}
3131
0e8fb7ba
DL		 3132/*
3133 * When setting up a new DDB allocation arrangement, we need to correctly
3134 * sequence the times at which the new allocations for the pipes are taken into
3135 * account or we'll have pipes fetching from space previously allocated to
3136 * another pipe.
3137 *
3138 * Roughly the sequence looks like:
3139 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3140 * overlapping with a previous light-up pipe (another way to put it is:
3141 * pipes with their new allocation strickly included into their old ones).
3142 * 2. re-allocate the other pipes that get their allocation reduced
3143 * 3. allocate the pipes having their allocation increased
3144 *
3145 * Steps 1. and 2. are here to take care of the following case:
3146 * - Initially DDB looks like this:
3147 * | B | C |
3148 * - enable pipe A.
3149 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3150 * allocation
3151 * | A | B | C |
3152 *
3153 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3154 */
3155
d21b795c
DL		 3156static void
3157skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3158{
0e8fb7ba
DL		 3159 int plane;
3160
d21b795c
DL		 3161 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3162
dd740780 3163 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3164 I915_WRITE(PLANE_SURF(pipe, plane),
3165 I915_READ(PLANE_SURF(pipe, plane)));
3166 }
3167 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3168}
3169
3170static bool
3171skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3172 const struct skl_ddb_allocation *new,
3173 enum pipe pipe)
3174{
3175 uint16_t old_size, new_size;
3176
3177 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3178 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3179
3180 return old_size != new_size &&
3181 new->pipe[pipe].start >= old->pipe[pipe].start &&
3182 new->pipe[pipe].end <= old->pipe[pipe].end;
3183}
3184
3185static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3186 struct skl_wm_values *new_values)
3187{
3188 struct drm_device *dev = dev_priv->dev;
3189 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3190 bool reallocated[I915_MAX_PIPES] = {false, false, false};
3191 struct intel_crtc *crtc;
3192 enum pipe pipe;
3193
3194 new_ddb = &new_values->ddb;
3195 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3196
3197 /*
3198 * First pass: flush the pipes with the new allocation contained into
3199 * the old space.
3200 *
3201 * We'll wait for the vblank on those pipes to ensure we can safely
3202 * re-allocate the freed space without this pipe fetching from it.
3203 */
3204 for_each_intel_crtc(dev, crtc) {
3205 if (!crtc->active)
3206 continue;
3207
3208 pipe = crtc->pipe;
3209
3210 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3211 continue;
3212
d21b795c 3213 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3214 intel_wait_for_vblank(dev, pipe);
3215
3216 reallocated[pipe] = true;
3217 }
3218
3219
3220 /*
3221 * Second pass: flush the pipes that are having their allocation
3222 * reduced, but overlapping with a previous allocation.
3223 *
3224 * Here as well we need to wait for the vblank to make sure the freed
3225 * space is not used anymore.
3226 */
3227 for_each_intel_crtc(dev, crtc) {
3228 if (!crtc->active)
3229 continue;
3230
3231 pipe = crtc->pipe;
3232
3233 if (reallocated[pipe])
3234 continue;
3235
3236 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3237 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3238 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3239 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3240 reallocated[pipe] = true;
0e8fb7ba 3241 }
0e8fb7ba
DL		 3242 }
3243
3244 /*
3245 * Third pass: flush the pipes that got more space allocated.
3246 *
3247 * We don't need to actively wait for the update here, next vblank
3248 * will just get more DDB space with the correct WM values.
3249 */
3250 for_each_intel_crtc(dev, crtc) {
3251 if (!crtc->active)
3252 continue;
3253
3254 pipe = crtc->pipe;
3255
3256 /*
3257 * At this point, only the pipes more space than before are
3258 * left to re-allocate.
3259 */
3260 if (reallocated[pipe])
3261 continue;
3262
d21b795c 3263 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3264 }
3265}
3266
2d41c0b5
PB		 3267static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3268 struct skl_pipe_wm_parameters *params,
3269 struct intel_wm_config *config,
3270 struct skl_ddb_allocation *ddb, /* out */
3271 struct skl_pipe_wm *pipe_wm /* out */)
3272{
3273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3274
3275 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3276 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3277 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3278
3279 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3280 return false;
3281
3282 intel_crtc->wm.skl_active = *pipe_wm;
3283 return true;
3284}
3285
3286static void skl_update_other_pipe_wm(struct drm_device *dev,
3287 struct drm_crtc *crtc,
3288 struct intel_wm_config *config,
3289 struct skl_wm_values *r)
3290{
3291 struct intel_crtc *intel_crtc;
3292 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3293
3294 /*
3295 * If the WM update hasn't changed the allocation for this_crtc (the
3296 * crtc we are currently computing the new WM values for), other
3297 * enabled crtcs will keep the same allocation and we don't need to
3298 * recompute anything for them.
3299 */
3300 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3301 return;
3302
3303 /*
3304 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3305 * other active pipes need new DDB allocation and WM values.
3306 */
3307 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3308 base.head) {
3309 struct skl_pipe_wm_parameters params = {};
3310 struct skl_pipe_wm pipe_wm = {};
3311 bool wm_changed;
3312
3313 if (this_crtc->pipe == intel_crtc->pipe)
3314 continue;
3315
3316 if (!intel_crtc->active)
3317 continue;
3318
3319 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3320 &params, config,
3321 &r->ddb, &pipe_wm);
3322
3323 /*
3324 * If we end up re-computing the other pipe WM values, it's
3325 * because it was really needed, so we expect the WM values to
3326 * be different.
3327 */
3328 WARN_ON(!wm_changed);
3329
3330 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3331 r->dirty[intel_crtc->pipe] = true;
3332 }
3333}
3334
3335static void skl_update_wm(struct drm_crtc *crtc)
3336{
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct skl_pipe_wm_parameters params = {};
3341 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3342 struct skl_pipe_wm pipe_wm = {};
3343 struct intel_wm_config config = {};
3344
3345 memset(results, 0, sizeof(*results));
3346
3347 skl_compute_wm_global_parameters(dev, &config);
3348
3349 if (!skl_update_pipe_wm(crtc, &params, &config,
3350 &results->ddb, &pipe_wm))
3351 return;
3352
3353 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3354 results->dirty[intel_crtc->pipe] = true;
3355
3356 skl_update_other_pipe_wm(dev, crtc, &config, results);
3357 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3358 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3359
3360 /* store the new configuration */
3361 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3362}
3363
3364static void
3365skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3366 uint32_t sprite_width, uint32_t sprite_height,
3367 int pixel_size, bool enabled, bool scaled)
3368{
3369 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3370 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3371
3372 intel_plane->wm.enabled = enabled;
3373 intel_plane->wm.scaled = scaled;
3374 intel_plane->wm.horiz_pixels = sprite_width;
3375 intel_plane->wm.vert_pixels = sprite_height;
3376 intel_plane->wm.bytes_per_pixel = pixel_size;
0fda6568
TU		 3377 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3378 /*
3379 * Framebuffer can be NULL on plane disable, but it does not
3380 * matter for watermarks if we assume no tiling in that case.
3381 */
3382 if (fb)
3383 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3384 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3385
3386 skl_update_wm(crtc);
3387}
3388
820c1980 3389static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3390{
7c4a395f 3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3392 struct drm_device *dev = crtc->dev;
801bcfff 3393 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3394 struct ilk_wm_maximums max;
3395 struct ilk_pipe_wm_parameters params = {};
3396 struct ilk_wm_values results = {};
77c122bc 3397 enum intel_ddb_partitioning partitioning;
7c4a395f 3398 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3399 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3400 struct intel_wm_config config = {};
7c4a395f 3401
2a44b76b 3402 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3403
3404 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3405
3406 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3407 return;
861f3389 3408
7c4a395f 3409 intel_crtc->wm.active = pipe_wm;
861f3389 3410
2a44b76b
VS		 3411 ilk_compute_wm_config(dev, &config);
3412
34982fe1 3413 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3414 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3415
3416 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3417 if (INTEL_INFO(dev)->gen >= 7 &&
3418 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3419 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3420 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3421
820c1980 3422 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3423 } else {
198a1e9b 3424 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3425 }
3426
198a1e9b 3427 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3428 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3429
820c1980 3430 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3431
820c1980 3432 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3433}
3434
ed57cb8a
DL		 3435static void
3436ilk_update_sprite_wm(struct drm_plane *plane,
3437 struct drm_crtc *crtc,
3438 uint32_t sprite_width, uint32_t sprite_height,
3439 int pixel_size, bool enabled, bool scaled)
526682e9 3440{
8553c18e 3441 struct drm_device *dev = plane->dev;
adf3d35e 3442 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3443
adf3d35e
VS		 3444 intel_plane->wm.enabled = enabled;
3445 intel_plane->wm.scaled = scaled;
3446 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3447 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3448 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3449
8553c18e
VS		 3450 /*
3451 * IVB workaround: must disable low power watermarks for at least
3452 * one frame before enabling scaling. LP watermarks can be re-enabled
3453 * when scaling is disabled.
3454 *
3455 * WaCxSRDisabledForSpriteScaling:ivb
3456 */
3457 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3458 intel_wait_for_vblank(dev, intel_plane->pipe);
3459
820c1980 3460 ilk_update_wm(crtc);
526682e9
PZ		 3461}
3462
3078999f
PB		 3463static void skl_pipe_wm_active_state(uint32_t val,
3464 struct skl_pipe_wm *active,
3465 bool is_transwm,
3466 bool is_cursor,
3467 int i,
3468 int level)
3469{
3470 bool is_enabled = (val & PLANE_WM_EN) != 0;
3471
3472 if (!is_transwm) {
3473 if (!is_cursor) {
3474 active->wm[level].plane_en[i] = is_enabled;
3475 active->wm[level].plane_res_b[i] =
3476 val & PLANE_WM_BLOCKS_MASK;
3477 active->wm[level].plane_res_l[i] =
3478 (val >> PLANE_WM_LINES_SHIFT) &
3479 PLANE_WM_LINES_MASK;
3480 } else {
3481 active->wm[level].cursor_en = is_enabled;
3482 active->wm[level].cursor_res_b =
3483 val & PLANE_WM_BLOCKS_MASK;
3484 active->wm[level].cursor_res_l =
3485 (val >> PLANE_WM_LINES_SHIFT) &
3486 PLANE_WM_LINES_MASK;
3487 }
3488 } else {
3489 if (!is_cursor) {
3490 active->trans_wm.plane_en[i] = is_enabled;
3491 active->trans_wm.plane_res_b[i] =
3492 val & PLANE_WM_BLOCKS_MASK;
3493 active->trans_wm.plane_res_l[i] =
3494 (val >> PLANE_WM_LINES_SHIFT) &
3495 PLANE_WM_LINES_MASK;
3496 } else {
3497 active->trans_wm.cursor_en = is_enabled;
3498 active->trans_wm.cursor_res_b =
3499 val & PLANE_WM_BLOCKS_MASK;
3500 active->trans_wm.cursor_res_l =
3501 (val >> PLANE_WM_LINES_SHIFT) &
3502 PLANE_WM_LINES_MASK;
3503 }
3504 }
3505}
3506
3507static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3508{
3509 struct drm_device *dev = crtc->dev;
3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3514 enum pipe pipe = intel_crtc->pipe;
3515 int level, i, max_level;
3516 uint32_t temp;
3517
3518 max_level = ilk_wm_max_level(dev);
3519
3520 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3521
3522 for (level = 0; level <= max_level; level++) {
3523 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3524 hw->plane[pipe][i][level] =
3525 I915_READ(PLANE_WM(pipe, i, level));
3526 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3527 }
3528
3529 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3530 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3531 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3532
3ef00284 3533 if (!intel_crtc->active)
3078999f
PB		 3534 return;
3535
3536 hw->dirty[pipe] = true;
3537
3538 active->linetime = hw->wm_linetime[pipe];
3539
3540 for (level = 0; level <= max_level; level++) {
3541 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3542 temp = hw->plane[pipe][i][level];
3543 skl_pipe_wm_active_state(temp, active, false,
3544 false, i, level);
3545 }
3546 temp = hw->cursor[pipe][level];
3547 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3548 }
3549
3550 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3551 temp = hw->plane_trans[pipe][i];
3552 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3553 }
3554
3555 temp = hw->cursor_trans[pipe];
3556 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3557}
3558
3559void skl_wm_get_hw_state(struct drm_device *dev)
3560{
a269c583
DL		 3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3563 struct drm_crtc *crtc;
3564
a269c583 3565 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3566 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3567 skl_pipe_wm_get_hw_state(crtc);
3568}
3569
243e6a44
VS		 3570static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3571{
3572 struct drm_device *dev = crtc->dev;
3573 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3574 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3576 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3577 enum pipe pipe = intel_crtc->pipe;
3578 static const unsigned int wm0_pipe_reg[] = {
3579 [PIPE_A] = WM0_PIPEA_ILK,
3580 [PIPE_B] = WM0_PIPEB_ILK,
3581 [PIPE_C] = WM0_PIPEC_IVB,
3582 };
3583
3584 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3585 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3586 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3587
3ef00284 3588 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3589
3590 if (active->pipe_enabled) {
243e6a44
VS		 3591 u32 tmp = hw->wm_pipe[pipe];
3592
3593 /*
3594 * For active pipes LP0 watermark is marked as
3595 * enabled, and LP1+ watermaks as disabled since
3596 * we can't really reverse compute them in case
3597 * multiple pipes are active.
3598 */
3599 active->wm[0].enable = true;
3600 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3601 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3602 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3603 active->linetime = hw->wm_linetime[pipe];
3604 } else {
3605 int level, max_level = ilk_wm_max_level(dev);
3606
3607 /*
3608 * For inactive pipes, all watermark levels
3609 * should be marked as enabled but zeroed,
3610 * which is what we'd compute them to.
3611 */
3612 for (level = 0; level <= max_level; level++)
3613 active->wm[level].enable = true;
3614 }
3615}
3616
3617void ilk_wm_get_hw_state(struct drm_device *dev)
3618{
3619 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3620 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3621 struct drm_crtc *crtc;
3622
70e1e0ec 3623 for_each_crtc(dev, crtc)
243e6a44
VS		 3624 ilk_pipe_wm_get_hw_state(crtc);
3625
3626 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3627 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3628 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3629
3630 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3631 if (INTEL_INFO(dev)->gen >= 7) {
3632 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3633 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3634 }
243e6a44 3635
a42a5719 3636 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3637 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3638 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3639 else if (IS_IVYBRIDGE(dev))
3640 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3641 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3642
3643 hw->enable_fbc_wm =
3644 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3645}
3646
b445e3b0
ED		 3647/**
3648 * intel_update_watermarks - update FIFO watermark values based on current modes
3649 *
3650 * Calculate watermark values for the various WM regs based on current mode
3651 * and plane configuration.
3652 *
3653 * There are several cases to deal with here:
3654 * - normal (i.e. non-self-refresh)
3655 * - self-refresh (SR) mode
3656 * - lines are large relative to FIFO size (buffer can hold up to 2)
3657 * - lines are small relative to FIFO size (buffer can hold more than 2
3658 * lines), so need to account for TLB latency
3659 *
3660 * The normal calculation is:
3661 * watermark = dotclock * bytes per pixel * latency
3662 * where latency is platform & configuration dependent (we assume pessimal
3663 * values here).
3664 *
3665 * The SR calculation is:
3666 * watermark = (trunc(latency/line time)+1) * surface width *
3667 * bytes per pixel
3668 * where
3669 * line time = htotal / dotclock
3670 * surface width = hdisplay for normal plane and 64 for cursor
3671 * and latency is assumed to be high, as above.
3672 *
3673 * The final value programmed to the register should always be rounded up,
3674 * and include an extra 2 entries to account for clock crossings.
3675 *
3676 * We don't use the sprite, so we can ignore that. And on Crestline we have
3677 * to set the non-SR watermarks to 8.
3678 */
46ba614c 3679void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3680{
46ba614c 3681 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3682
3683 if (dev_priv->display.update_wm)
46ba614c 3684 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3685}
3686
adf3d35e
VS		 3687void intel_update_sprite_watermarks(struct drm_plane *plane,
3688 struct drm_crtc *crtc,
ed57cb8a
DL		 3689 uint32_t sprite_width,
3690 uint32_t sprite_height,
3691 int pixel_size,
39db4a4d 3692 bool enabled, bool scaled)
b445e3b0 3693{
adf3d35e 3694 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3695
3696 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3697 dev_priv->display.update_sprite_wm(plane, crtc,
3698 sprite_width, sprite_height,
39db4a4d 3699 pixel_size, enabled, scaled);
b445e3b0
ED		 3700}
3701
9270388e
DV		 3702/**
3703 * Lock protecting IPS related data structures
9270388e
DV		 3704 */
3705DEFINE_SPINLOCK(mchdev_lock);
3706
3707/* Global for IPS driver to get at the current i915 device. Protected by
3708 * mchdev_lock. */
3709static struct drm_i915_private *i915_mch_dev;
3710
2b4e57bd
ED		 3711bool ironlake_set_drps(struct drm_device *dev, u8 val)
3712{
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3714 u16 rgvswctl;
3715
9270388e
DV		 3716 assert_spin_locked(&mchdev_lock);
3717
2b4e57bd
ED		 3718 rgvswctl = I915_READ16(MEMSWCTL);
3719 if (rgvswctl & MEMCTL_CMD_STS) {
3720 DRM_DEBUG("gpu busy, RCS change rejected\n");
3721 return false; /* still busy with another command */
3722 }
3723
3724 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3725 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3726 I915_WRITE16(MEMSWCTL, rgvswctl);
3727 POSTING_READ16(MEMSWCTL);
3728
3729 rgvswctl |= MEMCTL_CMD_STS;
3730 I915_WRITE16(MEMSWCTL, rgvswctl);
3731
3732 return true;
3733}
3734
8090c6b9 3735static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3736{
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 u32 rgvmodectl = I915_READ(MEMMODECTL);
3739 u8 fmax, fmin, fstart, vstart;
3740
9270388e
DV		 3741 spin_lock_irq(&mchdev_lock);
3742
2b4e57bd
ED		 3743 /* Enable temp reporting */
3744 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3745 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3746
3747 /* 100ms RC evaluation intervals */
3748 I915_WRITE(RCUPEI, 100000);
3749 I915_WRITE(RCDNEI, 100000);
3750
3751 /* Set max/min thresholds to 90ms and 80ms respectively */
3752 I915_WRITE(RCBMAXAVG, 90000);
3753 I915_WRITE(RCBMINAVG, 80000);
3754
3755 I915_WRITE(MEMIHYST, 1);
3756
3757 /* Set up min, max, and cur for interrupt handling */
3758 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3759 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3760 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3761 MEMMODE_FSTART_SHIFT;
3762
3763 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3764 PXVFREQ_PX_SHIFT;
3765
20e4d407
DV		 3766 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3767 dev_priv->ips.fstart = fstart;
2b4e57bd 3768
20e4d407
DV		 3769 dev_priv->ips.max_delay = fstart;
3770 dev_priv->ips.min_delay = fmin;
3771 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3772
3773 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3774 fmax, fmin, fstart);
3775
3776 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3777
3778 /*
3779 * Interrupts will be enabled in ironlake_irq_postinstall
3780 */
3781
3782 I915_WRITE(VIDSTART, vstart);
3783 POSTING_READ(VIDSTART);
3784
3785 rgvmodectl |= MEMMODE_SWMODE_EN;
3786 I915_WRITE(MEMMODECTL, rgvmodectl);
3787
9270388e 3788 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3789 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3790 mdelay(1);
2b4e57bd
ED		 3791
3792 ironlake_set_drps(dev, fstart);
3793
20e4d407 3794 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3795 I915_READ(0x112e0);
20e4d407
DV		 3796 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3797 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3798 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3799
3800 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3801}
3802
8090c6b9 3803static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3804{
3805 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3806 u16 rgvswctl;
3807
3808 spin_lock_irq(&mchdev_lock);
3809
3810 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3811
3812 /* Ack interrupts, disable EFC interrupt */
3813 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3814 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3815 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3816 I915_WRITE(DEIIR, DE_PCU_EVENT);
3817 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3818
3819 /* Go back to the starting frequency */
20e4d407 3820 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3821 mdelay(1);
2b4e57bd
ED		 3822 rgvswctl |= MEMCTL_CMD_STS;
3823 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3824 mdelay(1);
2b4e57bd 3825
9270388e 3826 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3827}
3828
acbe9475
DV		 3829/* There's a funny hw issue where the hw returns all 0 when reading from
3830 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3831 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3832 * all limits and the gpu stuck at whatever frequency it is at atm).
3833 */
74ef1173 3834static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3835{
7b9e0ae6 3836 u32 limits;
2b4e57bd 3837
20b46e59
DV		 3838 /* Only set the down limit when we've reached the lowest level to avoid
3839 * getting more interrupts, otherwise leave this clear. This prevents a
3840 * race in the hw when coming out of rc6: There's a tiny window where
3841 * the hw runs at the minimal clock before selecting the desired
3842 * frequency, if the down threshold expires in that window we will not
3843 * receive a down interrupt. */
74ef1173
AG		 3844 if (IS_GEN9(dev_priv->dev)) {
3845 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3846 if (val <= dev_priv->rps.min_freq_softlimit)
3847 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3848 } else {
3849 limits = dev_priv->rps.max_freq_softlimit << 24;
3850 if (val <= dev_priv->rps.min_freq_softlimit)
3851 limits |= dev_priv->rps.min_freq_softlimit << 16;
3852 }
20b46e59
DV		 3853
3854 return limits;
3855}
3856
dd75fdc8
CW		 3857static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3858{
3859 int new_power;
8a586437
AG		 3860 u32 threshold_up = 0, threshold_down = 0; /* in % */
3861 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 3862
3863 new_power = dev_priv->rps.power;
3864 switch (dev_priv->rps.power) {
3865 case LOW_POWER:
b39fb297 3866 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3867 new_power = BETWEEN;
3868 break;
3869
3870 case BETWEEN:
b39fb297 3871 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3872 new_power = LOW_POWER;
b39fb297 3873 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3874 new_power = HIGH_POWER;
3875 break;
3876
3877 case HIGH_POWER:
b39fb297 3878 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3879 new_power = BETWEEN;
3880 break;
3881 }
3882 /* Max/min bins are special */
aed242ff 3883 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 3884 new_power = LOW_POWER;
aed242ff 3885 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3886 new_power = HIGH_POWER;
3887 if (new_power == dev_priv->rps.power)
3888 return;
3889
3890 /* Note the units here are not exactly 1us, but 1280ns. */
3891 switch (new_power) {
3892 case LOW_POWER:
3893 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 3894 ei_up = 16000;
3895 threshold_up = 95;
dd75fdc8
CW		 3896
3897 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 3898 ei_down = 32000;
3899 threshold_down = 85;
dd75fdc8
CW		 3900 break;
3901
3902 case BETWEEN:
3903 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 3904 ei_up = 13000;
3905 threshold_up = 90;
dd75fdc8
CW		 3906
3907 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 3908 ei_down = 32000;
3909 threshold_down = 75;
dd75fdc8
CW		 3910 break;
3911
3912 case HIGH_POWER:
3913 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 3914 ei_up = 10000;
3915 threshold_up = 85;
dd75fdc8
CW		 3916
3917 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 3918 ei_down = 32000;
3919 threshold_down = 60;
dd75fdc8
CW		 3920 break;
3921 }
3922
8a586437
AG		 3923 I915_WRITE(GEN6_RP_UP_EI,
3924 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3925 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3926 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3927
3928 I915_WRITE(GEN6_RP_DOWN_EI,
3929 GT_INTERVAL_FROM_US(dev_priv, ei_down));
3930 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3931 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
3932
3933 I915_WRITE(GEN6_RP_CONTROL,
3934 GEN6_RP_MEDIA_TURBO |
3935 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3936 GEN6_RP_MEDIA_IS_GFX |
3937 GEN6_RP_ENABLE |
3938 GEN6_RP_UP_BUSY_AVG |
3939 GEN6_RP_DOWN_IDLE_AVG);
3940
dd75fdc8
CW		 3941 dev_priv->rps.power = new_power;
3942 dev_priv->rps.last_adj = 0;
3943}
3944
2876ce73
CW		 3945static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3946{
3947 u32 mask = 0;
3948
3949 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 3950 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 3951 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 3952 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 3953
7b3c29f6
CW		 3954 mask &= dev_priv->pm_rps_events;
3955
59d02a1f 3956 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 3957}
3958
b8a5ff8d
JM		 3959/* gen6_set_rps is called to update the frequency request, but should also be
3960 * called when the range (min_delay and max_delay) is modified so that we can
3961 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 3962static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 3963{
3964 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3965
4fc688ce 3966 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 3967 WARN_ON(val > dev_priv->rps.max_freq);
3968 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 3969
eb64cad1
CW		 3970 /* min/max delay may still have been modified so be sure to
3971 * write the limits value.
3972 */
3973 if (val != dev_priv->rps.cur_freq) {
3974 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3975
5704195c
AG		 3976 if (IS_GEN9(dev))
3977 I915_WRITE(GEN6_RPNSWREQ,
3978 GEN9_FREQUENCY(val));
3979 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3980 I915_WRITE(GEN6_RPNSWREQ,
3981 HSW_FREQUENCY(val));
3982 else
3983 I915_WRITE(GEN6_RPNSWREQ,
3984 GEN6_FREQUENCY(val) |
3985 GEN6_OFFSET(0) |
3986 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3987 }
7b9e0ae6 3988
7b9e0ae6
CW		 3989 /* Make sure we continue to get interrupts
3990 * until we hit the minimum or maximum frequencies.
3991 */
74ef1173 3992 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 3993 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3994
d5570a72
BW		 3995 POSTING_READ(GEN6_RPNSWREQ);
3996
b39fb297 3997 dev_priv->rps.cur_freq = val;
be2cde9a 3998 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3999}
4000
ffe02b40
VS		 4001static void valleyview_set_rps(struct drm_device *dev, u8 val)
4002{
4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004
4005 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4006 WARN_ON(val > dev_priv->rps.max_freq);
4007 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4008
4009 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4010 "Odd GPU freq value\n"))
4011 val &= ~1;
4012
4013 if (val != dev_priv->rps.cur_freq)
4014 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4015
4016 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4017
4018 dev_priv->rps.cur_freq = val;
4019 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4020}
4021
76c3552f
D		 4022/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4023 *
4024 * * If Gfx is Idle, then
4025 * 1. Mask Turbo interrupts
4026 * 2. Bring up Gfx clock
4027 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4028 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4029 * 5. Unmask Turbo interrupts
4030*/
4031static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4032{
5549d25f 4033 struct drm_device *dev = dev_priv->dev;
aed242ff 4034 u32 val = dev_priv->rps.idle_freq;
5549d25f 4035
21a11fff
VS		 4036 /* CHV and latest VLV don't need to force the gfx clock */
4037 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
aed242ff 4038 valleyview_set_rps(dev_priv->dev, val);
5549d25f
D		 4039 return;
4040 }
4041
76c3552f
D		 4042 /*
4043 * When we are idle. Drop to min voltage state.
4044 */
4045
aed242ff 4046 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4047 return;
4048
4049 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID		 4050 I915_WRITE(GEN6_PMINTRMSK,
4051 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 4052
650ad970 4053 vlv_force_gfx_clock(dev_priv, true);
76c3552f 4054
aed242ff 4055 dev_priv->rps.cur_freq = val;
76c3552f 4056
aed242ff 4057 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
76c3552f
D		 4058
4059 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 4060 & GENFREQSTATUS) == 0, 100))
76c3552f
D		 4061 DRM_ERROR("timed out waiting for Punit\n");
4062
650ad970 4063 vlv_force_gfx_clock(dev_priv, false);
76c3552f 4064
aed242ff 4065 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
76c3552f
D		 4066}
4067
43cf3bf0
CW		 4068void gen6_rps_busy(struct drm_i915_private *dev_priv)
4069{
4070 mutex_lock(&dev_priv->rps.hw_lock);
4071 if (dev_priv->rps.enabled) {
4072 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4073 gen6_rps_reset_ei(dev_priv);
4074 I915_WRITE(GEN6_PMINTRMSK,
4075 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4076 }
4077 mutex_unlock(&dev_priv->rps.hw_lock);
4078}
4079
b29c19b6
CW		 4080void gen6_rps_idle(struct drm_i915_private *dev_priv)
4081{
691bb717
DL		 4082 struct drm_device *dev = dev_priv->dev;
4083
b29c19b6 4084 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4085 if (dev_priv->rps.enabled) {
21a11fff 4086 if (IS_VALLEYVIEW(dev))
76c3552f 4087 vlv_set_rps_idle(dev_priv);
7526ed79 4088 else
aed242ff 4089 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4090 dev_priv->rps.last_adj = 0;
43cf3bf0 4091 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4092 }
b29c19b6
CW		 4093 mutex_unlock(&dev_priv->rps.hw_lock);
4094}
4095
4096void gen6_rps_boost(struct drm_i915_private *dev_priv)
4097{
43cf3bf0
CW		 4098 u32 val;
4099
b29c19b6 4100 mutex_lock(&dev_priv->rps.hw_lock);
43cf3bf0
CW		 4101 val = dev_priv->rps.max_freq_softlimit;
4102 if (dev_priv->rps.enabled &&
4103 dev_priv->mm.busy &&
4104 dev_priv->rps.cur_freq < val) {
4105 intel_set_rps(dev_priv->dev, val);
c0951f0c
CW		 4106 dev_priv->rps.last_adj = 0;
4107 }
b29c19b6
CW		 4108 mutex_unlock(&dev_priv->rps.hw_lock);
4109}
4110
ffe02b40 4111void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4112{
ffe02b40
VS		 4113 if (IS_VALLEYVIEW(dev))
4114 valleyview_set_rps(dev, val);
4115 else
4116 gen6_set_rps(dev, val);
0a073b84
JB		 4117}
4118
20e49366
ZW		 4119static void gen9_disable_rps(struct drm_device *dev)
4120{
4121 struct drm_i915_private *dev_priv = dev->dev_private;
4122
4123 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4124 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4125}
4126
44fc7d5c 4127static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4128{
4129 struct drm_i915_private *dev_priv = dev->dev_private;
4130
4131 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4132 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4133}
4134
38807746
D		 4135static void cherryview_disable_rps(struct drm_device *dev)
4136{
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138
4139 I915_WRITE(GEN6_RC_CONTROL, 0);
4140}
4141
44fc7d5c
DV		 4142static void valleyview_disable_rps(struct drm_device *dev)
4143{
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145
98a2e5f9
D		 4146 /* we're doing forcewake before Disabling RC6,
4147 * This what the BIOS expects when going into suspend */
59bad947 4148 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4149
44fc7d5c 4150 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4151
59bad947 4152 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4153}
4154
dc39fff7
BW		 4155static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4156{
91ca689a
ID		 4157 if (IS_VALLEYVIEW(dev)) {
4158 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4159 mode = GEN6_RC_CTL_RC6_ENABLE;
4160 else
4161 mode = 0;
4162 }
58abf1da
RV		 4163 if (HAS_RC6p(dev))
4164 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4165 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4166 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4167 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4168
4169 else
4170 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4171 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4172}
4173
e6069ca8 4174static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4175{
eb4926e4
DL		 4176 /* No RC6 before Ironlake */
4177 if (INTEL_INFO(dev)->gen < 5)
4178 return 0;
4179
e6069ca8
ID		 4180 /* RC6 is only on Ironlake mobile not on desktop */
4181 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4182 return 0;
4183
456470eb 4184 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4185 if (enable_rc6 >= 0) {
4186 int mask;
4187
58abf1da 4188 if (HAS_RC6p(dev))
e6069ca8
ID		 4189 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4190 INTEL_RC6pp_ENABLE;
4191 else
4192 mask = INTEL_RC6_ENABLE;
4193
4194 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4195 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4196 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4197
4198 return enable_rc6 & mask;
4199 }
2b4e57bd 4200
6567d748
CW		 4201 /* Disable RC6 on Ironlake */
4202 if (INTEL_INFO(dev)->gen == 5)
4203 return 0;
2b4e57bd 4204
8bade1ad 4205 if (IS_IVYBRIDGE(dev))
cca84a1f 4206 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4207
4208 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4209}
4210
e6069ca8
ID		 4211int intel_enable_rc6(const struct drm_device *dev)
4212{
4213 return i915.enable_rc6;
4214}
4215
93ee2920 4216static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4217{
93ee2920
TR		 4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 uint32_t rp_state_cap;
4220 u32 ddcc_status = 0;
4221 int ret;
4222
4223 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW		 4224 /* All of these values are in units of 50MHz */
4225 dev_priv->rps.cur_freq = 0;
93ee2920 4226 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 4227 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 4228 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 4229 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
cee991cb
AG		 4230 if (IS_SKYLAKE(dev)) {
4231 /* Store the frequency values in 16.66 MHZ units, which is
4232 the natural hardware unit for SKL */
4233 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4234 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4235 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4236 }
3280e8b0
BW		 4237 /* hw_max = RP0 until we check for overclocking */
4238 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4239
93ee2920
TR		 4240 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4241 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4242 ret = sandybridge_pcode_read(dev_priv,
4243 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4244 &ddcc_status);
4245 if (0 == ret)
4246 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4247 clamp_t(u8,
4248 ((ddcc_status >> 8) & 0xff),
4249 dev_priv->rps.min_freq,
4250 dev_priv->rps.max_freq);
93ee2920
TR		 4251 }
4252
aed242ff
CW		 4253 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4254
3280e8b0
BW		 4255 /* Preserve min/max settings in case of re-init */
4256 if (dev_priv->rps.max_freq_softlimit == 0)
4257 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4258
93ee2920
TR		 4259 if (dev_priv->rps.min_freq_softlimit == 0) {
4260 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4261 dev_priv->rps.min_freq_softlimit =
f4ab408c
TR		 4262 /* max(RPe, 450 MHz) */
4263 max(dev_priv->rps.efficient_freq, (u8) 9);
93ee2920
TR		 4264 else
4265 dev_priv->rps.min_freq_softlimit =
4266 dev_priv->rps.min_freq;
4267 }
3280e8b0
BW		 4268}
4269
b6fef0ef 4270/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4271static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4272{
4273 struct drm_i915_private *dev_priv = dev->dev_private;
4274
4275 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4276
ba1c554c
DL		 4277 gen6_init_rps_frequencies(dev);
4278
0beb059a
AG		 4279 /* Program defaults and thresholds for RPS*/
4280 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4281 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4282
4283 /* 1 second timeout*/
4284 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4285 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4286
b6fef0ef 4287 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4288
0beb059a
AG		 4289 /* Leaning on the below call to gen6_set_rps to program/setup the
4290 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4291 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4292 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4293 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4294
4295 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4296}
4297
4298static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4299{
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 struct intel_engine_cs *ring;
4302 uint32_t rc6_mask = 0;
4303 int unused;
4304
4305 /* 1a: Software RC state - RC0 */
4306 I915_WRITE(GEN6_RC_STATE, 0);
4307
4308 /* 1b: Get forcewake during program sequence. Although the driver
4309 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4310 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4311
4312 /* 2a: Disable RC states. */
4313 I915_WRITE(GEN6_RC_CONTROL, 0);
4314
4315 /* 2b: Program RC6 thresholds.*/
4316 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4317 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4318 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4319 for_each_ring(ring, dev_priv, unused)
4320 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4321 I915_WRITE(GEN6_RC_SLEEP, 0);
4322 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4323
38c23527
ZW		 4324 /* 2c: Program Coarse Power Gating Policies. */
4325 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4326 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4327
20e49366
ZW		 4328 /* 3a: Enable RC6 */
4329 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4330 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4331 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4332 "on" : "off");
4333 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4334 GEN6_RC_CTL_EI_MODE(1) |
4335 rc6_mask);
4336
38c23527
ZW		 4337 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4338 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
4339
59bad947 4340 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4341
4342}
4343
6edee7f3
BW		 4344static void gen8_enable_rps(struct drm_device *dev)
4345{
4346 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4347 struct intel_engine_cs *ring;
93ee2920 4348 uint32_t rc6_mask = 0;
6edee7f3
BW		 4349 int unused;
4350
4351 /* 1a: Software RC state - RC0 */
4352 I915_WRITE(GEN6_RC_STATE, 0);
4353
4354 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4355 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4356 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4357
4358 /* 2a: Disable RC states. */
4359 I915_WRITE(GEN6_RC_CONTROL, 0);
4360
93ee2920
TR		 4361 /* Initialize rps frequencies */
4362 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4363
4364 /* 2b: Program RC6 thresholds.*/
4365 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4366 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4367 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4368 for_each_ring(ring, dev_priv, unused)
4369 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4370 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4371 if (IS_BROADWELL(dev))
4372 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4373 else
4374 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4375
4376 /* 3: Enable RC6 */
4377 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4378 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4379 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4380 if (IS_BROADWELL(dev))
4381 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4382 GEN7_RC_CTL_TO_MODE |
4383 rc6_mask);
4384 else
4385 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4386 GEN6_RC_CTL_EI_MODE(1) |
4387 rc6_mask);
6edee7f3
BW		 4388
4389 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4390 I915_WRITE(GEN6_RPNSWREQ,
4391 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4392 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4393 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4394 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4395 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4396
4397 /* Docs recommend 900MHz, and 300 MHz respectively */
4398 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4399 dev_priv->rps.max_freq_softlimit << 24 |
4400 dev_priv->rps.min_freq_softlimit << 16);
4401
4402 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4403 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4404 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4405 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4406
4407 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4408
4409 /* 5: Enable RPS */
7526ed79
DV		 4410 I915_WRITE(GEN6_RP_CONTROL,
4411 GEN6_RP_MEDIA_TURBO |
4412 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4413 GEN6_RP_MEDIA_IS_GFX |
4414 GEN6_RP_ENABLE |
4415 GEN6_RP_UP_BUSY_AVG |
4416 GEN6_RP_DOWN_IDLE_AVG);
4417
4418 /* 6: Ring frequency + overclocking (our driver does this later */
4419
c7f3153a 4420 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4421 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4422
59bad947 4423 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4424}
4425
79f5b2c7 4426static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4427{
79f5b2c7 4428 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4429 struct intel_engine_cs *ring;
d060c169 4430 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4431 u32 gtfifodbg;
2b4e57bd 4432 int rc6_mode;
42c0526c 4433 int i, ret;
2b4e57bd 4434
4fc688ce 4435 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4436
2b4e57bd
ED		 4437 /* Here begins a magic sequence of register writes to enable
4438 * auto-downclocking.
4439 *
4440 * Perhaps there might be some value in exposing these to
4441 * userspace...
4442 */
4443 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4444
4445 /* Clear the DBG now so we don't confuse earlier errors */
4446 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4447 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4448 I915_WRITE(GTFIFODBG, gtfifodbg);
4449 }
4450
59bad947 4451 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4452
93ee2920
TR		 4453 /* Initialize rps frequencies */
4454 gen6_init_rps_frequencies(dev);
dd0a1aa1 4455
2b4e57bd
ED		 4456 /* disable the counters and set deterministic thresholds */
4457 I915_WRITE(GEN6_RC_CONTROL, 0);
4458
4459 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4460 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4461 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4462 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4463 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4464
b4519513
CW		 4465 for_each_ring(ring, dev_priv, i)
4466 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4467
4468 I915_WRITE(GEN6_RC_SLEEP, 0);
4469 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4470 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4471 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4472 else
4473 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4474 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4475 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4476
5a7dc92a 4477 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4478 rc6_mode = intel_enable_rc6(dev_priv->dev);
4479 if (rc6_mode & INTEL_RC6_ENABLE)
4480 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4481
5a7dc92a
ED		 4482 /* We don't use those on Haswell */
4483 if (!IS_HASWELL(dev)) {
4484 if (rc6_mode & INTEL_RC6p_ENABLE)
4485 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4486
5a7dc92a
ED		 4487 if (rc6_mode & INTEL_RC6pp_ENABLE)
4488 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4489 }
2b4e57bd 4490
dc39fff7 4491 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4492
4493 I915_WRITE(GEN6_RC_CONTROL,
4494 rc6_mask |
4495 GEN6_RC_CTL_EI_MODE(1) |
4496 GEN6_RC_CTL_HW_ENABLE);
4497
dd75fdc8
CW		 4498 /* Power down if completely idle for over 50ms */
4499 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4500 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4501
42c0526c 4502 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4503 if (ret)
42c0526c 4504 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4505
4506 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4507 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4508 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4509 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4510 (pcu_mbox & 0xff) * 50);
b39fb297 4511 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4512 }
4513
dd75fdc8 4514 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4515 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4516
31643d54
BW		 4517 rc6vids = 0;
4518 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4519 if (IS_GEN6(dev) && ret) {
4520 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4521 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4522 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4523 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4524 rc6vids &= 0xffff00;
4525 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4526 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4527 if (ret)
4528 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4529 }
4530
59bad947 4531 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4532}
4533
c2bc2fc5 4534static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4535{
79f5b2c7 4536 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4537 int min_freq = 15;
3ebecd07
CW		 4538 unsigned int gpu_freq;
4539 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4540 int scaling_factor = 180;
eda79642 4541 struct cpufreq_policy *policy;
2b4e57bd 4542
4fc688ce 4543 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4544
eda79642
BW		 4545 policy = cpufreq_cpu_get(0);
4546 if (policy) {
4547 max_ia_freq = policy->cpuinfo.max_freq;
4548 cpufreq_cpu_put(policy);
4549 } else {
4550 /*
4551 * Default to measured freq if none found, PCU will ensure we
4552 * don't go over
4553 */
2b4e57bd 4554 max_ia_freq = tsc_khz;
eda79642 4555 }
2b4e57bd
ED		 4556
4557 /* Convert from kHz to MHz */
4558 max_ia_freq /= 1000;
4559
153b4b95 4560 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4561 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4562 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4563
2b4e57bd
ED		 4564 /*
4565 * For each potential GPU frequency, load a ring frequency we'd like
4566 * to use for memory access. We do this by specifying the IA frequency
4567 * the PCU should use as a reference to determine the ring frequency.
4568 */
6985b352 4569 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4570 gpu_freq--) {
6985b352 4571 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 4572 unsigned int ia_freq = 0, ring_freq = 0;
4573
46c764d4
BW		 4574 if (INTEL_INFO(dev)->gen >= 8) {
4575 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4576 ring_freq = max(min_ring_freq, gpu_freq);
4577 } else if (IS_HASWELL(dev)) {
f6aca45c 4578 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4579 ring_freq = max(min_ring_freq, ring_freq);
4580 /* leave ia_freq as the default, chosen by cpufreq */
4581 } else {
4582 /* On older processors, there is no separate ring
4583 * clock domain, so in order to boost the bandwidth
4584 * of the ring, we need to upclock the CPU (ia_freq).
4585 *
4586 * For GPU frequencies less than 750MHz,
4587 * just use the lowest ring freq.
4588 */
4589 if (gpu_freq < min_freq)
4590 ia_freq = 800;
4591 else
4592 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4593 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4594 }
2b4e57bd 4595
42c0526c
BW		 4596 sandybridge_pcode_write(dev_priv,
4597 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4598 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4599 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4600 gpu_freq);
2b4e57bd 4601 }
2b4e57bd
ED		 4602}
4603
c2bc2fc5
ID		 4604void gen6_update_ring_freq(struct drm_device *dev)
4605{
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607
4608 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4609 return;
4610
4611 mutex_lock(&dev_priv->rps.hw_lock);
4612 __gen6_update_ring_freq(dev);
4613 mutex_unlock(&dev_priv->rps.hw_lock);
4614}
4615
03af2045 4616static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4617{
095acd5f 4618 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4619 u32 val, rp0;
4620
095acd5f
D		 4621 if (dev->pdev->revision >= 0x20) {
4622 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4623
095acd5f
D		 4624 switch (INTEL_INFO(dev)->eu_total) {
4625 case 8:
4626 /* (2 * 4) config */
4627 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4628 break;
4629 case 12:
4630 /* (2 * 6) config */
4631 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4632 break;
4633 case 16:
4634 /* (2 * 8) config */
4635 default:
4636 /* Setting (2 * 8) Min RP0 for any other combination */
4637 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4638 break;
4639 }
4640 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4641 } else {
4642 /* For pre-production hardware */
4643 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4644 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4645 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4646 }
2b6b3a09
D		 4647 return rp0;
4648}
4649
4650static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4651{
4652 u32 val, rpe;
4653
4654 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4655 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4656
4657 return rpe;
4658}
4659
7707df4a
D		 4660static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4661{
095acd5f 4662 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 4663 u32 val, rp1;
4664
095acd5f
D		 4665 if (dev->pdev->revision >= 0x20) {
4666 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4667 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4668 } else {
4669 /* For pre-production hardware */
4670 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4671 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4672 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4673 }
7707df4a
D		 4674 return rp1;
4675}
4676
03af2045 4677static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4678{
095acd5f 4679 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4680 u32 val, rpn;
4681
095acd5f
D		 4682 if (dev->pdev->revision >= 0x20) {
4683 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4684 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4685 FB_GFX_FREQ_FUSE_MASK);
4686 } else { /* For pre-production hardware */
4687 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4688 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4689 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4690 }
4691
2b6b3a09
D		 4692 return rpn;
4693}
4694
f8f2b001
D		 4695static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4696{
4697 u32 val, rp1;
4698
4699 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4700
4701 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4702
4703 return rp1;
4704}
4705
03af2045 4706static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4707{
4708 u32 val, rp0;
4709
64936258 4710 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4711
4712 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4713 /* Clamp to max */
4714 rp0 = min_t(u32, rp0, 0xea);
4715
4716 return rp0;
4717}
4718
4719static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4720{
4721 u32 val, rpe;
4722
64936258 4723 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4724 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4725 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4726 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4727
4728 return rpe;
4729}
4730
03af2045 4731static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4732{
64936258 4733 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4734}
4735
ae48434c
ID		 4736/* Check that the pctx buffer wasn't move under us. */
4737static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4738{
4739 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4740
4741 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4742 dev_priv->vlv_pctx->stolen->start);
4743}
4744
38807746
D		 4745
4746/* Check that the pcbr address is not empty. */
4747static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4748{
4749 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4750
4751 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4752}
4753
4754static void cherryview_setup_pctx(struct drm_device *dev)
4755{
4756 struct drm_i915_private *dev_priv = dev->dev_private;
4757 unsigned long pctx_paddr, paddr;
4758 struct i915_gtt *gtt = &dev_priv->gtt;
4759 u32 pcbr;
4760 int pctx_size = 32*1024;
4761
4762 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4763
4764 pcbr = I915_READ(VLV_PCBR);
4765 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4766 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 4767 paddr = (dev_priv->mm.stolen_base +
4768 (gtt->stolen_size - pctx_size));
4769
4770 pctx_paddr = (paddr & (~4095));
4771 I915_WRITE(VLV_PCBR, pctx_paddr);
4772 }
ce611ef8
VS		 4773
4774 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 4775}
4776
c9cddffc
JB		 4777static void valleyview_setup_pctx(struct drm_device *dev)
4778{
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4780 struct drm_i915_gem_object *pctx;
4781 unsigned long pctx_paddr;
4782 u32 pcbr;
4783 int pctx_size = 24*1024;
4784
17b0c1f7
ID		 4785 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4786
c9cddffc
JB		 4787 pcbr = I915_READ(VLV_PCBR);
4788 if (pcbr) {
4789 /* BIOS set it up already, grab the pre-alloc'd space */
4790 int pcbr_offset;
4791
4792 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4793 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4794 pcbr_offset,
190d6cd5 4795 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4796 pctx_size);
4797 goto out;
4798 }
4799
ce611ef8
VS		 4800 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4801
c9cddffc
JB		 4802 /*
4803 * From the Gunit register HAS:
4804 * The Gfx driver is expected to program this register and ensure
4805 * proper allocation within Gfx stolen memory. For example, this
4806 * register should be programmed such than the PCBR range does not
4807 * overlap with other ranges, such as the frame buffer, protected
4808 * memory, or any other relevant ranges.
4809 */
4810 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4811 if (!pctx) {
4812 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4813 return;
4814 }
4815
4816 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4817 I915_WRITE(VLV_PCBR, pctx_paddr);
4818
4819out:
ce611ef8 4820 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 4821 dev_priv->vlv_pctx = pctx;
4822}
4823
ae48434c
ID		 4824static void valleyview_cleanup_pctx(struct drm_device *dev)
4825{
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4827
4828 if (WARN_ON(!dev_priv->vlv_pctx))
4829 return;
4830
4831 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4832 dev_priv->vlv_pctx = NULL;
4833}
4834
4e80519e
ID		 4835static void valleyview_init_gt_powersave(struct drm_device *dev)
4836{
4837 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4838 u32 val;
4e80519e
ID		 4839
4840 valleyview_setup_pctx(dev);
4841
4842 mutex_lock(&dev_priv->rps.hw_lock);
4843
2bb25c17
VS		 4844 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4845 switch ((val >> 6) & 3) {
4846 case 0:
4847 case 1:
4848 dev_priv->mem_freq = 800;
4849 break;
4850 case 2:
4851 dev_priv->mem_freq = 1066;
4852 break;
4853 case 3:
4854 dev_priv->mem_freq = 1333;
4855 break;
4856 }
80b83b62 4857 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4858
4e80519e
ID		 4859 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4860 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4861 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4862 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 4863 dev_priv->rps.max_freq);
4864
4865 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4866 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4867 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 4868 dev_priv->rps.efficient_freq);
4869
f8f2b001
D		 4870 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4871 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4872 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 4873 dev_priv->rps.rp1_freq);
4874
4e80519e
ID		 4875 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4876 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4877 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 4878 dev_priv->rps.min_freq);
4879
aed242ff
CW		 4880 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4881
4e80519e
ID		 4882 /* Preserve min/max settings in case of re-init */
4883 if (dev_priv->rps.max_freq_softlimit == 0)
4884 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4885
4886 if (dev_priv->rps.min_freq_softlimit == 0)
4887 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4888
4889 mutex_unlock(&dev_priv->rps.hw_lock);
4890}
4891
38807746
D		 4892static void cherryview_init_gt_powersave(struct drm_device *dev)
4893{
2b6b3a09 4894 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4895 u32 val;
2b6b3a09 4896
38807746 4897 cherryview_setup_pctx(dev);
2b6b3a09
D		 4898
4899 mutex_lock(&dev_priv->rps.hw_lock);
4900
c6e8f39d
VS		 4901 mutex_lock(&dev_priv->dpio_lock);
4902 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4903 mutex_unlock(&dev_priv->dpio_lock);
4904
2bb25c17
VS		 4905 switch ((val >> 2) & 0x7) {
4906 case 0:
4907 case 1:
4908 dev_priv->rps.cz_freq = 200;
4909 dev_priv->mem_freq = 1600;
4910 break;
4911 case 2:
4912 dev_priv->rps.cz_freq = 267;
4913 dev_priv->mem_freq = 1600;
4914 break;
4915 case 3:
4916 dev_priv->rps.cz_freq = 333;
4917 dev_priv->mem_freq = 2000;
4918 break;
4919 case 4:
4920 dev_priv->rps.cz_freq = 320;
4921 dev_priv->mem_freq = 1600;
4922 break;
4923 case 5:
4924 dev_priv->rps.cz_freq = 400;
4925 dev_priv->mem_freq = 1600;
4926 break;
4927 }
80b83b62 4928 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4929
2b6b3a09
D		 4930 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4931 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4932 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4933 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 4934 dev_priv->rps.max_freq);
4935
4936 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4937 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4938 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4939 dev_priv->rps.efficient_freq);
4940
7707df4a
D		 4941 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4942 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 4943 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 4944 dev_priv->rps.rp1_freq);
4945
2b6b3a09
D		 4946 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4947 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4948 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 4949 dev_priv->rps.min_freq);
4950
1c14762d
VS		 4951 WARN_ONCE((dev_priv->rps.max_freq |
4952 dev_priv->rps.efficient_freq |
4953 dev_priv->rps.rp1_freq |
4954 dev_priv->rps.min_freq) & 1,
4955 "Odd GPU freq values\n");
4956
aed242ff
CW		 4957 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4958
2b6b3a09
D		 4959 /* Preserve min/max settings in case of re-init */
4960 if (dev_priv->rps.max_freq_softlimit == 0)
4961 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4962
4963 if (dev_priv->rps.min_freq_softlimit == 0)
4964 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4965
4966 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4967}
4968
4e80519e
ID		 4969static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4970{
4971 valleyview_cleanup_pctx(dev);
4972}
4973
38807746
D		 4974static void cherryview_enable_rps(struct drm_device *dev)
4975{
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 struct intel_engine_cs *ring;
2b6b3a09 4978 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4979 int i;
4980
4981 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4982
4983 gtfifodbg = I915_READ(GTFIFODBG);
4984 if (gtfifodbg) {
4985 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4986 gtfifodbg);
4987 I915_WRITE(GTFIFODBG, gtfifodbg);
4988 }
4989
4990 cherryview_check_pctx(dev_priv);
4991
4992 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4993 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4994 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 4995
160614a2
VS		 4996 /* Disable RC states. */
4997 I915_WRITE(GEN6_RC_CONTROL, 0);
4998
38807746
D		 4999 /* 2a: Program RC6 thresholds.*/
5000 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5001 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5002 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5003
5004 for_each_ring(ring, dev_priv, i)
5005 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5006 I915_WRITE(GEN6_RC_SLEEP, 0);
5007
af5a75a3
VS		 5008 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
5009 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
38807746
D		 5010
5011 /* allows RC6 residency counter to work */
5012 I915_WRITE(VLV_COUNTER_CONTROL,
5013 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5014 VLV_MEDIA_RC6_COUNT_EN |
5015 VLV_RENDER_RC6_COUNT_EN));
5016
5017 /* For now we assume BIOS is allocating and populating the PCBR */
5018 pcbr = I915_READ(VLV_PCBR);
5019
38807746
D		 5020 /* 3: Enable RC6 */
5021 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5022 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5023 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5024
5025 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5026
2b6b3a09 5027 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5028 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5029 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5030 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5031 I915_WRITE(GEN6_RP_UP_EI, 66000);
5032 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5033
5034 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5035
5036 /* 5: Enable RPS */
5037 I915_WRITE(GEN6_RP_CONTROL,
5038 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5039 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5040 GEN6_RP_ENABLE |
5041 GEN6_RP_UP_BUSY_AVG |
5042 GEN6_RP_DOWN_IDLE_AVG);
5043
5044 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5045
8d40c3ae
VS		 5046 /* RPS code assumes GPLL is used */
5047 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5048
c8e9627d 5049 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5050 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5051
5052 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5053 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5054 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5055 dev_priv->rps.cur_freq);
5056
5057 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5058 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5059 dev_priv->rps.efficient_freq);
5060
5061 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5062
59bad947 5063 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5064}
5065
0a073b84
JB		 5066static void valleyview_enable_rps(struct drm_device *dev)
5067{
5068 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5069 struct intel_engine_cs *ring;
2a5913a8 5070 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5071 int i;
5072
5073 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5074
ae48434c
ID		 5075 valleyview_check_pctx(dev_priv);
5076
0a073b84 5077 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5078 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5079 gtfifodbg);
0a073b84
JB		 5080 I915_WRITE(GTFIFODBG, gtfifodbg);
5081 }
5082
c8d9a590 5083 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5084 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5085
160614a2
VS		 5086 /* Disable RC states. */
5087 I915_WRITE(GEN6_RC_CONTROL, 0);
5088
cad725fe 5089 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5090 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5091 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5092 I915_WRITE(GEN6_RP_UP_EI, 66000);
5093 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5094
5095 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5096
5097 I915_WRITE(GEN6_RP_CONTROL,
5098 GEN6_RP_MEDIA_TURBO |
5099 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5100 GEN6_RP_MEDIA_IS_GFX |
5101 GEN6_RP_ENABLE |
5102 GEN6_RP_UP_BUSY_AVG |
5103 GEN6_RP_DOWN_IDLE_CONT);
5104
5105 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5106 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5107 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5108
5109 for_each_ring(ring, dev_priv, i)
5110 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5111
2f0aa304 5112 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5113
5114 /* allows RC6 residency counter to work */
49798eb2 5115 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5116 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5117 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5118 VLV_MEDIA_RC6_COUNT_EN |
5119 VLV_RENDER_RC6_COUNT_EN));
31685c25 5120
a2b23fe0 5121 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5122 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5123
5124 intel_print_rc6_info(dev, rc6_mode);
5125
a2b23fe0 5126 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5127
64936258 5128 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5129
8d40c3ae
VS		 5130 /* RPS code assumes GPLL is used */
5131 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5132
c8e9627d 5133 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5134 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5135
b39fb297 5136 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5137 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5138 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5139 dev_priv->rps.cur_freq);
0a073b84 5140
73008b98 5141 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5142 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5143 dev_priv->rps.efficient_freq);
0a073b84 5144
b39fb297 5145 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5146
59bad947 5147 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5148}
5149
dde18883
ED		 5150static unsigned long intel_pxfreq(u32 vidfreq)
5151{
5152 unsigned long freq;
5153 int div = (vidfreq & 0x3f0000) >> 16;
5154 int post = (vidfreq & 0x3000) >> 12;
5155 int pre = (vidfreq & 0x7);
5156
5157 if (!pre)
5158 return 0;
5159
5160 freq = ((div * 133333) / ((1<<post) * pre));
5161
5162 return freq;
5163}
5164
eb48eb00
DV		 5165static const struct cparams {
5166 u16 i;
5167 u16 t;
5168 u16 m;
5169 u16 c;
5170} cparams[] = {
5171 { 1, 1333, 301, 28664 },
5172 { 1, 1066, 294, 24460 },
5173 { 1, 800, 294, 25192 },
5174 { 0, 1333, 276, 27605 },
5175 { 0, 1066, 276, 27605 },
5176 { 0, 800, 231, 23784 },
5177};
5178
f531dcb2 5179static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5180{
5181 u64 total_count, diff, ret;
5182 u32 count1, count2, count3, m = 0, c = 0;
5183 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5184 int i;
5185
02d71956
DV		 5186 assert_spin_locked(&mchdev_lock);
5187
20e4d407 5188 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5189
5190 /* Prevent division-by-zero if we are asking too fast.
5191 * Also, we don't get interesting results if we are polling
5192 * faster than once in 10ms, so just return the saved value
5193 * in such cases.
5194 */
5195 if (diff1 <= 10)
20e4d407 5196 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5197
5198 count1 = I915_READ(DMIEC);
5199 count2 = I915_READ(DDREC);
5200 count3 = I915_READ(CSIEC);
5201
5202 total_count = count1 + count2 + count3;
5203
5204 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5205 if (total_count < dev_priv->ips.last_count1) {
5206 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5207 diff += total_count;
5208 } else {
20e4d407 5209 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5210 }
5211
5212 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5213 if (cparams[i].i == dev_priv->ips.c_m &&
5214 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5215 m = cparams[i].m;
5216 c = cparams[i].c;
5217 break;
5218 }
5219 }
5220
5221 diff = div_u64(diff, diff1);
5222 ret = ((m * diff) + c);
5223 ret = div_u64(ret, 10);
5224
20e4d407
DV		 5225 dev_priv->ips.last_count1 = total_count;
5226 dev_priv->ips.last_time1 = now;
eb48eb00 5227
20e4d407 5228 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5229
5230 return ret;
5231}
5232
f531dcb2
CW		 5233unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5234{
3d13ef2e 5235 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5236 unsigned long val;
5237
3d13ef2e 5238 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5239 return 0;
5240
5241 spin_lock_irq(&mchdev_lock);
5242
5243 val = __i915_chipset_val(dev_priv);
5244
5245 spin_unlock_irq(&mchdev_lock);
5246
5247 return val;
5248}
5249
eb48eb00
DV		 5250unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5251{
5252 unsigned long m, x, b;
5253 u32 tsfs;
5254
5255 tsfs = I915_READ(TSFS);
5256
5257 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5258 x = I915_READ8(TR1);
5259
5260 b = tsfs & TSFS_INTR_MASK;
5261
5262 return ((m * x) / 127) - b;
5263}
5264
d972d6ee
MK		 5265static int _pxvid_to_vd(u8 pxvid)
5266{
5267 if (pxvid == 0)
5268 return 0;
5269
5270 if (pxvid >= 8 && pxvid < 31)
5271 pxvid = 31;
5272
5273 return (pxvid + 2) * 125;
5274}
5275
5276static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5277{
3d13ef2e 5278 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5279 const int vd = _pxvid_to_vd(pxvid);
5280 const int vm = vd - 1125;
5281
3d13ef2e 5282 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5283 return vm > 0 ? vm : 0;
5284
5285 return vd;
eb48eb00
DV		 5286}
5287
02d71956 5288static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5289{
5ed0bdf2 5290 u64 now, diff, diffms;
eb48eb00
DV		 5291 u32 count;
5292
02d71956 5293 assert_spin_locked(&mchdev_lock);
eb48eb00 5294
5ed0bdf2
TG		 5295 now = ktime_get_raw_ns();
5296 diffms = now - dev_priv->ips.last_time2;
5297 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5298
5299 /* Don't divide by 0 */
eb48eb00
DV		 5300 if (!diffms)
5301 return;
5302
5303 count = I915_READ(GFXEC);
5304
20e4d407
DV		 5305 if (count < dev_priv->ips.last_count2) {
5306 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5307 diff += count;
5308 } else {
20e4d407 5309 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5310 }
5311
20e4d407
DV		 5312 dev_priv->ips.last_count2 = count;
5313 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5314
5315 /* More magic constants... */
5316 diff = diff * 1181;
5317 diff = div_u64(diff, diffms * 10);
20e4d407 5318 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5319}
5320
02d71956
DV		 5321void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5322{
3d13ef2e
DL		 5323 struct drm_device *dev = dev_priv->dev;
5324
5325 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5326 return;
5327
9270388e 5328 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5329
5330 __i915_update_gfx_val(dev_priv);
5331
9270388e 5332 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5333}
5334
f531dcb2 5335static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5336{
5337 unsigned long t, corr, state1, corr2, state2;
5338 u32 pxvid, ext_v;
5339
02d71956
DV		 5340 assert_spin_locked(&mchdev_lock);
5341
b39fb297 5342 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5343 pxvid = (pxvid >> 24) & 0x7f;
5344 ext_v = pvid_to_extvid(dev_priv, pxvid);
5345
5346 state1 = ext_v;
5347
5348 t = i915_mch_val(dev_priv);
5349
5350 /* Revel in the empirically derived constants */
5351
5352 /* Correction factor in 1/100000 units */
5353 if (t > 80)
5354 corr = ((t * 2349) + 135940);
5355 else if (t >= 50)
5356 corr = ((t * 964) + 29317);
5357 else /* < 50 */
5358 corr = ((t * 301) + 1004);
5359
5360 corr = corr * ((150142 * state1) / 10000 - 78642);
5361 corr /= 100000;
20e4d407 5362 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5363
5364 state2 = (corr2 * state1) / 10000;
5365 state2 /= 100; /* convert to mW */
5366
02d71956 5367 __i915_update_gfx_val(dev_priv);
eb48eb00 5368
20e4d407 5369 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5370}
5371
f531dcb2
CW		 5372unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5373{
3d13ef2e 5374 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5375 unsigned long val;
5376
3d13ef2e 5377 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5378 return 0;
5379
5380 spin_lock_irq(&mchdev_lock);
5381
5382 val = __i915_gfx_val(dev_priv);
5383
5384 spin_unlock_irq(&mchdev_lock);
5385
5386 return val;
5387}
5388
eb48eb00
DV		 5389/**
5390 * i915_read_mch_val - return value for IPS use
5391 *
5392 * Calculate and return a value for the IPS driver to use when deciding whether
5393 * we have thermal and power headroom to increase CPU or GPU power budget.
5394 */
5395unsigned long i915_read_mch_val(void)
5396{
5397 struct drm_i915_private *dev_priv;
5398 unsigned long chipset_val, graphics_val, ret = 0;
5399
9270388e 5400 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5401 if (!i915_mch_dev)
5402 goto out_unlock;
5403 dev_priv = i915_mch_dev;
5404
f531dcb2
CW		 5405 chipset_val = __i915_chipset_val(dev_priv);
5406 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5407
5408 ret = chipset_val + graphics_val;
5409
5410out_unlock:
9270388e 5411 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5412
5413 return ret;
5414}
5415EXPORT_SYMBOL_GPL(i915_read_mch_val);
5416
5417/**
5418 * i915_gpu_raise - raise GPU frequency limit
5419 *
5420 * Raise the limit; IPS indicates we have thermal headroom.
5421 */
5422bool i915_gpu_raise(void)
5423{
5424 struct drm_i915_private *dev_priv;
5425 bool ret = true;
5426
9270388e 5427 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5428 if (!i915_mch_dev) {
5429 ret = false;
5430 goto out_unlock;
5431 }
5432 dev_priv = i915_mch_dev;
5433
20e4d407
DV		 5434 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5435 dev_priv->ips.max_delay--;
eb48eb00
DV		 5436
5437out_unlock:
9270388e 5438 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5439
5440 return ret;
5441}
5442EXPORT_SYMBOL_GPL(i915_gpu_raise);
5443
5444/**
5445 * i915_gpu_lower - lower GPU frequency limit
5446 *
5447 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5448 * frequency maximum.
5449 */
5450bool i915_gpu_lower(void)
5451{
5452 struct drm_i915_private *dev_priv;
5453 bool ret = true;
5454
9270388e 5455 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5456 if (!i915_mch_dev) {
5457 ret = false;
5458 goto out_unlock;
5459 }
5460 dev_priv = i915_mch_dev;
5461
20e4d407
DV		 5462 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5463 dev_priv->ips.max_delay++;
eb48eb00
DV		 5464
5465out_unlock:
9270388e 5466 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5467
5468 return ret;
5469}
5470EXPORT_SYMBOL_GPL(i915_gpu_lower);
5471
5472/**
5473 * i915_gpu_busy - indicate GPU business to IPS
5474 *
5475 * Tell the IPS driver whether or not the GPU is busy.
5476 */
5477bool i915_gpu_busy(void)
5478{
5479 struct drm_i915_private *dev_priv;
a4872ba6 5480 struct intel_engine_cs *ring;
eb48eb00 5481 bool ret = false;
f047e395 5482 int i;
eb48eb00 5483
9270388e 5484 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5485 if (!i915_mch_dev)
5486 goto out_unlock;
5487 dev_priv = i915_mch_dev;
5488
f047e395
CW		 5489 for_each_ring(ring, dev_priv, i)
5490 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5491
5492out_unlock:
9270388e 5493 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5494
5495 return ret;
5496}
5497EXPORT_SYMBOL_GPL(i915_gpu_busy);
5498
5499/**
5500 * i915_gpu_turbo_disable - disable graphics turbo
5501 *
5502 * Disable graphics turbo by resetting the max frequency and setting the
5503 * current frequency to the default.
5504 */
5505bool i915_gpu_turbo_disable(void)
5506{
5507 struct drm_i915_private *dev_priv;
5508 bool ret = true;
5509
9270388e 5510 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5511 if (!i915_mch_dev) {
5512 ret = false;
5513 goto out_unlock;
5514 }
5515 dev_priv = i915_mch_dev;
5516
20e4d407 5517 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5518
20e4d407 5519 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5520 ret = false;
5521
5522out_unlock:
9270388e 5523 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5524
5525 return ret;
5526}
5527EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5528
5529/**
5530 * Tells the intel_ips driver that the i915 driver is now loaded, if
5531 * IPS got loaded first.
5532 *
5533 * This awkward dance is so that neither module has to depend on the
5534 * other in order for IPS to do the appropriate communication of
5535 * GPU turbo limits to i915.
5536 */
5537static void
5538ips_ping_for_i915_load(void)
5539{
5540 void (*link)(void);
5541
5542 link = symbol_get(ips_link_to_i915_driver);
5543 if (link) {
5544 link();
5545 symbol_put(ips_link_to_i915_driver);
5546 }
5547}
5548
5549void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5550{
02d71956
DV		 5551 /* We only register the i915 ips part with intel-ips once everything is
5552 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5553 spin_lock_irq(&mchdev_lock);
eb48eb00 5554 i915_mch_dev = dev_priv;
9270388e 5555 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5556
5557 ips_ping_for_i915_load();
5558}
5559
5560void intel_gpu_ips_teardown(void)
5561{
9270388e 5562 spin_lock_irq(&mchdev_lock);
eb48eb00 5563 i915_mch_dev = NULL;
9270388e 5564 spin_unlock_irq(&mchdev_lock);
eb48eb00 5565}
76c3552f 5566
8090c6b9 5567static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5568{
5569 struct drm_i915_private *dev_priv = dev->dev_private;
5570 u32 lcfuse;
5571 u8 pxw[16];
5572 int i;
5573
5574 /* Disable to program */
5575 I915_WRITE(ECR, 0);
5576 POSTING_READ(ECR);
5577
5578 /* Program energy weights for various events */
5579 I915_WRITE(SDEW, 0x15040d00);
5580 I915_WRITE(CSIEW0, 0x007f0000);
5581 I915_WRITE(CSIEW1, 0x1e220004);
5582 I915_WRITE(CSIEW2, 0x04000004);
5583
5584 for (i = 0; i < 5; i++)
5585 I915_WRITE(PEW + (i * 4), 0);
5586 for (i = 0; i < 3; i++)
5587 I915_WRITE(DEW + (i * 4), 0);
5588
5589 /* Program P-state weights to account for frequency power adjustment */
5590 for (i = 0; i < 16; i++) {
5591 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5592 unsigned long freq = intel_pxfreq(pxvidfreq);
5593 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5594 PXVFREQ_PX_SHIFT;
5595 unsigned long val;
5596
5597 val = vid * vid;
5598 val *= (freq / 1000);
5599 val *= 255;
5600 val /= (127*127*900);
5601 if (val > 0xff)
5602 DRM_ERROR("bad pxval: %ld\n", val);
5603 pxw[i] = val;
5604 }
5605 /* Render standby states get 0 weight */
5606 pxw[14] = 0;
5607 pxw[15] = 0;
5608
5609 for (i = 0; i < 4; i++) {
5610 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5611 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5612 I915_WRITE(PXW + (i * 4), val);
5613 }
5614
5615 /* Adjust magic regs to magic values (more experimental results) */
5616 I915_WRITE(OGW0, 0);
5617 I915_WRITE(OGW1, 0);
5618 I915_WRITE(EG0, 0x00007f00);
5619 I915_WRITE(EG1, 0x0000000e);
5620 I915_WRITE(EG2, 0x000e0000);
5621 I915_WRITE(EG3, 0x68000300);
5622 I915_WRITE(EG4, 0x42000000);
5623 I915_WRITE(EG5, 0x00140031);
5624 I915_WRITE(EG6, 0);
5625 I915_WRITE(EG7, 0);
5626
5627 for (i = 0; i < 8; i++)
5628 I915_WRITE(PXWL + (i * 4), 0);
5629
5630 /* Enable PMON + select events */
5631 I915_WRITE(ECR, 0x80000019);
5632
5633 lcfuse = I915_READ(LCFUSE02);
5634
20e4d407 5635 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5636}
5637
ae48434c
ID		 5638void intel_init_gt_powersave(struct drm_device *dev)
5639{
e6069ca8
ID		 5640 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5641
38807746
D		 5642 if (IS_CHERRYVIEW(dev))
5643 cherryview_init_gt_powersave(dev);
5644 else if (IS_VALLEYVIEW(dev))
4e80519e 5645 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5646}
5647
5648void intel_cleanup_gt_powersave(struct drm_device *dev)
5649{
38807746
D		 5650 if (IS_CHERRYVIEW(dev))
5651 return;
5652 else if (IS_VALLEYVIEW(dev))
4e80519e 5653 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5654}
5655
dbea3cea
ID		 5656static void gen6_suspend_rps(struct drm_device *dev)
5657{
5658 struct drm_i915_private *dev_priv = dev->dev_private;
5659
5660 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5661
4c2a8897 5662 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 5663}
5664
156c7ca0
JB		 5665/**
5666 * intel_suspend_gt_powersave - suspend PM work and helper threads
5667 * @dev: drm device
5668 *
5669 * We don't want to disable RC6 or other features here, we just want
5670 * to make sure any work we've queued has finished and won't bother
5671 * us while we're suspended.
5672 */
5673void intel_suspend_gt_powersave(struct drm_device *dev)
5674{
5675 struct drm_i915_private *dev_priv = dev->dev_private;
5676
d4d70aa5
ID		 5677 if (INTEL_INFO(dev)->gen < 6)
5678 return;
5679
dbea3cea 5680 gen6_suspend_rps(dev);
b47adc17
D		 5681
5682 /* Force GPU to min freq during suspend */
5683 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5684}
5685
8090c6b9
DV		 5686void intel_disable_gt_powersave(struct drm_device *dev)
5687{
1a01ab3b
JB		 5688 struct drm_i915_private *dev_priv = dev->dev_private;
5689
930ebb46 5690 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5691 ironlake_disable_drps(dev);
38807746 5692 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5693 intel_suspend_gt_powersave(dev);
e494837a 5694
4fc688ce 5695 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 5696 if (INTEL_INFO(dev)->gen >= 9)
5697 gen9_disable_rps(dev);
5698 else if (IS_CHERRYVIEW(dev))
38807746
D		 5699 cherryview_disable_rps(dev);
5700 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5701 valleyview_disable_rps(dev);
5702 else
5703 gen6_disable_rps(dev);
e534770a 5704
c0951f0c 5705 dev_priv->rps.enabled = false;
4fc688ce 5706 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5707 }
8090c6b9
DV		 5708}
5709
1a01ab3b
JB		 5710static void intel_gen6_powersave_work(struct work_struct *work)
5711{
5712 struct drm_i915_private *dev_priv =
5713 container_of(work, struct drm_i915_private,
5714 rps.delayed_resume_work.work);
5715 struct drm_device *dev = dev_priv->dev;
5716
4fc688ce 5717 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5718
4c2a8897 5719 gen6_reset_rps_interrupts(dev);
3cc134e3 5720
38807746
D		 5721 if (IS_CHERRYVIEW(dev)) {
5722 cherryview_enable_rps(dev);
5723 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5724 valleyview_enable_rps(dev);
20e49366 5725 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5726 gen9_enable_rc6(dev);
20e49366 5727 gen9_enable_rps(dev);
b6fef0ef 5728 __gen6_update_ring_freq(dev);
6edee7f3
BW		 5729 } else if (IS_BROADWELL(dev)) {
5730 gen8_enable_rps(dev);
c2bc2fc5 5731 __gen6_update_ring_freq(dev);
0a073b84
JB		 5732 } else {
5733 gen6_enable_rps(dev);
c2bc2fc5 5734 __gen6_update_ring_freq(dev);
0a073b84 5735 }
aed242ff
CW		 5736
5737 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5738 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5739
5740 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5741 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5742
c0951f0c 5743 dev_priv->rps.enabled = true;
3cc134e3 5744
4c2a8897 5745 gen6_enable_rps_interrupts(dev);
3cc134e3 5746
4fc688ce 5747 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5748
5749 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5750}
5751
8090c6b9
DV		 5752void intel_enable_gt_powersave(struct drm_device *dev)
5753{
1a01ab3b
JB		 5754 struct drm_i915_private *dev_priv = dev->dev_private;
5755
f61018b1
YZ		 5756 /* Powersaving is controlled by the host when inside a VM */
5757 if (intel_vgpu_active(dev))
5758 return;
5759
8090c6b9 5760 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5761 mutex_lock(&dev->struct_mutex);
8090c6b9 5762 ironlake_enable_drps(dev);
8090c6b9 5763 intel_init_emon(dev);
dc1d0136 5764 mutex_unlock(&dev->struct_mutex);
38807746 5765 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5766 /*
5767 * PCU communication is slow and this doesn't need to be
5768 * done at any specific time, so do this out of our fast path
5769 * to make resume and init faster.
c6df39b5
ID		 5770 *
5771 * We depend on the HW RC6 power context save/restore
5772 * mechanism when entering D3 through runtime PM suspend. So
5773 * disable RPM until RPS/RC6 is properly setup. We can only
5774 * get here via the driver load/system resume/runtime resume
5775 * paths, so the _noresume version is enough (and in case of
5776 * runtime resume it's necessary).
1a01ab3b 5777 */
c6df39b5
ID		 5778 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5779 round_jiffies_up_relative(HZ)))
5780 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5781 }
5782}
5783
c6df39b5
ID		 5784void intel_reset_gt_powersave(struct drm_device *dev)
5785{
5786 struct drm_i915_private *dev_priv = dev->dev_private;
5787
dbea3cea
ID		 5788 if (INTEL_INFO(dev)->gen < 6)
5789 return;
5790
5791 gen6_suspend_rps(dev);
c6df39b5 5792 dev_priv->rps.enabled = false;
c6df39b5
ID		 5793}
5794
3107bd48
DV		 5795static void ibx_init_clock_gating(struct drm_device *dev)
5796{
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798
5799 /*
5800 * On Ibex Peak and Cougar Point, we need to disable clock
5801 * gating for the panel power sequencer or it will fail to
5802 * start up when no ports are active.
5803 */
5804 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5805}
5806
0e088b8f
VS		 5807static void g4x_disable_trickle_feed(struct drm_device *dev)
5808{
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 int pipe;
5811
055e393f 5812 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5813 I915_WRITE(DSPCNTR(pipe),
5814 I915_READ(DSPCNTR(pipe)) |
5815 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5816 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5817 }
5818}
5819
017636cc
VS		 5820static void ilk_init_lp_watermarks(struct drm_device *dev)
5821{
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823
5824 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5825 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5826 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5827
5828 /*
5829 * Don't touch WM1S_LP_EN here.
5830 * Doing so could cause underruns.
5831 */
5832}
5833
1fa61106 5834static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5835{
5836 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5837 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5838
f1e8fa56
DL		 5839 /*
5840 * Required for FBC
5841 * WaFbcDisableDpfcClockGating:ilk
5842 */
4d47e4f5
DL		 5843 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5844 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5845 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5846
5847 I915_WRITE(PCH_3DCGDIS0,
5848 MARIUNIT_CLOCK_GATE_DISABLE |
5849 SVSMUNIT_CLOCK_GATE_DISABLE);
5850 I915_WRITE(PCH_3DCGDIS1,
5851 VFMUNIT_CLOCK_GATE_DISABLE);
5852
6f1d69b0
ED		 5853 /*
5854 * According to the spec the following bits should be set in
5855 * order to enable memory self-refresh
5856 * The bit 22/21 of 0x42004
5857 * The bit 5 of 0x42020
5858 * The bit 15 of 0x45000
5859 */
5860 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5861 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5862 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5863 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5864 I915_WRITE(DISP_ARB_CTL,
5865 (I915_READ(DISP_ARB_CTL) |
5866 DISP_FBC_WM_DIS));
017636cc
VS		 5867
5868 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5869
5870 /*
5871 * Based on the document from hardware guys the following bits
5872 * should be set unconditionally in order to enable FBC.
5873 * The bit 22 of 0x42000
5874 * The bit 22 of 0x42004
5875 * The bit 7,8,9 of 0x42020.
5876 */
5877 if (IS_IRONLAKE_M(dev)) {
4bb35334 5878 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5879 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5880 I915_READ(ILK_DISPLAY_CHICKEN1) |
5881 ILK_FBCQ_DIS);
5882 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5883 I915_READ(ILK_DISPLAY_CHICKEN2) |
5884 ILK_DPARB_GATE);
6f1d69b0
ED		 5885 }
5886
4d47e4f5
DL		 5887 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5888
6f1d69b0
ED		 5889 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5890 I915_READ(ILK_DISPLAY_CHICKEN2) |
5891 ILK_ELPIN_409_SELECT);
5892 I915_WRITE(_3D_CHICKEN2,
5893 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5894 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5895
ecdb4eb7 5896 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5897 I915_WRITE(CACHE_MODE_0,
5898 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5899
4e04632e
AG		 5900 /* WaDisable_RenderCache_OperationalFlush:ilk */
5901 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5902
0e088b8f 5903 g4x_disable_trickle_feed(dev);
bdad2b2f 5904
3107bd48
DV		 5905 ibx_init_clock_gating(dev);
5906}
5907
5908static void cpt_init_clock_gating(struct drm_device *dev)
5909{
5910 struct drm_i915_private *dev_priv = dev->dev_private;
5911 int pipe;
3f704fa2 5912 uint32_t val;
3107bd48
DV		 5913
5914 /*
5915 * On Ibex Peak and Cougar Point, we need to disable clock
5916 * gating for the panel power sequencer or it will fail to
5917 * start up when no ports are active.
5918 */
cd664078
JB		 5919 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5920 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5921 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5922 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5923 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5924 /* The below fixes the weird display corruption, a few pixels shifted
5925 * downward, on (only) LVDS of some HP laptops with IVY.
5926 */
055e393f 5927 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5928 val = I915_READ(TRANS_CHICKEN2(pipe));
5929 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5930 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5931 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5932 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5933 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5934 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5935 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5936 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5937 }
3107bd48 5938 /* WADP0ClockGatingDisable */
055e393f 5939 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5940 I915_WRITE(TRANS_CHICKEN1(pipe),
5941 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5942 }
6f1d69b0
ED		 5943}
5944
1d7aaa0c
DV		 5945static void gen6_check_mch_setup(struct drm_device *dev)
5946{
5947 struct drm_i915_private *dev_priv = dev->dev_private;
5948 uint32_t tmp;
5949
5950 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5951 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5952 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5953 tmp);
1d7aaa0c
DV		 5954}
5955
1fa61106 5956static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5957{
5958 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5959 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5960
231e54f6 5961 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5962
5963 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5964 I915_READ(ILK_DISPLAY_CHICKEN2) |
5965 ILK_ELPIN_409_SELECT);
5966
ecdb4eb7 5967 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5968 I915_WRITE(_3D_CHICKEN,
5969 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5970
4e04632e
AG		 5971 /* WaDisable_RenderCache_OperationalFlush:snb */
5972 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5973
8d85d272
VS		 5974 /*
5975 * BSpec recoomends 8x4 when MSAA is used,
5976 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5977 *
5978 * Note that PS/WM thread counts depend on the WIZ hashing
5979 * disable bit, which we don't touch here, but it's good
5980 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5981 */
5982 I915_WRITE(GEN6_GT_MODE,
98533251 5983 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 5984
017636cc 5985 ilk_init_lp_watermarks(dev);
6f1d69b0 5986
6f1d69b0 5987 I915_WRITE(CACHE_MODE_0,
50743298 5988 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5989
5990 I915_WRITE(GEN6_UCGCTL1,
5991 I915_READ(GEN6_UCGCTL1) |
5992 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5993 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5994
5995 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5996 * gating disable must be set. Failure to set it results in
5997 * flickering pixels due to Z write ordering failures after
5998 * some amount of runtime in the Mesa "fire" demo, and Unigine
5999 * Sanctuary and Tropics, and apparently anything else with
6000 * alpha test or pixel discard.
6001 *
6002 * According to the spec, bit 11 (RCCUNIT) must also be set,
6003 * but we didn't debug actual testcases to find it out.
0f846f81 6004 *
ef59318c
VS		 6005 * WaDisableRCCUnitClockGating:snb
6006 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6007 */
6008 I915_WRITE(GEN6_UCGCTL2,
6009 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6010 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6011
5eb146dd 6012 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6013 I915_WRITE(_3D_CHICKEN3,
6014 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6015
e927ecde
VS		 6016 /*
6017 * Bspec says:
6018 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6019 * 3DSTATE_SF number of SF output attributes is more than 16."
6020 */
6021 I915_WRITE(_3D_CHICKEN3,
6022 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6023
6f1d69b0
ED		 6024 /*
6025 * According to the spec the following bits should be
6026 * set in order to enable memory self-refresh and fbc:
6027 * The bit21 and bit22 of 0x42000
6028 * The bit21 and bit22 of 0x42004
6029 * The bit5 and bit7 of 0x42020
6030 * The bit14 of 0x70180
6031 * The bit14 of 0x71180
4bb35334
DL		 6032 *
6033 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6034 */
6035 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6036 I915_READ(ILK_DISPLAY_CHICKEN1) |
6037 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6038 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6039 I915_READ(ILK_DISPLAY_CHICKEN2) |
6040 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6041 I915_WRITE(ILK_DSPCLK_GATE_D,
6042 I915_READ(ILK_DSPCLK_GATE_D) |
6043 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6044 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6045
0e088b8f 6046 g4x_disable_trickle_feed(dev);
f8f2ac9a 6047
3107bd48 6048 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6049
6050 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6051}
6052
6053static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6054{
6055 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6056
3aad9059 6057 /*
46680e0a 6058 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6059 *
6060 * This actually overrides the dispatch
6061 * mode for all thread types.
6062 */
6f1d69b0
ED		 6063 reg &= ~GEN7_FF_SCHED_MASK;
6064 reg |= GEN7_FF_TS_SCHED_HW;
6065 reg |= GEN7_FF_VS_SCHED_HW;
6066 reg |= GEN7_FF_DS_SCHED_HW;
6067
6068 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6069}
6070
17a303ec
PZ		 6071static void lpt_init_clock_gating(struct drm_device *dev)
6072{
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074
6075 /*
6076 * TODO: this bit should only be enabled when really needed, then
6077 * disabled when not needed anymore in order to save power.
6078 */
6079 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6080 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6081 I915_READ(SOUTH_DSPCLK_GATE_D) |
6082 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6083
6084 /* WADPOClockGatingDisable:hsw */
6085 I915_WRITE(_TRANSA_CHICKEN1,
6086 I915_READ(_TRANSA_CHICKEN1) |
6087 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6088}
6089
7d708ee4
ID		 6090static void lpt_suspend_hw(struct drm_device *dev)
6091{
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093
6094 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6095 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6096
6097 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6098 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6099 }
6100}
6101
47c2bd97 6102static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6103{
6104 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6105 enum pipe pipe;
1020a5c2
BW		 6106
6107 I915_WRITE(WM3_LP_ILK, 0);
6108 I915_WRITE(WM2_LP_ILK, 0);
6109 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 6110
ab57fff1 6111 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6112 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6113
ab57fff1 6114 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6115 I915_WRITE(CHICKEN_PAR1_1,
6116 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6117
ab57fff1 6118 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6119 for_each_pipe(dev_priv, pipe) {
07d27e20 6120 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6121 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6122 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6123 }
63801f21 6124
ab57fff1
BW		 6125 /* WaVSRefCountFullforceMissDisable:bdw */
6126 /* WaDSRefCountFullforceMissDisable:bdw */
6127 I915_WRITE(GEN7_FF_THREAD_MODE,
6128 I915_READ(GEN7_FF_THREAD_MODE) &
6129 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6130
295e8bb7
VS		 6131 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6132 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6133
6134 /* WaDisableSDEUnitClockGating:bdw */
6135 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6136 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6137
89d6b2b8 6138 lpt_init_clock_gating(dev);
1020a5c2
BW		 6139}
6140
cad2a2d7
ED		 6141static void haswell_init_clock_gating(struct drm_device *dev)
6142{
6143 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6144
017636cc 6145 ilk_init_lp_watermarks(dev);
cad2a2d7 6146
f3fc4884
FJ		 6147 /* L3 caching of data atomics doesn't work -- disable it. */
6148 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6149 I915_WRITE(HSW_ROW_CHICKEN3,
6150 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6151
ecdb4eb7 6152 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6153 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6154 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6155 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6156
e36ea7ff
VS		 6157 /* WaVSRefCountFullforceMissDisable:hsw */
6158 I915_WRITE(GEN7_FF_THREAD_MODE,
6159 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6160
4e04632e
AG		 6161 /* WaDisable_RenderCache_OperationalFlush:hsw */
6162 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6163
fe27c606
CW		 6164 /* enable HiZ Raw Stall Optimization */
6165 I915_WRITE(CACHE_MODE_0_GEN7,
6166 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6167
ecdb4eb7 6168 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6169 I915_WRITE(CACHE_MODE_1,
6170 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6171
a12c4967
VS		 6172 /*
6173 * BSpec recommends 8x4 when MSAA is used,
6174 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6175 *
6176 * Note that PS/WM thread counts depend on the WIZ hashing
6177 * disable bit, which we don't touch here, but it's good
6178 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6179 */
6180 I915_WRITE(GEN7_GT_MODE,
98533251 6181 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6182
94411593
KG		 6183 /* WaSampleCChickenBitEnable:hsw */
6184 I915_WRITE(HALF_SLICE_CHICKEN3,
6185 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6186
ecdb4eb7 6187 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6188 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6189
90a88643
PZ		 6190 /* WaRsPkgCStateDisplayPMReq:hsw */
6191 I915_WRITE(CHICKEN_PAR1_1,
6192 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6193
17a303ec 6194 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6195}
6196
1fa61106 6197static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6198{
6199 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6200 uint32_t snpcr;
6f1d69b0 6201
017636cc 6202 ilk_init_lp_watermarks(dev);
6f1d69b0 6203
231e54f6 6204 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6205
ecdb4eb7 6206 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6207 I915_WRITE(_3D_CHICKEN3,
6208 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6209
ecdb4eb7 6210 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6211 I915_WRITE(IVB_CHICKEN3,
6212 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6213 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6214
ecdb4eb7 6215 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6216 if (IS_IVB_GT1(dev))
6217 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6218 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6219
4e04632e
AG		 6220 /* WaDisable_RenderCache_OperationalFlush:ivb */
6221 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6222
ecdb4eb7 6223 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6224 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6225 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6226
ecdb4eb7 6227 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6228 I915_WRITE(GEN7_L3CNTLREG1,
6229 GEN7_WA_FOR_GEN7_L3_CONTROL);
6230 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6231 GEN7_WA_L3_CHICKEN_MODE);
6232 if (IS_IVB_GT1(dev))
6233 I915_WRITE(GEN7_ROW_CHICKEN2,
6234 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6235 else {
6236 /* must write both registers */
6237 I915_WRITE(GEN7_ROW_CHICKEN2,
6238 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6239 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6240 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6241 }
6f1d69b0 6242
ecdb4eb7 6243 /* WaForceL3Serialization:ivb */
61939d97
JB		 6244 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6245 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6246
1b80a19a 6247 /*
0f846f81 6248 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6249 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6250 */
6251 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6252 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6253
ecdb4eb7 6254 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6255 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6256 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6257 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6258
0e088b8f 6259 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6260
6261 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6262
22721343
CW		 6263 if (0) { /* causes HiZ corruption on ivb:gt1 */
6264 /* enable HiZ Raw Stall Optimization */
6265 I915_WRITE(CACHE_MODE_0_GEN7,
6266 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6267 }
116f2b6d 6268
ecdb4eb7 6269 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6270 I915_WRITE(CACHE_MODE_1,
6271 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6272
a607c1a4
VS		 6273 /*
6274 * BSpec recommends 8x4 when MSAA is used,
6275 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6276 *
6277 * Note that PS/WM thread counts depend on the WIZ hashing
6278 * disable bit, which we don't touch here, but it's good
6279 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6280 */
6281 I915_WRITE(GEN7_GT_MODE,
98533251 6282 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6283
20848223
BW		 6284 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6285 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6286 snpcr |= GEN6_MBC_SNPCR_MED;
6287 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6288
ab5c608b
BW		 6289 if (!HAS_PCH_NOP(dev))
6290 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6291
6292 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6293}
6294
c6beb13e
VS		 6295static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6296{
6297 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6298
6299 /*
6300 * Disable trickle feed and enable pnd deadline calculation
6301 */
6302 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6303 I915_WRITE(CBR1_VLV, 0);
6304}
6305
1fa61106 6306static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6307{
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6309
c6beb13e 6310 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6311
ecdb4eb7 6312 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6313 I915_WRITE(_3D_CHICKEN3,
6314 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6315
ecdb4eb7 6316 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6317 I915_WRITE(IVB_CHICKEN3,
6318 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6319 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6320
fad7d36e 6321 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6322 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6323 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6324 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6325 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6326
4e04632e
AG		 6327 /* WaDisable_RenderCache_OperationalFlush:vlv */
6328 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6329
ecdb4eb7 6330 /* WaForceL3Serialization:vlv */
61939d97
JB		 6331 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6332 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6333
ecdb4eb7 6334 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6335 I915_WRITE(GEN7_ROW_CHICKEN2,
6336 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6337
ecdb4eb7 6338 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6339 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6340 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6341 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6342
46680e0a
VS		 6343 gen7_setup_fixed_func_scheduler(dev_priv);
6344
3c0edaeb 6345 /*
0f846f81 6346 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6347 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6348 */
6349 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6350 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6351
c98f5062
AG		 6352 /* WaDisableL3Bank2xClockGate:vlv
6353 * Disabling L3 clock gating- MMIO 940c[25] = 1
6354 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6355 I915_WRITE(GEN7_UCGCTL4,
6356 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6357
afd58e79
VS		 6358 /*
6359 * BSpec says this must be set, even though
6360 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6361 */
6b26c86d
DV		 6362 I915_WRITE(CACHE_MODE_1,
6363 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6364
da2518f9
VS		 6365 /*
6366 * BSpec recommends 8x4 when MSAA is used,
6367 * however in practice 16x4 seems fastest.
6368 *
6369 * Note that PS/WM thread counts depend on the WIZ hashing
6370 * disable bit, which we don't touch here, but it's good
6371 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6372 */
6373 I915_WRITE(GEN7_GT_MODE,
6374 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6375
031994ee
VS		 6376 /*
6377 * WaIncreaseL3CreditsForVLVB0:vlv
6378 * This is the hardware default actually.
6379 */
6380 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6381
2d809570 6382 /*
ecdb4eb7 6383 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6384 * Disable clock gating on th GCFG unit to prevent a delay
6385 * in the reporting of vblank events.
6386 */
7a0d1eed 6387 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6388}
6389
a4565da8
VS		 6390static void cherryview_init_clock_gating(struct drm_device *dev)
6391{
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393
c6beb13e 6394 vlv_init_display_clock_gating(dev_priv);
dd811e70 6395
232ce337
VS		 6396 /* WaVSRefCountFullforceMissDisable:chv */
6397 /* WaDSRefCountFullforceMissDisable:chv */
6398 I915_WRITE(GEN7_FF_THREAD_MODE,
6399 I915_READ(GEN7_FF_THREAD_MODE) &
6400 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6401
6402 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6403 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6404 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6405
6406 /* WaDisableCSUnitClockGating:chv */
6407 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6408 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6409
6410 /* WaDisableSDEUnitClockGating:chv */
6411 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6412 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6413}
6414
1fa61106 6415static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6416{
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418 uint32_t dspclk_gate;
6419
6420 I915_WRITE(RENCLK_GATE_D1, 0);
6421 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6422 GS_UNIT_CLOCK_GATE_DISABLE |
6423 CL_UNIT_CLOCK_GATE_DISABLE);
6424 I915_WRITE(RAMCLK_GATE_D, 0);
6425 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6426 OVRUNIT_CLOCK_GATE_DISABLE |
6427 OVCUNIT_CLOCK_GATE_DISABLE;
6428 if (IS_GM45(dev))
6429 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6430 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6431
6432 /* WaDisableRenderCachePipelinedFlush */
6433 I915_WRITE(CACHE_MODE_0,
6434 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6435
4e04632e
AG		 6436 /* WaDisable_RenderCache_OperationalFlush:g4x */
6437 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6438
0e088b8f 6439 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6440}
6441
1fa61106 6442static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6443{
6444 struct drm_i915_private *dev_priv = dev->dev_private;
6445
6446 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6447 I915_WRITE(RENCLK_GATE_D2, 0);
6448 I915_WRITE(DSPCLK_GATE_D, 0);
6449 I915_WRITE(RAMCLK_GATE_D, 0);
6450 I915_WRITE16(DEUC, 0);
20f94967
VS		 6451 I915_WRITE(MI_ARB_STATE,
6452 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6453
6454 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6455 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6456}
6457
1fa61106 6458static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6459{
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461
6462 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6463 I965_RCC_CLOCK_GATE_DISABLE |
6464 I965_RCPB_CLOCK_GATE_DISABLE |
6465 I965_ISC_CLOCK_GATE_DISABLE |
6466 I965_FBC_CLOCK_GATE_DISABLE);
6467 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6468 I915_WRITE(MI_ARB_STATE,
6469 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6470
6471 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6472 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6473}
6474
1fa61106 6475static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6476{
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 u32 dstate = I915_READ(D_STATE);
6479
6480 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6481 DSTATE_DOT_CLOCK_GATING;
6482 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6483
6484 if (IS_PINEVIEW(dev))
6485 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6486
6487 /* IIR "flip pending" means done if this bit is set */
6488 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6489
6490 /* interrupts should cause a wake up from C3 */
3299254f 6491 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6492
6493 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6494 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6495
6496 I915_WRITE(MI_ARB_STATE,
6497 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6498}
6499
1fa61106 6500static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6501{
6502 struct drm_i915_private *dev_priv = dev->dev_private;
6503
6504 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6505
6506 /* interrupts should cause a wake up from C3 */
6507 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6508 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6509
6510 I915_WRITE(MEM_MODE,
6511 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6512}
6513
1fa61106 6514static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6515{
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517
6518 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6519
6520 I915_WRITE(MEM_MODE,
6521 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6522 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6523}
6524
6f1d69b0
ED		 6525void intel_init_clock_gating(struct drm_device *dev)
6526{
6527 struct drm_i915_private *dev_priv = dev->dev_private;
6528
c57e3551
DL		 6529 if (dev_priv->display.init_clock_gating)
6530 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6531}
6532
7d708ee4
ID		 6533void intel_suspend_hw(struct drm_device *dev)
6534{
6535 if (HAS_PCH_LPT(dev))
6536 lpt_suspend_hw(dev);
6537}
6538
1fa61106
ED		 6539/* Set up chip specific power management-related functions */
6540void intel_init_pm(struct drm_device *dev)
6541{
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543
7ff0ebcc 6544 intel_fbc_init(dev_priv);
1fa61106 6545
c921aba8
DV		 6546 /* For cxsr */
6547 if (IS_PINEVIEW(dev))
6548 i915_pineview_get_mem_freq(dev);
6549 else if (IS_GEN5(dev))
6550 i915_ironlake_get_mem_freq(dev);
6551
1fa61106 6552 /* For FIFO watermark updates */
f5ed50cb 6553 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6554 skl_setup_wm_latency(dev);
6555
a82abe43
ID		 6556 if (IS_BROXTON(dev))
6557 dev_priv->display.init_clock_gating =
6558 bxt_init_clock_gating;
6559 else if (IS_SKYLAKE(dev))
6560 dev_priv->display.init_clock_gating =
6561 skl_init_clock_gating;
2d41c0b5
PB		 6562 dev_priv->display.update_wm = skl_update_wm;
6563 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6564 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6565 ilk_setup_wm_latency(dev);
53615a5e 6566
bd602544
VS		 6567 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6568 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6569 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6570 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6571 dev_priv->display.update_wm = ilk_update_wm;
6572 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6573 } else {
6574 DRM_DEBUG_KMS("Failed to read display plane latency. "
6575 "Disable CxSR\n");
6576 }
6577
6578 if (IS_GEN5(dev))
1fa61106 6579 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6580 else if (IS_GEN6(dev))
1fa61106 6581 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6582 else if (IS_IVYBRIDGE(dev))
1fa61106 6583 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6584 else if (IS_HASWELL(dev))
cad2a2d7 6585 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6586 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6587 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6588 } else if (IS_CHERRYVIEW(dev)) {
ae80152d 6589 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6590 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6591 dev_priv->display.init_clock_gating =
6592 cherryview_init_clock_gating;
1fa61106
ED		 6593 } else if (IS_VALLEYVIEW(dev)) {
6594 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6595 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6596 dev_priv->display.init_clock_gating =
6597 valleyview_init_clock_gating;
1fa61106
ED		 6598 } else if (IS_PINEVIEW(dev)) {
6599 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6600 dev_priv->is_ddr3,
6601 dev_priv->fsb_freq,
6602 dev_priv->mem_freq)) {
6603 DRM_INFO("failed to find known CxSR latency "
6604 "(found ddr%s fsb freq %d, mem freq %d), "
6605 "disabling CxSR\n",
6606 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6607 dev_priv->fsb_freq, dev_priv->mem_freq);
6608 /* Disable CxSR and never update its watermark again */
5209b1f4 6609 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6610 dev_priv->display.update_wm = NULL;
6611 } else
6612 dev_priv->display.update_wm = pineview_update_wm;
6613 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6614 } else if (IS_G4X(dev)) {
6615 dev_priv->display.update_wm = g4x_update_wm;
6616 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6617 } else if (IS_GEN4(dev)) {
6618 dev_priv->display.update_wm = i965_update_wm;
6619 if (IS_CRESTLINE(dev))
6620 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6621 else if (IS_BROADWATER(dev))
6622 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6623 } else if (IS_GEN3(dev)) {
6624 dev_priv->display.update_wm = i9xx_update_wm;
6625 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6626 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6627 } else if (IS_GEN2(dev)) {
6628 if (INTEL_INFO(dev)->num_pipes == 1) {
6629 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6630 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6631 } else {
6632 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6633 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6634 }
6635
6636 if (IS_I85X(dev) || IS_I865G(dev))
6637 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6638 else
6639 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6640 } else {
6641 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6642 }
6643}
6644
151a49d0 6645int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6646{
4fc688ce 6647 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6648
6649 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6650 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6651 return -EAGAIN;
6652 }
6653
6654 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6655 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 6656 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6657
6658 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6659 500)) {
6660 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6661 return -ETIMEDOUT;
6662 }
6663
6664 *val = I915_READ(GEN6_PCODE_DATA);
6665 I915_WRITE(GEN6_PCODE_DATA, 0);
6666
6667 return 0;
6668}
6669
151a49d0 6670int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6671{
4fc688ce 6672 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6673
6674 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6675 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6676 return -EAGAIN;
6677 }
6678
6679 I915_WRITE(GEN6_PCODE_DATA, val);
6680 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6681
6682 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6683 500)) {
6684 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6685 return -ETIMEDOUT;
6686 }
6687
6688 I915_WRITE(GEN6_PCODE_DATA, 0);
6689
6690 return 0;
6691}
a0e4e199 6692
dd06f88c 6693static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6694{
dd06f88c
VS		 6695 switch (czclk_freq) {
6696 case 200:
6697 return 10;
6698 case 267:
6699 return 12;
6700 case 320:
6701 case 333:
dd06f88c 6702 return 16;
ab3fb157
VS		 6703 case 400:
6704 return 20;
855ba3be
JB		 6705 default:
6706 return -1;
6707 }
dd06f88c 6708}
855ba3be 6709
dd06f88c
VS		 6710static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6711{
6712 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6713
6714 div = vlv_gpu_freq_div(czclk_freq);
6715 if (div < 0)
6716 return div;
6717
6718 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 6719}
6720
b55dd647 6721static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6722{
dd06f88c 6723 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6724
dd06f88c
VS		 6725 mul = vlv_gpu_freq_div(czclk_freq);
6726 if (mul < 0)
6727 return mul;
855ba3be 6728
dd06f88c 6729 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 6730}
6731
b55dd647 6732static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6733{
dd06f88c 6734 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6735
dd06f88c
VS		 6736 div = vlv_gpu_freq_div(czclk_freq) / 2;
6737 if (div < 0)
6738 return div;
22b1b2f8 6739
dd06f88c 6740 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 6741}
6742
b55dd647 6743static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6744{
dd06f88c 6745 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6746
dd06f88c
VS		 6747 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6748 if (mul < 0)
6749 return mul;
22b1b2f8 6750
1c14762d 6751 /* CHV needs even values */
dd06f88c 6752 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 6753}
6754
616bc820 6755int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6756{
80b6dda4
AG		 6757 if (IS_GEN9(dev_priv->dev))
6758 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6759 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6760 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6761 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6762 return byt_gpu_freq(dev_priv, val);
6763 else
6764 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 6765}
6766
616bc820
VS		 6767int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6768{
80b6dda4
AG		 6769 if (IS_GEN9(dev_priv->dev))
6770 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6771 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6772 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6773 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6774 return byt_freq_opcode(dev_priv, val);
6775 else
6776 return val / GT_FREQUENCY_MULTIPLIER;
6777}
22b1b2f8 6778
f742a552 6779void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6780{
6781 struct drm_i915_private *dev_priv = dev->dev_private;
6782
f742a552
DV		 6783 mutex_init(&dev_priv->rps.hw_lock);
6784
907b28c5
CW		 6785 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6786 intel_gen6_powersave_work);
5d584b2e 6787
33688d95 6788 dev_priv->pm.suspended = false;
907b28c5 6789}
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