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drm/i915/bxt: add missing DSI power domain to power well 1
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
a82abe43
ID		 57static void bxt_init_clock_gating(struct drm_device *dev)
58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
a7546159
NH		 61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
32608ca2
ID		 65 /*
66 * FIXME:
868434c5 67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 68 */
32608ca2 69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 79}
80
c921aba8
DV		 81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
50227e1c 83 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
20e4d407 148 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
20e4d407 180 dev_priv->ips.c_m = 0;
c921aba8 181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 182 dev_priv->ips.c_m = 1;
c921aba8 183 } else {
20e4d407 184 dev_priv->ips.c_m = 2;
c921aba8
DV		 185 }
186}
187
b445e3b0
ED		 188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
63c62275 226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
fc1ac8de
VS		 250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
cfb41411
VS		 272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
f4998963
VS		 288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
5209b1f4 291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 292{
5209b1f4
ID		 293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
b445e3b0 295
666a4537 296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 298 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 299 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
a7a6c498 307 POSTING_READ(DSPFW3);
5209b1f4
ID		 308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 312 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
a7a6c498 317 POSTING_READ(INSTPM);
5209b1f4
ID		 318 } else {
319 return;
320 }
b445e3b0 321
5209b1f4
ID		 322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
b445e3b0
ED		 324}
325
fc1ac8de 326
b445e3b0
ED		 327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
5aef6003 341static const int pessimal_latency_ns = 5000;
b445e3b0 342
b5004720
VS		 343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
1fa61106 398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
feb56b93 414static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
1fa61106 431static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
b445e3b0
ED		 447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 461};
462static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 489};
b445e3b0 490static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 491 .fifo_size = I965_CURSOR_FIFO,
492 .max_wm = I965_CURSOR_MAX_WM,
493 .default_wm = I965_CURSOR_DFT_WM,
494 .guard_size = 2,
495 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 498 .fifo_size = I945_FIFO_SIZE,
499 .max_wm = I915_MAX_WM,
500 .default_wm = 1,
501 .guard_size = 2,
502 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 505 .fifo_size = I915_FIFO_SIZE,
506 .max_wm = I915_MAX_WM,
507 .default_wm = 1,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 510};
9d539105 511static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 512 .fifo_size = I855GM_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 517};
9d539105
VS		 518static const struct intel_watermark_params i830_bc_wm_info = {
519 .fifo_size = I855GM_FIFO_SIZE,
520 .max_wm = I915_MAX_WM/2,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I830_FIFO_LINE_SIZE,
524};
feb56b93 525static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 526 .fifo_size = I830_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532
b445e3b0
ED		 533/**
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
ac484963 537 * @cpp: bytes per pixel
b445e3b0
ED		 538 * @latency_ns: memory latency for the platform
539 *
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
544 *
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
550 */
551static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
552 const struct intel_watermark_params *wm,
ac484963 553 int fifo_size, int cpp,
b445e3b0
ED		 554 unsigned long latency_ns)
555{
556 long entries_required, wm_size;
557
558 /*
559 * Note: we need to make sure we don't overflow for various clock &
560 * latency values.
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
563 */
ac484963 564 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 565 1000;
566 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
567
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
569
570 wm_size = fifo_size - (entries_required + wm->guard_size);
571
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
573
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size > (long)wm->max_wm)
576 wm_size = wm->max_wm;
577 if (wm_size <= 0)
578 wm_size = wm->default_wm;
d6feb196
VS		 579
580 /*
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
585 * done).
586 */
587 if (wm_size <= 8)
588 wm_size = 8;
589
b445e3b0
ED		 590 return wm_size;
591}
592
593static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
594{
595 struct drm_crtc *crtc, *enabled = NULL;
596
70e1e0ec 597 for_each_crtc(dev, crtc) {
3490ea5d 598 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 599 if (enabled)
600 return NULL;
601 enabled = crtc;
602 }
603 }
604
605 return enabled;
606}
607
46ba614c 608static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 609{
46ba614c 610 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct drm_crtc *crtc;
613 const struct cxsr_latency *latency;
614 u32 reg;
615 unsigned long wm;
616
617 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
618 dev_priv->fsb_freq, dev_priv->mem_freq);
619 if (!latency) {
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 621 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 622 return;
623 }
624
625 crtc = single_enabled_crtc(dev);
626 if (crtc) {
7c5f93b0 627 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 628 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 629 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 630
631 /* Display SR */
632 wm = intel_calculate_wm(clock, &pineview_display_wm,
633 pineview_display_wm.fifo_size,
ac484963 634 cpp, latency->display_sr);
b445e3b0
ED		 635 reg = I915_READ(DSPFW1);
636 reg &= ~DSPFW_SR_MASK;
f4998963 637 reg |= FW_WM(wm, SR);
b445e3b0
ED		 638 I915_WRITE(DSPFW1, reg);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
640
641 /* cursor SR */
642 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
643 pineview_display_wm.fifo_size,
ac484963 644 cpp, latency->cursor_sr);
b445e3b0
ED		 645 reg = I915_READ(DSPFW3);
646 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 647 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 648 I915_WRITE(DSPFW3, reg);
649
650 /* Display HPLL off SR */
651 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
652 pineview_display_hplloff_wm.fifo_size,
ac484963 653 cpp, latency->display_hpll_disable);
b445e3b0
ED		 654 reg = I915_READ(DSPFW3);
655 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 656 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 657 I915_WRITE(DSPFW3, reg);
658
659 /* cursor HPLL off SR */
660 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
661 pineview_display_hplloff_wm.fifo_size,
ac484963 662 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 663 reg = I915_READ(DSPFW3);
664 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 665 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 666 I915_WRITE(DSPFW3, reg);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
668
5209b1f4 669 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 670 } else {
5209b1f4 671 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 672 }
673}
674
675static bool g4x_compute_wm0(struct drm_device *dev,
676 int plane,
677 const struct intel_watermark_params *display,
678 int display_latency_ns,
679 const struct intel_watermark_params *cursor,
680 int cursor_latency_ns,
681 int *plane_wm,
682 int *cursor_wm)
683{
684 struct drm_crtc *crtc;
4fe8590a 685 const struct drm_display_mode *adjusted_mode;
ac484963 686 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 687 int line_time_us, line_count;
688 int entries, tlb_miss;
689
690 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 691 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 692 *cursor_wm = cursor->guard_size;
693 *plane_wm = display->guard_size;
694 return false;
695 }
696
6e3c9717 697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 698 clock = adjusted_mode->crtc_clock;
fec8cba3 699 htotal = adjusted_mode->crtc_htotal;
6e3c9717 700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 701 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 702
703 /* Use the small buffer method to calculate plane watermark */
ac484963 704 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 705 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
706 if (tlb_miss > 0)
707 entries += tlb_miss;
708 entries = DIV_ROUND_UP(entries, display->cacheline_size);
709 *plane_wm = entries + display->guard_size;
710 if (*plane_wm > (int)display->max_wm)
711 *plane_wm = display->max_wm;
712
713 /* Use the large buffer method to calculate cursor watermark */
922044c9 714 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 715 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 716 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 717 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
718 if (tlb_miss > 0)
719 entries += tlb_miss;
720 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
721 *cursor_wm = entries + cursor->guard_size;
722 if (*cursor_wm > (int)cursor->max_wm)
723 *cursor_wm = (int)cursor->max_wm;
724
725 return true;
726}
727
728/*
729 * Check the wm result.
730 *
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
733 * must be disabled.
734 */
735static bool g4x_check_srwm(struct drm_device *dev,
736 int display_wm, int cursor_wm,
737 const struct intel_watermark_params *display,
738 const struct intel_watermark_params *cursor)
739{
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm, cursor_wm);
742
743 if (display_wm > display->max_wm) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm, display->max_wm);
746 return false;
747 }
748
749 if (cursor_wm > cursor->max_wm) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm, cursor->max_wm);
752 return false;
753 }
754
755 if (!(display_wm || cursor_wm)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
757 return false;
758 }
759
760 return true;
761}
762
763static bool g4x_compute_srwm(struct drm_device *dev,
764 int plane,
765 int latency_ns,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor,
768 int *display_wm, int *cursor_wm)
769{
770 struct drm_crtc *crtc;
4fe8590a 771 const struct drm_display_mode *adjusted_mode;
ac484963 772 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 773 unsigned long line_time_us;
774 int line_count, line_size;
775 int small, large;
776 int entries;
777
778 if (!latency_ns) {
779 *display_wm = *cursor_wm = 0;
780 return false;
781 }
782
783 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 784 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 785 clock = adjusted_mode->crtc_clock;
fec8cba3 786 htotal = adjusted_mode->crtc_htotal;
6e3c9717 787 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 788 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 789
922044c9 790 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 791 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 792 line_size = hdisplay * cpp;
b445e3b0
ED		 793
794 /* Use the minimum of the small and large buffer method for primary */
ac484963 795 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 796 large = line_count * line_size;
797
798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
799 *display_wm = entries + display->guard_size;
800
801 /* calculate the self-refresh watermark for display cursor */
ac484963 802 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
804 *cursor_wm = entries + cursor->guard_size;
805
806 return g4x_check_srwm(dev,
807 *display_wm, *cursor_wm,
808 display, cursor);
809}
810
15665979
VS		 811#define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
813
0018fda1
VS		 814static void vlv_write_wm_values(struct intel_crtc *crtc,
815 const struct vlv_wm_values *wm)
816{
817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
818 enum pipe pipe = crtc->pipe;
819
820 I915_WRITE(VLV_DDL(pipe),
821 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
822 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
825
ae80152d 826 I915_WRITE(DSPFW1,
15665979
VS		 827 FW_WM(wm->sr.plane, SR) |
828 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
829 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
830 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 831 I915_WRITE(DSPFW2,
15665979
VS		 832 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
833 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
834 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 835 I915_WRITE(DSPFW3,
15665979 836 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 837
838 if (IS_CHERRYVIEW(dev_priv)) {
839 I915_WRITE(DSPFW7_CHV,
15665979
VS		 840 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
841 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 842 I915_WRITE(DSPFW8_CHV,
15665979
VS		 843 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
844 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 845 I915_WRITE(DSPFW9_CHV,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
847 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 848 I915_WRITE(DSPHOWM,
15665979
VS		 849 FW_WM(wm->sr.plane >> 9, SR_HI) |
850 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
851 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
852 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
853 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
854 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
855 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
856 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
857 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
858 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 859 } else {
860 I915_WRITE(DSPFW7,
15665979
VS		 861 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
862 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 863 I915_WRITE(DSPHOWM,
15665979
VS		 864 FW_WM(wm->sr.plane >> 9, SR_HI) |
865 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
868 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
870 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 871 }
872
2cb389b7
VS		 873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4, 0);
875 I915_WRITE(DSPFW5, 0);
876 I915_WRITE(DSPFW6, 0);
877 I915_WRITE(DSPHOWM1, 0);
878
ae80152d 879 POSTING_READ(DSPFW1);
0018fda1
VS		 880}
881
15665979
VS		 882#undef FW_WM_VLV
883
6eb1a681
VS		 884enum vlv_wm_level {
885 VLV_WM_LEVEL_PM2,
886 VLV_WM_LEVEL_PM5,
887 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 888};
889
262cd2e1
VS		 890/* latency must be in 0.1us units. */
891static unsigned int vlv_wm_method2(unsigned int pixel_rate,
892 unsigned int pipe_htotal,
893 unsigned int horiz_pixels,
ac484963 894 unsigned int cpp,
262cd2e1
VS		 895 unsigned int latency)
896{
897 unsigned int ret;
898
899 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 900 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 901 ret = DIV_ROUND_UP(ret, 64);
902
903 return ret;
904}
905
906static void vlv_setup_wm_latency(struct drm_device *dev)
907{
908 struct drm_i915_private *dev_priv = dev->dev_private;
909
910 /* all latencies in usec */
911 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
912
58590c14
VS		 913 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
914
262cd2e1
VS		 915 if (IS_CHERRYVIEW(dev_priv)) {
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
917 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 918
919 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 920 }
921}
922
923static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
924 struct intel_crtc *crtc,
925 const struct intel_plane_state *state,
926 int level)
927{
928 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 929 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 930
931 if (dev_priv->wm.pri_latency[level] == 0)
932 return USHRT_MAX;
933
934 if (!state->visible)
935 return 0;
936
ac484963 937 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 938 clock = crtc->config->base.adjusted_mode.crtc_clock;
939 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
940 width = crtc->config->pipe_src_w;
941 if (WARN_ON(htotal == 0))
942 htotal = 1;
943
944 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
945 /*
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
950 */
951 wm = 63;
952 } else {
ac484963 953 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 954 dev_priv->wm.pri_latency[level] * 10);
955 }
956
957 return min_t(int, wm, USHRT_MAX);
958}
959
54f1b6e1
VS		 960static void vlv_compute_fifo(struct intel_crtc *crtc)
961{
962 struct drm_device *dev = crtc->base.dev;
963 struct vlv_wm_state *wm_state = &crtc->wm_state;
964 struct intel_plane *plane;
965 unsigned int total_rate = 0;
966 const int fifo_size = 512 - 1;
967 int fifo_extra, fifo_left = fifo_size;
968
969 for_each_intel_plane_on_crtc(dev, crtc, plane) {
970 struct intel_plane_state *state =
971 to_intel_plane_state(plane->base.state);
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
974 continue;
975
976 if (state->visible) {
977 wm_state->num_active_planes++;
978 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
979 }
980 }
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985 unsigned int rate;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 plane->wm.fifo_size = 63;
989 continue;
990 }
991
992 if (!state->visible) {
993 plane->wm.fifo_size = 0;
994 continue;
995 }
996
997 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 plane->wm.fifo_size = fifo_size * rate / total_rate;
999 fifo_left -= plane->wm.fifo_size;
1000 }
1001
1002 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 int plane_extra;
1007
1008 if (fifo_left == 0)
1009 break;
1010
1011 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012 continue;
1013
1014 /* give it all to the first plane if none are active */
1015 if (plane->wm.fifo_size == 0 &&
1016 wm_state->num_active_planes)
1017 continue;
1018
1019 plane_extra = min(fifo_extra, fifo_left);
1020 plane->wm.fifo_size += plane_extra;
1021 fifo_left -= plane_extra;
1022 }
1023
1024 WARN_ON(fifo_left != 0);
1025}
1026
262cd2e1
VS		 1027static void vlv_invert_wms(struct intel_crtc *crtc)
1028{
1029 struct vlv_wm_state *wm_state = &crtc->wm_state;
1030 int level;
1031
1032 for (level = 0; level < wm_state->num_levels; level++) {
1033 struct drm_device *dev = crtc->base.dev;
1034 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035 struct intel_plane *plane;
1036
1037 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041 switch (plane->base.type) {
1042 int sprite;
1043 case DRM_PLANE_TYPE_CURSOR:
1044 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045 wm_state->wm[level].cursor;
1046 break;
1047 case DRM_PLANE_TYPE_PRIMARY:
1048 wm_state->wm[level].primary = plane->wm.fifo_size -
1049 wm_state->wm[level].primary;
1050 break;
1051 case DRM_PLANE_TYPE_OVERLAY:
1052 sprite = plane->plane;
1053 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054 wm_state->wm[level].sprite[sprite];
1055 break;
1056 }
1057 }
1058 }
1059}
1060
26e1fe4f 1061static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1062{
1063 struct drm_device *dev = crtc->base.dev;
1064 struct vlv_wm_state *wm_state = &crtc->wm_state;
1065 struct intel_plane *plane;
1066 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067 int level;
1068
1069 memset(wm_state, 0, sizeof(*wm_state));
1070
852eb00d 1071 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1072 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1073
1074 wm_state->num_active_planes = 0;
262cd2e1 1075
54f1b6e1 1076 vlv_compute_fifo(crtc);
262cd2e1
VS		 1077
1078 if (wm_state->num_active_planes != 1)
1079 wm_state->cxsr = false;
1080
1081 if (wm_state->cxsr) {
1082 for (level = 0; level < wm_state->num_levels; level++) {
1083 wm_state->sr[level].plane = sr_fifo_size;
1084 wm_state->sr[level].cursor = 63;
1085 }
1086 }
1087
1088 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089 struct intel_plane_state *state =
1090 to_intel_plane_state(plane->base.state);
1091
1092 if (!state->visible)
1093 continue;
1094
1095 /* normal watermarks */
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100 /* hack */
1101 if (WARN_ON(level == 0 && wm > max_wm))
1102 wm = max_wm;
1103
1104 if (wm > plane->wm.fifo_size)
1105 break;
1106
1107 switch (plane->base.type) {
1108 int sprite;
1109 case DRM_PLANE_TYPE_CURSOR:
1110 wm_state->wm[level].cursor = wm;
1111 break;
1112 case DRM_PLANE_TYPE_PRIMARY:
1113 wm_state->wm[level].primary = wm;
1114 break;
1115 case DRM_PLANE_TYPE_OVERLAY:
1116 sprite = plane->plane;
1117 wm_state->wm[level].sprite[sprite] = wm;
1118 break;
1119 }
1120 }
1121
1122 wm_state->num_levels = level;
1123
1124 if (!wm_state->cxsr)
1125 continue;
1126
1127 /* maxfifo watermarks */
1128 switch (plane->base.type) {
1129 int sprite, level;
1130 case DRM_PLANE_TYPE_CURSOR:
1131 for (level = 0; level < wm_state->num_levels; level++)
1132 wm_state->sr[level].cursor =
5a37ed0a 1133 wm_state->wm[level].cursor;
262cd2e1
VS		 1134 break;
1135 case DRM_PLANE_TYPE_PRIMARY:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].plane =
1138 min(wm_state->sr[level].plane,
1139 wm_state->wm[level].primary);
1140 break;
1141 case DRM_PLANE_TYPE_OVERLAY:
1142 sprite = plane->plane;
1143 for (level = 0; level < wm_state->num_levels; level++)
1144 wm_state->sr[level].plane =
1145 min(wm_state->sr[level].plane,
1146 wm_state->wm[level].sprite[sprite]);
1147 break;
1148 }
1149 }
1150
1151 /* clear any (partially) filled invalid levels */
58590c14 1152 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1153 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155 }
1156
1157 vlv_invert_wms(crtc);
1158}
1159
54f1b6e1
VS		 1160#define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164{
1165 struct drm_device *dev = crtc->base.dev;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 struct intel_plane *plane;
1168 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172 WARN_ON(plane->wm.fifo_size != 63);
1173 continue;
1174 }
1175
1176 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177 sprite0_start = plane->wm.fifo_size;
1178 else if (plane->plane == 0)
1179 sprite1_start = sprite0_start + plane->wm.fifo_size;
1180 else
1181 fifo_size = sprite1_start + plane->wm.fifo_size;
1182 }
1183
1184 WARN_ON(fifo_size != 512 - 1);
1185
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc->pipe), sprite0_start,
1188 sprite1_start, fifo_size);
1189
1190 switch (crtc->pipe) {
1191 uint32_t dsparb, dsparb2, dsparb3;
1192 case PIPE_A:
1193 dsparb = I915_READ(DSPARB);
1194 dsparb2 = I915_READ(DSPARB2);
1195
1196 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197 VLV_FIFO(SPRITEB, 0xff));
1198 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199 VLV_FIFO(SPRITEB, sprite1_start));
1200
1201 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202 VLV_FIFO(SPRITEB_HI, 0x1));
1203 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206 I915_WRITE(DSPARB, dsparb);
1207 I915_WRITE(DSPARB2, dsparb2);
1208 break;
1209 case PIPE_B:
1210 dsparb = I915_READ(DSPARB);
1211 dsparb2 = I915_READ(DSPARB2);
1212
1213 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214 VLV_FIFO(SPRITED, 0xff));
1215 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216 VLV_FIFO(SPRITED, sprite1_start));
1217
1218 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219 VLV_FIFO(SPRITED_HI, 0xff));
1220 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223 I915_WRITE(DSPARB, dsparb);
1224 I915_WRITE(DSPARB2, dsparb2);
1225 break;
1226 case PIPE_C:
1227 dsparb3 = I915_READ(DSPARB3);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231 VLV_FIFO(SPRITEF, 0xff));
1232 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233 VLV_FIFO(SPRITEF, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236 VLV_FIFO(SPRITEF_HI, 0xff));
1237 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB3, dsparb3);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 default:
1244 break;
1245 }
1246}
1247
1248#undef VLV_FIFO
1249
262cd2e1
VS		 1250static void vlv_merge_wm(struct drm_device *dev,
1251 struct vlv_wm_values *wm)
1252{
1253 struct intel_crtc *crtc;
1254 int num_active_crtcs = 0;
1255
58590c14 1256 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1257 wm->cxsr = true;
1258
1259 for_each_intel_crtc(dev, crtc) {
1260 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262 if (!crtc->active)
1263 continue;
1264
1265 if (!wm_state->cxsr)
1266 wm->cxsr = false;
1267
1268 num_active_crtcs++;
1269 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270 }
1271
1272 if (num_active_crtcs != 1)
1273 wm->cxsr = false;
1274
6f9c784b
VS		 1275 if (num_active_crtcs > 1)
1276 wm->level = VLV_WM_LEVEL_PM2;
1277
262cd2e1
VS		 1278 for_each_intel_crtc(dev, crtc) {
1279 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280 enum pipe pipe = crtc->pipe;
1281
1282 if (!crtc->active)
1283 continue;
1284
1285 wm->pipe[pipe] = wm_state->wm[wm->level];
1286 if (wm->cxsr)
1287 wm->sr = wm_state->sr[wm->level];
1288
1289 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293 }
1294}
1295
1296static void vlv_update_wm(struct drm_crtc *crtc)
1297{
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301 enum pipe pipe = intel_crtc->pipe;
1302 struct vlv_wm_values wm = {};
1303
26e1fe4f 1304 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1305 vlv_merge_wm(dev, &wm);
1306
54f1b6e1
VS		 1307 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1310 return;
54f1b6e1 1311 }
262cd2e1
VS		 1312
1313 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315 chv_set_memory_dvfs(dev_priv, false);
1316
1317 if (wm.level < VLV_WM_LEVEL_PM5 &&
1318 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319 chv_set_memory_pm5(dev_priv, false);
1320
852eb00d 1321 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1322 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1323
54f1b6e1
VS		 1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc);
1326
262cd2e1
VS		 1327 vlv_write_wm_values(intel_crtc, &wm);
1328
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
852eb00d 1335 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1337
1338 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340 chv_set_memory_pm5(dev_priv, true);
1341
1342 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, true);
1345
1346 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1347}
1348
ae80152d
VS		 1349#define single_plane_enabled(mask) is_power_of_2(mask)
1350
46ba614c 1351static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1352{
46ba614c 1353 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
9858425c 1359 bool cxsr_enabled;
b445e3b0 1360
51cea1f4 1361 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1362 &g4x_wm_info, pessimal_latency_ns,
1363 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1364 &planea_wm, &cursora_wm))
51cea1f4 1365 enabled |= 1 << PIPE_A;
b445e3b0 1366
51cea1f4 1367 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1368 &g4x_wm_info, pessimal_latency_ns,
1369 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1370 &planeb_wm, &cursorb_wm))
51cea1f4 1371 enabled |= 1 << PIPE_B;
b445e3b0 1372
b445e3b0
ED		 1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
52bd02d8 1378 &plane_sr, &cursor_sr)) {
9858425c 1379 cxsr_enabled = true;
52bd02d8 1380 } else {
9858425c 1381 cxsr_enabled = false;
5209b1f4 1382 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1383 plane_sr = cursor_sr = 0;
1384 }
b445e3b0 1385
a5043453
VS		 1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1388 planea_wm, cursora_wm,
1389 planeb_wm, cursorb_wm,
1390 plane_sr, cursor_sr);
1391
1392 I915_WRITE(DSPFW1,
f4998963
VS		 1393 FW_WM(plane_sr, SR) |
1394 FW_WM(cursorb_wm, CURSORB) |
1395 FW_WM(planeb_wm, PLANEB) |
1396 FW_WM(planea_wm, PLANEA));
b445e3b0 1397 I915_WRITE(DSPFW2,
8c919b28 1398 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1399 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1400 /* HPLL off in SR has some issues on G4x... disable it */
1401 I915_WRITE(DSPFW3,
8c919b28 1402 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1403 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1407}
1408
46ba614c 1409static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1410{
46ba614c 1411 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc;
1414 int srwm = 1;
1415 int cursor_sr = 16;
9858425c 1416 bool cxsr_enabled;
b445e3b0
ED		 1417
1418 /* Calc sr entries for one plane configs */
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc) {
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns = 12000;
124abe07 1423 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1424 int clock = adjusted_mode->crtc_clock;
fec8cba3 1425 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1426 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1427 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1428 unsigned long line_time_us;
1429 int entries;
1430
922044c9 1431 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1432
1433 /* Use ns/us then divide to preserve precision */
1434 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1435 cpp * hdisplay;
b445e3b0
ED		 1436 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437 srwm = I965_FIFO_SIZE - entries;
1438 if (srwm < 0)
1439 srwm = 1;
1440 srwm &= 0x1ff;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442 entries, srwm);
1443
1444 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1445 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1446 entries = DIV_ROUND_UP(entries,
1447 i965_cursor_wm_info.cacheline_size);
1448 cursor_sr = i965_cursor_wm_info.fifo_size -
1449 (entries + i965_cursor_wm_info.guard_size);
1450
1451 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452 cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm, cursor_sr);
1456
9858425c 1457 cxsr_enabled = true;
b445e3b0 1458 } else {
9858425c 1459 cxsr_enabled = false;
b445e3b0 1460 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1461 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1462 }
1463
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465 srwm);
1466
1467 /* 965 has limitations... */
f4998963
VS		 1468 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469 FW_WM(8, CURSORB) |
1470 FW_WM(8, PLANEB) |
1471 FW_WM(8, PLANEA));
1472 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473 FW_WM(8, PLANEC_OLD));
b445e3b0 1474 /* update cursor SR watermark */
f4998963 1475 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1479}
1480
f4998963
VS		 1481#undef FW_WM
1482
46ba614c 1483static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1484{
46ba614c 1485 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 const struct intel_watermark_params *wm_info;
1488 uint32_t fwater_lo;
1489 uint32_t fwater_hi;
1490 int cwm, srwm = 1;
1491 int fifo_size;
1492 int planea_wm, planeb_wm;
1493 struct drm_crtc *crtc, *enabled = NULL;
1494
1495 if (IS_I945GM(dev))
1496 wm_info = &i945_wm_info;
1497 else if (!IS_GEN2(dev))
1498 wm_info = &i915_wm_info;
1499 else
9d539105 1500 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1504 if (intel_crtc_active(crtc)) {
241bfc38 1505 const struct drm_display_mode *adjusted_mode;
ac484963 1506 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1507 if (IS_GEN2(dev))
1508 cpp = 4;
1509
6e3c9717 1510 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1511 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1512 wm_info, fifo_size, cpp,
5aef6003 1513 pessimal_latency_ns);
b445e3b0 1514 enabled = crtc;
9d539105 1515 } else {
b445e3b0 1516 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1517 if (planea_wm > (long)wm_info->max_wm)
1518 planea_wm = wm_info->max_wm;
1519 }
1520
1521 if (IS_GEN2(dev))
1522 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1526 if (intel_crtc_active(crtc)) {
241bfc38 1527 const struct drm_display_mode *adjusted_mode;
ac484963 1528 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
6e3c9717 1532 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1534 wm_info, fifo_size, cpp,
5aef6003 1535 pessimal_latency_ns);
b445e3b0
ED		 1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
9d539105 1540 } else {
b445e3b0 1541 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1542 if (planeb_wm > (long)wm_info->max_wm)
1543 planeb_wm = wm_info->max_wm;
1544 }
b445e3b0
ED		 1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d 1548 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1549 struct drm_i915_gem_object *obj;
2ab1bc9d 1550
59bea882 1551 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1552
1553 /* self-refresh seems busted with untiled */
2ff8fde1 1554 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1564 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
124abe07 1570 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1571 int clock = adjusted_mode->crtc_clock;
fec8cba3 1572 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1573 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1574 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1575 unsigned long line_time_us;
1576 int entries;
1577
922044c9 1578 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1579
1580 /* Use ns/us then divide to preserve precision */
1581 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1582 cpp * hdisplay;
b445e3b0
ED		 1583 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585 srwm = wm_info->fifo_size - entries;
1586 if (srwm < 0)
1587 srwm = 1;
1588
1589 if (IS_I945G(dev) || IS_I945GM(dev))
1590 I915_WRITE(FW_BLC_SELF,
1591 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594 }
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm, planeb_wm, cwm, srwm);
1598
1599 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600 fwater_hi = (cwm & 0x1f);
1601
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604 fwater_hi = fwater_hi | (1 << 8);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 I915_WRITE(FW_BLC2, fwater_hi);
1608
5209b1f4
ID		 1609 if (enabled)
1610 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1611}
1612
feb56b93 1613static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1614{
46ba614c 1615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
241bfc38 1618 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
6e3c9717 1626 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1628 &i845_wm_info,
b445e3b0 1629 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1630 4, pessimal_latency_ns);
b445e3b0
ED		 1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637}
1638
8cfb3407 1639uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1640{
fd4daa9c 1641 uint32_t pixel_rate;
801bcfff 1642
8cfb3407 1643 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1644
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1647
8cfb3407 1648 if (pipe_config->pch_pfit.enabled) {
801bcfff 1649 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1650 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652 pipe_w = pipe_config->pipe_src_w;
1653 pipe_h = pipe_config->pipe_src_h;
801bcfff 1654
801bcfff
PZ		 1655 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656 pfit_h = pfit_size & 0xFFFF;
1657 if (pipe_w < pfit_w)
1658 pipe_w = pfit_w;
1659 if (pipe_h < pfit_h)
1660 pipe_h = pfit_h;
1661
15126882
MR		 1662 if (WARN_ON(!pfit_w || !pfit_h))
1663 return pixel_rate;
1664
801bcfff
PZ		 1665 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666 pfit_w * pfit_h);
1667 }
1668
1669 return pixel_rate;
1670}
1671
37126462 1672/* latency must be in 0.1us units. */
ac484963 1673static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1674{
1675 uint64_t ret;
1676
3312ba65
VS		 1677 if (WARN(latency == 0, "Latency value missing\n"))
1678 return UINT_MAX;
1679
ac484963 1680 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1681 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683 return ret;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
23297044 1687static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1688 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1689 uint32_t latency)
1690{
1691 uint32_t ret;
1692
3312ba65
VS		 1693 if (WARN(latency == 0, "Latency value missing\n"))
1694 return UINT_MAX;
15126882
MR		 1695 if (WARN_ON(!pipe_htotal))
1696 return UINT_MAX;
3312ba65 1697
801bcfff 1698 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1699 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1700 ret = DIV_ROUND_UP(ret, 64) + 2;
1701 return ret;
1702}
1703
23297044 1704static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1705 uint8_t cpp)
cca32e9a 1706{
15126882
MR		 1707 /*
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1712 */
ac484963 1713 if (WARN_ON(!cpp))
15126882
MR		 1714 return 0;
1715 if (WARN_ON(!horiz_pixels))
1716 return 0;
1717
ac484963 1718 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1719}
1720
820c1980 1721struct ilk_wm_maximums {
cca32e9a
PZ		 1722 uint16_t pri;
1723 uint16_t spr;
1724 uint16_t cur;
1725 uint16_t fbc;
1726};
1727
37126462
VS		 1728/*
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1731 */
7221fc33 1732static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1733 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1734 uint32_t mem_value,
1735 bool is_lp)
801bcfff 1736{
ac484963
VS		 1737 int cpp = pstate->base.fb ?
1738 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1739 uint32_t method1, method2;
1740
7221fc33 1741 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1742 return 0;
1743
ac484963 1744 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1745
1746 if (!is_lp)
1747 return method1;
1748
7221fc33
MR		 1749 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1751 drm_rect_width(&pstate->dst),
ac484963 1752 cpp, mem_value);
cca32e9a
PZ		 1753
1754 return min(method1, method2);
801bcfff
PZ		 1755}
1756
37126462
VS		 1757/*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
7221fc33 1761static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1762 const struct intel_plane_state *pstate,
801bcfff
PZ		 1763 uint32_t mem_value)
1764{
ac484963
VS		 1765 int cpp = pstate->base.fb ?
1766 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1767 uint32_t method1, method2;
1768
7221fc33 1769 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1770 return 0;
1771
ac484963 1772 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1775 drm_rect_width(&pstate->dst),
ac484963 1776 cpp, mem_value);
801bcfff
PZ		 1777 return min(method1, method2);
1778}
1779
37126462
VS		 1780/*
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1783 */
7221fc33 1784static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1785 const struct intel_plane_state *pstate,
801bcfff
PZ		 1786 uint32_t mem_value)
1787{
b2435692
MR		 1788 /*
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1792 */
1793 int cpp = 4;
1794 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1795
b2435692 1796 if (!cstate->base.active)
801bcfff
PZ		 1797 return 0;
1798
7221fc33
MR		 1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1801 width, cpp, mem_value);
801bcfff
PZ		 1802}
1803
cca32e9a 1804/* Only for WM_LP. */
7221fc33 1805static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1806 const struct intel_plane_state *pstate,
1fda9882 1807 uint32_t pri_val)
cca32e9a 1808{
ac484963
VS		 1809 int cpp = pstate->base.fb ?
1810 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1811
7221fc33 1812 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1813 return 0;
1814
ac484963 1815 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1816}
1817
158ae64f
VS		 1818static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819{
416f4727
VS		 1820 if (INTEL_INFO(dev)->gen >= 8)
1821 return 3072;
1822 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1823 return 768;
1824 else
1825 return 512;
1826}
1827
4e975081
VS		 1828static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829 int level, bool is_sprite)
1830{
1831 if (INTEL_INFO(dev)->gen >= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level == 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev)->gen >= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level == 0 ? 127 : 1023;
1837 else if (!is_sprite)
1838 /* ILK/SNB primary plane watermarks */
1839 return level == 0 ? 127 : 511;
1840 else
1841 /* ILK/SNB sprite plane watermarks */
1842 return level == 0 ? 63 : 255;
1843}
1844
1845static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846 int level)
1847{
1848 if (INTEL_INFO(dev)->gen >= 7)
1849 return level == 0 ? 63 : 255;
1850 else
1851 return level == 0 ? 31 : 63;
1852}
1853
1854static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855{
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 return 31;
1858 else
1859 return 15;
1860}
1861
158ae64f
VS		 1862/* Calculate the maximum primary/sprite plane watermark */
1863static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 int level,
240264f4 1865 const struct intel_wm_config *config,
158ae64f
VS		 1866 enum intel_ddb_partitioning ddb_partitioning,
1867 bool is_sprite)
1868{
1869 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1870
1871 /* if sprites aren't enabled, sprites get nothing */
240264f4 1872 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1873 return 0;
1874
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1876 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1877 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879 /*
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1883 */
1884 if (INTEL_INFO(dev)->gen <= 6)
1885 fifo_size /= 2;
1886 }
1887
240264f4 1888 if (config->sprites_enabled) {
158ae64f
VS		 1889 /* level 0 is always calculated with 1:1 split */
1890 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891 if (is_sprite)
1892 fifo_size *= 5;
1893 fifo_size /= 6;
1894 } else {
1895 fifo_size /= 2;
1896 }
1897 }
1898
1899 /* clamp to max that the registers can hold */
4e975081 1900 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1901}
1902
1903/* Calculate the maximum cursor plane watermark */
1904static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1905 int level,
1906 const struct intel_wm_config *config)
158ae64f
VS		 1907{
1908 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1909 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1910 return 64;
1911
1912 /* otherwise just report max that registers can hold */
4e975081 1913 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1914}
1915
d34ff9c6 1916static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1917 int level,
1918 const struct intel_wm_config *config,
1919 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1920 struct ilk_wm_maximums *max)
158ae64f 1921{
240264f4
VS		 1922 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1925 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1926}
1927
a3cb4048
VS		 1928static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 int level,
1930 struct ilk_wm_maximums *max)
1931{
1932 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934 max->cur = ilk_cursor_wm_reg_max(dev, level);
1935 max->fbc = ilk_fbc_wm_reg_max(dev);
1936}
1937
d9395655 1938static bool ilk_validate_wm_level(int level,
820c1980 1939 const struct ilk_wm_maximums *max,
d9395655 1940 struct intel_wm_level *result)
a9786a11
VS		 1941{
1942 bool ret;
1943
1944 /* already determined to be invalid? */
1945 if (!result->enable)
1946 return false;
1947
1948 result->enable = result->pri_val <= max->pri &&
1949 result->spr_val <= max->spr &&
1950 result->cur_val <= max->cur;
1951
1952 ret = result->enable;
1953
1954 /*
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1957 * are exceeded...
1958 */
1959 if (level == 0 && !result->enable) {
1960 if (result->pri_val > max->pri)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level, result->pri_val, max->pri);
1963 if (result->spr_val > max->spr)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level, result->spr_val, max->spr);
1966 if (result->cur_val > max->cur)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level, result->cur_val, max->cur);
1969
1970 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973 result->enable = true;
1974 }
1975
a9786a11
VS		 1976 return ret;
1977}
1978
d34ff9c6 1979static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1980 const struct intel_crtc *intel_crtc,
6f5ddd17 1981 int level,
7221fc33 1982 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1983 struct intel_plane_state *pristate,
1984 struct intel_plane_state *sprstate,
1985 struct intel_plane_state *curstate,
1fd527cc 1986 struct intel_wm_level *result)
6f5ddd17
VS		 1987{
1988 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992 /* WM1+ latency values stored in 0.5us units */
1993 if (level > 0) {
1994 pri_latency *= 5;
1995 spr_latency *= 5;
1996 cur_latency *= 5;
1997 }
1998
e3bddded
ML		 1999 if (pristate) {
2000 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001 pri_latency, level);
2002 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003 }
2004
2005 if (sprstate)
2006 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008 if (curstate)
2009 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
6f5ddd17
VS		 2011 result->enable = true;
2012}
2013
801bcfff 2014static uint32_t
ee91a159
MR		 2015hsw_compute_linetime_wm(struct drm_device *dev,
2016 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2017{
2018 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2019 const struct drm_display_mode *adjusted_mode =
2020 &cstate->base.adjusted_mode;
85a02deb 2021 u32 linetime, ips_linetime;
1f8eeabf 2022
ee91a159
MR		 2023 if (!cstate->base.active)
2024 return 0;
2025 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026 return 0;
2027 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2028 return 0;
1011d8c4 2029
1f8eeabf
ED		 2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2032 * */
124abe07
VS		 2033 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034 adjusted_mode->crtc_clock);
2035 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2036 dev_priv->cdclk_freq);
1f8eeabf 2037
801bcfff
PZ		 2038 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2040}
2041
2af30a5c 2042static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2043{
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045
2af30a5c
PB		 2046 if (IS_GEN9(dev)) {
2047 uint32_t val;
4f947386 2048 int ret, i;
367294be 2049 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2050
2051 /* read the first set of memory latencies[0:3] */
2052 val = 0; /* data0 to be programmed to 0 for first set */
2053 mutex_lock(&dev_priv->rps.hw_lock);
2054 ret = sandybridge_pcode_read(dev_priv,
2055 GEN9_PCODE_READ_MEM_LATENCY,
2056 &val);
2057 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059 if (ret) {
2060 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061 return;
2062 }
2063
2064 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072 /* read the second set of memory latencies[4:7] */
2073 val = 1; /* data0 to be programmed to 1 for second set */
2074 mutex_lock(&dev_priv->rps.hw_lock);
2075 ret = sandybridge_pcode_read(dev_priv,
2076 GEN9_PCODE_READ_MEM_LATENCY,
2077 &val);
2078 mutex_unlock(&dev_priv->rps.hw_lock);
2079 if (ret) {
2080 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081 return;
2082 }
2083
2084 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
367294be 2092 /*
6f97235b
DL		 2093 * WaWmMemoryReadLatency:skl
2094 *
367294be
VK		 2095 * punit doesn't take into account the read latency so we need
2096 * to add 2us to the various latency levels we retrieve from
2097 * the punit.
2098 * - W0 is a bit special in that it's the only level that
2099 * can't be disabled if we want to have display working, so
2100 * we always add 2us there.
2101 * - For levels >=1, punit returns 0us latency when they are
2102 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2103 *
2104 * Additionally, if a level n (n > 1) has a 0us latency, all
2105 * levels m (m >= n) need to be disabled. We make sure to
2106 * sanitize the values out of the punit to satisfy this
2107 * requirement.
367294be
VK		 2108 */
2109 wm[0] += 2;
2110 for (level = 1; level <= max_level; level++)
2111 if (wm[level] != 0)
2112 wm[level] += 2;
4f947386
VK		 2113 else {
2114 for (i = level + 1; i <= max_level; i++)
2115 wm[i] = 0;
367294be 2116
4f947386
VK		 2117 break;
2118 }
2af30a5c 2119 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2120 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122 wm[0] = (sskpd >> 56) & 0xFF;
2123 if (wm[0] == 0)
2124 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2125 wm[1] = (sskpd >> 4) & 0xFF;
2126 wm[2] = (sskpd >> 12) & 0xFF;
2127 wm[3] = (sskpd >> 20) & 0x1FF;
2128 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2129 } else if (INTEL_INFO(dev)->gen >= 6) {
2130 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2136 } else if (INTEL_INFO(dev)->gen >= 5) {
2137 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139 /* ILK primary LP0 latency is 700 ns */
2140 wm[0] = 7;
2141 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2143 }
2144}
2145
53615a5e
VS		 2146static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147{
2148 /* ILK sprite LP0 latency is 1300 ns */
2149 if (INTEL_INFO(dev)->gen == 5)
2150 wm[0] = 13;
2151}
2152
2153static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154{
2155 /* ILK cursor LP0 latency is 1300 ns */
2156 if (INTEL_INFO(dev)->gen == 5)
2157 wm[0] = 13;
2158
2159 /* WaDoubleCursorLP3Latency:ivb */
2160 if (IS_IVYBRIDGE(dev))
2161 wm[3] *= 2;
2162}
2163
546c81fd 2164int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2165{
26ec971e 2166 /* how many WM levels are we expecting */
b6e742f6 2167 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2168 return 7;
2169 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2170 return 4;
26ec971e 2171 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2172 return 3;
26ec971e 2173 else
ad0d6dc4
VS		 2174 return 2;
2175}
7526ed79 2176
ad0d6dc4
VS		 2177static void intel_print_wm_latency(struct drm_device *dev,
2178 const char *name,
2af30a5c 2179 const uint16_t wm[8])
ad0d6dc4
VS		 2180{
2181 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2182
2183 for (level = 0; level <= max_level; level++) {
2184 unsigned int latency = wm[level];
2185
2186 if (latency == 0) {
2187 DRM_ERROR("%s WM%d latency not provided\n",
2188 name, level);
2189 continue;
2190 }
2191
2af30a5c
PB		 2192 /*
2193 * - latencies are in us on gen9.
2194 * - before then, WM1+ latency values are in 0.5us units
2195 */
2196 if (IS_GEN9(dev))
2197 latency *= 10;
2198 else if (level > 0)
26ec971e
VS		 2199 latency *= 5;
2200
2201 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202 name, level, wm[level],
2203 latency / 10, latency % 10);
2204 }
2205}
2206
e95a2f75
VS		 2207static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208 uint16_t wm[5], uint16_t min)
2209{
2210 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212 if (wm[0] >= min)
2213 return false;
2214
2215 wm[0] = max(wm[0], min);
2216 for (level = 1; level <= max_level; level++)
2217 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219 return true;
2220}
2221
2222static void snb_wm_latency_quirk(struct drm_device *dev)
2223{
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 bool changed;
2226
2227 /*
2228 * The BIOS provided WM memory latency values are often
2229 * inadequate for high resolution displays. Adjust them.
2230 */
2231 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235 if (!changed)
2236 return;
2237
2238 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242}
2243
fa50ad61 2244static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2245{
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251 sizeof(dev_priv->wm.pri_latency));
2252 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254
2255 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2257
2258 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2261
2262 if (IS_GEN6(dev))
2263 snb_wm_latency_quirk(dev);
53615a5e
VS		 2264}
2265
2af30a5c
PB		 2266static void skl_setup_wm_latency(struct drm_device *dev)
2267{
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272}
2273
ed4a6a7c
MR		 2274static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275 struct intel_pipe_wm *pipe_wm)
2276{
2277 /* LP0 watermark maximums depend on this pipe alone */
2278 const struct intel_wm_config config = {
2279 .num_pipes_active = 1,
2280 .sprites_enabled = pipe_wm->sprites_enabled,
2281 .sprites_scaled = pipe_wm->sprites_scaled,
2282 };
2283 struct ilk_wm_maximums max;
2284
2285 /* LP0 watermarks always use 1/2 DDB partitioning */
2286 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288 /* At least LP0 must be valid */
2289 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291 return false;
2292 }
2293
2294 return true;
2295}
2296
0b2ae6d7 2297/* Compute new watermarks for the pipe */
e3bddded 2298static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2299{
e3bddded
ML		 2300 struct drm_atomic_state *state = cstate->base.state;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2302 struct intel_pipe_wm *pipe_wm;
e3bddded 2303 struct drm_device *dev = state->dev;
d34ff9c6 2304 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2305 struct intel_plane *intel_plane;
86c8bbbe 2306 struct intel_plane_state *pristate = NULL;
43d59eda 2307 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2308 struct intel_plane_state *curstate = NULL;
d81f04c5 2309 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2310 struct ilk_wm_maximums max;
0b2ae6d7 2311
86c8bbbe
MR		 2312 pipe_wm = &cstate->wm.optimal.ilk;
2313
43d59eda 2314 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2315 struct intel_plane_state *ps;
2316
2317 ps = intel_atomic_get_existing_plane_state(state,
2318 intel_plane);
2319 if (!ps)
2320 continue;
86c8bbbe
MR		 2321
2322 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2323 pristate = ps;
86c8bbbe 2324 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2325 sprstate = ps;
86c8bbbe 2326 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2327 curstate = ps;
43d59eda
MR		 2328 }
2329
ed4a6a7c 2330 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2331 if (sprstate) {
2332 pipe_wm->sprites_enabled = sprstate->visible;
2333 pipe_wm->sprites_scaled = sprstate->visible &&
2334 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336 }
2337
43d59eda 2338
d81f04c5
ML		 2339 usable_level = max_level;
2340
7b39a0b7 2341 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2342 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2343 usable_level = 1;
7b39a0b7
VS		 2344
2345 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2346 if (pipe_wm->sprites_scaled)
d81f04c5 2347 usable_level = 0;
7b39a0b7 2348
86c8bbbe
MR		 2349 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2350 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2351
a42a5719 2352 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2353 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2354
ed4a6a7c 2355 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2356 return -EINVAL;
a3cb4048
VS		 2357
2358 ilk_compute_wm_reg_maximums(dev, 1, &max);
2359
2360 for (level = 1; level <= max_level; level++) {
d81f04c5 2361 struct intel_wm_level *wm = &pipe_wm->wm[level];
a3cb4048 2362
86c8bbbe 2363 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2364 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2365
2366 /*
2367 * Disable any watermark level that exceeds the
2368 * register maximums since such watermarks are
2369 * always invalid.
2370 */
d81f04c5
ML		 2371 if (level > usable_level) {
2372 wm->enable = false;
2373 } else if (!ilk_validate_wm_level(level, &max, wm)) {
2374 wm->enable = false;
2375 usable_level = level;
2376 }
a3cb4048
VS		 2377 }
2378
86c8bbbe 2379 return 0;
0b2ae6d7
VS		 2380}
2381
ed4a6a7c
MR		 2382/*
2383 * Build a set of 'intermediate' watermark values that satisfy both the old
2384 * state and the new state. These can be programmed to the hardware
2385 * immediately.
2386 */
2387static int ilk_compute_intermediate_wm(struct drm_device *dev,
2388 struct intel_crtc *intel_crtc,
2389 struct intel_crtc_state *newstate)
2390{
2391 struct intel_pipe_wm *a = &newstate->wm.intermediate;
2392 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2393 int level, max_level = ilk_wm_max_level(dev);
2394
2395 /*
2396 * Start with the final, target watermarks, then combine with the
2397 * currently active watermarks to get values that are safe both before
2398 * and after the vblank.
2399 */
2400 *a = newstate->wm.optimal.ilk;
2401 a->pipe_enabled |= b->pipe_enabled;
2402 a->sprites_enabled |= b->sprites_enabled;
2403 a->sprites_scaled |= b->sprites_scaled;
2404
2405 for (level = 0; level <= max_level; level++) {
2406 struct intel_wm_level *a_wm = &a->wm[level];
2407 const struct intel_wm_level *b_wm = &b->wm[level];
2408
2409 a_wm->enable &= b_wm->enable;
2410 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2411 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2412 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2413 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2414 }
2415
2416 /*
2417 * We need to make sure that these merged watermark values are
2418 * actually a valid configuration themselves. If they're not,
2419 * there's no safe way to transition from the old state to
2420 * the new state, so we need to fail the atomic transaction.
2421 */
2422 if (!ilk_validate_pipe_wm(dev, a))
2423 return -EINVAL;
2424
2425 /*
2426 * If our intermediate WM are identical to the final WM, then we can
2427 * omit the post-vblank programming; only update if it's different.
2428 */
2429 if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2430 newstate->wm.need_postvbl_update = false;
2431
2432 return 0;
2433}
2434
0b2ae6d7
VS		 2435/*
2436 * Merge the watermarks from all active pipes for a specific level.
2437 */
2438static void ilk_merge_wm_level(struct drm_device *dev,
2439 int level,
2440 struct intel_wm_level *ret_wm)
2441{
2442 const struct intel_crtc *intel_crtc;
2443
d52fea5b
VS		 2444 ret_wm->enable = true;
2445
d3fcc808 2446 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2447 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2448 const struct intel_wm_level *wm = &active->wm[level];
2449
2450 if (!active->pipe_enabled)
2451 continue;
0b2ae6d7 2452
d52fea5b
VS		 2453 /*
2454 * The watermark values may have been used in the past,
2455 * so we must maintain them in the registers for some
2456 * time even if the level is now disabled.
2457 */
0b2ae6d7 2458 if (!wm->enable)
d52fea5b 2459 ret_wm->enable = false;
0b2ae6d7
VS		 2460
2461 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2462 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2463 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2464 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2465 }
0b2ae6d7
VS		 2466}
2467
2468/*
2469 * Merge all low power watermarks for all active pipes.
2470 */
2471static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2472 const struct intel_wm_config *config,
820c1980 2473 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2474 struct intel_pipe_wm *merged)
2475{
7733b49b 2476 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2477 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2478 int last_enabled_level = max_level;
0b2ae6d7 2479
0ba22e26
VS		 2480 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2481 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2482 config->num_pipes_active > 1)
2483 return;
2484
6c8b6c28
VS		 2485 /* ILK: FBC WM must be disabled always */
2486 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2487
2488 /* merge each WM1+ level */
2489 for (level = 1; level <= max_level; level++) {
2490 struct intel_wm_level *wm = &merged->wm[level];
2491
2492 ilk_merge_wm_level(dev, level, wm);
2493
d52fea5b
VS		 2494 if (level > last_enabled_level)
2495 wm->enable = false;
2496 else if (!ilk_validate_wm_level(level, max, wm))
2497 /* make sure all following levels get disabled */
2498 last_enabled_level = level - 1;
0b2ae6d7
VS		 2499
2500 /*
2501 * The spec says it is preferred to disable
2502 * FBC WMs instead of disabling a WM level.
2503 */
2504 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2505 if (wm->enable)
2506 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2507 wm->fbc_val = 0;
2508 }
2509 }
6c8b6c28
VS		 2510
2511 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2512 /*
2513 * FIXME this is racy. FBC might get enabled later.
2514 * What we should check here is whether FBC can be
2515 * enabled sometime later.
2516 */
7733b49b 2517 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2518 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2519 for (level = 2; level <= max_level; level++) {
2520 struct intel_wm_level *wm = &merged->wm[level];
2521
2522 wm->enable = false;
2523 }
2524 }
0b2ae6d7
VS		 2525}
2526
b380ca3c
VS		 2527static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2528{
2529 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2530 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2531}
2532
a68d68ee
VS		 2533/* The value we need to program into the WM_LPx latency field */
2534static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2535{
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537
a42a5719 2538 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2539 return 2 * level;
2540 else
2541 return dev_priv->wm.pri_latency[level];
2542}
2543
820c1980 2544static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2545 const struct intel_pipe_wm *merged,
609cedef 2546 enum intel_ddb_partitioning partitioning,
820c1980 2547 struct ilk_wm_values *results)
801bcfff 2548{
0b2ae6d7
VS		 2549 struct intel_crtc *intel_crtc;
2550 int level, wm_lp;
cca32e9a 2551
0362c781 2552 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2553 results->partitioning = partitioning;
cca32e9a 2554
0b2ae6d7 2555 /* LP1+ register values */
cca32e9a 2556 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2557 const struct intel_wm_level *r;
801bcfff 2558
b380ca3c 2559 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2560
0362c781 2561 r = &merged->wm[level];
cca32e9a 2562
d52fea5b
VS		 2563 /*
2564 * Maintain the watermark values even if the level is
2565 * disabled. Doing otherwise could cause underruns.
2566 */
2567 results->wm_lp[wm_lp - 1] =
a68d68ee 2568 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2569 (r->pri_val << WM1_LP_SR_SHIFT) |
2570 r->cur_val;
2571
d52fea5b
VS		 2572 if (r->enable)
2573 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2574
416f4727
VS		 2575 if (INTEL_INFO(dev)->gen >= 8)
2576 results->wm_lp[wm_lp - 1] |=
2577 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2578 else
2579 results->wm_lp[wm_lp - 1] |=
2580 r->fbc_val << WM1_LP_FBC_SHIFT;
2581
d52fea5b
VS		 2582 /*
2583 * Always set WM1S_LP_EN when spr_val != 0, even if the
2584 * level is disabled. Doing otherwise could cause underruns.
2585 */
6cef2b8a
VS		 2586 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2587 WARN_ON(wm_lp != 1);
2588 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2589 } else
2590 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2591 }
801bcfff 2592
0b2ae6d7 2593 /* LP0 register values */
d3fcc808 2594 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2595 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2596 const struct intel_wm_level *r =
2597 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2598
2599 if (WARN_ON(!r->enable))
2600 continue;
2601
ed4a6a7c 2602 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2603
0b2ae6d7
VS		 2604 results->wm_pipe[pipe] =
2605 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2606 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2607 r->cur_val;
801bcfff
PZ		 2608 }
2609}
2610
861f3389
PZ		 2611/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2612 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2613static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2614 struct intel_pipe_wm *r1,
2615 struct intel_pipe_wm *r2)
861f3389 2616{
198a1e9b
VS		 2617 int level, max_level = ilk_wm_max_level(dev);
2618 int level1 = 0, level2 = 0;
861f3389 2619
198a1e9b
VS		 2620 for (level = 1; level <= max_level; level++) {
2621 if (r1->wm[level].enable)
2622 level1 = level;
2623 if (r2->wm[level].enable)
2624 level2 = level;
861f3389
PZ		 2625 }
2626
198a1e9b
VS		 2627 if (level1 == level2) {
2628 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2629 return r2;
2630 else
2631 return r1;
198a1e9b 2632 } else if (level1 > level2) {
861f3389
PZ		 2633 return r1;
2634 } else {
2635 return r2;
2636 }
2637}
2638
49a687c4
VS		 2639/* dirty bits used to track which watermarks need changes */
2640#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2641#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2642#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2643#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2644#define WM_DIRTY_FBC (1 << 24)
2645#define WM_DIRTY_DDB (1 << 25)
2646
055e393f 2647static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2648 const struct ilk_wm_values *old,
2649 const struct ilk_wm_values *new)
49a687c4
VS		 2650{
2651 unsigned int dirty = 0;
2652 enum pipe pipe;
2653 int wm_lp;
2654
055e393f 2655 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2656 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2657 dirty |= WM_DIRTY_LINETIME(pipe);
2658 /* Must disable LP1+ watermarks too */
2659 dirty |= WM_DIRTY_LP_ALL;
2660 }
2661
2662 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2663 dirty |= WM_DIRTY_PIPE(pipe);
2664 /* Must disable LP1+ watermarks too */
2665 dirty |= WM_DIRTY_LP_ALL;
2666 }
2667 }
2668
2669 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2670 dirty |= WM_DIRTY_FBC;
2671 /* Must disable LP1+ watermarks too */
2672 dirty |= WM_DIRTY_LP_ALL;
2673 }
2674
2675 if (old->partitioning != new->partitioning) {
2676 dirty |= WM_DIRTY_DDB;
2677 /* Must disable LP1+ watermarks too */
2678 dirty |= WM_DIRTY_LP_ALL;
2679 }
2680
2681 /* LP1+ watermarks already deemed dirty, no need to continue */
2682 if (dirty & WM_DIRTY_LP_ALL)
2683 return dirty;
2684
2685 /* Find the lowest numbered LP1+ watermark in need of an update... */
2686 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2687 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2688 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2689 break;
2690 }
2691
2692 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2693 for (; wm_lp <= 3; wm_lp++)
2694 dirty |= WM_DIRTY_LP(wm_lp);
2695
2696 return dirty;
2697}
2698
8553c18e
VS		 2699static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2700 unsigned int dirty)
801bcfff 2701{
820c1980 2702 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2703 bool changed = false;
801bcfff 2704
facd619b
VS		 2705 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2706 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2707 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2708 changed = true;
facd619b
VS		 2709 }
2710 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2711 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2712 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2713 changed = true;
facd619b
VS		 2714 }
2715 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2716 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2717 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2718 changed = true;
facd619b 2719 }
801bcfff 2720
facd619b
VS		 2721 /*
2722 * Don't touch WM1S_LP_EN here.
2723 * Doing so could cause underruns.
2724 */
6cef2b8a 2725
8553c18e
VS		 2726 return changed;
2727}
2728
2729/*
2730 * The spec says we shouldn't write when we don't need, because every write
2731 * causes WMs to be re-evaluated, expending some power.
2732 */
820c1980
ID		 2733static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2734 struct ilk_wm_values *results)
8553c18e
VS		 2735{
2736 struct drm_device *dev = dev_priv->dev;
820c1980 2737 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2738 unsigned int dirty;
2739 uint32_t val;
2740
055e393f 2741 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2742 if (!dirty)
2743 return;
2744
2745 _ilk_disable_lp_wm(dev_priv, dirty);
2746
49a687c4 2747 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2748 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2749 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2750 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2751 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2752 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2753
49a687c4 2754 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2755 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2756 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2757 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2758 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2759 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2760
49a687c4 2761 if (dirty & WM_DIRTY_DDB) {
a42a5719 2762 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2763 val = I915_READ(WM_MISC);
2764 if (results->partitioning == INTEL_DDB_PART_1_2)
2765 val &= ~WM_MISC_DATA_PARTITION_5_6;
2766 else
2767 val |= WM_MISC_DATA_PARTITION_5_6;
2768 I915_WRITE(WM_MISC, val);
2769 } else {
2770 val = I915_READ(DISP_ARB_CTL2);
2771 if (results->partitioning == INTEL_DDB_PART_1_2)
2772 val &= ~DISP_DATA_PARTITION_5_6;
2773 else
2774 val |= DISP_DATA_PARTITION_5_6;
2775 I915_WRITE(DISP_ARB_CTL2, val);
2776 }
1011d8c4
PZ		 2777 }
2778
49a687c4 2779 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2780 val = I915_READ(DISP_ARB_CTL);
2781 if (results->enable_fbc_wm)
2782 val &= ~DISP_FBC_WM_DIS;
2783 else
2784 val |= DISP_FBC_WM_DIS;
2785 I915_WRITE(DISP_ARB_CTL, val);
2786 }
2787
954911eb
ID		 2788 if (dirty & WM_DIRTY_LP(1) &&
2789 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2790 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2791
2792 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2793 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2794 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2795 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2796 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2797 }
801bcfff 2798
facd619b 2799 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2800 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2801 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2802 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2803 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2804 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2805
2806 dev_priv->wm.hw = *results;
801bcfff
PZ		 2807}
2808
ed4a6a7c 2809bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2810{
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812
2813 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2814}
2815
b9cec075
DL		 2816/*
2817 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2818 * different active planes.
2819 */
2820
2821#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2822#define BXT_DDB_SIZE 512
b9cec075 2823
024c9045
MR		 2824/*
2825 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2826 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2827 * other universal planes are in indices 1..n. Note that this may leave unused
2828 * indices between the top "sprite" plane and the cursor.
2829 */
2830static int
2831skl_wm_plane_id(const struct intel_plane *plane)
2832{
2833 switch (plane->base.type) {
2834 case DRM_PLANE_TYPE_PRIMARY:
2835 return 0;
2836 case DRM_PLANE_TYPE_CURSOR:
2837 return PLANE_CURSOR;
2838 case DRM_PLANE_TYPE_OVERLAY:
2839 return plane->plane + 1;
2840 default:
2841 MISSING_CASE(plane->base.type);
2842 return plane->plane;
2843 }
2844}
2845
b9cec075
DL		 2846static void
2847skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2848 const struct intel_crtc_state *cstate,
b9cec075 2849 const struct intel_wm_config *config,
b9cec075
DL		 2850 struct skl_ddb_entry *alloc /* out */)
2851{
024c9045 2852 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2853 struct drm_crtc *crtc;
2854 unsigned int pipe_size, ddb_size;
2855 int nth_active_pipe;
2856
024c9045 2857 if (!cstate->base.active) {
b9cec075
DL		 2858 alloc->start = 0;
2859 alloc->end = 0;
2860 return;
2861 }
2862
43d735a6
DL		 2863 if (IS_BROXTON(dev))
2864 ddb_size = BXT_DDB_SIZE;
2865 else
2866 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2867
2868 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2869
2870 nth_active_pipe = 0;
2871 for_each_crtc(dev, crtc) {
3ef00284 2872 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2873 continue;
2874
2875 if (crtc == for_crtc)
2876 break;
2877
2878 nth_active_pipe++;
2879 }
2880
2881 pipe_size = ddb_size / config->num_pipes_active;
2882 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2883 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2884}
2885
2886static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2887{
2888 if (config->num_pipes_active == 1)
2889 return 32;
2890
2891 return 8;
2892}
2893
a269c583
DL		 2894static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2895{
2896 entry->start = reg & 0x3ff;
2897 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2898 if (entry->end)
2899 entry->end += 1;
a269c583
DL		 2900}
2901
08db6652
DL		 2902void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2903 struct skl_ddb_allocation *ddb /* out */)
a269c583 2904{
a269c583
DL		 2905 enum pipe pipe;
2906 int plane;
2907 u32 val;
2908
b10f1b20
ML		 2909 memset(ddb, 0, sizeof(*ddb));
2910
a269c583 2911 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2912 enum intel_display_power_domain power_domain;
2913
2914 power_domain = POWER_DOMAIN_PIPE(pipe);
2915 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2916 continue;
2917
dd740780 2918 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2919 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2920 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2921 val);
2922 }
2923
2924 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2925 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2926 val);
4d800030
ID		 2927
2928 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2929 }
2930}
2931
b9cec075 2932static unsigned int
024c9045
MR		 2933skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2934 const struct drm_plane_state *pstate,
2935 int y)
b9cec075 2936{
024c9045
MR		 2937 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2938 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2939
2940 /* for planar format */
024c9045 2941 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2942 if (y) /* y-plane data rate */
024c9045
MR		 2943 return intel_crtc->config->pipe_src_w *
2944 intel_crtc->config->pipe_src_h *
2945 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2946 else /* uv-plane data rate */
024c9045
MR		 2947 return (intel_crtc->config->pipe_src_w/2) *
2948 (intel_crtc->config->pipe_src_h/2) *
2949 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2950 }
2951
2952 /* for packed formats */
024c9045
MR		 2953 return intel_crtc->config->pipe_src_w *
2954 intel_crtc->config->pipe_src_h *
2955 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2956}
2957
2958/*
2959 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2960 * a 8192x4096@32bpp framebuffer:
2961 * 3 * 4096 * 8192 * 4 < 2^32
2962 */
2963static unsigned int
024c9045 2964skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2965{
024c9045
MR		 2966 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2967 struct drm_device *dev = intel_crtc->base.dev;
2968 const struct intel_plane *intel_plane;
b9cec075 2969 unsigned int total_data_rate = 0;
b9cec075 2970
024c9045
MR		 2971 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2972 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2973
024c9045 2974 if (pstate->fb == NULL)
b9cec075
DL		 2975 continue;
2976
024c9045
MR		 2977 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2978 continue;
2979
2980 /* packed/uv */
2981 total_data_rate += skl_plane_relative_data_rate(cstate,
2982 pstate,
2983 0);
2984
2985 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2986 /* y-plane */
2987 total_data_rate += skl_plane_relative_data_rate(cstate,
2988 pstate,
2989 1);
b9cec075
DL		 2990 }
2991
2992 return total_data_rate;
2993}
2994
2995static void
024c9045 2996skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2997 struct skl_ddb_allocation *ddb /* out */)
2998{
024c9045 2999 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 3000 struct drm_device *dev = crtc->dev;
aa363136
MR		 3001 struct drm_i915_private *dev_priv = to_i915(dev);
3002 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3004 struct intel_plane *intel_plane;
b9cec075 3005 enum pipe pipe = intel_crtc->pipe;
34bb56af 3006 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3007 uint16_t alloc_size, start, cursor_blocks;
80958155 3008 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 3009 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 3010 unsigned int total_data_rate;
b9cec075 3011
024c9045 3012 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 3013 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3014 if (alloc_size == 0) {
3015 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 3016 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3017 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 3018 return;
3019 }
3020
3021 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 3022 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3023 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3024
3025 alloc_size -= cursor_blocks;
34bb56af 3026 alloc->end -= cursor_blocks;
b9cec075 3027
80958155 3028 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 3029 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3030 struct drm_plane *plane = &intel_plane->base;
3031 struct drm_framebuffer *fb = plane->state->fb;
3032 int id = skl_wm_plane_id(intel_plane);
80958155 3033
024c9045
MR		 3034 if (fb == NULL)
3035 continue;
3036 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 3037 continue;
3038
024c9045
MR		 3039 minimum[id] = 8;
3040 alloc_size -= minimum[id];
3041 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3042 alloc_size -= y_minimum[id];
80958155
DL		 3043 }
3044
b9cec075 3045 /*
80958155
DL		 3046 * 2. Distribute the remaining space in proportion to the amount of
3047 * data each plane needs to fetch from memory.
b9cec075
DL		 3048 *
3049 * FIXME: we may not allocate every single block here.
3050 */
024c9045 3051 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 3052
34bb56af 3053 start = alloc->start;
024c9045
MR		 3054 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3055 struct drm_plane *plane = &intel_plane->base;
3056 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 3057 unsigned int data_rate, y_data_rate;
3058 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3059 int id = skl_wm_plane_id(intel_plane);
b9cec075 3060
024c9045
MR		 3061 if (pstate->fb == NULL)
3062 continue;
3063 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 3064 continue;
3065
024c9045 3066 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3067
3068 /*
2cd601c6 3069 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3070 * promote the expression to 64 bits to avoid overflowing, the
3071 * result is < available as data_rate / total_data_rate < 1
3072 */
024c9045 3073 plane_blocks = minimum[id];
80958155
DL		 3074 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3075 total_data_rate);
b9cec075 3076
024c9045
MR		 3077 ddb->plane[pipe][id].start = start;
3078 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3079
3080 start += plane_blocks;
2cd601c6
CK		 3081
3082 /*
3083 * allocation for y_plane part of planar format:
3084 */
024c9045
MR		 3085 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3086 y_data_rate = skl_plane_relative_data_rate(cstate,
3087 pstate,
3088 1);
3089 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3090 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3091 total_data_rate);
3092
024c9045
MR		 3093 ddb->y_plane[pipe][id].start = start;
3094 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3095
3096 start += y_plane_blocks;
3097 }
3098
b9cec075
DL		 3099 }
3100
3101}
3102
5cec258b 3103static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3104{
3105 /* TODO: Take into account the scalers once we support them */
2d112de7 3106 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3107}
3108
3109/*
3110 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3111 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3112 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3113 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3114*/
ac484963 3115static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3116{
3117 uint32_t wm_intermediate_val, ret;
3118
3119 if (latency == 0)
3120 return UINT_MAX;
3121
ac484963 3122 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3123 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3124
3125 return ret;
3126}
3127
3128static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3129 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3130 uint64_t tiling, uint32_t latency)
2d41c0b5 3131{
d4c2aa60
TU		 3132 uint32_t ret;
3133 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3134 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3135
3136 if (latency == 0)
3137 return UINT_MAX;
3138
ac484963 3139 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3140
3141 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3142 tiling == I915_FORMAT_MOD_Yf_TILED) {
3143 plane_bytes_per_line *= 4;
3144 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3145 plane_blocks_per_line /= 4;
3146 } else {
3147 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3148 }
3149
2d41c0b5
PB		 3150 wm_intermediate_val = latency * pixel_rate;
3151 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3152 plane_blocks_per_line;
2d41c0b5
PB		 3153
3154 return ret;
3155}
3156
2d41c0b5
PB		 3157static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3158 const struct intel_crtc *intel_crtc)
3159{
3160 struct drm_device *dev = intel_crtc->base.dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3163
e6d90023
KM		 3164 /*
3165 * If ddb allocation of pipes changed, it may require recalculation of
3166 * watermarks
3167 */
3168 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3169 return true;
3170
3171 return false;
3172}
3173
d4c2aa60 3174static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3175 struct intel_crtc_state *cstate,
3176 struct intel_plane *intel_plane,
afb024aa 3177 uint16_t ddb_allocation,
d4c2aa60 3178 int level,
afb024aa
DL		 3179 uint16_t *out_blocks, /* out */
3180 uint8_t *out_lines /* out */)
2d41c0b5 3181{
024c9045
MR		 3182 struct drm_plane *plane = &intel_plane->base;
3183 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3184 uint32_t latency = dev_priv->wm.skl_latency[level];
3185 uint32_t method1, method2;
3186 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3187 uint32_t res_blocks, res_lines;
3188 uint32_t selected_result;
ac484963 3189 uint8_t cpp;
2d41c0b5 3190
024c9045 3191 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3192 return false;
3193
ac484963 3194 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3195 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3196 cpp, latency);
024c9045
MR		 3197 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3198 cstate->base.adjusted_mode.crtc_htotal,
3199 cstate->pipe_src_w,
ac484963 3200 cpp, fb->modifier[0],
d4c2aa60 3201 latency);
2d41c0b5 3202
ac484963 3203 plane_bytes_per_line = cstate->pipe_src_w * cpp;
d4c2aa60 3204 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3205
024c9045
MR		 3206 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3207 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3208 uint32_t min_scanlines = 4;
3209 uint32_t y_tile_minimum;
024c9045 3210 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3211 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3212 drm_format_plane_cpp(fb->pixel_format, 1) :
3213 drm_format_plane_cpp(fb->pixel_format, 0);
3214
ac484963 3215 switch (cpp) {
1fc0a8f7
TU		 3216 case 1:
3217 min_scanlines = 16;
3218 break;
3219 case 2:
3220 min_scanlines = 8;
3221 break;
3222 case 8:
3223 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3224 }
1fc0a8f7
TU		 3225 }
3226 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3227 selected_result = max(method2, y_tile_minimum);
3228 } else {
3229 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3230 selected_result = min(method1, method2);
3231 else
3232 selected_result = method1;
3233 }
2d41c0b5 3234
d4c2aa60
TU		 3235 res_blocks = selected_result + 1;
3236 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3237
0fda6568 3238 if (level >= 1 && level <= 7) {
024c9045
MR		 3239 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3240 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3241 res_lines += 4;
3242 else
3243 res_blocks++;
3244 }
e6d66171 3245
d4c2aa60 3246 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3247 return false;
3248
3249 *out_blocks = res_blocks;
3250 *out_lines = res_lines;
2d41c0b5
PB		 3251
3252 return true;
3253}
3254
3255static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3256 struct skl_ddb_allocation *ddb,
024c9045 3257 struct intel_crtc_state *cstate,
2d41c0b5 3258 int level,
2d41c0b5
PB		 3259 struct skl_wm_level *result)
3260{
024c9045
MR		 3261 struct drm_device *dev = dev_priv->dev;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3263 struct intel_plane *intel_plane;
2d41c0b5 3264 uint16_t ddb_blocks;
024c9045
MR		 3265 enum pipe pipe = intel_crtc->pipe;
3266
3267 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3268 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3269
2d41c0b5
PB		 3270 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3271
d4c2aa60 3272 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3273 cstate,
3274 intel_plane,
2d41c0b5 3275 ddb_blocks,
d4c2aa60 3276 level,
2d41c0b5
PB		 3277 &result->plane_res_b[i],
3278 &result->plane_res_l[i]);
3279 }
2d41c0b5
PB		 3280}
3281
407b50f3 3282static uint32_t
024c9045 3283skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3284{
024c9045 3285 if (!cstate->base.active)
407b50f3
DL		 3286 return 0;
3287
024c9045 3288 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3289 return 0;
407b50f3 3290
024c9045
MR		 3291 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3292 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3293}
3294
024c9045 3295static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3296 struct skl_wm_level *trans_wm /* out */)
407b50f3 3297{
024c9045 3298 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3300 struct intel_plane *intel_plane;
9414f563 3301
024c9045 3302 if (!cstate->base.active)
407b50f3 3303 return;
9414f563
DL		 3304
3305 /* Until we know more, just disable transition WMs */
024c9045
MR		 3306 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3307 int i = skl_wm_plane_id(intel_plane);
3308
9414f563 3309 trans_wm->plane_en[i] = false;
024c9045 3310 }
407b50f3
DL		 3311}
3312
024c9045 3313static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3314 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3315 struct skl_pipe_wm *pipe_wm)
3316{
024c9045 3317 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3318 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3319 int level, max_level = ilk_wm_max_level(dev);
3320
3321 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3322 skl_compute_wm_level(dev_priv, ddb, cstate,
3323 level, &pipe_wm->wm[level]);
2d41c0b5 3324 }
024c9045 3325 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3326
024c9045 3327 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3328}
3329
3330static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3331 struct skl_pipe_wm *p_wm,
3332 struct skl_wm_values *r,
3333 struct intel_crtc *intel_crtc)
3334{
3335 int level, max_level = ilk_wm_max_level(dev);
3336 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3337 uint32_t temp;
3338 int i;
2d41c0b5
PB		 3339
3340 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3341 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3342 temp = 0;
2d41c0b5
PB		 3343
3344 temp |= p_wm->wm[level].plane_res_l[i] <<
3345 PLANE_WM_LINES_SHIFT;
3346 temp |= p_wm->wm[level].plane_res_b[i];
3347 if (p_wm->wm[level].plane_en[i])
3348 temp |= PLANE_WM_EN;
3349
3350 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3351 }
3352
3353 temp = 0;
2d41c0b5 3354
4969d33e
MR		 3355 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3356 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3357
4969d33e 3358 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3359 temp |= PLANE_WM_EN;
3360
4969d33e 3361 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3362
3363 }
3364
9414f563
DL		 3365 /* transition WMs */
3366 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3367 temp = 0;
3368 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3369 temp |= p_wm->trans_wm.plane_res_b[i];
3370 if (p_wm->trans_wm.plane_en[i])
3371 temp |= PLANE_WM_EN;
3372
3373 r->plane_trans[pipe][i] = temp;
3374 }
3375
3376 temp = 0;
4969d33e
MR		 3377 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3378 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3379 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3380 temp |= PLANE_WM_EN;
3381
4969d33e 3382 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3383
2d41c0b5
PB		 3384 r->wm_linetime[pipe] = p_wm->linetime;
3385}
3386
f0f59a00
VS		 3387static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3388 i915_reg_t reg,
16160e3d
DL		 3389 const struct skl_ddb_entry *entry)
3390{
3391 if (entry->end)
3392 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3393 else
3394 I915_WRITE(reg, 0);
3395}
3396
2d41c0b5
PB		 3397static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3398 const struct skl_wm_values *new)
3399{
3400 struct drm_device *dev = dev_priv->dev;
3401 struct intel_crtc *crtc;
3402
19c8054c 3403 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3404 int i, level, max_level = ilk_wm_max_level(dev);
3405 enum pipe pipe = crtc->pipe;
3406
5d374d96
DL		 3407 if (!new->dirty[pipe])
3408 continue;
8211bd5b 3409
5d374d96 3410 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3411
5d374d96
DL		 3412 for (level = 0; level <= max_level; level++) {
3413 for (i = 0; i < intel_num_planes(crtc); i++)
3414 I915_WRITE(PLANE_WM(pipe, i, level),
3415 new->plane[pipe][i][level]);
3416 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3417 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3418 }
5d374d96
DL		 3419 for (i = 0; i < intel_num_planes(crtc); i++)
3420 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3421 new->plane_trans[pipe][i]);
4969d33e
MR		 3422 I915_WRITE(CUR_WM_TRANS(pipe),
3423 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3424
2cd601c6 3425 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3426 skl_ddb_entry_write(dev_priv,
3427 PLANE_BUF_CFG(pipe, i),
3428 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3429 skl_ddb_entry_write(dev_priv,
3430 PLANE_NV12_BUF_CFG(pipe, i),
3431 &new->ddb.y_plane[pipe][i]);
3432 }
5d374d96
DL		 3433
3434 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3435 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3436 }
2d41c0b5
PB		 3437}
3438
0e8fb7ba
DL		 3439/*
3440 * When setting up a new DDB allocation arrangement, we need to correctly
3441 * sequence the times at which the new allocations for the pipes are taken into
3442 * account or we'll have pipes fetching from space previously allocated to
3443 * another pipe.
3444 *
3445 * Roughly the sequence looks like:
3446 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3447 * overlapping with a previous light-up pipe (another way to put it is:
3448 * pipes with their new allocation strickly included into their old ones).
3449 * 2. re-allocate the other pipes that get their allocation reduced
3450 * 3. allocate the pipes having their allocation increased
3451 *
3452 * Steps 1. and 2. are here to take care of the following case:
3453 * - Initially DDB looks like this:
3454 * | B | C |
3455 * - enable pipe A.
3456 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3457 * allocation
3458 * | A | B | C |
3459 *
3460 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3461 */
3462
d21b795c
DL		 3463static void
3464skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3465{
0e8fb7ba
DL		 3466 int plane;
3467
d21b795c
DL		 3468 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3469
dd740780 3470 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3471 I915_WRITE(PLANE_SURF(pipe, plane),
3472 I915_READ(PLANE_SURF(pipe, plane)));
3473 }
3474 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3475}
3476
3477static bool
3478skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3479 const struct skl_ddb_allocation *new,
3480 enum pipe pipe)
3481{
3482 uint16_t old_size, new_size;
3483
3484 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3485 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3486
3487 return old_size != new_size &&
3488 new->pipe[pipe].start >= old->pipe[pipe].start &&
3489 new->pipe[pipe].end <= old->pipe[pipe].end;
3490}
3491
3492static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3493 struct skl_wm_values *new_values)
3494{
3495 struct drm_device *dev = dev_priv->dev;
3496 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3497 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3498 struct intel_crtc *crtc;
3499 enum pipe pipe;
3500
3501 new_ddb = &new_values->ddb;
3502 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3503
3504 /*
3505 * First pass: flush the pipes with the new allocation contained into
3506 * the old space.
3507 *
3508 * We'll wait for the vblank on those pipes to ensure we can safely
3509 * re-allocate the freed space without this pipe fetching from it.
3510 */
3511 for_each_intel_crtc(dev, crtc) {
3512 if (!crtc->active)
3513 continue;
3514
3515 pipe = crtc->pipe;
3516
3517 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3518 continue;
3519
d21b795c 3520 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3521 intel_wait_for_vblank(dev, pipe);
3522
3523 reallocated[pipe] = true;
3524 }
3525
3526
3527 /*
3528 * Second pass: flush the pipes that are having their allocation
3529 * reduced, but overlapping with a previous allocation.
3530 *
3531 * Here as well we need to wait for the vblank to make sure the freed
3532 * space is not used anymore.
3533 */
3534 for_each_intel_crtc(dev, crtc) {
3535 if (!crtc->active)
3536 continue;
3537
3538 pipe = crtc->pipe;
3539
3540 if (reallocated[pipe])
3541 continue;
3542
3543 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3544 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3545 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3546 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3547 reallocated[pipe] = true;
0e8fb7ba 3548 }
0e8fb7ba
DL		 3549 }
3550
3551 /*
3552 * Third pass: flush the pipes that got more space allocated.
3553 *
3554 * We don't need to actively wait for the update here, next vblank
3555 * will just get more DDB space with the correct WM values.
3556 */
3557 for_each_intel_crtc(dev, crtc) {
3558 if (!crtc->active)
3559 continue;
3560
3561 pipe = crtc->pipe;
3562
3563 /*
3564 * At this point, only the pipes more space than before are
3565 * left to re-allocate.
3566 */
3567 if (reallocated[pipe])
3568 continue;
3569
d21b795c 3570 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3571 }
3572}
3573
2d41c0b5 3574static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3575 struct skl_ddb_allocation *ddb, /* out */
3576 struct skl_pipe_wm *pipe_wm /* out */)
3577{
3578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3579 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3580
aa363136 3581 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3582 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3583
4e0963c7 3584 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3585 return false;
3586
4e0963c7 3587 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3588
2d41c0b5
PB		 3589 return true;
3590}
3591
3592static void skl_update_other_pipe_wm(struct drm_device *dev,
3593 struct drm_crtc *crtc,
2d41c0b5
PB		 3594 struct skl_wm_values *r)
3595{
3596 struct intel_crtc *intel_crtc;
3597 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3598
3599 /*
3600 * If the WM update hasn't changed the allocation for this_crtc (the
3601 * crtc we are currently computing the new WM values for), other
3602 * enabled crtcs will keep the same allocation and we don't need to
3603 * recompute anything for them.
3604 */
3605 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3606 return;
3607
3608 /*
3609 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3610 * other active pipes need new DDB allocation and WM values.
3611 */
19c8054c 3612 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3613 struct skl_pipe_wm pipe_wm = {};
3614 bool wm_changed;
3615
3616 if (this_crtc->pipe == intel_crtc->pipe)
3617 continue;
3618
3619 if (!intel_crtc->active)
3620 continue;
3621
aa363136 3622 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3623 &r->ddb, &pipe_wm);
3624
3625 /*
3626 * If we end up re-computing the other pipe WM values, it's
3627 * because it was really needed, so we expect the WM values to
3628 * be different.
3629 */
3630 WARN_ON(!wm_changed);
3631
024c9045 3632 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3633 r->dirty[intel_crtc->pipe] = true;
3634 }
3635}
3636
adda50b8
BP		 3637static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3638{
3639 watermarks->wm_linetime[pipe] = 0;
3640 memset(watermarks->plane[pipe], 0,
3641 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3642 memset(watermarks->plane_trans[pipe],
3643 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3644 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3645
3646 /* Clear ddb entries for pipe */
3647 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3648 memset(&watermarks->ddb.plane[pipe], 0,
3649 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3650 memset(&watermarks->ddb.y_plane[pipe], 0,
3651 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3652 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3653 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3654
3655}
3656
2d41c0b5
PB		 3657static void skl_update_wm(struct drm_crtc *crtc)
3658{
3659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 struct drm_device *dev = crtc->dev;
3661 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3662 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3663 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3664 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3665
adda50b8
BP		 3666
3667 /* Clear all dirty flags */
3668 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3669
3670 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3671
aa363136 3672 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3673 return;
3674
4e0963c7 3675 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3676 results->dirty[intel_crtc->pipe] = true;
3677
aa363136 3678 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3679 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3680 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3681
3682 /* store the new configuration */
3683 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3684}
3685
d890565c
VS		 3686static void ilk_compute_wm_config(struct drm_device *dev,
3687 struct intel_wm_config *config)
3688{
3689 struct intel_crtc *crtc;
3690
3691 /* Compute the currently _active_ config */
3692 for_each_intel_crtc(dev, crtc) {
3693 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3694
3695 if (!wm->pipe_enabled)
3696 continue;
3697
3698 config->sprites_enabled |= wm->sprites_enabled;
3699 config->sprites_scaled |= wm->sprites_scaled;
3700 config->num_pipes_active++;
3701 }
3702}
3703
ed4a6a7c 3704static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3705{
ed4a6a7c 3706 struct drm_device *dev = dev_priv->dev;
b9d5c839 3707 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3708 struct ilk_wm_maximums max;
d890565c 3709 struct intel_wm_config config = {};
820c1980 3710 struct ilk_wm_values results = {};
77c122bc 3711 enum intel_ddb_partitioning partitioning;
261a27d1 3712
d890565c
VS		 3713 ilk_compute_wm_config(dev, &config);
3714
3715 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3716 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3717
3718 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3719 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3720 config.num_pipes_active == 1 && config.sprites_enabled) {
3721 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3722 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3723
820c1980 3724 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3725 } else {
198a1e9b 3726 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3727 }
3728
198a1e9b 3729 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3730 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3731
820c1980 3732 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3733
820c1980 3734 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3735}
3736
ed4a6a7c 3737static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 3738{
ed4a6a7c
MR		 3739 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3740 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3741
ed4a6a7c
MR		 3742 mutex_lock(&dev_priv->wm.wm_mutex);
3743 intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3744 ilk_program_watermarks(dev_priv);
3745 mutex_unlock(&dev_priv->wm.wm_mutex);
3746}
bf220452 3747
ed4a6a7c
MR		 3748static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3749{
3750 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3751 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 3752
ed4a6a7c
MR		 3753 mutex_lock(&dev_priv->wm.wm_mutex);
3754 if (cstate->wm.need_postvbl_update) {
3755 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3756 ilk_program_watermarks(dev_priv);
3757 }
3758 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 3759}
3760
3078999f
PB		 3761static void skl_pipe_wm_active_state(uint32_t val,
3762 struct skl_pipe_wm *active,
3763 bool is_transwm,
3764 bool is_cursor,
3765 int i,
3766 int level)
3767{
3768 bool is_enabled = (val & PLANE_WM_EN) != 0;
3769
3770 if (!is_transwm) {
3771 if (!is_cursor) {
3772 active->wm[level].plane_en[i] = is_enabled;
3773 active->wm[level].plane_res_b[i] =
3774 val & PLANE_WM_BLOCKS_MASK;
3775 active->wm[level].plane_res_l[i] =
3776 (val >> PLANE_WM_LINES_SHIFT) &
3777 PLANE_WM_LINES_MASK;
3778 } else {
4969d33e
MR		 3779 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3780 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3781 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3782 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3783 (val >> PLANE_WM_LINES_SHIFT) &
3784 PLANE_WM_LINES_MASK;
3785 }
3786 } else {
3787 if (!is_cursor) {
3788 active->trans_wm.plane_en[i] = is_enabled;
3789 active->trans_wm.plane_res_b[i] =
3790 val & PLANE_WM_BLOCKS_MASK;
3791 active->trans_wm.plane_res_l[i] =
3792 (val >> PLANE_WM_LINES_SHIFT) &
3793 PLANE_WM_LINES_MASK;
3794 } else {
4969d33e
MR		 3795 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3796 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3797 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3798 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3799 (val >> PLANE_WM_LINES_SHIFT) &
3800 PLANE_WM_LINES_MASK;
3801 }
3802 }
3803}
3804
3805static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3806{
3807 struct drm_device *dev = crtc->dev;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3811 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3812 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3813 enum pipe pipe = intel_crtc->pipe;
3814 int level, i, max_level;
3815 uint32_t temp;
3816
3817 max_level = ilk_wm_max_level(dev);
3818
3819 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3820
3821 for (level = 0; level <= max_level; level++) {
3822 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3823 hw->plane[pipe][i][level] =
3824 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3825 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3826 }
3827
3828 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3829 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3830 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3831
3ef00284 3832 if (!intel_crtc->active)
3078999f
PB		 3833 return;
3834
3835 hw->dirty[pipe] = true;
3836
3837 active->linetime = hw->wm_linetime[pipe];
3838
3839 for (level = 0; level <= max_level; level++) {
3840 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3841 temp = hw->plane[pipe][i][level];
3842 skl_pipe_wm_active_state(temp, active, false,
3843 false, i, level);
3844 }
4969d33e 3845 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3846 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3847 }
3848
3849 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3850 temp = hw->plane_trans[pipe][i];
3851 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3852 }
3853
4969d33e 3854 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3855 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3856
3857 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3858}
3859
3860void skl_wm_get_hw_state(struct drm_device *dev)
3861{
a269c583
DL		 3862 struct drm_i915_private *dev_priv = dev->dev_private;
3863 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3864 struct drm_crtc *crtc;
3865
a269c583 3866 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3867 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3868 skl_pipe_wm_get_hw_state(crtc);
3869}
3870
243e6a44
VS		 3871static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3872{
3873 struct drm_device *dev = crtc->dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3875 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3877 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3878 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3879 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3880 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3881 [PIPE_A] = WM0_PIPEA_ILK,
3882 [PIPE_B] = WM0_PIPEB_ILK,
3883 [PIPE_C] = WM0_PIPEC_IVB,
3884 };
3885
3886 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3887 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3888 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3889
3ef00284 3890 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3891
3892 if (active->pipe_enabled) {
243e6a44
VS		 3893 u32 tmp = hw->wm_pipe[pipe];
3894
3895 /*
3896 * For active pipes LP0 watermark is marked as
3897 * enabled, and LP1+ watermaks as disabled since
3898 * we can't really reverse compute them in case
3899 * multiple pipes are active.
3900 */
3901 active->wm[0].enable = true;
3902 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3903 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3904 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3905 active->linetime = hw->wm_linetime[pipe];
3906 } else {
3907 int level, max_level = ilk_wm_max_level(dev);
3908
3909 /*
3910 * For inactive pipes, all watermark levels
3911 * should be marked as enabled but zeroed,
3912 * which is what we'd compute them to.
3913 */
3914 for (level = 0; level <= max_level; level++)
3915 active->wm[level].enable = true;
3916 }
4e0963c7
MR		 3917
3918 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3919}
3920
6eb1a681
VS		 3921#define _FW_WM(value, plane) \
3922 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3923#define _FW_WM_VLV(value, plane) \
3924 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3925
3926static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3927 struct vlv_wm_values *wm)
3928{
3929 enum pipe pipe;
3930 uint32_t tmp;
3931
3932 for_each_pipe(dev_priv, pipe) {
3933 tmp = I915_READ(VLV_DDL(pipe));
3934
3935 wm->ddl[pipe].primary =
3936 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3937 wm->ddl[pipe].cursor =
3938 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3939 wm->ddl[pipe].sprite[0] =
3940 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3941 wm->ddl[pipe].sprite[1] =
3942 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3943 }
3944
3945 tmp = I915_READ(DSPFW1);
3946 wm->sr.plane = _FW_WM(tmp, SR);
3947 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3948 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3949 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3950
3951 tmp = I915_READ(DSPFW2);
3952 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3953 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3954 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3955
3956 tmp = I915_READ(DSPFW3);
3957 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3958
3959 if (IS_CHERRYVIEW(dev_priv)) {
3960 tmp = I915_READ(DSPFW7_CHV);
3961 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3962 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3963
3964 tmp = I915_READ(DSPFW8_CHV);
3965 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3966 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3967
3968 tmp = I915_READ(DSPFW9_CHV);
3969 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3970 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3971
3972 tmp = I915_READ(DSPHOWM);
3973 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3974 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3975 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3976 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3977 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3978 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3979 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3980 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3981 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3982 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3983 } else {
3984 tmp = I915_READ(DSPFW7);
3985 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3986 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3987
3988 tmp = I915_READ(DSPHOWM);
3989 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3990 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3991 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3992 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3993 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3994 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3995 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3996 }
3997}
3998
3999#undef _FW_WM
4000#undef _FW_WM_VLV
4001
4002void vlv_wm_get_hw_state(struct drm_device *dev)
4003{
4004 struct drm_i915_private *dev_priv = to_i915(dev);
4005 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4006 struct intel_plane *plane;
4007 enum pipe pipe;
4008 u32 val;
4009
4010 vlv_read_wm_values(dev_priv, wm);
4011
4012 for_each_intel_plane(dev, plane) {
4013 switch (plane->base.type) {
4014 int sprite;
4015 case DRM_PLANE_TYPE_CURSOR:
4016 plane->wm.fifo_size = 63;
4017 break;
4018 case DRM_PLANE_TYPE_PRIMARY:
4019 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4020 break;
4021 case DRM_PLANE_TYPE_OVERLAY:
4022 sprite = plane->plane;
4023 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4024 break;
4025 }
4026 }
4027
4028 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4029 wm->level = VLV_WM_LEVEL_PM2;
4030
4031 if (IS_CHERRYVIEW(dev_priv)) {
4032 mutex_lock(&dev_priv->rps.hw_lock);
4033
4034 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4035 if (val & DSP_MAXFIFO_PM5_ENABLE)
4036 wm->level = VLV_WM_LEVEL_PM5;
4037
58590c14
VS		 4038 /*
4039 * If DDR DVFS is disabled in the BIOS, Punit
4040 * will never ack the request. So if that happens
4041 * assume we don't have to enable/disable DDR DVFS
4042 * dynamically. To test that just set the REQ_ACK
4043 * bit to poke the Punit, but don't change the
4044 * HIGH/LOW bits so that we don't actually change
4045 * the current state.
4046 */
6eb1a681 4047 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4048 val |= FORCE_DDR_FREQ_REQ_ACK;
4049 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4050
4051 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4052 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4053 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4054 "assuming DDR DVFS is disabled\n");
4055 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4056 } else {
4057 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4058 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4059 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4060 }
6eb1a681
VS		 4061
4062 mutex_unlock(&dev_priv->rps.hw_lock);
4063 }
4064
4065 for_each_pipe(dev_priv, pipe)
4066 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4067 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4068 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4069
4070 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4071 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4072}
4073
243e6a44
VS		 4074void ilk_wm_get_hw_state(struct drm_device *dev)
4075{
4076 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4077 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4078 struct drm_crtc *crtc;
4079
70e1e0ec 4080 for_each_crtc(dev, crtc)
243e6a44
VS		 4081 ilk_pipe_wm_get_hw_state(crtc);
4082
4083 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4084 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4085 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4086
4087 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4088 if (INTEL_INFO(dev)->gen >= 7) {
4089 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4090 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4091 }
243e6a44 4092
a42a5719 4093 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4094 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4095 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4096 else if (IS_IVYBRIDGE(dev))
4097 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4098 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4099
4100 hw->enable_fbc_wm =
4101 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4102}
4103
b445e3b0
ED		 4104/**
4105 * intel_update_watermarks - update FIFO watermark values based on current modes
4106 *
4107 * Calculate watermark values for the various WM regs based on current mode
4108 * and plane configuration.
4109 *
4110 * There are several cases to deal with here:
4111 * - normal (i.e. non-self-refresh)
4112 * - self-refresh (SR) mode
4113 * - lines are large relative to FIFO size (buffer can hold up to 2)
4114 * - lines are small relative to FIFO size (buffer can hold more than 2
4115 * lines), so need to account for TLB latency
4116 *
4117 * The normal calculation is:
4118 * watermark = dotclock * bytes per pixel * latency
4119 * where latency is platform & configuration dependent (we assume pessimal
4120 * values here).
4121 *
4122 * The SR calculation is:
4123 * watermark = (trunc(latency/line time)+1) * surface width *
4124 * bytes per pixel
4125 * where
4126 * line time = htotal / dotclock
4127 * surface width = hdisplay for normal plane and 64 for cursor
4128 * and latency is assumed to be high, as above.
4129 *
4130 * The final value programmed to the register should always be rounded up,
4131 * and include an extra 2 entries to account for clock crossings.
4132 *
4133 * We don't use the sprite, so we can ignore that. And on Crestline we have
4134 * to set the non-SR watermarks to 8.
4135 */
46ba614c 4136void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4137{
46ba614c 4138 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4139
4140 if (dev_priv->display.update_wm)
46ba614c 4141 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4142}
4143
e2828914 4144/*
9270388e 4145 * Lock protecting IPS related data structures
9270388e
DV		 4146 */
4147DEFINE_SPINLOCK(mchdev_lock);
4148
4149/* Global for IPS driver to get at the current i915 device. Protected by
4150 * mchdev_lock. */
4151static struct drm_i915_private *i915_mch_dev;
4152
2b4e57bd
ED		 4153bool ironlake_set_drps(struct drm_device *dev, u8 val)
4154{
4155 struct drm_i915_private *dev_priv = dev->dev_private;
4156 u16 rgvswctl;
4157
9270388e
DV		 4158 assert_spin_locked(&mchdev_lock);
4159
2b4e57bd
ED		 4160 rgvswctl = I915_READ16(MEMSWCTL);
4161 if (rgvswctl & MEMCTL_CMD_STS) {
4162 DRM_DEBUG("gpu busy, RCS change rejected\n");
4163 return false; /* still busy with another command */
4164 }
4165
4166 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4167 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4168 I915_WRITE16(MEMSWCTL, rgvswctl);
4169 POSTING_READ16(MEMSWCTL);
4170
4171 rgvswctl |= MEMCTL_CMD_STS;
4172 I915_WRITE16(MEMSWCTL, rgvswctl);
4173
4174 return true;
4175}
4176
8090c6b9 4177static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4178{
4179 struct drm_i915_private *dev_priv = dev->dev_private;
84f1b20f 4180 u32 rgvmodectl;
2b4e57bd
ED		 4181 u8 fmax, fmin, fstart, vstart;
4182
9270388e
DV		 4183 spin_lock_irq(&mchdev_lock);
4184
84f1b20f
TU		 4185 rgvmodectl = I915_READ(MEMMODECTL);
4186
2b4e57bd
ED		 4187 /* Enable temp reporting */
4188 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4189 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4190
4191 /* 100ms RC evaluation intervals */
4192 I915_WRITE(RCUPEI, 100000);
4193 I915_WRITE(RCDNEI, 100000);
4194
4195 /* Set max/min thresholds to 90ms and 80ms respectively */
4196 I915_WRITE(RCBMAXAVG, 90000);
4197 I915_WRITE(RCBMINAVG, 80000);
4198
4199 I915_WRITE(MEMIHYST, 1);
4200
4201 /* Set up min, max, and cur for interrupt handling */
4202 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4203 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4204 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4205 MEMMODE_FSTART_SHIFT;
4206
616847e7 4207 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4208 PXVFREQ_PX_SHIFT;
4209
20e4d407
DV		 4210 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4211 dev_priv->ips.fstart = fstart;
2b4e57bd 4212
20e4d407
DV		 4213 dev_priv->ips.max_delay = fstart;
4214 dev_priv->ips.min_delay = fmin;
4215 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4216
4217 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4218 fmax, fmin, fstart);
4219
4220 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4221
4222 /*
4223 * Interrupts will be enabled in ironlake_irq_postinstall
4224 */
4225
4226 I915_WRITE(VIDSTART, vstart);
4227 POSTING_READ(VIDSTART);
4228
4229 rgvmodectl |= MEMMODE_SWMODE_EN;
4230 I915_WRITE(MEMMODECTL, rgvmodectl);
4231
9270388e 4232 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4233 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4234 mdelay(1);
2b4e57bd
ED		 4235
4236 ironlake_set_drps(dev, fstart);
4237
7d81c3e0
VS		 4238 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4239 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4240 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4241 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4242 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4243
4244 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4245}
4246
8090c6b9 4247static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4248{
4249 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4250 u16 rgvswctl;
4251
4252 spin_lock_irq(&mchdev_lock);
4253
4254 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4255
4256 /* Ack interrupts, disable EFC interrupt */
4257 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4258 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4259 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4260 I915_WRITE(DEIIR, DE_PCU_EVENT);
4261 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4262
4263 /* Go back to the starting frequency */
20e4d407 4264 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4265 mdelay(1);
2b4e57bd
ED		 4266 rgvswctl |= MEMCTL_CMD_STS;
4267 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4268 mdelay(1);
2b4e57bd 4269
9270388e 4270 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4271}
4272
acbe9475
DV		 4273/* There's a funny hw issue where the hw returns all 0 when reading from
4274 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4275 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4276 * all limits and the gpu stuck at whatever frequency it is at atm).
4277 */
74ef1173 4278static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4279{
7b9e0ae6 4280 u32 limits;
2b4e57bd 4281
20b46e59
DV		 4282 /* Only set the down limit when we've reached the lowest level to avoid
4283 * getting more interrupts, otherwise leave this clear. This prevents a
4284 * race in the hw when coming out of rc6: There's a tiny window where
4285 * the hw runs at the minimal clock before selecting the desired
4286 * frequency, if the down threshold expires in that window we will not
4287 * receive a down interrupt. */
74ef1173
AG		 4288 if (IS_GEN9(dev_priv->dev)) {
4289 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4290 if (val <= dev_priv->rps.min_freq_softlimit)
4291 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4292 } else {
4293 limits = dev_priv->rps.max_freq_softlimit << 24;
4294 if (val <= dev_priv->rps.min_freq_softlimit)
4295 limits |= dev_priv->rps.min_freq_softlimit << 16;
4296 }
20b46e59
DV		 4297
4298 return limits;
4299}
4300
dd75fdc8
CW		 4301static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4302{
4303 int new_power;
8a586437
AG		 4304 u32 threshold_up = 0, threshold_down = 0; /* in % */
4305 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4306
4307 new_power = dev_priv->rps.power;
4308 switch (dev_priv->rps.power) {
4309 case LOW_POWER:
b39fb297 4310 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4311 new_power = BETWEEN;
4312 break;
4313
4314 case BETWEEN:
b39fb297 4315 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4316 new_power = LOW_POWER;
b39fb297 4317 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4318 new_power = HIGH_POWER;
4319 break;
4320
4321 case HIGH_POWER:
b39fb297 4322 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4323 new_power = BETWEEN;
4324 break;
4325 }
4326 /* Max/min bins are special */
aed242ff 4327 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4328 new_power = LOW_POWER;
aed242ff 4329 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4330 new_power = HIGH_POWER;
4331 if (new_power == dev_priv->rps.power)
4332 return;
4333
4334 /* Note the units here are not exactly 1us, but 1280ns. */
4335 switch (new_power) {
4336 case LOW_POWER:
4337 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4338 ei_up = 16000;
4339 threshold_up = 95;
dd75fdc8
CW		 4340
4341 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4342 ei_down = 32000;
4343 threshold_down = 85;
dd75fdc8
CW		 4344 break;
4345
4346 case BETWEEN:
4347 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4348 ei_up = 13000;
4349 threshold_up = 90;
dd75fdc8
CW		 4350
4351 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4352 ei_down = 32000;
4353 threshold_down = 75;
dd75fdc8
CW		 4354 break;
4355
4356 case HIGH_POWER:
4357 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4358 ei_up = 10000;
4359 threshold_up = 85;
dd75fdc8
CW		 4360
4361 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4362 ei_down = 32000;
4363 threshold_down = 60;
dd75fdc8
CW		 4364 break;
4365 }
4366
8a586437
AG		 4367 I915_WRITE(GEN6_RP_UP_EI,
4368 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4369 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4370 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4371
4372 I915_WRITE(GEN6_RP_DOWN_EI,
4373 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4374 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4375 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4376
4377 I915_WRITE(GEN6_RP_CONTROL,
4378 GEN6_RP_MEDIA_TURBO |
4379 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4380 GEN6_RP_MEDIA_IS_GFX |
4381 GEN6_RP_ENABLE |
4382 GEN6_RP_UP_BUSY_AVG |
4383 GEN6_RP_DOWN_IDLE_AVG);
4384
dd75fdc8 4385 dev_priv->rps.power = new_power;
8fb55197
CW		 4386 dev_priv->rps.up_threshold = threshold_up;
4387 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4388 dev_priv->rps.last_adj = 0;
4389}
4390
2876ce73
CW		 4391static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4392{
4393 u32 mask = 0;
4394
4395 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4396 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4397 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4398 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4399
7b3c29f6
CW		 4400 mask &= dev_priv->pm_rps_events;
4401
59d02a1f 4402 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4403}
4404
b8a5ff8d
JM		 4405/* gen6_set_rps is called to update the frequency request, but should also be
4406 * called when the range (min_delay and max_delay) is modified so that we can
4407 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4408static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4409{
4410 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4411
23eafea6 4412 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4413 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4414 return;
4415
4fc688ce 4416 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4417 WARN_ON(val > dev_priv->rps.max_freq);
4418 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4419
eb64cad1
CW		 4420 /* min/max delay may still have been modified so be sure to
4421 * write the limits value.
4422 */
4423 if (val != dev_priv->rps.cur_freq) {
4424 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4425
5704195c
AG		 4426 if (IS_GEN9(dev))
4427 I915_WRITE(GEN6_RPNSWREQ,
4428 GEN9_FREQUENCY(val));
4429 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4430 I915_WRITE(GEN6_RPNSWREQ,
4431 HSW_FREQUENCY(val));
4432 else
4433 I915_WRITE(GEN6_RPNSWREQ,
4434 GEN6_FREQUENCY(val) |
4435 GEN6_OFFSET(0) |
4436 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4437 }
7b9e0ae6 4438
7b9e0ae6
CW		 4439 /* Make sure we continue to get interrupts
4440 * until we hit the minimum or maximum frequencies.
4441 */
74ef1173 4442 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4443 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4444
d5570a72
BW		 4445 POSTING_READ(GEN6_RPNSWREQ);
4446
b39fb297 4447 dev_priv->rps.cur_freq = val;
0f94592e 4448 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4449}
4450
ffe02b40
VS		 4451static void valleyview_set_rps(struct drm_device *dev, u8 val)
4452{
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454
4455 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4456 WARN_ON(val > dev_priv->rps.max_freq);
4457 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4458
4459 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4460 "Odd GPU freq value\n"))
4461 val &= ~1;
4462
cd25dd5b
D		 4463 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4464
8fb55197 4465 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4466 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4467 if (!IS_CHERRYVIEW(dev_priv))
4468 gen6_set_rps_thresholds(dev_priv, val);
4469 }
ffe02b40 4470
ffe02b40
VS		 4471 dev_priv->rps.cur_freq = val;
4472 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4473}
4474
a7f6e231 4475/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4476 *
4477 * * If Gfx is Idle, then
a7f6e231
D		 4478 * 1. Forcewake Media well.
4479 * 2. Request idle freq.
4480 * 3. Release Forcewake of Media well.
76c3552f
D		 4481*/
4482static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4483{
aed242ff 4484 u32 val = dev_priv->rps.idle_freq;
5549d25f 4485
aed242ff 4486 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4487 return;
4488
a7f6e231
D		 4489 /* Wake up the media well, as that takes a lot less
4490 * power than the Render well. */
4491 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4492 valleyview_set_rps(dev_priv->dev, val);
4493 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4494}
4495
43cf3bf0
CW		 4496void gen6_rps_busy(struct drm_i915_private *dev_priv)
4497{
4498 mutex_lock(&dev_priv->rps.hw_lock);
4499 if (dev_priv->rps.enabled) {
4500 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4501 gen6_rps_reset_ei(dev_priv);
4502 I915_WRITE(GEN6_PMINTRMSK,
4503 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4504 }
4505 mutex_unlock(&dev_priv->rps.hw_lock);
4506}
4507
b29c19b6
CW		 4508void gen6_rps_idle(struct drm_i915_private *dev_priv)
4509{
691bb717
DL		 4510 struct drm_device *dev = dev_priv->dev;
4511
b29c19b6 4512 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4513 if (dev_priv->rps.enabled) {
666a4537 4514 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4515 vlv_set_rps_idle(dev_priv);
7526ed79 4516 else
aed242ff 4517 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4518 dev_priv->rps.last_adj = 0;
43cf3bf0 4519 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4520 }
8d3afd7d 4521 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4522
8d3afd7d 4523 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4524 while (!list_empty(&dev_priv->rps.clients))
4525 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4526 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4527}
4528
1854d5ca 4529void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4530 struct intel_rps_client *rps,
4531 unsigned long submitted)
b29c19b6 4532{
8d3afd7d
CW		 4533 /* This is intentionally racy! We peek at the state here, then
4534 * validate inside the RPS worker.
4535 */
4536 if (!(dev_priv->mm.busy &&
4537 dev_priv->rps.enabled &&
4538 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4539 return;
43cf3bf0 4540
e61b9958
CW		 4541 /* Force a RPS boost (and don't count it against the client) if
4542 * the GPU is severely congested.
4543 */
d0bc54f2 4544 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4545 rps = NULL;
4546
8d3afd7d
CW		 4547 spin_lock(&dev_priv->rps.client_lock);
4548 if (rps == NULL || list_empty(&rps->link)) {
4549 spin_lock_irq(&dev_priv->irq_lock);
4550 if (dev_priv->rps.interrupts_enabled) {
4551 dev_priv->rps.client_boost = true;
4552 queue_work(dev_priv->wq, &dev_priv->rps.work);
4553 }
4554 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4555
2e1b8730
CW		 4556 if (rps != NULL) {
4557 list_add(&rps->link, &dev_priv->rps.clients);
4558 rps->boosts++;
1854d5ca
CW		 4559 } else
4560 dev_priv->rps.boosts++;
c0951f0c 4561 }
8d3afd7d 4562 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4563}
4564
ffe02b40 4565void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4566{
666a4537 4567 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4568 valleyview_set_rps(dev, val);
4569 else
4570 gen6_set_rps(dev, val);
0a073b84
JB		 4571}
4572
20e49366
ZW		 4573static void gen9_disable_rps(struct drm_device *dev)
4574{
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576
4577 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4578 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4579}
4580
44fc7d5c 4581static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4582{
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584
4585 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4586 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4587}
4588
38807746
D		 4589static void cherryview_disable_rps(struct drm_device *dev)
4590{
4591 struct drm_i915_private *dev_priv = dev->dev_private;
4592
4593 I915_WRITE(GEN6_RC_CONTROL, 0);
4594}
4595
44fc7d5c
DV		 4596static void valleyview_disable_rps(struct drm_device *dev)
4597{
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599
98a2e5f9
D		 4600 /* we're doing forcewake before Disabling RC6,
4601 * This what the BIOS expects when going into suspend */
59bad947 4602 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4603
44fc7d5c 4604 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4605
59bad947 4606 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4607}
4608
dc39fff7
BW		 4609static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4610{
666a4537 4611 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4612 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4613 mode = GEN6_RC_CTL_RC6_ENABLE;
4614 else
4615 mode = 0;
4616 }
58abf1da
RV		 4617 if (HAS_RC6p(dev))
4618 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4619 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4620 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4621 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4622
4623 else
4624 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4625 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4626}
4627
274008e8
SAK		 4628static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4629{
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 bool enable_rc6 = true;
4632 unsigned long rc6_ctx_base;
4633
4634 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4635 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4636 enable_rc6 = false;
4637 }
4638
4639 /*
4640 * The exact context size is not known for BXT, so assume a page size
4641 * for this check.
4642 */
4643 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4644 if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) &&
4645 (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base +
4646 dev_priv->gtt.stolen_reserved_size))) {
4647 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4648 enable_rc6 = false;
4649 }
4650
4651 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4652 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4653 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4654 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4655 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4656 enable_rc6 = false;
4657 }
4658
4659 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4660 GEN6_RC_CTL_HW_ENABLE)) &&
4661 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4662 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4663 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4664 enable_rc6 = false;
4665 }
4666
4667 return enable_rc6;
4668}
4669
4670int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4671{
e7d66d89
DV		 4672 /* No RC6 before Ironlake and code is gone for ilk. */
4673 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4674 return 0;
4675
274008e8
SAK		 4676 if (!enable_rc6)
4677 return 0;
4678
4679 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4680 DRM_INFO("RC6 disabled by BIOS\n");
4681 return 0;
4682 }
4683
456470eb 4684 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4685 if (enable_rc6 >= 0) {
4686 int mask;
4687
58abf1da 4688 if (HAS_RC6p(dev))
e6069ca8
ID		 4689 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4690 INTEL_RC6pp_ENABLE;
4691 else
4692 mask = INTEL_RC6_ENABLE;
4693
4694 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4695 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4696 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4697
4698 return enable_rc6 & mask;
4699 }
2b4e57bd 4700
8bade1ad 4701 if (IS_IVYBRIDGE(dev))
cca84a1f 4702 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4703
4704 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4705}
4706
e6069ca8
ID		 4707int intel_enable_rc6(const struct drm_device *dev)
4708{
4709 return i915.enable_rc6;
4710}
4711
93ee2920 4712static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4713{
93ee2920
TR		 4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715 uint32_t rp_state_cap;
4716 u32 ddcc_status = 0;
4717 int ret;
4718
3280e8b0
BW		 4719 /* All of these values are in units of 50MHz */
4720 dev_priv->rps.cur_freq = 0;
93ee2920 4721 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4722 if (IS_BROXTON(dev)) {
4723 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4724 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4725 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4726 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4727 } else {
4728 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4729 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4730 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4731 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4732 }
4733
3280e8b0
BW		 4734 /* hw_max = RP0 until we check for overclocking */
4735 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4736
93ee2920 4737 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4738 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4739 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4740 ret = sandybridge_pcode_read(dev_priv,
4741 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4742 &ddcc_status);
4743 if (0 == ret)
4744 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4745 clamp_t(u8,
4746 ((ddcc_status >> 8) & 0xff),
4747 dev_priv->rps.min_freq,
4748 dev_priv->rps.max_freq);
93ee2920
TR		 4749 }
4750
ef11bdb3 4751 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4752 /* Store the frequency values in 16.66 MHZ units, which is
4753 the natural hardware unit for SKL */
4754 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4755 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4756 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4757 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4758 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4759 }
4760
aed242ff
CW		 4761 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4762
3280e8b0
BW		 4763 /* Preserve min/max settings in case of re-init */
4764 if (dev_priv->rps.max_freq_softlimit == 0)
4765 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4766
93ee2920
TR		 4767 if (dev_priv->rps.min_freq_softlimit == 0) {
4768 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4769 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4770 max_t(int, dev_priv->rps.efficient_freq,
4771 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4772 else
4773 dev_priv->rps.min_freq_softlimit =
4774 dev_priv->rps.min_freq;
4775 }
3280e8b0
BW		 4776}
4777
b6fef0ef 4778/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4779static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4780{
4781 struct drm_i915_private *dev_priv = dev->dev_private;
4782
4783 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4784
ba1c554c
DL		 4785 gen6_init_rps_frequencies(dev);
4786
23eafea6 4787 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4788 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4789 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4790 return;
4791 }
4792
0beb059a
AG		 4793 /* Program defaults and thresholds for RPS*/
4794 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4795 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4796
4797 /* 1 second timeout*/
4798 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4799 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4800
b6fef0ef 4801 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4802
0beb059a
AG		 4803 /* Leaning on the below call to gen6_set_rps to program/setup the
4804 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4805 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4806 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4807 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4808
4809 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4810}
4811
4812static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4813{
4814 struct drm_i915_private *dev_priv = dev->dev_private;
4815 struct intel_engine_cs *ring;
4816 uint32_t rc6_mask = 0;
4817 int unused;
4818
4819 /* 1a: Software RC state - RC0 */
4820 I915_WRITE(GEN6_RC_STATE, 0);
4821
4822 /* 1b: Get forcewake during program sequence. Although the driver
4823 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4824 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4825
4826 /* 2a: Disable RC states. */
4827 I915_WRITE(GEN6_RC_CONTROL, 0);
4828
4829 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4830
4831 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4832 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4833 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4834 else
4835 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4836 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4837 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4838 for_each_ring(ring, dev_priv, unused)
4839 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4840
4841 if (HAS_GUC_UCODE(dev))
4842 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4843
20e49366 4844 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4845
38c23527
ZW		 4846 /* 2c: Program Coarse Power Gating Policies. */
4847 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4848 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4849
20e49366
ZW		 4850 /* 3a: Enable RC6 */
4851 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4852 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 4853 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 4854 /* WaRsUseTimeoutMode */
e87a005d 4855 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4856 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4857 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4858 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4859 GEN7_RC_CTL_TO_MODE |
4860 rc6_mask);
3e7732a0
SAK		 4861 } else {
4862 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4863 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4864 GEN6_RC_CTL_EI_MODE(1) |
4865 rc6_mask);
3e7732a0 4866 }
20e49366 4867
cb07bae0
SK		 4868 /*
4869 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4870 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4871 */
06e668ac 4872 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4873 I915_WRITE(GEN9_PG_ENABLE, 0);
4874 else
4875 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4876 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4877
59bad947 4878 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4879
4880}
4881
6edee7f3
BW		 4882static void gen8_enable_rps(struct drm_device *dev)
4883{
4884 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4885 struct intel_engine_cs *ring;
93ee2920 4886 uint32_t rc6_mask = 0;
6edee7f3
BW		 4887 int unused;
4888
4889 /* 1a: Software RC state - RC0 */
4890 I915_WRITE(GEN6_RC_STATE, 0);
4891
4892 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4893 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4894 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4895
4896 /* 2a: Disable RC states. */
4897 I915_WRITE(GEN6_RC_CONTROL, 0);
4898
93ee2920
TR		 4899 /* Initialize rps frequencies */
4900 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4901
4902 /* 2b: Program RC6 thresholds.*/
4903 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4904 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4905 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4906 for_each_ring(ring, dev_priv, unused)
4907 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4908 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4909 if (IS_BROADWELL(dev))
4910 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4911 else
4912 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4913
4914 /* 3: Enable RC6 */
4915 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4916 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4917 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4918 if (IS_BROADWELL(dev))
4919 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4920 GEN7_RC_CTL_TO_MODE |
4921 rc6_mask);
4922 else
4923 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4924 GEN6_RC_CTL_EI_MODE(1) |
4925 rc6_mask);
6edee7f3
BW		 4926
4927 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4928 I915_WRITE(GEN6_RPNSWREQ,
4929 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4930 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4931 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4932 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4933 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4934
4935 /* Docs recommend 900MHz, and 300 MHz respectively */
4936 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4937 dev_priv->rps.max_freq_softlimit << 24 |
4938 dev_priv->rps.min_freq_softlimit << 16);
4939
4940 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4941 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4942 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4943 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4944
4945 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4946
4947 /* 5: Enable RPS */
7526ed79
DV		 4948 I915_WRITE(GEN6_RP_CONTROL,
4949 GEN6_RP_MEDIA_TURBO |
4950 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4951 GEN6_RP_MEDIA_IS_GFX |
4952 GEN6_RP_ENABLE |
4953 GEN6_RP_UP_BUSY_AVG |
4954 GEN6_RP_DOWN_IDLE_AVG);
4955
4956 /* 6: Ring frequency + overclocking (our driver does this later */
4957
c7f3153a 4958 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4959 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4960
59bad947 4961 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4962}
4963
79f5b2c7 4964static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4965{
79f5b2c7 4966 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4967 struct intel_engine_cs *ring;
d060c169 4968 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4969 u32 gtfifodbg;
2b4e57bd 4970 int rc6_mode;
42c0526c 4971 int i, ret;
2b4e57bd 4972
4fc688ce 4973 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4974
2b4e57bd
ED		 4975 /* Here begins a magic sequence of register writes to enable
4976 * auto-downclocking.
4977 *
4978 * Perhaps there might be some value in exposing these to
4979 * userspace...
4980 */
4981 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4982
4983 /* Clear the DBG now so we don't confuse earlier errors */
4984 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4985 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4986 I915_WRITE(GTFIFODBG, gtfifodbg);
4987 }
4988
59bad947 4989 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4990
93ee2920
TR		 4991 /* Initialize rps frequencies */
4992 gen6_init_rps_frequencies(dev);
dd0a1aa1 4993
2b4e57bd
ED		 4994 /* disable the counters and set deterministic thresholds */
4995 I915_WRITE(GEN6_RC_CONTROL, 0);
4996
4997 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4998 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4999 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5000 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5001 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5002
b4519513
CW		 5003 for_each_ring(ring, dev_priv, i)
5004 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 5005
5006 I915_WRITE(GEN6_RC_SLEEP, 0);
5007 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 5008 if (IS_IVYBRIDGE(dev))
351aa566
SM		 5009 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5010 else
5011 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5012 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5013 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5014
5a7dc92a 5015 /* Check if we are enabling RC6 */
2b4e57bd
ED		 5016 rc6_mode = intel_enable_rc6(dev_priv->dev);
5017 if (rc6_mode & INTEL_RC6_ENABLE)
5018 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5019
5a7dc92a
ED		 5020 /* We don't use those on Haswell */
5021 if (!IS_HASWELL(dev)) {
5022 if (rc6_mode & INTEL_RC6p_ENABLE)
5023 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5024
5a7dc92a
ED		 5025 if (rc6_mode & INTEL_RC6pp_ENABLE)
5026 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5027 }
2b4e57bd 5028
dc39fff7 5029 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 5030
5031 I915_WRITE(GEN6_RC_CONTROL,
5032 rc6_mask |
5033 GEN6_RC_CTL_EI_MODE(1) |
5034 GEN6_RC_CTL_HW_ENABLE);
5035
dd75fdc8
CW		 5036 /* Power down if completely idle for over 50ms */
5037 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5038 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5039
42c0526c 5040 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5041 if (ret)
42c0526c 5042 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5043
5044 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5045 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5046 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5047 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5048 (pcu_mbox & 0xff) * 50);
b39fb297 5049 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5050 }
5051
dd75fdc8 5052 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5053 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5054
31643d54
BW		 5055 rc6vids = 0;
5056 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5057 if (IS_GEN6(dev) && ret) {
5058 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5059 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5060 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5061 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5062 rc6vids &= 0xffff00;
5063 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5064 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5065 if (ret)
5066 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5067 }
5068
59bad947 5069 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5070}
5071
c2bc2fc5 5072static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5073{
79f5b2c7 5074 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5075 int min_freq = 15;
3ebecd07
CW		 5076 unsigned int gpu_freq;
5077 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5078 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5079 int scaling_factor = 180;
eda79642 5080 struct cpufreq_policy *policy;
2b4e57bd 5081
4fc688ce 5082 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5083
eda79642
BW		 5084 policy = cpufreq_cpu_get(0);
5085 if (policy) {
5086 max_ia_freq = policy->cpuinfo.max_freq;
5087 cpufreq_cpu_put(policy);
5088 } else {
5089 /*
5090 * Default to measured freq if none found, PCU will ensure we
5091 * don't go over
5092 */
2b4e57bd 5093 max_ia_freq = tsc_khz;
eda79642 5094 }
2b4e57bd
ED		 5095
5096 /* Convert from kHz to MHz */
5097 max_ia_freq /= 1000;
5098
153b4b95 5099 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5100 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5101 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5102
ef11bdb3 5103 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5104 /* Convert GT frequency to 50 HZ units */
5105 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5106 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5107 } else {
5108 min_gpu_freq = dev_priv->rps.min_freq;
5109 max_gpu_freq = dev_priv->rps.max_freq;
5110 }
5111
2b4e57bd
ED		 5112 /*
5113 * For each potential GPU frequency, load a ring frequency we'd like
5114 * to use for memory access. We do this by specifying the IA frequency
5115 * the PCU should use as a reference to determine the ring frequency.
5116 */
4c8c7743
AG		 5117 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5118 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5119 unsigned int ia_freq = 0, ring_freq = 0;
5120
ef11bdb3 5121 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5122 /*
5123 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5124 * No floor required for ring frequency on SKL.
5125 */
5126 ring_freq = gpu_freq;
5127 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5128 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5129 ring_freq = max(min_ring_freq, gpu_freq);
5130 } else if (IS_HASWELL(dev)) {
f6aca45c 5131 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5132 ring_freq = max(min_ring_freq, ring_freq);
5133 /* leave ia_freq as the default, chosen by cpufreq */
5134 } else {
5135 /* On older processors, there is no separate ring
5136 * clock domain, so in order to boost the bandwidth
5137 * of the ring, we need to upclock the CPU (ia_freq).
5138 *
5139 * For GPU frequencies less than 750MHz,
5140 * just use the lowest ring freq.
5141 */
5142 if (gpu_freq < min_freq)
5143 ia_freq = 800;
5144 else
5145 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5146 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5147 }
2b4e57bd 5148
42c0526c
BW		 5149 sandybridge_pcode_write(dev_priv,
5150 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5151 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5152 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5153 gpu_freq);
2b4e57bd 5154 }
2b4e57bd
ED		 5155}
5156
c2bc2fc5
ID		 5157void gen6_update_ring_freq(struct drm_device *dev)
5158{
5159 struct drm_i915_private *dev_priv = dev->dev_private;
5160
97d3308a 5161 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5162 return;
5163
5164 mutex_lock(&dev_priv->rps.hw_lock);
5165 __gen6_update_ring_freq(dev);
5166 mutex_unlock(&dev_priv->rps.hw_lock);
5167}
5168
03af2045 5169static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5170{
095acd5f 5171 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5172 u32 val, rp0;
5173
5b5929cb 5174 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5175
5b5929cb
JN		 5176 switch (INTEL_INFO(dev)->eu_total) {
5177 case 8:
5178 /* (2 * 4) config */
5179 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5180 break;
5181 case 12:
5182 /* (2 * 6) config */
5183 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5184 break;
5185 case 16:
5186 /* (2 * 8) config */
5187 default:
5188 /* Setting (2 * 8) Min RP0 for any other combination */
5189 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5190 break;
095acd5f 5191 }
5b5929cb
JN		 5192
5193 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5194
2b6b3a09
D		 5195 return rp0;
5196}
5197
5198static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5199{
5200 u32 val, rpe;
5201
5202 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5203 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5204
5205 return rpe;
5206}
5207
7707df4a
D		 5208static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5209{
5210 u32 val, rp1;
5211
5b5929cb
JN		 5212 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5213 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5214
7707df4a
D		 5215 return rp1;
5216}
5217
f8f2b001
D		 5218static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5219{
5220 u32 val, rp1;
5221
5222 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5223
5224 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5225
5226 return rp1;
5227}
5228
03af2045 5229static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5230{
5231 u32 val, rp0;
5232
64936258 5233 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5234
5235 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5236 /* Clamp to max */
5237 rp0 = min_t(u32, rp0, 0xea);
5238
5239 return rp0;
5240}
5241
5242static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5243{
5244 u32 val, rpe;
5245
64936258 5246 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5247 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5248 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5249 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5250
5251 return rpe;
5252}
5253
03af2045 5254static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5255{
36146035
ID		 5256 u32 val;
5257
5258 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5259 /*
5260 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5261 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5262 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5263 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5264 * to make sure it matches what Punit accepts.
5265 */
5266 return max_t(u32, val, 0xc0);
0a073b84
JB		 5267}
5268
ae48434c
ID		 5269/* Check that the pctx buffer wasn't move under us. */
5270static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5271{
5272 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5273
5274 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5275 dev_priv->vlv_pctx->stolen->start);
5276}
5277
38807746
D		 5278
5279/* Check that the pcbr address is not empty. */
5280static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5281{
5282 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5283
5284 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5285}
5286
5287static void cherryview_setup_pctx(struct drm_device *dev)
5288{
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5290 unsigned long pctx_paddr, paddr;
5291 struct i915_gtt *gtt = &dev_priv->gtt;
5292 u32 pcbr;
5293 int pctx_size = 32*1024;
5294
38807746
D		 5295 pcbr = I915_READ(VLV_PCBR);
5296 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5297 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5298 paddr = (dev_priv->mm.stolen_base +
5299 (gtt->stolen_size - pctx_size));
5300
5301 pctx_paddr = (paddr & (~4095));
5302 I915_WRITE(VLV_PCBR, pctx_paddr);
5303 }
ce611ef8
VS		 5304
5305 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5306}
5307
c9cddffc
JB		 5308static void valleyview_setup_pctx(struct drm_device *dev)
5309{
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311 struct drm_i915_gem_object *pctx;
5312 unsigned long pctx_paddr;
5313 u32 pcbr;
5314 int pctx_size = 24*1024;
5315
ee504898 5316 mutex_lock(&dev->struct_mutex);
17b0c1f7 5317
c9cddffc
JB		 5318 pcbr = I915_READ(VLV_PCBR);
5319 if (pcbr) {
5320 /* BIOS set it up already, grab the pre-alloc'd space */
5321 int pcbr_offset;
5322
5323 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5324 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5325 pcbr_offset,
190d6cd5 5326 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5327 pctx_size);
5328 goto out;
5329 }
5330
ce611ef8
VS		 5331 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5332
c9cddffc
JB		 5333 /*
5334 * From the Gunit register HAS:
5335 * The Gfx driver is expected to program this register and ensure
5336 * proper allocation within Gfx stolen memory. For example, this
5337 * register should be programmed such than the PCBR range does not
5338 * overlap with other ranges, such as the frame buffer, protected
5339 * memory, or any other relevant ranges.
5340 */
5341 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5342 if (!pctx) {
5343 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5344 goto out;
c9cddffc
JB		 5345 }
5346
5347 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5348 I915_WRITE(VLV_PCBR, pctx_paddr);
5349
5350out:
ce611ef8 5351 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5352 dev_priv->vlv_pctx = pctx;
ee504898 5353 mutex_unlock(&dev->struct_mutex);
c9cddffc
JB		 5354}
5355
ae48434c
ID		 5356static void valleyview_cleanup_pctx(struct drm_device *dev)
5357{
5358 struct drm_i915_private *dev_priv = dev->dev_private;
5359
5360 if (WARN_ON(!dev_priv->vlv_pctx))
5361 return;
5362
ee504898 5363 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5364 dev_priv->vlv_pctx = NULL;
5365}
5366
4e80519e
ID		 5367static void valleyview_init_gt_powersave(struct drm_device *dev)
5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5370 u32 val;
4e80519e
ID		 5371
5372 valleyview_setup_pctx(dev);
5373
5374 mutex_lock(&dev_priv->rps.hw_lock);
5375
2bb25c17
VS		 5376 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5377 switch ((val >> 6) & 3) {
5378 case 0:
5379 case 1:
5380 dev_priv->mem_freq = 800;
5381 break;
5382 case 2:
5383 dev_priv->mem_freq = 1066;
5384 break;
5385 case 3:
5386 dev_priv->mem_freq = 1333;
5387 break;
5388 }
80b83b62 5389 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5390
4e80519e
ID		 5391 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5392 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5393 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5394 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5395 dev_priv->rps.max_freq);
5396
5397 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5398 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5399 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5400 dev_priv->rps.efficient_freq);
5401
f8f2b001
D		 5402 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5403 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5404 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5405 dev_priv->rps.rp1_freq);
5406
4e80519e
ID		 5407 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5408 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5409 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5410 dev_priv->rps.min_freq);
5411
aed242ff
CW		 5412 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5413
4e80519e
ID		 5414 /* Preserve min/max settings in case of re-init */
5415 if (dev_priv->rps.max_freq_softlimit == 0)
5416 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5417
5418 if (dev_priv->rps.min_freq_softlimit == 0)
5419 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5420
5421 mutex_unlock(&dev_priv->rps.hw_lock);
5422}
5423
38807746
D		 5424static void cherryview_init_gt_powersave(struct drm_device *dev)
5425{
2b6b3a09 5426 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5427 u32 val;
2b6b3a09 5428
38807746 5429 cherryview_setup_pctx(dev);
2b6b3a09
D		 5430
5431 mutex_lock(&dev_priv->rps.hw_lock);
5432
a580516d 5433 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5434 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5435 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5436
2bb25c17 5437 switch ((val >> 2) & 0x7) {
2bb25c17 5438 case 3:
2bb25c17
VS		 5439 dev_priv->mem_freq = 2000;
5440 break;
bfa7df01 5441 default:
2bb25c17
VS		 5442 dev_priv->mem_freq = 1600;
5443 break;
5444 }
80b83b62 5445 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5446
2b6b3a09
D		 5447 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5448 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5449 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5450 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5451 dev_priv->rps.max_freq);
5452
5453 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5454 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5455 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5456 dev_priv->rps.efficient_freq);
5457
7707df4a
D		 5458 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5459 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5460 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5461 dev_priv->rps.rp1_freq);
5462
5b7c91b7
D		 5463 /* PUnit validated range is only [RPe, RP0] */
5464 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5465 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5466 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5467 dev_priv->rps.min_freq);
5468
1c14762d
VS		 5469 WARN_ONCE((dev_priv->rps.max_freq |
5470 dev_priv->rps.efficient_freq |
5471 dev_priv->rps.rp1_freq |
5472 dev_priv->rps.min_freq) & 1,
5473 "Odd GPU freq values\n");
5474
aed242ff
CW		 5475 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5476
2b6b3a09
D		 5477 /* Preserve min/max settings in case of re-init */
5478 if (dev_priv->rps.max_freq_softlimit == 0)
5479 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5480
5481 if (dev_priv->rps.min_freq_softlimit == 0)
5482 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5483
5484 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5485}
5486
4e80519e
ID		 5487static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5488{
5489 valleyview_cleanup_pctx(dev);
5490}
5491
38807746
D		 5492static void cherryview_enable_rps(struct drm_device *dev)
5493{
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495 struct intel_engine_cs *ring;
2b6b3a09 5496 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5497 int i;
5498
5499 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5500
5501 gtfifodbg = I915_READ(GTFIFODBG);
5502 if (gtfifodbg) {
5503 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5504 gtfifodbg);
5505 I915_WRITE(GTFIFODBG, gtfifodbg);
5506 }
5507
5508 cherryview_check_pctx(dev_priv);
5509
5510 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5511 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5512 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5513
160614a2
VS		 5514 /* Disable RC states. */
5515 I915_WRITE(GEN6_RC_CONTROL, 0);
5516
38807746
D		 5517 /* 2a: Program RC6 thresholds.*/
5518 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5519 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5520 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5521
5522 for_each_ring(ring, dev_priv, i)
5523 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5524 I915_WRITE(GEN6_RC_SLEEP, 0);
5525
f4f71c7d
D		 5526 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5527 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5528
5529 /* allows RC6 residency counter to work */
5530 I915_WRITE(VLV_COUNTER_CONTROL,
5531 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5532 VLV_MEDIA_RC6_COUNT_EN |
5533 VLV_RENDER_RC6_COUNT_EN));
5534
5535 /* For now we assume BIOS is allocating and populating the PCBR */
5536 pcbr = I915_READ(VLV_PCBR);
5537
38807746
D		 5538 /* 3: Enable RC6 */
5539 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5540 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5541 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5542
5543 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5544
2b6b3a09 5545 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5546 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5547 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5548 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5549 I915_WRITE(GEN6_RP_UP_EI, 66000);
5550 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5551
5552 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5553
5554 /* 5: Enable RPS */
5555 I915_WRITE(GEN6_RP_CONTROL,
5556 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5557 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5558 GEN6_RP_ENABLE |
5559 GEN6_RP_UP_BUSY_AVG |
5560 GEN6_RP_DOWN_IDLE_AVG);
5561
3ef62342
D		 5562 /* Setting Fixed Bias */
5563 val = VLV_OVERRIDE_EN |
5564 VLV_SOC_TDP_EN |
5565 CHV_BIAS_CPU_50_SOC_50;
5566 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5567
2b6b3a09
D		 5568 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5569
8d40c3ae
VS		 5570 /* RPS code assumes GPLL is used */
5571 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5572
742f491d 5573 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5574 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5575
5576 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5577 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5578 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5579 dev_priv->rps.cur_freq);
5580
5581 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5582 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5583 dev_priv->rps.efficient_freq);
5584
5585 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5586
59bad947 5587 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5588}
5589
0a073b84
JB		 5590static void valleyview_enable_rps(struct drm_device *dev)
5591{
5592 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5593 struct intel_engine_cs *ring;
2a5913a8 5594 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5595 int i;
5596
5597 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5598
ae48434c
ID		 5599 valleyview_check_pctx(dev_priv);
5600
0a073b84 5601 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5602 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5603 gtfifodbg);
0a073b84
JB		 5604 I915_WRITE(GTFIFODBG, gtfifodbg);
5605 }
5606
c8d9a590 5607 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5608 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5609
160614a2
VS		 5610 /* Disable RC states. */
5611 I915_WRITE(GEN6_RC_CONTROL, 0);
5612
cad725fe 5613 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5614 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5615 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5616 I915_WRITE(GEN6_RP_UP_EI, 66000);
5617 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5618
5619 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5620
5621 I915_WRITE(GEN6_RP_CONTROL,
5622 GEN6_RP_MEDIA_TURBO |
5623 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5624 GEN6_RP_MEDIA_IS_GFX |
5625 GEN6_RP_ENABLE |
5626 GEN6_RP_UP_BUSY_AVG |
5627 GEN6_RP_DOWN_IDLE_CONT);
5628
5629 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5630 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5631 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5632
5633 for_each_ring(ring, dev_priv, i)
5634 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5635
2f0aa304 5636 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5637
5638 /* allows RC6 residency counter to work */
49798eb2 5639 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5640 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5641 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5642 VLV_MEDIA_RC6_COUNT_EN |
5643 VLV_RENDER_RC6_COUNT_EN));
31685c25 5644
a2b23fe0 5645 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5646 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5647
5648 intel_print_rc6_info(dev, rc6_mode);
5649
a2b23fe0 5650 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5651
3ef62342
D		 5652 /* Setting Fixed Bias */
5653 val = VLV_OVERRIDE_EN |
5654 VLV_SOC_TDP_EN |
5655 VLV_BIAS_CPU_125_SOC_875;
5656 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5657
64936258 5658 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5659
8d40c3ae
VS		 5660 /* RPS code assumes GPLL is used */
5661 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5662
742f491d 5663 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5664 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5665
b39fb297 5666 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5667 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5668 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5669 dev_priv->rps.cur_freq);
0a073b84 5670
73008b98 5671 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5672 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5673 dev_priv->rps.efficient_freq);
0a073b84 5674
b39fb297 5675 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5676
59bad947 5677 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5678}
5679
dde18883
ED		 5680static unsigned long intel_pxfreq(u32 vidfreq)
5681{
5682 unsigned long freq;
5683 int div = (vidfreq & 0x3f0000) >> 16;
5684 int post = (vidfreq & 0x3000) >> 12;
5685 int pre = (vidfreq & 0x7);
5686
5687 if (!pre)
5688 return 0;
5689
5690 freq = ((div * 133333) / ((1<<post) * pre));
5691
5692 return freq;
5693}
5694
eb48eb00
DV		 5695static const struct cparams {
5696 u16 i;
5697 u16 t;
5698 u16 m;
5699 u16 c;
5700} cparams[] = {
5701 { 1, 1333, 301, 28664 },
5702 { 1, 1066, 294, 24460 },
5703 { 1, 800, 294, 25192 },
5704 { 0, 1333, 276, 27605 },
5705 { 0, 1066, 276, 27605 },
5706 { 0, 800, 231, 23784 },
5707};
5708
f531dcb2 5709static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5710{
5711 u64 total_count, diff, ret;
5712 u32 count1, count2, count3, m = 0, c = 0;
5713 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5714 int i;
5715
02d71956
DV		 5716 assert_spin_locked(&mchdev_lock);
5717
20e4d407 5718 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5719
5720 /* Prevent division-by-zero if we are asking too fast.
5721 * Also, we don't get interesting results if we are polling
5722 * faster than once in 10ms, so just return the saved value
5723 * in such cases.
5724 */
5725 if (diff1 <= 10)
20e4d407 5726 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5727
5728 count1 = I915_READ(DMIEC);
5729 count2 = I915_READ(DDREC);
5730 count3 = I915_READ(CSIEC);
5731
5732 total_count = count1 + count2 + count3;
5733
5734 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5735 if (total_count < dev_priv->ips.last_count1) {
5736 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5737 diff += total_count;
5738 } else {
20e4d407 5739 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5740 }
5741
5742 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5743 if (cparams[i].i == dev_priv->ips.c_m &&
5744 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5745 m = cparams[i].m;
5746 c = cparams[i].c;
5747 break;
5748 }
5749 }
5750
5751 diff = div_u64(diff, diff1);
5752 ret = ((m * diff) + c);
5753 ret = div_u64(ret, 10);
5754
20e4d407
DV		 5755 dev_priv->ips.last_count1 = total_count;
5756 dev_priv->ips.last_time1 = now;
eb48eb00 5757
20e4d407 5758 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5759
5760 return ret;
5761}
5762
f531dcb2
CW		 5763unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5764{
3d13ef2e 5765 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5766 unsigned long val;
5767
3d13ef2e 5768 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5769 return 0;
5770
5771 spin_lock_irq(&mchdev_lock);
5772
5773 val = __i915_chipset_val(dev_priv);
5774
5775 spin_unlock_irq(&mchdev_lock);
5776
5777 return val;
5778}
5779
eb48eb00
DV		 5780unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5781{
5782 unsigned long m, x, b;
5783 u32 tsfs;
5784
5785 tsfs = I915_READ(TSFS);
5786
5787 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5788 x = I915_READ8(TR1);
5789
5790 b = tsfs & TSFS_INTR_MASK;
5791
5792 return ((m * x) / 127) - b;
5793}
5794
d972d6ee
MK		 5795static int _pxvid_to_vd(u8 pxvid)
5796{
5797 if (pxvid == 0)
5798 return 0;
5799
5800 if (pxvid >= 8 && pxvid < 31)
5801 pxvid = 31;
5802
5803 return (pxvid + 2) * 125;
5804}
5805
5806static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5807{
3d13ef2e 5808 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5809 const int vd = _pxvid_to_vd(pxvid);
5810 const int vm = vd - 1125;
5811
3d13ef2e 5812 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5813 return vm > 0 ? vm : 0;
5814
5815 return vd;
eb48eb00
DV		 5816}
5817
02d71956 5818static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5819{
5ed0bdf2 5820 u64 now, diff, diffms;
eb48eb00
DV		 5821 u32 count;
5822
02d71956 5823 assert_spin_locked(&mchdev_lock);
eb48eb00 5824
5ed0bdf2
TG		 5825 now = ktime_get_raw_ns();
5826 diffms = now - dev_priv->ips.last_time2;
5827 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5828
5829 /* Don't divide by 0 */
eb48eb00
DV		 5830 if (!diffms)
5831 return;
5832
5833 count = I915_READ(GFXEC);
5834
20e4d407
DV		 5835 if (count < dev_priv->ips.last_count2) {
5836 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5837 diff += count;
5838 } else {
20e4d407 5839 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5840 }
5841
20e4d407
DV		 5842 dev_priv->ips.last_count2 = count;
5843 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5844
5845 /* More magic constants... */
5846 diff = diff * 1181;
5847 diff = div_u64(diff, diffms * 10);
20e4d407 5848 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5849}
5850
02d71956
DV		 5851void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5852{
3d13ef2e
DL		 5853 struct drm_device *dev = dev_priv->dev;
5854
5855 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5856 return;
5857
9270388e 5858 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5859
5860 __i915_update_gfx_val(dev_priv);
5861
9270388e 5862 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5863}
5864
f531dcb2 5865static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5866{
5867 unsigned long t, corr, state1, corr2, state2;
5868 u32 pxvid, ext_v;
5869
02d71956
DV		 5870 assert_spin_locked(&mchdev_lock);
5871
616847e7 5872 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5873 pxvid = (pxvid >> 24) & 0x7f;
5874 ext_v = pvid_to_extvid(dev_priv, pxvid);
5875
5876 state1 = ext_v;
5877
5878 t = i915_mch_val(dev_priv);
5879
5880 /* Revel in the empirically derived constants */
5881
5882 /* Correction factor in 1/100000 units */
5883 if (t > 80)
5884 corr = ((t * 2349) + 135940);
5885 else if (t >= 50)
5886 corr = ((t * 964) + 29317);
5887 else /* < 50 */
5888 corr = ((t * 301) + 1004);
5889
5890 corr = corr * ((150142 * state1) / 10000 - 78642);
5891 corr /= 100000;
20e4d407 5892 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5893
5894 state2 = (corr2 * state1) / 10000;
5895 state2 /= 100; /* convert to mW */
5896
02d71956 5897 __i915_update_gfx_val(dev_priv);
eb48eb00 5898
20e4d407 5899 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5900}
5901
f531dcb2
CW		 5902unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5903{
3d13ef2e 5904 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5905 unsigned long val;
5906
3d13ef2e 5907 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5908 return 0;
5909
5910 spin_lock_irq(&mchdev_lock);
5911
5912 val = __i915_gfx_val(dev_priv);
5913
5914 spin_unlock_irq(&mchdev_lock);
5915
5916 return val;
5917}
5918
eb48eb00
DV		 5919/**
5920 * i915_read_mch_val - return value for IPS use
5921 *
5922 * Calculate and return a value for the IPS driver to use when deciding whether
5923 * we have thermal and power headroom to increase CPU or GPU power budget.
5924 */
5925unsigned long i915_read_mch_val(void)
5926{
5927 struct drm_i915_private *dev_priv;
5928 unsigned long chipset_val, graphics_val, ret = 0;
5929
9270388e 5930 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5931 if (!i915_mch_dev)
5932 goto out_unlock;
5933 dev_priv = i915_mch_dev;
5934
f531dcb2
CW		 5935 chipset_val = __i915_chipset_val(dev_priv);
5936 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5937
5938 ret = chipset_val + graphics_val;
5939
5940out_unlock:
9270388e 5941 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5942
5943 return ret;
5944}
5945EXPORT_SYMBOL_GPL(i915_read_mch_val);
5946
5947/**
5948 * i915_gpu_raise - raise GPU frequency limit
5949 *
5950 * Raise the limit; IPS indicates we have thermal headroom.
5951 */
5952bool i915_gpu_raise(void)
5953{
5954 struct drm_i915_private *dev_priv;
5955 bool ret = true;
5956
9270388e 5957 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5958 if (!i915_mch_dev) {
5959 ret = false;
5960 goto out_unlock;
5961 }
5962 dev_priv = i915_mch_dev;
5963
20e4d407
DV		 5964 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5965 dev_priv->ips.max_delay--;
eb48eb00
DV		 5966
5967out_unlock:
9270388e 5968 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5969
5970 return ret;
5971}
5972EXPORT_SYMBOL_GPL(i915_gpu_raise);
5973
5974/**
5975 * i915_gpu_lower - lower GPU frequency limit
5976 *
5977 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5978 * frequency maximum.
5979 */
5980bool i915_gpu_lower(void)
5981{
5982 struct drm_i915_private *dev_priv;
5983 bool ret = true;
5984
9270388e 5985 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5986 if (!i915_mch_dev) {
5987 ret = false;
5988 goto out_unlock;
5989 }
5990 dev_priv = i915_mch_dev;
5991
20e4d407
DV		 5992 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5993 dev_priv->ips.max_delay++;
eb48eb00
DV		 5994
5995out_unlock:
9270388e 5996 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5997
5998 return ret;
5999}
6000EXPORT_SYMBOL_GPL(i915_gpu_lower);
6001
6002/**
6003 * i915_gpu_busy - indicate GPU business to IPS
6004 *
6005 * Tell the IPS driver whether or not the GPU is busy.
6006 */
6007bool i915_gpu_busy(void)
6008{
6009 struct drm_i915_private *dev_priv;
a4872ba6 6010 struct intel_engine_cs *ring;
eb48eb00 6011 bool ret = false;
f047e395 6012 int i;
eb48eb00 6013
9270388e 6014 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6015 if (!i915_mch_dev)
6016 goto out_unlock;
6017 dev_priv = i915_mch_dev;
6018
f047e395
CW		 6019 for_each_ring(ring, dev_priv, i)
6020 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 6021
6022out_unlock:
9270388e 6023 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6024
6025 return ret;
6026}
6027EXPORT_SYMBOL_GPL(i915_gpu_busy);
6028
6029/**
6030 * i915_gpu_turbo_disable - disable graphics turbo
6031 *
6032 * Disable graphics turbo by resetting the max frequency and setting the
6033 * current frequency to the default.
6034 */
6035bool i915_gpu_turbo_disable(void)
6036{
6037 struct drm_i915_private *dev_priv;
6038 bool ret = true;
6039
9270388e 6040 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6041 if (!i915_mch_dev) {
6042 ret = false;
6043 goto out_unlock;
6044 }
6045 dev_priv = i915_mch_dev;
6046
20e4d407 6047 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6048
20e4d407 6049 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6050 ret = false;
6051
6052out_unlock:
9270388e 6053 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6054
6055 return ret;
6056}
6057EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6058
6059/**
6060 * Tells the intel_ips driver that the i915 driver is now loaded, if
6061 * IPS got loaded first.
6062 *
6063 * This awkward dance is so that neither module has to depend on the
6064 * other in order for IPS to do the appropriate communication of
6065 * GPU turbo limits to i915.
6066 */
6067static void
6068ips_ping_for_i915_load(void)
6069{
6070 void (*link)(void);
6071
6072 link = symbol_get(ips_link_to_i915_driver);
6073 if (link) {
6074 link();
6075 symbol_put(ips_link_to_i915_driver);
6076 }
6077}
6078
6079void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6080{
02d71956
DV		 6081 /* We only register the i915 ips part with intel-ips once everything is
6082 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6083 spin_lock_irq(&mchdev_lock);
eb48eb00 6084 i915_mch_dev = dev_priv;
9270388e 6085 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6086
6087 ips_ping_for_i915_load();
6088}
6089
6090void intel_gpu_ips_teardown(void)
6091{
9270388e 6092 spin_lock_irq(&mchdev_lock);
eb48eb00 6093 i915_mch_dev = NULL;
9270388e 6094 spin_unlock_irq(&mchdev_lock);
eb48eb00 6095}
76c3552f 6096
8090c6b9 6097static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6098{
6099 struct drm_i915_private *dev_priv = dev->dev_private;
6100 u32 lcfuse;
6101 u8 pxw[16];
6102 int i;
6103
6104 /* Disable to program */
6105 I915_WRITE(ECR, 0);
6106 POSTING_READ(ECR);
6107
6108 /* Program energy weights for various events */
6109 I915_WRITE(SDEW, 0x15040d00);
6110 I915_WRITE(CSIEW0, 0x007f0000);
6111 I915_WRITE(CSIEW1, 0x1e220004);
6112 I915_WRITE(CSIEW2, 0x04000004);
6113
6114 for (i = 0; i < 5; i++)
616847e7 6115 I915_WRITE(PEW(i), 0);
dde18883 6116 for (i = 0; i < 3; i++)
616847e7 6117 I915_WRITE(DEW(i), 0);
dde18883
ED		 6118
6119 /* Program P-state weights to account for frequency power adjustment */
6120 for (i = 0; i < 16; i++) {
616847e7 6121 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6122 unsigned long freq = intel_pxfreq(pxvidfreq);
6123 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6124 PXVFREQ_PX_SHIFT;
6125 unsigned long val;
6126
6127 val = vid * vid;
6128 val *= (freq / 1000);
6129 val *= 255;
6130 val /= (127*127*900);
6131 if (val > 0xff)
6132 DRM_ERROR("bad pxval: %ld\n", val);
6133 pxw[i] = val;
6134 }
6135 /* Render standby states get 0 weight */
6136 pxw[14] = 0;
6137 pxw[15] = 0;
6138
6139 for (i = 0; i < 4; i++) {
6140 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6141 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6142 I915_WRITE(PXW(i), val);
dde18883
ED		 6143 }
6144
6145 /* Adjust magic regs to magic values (more experimental results) */
6146 I915_WRITE(OGW0, 0);
6147 I915_WRITE(OGW1, 0);
6148 I915_WRITE(EG0, 0x00007f00);
6149 I915_WRITE(EG1, 0x0000000e);
6150 I915_WRITE(EG2, 0x000e0000);
6151 I915_WRITE(EG3, 0x68000300);
6152 I915_WRITE(EG4, 0x42000000);
6153 I915_WRITE(EG5, 0x00140031);
6154 I915_WRITE(EG6, 0);
6155 I915_WRITE(EG7, 0);
6156
6157 for (i = 0; i < 8; i++)
616847e7 6158 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6159
6160 /* Enable PMON + select events */
6161 I915_WRITE(ECR, 0x80000019);
6162
6163 lcfuse = I915_READ(LCFUSE02);
6164
20e4d407 6165 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6166}
6167
ae48434c
ID		 6168void intel_init_gt_powersave(struct drm_device *dev)
6169{
b268c699
ID		 6170 struct drm_i915_private *dev_priv = dev->dev_private;
6171
b268c699
ID		 6172 /*
6173 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6174 * requirement.
6175 */
6176 if (!i915.enable_rc6) {
6177 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6178 intel_runtime_pm_get(dev_priv);
6179 }
e6069ca8 6180
38807746
D		 6181 if (IS_CHERRYVIEW(dev))
6182 cherryview_init_gt_powersave(dev);
6183 else if (IS_VALLEYVIEW(dev))
4e80519e 6184 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6185}
6186
6187void intel_cleanup_gt_powersave(struct drm_device *dev)
6188{
b268c699
ID		 6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190
38807746
D		 6191 if (IS_CHERRYVIEW(dev))
6192 return;
6193 else if (IS_VALLEYVIEW(dev))
4e80519e 6194 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6195
6196 if (!i915.enable_rc6)
6197 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6198}
6199
dbea3cea
ID		 6200static void gen6_suspend_rps(struct drm_device *dev)
6201{
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203
6204 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6205
4c2a8897 6206 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6207}
6208
156c7ca0
JB		 6209/**
6210 * intel_suspend_gt_powersave - suspend PM work and helper threads
6211 * @dev: drm device
6212 *
6213 * We don't want to disable RC6 or other features here, we just want
6214 * to make sure any work we've queued has finished and won't bother
6215 * us while we're suspended.
6216 */
6217void intel_suspend_gt_powersave(struct drm_device *dev)
6218{
6219 struct drm_i915_private *dev_priv = dev->dev_private;
6220
d4d70aa5
ID		 6221 if (INTEL_INFO(dev)->gen < 6)
6222 return;
6223
dbea3cea 6224 gen6_suspend_rps(dev);
b47adc17
D		 6225
6226 /* Force GPU to min freq during suspend */
6227 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6228}
6229
8090c6b9
DV		 6230void intel_disable_gt_powersave(struct drm_device *dev)
6231{
1a01ab3b
JB		 6232 struct drm_i915_private *dev_priv = dev->dev_private;
6233
930ebb46 6234 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6235 ironlake_disable_drps(dev);
38807746 6236 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6237 intel_suspend_gt_powersave(dev);
e494837a 6238
4fc688ce 6239 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6240 if (INTEL_INFO(dev)->gen >= 9)
6241 gen9_disable_rps(dev);
6242 else if (IS_CHERRYVIEW(dev))
38807746
D		 6243 cherryview_disable_rps(dev);
6244 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6245 valleyview_disable_rps(dev);
6246 else
6247 gen6_disable_rps(dev);
e534770a 6248
c0951f0c 6249 dev_priv->rps.enabled = false;
4fc688ce 6250 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6251 }
8090c6b9
DV		 6252}
6253
1a01ab3b
JB		 6254static void intel_gen6_powersave_work(struct work_struct *work)
6255{
6256 struct drm_i915_private *dev_priv =
6257 container_of(work, struct drm_i915_private,
6258 rps.delayed_resume_work.work);
6259 struct drm_device *dev = dev_priv->dev;
6260
4fc688ce 6261 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6262
4c2a8897 6263 gen6_reset_rps_interrupts(dev);
3cc134e3 6264
38807746
D		 6265 if (IS_CHERRYVIEW(dev)) {
6266 cherryview_enable_rps(dev);
6267 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6268 valleyview_enable_rps(dev);
20e49366 6269 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6270 gen9_enable_rc6(dev);
20e49366 6271 gen9_enable_rps(dev);
ef11bdb3 6272 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6273 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6274 } else if (IS_BROADWELL(dev)) {
6275 gen8_enable_rps(dev);
c2bc2fc5 6276 __gen6_update_ring_freq(dev);
0a073b84
JB		 6277 } else {
6278 gen6_enable_rps(dev);
c2bc2fc5 6279 __gen6_update_ring_freq(dev);
0a073b84 6280 }
aed242ff
CW		 6281
6282 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6283 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6284
6285 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6286 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6287
c0951f0c 6288 dev_priv->rps.enabled = true;
3cc134e3 6289
4c2a8897 6290 gen6_enable_rps_interrupts(dev);
3cc134e3 6291
4fc688ce 6292 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6293
6294 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6295}
6296
8090c6b9
DV		 6297void intel_enable_gt_powersave(struct drm_device *dev)
6298{
1a01ab3b
JB		 6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300
f61018b1
YZ		 6301 /* Powersaving is controlled by the host when inside a VM */
6302 if (intel_vgpu_active(dev))
6303 return;
6304
8090c6b9
DV		 6305 if (IS_IRONLAKE_M(dev)) {
6306 ironlake_enable_drps(dev);
84f1b20f 6307 mutex_lock(&dev->struct_mutex);
8090c6b9 6308 intel_init_emon(dev);
dc1d0136 6309 mutex_unlock(&dev->struct_mutex);
38807746 6310 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6311 /*
6312 * PCU communication is slow and this doesn't need to be
6313 * done at any specific time, so do this out of our fast path
6314 * to make resume and init faster.
c6df39b5
ID		 6315 *
6316 * We depend on the HW RC6 power context save/restore
6317 * mechanism when entering D3 through runtime PM suspend. So
6318 * disable RPM until RPS/RC6 is properly setup. We can only
6319 * get here via the driver load/system resume/runtime resume
6320 * paths, so the _noresume version is enough (and in case of
6321 * runtime resume it's necessary).
1a01ab3b 6322 */
c6df39b5
ID		 6323 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6324 round_jiffies_up_relative(HZ)))
6325 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6326 }
6327}
6328
c6df39b5
ID		 6329void intel_reset_gt_powersave(struct drm_device *dev)
6330{
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332
dbea3cea
ID		 6333 if (INTEL_INFO(dev)->gen < 6)
6334 return;
6335
6336 gen6_suspend_rps(dev);
c6df39b5 6337 dev_priv->rps.enabled = false;
c6df39b5
ID		 6338}
6339
3107bd48
DV		 6340static void ibx_init_clock_gating(struct drm_device *dev)
6341{
6342 struct drm_i915_private *dev_priv = dev->dev_private;
6343
6344 /*
6345 * On Ibex Peak and Cougar Point, we need to disable clock
6346 * gating for the panel power sequencer or it will fail to
6347 * start up when no ports are active.
6348 */
6349 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6350}
6351
0e088b8f
VS		 6352static void g4x_disable_trickle_feed(struct drm_device *dev)
6353{
6354 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6355 enum pipe pipe;
0e088b8f 6356
055e393f 6357 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6358 I915_WRITE(DSPCNTR(pipe),
6359 I915_READ(DSPCNTR(pipe)) |
6360 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6361
6362 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6363 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6364 }
6365}
6366
017636cc
VS		 6367static void ilk_init_lp_watermarks(struct drm_device *dev)
6368{
6369 struct drm_i915_private *dev_priv = dev->dev_private;
6370
6371 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6372 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6373 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6374
6375 /*
6376 * Don't touch WM1S_LP_EN here.
6377 * Doing so could cause underruns.
6378 */
6379}
6380
1fa61106 6381static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6382{
6383 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6384 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6385
f1e8fa56
DL		 6386 /*
6387 * Required for FBC
6388 * WaFbcDisableDpfcClockGating:ilk
6389 */
4d47e4f5
DL		 6390 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6391 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6392 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6393
6394 I915_WRITE(PCH_3DCGDIS0,
6395 MARIUNIT_CLOCK_GATE_DISABLE |
6396 SVSMUNIT_CLOCK_GATE_DISABLE);
6397 I915_WRITE(PCH_3DCGDIS1,
6398 VFMUNIT_CLOCK_GATE_DISABLE);
6399
6f1d69b0
ED		 6400 /*
6401 * According to the spec the following bits should be set in
6402 * order to enable memory self-refresh
6403 * The bit 22/21 of 0x42004
6404 * The bit 5 of 0x42020
6405 * The bit 15 of 0x45000
6406 */
6407 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6408 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6409 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6410 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6411 I915_WRITE(DISP_ARB_CTL,
6412 (I915_READ(DISP_ARB_CTL) |
6413 DISP_FBC_WM_DIS));
017636cc
VS		 6414
6415 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6416
6417 /*
6418 * Based on the document from hardware guys the following bits
6419 * should be set unconditionally in order to enable FBC.
6420 * The bit 22 of 0x42000
6421 * The bit 22 of 0x42004
6422 * The bit 7,8,9 of 0x42020.
6423 */
6424 if (IS_IRONLAKE_M(dev)) {
4bb35334 6425 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6426 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6427 I915_READ(ILK_DISPLAY_CHICKEN1) |
6428 ILK_FBCQ_DIS);
6429 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6430 I915_READ(ILK_DISPLAY_CHICKEN2) |
6431 ILK_DPARB_GATE);
6f1d69b0
ED		 6432 }
6433
4d47e4f5
DL		 6434 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6435
6f1d69b0
ED		 6436 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6437 I915_READ(ILK_DISPLAY_CHICKEN2) |
6438 ILK_ELPIN_409_SELECT);
6439 I915_WRITE(_3D_CHICKEN2,
6440 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6441 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6442
ecdb4eb7 6443 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6444 I915_WRITE(CACHE_MODE_0,
6445 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6446
4e04632e
AG		 6447 /* WaDisable_RenderCache_OperationalFlush:ilk */
6448 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6449
0e088b8f 6450 g4x_disable_trickle_feed(dev);
bdad2b2f 6451
3107bd48
DV		 6452 ibx_init_clock_gating(dev);
6453}
6454
6455static void cpt_init_clock_gating(struct drm_device *dev)
6456{
6457 struct drm_i915_private *dev_priv = dev->dev_private;
6458 int pipe;
3f704fa2 6459 uint32_t val;
3107bd48
DV		 6460
6461 /*
6462 * On Ibex Peak and Cougar Point, we need to disable clock
6463 * gating for the panel power sequencer or it will fail to
6464 * start up when no ports are active.
6465 */
cd664078
JB		 6466 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6467 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6468 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6469 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6470 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6471 /* The below fixes the weird display corruption, a few pixels shifted
6472 * downward, on (only) LVDS of some HP laptops with IVY.
6473 */
055e393f 6474 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6475 val = I915_READ(TRANS_CHICKEN2(pipe));
6476 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6477 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6478 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6479 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6480 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6481 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6482 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6483 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6484 }
3107bd48 6485 /* WADP0ClockGatingDisable */
055e393f 6486 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6487 I915_WRITE(TRANS_CHICKEN1(pipe),
6488 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6489 }
6f1d69b0
ED		 6490}
6491
1d7aaa0c
DV		 6492static void gen6_check_mch_setup(struct drm_device *dev)
6493{
6494 struct drm_i915_private *dev_priv = dev->dev_private;
6495 uint32_t tmp;
6496
6497 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6498 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6499 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6500 tmp);
1d7aaa0c
DV		 6501}
6502
1fa61106 6503static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6504{
6505 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6506 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6507
231e54f6 6508 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6509
6510 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6511 I915_READ(ILK_DISPLAY_CHICKEN2) |
6512 ILK_ELPIN_409_SELECT);
6513
ecdb4eb7 6514 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6515 I915_WRITE(_3D_CHICKEN,
6516 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6517
4e04632e
AG		 6518 /* WaDisable_RenderCache_OperationalFlush:snb */
6519 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6520
8d85d272
VS		 6521 /*
6522 * BSpec recoomends 8x4 when MSAA is used,
6523 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6524 *
6525 * Note that PS/WM thread counts depend on the WIZ hashing
6526 * disable bit, which we don't touch here, but it's good
6527 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6528 */
6529 I915_WRITE(GEN6_GT_MODE,
98533251 6530 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6531
017636cc 6532 ilk_init_lp_watermarks(dev);
6f1d69b0 6533
6f1d69b0 6534 I915_WRITE(CACHE_MODE_0,
50743298 6535 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6536
6537 I915_WRITE(GEN6_UCGCTL1,
6538 I915_READ(GEN6_UCGCTL1) |
6539 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6540 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6541
6542 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6543 * gating disable must be set. Failure to set it results in
6544 * flickering pixels due to Z write ordering failures after
6545 * some amount of runtime in the Mesa "fire" demo, and Unigine
6546 * Sanctuary and Tropics, and apparently anything else with
6547 * alpha test or pixel discard.
6548 *
6549 * According to the spec, bit 11 (RCCUNIT) must also be set,
6550 * but we didn't debug actual testcases to find it out.
0f846f81 6551 *
ef59318c
VS		 6552 * WaDisableRCCUnitClockGating:snb
6553 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6554 */
6555 I915_WRITE(GEN6_UCGCTL2,
6556 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6557 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6558
5eb146dd 6559 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6560 I915_WRITE(_3D_CHICKEN3,
6561 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6562
e927ecde
VS		 6563 /*
6564 * Bspec says:
6565 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6566 * 3DSTATE_SF number of SF output attributes is more than 16."
6567 */
6568 I915_WRITE(_3D_CHICKEN3,
6569 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6570
6f1d69b0
ED		 6571 /*
6572 * According to the spec the following bits should be
6573 * set in order to enable memory self-refresh and fbc:
6574 * The bit21 and bit22 of 0x42000
6575 * The bit21 and bit22 of 0x42004
6576 * The bit5 and bit7 of 0x42020
6577 * The bit14 of 0x70180
6578 * The bit14 of 0x71180
4bb35334
DL		 6579 *
6580 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6581 */
6582 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6583 I915_READ(ILK_DISPLAY_CHICKEN1) |
6584 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6585 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6586 I915_READ(ILK_DISPLAY_CHICKEN2) |
6587 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6588 I915_WRITE(ILK_DSPCLK_GATE_D,
6589 I915_READ(ILK_DSPCLK_GATE_D) |
6590 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6591 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6592
0e088b8f 6593 g4x_disable_trickle_feed(dev);
f8f2ac9a 6594
3107bd48 6595 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6596
6597 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6598}
6599
6600static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6601{
6602 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6603
3aad9059 6604 /*
46680e0a 6605 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6606 *
6607 * This actually overrides the dispatch
6608 * mode for all thread types.
6609 */
6f1d69b0
ED		 6610 reg &= ~GEN7_FF_SCHED_MASK;
6611 reg |= GEN7_FF_TS_SCHED_HW;
6612 reg |= GEN7_FF_VS_SCHED_HW;
6613 reg |= GEN7_FF_DS_SCHED_HW;
6614
6615 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6616}
6617
17a303ec
PZ		 6618static void lpt_init_clock_gating(struct drm_device *dev)
6619{
6620 struct drm_i915_private *dev_priv = dev->dev_private;
6621
6622 /*
6623 * TODO: this bit should only be enabled when really needed, then
6624 * disabled when not needed anymore in order to save power.
6625 */
c2699524 6626 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6627 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6628 I915_READ(SOUTH_DSPCLK_GATE_D) |
6629 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6630
6631 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6632 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6633 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6634 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6635}
6636
7d708ee4
ID		 6637static void lpt_suspend_hw(struct drm_device *dev)
6638{
6639 struct drm_i915_private *dev_priv = dev->dev_private;
6640
c2699524 6641 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6642 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6643
6644 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6645 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6646 }
6647}
6648
47c2bd97 6649static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6650{
6651 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6652 enum pipe pipe;
4d487cff 6653 uint32_t misccpctl;
1020a5c2 6654
7ad0dbab 6655 ilk_init_lp_watermarks(dev);
50ed5fbd 6656
ab57fff1 6657 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6658 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6659
ab57fff1 6660 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6661 I915_WRITE(CHICKEN_PAR1_1,
6662 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6663
ab57fff1 6664 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6665 for_each_pipe(dev_priv, pipe) {
07d27e20 6666 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6667 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6668 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6669 }
63801f21 6670
ab57fff1
BW		 6671 /* WaVSRefCountFullforceMissDisable:bdw */
6672 /* WaDSRefCountFullforceMissDisable:bdw */
6673 I915_WRITE(GEN7_FF_THREAD_MODE,
6674 I915_READ(GEN7_FF_THREAD_MODE) &
6675 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6676
295e8bb7
VS		 6677 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6678 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6679
6680 /* WaDisableSDEUnitClockGating:bdw */
6681 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6682 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6683
4d487cff
VS		 6684 /*
6685 * WaProgramL3SqcReg1Default:bdw
6686 * WaTempDisableDOPClkGating:bdw
6687 */
6688 misccpctl = I915_READ(GEN7_MISCCPCTL);
6689 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6690 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6691 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6692
6d50b065
VS		 6693 /*
6694 * WaGttCachingOffByDefault:bdw
6695 * GTT cache may not work with big pages, so if those
6696 * are ever enabled GTT cache may need to be disabled.
6697 */
6698 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6699
89d6b2b8 6700 lpt_init_clock_gating(dev);
1020a5c2
BW		 6701}
6702
cad2a2d7
ED		 6703static void haswell_init_clock_gating(struct drm_device *dev)
6704{
6705 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6706
017636cc 6707 ilk_init_lp_watermarks(dev);
cad2a2d7 6708
f3fc4884
FJ		 6709 /* L3 caching of data atomics doesn't work -- disable it. */
6710 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6711 I915_WRITE(HSW_ROW_CHICKEN3,
6712 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6713
ecdb4eb7 6714 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6715 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6716 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6717 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6718
e36ea7ff
VS		 6719 /* WaVSRefCountFullforceMissDisable:hsw */
6720 I915_WRITE(GEN7_FF_THREAD_MODE,
6721 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6722
4e04632e
AG		 6723 /* WaDisable_RenderCache_OperationalFlush:hsw */
6724 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6725
fe27c606
CW		 6726 /* enable HiZ Raw Stall Optimization */
6727 I915_WRITE(CACHE_MODE_0_GEN7,
6728 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6729
ecdb4eb7 6730 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6731 I915_WRITE(CACHE_MODE_1,
6732 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6733
a12c4967
VS		 6734 /*
6735 * BSpec recommends 8x4 when MSAA is used,
6736 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6737 *
6738 * Note that PS/WM thread counts depend on the WIZ hashing
6739 * disable bit, which we don't touch here, but it's good
6740 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6741 */
6742 I915_WRITE(GEN7_GT_MODE,
98533251 6743 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6744
94411593
KG		 6745 /* WaSampleCChickenBitEnable:hsw */
6746 I915_WRITE(HALF_SLICE_CHICKEN3,
6747 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6748
ecdb4eb7 6749 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6750 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6751
90a88643
PZ		 6752 /* WaRsPkgCStateDisplayPMReq:hsw */
6753 I915_WRITE(CHICKEN_PAR1_1,
6754 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6755
17a303ec 6756 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6757}
6758
1fa61106 6759static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6760{
6761 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6762 uint32_t snpcr;
6f1d69b0 6763
017636cc 6764 ilk_init_lp_watermarks(dev);
6f1d69b0 6765
231e54f6 6766 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6767
ecdb4eb7 6768 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6769 I915_WRITE(_3D_CHICKEN3,
6770 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6771
ecdb4eb7 6772 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6773 I915_WRITE(IVB_CHICKEN3,
6774 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6775 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6776
ecdb4eb7 6777 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6778 if (IS_IVB_GT1(dev))
6779 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6780 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6781
4e04632e
AG		 6782 /* WaDisable_RenderCache_OperationalFlush:ivb */
6783 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6784
ecdb4eb7 6785 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6786 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6787 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6788
ecdb4eb7 6789 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6790 I915_WRITE(GEN7_L3CNTLREG1,
6791 GEN7_WA_FOR_GEN7_L3_CONTROL);
6792 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6793 GEN7_WA_L3_CHICKEN_MODE);
6794 if (IS_IVB_GT1(dev))
6795 I915_WRITE(GEN7_ROW_CHICKEN2,
6796 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6797 else {
6798 /* must write both registers */
6799 I915_WRITE(GEN7_ROW_CHICKEN2,
6800 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6801 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6802 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6803 }
6f1d69b0 6804
ecdb4eb7 6805 /* WaForceL3Serialization:ivb */
61939d97
JB		 6806 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6807 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6808
1b80a19a 6809 /*
0f846f81 6810 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6811 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6812 */
6813 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6814 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6815
ecdb4eb7 6816 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6817 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6818 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6819 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6820
0e088b8f 6821 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6822
6823 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6824
22721343
CW		 6825 if (0) { /* causes HiZ corruption on ivb:gt1 */
6826 /* enable HiZ Raw Stall Optimization */
6827 I915_WRITE(CACHE_MODE_0_GEN7,
6828 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6829 }
116f2b6d 6830
ecdb4eb7 6831 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6832 I915_WRITE(CACHE_MODE_1,
6833 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6834
a607c1a4
VS		 6835 /*
6836 * BSpec recommends 8x4 when MSAA is used,
6837 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6838 *
6839 * Note that PS/WM thread counts depend on the WIZ hashing
6840 * disable bit, which we don't touch here, but it's good
6841 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6842 */
6843 I915_WRITE(GEN7_GT_MODE,
98533251 6844 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6845
20848223
BW		 6846 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6847 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6848 snpcr |= GEN6_MBC_SNPCR_MED;
6849 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6850
ab5c608b
BW		 6851 if (!HAS_PCH_NOP(dev))
6852 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6853
6854 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6855}
6856
c6beb13e
VS		 6857static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6858{
6859 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6860
6861 /*
6862 * Disable trickle feed and enable pnd deadline calculation
6863 */
6864 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6865 I915_WRITE(CBR1_VLV, 0);
6866}
6867
1fa61106 6868static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6869{
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6871
c6beb13e 6872 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6873
ecdb4eb7 6874 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6875 I915_WRITE(_3D_CHICKEN3,
6876 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6877
ecdb4eb7 6878 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6879 I915_WRITE(IVB_CHICKEN3,
6880 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6881 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6882
fad7d36e 6883 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6884 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6885 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6886 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6887 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6888
4e04632e
AG		 6889 /* WaDisable_RenderCache_OperationalFlush:vlv */
6890 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6891
ecdb4eb7 6892 /* WaForceL3Serialization:vlv */
61939d97
JB		 6893 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6894 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6895
ecdb4eb7 6896 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6897 I915_WRITE(GEN7_ROW_CHICKEN2,
6898 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6899
ecdb4eb7 6900 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6901 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6902 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6903 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6904
46680e0a
VS		 6905 gen7_setup_fixed_func_scheduler(dev_priv);
6906
3c0edaeb 6907 /*
0f846f81 6908 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6909 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6910 */
6911 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6912 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6913
c98f5062
AG		 6914 /* WaDisableL3Bank2xClockGate:vlv
6915 * Disabling L3 clock gating- MMIO 940c[25] = 1
6916 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6917 I915_WRITE(GEN7_UCGCTL4,
6918 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6919
afd58e79
VS		 6920 /*
6921 * BSpec says this must be set, even though
6922 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6923 */
6b26c86d
DV		 6924 I915_WRITE(CACHE_MODE_1,
6925 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6926
da2518f9
VS		 6927 /*
6928 * BSpec recommends 8x4 when MSAA is used,
6929 * however in practice 16x4 seems fastest.
6930 *
6931 * Note that PS/WM thread counts depend on the WIZ hashing
6932 * disable bit, which we don't touch here, but it's good
6933 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6934 */
6935 I915_WRITE(GEN7_GT_MODE,
6936 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6937
031994ee
VS		 6938 /*
6939 * WaIncreaseL3CreditsForVLVB0:vlv
6940 * This is the hardware default actually.
6941 */
6942 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6943
2d809570 6944 /*
ecdb4eb7 6945 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6946 * Disable clock gating on th GCFG unit to prevent a delay
6947 * in the reporting of vblank events.
6948 */
7a0d1eed 6949 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6950}
6951
a4565da8
VS		 6952static void cherryview_init_clock_gating(struct drm_device *dev)
6953{
6954 struct drm_i915_private *dev_priv = dev->dev_private;
6955
c6beb13e 6956 vlv_init_display_clock_gating(dev_priv);
dd811e70 6957
232ce337
VS		 6958 /* WaVSRefCountFullforceMissDisable:chv */
6959 /* WaDSRefCountFullforceMissDisable:chv */
6960 I915_WRITE(GEN7_FF_THREAD_MODE,
6961 I915_READ(GEN7_FF_THREAD_MODE) &
6962 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6963
6964 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6965 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6966 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6967
6968 /* WaDisableCSUnitClockGating:chv */
6969 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6970 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6971
6972 /* WaDisableSDEUnitClockGating:chv */
6973 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6974 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6975
6976 /*
6977 * GTT cache may not work with big pages, so if those
6978 * are ever enabled GTT cache may need to be disabled.
6979 */
6980 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6981}
6982
1fa61106 6983static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6984{
6985 struct drm_i915_private *dev_priv = dev->dev_private;
6986 uint32_t dspclk_gate;
6987
6988 I915_WRITE(RENCLK_GATE_D1, 0);
6989 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6990 GS_UNIT_CLOCK_GATE_DISABLE |
6991 CL_UNIT_CLOCK_GATE_DISABLE);
6992 I915_WRITE(RAMCLK_GATE_D, 0);
6993 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6994 OVRUNIT_CLOCK_GATE_DISABLE |
6995 OVCUNIT_CLOCK_GATE_DISABLE;
6996 if (IS_GM45(dev))
6997 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6998 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6999
7000 /* WaDisableRenderCachePipelinedFlush */
7001 I915_WRITE(CACHE_MODE_0,
7002 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7003
4e04632e
AG		 7004 /* WaDisable_RenderCache_OperationalFlush:g4x */
7005 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7006
0e088b8f 7007 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7008}
7009
1fa61106 7010static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7011{
7012 struct drm_i915_private *dev_priv = dev->dev_private;
7013
7014 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7015 I915_WRITE(RENCLK_GATE_D2, 0);
7016 I915_WRITE(DSPCLK_GATE_D, 0);
7017 I915_WRITE(RAMCLK_GATE_D, 0);
7018 I915_WRITE16(DEUC, 0);
20f94967
VS		 7019 I915_WRITE(MI_ARB_STATE,
7020 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7021
7022 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7023 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7024}
7025
1fa61106 7026static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7027{
7028 struct drm_i915_private *dev_priv = dev->dev_private;
7029
7030 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7031 I965_RCC_CLOCK_GATE_DISABLE |
7032 I965_RCPB_CLOCK_GATE_DISABLE |
7033 I965_ISC_CLOCK_GATE_DISABLE |
7034 I965_FBC_CLOCK_GATE_DISABLE);
7035 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7036 I915_WRITE(MI_ARB_STATE,
7037 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7038
7039 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7040 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7041}
7042
1fa61106 7043static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7044{
7045 struct drm_i915_private *dev_priv = dev->dev_private;
7046 u32 dstate = I915_READ(D_STATE);
7047
7048 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7049 DSTATE_DOT_CLOCK_GATING;
7050 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7051
7052 if (IS_PINEVIEW(dev))
7053 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7054
7055 /* IIR "flip pending" means done if this bit is set */
7056 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7057
7058 /* interrupts should cause a wake up from C3 */
3299254f 7059 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7060
7061 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7062 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7063
7064 I915_WRITE(MI_ARB_STATE,
7065 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7066}
7067
1fa61106 7068static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7069{
7070 struct drm_i915_private *dev_priv = dev->dev_private;
7071
7072 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7073
7074 /* interrupts should cause a wake up from C3 */
7075 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7076 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7077
7078 I915_WRITE(MEM_MODE,
7079 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7080}
7081
1fa61106 7082static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7083{
7084 struct drm_i915_private *dev_priv = dev->dev_private;
7085
7086 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7087
7088 I915_WRITE(MEM_MODE,
7089 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7090 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7091}
7092
6f1d69b0
ED		 7093void intel_init_clock_gating(struct drm_device *dev)
7094{
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096
c57e3551
DL		 7097 if (dev_priv->display.init_clock_gating)
7098 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7099}
7100
7d708ee4
ID		 7101void intel_suspend_hw(struct drm_device *dev)
7102{
7103 if (HAS_PCH_LPT(dev))
7104 lpt_suspend_hw(dev);
7105}
7106
1fa61106
ED		 7107/* Set up chip specific power management-related functions */
7108void intel_init_pm(struct drm_device *dev)
7109{
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111
7ff0ebcc 7112 intel_fbc_init(dev_priv);
1fa61106 7113
c921aba8
DV		 7114 /* For cxsr */
7115 if (IS_PINEVIEW(dev))
7116 i915_pineview_get_mem_freq(dev);
7117 else if (IS_GEN5(dev))
7118 i915_ironlake_get_mem_freq(dev);
7119
1fa61106 7120 /* For FIFO watermark updates */
f5ed50cb 7121 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7122 skl_setup_wm_latency(dev);
7123
a82abe43
ID		 7124 if (IS_BROXTON(dev))
7125 dev_priv->display.init_clock_gating =
7126 bxt_init_clock_gating;
2d41c0b5 7127 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7128 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7129 ilk_setup_wm_latency(dev);
53615a5e 7130
bd602544
VS		 7131 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7132 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7133 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7134 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7135 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7136 dev_priv->display.compute_intermediate_wm =
7137 ilk_compute_intermediate_wm;
7138 dev_priv->display.initial_watermarks =
7139 ilk_initial_watermarks;
7140 dev_priv->display.optimize_watermarks =
7141 ilk_optimize_watermarks;
bd602544
VS		 7142 } else {
7143 DRM_DEBUG_KMS("Failed to read display plane latency. "
7144 "Disable CxSR\n");
7145 }
7146
7147 if (IS_GEN5(dev))
1fa61106 7148 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7149 else if (IS_GEN6(dev))
1fa61106 7150 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7151 else if (IS_IVYBRIDGE(dev))
1fa61106 7152 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7153 else if (IS_HASWELL(dev))
cad2a2d7 7154 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7155 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7156 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7157 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7158 vlv_setup_wm_latency(dev);
7159
7160 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7161 dev_priv->display.init_clock_gating =
7162 cherryview_init_clock_gating;
1fa61106 7163 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7164 vlv_setup_wm_latency(dev);
7165
7166 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7167 dev_priv->display.init_clock_gating =
7168 valleyview_init_clock_gating;
1fa61106
ED		 7169 } else if (IS_PINEVIEW(dev)) {
7170 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7171 dev_priv->is_ddr3,
7172 dev_priv->fsb_freq,
7173 dev_priv->mem_freq)) {
7174 DRM_INFO("failed to find known CxSR latency "
7175 "(found ddr%s fsb freq %d, mem freq %d), "
7176 "disabling CxSR\n",
7177 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7178 dev_priv->fsb_freq, dev_priv->mem_freq);
7179 /* Disable CxSR and never update its watermark again */
5209b1f4 7180 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7181 dev_priv->display.update_wm = NULL;
7182 } else
7183 dev_priv->display.update_wm = pineview_update_wm;
7184 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7185 } else if (IS_G4X(dev)) {
7186 dev_priv->display.update_wm = g4x_update_wm;
7187 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7188 } else if (IS_GEN4(dev)) {
7189 dev_priv->display.update_wm = i965_update_wm;
7190 if (IS_CRESTLINE(dev))
7191 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7192 else if (IS_BROADWATER(dev))
7193 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7194 } else if (IS_GEN3(dev)) {
7195 dev_priv->display.update_wm = i9xx_update_wm;
7196 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7197 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7198 } else if (IS_GEN2(dev)) {
7199 if (INTEL_INFO(dev)->num_pipes == 1) {
7200 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7201 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7202 } else {
7203 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7204 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7205 }
7206
7207 if (IS_I85X(dev) || IS_I865G(dev))
7208 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7209 else
7210 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7211 } else {
7212 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7213 }
7214}
7215
151a49d0 7216int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7217{
4fc688ce 7218 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7219
7220 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7221 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7222 return -EAGAIN;
7223 }
7224
7225 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7226 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7227 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7228
7229 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7230 500)) {
7231 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7232 return -ETIMEDOUT;
7233 }
7234
7235 *val = I915_READ(GEN6_PCODE_DATA);
7236 I915_WRITE(GEN6_PCODE_DATA, 0);
7237
7238 return 0;
7239}
7240
151a49d0 7241int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7242{
4fc688ce 7243 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7244
7245 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7246 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7247 return -EAGAIN;
7248 }
7249
7250 I915_WRITE(GEN6_PCODE_DATA, val);
7251 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7252
7253 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7254 500)) {
7255 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7256 return -ETIMEDOUT;
7257 }
7258
7259 I915_WRITE(GEN6_PCODE_DATA, 0);
7260
7261 return 0;
7262}
a0e4e199 7263
dd06f88c 7264static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7265{
dd06f88c
VS		 7266 switch (czclk_freq) {
7267 case 200:
7268 return 10;
7269 case 267:
7270 return 12;
7271 case 320:
7272 case 333:
dd06f88c 7273 return 16;
ab3fb157
VS		 7274 case 400:
7275 return 20;
855ba3be
JB		 7276 default:
7277 return -1;
7278 }
dd06f88c 7279}
855ba3be 7280
dd06f88c
VS		 7281static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7282{
bfa7df01 7283 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7284
7285 div = vlv_gpu_freq_div(czclk_freq);
7286 if (div < 0)
7287 return div;
7288
7289 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7290}
7291
b55dd647 7292static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7293{
bfa7df01 7294 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7295
dd06f88c
VS		 7296 mul = vlv_gpu_freq_div(czclk_freq);
7297 if (mul < 0)
7298 return mul;
855ba3be 7299
dd06f88c 7300 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7301}
7302
b55dd647 7303static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7304{
bfa7df01 7305 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7306
9c06f674 7307 div = vlv_gpu_freq_div(czclk_freq);
dd06f88c
VS		 7308 if (div < 0)
7309 return div;
9c06f674 7310 div /= 2;
22b1b2f8 7311
dd06f88c 7312 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7313}
7314
b55dd647 7315static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7316{
bfa7df01 7317 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7318
9c06f674 7319 mul = vlv_gpu_freq_div(czclk_freq);
dd06f88c
VS		 7320 if (mul < 0)
7321 return mul;
9c06f674 7322 mul /= 2;
22b1b2f8 7323
1c14762d 7324 /* CHV needs even values */
dd06f88c 7325 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7326}
7327
616bc820 7328int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7329{
80b6dda4 7330 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7331 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7332 GEN9_FREQ_SCALER);
80b6dda4 7333 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7334 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7335 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7336 return byt_gpu_freq(dev_priv, val);
7337 else
7338 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7339}
7340
616bc820
VS		 7341int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7342{
80b6dda4 7343 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7344 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7345 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7346 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7347 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7348 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7349 return byt_freq_opcode(dev_priv, val);
7350 else
500a3d2e 7351 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7352}
22b1b2f8 7353
6ad790c0
CW		 7354struct request_boost {
7355 struct work_struct work;
eed29a5b 7356 struct drm_i915_gem_request *req;
6ad790c0
CW		 7357};
7358
7359static void __intel_rps_boost_work(struct work_struct *work)
7360{
7361 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7362 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7363
e61b9958
CW		 7364 if (!i915_gem_request_completed(req, true))
7365 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7366 req->emitted_jiffies);
6ad790c0 7367
e61b9958 7368 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7369 kfree(boost);
7370}
7371
7372void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7373 struct drm_i915_gem_request *req)
6ad790c0
CW		 7374{
7375 struct request_boost *boost;
7376
eed29a5b 7377 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7378 return;
7379
e61b9958
CW		 7380 if (i915_gem_request_completed(req, true))
7381 return;
7382
6ad790c0
CW		 7383 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7384 if (boost == NULL)
7385 return;
7386
eed29a5b
DV		 7387 i915_gem_request_reference(req);
7388 boost->req = req;
6ad790c0
CW		 7389
7390 INIT_WORK(&boost->work, __intel_rps_boost_work);
7391 queue_work(to_i915(dev)->wq, &boost->work);
7392}
7393
f742a552 7394void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7395{
7396 struct drm_i915_private *dev_priv = dev->dev_private;
7397
f742a552 7398 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7399 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7400
907b28c5
CW		 7401 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7402 intel_gen6_powersave_work);
1854d5ca 7403 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7404 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7405 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7406
33688d95 7407 dev_priv->pm.suspended = false;
1f814dac 7408 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7409 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7410}
Ubuntu Artful kernel mirror