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drm/i915: Relax RPS contraints to allows setting minfreq on idle
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
3dcd020a
HN		 70 if (INTEL_REVID(dev) == SKL_REVID_A0) {
71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a
HN		 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
78 }
8bc0ccf6 79
2caa3b26 80 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 81 /* WaDisableHDCInvalidation:skl */
82 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
83 BDW_DISABLE_HDC_INVALIDATION);
84
2caa3b26
DL		 85 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
86 I915_WRITE(FF_SLICE_CS_CHICKEN2,
87 I915_READ(FF_SLICE_CS_CHICKEN2) |
88 GEN9_TSG_BARRIER_ACK_DISABLE);
89 }
81e231af 90
8bc0ccf6
DL		 91 if (INTEL_REVID(dev) <= SKL_REVID_E0)
92 /* WaDisableLSQCROPERFforOCL:skl */
93 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
94 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 95}
96
c921aba8
DV		 97static void i915_pineview_get_mem_freq(struct drm_device *dev)
98{
50227e1c 99 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 100 u32 tmp;
101
102 tmp = I915_READ(CLKCFG);
103
104 switch (tmp & CLKCFG_FSB_MASK) {
105 case CLKCFG_FSB_533:
106 dev_priv->fsb_freq = 533; /* 133*4 */
107 break;
108 case CLKCFG_FSB_800:
109 dev_priv->fsb_freq = 800; /* 200*4 */
110 break;
111 case CLKCFG_FSB_667:
112 dev_priv->fsb_freq = 667; /* 167*4 */
113 break;
114 case CLKCFG_FSB_400:
115 dev_priv->fsb_freq = 400; /* 100*4 */
116 break;
117 }
118
119 switch (tmp & CLKCFG_MEM_MASK) {
120 case CLKCFG_MEM_533:
121 dev_priv->mem_freq = 533;
122 break;
123 case CLKCFG_MEM_667:
124 dev_priv->mem_freq = 667;
125 break;
126 case CLKCFG_MEM_800:
127 dev_priv->mem_freq = 800;
128 break;
129 }
130
131 /* detect pineview DDR3 setting */
132 tmp = I915_READ(CSHRDDR3CTL);
133 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
134}
135
136static void i915_ironlake_get_mem_freq(struct drm_device *dev)
137{
50227e1c 138 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 139 u16 ddrpll, csipll;
140
141 ddrpll = I915_READ16(DDRMPLL1);
142 csipll = I915_READ16(CSIPLL0);
143
144 switch (ddrpll & 0xff) {
145 case 0xc:
146 dev_priv->mem_freq = 800;
147 break;
148 case 0x10:
149 dev_priv->mem_freq = 1066;
150 break;
151 case 0x14:
152 dev_priv->mem_freq = 1333;
153 break;
154 case 0x18:
155 dev_priv->mem_freq = 1600;
156 break;
157 default:
158 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
159 ddrpll & 0xff);
160 dev_priv->mem_freq = 0;
161 break;
162 }
163
20e4d407 164 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 165
166 switch (csipll & 0x3ff) {
167 case 0x00c:
168 dev_priv->fsb_freq = 3200;
169 break;
170 case 0x00e:
171 dev_priv->fsb_freq = 3733;
172 break;
173 case 0x010:
174 dev_priv->fsb_freq = 4266;
175 break;
176 case 0x012:
177 dev_priv->fsb_freq = 4800;
178 break;
179 case 0x014:
180 dev_priv->fsb_freq = 5333;
181 break;
182 case 0x016:
183 dev_priv->fsb_freq = 5866;
184 break;
185 case 0x018:
186 dev_priv->fsb_freq = 6400;
187 break;
188 default:
189 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
190 csipll & 0x3ff);
191 dev_priv->fsb_freq = 0;
192 break;
193 }
194
195 if (dev_priv->fsb_freq == 3200) {
20e4d407 196 dev_priv->ips.c_m = 0;
c921aba8 197 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 198 dev_priv->ips.c_m = 1;
c921aba8 199 } else {
20e4d407 200 dev_priv->ips.c_m = 2;
c921aba8
DV		 201 }
202}
203
b445e3b0
ED		 204static const struct cxsr_latency cxsr_latency_table[] = {
205 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
206 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
207 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
208 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
209 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
210
211 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
212 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
213 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
214 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
215 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
216
217 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
218 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
219 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
220 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
221 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
222
223 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
224 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
225 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
226 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
227 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
228
229 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
230 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
231 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
232 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
233 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
234
235 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
236 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
237 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
238 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
239 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
240};
241
63c62275 242static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 243 int is_ddr3,
244 int fsb,
245 int mem)
246{
247 const struct cxsr_latency *latency;
248 int i;
249
250 if (fsb == 0 || mem == 0)
251 return NULL;
252
253 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
254 latency = &cxsr_latency_table[i];
255 if (is_desktop == latency->is_desktop &&
256 is_ddr3 == latency->is_ddr3 &&
257 fsb == latency->fsb_freq && mem == latency->mem_freq)
258 return latency;
259 }
260
261 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
262
263 return NULL;
264}
265
fc1ac8de
VS		 266static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
267{
268 u32 val;
269
270 mutex_lock(&dev_priv->rps.hw_lock);
271
272 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
273 if (enable)
274 val &= ~FORCE_DDR_HIGH_FREQ;
275 else
276 val |= FORCE_DDR_HIGH_FREQ;
277 val &= ~FORCE_DDR_LOW_FREQ;
278 val |= FORCE_DDR_FREQ_REQ_ACK;
279 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
280
281 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
282 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
283 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
cfb41411
VS		 288static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
289{
290 u32 val;
291
292 mutex_lock(&dev_priv->rps.hw_lock);
293
294 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
295 if (enable)
296 val |= DSP_MAXFIFO_PM5_ENABLE;
297 else
298 val &= ~DSP_MAXFIFO_PM5_ENABLE;
299 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
300
301 mutex_unlock(&dev_priv->rps.hw_lock);
302}
303
f4998963
VS		 304#define FW_WM(value, plane) \
305 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
306
5209b1f4 307void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 308{
5209b1f4
ID		 309 struct drm_device *dev = dev_priv->dev;
310 u32 val;
b445e3b0 311
5209b1f4
ID		 312 if (IS_VALLEYVIEW(dev)) {
313 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
cfb41411
VS		 314 if (IS_CHERRYVIEW(dev))
315 chv_set_memory_pm5(dev_priv, enable);
5209b1f4
ID		 316 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
317 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
318 } else if (IS_PINEVIEW(dev)) {
319 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
320 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
321 I915_WRITE(DSPFW3, val);
322 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
323 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
324 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
325 I915_WRITE(FW_BLC_SELF, val);
326 } else if (IS_I915GM(dev)) {
327 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
328 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
329 I915_WRITE(INSTPM, val);
330 } else {
331 return;
332 }
b445e3b0 333
5209b1f4
ID		 334 DRM_DEBUG_KMS("memory self-refresh is %s\n",
335 enable ? "enabled" : "disabled");
b445e3b0
ED		 336}
337
fc1ac8de 338
b445e3b0
ED		 339/*
340 * Latency for FIFO fetches is dependent on several factors:
341 * - memory configuration (speed, channels)
342 * - chipset
343 * - current MCH state
344 * It can be fairly high in some situations, so here we assume a fairly
345 * pessimal value. It's a tradeoff between extra memory fetches (if we
346 * set this value too high, the FIFO will fetch frequently to stay full)
347 * and power consumption (set it too low to save power and we might see
348 * FIFO underruns and display "flicker").
349 *
350 * A value of 5us seems to be a good balance; safe for very low end
351 * platforms but not overly aggressive on lower latency configs.
352 */
5aef6003 353static const int pessimal_latency_ns = 5000;
b445e3b0 354
b5004720
VS		 355#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
356 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
357
358static int vlv_get_fifo_size(struct drm_device *dev,
359 enum pipe pipe, int plane)
360{
361 struct drm_i915_private *dev_priv = dev->dev_private;
362 int sprite0_start, sprite1_start, size;
363
364 switch (pipe) {
365 uint32_t dsparb, dsparb2, dsparb3;
366 case PIPE_A:
367 dsparb = I915_READ(DSPARB);
368 dsparb2 = I915_READ(DSPARB2);
369 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
370 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
371 break;
372 case PIPE_B:
373 dsparb = I915_READ(DSPARB);
374 dsparb2 = I915_READ(DSPARB2);
375 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
376 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
377 break;
378 case PIPE_C:
379 dsparb2 = I915_READ(DSPARB2);
380 dsparb3 = I915_READ(DSPARB3);
381 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
382 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
383 break;
384 default:
385 return 0;
386 }
387
388 switch (plane) {
389 case 0:
390 size = sprite0_start;
391 break;
392 case 1:
393 size = sprite1_start - sprite0_start;
394 break;
395 case 2:
396 size = 512 - 1 - sprite1_start;
397 break;
398 default:
399 return 0;
400 }
401
402 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
403 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
404 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
405 size);
406
407 return size;
408}
409
1fa61106 410static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 411{
412 struct drm_i915_private *dev_priv = dev->dev_private;
413 uint32_t dsparb = I915_READ(DSPARB);
414 int size;
415
416 size = dsparb & 0x7f;
417 if (plane)
418 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
419
420 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
421 plane ? "B" : "A", size);
422
423 return size;
424}
425
feb56b93 426static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 427{
428 struct drm_i915_private *dev_priv = dev->dev_private;
429 uint32_t dsparb = I915_READ(DSPARB);
430 int size;
431
432 size = dsparb & 0x1ff;
433 if (plane)
434 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
435 size >>= 1; /* Convert to cachelines */
436
437 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
438 plane ? "B" : "A", size);
439
440 return size;
441}
442
1fa61106 443static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 444{
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 uint32_t dsparb = I915_READ(DSPARB);
447 int size;
448
449 size = dsparb & 0x7f;
450 size >>= 2; /* Convert to cachelines */
451
452 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
453 plane ? "B" : "A",
454 size);
455
456 return size;
457}
458
b445e3b0
ED		 459/* Pineview has different values for various configs */
460static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 461 .fifo_size = PINEVIEW_DISPLAY_FIFO,
462 .max_wm = PINEVIEW_MAX_WM,
463 .default_wm = PINEVIEW_DFT_WM,
464 .guard_size = PINEVIEW_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 466};
467static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 468 .fifo_size = PINEVIEW_DISPLAY_FIFO,
469 .max_wm = PINEVIEW_MAX_WM,
470 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
471 .guard_size = PINEVIEW_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 473};
474static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 475 .fifo_size = PINEVIEW_CURSOR_FIFO,
476 .max_wm = PINEVIEW_CURSOR_MAX_WM,
477 .default_wm = PINEVIEW_CURSOR_DFT_WM,
478 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
479 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 480};
481static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 482 .fifo_size = PINEVIEW_CURSOR_FIFO,
483 .max_wm = PINEVIEW_CURSOR_MAX_WM,
484 .default_wm = PINEVIEW_CURSOR_DFT_WM,
485 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
486 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 487};
488static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 489 .fifo_size = G4X_FIFO_SIZE,
490 .max_wm = G4X_MAX_WM,
491 .default_wm = G4X_MAX_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 494};
495static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = I965_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 503 .fifo_size = VALLEYVIEW_FIFO_SIZE,
504 .max_wm = VALLEYVIEW_MAX_WM,
505 .default_wm = VALLEYVIEW_MAX_WM,
506 .guard_size = 2,
507 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 510 .fifo_size = I965_CURSOR_FIFO,
511 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
512 .default_wm = I965_CURSOR_DFT_WM,
513 .guard_size = 2,
514 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 517 .fifo_size = I965_CURSOR_FIFO,
518 .max_wm = I965_CURSOR_MAX_WM,
519 .default_wm = I965_CURSOR_DFT_WM,
520 .guard_size = 2,
521 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 522};
523static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 524 .fifo_size = I945_FIFO_SIZE,
525 .max_wm = I915_MAX_WM,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 529};
530static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 531 .fifo_size = I915_FIFO_SIZE,
532 .max_wm = I915_MAX_WM,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 536};
9d539105 537static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 538 .fifo_size = I855GM_FIFO_SIZE,
539 .max_wm = I915_MAX_WM,
540 .default_wm = 1,
541 .guard_size = 2,
542 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 543};
9d539105
VS		 544static const struct intel_watermark_params i830_bc_wm_info = {
545 .fifo_size = I855GM_FIFO_SIZE,
546 .max_wm = I915_MAX_WM/2,
547 .default_wm = 1,
548 .guard_size = 2,
549 .cacheline_size = I830_FIFO_LINE_SIZE,
550};
feb56b93 551static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 552 .fifo_size = I830_FIFO_SIZE,
553 .max_wm = I915_MAX_WM,
554 .default_wm = 1,
555 .guard_size = 2,
556 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 557};
558
b445e3b0
ED		 559/**
560 * intel_calculate_wm - calculate watermark level
561 * @clock_in_khz: pixel clock
562 * @wm: chip FIFO params
563 * @pixel_size: display pixel size
564 * @latency_ns: memory latency for the platform
565 *
566 * Calculate the watermark level (the level at which the display plane will
567 * start fetching from memory again). Each chip has a different display
568 * FIFO size and allocation, so the caller needs to figure that out and pass
569 * in the correct intel_watermark_params structure.
570 *
571 * As the pixel clock runs, the FIFO will be drained at a rate that depends
572 * on the pixel size. When it reaches the watermark level, it'll start
573 * fetching FIFO line sized based chunks from memory until the FIFO fills
574 * past the watermark point. If the FIFO drains completely, a FIFO underrun
575 * will occur, and a display engine hang could result.
576 */
577static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
578 const struct intel_watermark_params *wm,
579 int fifo_size,
580 int pixel_size,
581 unsigned long latency_ns)
582{
583 long entries_required, wm_size;
584
585 /*
586 * Note: we need to make sure we don't overflow for various clock &
587 * latency values.
588 * clocks go from a few thousand to several hundred thousand.
589 * latency is usually a few thousand
590 */
591 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
592 1000;
593 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
594
595 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
596
597 wm_size = fifo_size - (entries_required + wm->guard_size);
598
599 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
600
601 /* Don't promote wm_size to unsigned... */
602 if (wm_size > (long)wm->max_wm)
603 wm_size = wm->max_wm;
604 if (wm_size <= 0)
605 wm_size = wm->default_wm;
d6feb196
VS		 606
607 /*
608 * Bspec seems to indicate that the value shouldn't be lower than
609 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
610 * Lets go for 8 which is the burst size since certain platforms
611 * already use a hardcoded 8 (which is what the spec says should be
612 * done).
613 */
614 if (wm_size <= 8)
615 wm_size = 8;
616
b445e3b0
ED		 617 return wm_size;
618}
619
620static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
621{
622 struct drm_crtc *crtc, *enabled = NULL;
623
70e1e0ec 624 for_each_crtc(dev, crtc) {
3490ea5d 625 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 626 if (enabled)
627 return NULL;
628 enabled = crtc;
629 }
630 }
631
632 return enabled;
633}
634
46ba614c 635static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 636{
46ba614c 637 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_crtc *crtc;
640 const struct cxsr_latency *latency;
641 u32 reg;
642 unsigned long wm;
643
644 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
645 dev_priv->fsb_freq, dev_priv->mem_freq);
646 if (!latency) {
647 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 648 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 649 return;
650 }
651
652 crtc = single_enabled_crtc(dev);
653 if (crtc) {
241bfc38 654 const struct drm_display_mode *adjusted_mode;
59bea882 655 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 656 int clock;
657
6e3c9717 658 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 659 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 660
661 /* Display SR */
662 wm = intel_calculate_wm(clock, &pineview_display_wm,
663 pineview_display_wm.fifo_size,
664 pixel_size, latency->display_sr);
665 reg = I915_READ(DSPFW1);
666 reg &= ~DSPFW_SR_MASK;
f4998963 667 reg |= FW_WM(wm, SR);
b445e3b0
ED		 668 I915_WRITE(DSPFW1, reg);
669 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
670
671 /* cursor SR */
672 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
673 pineview_display_wm.fifo_size,
674 pixel_size, latency->cursor_sr);
675 reg = I915_READ(DSPFW3);
676 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 677 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 678 I915_WRITE(DSPFW3, reg);
679
680 /* Display HPLL off SR */
681 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
682 pineview_display_hplloff_wm.fifo_size,
683 pixel_size, latency->display_hpll_disable);
684 reg = I915_READ(DSPFW3);
685 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 686 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 687 I915_WRITE(DSPFW3, reg);
688
689 /* cursor HPLL off SR */
690 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
691 pineview_display_hplloff_wm.fifo_size,
692 pixel_size, latency->cursor_hpll_disable);
693 reg = I915_READ(DSPFW3);
694 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 695 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 696 I915_WRITE(DSPFW3, reg);
697 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
698
5209b1f4 699 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 700 } else {
5209b1f4 701 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 702 }
703}
704
705static bool g4x_compute_wm0(struct drm_device *dev,
706 int plane,
707 const struct intel_watermark_params *display,
708 int display_latency_ns,
709 const struct intel_watermark_params *cursor,
710 int cursor_latency_ns,
711 int *plane_wm,
712 int *cursor_wm)
713{
714 struct drm_crtc *crtc;
4fe8590a 715 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 716 int htotal, hdisplay, clock, pixel_size;
717 int line_time_us, line_count;
718 int entries, tlb_miss;
719
720 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 721 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 722 *cursor_wm = cursor->guard_size;
723 *plane_wm = display->guard_size;
724 return false;
725 }
726
6e3c9717 727 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 728 clock = adjusted_mode->crtc_clock;
fec8cba3 729 htotal = adjusted_mode->crtc_htotal;
6e3c9717 730 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 731 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 732
733 /* Use the small buffer method to calculate plane watermark */
734 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
735 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
736 if (tlb_miss > 0)
737 entries += tlb_miss;
738 entries = DIV_ROUND_UP(entries, display->cacheline_size);
739 *plane_wm = entries + display->guard_size;
740 if (*plane_wm > (int)display->max_wm)
741 *plane_wm = display->max_wm;
742
743 /* Use the large buffer method to calculate cursor watermark */
922044c9 744 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 745 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 746 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 747 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
748 if (tlb_miss > 0)
749 entries += tlb_miss;
750 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
751 *cursor_wm = entries + cursor->guard_size;
752 if (*cursor_wm > (int)cursor->max_wm)
753 *cursor_wm = (int)cursor->max_wm;
754
755 return true;
756}
757
758/*
759 * Check the wm result.
760 *
761 * If any calculated watermark values is larger than the maximum value that
762 * can be programmed into the associated watermark register, that watermark
763 * must be disabled.
764 */
765static bool g4x_check_srwm(struct drm_device *dev,
766 int display_wm, int cursor_wm,
767 const struct intel_watermark_params *display,
768 const struct intel_watermark_params *cursor)
769{
770 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
771 display_wm, cursor_wm);
772
773 if (display_wm > display->max_wm) {
774 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
775 display_wm, display->max_wm);
776 return false;
777 }
778
779 if (cursor_wm > cursor->max_wm) {
780 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
781 cursor_wm, cursor->max_wm);
782 return false;
783 }
784
785 if (!(display_wm || cursor_wm)) {
786 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
787 return false;
788 }
789
790 return true;
791}
792
793static bool g4x_compute_srwm(struct drm_device *dev,
794 int plane,
795 int latency_ns,
796 const struct intel_watermark_params *display,
797 const struct intel_watermark_params *cursor,
798 int *display_wm, int *cursor_wm)
799{
800 struct drm_crtc *crtc;
4fe8590a 801 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 802 int hdisplay, htotal, pixel_size, clock;
803 unsigned long line_time_us;
804 int line_count, line_size;
805 int small, large;
806 int entries;
807
808 if (!latency_ns) {
809 *display_wm = *cursor_wm = 0;
810 return false;
811 }
812
813 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 814 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 815 clock = adjusted_mode->crtc_clock;
fec8cba3 816 htotal = adjusted_mode->crtc_htotal;
6e3c9717 817 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 818 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 819
922044c9 820 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 821 line_count = (latency_ns / line_time_us + 1000) / 1000;
822 line_size = hdisplay * pixel_size;
823
824 /* Use the minimum of the small and large buffer method for primary */
825 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
826 large = line_count * line_size;
827
828 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
829 *display_wm = entries + display->guard_size;
830
831 /* calculate the self-refresh watermark for display cursor */
3dd512fb 832 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 833 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
834 *cursor_wm = entries + cursor->guard_size;
835
836 return g4x_check_srwm(dev,
837 *display_wm, *cursor_wm,
838 display, cursor);
839}
840
15665979
VS		 841#define FW_WM_VLV(value, plane) \
842 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
843
0018fda1
VS		 844static void vlv_write_wm_values(struct intel_crtc *crtc,
845 const struct vlv_wm_values *wm)
846{
847 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
848 enum pipe pipe = crtc->pipe;
849
850 I915_WRITE(VLV_DDL(pipe),
851 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
852 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
853 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
854 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
855
ae80152d 856 I915_WRITE(DSPFW1,
15665979
VS		 857 FW_WM(wm->sr.plane, SR) |
858 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
859 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
860 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 861 I915_WRITE(DSPFW2,
15665979
VS		 862 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
863 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
864 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 865 I915_WRITE(DSPFW3,
15665979 866 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 867
868 if (IS_CHERRYVIEW(dev_priv)) {
869 I915_WRITE(DSPFW7_CHV,
15665979
VS		 870 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
871 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 872 I915_WRITE(DSPFW8_CHV,
15665979
VS		 873 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
874 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 875 I915_WRITE(DSPFW9_CHV,
15665979
VS		 876 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
877 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 878 I915_WRITE(DSPHOWM,
15665979
VS		 879 FW_WM(wm->sr.plane >> 9, SR_HI) |
880 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
881 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
882 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
883 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
884 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
885 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
886 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
887 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
888 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 889 } else {
890 I915_WRITE(DSPFW7,
15665979
VS		 891 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
892 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 893 I915_WRITE(DSPHOWM,
15665979
VS		 894 FW_WM(wm->sr.plane >> 9, SR_HI) |
895 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
896 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
897 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
898 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
899 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
900 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 901 }
902
903 POSTING_READ(DSPFW1);
904
0018fda1
VS		 905 dev_priv->wm.vlv = *wm;
906}
907
15665979
VS		 908#undef FW_WM_VLV
909
341c526f 910static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
883a3d2f 911 struct drm_plane *plane)
b445e3b0 912{
5e56ba45 913 struct drm_device *dev = crtc->dev;
883a3d2f
VS		 914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
915 int entries, prec_mult, drain_latency, pixel_size;
916 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
341c526f 917 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
b445e3b0 918
883a3d2f
VS		 919 /*
920 * FIXME the plane might have an fb
921 * but be invisible (eg. due to clipping)
922 */
923 if (!intel_crtc->active || !plane->state->fb)
924 return 0;
925
0948c265 926 if (WARN(clock == 0, "Pixel clock is zero!\n"))
341c526f 927 return 0;
b445e3b0 928
883a3d2f
VS		 929 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
930
0948c265 931 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
341c526f 932 return 0;
b445e3b0 933
a398e9c7 934 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
abfc00b5 935
341c526f
VS		 936 prec_mult = high_precision;
937 drain_latency = 64 * prec_mult * 4 / entries;
b445e3b0 938
341c526f
VS		 939 if (drain_latency > DRAIN_LATENCY_MASK) {
940 prec_mult /= 2;
941 drain_latency = 64 * prec_mult * 4 / entries;
abfc00b5
VS		 942 }
943
341c526f
VS		 944 if (drain_latency > DRAIN_LATENCY_MASK)
945 drain_latency = DRAIN_LATENCY_MASK;
b445e3b0 946
341c526f
VS		 947 return drain_latency | (prec_mult == high_precision ?
948 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
b445e3b0
ED		 949}
950
ae80152d
VS		 951static int vlv_compute_wm(struct intel_crtc *crtc,
952 struct intel_plane *plane,
953 int fifo_size)
b445e3b0 954{
ae80152d 955 int clock, entries, pixel_size;
b445e3b0 956
ae80152d
VS		 957 /*
958 * FIXME the plane might have an fb
959 * but be invisible (eg. due to clipping)
960 */
961 if (!crtc->active || !plane->base.state->fb)
962 return 0;
0948c265 963
ae80152d
VS		 964 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
965 clock = crtc->config->base.adjusted_mode.crtc_clock;
b445e3b0 966
ae80152d 967 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
b445e3b0 968
ae80152d
VS		 969 /*
970 * Set up the watermark such that we don't start issuing memory
971 * requests until we are within PND's max deadline value (256us).
972 * Idea being to be idle as long as possible while still taking
973 * advatange of PND's deadline scheduling. The limit of 8
974 * cachelines (used when the FIFO will anyway drain in less time
975 * than 256us) should match what we would be done if trickle
976 * feed were enabled.
977 */
978 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
979}
980
981static bool vlv_compute_sr_wm(struct drm_device *dev,
982 struct vlv_wm_values *wm)
b445e3b0 983{
ae80152d
VS		 984 struct drm_i915_private *dev_priv = to_i915(dev);
985 struct drm_crtc *crtc;
986 enum pipe pipe = INVALID_PIPE;
987 int num_planes = 0;
988 int fifo_size = 0;
989 struct intel_plane *plane;
b445e3b0 990
ae80152d 991 wm->sr.cursor = wm->sr.plane = 0;
b445e3b0 992
ae80152d
VS		 993 crtc = single_enabled_crtc(dev);
994 /* maxfifo not supported on pipe C */
995 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
996 pipe = to_intel_crtc(crtc)->pipe;
997 num_planes = !!wm->pipe[pipe].primary +
998 !!wm->pipe[pipe].sprite[0] +
999 !!wm->pipe[pipe].sprite[1];
1000 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1001 }
b445e3b0 1002
ae80152d
VS		 1003 if (fifo_size == 0 || num_planes > 1)
1004 return false;
b445e3b0 1005
ae80152d
VS		 1006 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1007 to_intel_plane(crtc->cursor), 0x3f);
b445e3b0 1008
ae80152d
VS		 1009 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1010 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1011 continue;
b445e3b0 1012
ae80152d
VS		 1013 if (plane->pipe != pipe)
1014 continue;
9858425c 1015
ae80152d
VS		 1016 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1017 plane, fifo_size);
1018 if (wm->sr.plane != 0)
1019 break;
1020 }
1021
1022 return true;
b445e3b0
ED		 1023}
1024
ae80152d 1025static void valleyview_update_wm(struct drm_crtc *crtc)
3c2777fd
VS		 1026{
1027 struct drm_device *dev = crtc->dev;
3c2777fd 1028 struct drm_i915_private *dev_priv = dev->dev_private;
ae80152d
VS		 1029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1030 enum pipe pipe = intel_crtc->pipe;
3c2777fd 1031 bool cxsr_enabled;
ae80152d 1032 struct vlv_wm_values wm = dev_priv->wm.vlv;
3c2777fd 1033
ae80152d
VS		 1034 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1035 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1036 to_intel_plane(crtc->primary),
1037 vlv_get_fifo_size(dev, pipe, 0));
3c2777fd 1038
ae80152d
VS		 1039 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1040 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1041 to_intel_plane(crtc->cursor),
1042 0x3f);
3c2777fd 1043
ae80152d 1044 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
3c2777fd 1045
ae80152d
VS		 1046 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1047 return;
3c2777fd 1048
ae80152d
VS		 1049 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1050 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1051 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1052 wm.sr.plane, wm.sr.cursor);
3c2777fd 1053
fc1ac8de
VS		 1054 /*
1055 * FIXME DDR DVFS introduces massive memory latencies which
1056 * are not known to system agent so any deadline specified
1057 * by the display may not be respected. To support DDR DVFS
1058 * the watermark code needs to be rewritten to essentially
1059 * bypass deadline mechanism and rely solely on the
1060 * watermarks. For now disable DDR DVFS.
1061 */
1062 if (IS_CHERRYVIEW(dev_priv))
1063 chv_set_memory_dvfs(dev_priv, false);
1064
ae80152d
VS		 1065 if (!cxsr_enabled)
1066 intel_set_memory_cxsr(dev_priv, false);
3c2777fd 1067
ae80152d 1068 vlv_write_wm_values(intel_crtc, &wm);
3c2777fd
VS		 1069
1070 if (cxsr_enabled)
1071 intel_set_memory_cxsr(dev_priv, true);
1072}
1073
01e184cc
GB		 1074static void valleyview_update_sprite_wm(struct drm_plane *plane,
1075 struct drm_crtc *crtc,
1076 uint32_t sprite_width,
1077 uint32_t sprite_height,
1078 int pixel_size,
1079 bool enabled, bool scaled)
1080{
1081 struct drm_device *dev = crtc->dev;
1082 struct drm_i915_private *dev_priv = dev->dev_private;
0018fda1
VS		 1083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1084 enum pipe pipe = intel_crtc->pipe;
01e184cc 1085 int sprite = to_intel_plane(plane)->plane;
ae80152d 1086 bool cxsr_enabled;
0018fda1 1087 struct vlv_wm_values wm = dev_priv->wm.vlv;
01e184cc 1088
ae80152d 1089 if (enabled) {
0018fda1 1090 wm.ddl[pipe].sprite[sprite] =
883a3d2f 1091 vlv_compute_drain_latency(crtc, plane);
ae80152d
VS		 1092
1093 wm.pipe[pipe].sprite[sprite] =
1094 vlv_compute_wm(intel_crtc,
1095 to_intel_plane(plane),
1096 vlv_get_fifo_size(dev, pipe, sprite+1));
1097 } else {
0018fda1 1098 wm.ddl[pipe].sprite[sprite] = 0;
ae80152d
VS		 1099 wm.pipe[pipe].sprite[sprite] = 0;
1100 }
1101
1102 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1103
1104 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1105 return;
1106
1107 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1108 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1109 sprite_name(pipe, sprite),
1110 wm.pipe[pipe].sprite[sprite],
1111 wm.sr.plane, wm.sr.cursor);
1112
1113 if (!cxsr_enabled)
1114 intel_set_memory_cxsr(dev_priv, false);
01e184cc 1115
0018fda1 1116 vlv_write_wm_values(intel_crtc, &wm);
ae80152d
VS		 1117
1118 if (cxsr_enabled)
1119 intel_set_memory_cxsr(dev_priv, true);
01e184cc
GB		 1120}
1121
ae80152d
VS		 1122#define single_plane_enabled(mask) is_power_of_2(mask)
1123
46ba614c 1124static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1125{
46ba614c 1126 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1127 static const int sr_latency_ns = 12000;
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1130 int plane_sr, cursor_sr;
1131 unsigned int enabled = 0;
9858425c 1132 bool cxsr_enabled;
b445e3b0 1133
51cea1f4 1134 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1135 &g4x_wm_info, pessimal_latency_ns,
1136 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1137 &planea_wm, &cursora_wm))
51cea1f4 1138 enabled |= 1 << PIPE_A;
b445e3b0 1139
51cea1f4 1140 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1141 &g4x_wm_info, pessimal_latency_ns,
1142 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1143 &planeb_wm, &cursorb_wm))
51cea1f4 1144 enabled |= 1 << PIPE_B;
b445e3b0 1145
b445e3b0
ED		 1146 if (single_plane_enabled(enabled) &&
1147 g4x_compute_srwm(dev, ffs(enabled) - 1,
1148 sr_latency_ns,
1149 &g4x_wm_info,
1150 &g4x_cursor_wm_info,
52bd02d8 1151 &plane_sr, &cursor_sr)) {
9858425c 1152 cxsr_enabled = true;
52bd02d8 1153 } else {
9858425c 1154 cxsr_enabled = false;
5209b1f4 1155 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1156 plane_sr = cursor_sr = 0;
1157 }
b445e3b0 1158
a5043453
VS		 1159 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1160 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1161 planea_wm, cursora_wm,
1162 planeb_wm, cursorb_wm,
1163 plane_sr, cursor_sr);
1164
1165 I915_WRITE(DSPFW1,
f4998963
VS		 1166 FW_WM(plane_sr, SR) |
1167 FW_WM(cursorb_wm, CURSORB) |
1168 FW_WM(planeb_wm, PLANEB) |
1169 FW_WM(planea_wm, PLANEA));
b445e3b0 1170 I915_WRITE(DSPFW2,
8c919b28 1171 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1172 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1173 /* HPLL off in SR has some issues on G4x... disable it */
1174 I915_WRITE(DSPFW3,
8c919b28 1175 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1176 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1177
1178 if (cxsr_enabled)
1179 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1180}
1181
46ba614c 1182static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1183{
46ba614c 1184 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 struct drm_crtc *crtc;
1187 int srwm = 1;
1188 int cursor_sr = 16;
9858425c 1189 bool cxsr_enabled;
b445e3b0
ED		 1190
1191 /* Calc sr entries for one plane configs */
1192 crtc = single_enabled_crtc(dev);
1193 if (crtc) {
1194 /* self-refresh has much higher latency */
1195 static const int sr_latency_ns = 12000;
4fe8590a 1196 const struct drm_display_mode *adjusted_mode =
6e3c9717 1197 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1198 int clock = adjusted_mode->crtc_clock;
fec8cba3 1199 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1200 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1201 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1202 unsigned long line_time_us;
1203 int entries;
1204
922044c9 1205 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1206
1207 /* Use ns/us then divide to preserve precision */
1208 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1209 pixel_size * hdisplay;
1210 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1211 srwm = I965_FIFO_SIZE - entries;
1212 if (srwm < 0)
1213 srwm = 1;
1214 srwm &= 0x1ff;
1215 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1216 entries, srwm);
1217
1218 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1219 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1220 entries = DIV_ROUND_UP(entries,
1221 i965_cursor_wm_info.cacheline_size);
1222 cursor_sr = i965_cursor_wm_info.fifo_size -
1223 (entries + i965_cursor_wm_info.guard_size);
1224
1225 if (cursor_sr > i965_cursor_wm_info.max_wm)
1226 cursor_sr = i965_cursor_wm_info.max_wm;
1227
1228 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1229 "cursor %d\n", srwm, cursor_sr);
1230
9858425c 1231 cxsr_enabled = true;
b445e3b0 1232 } else {
9858425c 1233 cxsr_enabled = false;
b445e3b0 1234 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1235 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1236 }
1237
1238 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1239 srwm);
1240
1241 /* 965 has limitations... */
f4998963
VS		 1242 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1243 FW_WM(8, CURSORB) |
1244 FW_WM(8, PLANEB) |
1245 FW_WM(8, PLANEA));
1246 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1247 FW_WM(8, PLANEC_OLD));
b445e3b0 1248 /* update cursor SR watermark */
f4998963 1249 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1250
1251 if (cxsr_enabled)
1252 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1253}
1254
f4998963
VS		 1255#undef FW_WM
1256
46ba614c 1257static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1258{
46ba614c 1259 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 const struct intel_watermark_params *wm_info;
1262 uint32_t fwater_lo;
1263 uint32_t fwater_hi;
1264 int cwm, srwm = 1;
1265 int fifo_size;
1266 int planea_wm, planeb_wm;
1267 struct drm_crtc *crtc, *enabled = NULL;
1268
1269 if (IS_I945GM(dev))
1270 wm_info = &i945_wm_info;
1271 else if (!IS_GEN2(dev))
1272 wm_info = &i915_wm_info;
1273 else
9d539105 1274 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1275
1276 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1277 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1278 if (intel_crtc_active(crtc)) {
241bfc38 1279 const struct drm_display_mode *adjusted_mode;
59bea882 1280 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1281 if (IS_GEN2(dev))
1282 cpp = 4;
1283
6e3c9717 1284 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1285 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1286 wm_info, fifo_size, cpp,
5aef6003 1287 pessimal_latency_ns);
b445e3b0 1288 enabled = crtc;
9d539105 1289 } else {
b445e3b0 1290 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1291 if (planea_wm > (long)wm_info->max_wm)
1292 planea_wm = wm_info->max_wm;
1293 }
1294
1295 if (IS_GEN2(dev))
1296 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1297
1298 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1299 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1300 if (intel_crtc_active(crtc)) {
241bfc38 1301 const struct drm_display_mode *adjusted_mode;
59bea882 1302 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1303 if (IS_GEN2(dev))
1304 cpp = 4;
1305
6e3c9717 1306 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1307 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1308 wm_info, fifo_size, cpp,
5aef6003 1309 pessimal_latency_ns);
b445e3b0
ED		 1310 if (enabled == NULL)
1311 enabled = crtc;
1312 else
1313 enabled = NULL;
9d539105 1314 } else {
b445e3b0 1315 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1316 if (planeb_wm > (long)wm_info->max_wm)
1317 planeb_wm = wm_info->max_wm;
1318 }
b445e3b0
ED		 1319
1320 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1321
2ab1bc9d 1322 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1323 struct drm_i915_gem_object *obj;
2ab1bc9d 1324
59bea882 1325 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1326
1327 /* self-refresh seems busted with untiled */
2ff8fde1 1328 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1329 enabled = NULL;
1330 }
1331
b445e3b0
ED		 1332 /*
1333 * Overlay gets an aggressive default since video jitter is bad.
1334 */
1335 cwm = 2;
1336
1337 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1338 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1339
1340 /* Calc sr entries for one plane configs */
1341 if (HAS_FW_BLC(dev) && enabled) {
1342 /* self-refresh has much higher latency */
1343 static const int sr_latency_ns = 6000;
4fe8590a 1344 const struct drm_display_mode *adjusted_mode =
6e3c9717 1345 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1346 int clock = adjusted_mode->crtc_clock;
fec8cba3 1347 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1348 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1349 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1350 unsigned long line_time_us;
1351 int entries;
1352
922044c9 1353 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1354
1355 /* Use ns/us then divide to preserve precision */
1356 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1357 pixel_size * hdisplay;
1358 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1359 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1360 srwm = wm_info->fifo_size - entries;
1361 if (srwm < 0)
1362 srwm = 1;
1363
1364 if (IS_I945G(dev) || IS_I945GM(dev))
1365 I915_WRITE(FW_BLC_SELF,
1366 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1367 else if (IS_I915GM(dev))
1368 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1369 }
1370
1371 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1372 planea_wm, planeb_wm, cwm, srwm);
1373
1374 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1375 fwater_hi = (cwm & 0x1f);
1376
1377 /* Set request length to 8 cachelines per fetch */
1378 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1379 fwater_hi = fwater_hi | (1 << 8);
1380
1381 I915_WRITE(FW_BLC, fwater_lo);
1382 I915_WRITE(FW_BLC2, fwater_hi);
1383
5209b1f4
ID		 1384 if (enabled)
1385 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1386}
1387
feb56b93 1388static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1389{
46ba614c 1390 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 struct drm_crtc *crtc;
241bfc38 1393 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1394 uint32_t fwater_lo;
1395 int planea_wm;
1396
1397 crtc = single_enabled_crtc(dev);
1398 if (crtc == NULL)
1399 return;
1400
6e3c9717 1401 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1402 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1403 &i845_wm_info,
b445e3b0 1404 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1405 4, pessimal_latency_ns);
b445e3b0
ED		 1406 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1407 fwater_lo |= (3<<8) | planea_wm;
1408
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1410
1411 I915_WRITE(FW_BLC, fwater_lo);
1412}
1413
3658729a
VS		 1414static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1415 struct drm_crtc *crtc)
801bcfff
PZ		 1416{
1417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1418 uint32_t pixel_rate;
801bcfff 1419
6e3c9717 1420 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1421
1422 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1423 * adjust the pixel_rate here. */
1424
6e3c9717 1425 if (intel_crtc->config->pch_pfit.enabled) {
801bcfff 1426 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6e3c9717 1427 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
801bcfff 1428
6e3c9717
ACO		 1429 pipe_w = intel_crtc->config->pipe_src_w;
1430 pipe_h = intel_crtc->config->pipe_src_h;
801bcfff
PZ		 1431 pfit_w = (pfit_size >> 16) & 0xFFFF;
1432 pfit_h = pfit_size & 0xFFFF;
1433 if (pipe_w < pfit_w)
1434 pipe_w = pfit_w;
1435 if (pipe_h < pfit_h)
1436 pipe_h = pfit_h;
1437
1438 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1439 pfit_w * pfit_h);
1440 }
1441
1442 return pixel_rate;
1443}
1444
37126462 1445/* latency must be in 0.1us units. */
23297044 1446static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1447 uint32_t latency)
1448{
1449 uint64_t ret;
1450
3312ba65
VS		 1451 if (WARN(latency == 0, "Latency value missing\n"))
1452 return UINT_MAX;
1453
801bcfff
PZ		 1454 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1455 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1456
1457 return ret;
1458}
1459
37126462 1460/* latency must be in 0.1us units. */
23297044 1461static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1462 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1463 uint32_t latency)
1464{
1465 uint32_t ret;
1466
3312ba65
VS		 1467 if (WARN(latency == 0, "Latency value missing\n"))
1468 return UINT_MAX;
1469
801bcfff
PZ		 1470 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1471 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1472 ret = DIV_ROUND_UP(ret, 64) + 2;
1473 return ret;
1474}
1475
23297044 1476static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1477 uint8_t bytes_per_pixel)
1478{
1479 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1480}
1481
2ac96d2a
PB		 1482struct skl_pipe_wm_parameters {
1483 bool active;
1484 uint32_t pipe_htotal;
1485 uint32_t pixel_rate; /* in KHz */
1486 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1487 struct intel_plane_wm_parameters cursor;
1488};
1489
820c1980 1490struct ilk_pipe_wm_parameters {
801bcfff 1491 bool active;
801bcfff
PZ		 1492 uint32_t pipe_htotal;
1493 uint32_t pixel_rate;
c35426d2
VS		 1494 struct intel_plane_wm_parameters pri;
1495 struct intel_plane_wm_parameters spr;
1496 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1497};
1498
820c1980 1499struct ilk_wm_maximums {
cca32e9a
PZ		 1500 uint16_t pri;
1501 uint16_t spr;
1502 uint16_t cur;
1503 uint16_t fbc;
1504};
1505
240264f4
VS		 1506/* used in computing the new watermarks state */
1507struct intel_wm_config {
1508 unsigned int num_pipes_active;
1509 bool sprites_enabled;
1510 bool sprites_scaled;
240264f4
VS		 1511};
1512
37126462
VS		 1513/*
1514 * For both WM_PIPE and WM_LP.
1515 * mem_value must be in 0.1us units.
1516 */
820c1980 1517static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1518 uint32_t mem_value,
1519 bool is_lp)
801bcfff 1520{
cca32e9a
PZ		 1521 uint32_t method1, method2;
1522
c35426d2 1523 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1524 return 0;
1525
23297044 1526 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1527 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1528 mem_value);
1529
1530 if (!is_lp)
1531 return method1;
1532
23297044 1533 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1534 params->pipe_htotal,
c35426d2
VS		 1535 params->pri.horiz_pixels,
1536 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1537 mem_value);
1538
1539 return min(method1, method2);
801bcfff
PZ		 1540}
1541
37126462
VS		 1542/*
1543 * For both WM_PIPE and WM_LP.
1544 * mem_value must be in 0.1us units.
1545 */
820c1980 1546static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1547 uint32_t mem_value)
1548{
1549 uint32_t method1, method2;
1550
c35426d2 1551 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1552 return 0;
1553
23297044 1554 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1555 params->spr.bytes_per_pixel,
801bcfff 1556 mem_value);
23297044 1557 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1558 params->pipe_htotal,
c35426d2
VS		 1559 params->spr.horiz_pixels,
1560 params->spr.bytes_per_pixel,
801bcfff
PZ		 1561 mem_value);
1562 return min(method1, method2);
1563}
1564
37126462
VS		 1565/*
1566 * For both WM_PIPE and WM_LP.
1567 * mem_value must be in 0.1us units.
1568 */
820c1980 1569static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1570 uint32_t mem_value)
1571{
c35426d2 1572 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1573 return 0;
1574
23297044 1575 return ilk_wm_method2(params->pixel_rate,
801bcfff 1576 params->pipe_htotal,
c35426d2
VS		 1577 params->cur.horiz_pixels,
1578 params->cur.bytes_per_pixel,
801bcfff
PZ		 1579 mem_value);
1580}
1581
cca32e9a 1582/* Only for WM_LP. */
820c1980 1583static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1584 uint32_t pri_val)
cca32e9a 1585{
c35426d2 1586 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1587 return 0;
1588
23297044 1589 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1590 params->pri.horiz_pixels,
1591 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1592}
1593
158ae64f
VS		 1594static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1595{
416f4727
VS		 1596 if (INTEL_INFO(dev)->gen >= 8)
1597 return 3072;
1598 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1599 return 768;
1600 else
1601 return 512;
1602}
1603
4e975081
VS		 1604static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1605 int level, bool is_sprite)
1606{
1607 if (INTEL_INFO(dev)->gen >= 8)
1608 /* BDW primary/sprite plane watermarks */
1609 return level == 0 ? 255 : 2047;
1610 else if (INTEL_INFO(dev)->gen >= 7)
1611 /* IVB/HSW primary/sprite plane watermarks */
1612 return level == 0 ? 127 : 1023;
1613 else if (!is_sprite)
1614 /* ILK/SNB primary plane watermarks */
1615 return level == 0 ? 127 : 511;
1616 else
1617 /* ILK/SNB sprite plane watermarks */
1618 return level == 0 ? 63 : 255;
1619}
1620
1621static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1622 int level)
1623{
1624 if (INTEL_INFO(dev)->gen >= 7)
1625 return level == 0 ? 63 : 255;
1626 else
1627 return level == 0 ? 31 : 63;
1628}
1629
1630static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1631{
1632 if (INTEL_INFO(dev)->gen >= 8)
1633 return 31;
1634 else
1635 return 15;
1636}
1637
158ae64f
VS		 1638/* Calculate the maximum primary/sprite plane watermark */
1639static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1640 int level,
240264f4 1641 const struct intel_wm_config *config,
158ae64f
VS		 1642 enum intel_ddb_partitioning ddb_partitioning,
1643 bool is_sprite)
1644{
1645 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1646
1647 /* if sprites aren't enabled, sprites get nothing */
240264f4 1648 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1649 return 0;
1650
1651 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1652 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1653 fifo_size /= INTEL_INFO(dev)->num_pipes;
1654
1655 /*
1656 * For some reason the non self refresh
1657 * FIFO size is only half of the self
1658 * refresh FIFO size on ILK/SNB.
1659 */
1660 if (INTEL_INFO(dev)->gen <= 6)
1661 fifo_size /= 2;
1662 }
1663
240264f4 1664 if (config->sprites_enabled) {
158ae64f
VS		 1665 /* level 0 is always calculated with 1:1 split */
1666 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1667 if (is_sprite)
1668 fifo_size *= 5;
1669 fifo_size /= 6;
1670 } else {
1671 fifo_size /= 2;
1672 }
1673 }
1674
1675 /* clamp to max that the registers can hold */
4e975081 1676 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1677}
1678
1679/* Calculate the maximum cursor plane watermark */
1680static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1681 int level,
1682 const struct intel_wm_config *config)
158ae64f
VS		 1683{
1684 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1685 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1686 return 64;
1687
1688 /* otherwise just report max that registers can hold */
4e975081 1689 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1690}
1691
d34ff9c6 1692static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1693 int level,
1694 const struct intel_wm_config *config,
1695 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1696 struct ilk_wm_maximums *max)
158ae64f 1697{
240264f4
VS		 1698 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1699 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1700 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1701 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1702}
1703
a3cb4048
VS		 1704static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1705 int level,
1706 struct ilk_wm_maximums *max)
1707{
1708 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1709 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1710 max->cur = ilk_cursor_wm_reg_max(dev, level);
1711 max->fbc = ilk_fbc_wm_reg_max(dev);
1712}
1713
d9395655 1714static bool ilk_validate_wm_level(int level,
820c1980 1715 const struct ilk_wm_maximums *max,
d9395655 1716 struct intel_wm_level *result)
a9786a11
VS		 1717{
1718 bool ret;
1719
1720 /* already determined to be invalid? */
1721 if (!result->enable)
1722 return false;
1723
1724 result->enable = result->pri_val <= max->pri &&
1725 result->spr_val <= max->spr &&
1726 result->cur_val <= max->cur;
1727
1728 ret = result->enable;
1729
1730 /*
1731 * HACK until we can pre-compute everything,
1732 * and thus fail gracefully if LP0 watermarks
1733 * are exceeded...
1734 */
1735 if (level == 0 && !result->enable) {
1736 if (result->pri_val > max->pri)
1737 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1738 level, result->pri_val, max->pri);
1739 if (result->spr_val > max->spr)
1740 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1741 level, result->spr_val, max->spr);
1742 if (result->cur_val > max->cur)
1743 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1744 level, result->cur_val, max->cur);
1745
1746 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1747 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1748 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1749 result->enable = true;
1750 }
1751
a9786a11
VS		 1752 return ret;
1753}
1754
d34ff9c6 1755static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1756 int level,
820c1980 1757 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1758 struct intel_wm_level *result)
6f5ddd17
VS		 1759{
1760 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1761 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1762 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1763
1764 /* WM1+ latency values stored in 0.5us units */
1765 if (level > 0) {
1766 pri_latency *= 5;
1767 spr_latency *= 5;
1768 cur_latency *= 5;
1769 }
1770
1771 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1772 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1773 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1774 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1775 result->enable = true;
1776}
1777
801bcfff
PZ		 1778static uint32_t
1779hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1780{
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1783 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1784 u32 linetime, ips_linetime;
1f8eeabf 1785
3ef00284 1786 if (!intel_crtc->active)
801bcfff 1787 return 0;
1011d8c4 1788
1f8eeabf
ED		 1789 /* The WM are computed with base on how long it takes to fill a single
1790 * row at the given clock rate, multiplied by 8.
1791 * */
fec8cba3
JB		 1792 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1793 mode->crtc_clock);
1794 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
85a02deb 1795 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 1796
801bcfff
PZ		 1797 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1798 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1799}
1800
2af30a5c 1801static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 1802{
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804
2af30a5c
PB		 1805 if (IS_GEN9(dev)) {
1806 uint32_t val;
4f947386 1807 int ret, i;
367294be 1808 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 1809
1810 /* read the first set of memory latencies[0:3] */
1811 val = 0; /* data0 to be programmed to 0 for first set */
1812 mutex_lock(&dev_priv->rps.hw_lock);
1813 ret = sandybridge_pcode_read(dev_priv,
1814 GEN9_PCODE_READ_MEM_LATENCY,
1815 &val);
1816 mutex_unlock(&dev_priv->rps.hw_lock);
1817
1818 if (ret) {
1819 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1820 return;
1821 }
1822
1823 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1824 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1825 GEN9_MEM_LATENCY_LEVEL_MASK;
1826 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1827 GEN9_MEM_LATENCY_LEVEL_MASK;
1828 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1829 GEN9_MEM_LATENCY_LEVEL_MASK;
1830
1831 /* read the second set of memory latencies[4:7] */
1832 val = 1; /* data0 to be programmed to 1 for second set */
1833 mutex_lock(&dev_priv->rps.hw_lock);
1834 ret = sandybridge_pcode_read(dev_priv,
1835 GEN9_PCODE_READ_MEM_LATENCY,
1836 &val);
1837 mutex_unlock(&dev_priv->rps.hw_lock);
1838 if (ret) {
1839 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1840 return;
1841 }
1842
1843 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1844 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1845 GEN9_MEM_LATENCY_LEVEL_MASK;
1846 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1847 GEN9_MEM_LATENCY_LEVEL_MASK;
1848 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1849 GEN9_MEM_LATENCY_LEVEL_MASK;
1850
367294be 1851 /*
6f97235b
DL		 1852 * WaWmMemoryReadLatency:skl
1853 *
367294be
VK		 1854 * punit doesn't take into account the read latency so we need
1855 * to add 2us to the various latency levels we retrieve from
1856 * the punit.
1857 * - W0 is a bit special in that it's the only level that
1858 * can't be disabled if we want to have display working, so
1859 * we always add 2us there.
1860 * - For levels >=1, punit returns 0us latency when they are
1861 * disabled, so we respect that and don't add 2us then
4f947386
VK		 1862 *
1863 * Additionally, if a level n (n > 1) has a 0us latency, all
1864 * levels m (m >= n) need to be disabled. We make sure to
1865 * sanitize the values out of the punit to satisfy this
1866 * requirement.
367294be
VK		 1867 */
1868 wm[0] += 2;
1869 for (level = 1; level <= max_level; level++)
1870 if (wm[level] != 0)
1871 wm[level] += 2;
4f947386
VK		 1872 else {
1873 for (i = level + 1; i <= max_level; i++)
1874 wm[i] = 0;
367294be 1875
4f947386
VK		 1876 break;
1877 }
2af30a5c 1878 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 1879 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1880
1881 wm[0] = (sskpd >> 56) & 0xFF;
1882 if (wm[0] == 0)
1883 wm[0] = sskpd & 0xF;
e5d5019e
VS		 1884 wm[1] = (sskpd >> 4) & 0xFF;
1885 wm[2] = (sskpd >> 12) & 0xFF;
1886 wm[3] = (sskpd >> 20) & 0x1FF;
1887 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 1888 } else if (INTEL_INFO(dev)->gen >= 6) {
1889 uint32_t sskpd = I915_READ(MCH_SSKPD);
1890
1891 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1892 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1893 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1894 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 1895 } else if (INTEL_INFO(dev)->gen >= 5) {
1896 uint32_t mltr = I915_READ(MLTR_ILK);
1897
1898 /* ILK primary LP0 latency is 700 ns */
1899 wm[0] = 7;
1900 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1901 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 1902 }
1903}
1904
53615a5e
VS		 1905static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1906{
1907 /* ILK sprite LP0 latency is 1300 ns */
1908 if (INTEL_INFO(dev)->gen == 5)
1909 wm[0] = 13;
1910}
1911
1912static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1913{
1914 /* ILK cursor LP0 latency is 1300 ns */
1915 if (INTEL_INFO(dev)->gen == 5)
1916 wm[0] = 13;
1917
1918 /* WaDoubleCursorLP3Latency:ivb */
1919 if (IS_IVYBRIDGE(dev))
1920 wm[3] *= 2;
1921}
1922
546c81fd 1923int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1924{
26ec971e 1925 /* how many WM levels are we expecting */
2af30a5c
PB		 1926 if (IS_GEN9(dev))
1927 return 7;
1928 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1929 return 4;
26ec971e 1930 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1931 return 3;
26ec971e 1932 else
ad0d6dc4
VS		 1933 return 2;
1934}
7526ed79 1935
ad0d6dc4
VS		 1936static void intel_print_wm_latency(struct drm_device *dev,
1937 const char *name,
2af30a5c 1938 const uint16_t wm[8])
ad0d6dc4
VS		 1939{
1940 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 1941
1942 for (level = 0; level <= max_level; level++) {
1943 unsigned int latency = wm[level];
1944
1945 if (latency == 0) {
1946 DRM_ERROR("%s WM%d latency not provided\n",
1947 name, level);
1948 continue;
1949 }
1950
2af30a5c
PB		 1951 /*
1952 * - latencies are in us on gen9.
1953 * - before then, WM1+ latency values are in 0.5us units
1954 */
1955 if (IS_GEN9(dev))
1956 latency *= 10;
1957 else if (level > 0)
26ec971e
VS		 1958 latency *= 5;
1959
1960 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1961 name, level, wm[level],
1962 latency / 10, latency % 10);
1963 }
1964}
1965
e95a2f75
VS		 1966static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1967 uint16_t wm[5], uint16_t min)
1968{
1969 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1970
1971 if (wm[0] >= min)
1972 return false;
1973
1974 wm[0] = max(wm[0], min);
1975 for (level = 1; level <= max_level; level++)
1976 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1977
1978 return true;
1979}
1980
1981static void snb_wm_latency_quirk(struct drm_device *dev)
1982{
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984 bool changed;
1985
1986 /*
1987 * The BIOS provided WM memory latency values are often
1988 * inadequate for high resolution displays. Adjust them.
1989 */
1990 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
1991 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
1992 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
1993
1994 if (!changed)
1995 return;
1996
1997 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
1998 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
1999 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2000 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2001}
2002
fa50ad61 2003static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2004{
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006
2007 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2008
2009 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2010 sizeof(dev_priv->wm.pri_latency));
2011 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2012 sizeof(dev_priv->wm.pri_latency));
2013
2014 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2015 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2016
2017 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2018 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2019 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2020
2021 if (IS_GEN6(dev))
2022 snb_wm_latency_quirk(dev);
53615a5e
VS		 2023}
2024
2af30a5c
PB		 2025static void skl_setup_wm_latency(struct drm_device *dev)
2026{
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028
2029 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2030 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2031}
2032
820c1980 2033static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2034 struct ilk_pipe_wm_parameters *p)
1011d8c4 2035{
7c4a395f
VS		 2036 struct drm_device *dev = crtc->dev;
2037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2038 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2039 struct drm_plane *plane;
1011d8c4 2040
3ef00284 2041 if (!intel_crtc->active)
2a44b76b 2042 return;
801bcfff 2043
2a44b76b 2044 p->active = true;
6e3c9717 2045 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2a44b76b 2046 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c9f038a1
MR		 2047
2048 if (crtc->primary->state->fb) {
2049 p->pri.enabled = true;
2050 p->pri.bytes_per_pixel =
2051 crtc->primary->state->fb->bits_per_pixel / 8;
2052 } else {
2053 p->pri.enabled = false;
2054 p->pri.bytes_per_pixel = 0;
2055 }
2056
2057 if (crtc->cursor->state->fb) {
2058 p->cur.enabled = true;
2059 p->cur.bytes_per_pixel = 4;
2060 } else {
2061 p->cur.enabled = false;
2062 p->cur.bytes_per_pixel = 0;
2063 }
6e3c9717 2064 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2065 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2066
af2b653b 2067 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2068 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2069
2a44b76b 2070 if (intel_plane->pipe == pipe) {
7c4a395f 2071 p->spr = intel_plane->wm;
2a44b76b
VS		 2072 break;
2073 }
2074 }
2075}
2076
2077static void ilk_compute_wm_config(struct drm_device *dev,
2078 struct intel_wm_config *config)
2079{
2080 struct intel_crtc *intel_crtc;
2081
2082 /* Compute the currently _active_ config */
d3fcc808 2083 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2084 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2085
2a44b76b
VS		 2086 if (!wm->pipe_enabled)
2087 continue;
cca32e9a 2088
2a44b76b
VS		 2089 config->sprites_enabled |= wm->sprites_enabled;
2090 config->sprites_scaled |= wm->sprites_scaled;
2091 config->num_pipes_active++;
cca32e9a 2092 }
801bcfff
PZ		 2093}
2094
0b2ae6d7
VS		 2095/* Compute new watermarks for the pipe */
2096static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2097 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2098 struct intel_pipe_wm *pipe_wm)
2099{
2100 struct drm_device *dev = crtc->dev;
d34ff9c6 2101 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2102 int level, max_level = ilk_wm_max_level(dev);
2103 /* LP0 watermark maximums depend on this pipe alone */
2104 struct intel_wm_config config = {
2105 .num_pipes_active = 1,
2106 .sprites_enabled = params->spr.enabled,
2107 .sprites_scaled = params->spr.scaled,
2108 };
820c1980 2109 struct ilk_wm_maximums max;
0b2ae6d7 2110
2a44b76b
VS		 2111 pipe_wm->pipe_enabled = params->active;
2112 pipe_wm->sprites_enabled = params->spr.enabled;
2113 pipe_wm->sprites_scaled = params->spr.scaled;
2114
7b39a0b7
VS		 2115 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2116 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2117 max_level = 1;
2118
2119 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2120 if (params->spr.scaled)
2121 max_level = 0;
2122
a3cb4048 2123 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2124
a42a5719 2125 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2126 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2127
a3cb4048
VS		 2128 /* LP0 watermarks always use 1/2 DDB partitioning */
2129 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2130
0b2ae6d7 2131 /* At least LP0 must be valid */
a3cb4048
VS		 2132 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2133 return false;
2134
2135 ilk_compute_wm_reg_maximums(dev, 1, &max);
2136
2137 for (level = 1; level <= max_level; level++) {
2138 struct intel_wm_level wm = {};
2139
2140 ilk_compute_wm_level(dev_priv, level, params, &wm);
2141
2142 /*
2143 * Disable any watermark level that exceeds the
2144 * register maximums since such watermarks are
2145 * always invalid.
2146 */
2147 if (!ilk_validate_wm_level(level, &max, &wm))
2148 break;
2149
2150 pipe_wm->wm[level] = wm;
2151 }
2152
2153 return true;
0b2ae6d7
VS		 2154}
2155
2156/*
2157 * Merge the watermarks from all active pipes for a specific level.
2158 */
2159static void ilk_merge_wm_level(struct drm_device *dev,
2160 int level,
2161 struct intel_wm_level *ret_wm)
2162{
2163 const struct intel_crtc *intel_crtc;
2164
d52fea5b
VS		 2165 ret_wm->enable = true;
2166
d3fcc808 2167 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2168 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2169 const struct intel_wm_level *wm = &active->wm[level];
2170
2171 if (!active->pipe_enabled)
2172 continue;
0b2ae6d7 2173
d52fea5b
VS		 2174 /*
2175 * The watermark values may have been used in the past,
2176 * so we must maintain them in the registers for some
2177 * time even if the level is now disabled.
2178 */
0b2ae6d7 2179 if (!wm->enable)
d52fea5b 2180 ret_wm->enable = false;
0b2ae6d7
VS		 2181
2182 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2183 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2184 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2185 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2186 }
0b2ae6d7
VS		 2187}
2188
2189/*
2190 * Merge all low power watermarks for all active pipes.
2191 */
2192static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2193 const struct intel_wm_config *config,
820c1980 2194 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2195 struct intel_pipe_wm *merged)
2196{
2197 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2198 int last_enabled_level = max_level;
0b2ae6d7 2199
0ba22e26
VS		 2200 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2201 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2202 config->num_pipes_active > 1)
2203 return;
2204
6c8b6c28
VS		 2205 /* ILK: FBC WM must be disabled always */
2206 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2207
2208 /* merge each WM1+ level */
2209 for (level = 1; level <= max_level; level++) {
2210 struct intel_wm_level *wm = &merged->wm[level];
2211
2212 ilk_merge_wm_level(dev, level, wm);
2213
d52fea5b
VS		 2214 if (level > last_enabled_level)
2215 wm->enable = false;
2216 else if (!ilk_validate_wm_level(level, max, wm))
2217 /* make sure all following levels get disabled */
2218 last_enabled_level = level - 1;
0b2ae6d7
VS		 2219
2220 /*
2221 * The spec says it is preferred to disable
2222 * FBC WMs instead of disabling a WM level.
2223 */
2224 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2225 if (wm->enable)
2226 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2227 wm->fbc_val = 0;
2228 }
2229 }
6c8b6c28
VS		 2230
2231 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2232 /*
2233 * FIXME this is racy. FBC might get enabled later.
2234 * What we should check here is whether FBC can be
2235 * enabled sometime later.
2236 */
2237 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2238 for (level = 2; level <= max_level; level++) {
2239 struct intel_wm_level *wm = &merged->wm[level];
2240
2241 wm->enable = false;
2242 }
2243 }
0b2ae6d7
VS		 2244}
2245
b380ca3c
VS		 2246static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2247{
2248 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2249 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2250}
2251
a68d68ee
VS		 2252/* The value we need to program into the WM_LPx latency field */
2253static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2254{
2255 struct drm_i915_private *dev_priv = dev->dev_private;
2256
a42a5719 2257 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2258 return 2 * level;
2259 else
2260 return dev_priv->wm.pri_latency[level];
2261}
2262
820c1980 2263static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2264 const struct intel_pipe_wm *merged,
609cedef 2265 enum intel_ddb_partitioning partitioning,
820c1980 2266 struct ilk_wm_values *results)
801bcfff 2267{
0b2ae6d7
VS		 2268 struct intel_crtc *intel_crtc;
2269 int level, wm_lp;
cca32e9a 2270
0362c781 2271 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2272 results->partitioning = partitioning;
cca32e9a 2273
0b2ae6d7 2274 /* LP1+ register values */
cca32e9a 2275 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2276 const struct intel_wm_level *r;
801bcfff 2277
b380ca3c 2278 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2279
0362c781 2280 r = &merged->wm[level];
cca32e9a 2281
d52fea5b
VS		 2282 /*
2283 * Maintain the watermark values even if the level is
2284 * disabled. Doing otherwise could cause underruns.
2285 */
2286 results->wm_lp[wm_lp - 1] =
a68d68ee 2287 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2288 (r->pri_val << WM1_LP_SR_SHIFT) |
2289 r->cur_val;
2290
d52fea5b
VS		 2291 if (r->enable)
2292 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2293
416f4727
VS		 2294 if (INTEL_INFO(dev)->gen >= 8)
2295 results->wm_lp[wm_lp - 1] |=
2296 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2297 else
2298 results->wm_lp[wm_lp - 1] |=
2299 r->fbc_val << WM1_LP_FBC_SHIFT;
2300
d52fea5b
VS		 2301 /*
2302 * Always set WM1S_LP_EN when spr_val != 0, even if the
2303 * level is disabled. Doing otherwise could cause underruns.
2304 */
6cef2b8a
VS		 2305 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2306 WARN_ON(wm_lp != 1);
2307 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2308 } else
2309 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2310 }
801bcfff 2311
0b2ae6d7 2312 /* LP0 register values */
d3fcc808 2313 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2314 enum pipe pipe = intel_crtc->pipe;
2315 const struct intel_wm_level *r =
2316 &intel_crtc->wm.active.wm[0];
2317
2318 if (WARN_ON(!r->enable))
2319 continue;
2320
2321 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2322
0b2ae6d7
VS		 2323 results->wm_pipe[pipe] =
2324 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2325 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2326 r->cur_val;
801bcfff
PZ		 2327 }
2328}
2329
861f3389
PZ		 2330/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2331 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2332static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2333 struct intel_pipe_wm *r1,
2334 struct intel_pipe_wm *r2)
861f3389 2335{
198a1e9b
VS		 2336 int level, max_level = ilk_wm_max_level(dev);
2337 int level1 = 0, level2 = 0;
861f3389 2338
198a1e9b
VS		 2339 for (level = 1; level <= max_level; level++) {
2340 if (r1->wm[level].enable)
2341 level1 = level;
2342 if (r2->wm[level].enable)
2343 level2 = level;
861f3389
PZ		 2344 }
2345
198a1e9b
VS		 2346 if (level1 == level2) {
2347 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2348 return r2;
2349 else
2350 return r1;
198a1e9b 2351 } else if (level1 > level2) {
861f3389
PZ		 2352 return r1;
2353 } else {
2354 return r2;
2355 }
2356}
2357
49a687c4
VS		 2358/* dirty bits used to track which watermarks need changes */
2359#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2360#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2361#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2362#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2363#define WM_DIRTY_FBC (1 << 24)
2364#define WM_DIRTY_DDB (1 << 25)
2365
055e393f 2366static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2367 const struct ilk_wm_values *old,
2368 const struct ilk_wm_values *new)
49a687c4
VS		 2369{
2370 unsigned int dirty = 0;
2371 enum pipe pipe;
2372 int wm_lp;
2373
055e393f 2374 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2375 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2376 dirty |= WM_DIRTY_LINETIME(pipe);
2377 /* Must disable LP1+ watermarks too */
2378 dirty |= WM_DIRTY_LP_ALL;
2379 }
2380
2381 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2382 dirty |= WM_DIRTY_PIPE(pipe);
2383 /* Must disable LP1+ watermarks too */
2384 dirty |= WM_DIRTY_LP_ALL;
2385 }
2386 }
2387
2388 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2389 dirty |= WM_DIRTY_FBC;
2390 /* Must disable LP1+ watermarks too */
2391 dirty |= WM_DIRTY_LP_ALL;
2392 }
2393
2394 if (old->partitioning != new->partitioning) {
2395 dirty |= WM_DIRTY_DDB;
2396 /* Must disable LP1+ watermarks too */
2397 dirty |= WM_DIRTY_LP_ALL;
2398 }
2399
2400 /* LP1+ watermarks already deemed dirty, no need to continue */
2401 if (dirty & WM_DIRTY_LP_ALL)
2402 return dirty;
2403
2404 /* Find the lowest numbered LP1+ watermark in need of an update... */
2405 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2406 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2407 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2408 break;
2409 }
2410
2411 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2412 for (; wm_lp <= 3; wm_lp++)
2413 dirty |= WM_DIRTY_LP(wm_lp);
2414
2415 return dirty;
2416}
2417
8553c18e
VS		 2418static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2419 unsigned int dirty)
801bcfff 2420{
820c1980 2421 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2422 bool changed = false;
801bcfff 2423
facd619b
VS		 2424 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2425 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2426 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2427 changed = true;
facd619b
VS		 2428 }
2429 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2430 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2431 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2432 changed = true;
facd619b
VS		 2433 }
2434 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2435 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2436 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2437 changed = true;
facd619b 2438 }
801bcfff 2439
facd619b
VS		 2440 /*
2441 * Don't touch WM1S_LP_EN here.
2442 * Doing so could cause underruns.
2443 */
6cef2b8a 2444
8553c18e
VS		 2445 return changed;
2446}
2447
2448/*
2449 * The spec says we shouldn't write when we don't need, because every write
2450 * causes WMs to be re-evaluated, expending some power.
2451 */
820c1980
ID		 2452static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2453 struct ilk_wm_values *results)
8553c18e
VS		 2454{
2455 struct drm_device *dev = dev_priv->dev;
820c1980 2456 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2457 unsigned int dirty;
2458 uint32_t val;
2459
055e393f 2460 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2461 if (!dirty)
2462 return;
2463
2464 _ilk_disable_lp_wm(dev_priv, dirty);
2465
49a687c4 2466 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2467 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2468 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2469 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2470 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2471 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2472
49a687c4 2473 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2474 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2475 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2476 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2477 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2478 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2479
49a687c4 2480 if (dirty & WM_DIRTY_DDB) {
a42a5719 2481 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2482 val = I915_READ(WM_MISC);
2483 if (results->partitioning == INTEL_DDB_PART_1_2)
2484 val &= ~WM_MISC_DATA_PARTITION_5_6;
2485 else
2486 val |= WM_MISC_DATA_PARTITION_5_6;
2487 I915_WRITE(WM_MISC, val);
2488 } else {
2489 val = I915_READ(DISP_ARB_CTL2);
2490 if (results->partitioning == INTEL_DDB_PART_1_2)
2491 val &= ~DISP_DATA_PARTITION_5_6;
2492 else
2493 val |= DISP_DATA_PARTITION_5_6;
2494 I915_WRITE(DISP_ARB_CTL2, val);
2495 }
1011d8c4
PZ		 2496 }
2497
49a687c4 2498 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2499 val = I915_READ(DISP_ARB_CTL);
2500 if (results->enable_fbc_wm)
2501 val &= ~DISP_FBC_WM_DIS;
2502 else
2503 val |= DISP_FBC_WM_DIS;
2504 I915_WRITE(DISP_ARB_CTL, val);
2505 }
2506
954911eb
ID		 2507 if (dirty & WM_DIRTY_LP(1) &&
2508 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2509 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2510
2511 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2512 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2513 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2514 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2515 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2516 }
801bcfff 2517
facd619b 2518 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2519 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2520 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2521 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2522 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2523 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2524
2525 dev_priv->wm.hw = *results;
801bcfff
PZ		 2526}
2527
8553c18e
VS		 2528static bool ilk_disable_lp_wm(struct drm_device *dev)
2529{
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531
2532 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2533}
2534
b9cec075
DL		 2535/*
2536 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2537 * different active planes.
2538 */
2539
2540#define SKL_DDB_SIZE 896 /* in blocks */
2541
2542static void
2543skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2544 struct drm_crtc *for_crtc,
2545 const struct intel_wm_config *config,
2546 const struct skl_pipe_wm_parameters *params,
2547 struct skl_ddb_entry *alloc /* out */)
2548{
2549 struct drm_crtc *crtc;
2550 unsigned int pipe_size, ddb_size;
2551 int nth_active_pipe;
2552
2553 if (!params->active) {
2554 alloc->start = 0;
2555 alloc->end = 0;
2556 return;
2557 }
2558
2559 ddb_size = SKL_DDB_SIZE;
2560
2561 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2562
2563 nth_active_pipe = 0;
2564 for_each_crtc(dev, crtc) {
3ef00284 2565 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2566 continue;
2567
2568 if (crtc == for_crtc)
2569 break;
2570
2571 nth_active_pipe++;
2572 }
2573
2574 pipe_size = ddb_size / config->num_pipes_active;
2575 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2576 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2577}
2578
2579static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2580{
2581 if (config->num_pipes_active == 1)
2582 return 32;
2583
2584 return 8;
2585}
2586
a269c583
DL		 2587static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2588{
2589 entry->start = reg & 0x3ff;
2590 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2591 if (entry->end)
2592 entry->end += 1;
a269c583
DL		 2593}
2594
08db6652
DL		 2595void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2596 struct skl_ddb_allocation *ddb /* out */)
a269c583 2597{
a269c583
DL		 2598 enum pipe pipe;
2599 int plane;
2600 u32 val;
2601
2602 for_each_pipe(dev_priv, pipe) {
dd740780 2603 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2604 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2605 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2606 val);
2607 }
2608
2609 val = I915_READ(CUR_BUF_CFG(pipe));
2610 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2611 }
2612}
2613
b9cec075
DL		 2614static unsigned int
2615skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p)
2616{
2617 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2618}
2619
2620/*
2621 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2622 * a 8192x4096@32bpp framebuffer:
2623 * 3 * 4096 * 8192 * 4 < 2^32
2624 */
2625static unsigned int
2626skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2627 const struct skl_pipe_wm_parameters *params)
2628{
2629 unsigned int total_data_rate = 0;
2630 int plane;
2631
2632 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2633 const struct intel_plane_wm_parameters *p;
2634
2635 p = &params->plane[plane];
2636 if (!p->enabled)
2637 continue;
2638
2639 total_data_rate += skl_plane_relative_data_rate(p);
2640 }
2641
2642 return total_data_rate;
2643}
2644
2645static void
2646skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2647 const struct intel_wm_config *config,
2648 const struct skl_pipe_wm_parameters *params,
2649 struct skl_ddb_allocation *ddb /* out */)
2650{
2651 struct drm_device *dev = crtc->dev;
dd740780 2652 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2654 enum pipe pipe = intel_crtc->pipe;
34bb56af 2655 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2656 uint16_t alloc_size, start, cursor_blocks;
80958155 2657 uint16_t minimum[I915_MAX_PLANES];
b9cec075
DL		 2658 unsigned int total_data_rate;
2659 int plane;
2660
34bb56af
DL		 2661 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2662 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2663 if (alloc_size == 0) {
2664 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2665 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2666 return;
2667 }
2668
2669 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2670 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2671 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2672
2673 alloc_size -= cursor_blocks;
34bb56af 2674 alloc->end -= cursor_blocks;
b9cec075 2675
80958155 2676 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2677 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2678 const struct intel_plane_wm_parameters *p;
2679
2680 p = &params->plane[plane];
2681 if (!p->enabled)
2682 continue;
2683
2684 minimum[plane] = 8;
2685 alloc_size -= minimum[plane];
2686 }
2687
b9cec075 2688 /*
80958155
DL		 2689 * 2. Distribute the remaining space in proportion to the amount of
2690 * data each plane needs to fetch from memory.
b9cec075
DL		 2691 *
2692 * FIXME: we may not allocate every single block here.
2693 */
2694 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2695
34bb56af 2696 start = alloc->start;
b9cec075
DL		 2697 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2698 const struct intel_plane_wm_parameters *p;
2699 unsigned int data_rate;
2700 uint16_t plane_blocks;
2701
2702 p = &params->plane[plane];
2703 if (!p->enabled)
2704 continue;
2705
2706 data_rate = skl_plane_relative_data_rate(p);
2707
2708 /*
2709 * promote the expression to 64 bits to avoid overflowing, the
2710 * result is < available as data_rate / total_data_rate < 1
2711 */
80958155
DL		 2712 plane_blocks = minimum[plane];
2713 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2714 total_data_rate);
b9cec075
DL		 2715
2716 ddb->plane[pipe][plane].start = start;
16160e3d 2717 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 2718
2719 start += plane_blocks;
2720 }
2721
2722}
2723
5cec258b 2724static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 2725{
2726 /* TODO: Take into account the scalers once we support them */
2d112de7 2727 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 2728}
2729
2730/*
2731 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2732 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2733 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2734 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2735*/
2736static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2737 uint32_t latency)
2738{
2739 uint32_t wm_intermediate_val, ret;
2740
2741 if (latency == 0)
2742 return UINT_MAX;
2743
d4c2aa60 2744 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 2745 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2746
2747 return ret;
2748}
2749
2750static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2751 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 2752 uint64_t tiling, uint32_t latency)
2d41c0b5 2753{
d4c2aa60
TU		 2754 uint32_t ret;
2755 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2756 uint32_t wm_intermediate_val;
2d41c0b5
PB		 2757
2758 if (latency == 0)
2759 return UINT_MAX;
2760
2761 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 2762
2763 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2764 tiling == I915_FORMAT_MOD_Yf_TILED) {
2765 plane_bytes_per_line *= 4;
2766 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2767 plane_blocks_per_line /= 4;
2768 } else {
2769 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2770 }
2771
2d41c0b5
PB		 2772 wm_intermediate_val = latency * pixel_rate;
2773 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 2774 plane_blocks_per_line;
2d41c0b5
PB		 2775
2776 return ret;
2777}
2778
2d41c0b5
PB		 2779static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2780 const struct intel_crtc *intel_crtc)
2781{
2782 struct drm_device *dev = intel_crtc->base.dev;
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2785 enum pipe pipe = intel_crtc->pipe;
2786
2787 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2788 sizeof(new_ddb->plane[pipe])))
2789 return true;
2790
2791 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2792 sizeof(new_ddb->cursor[pipe])))
2793 return true;
2794
2795 return false;
2796}
2797
2798static void skl_compute_wm_global_parameters(struct drm_device *dev,
2799 struct intel_wm_config *config)
2800{
2801 struct drm_crtc *crtc;
2802 struct drm_plane *plane;
2803
2804 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 2805 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 2806
2807 /* FIXME: I don't think we need those two global parameters on SKL */
2808 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2809 struct intel_plane *intel_plane = to_intel_plane(plane);
2810
2811 config->sprites_enabled |= intel_plane->wm.enabled;
2812 config->sprites_scaled |= intel_plane->wm.scaled;
2813 }
2814}
2815
2816static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2817 struct skl_pipe_wm_parameters *p)
2818{
2819 struct drm_device *dev = crtc->dev;
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821 enum pipe pipe = intel_crtc->pipe;
2822 struct drm_plane *plane;
0fda6568 2823 struct drm_framebuffer *fb;
2d41c0b5
PB		 2824 int i = 1; /* Index for sprite planes start */
2825
3ef00284 2826 p->active = intel_crtc->active;
2d41c0b5 2827 if (p->active) {
6e3c9717
ACO		 2828 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2829 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 2830
0fda6568 2831 fb = crtc->primary->state->fb;
c9f038a1
MR		 2832 if (fb) {
2833 p->plane[0].enabled = true;
2834 p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8;
0fda6568 2835 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 2836 } else {
2837 p->plane[0].enabled = false;
2838 p->plane[0].bytes_per_pixel = 0;
2839 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2840 }
2841 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2842 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
2d41c0b5 2843
c9f038a1
MR		 2844 fb = crtc->cursor->state->fb;
2845 if (fb) {
2846 p->cursor.enabled = true;
2847 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2848 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2849 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2850 } else {
2851 p->cursor.enabled = false;
2852 p->cursor.bytes_per_pixel = 0;
2853 p->cursor.horiz_pixels = 64;
2854 p->cursor.vert_pixels = 64;
2855 }
2d41c0b5
PB		 2856 }
2857
2858 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2859 struct intel_plane *intel_plane = to_intel_plane(plane);
2860
a712f8eb
SJ		 2861 if (intel_plane->pipe == pipe &&
2862 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 2863 p->plane[i++] = intel_plane->wm;
2864 }
2865}
2866
d4c2aa60
TU		 2867static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2868 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 2869 struct intel_plane_wm_parameters *p_params,
2870 uint16_t ddb_allocation,
d4c2aa60 2871 int level,
afb024aa
DL		 2872 uint16_t *out_blocks, /* out */
2873 uint8_t *out_lines /* out */)
2d41c0b5 2874{
d4c2aa60
TU		 2875 uint32_t latency = dev_priv->wm.skl_latency[level];
2876 uint32_t method1, method2;
2877 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2878 uint32_t res_blocks, res_lines;
2879 uint32_t selected_result;
2d41c0b5 2880
d4c2aa60 2881 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 2882 return false;
2883
2884 method1 = skl_wm_method1(p->pixel_rate,
2885 p_params->bytes_per_pixel,
d4c2aa60 2886 latency);
2d41c0b5
PB		 2887 method2 = skl_wm_method2(p->pixel_rate,
2888 p->pipe_htotal,
2889 p_params->horiz_pixels,
2890 p_params->bytes_per_pixel,
0fda6568 2891 p_params->tiling,
d4c2aa60 2892 latency);
2d41c0b5
PB		 2893
2894 plane_bytes_per_line = p_params->horiz_pixels *
2895 p_params->bytes_per_pixel;
d4c2aa60 2896 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 2897
0fda6568
TU		 2898 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2899 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
2900 uint32_t y_tile_minimum = plane_blocks_per_line * 4;
2901 selected_result = max(method2, y_tile_minimum);
2902 } else {
2903 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2904 selected_result = min(method1, method2);
2905 else
2906 selected_result = method1;
2907 }
2d41c0b5 2908
d4c2aa60
TU		 2909 res_blocks = selected_result + 1;
2910 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 2911
0fda6568
TU		 2912 if (level >= 1 && level <= 7) {
2913 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2914 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2915 res_lines += 4;
2916 else
2917 res_blocks++;
2918 }
e6d66171 2919
d4c2aa60 2920 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 2921 return false;
2922
2923 *out_blocks = res_blocks;
2924 *out_lines = res_lines;
2d41c0b5
PB		 2925
2926 return true;
2927}
2928
2929static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
2930 struct skl_ddb_allocation *ddb,
2931 struct skl_pipe_wm_parameters *p,
2932 enum pipe pipe,
2933 int level,
2934 int num_planes,
2935 struct skl_wm_level *result)
2936{
2d41c0b5
PB		 2937 uint16_t ddb_blocks;
2938 int i;
2939
2940 for (i = 0; i < num_planes; i++) {
2941 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2942
d4c2aa60
TU		 2943 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
2944 p, &p->plane[i],
2d41c0b5 2945 ddb_blocks,
d4c2aa60 2946 level,
2d41c0b5
PB		 2947 &result->plane_res_b[i],
2948 &result->plane_res_l[i]);
2949 }
2950
2951 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 2952 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
2953 ddb_blocks, level,
2954 &result->cursor_res_b,
2d41c0b5
PB		 2955 &result->cursor_res_l);
2956}
2957
407b50f3
DL		 2958static uint32_t
2959skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
2960{
3ef00284 2961 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 2962 return 0;
2963
2964 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
2965
2966}
2967
2968static void skl_compute_transition_wm(struct drm_crtc *crtc,
2969 struct skl_pipe_wm_parameters *params,
9414f563 2970 struct skl_wm_level *trans_wm /* out */)
407b50f3 2971{
9414f563
DL		 2972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2973 int i;
2974
407b50f3
DL		 2975 if (!params->active)
2976 return;
9414f563
DL		 2977
2978 /* Until we know more, just disable transition WMs */
2979 for (i = 0; i < intel_num_planes(intel_crtc); i++)
2980 trans_wm->plane_en[i] = false;
2981 trans_wm->cursor_en = false;
407b50f3
DL		 2982}
2983
2d41c0b5
PB		 2984static void skl_compute_pipe_wm(struct drm_crtc *crtc,
2985 struct skl_ddb_allocation *ddb,
2986 struct skl_pipe_wm_parameters *params,
2987 struct skl_pipe_wm *pipe_wm)
2988{
2989 struct drm_device *dev = crtc->dev;
2990 const struct drm_i915_private *dev_priv = dev->dev_private;
2991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2992 int level, max_level = ilk_wm_max_level(dev);
2993
2994 for (level = 0; level <= max_level; level++) {
2995 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
2996 level, intel_num_planes(intel_crtc),
2997 &pipe_wm->wm[level]);
2998 }
2999 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3000
9414f563 3001 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3002}
3003
3004static void skl_compute_wm_results(struct drm_device *dev,
3005 struct skl_pipe_wm_parameters *p,
3006 struct skl_pipe_wm *p_wm,
3007 struct skl_wm_values *r,
3008 struct intel_crtc *intel_crtc)
3009{
3010 int level, max_level = ilk_wm_max_level(dev);
3011 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3012 uint32_t temp;
3013 int i;
2d41c0b5
PB		 3014
3015 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3016 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3017 temp = 0;
2d41c0b5
PB		 3018
3019 temp |= p_wm->wm[level].plane_res_l[i] <<
3020 PLANE_WM_LINES_SHIFT;
3021 temp |= p_wm->wm[level].plane_res_b[i];
3022 if (p_wm->wm[level].plane_en[i])
3023 temp |= PLANE_WM_EN;
3024
3025 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3026 }
3027
3028 temp = 0;
2d41c0b5
PB		 3029
3030 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3031 temp |= p_wm->wm[level].cursor_res_b;
3032
3033 if (p_wm->wm[level].cursor_en)
3034 temp |= PLANE_WM_EN;
3035
3036 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3037
3038 }
3039
9414f563
DL		 3040 /* transition WMs */
3041 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3042 temp = 0;
3043 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3044 temp |= p_wm->trans_wm.plane_res_b[i];
3045 if (p_wm->trans_wm.plane_en[i])
3046 temp |= PLANE_WM_EN;
3047
3048 r->plane_trans[pipe][i] = temp;
3049 }
3050
3051 temp = 0;
3052 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3053 temp |= p_wm->trans_wm.cursor_res_b;
3054 if (p_wm->trans_wm.cursor_en)
3055 temp |= PLANE_WM_EN;
3056
3057 r->cursor_trans[pipe] = temp;
3058
2d41c0b5
PB		 3059 r->wm_linetime[pipe] = p_wm->linetime;
3060}
3061
16160e3d
DL		 3062static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3063 const struct skl_ddb_entry *entry)
3064{
3065 if (entry->end)
3066 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3067 else
3068 I915_WRITE(reg, 0);
3069}
3070
2d41c0b5
PB		 3071static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3072 const struct skl_wm_values *new)
3073{
3074 struct drm_device *dev = dev_priv->dev;
3075 struct intel_crtc *crtc;
3076
3077 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3078 int i, level, max_level = ilk_wm_max_level(dev);
3079 enum pipe pipe = crtc->pipe;
3080
5d374d96
DL		 3081 if (!new->dirty[pipe])
3082 continue;
8211bd5b 3083
5d374d96 3084 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3085
5d374d96
DL		 3086 for (level = 0; level <= max_level; level++) {
3087 for (i = 0; i < intel_num_planes(crtc); i++)
3088 I915_WRITE(PLANE_WM(pipe, i, level),
3089 new->plane[pipe][i][level]);
3090 I915_WRITE(CUR_WM(pipe, level),
3091 new->cursor[pipe][level]);
2d41c0b5 3092 }
5d374d96
DL		 3093 for (i = 0; i < intel_num_planes(crtc); i++)
3094 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3095 new->plane_trans[pipe][i]);
3096 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3097
3098 for (i = 0; i < intel_num_planes(crtc); i++)
3099 skl_ddb_entry_write(dev_priv,
3100 PLANE_BUF_CFG(pipe, i),
3101 &new->ddb.plane[pipe][i]);
3102
3103 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3104 &new->ddb.cursor[pipe]);
2d41c0b5 3105 }
2d41c0b5
PB		 3106}
3107
0e8fb7ba
DL		 3108/*
3109 * When setting up a new DDB allocation arrangement, we need to correctly
3110 * sequence the times at which the new allocations for the pipes are taken into
3111 * account or we'll have pipes fetching from space previously allocated to
3112 * another pipe.
3113 *
3114 * Roughly the sequence looks like:
3115 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3116 * overlapping with a previous light-up pipe (another way to put it is:
3117 * pipes with their new allocation strickly included into their old ones).
3118 * 2. re-allocate the other pipes that get their allocation reduced
3119 * 3. allocate the pipes having their allocation increased
3120 *
3121 * Steps 1. and 2. are here to take care of the following case:
3122 * - Initially DDB looks like this:
3123 * | B | C |
3124 * - enable pipe A.
3125 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3126 * allocation
3127 * | A | B | C |
3128 *
3129 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3130 */
3131
d21b795c
DL		 3132static void
3133skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3134{
0e8fb7ba
DL		 3135 int plane;
3136
d21b795c
DL		 3137 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3138
dd740780 3139 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3140 I915_WRITE(PLANE_SURF(pipe, plane),
3141 I915_READ(PLANE_SURF(pipe, plane)));
3142 }
3143 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3144}
3145
3146static bool
3147skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3148 const struct skl_ddb_allocation *new,
3149 enum pipe pipe)
3150{
3151 uint16_t old_size, new_size;
3152
3153 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3154 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3155
3156 return old_size != new_size &&
3157 new->pipe[pipe].start >= old->pipe[pipe].start &&
3158 new->pipe[pipe].end <= old->pipe[pipe].end;
3159}
3160
3161static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3162 struct skl_wm_values *new_values)
3163{
3164 struct drm_device *dev = dev_priv->dev;
3165 struct skl_ddb_allocation *cur_ddb, *new_ddb;
3166 bool reallocated[I915_MAX_PIPES] = {false, false, false};
3167 struct intel_crtc *crtc;
3168 enum pipe pipe;
3169
3170 new_ddb = &new_values->ddb;
3171 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3172
3173 /*
3174 * First pass: flush the pipes with the new allocation contained into
3175 * the old space.
3176 *
3177 * We'll wait for the vblank on those pipes to ensure we can safely
3178 * re-allocate the freed space without this pipe fetching from it.
3179 */
3180 for_each_intel_crtc(dev, crtc) {
3181 if (!crtc->active)
3182 continue;
3183
3184 pipe = crtc->pipe;
3185
3186 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3187 continue;
3188
d21b795c 3189 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3190 intel_wait_for_vblank(dev, pipe);
3191
3192 reallocated[pipe] = true;
3193 }
3194
3195
3196 /*
3197 * Second pass: flush the pipes that are having their allocation
3198 * reduced, but overlapping with a previous allocation.
3199 *
3200 * Here as well we need to wait for the vblank to make sure the freed
3201 * space is not used anymore.
3202 */
3203 for_each_intel_crtc(dev, crtc) {
3204 if (!crtc->active)
3205 continue;
3206
3207 pipe = crtc->pipe;
3208
3209 if (reallocated[pipe])
3210 continue;
3211
3212 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3213 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3214 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3215 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3216 reallocated[pipe] = true;
0e8fb7ba 3217 }
0e8fb7ba
DL		 3218 }
3219
3220 /*
3221 * Third pass: flush the pipes that got more space allocated.
3222 *
3223 * We don't need to actively wait for the update here, next vblank
3224 * will just get more DDB space with the correct WM values.
3225 */
3226 for_each_intel_crtc(dev, crtc) {
3227 if (!crtc->active)
3228 continue;
3229
3230 pipe = crtc->pipe;
3231
3232 /*
3233 * At this point, only the pipes more space than before are
3234 * left to re-allocate.
3235 */
3236 if (reallocated[pipe])
3237 continue;
3238
d21b795c 3239 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3240 }
3241}
3242
2d41c0b5
PB		 3243static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3244 struct skl_pipe_wm_parameters *params,
3245 struct intel_wm_config *config,
3246 struct skl_ddb_allocation *ddb, /* out */
3247 struct skl_pipe_wm *pipe_wm /* out */)
3248{
3249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3250
3251 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3252 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3253 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3254
3255 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3256 return false;
3257
3258 intel_crtc->wm.skl_active = *pipe_wm;
3259 return true;
3260}
3261
3262static void skl_update_other_pipe_wm(struct drm_device *dev,
3263 struct drm_crtc *crtc,
3264 struct intel_wm_config *config,
3265 struct skl_wm_values *r)
3266{
3267 struct intel_crtc *intel_crtc;
3268 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3269
3270 /*
3271 * If the WM update hasn't changed the allocation for this_crtc (the
3272 * crtc we are currently computing the new WM values for), other
3273 * enabled crtcs will keep the same allocation and we don't need to
3274 * recompute anything for them.
3275 */
3276 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3277 return;
3278
3279 /*
3280 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3281 * other active pipes need new DDB allocation and WM values.
3282 */
3283 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3284 base.head) {
3285 struct skl_pipe_wm_parameters params = {};
3286 struct skl_pipe_wm pipe_wm = {};
3287 bool wm_changed;
3288
3289 if (this_crtc->pipe == intel_crtc->pipe)
3290 continue;
3291
3292 if (!intel_crtc->active)
3293 continue;
3294
3295 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3296 &params, config,
3297 &r->ddb, &pipe_wm);
3298
3299 /*
3300 * If we end up re-computing the other pipe WM values, it's
3301 * because it was really needed, so we expect the WM values to
3302 * be different.
3303 */
3304 WARN_ON(!wm_changed);
3305
3306 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3307 r->dirty[intel_crtc->pipe] = true;
3308 }
3309}
3310
3311static void skl_update_wm(struct drm_crtc *crtc)
3312{
3313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3314 struct drm_device *dev = crtc->dev;
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 struct skl_pipe_wm_parameters params = {};
3317 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3318 struct skl_pipe_wm pipe_wm = {};
3319 struct intel_wm_config config = {};
3320
3321 memset(results, 0, sizeof(*results));
3322
3323 skl_compute_wm_global_parameters(dev, &config);
3324
3325 if (!skl_update_pipe_wm(crtc, &params, &config,
3326 &results->ddb, &pipe_wm))
3327 return;
3328
3329 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3330 results->dirty[intel_crtc->pipe] = true;
3331
3332 skl_update_other_pipe_wm(dev, crtc, &config, results);
3333 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3334 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3335
3336 /* store the new configuration */
3337 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3338}
3339
3340static void
3341skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3342 uint32_t sprite_width, uint32_t sprite_height,
3343 int pixel_size, bool enabled, bool scaled)
3344{
3345 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3346 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3347
3348 intel_plane->wm.enabled = enabled;
3349 intel_plane->wm.scaled = scaled;
3350 intel_plane->wm.horiz_pixels = sprite_width;
3351 intel_plane->wm.vert_pixels = sprite_height;
3352 intel_plane->wm.bytes_per_pixel = pixel_size;
0fda6568
TU		 3353 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3354 /*
3355 * Framebuffer can be NULL on plane disable, but it does not
3356 * matter for watermarks if we assume no tiling in that case.
3357 */
3358 if (fb)
3359 intel_plane->wm.tiling = fb->modifier[0];
2d41c0b5
PB		 3360
3361 skl_update_wm(crtc);
3362}
3363
820c1980 3364static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3365{
7c4a395f 3366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3367 struct drm_device *dev = crtc->dev;
801bcfff 3368 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3369 struct ilk_wm_maximums max;
3370 struct ilk_pipe_wm_parameters params = {};
3371 struct ilk_wm_values results = {};
77c122bc 3372 enum intel_ddb_partitioning partitioning;
7c4a395f 3373 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3374 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3375 struct intel_wm_config config = {};
7c4a395f 3376
2a44b76b 3377 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3378
3379 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3380
3381 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3382 return;
861f3389 3383
7c4a395f 3384 intel_crtc->wm.active = pipe_wm;
861f3389 3385
2a44b76b
VS		 3386 ilk_compute_wm_config(dev, &config);
3387
34982fe1 3388 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3389 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3390
3391 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3392 if (INTEL_INFO(dev)->gen >= 7 &&
3393 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3394 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3395 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3396
820c1980 3397 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3398 } else {
198a1e9b 3399 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3400 }
3401
198a1e9b 3402 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3403 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3404
820c1980 3405 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3406
820c1980 3407 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3408}
3409
ed57cb8a
DL		 3410static void
3411ilk_update_sprite_wm(struct drm_plane *plane,
3412 struct drm_crtc *crtc,
3413 uint32_t sprite_width, uint32_t sprite_height,
3414 int pixel_size, bool enabled, bool scaled)
526682e9 3415{
8553c18e 3416 struct drm_device *dev = plane->dev;
adf3d35e 3417 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3418
adf3d35e
VS		 3419 intel_plane->wm.enabled = enabled;
3420 intel_plane->wm.scaled = scaled;
3421 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3422 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3423 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3424
8553c18e
VS		 3425 /*
3426 * IVB workaround: must disable low power watermarks for at least
3427 * one frame before enabling scaling. LP watermarks can be re-enabled
3428 * when scaling is disabled.
3429 *
3430 * WaCxSRDisabledForSpriteScaling:ivb
3431 */
3432 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3433 intel_wait_for_vblank(dev, intel_plane->pipe);
3434
820c1980 3435 ilk_update_wm(crtc);
526682e9
PZ		 3436}
3437
3078999f
PB		 3438static void skl_pipe_wm_active_state(uint32_t val,
3439 struct skl_pipe_wm *active,
3440 bool is_transwm,
3441 bool is_cursor,
3442 int i,
3443 int level)
3444{
3445 bool is_enabled = (val & PLANE_WM_EN) != 0;
3446
3447 if (!is_transwm) {
3448 if (!is_cursor) {
3449 active->wm[level].plane_en[i] = is_enabled;
3450 active->wm[level].plane_res_b[i] =
3451 val & PLANE_WM_BLOCKS_MASK;
3452 active->wm[level].plane_res_l[i] =
3453 (val >> PLANE_WM_LINES_SHIFT) &
3454 PLANE_WM_LINES_MASK;
3455 } else {
3456 active->wm[level].cursor_en = is_enabled;
3457 active->wm[level].cursor_res_b =
3458 val & PLANE_WM_BLOCKS_MASK;
3459 active->wm[level].cursor_res_l =
3460 (val >> PLANE_WM_LINES_SHIFT) &
3461 PLANE_WM_LINES_MASK;
3462 }
3463 } else {
3464 if (!is_cursor) {
3465 active->trans_wm.plane_en[i] = is_enabled;
3466 active->trans_wm.plane_res_b[i] =
3467 val & PLANE_WM_BLOCKS_MASK;
3468 active->trans_wm.plane_res_l[i] =
3469 (val >> PLANE_WM_LINES_SHIFT) &
3470 PLANE_WM_LINES_MASK;
3471 } else {
3472 active->trans_wm.cursor_en = is_enabled;
3473 active->trans_wm.cursor_res_b =
3474 val & PLANE_WM_BLOCKS_MASK;
3475 active->trans_wm.cursor_res_l =
3476 (val >> PLANE_WM_LINES_SHIFT) &
3477 PLANE_WM_LINES_MASK;
3478 }
3479 }
3480}
3481
3482static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3483{
3484 struct drm_device *dev = crtc->dev;
3485 struct drm_i915_private *dev_priv = dev->dev_private;
3486 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3489 enum pipe pipe = intel_crtc->pipe;
3490 int level, i, max_level;
3491 uint32_t temp;
3492
3493 max_level = ilk_wm_max_level(dev);
3494
3495 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3496
3497 for (level = 0; level <= max_level; level++) {
3498 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3499 hw->plane[pipe][i][level] =
3500 I915_READ(PLANE_WM(pipe, i, level));
3501 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3502 }
3503
3504 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3505 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3506 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3507
3ef00284 3508 if (!intel_crtc->active)
3078999f
PB		 3509 return;
3510
3511 hw->dirty[pipe] = true;
3512
3513 active->linetime = hw->wm_linetime[pipe];
3514
3515 for (level = 0; level <= max_level; level++) {
3516 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3517 temp = hw->plane[pipe][i][level];
3518 skl_pipe_wm_active_state(temp, active, false,
3519 false, i, level);
3520 }
3521 temp = hw->cursor[pipe][level];
3522 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3523 }
3524
3525 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3526 temp = hw->plane_trans[pipe][i];
3527 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3528 }
3529
3530 temp = hw->cursor_trans[pipe];
3531 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3532}
3533
3534void skl_wm_get_hw_state(struct drm_device *dev)
3535{
a269c583
DL		 3536 struct drm_i915_private *dev_priv = dev->dev_private;
3537 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3538 struct drm_crtc *crtc;
3539
a269c583 3540 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3541 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3542 skl_pipe_wm_get_hw_state(crtc);
3543}
3544
243e6a44
VS		 3545static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3546{
3547 struct drm_device *dev = crtc->dev;
3548 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3549 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3551 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3552 enum pipe pipe = intel_crtc->pipe;
3553 static const unsigned int wm0_pipe_reg[] = {
3554 [PIPE_A] = WM0_PIPEA_ILK,
3555 [PIPE_B] = WM0_PIPEB_ILK,
3556 [PIPE_C] = WM0_PIPEC_IVB,
3557 };
3558
3559 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3560 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3561 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3562
3ef00284 3563 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3564
3565 if (active->pipe_enabled) {
243e6a44
VS		 3566 u32 tmp = hw->wm_pipe[pipe];
3567
3568 /*
3569 * For active pipes LP0 watermark is marked as
3570 * enabled, and LP1+ watermaks as disabled since
3571 * we can't really reverse compute them in case
3572 * multiple pipes are active.
3573 */
3574 active->wm[0].enable = true;
3575 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3576 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3577 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3578 active->linetime = hw->wm_linetime[pipe];
3579 } else {
3580 int level, max_level = ilk_wm_max_level(dev);
3581
3582 /*
3583 * For inactive pipes, all watermark levels
3584 * should be marked as enabled but zeroed,
3585 * which is what we'd compute them to.
3586 */
3587 for (level = 0; level <= max_level; level++)
3588 active->wm[level].enable = true;
3589 }
3590}
3591
3592void ilk_wm_get_hw_state(struct drm_device *dev)
3593{
3594 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3595 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3596 struct drm_crtc *crtc;
3597
70e1e0ec 3598 for_each_crtc(dev, crtc)
243e6a44
VS		 3599 ilk_pipe_wm_get_hw_state(crtc);
3600
3601 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3602 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3603 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3604
3605 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3606 if (INTEL_INFO(dev)->gen >= 7) {
3607 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3608 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3609 }
243e6a44 3610
a42a5719 3611 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3612 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3613 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3614 else if (IS_IVYBRIDGE(dev))
3615 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3616 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3617
3618 hw->enable_fbc_wm =
3619 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3620}
3621
b445e3b0
ED		 3622/**
3623 * intel_update_watermarks - update FIFO watermark values based on current modes
3624 *
3625 * Calculate watermark values for the various WM regs based on current mode
3626 * and plane configuration.
3627 *
3628 * There are several cases to deal with here:
3629 * - normal (i.e. non-self-refresh)
3630 * - self-refresh (SR) mode
3631 * - lines are large relative to FIFO size (buffer can hold up to 2)
3632 * - lines are small relative to FIFO size (buffer can hold more than 2
3633 * lines), so need to account for TLB latency
3634 *
3635 * The normal calculation is:
3636 * watermark = dotclock * bytes per pixel * latency
3637 * where latency is platform & configuration dependent (we assume pessimal
3638 * values here).
3639 *
3640 * The SR calculation is:
3641 * watermark = (trunc(latency/line time)+1) * surface width *
3642 * bytes per pixel
3643 * where
3644 * line time = htotal / dotclock
3645 * surface width = hdisplay for normal plane and 64 for cursor
3646 * and latency is assumed to be high, as above.
3647 *
3648 * The final value programmed to the register should always be rounded up,
3649 * and include an extra 2 entries to account for clock crossings.
3650 *
3651 * We don't use the sprite, so we can ignore that. And on Crestline we have
3652 * to set the non-SR watermarks to 8.
3653 */
46ba614c 3654void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3655{
46ba614c 3656 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3657
3658 if (dev_priv->display.update_wm)
46ba614c 3659 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3660}
3661
adf3d35e
VS		 3662void intel_update_sprite_watermarks(struct drm_plane *plane,
3663 struct drm_crtc *crtc,
ed57cb8a
DL		 3664 uint32_t sprite_width,
3665 uint32_t sprite_height,
3666 int pixel_size,
39db4a4d 3667 bool enabled, bool scaled)
b445e3b0 3668{
adf3d35e 3669 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3670
3671 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3672 dev_priv->display.update_sprite_wm(plane, crtc,
3673 sprite_width, sprite_height,
39db4a4d 3674 pixel_size, enabled, scaled);
b445e3b0
ED		 3675}
3676
9270388e
DV		 3677/**
3678 * Lock protecting IPS related data structures
9270388e
DV		 3679 */
3680DEFINE_SPINLOCK(mchdev_lock);
3681
3682/* Global for IPS driver to get at the current i915 device. Protected by
3683 * mchdev_lock. */
3684static struct drm_i915_private *i915_mch_dev;
3685
2b4e57bd
ED		 3686bool ironlake_set_drps(struct drm_device *dev, u8 val)
3687{
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 u16 rgvswctl;
3690
9270388e
DV		 3691 assert_spin_locked(&mchdev_lock);
3692
2b4e57bd
ED		 3693 rgvswctl = I915_READ16(MEMSWCTL);
3694 if (rgvswctl & MEMCTL_CMD_STS) {
3695 DRM_DEBUG("gpu busy, RCS change rejected\n");
3696 return false; /* still busy with another command */
3697 }
3698
3699 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3700 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3701 I915_WRITE16(MEMSWCTL, rgvswctl);
3702 POSTING_READ16(MEMSWCTL);
3703
3704 rgvswctl |= MEMCTL_CMD_STS;
3705 I915_WRITE16(MEMSWCTL, rgvswctl);
3706
3707 return true;
3708}
3709
8090c6b9 3710static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3711{
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 u32 rgvmodectl = I915_READ(MEMMODECTL);
3714 u8 fmax, fmin, fstart, vstart;
3715
9270388e
DV		 3716 spin_lock_irq(&mchdev_lock);
3717
2b4e57bd
ED		 3718 /* Enable temp reporting */
3719 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3720 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3721
3722 /* 100ms RC evaluation intervals */
3723 I915_WRITE(RCUPEI, 100000);
3724 I915_WRITE(RCDNEI, 100000);
3725
3726 /* Set max/min thresholds to 90ms and 80ms respectively */
3727 I915_WRITE(RCBMAXAVG, 90000);
3728 I915_WRITE(RCBMINAVG, 80000);
3729
3730 I915_WRITE(MEMIHYST, 1);
3731
3732 /* Set up min, max, and cur for interrupt handling */
3733 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3734 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3735 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3736 MEMMODE_FSTART_SHIFT;
3737
3738 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3739 PXVFREQ_PX_SHIFT;
3740
20e4d407
DV		 3741 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3742 dev_priv->ips.fstart = fstart;
2b4e57bd 3743
20e4d407
DV		 3744 dev_priv->ips.max_delay = fstart;
3745 dev_priv->ips.min_delay = fmin;
3746 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3747
3748 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3749 fmax, fmin, fstart);
3750
3751 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3752
3753 /*
3754 * Interrupts will be enabled in ironlake_irq_postinstall
3755 */
3756
3757 I915_WRITE(VIDSTART, vstart);
3758 POSTING_READ(VIDSTART);
3759
3760 rgvmodectl |= MEMMODE_SWMODE_EN;
3761 I915_WRITE(MEMMODECTL, rgvmodectl);
3762
9270388e 3763 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3764 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3765 mdelay(1);
2b4e57bd
ED		 3766
3767 ironlake_set_drps(dev, fstart);
3768
20e4d407 3769 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3770 I915_READ(0x112e0);
20e4d407
DV		 3771 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3772 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3773 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3774
3775 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3776}
3777
8090c6b9 3778static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3779{
3780 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3781 u16 rgvswctl;
3782
3783 spin_lock_irq(&mchdev_lock);
3784
3785 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3786
3787 /* Ack interrupts, disable EFC interrupt */
3788 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3789 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3790 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3791 I915_WRITE(DEIIR, DE_PCU_EVENT);
3792 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3793
3794 /* Go back to the starting frequency */
20e4d407 3795 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3796 mdelay(1);
2b4e57bd
ED		 3797 rgvswctl |= MEMCTL_CMD_STS;
3798 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3799 mdelay(1);
2b4e57bd 3800
9270388e 3801 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3802}
3803
acbe9475
DV		 3804/* There's a funny hw issue where the hw returns all 0 when reading from
3805 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3806 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3807 * all limits and the gpu stuck at whatever frequency it is at atm).
3808 */
74ef1173 3809static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3810{
7b9e0ae6 3811 u32 limits;
2b4e57bd 3812
20b46e59
DV		 3813 /* Only set the down limit when we've reached the lowest level to avoid
3814 * getting more interrupts, otherwise leave this clear. This prevents a
3815 * race in the hw when coming out of rc6: There's a tiny window where
3816 * the hw runs at the minimal clock before selecting the desired
3817 * frequency, if the down threshold expires in that window we will not
3818 * receive a down interrupt. */
74ef1173
AG		 3819 if (IS_GEN9(dev_priv->dev)) {
3820 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3821 if (val <= dev_priv->rps.min_freq_softlimit)
3822 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3823 } else {
3824 limits = dev_priv->rps.max_freq_softlimit << 24;
3825 if (val <= dev_priv->rps.min_freq_softlimit)
3826 limits |= dev_priv->rps.min_freq_softlimit << 16;
3827 }
20b46e59
DV		 3828
3829 return limits;
3830}
3831
dd75fdc8
CW		 3832static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3833{
3834 int new_power;
8a586437
AG		 3835 u32 threshold_up = 0, threshold_down = 0; /* in % */
3836 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 3837
3838 new_power = dev_priv->rps.power;
3839 switch (dev_priv->rps.power) {
3840 case LOW_POWER:
b39fb297 3841 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3842 new_power = BETWEEN;
3843 break;
3844
3845 case BETWEEN:
b39fb297 3846 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3847 new_power = LOW_POWER;
b39fb297 3848 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3849 new_power = HIGH_POWER;
3850 break;
3851
3852 case HIGH_POWER:
b39fb297 3853 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3854 new_power = BETWEEN;
3855 break;
3856 }
3857 /* Max/min bins are special */
aed242ff 3858 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 3859 new_power = LOW_POWER;
aed242ff 3860 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3861 new_power = HIGH_POWER;
3862 if (new_power == dev_priv->rps.power)
3863 return;
3864
3865 /* Note the units here are not exactly 1us, but 1280ns. */
3866 switch (new_power) {
3867 case LOW_POWER:
3868 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 3869 ei_up = 16000;
3870 threshold_up = 95;
dd75fdc8
CW		 3871
3872 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 3873 ei_down = 32000;
3874 threshold_down = 85;
dd75fdc8
CW		 3875 break;
3876
3877 case BETWEEN:
3878 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 3879 ei_up = 13000;
3880 threshold_up = 90;
dd75fdc8
CW		 3881
3882 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 3883 ei_down = 32000;
3884 threshold_down = 75;
dd75fdc8
CW		 3885 break;
3886
3887 case HIGH_POWER:
3888 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 3889 ei_up = 10000;
3890 threshold_up = 85;
dd75fdc8
CW		 3891
3892 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 3893 ei_down = 32000;
3894 threshold_down = 60;
dd75fdc8
CW		 3895 break;
3896 }
3897
8a586437
AG		 3898 I915_WRITE(GEN6_RP_UP_EI,
3899 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3900 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3901 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3902
3903 I915_WRITE(GEN6_RP_DOWN_EI,
3904 GT_INTERVAL_FROM_US(dev_priv, ei_down));
3905 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
3906 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
3907
3908 I915_WRITE(GEN6_RP_CONTROL,
3909 GEN6_RP_MEDIA_TURBO |
3910 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3911 GEN6_RP_MEDIA_IS_GFX |
3912 GEN6_RP_ENABLE |
3913 GEN6_RP_UP_BUSY_AVG |
3914 GEN6_RP_DOWN_IDLE_AVG);
3915
dd75fdc8
CW		 3916 dev_priv->rps.power = new_power;
3917 dev_priv->rps.last_adj = 0;
3918}
3919
2876ce73
CW		 3920static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3921{
3922 u32 mask = 0;
3923
3924 if (val > dev_priv->rps.min_freq_softlimit)
3925 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3926 if (val < dev_priv->rps.max_freq_softlimit)
3927 mask |= GEN6_PM_RP_UP_THRESHOLD;
3928
7b3c29f6
CW		 3929 mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED);
3930 mask &= dev_priv->pm_rps_events;
3931
59d02a1f 3932 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 3933}
3934
b8a5ff8d
JM		 3935/* gen6_set_rps is called to update the frequency request, but should also be
3936 * called when the range (min_delay and max_delay) is modified so that we can
3937 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 3938static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 3939{
3940 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3941
4fc688ce 3942 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 3943 WARN_ON(val > dev_priv->rps.max_freq);
3944 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 3945
eb64cad1
CW		 3946 /* min/max delay may still have been modified so be sure to
3947 * write the limits value.
3948 */
3949 if (val != dev_priv->rps.cur_freq) {
3950 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 3951
5704195c
AG		 3952 if (IS_GEN9(dev))
3953 I915_WRITE(GEN6_RPNSWREQ,
3954 GEN9_FREQUENCY(val));
3955 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 3956 I915_WRITE(GEN6_RPNSWREQ,
3957 HSW_FREQUENCY(val));
3958 else
3959 I915_WRITE(GEN6_RPNSWREQ,
3960 GEN6_FREQUENCY(val) |
3961 GEN6_OFFSET(0) |
3962 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 3963 }
7b9e0ae6 3964
7b9e0ae6
CW		 3965 /* Make sure we continue to get interrupts
3966 * until we hit the minimum or maximum frequencies.
3967 */
74ef1173 3968 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 3969 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 3970
d5570a72
BW		 3971 POSTING_READ(GEN6_RPNSWREQ);
3972
b39fb297 3973 dev_priv->rps.cur_freq = val;
be2cde9a 3974 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3975}
3976
ffe02b40
VS		 3977static void valleyview_set_rps(struct drm_device *dev, u8 val)
3978{
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980
3981 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 3982 WARN_ON(val > dev_priv->rps.max_freq);
3983 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 3984
3985 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
3986 "Odd GPU freq value\n"))
3987 val &= ~1;
3988
3989 if (val != dev_priv->rps.cur_freq)
3990 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3991
3992 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3993
3994 dev_priv->rps.cur_freq = val;
3995 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
3996}
3997
76c3552f
D		 3998/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3999 *
4000 * * If Gfx is Idle, then
4001 * 1. Mask Turbo interrupts
4002 * 2. Bring up Gfx clock
4003 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4004 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4005 * 5. Unmask Turbo interrupts
4006*/
4007static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4008{
5549d25f 4009 struct drm_device *dev = dev_priv->dev;
aed242ff 4010 u32 val = dev_priv->rps.idle_freq;
5549d25f 4011
21a11fff
VS		 4012 /* CHV and latest VLV don't need to force the gfx clock */
4013 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
aed242ff 4014 valleyview_set_rps(dev_priv->dev, val);
5549d25f
D		 4015 return;
4016 }
4017
76c3552f
D		 4018 /*
4019 * When we are idle. Drop to min voltage state.
4020 */
4021
aed242ff 4022 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4023 return;
4024
4025 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID		 4026 I915_WRITE(GEN6_PMINTRMSK,
4027 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 4028
650ad970 4029 vlv_force_gfx_clock(dev_priv, true);
76c3552f 4030
aed242ff 4031 dev_priv->rps.cur_freq = val;
76c3552f 4032
aed242ff 4033 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
76c3552f
D		 4034
4035 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 4036 & GENFREQSTATUS) == 0, 100))
76c3552f
D		 4037 DRM_ERROR("timed out waiting for Punit\n");
4038
650ad970 4039 vlv_force_gfx_clock(dev_priv, false);
76c3552f 4040
aed242ff 4041 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
76c3552f
D		 4042}
4043
b29c19b6
CW		 4044void gen6_rps_idle(struct drm_i915_private *dev_priv)
4045{
691bb717
DL		 4046 struct drm_device *dev = dev_priv->dev;
4047
b29c19b6 4048 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4049 if (dev_priv->rps.enabled) {
21a11fff 4050 if (IS_VALLEYVIEW(dev))
76c3552f 4051 vlv_set_rps_idle(dev_priv);
7526ed79 4052 else
aed242ff 4053 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c
CW		 4054 dev_priv->rps.last_adj = 0;
4055 }
b29c19b6
CW		 4056 mutex_unlock(&dev_priv->rps.hw_lock);
4057}
4058
4059void gen6_rps_boost(struct drm_i915_private *dev_priv)
4060{
4061 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4062 if (dev_priv->rps.enabled) {
ffe02b40 4063 intel_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
c0951f0c
CW		 4064 dev_priv->rps.last_adj = 0;
4065 }
b29c19b6
CW		 4066 mutex_unlock(&dev_priv->rps.hw_lock);
4067}
4068
ffe02b40 4069void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4070{
ffe02b40
VS		 4071 if (IS_VALLEYVIEW(dev))
4072 valleyview_set_rps(dev, val);
4073 else
4074 gen6_set_rps(dev, val);
0a073b84
JB		 4075}
4076
20e49366
ZW		 4077static void gen9_disable_rps(struct drm_device *dev)
4078{
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4080
4081 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4082 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4083}
4084
44fc7d5c 4085static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4086{
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088
4089 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4090 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4091}
4092
38807746
D		 4093static void cherryview_disable_rps(struct drm_device *dev)
4094{
4095 struct drm_i915_private *dev_priv = dev->dev_private;
4096
4097 I915_WRITE(GEN6_RC_CONTROL, 0);
4098}
4099
44fc7d5c
DV		 4100static void valleyview_disable_rps(struct drm_device *dev)
4101{
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103
98a2e5f9
D		 4104 /* we're doing forcewake before Disabling RC6,
4105 * This what the BIOS expects when going into suspend */
59bad947 4106 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4107
44fc7d5c 4108 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4109
59bad947 4110 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4111}
4112
dc39fff7
BW		 4113static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4114{
91ca689a
ID		 4115 if (IS_VALLEYVIEW(dev)) {
4116 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4117 mode = GEN6_RC_CTL_RC6_ENABLE;
4118 else
4119 mode = 0;
4120 }
58abf1da
RV		 4121 if (HAS_RC6p(dev))
4122 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4123 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4124 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4125 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4126
4127 else
4128 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4129 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4130}
4131
e6069ca8 4132static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4133{
eb4926e4
DL		 4134 /* No RC6 before Ironlake */
4135 if (INTEL_INFO(dev)->gen < 5)
4136 return 0;
4137
e6069ca8
ID		 4138 /* RC6 is only on Ironlake mobile not on desktop */
4139 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4140 return 0;
4141
456470eb 4142 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4143 if (enable_rc6 >= 0) {
4144 int mask;
4145
58abf1da 4146 if (HAS_RC6p(dev))
e6069ca8
ID		 4147 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4148 INTEL_RC6pp_ENABLE;
4149 else
4150 mask = INTEL_RC6_ENABLE;
4151
4152 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4153 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4154 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4155
4156 return enable_rc6 & mask;
4157 }
2b4e57bd 4158
6567d748
CW		 4159 /* Disable RC6 on Ironlake */
4160 if (INTEL_INFO(dev)->gen == 5)
4161 return 0;
2b4e57bd 4162
8bade1ad 4163 if (IS_IVYBRIDGE(dev))
cca84a1f 4164 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4165
4166 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4167}
4168
e6069ca8
ID		 4169int intel_enable_rc6(const struct drm_device *dev)
4170{
4171 return i915.enable_rc6;
4172}
4173
93ee2920 4174static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4175{
93ee2920
TR		 4176 struct drm_i915_private *dev_priv = dev->dev_private;
4177 uint32_t rp_state_cap;
4178 u32 ddcc_status = 0;
4179 int ret;
4180
4181 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW		 4182 /* All of these values are in units of 50MHz */
4183 dev_priv->rps.cur_freq = 0;
93ee2920 4184 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 4185 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 4186 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 4187 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
cee991cb
AG		 4188 if (IS_SKYLAKE(dev)) {
4189 /* Store the frequency values in 16.66 MHZ units, which is
4190 the natural hardware unit for SKL */
4191 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4192 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4193 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4194 }
3280e8b0
BW		 4195 /* hw_max = RP0 until we check for overclocking */
4196 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4197
93ee2920
TR		 4198 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4199 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4200 ret = sandybridge_pcode_read(dev_priv,
4201 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4202 &ddcc_status);
4203 if (0 == ret)
4204 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4205 clamp_t(u8,
4206 ((ddcc_status >> 8) & 0xff),
4207 dev_priv->rps.min_freq,
4208 dev_priv->rps.max_freq);
93ee2920
TR		 4209 }
4210
aed242ff
CW		 4211 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4212
3280e8b0
BW		 4213 /* Preserve min/max settings in case of re-init */
4214 if (dev_priv->rps.max_freq_softlimit == 0)
4215 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4216
93ee2920
TR		 4217 if (dev_priv->rps.min_freq_softlimit == 0) {
4218 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4219 dev_priv->rps.min_freq_softlimit =
f4ab408c
TR		 4220 /* max(RPe, 450 MHz) */
4221 max(dev_priv->rps.efficient_freq, (u8) 9);
93ee2920
TR		 4222 else
4223 dev_priv->rps.min_freq_softlimit =
4224 dev_priv->rps.min_freq;
4225 }
3280e8b0
BW		 4226}
4227
b6fef0ef 4228/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4229static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4230{
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232
4233 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4234
ba1c554c
DL		 4235 gen6_init_rps_frequencies(dev);
4236
0beb059a
AG		 4237 /* Program defaults and thresholds for RPS*/
4238 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4239 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4240
4241 /* 1 second timeout*/
4242 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4243 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4244
b6fef0ef 4245 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4246
0beb059a
AG		 4247 /* Leaning on the below call to gen6_set_rps to program/setup the
4248 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4249 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4250 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4251 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4252
4253 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4254}
4255
4256static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4257{
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4259 struct intel_engine_cs *ring;
4260 uint32_t rc6_mask = 0;
4261 int unused;
4262
4263 /* 1a: Software RC state - RC0 */
4264 I915_WRITE(GEN6_RC_STATE, 0);
4265
4266 /* 1b: Get forcewake during program sequence. Although the driver
4267 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4268 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4269
4270 /* 2a: Disable RC states. */
4271 I915_WRITE(GEN6_RC_CONTROL, 0);
4272
4273 /* 2b: Program RC6 thresholds.*/
4274 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4275 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4276 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4277 for_each_ring(ring, dev_priv, unused)
4278 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4279 I915_WRITE(GEN6_RC_SLEEP, 0);
4280 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4281
38c23527
ZW		 4282 /* 2c: Program Coarse Power Gating Policies. */
4283 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4284 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4285
20e49366
ZW		 4286 /* 3a: Enable RC6 */
4287 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4288 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4289 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4290 "on" : "off");
4291 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4292 GEN6_RC_CTL_EI_MODE(1) |
4293 rc6_mask);
4294
38c23527
ZW		 4295 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4296 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
4297
59bad947 4298 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4299
4300}
4301
6edee7f3
BW		 4302static void gen8_enable_rps(struct drm_device *dev)
4303{
4304 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4305 struct intel_engine_cs *ring;
93ee2920 4306 uint32_t rc6_mask = 0;
6edee7f3
BW		 4307 int unused;
4308
4309 /* 1a: Software RC state - RC0 */
4310 I915_WRITE(GEN6_RC_STATE, 0);
4311
4312 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4313 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4314 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4315
4316 /* 2a: Disable RC states. */
4317 I915_WRITE(GEN6_RC_CONTROL, 0);
4318
93ee2920
TR		 4319 /* Initialize rps frequencies */
4320 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4321
4322 /* 2b: Program RC6 thresholds.*/
4323 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4324 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4325 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4326 for_each_ring(ring, dev_priv, unused)
4327 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4328 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4329 if (IS_BROADWELL(dev))
4330 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4331 else
4332 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4333
4334 /* 3: Enable RC6 */
4335 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4336 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4337 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4338 if (IS_BROADWELL(dev))
4339 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4340 GEN7_RC_CTL_TO_MODE |
4341 rc6_mask);
4342 else
4343 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4344 GEN6_RC_CTL_EI_MODE(1) |
4345 rc6_mask);
6edee7f3
BW		 4346
4347 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4348 I915_WRITE(GEN6_RPNSWREQ,
4349 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4350 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4351 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4352 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4353 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4354
4355 /* Docs recommend 900MHz, and 300 MHz respectively */
4356 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4357 dev_priv->rps.max_freq_softlimit << 24 |
4358 dev_priv->rps.min_freq_softlimit << 16);
4359
4360 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4361 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4362 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4363 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4364
4365 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4366
4367 /* 5: Enable RPS */
7526ed79
DV		 4368 I915_WRITE(GEN6_RP_CONTROL,
4369 GEN6_RP_MEDIA_TURBO |
4370 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4371 GEN6_RP_MEDIA_IS_GFX |
4372 GEN6_RP_ENABLE |
4373 GEN6_RP_UP_BUSY_AVG |
4374 GEN6_RP_DOWN_IDLE_AVG);
4375
4376 /* 6: Ring frequency + overclocking (our driver does this later */
4377
c7f3153a 4378 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4379 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4380
59bad947 4381 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4382}
4383
79f5b2c7 4384static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4385{
79f5b2c7 4386 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4387 struct intel_engine_cs *ring;
d060c169 4388 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4389 u32 gtfifodbg;
2b4e57bd 4390 int rc6_mode;
42c0526c 4391 int i, ret;
2b4e57bd 4392
4fc688ce 4393 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4394
2b4e57bd
ED		 4395 /* Here begins a magic sequence of register writes to enable
4396 * auto-downclocking.
4397 *
4398 * Perhaps there might be some value in exposing these to
4399 * userspace...
4400 */
4401 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4402
4403 /* Clear the DBG now so we don't confuse earlier errors */
4404 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4405 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4406 I915_WRITE(GTFIFODBG, gtfifodbg);
4407 }
4408
59bad947 4409 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4410
93ee2920
TR		 4411 /* Initialize rps frequencies */
4412 gen6_init_rps_frequencies(dev);
dd0a1aa1 4413
2b4e57bd
ED		 4414 /* disable the counters and set deterministic thresholds */
4415 I915_WRITE(GEN6_RC_CONTROL, 0);
4416
4417 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4418 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4419 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4420 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4421 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4422
b4519513
CW		 4423 for_each_ring(ring, dev_priv, i)
4424 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4425
4426 I915_WRITE(GEN6_RC_SLEEP, 0);
4427 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4428 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4429 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4430 else
4431 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4432 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4433 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4434
5a7dc92a 4435 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4436 rc6_mode = intel_enable_rc6(dev_priv->dev);
4437 if (rc6_mode & INTEL_RC6_ENABLE)
4438 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4439
5a7dc92a
ED		 4440 /* We don't use those on Haswell */
4441 if (!IS_HASWELL(dev)) {
4442 if (rc6_mode & INTEL_RC6p_ENABLE)
4443 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4444
5a7dc92a
ED		 4445 if (rc6_mode & INTEL_RC6pp_ENABLE)
4446 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4447 }
2b4e57bd 4448
dc39fff7 4449 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4450
4451 I915_WRITE(GEN6_RC_CONTROL,
4452 rc6_mask |
4453 GEN6_RC_CTL_EI_MODE(1) |
4454 GEN6_RC_CTL_HW_ENABLE);
4455
dd75fdc8
CW		 4456 /* Power down if completely idle for over 50ms */
4457 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4458 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4459
42c0526c 4460 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4461 if (ret)
42c0526c 4462 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4463
4464 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4465 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4466 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4467 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4468 (pcu_mbox & 0xff) * 50);
b39fb297 4469 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4470 }
4471
dd75fdc8 4472 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4473 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4474
31643d54
BW		 4475 rc6vids = 0;
4476 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4477 if (IS_GEN6(dev) && ret) {
4478 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4479 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4480 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4481 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4482 rc6vids &= 0xffff00;
4483 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4484 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4485 if (ret)
4486 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4487 }
4488
59bad947 4489 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4490}
4491
c2bc2fc5 4492static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4493{
79f5b2c7 4494 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4495 int min_freq = 15;
3ebecd07
CW		 4496 unsigned int gpu_freq;
4497 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4498 int scaling_factor = 180;
eda79642 4499 struct cpufreq_policy *policy;
2b4e57bd 4500
4fc688ce 4501 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4502
eda79642
BW		 4503 policy = cpufreq_cpu_get(0);
4504 if (policy) {
4505 max_ia_freq = policy->cpuinfo.max_freq;
4506 cpufreq_cpu_put(policy);
4507 } else {
4508 /*
4509 * Default to measured freq if none found, PCU will ensure we
4510 * don't go over
4511 */
2b4e57bd 4512 max_ia_freq = tsc_khz;
eda79642 4513 }
2b4e57bd
ED		 4514
4515 /* Convert from kHz to MHz */
4516 max_ia_freq /= 1000;
4517
153b4b95 4518 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4519 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4520 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4521
2b4e57bd
ED		 4522 /*
4523 * For each potential GPU frequency, load a ring frequency we'd like
4524 * to use for memory access. We do this by specifying the IA frequency
4525 * the PCU should use as a reference to determine the ring frequency.
4526 */
6985b352 4527 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4528 gpu_freq--) {
6985b352 4529 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 4530 unsigned int ia_freq = 0, ring_freq = 0;
4531
46c764d4
BW		 4532 if (INTEL_INFO(dev)->gen >= 8) {
4533 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4534 ring_freq = max(min_ring_freq, gpu_freq);
4535 } else if (IS_HASWELL(dev)) {
f6aca45c 4536 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4537 ring_freq = max(min_ring_freq, ring_freq);
4538 /* leave ia_freq as the default, chosen by cpufreq */
4539 } else {
4540 /* On older processors, there is no separate ring
4541 * clock domain, so in order to boost the bandwidth
4542 * of the ring, we need to upclock the CPU (ia_freq).
4543 *
4544 * For GPU frequencies less than 750MHz,
4545 * just use the lowest ring freq.
4546 */
4547 if (gpu_freq < min_freq)
4548 ia_freq = 800;
4549 else
4550 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4551 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4552 }
2b4e57bd 4553
42c0526c
BW		 4554 sandybridge_pcode_write(dev_priv,
4555 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4556 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4557 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4558 gpu_freq);
2b4e57bd 4559 }
2b4e57bd
ED		 4560}
4561
c2bc2fc5
ID		 4562void gen6_update_ring_freq(struct drm_device *dev)
4563{
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565
4566 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4567 return;
4568
4569 mutex_lock(&dev_priv->rps.hw_lock);
4570 __gen6_update_ring_freq(dev);
4571 mutex_unlock(&dev_priv->rps.hw_lock);
4572}
4573
03af2045 4574static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4575{
095acd5f 4576 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4577 u32 val, rp0;
4578
095acd5f
D		 4579 if (dev->pdev->revision >= 0x20) {
4580 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4581
095acd5f
D		 4582 switch (INTEL_INFO(dev)->eu_total) {
4583 case 8:
4584 /* (2 * 4) config */
4585 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4586 break;
4587 case 12:
4588 /* (2 * 6) config */
4589 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4590 break;
4591 case 16:
4592 /* (2 * 8) config */
4593 default:
4594 /* Setting (2 * 8) Min RP0 for any other combination */
4595 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4596 break;
4597 }
4598 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4599 } else {
4600 /* For pre-production hardware */
4601 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4602 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4603 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4604 }
2b6b3a09
D		 4605 return rp0;
4606}
4607
4608static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4609{
4610 u32 val, rpe;
4611
4612 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4613 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4614
4615 return rpe;
4616}
4617
7707df4a
D		 4618static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4619{
095acd5f 4620 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 4621 u32 val, rp1;
4622
095acd5f
D		 4623 if (dev->pdev->revision >= 0x20) {
4624 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4625 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4626 } else {
4627 /* For pre-production hardware */
4628 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4629 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4630 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4631 }
7707df4a
D		 4632 return rp1;
4633}
4634
03af2045 4635static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4636{
095acd5f 4637 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4638 u32 val, rpn;
4639
095acd5f
D		 4640 if (dev->pdev->revision >= 0x20) {
4641 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4642 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4643 FB_GFX_FREQ_FUSE_MASK);
4644 } else { /* For pre-production hardware */
4645 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4646 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4647 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4648 }
4649
2b6b3a09
D		 4650 return rpn;
4651}
4652
f8f2b001
D		 4653static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4654{
4655 u32 val, rp1;
4656
4657 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4658
4659 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4660
4661 return rp1;
4662}
4663
03af2045 4664static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4665{
4666 u32 val, rp0;
4667
64936258 4668 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4669
4670 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4671 /* Clamp to max */
4672 rp0 = min_t(u32, rp0, 0xea);
4673
4674 return rp0;
4675}
4676
4677static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4678{
4679 u32 val, rpe;
4680
64936258 4681 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4682 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4683 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4684 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4685
4686 return rpe;
4687}
4688
03af2045 4689static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4690{
64936258 4691 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4692}
4693
ae48434c
ID		 4694/* Check that the pctx buffer wasn't move under us. */
4695static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4696{
4697 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4698
4699 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4700 dev_priv->vlv_pctx->stolen->start);
4701}
4702
38807746
D		 4703
4704/* Check that the pcbr address is not empty. */
4705static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4706{
4707 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4708
4709 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4710}
4711
4712static void cherryview_setup_pctx(struct drm_device *dev)
4713{
4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715 unsigned long pctx_paddr, paddr;
4716 struct i915_gtt *gtt = &dev_priv->gtt;
4717 u32 pcbr;
4718 int pctx_size = 32*1024;
4719
4720 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4721
4722 pcbr = I915_READ(VLV_PCBR);
4723 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4724 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 4725 paddr = (dev_priv->mm.stolen_base +
4726 (gtt->stolen_size - pctx_size));
4727
4728 pctx_paddr = (paddr & (~4095));
4729 I915_WRITE(VLV_PCBR, pctx_paddr);
4730 }
ce611ef8
VS		 4731
4732 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 4733}
4734
c9cddffc
JB		 4735static void valleyview_setup_pctx(struct drm_device *dev)
4736{
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct drm_i915_gem_object *pctx;
4739 unsigned long pctx_paddr;
4740 u32 pcbr;
4741 int pctx_size = 24*1024;
4742
17b0c1f7
ID		 4743 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4744
c9cddffc
JB		 4745 pcbr = I915_READ(VLV_PCBR);
4746 if (pcbr) {
4747 /* BIOS set it up already, grab the pre-alloc'd space */
4748 int pcbr_offset;
4749
4750 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4751 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4752 pcbr_offset,
190d6cd5 4753 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4754 pctx_size);
4755 goto out;
4756 }
4757
ce611ef8
VS		 4758 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4759
c9cddffc
JB		 4760 /*
4761 * From the Gunit register HAS:
4762 * The Gfx driver is expected to program this register and ensure
4763 * proper allocation within Gfx stolen memory. For example, this
4764 * register should be programmed such than the PCBR range does not
4765 * overlap with other ranges, such as the frame buffer, protected
4766 * memory, or any other relevant ranges.
4767 */
4768 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4769 if (!pctx) {
4770 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4771 return;
4772 }
4773
4774 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4775 I915_WRITE(VLV_PCBR, pctx_paddr);
4776
4777out:
ce611ef8 4778 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 4779 dev_priv->vlv_pctx = pctx;
4780}
4781
ae48434c
ID		 4782static void valleyview_cleanup_pctx(struct drm_device *dev)
4783{
4784 struct drm_i915_private *dev_priv = dev->dev_private;
4785
4786 if (WARN_ON(!dev_priv->vlv_pctx))
4787 return;
4788
4789 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4790 dev_priv->vlv_pctx = NULL;
4791}
4792
4e80519e
ID		 4793static void valleyview_init_gt_powersave(struct drm_device *dev)
4794{
4795 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4796 u32 val;
4e80519e
ID		 4797
4798 valleyview_setup_pctx(dev);
4799
4800 mutex_lock(&dev_priv->rps.hw_lock);
4801
2bb25c17
VS		 4802 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4803 switch ((val >> 6) & 3) {
4804 case 0:
4805 case 1:
4806 dev_priv->mem_freq = 800;
4807 break;
4808 case 2:
4809 dev_priv->mem_freq = 1066;
4810 break;
4811 case 3:
4812 dev_priv->mem_freq = 1333;
4813 break;
4814 }
80b83b62 4815 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4816
4e80519e
ID		 4817 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4818 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4819 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4820 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 4821 dev_priv->rps.max_freq);
4822
4823 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4824 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4825 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 4826 dev_priv->rps.efficient_freq);
4827
f8f2b001
D		 4828 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4829 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4830 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 4831 dev_priv->rps.rp1_freq);
4832
4e80519e
ID		 4833 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4834 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4835 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 4836 dev_priv->rps.min_freq);
4837
aed242ff
CW		 4838 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4839
4e80519e
ID		 4840 /* Preserve min/max settings in case of re-init */
4841 if (dev_priv->rps.max_freq_softlimit == 0)
4842 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4843
4844 if (dev_priv->rps.min_freq_softlimit == 0)
4845 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4846
4847 mutex_unlock(&dev_priv->rps.hw_lock);
4848}
4849
38807746
D		 4850static void cherryview_init_gt_powersave(struct drm_device *dev)
4851{
2b6b3a09 4852 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4853 u32 val;
2b6b3a09 4854
38807746 4855 cherryview_setup_pctx(dev);
2b6b3a09
D		 4856
4857 mutex_lock(&dev_priv->rps.hw_lock);
4858
c6e8f39d
VS		 4859 mutex_lock(&dev_priv->dpio_lock);
4860 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4861 mutex_unlock(&dev_priv->dpio_lock);
4862
2bb25c17
VS		 4863 switch ((val >> 2) & 0x7) {
4864 case 0:
4865 case 1:
4866 dev_priv->rps.cz_freq = 200;
4867 dev_priv->mem_freq = 1600;
4868 break;
4869 case 2:
4870 dev_priv->rps.cz_freq = 267;
4871 dev_priv->mem_freq = 1600;
4872 break;
4873 case 3:
4874 dev_priv->rps.cz_freq = 333;
4875 dev_priv->mem_freq = 2000;
4876 break;
4877 case 4:
4878 dev_priv->rps.cz_freq = 320;
4879 dev_priv->mem_freq = 1600;
4880 break;
4881 case 5:
4882 dev_priv->rps.cz_freq = 400;
4883 dev_priv->mem_freq = 1600;
4884 break;
4885 }
80b83b62 4886 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4887
2b6b3a09
D		 4888 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4889 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4890 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4891 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 4892 dev_priv->rps.max_freq);
4893
4894 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4895 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4896 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 4897 dev_priv->rps.efficient_freq);
4898
7707df4a
D		 4899 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4900 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 4901 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 4902 dev_priv->rps.rp1_freq);
4903
2b6b3a09
D		 4904 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4905 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4906 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 4907 dev_priv->rps.min_freq);
4908
1c14762d
VS		 4909 WARN_ONCE((dev_priv->rps.max_freq |
4910 dev_priv->rps.efficient_freq |
4911 dev_priv->rps.rp1_freq |
4912 dev_priv->rps.min_freq) & 1,
4913 "Odd GPU freq values\n");
4914
aed242ff
CW		 4915 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4916
2b6b3a09
D		 4917 /* Preserve min/max settings in case of re-init */
4918 if (dev_priv->rps.max_freq_softlimit == 0)
4919 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4920
4921 if (dev_priv->rps.min_freq_softlimit == 0)
4922 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4923
4924 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 4925}
4926
4e80519e
ID		 4927static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
4928{
4929 valleyview_cleanup_pctx(dev);
4930}
4931
38807746
D		 4932static void cherryview_enable_rps(struct drm_device *dev)
4933{
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935 struct intel_engine_cs *ring;
2b6b3a09 4936 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 4937 int i;
4938
4939 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4940
4941 gtfifodbg = I915_READ(GTFIFODBG);
4942 if (gtfifodbg) {
4943 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4944 gtfifodbg);
4945 I915_WRITE(GTFIFODBG, gtfifodbg);
4946 }
4947
4948 cherryview_check_pctx(dev_priv);
4949
4950 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4951 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4952 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 4953
160614a2
VS		 4954 /* Disable RC states. */
4955 I915_WRITE(GEN6_RC_CONTROL, 0);
4956
38807746
D		 4957 /* 2a: Program RC6 thresholds.*/
4958 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4959 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4960 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4961
4962 for_each_ring(ring, dev_priv, i)
4963 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4964 I915_WRITE(GEN6_RC_SLEEP, 0);
4965
af5a75a3
VS		 4966 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4967 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
38807746
D		 4968
4969 /* allows RC6 residency counter to work */
4970 I915_WRITE(VLV_COUNTER_CONTROL,
4971 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4972 VLV_MEDIA_RC6_COUNT_EN |
4973 VLV_RENDER_RC6_COUNT_EN));
4974
4975 /* For now we assume BIOS is allocating and populating the PCBR */
4976 pcbr = I915_READ(VLV_PCBR);
4977
38807746
D		 4978 /* 3: Enable RC6 */
4979 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4980 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 4981 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 4982
4983 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4984
2b6b3a09 4985 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 4986 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 4987 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4988 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4989 I915_WRITE(GEN6_RP_UP_EI, 66000);
4990 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4991
4992 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4993
4994 /* 5: Enable RPS */
4995 I915_WRITE(GEN6_RP_CONTROL,
4996 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 4997 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 4998 GEN6_RP_ENABLE |
4999 GEN6_RP_UP_BUSY_AVG |
5000 GEN6_RP_DOWN_IDLE_AVG);
5001
5002 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5003
8d40c3ae
VS		 5004 /* RPS code assumes GPLL is used */
5005 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5006
c8e9627d 5007 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5008 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5009
5010 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5011 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5012 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5013 dev_priv->rps.cur_freq);
5014
5015 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5016 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5017 dev_priv->rps.efficient_freq);
5018
5019 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5020
59bad947 5021 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5022}
5023
0a073b84
JB		 5024static void valleyview_enable_rps(struct drm_device *dev)
5025{
5026 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5027 struct intel_engine_cs *ring;
2a5913a8 5028 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5029 int i;
5030
5031 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5032
ae48434c
ID		 5033 valleyview_check_pctx(dev_priv);
5034
0a073b84 5035 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5036 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5037 gtfifodbg);
0a073b84
JB		 5038 I915_WRITE(GTFIFODBG, gtfifodbg);
5039 }
5040
c8d9a590 5041 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5042 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5043
160614a2
VS		 5044 /* Disable RC states. */
5045 I915_WRITE(GEN6_RC_CONTROL, 0);
5046
cad725fe 5047 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5048 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5049 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5050 I915_WRITE(GEN6_RP_UP_EI, 66000);
5051 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5052
5053 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5054
5055 I915_WRITE(GEN6_RP_CONTROL,
5056 GEN6_RP_MEDIA_TURBO |
5057 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5058 GEN6_RP_MEDIA_IS_GFX |
5059 GEN6_RP_ENABLE |
5060 GEN6_RP_UP_BUSY_AVG |
5061 GEN6_RP_DOWN_IDLE_CONT);
5062
5063 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5064 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5065 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5066
5067 for_each_ring(ring, dev_priv, i)
5068 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5069
2f0aa304 5070 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5071
5072 /* allows RC6 residency counter to work */
49798eb2 5073 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5074 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5075 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5076 VLV_MEDIA_RC6_COUNT_EN |
5077 VLV_RENDER_RC6_COUNT_EN));
31685c25 5078
a2b23fe0 5079 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5080 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5081
5082 intel_print_rc6_info(dev, rc6_mode);
5083
a2b23fe0 5084 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5085
64936258 5086 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5087
8d40c3ae
VS		 5088 /* RPS code assumes GPLL is used */
5089 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5090
c8e9627d 5091 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5092 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5093
b39fb297 5094 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5095 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5096 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5097 dev_priv->rps.cur_freq);
0a073b84 5098
73008b98 5099 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5100 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5101 dev_priv->rps.efficient_freq);
0a073b84 5102
b39fb297 5103 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5104
59bad947 5105 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5106}
5107
dde18883
ED		 5108static unsigned long intel_pxfreq(u32 vidfreq)
5109{
5110 unsigned long freq;
5111 int div = (vidfreq & 0x3f0000) >> 16;
5112 int post = (vidfreq & 0x3000) >> 12;
5113 int pre = (vidfreq & 0x7);
5114
5115 if (!pre)
5116 return 0;
5117
5118 freq = ((div * 133333) / ((1<<post) * pre));
5119
5120 return freq;
5121}
5122
eb48eb00
DV		 5123static const struct cparams {
5124 u16 i;
5125 u16 t;
5126 u16 m;
5127 u16 c;
5128} cparams[] = {
5129 { 1, 1333, 301, 28664 },
5130 { 1, 1066, 294, 24460 },
5131 { 1, 800, 294, 25192 },
5132 { 0, 1333, 276, 27605 },
5133 { 0, 1066, 276, 27605 },
5134 { 0, 800, 231, 23784 },
5135};
5136
f531dcb2 5137static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5138{
5139 u64 total_count, diff, ret;
5140 u32 count1, count2, count3, m = 0, c = 0;
5141 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5142 int i;
5143
02d71956
DV		 5144 assert_spin_locked(&mchdev_lock);
5145
20e4d407 5146 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5147
5148 /* Prevent division-by-zero if we are asking too fast.
5149 * Also, we don't get interesting results if we are polling
5150 * faster than once in 10ms, so just return the saved value
5151 * in such cases.
5152 */
5153 if (diff1 <= 10)
20e4d407 5154 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5155
5156 count1 = I915_READ(DMIEC);
5157 count2 = I915_READ(DDREC);
5158 count3 = I915_READ(CSIEC);
5159
5160 total_count = count1 + count2 + count3;
5161
5162 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5163 if (total_count < dev_priv->ips.last_count1) {
5164 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5165 diff += total_count;
5166 } else {
20e4d407 5167 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5168 }
5169
5170 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5171 if (cparams[i].i == dev_priv->ips.c_m &&
5172 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5173 m = cparams[i].m;
5174 c = cparams[i].c;
5175 break;
5176 }
5177 }
5178
5179 diff = div_u64(diff, diff1);
5180 ret = ((m * diff) + c);
5181 ret = div_u64(ret, 10);
5182
20e4d407
DV		 5183 dev_priv->ips.last_count1 = total_count;
5184 dev_priv->ips.last_time1 = now;
eb48eb00 5185
20e4d407 5186 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5187
5188 return ret;
5189}
5190
f531dcb2
CW		 5191unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5192{
3d13ef2e 5193 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5194 unsigned long val;
5195
3d13ef2e 5196 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5197 return 0;
5198
5199 spin_lock_irq(&mchdev_lock);
5200
5201 val = __i915_chipset_val(dev_priv);
5202
5203 spin_unlock_irq(&mchdev_lock);
5204
5205 return val;
5206}
5207
eb48eb00
DV		 5208unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5209{
5210 unsigned long m, x, b;
5211 u32 tsfs;
5212
5213 tsfs = I915_READ(TSFS);
5214
5215 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5216 x = I915_READ8(TR1);
5217
5218 b = tsfs & TSFS_INTR_MASK;
5219
5220 return ((m * x) / 127) - b;
5221}
5222
d972d6ee
MK		 5223static int _pxvid_to_vd(u8 pxvid)
5224{
5225 if (pxvid == 0)
5226 return 0;
5227
5228 if (pxvid >= 8 && pxvid < 31)
5229 pxvid = 31;
5230
5231 return (pxvid + 2) * 125;
5232}
5233
5234static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5235{
3d13ef2e 5236 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5237 const int vd = _pxvid_to_vd(pxvid);
5238 const int vm = vd - 1125;
5239
3d13ef2e 5240 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5241 return vm > 0 ? vm : 0;
5242
5243 return vd;
eb48eb00
DV		 5244}
5245
02d71956 5246static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5247{
5ed0bdf2 5248 u64 now, diff, diffms;
eb48eb00
DV		 5249 u32 count;
5250
02d71956 5251 assert_spin_locked(&mchdev_lock);
eb48eb00 5252
5ed0bdf2
TG		 5253 now = ktime_get_raw_ns();
5254 diffms = now - dev_priv->ips.last_time2;
5255 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5256
5257 /* Don't divide by 0 */
eb48eb00
DV		 5258 if (!diffms)
5259 return;
5260
5261 count = I915_READ(GFXEC);
5262
20e4d407
DV		 5263 if (count < dev_priv->ips.last_count2) {
5264 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5265 diff += count;
5266 } else {
20e4d407 5267 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5268 }
5269
20e4d407
DV		 5270 dev_priv->ips.last_count2 = count;
5271 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5272
5273 /* More magic constants... */
5274 diff = diff * 1181;
5275 diff = div_u64(diff, diffms * 10);
20e4d407 5276 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5277}
5278
02d71956
DV		 5279void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5280{
3d13ef2e
DL		 5281 struct drm_device *dev = dev_priv->dev;
5282
5283 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5284 return;
5285
9270388e 5286 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5287
5288 __i915_update_gfx_val(dev_priv);
5289
9270388e 5290 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5291}
5292
f531dcb2 5293static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5294{
5295 unsigned long t, corr, state1, corr2, state2;
5296 u32 pxvid, ext_v;
5297
02d71956
DV		 5298 assert_spin_locked(&mchdev_lock);
5299
b39fb297 5300 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5301 pxvid = (pxvid >> 24) & 0x7f;
5302 ext_v = pvid_to_extvid(dev_priv, pxvid);
5303
5304 state1 = ext_v;
5305
5306 t = i915_mch_val(dev_priv);
5307
5308 /* Revel in the empirically derived constants */
5309
5310 /* Correction factor in 1/100000 units */
5311 if (t > 80)
5312 corr = ((t * 2349) + 135940);
5313 else if (t >= 50)
5314 corr = ((t * 964) + 29317);
5315 else /* < 50 */
5316 corr = ((t * 301) + 1004);
5317
5318 corr = corr * ((150142 * state1) / 10000 - 78642);
5319 corr /= 100000;
20e4d407 5320 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5321
5322 state2 = (corr2 * state1) / 10000;
5323 state2 /= 100; /* convert to mW */
5324
02d71956 5325 __i915_update_gfx_val(dev_priv);
eb48eb00 5326
20e4d407 5327 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5328}
5329
f531dcb2
CW		 5330unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5331{
3d13ef2e 5332 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5333 unsigned long val;
5334
3d13ef2e 5335 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5336 return 0;
5337
5338 spin_lock_irq(&mchdev_lock);
5339
5340 val = __i915_gfx_val(dev_priv);
5341
5342 spin_unlock_irq(&mchdev_lock);
5343
5344 return val;
5345}
5346
eb48eb00
DV		 5347/**
5348 * i915_read_mch_val - return value for IPS use
5349 *
5350 * Calculate and return a value for the IPS driver to use when deciding whether
5351 * we have thermal and power headroom to increase CPU or GPU power budget.
5352 */
5353unsigned long i915_read_mch_val(void)
5354{
5355 struct drm_i915_private *dev_priv;
5356 unsigned long chipset_val, graphics_val, ret = 0;
5357
9270388e 5358 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5359 if (!i915_mch_dev)
5360 goto out_unlock;
5361 dev_priv = i915_mch_dev;
5362
f531dcb2
CW		 5363 chipset_val = __i915_chipset_val(dev_priv);
5364 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5365
5366 ret = chipset_val + graphics_val;
5367
5368out_unlock:
9270388e 5369 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5370
5371 return ret;
5372}
5373EXPORT_SYMBOL_GPL(i915_read_mch_val);
5374
5375/**
5376 * i915_gpu_raise - raise GPU frequency limit
5377 *
5378 * Raise the limit; IPS indicates we have thermal headroom.
5379 */
5380bool i915_gpu_raise(void)
5381{
5382 struct drm_i915_private *dev_priv;
5383 bool ret = true;
5384
9270388e 5385 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5386 if (!i915_mch_dev) {
5387 ret = false;
5388 goto out_unlock;
5389 }
5390 dev_priv = i915_mch_dev;
5391
20e4d407
DV		 5392 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5393 dev_priv->ips.max_delay--;
eb48eb00
DV		 5394
5395out_unlock:
9270388e 5396 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5397
5398 return ret;
5399}
5400EXPORT_SYMBOL_GPL(i915_gpu_raise);
5401
5402/**
5403 * i915_gpu_lower - lower GPU frequency limit
5404 *
5405 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5406 * frequency maximum.
5407 */
5408bool i915_gpu_lower(void)
5409{
5410 struct drm_i915_private *dev_priv;
5411 bool ret = true;
5412
9270388e 5413 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5414 if (!i915_mch_dev) {
5415 ret = false;
5416 goto out_unlock;
5417 }
5418 dev_priv = i915_mch_dev;
5419
20e4d407
DV		 5420 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5421 dev_priv->ips.max_delay++;
eb48eb00
DV		 5422
5423out_unlock:
9270388e 5424 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5425
5426 return ret;
5427}
5428EXPORT_SYMBOL_GPL(i915_gpu_lower);
5429
5430/**
5431 * i915_gpu_busy - indicate GPU business to IPS
5432 *
5433 * Tell the IPS driver whether or not the GPU is busy.
5434 */
5435bool i915_gpu_busy(void)
5436{
5437 struct drm_i915_private *dev_priv;
a4872ba6 5438 struct intel_engine_cs *ring;
eb48eb00 5439 bool ret = false;
f047e395 5440 int i;
eb48eb00 5441
9270388e 5442 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5443 if (!i915_mch_dev)
5444 goto out_unlock;
5445 dev_priv = i915_mch_dev;
5446
f047e395
CW		 5447 for_each_ring(ring, dev_priv, i)
5448 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5449
5450out_unlock:
9270388e 5451 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5452
5453 return ret;
5454}
5455EXPORT_SYMBOL_GPL(i915_gpu_busy);
5456
5457/**
5458 * i915_gpu_turbo_disable - disable graphics turbo
5459 *
5460 * Disable graphics turbo by resetting the max frequency and setting the
5461 * current frequency to the default.
5462 */
5463bool i915_gpu_turbo_disable(void)
5464{
5465 struct drm_i915_private *dev_priv;
5466 bool ret = true;
5467
9270388e 5468 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5469 if (!i915_mch_dev) {
5470 ret = false;
5471 goto out_unlock;
5472 }
5473 dev_priv = i915_mch_dev;
5474
20e4d407 5475 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5476
20e4d407 5477 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5478 ret = false;
5479
5480out_unlock:
9270388e 5481 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5482
5483 return ret;
5484}
5485EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5486
5487/**
5488 * Tells the intel_ips driver that the i915 driver is now loaded, if
5489 * IPS got loaded first.
5490 *
5491 * This awkward dance is so that neither module has to depend on the
5492 * other in order for IPS to do the appropriate communication of
5493 * GPU turbo limits to i915.
5494 */
5495static void
5496ips_ping_for_i915_load(void)
5497{
5498 void (*link)(void);
5499
5500 link = symbol_get(ips_link_to_i915_driver);
5501 if (link) {
5502 link();
5503 symbol_put(ips_link_to_i915_driver);
5504 }
5505}
5506
5507void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5508{
02d71956
DV		 5509 /* We only register the i915 ips part with intel-ips once everything is
5510 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5511 spin_lock_irq(&mchdev_lock);
eb48eb00 5512 i915_mch_dev = dev_priv;
9270388e 5513 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5514
5515 ips_ping_for_i915_load();
5516}
5517
5518void intel_gpu_ips_teardown(void)
5519{
9270388e 5520 spin_lock_irq(&mchdev_lock);
eb48eb00 5521 i915_mch_dev = NULL;
9270388e 5522 spin_unlock_irq(&mchdev_lock);
eb48eb00 5523}
76c3552f 5524
8090c6b9 5525static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5526{
5527 struct drm_i915_private *dev_priv = dev->dev_private;
5528 u32 lcfuse;
5529 u8 pxw[16];
5530 int i;
5531
5532 /* Disable to program */
5533 I915_WRITE(ECR, 0);
5534 POSTING_READ(ECR);
5535
5536 /* Program energy weights for various events */
5537 I915_WRITE(SDEW, 0x15040d00);
5538 I915_WRITE(CSIEW0, 0x007f0000);
5539 I915_WRITE(CSIEW1, 0x1e220004);
5540 I915_WRITE(CSIEW2, 0x04000004);
5541
5542 for (i = 0; i < 5; i++)
5543 I915_WRITE(PEW + (i * 4), 0);
5544 for (i = 0; i < 3; i++)
5545 I915_WRITE(DEW + (i * 4), 0);
5546
5547 /* Program P-state weights to account for frequency power adjustment */
5548 for (i = 0; i < 16; i++) {
5549 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5550 unsigned long freq = intel_pxfreq(pxvidfreq);
5551 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5552 PXVFREQ_PX_SHIFT;
5553 unsigned long val;
5554
5555 val = vid * vid;
5556 val *= (freq / 1000);
5557 val *= 255;
5558 val /= (127*127*900);
5559 if (val > 0xff)
5560 DRM_ERROR("bad pxval: %ld\n", val);
5561 pxw[i] = val;
5562 }
5563 /* Render standby states get 0 weight */
5564 pxw[14] = 0;
5565 pxw[15] = 0;
5566
5567 for (i = 0; i < 4; i++) {
5568 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5569 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5570 I915_WRITE(PXW + (i * 4), val);
5571 }
5572
5573 /* Adjust magic regs to magic values (more experimental results) */
5574 I915_WRITE(OGW0, 0);
5575 I915_WRITE(OGW1, 0);
5576 I915_WRITE(EG0, 0x00007f00);
5577 I915_WRITE(EG1, 0x0000000e);
5578 I915_WRITE(EG2, 0x000e0000);
5579 I915_WRITE(EG3, 0x68000300);
5580 I915_WRITE(EG4, 0x42000000);
5581 I915_WRITE(EG5, 0x00140031);
5582 I915_WRITE(EG6, 0);
5583 I915_WRITE(EG7, 0);
5584
5585 for (i = 0; i < 8; i++)
5586 I915_WRITE(PXWL + (i * 4), 0);
5587
5588 /* Enable PMON + select events */
5589 I915_WRITE(ECR, 0x80000019);
5590
5591 lcfuse = I915_READ(LCFUSE02);
5592
20e4d407 5593 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5594}
5595
ae48434c
ID		 5596void intel_init_gt_powersave(struct drm_device *dev)
5597{
e6069ca8
ID		 5598 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5599
38807746
D		 5600 if (IS_CHERRYVIEW(dev))
5601 cherryview_init_gt_powersave(dev);
5602 else if (IS_VALLEYVIEW(dev))
4e80519e 5603 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5604}
5605
5606void intel_cleanup_gt_powersave(struct drm_device *dev)
5607{
38807746
D		 5608 if (IS_CHERRYVIEW(dev))
5609 return;
5610 else if (IS_VALLEYVIEW(dev))
4e80519e 5611 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5612}
5613
dbea3cea
ID		 5614static void gen6_suspend_rps(struct drm_device *dev)
5615{
5616 struct drm_i915_private *dev_priv = dev->dev_private;
5617
5618 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5619
4c2a8897 5620 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 5621}
5622
156c7ca0
JB		 5623/**
5624 * intel_suspend_gt_powersave - suspend PM work and helper threads
5625 * @dev: drm device
5626 *
5627 * We don't want to disable RC6 or other features here, we just want
5628 * to make sure any work we've queued has finished and won't bother
5629 * us while we're suspended.
5630 */
5631void intel_suspend_gt_powersave(struct drm_device *dev)
5632{
5633 struct drm_i915_private *dev_priv = dev->dev_private;
5634
d4d70aa5
ID		 5635 if (INTEL_INFO(dev)->gen < 6)
5636 return;
5637
dbea3cea 5638 gen6_suspend_rps(dev);
b47adc17
D		 5639
5640 /* Force GPU to min freq during suspend */
5641 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5642}
5643
8090c6b9
DV		 5644void intel_disable_gt_powersave(struct drm_device *dev)
5645{
1a01ab3b
JB		 5646 struct drm_i915_private *dev_priv = dev->dev_private;
5647
930ebb46 5648 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5649 ironlake_disable_drps(dev);
38807746 5650 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5651 intel_suspend_gt_powersave(dev);
e494837a 5652
4fc688ce 5653 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 5654 if (INTEL_INFO(dev)->gen >= 9)
5655 gen9_disable_rps(dev);
5656 else if (IS_CHERRYVIEW(dev))
38807746
D		 5657 cherryview_disable_rps(dev);
5658 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5659 valleyview_disable_rps(dev);
5660 else
5661 gen6_disable_rps(dev);
e534770a 5662
c0951f0c 5663 dev_priv->rps.enabled = false;
4fc688ce 5664 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5665 }
8090c6b9
DV		 5666}
5667
1a01ab3b
JB		 5668static void intel_gen6_powersave_work(struct work_struct *work)
5669{
5670 struct drm_i915_private *dev_priv =
5671 container_of(work, struct drm_i915_private,
5672 rps.delayed_resume_work.work);
5673 struct drm_device *dev = dev_priv->dev;
5674
4fc688ce 5675 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5676
4c2a8897 5677 gen6_reset_rps_interrupts(dev);
3cc134e3 5678
38807746
D		 5679 if (IS_CHERRYVIEW(dev)) {
5680 cherryview_enable_rps(dev);
5681 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5682 valleyview_enable_rps(dev);
20e49366 5683 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5684 gen9_enable_rc6(dev);
20e49366 5685 gen9_enable_rps(dev);
b6fef0ef 5686 __gen6_update_ring_freq(dev);
6edee7f3
BW		 5687 } else if (IS_BROADWELL(dev)) {
5688 gen8_enable_rps(dev);
c2bc2fc5 5689 __gen6_update_ring_freq(dev);
0a073b84
JB		 5690 } else {
5691 gen6_enable_rps(dev);
c2bc2fc5 5692 __gen6_update_ring_freq(dev);
0a073b84 5693 }
aed242ff
CW		 5694
5695 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5696 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5697
5698 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5699 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5700
c0951f0c 5701 dev_priv->rps.enabled = true;
3cc134e3 5702
4c2a8897 5703 gen6_enable_rps_interrupts(dev);
3cc134e3 5704
4fc688ce 5705 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5706
5707 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5708}
5709
8090c6b9
DV		 5710void intel_enable_gt_powersave(struct drm_device *dev)
5711{
1a01ab3b
JB		 5712 struct drm_i915_private *dev_priv = dev->dev_private;
5713
f61018b1
YZ		 5714 /* Powersaving is controlled by the host when inside a VM */
5715 if (intel_vgpu_active(dev))
5716 return;
5717
8090c6b9 5718 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5719 mutex_lock(&dev->struct_mutex);
8090c6b9 5720 ironlake_enable_drps(dev);
8090c6b9 5721 intel_init_emon(dev);
dc1d0136 5722 mutex_unlock(&dev->struct_mutex);
38807746 5723 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5724 /*
5725 * PCU communication is slow and this doesn't need to be
5726 * done at any specific time, so do this out of our fast path
5727 * to make resume and init faster.
c6df39b5
ID		 5728 *
5729 * We depend on the HW RC6 power context save/restore
5730 * mechanism when entering D3 through runtime PM suspend. So
5731 * disable RPM until RPS/RC6 is properly setup. We can only
5732 * get here via the driver load/system resume/runtime resume
5733 * paths, so the _noresume version is enough (and in case of
5734 * runtime resume it's necessary).
1a01ab3b 5735 */
c6df39b5
ID		 5736 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5737 round_jiffies_up_relative(HZ)))
5738 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5739 }
5740}
5741
c6df39b5
ID		 5742void intel_reset_gt_powersave(struct drm_device *dev)
5743{
5744 struct drm_i915_private *dev_priv = dev->dev_private;
5745
dbea3cea
ID		 5746 if (INTEL_INFO(dev)->gen < 6)
5747 return;
5748
5749 gen6_suspend_rps(dev);
c6df39b5 5750 dev_priv->rps.enabled = false;
c6df39b5
ID		 5751}
5752
3107bd48
DV		 5753static void ibx_init_clock_gating(struct drm_device *dev)
5754{
5755 struct drm_i915_private *dev_priv = dev->dev_private;
5756
5757 /*
5758 * On Ibex Peak and Cougar Point, we need to disable clock
5759 * gating for the panel power sequencer or it will fail to
5760 * start up when no ports are active.
5761 */
5762 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5763}
5764
0e088b8f
VS		 5765static void g4x_disable_trickle_feed(struct drm_device *dev)
5766{
5767 struct drm_i915_private *dev_priv = dev->dev_private;
5768 int pipe;
5769
055e393f 5770 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5771 I915_WRITE(DSPCNTR(pipe),
5772 I915_READ(DSPCNTR(pipe)) |
5773 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5774 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5775 }
5776}
5777
017636cc
VS		 5778static void ilk_init_lp_watermarks(struct drm_device *dev)
5779{
5780 struct drm_i915_private *dev_priv = dev->dev_private;
5781
5782 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5783 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5784 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5785
5786 /*
5787 * Don't touch WM1S_LP_EN here.
5788 * Doing so could cause underruns.
5789 */
5790}
5791
1fa61106 5792static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5793{
5794 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5795 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5796
f1e8fa56
DL		 5797 /*
5798 * Required for FBC
5799 * WaFbcDisableDpfcClockGating:ilk
5800 */
4d47e4f5
DL		 5801 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5802 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5803 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5804
5805 I915_WRITE(PCH_3DCGDIS0,
5806 MARIUNIT_CLOCK_GATE_DISABLE |
5807 SVSMUNIT_CLOCK_GATE_DISABLE);
5808 I915_WRITE(PCH_3DCGDIS1,
5809 VFMUNIT_CLOCK_GATE_DISABLE);
5810
6f1d69b0
ED		 5811 /*
5812 * According to the spec the following bits should be set in
5813 * order to enable memory self-refresh
5814 * The bit 22/21 of 0x42004
5815 * The bit 5 of 0x42020
5816 * The bit 15 of 0x45000
5817 */
5818 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5819 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5820 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5821 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5822 I915_WRITE(DISP_ARB_CTL,
5823 (I915_READ(DISP_ARB_CTL) |
5824 DISP_FBC_WM_DIS));
017636cc
VS		 5825
5826 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5827
5828 /*
5829 * Based on the document from hardware guys the following bits
5830 * should be set unconditionally in order to enable FBC.
5831 * The bit 22 of 0x42000
5832 * The bit 22 of 0x42004
5833 * The bit 7,8,9 of 0x42020.
5834 */
5835 if (IS_IRONLAKE_M(dev)) {
4bb35334 5836 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5837 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5838 I915_READ(ILK_DISPLAY_CHICKEN1) |
5839 ILK_FBCQ_DIS);
5840 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5841 I915_READ(ILK_DISPLAY_CHICKEN2) |
5842 ILK_DPARB_GATE);
6f1d69b0
ED		 5843 }
5844
4d47e4f5
DL		 5845 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5846
6f1d69b0
ED		 5847 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5848 I915_READ(ILK_DISPLAY_CHICKEN2) |
5849 ILK_ELPIN_409_SELECT);
5850 I915_WRITE(_3D_CHICKEN2,
5851 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5852 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5853
ecdb4eb7 5854 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5855 I915_WRITE(CACHE_MODE_0,
5856 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5857
4e04632e
AG		 5858 /* WaDisable_RenderCache_OperationalFlush:ilk */
5859 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5860
0e088b8f 5861 g4x_disable_trickle_feed(dev);
bdad2b2f 5862
3107bd48
DV		 5863 ibx_init_clock_gating(dev);
5864}
5865
5866static void cpt_init_clock_gating(struct drm_device *dev)
5867{
5868 struct drm_i915_private *dev_priv = dev->dev_private;
5869 int pipe;
3f704fa2 5870 uint32_t val;
3107bd48
DV		 5871
5872 /*
5873 * On Ibex Peak and Cougar Point, we need to disable clock
5874 * gating for the panel power sequencer or it will fail to
5875 * start up when no ports are active.
5876 */
cd664078
JB		 5877 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5878 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5879 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5880 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5881 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5882 /* The below fixes the weird display corruption, a few pixels shifted
5883 * downward, on (only) LVDS of some HP laptops with IVY.
5884 */
055e393f 5885 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 5886 val = I915_READ(TRANS_CHICKEN2(pipe));
5887 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5888 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5889 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5890 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5891 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5892 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5893 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5894 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5895 }
3107bd48 5896 /* WADP0ClockGatingDisable */
055e393f 5897 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 5898 I915_WRITE(TRANS_CHICKEN1(pipe),
5899 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5900 }
6f1d69b0
ED		 5901}
5902
1d7aaa0c
DV		 5903static void gen6_check_mch_setup(struct drm_device *dev)
5904{
5905 struct drm_i915_private *dev_priv = dev->dev_private;
5906 uint32_t tmp;
5907
5908 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 5909 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
5910 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
5911 tmp);
1d7aaa0c
DV		 5912}
5913
1fa61106 5914static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5915{
5916 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5917 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5918
231e54f6 5919 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5920
5921 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5922 I915_READ(ILK_DISPLAY_CHICKEN2) |
5923 ILK_ELPIN_409_SELECT);
5924
ecdb4eb7 5925 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5926 I915_WRITE(_3D_CHICKEN,
5927 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5928
4e04632e
AG		 5929 /* WaDisable_RenderCache_OperationalFlush:snb */
5930 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5931
8d85d272
VS		 5932 /*
5933 * BSpec recoomends 8x4 when MSAA is used,
5934 * however in practice 16x4 seems fastest.
c5c98a58
VS		 5935 *
5936 * Note that PS/WM thread counts depend on the WIZ hashing
5937 * disable bit, which we don't touch here, but it's good
5938 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 5939 */
5940 I915_WRITE(GEN6_GT_MODE,
98533251 5941 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 5942
017636cc 5943 ilk_init_lp_watermarks(dev);
6f1d69b0 5944
6f1d69b0 5945 I915_WRITE(CACHE_MODE_0,
50743298 5946 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5947
5948 I915_WRITE(GEN6_UCGCTL1,
5949 I915_READ(GEN6_UCGCTL1) |
5950 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5951 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5952
5953 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5954 * gating disable must be set. Failure to set it results in
5955 * flickering pixels due to Z write ordering failures after
5956 * some amount of runtime in the Mesa "fire" demo, and Unigine
5957 * Sanctuary and Tropics, and apparently anything else with
5958 * alpha test or pixel discard.
5959 *
5960 * According to the spec, bit 11 (RCCUNIT) must also be set,
5961 * but we didn't debug actual testcases to find it out.
0f846f81 5962 *
ef59318c
VS		 5963 * WaDisableRCCUnitClockGating:snb
5964 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 5965 */
5966 I915_WRITE(GEN6_UCGCTL2,
5967 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5968 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5969
5eb146dd 5970 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 5971 I915_WRITE(_3D_CHICKEN3,
5972 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 5973
e927ecde
VS		 5974 /*
5975 * Bspec says:
5976 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5977 * 3DSTATE_SF number of SF output attributes is more than 16."
5978 */
5979 I915_WRITE(_3D_CHICKEN3,
5980 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5981
6f1d69b0
ED		 5982 /*
5983 * According to the spec the following bits should be
5984 * set in order to enable memory self-refresh and fbc:
5985 * The bit21 and bit22 of 0x42000
5986 * The bit21 and bit22 of 0x42004
5987 * The bit5 and bit7 of 0x42020
5988 * The bit14 of 0x70180
5989 * The bit14 of 0x71180
4bb35334
DL		 5990 *
5991 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5992 */
5993 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5994 I915_READ(ILK_DISPLAY_CHICKEN1) |
5995 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5996 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5997 I915_READ(ILK_DISPLAY_CHICKEN2) |
5998 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5999 I915_WRITE(ILK_DSPCLK_GATE_D,
6000 I915_READ(ILK_DSPCLK_GATE_D) |
6001 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6002 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6003
0e088b8f 6004 g4x_disable_trickle_feed(dev);
f8f2ac9a 6005
3107bd48 6006 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6007
6008 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6009}
6010
6011static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6012{
6013 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6014
3aad9059 6015 /*
46680e0a 6016 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6017 *
6018 * This actually overrides the dispatch
6019 * mode for all thread types.
6020 */
6f1d69b0
ED		 6021 reg &= ~GEN7_FF_SCHED_MASK;
6022 reg |= GEN7_FF_TS_SCHED_HW;
6023 reg |= GEN7_FF_VS_SCHED_HW;
6024 reg |= GEN7_FF_DS_SCHED_HW;
6025
6026 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6027}
6028
17a303ec
PZ		 6029static void lpt_init_clock_gating(struct drm_device *dev)
6030{
6031 struct drm_i915_private *dev_priv = dev->dev_private;
6032
6033 /*
6034 * TODO: this bit should only be enabled when really needed, then
6035 * disabled when not needed anymore in order to save power.
6036 */
6037 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6038 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6039 I915_READ(SOUTH_DSPCLK_GATE_D) |
6040 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6041
6042 /* WADPOClockGatingDisable:hsw */
6043 I915_WRITE(_TRANSA_CHICKEN1,
6044 I915_READ(_TRANSA_CHICKEN1) |
6045 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6046}
6047
7d708ee4
ID		 6048static void lpt_suspend_hw(struct drm_device *dev)
6049{
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051
6052 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6053 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6054
6055 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6056 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6057 }
6058}
6059
47c2bd97 6060static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6061{
6062 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6063 enum pipe pipe;
1020a5c2
BW		 6064
6065 I915_WRITE(WM3_LP_ILK, 0);
6066 I915_WRITE(WM2_LP_ILK, 0);
6067 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 6068
ab57fff1 6069 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6070 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6071
ab57fff1 6072 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6073 I915_WRITE(CHICKEN_PAR1_1,
6074 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6075
ab57fff1 6076 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6077 for_each_pipe(dev_priv, pipe) {
07d27e20 6078 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6079 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6080 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6081 }
63801f21 6082
ab57fff1
BW		 6083 /* WaVSRefCountFullforceMissDisable:bdw */
6084 /* WaDSRefCountFullforceMissDisable:bdw */
6085 I915_WRITE(GEN7_FF_THREAD_MODE,
6086 I915_READ(GEN7_FF_THREAD_MODE) &
6087 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6088
295e8bb7
VS		 6089 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6090 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6091
6092 /* WaDisableSDEUnitClockGating:bdw */
6093 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6094 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6095
89d6b2b8 6096 lpt_init_clock_gating(dev);
1020a5c2
BW		 6097}
6098
cad2a2d7
ED		 6099static void haswell_init_clock_gating(struct drm_device *dev)
6100{
6101 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6102
017636cc 6103 ilk_init_lp_watermarks(dev);
cad2a2d7 6104
f3fc4884
FJ		 6105 /* L3 caching of data atomics doesn't work -- disable it. */
6106 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6107 I915_WRITE(HSW_ROW_CHICKEN3,
6108 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6109
ecdb4eb7 6110 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6111 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6112 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6113 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6114
e36ea7ff
VS		 6115 /* WaVSRefCountFullforceMissDisable:hsw */
6116 I915_WRITE(GEN7_FF_THREAD_MODE,
6117 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6118
4e04632e
AG		 6119 /* WaDisable_RenderCache_OperationalFlush:hsw */
6120 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6121
fe27c606
CW		 6122 /* enable HiZ Raw Stall Optimization */
6123 I915_WRITE(CACHE_MODE_0_GEN7,
6124 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6125
ecdb4eb7 6126 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6127 I915_WRITE(CACHE_MODE_1,
6128 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6129
a12c4967
VS		 6130 /*
6131 * BSpec recommends 8x4 when MSAA is used,
6132 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6133 *
6134 * Note that PS/WM thread counts depend on the WIZ hashing
6135 * disable bit, which we don't touch here, but it's good
6136 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6137 */
6138 I915_WRITE(GEN7_GT_MODE,
98533251 6139 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6140
94411593
KG		 6141 /* WaSampleCChickenBitEnable:hsw */
6142 I915_WRITE(HALF_SLICE_CHICKEN3,
6143 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6144
ecdb4eb7 6145 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6146 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6147
90a88643
PZ		 6148 /* WaRsPkgCStateDisplayPMReq:hsw */
6149 I915_WRITE(CHICKEN_PAR1_1,
6150 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6151
17a303ec 6152 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6153}
6154
1fa61106 6155static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6156{
6157 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6158 uint32_t snpcr;
6f1d69b0 6159
017636cc 6160 ilk_init_lp_watermarks(dev);
6f1d69b0 6161
231e54f6 6162 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6163
ecdb4eb7 6164 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6165 I915_WRITE(_3D_CHICKEN3,
6166 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6167
ecdb4eb7 6168 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6169 I915_WRITE(IVB_CHICKEN3,
6170 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6171 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6172
ecdb4eb7 6173 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6174 if (IS_IVB_GT1(dev))
6175 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6176 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6177
4e04632e
AG		 6178 /* WaDisable_RenderCache_OperationalFlush:ivb */
6179 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6180
ecdb4eb7 6181 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6182 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6183 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6184
ecdb4eb7 6185 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6186 I915_WRITE(GEN7_L3CNTLREG1,
6187 GEN7_WA_FOR_GEN7_L3_CONTROL);
6188 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6189 GEN7_WA_L3_CHICKEN_MODE);
6190 if (IS_IVB_GT1(dev))
6191 I915_WRITE(GEN7_ROW_CHICKEN2,
6192 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6193 else {
6194 /* must write both registers */
6195 I915_WRITE(GEN7_ROW_CHICKEN2,
6196 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6197 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6198 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6199 }
6f1d69b0 6200
ecdb4eb7 6201 /* WaForceL3Serialization:ivb */
61939d97
JB		 6202 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6203 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6204
1b80a19a 6205 /*
0f846f81 6206 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6207 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6208 */
6209 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6210 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6211
ecdb4eb7 6212 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6213 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6214 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6215 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6216
0e088b8f 6217 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6218
6219 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6220
22721343
CW		 6221 if (0) { /* causes HiZ corruption on ivb:gt1 */
6222 /* enable HiZ Raw Stall Optimization */
6223 I915_WRITE(CACHE_MODE_0_GEN7,
6224 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6225 }
116f2b6d 6226
ecdb4eb7 6227 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6228 I915_WRITE(CACHE_MODE_1,
6229 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6230
a607c1a4
VS		 6231 /*
6232 * BSpec recommends 8x4 when MSAA is used,
6233 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6234 *
6235 * Note that PS/WM thread counts depend on the WIZ hashing
6236 * disable bit, which we don't touch here, but it's good
6237 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6238 */
6239 I915_WRITE(GEN7_GT_MODE,
98533251 6240 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6241
20848223
BW		 6242 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6243 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6244 snpcr |= GEN6_MBC_SNPCR_MED;
6245 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6246
ab5c608b
BW		 6247 if (!HAS_PCH_NOP(dev))
6248 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6249
6250 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6251}
6252
c6beb13e
VS		 6253static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6254{
6255 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6256
6257 /*
6258 * Disable trickle feed and enable pnd deadline calculation
6259 */
6260 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6261 I915_WRITE(CBR1_VLV, 0);
6262}
6263
1fa61106 6264static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6265{
6266 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6267
c6beb13e 6268 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6269
ecdb4eb7 6270 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6271 I915_WRITE(_3D_CHICKEN3,
6272 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6273
ecdb4eb7 6274 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6275 I915_WRITE(IVB_CHICKEN3,
6276 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6277 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6278
fad7d36e 6279 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6280 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6281 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6282 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6283 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6284
4e04632e
AG		 6285 /* WaDisable_RenderCache_OperationalFlush:vlv */
6286 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6287
ecdb4eb7 6288 /* WaForceL3Serialization:vlv */
61939d97
JB		 6289 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6290 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6291
ecdb4eb7 6292 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6293 I915_WRITE(GEN7_ROW_CHICKEN2,
6294 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6295
ecdb4eb7 6296 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6297 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6298 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6299 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6300
46680e0a
VS		 6301 gen7_setup_fixed_func_scheduler(dev_priv);
6302
3c0edaeb 6303 /*
0f846f81 6304 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6305 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6306 */
6307 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6308 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6309
c98f5062
AG		 6310 /* WaDisableL3Bank2xClockGate:vlv
6311 * Disabling L3 clock gating- MMIO 940c[25] = 1
6312 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6313 I915_WRITE(GEN7_UCGCTL4,
6314 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6315
afd58e79
VS		 6316 /*
6317 * BSpec says this must be set, even though
6318 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6319 */
6b26c86d
DV		 6320 I915_WRITE(CACHE_MODE_1,
6321 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6322
da2518f9
VS		 6323 /*
6324 * BSpec recommends 8x4 when MSAA is used,
6325 * however in practice 16x4 seems fastest.
6326 *
6327 * Note that PS/WM thread counts depend on the WIZ hashing
6328 * disable bit, which we don't touch here, but it's good
6329 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6330 */
6331 I915_WRITE(GEN7_GT_MODE,
6332 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6333
031994ee
VS		 6334 /*
6335 * WaIncreaseL3CreditsForVLVB0:vlv
6336 * This is the hardware default actually.
6337 */
6338 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6339
2d809570 6340 /*
ecdb4eb7 6341 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6342 * Disable clock gating on th GCFG unit to prevent a delay
6343 * in the reporting of vblank events.
6344 */
7a0d1eed 6345 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6346}
6347
a4565da8
VS		 6348static void cherryview_init_clock_gating(struct drm_device *dev)
6349{
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351
c6beb13e 6352 vlv_init_display_clock_gating(dev_priv);
dd811e70 6353
232ce337
VS		 6354 /* WaVSRefCountFullforceMissDisable:chv */
6355 /* WaDSRefCountFullforceMissDisable:chv */
6356 I915_WRITE(GEN7_FF_THREAD_MODE,
6357 I915_READ(GEN7_FF_THREAD_MODE) &
6358 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6359
6360 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6361 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6362 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6363
6364 /* WaDisableCSUnitClockGating:chv */
6365 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6366 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6367
6368 /* WaDisableSDEUnitClockGating:chv */
6369 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6370 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6371}
6372
1fa61106 6373static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6374{
6375 struct drm_i915_private *dev_priv = dev->dev_private;
6376 uint32_t dspclk_gate;
6377
6378 I915_WRITE(RENCLK_GATE_D1, 0);
6379 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6380 GS_UNIT_CLOCK_GATE_DISABLE |
6381 CL_UNIT_CLOCK_GATE_DISABLE);
6382 I915_WRITE(RAMCLK_GATE_D, 0);
6383 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6384 OVRUNIT_CLOCK_GATE_DISABLE |
6385 OVCUNIT_CLOCK_GATE_DISABLE;
6386 if (IS_GM45(dev))
6387 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6388 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6389
6390 /* WaDisableRenderCachePipelinedFlush */
6391 I915_WRITE(CACHE_MODE_0,
6392 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6393
4e04632e
AG		 6394 /* WaDisable_RenderCache_OperationalFlush:g4x */
6395 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6396
0e088b8f 6397 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6398}
6399
1fa61106 6400static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6401{
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403
6404 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6405 I915_WRITE(RENCLK_GATE_D2, 0);
6406 I915_WRITE(DSPCLK_GATE_D, 0);
6407 I915_WRITE(RAMCLK_GATE_D, 0);
6408 I915_WRITE16(DEUC, 0);
20f94967
VS		 6409 I915_WRITE(MI_ARB_STATE,
6410 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6411
6412 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6413 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6414}
6415
1fa61106 6416static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6417{
6418 struct drm_i915_private *dev_priv = dev->dev_private;
6419
6420 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6421 I965_RCC_CLOCK_GATE_DISABLE |
6422 I965_RCPB_CLOCK_GATE_DISABLE |
6423 I965_ISC_CLOCK_GATE_DISABLE |
6424 I965_FBC_CLOCK_GATE_DISABLE);
6425 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6426 I915_WRITE(MI_ARB_STATE,
6427 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6428
6429 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6430 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6431}
6432
1fa61106 6433static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6434{
6435 struct drm_i915_private *dev_priv = dev->dev_private;
6436 u32 dstate = I915_READ(D_STATE);
6437
6438 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6439 DSTATE_DOT_CLOCK_GATING;
6440 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6441
6442 if (IS_PINEVIEW(dev))
6443 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6444
6445 /* IIR "flip pending" means done if this bit is set */
6446 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6447
6448 /* interrupts should cause a wake up from C3 */
3299254f 6449 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6450
6451 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6452 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6453
6454 I915_WRITE(MI_ARB_STATE,
6455 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6456}
6457
1fa61106 6458static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6459{
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461
6462 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6463
6464 /* interrupts should cause a wake up from C3 */
6465 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6466 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6467
6468 I915_WRITE(MEM_MODE,
6469 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6470}
6471
1fa61106 6472static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6473{
6474 struct drm_i915_private *dev_priv = dev->dev_private;
6475
6476 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6477
6478 I915_WRITE(MEM_MODE,
6479 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6480 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6481}
6482
6f1d69b0
ED		 6483void intel_init_clock_gating(struct drm_device *dev)
6484{
6485 struct drm_i915_private *dev_priv = dev->dev_private;
6486
c57e3551
DL		 6487 if (dev_priv->display.init_clock_gating)
6488 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6489}
6490
7d708ee4
ID		 6491void intel_suspend_hw(struct drm_device *dev)
6492{
6493 if (HAS_PCH_LPT(dev))
6494 lpt_suspend_hw(dev);
6495}
6496
1fa61106
ED		 6497/* Set up chip specific power management-related functions */
6498void intel_init_pm(struct drm_device *dev)
6499{
6500 struct drm_i915_private *dev_priv = dev->dev_private;
6501
7ff0ebcc 6502 intel_fbc_init(dev_priv);
1fa61106 6503
c921aba8
DV		 6504 /* For cxsr */
6505 if (IS_PINEVIEW(dev))
6506 i915_pineview_get_mem_freq(dev);
6507 else if (IS_GEN5(dev))
6508 i915_ironlake_get_mem_freq(dev);
6509
1fa61106 6510 /* For FIFO watermark updates */
f5ed50cb 6511 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6512 skl_setup_wm_latency(dev);
6513
45db2194 6514 dev_priv->display.init_clock_gating = skl_init_clock_gating;
2d41c0b5
PB		 6515 dev_priv->display.update_wm = skl_update_wm;
6516 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6517 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6518 ilk_setup_wm_latency(dev);
53615a5e 6519
bd602544
VS		 6520 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6521 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6522 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6523 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6524 dev_priv->display.update_wm = ilk_update_wm;
6525 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6526 } else {
6527 DRM_DEBUG_KMS("Failed to read display plane latency. "
6528 "Disable CxSR\n");
6529 }
6530
6531 if (IS_GEN5(dev))
1fa61106 6532 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6533 else if (IS_GEN6(dev))
1fa61106 6534 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6535 else if (IS_IVYBRIDGE(dev))
1fa61106 6536 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6537 else if (IS_HASWELL(dev))
cad2a2d7 6538 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6539 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6540 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6541 } else if (IS_CHERRYVIEW(dev)) {
ae80152d 6542 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6543 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6544 dev_priv->display.init_clock_gating =
6545 cherryview_init_clock_gating;
1fa61106
ED		 6546 } else if (IS_VALLEYVIEW(dev)) {
6547 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6548 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6549 dev_priv->display.init_clock_gating =
6550 valleyview_init_clock_gating;
1fa61106
ED		 6551 } else if (IS_PINEVIEW(dev)) {
6552 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6553 dev_priv->is_ddr3,
6554 dev_priv->fsb_freq,
6555 dev_priv->mem_freq)) {
6556 DRM_INFO("failed to find known CxSR latency "
6557 "(found ddr%s fsb freq %d, mem freq %d), "
6558 "disabling CxSR\n",
6559 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6560 dev_priv->fsb_freq, dev_priv->mem_freq);
6561 /* Disable CxSR and never update its watermark again */
5209b1f4 6562 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6563 dev_priv->display.update_wm = NULL;
6564 } else
6565 dev_priv->display.update_wm = pineview_update_wm;
6566 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6567 } else if (IS_G4X(dev)) {
6568 dev_priv->display.update_wm = g4x_update_wm;
6569 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6570 } else if (IS_GEN4(dev)) {
6571 dev_priv->display.update_wm = i965_update_wm;
6572 if (IS_CRESTLINE(dev))
6573 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6574 else if (IS_BROADWATER(dev))
6575 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6576 } else if (IS_GEN3(dev)) {
6577 dev_priv->display.update_wm = i9xx_update_wm;
6578 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6579 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6580 } else if (IS_GEN2(dev)) {
6581 if (INTEL_INFO(dev)->num_pipes == 1) {
6582 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6583 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6584 } else {
6585 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6586 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6587 }
6588
6589 if (IS_I85X(dev) || IS_I865G(dev))
6590 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6591 else
6592 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6593 } else {
6594 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6595 }
6596}
6597
151a49d0 6598int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6599{
4fc688ce 6600 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6601
6602 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6603 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6604 return -EAGAIN;
6605 }
6606
6607 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6608 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 6609 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6610
6611 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6612 500)) {
6613 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6614 return -ETIMEDOUT;
6615 }
6616
6617 *val = I915_READ(GEN6_PCODE_DATA);
6618 I915_WRITE(GEN6_PCODE_DATA, 0);
6619
6620 return 0;
6621}
6622
151a49d0 6623int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6624{
4fc688ce 6625 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6626
6627 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6628 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6629 return -EAGAIN;
6630 }
6631
6632 I915_WRITE(GEN6_PCODE_DATA, val);
6633 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6634
6635 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6636 500)) {
6637 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6638 return -ETIMEDOUT;
6639 }
6640
6641 I915_WRITE(GEN6_PCODE_DATA, 0);
6642
6643 return 0;
6644}
a0e4e199 6645
dd06f88c 6646static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6647{
dd06f88c
VS		 6648 switch (czclk_freq) {
6649 case 200:
6650 return 10;
6651 case 267:
6652 return 12;
6653 case 320:
6654 case 333:
dd06f88c 6655 return 16;
ab3fb157
VS		 6656 case 400:
6657 return 20;
855ba3be
JB		 6658 default:
6659 return -1;
6660 }
dd06f88c 6661}
855ba3be 6662
dd06f88c
VS		 6663static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6664{
6665 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6666
6667 div = vlv_gpu_freq_div(czclk_freq);
6668 if (div < 0)
6669 return div;
6670
6671 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 6672}
6673
b55dd647 6674static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6675{
dd06f88c 6676 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6677
dd06f88c
VS		 6678 mul = vlv_gpu_freq_div(czclk_freq);
6679 if (mul < 0)
6680 return mul;
855ba3be 6681
dd06f88c 6682 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 6683}
6684
b55dd647 6685static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6686{
dd06f88c 6687 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6688
dd06f88c
VS		 6689 div = vlv_gpu_freq_div(czclk_freq) / 2;
6690 if (div < 0)
6691 return div;
22b1b2f8 6692
dd06f88c 6693 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 6694}
6695
b55dd647 6696static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6697{
dd06f88c 6698 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6699
dd06f88c
VS		 6700 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6701 if (mul < 0)
6702 return mul;
22b1b2f8 6703
1c14762d 6704 /* CHV needs even values */
dd06f88c 6705 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 6706}
6707
616bc820 6708int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6709{
80b6dda4
AG		 6710 if (IS_GEN9(dev_priv->dev))
6711 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6712 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6713 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6714 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6715 return byt_gpu_freq(dev_priv, val);
6716 else
6717 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 6718}
6719
616bc820
VS		 6720int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6721{
80b6dda4
AG		 6722 if (IS_GEN9(dev_priv->dev))
6723 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6724 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6725 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6726 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6727 return byt_freq_opcode(dev_priv, val);
6728 else
6729 return val / GT_FREQUENCY_MULTIPLIER;
6730}
22b1b2f8 6731
f742a552 6732void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6733{
6734 struct drm_i915_private *dev_priv = dev->dev_private;
6735
f742a552
DV		 6736 mutex_init(&dev_priv->rps.hw_lock);
6737
907b28c5
CW		 6738 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6739 intel_gen6_powersave_work);
5d584b2e 6740
33688d95 6741 dev_priv->pm.suspended = false;
907b28c5 6742}
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