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drm/i915: Fix a few style issues found by checkpatch.pl
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
3490ea5d
CW		 47static bool intel_crtc_active(struct drm_crtc *crtc)
48{
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53}
54
1fa61106 55static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 56{
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75}
76
1fa61106 77static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 78{
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
84f44ce7
VS		 116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
117 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 118}
119
1fa61106 120static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125}
126
1fa61106 127static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 128{
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
84f44ce7 151 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 152}
153
1fa61106 154static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 155{
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167}
168
1fa61106 169static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 170{
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174}
175
176static void sandybridge_blit_fbc_update(struct drm_device *dev)
177{
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194}
195
1fa61106 196static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 197{
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
84f44ce7 231 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 232}
233
1fa61106 234static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 235{
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
b74ea102 245 if (IS_IVYBRIDGE(dev))
7dd23ba0 246 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 247 I915_WRITE(ILK_DSPCLK_GATE_D,
248 I915_READ(ILK_DSPCLK_GATE_D) &
249 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
250
d89f2071 251 if (IS_HASWELL(dev))
7dd23ba0 252 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 253 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
254 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
255 ~HSW_DPFC_GATING_DISABLE);
256
85208be0
ED		 257 DRM_DEBUG_KMS("disabled FBC\n");
258 }
259}
260
1fa61106 261static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264
265 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
266}
267
abe959c7
RV		 268static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269{
270 struct drm_device *dev = crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 struct drm_framebuffer *fb = crtc->fb;
273 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276
fd3da6c9 277 I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset);
abe959c7
RV		 278
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN |
281 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282
891348b2 283 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 285 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 286 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 287 I915_WRITE(ILK_DSPCLK_GATE_D,
288 I915_READ(ILK_DSPCLK_GATE_D) |
289 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 290 } else {
7dd23ba0 291 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 292 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
293 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 294 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 295 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
296 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
297 HSW_DPFC_GATING_DISABLE);
891348b2 298 }
b74ea102 299
abe959c7
RV		 300 I915_WRITE(SNB_DPFC_CTL_SA,
301 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
302 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
303
304 sandybridge_blit_fbc_update(dev);
305
306 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
307}
308
85208be0
ED		 309bool intel_fbc_enabled(struct drm_device *dev)
310{
311 struct drm_i915_private *dev_priv = dev->dev_private;
312
313 if (!dev_priv->display.fbc_enabled)
314 return false;
315
316 return dev_priv->display.fbc_enabled(dev);
317}
318
319static void intel_fbc_work_fn(struct work_struct *__work)
320{
321 struct intel_fbc_work *work =
322 container_of(to_delayed_work(__work),
323 struct intel_fbc_work, work);
324 struct drm_device *dev = work->crtc->dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326
327 mutex_lock(&dev->struct_mutex);
328 if (work == dev_priv->fbc_work) {
329 /* Double check that we haven't switched fb without cancelling
330 * the prior work.
331 */
332 if (work->crtc->fb == work->fb) {
333 dev_priv->display.enable_fbc(work->crtc,
334 work->interval);
335
336 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->cfb_fb = work->crtc->fb->base.id;
338 dev_priv->cfb_y = work->crtc->y;
339 }
340
341 dev_priv->fbc_work = NULL;
342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346}
347
348static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349{
350 if (dev_priv->fbc_work == NULL)
351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
356 * dev_priv->fbc_work, so we can perform the cancellation
357 * entirely asynchronously.
358 */
359 if (cancel_delayed_work(&dev_priv->fbc_work->work))
360 /* tasklet was killed before being run, clean up */
361 kfree(dev_priv->fbc_work);
362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
368 dev_priv->fbc_work = NULL;
369}
370
b63fb44c 371static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 372{
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
382 work = kzalloc(sizeof *work, GFP_KERNEL);
383 if (work == NULL) {
6cdcb5e7 384 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 385 dev_priv->display.enable_fbc(crtc, interval);
386 return;
387 }
388
389 work->crtc = crtc;
390 work->fb = crtc->fb;
391 work->interval = interval;
392 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
393
394 dev_priv->fbc_work = work;
395
85208be0
ED		 396 /* Delay the actual enabling to let pageflipping cease and the
397 * display to settle before starting the compression. Note that
398 * this delay also serves a second purpose: it allows for a
399 * vblank to pass after disabling the FBC before we attempt
400 * to modify the control registers.
401 *
402 * A more complicated solution would involve tracking vblanks
403 * following the termination of the page-flipping sequence
404 * and indeed performing the enable as a co-routine and not
405 * waiting synchronously upon the vblank.
406 */
407 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
408}
409
410void intel_disable_fbc(struct drm_device *dev)
411{
412 struct drm_i915_private *dev_priv = dev->dev_private;
413
414 intel_cancel_fbc_work(dev_priv);
415
416 if (!dev_priv->display.disable_fbc)
417 return;
418
419 dev_priv->display.disable_fbc(dev);
420 dev_priv->cfb_plane = -1;
421}
422
423/**
424 * intel_update_fbc - enable/disable FBC as needed
425 * @dev: the drm_device
426 *
427 * Set up the framebuffer compression hardware at mode set time. We
428 * enable it if possible:
429 * - plane A only (on pre-965)
430 * - no pixel mulitply/line duplication
431 * - no alpha buffer discard
432 * - no dual wide
f85da868 433 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 434 *
435 * We can't assume that any compression will take place (worst case),
436 * so the compressed buffer has to be the same size as the uncompressed
437 * one. It also must reside (along with the line length buffer) in
438 * stolen memory.
439 *
440 * We need to enable/disable FBC on a global basis.
441 */
442void intel_update_fbc(struct drm_device *dev)
443{
444 struct drm_i915_private *dev_priv = dev->dev_private;
445 struct drm_crtc *crtc = NULL, *tmp_crtc;
446 struct intel_crtc *intel_crtc;
447 struct drm_framebuffer *fb;
448 struct intel_framebuffer *intel_fb;
449 struct drm_i915_gem_object *obj;
f85da868 450 unsigned int max_hdisplay, max_vdisplay;
85208be0 451
85208be0
ED		 452 if (!i915_powersave)
453 return;
454
455 if (!I915_HAS_FBC(dev))
456 return;
457
458 /*
459 * If FBC is already on, we just have to verify that we can
460 * keep it that way...
461 * Need to disable if:
462 * - more than one pipe is active
463 * - changing FBC params (stride, fence, mode)
464 * - new fb is too large to fit in compressed buffer
465 * - going to an unsupported config (interlace, pixel multiply, etc.)
466 */
467 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 468 if (intel_crtc_active(tmp_crtc) &&
469 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 470 if (crtc) {
471 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
472 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
473 goto out_disable;
474 }
475 crtc = tmp_crtc;
476 }
477 }
478
479 if (!crtc || crtc->fb == NULL) {
480 DRM_DEBUG_KMS("no output, disabling\n");
481 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
482 goto out_disable;
483 }
484
485 intel_crtc = to_intel_crtc(crtc);
486 fb = crtc->fb;
487 intel_fb = to_intel_framebuffer(fb);
488 obj = intel_fb->obj;
489
8a5729a3
DL		 490 if (i915_enable_fbc < 0 &&
491 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
492 DRM_DEBUG_KMS("disabled per chip default\n");
493 dev_priv->no_fbc_reason = FBC_CHIP_DEFAULT;
494 goto out_disable;
85208be0 495 }
8a5729a3 496 if (!i915_enable_fbc) {
85208be0
ED		 497 DRM_DEBUG_KMS("fbc disabled per module param\n");
498 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
499 goto out_disable;
500 }
85208be0
ED		 501 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
502 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
503 DRM_DEBUG_KMS("mode incompatible with compression, "
504 "disabling\n");
505 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
506 goto out_disable;
507 }
f85da868
PZ		 508
509 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
510 max_hdisplay = 4096;
511 max_vdisplay = 2048;
512 } else {
513 max_hdisplay = 2048;
514 max_vdisplay = 1536;
515 }
516 if ((crtc->mode.hdisplay > max_hdisplay) ||
517 (crtc->mode.vdisplay > max_vdisplay)) {
85208be0
ED		 518 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
519 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
520 goto out_disable;
521 }
891348b2
RV		 522 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
523 intel_crtc->plane != 0) {
85208be0
ED		 524 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
525 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
526 goto out_disable;
527 }
528
529 /* The use of a CPU fence is mandatory in order to detect writes
530 * by the CPU to the scanout and trigger updates to the FBC.
531 */
532 if (obj->tiling_mode != I915_TILING_X ||
533 obj->fence_reg == I915_FENCE_REG_NONE) {
534 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
535 dev_priv->no_fbc_reason = FBC_NOT_TILED;
536 goto out_disable;
537 }
538
539 /* If the kernel debugger is active, always disable compression */
540 if (in_dbg_master())
541 goto out_disable;
542
11be49eb 543 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
11be49eb
CW		 544 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
545 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
546 goto out_disable;
547 }
548
85208be0
ED		 549 /* If the scanout has not changed, don't modify the FBC settings.
550 * Note that we make the fundamental assumption that the fb->obj
551 * cannot be unpinned (and have its GTT offset and fence revoked)
552 * without first being decoupled from the scanout and FBC disabled.
553 */
554 if (dev_priv->cfb_plane == intel_crtc->plane &&
555 dev_priv->cfb_fb == fb->base.id &&
556 dev_priv->cfb_y == crtc->y)
557 return;
558
559 if (intel_fbc_enabled(dev)) {
560 /* We update FBC along two paths, after changing fb/crtc
561 * configuration (modeswitching) and after page-flipping
562 * finishes. For the latter, we know that not only did
563 * we disable the FBC at the start of the page-flip
564 * sequence, but also more than one vblank has passed.
565 *
566 * For the former case of modeswitching, it is possible
567 * to switch between two FBC valid configurations
568 * instantaneously so we do need to disable the FBC
569 * before we can modify its control registers. We also
570 * have to wait for the next vblank for that to take
571 * effect. However, since we delay enabling FBC we can
572 * assume that a vblank has passed since disabling and
573 * that we can safely alter the registers in the deferred
574 * callback.
575 *
576 * In the scenario that we go from a valid to invalid
577 * and then back to valid FBC configuration we have
578 * no strict enforcement that a vblank occurred since
579 * disabling the FBC. However, along all current pipe
580 * disabling paths we do need to wait for a vblank at
581 * some point. And we wait before enabling FBC anyway.
582 */
583 DRM_DEBUG_KMS("disabling active FBC for update\n");
584 intel_disable_fbc(dev);
585 }
586
587 intel_enable_fbc(crtc, 500);
588 return;
589
590out_disable:
591 /* Multiple disables should be harmless */
592 if (intel_fbc_enabled(dev)) {
593 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
594 intel_disable_fbc(dev);
595 }
11be49eb 596 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 597}
598
c921aba8
DV		 599static void i915_pineview_get_mem_freq(struct drm_device *dev)
600{
601 drm_i915_private_t *dev_priv = dev->dev_private;
602 u32 tmp;
603
604 tmp = I915_READ(CLKCFG);
605
606 switch (tmp & CLKCFG_FSB_MASK) {
607 case CLKCFG_FSB_533:
608 dev_priv->fsb_freq = 533; /* 133*4 */
609 break;
610 case CLKCFG_FSB_800:
611 dev_priv->fsb_freq = 800; /* 200*4 */
612 break;
613 case CLKCFG_FSB_667:
614 dev_priv->fsb_freq = 667; /* 167*4 */
615 break;
616 case CLKCFG_FSB_400:
617 dev_priv->fsb_freq = 400; /* 100*4 */
618 break;
619 }
620
621 switch (tmp & CLKCFG_MEM_MASK) {
622 case CLKCFG_MEM_533:
623 dev_priv->mem_freq = 533;
624 break;
625 case CLKCFG_MEM_667:
626 dev_priv->mem_freq = 667;
627 break;
628 case CLKCFG_MEM_800:
629 dev_priv->mem_freq = 800;
630 break;
631 }
632
633 /* detect pineview DDR3 setting */
634 tmp = I915_READ(CSHRDDR3CTL);
635 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
636}
637
638static void i915_ironlake_get_mem_freq(struct drm_device *dev)
639{
640 drm_i915_private_t *dev_priv = dev->dev_private;
641 u16 ddrpll, csipll;
642
643 ddrpll = I915_READ16(DDRMPLL1);
644 csipll = I915_READ16(CSIPLL0);
645
646 switch (ddrpll & 0xff) {
647 case 0xc:
648 dev_priv->mem_freq = 800;
649 break;
650 case 0x10:
651 dev_priv->mem_freq = 1066;
652 break;
653 case 0x14:
654 dev_priv->mem_freq = 1333;
655 break;
656 case 0x18:
657 dev_priv->mem_freq = 1600;
658 break;
659 default:
660 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
661 ddrpll & 0xff);
662 dev_priv->mem_freq = 0;
663 break;
664 }
665
20e4d407 666 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 667
668 switch (csipll & 0x3ff) {
669 case 0x00c:
670 dev_priv->fsb_freq = 3200;
671 break;
672 case 0x00e:
673 dev_priv->fsb_freq = 3733;
674 break;
675 case 0x010:
676 dev_priv->fsb_freq = 4266;
677 break;
678 case 0x012:
679 dev_priv->fsb_freq = 4800;
680 break;
681 case 0x014:
682 dev_priv->fsb_freq = 5333;
683 break;
684 case 0x016:
685 dev_priv->fsb_freq = 5866;
686 break;
687 case 0x018:
688 dev_priv->fsb_freq = 6400;
689 break;
690 default:
691 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
692 csipll & 0x3ff);
693 dev_priv->fsb_freq = 0;
694 break;
695 }
696
697 if (dev_priv->fsb_freq == 3200) {
20e4d407 698 dev_priv->ips.c_m = 0;
c921aba8 699 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 700 dev_priv->ips.c_m = 1;
c921aba8 701 } else {
20e4d407 702 dev_priv->ips.c_m = 2;
c921aba8
DV		 703 }
704}
705
b445e3b0
ED		 706static const struct cxsr_latency cxsr_latency_table[] = {
707 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
708 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
709 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
710 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
711 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
712
713 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
714 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
715 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
716 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
717 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
718
719 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
720 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
721 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
722 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
723 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
724
725 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
726 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
727 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
728 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
729 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
730
731 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
732 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
733 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
734 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
735 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
736
737 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
738 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
739 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
740 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
741 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
742};
743
63c62275 744static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 745 int is_ddr3,
746 int fsb,
747 int mem)
748{
749 const struct cxsr_latency *latency;
750 int i;
751
752 if (fsb == 0 || mem == 0)
753 return NULL;
754
755 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
756 latency = &cxsr_latency_table[i];
757 if (is_desktop == latency->is_desktop &&
758 is_ddr3 == latency->is_ddr3 &&
759 fsb == latency->fsb_freq && mem == latency->mem_freq)
760 return latency;
761 }
762
763 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
764
765 return NULL;
766}
767
1fa61106 768static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 769{
770 struct drm_i915_private *dev_priv = dev->dev_private;
771
772 /* deactivate cxsr */
773 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
774}
775
776/*
777 * Latency for FIFO fetches is dependent on several factors:
778 * - memory configuration (speed, channels)
779 * - chipset
780 * - current MCH state
781 * It can be fairly high in some situations, so here we assume a fairly
782 * pessimal value. It's a tradeoff between extra memory fetches (if we
783 * set this value too high, the FIFO will fetch frequently to stay full)
784 * and power consumption (set it too low to save power and we might see
785 * FIFO underruns and display "flicker").
786 *
787 * A value of 5us seems to be a good balance; safe for very low end
788 * platforms but not overly aggressive on lower latency configs.
789 */
790static const int latency_ns = 5000;
791
1fa61106 792static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 793{
794 struct drm_i915_private *dev_priv = dev->dev_private;
795 uint32_t dsparb = I915_READ(DSPARB);
796 int size;
797
798 size = dsparb & 0x7f;
799 if (plane)
800 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
801
802 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
803 plane ? "B" : "A", size);
804
805 return size;
806}
807
1fa61106 808static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 809{
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 uint32_t dsparb = I915_READ(DSPARB);
812 int size;
813
814 size = dsparb & 0x1ff;
815 if (plane)
816 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
817 size >>= 1; /* Convert to cachelines */
818
819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
820 plane ? "B" : "A", size);
821
822 return size;
823}
824
1fa61106 825static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 uint32_t dsparb = I915_READ(DSPARB);
829 int size;
830
831 size = dsparb & 0x7f;
832 size >>= 2; /* Convert to cachelines */
833
834 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
835 plane ? "B" : "A",
836 size);
837
838 return size;
839}
840
1fa61106 841static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 842{
843 struct drm_i915_private *dev_priv = dev->dev_private;
844 uint32_t dsparb = I915_READ(DSPARB);
845 int size;
846
847 size = dsparb & 0x7f;
848 size >>= 1; /* Convert to cachelines */
849
850 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
851 plane ? "B" : "A", size);
852
853 return size;
854}
855
856/* Pineview has different values for various configs */
857static const struct intel_watermark_params pineview_display_wm = {
858 PINEVIEW_DISPLAY_FIFO,
859 PINEVIEW_MAX_WM,
860 PINEVIEW_DFT_WM,
861 PINEVIEW_GUARD_WM,
862 PINEVIEW_FIFO_LINE_SIZE
863};
864static const struct intel_watermark_params pineview_display_hplloff_wm = {
865 PINEVIEW_DISPLAY_FIFO,
866 PINEVIEW_MAX_WM,
867 PINEVIEW_DFT_HPLLOFF_WM,
868 PINEVIEW_GUARD_WM,
869 PINEVIEW_FIFO_LINE_SIZE
870};
871static const struct intel_watermark_params pineview_cursor_wm = {
872 PINEVIEW_CURSOR_FIFO,
873 PINEVIEW_CURSOR_MAX_WM,
874 PINEVIEW_CURSOR_DFT_WM,
875 PINEVIEW_CURSOR_GUARD_WM,
876 PINEVIEW_FIFO_LINE_SIZE,
877};
878static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
879 PINEVIEW_CURSOR_FIFO,
880 PINEVIEW_CURSOR_MAX_WM,
881 PINEVIEW_CURSOR_DFT_WM,
882 PINEVIEW_CURSOR_GUARD_WM,
883 PINEVIEW_FIFO_LINE_SIZE
884};
885static const struct intel_watermark_params g4x_wm_info = {
886 G4X_FIFO_SIZE,
887 G4X_MAX_WM,
888 G4X_MAX_WM,
889 2,
890 G4X_FIFO_LINE_SIZE,
891};
892static const struct intel_watermark_params g4x_cursor_wm_info = {
893 I965_CURSOR_FIFO,
894 I965_CURSOR_MAX_WM,
895 I965_CURSOR_DFT_WM,
896 2,
897 G4X_FIFO_LINE_SIZE,
898};
899static const struct intel_watermark_params valleyview_wm_info = {
900 VALLEYVIEW_FIFO_SIZE,
901 VALLEYVIEW_MAX_WM,
902 VALLEYVIEW_MAX_WM,
903 2,
904 G4X_FIFO_LINE_SIZE,
905};
906static const struct intel_watermark_params valleyview_cursor_wm_info = {
907 I965_CURSOR_FIFO,
908 VALLEYVIEW_CURSOR_MAX_WM,
909 I965_CURSOR_DFT_WM,
910 2,
911 G4X_FIFO_LINE_SIZE,
912};
913static const struct intel_watermark_params i965_cursor_wm_info = {
914 I965_CURSOR_FIFO,
915 I965_CURSOR_MAX_WM,
916 I965_CURSOR_DFT_WM,
917 2,
918 I915_FIFO_LINE_SIZE,
919};
920static const struct intel_watermark_params i945_wm_info = {
921 I945_FIFO_SIZE,
922 I915_MAX_WM,
923 1,
924 2,
925 I915_FIFO_LINE_SIZE
926};
927static const struct intel_watermark_params i915_wm_info = {
928 I915_FIFO_SIZE,
929 I915_MAX_WM,
930 1,
931 2,
932 I915_FIFO_LINE_SIZE
933};
934static const struct intel_watermark_params i855_wm_info = {
935 I855GM_FIFO_SIZE,
936 I915_MAX_WM,
937 1,
938 2,
939 I830_FIFO_LINE_SIZE
940};
941static const struct intel_watermark_params i830_wm_info = {
942 I830_FIFO_SIZE,
943 I915_MAX_WM,
944 1,
945 2,
946 I830_FIFO_LINE_SIZE
947};
948
949static const struct intel_watermark_params ironlake_display_wm_info = {
950 ILK_DISPLAY_FIFO,
951 ILK_DISPLAY_MAXWM,
952 ILK_DISPLAY_DFTWM,
953 2,
954 ILK_FIFO_LINE_SIZE
955};
956static const struct intel_watermark_params ironlake_cursor_wm_info = {
957 ILK_CURSOR_FIFO,
958 ILK_CURSOR_MAXWM,
959 ILK_CURSOR_DFTWM,
960 2,
961 ILK_FIFO_LINE_SIZE
962};
963static const struct intel_watermark_params ironlake_display_srwm_info = {
964 ILK_DISPLAY_SR_FIFO,
965 ILK_DISPLAY_MAX_SRWM,
966 ILK_DISPLAY_DFT_SRWM,
967 2,
968 ILK_FIFO_LINE_SIZE
969};
970static const struct intel_watermark_params ironlake_cursor_srwm_info = {
971 ILK_CURSOR_SR_FIFO,
972 ILK_CURSOR_MAX_SRWM,
973 ILK_CURSOR_DFT_SRWM,
974 2,
975 ILK_FIFO_LINE_SIZE
976};
977
978static const struct intel_watermark_params sandybridge_display_wm_info = {
979 SNB_DISPLAY_FIFO,
980 SNB_DISPLAY_MAXWM,
981 SNB_DISPLAY_DFTWM,
982 2,
983 SNB_FIFO_LINE_SIZE
984};
985static const struct intel_watermark_params sandybridge_cursor_wm_info = {
986 SNB_CURSOR_FIFO,
987 SNB_CURSOR_MAXWM,
988 SNB_CURSOR_DFTWM,
989 2,
990 SNB_FIFO_LINE_SIZE
991};
992static const struct intel_watermark_params sandybridge_display_srwm_info = {
993 SNB_DISPLAY_SR_FIFO,
994 SNB_DISPLAY_MAX_SRWM,
995 SNB_DISPLAY_DFT_SRWM,
996 2,
997 SNB_FIFO_LINE_SIZE
998};
999static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1000 SNB_CURSOR_SR_FIFO,
1001 SNB_CURSOR_MAX_SRWM,
1002 SNB_CURSOR_DFT_SRWM,
1003 2,
1004 SNB_FIFO_LINE_SIZE
1005};
1006
1007
1008/**
1009 * intel_calculate_wm - calculate watermark level
1010 * @clock_in_khz: pixel clock
1011 * @wm: chip FIFO params
1012 * @pixel_size: display pixel size
1013 * @latency_ns: memory latency for the platform
1014 *
1015 * Calculate the watermark level (the level at which the display plane will
1016 * start fetching from memory again). Each chip has a different display
1017 * FIFO size and allocation, so the caller needs to figure that out and pass
1018 * in the correct intel_watermark_params structure.
1019 *
1020 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1021 * on the pixel size. When it reaches the watermark level, it'll start
1022 * fetching FIFO line sized based chunks from memory until the FIFO fills
1023 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1024 * will occur, and a display engine hang could result.
1025 */
1026static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1027 const struct intel_watermark_params *wm,
1028 int fifo_size,
1029 int pixel_size,
1030 unsigned long latency_ns)
1031{
1032 long entries_required, wm_size;
1033
1034 /*
1035 * Note: we need to make sure we don't overflow for various clock &
1036 * latency values.
1037 * clocks go from a few thousand to several hundred thousand.
1038 * latency is usually a few thousand
1039 */
1040 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1041 1000;
1042 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1043
1044 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1045
1046 wm_size = fifo_size - (entries_required + wm->guard_size);
1047
1048 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1049
1050 /* Don't promote wm_size to unsigned... */
1051 if (wm_size > (long)wm->max_wm)
1052 wm_size = wm->max_wm;
1053 if (wm_size <= 0)
1054 wm_size = wm->default_wm;
1055 return wm_size;
1056}
1057
1058static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1059{
1060 struct drm_crtc *crtc, *enabled = NULL;
1061
1062 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1063 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1064 if (enabled)
1065 return NULL;
1066 enabled = crtc;
1067 }
1068 }
1069
1070 return enabled;
1071}
1072
1fa61106 1073static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1074{
1075 struct drm_i915_private *dev_priv = dev->dev_private;
1076 struct drm_crtc *crtc;
1077 const struct cxsr_latency *latency;
1078 u32 reg;
1079 unsigned long wm;
1080
1081 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1082 dev_priv->fsb_freq, dev_priv->mem_freq);
1083 if (!latency) {
1084 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1085 pineview_disable_cxsr(dev);
1086 return;
1087 }
1088
1089 crtc = single_enabled_crtc(dev);
1090 if (crtc) {
1091 int clock = crtc->mode.clock;
1092 int pixel_size = crtc->fb->bits_per_pixel / 8;
1093
1094 /* Display SR */
1095 wm = intel_calculate_wm(clock, &pineview_display_wm,
1096 pineview_display_wm.fifo_size,
1097 pixel_size, latency->display_sr);
1098 reg = I915_READ(DSPFW1);
1099 reg &= ~DSPFW_SR_MASK;
1100 reg |= wm << DSPFW_SR_SHIFT;
1101 I915_WRITE(DSPFW1, reg);
1102 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1103
1104 /* cursor SR */
1105 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1106 pineview_display_wm.fifo_size,
1107 pixel_size, latency->cursor_sr);
1108 reg = I915_READ(DSPFW3);
1109 reg &= ~DSPFW_CURSOR_SR_MASK;
1110 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1111 I915_WRITE(DSPFW3, reg);
1112
1113 /* Display HPLL off SR */
1114 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1115 pineview_display_hplloff_wm.fifo_size,
1116 pixel_size, latency->display_hpll_disable);
1117 reg = I915_READ(DSPFW3);
1118 reg &= ~DSPFW_HPLL_SR_MASK;
1119 reg |= wm & DSPFW_HPLL_SR_MASK;
1120 I915_WRITE(DSPFW3, reg);
1121
1122 /* cursor HPLL off SR */
1123 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1124 pineview_display_hplloff_wm.fifo_size,
1125 pixel_size, latency->cursor_hpll_disable);
1126 reg = I915_READ(DSPFW3);
1127 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1128 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1129 I915_WRITE(DSPFW3, reg);
1130 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1131
1132 /* activate cxsr */
1133 I915_WRITE(DSPFW3,
1134 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1135 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1136 } else {
1137 pineview_disable_cxsr(dev);
1138 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1139 }
1140}
1141
1142static bool g4x_compute_wm0(struct drm_device *dev,
1143 int plane,
1144 const struct intel_watermark_params *display,
1145 int display_latency_ns,
1146 const struct intel_watermark_params *cursor,
1147 int cursor_latency_ns,
1148 int *plane_wm,
1149 int *cursor_wm)
1150{
1151 struct drm_crtc *crtc;
1152 int htotal, hdisplay, clock, pixel_size;
1153 int line_time_us, line_count;
1154 int entries, tlb_miss;
1155
1156 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1157 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1158 *cursor_wm = cursor->guard_size;
1159 *plane_wm = display->guard_size;
1160 return false;
1161 }
1162
1163 htotal = crtc->mode.htotal;
1164 hdisplay = crtc->mode.hdisplay;
1165 clock = crtc->mode.clock;
1166 pixel_size = crtc->fb->bits_per_pixel / 8;
1167
1168 /* Use the small buffer method to calculate plane watermark */
1169 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1170 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1171 if (tlb_miss > 0)
1172 entries += tlb_miss;
1173 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1174 *plane_wm = entries + display->guard_size;
1175 if (*plane_wm > (int)display->max_wm)
1176 *plane_wm = display->max_wm;
1177
1178 /* Use the large buffer method to calculate cursor watermark */
1179 line_time_us = ((htotal * 1000) / clock);
1180 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1181 entries = line_count * 64 * pixel_size;
1182 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1183 if (tlb_miss > 0)
1184 entries += tlb_miss;
1185 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1186 *cursor_wm = entries + cursor->guard_size;
1187 if (*cursor_wm > (int)cursor->max_wm)
1188 *cursor_wm = (int)cursor->max_wm;
1189
1190 return true;
1191}
1192
1193/*
1194 * Check the wm result.
1195 *
1196 * If any calculated watermark values is larger than the maximum value that
1197 * can be programmed into the associated watermark register, that watermark
1198 * must be disabled.
1199 */
1200static bool g4x_check_srwm(struct drm_device *dev,
1201 int display_wm, int cursor_wm,
1202 const struct intel_watermark_params *display,
1203 const struct intel_watermark_params *cursor)
1204{
1205 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1206 display_wm, cursor_wm);
1207
1208 if (display_wm > display->max_wm) {
1209 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1210 display_wm, display->max_wm);
1211 return false;
1212 }
1213
1214 if (cursor_wm > cursor->max_wm) {
1215 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1216 cursor_wm, cursor->max_wm);
1217 return false;
1218 }
1219
1220 if (!(display_wm || cursor_wm)) {
1221 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1222 return false;
1223 }
1224
1225 return true;
1226}
1227
1228static bool g4x_compute_srwm(struct drm_device *dev,
1229 int plane,
1230 int latency_ns,
1231 const struct intel_watermark_params *display,
1232 const struct intel_watermark_params *cursor,
1233 int *display_wm, int *cursor_wm)
1234{
1235 struct drm_crtc *crtc;
1236 int hdisplay, htotal, pixel_size, clock;
1237 unsigned long line_time_us;
1238 int line_count, line_size;
1239 int small, large;
1240 int entries;
1241
1242 if (!latency_ns) {
1243 *display_wm = *cursor_wm = 0;
1244 return false;
1245 }
1246
1247 crtc = intel_get_crtc_for_plane(dev, plane);
1248 hdisplay = crtc->mode.hdisplay;
1249 htotal = crtc->mode.htotal;
1250 clock = crtc->mode.clock;
1251 pixel_size = crtc->fb->bits_per_pixel / 8;
1252
1253 line_time_us = (htotal * 1000) / clock;
1254 line_count = (latency_ns / line_time_us + 1000) / 1000;
1255 line_size = hdisplay * pixel_size;
1256
1257 /* Use the minimum of the small and large buffer method for primary */
1258 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1259 large = line_count * line_size;
1260
1261 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1262 *display_wm = entries + display->guard_size;
1263
1264 /* calculate the self-refresh watermark for display cursor */
1265 entries = line_count * pixel_size * 64;
1266 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1267 *cursor_wm = entries + cursor->guard_size;
1268
1269 return g4x_check_srwm(dev,
1270 *display_wm, *cursor_wm,
1271 display, cursor);
1272}
1273
1274static bool vlv_compute_drain_latency(struct drm_device *dev,
1275 int plane,
1276 int *plane_prec_mult,
1277 int *plane_dl,
1278 int *cursor_prec_mult,
1279 int *cursor_dl)
1280{
1281 struct drm_crtc *crtc;
1282 int clock, pixel_size;
1283 int entries;
1284
1285 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1286 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1287 return false;
1288
1289 clock = crtc->mode.clock; /* VESA DOT Clock */
1290 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1291
1292 entries = (clock / 1000) * pixel_size;
1293 *plane_prec_mult = (entries > 256) ?
1294 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1295 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1296 pixel_size);
1297
1298 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1299 *cursor_prec_mult = (entries > 256) ?
1300 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1301 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1302
1303 return true;
1304}
1305
1306/*
1307 * Update drain latency registers of memory arbiter
1308 *
1309 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1310 * to be programmed. Each plane has a drain latency multiplier and a drain
1311 * latency value.
1312 */
1313
1314static void vlv_update_drain_latency(struct drm_device *dev)
1315{
1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1318 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1319 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1320 either 16 or 32 */
1321
1322 /* For plane A, Cursor A */
1323 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1324 &cursor_prec_mult, &cursora_dl)) {
1325 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1326 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1327 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1328 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1329
1330 I915_WRITE(VLV_DDL1, cursora_prec |
1331 (cursora_dl << DDL_CURSORA_SHIFT) |
1332 planea_prec | planea_dl);
1333 }
1334
1335 /* For plane B, Cursor B */
1336 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1337 &cursor_prec_mult, &cursorb_dl)) {
1338 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1339 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1340 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1341 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1342
1343 I915_WRITE(VLV_DDL2, cursorb_prec |
1344 (cursorb_dl << DDL_CURSORB_SHIFT) |
1345 planeb_prec | planeb_dl);
1346 }
1347}
1348
1349#define single_plane_enabled(mask) is_power_of_2(mask)
1350
1fa61106 1351static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1352{
1353 static const int sr_latency_ns = 12000;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1356 int plane_sr, cursor_sr;
af6c4575 1357 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1358 unsigned int enabled = 0;
1359
1360 vlv_update_drain_latency(dev);
1361
51cea1f4 1362 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1363 &valleyview_wm_info, latency_ns,
1364 &valleyview_cursor_wm_info, latency_ns,
1365 &planea_wm, &cursora_wm))
51cea1f4 1366 enabled |= 1 << PIPE_A;
b445e3b0 1367
51cea1f4 1368 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1369 &valleyview_wm_info, latency_ns,
1370 &valleyview_cursor_wm_info, latency_ns,
1371 &planeb_wm, &cursorb_wm))
51cea1f4 1372 enabled |= 1 << PIPE_B;
b445e3b0 1373
b445e3b0
ED		 1374 if (single_plane_enabled(enabled) &&
1375 g4x_compute_srwm(dev, ffs(enabled) - 1,
1376 sr_latency_ns,
1377 &valleyview_wm_info,
1378 &valleyview_cursor_wm_info,
af6c4575
CW		 1379 &plane_sr, &ignore_cursor_sr) &&
1380 g4x_compute_srwm(dev, ffs(enabled) - 1,
1381 2*sr_latency_ns,
1382 &valleyview_wm_info,
1383 &valleyview_cursor_wm_info,
52bd02d8 1384 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1385 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1386 } else {
b445e3b0
ED		 1387 I915_WRITE(FW_BLC_SELF_VLV,
1388 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1389 plane_sr = cursor_sr = 0;
1390 }
b445e3b0
ED		 1391
1392 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393 planea_wm, cursora_wm,
1394 planeb_wm, cursorb_wm,
1395 plane_sr, cursor_sr);
1396
1397 I915_WRITE(DSPFW1,
1398 (plane_sr << DSPFW_SR_SHIFT) |
1399 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1400 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1401 planea_wm);
1402 I915_WRITE(DSPFW2,
8c919b28 1403 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1404 (cursora_wm << DSPFW_CURSORA_SHIFT));
1405 I915_WRITE(DSPFW3,
8c919b28
CW		 1406 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1407 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1408}
1409
1fa61106 1410static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1411{
1412 static const int sr_latency_ns = 12000;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1415 int plane_sr, cursor_sr;
1416 unsigned int enabled = 0;
1417
51cea1f4 1418 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1419 &g4x_wm_info, latency_ns,
1420 &g4x_cursor_wm_info, latency_ns,
1421 &planea_wm, &cursora_wm))
51cea1f4 1422 enabled |= 1 << PIPE_A;
b445e3b0 1423
51cea1f4 1424 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1425 &g4x_wm_info, latency_ns,
1426 &g4x_cursor_wm_info, latency_ns,
1427 &planeb_wm, &cursorb_wm))
51cea1f4 1428 enabled |= 1 << PIPE_B;
b445e3b0 1429
b445e3b0
ED		 1430 if (single_plane_enabled(enabled) &&
1431 g4x_compute_srwm(dev, ffs(enabled) - 1,
1432 sr_latency_ns,
1433 &g4x_wm_info,
1434 &g4x_cursor_wm_info,
52bd02d8 1435 &plane_sr, &cursor_sr)) {
b445e3b0 1436 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1437 } else {
b445e3b0
ED		 1438 I915_WRITE(FW_BLC_SELF,
1439 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1440 plane_sr = cursor_sr = 0;
1441 }
b445e3b0
ED		 1442
1443 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1444 planea_wm, cursora_wm,
1445 planeb_wm, cursorb_wm,
1446 plane_sr, cursor_sr);
1447
1448 I915_WRITE(DSPFW1,
1449 (plane_sr << DSPFW_SR_SHIFT) |
1450 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1451 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1452 planea_wm);
1453 I915_WRITE(DSPFW2,
8c919b28 1454 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1455 (cursora_wm << DSPFW_CURSORA_SHIFT));
1456 /* HPLL off in SR has some issues on G4x... disable it */
1457 I915_WRITE(DSPFW3,
8c919b28 1458 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1459 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1460}
1461
1fa61106 1462static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1463{
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 struct drm_crtc *crtc;
1466 int srwm = 1;
1467 int cursor_sr = 16;
1468
1469 /* Calc sr entries for one plane configs */
1470 crtc = single_enabled_crtc(dev);
1471 if (crtc) {
1472 /* self-refresh has much higher latency */
1473 static const int sr_latency_ns = 12000;
1474 int clock = crtc->mode.clock;
1475 int htotal = crtc->mode.htotal;
1476 int hdisplay = crtc->mode.hdisplay;
1477 int pixel_size = crtc->fb->bits_per_pixel / 8;
1478 unsigned long line_time_us;
1479 int entries;
1480
1481 line_time_us = ((htotal * 1000) / clock);
1482
1483 /* Use ns/us then divide to preserve precision */
1484 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1485 pixel_size * hdisplay;
1486 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1487 srwm = I965_FIFO_SIZE - entries;
1488 if (srwm < 0)
1489 srwm = 1;
1490 srwm &= 0x1ff;
1491 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1492 entries, srwm);
1493
1494 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1495 pixel_size * 64;
1496 entries = DIV_ROUND_UP(entries,
1497 i965_cursor_wm_info.cacheline_size);
1498 cursor_sr = i965_cursor_wm_info.fifo_size -
1499 (entries + i965_cursor_wm_info.guard_size);
1500
1501 if (cursor_sr > i965_cursor_wm_info.max_wm)
1502 cursor_sr = i965_cursor_wm_info.max_wm;
1503
1504 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1505 "cursor %d\n", srwm, cursor_sr);
1506
1507 if (IS_CRESTLINE(dev))
1508 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1509 } else {
1510 /* Turn off self refresh if both pipes are enabled */
1511 if (IS_CRESTLINE(dev))
1512 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1513 & ~FW_BLC_SELF_EN);
1514 }
1515
1516 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1517 srwm);
1518
1519 /* 965 has limitations... */
1520 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1521 (8 << 16) | (8 << 8) | (8 << 0));
1522 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1523 /* update cursor SR watermark */
1524 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1525}
1526
1fa61106 1527static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1528{
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 const struct intel_watermark_params *wm_info;
1531 uint32_t fwater_lo;
1532 uint32_t fwater_hi;
1533 int cwm, srwm = 1;
1534 int fifo_size;
1535 int planea_wm, planeb_wm;
1536 struct drm_crtc *crtc, *enabled = NULL;
1537
1538 if (IS_I945GM(dev))
1539 wm_info = &i945_wm_info;
1540 else if (!IS_GEN2(dev))
1541 wm_info = &i915_wm_info;
1542 else
1543 wm_info = &i855_wm_info;
1544
1545 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1546 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1547 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1548 int cpp = crtc->fb->bits_per_pixel / 8;
1549 if (IS_GEN2(dev))
1550 cpp = 4;
1551
b445e3b0 1552 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1553 wm_info, fifo_size, cpp,
b445e3b0
ED		 1554 latency_ns);
1555 enabled = crtc;
1556 } else
1557 planea_wm = fifo_size - wm_info->guard_size;
1558
1559 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1560 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1561 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1562 int cpp = crtc->fb->bits_per_pixel / 8;
1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
b445e3b0 1566 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1567 wm_info, fifo_size, cpp,
b445e3b0
ED		 1568 latency_ns);
1569 if (enabled == NULL)
1570 enabled = crtc;
1571 else
1572 enabled = NULL;
1573 } else
1574 planeb_wm = fifo_size - wm_info->guard_size;
1575
1576 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1577
1578 /*
1579 * Overlay gets an aggressive default since video jitter is bad.
1580 */
1581 cwm = 2;
1582
1583 /* Play safe and disable self-refresh before adjusting watermarks. */
1584 if (IS_I945G(dev) || IS_I945GM(dev))
1585 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1586 else if (IS_I915GM(dev))
1587 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1588
1589 /* Calc sr entries for one plane configs */
1590 if (HAS_FW_BLC(dev) && enabled) {
1591 /* self-refresh has much higher latency */
1592 static const int sr_latency_ns = 6000;
1593 int clock = enabled->mode.clock;
1594 int htotal = enabled->mode.htotal;
1595 int hdisplay = enabled->mode.hdisplay;
1596 int pixel_size = enabled->fb->bits_per_pixel / 8;
1597 unsigned long line_time_us;
1598 int entries;
1599
1600 line_time_us = (htotal * 1000) / clock;
1601
1602 /* Use ns/us then divide to preserve precision */
1603 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1604 pixel_size * hdisplay;
1605 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1606 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1607 srwm = wm_info->fifo_size - entries;
1608 if (srwm < 0)
1609 srwm = 1;
1610
1611 if (IS_I945G(dev) || IS_I945GM(dev))
1612 I915_WRITE(FW_BLC_SELF,
1613 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1614 else if (IS_I915GM(dev))
1615 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1616 }
1617
1618 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1619 planea_wm, planeb_wm, cwm, srwm);
1620
1621 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1622 fwater_hi = (cwm & 0x1f);
1623
1624 /* Set request length to 8 cachelines per fetch */
1625 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1626 fwater_hi = fwater_hi | (1 << 8);
1627
1628 I915_WRITE(FW_BLC, fwater_lo);
1629 I915_WRITE(FW_BLC2, fwater_hi);
1630
1631 if (HAS_FW_BLC(dev)) {
1632 if (enabled) {
1633 if (IS_I945G(dev) || IS_I945GM(dev))
1634 I915_WRITE(FW_BLC_SELF,
1635 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1636 else if (IS_I915GM(dev))
1637 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1638 DRM_DEBUG_KMS("memory self refresh enabled\n");
1639 } else
1640 DRM_DEBUG_KMS("memory self refresh disabled\n");
1641 }
1642}
1643
1fa61106 1644static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1645{
1646 struct drm_i915_private *dev_priv = dev->dev_private;
1647 struct drm_crtc *crtc;
1648 uint32_t fwater_lo;
1649 int planea_wm;
1650
1651 crtc = single_enabled_crtc(dev);
1652 if (crtc == NULL)
1653 return;
1654
1655 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1656 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1657 4, latency_ns);
b445e3b0
ED		 1658 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1659 fwater_lo |= (3<<8) | planea_wm;
1660
1661 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1662
1663 I915_WRITE(FW_BLC, fwater_lo);
1664}
1665
1666#define ILK_LP0_PLANE_LATENCY 700
1667#define ILK_LP0_CURSOR_LATENCY 1300
1668
1669/*
1670 * Check the wm result.
1671 *
1672 * If any calculated watermark values is larger than the maximum value that
1673 * can be programmed into the associated watermark register, that watermark
1674 * must be disabled.
1675 */
1676static bool ironlake_check_srwm(struct drm_device *dev, int level,
1677 int fbc_wm, int display_wm, int cursor_wm,
1678 const struct intel_watermark_params *display,
1679 const struct intel_watermark_params *cursor)
1680{
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682
1683 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1684 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1685
1686 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1687 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1688 fbc_wm, SNB_FBC_MAX_SRWM, level);
1689
1690 /* fbc has it's own way to disable FBC WM */
1691 I915_WRITE(DISP_ARB_CTL,
1692 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1693 return false;
615aaa5f
VS		 1694 } else if (INTEL_INFO(dev)->gen >= 6) {
1695 /* enable FBC WM (except on ILK, where it must remain off) */
1696 I915_WRITE(DISP_ARB_CTL,
1697 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1698 }
1699
1700 if (display_wm > display->max_wm) {
1701 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1702 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1703 return false;
1704 }
1705
1706 if (cursor_wm > cursor->max_wm) {
1707 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1708 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1709 return false;
1710 }
1711
1712 if (!(fbc_wm || display_wm || cursor_wm)) {
1713 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1714 return false;
1715 }
1716
1717 return true;
1718}
1719
1720/*
1721 * Compute watermark values of WM[1-3],
1722 */
1723static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1724 int latency_ns,
1725 const struct intel_watermark_params *display,
1726 const struct intel_watermark_params *cursor,
1727 int *fbc_wm, int *display_wm, int *cursor_wm)
1728{
1729 struct drm_crtc *crtc;
1730 unsigned long line_time_us;
1731 int hdisplay, htotal, pixel_size, clock;
1732 int line_count, line_size;
1733 int small, large;
1734 int entries;
1735
1736 if (!latency_ns) {
1737 *fbc_wm = *display_wm = *cursor_wm = 0;
1738 return false;
1739 }
1740
1741 crtc = intel_get_crtc_for_plane(dev, plane);
1742 hdisplay = crtc->mode.hdisplay;
1743 htotal = crtc->mode.htotal;
1744 clock = crtc->mode.clock;
1745 pixel_size = crtc->fb->bits_per_pixel / 8;
1746
1747 line_time_us = (htotal * 1000) / clock;
1748 line_count = (latency_ns / line_time_us + 1000) / 1000;
1749 line_size = hdisplay * pixel_size;
1750
1751 /* Use the minimum of the small and large buffer method for primary */
1752 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1753 large = line_count * line_size;
1754
1755 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1756 *display_wm = entries + display->guard_size;
1757
1758 /*
1759 * Spec says:
1760 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1761 */
1762 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1763
1764 /* calculate the self-refresh watermark for display cursor */
1765 entries = line_count * pixel_size * 64;
1766 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1767 *cursor_wm = entries + cursor->guard_size;
1768
1769 return ironlake_check_srwm(dev, level,
1770 *fbc_wm, *display_wm, *cursor_wm,
1771 display, cursor);
1772}
1773
1fa61106 1774static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1775{
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 int fbc_wm, plane_wm, cursor_wm;
1778 unsigned int enabled;
1779
1780 enabled = 0;
51cea1f4 1781 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1782 &ironlake_display_wm_info,
1783 ILK_LP0_PLANE_LATENCY,
1784 &ironlake_cursor_wm_info,
1785 ILK_LP0_CURSOR_LATENCY,
1786 &plane_wm, &cursor_wm)) {
1787 I915_WRITE(WM0_PIPEA_ILK,
1788 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1789 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1790 " plane %d, " "cursor: %d\n",
1791 plane_wm, cursor_wm);
51cea1f4 1792 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1793 }
1794
51cea1f4 1795 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1796 &ironlake_display_wm_info,
1797 ILK_LP0_PLANE_LATENCY,
1798 &ironlake_cursor_wm_info,
1799 ILK_LP0_CURSOR_LATENCY,
1800 &plane_wm, &cursor_wm)) {
1801 I915_WRITE(WM0_PIPEB_ILK,
1802 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1803 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1804 " plane %d, cursor: %d\n",
1805 plane_wm, cursor_wm);
51cea1f4 1806 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1807 }
1808
1809 /*
1810 * Calculate and update the self-refresh watermark only when one
1811 * display plane is used.
1812 */
1813 I915_WRITE(WM3_LP_ILK, 0);
1814 I915_WRITE(WM2_LP_ILK, 0);
1815 I915_WRITE(WM1_LP_ILK, 0);
1816
1817 if (!single_plane_enabled(enabled))
1818 return;
1819 enabled = ffs(enabled) - 1;
1820
1821 /* WM1 */
1822 if (!ironlake_compute_srwm(dev, 1, enabled,
1823 ILK_READ_WM1_LATENCY() * 500,
1824 &ironlake_display_srwm_info,
1825 &ironlake_cursor_srwm_info,
1826 &fbc_wm, &plane_wm, &cursor_wm))
1827 return;
1828
1829 I915_WRITE(WM1_LP_ILK,
1830 WM1_LP_SR_EN |
1831 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1832 (fbc_wm << WM1_LP_FBC_SHIFT) |
1833 (plane_wm << WM1_LP_SR_SHIFT) |
1834 cursor_wm);
1835
1836 /* WM2 */
1837 if (!ironlake_compute_srwm(dev, 2, enabled,
1838 ILK_READ_WM2_LATENCY() * 500,
1839 &ironlake_display_srwm_info,
1840 &ironlake_cursor_srwm_info,
1841 &fbc_wm, &plane_wm, &cursor_wm))
1842 return;
1843
1844 I915_WRITE(WM2_LP_ILK,
1845 WM2_LP_EN |
1846 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1847 (fbc_wm << WM1_LP_FBC_SHIFT) |
1848 (plane_wm << WM1_LP_SR_SHIFT) |
1849 cursor_wm);
1850
1851 /*
1852 * WM3 is unsupported on ILK, probably because we don't have latency
1853 * data for that power state
1854 */
1855}
1856
1fa61106 1857static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1858{
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1861 u32 val;
1862 int fbc_wm, plane_wm, cursor_wm;
1863 unsigned int enabled;
1864
1865 enabled = 0;
51cea1f4 1866 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1867 &sandybridge_display_wm_info, latency,
1868 &sandybridge_cursor_wm_info, latency,
1869 &plane_wm, &cursor_wm)) {
1870 val = I915_READ(WM0_PIPEA_ILK);
1871 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1872 I915_WRITE(WM0_PIPEA_ILK, val |
1873 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1874 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1875 " plane %d, " "cursor: %d\n",
1876 plane_wm, cursor_wm);
51cea1f4 1877 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1878 }
1879
51cea1f4 1880 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1881 &sandybridge_display_wm_info, latency,
1882 &sandybridge_cursor_wm_info, latency,
1883 &plane_wm, &cursor_wm)) {
1884 val = I915_READ(WM0_PIPEB_ILK);
1885 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1886 I915_WRITE(WM0_PIPEB_ILK, val |
1887 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1888 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1889 " plane %d, cursor: %d\n",
1890 plane_wm, cursor_wm);
51cea1f4 1891 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1892 }
1893
c43d0188
CW		 1894 /*
1895 * Calculate and update the self-refresh watermark only when one
1896 * display plane is used.
1897 *
1898 * SNB support 3 levels of watermark.
1899 *
1900 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1901 * and disabled in the descending order
1902 *
1903 */
1904 I915_WRITE(WM3_LP_ILK, 0);
1905 I915_WRITE(WM2_LP_ILK, 0);
1906 I915_WRITE(WM1_LP_ILK, 0);
1907
1908 if (!single_plane_enabled(enabled) ||
1909 dev_priv->sprite_scaling_enabled)
1910 return;
1911 enabled = ffs(enabled) - 1;
1912
1913 /* WM1 */
1914 if (!ironlake_compute_srwm(dev, 1, enabled,
1915 SNB_READ_WM1_LATENCY() * 500,
1916 &sandybridge_display_srwm_info,
1917 &sandybridge_cursor_srwm_info,
1918 &fbc_wm, &plane_wm, &cursor_wm))
1919 return;
1920
1921 I915_WRITE(WM1_LP_ILK,
1922 WM1_LP_SR_EN |
1923 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1924 (fbc_wm << WM1_LP_FBC_SHIFT) |
1925 (plane_wm << WM1_LP_SR_SHIFT) |
1926 cursor_wm);
1927
1928 /* WM2 */
1929 if (!ironlake_compute_srwm(dev, 2, enabled,
1930 SNB_READ_WM2_LATENCY() * 500,
1931 &sandybridge_display_srwm_info,
1932 &sandybridge_cursor_srwm_info,
1933 &fbc_wm, &plane_wm, &cursor_wm))
1934 return;
1935
1936 I915_WRITE(WM2_LP_ILK,
1937 WM2_LP_EN |
1938 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1939 (fbc_wm << WM1_LP_FBC_SHIFT) |
1940 (plane_wm << WM1_LP_SR_SHIFT) |
1941 cursor_wm);
1942
1943 /* WM3 */
1944 if (!ironlake_compute_srwm(dev, 3, enabled,
1945 SNB_READ_WM3_LATENCY() * 500,
1946 &sandybridge_display_srwm_info,
1947 &sandybridge_cursor_srwm_info,
1948 &fbc_wm, &plane_wm, &cursor_wm))
1949 return;
1950
1951 I915_WRITE(WM3_LP_ILK,
1952 WM3_LP_EN |
1953 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1954 (fbc_wm << WM1_LP_FBC_SHIFT) |
1955 (plane_wm << WM1_LP_SR_SHIFT) |
1956 cursor_wm);
1957}
1958
1959static void ivybridge_update_wm(struct drm_device *dev)
1960{
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1963 u32 val;
1964 int fbc_wm, plane_wm, cursor_wm;
1965 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1966 unsigned int enabled;
1967
1968 enabled = 0;
51cea1f4 1969 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1970 &sandybridge_display_wm_info, latency,
1971 &sandybridge_cursor_wm_info, latency,
1972 &plane_wm, &cursor_wm)) {
1973 val = I915_READ(WM0_PIPEA_ILK);
1974 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1975 I915_WRITE(WM0_PIPEA_ILK, val |
1976 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1977 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1978 " plane %d, " "cursor: %d\n",
1979 plane_wm, cursor_wm);
51cea1f4 1980 enabled |= 1 << PIPE_A;
c43d0188
CW		 1981 }
1982
51cea1f4 1983 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 1984 &sandybridge_display_wm_info, latency,
1985 &sandybridge_cursor_wm_info, latency,
1986 &plane_wm, &cursor_wm)) {
1987 val = I915_READ(WM0_PIPEB_ILK);
1988 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1989 I915_WRITE(WM0_PIPEB_ILK, val |
1990 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1991 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1992 " plane %d, cursor: %d\n",
1993 plane_wm, cursor_wm);
51cea1f4 1994 enabled |= 1 << PIPE_B;
c43d0188
CW		 1995 }
1996
51cea1f4 1997 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 1998 &sandybridge_display_wm_info, latency,
1999 &sandybridge_cursor_wm_info, latency,
2000 &plane_wm, &cursor_wm)) {
2001 val = I915_READ(WM0_PIPEC_IVB);
2002 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2003 I915_WRITE(WM0_PIPEC_IVB, val |
2004 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2005 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2006 " plane %d, cursor: %d\n",
2007 plane_wm, cursor_wm);
51cea1f4 2008 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2009 }
2010
2011 /*
2012 * Calculate and update the self-refresh watermark only when one
2013 * display plane is used.
2014 *
2015 * SNB support 3 levels of watermark.
2016 *
2017 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2018 * and disabled in the descending order
2019 *
2020 */
2021 I915_WRITE(WM3_LP_ILK, 0);
2022 I915_WRITE(WM2_LP_ILK, 0);
2023 I915_WRITE(WM1_LP_ILK, 0);
2024
2025 if (!single_plane_enabled(enabled) ||
2026 dev_priv->sprite_scaling_enabled)
2027 return;
2028 enabled = ffs(enabled) - 1;
2029
2030 /* WM1 */
2031 if (!ironlake_compute_srwm(dev, 1, enabled,
2032 SNB_READ_WM1_LATENCY() * 500,
2033 &sandybridge_display_srwm_info,
2034 &sandybridge_cursor_srwm_info,
2035 &fbc_wm, &plane_wm, &cursor_wm))
2036 return;
2037
2038 I915_WRITE(WM1_LP_ILK,
2039 WM1_LP_SR_EN |
2040 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2041 (fbc_wm << WM1_LP_FBC_SHIFT) |
2042 (plane_wm << WM1_LP_SR_SHIFT) |
2043 cursor_wm);
2044
2045 /* WM2 */
2046 if (!ironlake_compute_srwm(dev, 2, enabled,
2047 SNB_READ_WM2_LATENCY() * 500,
2048 &sandybridge_display_srwm_info,
2049 &sandybridge_cursor_srwm_info,
2050 &fbc_wm, &plane_wm, &cursor_wm))
2051 return;
2052
2053 I915_WRITE(WM2_LP_ILK,
2054 WM2_LP_EN |
2055 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2056 (fbc_wm << WM1_LP_FBC_SHIFT) |
2057 (plane_wm << WM1_LP_SR_SHIFT) |
2058 cursor_wm);
2059
c43d0188 2060 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2061 if (!ironlake_compute_srwm(dev, 3, enabled,
2062 SNB_READ_WM3_LATENCY() * 500,
2063 &sandybridge_display_srwm_info,
2064 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2065 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2066 !ironlake_compute_srwm(dev, 3, enabled,
2067 2 * SNB_READ_WM3_LATENCY() * 500,
2068 &sandybridge_display_srwm_info,
2069 &sandybridge_cursor_srwm_info,
2070 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2071 return;
2072
2073 I915_WRITE(WM3_LP_ILK,
2074 WM3_LP_EN |
2075 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2076 (fbc_wm << WM1_LP_FBC_SHIFT) |
2077 (plane_wm << WM1_LP_SR_SHIFT) |
2078 cursor_wm);
2079}
2080
801bcfff
PZ		 2081static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2082 struct drm_crtc *crtc)
2083{
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 uint32_t pixel_rate, pfit_size;
2086
ff9a6750 2087 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2088
2089 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2090 * adjust the pixel_rate here. */
2091
2092 pfit_size = intel_crtc->config.pch_pfit.size;
2093 if (pfit_size) {
2094 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2095
2096 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2097 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2098 pfit_w = (pfit_size >> 16) & 0xFFFF;
2099 pfit_h = pfit_size & 0xFFFF;
2100 if (pipe_w < pfit_w)
2101 pipe_w = pfit_w;
2102 if (pipe_h < pfit_h)
2103 pipe_h = pfit_h;
2104
2105 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2106 pfit_w * pfit_h);
2107 }
2108
2109 return pixel_rate;
2110}
2111
2112static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2113 uint32_t latency)
2114{
2115 uint64_t ret;
2116
2117 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2118 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2119
2120 return ret;
2121}
2122
2123static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2124 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2125 uint32_t latency)
2126{
2127 uint32_t ret;
2128
2129 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2130 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2131 ret = DIV_ROUND_UP(ret, 64) + 2;
2132 return ret;
2133}
2134
cca32e9a
PZ		 2135static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2136 uint8_t bytes_per_pixel)
2137{
2138 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2139}
2140
801bcfff
PZ		 2141struct hsw_pipe_wm_parameters {
2142 bool active;
2143 bool sprite_enabled;
2144 uint8_t pri_bytes_per_pixel;
2145 uint8_t spr_bytes_per_pixel;
2146 uint8_t cur_bytes_per_pixel;
2147 uint32_t pri_horiz_pixels;
2148 uint32_t spr_horiz_pixels;
2149 uint32_t cur_horiz_pixels;
2150 uint32_t pipe_htotal;
2151 uint32_t pixel_rate;
2152};
2153
cca32e9a
PZ		 2154struct hsw_wm_maximums {
2155 uint16_t pri;
2156 uint16_t spr;
2157 uint16_t cur;
2158 uint16_t fbc;
2159};
2160
2161struct hsw_lp_wm_result {
2162 bool enable;
2163 bool fbc_enable;
2164 uint32_t pri_val;
2165 uint32_t spr_val;
2166 uint32_t cur_val;
2167 uint32_t fbc_val;
2168};
2169
801bcfff
PZ		 2170struct hsw_wm_values {
2171 uint32_t wm_pipe[3];
2172 uint32_t wm_lp[3];
2173 uint32_t wm_lp_spr[3];
2174 uint32_t wm_linetime[3];
cca32e9a 2175 bool enable_fbc_wm;
801bcfff
PZ		 2176};
2177
2178enum hsw_data_buf_partitioning {
2179 HSW_DATA_BUF_PART_1_2,
2180 HSW_DATA_BUF_PART_5_6,
2181};
2182
cca32e9a
PZ		 2183/* For both WM_PIPE and WM_LP. */
2184static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2185 uint32_t mem_value,
2186 bool is_lp)
801bcfff 2187{
cca32e9a
PZ		 2188 uint32_t method1, method2;
2189
801bcfff
PZ		 2190 /* TODO: for now, assume the primary plane is always enabled. */
2191 if (!params->active)
2192 return 0;
2193
cca32e9a
PZ		 2194 method1 = hsw_wm_method1(params->pixel_rate,
2195 params->pri_bytes_per_pixel,
2196 mem_value);
2197
2198 if (!is_lp)
2199 return method1;
2200
2201 method2 = hsw_wm_method2(params->pixel_rate,
2202 params->pipe_htotal,
2203 params->pri_horiz_pixels,
2204 params->pri_bytes_per_pixel,
2205 mem_value);
2206
2207 return min(method1, method2);
801bcfff
PZ		 2208}
2209
2210/* For both WM_PIPE and WM_LP. */
2211static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2212 uint32_t mem_value)
2213{
2214 uint32_t method1, method2;
2215
2216 if (!params->active || !params->sprite_enabled)
2217 return 0;
2218
2219 method1 = hsw_wm_method1(params->pixel_rate,
2220 params->spr_bytes_per_pixel,
2221 mem_value);
2222 method2 = hsw_wm_method2(params->pixel_rate,
2223 params->pipe_htotal,
2224 params->spr_horiz_pixels,
2225 params->spr_bytes_per_pixel,
2226 mem_value);
2227 return min(method1, method2);
2228}
2229
2230/* For both WM_PIPE and WM_LP. */
2231static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2232 uint32_t mem_value)
2233{
2234 if (!params->active)
2235 return 0;
2236
2237 return hsw_wm_method2(params->pixel_rate,
2238 params->pipe_htotal,
2239 params->cur_horiz_pixels,
2240 params->cur_bytes_per_pixel,
2241 mem_value);
2242}
2243
cca32e9a
PZ		 2244/* Only for WM_LP. */
2245static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2246 uint32_t pri_val,
2247 uint32_t mem_value)
2248{
2249 if (!params->active)
2250 return 0;
2251
2252 return hsw_wm_fbc(pri_val,
2253 params->pri_horiz_pixels,
2254 params->pri_bytes_per_pixel);
2255}
2256
2257static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
2258 struct hsw_pipe_wm_parameters *params,
2259 struct hsw_lp_wm_result *result)
2260{
2261 enum pipe pipe;
2262 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2263
2264 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2265 struct hsw_pipe_wm_parameters *p = &params[pipe];
2266
2267 pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
2268 spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
2269 cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
2270 fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
2271 }
2272
2273 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2274 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2275 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2276 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2277
2278 if (result->fbc_val > max->fbc) {
2279 result->fbc_enable = false;
2280 result->fbc_val = 0;
2281 } else {
2282 result->fbc_enable = true;
2283 }
2284
2285 result->enable = result->pri_val <= max->pri &&
2286 result->spr_val <= max->spr &&
2287 result->cur_val <= max->cur;
2288 return result->enable;
2289}
2290
801bcfff
PZ		 2291static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2292 uint32_t mem_value, enum pipe pipe,
2293 struct hsw_pipe_wm_parameters *params)
2294{
2295 uint32_t pri_val, cur_val, spr_val;
2296
cca32e9a 2297 pri_val = hsw_compute_pri_wm(params, mem_value, false);
801bcfff
PZ		 2298 spr_val = hsw_compute_spr_wm(params, mem_value);
2299 cur_val = hsw_compute_cur_wm(params, mem_value);
2300
2301 WARN(pri_val > 127,
2302 "Primary WM error, mode not supported for pipe %c\n",
2303 pipe_name(pipe));
2304 WARN(spr_val > 127,
2305 "Sprite WM error, mode not supported for pipe %c\n",
2306 pipe_name(pipe));
2307 WARN(cur_val > 63,
2308 "Cursor WM error, mode not supported for pipe %c\n",
2309 pipe_name(pipe));
2310
2311 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2312 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2313 cur_val;
2314}
2315
2316static uint32_t
2317hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2318{
2319 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2321 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2322 u32 linetime, ips_linetime;
1f8eeabf 2323
801bcfff
PZ		 2324 if (!intel_crtc_active(crtc))
2325 return 0;
1011d8c4 2326
1f8eeabf
ED		 2327 /* The WM are computed with base on how long it takes to fill a single
2328 * row at the given clock rate, multiplied by 8.
2329 * */
85a02deb
PZ		 2330 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2331 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2332 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2333
801bcfff
PZ		 2334 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2335 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2336}
2337
801bcfff
PZ		 2338static void hsw_compute_wm_parameters(struct drm_device *dev,
2339 struct hsw_pipe_wm_parameters *params,
cca32e9a 2340 uint32_t *wm,
861f3389
PZ		 2341 struct hsw_wm_maximums *lp_max_1_2,
2342 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4
PZ		 2343{
2344 struct drm_i915_private *dev_priv = dev->dev_private;
2345 struct drm_crtc *crtc;
801bcfff
PZ		 2346 struct drm_plane *plane;
2347 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1011d8c4 2348 enum pipe pipe;
cca32e9a 2349 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2350
801bcfff
PZ		 2351 if ((sskpd >> 56) & 0xFF)
2352 wm[0] = (sskpd >> 56) & 0xFF;
2353 else
2354 wm[0] = sskpd & 0xF;
2355 wm[1] = ((sskpd >> 4) & 0xFF) * 5;
2356 wm[2] = ((sskpd >> 12) & 0xFF) * 5;
2357 wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
2358 wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
2359
2360 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2362 struct hsw_pipe_wm_parameters *p;
2363
2364 pipe = intel_crtc->pipe;
2365 p = &params[pipe];
2366
2367 p->active = intel_crtc_active(crtc);
2368 if (!p->active)
2369 continue;
2370
cca32e9a
PZ		 2371 pipes_active++;
2372
801bcfff
PZ		 2373 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2374 p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2375 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2376 p->cur_bytes_per_pixel = 4;
2377 p->pri_horiz_pixels =
2378 intel_crtc->config.requested_mode.hdisplay;
2379 p->cur_horiz_pixels = 64;
2380 }
2381
2382 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2383 struct intel_plane *intel_plane = to_intel_plane(plane);
2384 struct hsw_pipe_wm_parameters *p;
2385
2386 pipe = intel_plane->pipe;
2387 p = &params[pipe];
2388
2389 p->sprite_enabled = intel_plane->wm.enable;
2390 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2391 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2392
2393 if (p->sprite_enabled)
2394 sprites_enabled++;
2395 }
2396
2397 if (pipes_active > 1) {
861f3389
PZ		 2398 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2399 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2400 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2401 } else {
2402 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2403 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2404 lp_max_1_2->spr = 384;
861f3389
PZ		 2405 lp_max_5_6->spr = 640;
2406 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2407 }
861f3389 2408 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2409}
2410
2411static void hsw_compute_wm_results(struct drm_device *dev,
2412 struct hsw_pipe_wm_parameters *params,
2413 uint32_t *wm,
cca32e9a 2414 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2415 struct hsw_wm_values *results)
2416{
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct drm_crtc *crtc;
cca32e9a 2419 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2420 enum pipe pipe;
cca32e9a
PZ		 2421 int level, max_level, wm_lp;
2422
2423 for (level = 1; level <= 4; level++)
2424 if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
2425 &lp_results[level - 1]))
2426 break;
2427 max_level = level - 1;
2428
2429 /* The spec says it is preferred to disable FBC WMs instead of disabling
2430 * a WM level. */
2431 results->enable_fbc_wm = true;
2432 for (level = 1; level <= max_level; level++) {
2433 if (!lp_results[level - 1].fbc_enable) {
2434 results->enable_fbc_wm = false;
2435 break;
2436 }
2437 }
2438
2439 memset(results, 0, sizeof(*results));
2440 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2441 const struct hsw_lp_wm_result *r;
801bcfff 2442
cca32e9a
PZ		 2443 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2444 if (level > max_level)
2445 break;
2446
2447 r = &lp_results[level - 1];
2448 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2449 r->fbc_val,
2450 r->pri_val,
2451 r->cur_val);
2452 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2453 }
801bcfff
PZ		 2454
2455 for_each_pipe(pipe)
2456 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2457 pipe,
2458 &params[pipe]);
1011d8c4
PZ		 2459
2460 for_each_pipe(pipe) {
2461 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2462 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2463 }
2464}
2465
861f3389
PZ		 2466/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2467 * case both are at the same level. Prefer r1 in case they're the same. */
2468struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2469 struct hsw_wm_values *r2)
2470{
2471 int i, val_r1 = 0, val_r2 = 0;
2472
2473 for (i = 0; i < 3; i++) {
2474 if (r1->wm_lp[i] & WM3_LP_EN)
2475 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2476 if (r2->wm_lp[i] & WM3_LP_EN)
2477 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2478 }
2479
2480 if (val_r1 == val_r2) {
2481 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2482 return r2;
2483 else
2484 return r1;
2485 } else if (val_r1 > val_r2) {
2486 return r1;
2487 } else {
2488 return r2;
2489 }
2490}
2491
801bcfff
PZ		 2492/*
2493 * The spec says we shouldn't write when we don't need, because every write
2494 * causes WMs to be re-evaluated, expending some power.
2495 */
2496static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2497 struct hsw_wm_values *results,
2498 enum hsw_data_buf_partitioning partitioning)
2499{
2500 struct hsw_wm_values previous;
2501 uint32_t val;
2502 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2503 bool prev_enable_fbc_wm;
801bcfff
PZ		 2504
2505 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2506 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2507 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2508 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2509 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2510 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2511 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2512 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2513 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2514 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2515 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2516 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2517
2518 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2519 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2520
cca32e9a
PZ		 2521 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2522
801bcfff
PZ		 2523 if (memcmp(results->wm_pipe, previous.wm_pipe,
2524 sizeof(results->wm_pipe)) == 0 &&
2525 memcmp(results->wm_lp, previous.wm_lp,
2526 sizeof(results->wm_lp)) == 0 &&
2527 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2528 sizeof(results->wm_lp_spr)) == 0 &&
2529 memcmp(results->wm_linetime, previous.wm_linetime,
2530 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2531 partitioning == prev_partitioning &&
2532 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2533 return;
2534
2535 if (previous.wm_lp[2] != 0)
2536 I915_WRITE(WM3_LP_ILK, 0);
2537 if (previous.wm_lp[1] != 0)
2538 I915_WRITE(WM2_LP_ILK, 0);
2539 if (previous.wm_lp[0] != 0)
2540 I915_WRITE(WM1_LP_ILK, 0);
2541
2542 if (previous.wm_pipe[0] != results->wm_pipe[0])
2543 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2544 if (previous.wm_pipe[1] != results->wm_pipe[1])
2545 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2546 if (previous.wm_pipe[2] != results->wm_pipe[2])
2547 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2548
2549 if (previous.wm_linetime[0] != results->wm_linetime[0])
2550 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2551 if (previous.wm_linetime[1] != results->wm_linetime[1])
2552 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2553 if (previous.wm_linetime[2] != results->wm_linetime[2])
2554 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2555
2556 if (prev_partitioning != partitioning) {
2557 val = I915_READ(WM_MISC);
2558 if (partitioning == HSW_DATA_BUF_PART_1_2)
2559 val &= ~WM_MISC_DATA_PARTITION_5_6;
2560 else
2561 val |= WM_MISC_DATA_PARTITION_5_6;
2562 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2563 }
2564
cca32e9a
PZ		 2565 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2566 val = I915_READ(DISP_ARB_CTL);
2567 if (results->enable_fbc_wm)
2568 val &= ~DISP_FBC_WM_DIS;
2569 else
2570 val |= DISP_FBC_WM_DIS;
2571 I915_WRITE(DISP_ARB_CTL, val);
2572 }
2573
801bcfff
PZ		 2574 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2575 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2576 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2577 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2578 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2579 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2580
2581 if (results->wm_lp[0] != 0)
2582 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2583 if (results->wm_lp[1] != 0)
2584 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2585 if (results->wm_lp[2] != 0)
2586 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2587}
2588
2589static void haswell_update_wm(struct drm_device *dev)
2590{
2591 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2592 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2593 struct hsw_pipe_wm_parameters params[3];
861f3389 2594 struct hsw_wm_values results_1_2, results_5_6, *best_results;
801bcfff 2595 uint32_t wm[5];
861f3389
PZ		 2596 enum hsw_data_buf_partitioning partitioning;
2597
2598 hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6);
2599
2600 hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
2601 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2602 hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
2603 &results_5_6);
2604 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2605 } else {
2606 best_results = &results_1_2;
2607 }
2608
2609 partitioning = (best_results == &results_1_2) ?
2610 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2611
861f3389 2612 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2613}
2614
526682e9
PZ		 2615static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2616 uint32_t sprite_width, int pixel_size,
2617 bool enable)
2618{
2619 struct drm_plane *plane;
2620
2621 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2622 struct intel_plane *intel_plane = to_intel_plane(plane);
2623
2624 if (intel_plane->pipe == pipe) {
2625 intel_plane->wm.enable = enable;
2626 intel_plane->wm.horiz_pixels = sprite_width + 1;
2627 intel_plane->wm.bytes_per_pixel = pixel_size;
2628 break;
2629 }
2630 }
2631
2632 haswell_update_wm(dev);
2633}
2634
b445e3b0
ED		 2635static bool
2636sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2637 uint32_t sprite_width, int pixel_size,
2638 const struct intel_watermark_params *display,
2639 int display_latency_ns, int *sprite_wm)
2640{
2641 struct drm_crtc *crtc;
2642 int clock;
2643 int entries, tlb_miss;
2644
2645 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2646 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2647 *sprite_wm = display->guard_size;
2648 return false;
2649 }
2650
2651 clock = crtc->mode.clock;
2652
2653 /* Use the small buffer method to calculate the sprite watermark */
2654 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2655 tlb_miss = display->fifo_size*display->cacheline_size -
2656 sprite_width * 8;
2657 if (tlb_miss > 0)
2658 entries += tlb_miss;
2659 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2660 *sprite_wm = entries + display->guard_size;
2661 if (*sprite_wm > (int)display->max_wm)
2662 *sprite_wm = display->max_wm;
2663
2664 return true;
2665}
2666
2667static bool
2668sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2669 uint32_t sprite_width, int pixel_size,
2670 const struct intel_watermark_params *display,
2671 int latency_ns, int *sprite_wm)
2672{
2673 struct drm_crtc *crtc;
2674 unsigned long line_time_us;
2675 int clock;
2676 int line_count, line_size;
2677 int small, large;
2678 int entries;
2679
2680 if (!latency_ns) {
2681 *sprite_wm = 0;
2682 return false;
2683 }
2684
2685 crtc = intel_get_crtc_for_plane(dev, plane);
2686 clock = crtc->mode.clock;
2687 if (!clock) {
2688 *sprite_wm = 0;
2689 return false;
2690 }
2691
2692 line_time_us = (sprite_width * 1000) / clock;
2693 if (!line_time_us) {
2694 *sprite_wm = 0;
2695 return false;
2696 }
2697
2698 line_count = (latency_ns / line_time_us + 1000) / 1000;
2699 line_size = sprite_width * pixel_size;
2700
2701 /* Use the minimum of the small and large buffer method for primary */
2702 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2703 large = line_count * line_size;
2704
2705 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2706 *sprite_wm = entries + display->guard_size;
2707
2708 return *sprite_wm > 0x3ff ? false : true;
2709}
2710
1fa61106 2711static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2712 uint32_t sprite_width, int pixel_size,
2713 bool enable)
b445e3b0
ED		 2714{
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2717 u32 val;
2718 int sprite_wm, reg;
2719 int ret;
2720
4c4ff43a
PZ		 2721 if (!enable)
2722 return;
2723
b445e3b0
ED		 2724 switch (pipe) {
2725 case 0:
2726 reg = WM0_PIPEA_ILK;
2727 break;
2728 case 1:
2729 reg = WM0_PIPEB_ILK;
2730 break;
2731 case 2:
2732 reg = WM0_PIPEC_IVB;
2733 break;
2734 default:
2735 return; /* bad pipe */
2736 }
2737
2738 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2739 &sandybridge_display_wm_info,
2740 latency, &sprite_wm);
2741 if (!ret) {
84f44ce7
VS		 2742 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2743 pipe_name(pipe));
b445e3b0
ED		 2744 return;
2745 }
2746
2747 val = I915_READ(reg);
2748 val &= ~WM0_PIPE_SPRITE_MASK;
2749 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2750 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2751
2752
2753 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2754 pixel_size,
2755 &sandybridge_display_srwm_info,
2756 SNB_READ_WM1_LATENCY() * 500,
2757 &sprite_wm);
2758 if (!ret) {
84f44ce7
VS		 2759 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2760 pipe_name(pipe));
b445e3b0
ED		 2761 return;
2762 }
2763 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2764
2765 /* Only IVB has two more LP watermarks for sprite */
2766 if (!IS_IVYBRIDGE(dev))
2767 return;
2768
2769 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2770 pixel_size,
2771 &sandybridge_display_srwm_info,
2772 SNB_READ_WM2_LATENCY() * 500,
2773 &sprite_wm);
2774 if (!ret) {
84f44ce7
VS		 2775 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2776 pipe_name(pipe));
b445e3b0
ED		 2777 return;
2778 }
2779 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2780
2781 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2782 pixel_size,
2783 &sandybridge_display_srwm_info,
2784 SNB_READ_WM3_LATENCY() * 500,
2785 &sprite_wm);
2786 if (!ret) {
84f44ce7
VS		 2787 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2788 pipe_name(pipe));
b445e3b0
ED		 2789 return;
2790 }
2791 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2792}
2793
2794/**
2795 * intel_update_watermarks - update FIFO watermark values based on current modes
2796 *
2797 * Calculate watermark values for the various WM regs based on current mode
2798 * and plane configuration.
2799 *
2800 * There are several cases to deal with here:
2801 * - normal (i.e. non-self-refresh)
2802 * - self-refresh (SR) mode
2803 * - lines are large relative to FIFO size (buffer can hold up to 2)
2804 * - lines are small relative to FIFO size (buffer can hold more than 2
2805 * lines), so need to account for TLB latency
2806 *
2807 * The normal calculation is:
2808 * watermark = dotclock * bytes per pixel * latency
2809 * where latency is platform & configuration dependent (we assume pessimal
2810 * values here).
2811 *
2812 * The SR calculation is:
2813 * watermark = (trunc(latency/line time)+1) * surface width *
2814 * bytes per pixel
2815 * where
2816 * line time = htotal / dotclock
2817 * surface width = hdisplay for normal plane and 64 for cursor
2818 * and latency is assumed to be high, as above.
2819 *
2820 * The final value programmed to the register should always be rounded up,
2821 * and include an extra 2 entries to account for clock crossings.
2822 *
2823 * We don't use the sprite, so we can ignore that. And on Crestline we have
2824 * to set the non-SR watermarks to 8.
2825 */
2826void intel_update_watermarks(struct drm_device *dev)
2827{
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829
2830 if (dev_priv->display.update_wm)
2831 dev_priv->display.update_wm(dev);
2832}
2833
2834void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2835 uint32_t sprite_width, int pixel_size,
2836 bool enable)
b445e3b0
ED		 2837{
2838 struct drm_i915_private *dev_priv = dev->dev_private;
2839
2840 if (dev_priv->display.update_sprite_wm)
2841 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4c4ff43a 2842 pixel_size, enable);
b445e3b0
ED		 2843}
2844
2b4e57bd
ED		 2845static struct drm_i915_gem_object *
2846intel_alloc_context_page(struct drm_device *dev)
2847{
2848 struct drm_i915_gem_object *ctx;
2849 int ret;
2850
2851 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2852
2853 ctx = i915_gem_alloc_object(dev, 4096);
2854 if (!ctx) {
2855 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2856 return NULL;
2857 }
2858
86a1ee26 2859 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2860 if (ret) {
2861 DRM_ERROR("failed to pin power context: %d\n", ret);
2862 goto err_unref;
2863 }
2864
2865 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2866 if (ret) {
2867 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2868 goto err_unpin;
2869 }
2870
2871 return ctx;
2872
2873err_unpin:
2874 i915_gem_object_unpin(ctx);
2875err_unref:
2876 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2877 return NULL;
2878}
2879
9270388e
DV		 2880/**
2881 * Lock protecting IPS related data structures
9270388e
DV		 2882 */
2883DEFINE_SPINLOCK(mchdev_lock);
2884
2885/* Global for IPS driver to get at the current i915 device. Protected by
2886 * mchdev_lock. */
2887static struct drm_i915_private *i915_mch_dev;
2888
2b4e57bd
ED		 2889bool ironlake_set_drps(struct drm_device *dev, u8 val)
2890{
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 u16 rgvswctl;
2893
9270388e
DV		 2894 assert_spin_locked(&mchdev_lock);
2895
2b4e57bd
ED		 2896 rgvswctl = I915_READ16(MEMSWCTL);
2897 if (rgvswctl & MEMCTL_CMD_STS) {
2898 DRM_DEBUG("gpu busy, RCS change rejected\n");
2899 return false; /* still busy with another command */
2900 }
2901
2902 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2903 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2904 I915_WRITE16(MEMSWCTL, rgvswctl);
2905 POSTING_READ16(MEMSWCTL);
2906
2907 rgvswctl |= MEMCTL_CMD_STS;
2908 I915_WRITE16(MEMSWCTL, rgvswctl);
2909
2910 return true;
2911}
2912
8090c6b9 2913static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2914{
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 u32 rgvmodectl = I915_READ(MEMMODECTL);
2917 u8 fmax, fmin, fstart, vstart;
2918
9270388e
DV		 2919 spin_lock_irq(&mchdev_lock);
2920
2b4e57bd
ED		 2921 /* Enable temp reporting */
2922 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2923 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2924
2925 /* 100ms RC evaluation intervals */
2926 I915_WRITE(RCUPEI, 100000);
2927 I915_WRITE(RCDNEI, 100000);
2928
2929 /* Set max/min thresholds to 90ms and 80ms respectively */
2930 I915_WRITE(RCBMAXAVG, 90000);
2931 I915_WRITE(RCBMINAVG, 80000);
2932
2933 I915_WRITE(MEMIHYST, 1);
2934
2935 /* Set up min, max, and cur for interrupt handling */
2936 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2937 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2938 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2939 MEMMODE_FSTART_SHIFT;
2940
2941 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2942 PXVFREQ_PX_SHIFT;
2943
20e4d407
DV		 2944 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2945 dev_priv->ips.fstart = fstart;
2b4e57bd 2946
20e4d407
DV		 2947 dev_priv->ips.max_delay = fstart;
2948 dev_priv->ips.min_delay = fmin;
2949 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2950
2951 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2952 fmax, fmin, fstart);
2953
2954 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2955
2956 /*
2957 * Interrupts will be enabled in ironlake_irq_postinstall
2958 */
2959
2960 I915_WRITE(VIDSTART, vstart);
2961 POSTING_READ(VIDSTART);
2962
2963 rgvmodectl |= MEMMODE_SWMODE_EN;
2964 I915_WRITE(MEMMODECTL, rgvmodectl);
2965
9270388e 2966 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2967 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2968 mdelay(1);
2b4e57bd
ED		 2969
2970 ironlake_set_drps(dev, fstart);
2971
20e4d407 2972 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2973 I915_READ(0x112e0);
20e4d407
DV		 2974 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2975 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2976 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2977
2978 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2979}
2980
8090c6b9 2981static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2982{
2983 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2984 u16 rgvswctl;
2985
2986 spin_lock_irq(&mchdev_lock);
2987
2988 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2989
2990 /* Ack interrupts, disable EFC interrupt */
2991 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2992 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2993 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2994 I915_WRITE(DEIIR, DE_PCU_EVENT);
2995 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2996
2997 /* Go back to the starting frequency */
20e4d407 2998 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2999 mdelay(1);
2b4e57bd
ED		 3000 rgvswctl |= MEMCTL_CMD_STS;
3001 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3002 mdelay(1);
2b4e57bd 3003
9270388e 3004 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3005}
3006
acbe9475
DV		 3007/* There's a funny hw issue where the hw returns all 0 when reading from
3008 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3009 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3010 * all limits and the gpu stuck at whatever frequency it is at atm).
3011 */
65bccb5c 3012static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3013{
7b9e0ae6 3014 u32 limits;
2b4e57bd 3015
7b9e0ae6 3016 limits = 0;
c6a828d3
DV		 3017
3018 if (*val >= dev_priv->rps.max_delay)
3019 *val = dev_priv->rps.max_delay;
3020 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3021
3022 /* Only set the down limit when we've reached the lowest level to avoid
3023 * getting more interrupts, otherwise leave this clear. This prevents a
3024 * race in the hw when coming out of rc6: There's a tiny window where
3025 * the hw runs at the minimal clock before selecting the desired
3026 * frequency, if the down threshold expires in that window we will not
3027 * receive a down interrupt. */
c6a828d3
DV		 3028 if (*val <= dev_priv->rps.min_delay) {
3029 *val = dev_priv->rps.min_delay;
3030 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3031 }
3032
3033 return limits;
3034}
3035
3036void gen6_set_rps(struct drm_device *dev, u8 val)
3037{
3038 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3039 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3040
4fc688ce 3041 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3042 WARN_ON(val > dev_priv->rps.max_delay);
3043 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3044
c6a828d3 3045 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3046 return;
3047
92bd1bf0
RV		 3048 if (IS_HASWELL(dev))
3049 I915_WRITE(GEN6_RPNSWREQ,
3050 HSW_FREQUENCY(val));
3051 else
3052 I915_WRITE(GEN6_RPNSWREQ,
3053 GEN6_FREQUENCY(val) |
3054 GEN6_OFFSET(0) |
3055 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3056
3057 /* Make sure we continue to get interrupts
3058 * until we hit the minimum or maximum frequencies.
3059 */
3060 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3061
d5570a72
BW		 3062 POSTING_READ(GEN6_RPNSWREQ);
3063
c6a828d3 3064 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3065
3066 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3067}
3068
80814ae4
VS		 3069/*
3070 * Wait until the previous freq change has completed,
3071 * or the timeout elapsed, and then update our notion
3072 * of the current GPU frequency.
3073 */
3074static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3075{
3076 unsigned long timeout = jiffies + msecs_to_jiffies(10);
3077 u32 pval;
3078
3079 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3080
3081 do {
3082 pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3083 if (time_after(jiffies, timeout)) {
3084 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3085 break;
3086 }
3087 udelay(10);
3088 } while (pval & 1);
3089
3090 pval >>= 8;
3091
3092 if (pval != dev_priv->rps.cur_delay)
3093 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3094 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3095 dev_priv->rps.cur_delay,
3096 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3097
3098 dev_priv->rps.cur_delay = pval;
3099}
3100
0a073b84
JB		 3101void valleyview_set_rps(struct drm_device *dev, u8 val)
3102{
3103 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3104
3105 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3106
3107 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3108 WARN_ON(val > dev_priv->rps.max_delay);
3109 WARN_ON(val < dev_priv->rps.min_delay);
3110
80814ae4
VS		 3111 vlv_update_rps_cur_delay(dev_priv);
3112
73008b98 3113 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3114 vlv_gpu_freq(dev_priv->mem_freq,
3115 dev_priv->rps.cur_delay),
73008b98
VS		 3116 dev_priv->rps.cur_delay,
3117 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3118
3119 if (val == dev_priv->rps.cur_delay)
3120 return;
3121
ae99258f 3122 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3123
80814ae4 3124 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3125
3126 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3127}
3128
3129
8090c6b9 3130static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 3131{
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133
88509484 3134 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 3135 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3136 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3137 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3138 /* Complete PM interrupt masking here doesn't race with the rps work
3139 * item again unmasking PM interrupts because that is using a different
3140 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3141 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3142
c6a828d3
DV		 3143 spin_lock_irq(&dev_priv->rps.lock);
3144 dev_priv->rps.pm_iir = 0;
3145 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd 3146
4848405c 3147 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3148}
3149
d20d4f0c
JB		 3150static void valleyview_disable_rps(struct drm_device *dev)
3151{
3152 struct drm_i915_private *dev_priv = dev->dev_private;
3153
3154 I915_WRITE(GEN6_RC_CONTROL, 0);
3155 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3156 I915_WRITE(GEN6_PMIER, 0);
3157 /* Complete PM interrupt masking here doesn't race with the rps work
3158 * item again unmasking PM interrupts because that is using a different
3159 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3160 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3161
3162 spin_lock_irq(&dev_priv->rps.lock);
3163 dev_priv->rps.pm_iir = 0;
3164 spin_unlock_irq(&dev_priv->rps.lock);
3165
3166 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
c9cddffc
JB		 3167
3168 if (dev_priv->vlv_pctx) {
3169 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3170 dev_priv->vlv_pctx = NULL;
3171 }
d20d4f0c
JB		 3172}
3173
2b4e57bd
ED		 3174int intel_enable_rc6(const struct drm_device *dev)
3175{
456470eb 3176 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3177 if (i915_enable_rc6 >= 0)
3178 return i915_enable_rc6;
3179
6567d748
CW		 3180 /* Disable RC6 on Ironlake */
3181 if (INTEL_INFO(dev)->gen == 5)
3182 return 0;
2b4e57bd 3183
456470eb
DV		 3184 if (IS_HASWELL(dev)) {
3185 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3186 return INTEL_RC6_ENABLE;
456470eb 3187 }
2b4e57bd 3188
456470eb 3189 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3190 if (INTEL_INFO(dev)->gen == 6) {
3191 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3192 return INTEL_RC6_ENABLE;
3193 }
456470eb 3194
2b4e57bd
ED		 3195 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3196 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3197}
3198
79f5b2c7 3199static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3200{
79f5b2c7 3201 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3202 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3203 u32 rp_state_cap;
3204 u32 gt_perf_status;
31643d54 3205 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3206 u32 gtfifodbg;
2b4e57bd 3207 int rc6_mode;
42c0526c 3208 int i, ret;
2b4e57bd 3209
4fc688ce 3210 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3211
2b4e57bd
ED		 3212 /* Here begins a magic sequence of register writes to enable
3213 * auto-downclocking.
3214 *
3215 * Perhaps there might be some value in exposing these to
3216 * userspace...
3217 */
3218 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3219
3220 /* Clear the DBG now so we don't confuse earlier errors */
3221 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3222 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3223 I915_WRITE(GTFIFODBG, gtfifodbg);
3224 }
3225
3226 gen6_gt_force_wake_get(dev_priv);
3227
7b9e0ae6
CW		 3228 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3229 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3230
31c77388
BW		 3231 /* In units of 50MHz */
3232 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3233 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3234 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3235
2b4e57bd
ED		 3236 /* disable the counters and set deterministic thresholds */
3237 I915_WRITE(GEN6_RC_CONTROL, 0);
3238
3239 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3240 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3241 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3242 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3243 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3244
b4519513
CW		 3245 for_each_ring(ring, dev_priv, i)
3246 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3247
3248 I915_WRITE(GEN6_RC_SLEEP, 0);
3249 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3250 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3251 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3252 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3253
5a7dc92a 3254 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3255 rc6_mode = intel_enable_rc6(dev_priv->dev);
3256 if (rc6_mode & INTEL_RC6_ENABLE)
3257 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3258
5a7dc92a
ED		 3259 /* We don't use those on Haswell */
3260 if (!IS_HASWELL(dev)) {
3261 if (rc6_mode & INTEL_RC6p_ENABLE)
3262 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3263
5a7dc92a
ED		 3264 if (rc6_mode & INTEL_RC6pp_ENABLE)
3265 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3266 }
2b4e57bd
ED		 3267
3268 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3269 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3270 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3271 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3272
3273 I915_WRITE(GEN6_RC_CONTROL,
3274 rc6_mask |
3275 GEN6_RC_CTL_EI_MODE(1) |
3276 GEN6_RC_CTL_HW_ENABLE);
3277
92bd1bf0
RV		 3278 if (IS_HASWELL(dev)) {
3279 I915_WRITE(GEN6_RPNSWREQ,
3280 HSW_FREQUENCY(10));
3281 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3282 HSW_FREQUENCY(12));
3283 } else {
3284 I915_WRITE(GEN6_RPNSWREQ,
3285 GEN6_FREQUENCY(10) |
3286 GEN6_OFFSET(0) |
3287 GEN6_AGGRESSIVE_TURBO);
3288 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3289 GEN6_FREQUENCY(12));
3290 }
2b4e57bd
ED		 3291
3292 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3293 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3294 dev_priv->rps.max_delay << 24 |
3295 dev_priv->rps.min_delay << 16);
5a7dc92a 3296
1ee9ae32
DV		 3297 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3298 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3299 I915_WRITE(GEN6_RP_UP_EI, 66000);
3300 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3301
2b4e57bd
ED		 3302 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3303 I915_WRITE(GEN6_RP_CONTROL,
3304 GEN6_RP_MEDIA_TURBO |
89ba829e 3305 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3306 GEN6_RP_MEDIA_IS_GFX |
3307 GEN6_RP_ENABLE |
3308 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3309 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3310
42c0526c 3311 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3312 if (!ret) {
42c0526c
BW		 3313 pcu_mbox = 0;
3314 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3315 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3316 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3317 (dev_priv->rps.max_delay & 0xff) * 50,
3318 (pcu_mbox & 0xff) * 50);
31c77388 3319 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3320 }
3321 } else {
3322 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3323 }
3324
7b9e0ae6 3325 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 3326
3327 /* requires MSI enabled */
4848405c 3328 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
c6a828d3 3329 spin_lock_irq(&dev_priv->rps.lock);
eda63ffb
BW		 3330 /* FIXME: Our interrupt enabling sequence is bonghits.
3331 * dev_priv->rps.pm_iir really should be 0 here. */
3332 dev_priv->rps.pm_iir = 0;
4848405c
BW		 3333 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3334 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
c6a828d3 3335 spin_unlock_irq(&dev_priv->rps.lock);
4848405c 3336 /* unmask all PM interrupts */
2b4e57bd
ED		 3337 I915_WRITE(GEN6_PMINTRMSK, 0);
3338
31643d54
BW		 3339 rc6vids = 0;
3340 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3341 if (IS_GEN6(dev) && ret) {
3342 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3343 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3344 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3345 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3346 rc6vids &= 0xffff00;
3347 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3348 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3349 if (ret)
3350 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3351 }
3352
2b4e57bd 3353 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3354}
3355
79f5b2c7 3356static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3357{
79f5b2c7 3358 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3359 int min_freq = 15;
3ebecd07
CW		 3360 unsigned int gpu_freq;
3361 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3362 int scaling_factor = 180;
3363
4fc688ce 3364 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3365
2b4e57bd
ED		 3366 max_ia_freq = cpufreq_quick_get_max(0);
3367 /*
3368 * Default to measured freq if none found, PCU will ensure we don't go
3369 * over
3370 */
3371 if (!max_ia_freq)
3372 max_ia_freq = tsc_khz;
3373
3374 /* Convert from kHz to MHz */
3375 max_ia_freq /= 1000;
3376
3ebecd07
CW		 3377 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3378 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3379 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3380
2b4e57bd
ED		 3381 /*
3382 * For each potential GPU frequency, load a ring frequency we'd like
3383 * to use for memory access. We do this by specifying the IA frequency
3384 * the PCU should use as a reference to determine the ring frequency.
3385 */
c6a828d3 3386 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3387 gpu_freq--) {
c6a828d3 3388 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3389 unsigned int ia_freq = 0, ring_freq = 0;
3390
3391 if (IS_HASWELL(dev)) {
3392 ring_freq = (gpu_freq * 5 + 3) / 4;
3393 ring_freq = max(min_ring_freq, ring_freq);
3394 /* leave ia_freq as the default, chosen by cpufreq */
3395 } else {
3396 /* On older processors, there is no separate ring
3397 * clock domain, so in order to boost the bandwidth
3398 * of the ring, we need to upclock the CPU (ia_freq).
3399 *
3400 * For GPU frequencies less than 750MHz,
3401 * just use the lowest ring freq.
3402 */
3403 if (gpu_freq < min_freq)
3404 ia_freq = 800;
3405 else
3406 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3407 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3408 }
2b4e57bd 3409
42c0526c
BW		 3410 sandybridge_pcode_write(dev_priv,
3411 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3412 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3413 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3414 gpu_freq);
2b4e57bd 3415 }
2b4e57bd
ED		 3416}
3417
0a073b84
JB		 3418int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3419{
3420 u32 val, rp0;
3421
64936258 3422 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3423
3424 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3425 /* Clamp to max */
3426 rp0 = min_t(u32, rp0, 0xea);
3427
3428 return rp0;
3429}
3430
3431static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3432{
3433 u32 val, rpe;
3434
64936258 3435 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3436 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3437 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3438 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3439
3440 return rpe;
3441}
3442
3443int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3444{
64936258 3445 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3446}
3447
52ceb908
JB		 3448static void vlv_rps_timer_work(struct work_struct *work)
3449{
3450 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3451 rps.vlv_work.work);
3452
3453 /*
3454 * Timer fired, we must be idle. Drop to min voltage state.
3455 * Note: we use RPe here since it should match the
3456 * Vmin we were shooting for. That should give us better
3457 * perf when we come back out of RC6 than if we used the
3458 * min freq available.
3459 */
3460 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3461 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3462 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3463 mutex_unlock(&dev_priv->rps.hw_lock);
3464}
3465
c9cddffc
JB		 3466static void valleyview_setup_pctx(struct drm_device *dev)
3467{
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 struct drm_i915_gem_object *pctx;
3470 unsigned long pctx_paddr;
3471 u32 pcbr;
3472 int pctx_size = 24*1024;
3473
3474 pcbr = I915_READ(VLV_PCBR);
3475 if (pcbr) {
3476 /* BIOS set it up already, grab the pre-alloc'd space */
3477 int pcbr_offset;
3478
3479 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3480 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3481 pcbr_offset,
3727d55e 3482 -1,
c9cddffc
JB		 3483 pctx_size);
3484 goto out;
3485 }
3486
3487 /*
3488 * From the Gunit register HAS:
3489 * The Gfx driver is expected to program this register and ensure
3490 * proper allocation within Gfx stolen memory. For example, this
3491 * register should be programmed such than the PCBR range does not
3492 * overlap with other ranges, such as the frame buffer, protected
3493 * memory, or any other relevant ranges.
3494 */
3495 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3496 if (!pctx) {
3497 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3498 return;
3499 }
3500
3501 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3502 I915_WRITE(VLV_PCBR, pctx_paddr);
3503
3504out:
3505 dev_priv->vlv_pctx = pctx;
3506}
3507
0a073b84
JB		 3508static void valleyview_enable_rps(struct drm_device *dev)
3509{
3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511 struct intel_ring_buffer *ring;
73008b98 3512 u32 gtfifodbg, val;
0a073b84
JB		 3513 int i;
3514
3515 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3516
3517 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3518 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3519 I915_WRITE(GTFIFODBG, gtfifodbg);
3520 }
3521
c9cddffc
JB		 3522 valleyview_setup_pctx(dev);
3523
0a073b84
JB		 3524 gen6_gt_force_wake_get(dev_priv);
3525
3526 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3527 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3528 I915_WRITE(GEN6_RP_UP_EI, 66000);
3529 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3530
3531 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3532
3533 I915_WRITE(GEN6_RP_CONTROL,
3534 GEN6_RP_MEDIA_TURBO |
3535 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3536 GEN6_RP_MEDIA_IS_GFX |
3537 GEN6_RP_ENABLE |
3538 GEN6_RP_UP_BUSY_AVG |
3539 GEN6_RP_DOWN_IDLE_CONT);
3540
3541 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3542 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3543 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3544
3545 for_each_ring(ring, dev_priv, i)
3546 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3547
3548 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3549
3550 /* allows RC6 residency counter to work */
3551 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3552 I915_WRITE(GEN6_RC_CONTROL,
3553 GEN7_RC_CTL_TO_MODE);
3554
64936258 3555 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3556 switch ((val >> 6) & 3) {
3557 case 0:
3558 case 1:
3559 dev_priv->mem_freq = 800;
3560 break;
3561 case 2:
3562 dev_priv->mem_freq = 1066;
3563 break;
3564 case 3:
3565 dev_priv->mem_freq = 1333;
3566 break;
3567 }
0a073b84
JB		 3568 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3569
3570 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3571 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3572
0a073b84 3573 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3574 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3575 vlv_gpu_freq(dev_priv->mem_freq,
3576 dev_priv->rps.cur_delay),
3577 dev_priv->rps.cur_delay);
0a073b84
JB		 3578
3579 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3580 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3581 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3582 vlv_gpu_freq(dev_priv->mem_freq,
3583 dev_priv->rps.max_delay),
3584 dev_priv->rps.max_delay);
0a073b84 3585
73008b98
VS		 3586 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3587 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3588 vlv_gpu_freq(dev_priv->mem_freq,
3589 dev_priv->rps.rpe_delay),
3590 dev_priv->rps.rpe_delay);
0a073b84 3591
73008b98
VS		 3592 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3593 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3594 vlv_gpu_freq(dev_priv->mem_freq,
3595 dev_priv->rps.min_delay),
3596 dev_priv->rps.min_delay);
0a073b84 3597
73008b98
VS		 3598 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3599 vlv_gpu_freq(dev_priv->mem_freq,
3600 dev_priv->rps.rpe_delay),
3601 dev_priv->rps.rpe_delay);
0a073b84 3602
52ceb908
JB		 3603 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3604
73008b98 3605 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84
JB		 3606
3607 /* requires MSI enabled */
4848405c 3608 I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
0a073b84
JB		 3609 spin_lock_irq(&dev_priv->rps.lock);
3610 WARN_ON(dev_priv->rps.pm_iir != 0);
3611 I915_WRITE(GEN6_PMIMR, 0);
3612 spin_unlock_irq(&dev_priv->rps.lock);
3613 /* enable all PM interrupts */
3614 I915_WRITE(GEN6_PMINTRMSK, 0);
3615
3616 gen6_gt_force_wake_put(dev_priv);
3617}
3618
930ebb46 3619void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3620{
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622
3e373948
DV		 3623 if (dev_priv->ips.renderctx) {
3624 i915_gem_object_unpin(dev_priv->ips.renderctx);
3625 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3626 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3627 }
3628
3e373948
DV		 3629 if (dev_priv->ips.pwrctx) {
3630 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3631 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3632 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3633 }
3634}
3635
930ebb46 3636static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3637{
3638 struct drm_i915_private *dev_priv = dev->dev_private;
3639
3640 if (I915_READ(PWRCTXA)) {
3641 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3642 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3643 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3644 50);
3645
3646 I915_WRITE(PWRCTXA, 0);
3647 POSTING_READ(PWRCTXA);
3648
3649 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3650 POSTING_READ(RSTDBYCTL);
3651 }
2b4e57bd
ED		 3652}
3653
3654static int ironlake_setup_rc6(struct drm_device *dev)
3655{
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657
3e373948
DV		 3658 if (dev_priv->ips.renderctx == NULL)
3659 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3660 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3661 return -ENOMEM;
3662
3e373948
DV		 3663 if (dev_priv->ips.pwrctx == NULL)
3664 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3665 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3666 ironlake_teardown_rc6(dev);
3667 return -ENOMEM;
3668 }
3669
3670 return 0;
3671}
3672
930ebb46 3673static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3674{
3675 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3676 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3677 bool was_interruptible;
2b4e57bd
ED		 3678 int ret;
3679
3680 /* rc6 disabled by default due to repeated reports of hanging during
3681 * boot and resume.
3682 */
3683 if (!intel_enable_rc6(dev))
3684 return;
3685
79f5b2c7
DV		 3686 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3687
2b4e57bd 3688 ret = ironlake_setup_rc6(dev);
79f5b2c7 3689 if (ret)
2b4e57bd 3690 return;
2b4e57bd 3691
3e960501
CW		 3692 was_interruptible = dev_priv->mm.interruptible;
3693 dev_priv->mm.interruptible = false;
3694
2b4e57bd
ED		 3695 /*
3696 * GPU can automatically power down the render unit if given a page
3697 * to save state.
3698 */
6d90c952 3699 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3700 if (ret) {
3701 ironlake_teardown_rc6(dev);
3e960501 3702 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3703 return;
3704 }
3705
6d90c952
DV		 3706 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3707 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 3708 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 3709 MI_MM_SPACE_GTT |
3710 MI_SAVE_EXT_STATE_EN |
3711 MI_RESTORE_EXT_STATE_EN |
3712 MI_RESTORE_INHIBIT);
3713 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3714 intel_ring_emit(ring, MI_NOOP);
3715 intel_ring_emit(ring, MI_FLUSH);
3716 intel_ring_advance(ring);
2b4e57bd
ED		 3717
3718 /*
3719 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3720 * does an implicit flush, combined with MI_FLUSH above, it should be
3721 * safe to assume that renderctx is valid
3722 */
3e960501
CW		 3723 ret = intel_ring_idle(ring);
3724 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3725 if (ret) {
def27a58 3726 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3727 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3728 return;
3729 }
3730
3e373948 3731 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 3732 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3733}
3734
dde18883
ED		 3735static unsigned long intel_pxfreq(u32 vidfreq)
3736{
3737 unsigned long freq;
3738 int div = (vidfreq & 0x3f0000) >> 16;
3739 int post = (vidfreq & 0x3000) >> 12;
3740 int pre = (vidfreq & 0x7);
3741
3742 if (!pre)
3743 return 0;
3744
3745 freq = ((div * 133333) / ((1<<post) * pre));
3746
3747 return freq;
3748}
3749
eb48eb00
DV		 3750static const struct cparams {
3751 u16 i;
3752 u16 t;
3753 u16 m;
3754 u16 c;
3755} cparams[] = {
3756 { 1, 1333, 301, 28664 },
3757 { 1, 1066, 294, 24460 },
3758 { 1, 800, 294, 25192 },
3759 { 0, 1333, 276, 27605 },
3760 { 0, 1066, 276, 27605 },
3761 { 0, 800, 231, 23784 },
3762};
3763
f531dcb2 3764static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3765{
3766 u64 total_count, diff, ret;
3767 u32 count1, count2, count3, m = 0, c = 0;
3768 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3769 int i;
3770
02d71956
DV		 3771 assert_spin_locked(&mchdev_lock);
3772
20e4d407 3773 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3774
3775 /* Prevent division-by-zero if we are asking too fast.
3776 * Also, we don't get interesting results if we are polling
3777 * faster than once in 10ms, so just return the saved value
3778 * in such cases.
3779 */
3780 if (diff1 <= 10)
20e4d407 3781 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3782
3783 count1 = I915_READ(DMIEC);
3784 count2 = I915_READ(DDREC);
3785 count3 = I915_READ(CSIEC);
3786
3787 total_count = count1 + count2 + count3;
3788
3789 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3790 if (total_count < dev_priv->ips.last_count1) {
3791 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3792 diff += total_count;
3793 } else {
20e4d407 3794 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3795 }
3796
3797 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3798 if (cparams[i].i == dev_priv->ips.c_m &&
3799 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3800 m = cparams[i].m;
3801 c = cparams[i].c;
3802 break;
3803 }
3804 }
3805
3806 diff = div_u64(diff, diff1);
3807 ret = ((m * diff) + c);
3808 ret = div_u64(ret, 10);
3809
20e4d407
DV		 3810 dev_priv->ips.last_count1 = total_count;
3811 dev_priv->ips.last_time1 = now;
eb48eb00 3812
20e4d407 3813 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3814
3815 return ret;
3816}
3817
f531dcb2
CW		 3818unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3819{
3820 unsigned long val;
3821
3822 if (dev_priv->info->gen != 5)
3823 return 0;
3824
3825 spin_lock_irq(&mchdev_lock);
3826
3827 val = __i915_chipset_val(dev_priv);
3828
3829 spin_unlock_irq(&mchdev_lock);
3830
3831 return val;
3832}
3833
eb48eb00
DV		 3834unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3835{
3836 unsigned long m, x, b;
3837 u32 tsfs;
3838
3839 tsfs = I915_READ(TSFS);
3840
3841 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3842 x = I915_READ8(TR1);
3843
3844 b = tsfs & TSFS_INTR_MASK;
3845
3846 return ((m * x) / 127) - b;
3847}
3848
3849static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3850{
3851 static const struct v_table {
3852 u16 vd; /* in .1 mil */
3853 u16 vm; /* in .1 mil */
3854 } v_table[] = {
3855 { 0, 0, },
3856 { 375, 0, },
3857 { 500, 0, },
3858 { 625, 0, },
3859 { 750, 0, },
3860 { 875, 0, },
3861 { 1000, 0, },
3862 { 1125, 0, },
3863 { 4125, 3000, },
3864 { 4125, 3000, },
3865 { 4125, 3000, },
3866 { 4125, 3000, },
3867 { 4125, 3000, },
3868 { 4125, 3000, },
3869 { 4125, 3000, },
3870 { 4125, 3000, },
3871 { 4125, 3000, },
3872 { 4125, 3000, },
3873 { 4125, 3000, },
3874 { 4125, 3000, },
3875 { 4125, 3000, },
3876 { 4125, 3000, },
3877 { 4125, 3000, },
3878 { 4125, 3000, },
3879 { 4125, 3000, },
3880 { 4125, 3000, },
3881 { 4125, 3000, },
3882 { 4125, 3000, },
3883 { 4125, 3000, },
3884 { 4125, 3000, },
3885 { 4125, 3000, },
3886 { 4125, 3000, },
3887 { 4250, 3125, },
3888 { 4375, 3250, },
3889 { 4500, 3375, },
3890 { 4625, 3500, },
3891 { 4750, 3625, },
3892 { 4875, 3750, },
3893 { 5000, 3875, },
3894 { 5125, 4000, },
3895 { 5250, 4125, },
3896 { 5375, 4250, },
3897 { 5500, 4375, },
3898 { 5625, 4500, },
3899 { 5750, 4625, },
3900 { 5875, 4750, },
3901 { 6000, 4875, },
3902 { 6125, 5000, },
3903 { 6250, 5125, },
3904 { 6375, 5250, },
3905 { 6500, 5375, },
3906 { 6625, 5500, },
3907 { 6750, 5625, },
3908 { 6875, 5750, },
3909 { 7000, 5875, },
3910 { 7125, 6000, },
3911 { 7250, 6125, },
3912 { 7375, 6250, },
3913 { 7500, 6375, },
3914 { 7625, 6500, },
3915 { 7750, 6625, },
3916 { 7875, 6750, },
3917 { 8000, 6875, },
3918 { 8125, 7000, },
3919 { 8250, 7125, },
3920 { 8375, 7250, },
3921 { 8500, 7375, },
3922 { 8625, 7500, },
3923 { 8750, 7625, },
3924 { 8875, 7750, },
3925 { 9000, 7875, },
3926 { 9125, 8000, },
3927 { 9250, 8125, },
3928 { 9375, 8250, },
3929 { 9500, 8375, },
3930 { 9625, 8500, },
3931 { 9750, 8625, },
3932 { 9875, 8750, },
3933 { 10000, 8875, },
3934 { 10125, 9000, },
3935 { 10250, 9125, },
3936 { 10375, 9250, },
3937 { 10500, 9375, },
3938 { 10625, 9500, },
3939 { 10750, 9625, },
3940 { 10875, 9750, },
3941 { 11000, 9875, },
3942 { 11125, 10000, },
3943 { 11250, 10125, },
3944 { 11375, 10250, },
3945 { 11500, 10375, },
3946 { 11625, 10500, },
3947 { 11750, 10625, },
3948 { 11875, 10750, },
3949 { 12000, 10875, },
3950 { 12125, 11000, },
3951 { 12250, 11125, },
3952 { 12375, 11250, },
3953 { 12500, 11375, },
3954 { 12625, 11500, },
3955 { 12750, 11625, },
3956 { 12875, 11750, },
3957 { 13000, 11875, },
3958 { 13125, 12000, },
3959 { 13250, 12125, },
3960 { 13375, 12250, },
3961 { 13500, 12375, },
3962 { 13625, 12500, },
3963 { 13750, 12625, },
3964 { 13875, 12750, },
3965 { 14000, 12875, },
3966 { 14125, 13000, },
3967 { 14250, 13125, },
3968 { 14375, 13250, },
3969 { 14500, 13375, },
3970 { 14625, 13500, },
3971 { 14750, 13625, },
3972 { 14875, 13750, },
3973 { 15000, 13875, },
3974 { 15125, 14000, },
3975 { 15250, 14125, },
3976 { 15375, 14250, },
3977 { 15500, 14375, },
3978 { 15625, 14500, },
3979 { 15750, 14625, },
3980 { 15875, 14750, },
3981 { 16000, 14875, },
3982 { 16125, 15000, },
3983 };
3984 if (dev_priv->info->is_mobile)
3985 return v_table[pxvid].vm;
3986 else
3987 return v_table[pxvid].vd;
3988}
3989
02d71956 3990static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3991{
3992 struct timespec now, diff1;
3993 u64 diff;
3994 unsigned long diffms;
3995 u32 count;
3996
02d71956 3997 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3998
3999 getrawmonotonic(&now);
20e4d407 4000 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4001
4002 /* Don't divide by 0 */
4003 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4004 if (!diffms)
4005 return;
4006
4007 count = I915_READ(GFXEC);
4008
20e4d407
DV		 4009 if (count < dev_priv->ips.last_count2) {
4010 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4011 diff += count;
4012 } else {
20e4d407 4013 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4014 }
4015
20e4d407
DV		 4016 dev_priv->ips.last_count2 = count;
4017 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4018
4019 /* More magic constants... */
4020 diff = diff * 1181;
4021 diff = div_u64(diff, diffms * 10);
20e4d407 4022 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4023}
4024
02d71956
DV		 4025void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4026{
4027 if (dev_priv->info->gen != 5)
4028 return;
4029
9270388e 4030 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4031
4032 __i915_update_gfx_val(dev_priv);
4033
9270388e 4034 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4035}
4036
f531dcb2 4037static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4038{
4039 unsigned long t, corr, state1, corr2, state2;
4040 u32 pxvid, ext_v;
4041
02d71956
DV		 4042 assert_spin_locked(&mchdev_lock);
4043
c6a828d3 4044 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4045 pxvid = (pxvid >> 24) & 0x7f;
4046 ext_v = pvid_to_extvid(dev_priv, pxvid);
4047
4048 state1 = ext_v;
4049
4050 t = i915_mch_val(dev_priv);
4051
4052 /* Revel in the empirically derived constants */
4053
4054 /* Correction factor in 1/100000 units */
4055 if (t > 80)
4056 corr = ((t * 2349) + 135940);
4057 else if (t >= 50)
4058 corr = ((t * 964) + 29317);
4059 else /* < 50 */
4060 corr = ((t * 301) + 1004);
4061
4062 corr = corr * ((150142 * state1) / 10000 - 78642);
4063 corr /= 100000;
20e4d407 4064 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4065
4066 state2 = (corr2 * state1) / 10000;
4067 state2 /= 100; /* convert to mW */
4068
02d71956 4069 __i915_update_gfx_val(dev_priv);
eb48eb00 4070
20e4d407 4071 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4072}
4073
f531dcb2
CW		 4074unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4075{
4076 unsigned long val;
4077
4078 if (dev_priv->info->gen != 5)
4079 return 0;
4080
4081 spin_lock_irq(&mchdev_lock);
4082
4083 val = __i915_gfx_val(dev_priv);
4084
4085 spin_unlock_irq(&mchdev_lock);
4086
4087 return val;
4088}
4089
eb48eb00
DV		 4090/**
4091 * i915_read_mch_val - return value for IPS use
4092 *
4093 * Calculate and return a value for the IPS driver to use when deciding whether
4094 * we have thermal and power headroom to increase CPU or GPU power budget.
4095 */
4096unsigned long i915_read_mch_val(void)
4097{
4098 struct drm_i915_private *dev_priv;
4099 unsigned long chipset_val, graphics_val, ret = 0;
4100
9270388e 4101 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4102 if (!i915_mch_dev)
4103 goto out_unlock;
4104 dev_priv = i915_mch_dev;
4105
f531dcb2
CW		 4106 chipset_val = __i915_chipset_val(dev_priv);
4107 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4108
4109 ret = chipset_val + graphics_val;
4110
4111out_unlock:
9270388e 4112 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4113
4114 return ret;
4115}
4116EXPORT_SYMBOL_GPL(i915_read_mch_val);
4117
4118/**
4119 * i915_gpu_raise - raise GPU frequency limit
4120 *
4121 * Raise the limit; IPS indicates we have thermal headroom.
4122 */
4123bool i915_gpu_raise(void)
4124{
4125 struct drm_i915_private *dev_priv;
4126 bool ret = true;
4127
9270388e 4128 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4129 if (!i915_mch_dev) {
4130 ret = false;
4131 goto out_unlock;
4132 }
4133 dev_priv = i915_mch_dev;
4134
20e4d407
DV		 4135 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4136 dev_priv->ips.max_delay--;
eb48eb00
DV		 4137
4138out_unlock:
9270388e 4139 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4140
4141 return ret;
4142}
4143EXPORT_SYMBOL_GPL(i915_gpu_raise);
4144
4145/**
4146 * i915_gpu_lower - lower GPU frequency limit
4147 *
4148 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4149 * frequency maximum.
4150 */
4151bool i915_gpu_lower(void)
4152{
4153 struct drm_i915_private *dev_priv;
4154 bool ret = true;
4155
9270388e 4156 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4157 if (!i915_mch_dev) {
4158 ret = false;
4159 goto out_unlock;
4160 }
4161 dev_priv = i915_mch_dev;
4162
20e4d407
DV		 4163 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4164 dev_priv->ips.max_delay++;
eb48eb00
DV		 4165
4166out_unlock:
9270388e 4167 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4168
4169 return ret;
4170}
4171EXPORT_SYMBOL_GPL(i915_gpu_lower);
4172
4173/**
4174 * i915_gpu_busy - indicate GPU business to IPS
4175 *
4176 * Tell the IPS driver whether or not the GPU is busy.
4177 */
4178bool i915_gpu_busy(void)
4179{
4180 struct drm_i915_private *dev_priv;
f047e395 4181 struct intel_ring_buffer *ring;
eb48eb00 4182 bool ret = false;
f047e395 4183 int i;
eb48eb00 4184
9270388e 4185 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4186 if (!i915_mch_dev)
4187 goto out_unlock;
4188 dev_priv = i915_mch_dev;
4189
f047e395
CW		 4190 for_each_ring(ring, dev_priv, i)
4191 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4192
4193out_unlock:
9270388e 4194 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4195
4196 return ret;
4197}
4198EXPORT_SYMBOL_GPL(i915_gpu_busy);
4199
4200/**
4201 * i915_gpu_turbo_disable - disable graphics turbo
4202 *
4203 * Disable graphics turbo by resetting the max frequency and setting the
4204 * current frequency to the default.
4205 */
4206bool i915_gpu_turbo_disable(void)
4207{
4208 struct drm_i915_private *dev_priv;
4209 bool ret = true;
4210
9270388e 4211 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4212 if (!i915_mch_dev) {
4213 ret = false;
4214 goto out_unlock;
4215 }
4216 dev_priv = i915_mch_dev;
4217
20e4d407 4218 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4219
20e4d407 4220 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4221 ret = false;
4222
4223out_unlock:
9270388e 4224 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4225
4226 return ret;
4227}
4228EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4229
4230/**
4231 * Tells the intel_ips driver that the i915 driver is now loaded, if
4232 * IPS got loaded first.
4233 *
4234 * This awkward dance is so that neither module has to depend on the
4235 * other in order for IPS to do the appropriate communication of
4236 * GPU turbo limits to i915.
4237 */
4238static void
4239ips_ping_for_i915_load(void)
4240{
4241 void (*link)(void);
4242
4243 link = symbol_get(ips_link_to_i915_driver);
4244 if (link) {
4245 link();
4246 symbol_put(ips_link_to_i915_driver);
4247 }
4248}
4249
4250void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4251{
02d71956
DV		 4252 /* We only register the i915 ips part with intel-ips once everything is
4253 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4254 spin_lock_irq(&mchdev_lock);
eb48eb00 4255 i915_mch_dev = dev_priv;
9270388e 4256 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4257
4258 ips_ping_for_i915_load();
4259}
4260
4261void intel_gpu_ips_teardown(void)
4262{
9270388e 4263 spin_lock_irq(&mchdev_lock);
eb48eb00 4264 i915_mch_dev = NULL;
9270388e 4265 spin_unlock_irq(&mchdev_lock);
eb48eb00 4266}
8090c6b9 4267static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4268{
4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270 u32 lcfuse;
4271 u8 pxw[16];
4272 int i;
4273
4274 /* Disable to program */
4275 I915_WRITE(ECR, 0);
4276 POSTING_READ(ECR);
4277
4278 /* Program energy weights for various events */
4279 I915_WRITE(SDEW, 0x15040d00);
4280 I915_WRITE(CSIEW0, 0x007f0000);
4281 I915_WRITE(CSIEW1, 0x1e220004);
4282 I915_WRITE(CSIEW2, 0x04000004);
4283
4284 for (i = 0; i < 5; i++)
4285 I915_WRITE(PEW + (i * 4), 0);
4286 for (i = 0; i < 3; i++)
4287 I915_WRITE(DEW + (i * 4), 0);
4288
4289 /* Program P-state weights to account for frequency power adjustment */
4290 for (i = 0; i < 16; i++) {
4291 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4292 unsigned long freq = intel_pxfreq(pxvidfreq);
4293 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4294 PXVFREQ_PX_SHIFT;
4295 unsigned long val;
4296
4297 val = vid * vid;
4298 val *= (freq / 1000);
4299 val *= 255;
4300 val /= (127*127*900);
4301 if (val > 0xff)
4302 DRM_ERROR("bad pxval: %ld\n", val);
4303 pxw[i] = val;
4304 }
4305 /* Render standby states get 0 weight */
4306 pxw[14] = 0;
4307 pxw[15] = 0;
4308
4309 for (i = 0; i < 4; i++) {
4310 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4311 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4312 I915_WRITE(PXW + (i * 4), val);
4313 }
4314
4315 /* Adjust magic regs to magic values (more experimental results) */
4316 I915_WRITE(OGW0, 0);
4317 I915_WRITE(OGW1, 0);
4318 I915_WRITE(EG0, 0x00007f00);
4319 I915_WRITE(EG1, 0x0000000e);
4320 I915_WRITE(EG2, 0x000e0000);
4321 I915_WRITE(EG3, 0x68000300);
4322 I915_WRITE(EG4, 0x42000000);
4323 I915_WRITE(EG5, 0x00140031);
4324 I915_WRITE(EG6, 0);
4325 I915_WRITE(EG7, 0);
4326
4327 for (i = 0; i < 8; i++)
4328 I915_WRITE(PXWL + (i * 4), 0);
4329
4330 /* Enable PMON + select events */
4331 I915_WRITE(ECR, 0x80000019);
4332
4333 lcfuse = I915_READ(LCFUSE02);
4334
20e4d407 4335 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4336}
4337
8090c6b9
DV		 4338void intel_disable_gt_powersave(struct drm_device *dev)
4339{
1a01ab3b
JB		 4340 struct drm_i915_private *dev_priv = dev->dev_private;
4341
fd0c0642
DV		 4342 /* Interrupts should be disabled already to avoid re-arming. */
4343 WARN_ON(dev->irq_enabled);
4344
930ebb46 4345 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4346 ironlake_disable_drps(dev);
930ebb46 4347 ironlake_disable_rc6(dev);
0a073b84 4348 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4349 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4350 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4351 if (IS_VALLEYVIEW(dev))
4352 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4353 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4354 if (IS_VALLEYVIEW(dev))
4355 valleyview_disable_rps(dev);
4356 else
4357 gen6_disable_rps(dev);
4fc688ce 4358 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4359 }
8090c6b9
DV		 4360}
4361
1a01ab3b
JB		 4362static void intel_gen6_powersave_work(struct work_struct *work)
4363{
4364 struct drm_i915_private *dev_priv =
4365 container_of(work, struct drm_i915_private,
4366 rps.delayed_resume_work.work);
4367 struct drm_device *dev = dev_priv->dev;
4368
4fc688ce 4369 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4370
4371 if (IS_VALLEYVIEW(dev)) {
4372 valleyview_enable_rps(dev);
4373 } else {
4374 gen6_enable_rps(dev);
4375 gen6_update_ring_freq(dev);
4376 }
4fc688ce 4377 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4378}
4379
8090c6b9
DV		 4380void intel_enable_gt_powersave(struct drm_device *dev)
4381{
1a01ab3b
JB		 4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383
8090c6b9
DV		 4384 if (IS_IRONLAKE_M(dev)) {
4385 ironlake_enable_drps(dev);
4386 ironlake_enable_rc6(dev);
4387 intel_init_emon(dev);
0a073b84 4388 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4389 /*
4390 * PCU communication is slow and this doesn't need to be
4391 * done at any specific time, so do this out of our fast path
4392 * to make resume and init faster.
4393 */
4394 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4395 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4396 }
4397}
4398
3107bd48
DV		 4399static void ibx_init_clock_gating(struct drm_device *dev)
4400{
4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402
4403 /*
4404 * On Ibex Peak and Cougar Point, we need to disable clock
4405 * gating for the panel power sequencer or it will fail to
4406 * start up when no ports are active.
4407 */
4408 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4409}
4410
0e088b8f
VS		 4411static void g4x_disable_trickle_feed(struct drm_device *dev)
4412{
4413 struct drm_i915_private *dev_priv = dev->dev_private;
4414 int pipe;
4415
4416 for_each_pipe(pipe) {
4417 I915_WRITE(DSPCNTR(pipe),
4418 I915_READ(DSPCNTR(pipe)) |
4419 DISPPLANE_TRICKLE_FEED_DISABLE);
4420 intel_flush_display_plane(dev_priv, pipe);
4421 }
4422}
4423
1fa61106 4424static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4425{
4426 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4427 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 4428
4429 /* Required for FBC */
4d47e4f5
DL		 4430 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4431 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4432 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4433
4434 I915_WRITE(PCH_3DCGDIS0,
4435 MARIUNIT_CLOCK_GATE_DISABLE |
4436 SVSMUNIT_CLOCK_GATE_DISABLE);
4437 I915_WRITE(PCH_3DCGDIS1,
4438 VFMUNIT_CLOCK_GATE_DISABLE);
4439
6f1d69b0
ED		 4440 /*
4441 * According to the spec the following bits should be set in
4442 * order to enable memory self-refresh
4443 * The bit 22/21 of 0x42004
4444 * The bit 5 of 0x42020
4445 * The bit 15 of 0x45000
4446 */
4447 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4448 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4449 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4450 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4451 I915_WRITE(DISP_ARB_CTL,
4452 (I915_READ(DISP_ARB_CTL) |
4453 DISP_FBC_WM_DIS));
4454 I915_WRITE(WM3_LP_ILK, 0);
4455 I915_WRITE(WM2_LP_ILK, 0);
4456 I915_WRITE(WM1_LP_ILK, 0);
4457
4458 /*
4459 * Based on the document from hardware guys the following bits
4460 * should be set unconditionally in order to enable FBC.
4461 * The bit 22 of 0x42000
4462 * The bit 22 of 0x42004
4463 * The bit 7,8,9 of 0x42020.
4464 */
4465 if (IS_IRONLAKE_M(dev)) {
4466 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4467 I915_READ(ILK_DISPLAY_CHICKEN1) |
4468 ILK_FBCQ_DIS);
4469 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4470 I915_READ(ILK_DISPLAY_CHICKEN2) |
4471 ILK_DPARB_GATE);
6f1d69b0
ED		 4472 }
4473
4d47e4f5
DL		 4474 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4475
6f1d69b0
ED		 4476 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4477 I915_READ(ILK_DISPLAY_CHICKEN2) |
4478 ILK_ELPIN_409_SELECT);
4479 I915_WRITE(_3D_CHICKEN2,
4480 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4481 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4482
ecdb4eb7 4483 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4484 I915_WRITE(CACHE_MODE_0,
4485 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4486
0e088b8f 4487 g4x_disable_trickle_feed(dev);
bdad2b2f 4488
3107bd48
DV		 4489 ibx_init_clock_gating(dev);
4490}
4491
4492static void cpt_init_clock_gating(struct drm_device *dev)
4493{
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 int pipe;
3f704fa2 4496 uint32_t val;
3107bd48
DV		 4497
4498 /*
4499 * On Ibex Peak and Cougar Point, we need to disable clock
4500 * gating for the panel power sequencer or it will fail to
4501 * start up when no ports are active.
4502 */
4503 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4504 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4505 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4506 /* The below fixes the weird display corruption, a few pixels shifted
4507 * downward, on (only) LVDS of some HP laptops with IVY.
4508 */
3f704fa2 4509 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4510 val = I915_READ(TRANS_CHICKEN2(pipe));
4511 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4512 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4513 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4514 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4515 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4516 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4517 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4518 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4519 }
3107bd48
DV		 4520 /* WADP0ClockGatingDisable */
4521 for_each_pipe(pipe) {
4522 I915_WRITE(TRANS_CHICKEN1(pipe),
4523 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4524 }
6f1d69b0
ED		 4525}
4526
1d7aaa0c
DV		 4527static void gen6_check_mch_setup(struct drm_device *dev)
4528{
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 uint32_t tmp;
4531
4532 tmp = I915_READ(MCH_SSKPD);
4533 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4534 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4535 DRM_INFO("This can cause pipe underruns and display issues.\n");
4536 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4537 }
4538}
4539
1fa61106 4540static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4541{
4542 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4543 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4544
231e54f6 4545 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4546
4547 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4548 I915_READ(ILK_DISPLAY_CHICKEN2) |
4549 ILK_ELPIN_409_SELECT);
4550
ecdb4eb7 4551 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4552 I915_WRITE(_3D_CHICKEN,
4553 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4554
ecdb4eb7 4555 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4556 if (IS_SNB_GT1(dev))
4557 I915_WRITE(GEN6_GT_MODE,
4558 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4559
6f1d69b0
ED		 4560 I915_WRITE(WM3_LP_ILK, 0);
4561 I915_WRITE(WM2_LP_ILK, 0);
4562 I915_WRITE(WM1_LP_ILK, 0);
4563
6f1d69b0 4564 I915_WRITE(CACHE_MODE_0,
50743298 4565 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4566
4567 I915_WRITE(GEN6_UCGCTL1,
4568 I915_READ(GEN6_UCGCTL1) |
4569 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4570 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4571
4572 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4573 * gating disable must be set. Failure to set it results in
4574 * flickering pixels due to Z write ordering failures after
4575 * some amount of runtime in the Mesa "fire" demo, and Unigine
4576 * Sanctuary and Tropics, and apparently anything else with
4577 * alpha test or pixel discard.
4578 *
4579 * According to the spec, bit 11 (RCCUNIT) must also be set,
4580 * but we didn't debug actual testcases to find it out.
0f846f81 4581 *
ecdb4eb7
DL		 4582 * Also apply WaDisableVDSUnitClockGating:snb and
4583 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4584 */
4585 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4586 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4587 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4588 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4589
4590 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4591 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4592 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4593
4594 /*
4595 * According to the spec the following bits should be
4596 * set in order to enable memory self-refresh and fbc:
4597 * The bit21 and bit22 of 0x42000
4598 * The bit21 and bit22 of 0x42004
4599 * The bit5 and bit7 of 0x42020
4600 * The bit14 of 0x70180
4601 * The bit14 of 0x71180
4602 */
4603 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4604 I915_READ(ILK_DISPLAY_CHICKEN1) |
4605 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4606 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4607 I915_READ(ILK_DISPLAY_CHICKEN2) |
4608 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4609 I915_WRITE(ILK_DSPCLK_GATE_D,
4610 I915_READ(ILK_DSPCLK_GATE_D) |
4611 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4612 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4613
ecdb4eb7 4614 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4615 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4616 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4617
0e088b8f 4618 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4619
4620 /* The default value should be 0x200 according to docs, but the two
4621 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4622 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4623 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4624
4625 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4626
4627 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4628}
4629
4630static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4631{
4632 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4633
4634 reg &= ~GEN7_FF_SCHED_MASK;
4635 reg |= GEN7_FF_TS_SCHED_HW;
4636 reg |= GEN7_FF_VS_SCHED_HW;
4637 reg |= GEN7_FF_DS_SCHED_HW;
4638
41c0b3a8
BW		 4639 if (IS_HASWELL(dev_priv->dev))
4640 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4641
6f1d69b0
ED		 4642 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4643}
4644
17a303ec
PZ		 4645static void lpt_init_clock_gating(struct drm_device *dev)
4646{
4647 struct drm_i915_private *dev_priv = dev->dev_private;
4648
4649 /*
4650 * TODO: this bit should only be enabled when really needed, then
4651 * disabled when not needed anymore in order to save power.
4652 */
4653 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4654 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4655 I915_READ(SOUTH_DSPCLK_GATE_D) |
4656 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4657
4658 /* WADPOClockGatingDisable:hsw */
4659 I915_WRITE(_TRANSA_CHICKEN1,
4660 I915_READ(_TRANSA_CHICKEN1) |
4661 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4662}
4663
7d708ee4
ID		 4664static void lpt_suspend_hw(struct drm_device *dev)
4665{
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667
4668 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4669 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4670
4671 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4672 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4673 }
4674}
4675
cad2a2d7
ED		 4676static void haswell_init_clock_gating(struct drm_device *dev)
4677{
4678 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4679
4680 I915_WRITE(WM3_LP_ILK, 0);
4681 I915_WRITE(WM2_LP_ILK, 0);
4682 I915_WRITE(WM1_LP_ILK, 0);
4683
4684 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4685 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4686 */
4687 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4688
ecdb4eb7 4689 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4690 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4691 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4692
ecdb4eb7 4693 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4694 I915_WRITE(GEN7_L3CNTLREG1,
4695 GEN7_WA_FOR_GEN7_L3_CONTROL);
4696 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4697 GEN7_WA_L3_CHICKEN_MODE);
4698
ecdb4eb7 4699 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4700 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4701 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4702 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4703
0e088b8f 4704 g4x_disable_trickle_feed(dev);
cad2a2d7 4705
ecdb4eb7 4706 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4707 gen7_setup_fixed_func_scheduler(dev_priv);
4708
ecdb4eb7 4709 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4710 I915_WRITE(CACHE_MODE_1,
4711 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4712
ecdb4eb7 4713 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4714 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4715 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4716
ecdb4eb7 4717 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4718 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4719
90a88643
PZ		 4720 /* WaRsPkgCStateDisplayPMReq:hsw */
4721 I915_WRITE(CHICKEN_PAR1_1,
4722 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4723
17a303ec 4724 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4725}
4726
1fa61106 4727static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4728{
4729 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4730 uint32_t snpcr;
6f1d69b0 4731
6f1d69b0
ED		 4732 I915_WRITE(WM3_LP_ILK, 0);
4733 I915_WRITE(WM2_LP_ILK, 0);
4734 I915_WRITE(WM1_LP_ILK, 0);
4735
231e54f6 4736 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4737
ecdb4eb7 4738 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4739 I915_WRITE(_3D_CHICKEN3,
4740 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4741
ecdb4eb7 4742 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4743 I915_WRITE(IVB_CHICKEN3,
4744 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4745 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4746
ecdb4eb7 4747 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4748 if (IS_IVB_GT1(dev))
4749 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4750 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4751 else
4752 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4753 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4754
ecdb4eb7 4755 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4756 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4757 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4758
ecdb4eb7 4759 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4760 I915_WRITE(GEN7_L3CNTLREG1,
4761 GEN7_WA_FOR_GEN7_L3_CONTROL);
4762 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4763 GEN7_WA_L3_CHICKEN_MODE);
4764 if (IS_IVB_GT1(dev))
4765 I915_WRITE(GEN7_ROW_CHICKEN2,
4766 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4767 else
4768 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4769 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4770
6f1d69b0 4771
ecdb4eb7 4772 /* WaForceL3Serialization:ivb */
61939d97
JB		 4773 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4774 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4775
0f846f81
JB		 4776 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4777 * gating disable must be set. Failure to set it results in
4778 * flickering pixels due to Z write ordering failures after
4779 * some amount of runtime in the Mesa "fire" demo, and Unigine
4780 * Sanctuary and Tropics, and apparently anything else with
4781 * alpha test or pixel discard.
4782 *
4783 * According to the spec, bit 11 (RCCUNIT) must also be set,
4784 * but we didn't debug actual testcases to find it out.
4785 *
4786 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4787 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4788 */
4789 I915_WRITE(GEN6_UCGCTL2,
4790 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4791 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4792
ecdb4eb7 4793 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4794 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4795 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4796 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4797
0e088b8f 4798 g4x_disable_trickle_feed(dev);
6f1d69b0 4799
ecdb4eb7 4800 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4801 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4802 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4803
ecdb4eb7 4804 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4805 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4806
ecdb4eb7 4807 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4808 I915_WRITE(CACHE_MODE_1,
4809 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4810
4811 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4812 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4813 snpcr |= GEN6_MBC_SNPCR_MED;
4814 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4815
ab5c608b
BW		 4816 if (!HAS_PCH_NOP(dev))
4817 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4818
4819 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4820}
4821
1fa61106 4822static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4823{
4824 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 4825
d7fe0cc0 4826 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4827
ecdb4eb7 4828 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4829 I915_WRITE(_3D_CHICKEN3,
4830 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4831
ecdb4eb7 4832 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4833 I915_WRITE(IVB_CHICKEN3,
4834 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4835 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4836
ecdb4eb7 4837 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4838 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4839 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4840 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4841
ecdb4eb7 4842 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4843 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4844 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4845
ecdb4eb7 4846 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4847 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4848 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4849
ecdb4eb7 4850 /* WaForceL3Serialization:vlv */
61939d97
JB		 4851 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4852 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4853
ecdb4eb7 4854 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4855 I915_WRITE(GEN7_ROW_CHICKEN2,
4856 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4857
ecdb4eb7 4858 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4859 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4860 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4861 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4862
ecdb4eb7 4863 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4864 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4865 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4866
0f846f81
JB		 4867
4868 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4869 * gating disable must be set. Failure to set it results in
4870 * flickering pixels due to Z write ordering failures after
4871 * some amount of runtime in the Mesa "fire" demo, and Unigine
4872 * Sanctuary and Tropics, and apparently anything else with
4873 * alpha test or pixel discard.
4874 *
4875 * According to the spec, bit 11 (RCCUNIT) must also be set,
4876 * but we didn't debug actual testcases to find it out.
4877 *
4878 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4879 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4880 *
ecdb4eb7
DL		 4881 * Also apply WaDisableVDSUnitClockGating:vlv and
4882 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4883 */
4884 I915_WRITE(GEN6_UCGCTL2,
4885 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4886 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4887 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4888 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4889 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4890
e3f33d46
JB		 4891 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4892
e0d8d59b 4893 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 4894
6b26c86d
DV		 4895 I915_WRITE(CACHE_MODE_1,
4896 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4897
2d809570 4898 /*
ecdb4eb7 4899 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4900 * Disable clock gating on th GCFG unit to prevent a delay
4901 * in the reporting of vblank events.
4902 */
4e8c84a5
JB		 4903 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4904
4905 /* Conservative clock gating settings for now */
4906 I915_WRITE(0x9400, 0xffffffff);
4907 I915_WRITE(0x9404, 0xffffffff);
4908 I915_WRITE(0x9408, 0xffffffff);
4909 I915_WRITE(0x940c, 0xffffffff);
4910 I915_WRITE(0x9410, 0xffffffff);
4911 I915_WRITE(0x9414, 0xffffffff);
4912 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4913}
4914
1fa61106 4915static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4916{
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918 uint32_t dspclk_gate;
4919
4920 I915_WRITE(RENCLK_GATE_D1, 0);
4921 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4922 GS_UNIT_CLOCK_GATE_DISABLE |
4923 CL_UNIT_CLOCK_GATE_DISABLE);
4924 I915_WRITE(RAMCLK_GATE_D, 0);
4925 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4926 OVRUNIT_CLOCK_GATE_DISABLE |
4927 OVCUNIT_CLOCK_GATE_DISABLE;
4928 if (IS_GM45(dev))
4929 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4930 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4931
4932 /* WaDisableRenderCachePipelinedFlush */
4933 I915_WRITE(CACHE_MODE_0,
4934 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 4935
0e088b8f 4936 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 4937}
4938
1fa61106 4939static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4940{
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4942
4943 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4944 I915_WRITE(RENCLK_GATE_D2, 0);
4945 I915_WRITE(DSPCLK_GATE_D, 0);
4946 I915_WRITE(RAMCLK_GATE_D, 0);
4947 I915_WRITE16(DEUC, 0);
20f94967
VS		 4948 I915_WRITE(MI_ARB_STATE,
4949 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4950}
4951
1fa61106 4952static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4953{
4954 struct drm_i915_private *dev_priv = dev->dev_private;
4955
4956 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4957 I965_RCC_CLOCK_GATE_DISABLE |
4958 I965_RCPB_CLOCK_GATE_DISABLE |
4959 I965_ISC_CLOCK_GATE_DISABLE |
4960 I965_FBC_CLOCK_GATE_DISABLE);
4961 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 4962 I915_WRITE(MI_ARB_STATE,
4963 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4964}
4965
1fa61106 4966static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4967{
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 u32 dstate = I915_READ(D_STATE);
4970
4971 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4972 DSTATE_DOT_CLOCK_GATING;
4973 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4974
4975 if (IS_PINEVIEW(dev))
4976 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4977
4978 /* IIR "flip pending" means done if this bit is set */
4979 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4980}
4981
1fa61106 4982static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4983{
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985
4986 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4987}
4988
1fa61106 4989static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4990{
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992
4993 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4994}
4995
6f1d69b0
ED		 4996void intel_init_clock_gating(struct drm_device *dev)
4997{
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999
5000 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5001}
5002
7d708ee4
ID		 5003void intel_suspend_hw(struct drm_device *dev)
5004{
5005 if (HAS_PCH_LPT(dev))
5006 lpt_suspend_hw(dev);
5007}
5008
15d199ea
PZ		 5009/**
5010 * We should only use the power well if we explicitly asked the hardware to
5011 * enable it, so check if it's enabled and also check if we've requested it to
5012 * be enabled.
5013 */
b97186f0
PZ		 5014bool intel_display_power_enabled(struct drm_device *dev,
5015 enum intel_display_power_domain domain)
15d199ea
PZ		 5016{
5017 struct drm_i915_private *dev_priv = dev->dev_private;
5018
b97186f0
PZ		 5019 if (!HAS_POWER_WELL(dev))
5020 return true;
5021
5022 switch (domain) {
5023 case POWER_DOMAIN_PIPE_A:
5024 case POWER_DOMAIN_TRANSCODER_EDP:
5025 return true;
5026 case POWER_DOMAIN_PIPE_B:
5027 case POWER_DOMAIN_PIPE_C:
5028 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5029 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5030 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5031 case POWER_DOMAIN_TRANSCODER_A:
5032 case POWER_DOMAIN_TRANSCODER_B:
5033 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5034 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5035 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5036 default:
5037 BUG();
5038 }
15d199ea
PZ		 5039}
5040
a38911a3 5041static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5042{
5043 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5044 bool is_enabled, enable_requested;
5045 uint32_t tmp;
d0d3e513 5046
fa42e23c
PZ		 5047 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5048 is_enabled = tmp & HSW_PWR_WELL_STATE;
5049 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5050
fa42e23c
PZ		 5051 if (enable) {
5052 if (!enable_requested)
5053 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5054
fa42e23c
PZ		 5055 if (!is_enabled) {
5056 DRM_DEBUG_KMS("Enabling power well\n");
5057 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5058 HSW_PWR_WELL_STATE), 20))
5059 DRM_ERROR("Timeout enabling power well\n");
5060 }
5061 } else {
5062 if (enable_requested) {
5063 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5064 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5065 }
5066 }
fa42e23c 5067}
d0d3e513 5068
a38911a3
WX		 5069static struct i915_power_well *hsw_pwr;
5070
5071/* Display audio driver power well request */
5072void i915_request_power_well(void)
5073{
5074 if (WARN_ON(!hsw_pwr))
5075 return;
5076
5077 spin_lock_irq(&hsw_pwr->lock);
5078 if (!hsw_pwr->count++ &&
5079 !hsw_pwr->i915_request)
5080 __intel_set_power_well(hsw_pwr->device, true);
5081 spin_unlock_irq(&hsw_pwr->lock);
5082}
5083EXPORT_SYMBOL_GPL(i915_request_power_well);
5084
5085/* Display audio driver power well release */
5086void i915_release_power_well(void)
5087{
5088 if (WARN_ON(!hsw_pwr))
5089 return;
5090
5091 spin_lock_irq(&hsw_pwr->lock);
5092 WARN_ON(!hsw_pwr->count);
5093 if (!--hsw_pwr->count &&
5094 !hsw_pwr->i915_request)
5095 __intel_set_power_well(hsw_pwr->device, false);
5096 spin_unlock_irq(&hsw_pwr->lock);
5097}
5098EXPORT_SYMBOL_GPL(i915_release_power_well);
5099
5100int i915_init_power_well(struct drm_device *dev)
5101{
5102 struct drm_i915_private *dev_priv = dev->dev_private;
5103
5104 hsw_pwr = &dev_priv->power_well;
5105
5106 hsw_pwr->device = dev;
5107 spin_lock_init(&hsw_pwr->lock);
5108 hsw_pwr->count = 0;
5109
5110 return 0;
5111}
5112
5113void i915_remove_power_well(struct drm_device *dev)
5114{
5115 hsw_pwr = NULL;
5116}
5117
5118void intel_set_power_well(struct drm_device *dev, bool enable)
5119{
5120 struct drm_i915_private *dev_priv = dev->dev_private;
5121 struct i915_power_well *power_well = &dev_priv->power_well;
5122
5123 if (!HAS_POWER_WELL(dev))
5124 return;
5125
5126 if (!i915_disable_power_well && !enable)
5127 return;
5128
5129 spin_lock_irq(&power_well->lock);
5130 power_well->i915_request = enable;
5131
5132 /* only reject "disable" power well request */
5133 if (power_well->count && !enable) {
5134 spin_unlock_irq(&power_well->lock);
5135 return;
5136 }
5137
5138 __intel_set_power_well(dev, enable);
5139 spin_unlock_irq(&power_well->lock);
5140}
5141
fa42e23c
PZ		 5142/*
5143 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5144 * when not needed anymore. We have 4 registers that can request the power well
5145 * to be enabled, and it will only be disabled if none of the registers is
5146 * requesting it to be enabled.
d0d3e513 5147 */
fa42e23c 5148void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5149{
5150 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5151
86d52df6 5152 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5153 return;
5154
fa42e23c
PZ		 5155 /* For now, we need the power well to be always enabled. */
5156 intel_set_power_well(dev, true);
d0d3e513 5157
fa42e23c
PZ		 5158 /* We're taking over the BIOS, so clear any requests made by it since
5159 * the driver is in charge now. */
5160 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5161 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5162}
5163
1fa61106
ED		 5164/* Set up chip specific power management-related functions */
5165void intel_init_pm(struct drm_device *dev)
5166{
5167 struct drm_i915_private *dev_priv = dev->dev_private;
5168
5169 if (I915_HAS_FBC(dev)) {
5170 if (HAS_PCH_SPLIT(dev)) {
5171 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5172 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5173 dev_priv->display.enable_fbc =
5174 gen7_enable_fbc;
5175 else
5176 dev_priv->display.enable_fbc =
5177 ironlake_enable_fbc;
1fa61106
ED		 5178 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5179 } else if (IS_GM45(dev)) {
5180 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5181 dev_priv->display.enable_fbc = g4x_enable_fbc;
5182 dev_priv->display.disable_fbc = g4x_disable_fbc;
5183 } else if (IS_CRESTLINE(dev)) {
5184 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5185 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5186 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5187 }
5188 /* 855GM needs testing */
5189 }
5190
c921aba8
DV		 5191 /* For cxsr */
5192 if (IS_PINEVIEW(dev))
5193 i915_pineview_get_mem_freq(dev);
5194 else if (IS_GEN5(dev))
5195 i915_ironlake_get_mem_freq(dev);
5196
1fa61106
ED		 5197 /* For FIFO watermark updates */
5198 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 5199 if (IS_GEN5(dev)) {
5200 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5201 dev_priv->display.update_wm = ironlake_update_wm;
5202 else {
5203 DRM_DEBUG_KMS("Failed to get proper latency. "
5204 "Disable CxSR\n");
5205 dev_priv->display.update_wm = NULL;
5206 }
5207 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5208 } else if (IS_GEN6(dev)) {
5209 if (SNB_READ_WM0_LATENCY()) {
5210 dev_priv->display.update_wm = sandybridge_update_wm;
5211 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5212 } else {
5213 DRM_DEBUG_KMS("Failed to read display plane latency. "
5214 "Disable CxSR\n");
5215 dev_priv->display.update_wm = NULL;
5216 }
5217 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5218 } else if (IS_IVYBRIDGE(dev)) {
1fa61106 5219 if (SNB_READ_WM0_LATENCY()) {
c43d0188 5220 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5221 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5222 } else {
5223 DRM_DEBUG_KMS("Failed to read display plane latency. "
5224 "Disable CxSR\n");
5225 dev_priv->display.update_wm = NULL;
5226 }
5227 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5228 } else if (IS_HASWELL(dev)) {
3e1f7266 5229 if (I915_READ64(MCH_SSKPD)) {
1011d8c4 5230 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5231 dev_priv->display.update_sprite_wm =
5232 haswell_update_sprite_wm;
6b8a5eeb
ED		 5233 } else {
5234 DRM_DEBUG_KMS("Failed to read display plane latency. "
5235 "Disable CxSR\n");
5236 dev_priv->display.update_wm = NULL;
5237 }
cad2a2d7 5238 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5239 } else
5240 dev_priv->display.update_wm = NULL;
5241 } else if (IS_VALLEYVIEW(dev)) {
5242 dev_priv->display.update_wm = valleyview_update_wm;
5243 dev_priv->display.init_clock_gating =
5244 valleyview_init_clock_gating;
1fa61106
ED		 5245 } else if (IS_PINEVIEW(dev)) {
5246 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5247 dev_priv->is_ddr3,
5248 dev_priv->fsb_freq,
5249 dev_priv->mem_freq)) {
5250 DRM_INFO("failed to find known CxSR latency "
5251 "(found ddr%s fsb freq %d, mem freq %d), "
5252 "disabling CxSR\n",
5253 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5254 dev_priv->fsb_freq, dev_priv->mem_freq);
5255 /* Disable CxSR and never update its watermark again */
5256 pineview_disable_cxsr(dev);
5257 dev_priv->display.update_wm = NULL;
5258 } else
5259 dev_priv->display.update_wm = pineview_update_wm;
5260 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5261 } else if (IS_G4X(dev)) {
5262 dev_priv->display.update_wm = g4x_update_wm;
5263 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5264 } else if (IS_GEN4(dev)) {
5265 dev_priv->display.update_wm = i965_update_wm;
5266 if (IS_CRESTLINE(dev))
5267 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5268 else if (IS_BROADWATER(dev))
5269 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5270 } else if (IS_GEN3(dev)) {
5271 dev_priv->display.update_wm = i9xx_update_wm;
5272 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5273 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5274 } else if (IS_I865G(dev)) {
5275 dev_priv->display.update_wm = i830_update_wm;
5276 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5277 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5278 } else if (IS_I85X(dev)) {
5279 dev_priv->display.update_wm = i9xx_update_wm;
5280 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5281 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5282 } else {
5283 dev_priv->display.update_wm = i830_update_wm;
5284 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5285 if (IS_845G(dev))
5286 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5287 else
5288 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5289 }
5290}
5291
6590190d
ED		 5292static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
5293{
5294 u32 gt_thread_status_mask;
5295
5296 if (IS_HASWELL(dev_priv->dev))
5297 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
5298 else
5299 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
5300
5301 /* w/a for a sporadic read returning 0 by waiting for the GT
5302 * thread to wake up.
5303 */
5304 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
5305 DRM_ERROR("GT thread status wait timed out\n");
5306}
5307
16995a9f
CW		 5308static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
5309{
5310 I915_WRITE_NOTRACE(FORCEWAKE, 0);
5311 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
5312}
5313
6590190d
ED		 5314static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5315{
ebd37ce1 5316 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
057d3860 5317 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5318 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5319
30771e16 5320 I915_WRITE_NOTRACE(FORCEWAKE, 1);
8dee3eea 5321 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 5322
ebd37ce1 5323 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
057d3860 5324 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5325 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5326
8693a824 5327 /* WaRsForcewakeWaitTC0:snb */
6590190d
ED		 5328 __gen6_gt_wait_for_thread_c0(dev_priv);
5329}
5330
16995a9f
CW		 5331static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
5332{
5333 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5334 /* something from same cacheline, but !FORCEWAKE_MT */
5335 POSTING_READ(ECOBUS);
16995a9f
CW		 5336}
5337
6590190d
ED		 5338static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
5339{
5340 u32 forcewake_ack;
5341
5342 if (IS_HASWELL(dev_priv->dev))
5343 forcewake_ack = FORCEWAKE_ACK_HSW;
5344 else
5345 forcewake_ack = FORCEWAKE_MT_ACK;
5346
83983c8b 5347 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
057d3860 5348 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5349 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5350
c5836c27 5351 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5352 /* something from same cacheline, but !FORCEWAKE_MT */
5353 POSTING_READ(ECOBUS);
6590190d 5354
83983c8b 5355 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
057d3860 5356 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5357 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d 5358
8693a824 5359 /* WaRsForcewakeWaitTC0:ivb,hsw */
6590190d
ED		 5360 __gen6_gt_wait_for_thread_c0(dev_priv);
5361}
5362
5363/*
5364 * Generally this is called implicitly by the register read function. However,
5365 * if some sequence requires the GT to not power down then this function should
5366 * be called at the beginning of the sequence followed by a call to
5367 * gen6_gt_force_wake_put() at the end of the sequence.
5368 */
5369void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
5370{
5371 unsigned long irqflags;
5372
5373 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5374 if (dev_priv->forcewake_count++ == 0)
5375 dev_priv->gt.force_wake_get(dev_priv);
5376 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5377}
5378
5379void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
5380{
5381 u32 gtfifodbg;
5382 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
5383 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
5384 "MMIO read or write has been dropped %x\n", gtfifodbg))
5385 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
5386}
5387
5388static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5389{
5390 I915_WRITE_NOTRACE(FORCEWAKE, 0);
b5144075
JN		 5391 /* something from same cacheline, but !FORCEWAKE */
5392 POSTING_READ(ECOBUS);
6590190d
ED		 5393 gen6_gt_check_fifodbg(dev_priv);
5394}
5395
5396static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
5397{
c5836c27 5398 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
b5144075
JN		 5399 /* something from same cacheline, but !FORCEWAKE_MT */
5400 POSTING_READ(ECOBUS);
6590190d
ED		 5401 gen6_gt_check_fifodbg(dev_priv);
5402}
5403
5404/*
5405 * see gen6_gt_force_wake_get()
5406 */
5407void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
5408{
5409 unsigned long irqflags;
5410
5411 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
5412 if (--dev_priv->forcewake_count == 0)
5413 dev_priv->gt.force_wake_put(dev_priv);
5414 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
5415}
5416
5417int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
5418{
5419 int ret = 0;
5420
5421 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
5422 int loop = 500;
5423 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5424 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
5425 udelay(10);
5426 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
5427 }
5428 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
5429 ++ret;
5430 dev_priv->gt_fifo_count = fifo;
5431 }
5432 dev_priv->gt_fifo_count--;
5433
5434 return ret;
5435}
5436
16995a9f
CW		 5437static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
5438{
5439 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 5440 /* something from same cacheline, but !FORCEWAKE_VLV */
5441 POSTING_READ(FORCEWAKE_ACK_VLV);
16995a9f
CW		 5442}
5443
6590190d
ED		 5444static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
5445{
83983c8b 5446 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
057d3860 5447 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 5448 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 5449
c5836c27 5450 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5451 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5452 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 5453
83983c8b 5454 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
057d3860 5455 FORCEWAKE_ACK_TIMEOUT_MS))
ed5de399
JB		 5456 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
5457
5458 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
5459 FORCEWAKE_KERNEL),
5460 FORCEWAKE_ACK_TIMEOUT_MS))
5461 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
6590190d 5462
8693a824 5463 /* WaRsForcewakeWaitTC0:vlv */
6590190d
ED		 5464 __gen6_gt_wait_for_thread_c0(dev_priv);
5465}
5466
5467static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
5468{
c5836c27 5469 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 5470 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
5471 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5472 /* The below doubles as a POSTING_READ */
5ab140a4 5473 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 5474}
5475
16995a9f
CW		 5476void intel_gt_reset(struct drm_device *dev)
5477{
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479
5480 if (IS_VALLEYVIEW(dev)) {
5481 vlv_force_wake_reset(dev_priv);
5482 } else if (INTEL_INFO(dev)->gen >= 6) {
5483 __gen6_gt_force_wake_reset(dev_priv);
5484 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5485 __gen6_gt_force_wake_mt_reset(dev_priv);
5486 }
5487}
5488
6590190d
ED		 5489void intel_gt_init(struct drm_device *dev)
5490{
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492
5493 spin_lock_init(&dev_priv->gt_lock);
5494
16995a9f
CW		 5495 intel_gt_reset(dev);
5496
6590190d
ED		 5497 if (IS_VALLEYVIEW(dev)) {
5498 dev_priv->gt.force_wake_get = vlv_force_wake_get;
5499 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 5500 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5501 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
5502 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
5503 } else if (IS_GEN6(dev)) {
6590190d
ED		 5504 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
5505 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 5506 }
1a01ab3b
JB		 5507 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5508 intel_gen6_powersave_work);
6590190d
ED		 5509}
5510
42c0526c
BW		 5511int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5512{
4fc688ce 5513 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5514
5515 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5516 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5517 return -EAGAIN;
5518 }
5519
5520 I915_WRITE(GEN6_PCODE_DATA, *val);
5521 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5522
5523 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5524 500)) {
5525 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5526 return -ETIMEDOUT;
5527 }
5528
5529 *val = I915_READ(GEN6_PCODE_DATA);
5530 I915_WRITE(GEN6_PCODE_DATA, 0);
5531
5532 return 0;
5533}
5534
5535int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5536{
4fc688ce 5537 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5538
5539 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5540 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5541 return -EAGAIN;
5542 }
5543
5544 I915_WRITE(GEN6_PCODE_DATA, val);
5545 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5546
5547 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5548 500)) {
5549 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5550 return -ETIMEDOUT;
5551 }
5552
5553 I915_WRITE(GEN6_PCODE_DATA, 0);
5554
5555 return 0;
5556}
a0e4e199 5557
855ba3be
JB		 5558int vlv_gpu_freq(int ddr_freq, int val)
5559{
5560 int mult, base;
5561
5562 switch (ddr_freq) {
5563 case 800:
5564 mult = 20;
5565 base = 120;
5566 break;
5567 case 1066:
5568 mult = 22;
5569 base = 133;
5570 break;
5571 case 1333:
5572 mult = 21;
5573 base = 125;
5574 break;
5575 default:
5576 return -1;
5577 }
5578
5579 return ((val - 0xbd) * mult) + base;
5580}
5581
5582int vlv_freq_opcode(int ddr_freq, int val)
5583{
5584 int mult, base;
5585
5586 switch (ddr_freq) {
5587 case 800:
5588 mult = 20;
5589 base = 120;
5590 break;
5591 case 1066:
5592 mult = 22;
5593 base = 133;
5594 break;
5595 case 1333:
5596 mult = 21;
5597 base = 125;
5598 break;
5599 default:
5600 return -1;
5601 }
5602
5603 val /= mult;
5604 val -= base / mult;
5605 val += 0xbd;
5606
5607 if (val > 0xea)
5608 val = 0xea;
5609
5610 return val;
5611}
5612
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