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drm/i915: Use the watermark latency values from dev_priv for ILK/SNB/IVB too
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
3490ea5d
CW		 46static bool intel_crtc_active(struct drm_crtc *crtc)
47{
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
50 */
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
52}
53
1fa61106 54static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
57 u32 fbc_ctl;
58
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
62 return;
63
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
66
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
70 return;
71 }
72
73 DRM_DEBUG_KMS("disabled FBC\n");
74}
75
1fa61106 76static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 77{
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84 int cfb_pitch;
85 int plane, i;
86 u32 fbc_ctl, fbc_ctl2;
87
5c3fe8b0 88 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
91
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
95
96 /* Clear old tags */
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
99
100 /* Set it up... */
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
102 fbc_ctl2 |= plane;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
105
106 /* enable it... */
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
108 if (IS_I945GM(dev))
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
114
84f44ce7
VS		 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
116 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 117}
118
1fa61106 119static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
124}
125
1fa61106 126static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 127{
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
136 u32 dpfc_ctl;
137
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
141
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
146
147 /* enable it... */
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
149
84f44ce7 150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 151}
152
1fa61106 153static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
156 u32 dpfc_ctl;
157
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
163
164 DRM_DEBUG_KMS("disabled FBC\n");
165 }
166}
167
1fa61106 168static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
173}
174
175static void sandybridge_blit_fbc_update(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 u32 blt_ecoskpd;
179
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
193}
194
1fa61106 195static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 196{
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
205 u32 dpfc_ctl;
206
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
214
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 219 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 220 /* enable it... */
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
222
223 if (IS_GEN6(dev)) {
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
228 }
229
84f44ce7 230 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 231}
232
1fa61106 233static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 u32 dpfc_ctl;
237
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
243
b74ea102 244 if (IS_IVYBRIDGE(dev))
7dd23ba0 245 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 246 I915_WRITE(ILK_DSPCLK_GATE_D,
247 I915_READ(ILK_DSPCLK_GATE_D) &
248 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
249
d89f2071 250 if (IS_HASWELL(dev))
7dd23ba0 251 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 252 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
253 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
254 ~HSW_DPFC_GATING_DISABLE);
255
85208be0
ED		 256 DRM_DEBUG_KMS("disabled FBC\n");
257 }
258}
259
1fa61106 260static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263
264 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
265}
266
abe959c7
RV		 267static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
268{
269 struct drm_device *dev = crtc->dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 struct drm_framebuffer *fb = crtc->fb;
272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
273 struct drm_i915_gem_object *obj = intel_fb->obj;
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
275
f343c5f6 276 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 277
278 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
279 IVB_DPFC_CTL_FENCE_EN |
280 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
281
891348b2 282 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 283 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 284 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 286 I915_WRITE(ILK_DSPCLK_GATE_D,
287 I915_READ(ILK_DSPCLK_GATE_D) |
288 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 289 } else {
7dd23ba0 290 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 291 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
292 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 293 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 294 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
295 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
296 HSW_DPFC_GATING_DISABLE);
891348b2 297 }
b74ea102 298
abe959c7
RV		 299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
302
303 sandybridge_blit_fbc_update(dev);
304
305 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
306}
307
85208be0
ED		 308bool intel_fbc_enabled(struct drm_device *dev)
309{
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 if (!dev_priv->display.fbc_enabled)
313 return false;
314
315 return dev_priv->display.fbc_enabled(dev);
316}
317
318static void intel_fbc_work_fn(struct work_struct *__work)
319{
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 mutex_lock(&dev->struct_mutex);
5c3fe8b0 327 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 328 /* Double check that we haven't switched fb without cancelling
329 * the prior work.
330 */
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
333 work->interval);
334
5c3fe8b0
BW		 335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 338 }
339
5c3fe8b0 340 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 341 }
342 mutex_unlock(&dev->struct_mutex);
343
344 kfree(work);
345}
346
347static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
348{
5c3fe8b0 349 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 350 return;
351
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
353
354 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 356 * entirely asynchronously.
357 */
5c3fe8b0 358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 359 /* tasklet was killed before being run, clean up */
5c3fe8b0 360 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 361
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
365 * necessary to run.
366 */
5c3fe8b0 367 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 368}
369
b63fb44c 370static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 371{
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375
376 if (!dev_priv->display.enable_fbc)
377 return;
378
379 intel_cancel_fbc_work(dev_priv);
380
381 work = kzalloc(sizeof *work, GFP_KERNEL);
382 if (work == NULL) {
6cdcb5e7 383 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
f85da868 461 unsigned int max_hdisplay, max_vdisplay;
85208be0 462
29ebf90f
CW		 463 if (!I915_HAS_FBC(dev)) {
464 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 465 return;
29ebf90f 466 }
85208be0 467
29ebf90f
CW		 468 if (!i915_powersave) {
469 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
470 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 471 return;
29ebf90f 472 }
85208be0
ED		 473
474 /*
475 * If FBC is already on, we just have to verify that we can
476 * keep it that way...
477 * Need to disable if:
478 * - more than one pipe is active
479 * - changing FBC params (stride, fence, mode)
480 * - new fb is too large to fit in compressed buffer
481 * - going to an unsupported config (interlace, pixel multiply, etc.)
482 */
483 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 484 if (intel_crtc_active(tmp_crtc) &&
485 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0 486 if (crtc) {
29ebf90f
CW		 487 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
488 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 489 goto out_disable;
490 }
491 crtc = tmp_crtc;
492 }
493 }
494
495 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 496 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
497 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 498 goto out_disable;
499 }
500
501 intel_crtc = to_intel_crtc(crtc);
502 fb = crtc->fb;
503 intel_fb = to_intel_framebuffer(fb);
504 obj = intel_fb->obj;
505
8a5729a3
DL		 506 if (i915_enable_fbc < 0 &&
507 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 508 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
509 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 510 goto out_disable;
85208be0 511 }
8a5729a3 512 if (!i915_enable_fbc) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
514 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 515 goto out_disable;
516 }
85208be0
ED		 517 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
518 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 519 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
520 DRM_DEBUG_KMS("mode incompatible with compression, "
521 "disabling\n");
85208be0
ED		 522 goto out_disable;
523 }
f85da868
PZ		 524
525 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
526 max_hdisplay = 4096;
527 max_vdisplay = 2048;
528 } else {
529 max_hdisplay = 2048;
530 max_vdisplay = 1536;
531 }
532 if ((crtc->mode.hdisplay > max_hdisplay) ||
533 (crtc->mode.vdisplay > max_vdisplay)) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
535 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 536 goto out_disable;
537 }
891348b2
RV		 538 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
539 intel_crtc->plane != 0) {
29ebf90f
CW		 540 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
541 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 542 goto out_disable;
543 }
544
545 /* The use of a CPU fence is mandatory in order to detect writes
546 * by the CPU to the scanout and trigger updates to the FBC.
547 */
548 if (obj->tiling_mode != I915_TILING_X ||
549 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 550 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
551 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 552 goto out_disable;
553 }
554
555 /* If the kernel debugger is active, always disable compression */
556 if (in_dbg_master())
557 goto out_disable;
558
11be49eb 559 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 560 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
561 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 562 goto out_disable;
563 }
564
85208be0
ED		 565 /* If the scanout has not changed, don't modify the FBC settings.
566 * Note that we make the fundamental assumption that the fb->obj
567 * cannot be unpinned (and have its GTT offset and fence revoked)
568 * without first being decoupled from the scanout and FBC disabled.
569 */
5c3fe8b0
BW		 570 if (dev_priv->fbc.plane == intel_crtc->plane &&
571 dev_priv->fbc.fb_id == fb->base.id &&
572 dev_priv->fbc.y == crtc->y)
85208be0
ED		 573 return;
574
575 if (intel_fbc_enabled(dev)) {
576 /* We update FBC along two paths, after changing fb/crtc
577 * configuration (modeswitching) and after page-flipping
578 * finishes. For the latter, we know that not only did
579 * we disable the FBC at the start of the page-flip
580 * sequence, but also more than one vblank has passed.
581 *
582 * For the former case of modeswitching, it is possible
583 * to switch between two FBC valid configurations
584 * instantaneously so we do need to disable the FBC
585 * before we can modify its control registers. We also
586 * have to wait for the next vblank for that to take
587 * effect. However, since we delay enabling FBC we can
588 * assume that a vblank has passed since disabling and
589 * that we can safely alter the registers in the deferred
590 * callback.
591 *
592 * In the scenario that we go from a valid to invalid
593 * and then back to valid FBC configuration we have
594 * no strict enforcement that a vblank occurred since
595 * disabling the FBC. However, along all current pipe
596 * disabling paths we do need to wait for a vblank at
597 * some point. And we wait before enabling FBC anyway.
598 */
599 DRM_DEBUG_KMS("disabling active FBC for update\n");
600 intel_disable_fbc(dev);
601 }
602
603 intel_enable_fbc(crtc, 500);
29ebf90f 604 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 605 return;
606
607out_disable:
608 /* Multiple disables should be harmless */
609 if (intel_fbc_enabled(dev)) {
610 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
611 intel_disable_fbc(dev);
612 }
11be49eb 613 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 614}
615
c921aba8
DV		 616static void i915_pineview_get_mem_freq(struct drm_device *dev)
617{
618 drm_i915_private_t *dev_priv = dev->dev_private;
619 u32 tmp;
620
621 tmp = I915_READ(CLKCFG);
622
623 switch (tmp & CLKCFG_FSB_MASK) {
624 case CLKCFG_FSB_533:
625 dev_priv->fsb_freq = 533; /* 133*4 */
626 break;
627 case CLKCFG_FSB_800:
628 dev_priv->fsb_freq = 800; /* 200*4 */
629 break;
630 case CLKCFG_FSB_667:
631 dev_priv->fsb_freq = 667; /* 167*4 */
632 break;
633 case CLKCFG_FSB_400:
634 dev_priv->fsb_freq = 400; /* 100*4 */
635 break;
636 }
637
638 switch (tmp & CLKCFG_MEM_MASK) {
639 case CLKCFG_MEM_533:
640 dev_priv->mem_freq = 533;
641 break;
642 case CLKCFG_MEM_667:
643 dev_priv->mem_freq = 667;
644 break;
645 case CLKCFG_MEM_800:
646 dev_priv->mem_freq = 800;
647 break;
648 }
649
650 /* detect pineview DDR3 setting */
651 tmp = I915_READ(CSHRDDR3CTL);
652 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
653}
654
655static void i915_ironlake_get_mem_freq(struct drm_device *dev)
656{
657 drm_i915_private_t *dev_priv = dev->dev_private;
658 u16 ddrpll, csipll;
659
660 ddrpll = I915_READ16(DDRMPLL1);
661 csipll = I915_READ16(CSIPLL0);
662
663 switch (ddrpll & 0xff) {
664 case 0xc:
665 dev_priv->mem_freq = 800;
666 break;
667 case 0x10:
668 dev_priv->mem_freq = 1066;
669 break;
670 case 0x14:
671 dev_priv->mem_freq = 1333;
672 break;
673 case 0x18:
674 dev_priv->mem_freq = 1600;
675 break;
676 default:
677 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
678 ddrpll & 0xff);
679 dev_priv->mem_freq = 0;
680 break;
681 }
682
20e4d407 683 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 684
685 switch (csipll & 0x3ff) {
686 case 0x00c:
687 dev_priv->fsb_freq = 3200;
688 break;
689 case 0x00e:
690 dev_priv->fsb_freq = 3733;
691 break;
692 case 0x010:
693 dev_priv->fsb_freq = 4266;
694 break;
695 case 0x012:
696 dev_priv->fsb_freq = 4800;
697 break;
698 case 0x014:
699 dev_priv->fsb_freq = 5333;
700 break;
701 case 0x016:
702 dev_priv->fsb_freq = 5866;
703 break;
704 case 0x018:
705 dev_priv->fsb_freq = 6400;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
709 csipll & 0x3ff);
710 dev_priv->fsb_freq = 0;
711 break;
712 }
713
714 if (dev_priv->fsb_freq == 3200) {
20e4d407 715 dev_priv->ips.c_m = 0;
c921aba8 716 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 717 dev_priv->ips.c_m = 1;
c921aba8 718 } else {
20e4d407 719 dev_priv->ips.c_m = 2;
c921aba8
DV		 720 }
721}
722
b445e3b0
ED		 723static const struct cxsr_latency cxsr_latency_table[] = {
724 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
725 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
726 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
727 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
728 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
729
730 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
731 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
732 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
733 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
734 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
735
736 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
737 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
738 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
739 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
740 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
741
742 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
743 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
744 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
745 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
746 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
747
748 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
749 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
750 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
751 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
752 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
753
754 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
755 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
756 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
757 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
758 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
759};
760
63c62275 761static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 762 int is_ddr3,
763 int fsb,
764 int mem)
765{
766 const struct cxsr_latency *latency;
767 int i;
768
769 if (fsb == 0 || mem == 0)
770 return NULL;
771
772 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
773 latency = &cxsr_latency_table[i];
774 if (is_desktop == latency->is_desktop &&
775 is_ddr3 == latency->is_ddr3 &&
776 fsb == latency->fsb_freq && mem == latency->mem_freq)
777 return latency;
778 }
779
780 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
781
782 return NULL;
783}
784
1fa61106 785static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 786{
787 struct drm_i915_private *dev_priv = dev->dev_private;
788
789 /* deactivate cxsr */
790 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
791}
792
793/*
794 * Latency for FIFO fetches is dependent on several factors:
795 * - memory configuration (speed, channels)
796 * - chipset
797 * - current MCH state
798 * It can be fairly high in some situations, so here we assume a fairly
799 * pessimal value. It's a tradeoff between extra memory fetches (if we
800 * set this value too high, the FIFO will fetch frequently to stay full)
801 * and power consumption (set it too low to save power and we might see
802 * FIFO underruns and display "flicker").
803 *
804 * A value of 5us seems to be a good balance; safe for very low end
805 * platforms but not overly aggressive on lower latency configs.
806 */
807static const int latency_ns = 5000;
808
1fa61106 809static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 uint32_t dsparb = I915_READ(DSPARB);
813 int size;
814
815 size = dsparb & 0x7f;
816 if (plane)
817 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
818
819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
820 plane ? "B" : "A", size);
821
822 return size;
823}
824
1fa61106 825static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 uint32_t dsparb = I915_READ(DSPARB);
829 int size;
830
831 size = dsparb & 0x1ff;
832 if (plane)
833 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
834 size >>= 1; /* Convert to cachelines */
835
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
837 plane ? "B" : "A", size);
838
839 return size;
840}
841
1fa61106 842static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 843{
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 uint32_t dsparb = I915_READ(DSPARB);
846 int size;
847
848 size = dsparb & 0x7f;
849 size >>= 2; /* Convert to cachelines */
850
851 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
852 plane ? "B" : "A",
853 size);
854
855 return size;
856}
857
1fa61106 858static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
862 int size;
863
864 size = dsparb & 0x7f;
865 size >>= 1; /* Convert to cachelines */
866
867 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
868 plane ? "B" : "A", size);
869
870 return size;
871}
872
873/* Pineview has different values for various configs */
874static const struct intel_watermark_params pineview_display_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_display_hplloff_wm = {
882 PINEVIEW_DISPLAY_FIFO,
883 PINEVIEW_MAX_WM,
884 PINEVIEW_DFT_HPLLOFF_WM,
885 PINEVIEW_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params pineview_cursor_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE,
894};
895static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
896 PINEVIEW_CURSOR_FIFO,
897 PINEVIEW_CURSOR_MAX_WM,
898 PINEVIEW_CURSOR_DFT_WM,
899 PINEVIEW_CURSOR_GUARD_WM,
900 PINEVIEW_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params g4x_wm_info = {
903 G4X_FIFO_SIZE,
904 G4X_MAX_WM,
905 G4X_MAX_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params g4x_cursor_wm_info = {
910 I965_CURSOR_FIFO,
911 I965_CURSOR_MAX_WM,
912 I965_CURSOR_DFT_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_wm_info = {
917 VALLEYVIEW_FIFO_SIZE,
918 VALLEYVIEW_MAX_WM,
919 VALLEYVIEW_MAX_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params valleyview_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 VALLEYVIEW_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 G4X_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i965_cursor_wm_info = {
931 I965_CURSOR_FIFO,
932 I965_CURSOR_MAX_WM,
933 I965_CURSOR_DFT_WM,
934 2,
935 I915_FIFO_LINE_SIZE,
936};
937static const struct intel_watermark_params i945_wm_info = {
938 I945_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
944static const struct intel_watermark_params i915_wm_info = {
945 I915_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I915_FIFO_LINE_SIZE
950};
951static const struct intel_watermark_params i855_wm_info = {
952 I855GM_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958static const struct intel_watermark_params i830_wm_info = {
959 I830_FIFO_SIZE,
960 I915_MAX_WM,
961 1,
962 2,
963 I830_FIFO_LINE_SIZE
964};
965
966static const struct intel_watermark_params ironlake_display_wm_info = {
967 ILK_DISPLAY_FIFO,
968 ILK_DISPLAY_MAXWM,
969 ILK_DISPLAY_DFTWM,
970 2,
971 ILK_FIFO_LINE_SIZE
972};
973static const struct intel_watermark_params ironlake_cursor_wm_info = {
974 ILK_CURSOR_FIFO,
975 ILK_CURSOR_MAXWM,
976 ILK_CURSOR_DFTWM,
977 2,
978 ILK_FIFO_LINE_SIZE
979};
980static const struct intel_watermark_params ironlake_display_srwm_info = {
981 ILK_DISPLAY_SR_FIFO,
982 ILK_DISPLAY_MAX_SRWM,
983 ILK_DISPLAY_DFT_SRWM,
984 2,
985 ILK_FIFO_LINE_SIZE
986};
987static const struct intel_watermark_params ironlake_cursor_srwm_info = {
988 ILK_CURSOR_SR_FIFO,
989 ILK_CURSOR_MAX_SRWM,
990 ILK_CURSOR_DFT_SRWM,
991 2,
992 ILK_FIFO_LINE_SIZE
993};
994
995static const struct intel_watermark_params sandybridge_display_wm_info = {
996 SNB_DISPLAY_FIFO,
997 SNB_DISPLAY_MAXWM,
998 SNB_DISPLAY_DFTWM,
999 2,
1000 SNB_FIFO_LINE_SIZE
1001};
1002static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003 SNB_CURSOR_FIFO,
1004 SNB_CURSOR_MAXWM,
1005 SNB_CURSOR_DFTWM,
1006 2,
1007 SNB_FIFO_LINE_SIZE
1008};
1009static const struct intel_watermark_params sandybridge_display_srwm_info = {
1010 SNB_DISPLAY_SR_FIFO,
1011 SNB_DISPLAY_MAX_SRWM,
1012 SNB_DISPLAY_DFT_SRWM,
1013 2,
1014 SNB_FIFO_LINE_SIZE
1015};
1016static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1017 SNB_CURSOR_SR_FIFO,
1018 SNB_CURSOR_MAX_SRWM,
1019 SNB_CURSOR_DFT_SRWM,
1020 2,
1021 SNB_FIFO_LINE_SIZE
1022};
1023
1024
1025/**
1026 * intel_calculate_wm - calculate watermark level
1027 * @clock_in_khz: pixel clock
1028 * @wm: chip FIFO params
1029 * @pixel_size: display pixel size
1030 * @latency_ns: memory latency for the platform
1031 *
1032 * Calculate the watermark level (the level at which the display plane will
1033 * start fetching from memory again). Each chip has a different display
1034 * FIFO size and allocation, so the caller needs to figure that out and pass
1035 * in the correct intel_watermark_params structure.
1036 *
1037 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1038 * on the pixel size. When it reaches the watermark level, it'll start
1039 * fetching FIFO line sized based chunks from memory until the FIFO fills
1040 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1041 * will occur, and a display engine hang could result.
1042 */
1043static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1044 const struct intel_watermark_params *wm,
1045 int fifo_size,
1046 int pixel_size,
1047 unsigned long latency_ns)
1048{
1049 long entries_required, wm_size;
1050
1051 /*
1052 * Note: we need to make sure we don't overflow for various clock &
1053 * latency values.
1054 * clocks go from a few thousand to several hundred thousand.
1055 * latency is usually a few thousand
1056 */
1057 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1058 1000;
1059 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1060
1061 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1062
1063 wm_size = fifo_size - (entries_required + wm->guard_size);
1064
1065 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1066
1067 /* Don't promote wm_size to unsigned... */
1068 if (wm_size > (long)wm->max_wm)
1069 wm_size = wm->max_wm;
1070 if (wm_size <= 0)
1071 wm_size = wm->default_wm;
1072 return wm_size;
1073}
1074
1075static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1076{
1077 struct drm_crtc *crtc, *enabled = NULL;
1078
1079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1080 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1081 if (enabled)
1082 return NULL;
1083 enabled = crtc;
1084 }
1085 }
1086
1087 return enabled;
1088}
1089
1fa61106 1090static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1091{
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc;
1094 const struct cxsr_latency *latency;
1095 u32 reg;
1096 unsigned long wm;
1097
1098 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1099 dev_priv->fsb_freq, dev_priv->mem_freq);
1100 if (!latency) {
1101 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1102 pineview_disable_cxsr(dev);
1103 return;
1104 }
1105
1106 crtc = single_enabled_crtc(dev);
1107 if (crtc) {
1108 int clock = crtc->mode.clock;
1109 int pixel_size = crtc->fb->bits_per_pixel / 8;
1110
1111 /* Display SR */
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121 /* cursor SR */
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1129
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149 /* activate cxsr */
1150 I915_WRITE(DSPFW3,
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 } else {
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156 }
1157}
1158
1159static bool g4x_compute_wm0(struct drm_device *dev,
1160 int plane,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1165 int *plane_wm,
1166 int *cursor_wm)
1167{
1168 struct drm_crtc *crtc;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1172
1173 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1174 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1177 return false;
1178 }
1179
1180 htotal = crtc->mode.htotal;
1181 hdisplay = crtc->mode.hdisplay;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 /* Use the small buffer method to calculate plane watermark */
1186 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1187 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1188 if (tlb_miss > 0)
1189 entries += tlb_miss;
1190 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1191 *plane_wm = entries + display->guard_size;
1192 if (*plane_wm > (int)display->max_wm)
1193 *plane_wm = display->max_wm;
1194
1195 /* Use the large buffer method to calculate cursor watermark */
1196 line_time_us = ((htotal * 1000) / clock);
1197 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1198 entries = line_count * 64 * pixel_size;
1199 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1200 if (tlb_miss > 0)
1201 entries += tlb_miss;
1202 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1203 *cursor_wm = entries + cursor->guard_size;
1204 if (*cursor_wm > (int)cursor->max_wm)
1205 *cursor_wm = (int)cursor->max_wm;
1206
1207 return true;
1208}
1209
1210/*
1211 * Check the wm result.
1212 *
1213 * If any calculated watermark values is larger than the maximum value that
1214 * can be programmed into the associated watermark register, that watermark
1215 * must be disabled.
1216 */
1217static bool g4x_check_srwm(struct drm_device *dev,
1218 int display_wm, int cursor_wm,
1219 const struct intel_watermark_params *display,
1220 const struct intel_watermark_params *cursor)
1221{
1222 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1223 display_wm, cursor_wm);
1224
1225 if (display_wm > display->max_wm) {
1226 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1227 display_wm, display->max_wm);
1228 return false;
1229 }
1230
1231 if (cursor_wm > cursor->max_wm) {
1232 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1233 cursor_wm, cursor->max_wm);
1234 return false;
1235 }
1236
1237 if (!(display_wm || cursor_wm)) {
1238 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1239 return false;
1240 }
1241
1242 return true;
1243}
1244
1245static bool g4x_compute_srwm(struct drm_device *dev,
1246 int plane,
1247 int latency_ns,
1248 const struct intel_watermark_params *display,
1249 const struct intel_watermark_params *cursor,
1250 int *display_wm, int *cursor_wm)
1251{
1252 struct drm_crtc *crtc;
1253 int hdisplay, htotal, pixel_size, clock;
1254 unsigned long line_time_us;
1255 int line_count, line_size;
1256 int small, large;
1257 int entries;
1258
1259 if (!latency_ns) {
1260 *display_wm = *cursor_wm = 0;
1261 return false;
1262 }
1263
1264 crtc = intel_get_crtc_for_plane(dev, plane);
1265 hdisplay = crtc->mode.hdisplay;
1266 htotal = crtc->mode.htotal;
1267 clock = crtc->mode.clock;
1268 pixel_size = crtc->fb->bits_per_pixel / 8;
1269
1270 line_time_us = (htotal * 1000) / clock;
1271 line_count = (latency_ns / line_time_us + 1000) / 1000;
1272 line_size = hdisplay * pixel_size;
1273
1274 /* Use the minimum of the small and large buffer method for primary */
1275 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1276 large = line_count * line_size;
1277
1278 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1279 *display_wm = entries + display->guard_size;
1280
1281 /* calculate the self-refresh watermark for display cursor */
1282 entries = line_count * pixel_size * 64;
1283 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1284 *cursor_wm = entries + cursor->guard_size;
1285
1286 return g4x_check_srwm(dev,
1287 *display_wm, *cursor_wm,
1288 display, cursor);
1289}
1290
1291static bool vlv_compute_drain_latency(struct drm_device *dev,
1292 int plane,
1293 int *plane_prec_mult,
1294 int *plane_dl,
1295 int *cursor_prec_mult,
1296 int *cursor_dl)
1297{
1298 struct drm_crtc *crtc;
1299 int clock, pixel_size;
1300 int entries;
1301
1302 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1303 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1304 return false;
1305
1306 clock = crtc->mode.clock; /* VESA DOT Clock */
1307 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1308
1309 entries = (clock / 1000) * pixel_size;
1310 *plane_prec_mult = (entries > 256) ?
1311 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1312 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1313 pixel_size);
1314
1315 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1316 *cursor_prec_mult = (entries > 256) ?
1317 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1318 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1319
1320 return true;
1321}
1322
1323/*
1324 * Update drain latency registers of memory arbiter
1325 *
1326 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1327 * to be programmed. Each plane has a drain latency multiplier and a drain
1328 * latency value.
1329 */
1330
1331static void vlv_update_drain_latency(struct drm_device *dev)
1332{
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1335 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1336 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1337 either 16 or 32 */
1338
1339 /* For plane A, Cursor A */
1340 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1341 &cursor_prec_mult, &cursora_dl)) {
1342 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1344 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1345 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1346
1347 I915_WRITE(VLV_DDL1, cursora_prec |
1348 (cursora_dl << DDL_CURSORA_SHIFT) |
1349 planea_prec | planea_dl);
1350 }
1351
1352 /* For plane B, Cursor B */
1353 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1354 &cursor_prec_mult, &cursorb_dl)) {
1355 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1357 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1358 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1359
1360 I915_WRITE(VLV_DDL2, cursorb_prec |
1361 (cursorb_dl << DDL_CURSORB_SHIFT) |
1362 planeb_prec | planeb_dl);
1363 }
1364}
1365
1366#define single_plane_enabled(mask) is_power_of_2(mask)
1367
1fa61106 1368static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1369{
1370 static const int sr_latency_ns = 12000;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373 int plane_sr, cursor_sr;
af6c4575 1374 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1375 unsigned int enabled = 0;
1376
1377 vlv_update_drain_latency(dev);
1378
51cea1f4 1379 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1380 &valleyview_wm_info, latency_ns,
1381 &valleyview_cursor_wm_info, latency_ns,
1382 &planea_wm, &cursora_wm))
51cea1f4 1383 enabled |= 1 << PIPE_A;
b445e3b0 1384
51cea1f4 1385 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1386 &valleyview_wm_info, latency_ns,
1387 &valleyview_cursor_wm_info, latency_ns,
1388 &planeb_wm, &cursorb_wm))
51cea1f4 1389 enabled |= 1 << PIPE_B;
b445e3b0 1390
b445e3b0
ED		 1391 if (single_plane_enabled(enabled) &&
1392 g4x_compute_srwm(dev, ffs(enabled) - 1,
1393 sr_latency_ns,
1394 &valleyview_wm_info,
1395 &valleyview_cursor_wm_info,
af6c4575
CW		 1396 &plane_sr, &ignore_cursor_sr) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 2*sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
52bd02d8 1401 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1402 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1403 } else {
b445e3b0
ED		 1404 I915_WRITE(FW_BLC_SELF_VLV,
1405 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1406 plane_sr = cursor_sr = 0;
1407 }
b445e3b0
ED		 1408
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410 planea_wm, cursora_wm,
1411 planeb_wm, cursorb_wm,
1412 plane_sr, cursor_sr);
1413
1414 I915_WRITE(DSPFW1,
1415 (plane_sr << DSPFW_SR_SHIFT) |
1416 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1418 planea_wm);
1419 I915_WRITE(DSPFW2,
8c919b28 1420 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1421 (cursora_wm << DSPFW_CURSORA_SHIFT));
1422 I915_WRITE(DSPFW3,
8c919b28
CW		 1423 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1424 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1425}
1426
1fa61106 1427static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1428{
1429 static const int sr_latency_ns = 12000;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1432 int plane_sr, cursor_sr;
1433 unsigned int enabled = 0;
1434
51cea1f4 1435 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1436 &g4x_wm_info, latency_ns,
1437 &g4x_cursor_wm_info, latency_ns,
1438 &planea_wm, &cursora_wm))
51cea1f4 1439 enabled |= 1 << PIPE_A;
b445e3b0 1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planeb_wm, &cursorb_wm))
51cea1f4 1445 enabled |= 1 << PIPE_B;
b445e3b0 1446
b445e3b0
ED		 1447 if (single_plane_enabled(enabled) &&
1448 g4x_compute_srwm(dev, ffs(enabled) - 1,
1449 sr_latency_ns,
1450 &g4x_wm_info,
1451 &g4x_cursor_wm_info,
52bd02d8 1452 &plane_sr, &cursor_sr)) {
b445e3b0 1453 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1454 } else {
b445e3b0
ED		 1455 I915_WRITE(FW_BLC_SELF,
1456 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1457 plane_sr = cursor_sr = 0;
1458 }
b445e3b0
ED		 1459
1460 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1461 planea_wm, cursora_wm,
1462 planeb_wm, cursorb_wm,
1463 plane_sr, cursor_sr);
1464
1465 I915_WRITE(DSPFW1,
1466 (plane_sr << DSPFW_SR_SHIFT) |
1467 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1468 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1469 planea_wm);
1470 I915_WRITE(DSPFW2,
8c919b28 1471 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1472 (cursora_wm << DSPFW_CURSORA_SHIFT));
1473 /* HPLL off in SR has some issues on G4x... disable it */
1474 I915_WRITE(DSPFW3,
8c919b28 1475 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1476 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1477}
1478
1fa61106 1479static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 struct drm_crtc *crtc;
1483 int srwm = 1;
1484 int cursor_sr = 16;
1485
1486 /* Calc sr entries for one plane configs */
1487 crtc = single_enabled_crtc(dev);
1488 if (crtc) {
1489 /* self-refresh has much higher latency */
1490 static const int sr_latency_ns = 12000;
1491 int clock = crtc->mode.clock;
1492 int htotal = crtc->mode.htotal;
1493 int hdisplay = crtc->mode.hdisplay;
1494 int pixel_size = crtc->fb->bits_per_pixel / 8;
1495 unsigned long line_time_us;
1496 int entries;
1497
1498 line_time_us = ((htotal * 1000) / clock);
1499
1500 /* Use ns/us then divide to preserve precision */
1501 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1502 pixel_size * hdisplay;
1503 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1504 srwm = I965_FIFO_SIZE - entries;
1505 if (srwm < 0)
1506 srwm = 1;
1507 srwm &= 0x1ff;
1508 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1509 entries, srwm);
1510
1511 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1512 pixel_size * 64;
1513 entries = DIV_ROUND_UP(entries,
1514 i965_cursor_wm_info.cacheline_size);
1515 cursor_sr = i965_cursor_wm_info.fifo_size -
1516 (entries + i965_cursor_wm_info.guard_size);
1517
1518 if (cursor_sr > i965_cursor_wm_info.max_wm)
1519 cursor_sr = i965_cursor_wm_info.max_wm;
1520
1521 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1522 "cursor %d\n", srwm, cursor_sr);
1523
1524 if (IS_CRESTLINE(dev))
1525 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1526 } else {
1527 /* Turn off self refresh if both pipes are enabled */
1528 if (IS_CRESTLINE(dev))
1529 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1530 & ~FW_BLC_SELF_EN);
1531 }
1532
1533 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1534 srwm);
1535
1536 /* 965 has limitations... */
1537 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1538 (8 << 16) | (8 << 8) | (8 << 0));
1539 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1540 /* update cursor SR watermark */
1541 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1542}
1543
1fa61106 1544static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1545{
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 const struct intel_watermark_params *wm_info;
1548 uint32_t fwater_lo;
1549 uint32_t fwater_hi;
1550 int cwm, srwm = 1;
1551 int fifo_size;
1552 int planea_wm, planeb_wm;
1553 struct drm_crtc *crtc, *enabled = NULL;
1554
1555 if (IS_I945GM(dev))
1556 wm_info = &i945_wm_info;
1557 else if (!IS_GEN2(dev))
1558 wm_info = &i915_wm_info;
1559 else
1560 wm_info = &i855_wm_info;
1561
1562 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1563 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1564 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1565 int cpp = crtc->fb->bits_per_pixel / 8;
1566 if (IS_GEN2(dev))
1567 cpp = 4;
1568
b445e3b0 1569 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
b445e3b0
ED		 1571 latency_ns);
1572 enabled = crtc;
1573 } else
1574 planea_wm = fifo_size - wm_info->guard_size;
1575
1576 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1577 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1578 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1579 int cpp = crtc->fb->bits_per_pixel / 8;
1580 if (IS_GEN2(dev))
1581 cpp = 4;
1582
b445e3b0 1583 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1584 wm_info, fifo_size, cpp,
b445e3b0
ED		 1585 latency_ns);
1586 if (enabled == NULL)
1587 enabled = crtc;
1588 else
1589 enabled = NULL;
1590 } else
1591 planeb_wm = fifo_size - wm_info->guard_size;
1592
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1594
1595 /*
1596 * Overlay gets an aggressive default since video jitter is bad.
1597 */
1598 cwm = 2;
1599
1600 /* Play safe and disable self-refresh before adjusting watermarks. */
1601 if (IS_I945G(dev) || IS_I945GM(dev))
1602 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1603 else if (IS_I915GM(dev))
1604 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1605
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev) && enabled) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
1610 int clock = enabled->mode.clock;
1611 int htotal = enabled->mode.htotal;
1612 int hdisplay = enabled->mode.hdisplay;
1613 int pixel_size = enabled->fb->bits_per_pixel / 8;
1614 unsigned long line_time_us;
1615 int entries;
1616
1617 line_time_us = (htotal * 1000) / clock;
1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621 pixel_size * hdisplay;
1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
1628 if (IS_I945G(dev) || IS_I945GM(dev))
1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631 else if (IS_I915GM(dev))
1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
1648 if (HAS_FW_BLC(dev)) {
1649 if (enabled) {
1650 if (IS_I945G(dev) || IS_I945GM(dev))
1651 I915_WRITE(FW_BLC_SELF,
1652 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1653 else if (IS_I915GM(dev))
1654 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1655 DRM_DEBUG_KMS("memory self refresh enabled\n");
1656 } else
1657 DRM_DEBUG_KMS("memory self refresh disabled\n");
1658 }
1659}
1660
1fa61106 1661static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct drm_crtc *crtc;
1665 uint32_t fwater_lo;
1666 int planea_wm;
1667
1668 crtc = single_enabled_crtc(dev);
1669 if (crtc == NULL)
1670 return;
1671
1672 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1673 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1674 4, latency_ns);
b445e3b0
ED		 1675 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1676 fwater_lo |= (3<<8) | planea_wm;
1677
1678 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1679
1680 I915_WRITE(FW_BLC, fwater_lo);
1681}
1682
b445e3b0
ED		 1683/*
1684 * Check the wm result.
1685 *
1686 * If any calculated watermark values is larger than the maximum value that
1687 * can be programmed into the associated watermark register, that watermark
1688 * must be disabled.
1689 */
1690static bool ironlake_check_srwm(struct drm_device *dev, int level,
1691 int fbc_wm, int display_wm, int cursor_wm,
1692 const struct intel_watermark_params *display,
1693 const struct intel_watermark_params *cursor)
1694{
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696
1697 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1698 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1699
1700 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1701 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1702 fbc_wm, SNB_FBC_MAX_SRWM, level);
1703
1704 /* fbc has it's own way to disable FBC WM */
1705 I915_WRITE(DISP_ARB_CTL,
1706 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1707 return false;
615aaa5f
VS		 1708 } else if (INTEL_INFO(dev)->gen >= 6) {
1709 /* enable FBC WM (except on ILK, where it must remain off) */
1710 I915_WRITE(DISP_ARB_CTL,
1711 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1712 }
1713
1714 if (display_wm > display->max_wm) {
1715 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1716 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1717 return false;
1718 }
1719
1720 if (cursor_wm > cursor->max_wm) {
1721 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1722 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1723 return false;
1724 }
1725
1726 if (!(fbc_wm || display_wm || cursor_wm)) {
1727 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1728 return false;
1729 }
1730
1731 return true;
1732}
1733
1734/*
1735 * Compute watermark values of WM[1-3],
1736 */
1737static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1738 int latency_ns,
1739 const struct intel_watermark_params *display,
1740 const struct intel_watermark_params *cursor,
1741 int *fbc_wm, int *display_wm, int *cursor_wm)
1742{
1743 struct drm_crtc *crtc;
1744 unsigned long line_time_us;
1745 int hdisplay, htotal, pixel_size, clock;
1746 int line_count, line_size;
1747 int small, large;
1748 int entries;
1749
1750 if (!latency_ns) {
1751 *fbc_wm = *display_wm = *cursor_wm = 0;
1752 return false;
1753 }
1754
1755 crtc = intel_get_crtc_for_plane(dev, plane);
1756 hdisplay = crtc->mode.hdisplay;
1757 htotal = crtc->mode.htotal;
1758 clock = crtc->mode.clock;
1759 pixel_size = crtc->fb->bits_per_pixel / 8;
1760
1761 line_time_us = (htotal * 1000) / clock;
1762 line_count = (latency_ns / line_time_us + 1000) / 1000;
1763 line_size = hdisplay * pixel_size;
1764
1765 /* Use the minimum of the small and large buffer method for primary */
1766 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1767 large = line_count * line_size;
1768
1769 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1770 *display_wm = entries + display->guard_size;
1771
1772 /*
1773 * Spec says:
1774 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1775 */
1776 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1777
1778 /* calculate the self-refresh watermark for display cursor */
1779 entries = line_count * pixel_size * 64;
1780 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1781 *cursor_wm = entries + cursor->guard_size;
1782
1783 return ironlake_check_srwm(dev, level,
1784 *fbc_wm, *display_wm, *cursor_wm,
1785 display, cursor);
1786}
1787
1fa61106 1788static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1789{
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 int fbc_wm, plane_wm, cursor_wm;
1792 unsigned int enabled;
1793
1794 enabled = 0;
51cea1f4 1795 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1796 &ironlake_display_wm_info,
b0aea5dc 1797 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1798 &ironlake_cursor_wm_info,
b0aea5dc 1799 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1800 &plane_wm, &cursor_wm)) {
1801 I915_WRITE(WM0_PIPEA_ILK,
1802 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1803 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1804 " plane %d, " "cursor: %d\n",
1805 plane_wm, cursor_wm);
51cea1f4 1806 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1807 }
1808
51cea1f4 1809 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1810 &ironlake_display_wm_info,
b0aea5dc 1811 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1812 &ironlake_cursor_wm_info,
b0aea5dc 1813 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1814 &plane_wm, &cursor_wm)) {
1815 I915_WRITE(WM0_PIPEB_ILK,
1816 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1817 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1818 " plane %d, cursor: %d\n",
1819 plane_wm, cursor_wm);
51cea1f4 1820 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1821 }
1822
1823 /*
1824 * Calculate and update the self-refresh watermark only when one
1825 * display plane is used.
1826 */
1827 I915_WRITE(WM3_LP_ILK, 0);
1828 I915_WRITE(WM2_LP_ILK, 0);
1829 I915_WRITE(WM1_LP_ILK, 0);
1830
1831 if (!single_plane_enabled(enabled))
1832 return;
1833 enabled = ffs(enabled) - 1;
1834
1835 /* WM1 */
1836 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1837 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1838 &ironlake_display_srwm_info,
1839 &ironlake_cursor_srwm_info,
1840 &fbc_wm, &plane_wm, &cursor_wm))
1841 return;
1842
1843 I915_WRITE(WM1_LP_ILK,
1844 WM1_LP_SR_EN |
b0aea5dc 1845 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1846 (fbc_wm << WM1_LP_FBC_SHIFT) |
1847 (plane_wm << WM1_LP_SR_SHIFT) |
1848 cursor_wm);
1849
1850 /* WM2 */
1851 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1852 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1853 &ironlake_display_srwm_info,
1854 &ironlake_cursor_srwm_info,
1855 &fbc_wm, &plane_wm, &cursor_wm))
1856 return;
1857
1858 I915_WRITE(WM2_LP_ILK,
1859 WM2_LP_EN |
b0aea5dc 1860 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1861 (fbc_wm << WM1_LP_FBC_SHIFT) |
1862 (plane_wm << WM1_LP_SR_SHIFT) |
1863 cursor_wm);
1864
1865 /*
1866 * WM3 is unsupported on ILK, probably because we don't have latency
1867 * data for that power state
1868 */
1869}
1870
1fa61106 1871static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1872{
1873 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1874 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1875 u32 val;
1876 int fbc_wm, plane_wm, cursor_wm;
1877 unsigned int enabled;
1878
1879 enabled = 0;
51cea1f4 1880 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1881 &sandybridge_display_wm_info, latency,
1882 &sandybridge_cursor_wm_info, latency,
1883 &plane_wm, &cursor_wm)) {
1884 val = I915_READ(WM0_PIPEA_ILK);
1885 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1886 I915_WRITE(WM0_PIPEA_ILK, val |
1887 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1888 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1889 " plane %d, " "cursor: %d\n",
1890 plane_wm, cursor_wm);
51cea1f4 1891 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1892 }
1893
51cea1f4 1894 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1895 &sandybridge_display_wm_info, latency,
1896 &sandybridge_cursor_wm_info, latency,
1897 &plane_wm, &cursor_wm)) {
1898 val = I915_READ(WM0_PIPEB_ILK);
1899 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1900 I915_WRITE(WM0_PIPEB_ILK, val |
1901 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1902 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1903 " plane %d, cursor: %d\n",
1904 plane_wm, cursor_wm);
51cea1f4 1905 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1906 }
1907
c43d0188
CW		 1908 /*
1909 * Calculate and update the self-refresh watermark only when one
1910 * display plane is used.
1911 *
1912 * SNB support 3 levels of watermark.
1913 *
1914 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1915 * and disabled in the descending order
1916 *
1917 */
1918 I915_WRITE(WM3_LP_ILK, 0);
1919 I915_WRITE(WM2_LP_ILK, 0);
1920 I915_WRITE(WM1_LP_ILK, 0);
1921
1922 if (!single_plane_enabled(enabled) ||
1923 dev_priv->sprite_scaling_enabled)
1924 return;
1925 enabled = ffs(enabled) - 1;
1926
1927 /* WM1 */
1928 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1929 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1930 &sandybridge_display_srwm_info,
1931 &sandybridge_cursor_srwm_info,
1932 &fbc_wm, &plane_wm, &cursor_wm))
1933 return;
1934
1935 I915_WRITE(WM1_LP_ILK,
1936 WM1_LP_SR_EN |
b0aea5dc 1937 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1938 (fbc_wm << WM1_LP_FBC_SHIFT) |
1939 (plane_wm << WM1_LP_SR_SHIFT) |
1940 cursor_wm);
1941
1942 /* WM2 */
1943 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1944 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1945 &sandybridge_display_srwm_info,
1946 &sandybridge_cursor_srwm_info,
1947 &fbc_wm, &plane_wm, &cursor_wm))
1948 return;
1949
1950 I915_WRITE(WM2_LP_ILK,
1951 WM2_LP_EN |
b0aea5dc 1952 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1953 (fbc_wm << WM1_LP_FBC_SHIFT) |
1954 (plane_wm << WM1_LP_SR_SHIFT) |
1955 cursor_wm);
1956
1957 /* WM3 */
1958 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1959 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1960 &sandybridge_display_srwm_info,
1961 &sandybridge_cursor_srwm_info,
1962 &fbc_wm, &plane_wm, &cursor_wm))
1963 return;
1964
1965 I915_WRITE(WM3_LP_ILK,
1966 WM3_LP_EN |
b0aea5dc 1967 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1968 (fbc_wm << WM1_LP_FBC_SHIFT) |
1969 (plane_wm << WM1_LP_SR_SHIFT) |
1970 cursor_wm);
1971}
1972
1973static void ivybridge_update_wm(struct drm_device *dev)
1974{
1975 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1976 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 1977 u32 val;
1978 int fbc_wm, plane_wm, cursor_wm;
1979 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1980 unsigned int enabled;
1981
1982 enabled = 0;
51cea1f4 1983 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1984 &sandybridge_display_wm_info, latency,
1985 &sandybridge_cursor_wm_info, latency,
1986 &plane_wm, &cursor_wm)) {
1987 val = I915_READ(WM0_PIPEA_ILK);
1988 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1989 I915_WRITE(WM0_PIPEA_ILK, val |
1990 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1991 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1992 " plane %d, " "cursor: %d\n",
1993 plane_wm, cursor_wm);
51cea1f4 1994 enabled |= 1 << PIPE_A;
c43d0188
CW		 1995 }
1996
51cea1f4 1997 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 1998 &sandybridge_display_wm_info, latency,
1999 &sandybridge_cursor_wm_info, latency,
2000 &plane_wm, &cursor_wm)) {
2001 val = I915_READ(WM0_PIPEB_ILK);
2002 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2003 I915_WRITE(WM0_PIPEB_ILK, val |
2004 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2005 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2006 " plane %d, cursor: %d\n",
2007 plane_wm, cursor_wm);
51cea1f4 2008 enabled |= 1 << PIPE_B;
c43d0188
CW		 2009 }
2010
51cea1f4 2011 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2012 &sandybridge_display_wm_info, latency,
2013 &sandybridge_cursor_wm_info, latency,
2014 &plane_wm, &cursor_wm)) {
2015 val = I915_READ(WM0_PIPEC_IVB);
2016 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2017 I915_WRITE(WM0_PIPEC_IVB, val |
2018 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2019 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2020 " plane %d, cursor: %d\n",
2021 plane_wm, cursor_wm);
51cea1f4 2022 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2023 }
2024
2025 /*
2026 * Calculate and update the self-refresh watermark only when one
2027 * display plane is used.
2028 *
2029 * SNB support 3 levels of watermark.
2030 *
2031 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2032 * and disabled in the descending order
2033 *
2034 */
2035 I915_WRITE(WM3_LP_ILK, 0);
2036 I915_WRITE(WM2_LP_ILK, 0);
2037 I915_WRITE(WM1_LP_ILK, 0);
2038
2039 if (!single_plane_enabled(enabled) ||
2040 dev_priv->sprite_scaling_enabled)
2041 return;
2042 enabled = ffs(enabled) - 1;
2043
2044 /* WM1 */
2045 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2046 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2047 &sandybridge_display_srwm_info,
2048 &sandybridge_cursor_srwm_info,
2049 &fbc_wm, &plane_wm, &cursor_wm))
2050 return;
2051
2052 I915_WRITE(WM1_LP_ILK,
2053 WM1_LP_SR_EN |
b0aea5dc 2054 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2055 (fbc_wm << WM1_LP_FBC_SHIFT) |
2056 (plane_wm << WM1_LP_SR_SHIFT) |
2057 cursor_wm);
2058
2059 /* WM2 */
2060 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2061 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2062 &sandybridge_display_srwm_info,
2063 &sandybridge_cursor_srwm_info,
2064 &fbc_wm, &plane_wm, &cursor_wm))
2065 return;
2066
2067 I915_WRITE(WM2_LP_ILK,
2068 WM2_LP_EN |
b0aea5dc 2069 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2070 (fbc_wm << WM1_LP_FBC_SHIFT) |
2071 (plane_wm << WM1_LP_SR_SHIFT) |
2072 cursor_wm);
2073
c43d0188 2074 /* WM3, note we have to correct the cursor latency */
b445e3b0 2075 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2076 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2077 &sandybridge_display_srwm_info,
2078 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2079 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2080 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2081 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2082 &sandybridge_display_srwm_info,
2083 &sandybridge_cursor_srwm_info,
2084 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2085 return;
2086
2087 I915_WRITE(WM3_LP_ILK,
2088 WM3_LP_EN |
b0aea5dc 2089 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2090 (fbc_wm << WM1_LP_FBC_SHIFT) |
2091 (plane_wm << WM1_LP_SR_SHIFT) |
2092 cursor_wm);
2093}
2094
3658729a
VS		 2095static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2096 struct drm_crtc *crtc)
801bcfff
PZ		 2097{
2098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2099 uint32_t pixel_rate, pfit_size;
2100
ff9a6750 2101 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2102
2103 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2104 * adjust the pixel_rate here. */
2105
2106 pfit_size = intel_crtc->config.pch_pfit.size;
2107 if (pfit_size) {
2108 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2109
2110 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2111 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2112 pfit_w = (pfit_size >> 16) & 0xFFFF;
2113 pfit_h = pfit_size & 0xFFFF;
2114 if (pipe_w < pfit_w)
2115 pipe_w = pfit_w;
2116 if (pipe_h < pfit_h)
2117 pipe_h = pfit_h;
2118
2119 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2120 pfit_w * pfit_h);
2121 }
2122
2123 return pixel_rate;
2124}
2125
23297044 2126static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2127 uint32_t latency)
2128{
2129 uint64_t ret;
2130
3312ba65
VS		 2131 if (WARN(latency == 0, "Latency value missing\n"))
2132 return UINT_MAX;
2133
801bcfff
PZ		 2134 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2135 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2136
2137 return ret;
2138}
2139
23297044 2140static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2141 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2142 uint32_t latency)
2143{
2144 uint32_t ret;
2145
3312ba65
VS		 2146 if (WARN(latency == 0, "Latency value missing\n"))
2147 return UINT_MAX;
2148
801bcfff
PZ		 2149 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2150 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2151 ret = DIV_ROUND_UP(ret, 64) + 2;
2152 return ret;
2153}
2154
23297044 2155static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2156 uint8_t bytes_per_pixel)
2157{
2158 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2159}
2160
801bcfff
PZ		 2161struct hsw_pipe_wm_parameters {
2162 bool active;
2163 bool sprite_enabled;
2164 uint8_t pri_bytes_per_pixel;
2165 uint8_t spr_bytes_per_pixel;
2166 uint8_t cur_bytes_per_pixel;
2167 uint32_t pri_horiz_pixels;
2168 uint32_t spr_horiz_pixels;
2169 uint32_t cur_horiz_pixels;
2170 uint32_t pipe_htotal;
2171 uint32_t pixel_rate;
2172};
2173
cca32e9a
PZ		 2174struct hsw_wm_maximums {
2175 uint16_t pri;
2176 uint16_t spr;
2177 uint16_t cur;
2178 uint16_t fbc;
2179};
2180
2181struct hsw_lp_wm_result {
2182 bool enable;
2183 bool fbc_enable;
2184 uint32_t pri_val;
2185 uint32_t spr_val;
2186 uint32_t cur_val;
2187 uint32_t fbc_val;
2188};
2189
801bcfff
PZ		 2190struct hsw_wm_values {
2191 uint32_t wm_pipe[3];
2192 uint32_t wm_lp[3];
2193 uint32_t wm_lp_spr[3];
2194 uint32_t wm_linetime[3];
cca32e9a 2195 bool enable_fbc_wm;
801bcfff
PZ		 2196};
2197
2198enum hsw_data_buf_partitioning {
2199 HSW_DATA_BUF_PART_1_2,
2200 HSW_DATA_BUF_PART_5_6,
2201};
2202
cca32e9a 2203/* For both WM_PIPE and WM_LP. */
23297044 2204static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2205 uint32_t mem_value,
2206 bool is_lp)
801bcfff 2207{
cca32e9a
PZ		 2208 uint32_t method1, method2;
2209
801bcfff
PZ		 2210 /* TODO: for now, assume the primary plane is always enabled. */
2211 if (!params->active)
2212 return 0;
2213
23297044 2214 method1 = ilk_wm_method1(params->pixel_rate,
cca32e9a
PZ		 2215 params->pri_bytes_per_pixel,
2216 mem_value);
2217
2218 if (!is_lp)
2219 return method1;
2220
23297044 2221 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a
PZ		 2222 params->pipe_htotal,
2223 params->pri_horiz_pixels,
2224 params->pri_bytes_per_pixel,
2225 mem_value);
2226
2227 return min(method1, method2);
801bcfff
PZ		 2228}
2229
2230/* For both WM_PIPE and WM_LP. */
23297044 2231static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2232 uint32_t mem_value)
2233{
2234 uint32_t method1, method2;
2235
2236 if (!params->active || !params->sprite_enabled)
2237 return 0;
2238
23297044 2239 method1 = ilk_wm_method1(params->pixel_rate,
801bcfff
PZ		 2240 params->spr_bytes_per_pixel,
2241 mem_value);
23297044 2242 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff
PZ		 2243 params->pipe_htotal,
2244 params->spr_horiz_pixels,
2245 params->spr_bytes_per_pixel,
2246 mem_value);
2247 return min(method1, method2);
2248}
2249
2250/* For both WM_PIPE and WM_LP. */
23297044 2251static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2252 uint32_t mem_value)
2253{
2254 if (!params->active)
2255 return 0;
2256
23297044 2257 return ilk_wm_method2(params->pixel_rate,
801bcfff
PZ		 2258 params->pipe_htotal,
2259 params->cur_horiz_pixels,
2260 params->cur_bytes_per_pixel,
2261 mem_value);
2262}
2263
cca32e9a 2264/* Only for WM_LP. */
23297044 2265static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
1fda9882 2266 uint32_t pri_val)
cca32e9a
PZ		 2267{
2268 if (!params->active)
2269 return 0;
2270
23297044 2271 return ilk_wm_fbc(pri_val,
cca32e9a
PZ		 2272 params->pri_horiz_pixels,
2273 params->pri_bytes_per_pixel);
2274}
2275
5b77da33
VS		 2276static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
2277 int level, struct hsw_wm_maximums *max,
cca32e9a
PZ		 2278 struct hsw_pipe_wm_parameters *params,
2279 struct hsw_lp_wm_result *result)
2280{
2281 enum pipe pipe;
2282 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2283
2284 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2285 struct hsw_pipe_wm_parameters *p = &params[pipe];
5b77da33
VS		 2286 /* WM1+ latency values stored in 0.5us units */
2287 uint16_t pri_latency = dev_priv->wm.pri_latency[level] * 5;
2288 uint16_t spr_latency = dev_priv->wm.spr_latency[level] * 5;
2289 uint16_t cur_latency = dev_priv->wm.cur_latency[level] * 5;
2290
2291 pri_val[pipe] = ilk_compute_pri_wm(p, pri_latency, true);
2292 spr_val[pipe] = ilk_compute_spr_wm(p, spr_latency);
2293 cur_val[pipe] = ilk_compute_cur_wm(p, cur_latency);
1fda9882 2294 fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]);
cca32e9a
PZ		 2295 }
2296
2297 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2298 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2299 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2300 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2301
2302 if (result->fbc_val > max->fbc) {
2303 result->fbc_enable = false;
2304 result->fbc_val = 0;
2305 } else {
2306 result->fbc_enable = true;
2307 }
2308
2309 result->enable = result->pri_val <= max->pri &&
2310 result->spr_val <= max->spr &&
2311 result->cur_val <= max->cur;
2312 return result->enable;
2313}
2314
801bcfff 2315static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
5b77da33 2316 enum pipe pipe,
801bcfff
PZ		 2317 struct hsw_pipe_wm_parameters *params)
2318{
2319 uint32_t pri_val, cur_val, spr_val;
5b77da33
VS		 2320 /* WM0 latency values stored in 0.1us units */
2321 uint16_t pri_latency = dev_priv->wm.pri_latency[0];
2322 uint16_t spr_latency = dev_priv->wm.spr_latency[0];
2323 uint16_t cur_latency = dev_priv->wm.cur_latency[0];
801bcfff 2324
5b77da33
VS		 2325 pri_val = ilk_compute_pri_wm(params, pri_latency, false);
2326 spr_val = ilk_compute_spr_wm(params, spr_latency);
2327 cur_val = ilk_compute_cur_wm(params, cur_latency);
801bcfff
PZ		 2328
2329 WARN(pri_val > 127,
2330 "Primary WM error, mode not supported for pipe %c\n",
2331 pipe_name(pipe));
2332 WARN(spr_val > 127,
2333 "Sprite WM error, mode not supported for pipe %c\n",
2334 pipe_name(pipe));
2335 WARN(cur_val > 63,
2336 "Cursor WM error, mode not supported for pipe %c\n",
2337 pipe_name(pipe));
2338
2339 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2340 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2341 cur_val;
2342}
2343
2344static uint32_t
2345hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2346{
2347 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2349 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2350 u32 linetime, ips_linetime;
1f8eeabf 2351
801bcfff
PZ		 2352 if (!intel_crtc_active(crtc))
2353 return 0;
1011d8c4 2354
1f8eeabf
ED		 2355 /* The WM are computed with base on how long it takes to fill a single
2356 * row at the given clock rate, multiplied by 8.
2357 * */
85a02deb
PZ		 2358 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2359 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2360 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2361
801bcfff
PZ		 2362 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2363 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2364}
2365
12b134df
VS		 2366static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2367{
2368 struct drm_i915_private *dev_priv = dev->dev_private;
2369
2370 if (IS_HASWELL(dev)) {
2371 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2372
2373 wm[0] = (sskpd >> 56) & 0xFF;
2374 if (wm[0] == 0)
2375 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2376 wm[1] = (sskpd >> 4) & 0xFF;
2377 wm[2] = (sskpd >> 12) & 0xFF;
2378 wm[3] = (sskpd >> 20) & 0x1FF;
2379 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2380 } else if (INTEL_INFO(dev)->gen >= 6) {
2381 uint32_t sskpd = I915_READ(MCH_SSKPD);
2382
2383 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2384 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2385 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2386 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2387 } else if (INTEL_INFO(dev)->gen >= 5) {
2388 uint32_t mltr = I915_READ(MLTR_ILK);
2389
2390 /* ILK primary LP0 latency is 700 ns */
2391 wm[0] = 7;
2392 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2393 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2394 }
2395}
2396
53615a5e
VS		 2397static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2398{
2399 /* ILK sprite LP0 latency is 1300 ns */
2400 if (INTEL_INFO(dev)->gen == 5)
2401 wm[0] = 13;
2402}
2403
2404static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2405{
2406 /* ILK cursor LP0 latency is 1300 ns */
2407 if (INTEL_INFO(dev)->gen == 5)
2408 wm[0] = 13;
2409
2410 /* WaDoubleCursorLP3Latency:ivb */
2411 if (IS_IVYBRIDGE(dev))
2412 wm[3] *= 2;
2413}
2414
26ec971e
VS		 2415static void intel_print_wm_latency(struct drm_device *dev,
2416 const char *name,
2417 const uint16_t wm[5])
2418{
2419 int level, max_level;
2420
2421 /* how many WM levels are we expecting */
2422 if (IS_HASWELL(dev))
2423 max_level = 4;
2424 else if (INTEL_INFO(dev)->gen >= 6)
2425 max_level = 3;
2426 else
2427 max_level = 2;
2428
2429 for (level = 0; level <= max_level; level++) {
2430 unsigned int latency = wm[level];
2431
2432 if (latency == 0) {
2433 DRM_ERROR("%s WM%d latency not provided\n",
2434 name, level);
2435 continue;
2436 }
2437
2438 /* WM1+ latency values in 0.5us units */
2439 if (level > 0)
2440 latency *= 5;
2441
2442 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2443 name, level, wm[level],
2444 latency / 10, latency % 10);
2445 }
2446}
2447
53615a5e
VS		 2448static void intel_setup_wm_latency(struct drm_device *dev)
2449{
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451
2452 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2453
2454 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2455 sizeof(dev_priv->wm.pri_latency));
2456 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2457 sizeof(dev_priv->wm.pri_latency));
2458
2459 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2460 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2461
2462 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2463 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2464 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2465}
2466
801bcfff
PZ		 2467static void hsw_compute_wm_parameters(struct drm_device *dev,
2468 struct hsw_pipe_wm_parameters *params,
861f3389
PZ		 2469 struct hsw_wm_maximums *lp_max_1_2,
2470 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4 2471{
1011d8c4 2472 struct drm_crtc *crtc;
801bcfff 2473 struct drm_plane *plane;
1011d8c4 2474 enum pipe pipe;
cca32e9a 2475 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2476
801bcfff
PZ		 2477 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2479 struct hsw_pipe_wm_parameters *p;
2480
2481 pipe = intel_crtc->pipe;
2482 p = &params[pipe];
2483
2484 p->active = intel_crtc_active(crtc);
2485 if (!p->active)
2486 continue;
2487
cca32e9a
PZ		 2488 pipes_active++;
2489
801bcfff 2490 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2491 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
801bcfff
PZ		 2492 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2493 p->cur_bytes_per_pixel = 4;
2494 p->pri_horiz_pixels =
2495 intel_crtc->config.requested_mode.hdisplay;
2496 p->cur_horiz_pixels = 64;
2497 }
2498
2499 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2500 struct intel_plane *intel_plane = to_intel_plane(plane);
2501 struct hsw_pipe_wm_parameters *p;
2502
2503 pipe = intel_plane->pipe;
2504 p = &params[pipe];
2505
bdd57d03 2506 p->sprite_enabled = intel_plane->wm.enabled;
801bcfff
PZ		 2507 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2508 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2509
2510 if (p->sprite_enabled)
2511 sprites_enabled++;
2512 }
2513
2514 if (pipes_active > 1) {
861f3389
PZ		 2515 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2516 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2517 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2518 } else {
2519 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2520 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2521 lp_max_1_2->spr = 384;
861f3389
PZ		 2522 lp_max_5_6->spr = 640;
2523 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2524 }
861f3389 2525 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2526}
2527
2528static void hsw_compute_wm_results(struct drm_device *dev,
2529 struct hsw_pipe_wm_parameters *params,
cca32e9a 2530 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2531 struct hsw_wm_values *results)
2532{
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 struct drm_crtc *crtc;
cca32e9a 2535 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2536 enum pipe pipe;
cca32e9a
PZ		 2537 int level, max_level, wm_lp;
2538
2539 for (level = 1; level <= 4; level++)
5b77da33
VS		 2540 if (!hsw_compute_lp_wm(dev_priv, level,
2541 lp_maximums, params,
cca32e9a
PZ		 2542 &lp_results[level - 1]))
2543 break;
2544 max_level = level - 1;
2545
2546 /* The spec says it is preferred to disable FBC WMs instead of disabling
2547 * a WM level. */
2548 results->enable_fbc_wm = true;
2549 for (level = 1; level <= max_level; level++) {
2550 if (!lp_results[level - 1].fbc_enable) {
2551 results->enable_fbc_wm = false;
2552 break;
2553 }
2554 }
2555
2556 memset(results, 0, sizeof(*results));
2557 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2558 const struct hsw_lp_wm_result *r;
801bcfff 2559
cca32e9a
PZ		 2560 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2561 if (level > max_level)
2562 break;
2563
2564 r = &lp_results[level - 1];
2565 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2566 r->fbc_val,
2567 r->pri_val,
2568 r->cur_val);
2569 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2570 }
801bcfff
PZ		 2571
2572 for_each_pipe(pipe)
5b77da33 2573 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
801bcfff 2574 &params[pipe]);
1011d8c4
PZ		 2575
2576 for_each_pipe(pipe) {
2577 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2578 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2579 }
2580}
2581
861f3389
PZ		 2582/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2583 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2584static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2585 struct hsw_wm_values *r2)
861f3389
PZ		 2586{
2587 int i, val_r1 = 0, val_r2 = 0;
2588
2589 for (i = 0; i < 3; i++) {
2590 if (r1->wm_lp[i] & WM3_LP_EN)
2591 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2592 if (r2->wm_lp[i] & WM3_LP_EN)
2593 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2594 }
2595
2596 if (val_r1 == val_r2) {
2597 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2598 return r2;
2599 else
2600 return r1;
2601 } else if (val_r1 > val_r2) {
2602 return r1;
2603 } else {
2604 return r2;
2605 }
2606}
2607
801bcfff
PZ		 2608/*
2609 * The spec says we shouldn't write when we don't need, because every write
2610 * causes WMs to be re-evaluated, expending some power.
2611 */
2612static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2613 struct hsw_wm_values *results,
2614 enum hsw_data_buf_partitioning partitioning)
2615{
2616 struct hsw_wm_values previous;
2617 uint32_t val;
2618 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2619 bool prev_enable_fbc_wm;
801bcfff
PZ		 2620
2621 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2622 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2623 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2624 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2625 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2626 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2627 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2628 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2629 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2630 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2631 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2632 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2633
2634 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2635 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2636
cca32e9a
PZ		 2637 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2638
801bcfff
PZ		 2639 if (memcmp(results->wm_pipe, previous.wm_pipe,
2640 sizeof(results->wm_pipe)) == 0 &&
2641 memcmp(results->wm_lp, previous.wm_lp,
2642 sizeof(results->wm_lp)) == 0 &&
2643 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2644 sizeof(results->wm_lp_spr)) == 0 &&
2645 memcmp(results->wm_linetime, previous.wm_linetime,
2646 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2647 partitioning == prev_partitioning &&
2648 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2649 return;
2650
2651 if (previous.wm_lp[2] != 0)
2652 I915_WRITE(WM3_LP_ILK, 0);
2653 if (previous.wm_lp[1] != 0)
2654 I915_WRITE(WM2_LP_ILK, 0);
2655 if (previous.wm_lp[0] != 0)
2656 I915_WRITE(WM1_LP_ILK, 0);
2657
2658 if (previous.wm_pipe[0] != results->wm_pipe[0])
2659 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2660 if (previous.wm_pipe[1] != results->wm_pipe[1])
2661 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2662 if (previous.wm_pipe[2] != results->wm_pipe[2])
2663 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2664
2665 if (previous.wm_linetime[0] != results->wm_linetime[0])
2666 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2667 if (previous.wm_linetime[1] != results->wm_linetime[1])
2668 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2669 if (previous.wm_linetime[2] != results->wm_linetime[2])
2670 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2671
2672 if (prev_partitioning != partitioning) {
2673 val = I915_READ(WM_MISC);
2674 if (partitioning == HSW_DATA_BUF_PART_1_2)
2675 val &= ~WM_MISC_DATA_PARTITION_5_6;
2676 else
2677 val |= WM_MISC_DATA_PARTITION_5_6;
2678 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2679 }
2680
cca32e9a
PZ		 2681 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2682 val = I915_READ(DISP_ARB_CTL);
2683 if (results->enable_fbc_wm)
2684 val &= ~DISP_FBC_WM_DIS;
2685 else
2686 val |= DISP_FBC_WM_DIS;
2687 I915_WRITE(DISP_ARB_CTL, val);
2688 }
2689
801bcfff
PZ		 2690 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2691 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2692 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2693 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2694 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2695 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2696
2697 if (results->wm_lp[0] != 0)
2698 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2699 if (results->wm_lp[1] != 0)
2700 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2701 if (results->wm_lp[2] != 0)
2702 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2703}
2704
2705static void haswell_update_wm(struct drm_device *dev)
2706{
2707 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2708 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2709 struct hsw_pipe_wm_parameters params[3];
861f3389 2710 struct hsw_wm_values results_1_2, results_5_6, *best_results;
861f3389
PZ		 2711 enum hsw_data_buf_partitioning partitioning;
2712
12b134df 2713 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
861f3389 2714
53615a5e 2715 hsw_compute_wm_results(dev, params,
53615a5e 2716 &lp_max_1_2, &results_1_2);
861f3389 2717 if (lp_max_1_2.pri != lp_max_5_6.pri) {
53615a5e 2718 hsw_compute_wm_results(dev, params,
53615a5e 2719 &lp_max_5_6, &results_5_6);
861f3389
PZ		 2720 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2721 } else {
2722 best_results = &results_1_2;
2723 }
2724
2725 partitioning = (best_results == &results_1_2) ?
2726 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2727
861f3389 2728 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2729}
2730
526682e9
PZ		 2731static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2732 uint32_t sprite_width, int pixel_size,
bdd57d03 2733 bool enabled, bool scaled)
526682e9
PZ		 2734{
2735 struct drm_plane *plane;
2736
2737 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2738 struct intel_plane *intel_plane = to_intel_plane(plane);
2739
2740 if (intel_plane->pipe == pipe) {
bdd57d03
VS		 2741 intel_plane->wm.enabled = enabled;
2742 intel_plane->wm.scaled = scaled;
67ca28f3 2743 intel_plane->wm.horiz_pixels = sprite_width;
526682e9
PZ		 2744 intel_plane->wm.bytes_per_pixel = pixel_size;
2745 break;
2746 }
2747 }
2748
2749 haswell_update_wm(dev);
2750}
2751
b445e3b0
ED		 2752static bool
2753sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2754 uint32_t sprite_width, int pixel_size,
2755 const struct intel_watermark_params *display,
2756 int display_latency_ns, int *sprite_wm)
2757{
2758 struct drm_crtc *crtc;
2759 int clock;
2760 int entries, tlb_miss;
2761
2762 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2763 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2764 *sprite_wm = display->guard_size;
2765 return false;
2766 }
2767
2768 clock = crtc->mode.clock;
2769
2770 /* Use the small buffer method to calculate the sprite watermark */
2771 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2772 tlb_miss = display->fifo_size*display->cacheline_size -
2773 sprite_width * 8;
2774 if (tlb_miss > 0)
2775 entries += tlb_miss;
2776 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2777 *sprite_wm = entries + display->guard_size;
2778 if (*sprite_wm > (int)display->max_wm)
2779 *sprite_wm = display->max_wm;
2780
2781 return true;
2782}
2783
2784static bool
2785sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2786 uint32_t sprite_width, int pixel_size,
2787 const struct intel_watermark_params *display,
2788 int latency_ns, int *sprite_wm)
2789{
2790 struct drm_crtc *crtc;
2791 unsigned long line_time_us;
2792 int clock;
2793 int line_count, line_size;
2794 int small, large;
2795 int entries;
2796
2797 if (!latency_ns) {
2798 *sprite_wm = 0;
2799 return false;
2800 }
2801
2802 crtc = intel_get_crtc_for_plane(dev, plane);
2803 clock = crtc->mode.clock;
2804 if (!clock) {
2805 *sprite_wm = 0;
2806 return false;
2807 }
2808
2809 line_time_us = (sprite_width * 1000) / clock;
2810 if (!line_time_us) {
2811 *sprite_wm = 0;
2812 return false;
2813 }
2814
2815 line_count = (latency_ns / line_time_us + 1000) / 1000;
2816 line_size = sprite_width * pixel_size;
2817
2818 /* Use the minimum of the small and large buffer method for primary */
2819 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2820 large = line_count * line_size;
2821
2822 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2823 *sprite_wm = entries + display->guard_size;
2824
2825 return *sprite_wm > 0x3ff ? false : true;
2826}
2827
1fa61106 2828static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a 2829 uint32_t sprite_width, int pixel_size,
bdd57d03 2830 bool enable, bool scaled)
b445e3b0
ED		 2831{
2832 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2833 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 2834 u32 val;
2835 int sprite_wm, reg;
2836 int ret;
2837
4c4ff43a
PZ		 2838 if (!enable)
2839 return;
2840
b445e3b0
ED		 2841 switch (pipe) {
2842 case 0:
2843 reg = WM0_PIPEA_ILK;
2844 break;
2845 case 1:
2846 reg = WM0_PIPEB_ILK;
2847 break;
2848 case 2:
2849 reg = WM0_PIPEC_IVB;
2850 break;
2851 default:
2852 return; /* bad pipe */
2853 }
2854
2855 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2856 &sandybridge_display_wm_info,
2857 latency, &sprite_wm);
2858 if (!ret) {
84f44ce7
VS		 2859 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2860 pipe_name(pipe));
b445e3b0
ED		 2861 return;
2862 }
2863
2864 val = I915_READ(reg);
2865 val &= ~WM0_PIPE_SPRITE_MASK;
2866 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2867 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2868
2869
2870 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2871 pixel_size,
2872 &sandybridge_display_srwm_info,
b0aea5dc 2873 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 2874 &sprite_wm);
2875 if (!ret) {
84f44ce7
VS		 2876 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2877 pipe_name(pipe));
b445e3b0
ED		 2878 return;
2879 }
2880 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2881
2882 /* Only IVB has two more LP watermarks for sprite */
2883 if (!IS_IVYBRIDGE(dev))
2884 return;
2885
2886 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2887 pixel_size,
2888 &sandybridge_display_srwm_info,
b0aea5dc 2889 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 2890 &sprite_wm);
2891 if (!ret) {
84f44ce7
VS		 2892 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2893 pipe_name(pipe));
b445e3b0
ED		 2894 return;
2895 }
2896 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2897
2898 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2899 pixel_size,
2900 &sandybridge_display_srwm_info,
b0aea5dc 2901 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 2902 &sprite_wm);
2903 if (!ret) {
84f44ce7
VS		 2904 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2905 pipe_name(pipe));
b445e3b0
ED		 2906 return;
2907 }
2908 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2909}
2910
2911/**
2912 * intel_update_watermarks - update FIFO watermark values based on current modes
2913 *
2914 * Calculate watermark values for the various WM regs based on current mode
2915 * and plane configuration.
2916 *
2917 * There are several cases to deal with here:
2918 * - normal (i.e. non-self-refresh)
2919 * - self-refresh (SR) mode
2920 * - lines are large relative to FIFO size (buffer can hold up to 2)
2921 * - lines are small relative to FIFO size (buffer can hold more than 2
2922 * lines), so need to account for TLB latency
2923 *
2924 * The normal calculation is:
2925 * watermark = dotclock * bytes per pixel * latency
2926 * where latency is platform & configuration dependent (we assume pessimal
2927 * values here).
2928 *
2929 * The SR calculation is:
2930 * watermark = (trunc(latency/line time)+1) * surface width *
2931 * bytes per pixel
2932 * where
2933 * line time = htotal / dotclock
2934 * surface width = hdisplay for normal plane and 64 for cursor
2935 * and latency is assumed to be high, as above.
2936 *
2937 * The final value programmed to the register should always be rounded up,
2938 * and include an extra 2 entries to account for clock crossings.
2939 *
2940 * We don't use the sprite, so we can ignore that. And on Crestline we have
2941 * to set the non-SR watermarks to 8.
2942 */
2943void intel_update_watermarks(struct drm_device *dev)
2944{
2945 struct drm_i915_private *dev_priv = dev->dev_private;
2946
2947 if (dev_priv->display.update_wm)
2948 dev_priv->display.update_wm(dev);
2949}
2950
2951void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a 2952 uint32_t sprite_width, int pixel_size,
bdd57d03 2953 bool enable, bool scaled)
b445e3b0
ED		 2954{
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956
2957 if (dev_priv->display.update_sprite_wm)
2958 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
bdd57d03 2959 pixel_size, enable, scaled);
b445e3b0
ED		 2960}
2961
2b4e57bd
ED		 2962static struct drm_i915_gem_object *
2963intel_alloc_context_page(struct drm_device *dev)
2964{
2965 struct drm_i915_gem_object *ctx;
2966 int ret;
2967
2968 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2969
2970 ctx = i915_gem_alloc_object(dev, 4096);
2971 if (!ctx) {
2972 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2973 return NULL;
2974 }
2975
c37e2204 2976 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2977 if (ret) {
2978 DRM_ERROR("failed to pin power context: %d\n", ret);
2979 goto err_unref;
2980 }
2981
2982 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2983 if (ret) {
2984 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2985 goto err_unpin;
2986 }
2987
2988 return ctx;
2989
2990err_unpin:
2991 i915_gem_object_unpin(ctx);
2992err_unref:
2993 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2994 return NULL;
2995}
2996
9270388e
DV		 2997/**
2998 * Lock protecting IPS related data structures
9270388e
DV		 2999 */
3000DEFINE_SPINLOCK(mchdev_lock);
3001
3002/* Global for IPS driver to get at the current i915 device. Protected by
3003 * mchdev_lock. */
3004static struct drm_i915_private *i915_mch_dev;
3005
2b4e57bd
ED		 3006bool ironlake_set_drps(struct drm_device *dev, u8 val)
3007{
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 u16 rgvswctl;
3010
9270388e
DV		 3011 assert_spin_locked(&mchdev_lock);
3012
2b4e57bd
ED		 3013 rgvswctl = I915_READ16(MEMSWCTL);
3014 if (rgvswctl & MEMCTL_CMD_STS) {
3015 DRM_DEBUG("gpu busy, RCS change rejected\n");
3016 return false; /* still busy with another command */
3017 }
3018
3019 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3020 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3021 I915_WRITE16(MEMSWCTL, rgvswctl);
3022 POSTING_READ16(MEMSWCTL);
3023
3024 rgvswctl |= MEMCTL_CMD_STS;
3025 I915_WRITE16(MEMSWCTL, rgvswctl);
3026
3027 return true;
3028}
3029
8090c6b9 3030static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3031{
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033 u32 rgvmodectl = I915_READ(MEMMODECTL);
3034 u8 fmax, fmin, fstart, vstart;
3035
9270388e
DV		 3036 spin_lock_irq(&mchdev_lock);
3037
2b4e57bd
ED		 3038 /* Enable temp reporting */
3039 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3040 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3041
3042 /* 100ms RC evaluation intervals */
3043 I915_WRITE(RCUPEI, 100000);
3044 I915_WRITE(RCDNEI, 100000);
3045
3046 /* Set max/min thresholds to 90ms and 80ms respectively */
3047 I915_WRITE(RCBMAXAVG, 90000);
3048 I915_WRITE(RCBMINAVG, 80000);
3049
3050 I915_WRITE(MEMIHYST, 1);
3051
3052 /* Set up min, max, and cur for interrupt handling */
3053 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3054 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3055 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3056 MEMMODE_FSTART_SHIFT;
3057
3058 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3059 PXVFREQ_PX_SHIFT;
3060
20e4d407
DV		 3061 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3062 dev_priv->ips.fstart = fstart;
2b4e57bd 3063
20e4d407
DV		 3064 dev_priv->ips.max_delay = fstart;
3065 dev_priv->ips.min_delay = fmin;
3066 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3067
3068 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3069 fmax, fmin, fstart);
3070
3071 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3072
3073 /*
3074 * Interrupts will be enabled in ironlake_irq_postinstall
3075 */
3076
3077 I915_WRITE(VIDSTART, vstart);
3078 POSTING_READ(VIDSTART);
3079
3080 rgvmodectl |= MEMMODE_SWMODE_EN;
3081 I915_WRITE(MEMMODECTL, rgvmodectl);
3082
9270388e 3083 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3084 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3085 mdelay(1);
2b4e57bd
ED		 3086
3087 ironlake_set_drps(dev, fstart);
3088
20e4d407 3089 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3090 I915_READ(0x112e0);
20e4d407
DV		 3091 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3092 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3093 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3094
3095 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3096}
3097
8090c6b9 3098static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3099{
3100 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3101 u16 rgvswctl;
3102
3103 spin_lock_irq(&mchdev_lock);
3104
3105 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3106
3107 /* Ack interrupts, disable EFC interrupt */
3108 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3109 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3110 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3111 I915_WRITE(DEIIR, DE_PCU_EVENT);
3112 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3113
3114 /* Go back to the starting frequency */
20e4d407 3115 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3116 mdelay(1);
2b4e57bd
ED		 3117 rgvswctl |= MEMCTL_CMD_STS;
3118 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3119 mdelay(1);
2b4e57bd 3120
9270388e 3121 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3122}
3123
acbe9475
DV		 3124/* There's a funny hw issue where the hw returns all 0 when reading from
3125 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3126 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3127 * all limits and the gpu stuck at whatever frequency it is at atm).
3128 */
65bccb5c 3129static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3130{
7b9e0ae6 3131 u32 limits;
2b4e57bd 3132
7b9e0ae6 3133 limits = 0;
c6a828d3
DV		 3134
3135 if (*val >= dev_priv->rps.max_delay)
3136 *val = dev_priv->rps.max_delay;
3137 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3138
3139 /* Only set the down limit when we've reached the lowest level to avoid
3140 * getting more interrupts, otherwise leave this clear. This prevents a
3141 * race in the hw when coming out of rc6: There's a tiny window where
3142 * the hw runs at the minimal clock before selecting the desired
3143 * frequency, if the down threshold expires in that window we will not
3144 * receive a down interrupt. */
c6a828d3
DV		 3145 if (*val <= dev_priv->rps.min_delay) {
3146 *val = dev_priv->rps.min_delay;
3147 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3148 }
3149
3150 return limits;
3151}
3152
3153void gen6_set_rps(struct drm_device *dev, u8 val)
3154{
3155 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3156 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3157
4fc688ce 3158 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3159 WARN_ON(val > dev_priv->rps.max_delay);
3160 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3161
c6a828d3 3162 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3163 return;
3164
92bd1bf0
RV		 3165 if (IS_HASWELL(dev))
3166 I915_WRITE(GEN6_RPNSWREQ,
3167 HSW_FREQUENCY(val));
3168 else
3169 I915_WRITE(GEN6_RPNSWREQ,
3170 GEN6_FREQUENCY(val) |
3171 GEN6_OFFSET(0) |
3172 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3173
3174 /* Make sure we continue to get interrupts
3175 * until we hit the minimum or maximum frequencies.
3176 */
3177 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3178
d5570a72
BW		 3179 POSTING_READ(GEN6_RPNSWREQ);
3180
c6a828d3 3181 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3182
3183 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3184}
3185
80814ae4
VS		 3186/*
3187 * Wait until the previous freq change has completed,
3188 * or the timeout elapsed, and then update our notion
3189 * of the current GPU frequency.
3190 */
3191static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3192{
80814ae4
VS		 3193 u32 pval;
3194
3195 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3196
e8474409
VS		 3197 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3198 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3199
3200 pval >>= 8;
3201
3202 if (pval != dev_priv->rps.cur_delay)
3203 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3204 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3205 dev_priv->rps.cur_delay,
3206 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3207
3208 dev_priv->rps.cur_delay = pval;
3209}
3210
0a073b84
JB		 3211void valleyview_set_rps(struct drm_device *dev, u8 val)
3212{
3213 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3214
3215 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3216
3217 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3218 WARN_ON(val > dev_priv->rps.max_delay);
3219 WARN_ON(val < dev_priv->rps.min_delay);
3220
80814ae4
VS		 3221 vlv_update_rps_cur_delay(dev_priv);
3222
73008b98 3223 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3224 vlv_gpu_freq(dev_priv->mem_freq,
3225 dev_priv->rps.cur_delay),
73008b98
VS		 3226 dev_priv->rps.cur_delay,
3227 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3228
3229 if (val == dev_priv->rps.cur_delay)
3230 return;
3231
ae99258f 3232 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3233
80814ae4 3234 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3235
3236 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3237}
3238
44fc7d5c 3239static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3240{
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242
2b4e57bd 3243 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3244 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3245 /* Complete PM interrupt masking here doesn't race with the rps work
3246 * item again unmasking PM interrupts because that is using a different
3247 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3248 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3249
59cdb63d 3250 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3251 dev_priv->rps.pm_iir = 0;
59cdb63d 3252 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3253
4848405c 3254 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3255}
3256
44fc7d5c 3257static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3258{
3259 struct drm_i915_private *dev_priv = dev->dev_private;
3260
3261 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3262 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3263
44fc7d5c
DV		 3264 gen6_disable_rps_interrupts(dev);
3265}
3266
3267static void valleyview_disable_rps(struct drm_device *dev)
3268{
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270
3271 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3272
44fc7d5c 3273 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3274
3275 if (dev_priv->vlv_pctx) {
3276 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3277 dev_priv->vlv_pctx = NULL;
3278 }
d20d4f0c
JB		 3279}
3280
2b4e57bd
ED		 3281int intel_enable_rc6(const struct drm_device *dev)
3282{
eb4926e4
DL		 3283 /* No RC6 before Ironlake */
3284 if (INTEL_INFO(dev)->gen < 5)
3285 return 0;
3286
456470eb 3287 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3288 if (i915_enable_rc6 >= 0)
3289 return i915_enable_rc6;
3290
6567d748
CW		 3291 /* Disable RC6 on Ironlake */
3292 if (INTEL_INFO(dev)->gen == 5)
3293 return 0;
2b4e57bd 3294
456470eb
DV		 3295 if (IS_HASWELL(dev)) {
3296 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3297 return INTEL_RC6_ENABLE;
456470eb 3298 }
2b4e57bd 3299
456470eb 3300 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3301 if (INTEL_INFO(dev)->gen == 6) {
3302 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3303 return INTEL_RC6_ENABLE;
3304 }
456470eb 3305
2b4e57bd
ED		 3306 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3307 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3308}
3309
44fc7d5c
DV		 3310static void gen6_enable_rps_interrupts(struct drm_device *dev)
3311{
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313
3314 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3315 WARN_ON(dev_priv->rps.pm_iir);
44fc7d5c
DV		 3316 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3317 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3318 spin_unlock_irq(&dev_priv->irq_lock);
3319 /* unmask all PM interrupts */
3320 I915_WRITE(GEN6_PMINTRMSK, 0);
3321}
3322
79f5b2c7 3323static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3324{
79f5b2c7 3325 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3326 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3327 u32 rp_state_cap;
3328 u32 gt_perf_status;
31643d54 3329 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3330 u32 gtfifodbg;
2b4e57bd 3331 int rc6_mode;
42c0526c 3332 int i, ret;
2b4e57bd 3333
4fc688ce 3334 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3335
2b4e57bd
ED		 3336 /* Here begins a magic sequence of register writes to enable
3337 * auto-downclocking.
3338 *
3339 * Perhaps there might be some value in exposing these to
3340 * userspace...
3341 */
3342 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3343
3344 /* Clear the DBG now so we don't confuse earlier errors */
3345 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3346 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3347 I915_WRITE(GTFIFODBG, gtfifodbg);
3348 }
3349
3350 gen6_gt_force_wake_get(dev_priv);
3351
7b9e0ae6
CW		 3352 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3353 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3354
31c77388
BW		 3355 /* In units of 50MHz */
3356 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3357 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3358 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3359
2b4e57bd
ED		 3360 /* disable the counters and set deterministic thresholds */
3361 I915_WRITE(GEN6_RC_CONTROL, 0);
3362
3363 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3364 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3365 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3366 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3367 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3368
b4519513
CW		 3369 for_each_ring(ring, dev_priv, i)
3370 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3371
3372 I915_WRITE(GEN6_RC_SLEEP, 0);
3373 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3374 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3375 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3376 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3377
5a7dc92a 3378 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3379 rc6_mode = intel_enable_rc6(dev_priv->dev);
3380 if (rc6_mode & INTEL_RC6_ENABLE)
3381 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3382
5a7dc92a
ED		 3383 /* We don't use those on Haswell */
3384 if (!IS_HASWELL(dev)) {
3385 if (rc6_mode & INTEL_RC6p_ENABLE)
3386 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3387
5a7dc92a
ED		 3388 if (rc6_mode & INTEL_RC6pp_ENABLE)
3389 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3390 }
2b4e57bd
ED		 3391
3392 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3393 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3394 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3395 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3396
3397 I915_WRITE(GEN6_RC_CONTROL,
3398 rc6_mask |
3399 GEN6_RC_CTL_EI_MODE(1) |
3400 GEN6_RC_CTL_HW_ENABLE);
3401
92bd1bf0
RV		 3402 if (IS_HASWELL(dev)) {
3403 I915_WRITE(GEN6_RPNSWREQ,
3404 HSW_FREQUENCY(10));
3405 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3406 HSW_FREQUENCY(12));
3407 } else {
3408 I915_WRITE(GEN6_RPNSWREQ,
3409 GEN6_FREQUENCY(10) |
3410 GEN6_OFFSET(0) |
3411 GEN6_AGGRESSIVE_TURBO);
3412 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3413 GEN6_FREQUENCY(12));
3414 }
2b4e57bd
ED		 3415
3416 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3417 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3418 dev_priv->rps.max_delay << 24 |
3419 dev_priv->rps.min_delay << 16);
5a7dc92a 3420
1ee9ae32
DV		 3421 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3422 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3423 I915_WRITE(GEN6_RP_UP_EI, 66000);
3424 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3425
2b4e57bd
ED		 3426 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3427 I915_WRITE(GEN6_RP_CONTROL,
3428 GEN6_RP_MEDIA_TURBO |
89ba829e 3429 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3430 GEN6_RP_MEDIA_IS_GFX |
3431 GEN6_RP_ENABLE |
3432 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3433 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3434
42c0526c 3435 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3436 if (!ret) {
42c0526c
BW		 3437 pcu_mbox = 0;
3438 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3439 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3440 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3441 (dev_priv->rps.max_delay & 0xff) * 50,
3442 (pcu_mbox & 0xff) * 50);
31c77388 3443 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3444 }
3445 } else {
3446 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3447 }
3448
7b9e0ae6 3449 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3450
44fc7d5c 3451 gen6_enable_rps_interrupts(dev);
2b4e57bd 3452
31643d54
BW		 3453 rc6vids = 0;
3454 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3455 if (IS_GEN6(dev) && ret) {
3456 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3457 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3458 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3459 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3460 rc6vids &= 0xffff00;
3461 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3462 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3463 if (ret)
3464 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3465 }
3466
2b4e57bd 3467 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3468}
3469
79f5b2c7 3470static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3471{
79f5b2c7 3472 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3473 int min_freq = 15;
3ebecd07
CW		 3474 unsigned int gpu_freq;
3475 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3476 int scaling_factor = 180;
3477
4fc688ce 3478 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3479
2b4e57bd
ED		 3480 max_ia_freq = cpufreq_quick_get_max(0);
3481 /*
3482 * Default to measured freq if none found, PCU will ensure we don't go
3483 * over
3484 */
3485 if (!max_ia_freq)
3486 max_ia_freq = tsc_khz;
3487
3488 /* Convert from kHz to MHz */
3489 max_ia_freq /= 1000;
3490
3ebecd07
CW		 3491 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3492 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3493 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3494
2b4e57bd
ED		 3495 /*
3496 * For each potential GPU frequency, load a ring frequency we'd like
3497 * to use for memory access. We do this by specifying the IA frequency
3498 * the PCU should use as a reference to determine the ring frequency.
3499 */
c6a828d3 3500 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3501 gpu_freq--) {
c6a828d3 3502 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3503 unsigned int ia_freq = 0, ring_freq = 0;
3504
3505 if (IS_HASWELL(dev)) {
3506 ring_freq = (gpu_freq * 5 + 3) / 4;
3507 ring_freq = max(min_ring_freq, ring_freq);
3508 /* leave ia_freq as the default, chosen by cpufreq */
3509 } else {
3510 /* On older processors, there is no separate ring
3511 * clock domain, so in order to boost the bandwidth
3512 * of the ring, we need to upclock the CPU (ia_freq).
3513 *
3514 * For GPU frequencies less than 750MHz,
3515 * just use the lowest ring freq.
3516 */
3517 if (gpu_freq < min_freq)
3518 ia_freq = 800;
3519 else
3520 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3521 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3522 }
2b4e57bd 3523
42c0526c
BW		 3524 sandybridge_pcode_write(dev_priv,
3525 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3526 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3527 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3528 gpu_freq);
2b4e57bd 3529 }
2b4e57bd
ED		 3530}
3531
0a073b84
JB		 3532int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3533{
3534 u32 val, rp0;
3535
64936258 3536 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3537
3538 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3539 /* Clamp to max */
3540 rp0 = min_t(u32, rp0, 0xea);
3541
3542 return rp0;
3543}
3544
3545static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3546{
3547 u32 val, rpe;
3548
64936258 3549 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3550 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3551 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3552 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3553
3554 return rpe;
3555}
3556
3557int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3558{
64936258 3559 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3560}
3561
52ceb908
JB		 3562static void vlv_rps_timer_work(struct work_struct *work)
3563{
3564 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3565 rps.vlv_work.work);
3566
3567 /*
3568 * Timer fired, we must be idle. Drop to min voltage state.
3569 * Note: we use RPe here since it should match the
3570 * Vmin we were shooting for. That should give us better
3571 * perf when we come back out of RC6 than if we used the
3572 * min freq available.
3573 */
3574 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3575 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3576 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3577 mutex_unlock(&dev_priv->rps.hw_lock);
3578}
3579
c9cddffc
JB		 3580static void valleyview_setup_pctx(struct drm_device *dev)
3581{
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct drm_i915_gem_object *pctx;
3584 unsigned long pctx_paddr;
3585 u32 pcbr;
3586 int pctx_size = 24*1024;
3587
3588 pcbr = I915_READ(VLV_PCBR);
3589 if (pcbr) {
3590 /* BIOS set it up already, grab the pre-alloc'd space */
3591 int pcbr_offset;
3592
3593 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3594 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3595 pcbr_offset,
190d6cd5 3596 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3597 pctx_size);
3598 goto out;
3599 }
3600
3601 /*
3602 * From the Gunit register HAS:
3603 * The Gfx driver is expected to program this register and ensure
3604 * proper allocation within Gfx stolen memory. For example, this
3605 * register should be programmed such than the PCBR range does not
3606 * overlap with other ranges, such as the frame buffer, protected
3607 * memory, or any other relevant ranges.
3608 */
3609 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3610 if (!pctx) {
3611 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3612 return;
3613 }
3614
3615 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3616 I915_WRITE(VLV_PCBR, pctx_paddr);
3617
3618out:
3619 dev_priv->vlv_pctx = pctx;
3620}
3621
0a073b84
JB		 3622static void valleyview_enable_rps(struct drm_device *dev)
3623{
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_ring_buffer *ring;
73008b98 3626 u32 gtfifodbg, val;
0a073b84
JB		 3627 int i;
3628
3629 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3630
3631 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3632 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3633 I915_WRITE(GTFIFODBG, gtfifodbg);
3634 }
3635
c9cddffc
JB		 3636 valleyview_setup_pctx(dev);
3637
0a073b84
JB		 3638 gen6_gt_force_wake_get(dev_priv);
3639
3640 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3641 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3642 I915_WRITE(GEN6_RP_UP_EI, 66000);
3643 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3644
3645 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3646
3647 I915_WRITE(GEN6_RP_CONTROL,
3648 GEN6_RP_MEDIA_TURBO |
3649 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3650 GEN6_RP_MEDIA_IS_GFX |
3651 GEN6_RP_ENABLE |
3652 GEN6_RP_UP_BUSY_AVG |
3653 GEN6_RP_DOWN_IDLE_CONT);
3654
3655 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3656 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3657 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3658
3659 for_each_ring(ring, dev_priv, i)
3660 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3661
3662 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3663
3664 /* allows RC6 residency counter to work */
3665 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3666 I915_WRITE(GEN6_RC_CONTROL,
3667 GEN7_RC_CTL_TO_MODE);
3668
64936258 3669 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3670 switch ((val >> 6) & 3) {
3671 case 0:
3672 case 1:
3673 dev_priv->mem_freq = 800;
3674 break;
3675 case 2:
3676 dev_priv->mem_freq = 1066;
3677 break;
3678 case 3:
3679 dev_priv->mem_freq = 1333;
3680 break;
3681 }
0a073b84
JB		 3682 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3683
3684 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3685 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3686
0a073b84 3687 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3688 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3689 vlv_gpu_freq(dev_priv->mem_freq,
3690 dev_priv->rps.cur_delay),
3691 dev_priv->rps.cur_delay);
0a073b84
JB		 3692
3693 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3694 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3695 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3696 vlv_gpu_freq(dev_priv->mem_freq,
3697 dev_priv->rps.max_delay),
3698 dev_priv->rps.max_delay);
0a073b84 3699
73008b98
VS		 3700 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3701 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3702 vlv_gpu_freq(dev_priv->mem_freq,
3703 dev_priv->rps.rpe_delay),
3704 dev_priv->rps.rpe_delay);
0a073b84 3705
73008b98
VS		 3706 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3707 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3708 vlv_gpu_freq(dev_priv->mem_freq,
3709 dev_priv->rps.min_delay),
3710 dev_priv->rps.min_delay);
0a073b84 3711
73008b98
VS		 3712 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3713 vlv_gpu_freq(dev_priv->mem_freq,
3714 dev_priv->rps.rpe_delay),
3715 dev_priv->rps.rpe_delay);
0a073b84 3716
52ceb908
JB		 3717 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3718
73008b98 3719 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3720
44fc7d5c 3721 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3722
3723 gen6_gt_force_wake_put(dev_priv);
3724}
3725
930ebb46 3726void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3727{
3728 struct drm_i915_private *dev_priv = dev->dev_private;
3729
3e373948
DV		 3730 if (dev_priv->ips.renderctx) {
3731 i915_gem_object_unpin(dev_priv->ips.renderctx);
3732 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3733 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3734 }
3735
3e373948
DV		 3736 if (dev_priv->ips.pwrctx) {
3737 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3738 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3739 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3740 }
3741}
3742
930ebb46 3743static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3744{
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3746
3747 if (I915_READ(PWRCTXA)) {
3748 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3749 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3750 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3751 50);
3752
3753 I915_WRITE(PWRCTXA, 0);
3754 POSTING_READ(PWRCTXA);
3755
3756 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3757 POSTING_READ(RSTDBYCTL);
3758 }
2b4e57bd
ED		 3759}
3760
3761static int ironlake_setup_rc6(struct drm_device *dev)
3762{
3763 struct drm_i915_private *dev_priv = dev->dev_private;
3764
3e373948
DV		 3765 if (dev_priv->ips.renderctx == NULL)
3766 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3767 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3768 return -ENOMEM;
3769
3e373948
DV		 3770 if (dev_priv->ips.pwrctx == NULL)
3771 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3772 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3773 ironlake_teardown_rc6(dev);
3774 return -ENOMEM;
3775 }
3776
3777 return 0;
3778}
3779
930ebb46 3780static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3781{
3782 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3783 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3784 bool was_interruptible;
2b4e57bd
ED		 3785 int ret;
3786
3787 /* rc6 disabled by default due to repeated reports of hanging during
3788 * boot and resume.
3789 */
3790 if (!intel_enable_rc6(dev))
3791 return;
3792
79f5b2c7
DV		 3793 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3794
2b4e57bd 3795 ret = ironlake_setup_rc6(dev);
79f5b2c7 3796 if (ret)
2b4e57bd 3797 return;
2b4e57bd 3798
3e960501
CW		 3799 was_interruptible = dev_priv->mm.interruptible;
3800 dev_priv->mm.interruptible = false;
3801
2b4e57bd
ED		 3802 /*
3803 * GPU can automatically power down the render unit if given a page
3804 * to save state.
3805 */
6d90c952 3806 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3807 if (ret) {
3808 ironlake_teardown_rc6(dev);
3e960501 3809 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3810 return;
3811 }
3812
6d90c952
DV		 3813 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3814 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3815 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3816 MI_MM_SPACE_GTT |
3817 MI_SAVE_EXT_STATE_EN |
3818 MI_RESTORE_EXT_STATE_EN |
3819 MI_RESTORE_INHIBIT);
3820 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3821 intel_ring_emit(ring, MI_NOOP);
3822 intel_ring_emit(ring, MI_FLUSH);
3823 intel_ring_advance(ring);
2b4e57bd
ED		 3824
3825 /*
3826 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3827 * does an implicit flush, combined with MI_FLUSH above, it should be
3828 * safe to assume that renderctx is valid
3829 */
3e960501
CW		 3830 ret = intel_ring_idle(ring);
3831 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3832 if (ret) {
def27a58 3833 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3834 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3835 return;
3836 }
3837
f343c5f6 3838 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3839 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3840}
3841
dde18883
ED		 3842static unsigned long intel_pxfreq(u32 vidfreq)
3843{
3844 unsigned long freq;
3845 int div = (vidfreq & 0x3f0000) >> 16;
3846 int post = (vidfreq & 0x3000) >> 12;
3847 int pre = (vidfreq & 0x7);
3848
3849 if (!pre)
3850 return 0;
3851
3852 freq = ((div * 133333) / ((1<<post) * pre));
3853
3854 return freq;
3855}
3856
eb48eb00
DV		 3857static const struct cparams {
3858 u16 i;
3859 u16 t;
3860 u16 m;
3861 u16 c;
3862} cparams[] = {
3863 { 1, 1333, 301, 28664 },
3864 { 1, 1066, 294, 24460 },
3865 { 1, 800, 294, 25192 },
3866 { 0, 1333, 276, 27605 },
3867 { 0, 1066, 276, 27605 },
3868 { 0, 800, 231, 23784 },
3869};
3870
f531dcb2 3871static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3872{
3873 u64 total_count, diff, ret;
3874 u32 count1, count2, count3, m = 0, c = 0;
3875 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3876 int i;
3877
02d71956
DV		 3878 assert_spin_locked(&mchdev_lock);
3879
20e4d407 3880 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3881
3882 /* Prevent division-by-zero if we are asking too fast.
3883 * Also, we don't get interesting results if we are polling
3884 * faster than once in 10ms, so just return the saved value
3885 * in such cases.
3886 */
3887 if (diff1 <= 10)
20e4d407 3888 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3889
3890 count1 = I915_READ(DMIEC);
3891 count2 = I915_READ(DDREC);
3892 count3 = I915_READ(CSIEC);
3893
3894 total_count = count1 + count2 + count3;
3895
3896 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3897 if (total_count < dev_priv->ips.last_count1) {
3898 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3899 diff += total_count;
3900 } else {
20e4d407 3901 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3902 }
3903
3904 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3905 if (cparams[i].i == dev_priv->ips.c_m &&
3906 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3907 m = cparams[i].m;
3908 c = cparams[i].c;
3909 break;
3910 }
3911 }
3912
3913 diff = div_u64(diff, diff1);
3914 ret = ((m * diff) + c);
3915 ret = div_u64(ret, 10);
3916
20e4d407
DV		 3917 dev_priv->ips.last_count1 = total_count;
3918 dev_priv->ips.last_time1 = now;
eb48eb00 3919
20e4d407 3920 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3921
3922 return ret;
3923}
3924
f531dcb2
CW		 3925unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3926{
3927 unsigned long val;
3928
3929 if (dev_priv->info->gen != 5)
3930 return 0;
3931
3932 spin_lock_irq(&mchdev_lock);
3933
3934 val = __i915_chipset_val(dev_priv);
3935
3936 spin_unlock_irq(&mchdev_lock);
3937
3938 return val;
3939}
3940
eb48eb00
DV		 3941unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3942{
3943 unsigned long m, x, b;
3944 u32 tsfs;
3945
3946 tsfs = I915_READ(TSFS);
3947
3948 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3949 x = I915_READ8(TR1);
3950
3951 b = tsfs & TSFS_INTR_MASK;
3952
3953 return ((m * x) / 127) - b;
3954}
3955
3956static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3957{
3958 static const struct v_table {
3959 u16 vd; /* in .1 mil */
3960 u16 vm; /* in .1 mil */
3961 } v_table[] = {
3962 { 0, 0, },
3963 { 375, 0, },
3964 { 500, 0, },
3965 { 625, 0, },
3966 { 750, 0, },
3967 { 875, 0, },
3968 { 1000, 0, },
3969 { 1125, 0, },
3970 { 4125, 3000, },
3971 { 4125, 3000, },
3972 { 4125, 3000, },
3973 { 4125, 3000, },
3974 { 4125, 3000, },
3975 { 4125, 3000, },
3976 { 4125, 3000, },
3977 { 4125, 3000, },
3978 { 4125, 3000, },
3979 { 4125, 3000, },
3980 { 4125, 3000, },
3981 { 4125, 3000, },
3982 { 4125, 3000, },
3983 { 4125, 3000, },
3984 { 4125, 3000, },
3985 { 4125, 3000, },
3986 { 4125, 3000, },
3987 { 4125, 3000, },
3988 { 4125, 3000, },
3989 { 4125, 3000, },
3990 { 4125, 3000, },
3991 { 4125, 3000, },
3992 { 4125, 3000, },
3993 { 4125, 3000, },
3994 { 4250, 3125, },
3995 { 4375, 3250, },
3996 { 4500, 3375, },
3997 { 4625, 3500, },
3998 { 4750, 3625, },
3999 { 4875, 3750, },
4000 { 5000, 3875, },
4001 { 5125, 4000, },
4002 { 5250, 4125, },
4003 { 5375, 4250, },
4004 { 5500, 4375, },
4005 { 5625, 4500, },
4006 { 5750, 4625, },
4007 { 5875, 4750, },
4008 { 6000, 4875, },
4009 { 6125, 5000, },
4010 { 6250, 5125, },
4011 { 6375, 5250, },
4012 { 6500, 5375, },
4013 { 6625, 5500, },
4014 { 6750, 5625, },
4015 { 6875, 5750, },
4016 { 7000, 5875, },
4017 { 7125, 6000, },
4018 { 7250, 6125, },
4019 { 7375, 6250, },
4020 { 7500, 6375, },
4021 { 7625, 6500, },
4022 { 7750, 6625, },
4023 { 7875, 6750, },
4024 { 8000, 6875, },
4025 { 8125, 7000, },
4026 { 8250, 7125, },
4027 { 8375, 7250, },
4028 { 8500, 7375, },
4029 { 8625, 7500, },
4030 { 8750, 7625, },
4031 { 8875, 7750, },
4032 { 9000, 7875, },
4033 { 9125, 8000, },
4034 { 9250, 8125, },
4035 { 9375, 8250, },
4036 { 9500, 8375, },
4037 { 9625, 8500, },
4038 { 9750, 8625, },
4039 { 9875, 8750, },
4040 { 10000, 8875, },
4041 { 10125, 9000, },
4042 { 10250, 9125, },
4043 { 10375, 9250, },
4044 { 10500, 9375, },
4045 { 10625, 9500, },
4046 { 10750, 9625, },
4047 { 10875, 9750, },
4048 { 11000, 9875, },
4049 { 11125, 10000, },
4050 { 11250, 10125, },
4051 { 11375, 10250, },
4052 { 11500, 10375, },
4053 { 11625, 10500, },
4054 { 11750, 10625, },
4055 { 11875, 10750, },
4056 { 12000, 10875, },
4057 { 12125, 11000, },
4058 { 12250, 11125, },
4059 { 12375, 11250, },
4060 { 12500, 11375, },
4061 { 12625, 11500, },
4062 { 12750, 11625, },
4063 { 12875, 11750, },
4064 { 13000, 11875, },
4065 { 13125, 12000, },
4066 { 13250, 12125, },
4067 { 13375, 12250, },
4068 { 13500, 12375, },
4069 { 13625, 12500, },
4070 { 13750, 12625, },
4071 { 13875, 12750, },
4072 { 14000, 12875, },
4073 { 14125, 13000, },
4074 { 14250, 13125, },
4075 { 14375, 13250, },
4076 { 14500, 13375, },
4077 { 14625, 13500, },
4078 { 14750, 13625, },
4079 { 14875, 13750, },
4080 { 15000, 13875, },
4081 { 15125, 14000, },
4082 { 15250, 14125, },
4083 { 15375, 14250, },
4084 { 15500, 14375, },
4085 { 15625, 14500, },
4086 { 15750, 14625, },
4087 { 15875, 14750, },
4088 { 16000, 14875, },
4089 { 16125, 15000, },
4090 };
4091 if (dev_priv->info->is_mobile)
4092 return v_table[pxvid].vm;
4093 else
4094 return v_table[pxvid].vd;
4095}
4096
02d71956 4097static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4098{
4099 struct timespec now, diff1;
4100 u64 diff;
4101 unsigned long diffms;
4102 u32 count;
4103
02d71956 4104 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4105
4106 getrawmonotonic(&now);
20e4d407 4107 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4108
4109 /* Don't divide by 0 */
4110 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4111 if (!diffms)
4112 return;
4113
4114 count = I915_READ(GFXEC);
4115
20e4d407
DV		 4116 if (count < dev_priv->ips.last_count2) {
4117 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4118 diff += count;
4119 } else {
20e4d407 4120 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4121 }
4122
20e4d407
DV		 4123 dev_priv->ips.last_count2 = count;
4124 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4125
4126 /* More magic constants... */
4127 diff = diff * 1181;
4128 diff = div_u64(diff, diffms * 10);
20e4d407 4129 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4130}
4131
02d71956
DV		 4132void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4133{
4134 if (dev_priv->info->gen != 5)
4135 return;
4136
9270388e 4137 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4138
4139 __i915_update_gfx_val(dev_priv);
4140
9270388e 4141 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4142}
4143
f531dcb2 4144static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4145{
4146 unsigned long t, corr, state1, corr2, state2;
4147 u32 pxvid, ext_v;
4148
02d71956
DV		 4149 assert_spin_locked(&mchdev_lock);
4150
c6a828d3 4151 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4152 pxvid = (pxvid >> 24) & 0x7f;
4153 ext_v = pvid_to_extvid(dev_priv, pxvid);
4154
4155 state1 = ext_v;
4156
4157 t = i915_mch_val(dev_priv);
4158
4159 /* Revel in the empirically derived constants */
4160
4161 /* Correction factor in 1/100000 units */
4162 if (t > 80)
4163 corr = ((t * 2349) + 135940);
4164 else if (t >= 50)
4165 corr = ((t * 964) + 29317);
4166 else /* < 50 */
4167 corr = ((t * 301) + 1004);
4168
4169 corr = corr * ((150142 * state1) / 10000 - 78642);
4170 corr /= 100000;
20e4d407 4171 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4172
4173 state2 = (corr2 * state1) / 10000;
4174 state2 /= 100; /* convert to mW */
4175
02d71956 4176 __i915_update_gfx_val(dev_priv);
eb48eb00 4177
20e4d407 4178 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4179}
4180
f531dcb2
CW		 4181unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4182{
4183 unsigned long val;
4184
4185 if (dev_priv->info->gen != 5)
4186 return 0;
4187
4188 spin_lock_irq(&mchdev_lock);
4189
4190 val = __i915_gfx_val(dev_priv);
4191
4192 spin_unlock_irq(&mchdev_lock);
4193
4194 return val;
4195}
4196
eb48eb00
DV		 4197/**
4198 * i915_read_mch_val - return value for IPS use
4199 *
4200 * Calculate and return a value for the IPS driver to use when deciding whether
4201 * we have thermal and power headroom to increase CPU or GPU power budget.
4202 */
4203unsigned long i915_read_mch_val(void)
4204{
4205 struct drm_i915_private *dev_priv;
4206 unsigned long chipset_val, graphics_val, ret = 0;
4207
9270388e 4208 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4209 if (!i915_mch_dev)
4210 goto out_unlock;
4211 dev_priv = i915_mch_dev;
4212
f531dcb2
CW		 4213 chipset_val = __i915_chipset_val(dev_priv);
4214 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4215
4216 ret = chipset_val + graphics_val;
4217
4218out_unlock:
9270388e 4219 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4220
4221 return ret;
4222}
4223EXPORT_SYMBOL_GPL(i915_read_mch_val);
4224
4225/**
4226 * i915_gpu_raise - raise GPU frequency limit
4227 *
4228 * Raise the limit; IPS indicates we have thermal headroom.
4229 */
4230bool i915_gpu_raise(void)
4231{
4232 struct drm_i915_private *dev_priv;
4233 bool ret = true;
4234
9270388e 4235 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4236 if (!i915_mch_dev) {
4237 ret = false;
4238 goto out_unlock;
4239 }
4240 dev_priv = i915_mch_dev;
4241
20e4d407
DV		 4242 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4243 dev_priv->ips.max_delay--;
eb48eb00
DV		 4244
4245out_unlock:
9270388e 4246 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4247
4248 return ret;
4249}
4250EXPORT_SYMBOL_GPL(i915_gpu_raise);
4251
4252/**
4253 * i915_gpu_lower - lower GPU frequency limit
4254 *
4255 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4256 * frequency maximum.
4257 */
4258bool i915_gpu_lower(void)
4259{
4260 struct drm_i915_private *dev_priv;
4261 bool ret = true;
4262
9270388e 4263 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4264 if (!i915_mch_dev) {
4265 ret = false;
4266 goto out_unlock;
4267 }
4268 dev_priv = i915_mch_dev;
4269
20e4d407
DV		 4270 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4271 dev_priv->ips.max_delay++;
eb48eb00
DV		 4272
4273out_unlock:
9270388e 4274 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4275
4276 return ret;
4277}
4278EXPORT_SYMBOL_GPL(i915_gpu_lower);
4279
4280/**
4281 * i915_gpu_busy - indicate GPU business to IPS
4282 *
4283 * Tell the IPS driver whether or not the GPU is busy.
4284 */
4285bool i915_gpu_busy(void)
4286{
4287 struct drm_i915_private *dev_priv;
f047e395 4288 struct intel_ring_buffer *ring;
eb48eb00 4289 bool ret = false;
f047e395 4290 int i;
eb48eb00 4291
9270388e 4292 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4293 if (!i915_mch_dev)
4294 goto out_unlock;
4295 dev_priv = i915_mch_dev;
4296
f047e395
CW		 4297 for_each_ring(ring, dev_priv, i)
4298 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4299
4300out_unlock:
9270388e 4301 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4302
4303 return ret;
4304}
4305EXPORT_SYMBOL_GPL(i915_gpu_busy);
4306
4307/**
4308 * i915_gpu_turbo_disable - disable graphics turbo
4309 *
4310 * Disable graphics turbo by resetting the max frequency and setting the
4311 * current frequency to the default.
4312 */
4313bool i915_gpu_turbo_disable(void)
4314{
4315 struct drm_i915_private *dev_priv;
4316 bool ret = true;
4317
9270388e 4318 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4319 if (!i915_mch_dev) {
4320 ret = false;
4321 goto out_unlock;
4322 }
4323 dev_priv = i915_mch_dev;
4324
20e4d407 4325 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4326
20e4d407 4327 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4328 ret = false;
4329
4330out_unlock:
9270388e 4331 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4332
4333 return ret;
4334}
4335EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4336
4337/**
4338 * Tells the intel_ips driver that the i915 driver is now loaded, if
4339 * IPS got loaded first.
4340 *
4341 * This awkward dance is so that neither module has to depend on the
4342 * other in order for IPS to do the appropriate communication of
4343 * GPU turbo limits to i915.
4344 */
4345static void
4346ips_ping_for_i915_load(void)
4347{
4348 void (*link)(void);
4349
4350 link = symbol_get(ips_link_to_i915_driver);
4351 if (link) {
4352 link();
4353 symbol_put(ips_link_to_i915_driver);
4354 }
4355}
4356
4357void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4358{
02d71956
DV		 4359 /* We only register the i915 ips part with intel-ips once everything is
4360 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4361 spin_lock_irq(&mchdev_lock);
eb48eb00 4362 i915_mch_dev = dev_priv;
9270388e 4363 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4364
4365 ips_ping_for_i915_load();
4366}
4367
4368void intel_gpu_ips_teardown(void)
4369{
9270388e 4370 spin_lock_irq(&mchdev_lock);
eb48eb00 4371 i915_mch_dev = NULL;
9270388e 4372 spin_unlock_irq(&mchdev_lock);
eb48eb00 4373}
8090c6b9 4374static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377 u32 lcfuse;
4378 u8 pxw[16];
4379 int i;
4380
4381 /* Disable to program */
4382 I915_WRITE(ECR, 0);
4383 POSTING_READ(ECR);
4384
4385 /* Program energy weights for various events */
4386 I915_WRITE(SDEW, 0x15040d00);
4387 I915_WRITE(CSIEW0, 0x007f0000);
4388 I915_WRITE(CSIEW1, 0x1e220004);
4389 I915_WRITE(CSIEW2, 0x04000004);
4390
4391 for (i = 0; i < 5; i++)
4392 I915_WRITE(PEW + (i * 4), 0);
4393 for (i = 0; i < 3; i++)
4394 I915_WRITE(DEW + (i * 4), 0);
4395
4396 /* Program P-state weights to account for frequency power adjustment */
4397 for (i = 0; i < 16; i++) {
4398 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4399 unsigned long freq = intel_pxfreq(pxvidfreq);
4400 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4401 PXVFREQ_PX_SHIFT;
4402 unsigned long val;
4403
4404 val = vid * vid;
4405 val *= (freq / 1000);
4406 val *= 255;
4407 val /= (127*127*900);
4408 if (val > 0xff)
4409 DRM_ERROR("bad pxval: %ld\n", val);
4410 pxw[i] = val;
4411 }
4412 /* Render standby states get 0 weight */
4413 pxw[14] = 0;
4414 pxw[15] = 0;
4415
4416 for (i = 0; i < 4; i++) {
4417 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4418 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4419 I915_WRITE(PXW + (i * 4), val);
4420 }
4421
4422 /* Adjust magic regs to magic values (more experimental results) */
4423 I915_WRITE(OGW0, 0);
4424 I915_WRITE(OGW1, 0);
4425 I915_WRITE(EG0, 0x00007f00);
4426 I915_WRITE(EG1, 0x0000000e);
4427 I915_WRITE(EG2, 0x000e0000);
4428 I915_WRITE(EG3, 0x68000300);
4429 I915_WRITE(EG4, 0x42000000);
4430 I915_WRITE(EG5, 0x00140031);
4431 I915_WRITE(EG6, 0);
4432 I915_WRITE(EG7, 0);
4433
4434 for (i = 0; i < 8; i++)
4435 I915_WRITE(PXWL + (i * 4), 0);
4436
4437 /* Enable PMON + select events */
4438 I915_WRITE(ECR, 0x80000019);
4439
4440 lcfuse = I915_READ(LCFUSE02);
4441
20e4d407 4442 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4443}
4444
8090c6b9
DV		 4445void intel_disable_gt_powersave(struct drm_device *dev)
4446{
1a01ab3b
JB		 4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448
fd0c0642
DV		 4449 /* Interrupts should be disabled already to avoid re-arming. */
4450 WARN_ON(dev->irq_enabled);
4451
930ebb46 4452 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4453 ironlake_disable_drps(dev);
930ebb46 4454 ironlake_disable_rc6(dev);
0a073b84 4455 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4456 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4457 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4458 if (IS_VALLEYVIEW(dev))
4459 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4460 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4461 if (IS_VALLEYVIEW(dev))
4462 valleyview_disable_rps(dev);
4463 else
4464 gen6_disable_rps(dev);
4fc688ce 4465 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4466 }
8090c6b9
DV		 4467}
4468
1a01ab3b
JB		 4469static void intel_gen6_powersave_work(struct work_struct *work)
4470{
4471 struct drm_i915_private *dev_priv =
4472 container_of(work, struct drm_i915_private,
4473 rps.delayed_resume_work.work);
4474 struct drm_device *dev = dev_priv->dev;
4475
4fc688ce 4476 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4477
4478 if (IS_VALLEYVIEW(dev)) {
4479 valleyview_enable_rps(dev);
4480 } else {
4481 gen6_enable_rps(dev);
4482 gen6_update_ring_freq(dev);
4483 }
4fc688ce 4484 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4485}
4486
8090c6b9
DV		 4487void intel_enable_gt_powersave(struct drm_device *dev)
4488{
1a01ab3b
JB		 4489 struct drm_i915_private *dev_priv = dev->dev_private;
4490
8090c6b9
DV		 4491 if (IS_IRONLAKE_M(dev)) {
4492 ironlake_enable_drps(dev);
4493 ironlake_enable_rc6(dev);
4494 intel_init_emon(dev);
0a073b84 4495 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4496 /*
4497 * PCU communication is slow and this doesn't need to be
4498 * done at any specific time, so do this out of our fast path
4499 * to make resume and init faster.
4500 */
4501 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4502 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4503 }
4504}
4505
3107bd48
DV		 4506static void ibx_init_clock_gating(struct drm_device *dev)
4507{
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509
4510 /*
4511 * On Ibex Peak and Cougar Point, we need to disable clock
4512 * gating for the panel power sequencer or it will fail to
4513 * start up when no ports are active.
4514 */
4515 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4516}
4517
0e088b8f
VS		 4518static void g4x_disable_trickle_feed(struct drm_device *dev)
4519{
4520 struct drm_i915_private *dev_priv = dev->dev_private;
4521 int pipe;
4522
4523 for_each_pipe(pipe) {
4524 I915_WRITE(DSPCNTR(pipe),
4525 I915_READ(DSPCNTR(pipe)) |
4526 DISPPLANE_TRICKLE_FEED_DISABLE);
4527 intel_flush_display_plane(dev_priv, pipe);
4528 }
4529}
4530
1fa61106 4531static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4532{
4533 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4534 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4535
f1e8fa56
DL		 4536 /*
4537 * Required for FBC
4538 * WaFbcDisableDpfcClockGating:ilk
4539 */
4d47e4f5
DL		 4540 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4541 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4542 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4543
4544 I915_WRITE(PCH_3DCGDIS0,
4545 MARIUNIT_CLOCK_GATE_DISABLE |
4546 SVSMUNIT_CLOCK_GATE_DISABLE);
4547 I915_WRITE(PCH_3DCGDIS1,
4548 VFMUNIT_CLOCK_GATE_DISABLE);
4549
6f1d69b0
ED		 4550 /*
4551 * According to the spec the following bits should be set in
4552 * order to enable memory self-refresh
4553 * The bit 22/21 of 0x42004
4554 * The bit 5 of 0x42020
4555 * The bit 15 of 0x45000
4556 */
4557 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4558 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4559 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4560 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4561 I915_WRITE(DISP_ARB_CTL,
4562 (I915_READ(DISP_ARB_CTL) |
4563 DISP_FBC_WM_DIS));
4564 I915_WRITE(WM3_LP_ILK, 0);
4565 I915_WRITE(WM2_LP_ILK, 0);
4566 I915_WRITE(WM1_LP_ILK, 0);
4567
4568 /*
4569 * Based on the document from hardware guys the following bits
4570 * should be set unconditionally in order to enable FBC.
4571 * The bit 22 of 0x42000
4572 * The bit 22 of 0x42004
4573 * The bit 7,8,9 of 0x42020.
4574 */
4575 if (IS_IRONLAKE_M(dev)) {
4bb35334 4576 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4577 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4578 I915_READ(ILK_DISPLAY_CHICKEN1) |
4579 ILK_FBCQ_DIS);
4580 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4581 I915_READ(ILK_DISPLAY_CHICKEN2) |
4582 ILK_DPARB_GATE);
6f1d69b0
ED		 4583 }
4584
4d47e4f5
DL		 4585 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4586
6f1d69b0
ED		 4587 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4588 I915_READ(ILK_DISPLAY_CHICKEN2) |
4589 ILK_ELPIN_409_SELECT);
4590 I915_WRITE(_3D_CHICKEN2,
4591 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4592 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4593
ecdb4eb7 4594 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4595 I915_WRITE(CACHE_MODE_0,
4596 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4597
0e088b8f 4598 g4x_disable_trickle_feed(dev);
bdad2b2f 4599
3107bd48
DV		 4600 ibx_init_clock_gating(dev);
4601}
4602
4603static void cpt_init_clock_gating(struct drm_device *dev)
4604{
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 int pipe;
3f704fa2 4607 uint32_t val;
3107bd48
DV		 4608
4609 /*
4610 * On Ibex Peak and Cougar Point, we need to disable clock
4611 * gating for the panel power sequencer or it will fail to
4612 * start up when no ports are active.
4613 */
4614 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4615 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4616 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4617 /* The below fixes the weird display corruption, a few pixels shifted
4618 * downward, on (only) LVDS of some HP laptops with IVY.
4619 */
3f704fa2 4620 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4621 val = I915_READ(TRANS_CHICKEN2(pipe));
4622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4623 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4624 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4625 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4626 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4627 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4628 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4629 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4630 }
3107bd48
DV		 4631 /* WADP0ClockGatingDisable */
4632 for_each_pipe(pipe) {
4633 I915_WRITE(TRANS_CHICKEN1(pipe),
4634 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4635 }
6f1d69b0
ED		 4636}
4637
1d7aaa0c
DV		 4638static void gen6_check_mch_setup(struct drm_device *dev)
4639{
4640 struct drm_i915_private *dev_priv = dev->dev_private;
4641 uint32_t tmp;
4642
4643 tmp = I915_READ(MCH_SSKPD);
4644 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4645 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4646 DRM_INFO("This can cause pipe underruns and display issues.\n");
4647 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4648 }
4649}
4650
1fa61106 4651static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4652{
4653 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4654 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4655
231e54f6 4656 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4657
4658 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4659 I915_READ(ILK_DISPLAY_CHICKEN2) |
4660 ILK_ELPIN_409_SELECT);
4661
ecdb4eb7 4662 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4663 I915_WRITE(_3D_CHICKEN,
4664 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4665
ecdb4eb7 4666 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4667 if (IS_SNB_GT1(dev))
4668 I915_WRITE(GEN6_GT_MODE,
4669 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4670
6f1d69b0
ED		 4671 I915_WRITE(WM3_LP_ILK, 0);
4672 I915_WRITE(WM2_LP_ILK, 0);
4673 I915_WRITE(WM1_LP_ILK, 0);
4674
6f1d69b0 4675 I915_WRITE(CACHE_MODE_0,
50743298 4676 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4677
4678 I915_WRITE(GEN6_UCGCTL1,
4679 I915_READ(GEN6_UCGCTL1) |
4680 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4681 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4682
4683 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4684 * gating disable must be set. Failure to set it results in
4685 * flickering pixels due to Z write ordering failures after
4686 * some amount of runtime in the Mesa "fire" demo, and Unigine
4687 * Sanctuary and Tropics, and apparently anything else with
4688 * alpha test or pixel discard.
4689 *
4690 * According to the spec, bit 11 (RCCUNIT) must also be set,
4691 * but we didn't debug actual testcases to find it out.
0f846f81 4692 *
ecdb4eb7
DL		 4693 * Also apply WaDisableVDSUnitClockGating:snb and
4694 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4695 */
4696 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4697 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4698 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4699 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4700
4701 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4702 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4703 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4704
4705 /*
4706 * According to the spec the following bits should be
4707 * set in order to enable memory self-refresh and fbc:
4708 * The bit21 and bit22 of 0x42000
4709 * The bit21 and bit22 of 0x42004
4710 * The bit5 and bit7 of 0x42020
4711 * The bit14 of 0x70180
4712 * The bit14 of 0x71180
4bb35334
DL		 4713 *
4714 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4715 */
4716 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4717 I915_READ(ILK_DISPLAY_CHICKEN1) |
4718 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4719 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4720 I915_READ(ILK_DISPLAY_CHICKEN2) |
4721 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4722 I915_WRITE(ILK_DSPCLK_GATE_D,
4723 I915_READ(ILK_DSPCLK_GATE_D) |
4724 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4725 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4726
ecdb4eb7 4727 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4728 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4729 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4730
0e088b8f 4731 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4732
4733 /* The default value should be 0x200 according to docs, but the two
4734 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4735 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4736 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4737
4738 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4739
4740 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4741}
4742
4743static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4744{
4745 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4746
4747 reg &= ~GEN7_FF_SCHED_MASK;
4748 reg |= GEN7_FF_TS_SCHED_HW;
4749 reg |= GEN7_FF_VS_SCHED_HW;
4750 reg |= GEN7_FF_DS_SCHED_HW;
4751
41c0b3a8
BW		 4752 if (IS_HASWELL(dev_priv->dev))
4753 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4754
6f1d69b0
ED		 4755 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4756}
4757
17a303ec
PZ		 4758static void lpt_init_clock_gating(struct drm_device *dev)
4759{
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761
4762 /*
4763 * TODO: this bit should only be enabled when really needed, then
4764 * disabled when not needed anymore in order to save power.
4765 */
4766 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4767 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4768 I915_READ(SOUTH_DSPCLK_GATE_D) |
4769 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4770
4771 /* WADPOClockGatingDisable:hsw */
4772 I915_WRITE(_TRANSA_CHICKEN1,
4773 I915_READ(_TRANSA_CHICKEN1) |
4774 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4775}
4776
7d708ee4
ID		 4777static void lpt_suspend_hw(struct drm_device *dev)
4778{
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4780
4781 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4782 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4783
4784 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4785 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4786 }
4787}
4788
cad2a2d7
ED		 4789static void haswell_init_clock_gating(struct drm_device *dev)
4790{
4791 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4792
4793 I915_WRITE(WM3_LP_ILK, 0);
4794 I915_WRITE(WM2_LP_ILK, 0);
4795 I915_WRITE(WM1_LP_ILK, 0);
4796
4797 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4798 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4799 */
4800 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4801
ecdb4eb7 4802 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4803 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4804 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4805
ecdb4eb7 4806 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4807 I915_WRITE(GEN7_L3CNTLREG1,
4808 GEN7_WA_FOR_GEN7_L3_CONTROL);
4809 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4810 GEN7_WA_L3_CHICKEN_MODE);
4811
ecdb4eb7 4812 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4813 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4814 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4815 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4816
0e088b8f 4817 g4x_disable_trickle_feed(dev);
cad2a2d7 4818
ecdb4eb7 4819 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4820 gen7_setup_fixed_func_scheduler(dev_priv);
4821
ecdb4eb7 4822 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4823 I915_WRITE(CACHE_MODE_1,
4824 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4825
ecdb4eb7 4826 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4827 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4828 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4829
ecdb4eb7 4830 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4831 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4832
90a88643
PZ		 4833 /* WaRsPkgCStateDisplayPMReq:hsw */
4834 I915_WRITE(CHICKEN_PAR1_1,
4835 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4836
17a303ec 4837 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4838}
4839
1fa61106 4840static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4841{
4842 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4843 uint32_t snpcr;
6f1d69b0 4844
6f1d69b0
ED		 4845 I915_WRITE(WM3_LP_ILK, 0);
4846 I915_WRITE(WM2_LP_ILK, 0);
4847 I915_WRITE(WM1_LP_ILK, 0);
4848
231e54f6 4849 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4850
ecdb4eb7 4851 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4852 I915_WRITE(_3D_CHICKEN3,
4853 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4854
ecdb4eb7 4855 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4856 I915_WRITE(IVB_CHICKEN3,
4857 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4858 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4859
ecdb4eb7 4860 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4861 if (IS_IVB_GT1(dev))
4862 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4863 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4864 else
4865 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4866 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4867
ecdb4eb7 4868 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4869 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4870 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4871
ecdb4eb7 4872 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4873 I915_WRITE(GEN7_L3CNTLREG1,
4874 GEN7_WA_FOR_GEN7_L3_CONTROL);
4875 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4876 GEN7_WA_L3_CHICKEN_MODE);
4877 if (IS_IVB_GT1(dev))
4878 I915_WRITE(GEN7_ROW_CHICKEN2,
4879 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4880 else
4881 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4882 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4883
6f1d69b0 4884
ecdb4eb7 4885 /* WaForceL3Serialization:ivb */
61939d97
JB		 4886 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4887 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4888
0f846f81
JB		 4889 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4890 * gating disable must be set. Failure to set it results in
4891 * flickering pixels due to Z write ordering failures after
4892 * some amount of runtime in the Mesa "fire" demo, and Unigine
4893 * Sanctuary and Tropics, and apparently anything else with
4894 * alpha test or pixel discard.
4895 *
4896 * According to the spec, bit 11 (RCCUNIT) must also be set,
4897 * but we didn't debug actual testcases to find it out.
4898 *
4899 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4900 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4901 */
4902 I915_WRITE(GEN6_UCGCTL2,
4903 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4904 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4905
ecdb4eb7 4906 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4907 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4908 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4909 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4910
0e088b8f 4911 g4x_disable_trickle_feed(dev);
6f1d69b0 4912
ecdb4eb7 4913 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4914 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4915 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4916
ecdb4eb7 4917 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4918 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4919
ecdb4eb7 4920 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4921 I915_WRITE(CACHE_MODE_1,
4922 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4923
4924 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4925 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4926 snpcr |= GEN6_MBC_SNPCR_MED;
4927 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4928
ab5c608b
BW		 4929 if (!HAS_PCH_NOP(dev))
4930 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4931
4932 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4933}
4934
1fa61106 4935static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4936{
4937 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 4938
d7fe0cc0 4939 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4940
ecdb4eb7 4941 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4942 I915_WRITE(_3D_CHICKEN3,
4943 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4944
ecdb4eb7 4945 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4946 I915_WRITE(IVB_CHICKEN3,
4947 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4948 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4949
ecdb4eb7 4950 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4951 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4952 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4953 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4954
ecdb4eb7 4955 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4956 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4957 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4958
ecdb4eb7 4959 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4960 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4961 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4962
ecdb4eb7 4963 /* WaForceL3Serialization:vlv */
61939d97
JB		 4964 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4965 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4966
ecdb4eb7 4967 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4968 I915_WRITE(GEN7_ROW_CHICKEN2,
4969 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4970
ecdb4eb7 4971 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4972 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4973 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4974 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4975
ecdb4eb7 4976 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4977 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4978 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4979
0f846f81
JB		 4980
4981 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4982 * gating disable must be set. Failure to set it results in
4983 * flickering pixels due to Z write ordering failures after
4984 * some amount of runtime in the Mesa "fire" demo, and Unigine
4985 * Sanctuary and Tropics, and apparently anything else with
4986 * alpha test or pixel discard.
4987 *
4988 * According to the spec, bit 11 (RCCUNIT) must also be set,
4989 * but we didn't debug actual testcases to find it out.
4990 *
4991 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4992 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4993 *
ecdb4eb7
DL		 4994 * Also apply WaDisableVDSUnitClockGating:vlv and
4995 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4996 */
4997 I915_WRITE(GEN6_UCGCTL2,
4998 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4999 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5000 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5001 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5002 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5003
e3f33d46
JB		 5004 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5005
e0d8d59b 5006 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5007
6b26c86d
DV		 5008 I915_WRITE(CACHE_MODE_1,
5009 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5010
2d809570 5011 /*
ecdb4eb7 5012 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5013 * Disable clock gating on th GCFG unit to prevent a delay
5014 * in the reporting of vblank events.
5015 */
4e8c84a5
JB		 5016 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5017
5018 /* Conservative clock gating settings for now */
5019 I915_WRITE(0x9400, 0xffffffff);
5020 I915_WRITE(0x9404, 0xffffffff);
5021 I915_WRITE(0x9408, 0xffffffff);
5022 I915_WRITE(0x940c, 0xffffffff);
5023 I915_WRITE(0x9410, 0xffffffff);
5024 I915_WRITE(0x9414, 0xffffffff);
5025 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5026}
5027
1fa61106 5028static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5029{
5030 struct drm_i915_private *dev_priv = dev->dev_private;
5031 uint32_t dspclk_gate;
5032
5033 I915_WRITE(RENCLK_GATE_D1, 0);
5034 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5035 GS_UNIT_CLOCK_GATE_DISABLE |
5036 CL_UNIT_CLOCK_GATE_DISABLE);
5037 I915_WRITE(RAMCLK_GATE_D, 0);
5038 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5039 OVRUNIT_CLOCK_GATE_DISABLE |
5040 OVCUNIT_CLOCK_GATE_DISABLE;
5041 if (IS_GM45(dev))
5042 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5043 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5044
5045 /* WaDisableRenderCachePipelinedFlush */
5046 I915_WRITE(CACHE_MODE_0,
5047 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5048
0e088b8f 5049 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5050}
5051
1fa61106 5052static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5053{
5054 struct drm_i915_private *dev_priv = dev->dev_private;
5055
5056 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5057 I915_WRITE(RENCLK_GATE_D2, 0);
5058 I915_WRITE(DSPCLK_GATE_D, 0);
5059 I915_WRITE(RAMCLK_GATE_D, 0);
5060 I915_WRITE16(DEUC, 0);
20f94967
VS		 5061 I915_WRITE(MI_ARB_STATE,
5062 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5063}
5064
1fa61106 5065static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5066{
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068
5069 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5070 I965_RCC_CLOCK_GATE_DISABLE |
5071 I965_RCPB_CLOCK_GATE_DISABLE |
5072 I965_ISC_CLOCK_GATE_DISABLE |
5073 I965_FBC_CLOCK_GATE_DISABLE);
5074 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5075 I915_WRITE(MI_ARB_STATE,
5076 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5077}
5078
1fa61106 5079static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5080{
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 u32 dstate = I915_READ(D_STATE);
5083
5084 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5085 DSTATE_DOT_CLOCK_GATING;
5086 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5087
5088 if (IS_PINEVIEW(dev))
5089 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5090
5091 /* IIR "flip pending" means done if this bit is set */
5092 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5093}
5094
1fa61106 5095static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5096{
5097 struct drm_i915_private *dev_priv = dev->dev_private;
5098
5099 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5100}
5101
1fa61106 5102static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5103{
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105
5106 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5107}
5108
6f1d69b0
ED		 5109void intel_init_clock_gating(struct drm_device *dev)
5110{
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112
5113 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5114}
5115
7d708ee4
ID		 5116void intel_suspend_hw(struct drm_device *dev)
5117{
5118 if (HAS_PCH_LPT(dev))
5119 lpt_suspend_hw(dev);
5120}
5121
15d199ea
PZ		 5122/**
5123 * We should only use the power well if we explicitly asked the hardware to
5124 * enable it, so check if it's enabled and also check if we've requested it to
5125 * be enabled.
5126 */
b97186f0
PZ		 5127bool intel_display_power_enabled(struct drm_device *dev,
5128 enum intel_display_power_domain domain)
15d199ea
PZ		 5129{
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131
b97186f0
PZ		 5132 if (!HAS_POWER_WELL(dev))
5133 return true;
5134
5135 switch (domain) {
5136 case POWER_DOMAIN_PIPE_A:
5137 case POWER_DOMAIN_TRANSCODER_EDP:
5138 return true;
5139 case POWER_DOMAIN_PIPE_B:
5140 case POWER_DOMAIN_PIPE_C:
5141 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5142 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5143 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5144 case POWER_DOMAIN_TRANSCODER_A:
5145 case POWER_DOMAIN_TRANSCODER_B:
5146 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5147 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5148 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5149 default:
5150 BUG();
5151 }
15d199ea
PZ		 5152}
5153
a38911a3 5154static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5155{
5156 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5157 bool is_enabled, enable_requested;
5158 uint32_t tmp;
d0d3e513 5159
fa42e23c
PZ		 5160 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5161 is_enabled = tmp & HSW_PWR_WELL_STATE;
5162 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5163
fa42e23c
PZ		 5164 if (enable) {
5165 if (!enable_requested)
5166 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5167
fa42e23c
PZ		 5168 if (!is_enabled) {
5169 DRM_DEBUG_KMS("Enabling power well\n");
5170 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5171 HSW_PWR_WELL_STATE), 20))
5172 DRM_ERROR("Timeout enabling power well\n");
5173 }
5174 } else {
5175 if (enable_requested) {
5176 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5177 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5178 }
5179 }
fa42e23c 5180}
d0d3e513 5181
a38911a3
WX		 5182static struct i915_power_well *hsw_pwr;
5183
5184/* Display audio driver power well request */
5185void i915_request_power_well(void)
5186{
5187 if (WARN_ON(!hsw_pwr))
5188 return;
5189
5190 spin_lock_irq(&hsw_pwr->lock);
5191 if (!hsw_pwr->count++ &&
5192 !hsw_pwr->i915_request)
5193 __intel_set_power_well(hsw_pwr->device, true);
5194 spin_unlock_irq(&hsw_pwr->lock);
5195}
5196EXPORT_SYMBOL_GPL(i915_request_power_well);
5197
5198/* Display audio driver power well release */
5199void i915_release_power_well(void)
5200{
5201 if (WARN_ON(!hsw_pwr))
5202 return;
5203
5204 spin_lock_irq(&hsw_pwr->lock);
5205 WARN_ON(!hsw_pwr->count);
5206 if (!--hsw_pwr->count &&
5207 !hsw_pwr->i915_request)
5208 __intel_set_power_well(hsw_pwr->device, false);
5209 spin_unlock_irq(&hsw_pwr->lock);
5210}
5211EXPORT_SYMBOL_GPL(i915_release_power_well);
5212
5213int i915_init_power_well(struct drm_device *dev)
5214{
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216
5217 hsw_pwr = &dev_priv->power_well;
5218
5219 hsw_pwr->device = dev;
5220 spin_lock_init(&hsw_pwr->lock);
5221 hsw_pwr->count = 0;
5222
5223 return 0;
5224}
5225
5226void i915_remove_power_well(struct drm_device *dev)
5227{
5228 hsw_pwr = NULL;
5229}
5230
5231void intel_set_power_well(struct drm_device *dev, bool enable)
5232{
5233 struct drm_i915_private *dev_priv = dev->dev_private;
5234 struct i915_power_well *power_well = &dev_priv->power_well;
5235
5236 if (!HAS_POWER_WELL(dev))
5237 return;
5238
5239 if (!i915_disable_power_well && !enable)
5240 return;
5241
5242 spin_lock_irq(&power_well->lock);
5243 power_well->i915_request = enable;
5244
5245 /* only reject "disable" power well request */
5246 if (power_well->count && !enable) {
5247 spin_unlock_irq(&power_well->lock);
5248 return;
5249 }
5250
5251 __intel_set_power_well(dev, enable);
5252 spin_unlock_irq(&power_well->lock);
5253}
5254
fa42e23c
PZ		 5255/*
5256 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5257 * when not needed anymore. We have 4 registers that can request the power well
5258 * to be enabled, and it will only be disabled if none of the registers is
5259 * requesting it to be enabled.
d0d3e513 5260 */
fa42e23c 5261void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5262{
5263 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5264
86d52df6 5265 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5266 return;
5267
fa42e23c
PZ		 5268 /* For now, we need the power well to be always enabled. */
5269 intel_set_power_well(dev, true);
d0d3e513 5270
fa42e23c
PZ		 5271 /* We're taking over the BIOS, so clear any requests made by it since
5272 * the driver is in charge now. */
5273 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5274 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5275}
5276
1fa61106
ED		 5277/* Set up chip specific power management-related functions */
5278void intel_init_pm(struct drm_device *dev)
5279{
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281
5282 if (I915_HAS_FBC(dev)) {
5283 if (HAS_PCH_SPLIT(dev)) {
5284 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5285 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5286 dev_priv->display.enable_fbc =
5287 gen7_enable_fbc;
5288 else
5289 dev_priv->display.enable_fbc =
5290 ironlake_enable_fbc;
1fa61106
ED		 5291 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5292 } else if (IS_GM45(dev)) {
5293 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5294 dev_priv->display.enable_fbc = g4x_enable_fbc;
5295 dev_priv->display.disable_fbc = g4x_disable_fbc;
5296 } else if (IS_CRESTLINE(dev)) {
5297 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5298 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5299 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5300 }
5301 /* 855GM needs testing */
5302 }
5303
c921aba8
DV		 5304 /* For cxsr */
5305 if (IS_PINEVIEW(dev))
5306 i915_pineview_get_mem_freq(dev);
5307 else if (IS_GEN5(dev))
5308 i915_ironlake_get_mem_freq(dev);
5309
1fa61106
ED		 5310 /* For FIFO watermark updates */
5311 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5312 intel_setup_wm_latency(dev);
5313
1fa61106 5314 if (IS_GEN5(dev)) {
53615a5e
VS		 5315 if (dev_priv->wm.pri_latency[1] &&
5316 dev_priv->wm.spr_latency[1] &&
5317 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5318 dev_priv->display.update_wm = ironlake_update_wm;
5319 else {
5320 DRM_DEBUG_KMS("Failed to get proper latency. "
5321 "Disable CxSR\n");
5322 dev_priv->display.update_wm = NULL;
5323 }
5324 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5325 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5326 if (dev_priv->wm.pri_latency[0] &&
5327 dev_priv->wm.spr_latency[0] &&
5328 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5329 dev_priv->display.update_wm = sandybridge_update_wm;
5330 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5331 } else {
5332 DRM_DEBUG_KMS("Failed to read display plane latency. "
5333 "Disable CxSR\n");
5334 dev_priv->display.update_wm = NULL;
5335 }
5336 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5337 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5338 if (dev_priv->wm.pri_latency[0] &&
5339 dev_priv->wm.spr_latency[0] &&
5340 dev_priv->wm.cur_latency[0]) {
c43d0188 5341 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5342 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5343 } else {
5344 DRM_DEBUG_KMS("Failed to read display plane latency. "
5345 "Disable CxSR\n");
5346 dev_priv->display.update_wm = NULL;
5347 }
5348 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5349 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5350 if (dev_priv->wm.pri_latency[0] &&
5351 dev_priv->wm.spr_latency[0] &&
5352 dev_priv->wm.cur_latency[0]) {
1011d8c4 5353 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5354 dev_priv->display.update_sprite_wm =
5355 haswell_update_sprite_wm;
6b8a5eeb
ED		 5356 } else {
5357 DRM_DEBUG_KMS("Failed to read display plane latency. "
5358 "Disable CxSR\n");
5359 dev_priv->display.update_wm = NULL;
5360 }
cad2a2d7 5361 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5362 } else
5363 dev_priv->display.update_wm = NULL;
5364 } else if (IS_VALLEYVIEW(dev)) {
5365 dev_priv->display.update_wm = valleyview_update_wm;
5366 dev_priv->display.init_clock_gating =
5367 valleyview_init_clock_gating;
1fa61106
ED		 5368 } else if (IS_PINEVIEW(dev)) {
5369 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5370 dev_priv->is_ddr3,
5371 dev_priv->fsb_freq,
5372 dev_priv->mem_freq)) {
5373 DRM_INFO("failed to find known CxSR latency "
5374 "(found ddr%s fsb freq %d, mem freq %d), "
5375 "disabling CxSR\n",
5376 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5377 dev_priv->fsb_freq, dev_priv->mem_freq);
5378 /* Disable CxSR and never update its watermark again */
5379 pineview_disable_cxsr(dev);
5380 dev_priv->display.update_wm = NULL;
5381 } else
5382 dev_priv->display.update_wm = pineview_update_wm;
5383 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5384 } else if (IS_G4X(dev)) {
5385 dev_priv->display.update_wm = g4x_update_wm;
5386 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5387 } else if (IS_GEN4(dev)) {
5388 dev_priv->display.update_wm = i965_update_wm;
5389 if (IS_CRESTLINE(dev))
5390 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5391 else if (IS_BROADWATER(dev))
5392 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5393 } else if (IS_GEN3(dev)) {
5394 dev_priv->display.update_wm = i9xx_update_wm;
5395 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5396 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5397 } else if (IS_I865G(dev)) {
5398 dev_priv->display.update_wm = i830_update_wm;
5399 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5400 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5401 } else if (IS_I85X(dev)) {
5402 dev_priv->display.update_wm = i9xx_update_wm;
5403 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5404 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5405 } else {
5406 dev_priv->display.update_wm = i830_update_wm;
5407 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5408 if (IS_845G(dev))
5409 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5410 else
5411 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5412 }
5413}
5414
42c0526c
BW		 5415int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5416{
4fc688ce 5417 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5418
5419 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5420 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5421 return -EAGAIN;
5422 }
5423
5424 I915_WRITE(GEN6_PCODE_DATA, *val);
5425 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5426
5427 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5428 500)) {
5429 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5430 return -ETIMEDOUT;
5431 }
5432
5433 *val = I915_READ(GEN6_PCODE_DATA);
5434 I915_WRITE(GEN6_PCODE_DATA, 0);
5435
5436 return 0;
5437}
5438
5439int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5440{
4fc688ce 5441 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5442
5443 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5444 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5445 return -EAGAIN;
5446 }
5447
5448 I915_WRITE(GEN6_PCODE_DATA, val);
5449 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5450
5451 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5452 500)) {
5453 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5454 return -ETIMEDOUT;
5455 }
5456
5457 I915_WRITE(GEN6_PCODE_DATA, 0);
5458
5459 return 0;
5460}
a0e4e199 5461
855ba3be
JB		 5462int vlv_gpu_freq(int ddr_freq, int val)
5463{
5464 int mult, base;
5465
5466 switch (ddr_freq) {
5467 case 800:
5468 mult = 20;
5469 base = 120;
5470 break;
5471 case 1066:
5472 mult = 22;
5473 base = 133;
5474 break;
5475 case 1333:
5476 mult = 21;
5477 base = 125;
5478 break;
5479 default:
5480 return -1;
5481 }
5482
5483 return ((val - 0xbd) * mult) + base;
5484}
5485
5486int vlv_freq_opcode(int ddr_freq, int val)
5487{
5488 int mult, base;
5489
5490 switch (ddr_freq) {
5491 case 800:
5492 mult = 20;
5493 base = 120;
5494 break;
5495 case 1066:
5496 mult = 22;
5497 base = 133;
5498 break;
5499 case 1333:
5500 mult = 21;
5501 base = 125;
5502 break;
5503 default:
5504 return -1;
5505 }
5506
5507 val /= mult;
5508 val -= base / mult;
5509 val += 0xbd;
5510
5511 if (val > 0xea)
5512 val = 0xea;
5513
5514 return val;
5515}
5516
907b28c5
CW		 5517void intel_pm_init(struct drm_device *dev)
5518{
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520
5521 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5522 intel_gen6_powersave_work);
5523}
5524
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