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1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the framebuffer contents in-memory, aiming at reducing the required bandwidth during in-memory transfers and, therefore, reduce the power packet. | |
32 | * | |
33 | * The benefits of FBC are mostly visible with solid backgrounds and variation-less patterns. | |
34 | * | |
35 | * FBC-related functionality can be enabled by the means of the i915.i915_enable_fbc parameter | |
36 | */ | |
37 | ||
38 | void i8xx_disable_fbc(struct drm_device *dev) | |
39 | { | |
40 | struct drm_i915_private *dev_priv = dev->dev_private; | |
41 | u32 fbc_ctl; | |
42 | ||
43 | /* Disable compression */ | |
44 | fbc_ctl = I915_READ(FBC_CONTROL); | |
45 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
46 | return; | |
47 | ||
48 | fbc_ctl &= ~FBC_CTL_EN; | |
49 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
50 | ||
51 | /* Wait for compressing bit to clear */ | |
52 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
53 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
54 | return; | |
55 | } | |
56 | ||
57 | DRM_DEBUG_KMS("disabled FBC\n"); | |
58 | } | |
59 | ||
60 | void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
61 | { | |
62 | struct drm_device *dev = crtc->dev; | |
63 | struct drm_i915_private *dev_priv = dev->dev_private; | |
64 | struct drm_framebuffer *fb = crtc->fb; | |
65 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
66 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
67 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
68 | int cfb_pitch; | |
69 | int plane, i; | |
70 | u32 fbc_ctl, fbc_ctl2; | |
71 | ||
72 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; | |
73 | if (fb->pitches[0] < cfb_pitch) | |
74 | cfb_pitch = fb->pitches[0]; | |
75 | ||
76 | /* FBC_CTL wants 64B units */ | |
77 | cfb_pitch = (cfb_pitch / 64) - 1; | |
78 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
79 | ||
80 | /* Clear old tags */ | |
81 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
82 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
83 | ||
84 | /* Set it up... */ | |
85 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
86 | fbc_ctl2 |= plane; | |
87 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
88 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
89 | ||
90 | /* enable it... */ | |
91 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
92 | if (IS_I945GM(dev)) | |
93 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
94 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
95 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
96 | fbc_ctl |= obj->fence_reg; | |
97 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
98 | ||
99 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", | |
100 | cfb_pitch, crtc->y, intel_crtc->plane); | |
101 | } | |
102 | ||
103 | bool i8xx_fbc_enabled(struct drm_device *dev) | |
104 | { | |
105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
106 | ||
107 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
108 | } | |
109 | ||
110 | void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
111 | { | |
112 | struct drm_device *dev = crtc->dev; | |
113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
114 | struct drm_framebuffer *fb = crtc->fb; | |
115 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
116 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
118 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; | |
119 | unsigned long stall_watermark = 200; | |
120 | u32 dpfc_ctl; | |
121 | ||
122 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
123 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
124 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
125 | ||
126 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | | |
127 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
128 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
129 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
130 | ||
131 | /* enable it... */ | |
132 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
133 | ||
134 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | |
135 | } | |
136 | ||
137 | void g4x_disable_fbc(struct drm_device *dev) | |
138 | { | |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
140 | u32 dpfc_ctl; | |
141 | ||
142 | /* Disable compression */ | |
143 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
144 | if (dpfc_ctl & DPFC_CTL_EN) { | |
145 | dpfc_ctl &= ~DPFC_CTL_EN; | |
146 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
147 | ||
148 | DRM_DEBUG_KMS("disabled FBC\n"); | |
149 | } | |
150 | } | |
151 | ||
152 | bool g4x_fbc_enabled(struct drm_device *dev) | |
153 | { | |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
155 | ||
156 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
157 | } | |
158 | ||
159 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | |
160 | { | |
161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
162 | u32 blt_ecoskpd; | |
163 | ||
164 | /* Make sure blitter notifies FBC of writes */ | |
165 | gen6_gt_force_wake_get(dev_priv); | |
166 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); | |
167 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
168 | GEN6_BLITTER_LOCK_SHIFT; | |
169 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
170 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
171 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
172 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
173 | GEN6_BLITTER_LOCK_SHIFT); | |
174 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
175 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
176 | gen6_gt_force_wake_put(dev_priv); | |
177 | } | |
178 | ||
179 | void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
180 | { | |
181 | struct drm_device *dev = crtc->dev; | |
182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
183 | struct drm_framebuffer *fb = crtc->fb; | |
184 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
185 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
186 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
187 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; | |
188 | unsigned long stall_watermark = 200; | |
189 | u32 dpfc_ctl; | |
190 | ||
191 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
192 | dpfc_ctl &= DPFC_RESERVED; | |
193 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
194 | /* Set persistent mode for front-buffer rendering, ala X. */ | |
195 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
196 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); | |
197 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
198 | ||
199 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | | |
200 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
201 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
202 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
203 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); | |
204 | /* enable it... */ | |
205 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
206 | ||
207 | if (IS_GEN6(dev)) { | |
208 | I915_WRITE(SNB_DPFC_CTL_SA, | |
209 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
210 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
211 | sandybridge_blit_fbc_update(dev); | |
212 | } | |
213 | ||
214 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | |
215 | } | |
216 | ||
217 | void ironlake_disable_fbc(struct drm_device *dev) | |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | u32 dpfc_ctl; | |
221 | ||
222 | /* Disable compression */ | |
223 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
224 | if (dpfc_ctl & DPFC_CTL_EN) { | |
225 | dpfc_ctl &= ~DPFC_CTL_EN; | |
226 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
227 | ||
228 | DRM_DEBUG_KMS("disabled FBC\n"); | |
229 | } | |
230 | } | |
231 | ||
232 | bool ironlake_fbc_enabled(struct drm_device *dev) | |
233 | { | |
234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
235 | ||
236 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
237 | } | |
238 | ||
239 | bool intel_fbc_enabled(struct drm_device *dev) | |
240 | { | |
241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
242 | ||
243 | if (!dev_priv->display.fbc_enabled) | |
244 | return false; | |
245 | ||
246 | return dev_priv->display.fbc_enabled(dev); | |
247 | } | |
248 | ||
249 | static void intel_fbc_work_fn(struct work_struct *__work) | |
250 | { | |
251 | struct intel_fbc_work *work = | |
252 | container_of(to_delayed_work(__work), | |
253 | struct intel_fbc_work, work); | |
254 | struct drm_device *dev = work->crtc->dev; | |
255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
256 | ||
257 | mutex_lock(&dev->struct_mutex); | |
258 | if (work == dev_priv->fbc_work) { | |
259 | /* Double check that we haven't switched fb without cancelling | |
260 | * the prior work. | |
261 | */ | |
262 | if (work->crtc->fb == work->fb) { | |
263 | dev_priv->display.enable_fbc(work->crtc, | |
264 | work->interval); | |
265 | ||
266 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; | |
267 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
268 | dev_priv->cfb_y = work->crtc->y; | |
269 | } | |
270 | ||
271 | dev_priv->fbc_work = NULL; | |
272 | } | |
273 | mutex_unlock(&dev->struct_mutex); | |
274 | ||
275 | kfree(work); | |
276 | } | |
277 | ||
278 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
279 | { | |
280 | if (dev_priv->fbc_work == NULL) | |
281 | return; | |
282 | ||
283 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
284 | ||
285 | /* Synchronisation is provided by struct_mutex and checking of | |
286 | * dev_priv->fbc_work, so we can perform the cancellation | |
287 | * entirely asynchronously. | |
288 | */ | |
289 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
290 | /* tasklet was killed before being run, clean up */ | |
291 | kfree(dev_priv->fbc_work); | |
292 | ||
293 | /* Mark the work as no longer wanted so that if it does | |
294 | * wake-up (because the work was already running and waiting | |
295 | * for our mutex), it will discover that is no longer | |
296 | * necessary to run. | |
297 | */ | |
298 | dev_priv->fbc_work = NULL; | |
299 | } | |
300 | ||
301 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
302 | { | |
303 | struct intel_fbc_work *work; | |
304 | struct drm_device *dev = crtc->dev; | |
305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
306 | ||
307 | if (!dev_priv->display.enable_fbc) | |
308 | return; | |
309 | ||
310 | intel_cancel_fbc_work(dev_priv); | |
311 | ||
312 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
313 | if (work == NULL) { | |
314 | dev_priv->display.enable_fbc(crtc, interval); | |
315 | return; | |
316 | } | |
317 | ||
318 | work->crtc = crtc; | |
319 | work->fb = crtc->fb; | |
320 | work->interval = interval; | |
321 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
322 | ||
323 | dev_priv->fbc_work = work; | |
324 | ||
325 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
326 | ||
327 | /* Delay the actual enabling to let pageflipping cease and the | |
328 | * display to settle before starting the compression. Note that | |
329 | * this delay also serves a second purpose: it allows for a | |
330 | * vblank to pass after disabling the FBC before we attempt | |
331 | * to modify the control registers. | |
332 | * | |
333 | * A more complicated solution would involve tracking vblanks | |
334 | * following the termination of the page-flipping sequence | |
335 | * and indeed performing the enable as a co-routine and not | |
336 | * waiting synchronously upon the vblank. | |
337 | */ | |
338 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
339 | } | |
340 | ||
341 | void intel_disable_fbc(struct drm_device *dev) | |
342 | { | |
343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
344 | ||
345 | intel_cancel_fbc_work(dev_priv); | |
346 | ||
347 | if (!dev_priv->display.disable_fbc) | |
348 | return; | |
349 | ||
350 | dev_priv->display.disable_fbc(dev); | |
351 | dev_priv->cfb_plane = -1; | |
352 | } | |
353 | ||
354 | /** | |
355 | * intel_update_fbc - enable/disable FBC as needed | |
356 | * @dev: the drm_device | |
357 | * | |
358 | * Set up the framebuffer compression hardware at mode set time. We | |
359 | * enable it if possible: | |
360 | * - plane A only (on pre-965) | |
361 | * - no pixel mulitply/line duplication | |
362 | * - no alpha buffer discard | |
363 | * - no dual wide | |
364 | * - framebuffer <= 2048 in width, 1536 in height | |
365 | * | |
366 | * We can't assume that any compression will take place (worst case), | |
367 | * so the compressed buffer has to be the same size as the uncompressed | |
368 | * one. It also must reside (along with the line length buffer) in | |
369 | * stolen memory. | |
370 | * | |
371 | * We need to enable/disable FBC on a global basis. | |
372 | */ | |
373 | void intel_update_fbc(struct drm_device *dev) | |
374 | { | |
375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
376 | struct drm_crtc *crtc = NULL, *tmp_crtc; | |
377 | struct intel_crtc *intel_crtc; | |
378 | struct drm_framebuffer *fb; | |
379 | struct intel_framebuffer *intel_fb; | |
380 | struct drm_i915_gem_object *obj; | |
381 | int enable_fbc; | |
382 | ||
383 | DRM_DEBUG_KMS("\n"); | |
384 | ||
385 | if (!i915_powersave) | |
386 | return; | |
387 | ||
388 | if (!I915_HAS_FBC(dev)) | |
389 | return; | |
390 | ||
391 | /* | |
392 | * If FBC is already on, we just have to verify that we can | |
393 | * keep it that way... | |
394 | * Need to disable if: | |
395 | * - more than one pipe is active | |
396 | * - changing FBC params (stride, fence, mode) | |
397 | * - new fb is too large to fit in compressed buffer | |
398 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
399 | */ | |
400 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { | |
401 | if (tmp_crtc->enabled && tmp_crtc->fb) { | |
402 | if (crtc) { | |
403 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
404 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
405 | goto out_disable; | |
406 | } | |
407 | crtc = tmp_crtc; | |
408 | } | |
409 | } | |
410 | ||
411 | if (!crtc || crtc->fb == NULL) { | |
412 | DRM_DEBUG_KMS("no output, disabling\n"); | |
413 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
414 | goto out_disable; | |
415 | } | |
416 | ||
417 | intel_crtc = to_intel_crtc(crtc); | |
418 | fb = crtc->fb; | |
419 | intel_fb = to_intel_framebuffer(fb); | |
420 | obj = intel_fb->obj; | |
421 | ||
422 | enable_fbc = i915_enable_fbc; | |
423 | if (enable_fbc < 0) { | |
424 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
425 | enable_fbc = 1; | |
426 | if (INTEL_INFO(dev)->gen <= 6) | |
427 | enable_fbc = 0; | |
428 | } | |
429 | if (!enable_fbc) { | |
430 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
431 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; | |
432 | goto out_disable; | |
433 | } | |
434 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { | |
435 | DRM_DEBUG_KMS("framebuffer too large, disabling " | |
436 | "compression\n"); | |
437 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; | |
438 | goto out_disable; | |
439 | } | |
440 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || | |
441 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
442 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
443 | "disabling\n"); | |
444 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; | |
445 | goto out_disable; | |
446 | } | |
447 | if ((crtc->mode.hdisplay > 2048) || | |
448 | (crtc->mode.vdisplay > 1536)) { | |
449 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
450 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; | |
451 | goto out_disable; | |
452 | } | |
453 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { | |
454 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); | |
455 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; | |
456 | goto out_disable; | |
457 | } | |
458 | ||
459 | /* The use of a CPU fence is mandatory in order to detect writes | |
460 | * by the CPU to the scanout and trigger updates to the FBC. | |
461 | */ | |
462 | if (obj->tiling_mode != I915_TILING_X || | |
463 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
464 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
465 | dev_priv->no_fbc_reason = FBC_NOT_TILED; | |
466 | goto out_disable; | |
467 | } | |
468 | ||
469 | /* If the kernel debugger is active, always disable compression */ | |
470 | if (in_dbg_master()) | |
471 | goto out_disable; | |
472 | ||
473 | /* If the scanout has not changed, don't modify the FBC settings. | |
474 | * Note that we make the fundamental assumption that the fb->obj | |
475 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
476 | * without first being decoupled from the scanout and FBC disabled. | |
477 | */ | |
478 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
479 | dev_priv->cfb_fb == fb->base.id && | |
480 | dev_priv->cfb_y == crtc->y) | |
481 | return; | |
482 | ||
483 | if (intel_fbc_enabled(dev)) { | |
484 | /* We update FBC along two paths, after changing fb/crtc | |
485 | * configuration (modeswitching) and after page-flipping | |
486 | * finishes. For the latter, we know that not only did | |
487 | * we disable the FBC at the start of the page-flip | |
488 | * sequence, but also more than one vblank has passed. | |
489 | * | |
490 | * For the former case of modeswitching, it is possible | |
491 | * to switch between two FBC valid configurations | |
492 | * instantaneously so we do need to disable the FBC | |
493 | * before we can modify its control registers. We also | |
494 | * have to wait for the next vblank for that to take | |
495 | * effect. However, since we delay enabling FBC we can | |
496 | * assume that a vblank has passed since disabling and | |
497 | * that we can safely alter the registers in the deferred | |
498 | * callback. | |
499 | * | |
500 | * In the scenario that we go from a valid to invalid | |
501 | * and then back to valid FBC configuration we have | |
502 | * no strict enforcement that a vblank occurred since | |
503 | * disabling the FBC. However, along all current pipe | |
504 | * disabling paths we do need to wait for a vblank at | |
505 | * some point. And we wait before enabling FBC anyway. | |
506 | */ | |
507 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
508 | intel_disable_fbc(dev); | |
509 | } | |
510 | ||
511 | intel_enable_fbc(crtc, 500); | |
512 | return; | |
513 | ||
514 | out_disable: | |
515 | /* Multiple disables should be harmless */ | |
516 | if (intel_fbc_enabled(dev)) { | |
517 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
518 | intel_disable_fbc(dev); | |
519 | } | |
520 | } | |
521 | ||
b445e3b0 ED |
522 | static const struct cxsr_latency cxsr_latency_table[] = { |
523 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
524 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
525 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
526 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
527 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
528 | ||
529 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
530 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
531 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
532 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
533 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
534 | ||
535 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
536 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
537 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
538 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
539 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
540 | ||
541 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
542 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
543 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
544 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
545 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
546 | ||
547 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
548 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
549 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
550 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
551 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
552 | ||
553 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
554 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
555 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
556 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
557 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
558 | }; | |
559 | ||
560 | const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, | |
561 | int is_ddr3, | |
562 | int fsb, | |
563 | int mem) | |
564 | { | |
565 | const struct cxsr_latency *latency; | |
566 | int i; | |
567 | ||
568 | if (fsb == 0 || mem == 0) | |
569 | return NULL; | |
570 | ||
571 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
572 | latency = &cxsr_latency_table[i]; | |
573 | if (is_desktop == latency->is_desktop && | |
574 | is_ddr3 == latency->is_ddr3 && | |
575 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
576 | return latency; | |
577 | } | |
578 | ||
579 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
580 | ||
581 | return NULL; | |
582 | } | |
583 | ||
584 | void pineview_disable_cxsr(struct drm_device *dev) | |
585 | { | |
586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
587 | ||
588 | /* deactivate cxsr */ | |
589 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); | |
590 | } | |
591 | ||
592 | /* | |
593 | * Latency for FIFO fetches is dependent on several factors: | |
594 | * - memory configuration (speed, channels) | |
595 | * - chipset | |
596 | * - current MCH state | |
597 | * It can be fairly high in some situations, so here we assume a fairly | |
598 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
599 | * set this value too high, the FIFO will fetch frequently to stay full) | |
600 | * and power consumption (set it too low to save power and we might see | |
601 | * FIFO underruns and display "flicker"). | |
602 | * | |
603 | * A value of 5us seems to be a good balance; safe for very low end | |
604 | * platforms but not overly aggressive on lower latency configs. | |
605 | */ | |
606 | static const int latency_ns = 5000; | |
607 | ||
608 | int i9xx_get_fifo_size(struct drm_device *dev, int plane) | |
609 | { | |
610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
611 | uint32_t dsparb = I915_READ(DSPARB); | |
612 | int size; | |
613 | ||
614 | size = dsparb & 0x7f; | |
615 | if (plane) | |
616 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
617 | ||
618 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
619 | plane ? "B" : "A", size); | |
620 | ||
621 | return size; | |
622 | } | |
623 | ||
624 | int i85x_get_fifo_size(struct drm_device *dev, int plane) | |
625 | { | |
626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
627 | uint32_t dsparb = I915_READ(DSPARB); | |
628 | int size; | |
629 | ||
630 | size = dsparb & 0x1ff; | |
631 | if (plane) | |
632 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
633 | size >>= 1; /* Convert to cachelines */ | |
634 | ||
635 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
636 | plane ? "B" : "A", size); | |
637 | ||
638 | return size; | |
639 | } | |
640 | ||
641 | int i845_get_fifo_size(struct drm_device *dev, int plane) | |
642 | { | |
643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
644 | uint32_t dsparb = I915_READ(DSPARB); | |
645 | int size; | |
646 | ||
647 | size = dsparb & 0x7f; | |
648 | size >>= 2; /* Convert to cachelines */ | |
649 | ||
650 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
651 | plane ? "B" : "A", | |
652 | size); | |
653 | ||
654 | return size; | |
655 | } | |
656 | ||
657 | int i830_get_fifo_size(struct drm_device *dev, int plane) | |
658 | { | |
659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
660 | uint32_t dsparb = I915_READ(DSPARB); | |
661 | int size; | |
662 | ||
663 | size = dsparb & 0x7f; | |
664 | size >>= 1; /* Convert to cachelines */ | |
665 | ||
666 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
667 | plane ? "B" : "A", size); | |
668 | ||
669 | return size; | |
670 | } | |
671 | ||
672 | /* Pineview has different values for various configs */ | |
673 | static const struct intel_watermark_params pineview_display_wm = { | |
674 | PINEVIEW_DISPLAY_FIFO, | |
675 | PINEVIEW_MAX_WM, | |
676 | PINEVIEW_DFT_WM, | |
677 | PINEVIEW_GUARD_WM, | |
678 | PINEVIEW_FIFO_LINE_SIZE | |
679 | }; | |
680 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
681 | PINEVIEW_DISPLAY_FIFO, | |
682 | PINEVIEW_MAX_WM, | |
683 | PINEVIEW_DFT_HPLLOFF_WM, | |
684 | PINEVIEW_GUARD_WM, | |
685 | PINEVIEW_FIFO_LINE_SIZE | |
686 | }; | |
687 | static const struct intel_watermark_params pineview_cursor_wm = { | |
688 | PINEVIEW_CURSOR_FIFO, | |
689 | PINEVIEW_CURSOR_MAX_WM, | |
690 | PINEVIEW_CURSOR_DFT_WM, | |
691 | PINEVIEW_CURSOR_GUARD_WM, | |
692 | PINEVIEW_FIFO_LINE_SIZE, | |
693 | }; | |
694 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
695 | PINEVIEW_CURSOR_FIFO, | |
696 | PINEVIEW_CURSOR_MAX_WM, | |
697 | PINEVIEW_CURSOR_DFT_WM, | |
698 | PINEVIEW_CURSOR_GUARD_WM, | |
699 | PINEVIEW_FIFO_LINE_SIZE | |
700 | }; | |
701 | static const struct intel_watermark_params g4x_wm_info = { | |
702 | G4X_FIFO_SIZE, | |
703 | G4X_MAX_WM, | |
704 | G4X_MAX_WM, | |
705 | 2, | |
706 | G4X_FIFO_LINE_SIZE, | |
707 | }; | |
708 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
709 | I965_CURSOR_FIFO, | |
710 | I965_CURSOR_MAX_WM, | |
711 | I965_CURSOR_DFT_WM, | |
712 | 2, | |
713 | G4X_FIFO_LINE_SIZE, | |
714 | }; | |
715 | static const struct intel_watermark_params valleyview_wm_info = { | |
716 | VALLEYVIEW_FIFO_SIZE, | |
717 | VALLEYVIEW_MAX_WM, | |
718 | VALLEYVIEW_MAX_WM, | |
719 | 2, | |
720 | G4X_FIFO_LINE_SIZE, | |
721 | }; | |
722 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
723 | I965_CURSOR_FIFO, | |
724 | VALLEYVIEW_CURSOR_MAX_WM, | |
725 | I965_CURSOR_DFT_WM, | |
726 | 2, | |
727 | G4X_FIFO_LINE_SIZE, | |
728 | }; | |
729 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
730 | I965_CURSOR_FIFO, | |
731 | I965_CURSOR_MAX_WM, | |
732 | I965_CURSOR_DFT_WM, | |
733 | 2, | |
734 | I915_FIFO_LINE_SIZE, | |
735 | }; | |
736 | static const struct intel_watermark_params i945_wm_info = { | |
737 | I945_FIFO_SIZE, | |
738 | I915_MAX_WM, | |
739 | 1, | |
740 | 2, | |
741 | I915_FIFO_LINE_SIZE | |
742 | }; | |
743 | static const struct intel_watermark_params i915_wm_info = { | |
744 | I915_FIFO_SIZE, | |
745 | I915_MAX_WM, | |
746 | 1, | |
747 | 2, | |
748 | I915_FIFO_LINE_SIZE | |
749 | }; | |
750 | static const struct intel_watermark_params i855_wm_info = { | |
751 | I855GM_FIFO_SIZE, | |
752 | I915_MAX_WM, | |
753 | 1, | |
754 | 2, | |
755 | I830_FIFO_LINE_SIZE | |
756 | }; | |
757 | static const struct intel_watermark_params i830_wm_info = { | |
758 | I830_FIFO_SIZE, | |
759 | I915_MAX_WM, | |
760 | 1, | |
761 | 2, | |
762 | I830_FIFO_LINE_SIZE | |
763 | }; | |
764 | ||
765 | static const struct intel_watermark_params ironlake_display_wm_info = { | |
766 | ILK_DISPLAY_FIFO, | |
767 | ILK_DISPLAY_MAXWM, | |
768 | ILK_DISPLAY_DFTWM, | |
769 | 2, | |
770 | ILK_FIFO_LINE_SIZE | |
771 | }; | |
772 | static const struct intel_watermark_params ironlake_cursor_wm_info = { | |
773 | ILK_CURSOR_FIFO, | |
774 | ILK_CURSOR_MAXWM, | |
775 | ILK_CURSOR_DFTWM, | |
776 | 2, | |
777 | ILK_FIFO_LINE_SIZE | |
778 | }; | |
779 | static const struct intel_watermark_params ironlake_display_srwm_info = { | |
780 | ILK_DISPLAY_SR_FIFO, | |
781 | ILK_DISPLAY_MAX_SRWM, | |
782 | ILK_DISPLAY_DFT_SRWM, | |
783 | 2, | |
784 | ILK_FIFO_LINE_SIZE | |
785 | }; | |
786 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { | |
787 | ILK_CURSOR_SR_FIFO, | |
788 | ILK_CURSOR_MAX_SRWM, | |
789 | ILK_CURSOR_DFT_SRWM, | |
790 | 2, | |
791 | ILK_FIFO_LINE_SIZE | |
792 | }; | |
793 | ||
794 | static const struct intel_watermark_params sandybridge_display_wm_info = { | |
795 | SNB_DISPLAY_FIFO, | |
796 | SNB_DISPLAY_MAXWM, | |
797 | SNB_DISPLAY_DFTWM, | |
798 | 2, | |
799 | SNB_FIFO_LINE_SIZE | |
800 | }; | |
801 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { | |
802 | SNB_CURSOR_FIFO, | |
803 | SNB_CURSOR_MAXWM, | |
804 | SNB_CURSOR_DFTWM, | |
805 | 2, | |
806 | SNB_FIFO_LINE_SIZE | |
807 | }; | |
808 | static const struct intel_watermark_params sandybridge_display_srwm_info = { | |
809 | SNB_DISPLAY_SR_FIFO, | |
810 | SNB_DISPLAY_MAX_SRWM, | |
811 | SNB_DISPLAY_DFT_SRWM, | |
812 | 2, | |
813 | SNB_FIFO_LINE_SIZE | |
814 | }; | |
815 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { | |
816 | SNB_CURSOR_SR_FIFO, | |
817 | SNB_CURSOR_MAX_SRWM, | |
818 | SNB_CURSOR_DFT_SRWM, | |
819 | 2, | |
820 | SNB_FIFO_LINE_SIZE | |
821 | }; | |
822 | ||
823 | ||
824 | /** | |
825 | * intel_calculate_wm - calculate watermark level | |
826 | * @clock_in_khz: pixel clock | |
827 | * @wm: chip FIFO params | |
828 | * @pixel_size: display pixel size | |
829 | * @latency_ns: memory latency for the platform | |
830 | * | |
831 | * Calculate the watermark level (the level at which the display plane will | |
832 | * start fetching from memory again). Each chip has a different display | |
833 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
834 | * in the correct intel_watermark_params structure. | |
835 | * | |
836 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
837 | * on the pixel size. When it reaches the watermark level, it'll start | |
838 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
839 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
840 | * will occur, and a display engine hang could result. | |
841 | */ | |
842 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
843 | const struct intel_watermark_params *wm, | |
844 | int fifo_size, | |
845 | int pixel_size, | |
846 | unsigned long latency_ns) | |
847 | { | |
848 | long entries_required, wm_size; | |
849 | ||
850 | /* | |
851 | * Note: we need to make sure we don't overflow for various clock & | |
852 | * latency values. | |
853 | * clocks go from a few thousand to several hundred thousand. | |
854 | * latency is usually a few thousand | |
855 | */ | |
856 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
857 | 1000; | |
858 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
859 | ||
860 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
861 | ||
862 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
863 | ||
864 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
865 | ||
866 | /* Don't promote wm_size to unsigned... */ | |
867 | if (wm_size > (long)wm->max_wm) | |
868 | wm_size = wm->max_wm; | |
869 | if (wm_size <= 0) | |
870 | wm_size = wm->default_wm; | |
871 | return wm_size; | |
872 | } | |
873 | ||
874 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
875 | { | |
876 | struct drm_crtc *crtc, *enabled = NULL; | |
877 | ||
878 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
879 | if (crtc->enabled && crtc->fb) { | |
880 | if (enabled) | |
881 | return NULL; | |
882 | enabled = crtc; | |
883 | } | |
884 | } | |
885 | ||
886 | return enabled; | |
887 | } | |
888 | ||
889 | void pineview_update_wm(struct drm_device *dev) | |
890 | { | |
891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
892 | struct drm_crtc *crtc; | |
893 | const struct cxsr_latency *latency; | |
894 | u32 reg; | |
895 | unsigned long wm; | |
896 | ||
897 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
898 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
899 | if (!latency) { | |
900 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
901 | pineview_disable_cxsr(dev); | |
902 | return; | |
903 | } | |
904 | ||
905 | crtc = single_enabled_crtc(dev); | |
906 | if (crtc) { | |
907 | int clock = crtc->mode.clock; | |
908 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
909 | ||
910 | /* Display SR */ | |
911 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
912 | pineview_display_wm.fifo_size, | |
913 | pixel_size, latency->display_sr); | |
914 | reg = I915_READ(DSPFW1); | |
915 | reg &= ~DSPFW_SR_MASK; | |
916 | reg |= wm << DSPFW_SR_SHIFT; | |
917 | I915_WRITE(DSPFW1, reg); | |
918 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
919 | ||
920 | /* cursor SR */ | |
921 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
922 | pineview_display_wm.fifo_size, | |
923 | pixel_size, latency->cursor_sr); | |
924 | reg = I915_READ(DSPFW3); | |
925 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
926 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
927 | I915_WRITE(DSPFW3, reg); | |
928 | ||
929 | /* Display HPLL off SR */ | |
930 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
931 | pineview_display_hplloff_wm.fifo_size, | |
932 | pixel_size, latency->display_hpll_disable); | |
933 | reg = I915_READ(DSPFW3); | |
934 | reg &= ~DSPFW_HPLL_SR_MASK; | |
935 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
936 | I915_WRITE(DSPFW3, reg); | |
937 | ||
938 | /* cursor HPLL off SR */ | |
939 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
940 | pineview_display_hplloff_wm.fifo_size, | |
941 | pixel_size, latency->cursor_hpll_disable); | |
942 | reg = I915_READ(DSPFW3); | |
943 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
944 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
945 | I915_WRITE(DSPFW3, reg); | |
946 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
947 | ||
948 | /* activate cxsr */ | |
949 | I915_WRITE(DSPFW3, | |
950 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
951 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); | |
952 | } else { | |
953 | pineview_disable_cxsr(dev); | |
954 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
955 | } | |
956 | } | |
957 | ||
958 | static bool g4x_compute_wm0(struct drm_device *dev, | |
959 | int plane, | |
960 | const struct intel_watermark_params *display, | |
961 | int display_latency_ns, | |
962 | const struct intel_watermark_params *cursor, | |
963 | int cursor_latency_ns, | |
964 | int *plane_wm, | |
965 | int *cursor_wm) | |
966 | { | |
967 | struct drm_crtc *crtc; | |
968 | int htotal, hdisplay, clock, pixel_size; | |
969 | int line_time_us, line_count; | |
970 | int entries, tlb_miss; | |
971 | ||
972 | crtc = intel_get_crtc_for_plane(dev, plane); | |
973 | if (crtc->fb == NULL || !crtc->enabled) { | |
974 | *cursor_wm = cursor->guard_size; | |
975 | *plane_wm = display->guard_size; | |
976 | return false; | |
977 | } | |
978 | ||
979 | htotal = crtc->mode.htotal; | |
980 | hdisplay = crtc->mode.hdisplay; | |
981 | clock = crtc->mode.clock; | |
982 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
983 | ||
984 | /* Use the small buffer method to calculate plane watermark */ | |
985 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
986 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
987 | if (tlb_miss > 0) | |
988 | entries += tlb_miss; | |
989 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
990 | *plane_wm = entries + display->guard_size; | |
991 | if (*plane_wm > (int)display->max_wm) | |
992 | *plane_wm = display->max_wm; | |
993 | ||
994 | /* Use the large buffer method to calculate cursor watermark */ | |
995 | line_time_us = ((htotal * 1000) / clock); | |
996 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
997 | entries = line_count * 64 * pixel_size; | |
998 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
999 | if (tlb_miss > 0) | |
1000 | entries += tlb_miss; | |
1001 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1002 | *cursor_wm = entries + cursor->guard_size; | |
1003 | if (*cursor_wm > (int)cursor->max_wm) | |
1004 | *cursor_wm = (int)cursor->max_wm; | |
1005 | ||
1006 | return true; | |
1007 | } | |
1008 | ||
1009 | /* | |
1010 | * Check the wm result. | |
1011 | * | |
1012 | * If any calculated watermark values is larger than the maximum value that | |
1013 | * can be programmed into the associated watermark register, that watermark | |
1014 | * must be disabled. | |
1015 | */ | |
1016 | static bool g4x_check_srwm(struct drm_device *dev, | |
1017 | int display_wm, int cursor_wm, | |
1018 | const struct intel_watermark_params *display, | |
1019 | const struct intel_watermark_params *cursor) | |
1020 | { | |
1021 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
1022 | display_wm, cursor_wm); | |
1023 | ||
1024 | if (display_wm > display->max_wm) { | |
1025 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
1026 | display_wm, display->max_wm); | |
1027 | return false; | |
1028 | } | |
1029 | ||
1030 | if (cursor_wm > cursor->max_wm) { | |
1031 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
1032 | cursor_wm, cursor->max_wm); | |
1033 | return false; | |
1034 | } | |
1035 | ||
1036 | if (!(display_wm || cursor_wm)) { | |
1037 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
1038 | return false; | |
1039 | } | |
1040 | ||
1041 | return true; | |
1042 | } | |
1043 | ||
1044 | static bool g4x_compute_srwm(struct drm_device *dev, | |
1045 | int plane, | |
1046 | int latency_ns, | |
1047 | const struct intel_watermark_params *display, | |
1048 | const struct intel_watermark_params *cursor, | |
1049 | int *display_wm, int *cursor_wm) | |
1050 | { | |
1051 | struct drm_crtc *crtc; | |
1052 | int hdisplay, htotal, pixel_size, clock; | |
1053 | unsigned long line_time_us; | |
1054 | int line_count, line_size; | |
1055 | int small, large; | |
1056 | int entries; | |
1057 | ||
1058 | if (!latency_ns) { | |
1059 | *display_wm = *cursor_wm = 0; | |
1060 | return false; | |
1061 | } | |
1062 | ||
1063 | crtc = intel_get_crtc_for_plane(dev, plane); | |
1064 | hdisplay = crtc->mode.hdisplay; | |
1065 | htotal = crtc->mode.htotal; | |
1066 | clock = crtc->mode.clock; | |
1067 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
1068 | ||
1069 | line_time_us = (htotal * 1000) / clock; | |
1070 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
1071 | line_size = hdisplay * pixel_size; | |
1072 | ||
1073 | /* Use the minimum of the small and large buffer method for primary */ | |
1074 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1075 | large = line_count * line_size; | |
1076 | ||
1077 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1078 | *display_wm = entries + display->guard_size; | |
1079 | ||
1080 | /* calculate the self-refresh watermark for display cursor */ | |
1081 | entries = line_count * pixel_size * 64; | |
1082 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1083 | *cursor_wm = entries + cursor->guard_size; | |
1084 | ||
1085 | return g4x_check_srwm(dev, | |
1086 | *display_wm, *cursor_wm, | |
1087 | display, cursor); | |
1088 | } | |
1089 | ||
1090 | static bool vlv_compute_drain_latency(struct drm_device *dev, | |
1091 | int plane, | |
1092 | int *plane_prec_mult, | |
1093 | int *plane_dl, | |
1094 | int *cursor_prec_mult, | |
1095 | int *cursor_dl) | |
1096 | { | |
1097 | struct drm_crtc *crtc; | |
1098 | int clock, pixel_size; | |
1099 | int entries; | |
1100 | ||
1101 | crtc = intel_get_crtc_for_plane(dev, plane); | |
1102 | if (crtc->fb == NULL || !crtc->enabled) | |
1103 | return false; | |
1104 | ||
1105 | clock = crtc->mode.clock; /* VESA DOT Clock */ | |
1106 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ | |
1107 | ||
1108 | entries = (clock / 1000) * pixel_size; | |
1109 | *plane_prec_mult = (entries > 256) ? | |
1110 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1111 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * | |
1112 | pixel_size); | |
1113 | ||
1114 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ | |
1115 | *cursor_prec_mult = (entries > 256) ? | |
1116 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1117 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); | |
1118 | ||
1119 | return true; | |
1120 | } | |
1121 | ||
1122 | /* | |
1123 | * Update drain latency registers of memory arbiter | |
1124 | * | |
1125 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
1126 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
1127 | * latency value. | |
1128 | */ | |
1129 | ||
1130 | static void vlv_update_drain_latency(struct drm_device *dev) | |
1131 | { | |
1132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1133 | int planea_prec, planea_dl, planeb_prec, planeb_dl; | |
1134 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; | |
1135 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is | |
1136 | either 16 or 32 */ | |
1137 | ||
1138 | /* For plane A, Cursor A */ | |
1139 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, | |
1140 | &cursor_prec_mult, &cursora_dl)) { | |
1141 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1142 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; | |
1143 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1144 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; | |
1145 | ||
1146 | I915_WRITE(VLV_DDL1, cursora_prec | | |
1147 | (cursora_dl << DDL_CURSORA_SHIFT) | | |
1148 | planea_prec | planea_dl); | |
1149 | } | |
1150 | ||
1151 | /* For plane B, Cursor B */ | |
1152 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, | |
1153 | &cursor_prec_mult, &cursorb_dl)) { | |
1154 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1155 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; | |
1156 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1157 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; | |
1158 | ||
1159 | I915_WRITE(VLV_DDL2, cursorb_prec | | |
1160 | (cursorb_dl << DDL_CURSORB_SHIFT) | | |
1161 | planeb_prec | planeb_dl); | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
1166 | ||
1167 | void valleyview_update_wm(struct drm_device *dev) | |
1168 | { | |
1169 | static const int sr_latency_ns = 12000; | |
1170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1171 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1172 | int plane_sr, cursor_sr; | |
1173 | unsigned int enabled = 0; | |
1174 | ||
1175 | vlv_update_drain_latency(dev); | |
1176 | ||
1177 | if (g4x_compute_wm0(dev, 0, | |
1178 | &valleyview_wm_info, latency_ns, | |
1179 | &valleyview_cursor_wm_info, latency_ns, | |
1180 | &planea_wm, &cursora_wm)) | |
1181 | enabled |= 1; | |
1182 | ||
1183 | if (g4x_compute_wm0(dev, 1, | |
1184 | &valleyview_wm_info, latency_ns, | |
1185 | &valleyview_cursor_wm_info, latency_ns, | |
1186 | &planeb_wm, &cursorb_wm)) | |
1187 | enabled |= 2; | |
1188 | ||
1189 | plane_sr = cursor_sr = 0; | |
1190 | if (single_plane_enabled(enabled) && | |
1191 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1192 | sr_latency_ns, | |
1193 | &valleyview_wm_info, | |
1194 | &valleyview_cursor_wm_info, | |
1195 | &plane_sr, &cursor_sr)) | |
1196 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); | |
1197 | else | |
1198 | I915_WRITE(FW_BLC_SELF_VLV, | |
1199 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); | |
1200 | ||
1201 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1202 | planea_wm, cursora_wm, | |
1203 | planeb_wm, cursorb_wm, | |
1204 | plane_sr, cursor_sr); | |
1205 | ||
1206 | I915_WRITE(DSPFW1, | |
1207 | (plane_sr << DSPFW_SR_SHIFT) | | |
1208 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1209 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1210 | planea_wm); | |
1211 | I915_WRITE(DSPFW2, | |
1212 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
1213 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
1214 | I915_WRITE(DSPFW3, | |
1215 | (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT))); | |
1216 | } | |
1217 | ||
1218 | void g4x_update_wm(struct drm_device *dev) | |
1219 | { | |
1220 | static const int sr_latency_ns = 12000; | |
1221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1222 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1223 | int plane_sr, cursor_sr; | |
1224 | unsigned int enabled = 0; | |
1225 | ||
1226 | if (g4x_compute_wm0(dev, 0, | |
1227 | &g4x_wm_info, latency_ns, | |
1228 | &g4x_cursor_wm_info, latency_ns, | |
1229 | &planea_wm, &cursora_wm)) | |
1230 | enabled |= 1; | |
1231 | ||
1232 | if (g4x_compute_wm0(dev, 1, | |
1233 | &g4x_wm_info, latency_ns, | |
1234 | &g4x_cursor_wm_info, latency_ns, | |
1235 | &planeb_wm, &cursorb_wm)) | |
1236 | enabled |= 2; | |
1237 | ||
1238 | plane_sr = cursor_sr = 0; | |
1239 | if (single_plane_enabled(enabled) && | |
1240 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1241 | sr_latency_ns, | |
1242 | &g4x_wm_info, | |
1243 | &g4x_cursor_wm_info, | |
1244 | &plane_sr, &cursor_sr)) | |
1245 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | |
1246 | else | |
1247 | I915_WRITE(FW_BLC_SELF, | |
1248 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
1249 | ||
1250 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1251 | planea_wm, cursora_wm, | |
1252 | planeb_wm, cursorb_wm, | |
1253 | plane_sr, cursor_sr); | |
1254 | ||
1255 | I915_WRITE(DSPFW1, | |
1256 | (plane_sr << DSPFW_SR_SHIFT) | | |
1257 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1258 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1259 | planea_wm); | |
1260 | I915_WRITE(DSPFW2, | |
1261 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
1262 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
1263 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1264 | I915_WRITE(DSPFW3, | |
1265 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
1266 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1267 | } | |
1268 | ||
1269 | void i965_update_wm(struct drm_device *dev) | |
1270 | { | |
1271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1272 | struct drm_crtc *crtc; | |
1273 | int srwm = 1; | |
1274 | int cursor_sr = 16; | |
1275 | ||
1276 | /* Calc sr entries for one plane configs */ | |
1277 | crtc = single_enabled_crtc(dev); | |
1278 | if (crtc) { | |
1279 | /* self-refresh has much higher latency */ | |
1280 | static const int sr_latency_ns = 12000; | |
1281 | int clock = crtc->mode.clock; | |
1282 | int htotal = crtc->mode.htotal; | |
1283 | int hdisplay = crtc->mode.hdisplay; | |
1284 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
1285 | unsigned long line_time_us; | |
1286 | int entries; | |
1287 | ||
1288 | line_time_us = ((htotal * 1000) / clock); | |
1289 | ||
1290 | /* Use ns/us then divide to preserve precision */ | |
1291 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1292 | pixel_size * hdisplay; | |
1293 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1294 | srwm = I965_FIFO_SIZE - entries; | |
1295 | if (srwm < 0) | |
1296 | srwm = 1; | |
1297 | srwm &= 0x1ff; | |
1298 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1299 | entries, srwm); | |
1300 | ||
1301 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1302 | pixel_size * 64; | |
1303 | entries = DIV_ROUND_UP(entries, | |
1304 | i965_cursor_wm_info.cacheline_size); | |
1305 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1306 | (entries + i965_cursor_wm_info.guard_size); | |
1307 | ||
1308 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1309 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1310 | ||
1311 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1312 | "cursor %d\n", srwm, cursor_sr); | |
1313 | ||
1314 | if (IS_CRESTLINE(dev)) | |
1315 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | |
1316 | } else { | |
1317 | /* Turn off self refresh if both pipes are enabled */ | |
1318 | if (IS_CRESTLINE(dev)) | |
1319 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
1320 | & ~FW_BLC_SELF_EN); | |
1321 | } | |
1322 | ||
1323 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1324 | srwm); | |
1325 | ||
1326 | /* 965 has limitations... */ | |
1327 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
1328 | (8 << 16) | (8 << 8) | (8 << 0)); | |
1329 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); | |
1330 | /* update cursor SR watermark */ | |
1331 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1332 | } | |
1333 | ||
1334 | void i9xx_update_wm(struct drm_device *dev) | |
1335 | { | |
1336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1337 | const struct intel_watermark_params *wm_info; | |
1338 | uint32_t fwater_lo; | |
1339 | uint32_t fwater_hi; | |
1340 | int cwm, srwm = 1; | |
1341 | int fifo_size; | |
1342 | int planea_wm, planeb_wm; | |
1343 | struct drm_crtc *crtc, *enabled = NULL; | |
1344 | ||
1345 | if (IS_I945GM(dev)) | |
1346 | wm_info = &i945_wm_info; | |
1347 | else if (!IS_GEN2(dev)) | |
1348 | wm_info = &i915_wm_info; | |
1349 | else | |
1350 | wm_info = &i855_wm_info; | |
1351 | ||
1352 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1353 | crtc = intel_get_crtc_for_plane(dev, 0); | |
1354 | if (crtc->enabled && crtc->fb) { | |
1355 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
1356 | wm_info, fifo_size, | |
1357 | crtc->fb->bits_per_pixel / 8, | |
1358 | latency_ns); | |
1359 | enabled = crtc; | |
1360 | } else | |
1361 | planea_wm = fifo_size - wm_info->guard_size; | |
1362 | ||
1363 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1364 | crtc = intel_get_crtc_for_plane(dev, 1); | |
1365 | if (crtc->enabled && crtc->fb) { | |
1366 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
1367 | wm_info, fifo_size, | |
1368 | crtc->fb->bits_per_pixel / 8, | |
1369 | latency_ns); | |
1370 | if (enabled == NULL) | |
1371 | enabled = crtc; | |
1372 | else | |
1373 | enabled = NULL; | |
1374 | } else | |
1375 | planeb_wm = fifo_size - wm_info->guard_size; | |
1376 | ||
1377 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1378 | ||
1379 | /* | |
1380 | * Overlay gets an aggressive default since video jitter is bad. | |
1381 | */ | |
1382 | cwm = 2; | |
1383 | ||
1384 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
1385 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1386 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
1387 | else if (IS_I915GM(dev)) | |
1388 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
1389 | ||
1390 | /* Calc sr entries for one plane configs */ | |
1391 | if (HAS_FW_BLC(dev) && enabled) { | |
1392 | /* self-refresh has much higher latency */ | |
1393 | static const int sr_latency_ns = 6000; | |
1394 | int clock = enabled->mode.clock; | |
1395 | int htotal = enabled->mode.htotal; | |
1396 | int hdisplay = enabled->mode.hdisplay; | |
1397 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
1398 | unsigned long line_time_us; | |
1399 | int entries; | |
1400 | ||
1401 | line_time_us = (htotal * 1000) / clock; | |
1402 | ||
1403 | /* Use ns/us then divide to preserve precision */ | |
1404 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1405 | pixel_size * hdisplay; | |
1406 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1407 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1408 | srwm = wm_info->fifo_size - entries; | |
1409 | if (srwm < 0) | |
1410 | srwm = 1; | |
1411 | ||
1412 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1413 | I915_WRITE(FW_BLC_SELF, | |
1414 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1415 | else if (IS_I915GM(dev)) | |
1416 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1417 | } | |
1418 | ||
1419 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1420 | planea_wm, planeb_wm, cwm, srwm); | |
1421 | ||
1422 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1423 | fwater_hi = (cwm & 0x1f); | |
1424 | ||
1425 | /* Set request length to 8 cachelines per fetch */ | |
1426 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1427 | fwater_hi = fwater_hi | (1 << 8); | |
1428 | ||
1429 | I915_WRITE(FW_BLC, fwater_lo); | |
1430 | I915_WRITE(FW_BLC2, fwater_hi); | |
1431 | ||
1432 | if (HAS_FW_BLC(dev)) { | |
1433 | if (enabled) { | |
1434 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1435 | I915_WRITE(FW_BLC_SELF, | |
1436 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
1437 | else if (IS_I915GM(dev)) | |
1438 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
1439 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
1440 | } else | |
1441 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | void i830_update_wm(struct drm_device *dev) | |
1446 | { | |
1447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1448 | struct drm_crtc *crtc; | |
1449 | uint32_t fwater_lo; | |
1450 | int planea_wm; | |
1451 | ||
1452 | crtc = single_enabled_crtc(dev); | |
1453 | if (crtc == NULL) | |
1454 | return; | |
1455 | ||
1456 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, | |
1457 | dev_priv->display.get_fifo_size(dev, 0), | |
1458 | crtc->fb->bits_per_pixel / 8, | |
1459 | latency_ns); | |
1460 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
1461 | fwater_lo |= (3<<8) | planea_wm; | |
1462 | ||
1463 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1464 | ||
1465 | I915_WRITE(FW_BLC, fwater_lo); | |
1466 | } | |
1467 | ||
1468 | #define ILK_LP0_PLANE_LATENCY 700 | |
1469 | #define ILK_LP0_CURSOR_LATENCY 1300 | |
1470 | ||
1471 | /* | |
1472 | * Check the wm result. | |
1473 | * | |
1474 | * If any calculated watermark values is larger than the maximum value that | |
1475 | * can be programmed into the associated watermark register, that watermark | |
1476 | * must be disabled. | |
1477 | */ | |
1478 | static bool ironlake_check_srwm(struct drm_device *dev, int level, | |
1479 | int fbc_wm, int display_wm, int cursor_wm, | |
1480 | const struct intel_watermark_params *display, | |
1481 | const struct intel_watermark_params *cursor) | |
1482 | { | |
1483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1484 | ||
1485 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
1486 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
1487 | ||
1488 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
1489 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
1490 | fbc_wm, SNB_FBC_MAX_SRWM, level); | |
1491 | ||
1492 | /* fbc has it's own way to disable FBC WM */ | |
1493 | I915_WRITE(DISP_ARB_CTL, | |
1494 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
1495 | return false; | |
1496 | } | |
1497 | ||
1498 | if (display_wm > display->max_wm) { | |
1499 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", | |
1500 | display_wm, SNB_DISPLAY_MAX_SRWM, level); | |
1501 | return false; | |
1502 | } | |
1503 | ||
1504 | if (cursor_wm > cursor->max_wm) { | |
1505 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", | |
1506 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); | |
1507 | return false; | |
1508 | } | |
1509 | ||
1510 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
1511 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
1512 | return false; | |
1513 | } | |
1514 | ||
1515 | return true; | |
1516 | } | |
1517 | ||
1518 | /* | |
1519 | * Compute watermark values of WM[1-3], | |
1520 | */ | |
1521 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, | |
1522 | int latency_ns, | |
1523 | const struct intel_watermark_params *display, | |
1524 | const struct intel_watermark_params *cursor, | |
1525 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1526 | { | |
1527 | struct drm_crtc *crtc; | |
1528 | unsigned long line_time_us; | |
1529 | int hdisplay, htotal, pixel_size, clock; | |
1530 | int line_count, line_size; | |
1531 | int small, large; | |
1532 | int entries; | |
1533 | ||
1534 | if (!latency_ns) { | |
1535 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
1536 | return false; | |
1537 | } | |
1538 | ||
1539 | crtc = intel_get_crtc_for_plane(dev, plane); | |
1540 | hdisplay = crtc->mode.hdisplay; | |
1541 | htotal = crtc->mode.htotal; | |
1542 | clock = crtc->mode.clock; | |
1543 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
1544 | ||
1545 | line_time_us = (htotal * 1000) / clock; | |
1546 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
1547 | line_size = hdisplay * pixel_size; | |
1548 | ||
1549 | /* Use the minimum of the small and large buffer method for primary */ | |
1550 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1551 | large = line_count * line_size; | |
1552 | ||
1553 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1554 | *display_wm = entries + display->guard_size; | |
1555 | ||
1556 | /* | |
1557 | * Spec says: | |
1558 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 | |
1559 | */ | |
1560 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
1561 | ||
1562 | /* calculate the self-refresh watermark for display cursor */ | |
1563 | entries = line_count * pixel_size * 64; | |
1564 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1565 | *cursor_wm = entries + cursor->guard_size; | |
1566 | ||
1567 | return ironlake_check_srwm(dev, level, | |
1568 | *fbc_wm, *display_wm, *cursor_wm, | |
1569 | display, cursor); | |
1570 | } | |
1571 | ||
1572 | void ironlake_update_wm(struct drm_device *dev) | |
1573 | { | |
1574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1575 | int fbc_wm, plane_wm, cursor_wm; | |
1576 | unsigned int enabled; | |
1577 | ||
1578 | enabled = 0; | |
1579 | if (g4x_compute_wm0(dev, 0, | |
1580 | &ironlake_display_wm_info, | |
1581 | ILK_LP0_PLANE_LATENCY, | |
1582 | &ironlake_cursor_wm_info, | |
1583 | ILK_LP0_CURSOR_LATENCY, | |
1584 | &plane_wm, &cursor_wm)) { | |
1585 | I915_WRITE(WM0_PIPEA_ILK, | |
1586 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
1587 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
1588 | " plane %d, " "cursor: %d\n", | |
1589 | plane_wm, cursor_wm); | |
1590 | enabled |= 1; | |
1591 | } | |
1592 | ||
1593 | if (g4x_compute_wm0(dev, 1, | |
1594 | &ironlake_display_wm_info, | |
1595 | ILK_LP0_PLANE_LATENCY, | |
1596 | &ironlake_cursor_wm_info, | |
1597 | ILK_LP0_CURSOR_LATENCY, | |
1598 | &plane_wm, &cursor_wm)) { | |
1599 | I915_WRITE(WM0_PIPEB_ILK, | |
1600 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
1601 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
1602 | " plane %d, cursor: %d\n", | |
1603 | plane_wm, cursor_wm); | |
1604 | enabled |= 2; | |
1605 | } | |
1606 | ||
1607 | /* | |
1608 | * Calculate and update the self-refresh watermark only when one | |
1609 | * display plane is used. | |
1610 | */ | |
1611 | I915_WRITE(WM3_LP_ILK, 0); | |
1612 | I915_WRITE(WM2_LP_ILK, 0); | |
1613 | I915_WRITE(WM1_LP_ILK, 0); | |
1614 | ||
1615 | if (!single_plane_enabled(enabled)) | |
1616 | return; | |
1617 | enabled = ffs(enabled) - 1; | |
1618 | ||
1619 | /* WM1 */ | |
1620 | if (!ironlake_compute_srwm(dev, 1, enabled, | |
1621 | ILK_READ_WM1_LATENCY() * 500, | |
1622 | &ironlake_display_srwm_info, | |
1623 | &ironlake_cursor_srwm_info, | |
1624 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1625 | return; | |
1626 | ||
1627 | I915_WRITE(WM1_LP_ILK, | |
1628 | WM1_LP_SR_EN | | |
1629 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1630 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1631 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1632 | cursor_wm); | |
1633 | ||
1634 | /* WM2 */ | |
1635 | if (!ironlake_compute_srwm(dev, 2, enabled, | |
1636 | ILK_READ_WM2_LATENCY() * 500, | |
1637 | &ironlake_display_srwm_info, | |
1638 | &ironlake_cursor_srwm_info, | |
1639 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1640 | return; | |
1641 | ||
1642 | I915_WRITE(WM2_LP_ILK, | |
1643 | WM2_LP_EN | | |
1644 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1645 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1646 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1647 | cursor_wm); | |
1648 | ||
1649 | /* | |
1650 | * WM3 is unsupported on ILK, probably because we don't have latency | |
1651 | * data for that power state | |
1652 | */ | |
1653 | } | |
1654 | ||
1655 | void sandybridge_update_wm(struct drm_device *dev) | |
1656 | { | |
1657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1658 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
1659 | u32 val; | |
1660 | int fbc_wm, plane_wm, cursor_wm; | |
1661 | unsigned int enabled; | |
1662 | ||
1663 | enabled = 0; | |
1664 | if (g4x_compute_wm0(dev, 0, | |
1665 | &sandybridge_display_wm_info, latency, | |
1666 | &sandybridge_cursor_wm_info, latency, | |
1667 | &plane_wm, &cursor_wm)) { | |
1668 | val = I915_READ(WM0_PIPEA_ILK); | |
1669 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1670 | I915_WRITE(WM0_PIPEA_ILK, val | | |
1671 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1672 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
1673 | " plane %d, " "cursor: %d\n", | |
1674 | plane_wm, cursor_wm); | |
1675 | enabled |= 1; | |
1676 | } | |
1677 | ||
1678 | if (g4x_compute_wm0(dev, 1, | |
1679 | &sandybridge_display_wm_info, latency, | |
1680 | &sandybridge_cursor_wm_info, latency, | |
1681 | &plane_wm, &cursor_wm)) { | |
1682 | val = I915_READ(WM0_PIPEB_ILK); | |
1683 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1684 | I915_WRITE(WM0_PIPEB_ILK, val | | |
1685 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1686 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
1687 | " plane %d, cursor: %d\n", | |
1688 | plane_wm, cursor_wm); | |
1689 | enabled |= 2; | |
1690 | } | |
1691 | ||
1692 | /* IVB has 3 pipes */ | |
1693 | if (IS_IVYBRIDGE(dev) && | |
1694 | g4x_compute_wm0(dev, 2, | |
1695 | &sandybridge_display_wm_info, latency, | |
1696 | &sandybridge_cursor_wm_info, latency, | |
1697 | &plane_wm, &cursor_wm)) { | |
1698 | val = I915_READ(WM0_PIPEC_IVB); | |
1699 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1700 | I915_WRITE(WM0_PIPEC_IVB, val | | |
1701 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1702 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" | |
1703 | " plane %d, cursor: %d\n", | |
1704 | plane_wm, cursor_wm); | |
1705 | enabled |= 3; | |
1706 | } | |
1707 | ||
1708 | /* | |
1709 | * Calculate and update the self-refresh watermark only when one | |
1710 | * display plane is used. | |
1711 | * | |
1712 | * SNB support 3 levels of watermark. | |
1713 | * | |
1714 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
1715 | * and disabled in the descending order | |
1716 | * | |
1717 | */ | |
1718 | I915_WRITE(WM3_LP_ILK, 0); | |
1719 | I915_WRITE(WM2_LP_ILK, 0); | |
1720 | I915_WRITE(WM1_LP_ILK, 0); | |
1721 | ||
1722 | if (!single_plane_enabled(enabled) || | |
1723 | dev_priv->sprite_scaling_enabled) | |
1724 | return; | |
1725 | enabled = ffs(enabled) - 1; | |
1726 | ||
1727 | /* WM1 */ | |
1728 | if (!ironlake_compute_srwm(dev, 1, enabled, | |
1729 | SNB_READ_WM1_LATENCY() * 500, | |
1730 | &sandybridge_display_srwm_info, | |
1731 | &sandybridge_cursor_srwm_info, | |
1732 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1733 | return; | |
1734 | ||
1735 | I915_WRITE(WM1_LP_ILK, | |
1736 | WM1_LP_SR_EN | | |
1737 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1738 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1739 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1740 | cursor_wm); | |
1741 | ||
1742 | /* WM2 */ | |
1743 | if (!ironlake_compute_srwm(dev, 2, enabled, | |
1744 | SNB_READ_WM2_LATENCY() * 500, | |
1745 | &sandybridge_display_srwm_info, | |
1746 | &sandybridge_cursor_srwm_info, | |
1747 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1748 | return; | |
1749 | ||
1750 | I915_WRITE(WM2_LP_ILK, | |
1751 | WM2_LP_EN | | |
1752 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1753 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1754 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1755 | cursor_wm); | |
1756 | ||
1757 | /* WM3 */ | |
1758 | if (!ironlake_compute_srwm(dev, 3, enabled, | |
1759 | SNB_READ_WM3_LATENCY() * 500, | |
1760 | &sandybridge_display_srwm_info, | |
1761 | &sandybridge_cursor_srwm_info, | |
1762 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1763 | return; | |
1764 | ||
1765 | I915_WRITE(WM3_LP_ILK, | |
1766 | WM3_LP_EN | | |
1767 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1768 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1769 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1770 | cursor_wm); | |
1771 | } | |
1772 | ||
1773 | static bool | |
1774 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, | |
1775 | uint32_t sprite_width, int pixel_size, | |
1776 | const struct intel_watermark_params *display, | |
1777 | int display_latency_ns, int *sprite_wm) | |
1778 | { | |
1779 | struct drm_crtc *crtc; | |
1780 | int clock; | |
1781 | int entries, tlb_miss; | |
1782 | ||
1783 | crtc = intel_get_crtc_for_plane(dev, plane); | |
1784 | if (crtc->fb == NULL || !crtc->enabled) { | |
1785 | *sprite_wm = display->guard_size; | |
1786 | return false; | |
1787 | } | |
1788 | ||
1789 | clock = crtc->mode.clock; | |
1790 | ||
1791 | /* Use the small buffer method to calculate the sprite watermark */ | |
1792 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
1793 | tlb_miss = display->fifo_size*display->cacheline_size - | |
1794 | sprite_width * 8; | |
1795 | if (tlb_miss > 0) | |
1796 | entries += tlb_miss; | |
1797 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
1798 | *sprite_wm = entries + display->guard_size; | |
1799 | if (*sprite_wm > (int)display->max_wm) | |
1800 | *sprite_wm = display->max_wm; | |
1801 | ||
1802 | return true; | |
1803 | } | |
1804 | ||
1805 | static bool | |
1806 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, | |
1807 | uint32_t sprite_width, int pixel_size, | |
1808 | const struct intel_watermark_params *display, | |
1809 | int latency_ns, int *sprite_wm) | |
1810 | { | |
1811 | struct drm_crtc *crtc; | |
1812 | unsigned long line_time_us; | |
1813 | int clock; | |
1814 | int line_count, line_size; | |
1815 | int small, large; | |
1816 | int entries; | |
1817 | ||
1818 | if (!latency_ns) { | |
1819 | *sprite_wm = 0; | |
1820 | return false; | |
1821 | } | |
1822 | ||
1823 | crtc = intel_get_crtc_for_plane(dev, plane); | |
1824 | clock = crtc->mode.clock; | |
1825 | if (!clock) { | |
1826 | *sprite_wm = 0; | |
1827 | return false; | |
1828 | } | |
1829 | ||
1830 | line_time_us = (sprite_width * 1000) / clock; | |
1831 | if (!line_time_us) { | |
1832 | *sprite_wm = 0; | |
1833 | return false; | |
1834 | } | |
1835 | ||
1836 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
1837 | line_size = sprite_width * pixel_size; | |
1838 | ||
1839 | /* Use the minimum of the small and large buffer method for primary */ | |
1840 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1841 | large = line_count * line_size; | |
1842 | ||
1843 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1844 | *sprite_wm = entries + display->guard_size; | |
1845 | ||
1846 | return *sprite_wm > 0x3ff ? false : true; | |
1847 | } | |
1848 | ||
1849 | void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, | |
1850 | uint32_t sprite_width, int pixel_size) | |
1851 | { | |
1852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1853 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
1854 | u32 val; | |
1855 | int sprite_wm, reg; | |
1856 | int ret; | |
1857 | ||
1858 | switch (pipe) { | |
1859 | case 0: | |
1860 | reg = WM0_PIPEA_ILK; | |
1861 | break; | |
1862 | case 1: | |
1863 | reg = WM0_PIPEB_ILK; | |
1864 | break; | |
1865 | case 2: | |
1866 | reg = WM0_PIPEC_IVB; | |
1867 | break; | |
1868 | default: | |
1869 | return; /* bad pipe */ | |
1870 | } | |
1871 | ||
1872 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, | |
1873 | &sandybridge_display_wm_info, | |
1874 | latency, &sprite_wm); | |
1875 | if (!ret) { | |
1876 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", | |
1877 | pipe); | |
1878 | return; | |
1879 | } | |
1880 | ||
1881 | val = I915_READ(reg); | |
1882 | val &= ~WM0_PIPE_SPRITE_MASK; | |
1883 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | |
1884 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); | |
1885 | ||
1886 | ||
1887 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
1888 | pixel_size, | |
1889 | &sandybridge_display_srwm_info, | |
1890 | SNB_READ_WM1_LATENCY() * 500, | |
1891 | &sprite_wm); | |
1892 | if (!ret) { | |
1893 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", | |
1894 | pipe); | |
1895 | return; | |
1896 | } | |
1897 | I915_WRITE(WM1S_LP_ILK, sprite_wm); | |
1898 | ||
1899 | /* Only IVB has two more LP watermarks for sprite */ | |
1900 | if (!IS_IVYBRIDGE(dev)) | |
1901 | return; | |
1902 | ||
1903 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
1904 | pixel_size, | |
1905 | &sandybridge_display_srwm_info, | |
1906 | SNB_READ_WM2_LATENCY() * 500, | |
1907 | &sprite_wm); | |
1908 | if (!ret) { | |
1909 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", | |
1910 | pipe); | |
1911 | return; | |
1912 | } | |
1913 | I915_WRITE(WM2S_LP_IVB, sprite_wm); | |
1914 | ||
1915 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
1916 | pixel_size, | |
1917 | &sandybridge_display_srwm_info, | |
1918 | SNB_READ_WM3_LATENCY() * 500, | |
1919 | &sprite_wm); | |
1920 | if (!ret) { | |
1921 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", | |
1922 | pipe); | |
1923 | return; | |
1924 | } | |
1925 | I915_WRITE(WM3S_LP_IVB, sprite_wm); | |
1926 | } | |
1927 | ||
1928 | /** | |
1929 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
1930 | * | |
1931 | * Calculate watermark values for the various WM regs based on current mode | |
1932 | * and plane configuration. | |
1933 | * | |
1934 | * There are several cases to deal with here: | |
1935 | * - normal (i.e. non-self-refresh) | |
1936 | * - self-refresh (SR) mode | |
1937 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
1938 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
1939 | * lines), so need to account for TLB latency | |
1940 | * | |
1941 | * The normal calculation is: | |
1942 | * watermark = dotclock * bytes per pixel * latency | |
1943 | * where latency is platform & configuration dependent (we assume pessimal | |
1944 | * values here). | |
1945 | * | |
1946 | * The SR calculation is: | |
1947 | * watermark = (trunc(latency/line time)+1) * surface width * | |
1948 | * bytes per pixel | |
1949 | * where | |
1950 | * line time = htotal / dotclock | |
1951 | * surface width = hdisplay for normal plane and 64 for cursor | |
1952 | * and latency is assumed to be high, as above. | |
1953 | * | |
1954 | * The final value programmed to the register should always be rounded up, | |
1955 | * and include an extra 2 entries to account for clock crossings. | |
1956 | * | |
1957 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
1958 | * to set the non-SR watermarks to 8. | |
1959 | */ | |
1960 | void intel_update_watermarks(struct drm_device *dev) | |
1961 | { | |
1962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1963 | ||
1964 | if (dev_priv->display.update_wm) | |
1965 | dev_priv->display.update_wm(dev); | |
1966 | } | |
1967 | ||
1968 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, | |
1969 | uint32_t sprite_width, int pixel_size) | |
1970 | { | |
1971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1972 | ||
1973 | if (dev_priv->display.update_sprite_wm) | |
1974 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, | |
1975 | pixel_size); | |
1976 | } | |
1977 |