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drm/i915: Be optimistic about future display engines having 7 WM levels
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL		 68 gen9_init_clock_gating(dev);
69
669506e7 70 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 78
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 82 }
8bc0ccf6 83
2caa3b26 84 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
2caa3b26
DL		 89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 91 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 92 }
81e231af 93
8bc0ccf6
DL		 94 if (INTEL_REVID(dev) <= SKL_REVID_E0)
95 /* WaDisableLSQCROPERFforOCL:skl */
96 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
97 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 98}
99
a82abe43
ID		 100static void bxt_init_clock_gating(struct drm_device *dev)
101{
32608ca2
ID		 102 struct drm_i915_private *dev_priv = dev->dev_private;
103
a82abe43 104 gen9_init_clock_gating(dev);
32608ca2
ID		 105
106 /*
107 * FIXME:
108 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 109 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID		 110 */
111 /* WaDisableSDEUnitClockGating:bxt */
112 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW		 113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 115
e3a29055
RB		 116 /* FIXME: apply on A0 only */
117 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
a82abe43
ID		 118}
119
c921aba8
DV		 120static void i915_pineview_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u32 tmp;
124
125 tmp = I915_READ(CLKCFG);
126
127 switch (tmp & CLKCFG_FSB_MASK) {
128 case CLKCFG_FSB_533:
129 dev_priv->fsb_freq = 533; /* 133*4 */
130 break;
131 case CLKCFG_FSB_800:
132 dev_priv->fsb_freq = 800; /* 200*4 */
133 break;
134 case CLKCFG_FSB_667:
135 dev_priv->fsb_freq = 667; /* 167*4 */
136 break;
137 case CLKCFG_FSB_400:
138 dev_priv->fsb_freq = 400; /* 100*4 */
139 break;
140 }
141
142 switch (tmp & CLKCFG_MEM_MASK) {
143 case CLKCFG_MEM_533:
144 dev_priv->mem_freq = 533;
145 break;
146 case CLKCFG_MEM_667:
147 dev_priv->mem_freq = 667;
148 break;
149 case CLKCFG_MEM_800:
150 dev_priv->mem_freq = 800;
151 break;
152 }
153
154 /* detect pineview DDR3 setting */
155 tmp = I915_READ(CSHRDDR3CTL);
156 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
157}
158
159static void i915_ironlake_get_mem_freq(struct drm_device *dev)
160{
50227e1c 161 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 162 u16 ddrpll, csipll;
163
164 ddrpll = I915_READ16(DDRMPLL1);
165 csipll = I915_READ16(CSIPLL0);
166
167 switch (ddrpll & 0xff) {
168 case 0xc:
169 dev_priv->mem_freq = 800;
170 break;
171 case 0x10:
172 dev_priv->mem_freq = 1066;
173 break;
174 case 0x14:
175 dev_priv->mem_freq = 1333;
176 break;
177 case 0x18:
178 dev_priv->mem_freq = 1600;
179 break;
180 default:
181 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
182 ddrpll & 0xff);
183 dev_priv->mem_freq = 0;
184 break;
185 }
186
20e4d407 187 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 188
189 switch (csipll & 0x3ff) {
190 case 0x00c:
191 dev_priv->fsb_freq = 3200;
192 break;
193 case 0x00e:
194 dev_priv->fsb_freq = 3733;
195 break;
196 case 0x010:
197 dev_priv->fsb_freq = 4266;
198 break;
199 case 0x012:
200 dev_priv->fsb_freq = 4800;
201 break;
202 case 0x014:
203 dev_priv->fsb_freq = 5333;
204 break;
205 case 0x016:
206 dev_priv->fsb_freq = 5866;
207 break;
208 case 0x018:
209 dev_priv->fsb_freq = 6400;
210 break;
211 default:
212 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
213 csipll & 0x3ff);
214 dev_priv->fsb_freq = 0;
215 break;
216 }
217
218 if (dev_priv->fsb_freq == 3200) {
20e4d407 219 dev_priv->ips.c_m = 0;
c921aba8 220 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 221 dev_priv->ips.c_m = 1;
c921aba8 222 } else {
20e4d407 223 dev_priv->ips.c_m = 2;
c921aba8
DV		 224 }
225}
226
b445e3b0
ED		 227static const struct cxsr_latency cxsr_latency_table[] = {
228 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
229 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
230 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
231 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
232 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
233
234 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
235 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
236 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
237 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
238 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
239
240 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
241 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
242 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
243 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
244 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
245
246 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
247 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
248 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
249 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
250 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
251
252 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
253 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
254 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
255 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
256 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
257
258 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
259 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
260 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
261 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
262 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
263};
264
63c62275 265static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 266 int is_ddr3,
267 int fsb,
268 int mem)
269{
270 const struct cxsr_latency *latency;
271 int i;
272
273 if (fsb == 0 || mem == 0)
274 return NULL;
275
276 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
277 latency = &cxsr_latency_table[i];
278 if (is_desktop == latency->is_desktop &&
279 is_ddr3 == latency->is_ddr3 &&
280 fsb == latency->fsb_freq && mem == latency->mem_freq)
281 return latency;
282 }
283
284 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
285
286 return NULL;
287}
288
fc1ac8de
VS		 289static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
290{
291 u32 val;
292
293 mutex_lock(&dev_priv->rps.hw_lock);
294
295 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
296 if (enable)
297 val &= ~FORCE_DDR_HIGH_FREQ;
298 else
299 val |= FORCE_DDR_HIGH_FREQ;
300 val &= ~FORCE_DDR_LOW_FREQ;
301 val |= FORCE_DDR_FREQ_REQ_ACK;
302 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
303
304 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
305 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
306 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
307
308 mutex_unlock(&dev_priv->rps.hw_lock);
309}
310
cfb41411
VS		 311static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
312{
313 u32 val;
314
315 mutex_lock(&dev_priv->rps.hw_lock);
316
317 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
318 if (enable)
319 val |= DSP_MAXFIFO_PM5_ENABLE;
320 else
321 val &= ~DSP_MAXFIFO_PM5_ENABLE;
322 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
323
324 mutex_unlock(&dev_priv->rps.hw_lock);
325}
326
f4998963
VS		 327#define FW_WM(value, plane) \
328 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
329
5209b1f4 330void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 331{
5209b1f4
ID		 332 struct drm_device *dev = dev_priv->dev;
333 u32 val;
b445e3b0 334
5209b1f4
ID		 335 if (IS_VALLEYVIEW(dev)) {
336 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
cfb41411
VS		 337 if (IS_CHERRYVIEW(dev))
338 chv_set_memory_pm5(dev_priv, enable);
5209b1f4
ID		 339 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
340 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
341 } else if (IS_PINEVIEW(dev)) {
342 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
343 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
344 I915_WRITE(DSPFW3, val);
345 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
346 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
347 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
348 I915_WRITE(FW_BLC_SELF, val);
349 } else if (IS_I915GM(dev)) {
350 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
351 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
352 I915_WRITE(INSTPM, val);
353 } else {
354 return;
355 }
b445e3b0 356
5209b1f4
ID		 357 DRM_DEBUG_KMS("memory self-refresh is %s\n",
358 enable ? "enabled" : "disabled");
b445e3b0
ED		 359}
360
fc1ac8de 361
b445e3b0
ED		 362/*
363 * Latency for FIFO fetches is dependent on several factors:
364 * - memory configuration (speed, channels)
365 * - chipset
366 * - current MCH state
367 * It can be fairly high in some situations, so here we assume a fairly
368 * pessimal value. It's a tradeoff between extra memory fetches (if we
369 * set this value too high, the FIFO will fetch frequently to stay full)
370 * and power consumption (set it too low to save power and we might see
371 * FIFO underruns and display "flicker").
372 *
373 * A value of 5us seems to be a good balance; safe for very low end
374 * platforms but not overly aggressive on lower latency configs.
375 */
5aef6003 376static const int pessimal_latency_ns = 5000;
b445e3b0 377
b5004720
VS		 378#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
379 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
380
381static int vlv_get_fifo_size(struct drm_device *dev,
382 enum pipe pipe, int plane)
383{
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 int sprite0_start, sprite1_start, size;
386
387 switch (pipe) {
388 uint32_t dsparb, dsparb2, dsparb3;
389 case PIPE_A:
390 dsparb = I915_READ(DSPARB);
391 dsparb2 = I915_READ(DSPARB2);
392 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
393 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
394 break;
395 case PIPE_B:
396 dsparb = I915_READ(DSPARB);
397 dsparb2 = I915_READ(DSPARB2);
398 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
399 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
400 break;
401 case PIPE_C:
402 dsparb2 = I915_READ(DSPARB2);
403 dsparb3 = I915_READ(DSPARB3);
404 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
405 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
406 break;
407 default:
408 return 0;
409 }
410
411 switch (plane) {
412 case 0:
413 size = sprite0_start;
414 break;
415 case 1:
416 size = sprite1_start - sprite0_start;
417 break;
418 case 2:
419 size = 512 - 1 - sprite1_start;
420 break;
421 default:
422 return 0;
423 }
424
425 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
426 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
427 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
428 size);
429
430 return size;
431}
432
1fa61106 433static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 434{
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 uint32_t dsparb = I915_READ(DSPARB);
437 int size;
438
439 size = dsparb & 0x7f;
440 if (plane)
441 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
442
443 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
444 plane ? "B" : "A", size);
445
446 return size;
447}
448
feb56b93 449static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 450{
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 uint32_t dsparb = I915_READ(DSPARB);
453 int size;
454
455 size = dsparb & 0x1ff;
456 if (plane)
457 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
458 size >>= 1; /* Convert to cachelines */
459
460 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
461 plane ? "B" : "A", size);
462
463 return size;
464}
465
1fa61106 466static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469 uint32_t dsparb = I915_READ(DSPARB);
470 int size;
471
472 size = dsparb & 0x7f;
473 size >>= 2; /* Convert to cachelines */
474
475 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
476 plane ? "B" : "A",
477 size);
478
479 return size;
480}
481
b445e3b0
ED		 482/* Pineview has different values for various configs */
483static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 484 .fifo_size = PINEVIEW_DISPLAY_FIFO,
485 .max_wm = PINEVIEW_MAX_WM,
486 .default_wm = PINEVIEW_DFT_WM,
487 .guard_size = PINEVIEW_GUARD_WM,
488 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 489};
490static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 491 .fifo_size = PINEVIEW_DISPLAY_FIFO,
492 .max_wm = PINEVIEW_MAX_WM,
493 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
494 .guard_size = PINEVIEW_GUARD_WM,
495 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 498 .fifo_size = PINEVIEW_CURSOR_FIFO,
499 .max_wm = PINEVIEW_CURSOR_MAX_WM,
500 .default_wm = PINEVIEW_CURSOR_DFT_WM,
501 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
502 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 505 .fifo_size = PINEVIEW_CURSOR_FIFO,
506 .max_wm = PINEVIEW_CURSOR_MAX_WM,
507 .default_wm = PINEVIEW_CURSOR_DFT_WM,
508 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
509 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 510};
511static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 512 .fifo_size = G4X_FIFO_SIZE,
513 .max_wm = G4X_MAX_WM,
514 .default_wm = G4X_MAX_WM,
515 .guard_size = 2,
516 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 517};
518static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 519 .fifo_size = I965_CURSOR_FIFO,
520 .max_wm = I965_CURSOR_MAX_WM,
521 .default_wm = I965_CURSOR_DFT_WM,
522 .guard_size = 2,
523 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 524};
525static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 526 .fifo_size = VALLEYVIEW_FIFO_SIZE,
527 .max_wm = VALLEYVIEW_MAX_WM,
528 .default_wm = VALLEYVIEW_MAX_WM,
529 .guard_size = 2,
530 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 533 .fifo_size = I965_CURSOR_FIFO,
534 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
535 .default_wm = I965_CURSOR_DFT_WM,
536 .guard_size = 2,
537 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 538};
539static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 540 .fifo_size = I965_CURSOR_FIFO,
541 .max_wm = I965_CURSOR_MAX_WM,
542 .default_wm = I965_CURSOR_DFT_WM,
543 .guard_size = 2,
544 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 545};
546static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 547 .fifo_size = I945_FIFO_SIZE,
548 .max_wm = I915_MAX_WM,
549 .default_wm = 1,
550 .guard_size = 2,
551 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 552};
553static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 554 .fifo_size = I915_FIFO_SIZE,
555 .max_wm = I915_MAX_WM,
556 .default_wm = 1,
557 .guard_size = 2,
558 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 559};
9d539105 560static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 561 .fifo_size = I855GM_FIFO_SIZE,
562 .max_wm = I915_MAX_WM,
563 .default_wm = 1,
564 .guard_size = 2,
565 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 566};
9d539105
VS		 567static const struct intel_watermark_params i830_bc_wm_info = {
568 .fifo_size = I855GM_FIFO_SIZE,
569 .max_wm = I915_MAX_WM/2,
570 .default_wm = 1,
571 .guard_size = 2,
572 .cacheline_size = I830_FIFO_LINE_SIZE,
573};
feb56b93 574static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 575 .fifo_size = I830_FIFO_SIZE,
576 .max_wm = I915_MAX_WM,
577 .default_wm = 1,
578 .guard_size = 2,
579 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 580};
581
b445e3b0
ED		 582/**
583 * intel_calculate_wm - calculate watermark level
584 * @clock_in_khz: pixel clock
585 * @wm: chip FIFO params
586 * @pixel_size: display pixel size
587 * @latency_ns: memory latency for the platform
588 *
589 * Calculate the watermark level (the level at which the display plane will
590 * start fetching from memory again). Each chip has a different display
591 * FIFO size and allocation, so the caller needs to figure that out and pass
592 * in the correct intel_watermark_params structure.
593 *
594 * As the pixel clock runs, the FIFO will be drained at a rate that depends
595 * on the pixel size. When it reaches the watermark level, it'll start
596 * fetching FIFO line sized based chunks from memory until the FIFO fills
597 * past the watermark point. If the FIFO drains completely, a FIFO underrun
598 * will occur, and a display engine hang could result.
599 */
600static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
601 const struct intel_watermark_params *wm,
602 int fifo_size,
603 int pixel_size,
604 unsigned long latency_ns)
605{
606 long entries_required, wm_size;
607
608 /*
609 * Note: we need to make sure we don't overflow for various clock &
610 * latency values.
611 * clocks go from a few thousand to several hundred thousand.
612 * latency is usually a few thousand
613 */
614 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
615 1000;
616 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
617
618 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
619
620 wm_size = fifo_size - (entries_required + wm->guard_size);
621
622 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
623
624 /* Don't promote wm_size to unsigned... */
625 if (wm_size > (long)wm->max_wm)
626 wm_size = wm->max_wm;
627 if (wm_size <= 0)
628 wm_size = wm->default_wm;
d6feb196
VS		 629
630 /*
631 * Bspec seems to indicate that the value shouldn't be lower than
632 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
633 * Lets go for 8 which is the burst size since certain platforms
634 * already use a hardcoded 8 (which is what the spec says should be
635 * done).
636 */
637 if (wm_size <= 8)
638 wm_size = 8;
639
b445e3b0
ED		 640 return wm_size;
641}
642
643static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
644{
645 struct drm_crtc *crtc, *enabled = NULL;
646
70e1e0ec 647 for_each_crtc(dev, crtc) {
3490ea5d 648 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 649 if (enabled)
650 return NULL;
651 enabled = crtc;
652 }
653 }
654
655 return enabled;
656}
657
46ba614c 658static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 659{
46ba614c 660 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 661 struct drm_i915_private *dev_priv = dev->dev_private;
662 struct drm_crtc *crtc;
663 const struct cxsr_latency *latency;
664 u32 reg;
665 unsigned long wm;
666
667 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
668 dev_priv->fsb_freq, dev_priv->mem_freq);
669 if (!latency) {
670 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 671 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 672 return;
673 }
674
675 crtc = single_enabled_crtc(dev);
676 if (crtc) {
241bfc38 677 const struct drm_display_mode *adjusted_mode;
59bea882 678 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 679 int clock;
680
6e3c9717 681 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 682 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 683
684 /* Display SR */
685 wm = intel_calculate_wm(clock, &pineview_display_wm,
686 pineview_display_wm.fifo_size,
687 pixel_size, latency->display_sr);
688 reg = I915_READ(DSPFW1);
689 reg &= ~DSPFW_SR_MASK;
f4998963 690 reg |= FW_WM(wm, SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW1, reg);
692 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
693
694 /* cursor SR */
695 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
696 pineview_display_wm.fifo_size,
697 pixel_size, latency->cursor_sr);
698 reg = I915_READ(DSPFW3);
699 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 700 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 701 I915_WRITE(DSPFW3, reg);
702
703 /* Display HPLL off SR */
704 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
705 pineview_display_hplloff_wm.fifo_size,
706 pixel_size, latency->display_hpll_disable);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 709 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 710 I915_WRITE(DSPFW3, reg);
711
712 /* cursor HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 pixel_size, latency->cursor_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 718 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 719 I915_WRITE(DSPFW3, reg);
720 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
721
5209b1f4 722 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 723 } else {
5209b1f4 724 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 725 }
726}
727
728static bool g4x_compute_wm0(struct drm_device *dev,
729 int plane,
730 const struct intel_watermark_params *display,
731 int display_latency_ns,
732 const struct intel_watermark_params *cursor,
733 int cursor_latency_ns,
734 int *plane_wm,
735 int *cursor_wm)
736{
737 struct drm_crtc *crtc;
4fe8590a 738 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 739 int htotal, hdisplay, clock, pixel_size;
740 int line_time_us, line_count;
741 int entries, tlb_miss;
742
743 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 744 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 745 *cursor_wm = cursor->guard_size;
746 *plane_wm = display->guard_size;
747 return false;
748 }
749
6e3c9717 750 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 751 clock = adjusted_mode->crtc_clock;
fec8cba3 752 htotal = adjusted_mode->crtc_htotal;
6e3c9717 753 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 754 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 755
756 /* Use the small buffer method to calculate plane watermark */
757 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
758 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
759 if (tlb_miss > 0)
760 entries += tlb_miss;
761 entries = DIV_ROUND_UP(entries, display->cacheline_size);
762 *plane_wm = entries + display->guard_size;
763 if (*plane_wm > (int)display->max_wm)
764 *plane_wm = display->max_wm;
765
766 /* Use the large buffer method to calculate cursor watermark */
922044c9 767 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 768 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 769 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 770 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
771 if (tlb_miss > 0)
772 entries += tlb_miss;
773 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
774 *cursor_wm = entries + cursor->guard_size;
775 if (*cursor_wm > (int)cursor->max_wm)
776 *cursor_wm = (int)cursor->max_wm;
777
778 return true;
779}
780
781/*
782 * Check the wm result.
783 *
784 * If any calculated watermark values is larger than the maximum value that
785 * can be programmed into the associated watermark register, that watermark
786 * must be disabled.
787 */
788static bool g4x_check_srwm(struct drm_device *dev,
789 int display_wm, int cursor_wm,
790 const struct intel_watermark_params *display,
791 const struct intel_watermark_params *cursor)
792{
793 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
794 display_wm, cursor_wm);
795
796 if (display_wm > display->max_wm) {
797 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
798 display_wm, display->max_wm);
799 return false;
800 }
801
802 if (cursor_wm > cursor->max_wm) {
803 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
804 cursor_wm, cursor->max_wm);
805 return false;
806 }
807
808 if (!(display_wm || cursor_wm)) {
809 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
810 return false;
811 }
812
813 return true;
814}
815
816static bool g4x_compute_srwm(struct drm_device *dev,
817 int plane,
818 int latency_ns,
819 const struct intel_watermark_params *display,
820 const struct intel_watermark_params *cursor,
821 int *display_wm, int *cursor_wm)
822{
823 struct drm_crtc *crtc;
4fe8590a 824 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 825 int hdisplay, htotal, pixel_size, clock;
826 unsigned long line_time_us;
827 int line_count, line_size;
828 int small, large;
829 int entries;
830
831 if (!latency_ns) {
832 *display_wm = *cursor_wm = 0;
833 return false;
834 }
835
836 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 837 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 838 clock = adjusted_mode->crtc_clock;
fec8cba3 839 htotal = adjusted_mode->crtc_htotal;
6e3c9717 840 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 841 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 842
922044c9 843 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 844 line_count = (latency_ns / line_time_us + 1000) / 1000;
845 line_size = hdisplay * pixel_size;
846
847 /* Use the minimum of the small and large buffer method for primary */
848 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
849 large = line_count * line_size;
850
851 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
852 *display_wm = entries + display->guard_size;
853
854 /* calculate the self-refresh watermark for display cursor */
3dd512fb 855 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 856 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
857 *cursor_wm = entries + cursor->guard_size;
858
859 return g4x_check_srwm(dev,
860 *display_wm, *cursor_wm,
861 display, cursor);
862}
863
15665979
VS		 864#define FW_WM_VLV(value, plane) \
865 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
866
0018fda1
VS		 867static void vlv_write_wm_values(struct intel_crtc *crtc,
868 const struct vlv_wm_values *wm)
869{
870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
871 enum pipe pipe = crtc->pipe;
872
873 I915_WRITE(VLV_DDL(pipe),
874 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
875 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
876 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
877 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
878
ae80152d 879 I915_WRITE(DSPFW1,
15665979
VS		 880 FW_WM(wm->sr.plane, SR) |
881 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
882 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
883 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 884 I915_WRITE(DSPFW2,
15665979
VS		 885 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
886 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
887 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 888 I915_WRITE(DSPFW3,
15665979 889 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 890
891 if (IS_CHERRYVIEW(dev_priv)) {
892 I915_WRITE(DSPFW7_CHV,
15665979
VS		 893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
894 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 895 I915_WRITE(DSPFW8_CHV,
15665979
VS		 896 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
897 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 898 I915_WRITE(DSPFW9_CHV,
15665979
VS		 899 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
900 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 901 I915_WRITE(DSPHOWM,
15665979
VS		 902 FW_WM(wm->sr.plane >> 9, SR_HI) |
903 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
904 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
905 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
906 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
907 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
908 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
909 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
910 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
911 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 912 } else {
913 I915_WRITE(DSPFW7,
15665979
VS		 914 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
915 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 916 I915_WRITE(DSPHOWM,
15665979
VS		 917 FW_WM(wm->sr.plane >> 9, SR_HI) |
918 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
919 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
920 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
921 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
922 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
923 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 924 }
925
926 POSTING_READ(DSPFW1);
927
0018fda1
VS		 928 dev_priv->wm.vlv = *wm;
929}
930
15665979
VS		 931#undef FW_WM_VLV
932
341c526f 933static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
883a3d2f 934 struct drm_plane *plane)
b445e3b0 935{
5e56ba45 936 struct drm_device *dev = crtc->dev;
883a3d2f
VS		 937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
938 int entries, prec_mult, drain_latency, pixel_size;
939 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
341c526f 940 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
b445e3b0 941
883a3d2f
VS		 942 /*
943 * FIXME the plane might have an fb
944 * but be invisible (eg. due to clipping)
945 */
946 if (!intel_crtc->active || !plane->state->fb)
947 return 0;
948
0948c265 949 if (WARN(clock == 0, "Pixel clock is zero!\n"))
341c526f 950 return 0;
b445e3b0 951
883a3d2f
VS		 952 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
953
0948c265 954 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
341c526f 955 return 0;
b445e3b0 956
a398e9c7 957 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
abfc00b5 958
341c526f
VS		 959 prec_mult = high_precision;
960 drain_latency = 64 * prec_mult * 4 / entries;
b445e3b0 961
341c526f
VS		 962 if (drain_latency > DRAIN_LATENCY_MASK) {
963 prec_mult /= 2;
964 drain_latency = 64 * prec_mult * 4 / entries;
abfc00b5
VS		 965 }
966
341c526f
VS		 967 if (drain_latency > DRAIN_LATENCY_MASK)
968 drain_latency = DRAIN_LATENCY_MASK;
b445e3b0 969
341c526f
VS		 970 return drain_latency | (prec_mult == high_precision ?
971 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
b445e3b0
ED		 972}
973
ae80152d
VS		 974static int vlv_compute_wm(struct intel_crtc *crtc,
975 struct intel_plane *plane,
976 int fifo_size)
b445e3b0 977{
ae80152d 978 int clock, entries, pixel_size;
b445e3b0 979
ae80152d
VS		 980 /*
981 * FIXME the plane might have an fb
982 * but be invisible (eg. due to clipping)
983 */
984 if (!crtc->active || !plane->base.state->fb)
985 return 0;
0948c265 986
ae80152d
VS		 987 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
988 clock = crtc->config->base.adjusted_mode.crtc_clock;
b445e3b0 989
ae80152d 990 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
b445e3b0 991
ae80152d
VS		 992 /*
993 * Set up the watermark such that we don't start issuing memory
994 * requests until we are within PND's max deadline value (256us).
995 * Idea being to be idle as long as possible while still taking
996 * advatange of PND's deadline scheduling. The limit of 8
997 * cachelines (used when the FIFO will anyway drain in less time
998 * than 256us) should match what we would be done if trickle
999 * feed were enabled.
1000 */
1001 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
1002}
1003
1004static bool vlv_compute_sr_wm(struct drm_device *dev,
1005 struct vlv_wm_values *wm)
b445e3b0 1006{
ae80152d
VS		 1007 struct drm_i915_private *dev_priv = to_i915(dev);
1008 struct drm_crtc *crtc;
1009 enum pipe pipe = INVALID_PIPE;
1010 int num_planes = 0;
1011 int fifo_size = 0;
1012 struct intel_plane *plane;
b445e3b0 1013
ae80152d 1014 wm->sr.cursor = wm->sr.plane = 0;
b445e3b0 1015
ae80152d
VS		 1016 crtc = single_enabled_crtc(dev);
1017 /* maxfifo not supported on pipe C */
1018 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1019 pipe = to_intel_crtc(crtc)->pipe;
1020 num_planes = !!wm->pipe[pipe].primary +
1021 !!wm->pipe[pipe].sprite[0] +
1022 !!wm->pipe[pipe].sprite[1];
1023 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1024 }
b445e3b0 1025
ae80152d
VS		 1026 if (fifo_size == 0 || num_planes > 1)
1027 return false;
b445e3b0 1028
ae80152d
VS		 1029 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1030 to_intel_plane(crtc->cursor), 0x3f);
b445e3b0 1031
ae80152d
VS		 1032 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1033 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1034 continue;
b445e3b0 1035
ae80152d
VS		 1036 if (plane->pipe != pipe)
1037 continue;
9858425c 1038
ae80152d
VS		 1039 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1040 plane, fifo_size);
1041 if (wm->sr.plane != 0)
1042 break;
1043 }
1044
1045 return true;
b445e3b0
ED		 1046}
1047
ae80152d 1048static void valleyview_update_wm(struct drm_crtc *crtc)
3c2777fd
VS		 1049{
1050 struct drm_device *dev = crtc->dev;
3c2777fd 1051 struct drm_i915_private *dev_priv = dev->dev_private;
ae80152d
VS		 1052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1053 enum pipe pipe = intel_crtc->pipe;
3c2777fd 1054 bool cxsr_enabled;
ae80152d 1055 struct vlv_wm_values wm = dev_priv->wm.vlv;
3c2777fd 1056
ae80152d
VS		 1057 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1058 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1059 to_intel_plane(crtc->primary),
1060 vlv_get_fifo_size(dev, pipe, 0));
3c2777fd 1061
ae80152d
VS		 1062 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1063 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1064 to_intel_plane(crtc->cursor),
1065 0x3f);
3c2777fd 1066
ae80152d 1067 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
3c2777fd 1068
ae80152d
VS		 1069 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1070 return;
3c2777fd 1071
ae80152d
VS		 1072 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1073 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1074 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1075 wm.sr.plane, wm.sr.cursor);
3c2777fd 1076
fc1ac8de
VS		 1077 /*
1078 * FIXME DDR DVFS introduces massive memory latencies which
1079 * are not known to system agent so any deadline specified
1080 * by the display may not be respected. To support DDR DVFS
1081 * the watermark code needs to be rewritten to essentially
1082 * bypass deadline mechanism and rely solely on the
1083 * watermarks. For now disable DDR DVFS.
1084 */
1085 if (IS_CHERRYVIEW(dev_priv))
1086 chv_set_memory_dvfs(dev_priv, false);
1087
ae80152d
VS		 1088 if (!cxsr_enabled)
1089 intel_set_memory_cxsr(dev_priv, false);
3c2777fd 1090
ae80152d 1091 vlv_write_wm_values(intel_crtc, &wm);
3c2777fd
VS		 1092
1093 if (cxsr_enabled)
1094 intel_set_memory_cxsr(dev_priv, true);
1095}
1096
01e184cc
GB		 1097static void valleyview_update_sprite_wm(struct drm_plane *plane,
1098 struct drm_crtc *crtc,
1099 uint32_t sprite_width,
1100 uint32_t sprite_height,
1101 int pixel_size,
1102 bool enabled, bool scaled)
1103{
1104 struct drm_device *dev = crtc->dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
0018fda1
VS		 1106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1107 enum pipe pipe = intel_crtc->pipe;
01e184cc 1108 int sprite = to_intel_plane(plane)->plane;
ae80152d 1109 bool cxsr_enabled;
0018fda1 1110 struct vlv_wm_values wm = dev_priv->wm.vlv;
01e184cc 1111
ae80152d 1112 if (enabled) {
0018fda1 1113 wm.ddl[pipe].sprite[sprite] =
883a3d2f 1114 vlv_compute_drain_latency(crtc, plane);
ae80152d
VS		 1115
1116 wm.pipe[pipe].sprite[sprite] =
1117 vlv_compute_wm(intel_crtc,
1118 to_intel_plane(plane),
1119 vlv_get_fifo_size(dev, pipe, sprite+1));
1120 } else {
0018fda1 1121 wm.ddl[pipe].sprite[sprite] = 0;
ae80152d
VS		 1122 wm.pipe[pipe].sprite[sprite] = 0;
1123 }
1124
1125 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1126
1127 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1128 return;
1129
1130 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1131 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1132 sprite_name(pipe, sprite),
1133 wm.pipe[pipe].sprite[sprite],
1134 wm.sr.plane, wm.sr.cursor);
1135
1136 if (!cxsr_enabled)
1137 intel_set_memory_cxsr(dev_priv, false);
01e184cc 1138
0018fda1 1139 vlv_write_wm_values(intel_crtc, &wm);
ae80152d
VS		 1140
1141 if (cxsr_enabled)
1142 intel_set_memory_cxsr(dev_priv, true);
01e184cc
GB		 1143}
1144
ae80152d
VS		 1145#define single_plane_enabled(mask) is_power_of_2(mask)
1146
46ba614c 1147static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1148{
46ba614c 1149 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1150 static const int sr_latency_ns = 12000;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1153 int plane_sr, cursor_sr;
1154 unsigned int enabled = 0;
9858425c 1155 bool cxsr_enabled;
b445e3b0 1156
51cea1f4 1157 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1158 &g4x_wm_info, pessimal_latency_ns,
1159 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1160 &planea_wm, &cursora_wm))
51cea1f4 1161 enabled |= 1 << PIPE_A;
b445e3b0 1162
51cea1f4 1163 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1164 &g4x_wm_info, pessimal_latency_ns,
1165 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1166 &planeb_wm, &cursorb_wm))
51cea1f4 1167 enabled |= 1 << PIPE_B;
b445e3b0 1168
b445e3b0
ED		 1169 if (single_plane_enabled(enabled) &&
1170 g4x_compute_srwm(dev, ffs(enabled) - 1,
1171 sr_latency_ns,
1172 &g4x_wm_info,
1173 &g4x_cursor_wm_info,
52bd02d8 1174 &plane_sr, &cursor_sr)) {
9858425c 1175 cxsr_enabled = true;
52bd02d8 1176 } else {
9858425c 1177 cxsr_enabled = false;
5209b1f4 1178 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1179 plane_sr = cursor_sr = 0;
1180 }
b445e3b0 1181
a5043453
VS		 1182 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1183 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1184 planea_wm, cursora_wm,
1185 planeb_wm, cursorb_wm,
1186 plane_sr, cursor_sr);
1187
1188 I915_WRITE(DSPFW1,
f4998963
VS		 1189 FW_WM(plane_sr, SR) |
1190 FW_WM(cursorb_wm, CURSORB) |
1191 FW_WM(planeb_wm, PLANEB) |
1192 FW_WM(planea_wm, PLANEA));
b445e3b0 1193 I915_WRITE(DSPFW2,
8c919b28 1194 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1195 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1196 /* HPLL off in SR has some issues on G4x... disable it */
1197 I915_WRITE(DSPFW3,
8c919b28 1198 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1199 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1200
1201 if (cxsr_enabled)
1202 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1203}
1204
46ba614c 1205static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1206{
46ba614c 1207 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 struct drm_crtc *crtc;
1210 int srwm = 1;
1211 int cursor_sr = 16;
9858425c 1212 bool cxsr_enabled;
b445e3b0
ED		 1213
1214 /* Calc sr entries for one plane configs */
1215 crtc = single_enabled_crtc(dev);
1216 if (crtc) {
1217 /* self-refresh has much higher latency */
1218 static const int sr_latency_ns = 12000;
4fe8590a 1219 const struct drm_display_mode *adjusted_mode =
6e3c9717 1220 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1221 int clock = adjusted_mode->crtc_clock;
fec8cba3 1222 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1223 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1224 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1225 unsigned long line_time_us;
1226 int entries;
1227
922044c9 1228 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1229
1230 /* Use ns/us then divide to preserve precision */
1231 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1232 pixel_size * hdisplay;
1233 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1234 srwm = I965_FIFO_SIZE - entries;
1235 if (srwm < 0)
1236 srwm = 1;
1237 srwm &= 0x1ff;
1238 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1239 entries, srwm);
1240
1241 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1242 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1243 entries = DIV_ROUND_UP(entries,
1244 i965_cursor_wm_info.cacheline_size);
1245 cursor_sr = i965_cursor_wm_info.fifo_size -
1246 (entries + i965_cursor_wm_info.guard_size);
1247
1248 if (cursor_sr > i965_cursor_wm_info.max_wm)
1249 cursor_sr = i965_cursor_wm_info.max_wm;
1250
1251 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1252 "cursor %d\n", srwm, cursor_sr);
1253
9858425c 1254 cxsr_enabled = true;
b445e3b0 1255 } else {
9858425c 1256 cxsr_enabled = false;
b445e3b0 1257 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1258 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1259 }
1260
1261 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1262 srwm);
1263
1264 /* 965 has limitations... */
f4998963
VS		 1265 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1266 FW_WM(8, CURSORB) |
1267 FW_WM(8, PLANEB) |
1268 FW_WM(8, PLANEA));
1269 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1270 FW_WM(8, PLANEC_OLD));
b445e3b0 1271 /* update cursor SR watermark */
f4998963 1272 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1273
1274 if (cxsr_enabled)
1275 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1276}
1277
f4998963
VS		 1278#undef FW_WM
1279
46ba614c 1280static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1281{
46ba614c 1282 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 const struct intel_watermark_params *wm_info;
1285 uint32_t fwater_lo;
1286 uint32_t fwater_hi;
1287 int cwm, srwm = 1;
1288 int fifo_size;
1289 int planea_wm, planeb_wm;
1290 struct drm_crtc *crtc, *enabled = NULL;
1291
1292 if (IS_I945GM(dev))
1293 wm_info = &i945_wm_info;
1294 else if (!IS_GEN2(dev))
1295 wm_info = &i915_wm_info;
1296 else
9d539105 1297 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1298
1299 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1300 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1301 if (intel_crtc_active(crtc)) {
241bfc38 1302 const struct drm_display_mode *adjusted_mode;
59bea882 1303 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1304 if (IS_GEN2(dev))
1305 cpp = 4;
1306
6e3c9717 1307 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1308 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1309 wm_info, fifo_size, cpp,
5aef6003 1310 pessimal_latency_ns);
b445e3b0 1311 enabled = crtc;
9d539105 1312 } else {
b445e3b0 1313 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1314 if (planea_wm > (long)wm_info->max_wm)
1315 planea_wm = wm_info->max_wm;
1316 }
1317
1318 if (IS_GEN2(dev))
1319 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1320
1321 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1322 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1323 if (intel_crtc_active(crtc)) {
241bfc38 1324 const struct drm_display_mode *adjusted_mode;
59bea882 1325 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1326 if (IS_GEN2(dev))
1327 cpp = 4;
1328
6e3c9717 1329 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1330 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1331 wm_info, fifo_size, cpp,
5aef6003 1332 pessimal_latency_ns);
b445e3b0
ED		 1333 if (enabled == NULL)
1334 enabled = crtc;
1335 else
1336 enabled = NULL;
9d539105 1337 } else {
b445e3b0 1338 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1339 if (planeb_wm > (long)wm_info->max_wm)
1340 planeb_wm = wm_info->max_wm;
1341 }
b445e3b0
ED		 1342
1343 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1344
2ab1bc9d 1345 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1346 struct drm_i915_gem_object *obj;
2ab1bc9d 1347
59bea882 1348 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1349
1350 /* self-refresh seems busted with untiled */
2ff8fde1 1351 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1352 enabled = NULL;
1353 }
1354
b445e3b0
ED		 1355 /*
1356 * Overlay gets an aggressive default since video jitter is bad.
1357 */
1358 cwm = 2;
1359
1360 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1361 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1362
1363 /* Calc sr entries for one plane configs */
1364 if (HAS_FW_BLC(dev) && enabled) {
1365 /* self-refresh has much higher latency */
1366 static const int sr_latency_ns = 6000;
4fe8590a 1367 const struct drm_display_mode *adjusted_mode =
6e3c9717 1368 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1369 int clock = adjusted_mode->crtc_clock;
fec8cba3 1370 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1371 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1372 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1373 unsigned long line_time_us;
1374 int entries;
1375
922044c9 1376 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1377
1378 /* Use ns/us then divide to preserve precision */
1379 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1380 pixel_size * hdisplay;
1381 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1382 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1383 srwm = wm_info->fifo_size - entries;
1384 if (srwm < 0)
1385 srwm = 1;
1386
1387 if (IS_I945G(dev) || IS_I945GM(dev))
1388 I915_WRITE(FW_BLC_SELF,
1389 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1390 else if (IS_I915GM(dev))
1391 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1392 }
1393
1394 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1395 planea_wm, planeb_wm, cwm, srwm);
1396
1397 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1398 fwater_hi = (cwm & 0x1f);
1399
1400 /* Set request length to 8 cachelines per fetch */
1401 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1402 fwater_hi = fwater_hi | (1 << 8);
1403
1404 I915_WRITE(FW_BLC, fwater_lo);
1405 I915_WRITE(FW_BLC2, fwater_hi);
1406
5209b1f4
ID		 1407 if (enabled)
1408 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1409}
1410
feb56b93 1411static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1412{
46ba614c 1413 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415 struct drm_crtc *crtc;
241bfc38 1416 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1417 uint32_t fwater_lo;
1418 int planea_wm;
1419
1420 crtc = single_enabled_crtc(dev);
1421 if (crtc == NULL)
1422 return;
1423
6e3c9717 1424 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1425 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1426 &i845_wm_info,
b445e3b0 1427 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1428 4, pessimal_latency_ns);
b445e3b0
ED		 1429 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1430 fwater_lo |= (3<<8) | planea_wm;
1431
1432 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1433
1434 I915_WRITE(FW_BLC, fwater_lo);
1435}
1436
3658729a
VS		 1437static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1438 struct drm_crtc *crtc)
801bcfff
PZ		 1439{
1440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 1441 uint32_t pixel_rate;
801bcfff 1442
6e3c9717 1443 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1444
1445 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1446 * adjust the pixel_rate here. */
1447
6e3c9717 1448 if (intel_crtc->config->pch_pfit.enabled) {
801bcfff 1449 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6e3c9717 1450 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
801bcfff 1451
6e3c9717
ACO		 1452 pipe_w = intel_crtc->config->pipe_src_w;
1453 pipe_h = intel_crtc->config->pipe_src_h;
801bcfff
PZ		 1454 pfit_w = (pfit_size >> 16) & 0xFFFF;
1455 pfit_h = pfit_size & 0xFFFF;
1456 if (pipe_w < pfit_w)
1457 pipe_w = pfit_w;
1458 if (pipe_h < pfit_h)
1459 pipe_h = pfit_h;
1460
1461 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1462 pfit_w * pfit_h);
1463 }
1464
1465 return pixel_rate;
1466}
1467
37126462 1468/* latency must be in 0.1us units. */
23297044 1469static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1470 uint32_t latency)
1471{
1472 uint64_t ret;
1473
3312ba65
VS		 1474 if (WARN(latency == 0, "Latency value missing\n"))
1475 return UINT_MAX;
1476
801bcfff
PZ		 1477 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1478 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1479
1480 return ret;
1481}
1482
37126462 1483/* latency must be in 0.1us units. */
23297044 1484static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1485 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1486 uint32_t latency)
1487{
1488 uint32_t ret;
1489
3312ba65
VS		 1490 if (WARN(latency == 0, "Latency value missing\n"))
1491 return UINT_MAX;
1492
801bcfff
PZ		 1493 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1494 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1495 ret = DIV_ROUND_UP(ret, 64) + 2;
1496 return ret;
1497}
1498
23297044 1499static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1500 uint8_t bytes_per_pixel)
1501{
1502 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1503}
1504
2ac96d2a
PB		 1505struct skl_pipe_wm_parameters {
1506 bool active;
1507 uint32_t pipe_htotal;
1508 uint32_t pixel_rate; /* in KHz */
1509 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1510 struct intel_plane_wm_parameters cursor;
1511};
1512
820c1980 1513struct ilk_pipe_wm_parameters {
801bcfff 1514 bool active;
801bcfff
PZ		 1515 uint32_t pipe_htotal;
1516 uint32_t pixel_rate;
c35426d2
VS		 1517 struct intel_plane_wm_parameters pri;
1518 struct intel_plane_wm_parameters spr;
1519 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1520};
1521
820c1980 1522struct ilk_wm_maximums {
cca32e9a
PZ		 1523 uint16_t pri;
1524 uint16_t spr;
1525 uint16_t cur;
1526 uint16_t fbc;
1527};
1528
240264f4
VS		 1529/* used in computing the new watermarks state */
1530struct intel_wm_config {
1531 unsigned int num_pipes_active;
1532 bool sprites_enabled;
1533 bool sprites_scaled;
240264f4
VS		 1534};
1535
37126462
VS		 1536/*
1537 * For both WM_PIPE and WM_LP.
1538 * mem_value must be in 0.1us units.
1539 */
820c1980 1540static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1541 uint32_t mem_value,
1542 bool is_lp)
801bcfff 1543{
cca32e9a
PZ		 1544 uint32_t method1, method2;
1545
c35426d2 1546 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1547 return 0;
1548
23297044 1549 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1550 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1551 mem_value);
1552
1553 if (!is_lp)
1554 return method1;
1555
23297044 1556 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1557 params->pipe_htotal,
c35426d2
VS		 1558 params->pri.horiz_pixels,
1559 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1560 mem_value);
1561
1562 return min(method1, method2);
801bcfff
PZ		 1563}
1564
37126462
VS		 1565/*
1566 * For both WM_PIPE and WM_LP.
1567 * mem_value must be in 0.1us units.
1568 */
820c1980 1569static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1570 uint32_t mem_value)
1571{
1572 uint32_t method1, method2;
1573
c35426d2 1574 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1575 return 0;
1576
23297044 1577 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1578 params->spr.bytes_per_pixel,
801bcfff 1579 mem_value);
23297044 1580 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1581 params->pipe_htotal,
c35426d2
VS		 1582 params->spr.horiz_pixels,
1583 params->spr.bytes_per_pixel,
801bcfff
PZ		 1584 mem_value);
1585 return min(method1, method2);
1586}
1587
37126462
VS		 1588/*
1589 * For both WM_PIPE and WM_LP.
1590 * mem_value must be in 0.1us units.
1591 */
820c1980 1592static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1593 uint32_t mem_value)
1594{
c35426d2 1595 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1596 return 0;
1597
23297044 1598 return ilk_wm_method2(params->pixel_rate,
801bcfff 1599 params->pipe_htotal,
c35426d2
VS		 1600 params->cur.horiz_pixels,
1601 params->cur.bytes_per_pixel,
801bcfff
PZ		 1602 mem_value);
1603}
1604
cca32e9a 1605/* Only for WM_LP. */
820c1980 1606static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1607 uint32_t pri_val)
cca32e9a 1608{
c35426d2 1609 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1610 return 0;
1611
23297044 1612 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1613 params->pri.horiz_pixels,
1614 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1615}
1616
158ae64f
VS		 1617static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1618{
416f4727
VS		 1619 if (INTEL_INFO(dev)->gen >= 8)
1620 return 3072;
1621 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1622 return 768;
1623 else
1624 return 512;
1625}
1626
4e975081
VS		 1627static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1628 int level, bool is_sprite)
1629{
1630 if (INTEL_INFO(dev)->gen >= 8)
1631 /* BDW primary/sprite plane watermarks */
1632 return level == 0 ? 255 : 2047;
1633 else if (INTEL_INFO(dev)->gen >= 7)
1634 /* IVB/HSW primary/sprite plane watermarks */
1635 return level == 0 ? 127 : 1023;
1636 else if (!is_sprite)
1637 /* ILK/SNB primary plane watermarks */
1638 return level == 0 ? 127 : 511;
1639 else
1640 /* ILK/SNB sprite plane watermarks */
1641 return level == 0 ? 63 : 255;
1642}
1643
1644static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1645 int level)
1646{
1647 if (INTEL_INFO(dev)->gen >= 7)
1648 return level == 0 ? 63 : 255;
1649 else
1650 return level == 0 ? 31 : 63;
1651}
1652
1653static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1654{
1655 if (INTEL_INFO(dev)->gen >= 8)
1656 return 31;
1657 else
1658 return 15;
1659}
1660
158ae64f
VS		 1661/* Calculate the maximum primary/sprite plane watermark */
1662static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1663 int level,
240264f4 1664 const struct intel_wm_config *config,
158ae64f
VS		 1665 enum intel_ddb_partitioning ddb_partitioning,
1666 bool is_sprite)
1667{
1668 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1669
1670 /* if sprites aren't enabled, sprites get nothing */
240264f4 1671 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1672 return 0;
1673
1674 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1675 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1676 fifo_size /= INTEL_INFO(dev)->num_pipes;
1677
1678 /*
1679 * For some reason the non self refresh
1680 * FIFO size is only half of the self
1681 * refresh FIFO size on ILK/SNB.
1682 */
1683 if (INTEL_INFO(dev)->gen <= 6)
1684 fifo_size /= 2;
1685 }
1686
240264f4 1687 if (config->sprites_enabled) {
158ae64f
VS		 1688 /* level 0 is always calculated with 1:1 split */
1689 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1690 if (is_sprite)
1691 fifo_size *= 5;
1692 fifo_size /= 6;
1693 } else {
1694 fifo_size /= 2;
1695 }
1696 }
1697
1698 /* clamp to max that the registers can hold */
4e975081 1699 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1700}
1701
1702/* Calculate the maximum cursor plane watermark */
1703static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1704 int level,
1705 const struct intel_wm_config *config)
158ae64f
VS		 1706{
1707 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1708 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1709 return 64;
1710
1711 /* otherwise just report max that registers can hold */
4e975081 1712 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1713}
1714
d34ff9c6 1715static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1716 int level,
1717 const struct intel_wm_config *config,
1718 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1719 struct ilk_wm_maximums *max)
158ae64f 1720{
240264f4
VS		 1721 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1722 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1723 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1724 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1725}
1726
a3cb4048
VS		 1727static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1728 int level,
1729 struct ilk_wm_maximums *max)
1730{
1731 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1732 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1733 max->cur = ilk_cursor_wm_reg_max(dev, level);
1734 max->fbc = ilk_fbc_wm_reg_max(dev);
1735}
1736
d9395655 1737static bool ilk_validate_wm_level(int level,
820c1980 1738 const struct ilk_wm_maximums *max,
d9395655 1739 struct intel_wm_level *result)
a9786a11
VS		 1740{
1741 bool ret;
1742
1743 /* already determined to be invalid? */
1744 if (!result->enable)
1745 return false;
1746
1747 result->enable = result->pri_val <= max->pri &&
1748 result->spr_val <= max->spr &&
1749 result->cur_val <= max->cur;
1750
1751 ret = result->enable;
1752
1753 /*
1754 * HACK until we can pre-compute everything,
1755 * and thus fail gracefully if LP0 watermarks
1756 * are exceeded...
1757 */
1758 if (level == 0 && !result->enable) {
1759 if (result->pri_val > max->pri)
1760 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1761 level, result->pri_val, max->pri);
1762 if (result->spr_val > max->spr)
1763 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1764 level, result->spr_val, max->spr);
1765 if (result->cur_val > max->cur)
1766 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1767 level, result->cur_val, max->cur);
1768
1769 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1770 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1771 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1772 result->enable = true;
1773 }
1774
a9786a11
VS		 1775 return ret;
1776}
1777
d34ff9c6 1778static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1779 int level,
820c1980 1780 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1781 struct intel_wm_level *result)
6f5ddd17
VS		 1782{
1783 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1784 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1785 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1786
1787 /* WM1+ latency values stored in 0.5us units */
1788 if (level > 0) {
1789 pri_latency *= 5;
1790 spr_latency *= 5;
1791 cur_latency *= 5;
1792 }
1793
1794 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1795 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1796 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1797 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1798 result->enable = true;
1799}
1800
801bcfff
PZ		 1801static uint32_t
1802hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 1803{
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1806 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1807 u32 linetime, ips_linetime;
1f8eeabf 1808
3ef00284 1809 if (!intel_crtc->active)
801bcfff 1810 return 0;
1011d8c4 1811
1f8eeabf
ED		 1812 /* The WM are computed with base on how long it takes to fill a single
1813 * row at the given clock rate, multiplied by 8.
1814 * */
fec8cba3
JB		 1815 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1816 mode->crtc_clock);
1817 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1652d19e 1818 dev_priv->display.get_display_clock_speed(dev_priv->dev));
1f8eeabf 1819
801bcfff
PZ		 1820 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1821 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 1822}
1823
2af30a5c 1824static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 1825{
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827
2af30a5c
PB		 1828 if (IS_GEN9(dev)) {
1829 uint32_t val;
4f947386 1830 int ret, i;
367294be 1831 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 1832
1833 /* read the first set of memory latencies[0:3] */
1834 val = 0; /* data0 to be programmed to 0 for first set */
1835 mutex_lock(&dev_priv->rps.hw_lock);
1836 ret = sandybridge_pcode_read(dev_priv,
1837 GEN9_PCODE_READ_MEM_LATENCY,
1838 &val);
1839 mutex_unlock(&dev_priv->rps.hw_lock);
1840
1841 if (ret) {
1842 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1843 return;
1844 }
1845
1846 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1847 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1848 GEN9_MEM_LATENCY_LEVEL_MASK;
1849 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1850 GEN9_MEM_LATENCY_LEVEL_MASK;
1851 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1852 GEN9_MEM_LATENCY_LEVEL_MASK;
1853
1854 /* read the second set of memory latencies[4:7] */
1855 val = 1; /* data0 to be programmed to 1 for second set */
1856 mutex_lock(&dev_priv->rps.hw_lock);
1857 ret = sandybridge_pcode_read(dev_priv,
1858 GEN9_PCODE_READ_MEM_LATENCY,
1859 &val);
1860 mutex_unlock(&dev_priv->rps.hw_lock);
1861 if (ret) {
1862 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1863 return;
1864 }
1865
1866 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1867 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1868 GEN9_MEM_LATENCY_LEVEL_MASK;
1869 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1870 GEN9_MEM_LATENCY_LEVEL_MASK;
1871 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1872 GEN9_MEM_LATENCY_LEVEL_MASK;
1873
367294be 1874 /*
6f97235b
DL		 1875 * WaWmMemoryReadLatency:skl
1876 *
367294be
VK		 1877 * punit doesn't take into account the read latency so we need
1878 * to add 2us to the various latency levels we retrieve from
1879 * the punit.
1880 * - W0 is a bit special in that it's the only level that
1881 * can't be disabled if we want to have display working, so
1882 * we always add 2us there.
1883 * - For levels >=1, punit returns 0us latency when they are
1884 * disabled, so we respect that and don't add 2us then
4f947386
VK		 1885 *
1886 * Additionally, if a level n (n > 1) has a 0us latency, all
1887 * levels m (m >= n) need to be disabled. We make sure to
1888 * sanitize the values out of the punit to satisfy this
1889 * requirement.
367294be
VK		 1890 */
1891 wm[0] += 2;
1892 for (level = 1; level <= max_level; level++)
1893 if (wm[level] != 0)
1894 wm[level] += 2;
4f947386
VK		 1895 else {
1896 for (i = level + 1; i <= max_level; i++)
1897 wm[i] = 0;
367294be 1898
4f947386
VK		 1899 break;
1900 }
2af30a5c 1901 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 1902 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1903
1904 wm[0] = (sskpd >> 56) & 0xFF;
1905 if (wm[0] == 0)
1906 wm[0] = sskpd & 0xF;
e5d5019e
VS		 1907 wm[1] = (sskpd >> 4) & 0xFF;
1908 wm[2] = (sskpd >> 12) & 0xFF;
1909 wm[3] = (sskpd >> 20) & 0x1FF;
1910 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 1911 } else if (INTEL_INFO(dev)->gen >= 6) {
1912 uint32_t sskpd = I915_READ(MCH_SSKPD);
1913
1914 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1915 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1916 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1917 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 1918 } else if (INTEL_INFO(dev)->gen >= 5) {
1919 uint32_t mltr = I915_READ(MLTR_ILK);
1920
1921 /* ILK primary LP0 latency is 700 ns */
1922 wm[0] = 7;
1923 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1924 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 1925 }
1926}
1927
53615a5e
VS		 1928static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1929{
1930 /* ILK sprite LP0 latency is 1300 ns */
1931 if (INTEL_INFO(dev)->gen == 5)
1932 wm[0] = 13;
1933}
1934
1935static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1936{
1937 /* ILK cursor LP0 latency is 1300 ns */
1938 if (INTEL_INFO(dev)->gen == 5)
1939 wm[0] = 13;
1940
1941 /* WaDoubleCursorLP3Latency:ivb */
1942 if (IS_IVYBRIDGE(dev))
1943 wm[3] *= 2;
1944}
1945
546c81fd 1946int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1947{
26ec971e 1948 /* how many WM levels are we expecting */
b6e742f6 1949 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 1950 return 7;
1951 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1952 return 4;
26ec971e 1953 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1954 return 3;
26ec971e 1955 else
ad0d6dc4
VS		 1956 return 2;
1957}
7526ed79 1958
ad0d6dc4
VS		 1959static void intel_print_wm_latency(struct drm_device *dev,
1960 const char *name,
2af30a5c 1961 const uint16_t wm[8])
ad0d6dc4
VS		 1962{
1963 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 1964
1965 for (level = 0; level <= max_level; level++) {
1966 unsigned int latency = wm[level];
1967
1968 if (latency == 0) {
1969 DRM_ERROR("%s WM%d latency not provided\n",
1970 name, level);
1971 continue;
1972 }
1973
2af30a5c
PB		 1974 /*
1975 * - latencies are in us on gen9.
1976 * - before then, WM1+ latency values are in 0.5us units
1977 */
1978 if (IS_GEN9(dev))
1979 latency *= 10;
1980 else if (level > 0)
26ec971e
VS		 1981 latency *= 5;
1982
1983 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1984 name, level, wm[level],
1985 latency / 10, latency % 10);
1986 }
1987}
1988
e95a2f75
VS		 1989static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1990 uint16_t wm[5], uint16_t min)
1991{
1992 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1993
1994 if (wm[0] >= min)
1995 return false;
1996
1997 wm[0] = max(wm[0], min);
1998 for (level = 1; level <= max_level; level++)
1999 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2000
2001 return true;
2002}
2003
2004static void snb_wm_latency_quirk(struct drm_device *dev)
2005{
2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 bool changed;
2008
2009 /*
2010 * The BIOS provided WM memory latency values are often
2011 * inadequate for high resolution displays. Adjust them.
2012 */
2013 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2014 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2015 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2016
2017 if (!changed)
2018 return;
2019
2020 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2021 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2022 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2023 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2024}
2025
fa50ad61 2026static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2027{
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029
2030 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2031
2032 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2033 sizeof(dev_priv->wm.pri_latency));
2034 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2035 sizeof(dev_priv->wm.pri_latency));
2036
2037 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2038 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2039
2040 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2041 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2042 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2043
2044 if (IS_GEN6(dev))
2045 snb_wm_latency_quirk(dev);
53615a5e
VS		 2046}
2047
2af30a5c
PB		 2048static void skl_setup_wm_latency(struct drm_device *dev)
2049{
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051
2052 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2053 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2054}
2055
820c1980 2056static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2057 struct ilk_pipe_wm_parameters *p)
1011d8c4 2058{
7c4a395f
VS		 2059 struct drm_device *dev = crtc->dev;
2060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2062 struct drm_plane *plane;
1011d8c4 2063
3ef00284 2064 if (!intel_crtc->active)
2a44b76b 2065 return;
801bcfff 2066
2a44b76b 2067 p->active = true;
6e3c9717 2068 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2a44b76b 2069 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c9f038a1
MR		 2070
2071 if (crtc->primary->state->fb) {
2072 p->pri.enabled = true;
2073 p->pri.bytes_per_pixel =
2074 crtc->primary->state->fb->bits_per_pixel / 8;
2075 } else {
2076 p->pri.enabled = false;
2077 p->pri.bytes_per_pixel = 0;
2078 }
2079
2080 if (crtc->cursor->state->fb) {
2081 p->cur.enabled = true;
2082 p->cur.bytes_per_pixel = 4;
2083 } else {
2084 p->cur.enabled = false;
2085 p->cur.bytes_per_pixel = 0;
2086 }
6e3c9717 2087 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2088 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2089
af2b653b 2090 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2091 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2092
2a44b76b 2093 if (intel_plane->pipe == pipe) {
7c4a395f 2094 p->spr = intel_plane->wm;
2a44b76b
VS		 2095 break;
2096 }
2097 }
2098}
2099
2100static void ilk_compute_wm_config(struct drm_device *dev,
2101 struct intel_wm_config *config)
2102{
2103 struct intel_crtc *intel_crtc;
2104
2105 /* Compute the currently _active_ config */
d3fcc808 2106 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2107 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2108
2a44b76b
VS		 2109 if (!wm->pipe_enabled)
2110 continue;
cca32e9a 2111
2a44b76b
VS		 2112 config->sprites_enabled |= wm->sprites_enabled;
2113 config->sprites_scaled |= wm->sprites_scaled;
2114 config->num_pipes_active++;
cca32e9a 2115 }
801bcfff
PZ		 2116}
2117
0b2ae6d7
VS		 2118/* Compute new watermarks for the pipe */
2119static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2120 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2121 struct intel_pipe_wm *pipe_wm)
2122{
2123 struct drm_device *dev = crtc->dev;
d34ff9c6 2124 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2125 int level, max_level = ilk_wm_max_level(dev);
2126 /* LP0 watermark maximums depend on this pipe alone */
2127 struct intel_wm_config config = {
2128 .num_pipes_active = 1,
2129 .sprites_enabled = params->spr.enabled,
2130 .sprites_scaled = params->spr.scaled,
2131 };
820c1980 2132 struct ilk_wm_maximums max;
0b2ae6d7 2133
2a44b76b
VS		 2134 pipe_wm->pipe_enabled = params->active;
2135 pipe_wm->sprites_enabled = params->spr.enabled;
2136 pipe_wm->sprites_scaled = params->spr.scaled;
2137
7b39a0b7
VS		 2138 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2139 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2140 max_level = 1;
2141
2142 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2143 if (params->spr.scaled)
2144 max_level = 0;
2145
a3cb4048 2146 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2147
a42a5719 2148 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2149 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2150
a3cb4048
VS		 2151 /* LP0 watermarks always use 1/2 DDB partitioning */
2152 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2153
0b2ae6d7 2154 /* At least LP0 must be valid */
a3cb4048
VS		 2155 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2156 return false;
2157
2158 ilk_compute_wm_reg_maximums(dev, 1, &max);
2159
2160 for (level = 1; level <= max_level; level++) {
2161 struct intel_wm_level wm = {};
2162
2163 ilk_compute_wm_level(dev_priv, level, params, &wm);
2164
2165 /*
2166 * Disable any watermark level that exceeds the
2167 * register maximums since such watermarks are
2168 * always invalid.
2169 */
2170 if (!ilk_validate_wm_level(level, &max, &wm))
2171 break;
2172
2173 pipe_wm->wm[level] = wm;
2174 }
2175
2176 return true;
0b2ae6d7
VS		 2177}
2178
2179/*
2180 * Merge the watermarks from all active pipes for a specific level.
2181 */
2182static void ilk_merge_wm_level(struct drm_device *dev,
2183 int level,
2184 struct intel_wm_level *ret_wm)
2185{
2186 const struct intel_crtc *intel_crtc;
2187
d52fea5b
VS		 2188 ret_wm->enable = true;
2189
d3fcc808 2190 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2191 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2192 const struct intel_wm_level *wm = &active->wm[level];
2193
2194 if (!active->pipe_enabled)
2195 continue;
0b2ae6d7 2196
d52fea5b
VS		 2197 /*
2198 * The watermark values may have been used in the past,
2199 * so we must maintain them in the registers for some
2200 * time even if the level is now disabled.
2201 */
0b2ae6d7 2202 if (!wm->enable)
d52fea5b 2203 ret_wm->enable = false;
0b2ae6d7
VS		 2204
2205 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2206 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2207 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2208 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2209 }
0b2ae6d7
VS		 2210}
2211
2212/*
2213 * Merge all low power watermarks for all active pipes.
2214 */
2215static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2216 const struct intel_wm_config *config,
820c1980 2217 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2218 struct intel_pipe_wm *merged)
2219{
2220 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2221 int last_enabled_level = max_level;
0b2ae6d7 2222
0ba22e26
VS		 2223 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2224 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2225 config->num_pipes_active > 1)
2226 return;
2227
6c8b6c28
VS		 2228 /* ILK: FBC WM must be disabled always */
2229 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2230
2231 /* merge each WM1+ level */
2232 for (level = 1; level <= max_level; level++) {
2233 struct intel_wm_level *wm = &merged->wm[level];
2234
2235 ilk_merge_wm_level(dev, level, wm);
2236
d52fea5b
VS		 2237 if (level > last_enabled_level)
2238 wm->enable = false;
2239 else if (!ilk_validate_wm_level(level, max, wm))
2240 /* make sure all following levels get disabled */
2241 last_enabled_level = level - 1;
0b2ae6d7
VS		 2242
2243 /*
2244 * The spec says it is preferred to disable
2245 * FBC WMs instead of disabling a WM level.
2246 */
2247 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2248 if (wm->enable)
2249 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2250 wm->fbc_val = 0;
2251 }
2252 }
6c8b6c28
VS		 2253
2254 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2255 /*
2256 * FIXME this is racy. FBC might get enabled later.
2257 * What we should check here is whether FBC can be
2258 * enabled sometime later.
2259 */
2260 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2261 for (level = 2; level <= max_level; level++) {
2262 struct intel_wm_level *wm = &merged->wm[level];
2263
2264 wm->enable = false;
2265 }
2266 }
0b2ae6d7
VS		 2267}
2268
b380ca3c
VS		 2269static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2270{
2271 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2272 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2273}
2274
a68d68ee
VS		 2275/* The value we need to program into the WM_LPx latency field */
2276static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2277{
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279
a42a5719 2280 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2281 return 2 * level;
2282 else
2283 return dev_priv->wm.pri_latency[level];
2284}
2285
820c1980 2286static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2287 const struct intel_pipe_wm *merged,
609cedef 2288 enum intel_ddb_partitioning partitioning,
820c1980 2289 struct ilk_wm_values *results)
801bcfff 2290{
0b2ae6d7
VS		 2291 struct intel_crtc *intel_crtc;
2292 int level, wm_lp;
cca32e9a 2293
0362c781 2294 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2295 results->partitioning = partitioning;
cca32e9a 2296
0b2ae6d7 2297 /* LP1+ register values */
cca32e9a 2298 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2299 const struct intel_wm_level *r;
801bcfff 2300
b380ca3c 2301 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2302
0362c781 2303 r = &merged->wm[level];
cca32e9a 2304
d52fea5b
VS		 2305 /*
2306 * Maintain the watermark values even if the level is
2307 * disabled. Doing otherwise could cause underruns.
2308 */
2309 results->wm_lp[wm_lp - 1] =
a68d68ee 2310 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2311 (r->pri_val << WM1_LP_SR_SHIFT) |
2312 r->cur_val;
2313
d52fea5b
VS		 2314 if (r->enable)
2315 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2316
416f4727
VS		 2317 if (INTEL_INFO(dev)->gen >= 8)
2318 results->wm_lp[wm_lp - 1] |=
2319 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2320 else
2321 results->wm_lp[wm_lp - 1] |=
2322 r->fbc_val << WM1_LP_FBC_SHIFT;
2323
d52fea5b
VS		 2324 /*
2325 * Always set WM1S_LP_EN when spr_val != 0, even if the
2326 * level is disabled. Doing otherwise could cause underruns.
2327 */
6cef2b8a
VS		 2328 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2329 WARN_ON(wm_lp != 1);
2330 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2331 } else
2332 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2333 }
801bcfff 2334
0b2ae6d7 2335 /* LP0 register values */
d3fcc808 2336 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2337 enum pipe pipe = intel_crtc->pipe;
2338 const struct intel_wm_level *r =
2339 &intel_crtc->wm.active.wm[0];
2340
2341 if (WARN_ON(!r->enable))
2342 continue;
2343
2344 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2345
0b2ae6d7
VS		 2346 results->wm_pipe[pipe] =
2347 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2348 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2349 r->cur_val;
801bcfff
PZ		 2350 }
2351}
2352
861f3389
PZ		 2353/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2354 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2355static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2356 struct intel_pipe_wm *r1,
2357 struct intel_pipe_wm *r2)
861f3389 2358{
198a1e9b
VS		 2359 int level, max_level = ilk_wm_max_level(dev);
2360 int level1 = 0, level2 = 0;
861f3389 2361
198a1e9b
VS		 2362 for (level = 1; level <= max_level; level++) {
2363 if (r1->wm[level].enable)
2364 level1 = level;
2365 if (r2->wm[level].enable)
2366 level2 = level;
861f3389
PZ		 2367 }
2368
198a1e9b
VS		 2369 if (level1 == level2) {
2370 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2371 return r2;
2372 else
2373 return r1;
198a1e9b 2374 } else if (level1 > level2) {
861f3389
PZ		 2375 return r1;
2376 } else {
2377 return r2;
2378 }
2379}
2380
49a687c4
VS		 2381/* dirty bits used to track which watermarks need changes */
2382#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2383#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2384#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2385#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2386#define WM_DIRTY_FBC (1 << 24)
2387#define WM_DIRTY_DDB (1 << 25)
2388
055e393f 2389static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2390 const struct ilk_wm_values *old,
2391 const struct ilk_wm_values *new)
49a687c4
VS		 2392{
2393 unsigned int dirty = 0;
2394 enum pipe pipe;
2395 int wm_lp;
2396
055e393f 2397 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2398 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2399 dirty |= WM_DIRTY_LINETIME(pipe);
2400 /* Must disable LP1+ watermarks too */
2401 dirty |= WM_DIRTY_LP_ALL;
2402 }
2403
2404 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2405 dirty |= WM_DIRTY_PIPE(pipe);
2406 /* Must disable LP1+ watermarks too */
2407 dirty |= WM_DIRTY_LP_ALL;
2408 }
2409 }
2410
2411 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2412 dirty |= WM_DIRTY_FBC;
2413 /* Must disable LP1+ watermarks too */
2414 dirty |= WM_DIRTY_LP_ALL;
2415 }
2416
2417 if (old->partitioning != new->partitioning) {
2418 dirty |= WM_DIRTY_DDB;
2419 /* Must disable LP1+ watermarks too */
2420 dirty |= WM_DIRTY_LP_ALL;
2421 }
2422
2423 /* LP1+ watermarks already deemed dirty, no need to continue */
2424 if (dirty & WM_DIRTY_LP_ALL)
2425 return dirty;
2426
2427 /* Find the lowest numbered LP1+ watermark in need of an update... */
2428 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2429 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2430 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2431 break;
2432 }
2433
2434 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2435 for (; wm_lp <= 3; wm_lp++)
2436 dirty |= WM_DIRTY_LP(wm_lp);
2437
2438 return dirty;
2439}
2440
8553c18e
VS		 2441static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2442 unsigned int dirty)
801bcfff 2443{
820c1980 2444 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2445 bool changed = false;
801bcfff 2446
facd619b
VS		 2447 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2448 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2449 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2450 changed = true;
facd619b
VS		 2451 }
2452 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2453 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2454 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2455 changed = true;
facd619b
VS		 2456 }
2457 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2458 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2459 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2460 changed = true;
facd619b 2461 }
801bcfff 2462
facd619b
VS		 2463 /*
2464 * Don't touch WM1S_LP_EN here.
2465 * Doing so could cause underruns.
2466 */
6cef2b8a 2467
8553c18e
VS		 2468 return changed;
2469}
2470
2471/*
2472 * The spec says we shouldn't write when we don't need, because every write
2473 * causes WMs to be re-evaluated, expending some power.
2474 */
820c1980
ID		 2475static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2476 struct ilk_wm_values *results)
8553c18e
VS		 2477{
2478 struct drm_device *dev = dev_priv->dev;
820c1980 2479 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2480 unsigned int dirty;
2481 uint32_t val;
2482
055e393f 2483 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2484 if (!dirty)
2485 return;
2486
2487 _ilk_disable_lp_wm(dev_priv, dirty);
2488
49a687c4 2489 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2490 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2491 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2492 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2493 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2494 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2495
49a687c4 2496 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2497 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2498 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2499 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2500 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2501 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2502
49a687c4 2503 if (dirty & WM_DIRTY_DDB) {
a42a5719 2504 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2505 val = I915_READ(WM_MISC);
2506 if (results->partitioning == INTEL_DDB_PART_1_2)
2507 val &= ~WM_MISC_DATA_PARTITION_5_6;
2508 else
2509 val |= WM_MISC_DATA_PARTITION_5_6;
2510 I915_WRITE(WM_MISC, val);
2511 } else {
2512 val = I915_READ(DISP_ARB_CTL2);
2513 if (results->partitioning == INTEL_DDB_PART_1_2)
2514 val &= ~DISP_DATA_PARTITION_5_6;
2515 else
2516 val |= DISP_DATA_PARTITION_5_6;
2517 I915_WRITE(DISP_ARB_CTL2, val);
2518 }
1011d8c4
PZ		 2519 }
2520
49a687c4 2521 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2522 val = I915_READ(DISP_ARB_CTL);
2523 if (results->enable_fbc_wm)
2524 val &= ~DISP_FBC_WM_DIS;
2525 else
2526 val |= DISP_FBC_WM_DIS;
2527 I915_WRITE(DISP_ARB_CTL, val);
2528 }
2529
954911eb
ID		 2530 if (dirty & WM_DIRTY_LP(1) &&
2531 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2532 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2533
2534 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2535 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2536 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2537 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2538 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2539 }
801bcfff 2540
facd619b 2541 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2542 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2543 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2544 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2545 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2546 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2547
2548 dev_priv->wm.hw = *results;
801bcfff
PZ		 2549}
2550
8553c18e
VS		 2551static bool ilk_disable_lp_wm(struct drm_device *dev)
2552{
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2554
2555 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2556}
2557
b9cec075
DL		 2558/*
2559 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2560 * different active planes.
2561 */
2562
2563#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2564#define BXT_DDB_SIZE 512
b9cec075
DL		 2565
2566static void
2567skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2568 struct drm_crtc *for_crtc,
2569 const struct intel_wm_config *config,
2570 const struct skl_pipe_wm_parameters *params,
2571 struct skl_ddb_entry *alloc /* out */)
2572{
2573 struct drm_crtc *crtc;
2574 unsigned int pipe_size, ddb_size;
2575 int nth_active_pipe;
2576
2577 if (!params->active) {
2578 alloc->start = 0;
2579 alloc->end = 0;
2580 return;
2581 }
2582
43d735a6
DL		 2583 if (IS_BROXTON(dev))
2584 ddb_size = BXT_DDB_SIZE;
2585 else
2586 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2587
2588 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2589
2590 nth_active_pipe = 0;
2591 for_each_crtc(dev, crtc) {
3ef00284 2592 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2593 continue;
2594
2595 if (crtc == for_crtc)
2596 break;
2597
2598 nth_active_pipe++;
2599 }
2600
2601 pipe_size = ddb_size / config->num_pipes_active;
2602 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2603 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2604}
2605
2606static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2607{
2608 if (config->num_pipes_active == 1)
2609 return 32;
2610
2611 return 8;
2612}
2613
a269c583
DL		 2614static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2615{
2616 entry->start = reg & 0x3ff;
2617 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2618 if (entry->end)
2619 entry->end += 1;
a269c583
DL		 2620}
2621
08db6652
DL		 2622void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2623 struct skl_ddb_allocation *ddb /* out */)
a269c583 2624{
a269c583
DL		 2625 enum pipe pipe;
2626 int plane;
2627 u32 val;
2628
2629 for_each_pipe(dev_priv, pipe) {
dd740780 2630 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2631 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2632 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2633 val);
2634 }
2635
2636 val = I915_READ(CUR_BUF_CFG(pipe));
2637 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2638 }
2639}
2640
b9cec075 2641static unsigned int
2cd601c6 2642skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2643{
2cd601c6
CK		 2644
2645 /* for planar format */
2646 if (p->y_bytes_per_pixel) {
2647 if (y) /* y-plane data rate */
2648 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2649 else /* uv-plane data rate */
2650 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2651 }
2652
2653 /* for packed formats */
b9cec075
DL		 2654 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2655}
2656
2657/*
2658 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2659 * a 8192x4096@32bpp framebuffer:
2660 * 3 * 4096 * 8192 * 4 < 2^32
2661 */
2662static unsigned int
2663skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2664 const struct skl_pipe_wm_parameters *params)
2665{
2666 unsigned int total_data_rate = 0;
2667 int plane;
2668
2669 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2670 const struct intel_plane_wm_parameters *p;
2671
2672 p = &params->plane[plane];
2673 if (!p->enabled)
2674 continue;
2675
2cd601c6
CK		 2676 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2677 if (p->y_bytes_per_pixel) {
2678 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2679 }
b9cec075
DL		 2680 }
2681
2682 return total_data_rate;
2683}
2684
2685static void
2686skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2687 const struct intel_wm_config *config,
2688 const struct skl_pipe_wm_parameters *params,
2689 struct skl_ddb_allocation *ddb /* out */)
2690{
2691 struct drm_device *dev = crtc->dev;
dd740780 2692 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2694 enum pipe pipe = intel_crtc->pipe;
34bb56af 2695 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2696 uint16_t alloc_size, start, cursor_blocks;
80958155 2697 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2698 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2699 unsigned int total_data_rate;
2700 int plane;
2701
34bb56af
DL		 2702 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2703 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2704 if (alloc_size == 0) {
2705 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2706 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2707 return;
2708 }
2709
2710 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2711 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2712 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2713
2714 alloc_size -= cursor_blocks;
34bb56af 2715 alloc->end -= cursor_blocks;
b9cec075 2716
80958155 2717 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2718 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2719 const struct intel_plane_wm_parameters *p;
2720
2721 p = &params->plane[plane];
2722 if (!p->enabled)
2723 continue;
2724
2725 minimum[plane] = 8;
2726 alloc_size -= minimum[plane];
2cd601c6
CK		 2727 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2728 alloc_size -= y_minimum[plane];
80958155
DL		 2729 }
2730
b9cec075 2731 /*
80958155
DL		 2732 * 2. Distribute the remaining space in proportion to the amount of
2733 * data each plane needs to fetch from memory.
b9cec075
DL		 2734 *
2735 * FIXME: we may not allocate every single block here.
2736 */
2737 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2738
34bb56af 2739 start = alloc->start;
b9cec075
DL		 2740 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2741 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 2742 unsigned int data_rate, y_data_rate;
2743 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 2744
2745 p = &params->plane[plane];
2746 if (!p->enabled)
2747 continue;
2748
2cd601c6 2749 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 2750
2751 /*
2cd601c6 2752 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 2753 * promote the expression to 64 bits to avoid overflowing, the
2754 * result is < available as data_rate / total_data_rate < 1
2755 */
80958155
DL		 2756 plane_blocks = minimum[plane];
2757 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2758 total_data_rate);
b9cec075
DL		 2759
2760 ddb->plane[pipe][plane].start = start;
16160e3d 2761 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 2762
2763 start += plane_blocks;
2cd601c6
CK		 2764
2765 /*
2766 * allocation for y_plane part of planar format:
2767 */
2768 if (p->y_bytes_per_pixel) {
2769 y_data_rate = skl_plane_relative_data_rate(p, 1);
2770 y_plane_blocks = y_minimum[plane];
2771 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2772 total_data_rate);
2773
2774 ddb->y_plane[pipe][plane].start = start;
2775 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2776
2777 start += y_plane_blocks;
2778 }
2779
b9cec075
DL		 2780 }
2781
2782}
2783
5cec258b 2784static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 2785{
2786 /* TODO: Take into account the scalers once we support them */
2d112de7 2787 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 2788}
2789
2790/*
2791 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2792 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2793 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2794 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2795*/
2796static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2797 uint32_t latency)
2798{
2799 uint32_t wm_intermediate_val, ret;
2800
2801 if (latency == 0)
2802 return UINT_MAX;
2803
d4c2aa60 2804 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 2805 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2806
2807 return ret;
2808}
2809
2810static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2811 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 2812 uint64_t tiling, uint32_t latency)
2d41c0b5 2813{
d4c2aa60
TU		 2814 uint32_t ret;
2815 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2816 uint32_t wm_intermediate_val;
2d41c0b5
PB		 2817
2818 if (latency == 0)
2819 return UINT_MAX;
2820
2821 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 2822
2823 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2824 tiling == I915_FORMAT_MOD_Yf_TILED) {
2825 plane_bytes_per_line *= 4;
2826 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2827 plane_blocks_per_line /= 4;
2828 } else {
2829 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2830 }
2831
2d41c0b5
PB		 2832 wm_intermediate_val = latency * pixel_rate;
2833 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 2834 plane_blocks_per_line;
2d41c0b5
PB		 2835
2836 return ret;
2837}
2838
2d41c0b5
PB		 2839static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2840 const struct intel_crtc *intel_crtc)
2841{
2842 struct drm_device *dev = intel_crtc->base.dev;
2843 struct drm_i915_private *dev_priv = dev->dev_private;
2844 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2845 enum pipe pipe = intel_crtc->pipe;
2846
2847 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2848 sizeof(new_ddb->plane[pipe])))
2849 return true;
2850
2851 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2852 sizeof(new_ddb->cursor[pipe])))
2853 return true;
2854
2855 return false;
2856}
2857
2858static void skl_compute_wm_global_parameters(struct drm_device *dev,
2859 struct intel_wm_config *config)
2860{
2861 struct drm_crtc *crtc;
2862 struct drm_plane *plane;
2863
2864 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 2865 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 2866
2867 /* FIXME: I don't think we need those two global parameters on SKL */
2868 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2869 struct intel_plane *intel_plane = to_intel_plane(plane);
2870
2871 config->sprites_enabled |= intel_plane->wm.enabled;
2872 config->sprites_scaled |= intel_plane->wm.scaled;
2873 }
2874}
2875
2876static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2877 struct skl_pipe_wm_parameters *p)
2878{
2879 struct drm_device *dev = crtc->dev;
2880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2881 enum pipe pipe = intel_crtc->pipe;
2882 struct drm_plane *plane;
0fda6568 2883 struct drm_framebuffer *fb;
2d41c0b5
PB		 2884 int i = 1; /* Index for sprite planes start */
2885
3ef00284 2886 p->active = intel_crtc->active;
2d41c0b5 2887 if (p->active) {
6e3c9717
ACO		 2888 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2889 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 2890
0fda6568 2891 fb = crtc->primary->state->fb;
2cd601c6 2892 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 2893 if (fb) {
2894 p->plane[0].enabled = true;
2cd601c6
CK		 2895 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2896 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
2897 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2898 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 2899 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 2900 } else {
2901 p->plane[0].enabled = false;
2902 p->plane[0].bytes_per_pixel = 0;
2cd601c6 2903 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 2904 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2905 }
2906 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2907 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 2908 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 2909
c9f038a1 2910 fb = crtc->cursor->state->fb;
2cd601c6 2911 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 2912 if (fb) {
2913 p->cursor.enabled = true;
2914 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2915 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2916 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2917 } else {
2918 p->cursor.enabled = false;
2919 p->cursor.bytes_per_pixel = 0;
2920 p->cursor.horiz_pixels = 64;
2921 p->cursor.vert_pixels = 64;
2922 }
2d41c0b5
PB		 2923 }
2924
2925 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2926 struct intel_plane *intel_plane = to_intel_plane(plane);
2927
a712f8eb
SJ		 2928 if (intel_plane->pipe == pipe &&
2929 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 2930 p->plane[i++] = intel_plane->wm;
2931 }
2932}
2933
d4c2aa60
TU		 2934static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2935 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 2936 struct intel_plane_wm_parameters *p_params,
2937 uint16_t ddb_allocation,
d4c2aa60 2938 int level,
afb024aa
DL		 2939 uint16_t *out_blocks, /* out */
2940 uint8_t *out_lines /* out */)
2d41c0b5 2941{
d4c2aa60
TU		 2942 uint32_t latency = dev_priv->wm.skl_latency[level];
2943 uint32_t method1, method2;
2944 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2945 uint32_t res_blocks, res_lines;
2946 uint32_t selected_result;
2cd601c6 2947 uint8_t bytes_per_pixel;
2d41c0b5 2948
d4c2aa60 2949 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 2950 return false;
2951
2cd601c6
CK		 2952 bytes_per_pixel = p_params->y_bytes_per_pixel ?
2953 p_params->y_bytes_per_pixel :
2954 p_params->bytes_per_pixel;
2d41c0b5 2955 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 2956 bytes_per_pixel,
d4c2aa60 2957 latency);
2d41c0b5
PB		 2958 method2 = skl_wm_method2(p->pixel_rate,
2959 p->pipe_htotal,
2960 p_params->horiz_pixels,
2cd601c6 2961 bytes_per_pixel,
0fda6568 2962 p_params->tiling,
d4c2aa60 2963 latency);
2d41c0b5 2964
2cd601c6 2965 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 2966 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 2967
0fda6568
TU		 2968 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2969 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 2970 uint32_t min_scanlines = 4;
2971 uint32_t y_tile_minimum;
2972 if (intel_rotation_90_or_270(p_params->rotation)) {
2973 switch (p_params->bytes_per_pixel) {
2974 case 1:
2975 min_scanlines = 16;
2976 break;
2977 case 2:
2978 min_scanlines = 8;
2979 break;
2980 case 8:
2981 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 2982 }
1fc0a8f7
TU		 2983 }
2984 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 2985 selected_result = max(method2, y_tile_minimum);
2986 } else {
2987 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2988 selected_result = min(method1, method2);
2989 else
2990 selected_result = method1;
2991 }
2d41c0b5 2992
d4c2aa60
TU		 2993 res_blocks = selected_result + 1;
2994 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 2995
0fda6568
TU		 2996 if (level >= 1 && level <= 7) {
2997 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2998 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2999 res_lines += 4;
3000 else
3001 res_blocks++;
3002 }
e6d66171 3003
d4c2aa60 3004 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3005 return false;
3006
3007 *out_blocks = res_blocks;
3008 *out_lines = res_lines;
2d41c0b5
PB		 3009
3010 return true;
3011}
3012
3013static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3014 struct skl_ddb_allocation *ddb,
3015 struct skl_pipe_wm_parameters *p,
3016 enum pipe pipe,
3017 int level,
3018 int num_planes,
3019 struct skl_wm_level *result)
3020{
2d41c0b5
PB		 3021 uint16_t ddb_blocks;
3022 int i;
3023
3024 for (i = 0; i < num_planes; i++) {
3025 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3026
d4c2aa60
TU		 3027 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3028 p, &p->plane[i],
2d41c0b5 3029 ddb_blocks,
d4c2aa60 3030 level,
2d41c0b5
PB		 3031 &result->plane_res_b[i],
3032 &result->plane_res_l[i]);
3033 }
3034
3035 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3036 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3037 ddb_blocks, level,
3038 &result->cursor_res_b,
2d41c0b5
PB		 3039 &result->cursor_res_l);
3040}
3041
407b50f3
DL		 3042static uint32_t
3043skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3044{
3ef00284 3045 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3046 return 0;
3047
3048 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3049
3050}
3051
3052static void skl_compute_transition_wm(struct drm_crtc *crtc,
3053 struct skl_pipe_wm_parameters *params,
9414f563 3054 struct skl_wm_level *trans_wm /* out */)
407b50f3 3055{
9414f563
DL		 3056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3057 int i;
3058
407b50f3
DL		 3059 if (!params->active)
3060 return;
9414f563
DL		 3061
3062 /* Until we know more, just disable transition WMs */
3063 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3064 trans_wm->plane_en[i] = false;
3065 trans_wm->cursor_en = false;
407b50f3
DL		 3066}
3067
2d41c0b5
PB		 3068static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3069 struct skl_ddb_allocation *ddb,
3070 struct skl_pipe_wm_parameters *params,
3071 struct skl_pipe_wm *pipe_wm)
3072{
3073 struct drm_device *dev = crtc->dev;
3074 const struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076 int level, max_level = ilk_wm_max_level(dev);
3077
3078 for (level = 0; level <= max_level; level++) {
3079 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3080 level, intel_num_planes(intel_crtc),
3081 &pipe_wm->wm[level]);
3082 }
3083 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3084
9414f563 3085 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3086}
3087
3088static void skl_compute_wm_results(struct drm_device *dev,
3089 struct skl_pipe_wm_parameters *p,
3090 struct skl_pipe_wm *p_wm,
3091 struct skl_wm_values *r,
3092 struct intel_crtc *intel_crtc)
3093{
3094 int level, max_level = ilk_wm_max_level(dev);
3095 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3096 uint32_t temp;
3097 int i;
2d41c0b5
PB		 3098
3099 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3100 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3101 temp = 0;
2d41c0b5
PB		 3102
3103 temp |= p_wm->wm[level].plane_res_l[i] <<
3104 PLANE_WM_LINES_SHIFT;
3105 temp |= p_wm->wm[level].plane_res_b[i];
3106 if (p_wm->wm[level].plane_en[i])
3107 temp |= PLANE_WM_EN;
3108
3109 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3110 }
3111
3112 temp = 0;
2d41c0b5
PB		 3113
3114 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3115 temp |= p_wm->wm[level].cursor_res_b;
3116
3117 if (p_wm->wm[level].cursor_en)
3118 temp |= PLANE_WM_EN;
3119
3120 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3121
3122 }
3123
9414f563
DL		 3124 /* transition WMs */
3125 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3126 temp = 0;
3127 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3128 temp |= p_wm->trans_wm.plane_res_b[i];
3129 if (p_wm->trans_wm.plane_en[i])
3130 temp |= PLANE_WM_EN;
3131
3132 r->plane_trans[pipe][i] = temp;
3133 }
3134
3135 temp = 0;
3136 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3137 temp |= p_wm->trans_wm.cursor_res_b;
3138 if (p_wm->trans_wm.cursor_en)
3139 temp |= PLANE_WM_EN;
3140
3141 r->cursor_trans[pipe] = temp;
3142
2d41c0b5
PB		 3143 r->wm_linetime[pipe] = p_wm->linetime;
3144}
3145
16160e3d
DL		 3146static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3147 const struct skl_ddb_entry *entry)
3148{
3149 if (entry->end)
3150 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3151 else
3152 I915_WRITE(reg, 0);
3153}
3154
2d41c0b5
PB		 3155static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3156 const struct skl_wm_values *new)
3157{
3158 struct drm_device *dev = dev_priv->dev;
3159 struct intel_crtc *crtc;
3160
3161 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3162 int i, level, max_level = ilk_wm_max_level(dev);
3163 enum pipe pipe = crtc->pipe;
3164
5d374d96
DL		 3165 if (!new->dirty[pipe])
3166 continue;
8211bd5b 3167
5d374d96 3168 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3169
5d374d96
DL		 3170 for (level = 0; level <= max_level; level++) {
3171 for (i = 0; i < intel_num_planes(crtc); i++)
3172 I915_WRITE(PLANE_WM(pipe, i, level),
3173 new->plane[pipe][i][level]);
3174 I915_WRITE(CUR_WM(pipe, level),
3175 new->cursor[pipe][level]);
2d41c0b5 3176 }
5d374d96
DL		 3177 for (i = 0; i < intel_num_planes(crtc); i++)
3178 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3179 new->plane_trans[pipe][i]);
3180 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3181
2cd601c6 3182 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3183 skl_ddb_entry_write(dev_priv,
3184 PLANE_BUF_CFG(pipe, i),
3185 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3186 skl_ddb_entry_write(dev_priv,
3187 PLANE_NV12_BUF_CFG(pipe, i),
3188 &new->ddb.y_plane[pipe][i]);
3189 }
5d374d96
DL		 3190
3191 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3192 &new->ddb.cursor[pipe]);
2d41c0b5 3193 }
2d41c0b5
PB		 3194}
3195
0e8fb7ba
DL		 3196/*
3197 * When setting up a new DDB allocation arrangement, we need to correctly
3198 * sequence the times at which the new allocations for the pipes are taken into
3199 * account or we'll have pipes fetching from space previously allocated to
3200 * another pipe.
3201 *
3202 * Roughly the sequence looks like:
3203 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3204 * overlapping with a previous light-up pipe (another way to put it is:
3205 * pipes with their new allocation strickly included into their old ones).
3206 * 2. re-allocate the other pipes that get their allocation reduced
3207 * 3. allocate the pipes having their allocation increased
3208 *
3209 * Steps 1. and 2. are here to take care of the following case:
3210 * - Initially DDB looks like this:
3211 * | B | C |
3212 * - enable pipe A.
3213 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3214 * allocation
3215 * | A | B | C |
3216 *
3217 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3218 */
3219
d21b795c
DL		 3220static void
3221skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3222{
0e8fb7ba
DL		 3223 int plane;
3224
d21b795c
DL		 3225 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3226
dd740780 3227 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3228 I915_WRITE(PLANE_SURF(pipe, plane),
3229 I915_READ(PLANE_SURF(pipe, plane)));
3230 }
3231 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3232}
3233
3234static bool
3235skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3236 const struct skl_ddb_allocation *new,
3237 enum pipe pipe)
3238{
3239 uint16_t old_size, new_size;
3240
3241 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3242 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3243
3244 return old_size != new_size &&
3245 new->pipe[pipe].start >= old->pipe[pipe].start &&
3246 new->pipe[pipe].end <= old->pipe[pipe].end;
3247}
3248
3249static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3250 struct skl_wm_values *new_values)
3251{
3252 struct drm_device *dev = dev_priv->dev;
3253 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3254 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3255 struct intel_crtc *crtc;
3256 enum pipe pipe;
3257
3258 new_ddb = &new_values->ddb;
3259 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3260
3261 /*
3262 * First pass: flush the pipes with the new allocation contained into
3263 * the old space.
3264 *
3265 * We'll wait for the vblank on those pipes to ensure we can safely
3266 * re-allocate the freed space without this pipe fetching from it.
3267 */
3268 for_each_intel_crtc(dev, crtc) {
3269 if (!crtc->active)
3270 continue;
3271
3272 pipe = crtc->pipe;
3273
3274 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3275 continue;
3276
d21b795c 3277 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3278 intel_wait_for_vblank(dev, pipe);
3279
3280 reallocated[pipe] = true;
3281 }
3282
3283
3284 /*
3285 * Second pass: flush the pipes that are having their allocation
3286 * reduced, but overlapping with a previous allocation.
3287 *
3288 * Here as well we need to wait for the vblank to make sure the freed
3289 * space is not used anymore.
3290 */
3291 for_each_intel_crtc(dev, crtc) {
3292 if (!crtc->active)
3293 continue;
3294
3295 pipe = crtc->pipe;
3296
3297 if (reallocated[pipe])
3298 continue;
3299
3300 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3301 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3302 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3303 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3304 reallocated[pipe] = true;
0e8fb7ba 3305 }
0e8fb7ba
DL		 3306 }
3307
3308 /*
3309 * Third pass: flush the pipes that got more space allocated.
3310 *
3311 * We don't need to actively wait for the update here, next vblank
3312 * will just get more DDB space with the correct WM values.
3313 */
3314 for_each_intel_crtc(dev, crtc) {
3315 if (!crtc->active)
3316 continue;
3317
3318 pipe = crtc->pipe;
3319
3320 /*
3321 * At this point, only the pipes more space than before are
3322 * left to re-allocate.
3323 */
3324 if (reallocated[pipe])
3325 continue;
3326
d21b795c 3327 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3328 }
3329}
3330
2d41c0b5
PB		 3331static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3332 struct skl_pipe_wm_parameters *params,
3333 struct intel_wm_config *config,
3334 struct skl_ddb_allocation *ddb, /* out */
3335 struct skl_pipe_wm *pipe_wm /* out */)
3336{
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338
3339 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3340 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3341 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3342
3343 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3344 return false;
3345
3346 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3347
2d41c0b5
PB		 3348 return true;
3349}
3350
3351static void skl_update_other_pipe_wm(struct drm_device *dev,
3352 struct drm_crtc *crtc,
3353 struct intel_wm_config *config,
3354 struct skl_wm_values *r)
3355{
3356 struct intel_crtc *intel_crtc;
3357 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3358
3359 /*
3360 * If the WM update hasn't changed the allocation for this_crtc (the
3361 * crtc we are currently computing the new WM values for), other
3362 * enabled crtcs will keep the same allocation and we don't need to
3363 * recompute anything for them.
3364 */
3365 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3366 return;
3367
3368 /*
3369 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3370 * other active pipes need new DDB allocation and WM values.
3371 */
3372 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3373 base.head) {
3374 struct skl_pipe_wm_parameters params = {};
3375 struct skl_pipe_wm pipe_wm = {};
3376 bool wm_changed;
3377
3378 if (this_crtc->pipe == intel_crtc->pipe)
3379 continue;
3380
3381 if (!intel_crtc->active)
3382 continue;
3383
3384 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3385 &params, config,
3386 &r->ddb, &pipe_wm);
3387
3388 /*
3389 * If we end up re-computing the other pipe WM values, it's
3390 * because it was really needed, so we expect the WM values to
3391 * be different.
3392 */
3393 WARN_ON(!wm_changed);
3394
3395 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3396 r->dirty[intel_crtc->pipe] = true;
3397 }
3398}
3399
3400static void skl_update_wm(struct drm_crtc *crtc)
3401{
3402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3403 struct drm_device *dev = crtc->dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 struct skl_pipe_wm_parameters params = {};
3406 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3407 struct skl_pipe_wm pipe_wm = {};
3408 struct intel_wm_config config = {};
3409
3410 memset(results, 0, sizeof(*results));
3411
3412 skl_compute_wm_global_parameters(dev, &config);
3413
3414 if (!skl_update_pipe_wm(crtc, &params, &config,
3415 &results->ddb, &pipe_wm))
3416 return;
3417
3418 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3419 results->dirty[intel_crtc->pipe] = true;
3420
3421 skl_update_other_pipe_wm(dev, crtc, &config, results);
3422 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3423 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3424
3425 /* store the new configuration */
3426 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3427}
3428
3429static void
3430skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3431 uint32_t sprite_width, uint32_t sprite_height,
3432 int pixel_size, bool enabled, bool scaled)
3433{
3434 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3435 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3436
3437 intel_plane->wm.enabled = enabled;
3438 intel_plane->wm.scaled = scaled;
3439 intel_plane->wm.horiz_pixels = sprite_width;
3440 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3441 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3442
3443 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3444 intel_plane->wm.bytes_per_pixel =
3445 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3446 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3447 intel_plane->wm.y_bytes_per_pixel =
3448 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3449 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3450
0fda6568
TU		 3451 /*
3452 * Framebuffer can be NULL on plane disable, but it does not
3453 * matter for watermarks if we assume no tiling in that case.
3454 */
3455 if (fb)
3456 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3457 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3458
3459 skl_update_wm(crtc);
3460}
3461
820c1980 3462static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3463{
7c4a395f 3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3465 struct drm_device *dev = crtc->dev;
801bcfff 3466 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3467 struct ilk_wm_maximums max;
3468 struct ilk_pipe_wm_parameters params = {};
3469 struct ilk_wm_values results = {};
77c122bc 3470 enum intel_ddb_partitioning partitioning;
7c4a395f 3471 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3472 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3473 struct intel_wm_config config = {};
7c4a395f 3474
2a44b76b 3475 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3476
3477 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3478
3479 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3480 return;
861f3389 3481
7c4a395f 3482 intel_crtc->wm.active = pipe_wm;
861f3389 3483
2a44b76b
VS		 3484 ilk_compute_wm_config(dev, &config);
3485
34982fe1 3486 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3487 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3488
3489 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3490 if (INTEL_INFO(dev)->gen >= 7 &&
3491 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3492 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3493 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3494
820c1980 3495 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3496 } else {
198a1e9b 3497 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3498 }
3499
198a1e9b 3500 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3501 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3502
820c1980 3503 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3504
820c1980 3505 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3506}
3507
ed57cb8a
DL		 3508static void
3509ilk_update_sprite_wm(struct drm_plane *plane,
3510 struct drm_crtc *crtc,
3511 uint32_t sprite_width, uint32_t sprite_height,
3512 int pixel_size, bool enabled, bool scaled)
526682e9 3513{
8553c18e 3514 struct drm_device *dev = plane->dev;
adf3d35e 3515 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3516
adf3d35e
VS		 3517 intel_plane->wm.enabled = enabled;
3518 intel_plane->wm.scaled = scaled;
3519 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3520 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3521 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3522
8553c18e
VS		 3523 /*
3524 * IVB workaround: must disable low power watermarks for at least
3525 * one frame before enabling scaling. LP watermarks can be re-enabled
3526 * when scaling is disabled.
3527 *
3528 * WaCxSRDisabledForSpriteScaling:ivb
3529 */
3530 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3531 intel_wait_for_vblank(dev, intel_plane->pipe);
3532
820c1980 3533 ilk_update_wm(crtc);
526682e9
PZ		 3534}
3535
3078999f
PB		 3536static void skl_pipe_wm_active_state(uint32_t val,
3537 struct skl_pipe_wm *active,
3538 bool is_transwm,
3539 bool is_cursor,
3540 int i,
3541 int level)
3542{
3543 bool is_enabled = (val & PLANE_WM_EN) != 0;
3544
3545 if (!is_transwm) {
3546 if (!is_cursor) {
3547 active->wm[level].plane_en[i] = is_enabled;
3548 active->wm[level].plane_res_b[i] =
3549 val & PLANE_WM_BLOCKS_MASK;
3550 active->wm[level].plane_res_l[i] =
3551 (val >> PLANE_WM_LINES_SHIFT) &
3552 PLANE_WM_LINES_MASK;
3553 } else {
3554 active->wm[level].cursor_en = is_enabled;
3555 active->wm[level].cursor_res_b =
3556 val & PLANE_WM_BLOCKS_MASK;
3557 active->wm[level].cursor_res_l =
3558 (val >> PLANE_WM_LINES_SHIFT) &
3559 PLANE_WM_LINES_MASK;
3560 }
3561 } else {
3562 if (!is_cursor) {
3563 active->trans_wm.plane_en[i] = is_enabled;
3564 active->trans_wm.plane_res_b[i] =
3565 val & PLANE_WM_BLOCKS_MASK;
3566 active->trans_wm.plane_res_l[i] =
3567 (val >> PLANE_WM_LINES_SHIFT) &
3568 PLANE_WM_LINES_MASK;
3569 } else {
3570 active->trans_wm.cursor_en = is_enabled;
3571 active->trans_wm.cursor_res_b =
3572 val & PLANE_WM_BLOCKS_MASK;
3573 active->trans_wm.cursor_res_l =
3574 (val >> PLANE_WM_LINES_SHIFT) &
3575 PLANE_WM_LINES_MASK;
3576 }
3577 }
3578}
3579
3580static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3581{
3582 struct drm_device *dev = crtc->dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3587 enum pipe pipe = intel_crtc->pipe;
3588 int level, i, max_level;
3589 uint32_t temp;
3590
3591 max_level = ilk_wm_max_level(dev);
3592
3593 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3594
3595 for (level = 0; level <= max_level; level++) {
3596 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3597 hw->plane[pipe][i][level] =
3598 I915_READ(PLANE_WM(pipe, i, level));
3599 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3600 }
3601
3602 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3603 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3604 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3605
3ef00284 3606 if (!intel_crtc->active)
3078999f
PB		 3607 return;
3608
3609 hw->dirty[pipe] = true;
3610
3611 active->linetime = hw->wm_linetime[pipe];
3612
3613 for (level = 0; level <= max_level; level++) {
3614 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3615 temp = hw->plane[pipe][i][level];
3616 skl_pipe_wm_active_state(temp, active, false,
3617 false, i, level);
3618 }
3619 temp = hw->cursor[pipe][level];
3620 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3621 }
3622
3623 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3624 temp = hw->plane_trans[pipe][i];
3625 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3626 }
3627
3628 temp = hw->cursor_trans[pipe];
3629 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3630}
3631
3632void skl_wm_get_hw_state(struct drm_device *dev)
3633{
a269c583
DL		 3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3636 struct drm_crtc *crtc;
3637
a269c583 3638 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3639 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3640 skl_pipe_wm_get_hw_state(crtc);
3641}
3642
243e6a44
VS		 3643static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3644{
3645 struct drm_device *dev = crtc->dev;
3646 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3647 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3650 enum pipe pipe = intel_crtc->pipe;
3651 static const unsigned int wm0_pipe_reg[] = {
3652 [PIPE_A] = WM0_PIPEA_ILK,
3653 [PIPE_B] = WM0_PIPEB_ILK,
3654 [PIPE_C] = WM0_PIPEC_IVB,
3655 };
3656
3657 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3658 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3659 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3660
3ef00284 3661 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3662
3663 if (active->pipe_enabled) {
243e6a44
VS		 3664 u32 tmp = hw->wm_pipe[pipe];
3665
3666 /*
3667 * For active pipes LP0 watermark is marked as
3668 * enabled, and LP1+ watermaks as disabled since
3669 * we can't really reverse compute them in case
3670 * multiple pipes are active.
3671 */
3672 active->wm[0].enable = true;
3673 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3674 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3675 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3676 active->linetime = hw->wm_linetime[pipe];
3677 } else {
3678 int level, max_level = ilk_wm_max_level(dev);
3679
3680 /*
3681 * For inactive pipes, all watermark levels
3682 * should be marked as enabled but zeroed,
3683 * which is what we'd compute them to.
3684 */
3685 for (level = 0; level <= max_level; level++)
3686 active->wm[level].enable = true;
3687 }
3688}
3689
3690void ilk_wm_get_hw_state(struct drm_device *dev)
3691{
3692 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3693 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3694 struct drm_crtc *crtc;
3695
70e1e0ec 3696 for_each_crtc(dev, crtc)
243e6a44
VS		 3697 ilk_pipe_wm_get_hw_state(crtc);
3698
3699 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3700 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3701 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3702
3703 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3704 if (INTEL_INFO(dev)->gen >= 7) {
3705 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3706 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3707 }
243e6a44 3708
a42a5719 3709 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3710 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3711 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3712 else if (IS_IVYBRIDGE(dev))
3713 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3714 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3715
3716 hw->enable_fbc_wm =
3717 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3718}
3719
b445e3b0
ED		 3720/**
3721 * intel_update_watermarks - update FIFO watermark values based on current modes
3722 *
3723 * Calculate watermark values for the various WM regs based on current mode
3724 * and plane configuration.
3725 *
3726 * There are several cases to deal with here:
3727 * - normal (i.e. non-self-refresh)
3728 * - self-refresh (SR) mode
3729 * - lines are large relative to FIFO size (buffer can hold up to 2)
3730 * - lines are small relative to FIFO size (buffer can hold more than 2
3731 * lines), so need to account for TLB latency
3732 *
3733 * The normal calculation is:
3734 * watermark = dotclock * bytes per pixel * latency
3735 * where latency is platform & configuration dependent (we assume pessimal
3736 * values here).
3737 *
3738 * The SR calculation is:
3739 * watermark = (trunc(latency/line time)+1) * surface width *
3740 * bytes per pixel
3741 * where
3742 * line time = htotal / dotclock
3743 * surface width = hdisplay for normal plane and 64 for cursor
3744 * and latency is assumed to be high, as above.
3745 *
3746 * The final value programmed to the register should always be rounded up,
3747 * and include an extra 2 entries to account for clock crossings.
3748 *
3749 * We don't use the sprite, so we can ignore that. And on Crestline we have
3750 * to set the non-SR watermarks to 8.
3751 */
46ba614c 3752void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3753{
46ba614c 3754 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3755
3756 if (dev_priv->display.update_wm)
46ba614c 3757 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3758}
3759
adf3d35e
VS		 3760void intel_update_sprite_watermarks(struct drm_plane *plane,
3761 struct drm_crtc *crtc,
ed57cb8a
DL		 3762 uint32_t sprite_width,
3763 uint32_t sprite_height,
3764 int pixel_size,
39db4a4d 3765 bool enabled, bool scaled)
b445e3b0 3766{
adf3d35e 3767 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3768
3769 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 3770 dev_priv->display.update_sprite_wm(plane, crtc,
3771 sprite_width, sprite_height,
39db4a4d 3772 pixel_size, enabled, scaled);
b445e3b0
ED		 3773}
3774
9270388e
DV		 3775/**
3776 * Lock protecting IPS related data structures
9270388e
DV		 3777 */
3778DEFINE_SPINLOCK(mchdev_lock);
3779
3780/* Global for IPS driver to get at the current i915 device. Protected by
3781 * mchdev_lock. */
3782static struct drm_i915_private *i915_mch_dev;
3783
2b4e57bd
ED		 3784bool ironlake_set_drps(struct drm_device *dev, u8 val)
3785{
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 u16 rgvswctl;
3788
9270388e
DV		 3789 assert_spin_locked(&mchdev_lock);
3790
2b4e57bd
ED		 3791 rgvswctl = I915_READ16(MEMSWCTL);
3792 if (rgvswctl & MEMCTL_CMD_STS) {
3793 DRM_DEBUG("gpu busy, RCS change rejected\n");
3794 return false; /* still busy with another command */
3795 }
3796
3797 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3798 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3799 I915_WRITE16(MEMSWCTL, rgvswctl);
3800 POSTING_READ16(MEMSWCTL);
3801
3802 rgvswctl |= MEMCTL_CMD_STS;
3803 I915_WRITE16(MEMSWCTL, rgvswctl);
3804
3805 return true;
3806}
3807
8090c6b9 3808static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3809{
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 u32 rgvmodectl = I915_READ(MEMMODECTL);
3812 u8 fmax, fmin, fstart, vstart;
3813
9270388e
DV		 3814 spin_lock_irq(&mchdev_lock);
3815
2b4e57bd
ED		 3816 /* Enable temp reporting */
3817 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3818 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3819
3820 /* 100ms RC evaluation intervals */
3821 I915_WRITE(RCUPEI, 100000);
3822 I915_WRITE(RCDNEI, 100000);
3823
3824 /* Set max/min thresholds to 90ms and 80ms respectively */
3825 I915_WRITE(RCBMAXAVG, 90000);
3826 I915_WRITE(RCBMINAVG, 80000);
3827
3828 I915_WRITE(MEMIHYST, 1);
3829
3830 /* Set up min, max, and cur for interrupt handling */
3831 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3832 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3833 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3834 MEMMODE_FSTART_SHIFT;
3835
3836 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3837 PXVFREQ_PX_SHIFT;
3838
20e4d407
DV		 3839 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3840 dev_priv->ips.fstart = fstart;
2b4e57bd 3841
20e4d407
DV		 3842 dev_priv->ips.max_delay = fstart;
3843 dev_priv->ips.min_delay = fmin;
3844 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3845
3846 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3847 fmax, fmin, fstart);
3848
3849 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3850
3851 /*
3852 * Interrupts will be enabled in ironlake_irq_postinstall
3853 */
3854
3855 I915_WRITE(VIDSTART, vstart);
3856 POSTING_READ(VIDSTART);
3857
3858 rgvmodectl |= MEMMODE_SWMODE_EN;
3859 I915_WRITE(MEMMODECTL, rgvmodectl);
3860
9270388e 3861 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3862 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3863 mdelay(1);
2b4e57bd
ED		 3864
3865 ironlake_set_drps(dev, fstart);
3866
20e4d407 3867 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3868 I915_READ(0x112e0);
20e4d407
DV		 3869 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3870 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3871 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 3872
3873 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3874}
3875
8090c6b9 3876static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3877{
3878 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3879 u16 rgvswctl;
3880
3881 spin_lock_irq(&mchdev_lock);
3882
3883 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3884
3885 /* Ack interrupts, disable EFC interrupt */
3886 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3887 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3888 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3889 I915_WRITE(DEIIR, DE_PCU_EVENT);
3890 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3891
3892 /* Go back to the starting frequency */
20e4d407 3893 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3894 mdelay(1);
2b4e57bd
ED		 3895 rgvswctl |= MEMCTL_CMD_STS;
3896 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3897 mdelay(1);
2b4e57bd 3898
9270388e 3899 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3900}
3901
acbe9475
DV		 3902/* There's a funny hw issue where the hw returns all 0 when reading from
3903 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3904 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3905 * all limits and the gpu stuck at whatever frequency it is at atm).
3906 */
74ef1173 3907static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3908{
7b9e0ae6 3909 u32 limits;
2b4e57bd 3910
20b46e59
DV		 3911 /* Only set the down limit when we've reached the lowest level to avoid
3912 * getting more interrupts, otherwise leave this clear. This prevents a
3913 * race in the hw when coming out of rc6: There's a tiny window where
3914 * the hw runs at the minimal clock before selecting the desired
3915 * frequency, if the down threshold expires in that window we will not
3916 * receive a down interrupt. */
74ef1173
AG		 3917 if (IS_GEN9(dev_priv->dev)) {
3918 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3919 if (val <= dev_priv->rps.min_freq_softlimit)
3920 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3921 } else {
3922 limits = dev_priv->rps.max_freq_softlimit << 24;
3923 if (val <= dev_priv->rps.min_freq_softlimit)
3924 limits |= dev_priv->rps.min_freq_softlimit << 16;
3925 }
20b46e59
DV		 3926
3927 return limits;
3928}
3929
dd75fdc8
CW		 3930static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3931{
3932 int new_power;
8a586437
AG		 3933 u32 threshold_up = 0, threshold_down = 0; /* in % */
3934 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 3935
3936 new_power = dev_priv->rps.power;
3937 switch (dev_priv->rps.power) {
3938 case LOW_POWER:
b39fb297 3939 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3940 new_power = BETWEEN;
3941 break;
3942
3943 case BETWEEN:
b39fb297 3944 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3945 new_power = LOW_POWER;
b39fb297 3946 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 3947 new_power = HIGH_POWER;
3948 break;
3949
3950 case HIGH_POWER:
b39fb297 3951 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 3952 new_power = BETWEEN;
3953 break;
3954 }
3955 /* Max/min bins are special */
aed242ff 3956 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 3957 new_power = LOW_POWER;
aed242ff 3958 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 3959 new_power = HIGH_POWER;
3960 if (new_power == dev_priv->rps.power)
3961 return;
3962
3963 /* Note the units here are not exactly 1us, but 1280ns. */
3964 switch (new_power) {
3965 case LOW_POWER:
3966 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 3967 ei_up = 16000;
3968 threshold_up = 95;
dd75fdc8
CW		 3969
3970 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 3971 ei_down = 32000;
3972 threshold_down = 85;
dd75fdc8
CW		 3973 break;
3974
3975 case BETWEEN:
3976 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 3977 ei_up = 13000;
3978 threshold_up = 90;
dd75fdc8
CW		 3979
3980 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 3981 ei_down = 32000;
3982 threshold_down = 75;
dd75fdc8
CW		 3983 break;
3984
3985 case HIGH_POWER:
3986 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 3987 ei_up = 10000;
3988 threshold_up = 85;
dd75fdc8
CW		 3989
3990 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 3991 ei_down = 32000;
3992 threshold_down = 60;
dd75fdc8
CW		 3993 break;
3994 }
3995
8a586437
AG		 3996 I915_WRITE(GEN6_RP_UP_EI,
3997 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3998 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3999 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4000
4001 I915_WRITE(GEN6_RP_DOWN_EI,
4002 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4003 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4004 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4005
4006 I915_WRITE(GEN6_RP_CONTROL,
4007 GEN6_RP_MEDIA_TURBO |
4008 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4009 GEN6_RP_MEDIA_IS_GFX |
4010 GEN6_RP_ENABLE |
4011 GEN6_RP_UP_BUSY_AVG |
4012 GEN6_RP_DOWN_IDLE_AVG);
4013
dd75fdc8 4014 dev_priv->rps.power = new_power;
8fb55197
CW		 4015 dev_priv->rps.up_threshold = threshold_up;
4016 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4017 dev_priv->rps.last_adj = 0;
4018}
4019
2876ce73
CW		 4020static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4021{
4022 u32 mask = 0;
4023
4024 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4025 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4026 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4027 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4028
7b3c29f6
CW		 4029 mask &= dev_priv->pm_rps_events;
4030
59d02a1f 4031 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4032}
4033
b8a5ff8d
JM		 4034/* gen6_set_rps is called to update the frequency request, but should also be
4035 * called when the range (min_delay and max_delay) is modified so that we can
4036 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4037static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4038{
4039 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4040
4fc688ce 4041 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4042 WARN_ON(val > dev_priv->rps.max_freq);
4043 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4044
eb64cad1
CW		 4045 /* min/max delay may still have been modified so be sure to
4046 * write the limits value.
4047 */
4048 if (val != dev_priv->rps.cur_freq) {
4049 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4050
5704195c
AG		 4051 if (IS_GEN9(dev))
4052 I915_WRITE(GEN6_RPNSWREQ,
4053 GEN9_FREQUENCY(val));
4054 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4055 I915_WRITE(GEN6_RPNSWREQ,
4056 HSW_FREQUENCY(val));
4057 else
4058 I915_WRITE(GEN6_RPNSWREQ,
4059 GEN6_FREQUENCY(val) |
4060 GEN6_OFFSET(0) |
4061 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4062 }
7b9e0ae6 4063
7b9e0ae6
CW		 4064 /* Make sure we continue to get interrupts
4065 * until we hit the minimum or maximum frequencies.
4066 */
74ef1173 4067 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4068 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4069
d5570a72
BW		 4070 POSTING_READ(GEN6_RPNSWREQ);
4071
b39fb297 4072 dev_priv->rps.cur_freq = val;
be2cde9a 4073 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4074}
4075
ffe02b40
VS		 4076static void valleyview_set_rps(struct drm_device *dev, u8 val)
4077{
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079
4080 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4081 WARN_ON(val > dev_priv->rps.max_freq);
4082 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4083
4084 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4085 "Odd GPU freq value\n"))
4086 val &= ~1;
4087
8fb55197 4088 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4089 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4090 if (!IS_CHERRYVIEW(dev_priv))
4091 gen6_set_rps_thresholds(dev_priv, val);
4092 }
ffe02b40
VS		 4093
4094 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4095
4096 dev_priv->rps.cur_freq = val;
4097 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4098}
4099
76c3552f
D		 4100/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
4101 *
4102 * * If Gfx is Idle, then
4103 * 1. Mask Turbo interrupts
4104 * 2. Bring up Gfx clock
4105 * 3. Change the freq to Rpn and wait till P-Unit updates freq
4106 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
4107 * 5. Unmask Turbo interrupts
4108*/
4109static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4110{
5549d25f 4111 struct drm_device *dev = dev_priv->dev;
aed242ff 4112 u32 val = dev_priv->rps.idle_freq;
5549d25f 4113
21a11fff
VS		 4114 /* CHV and latest VLV don't need to force the gfx clock */
4115 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
aed242ff 4116 valleyview_set_rps(dev_priv->dev, val);
5549d25f
D		 4117 return;
4118 }
4119
76c3552f
D		 4120 /*
4121 * When we are idle. Drop to min voltage state.
4122 */
4123
aed242ff 4124 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4125 return;
4126
4127 /* Mask turbo interrupt so that they will not come in between */
f24eeb19
ID		 4128 I915_WRITE(GEN6_PMINTRMSK,
4129 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
76c3552f 4130
650ad970 4131 vlv_force_gfx_clock(dev_priv, true);
76c3552f 4132
aed242ff 4133 dev_priv->rps.cur_freq = val;
76c3552f 4134
aed242ff 4135 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
76c3552f
D		 4136
4137 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
2837ac40 4138 & GENFREQSTATUS) == 0, 100))
76c3552f
D		 4139 DRM_ERROR("timed out waiting for Punit\n");
4140
8fb55197 4141 gen6_set_rps_thresholds(dev_priv, val);
650ad970 4142 vlv_force_gfx_clock(dev_priv, false);
76c3552f 4143
aed242ff 4144 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
76c3552f
D		 4145}
4146
43cf3bf0
CW		 4147void gen6_rps_busy(struct drm_i915_private *dev_priv)
4148{
4149 mutex_lock(&dev_priv->rps.hw_lock);
4150 if (dev_priv->rps.enabled) {
4151 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4152 gen6_rps_reset_ei(dev_priv);
4153 I915_WRITE(GEN6_PMINTRMSK,
4154 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4155 }
4156 mutex_unlock(&dev_priv->rps.hw_lock);
4157}
4158
b29c19b6
CW		 4159void gen6_rps_idle(struct drm_i915_private *dev_priv)
4160{
691bb717
DL		 4161 struct drm_device *dev = dev_priv->dev;
4162
b29c19b6 4163 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4164 if (dev_priv->rps.enabled) {
21a11fff 4165 if (IS_VALLEYVIEW(dev))
76c3552f 4166 vlv_set_rps_idle(dev_priv);
7526ed79 4167 else
aed242ff 4168 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4169 dev_priv->rps.last_adj = 0;
43cf3bf0 4170 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4171 }
1854d5ca
CW		 4172
4173 while (!list_empty(&dev_priv->rps.clients))
4174 list_del_init(dev_priv->rps.clients.next);
b29c19b6
CW		 4175 mutex_unlock(&dev_priv->rps.hw_lock);
4176}
4177
1854d5ca
CW		 4178void gen6_rps_boost(struct drm_i915_private *dev_priv,
4179 struct drm_i915_file_private *file_priv)
b29c19b6 4180{
43cf3bf0
CW		 4181 u32 val;
4182
b29c19b6 4183 mutex_lock(&dev_priv->rps.hw_lock);
43cf3bf0
CW		 4184 val = dev_priv->rps.max_freq_softlimit;
4185 if (dev_priv->rps.enabled &&
4186 dev_priv->mm.busy &&
1854d5ca
CW		 4187 dev_priv->rps.cur_freq < val &&
4188 (file_priv == NULL || list_empty(&file_priv->rps_boost))) {
43cf3bf0 4189 intel_set_rps(dev_priv->dev, val);
c0951f0c 4190 dev_priv->rps.last_adj = 0;
1854d5ca
CW		 4191
4192 if (file_priv != NULL) {
4193 list_add(&file_priv->rps_boost, &dev_priv->rps.clients);
4194 file_priv->rps_boosts++;
4195 } else
4196 dev_priv->rps.boosts++;
c0951f0c 4197 }
b29c19b6
CW		 4198 mutex_unlock(&dev_priv->rps.hw_lock);
4199}
4200
ffe02b40 4201void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4202{
ffe02b40
VS		 4203 if (IS_VALLEYVIEW(dev))
4204 valleyview_set_rps(dev, val);
4205 else
4206 gen6_set_rps(dev, val);
0a073b84
JB		 4207}
4208
20e49366
ZW		 4209static void gen9_disable_rps(struct drm_device *dev)
4210{
4211 struct drm_i915_private *dev_priv = dev->dev_private;
4212
4213 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4214 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4215}
4216
44fc7d5c 4217static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4218{
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220
4221 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4222 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4223}
4224
38807746
D		 4225static void cherryview_disable_rps(struct drm_device *dev)
4226{
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228
4229 I915_WRITE(GEN6_RC_CONTROL, 0);
4230}
4231
44fc7d5c
DV		 4232static void valleyview_disable_rps(struct drm_device *dev)
4233{
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235
98a2e5f9
D		 4236 /* we're doing forcewake before Disabling RC6,
4237 * This what the BIOS expects when going into suspend */
59bad947 4238 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4239
44fc7d5c 4240 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4241
59bad947 4242 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4243}
4244
dc39fff7
BW		 4245static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4246{
91ca689a
ID		 4247 if (IS_VALLEYVIEW(dev)) {
4248 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4249 mode = GEN6_RC_CTL_RC6_ENABLE;
4250 else
4251 mode = 0;
4252 }
58abf1da
RV		 4253 if (HAS_RC6p(dev))
4254 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4255 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4256 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4257 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4258
4259 else
4260 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4261 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4262}
4263
e6069ca8 4264static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4265{
eb4926e4
DL		 4266 /* No RC6 before Ironlake */
4267 if (INTEL_INFO(dev)->gen < 5)
4268 return 0;
4269
e6069ca8
ID		 4270 /* RC6 is only on Ironlake mobile not on desktop */
4271 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4272 return 0;
4273
456470eb 4274 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4275 if (enable_rc6 >= 0) {
4276 int mask;
4277
58abf1da 4278 if (HAS_RC6p(dev))
e6069ca8
ID		 4279 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4280 INTEL_RC6pp_ENABLE;
4281 else
4282 mask = INTEL_RC6_ENABLE;
4283
4284 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4285 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4286 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4287
4288 return enable_rc6 & mask;
4289 }
2b4e57bd 4290
6567d748
CW		 4291 /* Disable RC6 on Ironlake */
4292 if (INTEL_INFO(dev)->gen == 5)
4293 return 0;
2b4e57bd 4294
8bade1ad 4295 if (IS_IVYBRIDGE(dev))
cca84a1f 4296 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4297
4298 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4299}
4300
e6069ca8
ID		 4301int intel_enable_rc6(const struct drm_device *dev)
4302{
4303 return i915.enable_rc6;
4304}
4305
93ee2920 4306static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4307{
93ee2920
TR		 4308 struct drm_i915_private *dev_priv = dev->dev_private;
4309 uint32_t rp_state_cap;
4310 u32 ddcc_status = 0;
4311 int ret;
4312
4313 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW		 4314 /* All of these values are in units of 50MHz */
4315 dev_priv->rps.cur_freq = 0;
93ee2920 4316 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 4317 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 4318 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 4319 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
cee991cb
AG		 4320 if (IS_SKYLAKE(dev)) {
4321 /* Store the frequency values in 16.66 MHZ units, which is
4322 the natural hardware unit for SKL */
4323 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4324 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4325 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4326 }
3280e8b0
BW		 4327 /* hw_max = RP0 until we check for overclocking */
4328 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4329
93ee2920
TR		 4330 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4331 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4332 ret = sandybridge_pcode_read(dev_priv,
4333 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4334 &ddcc_status);
4335 if (0 == ret)
4336 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4337 clamp_t(u8,
4338 ((ddcc_status >> 8) & 0xff),
4339 dev_priv->rps.min_freq,
4340 dev_priv->rps.max_freq);
93ee2920
TR		 4341 }
4342
aed242ff
CW		 4343 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4344
3280e8b0
BW		 4345 /* Preserve min/max settings in case of re-init */
4346 if (dev_priv->rps.max_freq_softlimit == 0)
4347 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4348
93ee2920
TR		 4349 if (dev_priv->rps.min_freq_softlimit == 0) {
4350 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4351 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4352 max_t(int, dev_priv->rps.efficient_freq,
4353 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4354 else
4355 dev_priv->rps.min_freq_softlimit =
4356 dev_priv->rps.min_freq;
4357 }
3280e8b0
BW		 4358}
4359
b6fef0ef 4360/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4361static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4362{
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364
4365 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4366
ba1c554c
DL		 4367 gen6_init_rps_frequencies(dev);
4368
0beb059a
AG		 4369 /* Program defaults and thresholds for RPS*/
4370 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4371 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4372
4373 /* 1 second timeout*/
4374 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4375 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4376
b6fef0ef 4377 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4378
0beb059a
AG		 4379 /* Leaning on the below call to gen6_set_rps to program/setup the
4380 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4381 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4382 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4383 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4384
4385 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4386}
4387
4388static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4389{
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 struct intel_engine_cs *ring;
4392 uint32_t rc6_mask = 0;
4393 int unused;
4394
4395 /* 1a: Software RC state - RC0 */
4396 I915_WRITE(GEN6_RC_STATE, 0);
4397
4398 /* 1b: Get forcewake during program sequence. Although the driver
4399 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4400 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4401
4402 /* 2a: Disable RC states. */
4403 I915_WRITE(GEN6_RC_CONTROL, 0);
4404
4405 /* 2b: Program RC6 thresholds.*/
4406 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4407 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4408 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4409 for_each_ring(ring, dev_priv, unused)
4410 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4411 I915_WRITE(GEN6_RC_SLEEP, 0);
4412 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4413
38c23527
ZW		 4414 /* 2c: Program Coarse Power Gating Policies. */
4415 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4416 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4417
20e49366
ZW		 4418 /* 3a: Enable RC6 */
4419 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4420 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4421 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4422 "on" : "off");
4423 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4424 GEN6_RC_CTL_EI_MODE(1) |
4425 rc6_mask);
4426
cb07bae0
SK		 4427 /*
4428 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4429 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4430 */
a4104c55 4431 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
cb07bae0 4432 GEN9_MEDIA_PG_ENABLE : 0);
a4104c55 4433
38c23527 4434
59bad947 4435 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4436
4437}
4438
6edee7f3
BW		 4439static void gen8_enable_rps(struct drm_device *dev)
4440{
4441 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4442 struct intel_engine_cs *ring;
93ee2920 4443 uint32_t rc6_mask = 0;
6edee7f3
BW		 4444 int unused;
4445
4446 /* 1a: Software RC state - RC0 */
4447 I915_WRITE(GEN6_RC_STATE, 0);
4448
4449 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4450 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4451 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4452
4453 /* 2a: Disable RC states. */
4454 I915_WRITE(GEN6_RC_CONTROL, 0);
4455
93ee2920
TR		 4456 /* Initialize rps frequencies */
4457 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4458
4459 /* 2b: Program RC6 thresholds.*/
4460 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4461 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4462 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4463 for_each_ring(ring, dev_priv, unused)
4464 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4465 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4466 if (IS_BROADWELL(dev))
4467 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4468 else
4469 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4470
4471 /* 3: Enable RC6 */
4472 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4473 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4474 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4475 if (IS_BROADWELL(dev))
4476 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4477 GEN7_RC_CTL_TO_MODE |
4478 rc6_mask);
4479 else
4480 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4481 GEN6_RC_CTL_EI_MODE(1) |
4482 rc6_mask);
6edee7f3
BW		 4483
4484 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4485 I915_WRITE(GEN6_RPNSWREQ,
4486 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4487 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4488 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4489 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4490 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4491
4492 /* Docs recommend 900MHz, and 300 MHz respectively */
4493 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4494 dev_priv->rps.max_freq_softlimit << 24 |
4495 dev_priv->rps.min_freq_softlimit << 16);
4496
4497 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4498 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4499 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4500 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4501
4502 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4503
4504 /* 5: Enable RPS */
7526ed79
DV		 4505 I915_WRITE(GEN6_RP_CONTROL,
4506 GEN6_RP_MEDIA_TURBO |
4507 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4508 GEN6_RP_MEDIA_IS_GFX |
4509 GEN6_RP_ENABLE |
4510 GEN6_RP_UP_BUSY_AVG |
4511 GEN6_RP_DOWN_IDLE_AVG);
4512
4513 /* 6: Ring frequency + overclocking (our driver does this later */
4514
c7f3153a 4515 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4516 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4517
59bad947 4518 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4519}
4520
79f5b2c7 4521static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4522{
79f5b2c7 4523 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4524 struct intel_engine_cs *ring;
d060c169 4525 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4526 u32 gtfifodbg;
2b4e57bd 4527 int rc6_mode;
42c0526c 4528 int i, ret;
2b4e57bd 4529
4fc688ce 4530 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4531
2b4e57bd
ED		 4532 /* Here begins a magic sequence of register writes to enable
4533 * auto-downclocking.
4534 *
4535 * Perhaps there might be some value in exposing these to
4536 * userspace...
4537 */
4538 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4539
4540 /* Clear the DBG now so we don't confuse earlier errors */
4541 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4542 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4543 I915_WRITE(GTFIFODBG, gtfifodbg);
4544 }
4545
59bad947 4546 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4547
93ee2920
TR		 4548 /* Initialize rps frequencies */
4549 gen6_init_rps_frequencies(dev);
dd0a1aa1 4550
2b4e57bd
ED		 4551 /* disable the counters and set deterministic thresholds */
4552 I915_WRITE(GEN6_RC_CONTROL, 0);
4553
4554 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4555 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4556 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4557 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4558 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4559
b4519513
CW		 4560 for_each_ring(ring, dev_priv, i)
4561 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4562
4563 I915_WRITE(GEN6_RC_SLEEP, 0);
4564 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4565 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4566 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4567 else
4568 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4569 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4570 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4571
5a7dc92a 4572 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4573 rc6_mode = intel_enable_rc6(dev_priv->dev);
4574 if (rc6_mode & INTEL_RC6_ENABLE)
4575 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4576
5a7dc92a
ED		 4577 /* We don't use those on Haswell */
4578 if (!IS_HASWELL(dev)) {
4579 if (rc6_mode & INTEL_RC6p_ENABLE)
4580 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4581
5a7dc92a
ED		 4582 if (rc6_mode & INTEL_RC6pp_ENABLE)
4583 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4584 }
2b4e57bd 4585
dc39fff7 4586 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4587
4588 I915_WRITE(GEN6_RC_CONTROL,
4589 rc6_mask |
4590 GEN6_RC_CTL_EI_MODE(1) |
4591 GEN6_RC_CTL_HW_ENABLE);
4592
dd75fdc8
CW		 4593 /* Power down if completely idle for over 50ms */
4594 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4595 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4596
42c0526c 4597 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4598 if (ret)
42c0526c 4599 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4600
4601 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4602 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4603 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4604 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4605 (pcu_mbox & 0xff) * 50);
b39fb297 4606 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4607 }
4608
dd75fdc8 4609 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4610 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4611
31643d54
BW		 4612 rc6vids = 0;
4613 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4614 if (IS_GEN6(dev) && ret) {
4615 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4616 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4617 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4618 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4619 rc6vids &= 0xffff00;
4620 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4621 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4622 if (ret)
4623 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4624 }
4625
59bad947 4626 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4627}
4628
c2bc2fc5 4629static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4630{
79f5b2c7 4631 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4632 int min_freq = 15;
3ebecd07
CW		 4633 unsigned int gpu_freq;
4634 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4635 int scaling_factor = 180;
eda79642 4636 struct cpufreq_policy *policy;
2b4e57bd 4637
4fc688ce 4638 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4639
eda79642
BW		 4640 policy = cpufreq_cpu_get(0);
4641 if (policy) {
4642 max_ia_freq = policy->cpuinfo.max_freq;
4643 cpufreq_cpu_put(policy);
4644 } else {
4645 /*
4646 * Default to measured freq if none found, PCU will ensure we
4647 * don't go over
4648 */
2b4e57bd 4649 max_ia_freq = tsc_khz;
eda79642 4650 }
2b4e57bd
ED		 4651
4652 /* Convert from kHz to MHz */
4653 max_ia_freq /= 1000;
4654
153b4b95 4655 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4656 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4657 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4658
2b4e57bd
ED		 4659 /*
4660 * For each potential GPU frequency, load a ring frequency we'd like
4661 * to use for memory access. We do this by specifying the IA frequency
4662 * the PCU should use as a reference to determine the ring frequency.
4663 */
6985b352 4664 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4665 gpu_freq--) {
6985b352 4666 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW		 4667 unsigned int ia_freq = 0, ring_freq = 0;
4668
46c764d4
BW		 4669 if (INTEL_INFO(dev)->gen >= 8) {
4670 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4671 ring_freq = max(min_ring_freq, gpu_freq);
4672 } else if (IS_HASWELL(dev)) {
f6aca45c 4673 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4674 ring_freq = max(min_ring_freq, ring_freq);
4675 /* leave ia_freq as the default, chosen by cpufreq */
4676 } else {
4677 /* On older processors, there is no separate ring
4678 * clock domain, so in order to boost the bandwidth
4679 * of the ring, we need to upclock the CPU (ia_freq).
4680 *
4681 * For GPU frequencies less than 750MHz,
4682 * just use the lowest ring freq.
4683 */
4684 if (gpu_freq < min_freq)
4685 ia_freq = 800;
4686 else
4687 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4688 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4689 }
2b4e57bd 4690
42c0526c
BW		 4691 sandybridge_pcode_write(dev_priv,
4692 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4693 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4694 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4695 gpu_freq);
2b4e57bd 4696 }
2b4e57bd
ED		 4697}
4698
c2bc2fc5
ID		 4699void gen6_update_ring_freq(struct drm_device *dev)
4700{
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702
4703 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4704 return;
4705
4706 mutex_lock(&dev_priv->rps.hw_lock);
4707 __gen6_update_ring_freq(dev);
4708 mutex_unlock(&dev_priv->rps.hw_lock);
4709}
4710
03af2045 4711static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4712{
095acd5f 4713 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4714 u32 val, rp0;
4715
095acd5f
D		 4716 if (dev->pdev->revision >= 0x20) {
4717 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4718
095acd5f
D		 4719 switch (INTEL_INFO(dev)->eu_total) {
4720 case 8:
4721 /* (2 * 4) config */
4722 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4723 break;
4724 case 12:
4725 /* (2 * 6) config */
4726 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4727 break;
4728 case 16:
4729 /* (2 * 8) config */
4730 default:
4731 /* Setting (2 * 8) Min RP0 for any other combination */
4732 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4733 break;
4734 }
4735 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4736 } else {
4737 /* For pre-production hardware */
4738 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4739 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4740 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4741 }
2b6b3a09
D		 4742 return rp0;
4743}
4744
4745static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4746{
4747 u32 val, rpe;
4748
4749 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4750 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4751
4752 return rpe;
4753}
4754
7707df4a
D		 4755static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4756{
095acd5f 4757 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 4758 u32 val, rp1;
4759
095acd5f
D		 4760 if (dev->pdev->revision >= 0x20) {
4761 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4762 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4763 } else {
4764 /* For pre-production hardware */
4765 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4766 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4767 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4768 }
7707df4a
D		 4769 return rp1;
4770}
4771
03af2045 4772static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4773{
095acd5f 4774 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 4775 u32 val, rpn;
4776
095acd5f
D		 4777 if (dev->pdev->revision >= 0x20) {
4778 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4779 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4780 FB_GFX_FREQ_FUSE_MASK);
4781 } else { /* For pre-production hardware */
4782 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4783 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4784 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4785 }
4786
2b6b3a09
D		 4787 return rpn;
4788}
4789
f8f2b001
D		 4790static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4791{
4792 u32 val, rp1;
4793
4794 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4795
4796 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4797
4798 return rp1;
4799}
4800
03af2045 4801static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 4802{
4803 u32 val, rp0;
4804
64936258 4805 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4806
4807 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4808 /* Clamp to max */
4809 rp0 = min_t(u32, rp0, 0xea);
4810
4811 return rp0;
4812}
4813
4814static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4815{
4816 u32 val, rpe;
4817
64936258 4818 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4819 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4820 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4821 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4822
4823 return rpe;
4824}
4825
03af2045 4826static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4827{
64936258 4828 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4829}
4830
ae48434c
ID		 4831/* Check that the pctx buffer wasn't move under us. */
4832static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4833{
4834 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4835
4836 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4837 dev_priv->vlv_pctx->stolen->start);
4838}
4839
38807746
D		 4840
4841/* Check that the pcbr address is not empty. */
4842static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4843{
4844 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4845
4846 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4847}
4848
4849static void cherryview_setup_pctx(struct drm_device *dev)
4850{
4851 struct drm_i915_private *dev_priv = dev->dev_private;
4852 unsigned long pctx_paddr, paddr;
4853 struct i915_gtt *gtt = &dev_priv->gtt;
4854 u32 pcbr;
4855 int pctx_size = 32*1024;
4856
4857 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4858
4859 pcbr = I915_READ(VLV_PCBR);
4860 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4861 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 4862 paddr = (dev_priv->mm.stolen_base +
4863 (gtt->stolen_size - pctx_size));
4864
4865 pctx_paddr = (paddr & (~4095));
4866 I915_WRITE(VLV_PCBR, pctx_paddr);
4867 }
ce611ef8
VS		 4868
4869 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 4870}
4871
c9cddffc
JB		 4872static void valleyview_setup_pctx(struct drm_device *dev)
4873{
4874 struct drm_i915_private *dev_priv = dev->dev_private;
4875 struct drm_i915_gem_object *pctx;
4876 unsigned long pctx_paddr;
4877 u32 pcbr;
4878 int pctx_size = 24*1024;
4879
17b0c1f7
ID		 4880 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4881
c9cddffc
JB		 4882 pcbr = I915_READ(VLV_PCBR);
4883 if (pcbr) {
4884 /* BIOS set it up already, grab the pre-alloc'd space */
4885 int pcbr_offset;
4886
4887 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4888 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4889 pcbr_offset,
190d6cd5 4890 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4891 pctx_size);
4892 goto out;
4893 }
4894
ce611ef8
VS		 4895 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4896
c9cddffc
JB		 4897 /*
4898 * From the Gunit register HAS:
4899 * The Gfx driver is expected to program this register and ensure
4900 * proper allocation within Gfx stolen memory. For example, this
4901 * register should be programmed such than the PCBR range does not
4902 * overlap with other ranges, such as the frame buffer, protected
4903 * memory, or any other relevant ranges.
4904 */
4905 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4906 if (!pctx) {
4907 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4908 return;
4909 }
4910
4911 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4912 I915_WRITE(VLV_PCBR, pctx_paddr);
4913
4914out:
ce611ef8 4915 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 4916 dev_priv->vlv_pctx = pctx;
4917}
4918
ae48434c
ID		 4919static void valleyview_cleanup_pctx(struct drm_device *dev)
4920{
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922
4923 if (WARN_ON(!dev_priv->vlv_pctx))
4924 return;
4925
4926 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4927 dev_priv->vlv_pctx = NULL;
4928}
4929
4e80519e
ID		 4930static void valleyview_init_gt_powersave(struct drm_device *dev)
4931{
4932 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4933 u32 val;
4e80519e
ID		 4934
4935 valleyview_setup_pctx(dev);
4936
4937 mutex_lock(&dev_priv->rps.hw_lock);
4938
2bb25c17
VS		 4939 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4940 switch ((val >> 6) & 3) {
4941 case 0:
4942 case 1:
4943 dev_priv->mem_freq = 800;
4944 break;
4945 case 2:
4946 dev_priv->mem_freq = 1066;
4947 break;
4948 case 3:
4949 dev_priv->mem_freq = 1333;
4950 break;
4951 }
80b83b62 4952 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4953
4e80519e
ID		 4954 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4955 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4956 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4957 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 4958 dev_priv->rps.max_freq);
4959
4960 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4961 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4962 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 4963 dev_priv->rps.efficient_freq);
4964
f8f2b001
D		 4965 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4966 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4967 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 4968 dev_priv->rps.rp1_freq);
4969
4e80519e
ID		 4970 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4971 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4972 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 4973 dev_priv->rps.min_freq);
4974
aed242ff
CW		 4975 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4976
4e80519e
ID		 4977 /* Preserve min/max settings in case of re-init */
4978 if (dev_priv->rps.max_freq_softlimit == 0)
4979 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4980
4981 if (dev_priv->rps.min_freq_softlimit == 0)
4982 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4983
4984 mutex_unlock(&dev_priv->rps.hw_lock);
4985}
4986
38807746
D		 4987static void cherryview_init_gt_powersave(struct drm_device *dev)
4988{
2b6b3a09 4989 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4990 u32 val;
2b6b3a09 4991
38807746 4992 cherryview_setup_pctx(dev);
2b6b3a09
D		 4993
4994 mutex_lock(&dev_priv->rps.hw_lock);
4995
c6e8f39d
VS		 4996 mutex_lock(&dev_priv->dpio_lock);
4997 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
4998 mutex_unlock(&dev_priv->dpio_lock);
4999
2bb25c17
VS		 5000 switch ((val >> 2) & 0x7) {
5001 case 0:
5002 case 1:
5003 dev_priv->rps.cz_freq = 200;
5004 dev_priv->mem_freq = 1600;
5005 break;
5006 case 2:
5007 dev_priv->rps.cz_freq = 267;
5008 dev_priv->mem_freq = 1600;
5009 break;
5010 case 3:
5011 dev_priv->rps.cz_freq = 333;
5012 dev_priv->mem_freq = 2000;
5013 break;
5014 case 4:
5015 dev_priv->rps.cz_freq = 320;
5016 dev_priv->mem_freq = 1600;
5017 break;
5018 case 5:
5019 dev_priv->rps.cz_freq = 400;
5020 dev_priv->mem_freq = 1600;
5021 break;
5022 }
80b83b62 5023 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5024
2b6b3a09
D		 5025 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5026 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5027 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5028 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5029 dev_priv->rps.max_freq);
5030
5031 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5032 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5033 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5034 dev_priv->rps.efficient_freq);
5035
7707df4a
D		 5036 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5037 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5038 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5039 dev_priv->rps.rp1_freq);
5040
2b6b3a09
D		 5041 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
5042 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5043 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5044 dev_priv->rps.min_freq);
5045
1c14762d
VS		 5046 WARN_ONCE((dev_priv->rps.max_freq |
5047 dev_priv->rps.efficient_freq |
5048 dev_priv->rps.rp1_freq |
5049 dev_priv->rps.min_freq) & 1,
5050 "Odd GPU freq values\n");
5051
aed242ff
CW		 5052 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5053
2b6b3a09
D		 5054 /* Preserve min/max settings in case of re-init */
5055 if (dev_priv->rps.max_freq_softlimit == 0)
5056 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5057
5058 if (dev_priv->rps.min_freq_softlimit == 0)
5059 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5060
5061 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5062}
5063
4e80519e
ID		 5064static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5065{
5066 valleyview_cleanup_pctx(dev);
5067}
5068
38807746
D		 5069static void cherryview_enable_rps(struct drm_device *dev)
5070{
5071 struct drm_i915_private *dev_priv = dev->dev_private;
5072 struct intel_engine_cs *ring;
2b6b3a09 5073 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5074 int i;
5075
5076 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5077
5078 gtfifodbg = I915_READ(GTFIFODBG);
5079 if (gtfifodbg) {
5080 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5081 gtfifodbg);
5082 I915_WRITE(GTFIFODBG, gtfifodbg);
5083 }
5084
5085 cherryview_check_pctx(dev_priv);
5086
5087 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5088 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5089 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5090
160614a2
VS		 5091 /* Disable RC states. */
5092 I915_WRITE(GEN6_RC_CONTROL, 0);
5093
38807746
D		 5094 /* 2a: Program RC6 thresholds.*/
5095 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5096 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5097 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5098
5099 for_each_ring(ring, dev_priv, i)
5100 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5101 I915_WRITE(GEN6_RC_SLEEP, 0);
5102
f4f71c7d
D		 5103 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5104 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5105
5106 /* allows RC6 residency counter to work */
5107 I915_WRITE(VLV_COUNTER_CONTROL,
5108 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5109 VLV_MEDIA_RC6_COUNT_EN |
5110 VLV_RENDER_RC6_COUNT_EN));
5111
5112 /* For now we assume BIOS is allocating and populating the PCBR */
5113 pcbr = I915_READ(VLV_PCBR);
5114
38807746
D		 5115 /* 3: Enable RC6 */
5116 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5117 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5118 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5119
5120 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5121
2b6b3a09 5122 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5123 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5124 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5125 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5126 I915_WRITE(GEN6_RP_UP_EI, 66000);
5127 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5128
5129 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5130
5131 /* 5: Enable RPS */
5132 I915_WRITE(GEN6_RP_CONTROL,
5133 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5134 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5135 GEN6_RP_ENABLE |
5136 GEN6_RP_UP_BUSY_AVG |
5137 GEN6_RP_DOWN_IDLE_AVG);
5138
3ef62342
D		 5139 /* Setting Fixed Bias */
5140 val = VLV_OVERRIDE_EN |
5141 VLV_SOC_TDP_EN |
5142 CHV_BIAS_CPU_50_SOC_50;
5143 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5144
2b6b3a09
D		 5145 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5146
8d40c3ae
VS		 5147 /* RPS code assumes GPLL is used */
5148 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5149
c8e9627d 5150 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5151 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5152
5153 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5154 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5155 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5156 dev_priv->rps.cur_freq);
5157
5158 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5159 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5160 dev_priv->rps.efficient_freq);
5161
5162 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5163
59bad947 5164 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5165}
5166
0a073b84
JB		 5167static void valleyview_enable_rps(struct drm_device *dev)
5168{
5169 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5170 struct intel_engine_cs *ring;
2a5913a8 5171 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5172 int i;
5173
5174 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5175
ae48434c
ID		 5176 valleyview_check_pctx(dev_priv);
5177
0a073b84 5178 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5179 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5180 gtfifodbg);
0a073b84
JB		 5181 I915_WRITE(GTFIFODBG, gtfifodbg);
5182 }
5183
c8d9a590 5184 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5185 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5186
160614a2
VS		 5187 /* Disable RC states. */
5188 I915_WRITE(GEN6_RC_CONTROL, 0);
5189
cad725fe 5190 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5191 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5192 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5193 I915_WRITE(GEN6_RP_UP_EI, 66000);
5194 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5195
5196 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5197
5198 I915_WRITE(GEN6_RP_CONTROL,
5199 GEN6_RP_MEDIA_TURBO |
5200 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5201 GEN6_RP_MEDIA_IS_GFX |
5202 GEN6_RP_ENABLE |
5203 GEN6_RP_UP_BUSY_AVG |
5204 GEN6_RP_DOWN_IDLE_CONT);
5205
5206 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5207 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5208 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5209
5210 for_each_ring(ring, dev_priv, i)
5211 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5212
2f0aa304 5213 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5214
5215 /* allows RC6 residency counter to work */
49798eb2 5216 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5217 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5218 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5219 VLV_MEDIA_RC6_COUNT_EN |
5220 VLV_RENDER_RC6_COUNT_EN));
31685c25 5221
a2b23fe0 5222 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5223 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5224
5225 intel_print_rc6_info(dev, rc6_mode);
5226
a2b23fe0 5227 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5228
3ef62342
D		 5229 /* Setting Fixed Bias */
5230 val = VLV_OVERRIDE_EN |
5231 VLV_SOC_TDP_EN |
5232 VLV_BIAS_CPU_125_SOC_875;
5233 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5234
64936258 5235 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5236
8d40c3ae
VS		 5237 /* RPS code assumes GPLL is used */
5238 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5239
c8e9627d 5240 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5241 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5242
b39fb297 5243 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5244 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5245 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5246 dev_priv->rps.cur_freq);
0a073b84 5247
73008b98 5248 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5249 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5250 dev_priv->rps.efficient_freq);
0a073b84 5251
b39fb297 5252 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5253
59bad947 5254 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5255}
5256
dde18883
ED		 5257static unsigned long intel_pxfreq(u32 vidfreq)
5258{
5259 unsigned long freq;
5260 int div = (vidfreq & 0x3f0000) >> 16;
5261 int post = (vidfreq & 0x3000) >> 12;
5262 int pre = (vidfreq & 0x7);
5263
5264 if (!pre)
5265 return 0;
5266
5267 freq = ((div * 133333) / ((1<<post) * pre));
5268
5269 return freq;
5270}
5271
eb48eb00
DV		 5272static const struct cparams {
5273 u16 i;
5274 u16 t;
5275 u16 m;
5276 u16 c;
5277} cparams[] = {
5278 { 1, 1333, 301, 28664 },
5279 { 1, 1066, 294, 24460 },
5280 { 1, 800, 294, 25192 },
5281 { 0, 1333, 276, 27605 },
5282 { 0, 1066, 276, 27605 },
5283 { 0, 800, 231, 23784 },
5284};
5285
f531dcb2 5286static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5287{
5288 u64 total_count, diff, ret;
5289 u32 count1, count2, count3, m = 0, c = 0;
5290 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5291 int i;
5292
02d71956
DV		 5293 assert_spin_locked(&mchdev_lock);
5294
20e4d407 5295 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5296
5297 /* Prevent division-by-zero if we are asking too fast.
5298 * Also, we don't get interesting results if we are polling
5299 * faster than once in 10ms, so just return the saved value
5300 * in such cases.
5301 */
5302 if (diff1 <= 10)
20e4d407 5303 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5304
5305 count1 = I915_READ(DMIEC);
5306 count2 = I915_READ(DDREC);
5307 count3 = I915_READ(CSIEC);
5308
5309 total_count = count1 + count2 + count3;
5310
5311 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5312 if (total_count < dev_priv->ips.last_count1) {
5313 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5314 diff += total_count;
5315 } else {
20e4d407 5316 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5317 }
5318
5319 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5320 if (cparams[i].i == dev_priv->ips.c_m &&
5321 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5322 m = cparams[i].m;
5323 c = cparams[i].c;
5324 break;
5325 }
5326 }
5327
5328 diff = div_u64(diff, diff1);
5329 ret = ((m * diff) + c);
5330 ret = div_u64(ret, 10);
5331
20e4d407
DV		 5332 dev_priv->ips.last_count1 = total_count;
5333 dev_priv->ips.last_time1 = now;
eb48eb00 5334
20e4d407 5335 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5336
5337 return ret;
5338}
5339
f531dcb2
CW		 5340unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5341{
3d13ef2e 5342 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5343 unsigned long val;
5344
3d13ef2e 5345 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5346 return 0;
5347
5348 spin_lock_irq(&mchdev_lock);
5349
5350 val = __i915_chipset_val(dev_priv);
5351
5352 spin_unlock_irq(&mchdev_lock);
5353
5354 return val;
5355}
5356
eb48eb00
DV		 5357unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5358{
5359 unsigned long m, x, b;
5360 u32 tsfs;
5361
5362 tsfs = I915_READ(TSFS);
5363
5364 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5365 x = I915_READ8(TR1);
5366
5367 b = tsfs & TSFS_INTR_MASK;
5368
5369 return ((m * x) / 127) - b;
5370}
5371
d972d6ee
MK		 5372static int _pxvid_to_vd(u8 pxvid)
5373{
5374 if (pxvid == 0)
5375 return 0;
5376
5377 if (pxvid >= 8 && pxvid < 31)
5378 pxvid = 31;
5379
5380 return (pxvid + 2) * 125;
5381}
5382
5383static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5384{
3d13ef2e 5385 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5386 const int vd = _pxvid_to_vd(pxvid);
5387 const int vm = vd - 1125;
5388
3d13ef2e 5389 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5390 return vm > 0 ? vm : 0;
5391
5392 return vd;
eb48eb00
DV		 5393}
5394
02d71956 5395static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5396{
5ed0bdf2 5397 u64 now, diff, diffms;
eb48eb00
DV		 5398 u32 count;
5399
02d71956 5400 assert_spin_locked(&mchdev_lock);
eb48eb00 5401
5ed0bdf2
TG		 5402 now = ktime_get_raw_ns();
5403 diffms = now - dev_priv->ips.last_time2;
5404 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5405
5406 /* Don't divide by 0 */
eb48eb00
DV		 5407 if (!diffms)
5408 return;
5409
5410 count = I915_READ(GFXEC);
5411
20e4d407
DV		 5412 if (count < dev_priv->ips.last_count2) {
5413 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5414 diff += count;
5415 } else {
20e4d407 5416 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5417 }
5418
20e4d407
DV		 5419 dev_priv->ips.last_count2 = count;
5420 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5421
5422 /* More magic constants... */
5423 diff = diff * 1181;
5424 diff = div_u64(diff, diffms * 10);
20e4d407 5425 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5426}
5427
02d71956
DV		 5428void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5429{
3d13ef2e
DL		 5430 struct drm_device *dev = dev_priv->dev;
5431
5432 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5433 return;
5434
9270388e 5435 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5436
5437 __i915_update_gfx_val(dev_priv);
5438
9270388e 5439 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5440}
5441
f531dcb2 5442static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5443{
5444 unsigned long t, corr, state1, corr2, state2;
5445 u32 pxvid, ext_v;
5446
02d71956
DV		 5447 assert_spin_locked(&mchdev_lock);
5448
b39fb297 5449 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5450 pxvid = (pxvid >> 24) & 0x7f;
5451 ext_v = pvid_to_extvid(dev_priv, pxvid);
5452
5453 state1 = ext_v;
5454
5455 t = i915_mch_val(dev_priv);
5456
5457 /* Revel in the empirically derived constants */
5458
5459 /* Correction factor in 1/100000 units */
5460 if (t > 80)
5461 corr = ((t * 2349) + 135940);
5462 else if (t >= 50)
5463 corr = ((t * 964) + 29317);
5464 else /* < 50 */
5465 corr = ((t * 301) + 1004);
5466
5467 corr = corr * ((150142 * state1) / 10000 - 78642);
5468 corr /= 100000;
20e4d407 5469 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5470
5471 state2 = (corr2 * state1) / 10000;
5472 state2 /= 100; /* convert to mW */
5473
02d71956 5474 __i915_update_gfx_val(dev_priv);
eb48eb00 5475
20e4d407 5476 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5477}
5478
f531dcb2
CW		 5479unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5480{
3d13ef2e 5481 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5482 unsigned long val;
5483
3d13ef2e 5484 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5485 return 0;
5486
5487 spin_lock_irq(&mchdev_lock);
5488
5489 val = __i915_gfx_val(dev_priv);
5490
5491 spin_unlock_irq(&mchdev_lock);
5492
5493 return val;
5494}
5495
eb48eb00
DV		 5496/**
5497 * i915_read_mch_val - return value for IPS use
5498 *
5499 * Calculate and return a value for the IPS driver to use when deciding whether
5500 * we have thermal and power headroom to increase CPU or GPU power budget.
5501 */
5502unsigned long i915_read_mch_val(void)
5503{
5504 struct drm_i915_private *dev_priv;
5505 unsigned long chipset_val, graphics_val, ret = 0;
5506
9270388e 5507 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5508 if (!i915_mch_dev)
5509 goto out_unlock;
5510 dev_priv = i915_mch_dev;
5511
f531dcb2
CW		 5512 chipset_val = __i915_chipset_val(dev_priv);
5513 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5514
5515 ret = chipset_val + graphics_val;
5516
5517out_unlock:
9270388e 5518 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5519
5520 return ret;
5521}
5522EXPORT_SYMBOL_GPL(i915_read_mch_val);
5523
5524/**
5525 * i915_gpu_raise - raise GPU frequency limit
5526 *
5527 * Raise the limit; IPS indicates we have thermal headroom.
5528 */
5529bool i915_gpu_raise(void)
5530{
5531 struct drm_i915_private *dev_priv;
5532 bool ret = true;
5533
9270388e 5534 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5535 if (!i915_mch_dev) {
5536 ret = false;
5537 goto out_unlock;
5538 }
5539 dev_priv = i915_mch_dev;
5540
20e4d407
DV		 5541 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5542 dev_priv->ips.max_delay--;
eb48eb00
DV		 5543
5544out_unlock:
9270388e 5545 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5546
5547 return ret;
5548}
5549EXPORT_SYMBOL_GPL(i915_gpu_raise);
5550
5551/**
5552 * i915_gpu_lower - lower GPU frequency limit
5553 *
5554 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5555 * frequency maximum.
5556 */
5557bool i915_gpu_lower(void)
5558{
5559 struct drm_i915_private *dev_priv;
5560 bool ret = true;
5561
9270388e 5562 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5563 if (!i915_mch_dev) {
5564 ret = false;
5565 goto out_unlock;
5566 }
5567 dev_priv = i915_mch_dev;
5568
20e4d407
DV		 5569 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5570 dev_priv->ips.max_delay++;
eb48eb00
DV		 5571
5572out_unlock:
9270388e 5573 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5574
5575 return ret;
5576}
5577EXPORT_SYMBOL_GPL(i915_gpu_lower);
5578
5579/**
5580 * i915_gpu_busy - indicate GPU business to IPS
5581 *
5582 * Tell the IPS driver whether or not the GPU is busy.
5583 */
5584bool i915_gpu_busy(void)
5585{
5586 struct drm_i915_private *dev_priv;
a4872ba6 5587 struct intel_engine_cs *ring;
eb48eb00 5588 bool ret = false;
f047e395 5589 int i;
eb48eb00 5590
9270388e 5591 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5592 if (!i915_mch_dev)
5593 goto out_unlock;
5594 dev_priv = i915_mch_dev;
5595
f047e395
CW		 5596 for_each_ring(ring, dev_priv, i)
5597 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5598
5599out_unlock:
9270388e 5600 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5601
5602 return ret;
5603}
5604EXPORT_SYMBOL_GPL(i915_gpu_busy);
5605
5606/**
5607 * i915_gpu_turbo_disable - disable graphics turbo
5608 *
5609 * Disable graphics turbo by resetting the max frequency and setting the
5610 * current frequency to the default.
5611 */
5612bool i915_gpu_turbo_disable(void)
5613{
5614 struct drm_i915_private *dev_priv;
5615 bool ret = true;
5616
9270388e 5617 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5618 if (!i915_mch_dev) {
5619 ret = false;
5620 goto out_unlock;
5621 }
5622 dev_priv = i915_mch_dev;
5623
20e4d407 5624 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5625
20e4d407 5626 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5627 ret = false;
5628
5629out_unlock:
9270388e 5630 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5631
5632 return ret;
5633}
5634EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5635
5636/**
5637 * Tells the intel_ips driver that the i915 driver is now loaded, if
5638 * IPS got loaded first.
5639 *
5640 * This awkward dance is so that neither module has to depend on the
5641 * other in order for IPS to do the appropriate communication of
5642 * GPU turbo limits to i915.
5643 */
5644static void
5645ips_ping_for_i915_load(void)
5646{
5647 void (*link)(void);
5648
5649 link = symbol_get(ips_link_to_i915_driver);
5650 if (link) {
5651 link();
5652 symbol_put(ips_link_to_i915_driver);
5653 }
5654}
5655
5656void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5657{
02d71956
DV		 5658 /* We only register the i915 ips part with intel-ips once everything is
5659 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5660 spin_lock_irq(&mchdev_lock);
eb48eb00 5661 i915_mch_dev = dev_priv;
9270388e 5662 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5663
5664 ips_ping_for_i915_load();
5665}
5666
5667void intel_gpu_ips_teardown(void)
5668{
9270388e 5669 spin_lock_irq(&mchdev_lock);
eb48eb00 5670 i915_mch_dev = NULL;
9270388e 5671 spin_unlock_irq(&mchdev_lock);
eb48eb00 5672}
76c3552f 5673
8090c6b9 5674static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5675{
5676 struct drm_i915_private *dev_priv = dev->dev_private;
5677 u32 lcfuse;
5678 u8 pxw[16];
5679 int i;
5680
5681 /* Disable to program */
5682 I915_WRITE(ECR, 0);
5683 POSTING_READ(ECR);
5684
5685 /* Program energy weights for various events */
5686 I915_WRITE(SDEW, 0x15040d00);
5687 I915_WRITE(CSIEW0, 0x007f0000);
5688 I915_WRITE(CSIEW1, 0x1e220004);
5689 I915_WRITE(CSIEW2, 0x04000004);
5690
5691 for (i = 0; i < 5; i++)
5692 I915_WRITE(PEW + (i * 4), 0);
5693 for (i = 0; i < 3; i++)
5694 I915_WRITE(DEW + (i * 4), 0);
5695
5696 /* Program P-state weights to account for frequency power adjustment */
5697 for (i = 0; i < 16; i++) {
5698 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5699 unsigned long freq = intel_pxfreq(pxvidfreq);
5700 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5701 PXVFREQ_PX_SHIFT;
5702 unsigned long val;
5703
5704 val = vid * vid;
5705 val *= (freq / 1000);
5706 val *= 255;
5707 val /= (127*127*900);
5708 if (val > 0xff)
5709 DRM_ERROR("bad pxval: %ld\n", val);
5710 pxw[i] = val;
5711 }
5712 /* Render standby states get 0 weight */
5713 pxw[14] = 0;
5714 pxw[15] = 0;
5715
5716 for (i = 0; i < 4; i++) {
5717 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5718 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5719 I915_WRITE(PXW + (i * 4), val);
5720 }
5721
5722 /* Adjust magic regs to magic values (more experimental results) */
5723 I915_WRITE(OGW0, 0);
5724 I915_WRITE(OGW1, 0);
5725 I915_WRITE(EG0, 0x00007f00);
5726 I915_WRITE(EG1, 0x0000000e);
5727 I915_WRITE(EG2, 0x000e0000);
5728 I915_WRITE(EG3, 0x68000300);
5729 I915_WRITE(EG4, 0x42000000);
5730 I915_WRITE(EG5, 0x00140031);
5731 I915_WRITE(EG6, 0);
5732 I915_WRITE(EG7, 0);
5733
5734 for (i = 0; i < 8; i++)
5735 I915_WRITE(PXWL + (i * 4), 0);
5736
5737 /* Enable PMON + select events */
5738 I915_WRITE(ECR, 0x80000019);
5739
5740 lcfuse = I915_READ(LCFUSE02);
5741
20e4d407 5742 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 5743}
5744
ae48434c
ID		 5745void intel_init_gt_powersave(struct drm_device *dev)
5746{
e6069ca8
ID		 5747 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5748
38807746
D		 5749 if (IS_CHERRYVIEW(dev))
5750 cherryview_init_gt_powersave(dev);
5751 else if (IS_VALLEYVIEW(dev))
4e80519e 5752 valleyview_init_gt_powersave(dev);
ae48434c
ID		 5753}
5754
5755void intel_cleanup_gt_powersave(struct drm_device *dev)
5756{
38807746
D		 5757 if (IS_CHERRYVIEW(dev))
5758 return;
5759 else if (IS_VALLEYVIEW(dev))
4e80519e 5760 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 5761}
5762
dbea3cea
ID		 5763static void gen6_suspend_rps(struct drm_device *dev)
5764{
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766
5767 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5768
4c2a8897 5769 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 5770}
5771
156c7ca0
JB		 5772/**
5773 * intel_suspend_gt_powersave - suspend PM work and helper threads
5774 * @dev: drm device
5775 *
5776 * We don't want to disable RC6 or other features here, we just want
5777 * to make sure any work we've queued has finished and won't bother
5778 * us while we're suspended.
5779 */
5780void intel_suspend_gt_powersave(struct drm_device *dev)
5781{
5782 struct drm_i915_private *dev_priv = dev->dev_private;
5783
d4d70aa5
ID		 5784 if (INTEL_INFO(dev)->gen < 6)
5785 return;
5786
dbea3cea 5787 gen6_suspend_rps(dev);
b47adc17
D		 5788
5789 /* Force GPU to min freq during suspend */
5790 gen6_rps_idle(dev_priv);
156c7ca0
JB		 5791}
5792
8090c6b9
DV		 5793void intel_disable_gt_powersave(struct drm_device *dev)
5794{
1a01ab3b
JB		 5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796
930ebb46 5797 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5798 ironlake_disable_drps(dev);
38807746 5799 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5800 intel_suspend_gt_powersave(dev);
e494837a 5801
4fc688ce 5802 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 5803 if (INTEL_INFO(dev)->gen >= 9)
5804 gen9_disable_rps(dev);
5805 else if (IS_CHERRYVIEW(dev))
38807746
D		 5806 cherryview_disable_rps(dev);
5807 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 5808 valleyview_disable_rps(dev);
5809 else
5810 gen6_disable_rps(dev);
e534770a 5811
c0951f0c 5812 dev_priv->rps.enabled = false;
4fc688ce 5813 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5814 }
8090c6b9
DV		 5815}
5816
1a01ab3b
JB		 5817static void intel_gen6_powersave_work(struct work_struct *work)
5818{
5819 struct drm_i915_private *dev_priv =
5820 container_of(work, struct drm_i915_private,
5821 rps.delayed_resume_work.work);
5822 struct drm_device *dev = dev_priv->dev;
5823
4fc688ce 5824 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5825
4c2a8897 5826 gen6_reset_rps_interrupts(dev);
3cc134e3 5827
38807746
D		 5828 if (IS_CHERRYVIEW(dev)) {
5829 cherryview_enable_rps(dev);
5830 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5831 valleyview_enable_rps(dev);
20e49366 5832 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5833 gen9_enable_rc6(dev);
20e49366 5834 gen9_enable_rps(dev);
b6fef0ef 5835 __gen6_update_ring_freq(dev);
6edee7f3
BW		 5836 } else if (IS_BROADWELL(dev)) {
5837 gen8_enable_rps(dev);
c2bc2fc5 5838 __gen6_update_ring_freq(dev);
0a073b84
JB		 5839 } else {
5840 gen6_enable_rps(dev);
c2bc2fc5 5841 __gen6_update_ring_freq(dev);
0a073b84 5842 }
aed242ff
CW		 5843
5844 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5845 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5846
5847 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5848 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5849
c0951f0c 5850 dev_priv->rps.enabled = true;
3cc134e3 5851
4c2a8897 5852 gen6_enable_rps_interrupts(dev);
3cc134e3 5853
4fc688ce 5854 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 5855
5856 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 5857}
5858
8090c6b9
DV		 5859void intel_enable_gt_powersave(struct drm_device *dev)
5860{
1a01ab3b
JB		 5861 struct drm_i915_private *dev_priv = dev->dev_private;
5862
f61018b1
YZ		 5863 /* Powersaving is controlled by the host when inside a VM */
5864 if (intel_vgpu_active(dev))
5865 return;
5866
8090c6b9 5867 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5868 mutex_lock(&dev->struct_mutex);
8090c6b9 5869 ironlake_enable_drps(dev);
8090c6b9 5870 intel_init_emon(dev);
dc1d0136 5871 mutex_unlock(&dev->struct_mutex);
38807746 5872 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 5873 /*
5874 * PCU communication is slow and this doesn't need to be
5875 * done at any specific time, so do this out of our fast path
5876 * to make resume and init faster.
c6df39b5
ID		 5877 *
5878 * We depend on the HW RC6 power context save/restore
5879 * mechanism when entering D3 through runtime PM suspend. So
5880 * disable RPM until RPS/RC6 is properly setup. We can only
5881 * get here via the driver load/system resume/runtime resume
5882 * paths, so the _noresume version is enough (and in case of
5883 * runtime resume it's necessary).
1a01ab3b 5884 */
c6df39b5
ID		 5885 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5886 round_jiffies_up_relative(HZ)))
5887 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 5888 }
5889}
5890
c6df39b5
ID		 5891void intel_reset_gt_powersave(struct drm_device *dev)
5892{
5893 struct drm_i915_private *dev_priv = dev->dev_private;
5894
dbea3cea
ID		 5895 if (INTEL_INFO(dev)->gen < 6)
5896 return;
5897
5898 gen6_suspend_rps(dev);
c6df39b5 5899 dev_priv->rps.enabled = false;
c6df39b5
ID		 5900}
5901
3107bd48
DV		 5902static void ibx_init_clock_gating(struct drm_device *dev)
5903{
5904 struct drm_i915_private *dev_priv = dev->dev_private;
5905
5906 /*
5907 * On Ibex Peak and Cougar Point, we need to disable clock
5908 * gating for the panel power sequencer or it will fail to
5909 * start up when no ports are active.
5910 */
5911 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5912}
5913
0e088b8f
VS		 5914static void g4x_disable_trickle_feed(struct drm_device *dev)
5915{
5916 struct drm_i915_private *dev_priv = dev->dev_private;
5917 int pipe;
5918
055e393f 5919 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 5920 I915_WRITE(DSPCNTR(pipe),
5921 I915_READ(DSPCNTR(pipe)) |
5922 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5923 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5924 }
5925}
5926
017636cc
VS		 5927static void ilk_init_lp_watermarks(struct drm_device *dev)
5928{
5929 struct drm_i915_private *dev_priv = dev->dev_private;
5930
5931 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5932 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5933 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5934
5935 /*
5936 * Don't touch WM1S_LP_EN here.
5937 * Doing so could cause underruns.
5938 */
5939}
5940
1fa61106 5941static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5942{
5943 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5944 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5945
f1e8fa56
DL		 5946 /*
5947 * Required for FBC
5948 * WaFbcDisableDpfcClockGating:ilk
5949 */
4d47e4f5
DL		 5950 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5951 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5952 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5953
5954 I915_WRITE(PCH_3DCGDIS0,
5955 MARIUNIT_CLOCK_GATE_DISABLE |
5956 SVSMUNIT_CLOCK_GATE_DISABLE);
5957 I915_WRITE(PCH_3DCGDIS1,
5958 VFMUNIT_CLOCK_GATE_DISABLE);
5959
6f1d69b0
ED		 5960 /*
5961 * According to the spec the following bits should be set in
5962 * order to enable memory self-refresh
5963 * The bit 22/21 of 0x42004
5964 * The bit 5 of 0x42020
5965 * The bit 15 of 0x45000
5966 */
5967 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5968 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5969 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5970 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5971 I915_WRITE(DISP_ARB_CTL,
5972 (I915_READ(DISP_ARB_CTL) |
5973 DISP_FBC_WM_DIS));
017636cc
VS		 5974
5975 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 5976
5977 /*
5978 * Based on the document from hardware guys the following bits
5979 * should be set unconditionally in order to enable FBC.
5980 * The bit 22 of 0x42000
5981 * The bit 22 of 0x42004
5982 * The bit 7,8,9 of 0x42020.
5983 */
5984 if (IS_IRONLAKE_M(dev)) {
4bb35334 5985 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5986 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5987 I915_READ(ILK_DISPLAY_CHICKEN1) |
5988 ILK_FBCQ_DIS);
5989 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5990 I915_READ(ILK_DISPLAY_CHICKEN2) |
5991 ILK_DPARB_GATE);
6f1d69b0
ED		 5992 }
5993
4d47e4f5
DL		 5994 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5995
6f1d69b0
ED		 5996 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5997 I915_READ(ILK_DISPLAY_CHICKEN2) |
5998 ILK_ELPIN_409_SELECT);
5999 I915_WRITE(_3D_CHICKEN2,
6000 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6001 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6002
ecdb4eb7 6003 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6004 I915_WRITE(CACHE_MODE_0,
6005 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6006
4e04632e
AG		 6007 /* WaDisable_RenderCache_OperationalFlush:ilk */
6008 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6009
0e088b8f 6010 g4x_disable_trickle_feed(dev);
bdad2b2f 6011
3107bd48
DV		 6012 ibx_init_clock_gating(dev);
6013}
6014
6015static void cpt_init_clock_gating(struct drm_device *dev)
6016{
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 int pipe;
3f704fa2 6019 uint32_t val;
3107bd48
DV		 6020
6021 /*
6022 * On Ibex Peak and Cougar Point, we need to disable clock
6023 * gating for the panel power sequencer or it will fail to
6024 * start up when no ports are active.
6025 */
cd664078
JB		 6026 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6027 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6028 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6029 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6030 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6031 /* The below fixes the weird display corruption, a few pixels shifted
6032 * downward, on (only) LVDS of some HP laptops with IVY.
6033 */
055e393f 6034 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6035 val = I915_READ(TRANS_CHICKEN2(pipe));
6036 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6037 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6038 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6039 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6040 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6041 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6042 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6043 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6044 }
3107bd48 6045 /* WADP0ClockGatingDisable */
055e393f 6046 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6047 I915_WRITE(TRANS_CHICKEN1(pipe),
6048 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6049 }
6f1d69b0
ED		 6050}
6051
1d7aaa0c
DV		 6052static void gen6_check_mch_setup(struct drm_device *dev)
6053{
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055 uint32_t tmp;
6056
6057 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6058 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6059 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6060 tmp);
1d7aaa0c
DV		 6061}
6062
1fa61106 6063static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6064{
6065 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6066 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6067
231e54f6 6068 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6069
6070 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6071 I915_READ(ILK_DISPLAY_CHICKEN2) |
6072 ILK_ELPIN_409_SELECT);
6073
ecdb4eb7 6074 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6075 I915_WRITE(_3D_CHICKEN,
6076 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6077
4e04632e
AG		 6078 /* WaDisable_RenderCache_OperationalFlush:snb */
6079 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6080
8d85d272
VS		 6081 /*
6082 * BSpec recoomends 8x4 when MSAA is used,
6083 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6084 *
6085 * Note that PS/WM thread counts depend on the WIZ hashing
6086 * disable bit, which we don't touch here, but it's good
6087 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6088 */
6089 I915_WRITE(GEN6_GT_MODE,
98533251 6090 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6091
017636cc 6092 ilk_init_lp_watermarks(dev);
6f1d69b0 6093
6f1d69b0 6094 I915_WRITE(CACHE_MODE_0,
50743298 6095 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6096
6097 I915_WRITE(GEN6_UCGCTL1,
6098 I915_READ(GEN6_UCGCTL1) |
6099 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6100 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6101
6102 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6103 * gating disable must be set. Failure to set it results in
6104 * flickering pixels due to Z write ordering failures after
6105 * some amount of runtime in the Mesa "fire" demo, and Unigine
6106 * Sanctuary and Tropics, and apparently anything else with
6107 * alpha test or pixel discard.
6108 *
6109 * According to the spec, bit 11 (RCCUNIT) must also be set,
6110 * but we didn't debug actual testcases to find it out.
0f846f81 6111 *
ef59318c
VS		 6112 * WaDisableRCCUnitClockGating:snb
6113 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6114 */
6115 I915_WRITE(GEN6_UCGCTL2,
6116 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6117 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6118
5eb146dd 6119 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6120 I915_WRITE(_3D_CHICKEN3,
6121 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6122
e927ecde
VS		 6123 /*
6124 * Bspec says:
6125 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6126 * 3DSTATE_SF number of SF output attributes is more than 16."
6127 */
6128 I915_WRITE(_3D_CHICKEN3,
6129 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6130
6f1d69b0
ED		 6131 /*
6132 * According to the spec the following bits should be
6133 * set in order to enable memory self-refresh and fbc:
6134 * The bit21 and bit22 of 0x42000
6135 * The bit21 and bit22 of 0x42004
6136 * The bit5 and bit7 of 0x42020
6137 * The bit14 of 0x70180
6138 * The bit14 of 0x71180
4bb35334
DL		 6139 *
6140 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6141 */
6142 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6143 I915_READ(ILK_DISPLAY_CHICKEN1) |
6144 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6145 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6146 I915_READ(ILK_DISPLAY_CHICKEN2) |
6147 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6148 I915_WRITE(ILK_DSPCLK_GATE_D,
6149 I915_READ(ILK_DSPCLK_GATE_D) |
6150 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6151 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6152
0e088b8f 6153 g4x_disable_trickle_feed(dev);
f8f2ac9a 6154
3107bd48 6155 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6156
6157 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6158}
6159
6160static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6161{
6162 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6163
3aad9059 6164 /*
46680e0a 6165 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6166 *
6167 * This actually overrides the dispatch
6168 * mode for all thread types.
6169 */
6f1d69b0
ED		 6170 reg &= ~GEN7_FF_SCHED_MASK;
6171 reg |= GEN7_FF_TS_SCHED_HW;
6172 reg |= GEN7_FF_VS_SCHED_HW;
6173 reg |= GEN7_FF_DS_SCHED_HW;
6174
6175 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6176}
6177
17a303ec
PZ		 6178static void lpt_init_clock_gating(struct drm_device *dev)
6179{
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181
6182 /*
6183 * TODO: this bit should only be enabled when really needed, then
6184 * disabled when not needed anymore in order to save power.
6185 */
6186 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6187 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6188 I915_READ(SOUTH_DSPCLK_GATE_D) |
6189 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6190
6191 /* WADPOClockGatingDisable:hsw */
6192 I915_WRITE(_TRANSA_CHICKEN1,
6193 I915_READ(_TRANSA_CHICKEN1) |
6194 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6195}
6196
7d708ee4
ID		 6197static void lpt_suspend_hw(struct drm_device *dev)
6198{
6199 struct drm_i915_private *dev_priv = dev->dev_private;
6200
6201 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6202 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6203
6204 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6205 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6206 }
6207}
6208
47c2bd97 6209static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6210{
6211 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6212 enum pipe pipe;
1020a5c2
BW		 6213
6214 I915_WRITE(WM3_LP_ILK, 0);
6215 I915_WRITE(WM2_LP_ILK, 0);
6216 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd 6217
ab57fff1 6218 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6219 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6220
ab57fff1 6221 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6222 I915_WRITE(CHICKEN_PAR1_1,
6223 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6224
ab57fff1 6225 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6226 for_each_pipe(dev_priv, pipe) {
07d27e20 6227 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6228 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6229 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6230 }
63801f21 6231
ab57fff1
BW		 6232 /* WaVSRefCountFullforceMissDisable:bdw */
6233 /* WaDSRefCountFullforceMissDisable:bdw */
6234 I915_WRITE(GEN7_FF_THREAD_MODE,
6235 I915_READ(GEN7_FF_THREAD_MODE) &
6236 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6237
295e8bb7
VS		 6238 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6239 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6240
6241 /* WaDisableSDEUnitClockGating:bdw */
6242 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6243 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6244
89d6b2b8 6245 lpt_init_clock_gating(dev);
1020a5c2
BW		 6246}
6247
cad2a2d7
ED		 6248static void haswell_init_clock_gating(struct drm_device *dev)
6249{
6250 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6251
017636cc 6252 ilk_init_lp_watermarks(dev);
cad2a2d7 6253
f3fc4884
FJ		 6254 /* L3 caching of data atomics doesn't work -- disable it. */
6255 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6256 I915_WRITE(HSW_ROW_CHICKEN3,
6257 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6258
ecdb4eb7 6259 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6260 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6261 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6262 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6263
e36ea7ff
VS		 6264 /* WaVSRefCountFullforceMissDisable:hsw */
6265 I915_WRITE(GEN7_FF_THREAD_MODE,
6266 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6267
4e04632e
AG		 6268 /* WaDisable_RenderCache_OperationalFlush:hsw */
6269 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6270
fe27c606
CW		 6271 /* enable HiZ Raw Stall Optimization */
6272 I915_WRITE(CACHE_MODE_0_GEN7,
6273 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6274
ecdb4eb7 6275 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6276 I915_WRITE(CACHE_MODE_1,
6277 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6278
a12c4967
VS		 6279 /*
6280 * BSpec recommends 8x4 when MSAA is used,
6281 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6282 *
6283 * Note that PS/WM thread counts depend on the WIZ hashing
6284 * disable bit, which we don't touch here, but it's good
6285 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6286 */
6287 I915_WRITE(GEN7_GT_MODE,
98533251 6288 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6289
94411593
KG		 6290 /* WaSampleCChickenBitEnable:hsw */
6291 I915_WRITE(HALF_SLICE_CHICKEN3,
6292 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6293
ecdb4eb7 6294 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6295 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6296
90a88643
PZ		 6297 /* WaRsPkgCStateDisplayPMReq:hsw */
6298 I915_WRITE(CHICKEN_PAR1_1,
6299 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6300
17a303ec 6301 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6302}
6303
1fa61106 6304static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6305{
6306 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6307 uint32_t snpcr;
6f1d69b0 6308
017636cc 6309 ilk_init_lp_watermarks(dev);
6f1d69b0 6310
231e54f6 6311 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6312
ecdb4eb7 6313 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6314 I915_WRITE(_3D_CHICKEN3,
6315 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6316
ecdb4eb7 6317 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6318 I915_WRITE(IVB_CHICKEN3,
6319 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6320 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6321
ecdb4eb7 6322 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6323 if (IS_IVB_GT1(dev))
6324 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6325 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6326
4e04632e
AG		 6327 /* WaDisable_RenderCache_OperationalFlush:ivb */
6328 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6329
ecdb4eb7 6330 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6331 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6332 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6333
ecdb4eb7 6334 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6335 I915_WRITE(GEN7_L3CNTLREG1,
6336 GEN7_WA_FOR_GEN7_L3_CONTROL);
6337 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6338 GEN7_WA_L3_CHICKEN_MODE);
6339 if (IS_IVB_GT1(dev))
6340 I915_WRITE(GEN7_ROW_CHICKEN2,
6341 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6342 else {
6343 /* must write both registers */
6344 I915_WRITE(GEN7_ROW_CHICKEN2,
6345 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6346 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6347 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6348 }
6f1d69b0 6349
ecdb4eb7 6350 /* WaForceL3Serialization:ivb */
61939d97
JB		 6351 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6352 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6353
1b80a19a 6354 /*
0f846f81 6355 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6356 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6357 */
6358 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6359 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6360
ecdb4eb7 6361 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6362 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6363 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6364 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6365
0e088b8f 6366 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6367
6368 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6369
22721343
CW		 6370 if (0) { /* causes HiZ corruption on ivb:gt1 */
6371 /* enable HiZ Raw Stall Optimization */
6372 I915_WRITE(CACHE_MODE_0_GEN7,
6373 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6374 }
116f2b6d 6375
ecdb4eb7 6376 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6377 I915_WRITE(CACHE_MODE_1,
6378 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6379
a607c1a4
VS		 6380 /*
6381 * BSpec recommends 8x4 when MSAA is used,
6382 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6383 *
6384 * Note that PS/WM thread counts depend on the WIZ hashing
6385 * disable bit, which we don't touch here, but it's good
6386 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6387 */
6388 I915_WRITE(GEN7_GT_MODE,
98533251 6389 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6390
20848223
BW		 6391 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6392 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6393 snpcr |= GEN6_MBC_SNPCR_MED;
6394 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6395
ab5c608b
BW		 6396 if (!HAS_PCH_NOP(dev))
6397 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6398
6399 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6400}
6401
c6beb13e
VS		 6402static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6403{
6404 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6405
6406 /*
6407 * Disable trickle feed and enable pnd deadline calculation
6408 */
6409 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6410 I915_WRITE(CBR1_VLV, 0);
6411}
6412
1fa61106 6413static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6414{
6415 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6416
c6beb13e 6417 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6418
ecdb4eb7 6419 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6420 I915_WRITE(_3D_CHICKEN3,
6421 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6422
ecdb4eb7 6423 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6424 I915_WRITE(IVB_CHICKEN3,
6425 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6426 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6427
fad7d36e 6428 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6429 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6430 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6431 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6432 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6433
4e04632e
AG		 6434 /* WaDisable_RenderCache_OperationalFlush:vlv */
6435 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6436
ecdb4eb7 6437 /* WaForceL3Serialization:vlv */
61939d97
JB		 6438 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6439 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6440
ecdb4eb7 6441 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6442 I915_WRITE(GEN7_ROW_CHICKEN2,
6443 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6444
ecdb4eb7 6445 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6446 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6447 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6448 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6449
46680e0a
VS		 6450 gen7_setup_fixed_func_scheduler(dev_priv);
6451
3c0edaeb 6452 /*
0f846f81 6453 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6454 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6455 */
6456 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6457 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6458
c98f5062
AG		 6459 /* WaDisableL3Bank2xClockGate:vlv
6460 * Disabling L3 clock gating- MMIO 940c[25] = 1
6461 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6462 I915_WRITE(GEN7_UCGCTL4,
6463 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6464
afd58e79
VS		 6465 /*
6466 * BSpec says this must be set, even though
6467 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6468 */
6b26c86d
DV		 6469 I915_WRITE(CACHE_MODE_1,
6470 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6471
da2518f9
VS		 6472 /*
6473 * BSpec recommends 8x4 when MSAA is used,
6474 * however in practice 16x4 seems fastest.
6475 *
6476 * Note that PS/WM thread counts depend on the WIZ hashing
6477 * disable bit, which we don't touch here, but it's good
6478 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6479 */
6480 I915_WRITE(GEN7_GT_MODE,
6481 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6482
031994ee
VS		 6483 /*
6484 * WaIncreaseL3CreditsForVLVB0:vlv
6485 * This is the hardware default actually.
6486 */
6487 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6488
2d809570 6489 /*
ecdb4eb7 6490 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6491 * Disable clock gating on th GCFG unit to prevent a delay
6492 * in the reporting of vblank events.
6493 */
7a0d1eed 6494 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6495}
6496
a4565da8
VS		 6497static void cherryview_init_clock_gating(struct drm_device *dev)
6498{
6499 struct drm_i915_private *dev_priv = dev->dev_private;
6500
c6beb13e 6501 vlv_init_display_clock_gating(dev_priv);
dd811e70 6502
232ce337
VS		 6503 /* WaVSRefCountFullforceMissDisable:chv */
6504 /* WaDSRefCountFullforceMissDisable:chv */
6505 I915_WRITE(GEN7_FF_THREAD_MODE,
6506 I915_READ(GEN7_FF_THREAD_MODE) &
6507 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6508
6509 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6510 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6511 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6512
6513 /* WaDisableCSUnitClockGating:chv */
6514 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6515 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6516
6517 /* WaDisableSDEUnitClockGating:chv */
6518 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6519 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
a4565da8
VS		 6520}
6521
1fa61106 6522static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6523{
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 uint32_t dspclk_gate;
6526
6527 I915_WRITE(RENCLK_GATE_D1, 0);
6528 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6529 GS_UNIT_CLOCK_GATE_DISABLE |
6530 CL_UNIT_CLOCK_GATE_DISABLE);
6531 I915_WRITE(RAMCLK_GATE_D, 0);
6532 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6533 OVRUNIT_CLOCK_GATE_DISABLE |
6534 OVCUNIT_CLOCK_GATE_DISABLE;
6535 if (IS_GM45(dev))
6536 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6537 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6538
6539 /* WaDisableRenderCachePipelinedFlush */
6540 I915_WRITE(CACHE_MODE_0,
6541 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6542
4e04632e
AG		 6543 /* WaDisable_RenderCache_OperationalFlush:g4x */
6544 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6545
0e088b8f 6546 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6547}
6548
1fa61106 6549static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6550{
6551 struct drm_i915_private *dev_priv = dev->dev_private;
6552
6553 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6554 I915_WRITE(RENCLK_GATE_D2, 0);
6555 I915_WRITE(DSPCLK_GATE_D, 0);
6556 I915_WRITE(RAMCLK_GATE_D, 0);
6557 I915_WRITE16(DEUC, 0);
20f94967
VS		 6558 I915_WRITE(MI_ARB_STATE,
6559 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6560
6561 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6562 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6563}
6564
1fa61106 6565static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6566{
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568
6569 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6570 I965_RCC_CLOCK_GATE_DISABLE |
6571 I965_RCPB_CLOCK_GATE_DISABLE |
6572 I965_ISC_CLOCK_GATE_DISABLE |
6573 I965_FBC_CLOCK_GATE_DISABLE);
6574 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6575 I915_WRITE(MI_ARB_STATE,
6576 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6577
6578 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6579 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6580}
6581
1fa61106 6582static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6583{
6584 struct drm_i915_private *dev_priv = dev->dev_private;
6585 u32 dstate = I915_READ(D_STATE);
6586
6587 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6588 DSTATE_DOT_CLOCK_GATING;
6589 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6590
6591 if (IS_PINEVIEW(dev))
6592 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6593
6594 /* IIR "flip pending" means done if this bit is set */
6595 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6596
6597 /* interrupts should cause a wake up from C3 */
3299254f 6598 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6599
6600 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6601 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6602
6603 I915_WRITE(MI_ARB_STATE,
6604 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6605}
6606
1fa61106 6607static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6608{
6609 struct drm_i915_private *dev_priv = dev->dev_private;
6610
6611 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6612
6613 /* interrupts should cause a wake up from C3 */
6614 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6615 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6616
6617 I915_WRITE(MEM_MODE,
6618 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6619}
6620
1fa61106 6621static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6622{
6623 struct drm_i915_private *dev_priv = dev->dev_private;
6624
6625 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6626
6627 I915_WRITE(MEM_MODE,
6628 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6629 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6630}
6631
6f1d69b0
ED		 6632void intel_init_clock_gating(struct drm_device *dev)
6633{
6634 struct drm_i915_private *dev_priv = dev->dev_private;
6635
c57e3551
DL		 6636 if (dev_priv->display.init_clock_gating)
6637 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6638}
6639
7d708ee4
ID		 6640void intel_suspend_hw(struct drm_device *dev)
6641{
6642 if (HAS_PCH_LPT(dev))
6643 lpt_suspend_hw(dev);
6644}
6645
1fa61106
ED		 6646/* Set up chip specific power management-related functions */
6647void intel_init_pm(struct drm_device *dev)
6648{
6649 struct drm_i915_private *dev_priv = dev->dev_private;
6650
7ff0ebcc 6651 intel_fbc_init(dev_priv);
1fa61106 6652
c921aba8
DV		 6653 /* For cxsr */
6654 if (IS_PINEVIEW(dev))
6655 i915_pineview_get_mem_freq(dev);
6656 else if (IS_GEN5(dev))
6657 i915_ironlake_get_mem_freq(dev);
6658
1fa61106 6659 /* For FIFO watermark updates */
f5ed50cb 6660 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6661 skl_setup_wm_latency(dev);
6662
a82abe43
ID		 6663 if (IS_BROXTON(dev))
6664 dev_priv->display.init_clock_gating =
6665 bxt_init_clock_gating;
6666 else if (IS_SKYLAKE(dev))
6667 dev_priv->display.init_clock_gating =
6668 skl_init_clock_gating;
2d41c0b5
PB		 6669 dev_priv->display.update_wm = skl_update_wm;
6670 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6671 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6672 ilk_setup_wm_latency(dev);
53615a5e 6673
bd602544
VS		 6674 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6675 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6676 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6677 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6678 dev_priv->display.update_wm = ilk_update_wm;
6679 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6680 } else {
6681 DRM_DEBUG_KMS("Failed to read display plane latency. "
6682 "Disable CxSR\n");
6683 }
6684
6685 if (IS_GEN5(dev))
1fa61106 6686 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6687 else if (IS_GEN6(dev))
1fa61106 6688 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6689 else if (IS_IVYBRIDGE(dev))
1fa61106 6690 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6691 else if (IS_HASWELL(dev))
cad2a2d7 6692 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6693 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6694 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6695 } else if (IS_CHERRYVIEW(dev)) {
ae80152d 6696 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6697 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS		 6698 dev_priv->display.init_clock_gating =
6699 cherryview_init_clock_gating;
1fa61106
ED		 6700 } else if (IS_VALLEYVIEW(dev)) {
6701 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6702 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED		 6703 dev_priv->display.init_clock_gating =
6704 valleyview_init_clock_gating;
1fa61106
ED		 6705 } else if (IS_PINEVIEW(dev)) {
6706 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6707 dev_priv->is_ddr3,
6708 dev_priv->fsb_freq,
6709 dev_priv->mem_freq)) {
6710 DRM_INFO("failed to find known CxSR latency "
6711 "(found ddr%s fsb freq %d, mem freq %d), "
6712 "disabling CxSR\n",
6713 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6714 dev_priv->fsb_freq, dev_priv->mem_freq);
6715 /* Disable CxSR and never update its watermark again */
5209b1f4 6716 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 6717 dev_priv->display.update_wm = NULL;
6718 } else
6719 dev_priv->display.update_wm = pineview_update_wm;
6720 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6721 } else if (IS_G4X(dev)) {
6722 dev_priv->display.update_wm = g4x_update_wm;
6723 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6724 } else if (IS_GEN4(dev)) {
6725 dev_priv->display.update_wm = i965_update_wm;
6726 if (IS_CRESTLINE(dev))
6727 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6728 else if (IS_BROADWATER(dev))
6729 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6730 } else if (IS_GEN3(dev)) {
6731 dev_priv->display.update_wm = i9xx_update_wm;
6732 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6733 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 6734 } else if (IS_GEN2(dev)) {
6735 if (INTEL_INFO(dev)->num_pipes == 1) {
6736 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6737 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 6738 } else {
6739 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6740 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 6741 }
6742
6743 if (IS_I85X(dev) || IS_I865G(dev))
6744 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6745 else
6746 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6747 } else {
6748 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 6749 }
6750}
6751
151a49d0 6752int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6753{
4fc688ce 6754 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6755
6756 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6757 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6758 return -EAGAIN;
6759 }
6760
6761 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6762 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 6763 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6764
6765 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6766 500)) {
6767 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6768 return -ETIMEDOUT;
6769 }
6770
6771 *val = I915_READ(GEN6_PCODE_DATA);
6772 I915_WRITE(GEN6_PCODE_DATA, 0);
6773
6774 return 0;
6775}
6776
151a49d0 6777int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6778{
4fc688ce 6779 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6780
6781 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6782 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6783 return -EAGAIN;
6784 }
6785
6786 I915_WRITE(GEN6_PCODE_DATA, val);
6787 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6788
6789 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6790 500)) {
6791 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6792 return -ETIMEDOUT;
6793 }
6794
6795 I915_WRITE(GEN6_PCODE_DATA, 0);
6796
6797 return 0;
6798}
a0e4e199 6799
dd06f88c 6800static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6801{
dd06f88c
VS		 6802 switch (czclk_freq) {
6803 case 200:
6804 return 10;
6805 case 267:
6806 return 12;
6807 case 320:
6808 case 333:
dd06f88c 6809 return 16;
ab3fb157
VS		 6810 case 400:
6811 return 20;
855ba3be
JB		 6812 default:
6813 return -1;
6814 }
dd06f88c 6815}
855ba3be 6816
dd06f88c
VS		 6817static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6818{
6819 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6820
6821 div = vlv_gpu_freq_div(czclk_freq);
6822 if (div < 0)
6823 return div;
6824
6825 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 6826}
6827
b55dd647 6828static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6829{
dd06f88c 6830 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6831
dd06f88c
VS		 6832 mul = vlv_gpu_freq_div(czclk_freq);
6833 if (mul < 0)
6834 return mul;
855ba3be 6835
dd06f88c 6836 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 6837}
6838
b55dd647 6839static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6840{
dd06f88c 6841 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6842
dd06f88c
VS		 6843 div = vlv_gpu_freq_div(czclk_freq) / 2;
6844 if (div < 0)
6845 return div;
22b1b2f8 6846
dd06f88c 6847 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 6848}
6849
b55dd647 6850static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6851{
dd06f88c 6852 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6853
dd06f88c
VS		 6854 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6855 if (mul < 0)
6856 return mul;
22b1b2f8 6857
1c14762d 6858 /* CHV needs even values */
dd06f88c 6859 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 6860}
6861
616bc820 6862int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6863{
80b6dda4
AG		 6864 if (IS_GEN9(dev_priv->dev))
6865 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6866 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6867 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6868 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6869 return byt_gpu_freq(dev_priv, val);
6870 else
6871 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 6872}
6873
616bc820
VS		 6874int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6875{
80b6dda4
AG		 6876 if (IS_GEN9(dev_priv->dev))
6877 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6878 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6879 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6880 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 6881 return byt_freq_opcode(dev_priv, val);
6882 else
6883 return val / GT_FREQUENCY_MULTIPLIER;
6884}
22b1b2f8 6885
6ad790c0
CW		 6886struct request_boost {
6887 struct work_struct work;
6888 struct drm_i915_gem_request *rq;
6889};
6890
6891static void __intel_rps_boost_work(struct work_struct *work)
6892{
6893 struct request_boost *boost = container_of(work, struct request_boost, work);
6894
6895 if (!i915_gem_request_completed(boost->rq, true))
1854d5ca 6896 gen6_rps_boost(to_i915(boost->rq->ring->dev), NULL);
6ad790c0
CW		 6897
6898 i915_gem_request_unreference__unlocked(boost->rq);
6899 kfree(boost);
6900}
6901
6902void intel_queue_rps_boost_for_request(struct drm_device *dev,
6903 struct drm_i915_gem_request *rq)
6904{
6905 struct request_boost *boost;
6906
6907 if (rq == NULL || INTEL_INFO(dev)->gen < 6)
6908 return;
6909
6910 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
6911 if (boost == NULL)
6912 return;
6913
6914 i915_gem_request_reference(rq);
6915 boost->rq = rq;
6916
6917 INIT_WORK(&boost->work, __intel_rps_boost_work);
6918 queue_work(to_i915(dev)->wq, &boost->work);
6919}
6920
f742a552 6921void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 6922{
6923 struct drm_i915_private *dev_priv = dev->dev_private;
6924
f742a552
DV		 6925 mutex_init(&dev_priv->rps.hw_lock);
6926
907b28c5
CW		 6927 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6928 intel_gen6_powersave_work);
1854d5ca 6929 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 6930
33688d95 6931 dev_priv->pm.suspended = false;
907b28c5 6932}
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