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drm/i915/skl: Remove linetime from skl_wm_values
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
44a655ca
TU		 255static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
256 bool is_ddr3,
b445e3b0
ED		 257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
920a14b2 325 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 329 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
50a0bc90 337 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
50a0bc90 342 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
50a0bc90
TU		 651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
652 dev_priv->is_ddr3,
653 dev_priv->fsb_freq,
654 dev_priv->mem_freq);
b445e3b0
ED		 655 if (!latency) {
656 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 657 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 658 return;
659 }
660
661 crtc = single_enabled_crtc(dev);
662 if (crtc) {
7c5f93b0 663 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 664 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 665 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 666
667 /* Display SR */
668 wm = intel_calculate_wm(clock, &pineview_display_wm,
669 pineview_display_wm.fifo_size,
ac484963 670 cpp, latency->display_sr);
b445e3b0
ED		 671 reg = I915_READ(DSPFW1);
672 reg &= ~DSPFW_SR_MASK;
f4998963 673 reg |= FW_WM(wm, SR);
b445e3b0
ED		 674 I915_WRITE(DSPFW1, reg);
675 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
676
677 /* cursor SR */
678 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
679 pineview_display_wm.fifo_size,
ac484963 680 cpp, latency->cursor_sr);
b445e3b0
ED		 681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 683 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 684 I915_WRITE(DSPFW3, reg);
685
686 /* Display HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
ac484963 689 cpp, latency->display_hpll_disable);
b445e3b0
ED		 690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 692 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 693 I915_WRITE(DSPFW3, reg);
694
695 /* cursor HPLL off SR */
696 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
697 pineview_display_hplloff_wm.fifo_size,
ac484963 698 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 699 reg = I915_READ(DSPFW3);
700 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 701 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 702 I915_WRITE(DSPFW3, reg);
703 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
704
5209b1f4 705 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 706 } else {
5209b1f4 707 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 708 }
709}
710
711static bool g4x_compute_wm0(struct drm_device *dev,
712 int plane,
713 const struct intel_watermark_params *display,
714 int display_latency_ns,
715 const struct intel_watermark_params *cursor,
716 int cursor_latency_ns,
717 int *plane_wm,
718 int *cursor_wm)
719{
720 struct drm_crtc *crtc;
4fe8590a 721 const struct drm_display_mode *adjusted_mode;
ac484963 722 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 723 int line_time_us, line_count;
724 int entries, tlb_miss;
725
726 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 727 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 728 *cursor_wm = cursor->guard_size;
729 *plane_wm = display->guard_size;
730 return false;
731 }
732
6e3c9717 733 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 734 clock = adjusted_mode->crtc_clock;
fec8cba3 735 htotal = adjusted_mode->crtc_htotal;
6e3c9717 736 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 737 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 738
739 /* Use the small buffer method to calculate plane watermark */
ac484963 740 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 741 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
742 if (tlb_miss > 0)
743 entries += tlb_miss;
744 entries = DIV_ROUND_UP(entries, display->cacheline_size);
745 *plane_wm = entries + display->guard_size;
746 if (*plane_wm > (int)display->max_wm)
747 *plane_wm = display->max_wm;
748
749 /* Use the large buffer method to calculate cursor watermark */
922044c9 750 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 751 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 752 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 753 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
754 if (tlb_miss > 0)
755 entries += tlb_miss;
756 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
757 *cursor_wm = entries + cursor->guard_size;
758 if (*cursor_wm > (int)cursor->max_wm)
759 *cursor_wm = (int)cursor->max_wm;
760
761 return true;
762}
763
764/*
765 * Check the wm result.
766 *
767 * If any calculated watermark values is larger than the maximum value that
768 * can be programmed into the associated watermark register, that watermark
769 * must be disabled.
770 */
771static bool g4x_check_srwm(struct drm_device *dev,
772 int display_wm, int cursor_wm,
773 const struct intel_watermark_params *display,
774 const struct intel_watermark_params *cursor)
775{
776 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
777 display_wm, cursor_wm);
778
779 if (display_wm > display->max_wm) {
ae9400ca 780 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 781 display_wm, display->max_wm);
782 return false;
783 }
784
785 if (cursor_wm > cursor->max_wm) {
ae9400ca 786 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 787 cursor_wm, cursor->max_wm);
788 return false;
789 }
790
791 if (!(display_wm || cursor_wm)) {
792 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
793 return false;
794 }
795
796 return true;
797}
798
799static bool g4x_compute_srwm(struct drm_device *dev,
800 int plane,
801 int latency_ns,
802 const struct intel_watermark_params *display,
803 const struct intel_watermark_params *cursor,
804 int *display_wm, int *cursor_wm)
805{
806 struct drm_crtc *crtc;
4fe8590a 807 const struct drm_display_mode *adjusted_mode;
ac484963 808 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 809 unsigned long line_time_us;
810 int line_count, line_size;
811 int small, large;
812 int entries;
813
814 if (!latency_ns) {
815 *display_wm = *cursor_wm = 0;
816 return false;
817 }
818
819 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 820 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 821 clock = adjusted_mode->crtc_clock;
fec8cba3 822 htotal = adjusted_mode->crtc_htotal;
6e3c9717 823 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 824 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 825
922044c9 826 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 827 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 828 line_size = hdisplay * cpp;
b445e3b0
ED		 829
830 /* Use the minimum of the small and large buffer method for primary */
ac484963 831 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 832 large = line_count * line_size;
833
834 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
835 *display_wm = entries + display->guard_size;
836
837 /* calculate the self-refresh watermark for display cursor */
ac484963 838 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 839 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
840 *cursor_wm = entries + cursor->guard_size;
841
842 return g4x_check_srwm(dev,
843 *display_wm, *cursor_wm,
844 display, cursor);
845}
846
15665979
VS		 847#define FW_WM_VLV(value, plane) \
848 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
849
0018fda1
VS		 850static void vlv_write_wm_values(struct intel_crtc *crtc,
851 const struct vlv_wm_values *wm)
852{
853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
854 enum pipe pipe = crtc->pipe;
855
856 I915_WRITE(VLV_DDL(pipe),
857 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
858 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
859 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
860 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
861
ae80152d 862 I915_WRITE(DSPFW1,
15665979
VS		 863 FW_WM(wm->sr.plane, SR) |
864 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
865 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
866 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 867 I915_WRITE(DSPFW2,
15665979
VS		 868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
869 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
870 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 871 I915_WRITE(DSPFW3,
15665979 872 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 873
874 if (IS_CHERRYVIEW(dev_priv)) {
875 I915_WRITE(DSPFW7_CHV,
15665979
VS		 876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
877 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 878 I915_WRITE(DSPFW8_CHV,
15665979
VS		 879 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
880 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 881 I915_WRITE(DSPFW9_CHV,
15665979
VS		 882 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
883 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 884 I915_WRITE(DSPHOWM,
15665979
VS		 885 FW_WM(wm->sr.plane >> 9, SR_HI) |
886 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
887 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
888 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
890 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
891 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
892 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
893 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
894 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 895 } else {
896 I915_WRITE(DSPFW7,
15665979
VS		 897 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
898 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 899 I915_WRITE(DSPHOWM,
15665979
VS		 900 FW_WM(wm->sr.plane >> 9, SR_HI) |
901 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
902 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
903 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
904 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
905 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
906 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 907 }
908
2cb389b7
VS		 909 /* zero (unused) WM1 watermarks */
910 I915_WRITE(DSPFW4, 0);
911 I915_WRITE(DSPFW5, 0);
912 I915_WRITE(DSPFW6, 0);
913 I915_WRITE(DSPHOWM1, 0);
914
ae80152d 915 POSTING_READ(DSPFW1);
0018fda1
VS		 916}
917
15665979
VS		 918#undef FW_WM_VLV
919
6eb1a681
VS		 920enum vlv_wm_level {
921 VLV_WM_LEVEL_PM2,
922 VLV_WM_LEVEL_PM5,
923 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 924};
925
262cd2e1
VS		 926/* latency must be in 0.1us units. */
927static unsigned int vlv_wm_method2(unsigned int pixel_rate,
928 unsigned int pipe_htotal,
929 unsigned int horiz_pixels,
ac484963 930 unsigned int cpp,
262cd2e1
VS		 931 unsigned int latency)
932{
933 unsigned int ret;
934
935 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 936 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 937 ret = DIV_ROUND_UP(ret, 64);
938
939 return ret;
940}
941
942static void vlv_setup_wm_latency(struct drm_device *dev)
943{
fac5e23e 944 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 945
946 /* all latencies in usec */
947 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
948
58590c14
VS		 949 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
950
262cd2e1
VS		 951 if (IS_CHERRYVIEW(dev_priv)) {
952 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
953 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 954
955 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 956 }
957}
958
959static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
960 struct intel_crtc *crtc,
961 const struct intel_plane_state *state,
962 int level)
963{
964 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 965 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 966
967 if (dev_priv->wm.pri_latency[level] == 0)
968 return USHRT_MAX;
969
936e71e3 970 if (!state->base.visible)
262cd2e1
VS		 971 return 0;
972
ac484963 973 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 974 clock = crtc->config->base.adjusted_mode.crtc_clock;
975 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
976 width = crtc->config->pipe_src_w;
977 if (WARN_ON(htotal == 0))
978 htotal = 1;
979
980 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
981 /*
982 * FIXME the formula gives values that are
983 * too big for the cursor FIFO, and hence we
984 * would never be able to use cursors. For
985 * now just hardcode the watermark.
986 */
987 wm = 63;
988 } else {
ac484963 989 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 990 dev_priv->wm.pri_latency[level] * 10);
991 }
992
993 return min_t(int, wm, USHRT_MAX);
994}
995
54f1b6e1
VS		 996static void vlv_compute_fifo(struct intel_crtc *crtc)
997{
998 struct drm_device *dev = crtc->base.dev;
999 struct vlv_wm_state *wm_state = &crtc->wm_state;
1000 struct intel_plane *plane;
1001 unsigned int total_rate = 0;
1002 const int fifo_size = 512 - 1;
1003 int fifo_extra, fifo_left = fifo_size;
1004
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 struct intel_plane_state *state =
1007 to_intel_plane_state(plane->base.state);
1008
1009 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1010 continue;
1011
936e71e3 1012 if (state->base.visible) {
54f1b6e1
VS		 1013 wm_state->num_active_planes++;
1014 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1015 }
1016 }
1017
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 struct intel_plane_state *state =
1020 to_intel_plane_state(plane->base.state);
1021 unsigned int rate;
1022
1023 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1024 plane->wm.fifo_size = 63;
1025 continue;
1026 }
1027
936e71e3 1028 if (!state->base.visible) {
54f1b6e1
VS		 1029 plane->wm.fifo_size = 0;
1030 continue;
1031 }
1032
1033 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1034 plane->wm.fifo_size = fifo_size * rate / total_rate;
1035 fifo_left -= plane->wm.fifo_size;
1036 }
1037
1038 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1039
1040 /* spread the remainder evenly */
1041 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042 int plane_extra;
1043
1044 if (fifo_left == 0)
1045 break;
1046
1047 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1048 continue;
1049
1050 /* give it all to the first plane if none are active */
1051 if (plane->wm.fifo_size == 0 &&
1052 wm_state->num_active_planes)
1053 continue;
1054
1055 plane_extra = min(fifo_extra, fifo_left);
1056 plane->wm.fifo_size += plane_extra;
1057 fifo_left -= plane_extra;
1058 }
1059
1060 WARN_ON(fifo_left != 0);
1061}
1062
262cd2e1
VS		 1063static void vlv_invert_wms(struct intel_crtc *crtc)
1064{
1065 struct vlv_wm_state *wm_state = &crtc->wm_state;
1066 int level;
1067
1068 for (level = 0; level < wm_state->num_levels; level++) {
1069 struct drm_device *dev = crtc->base.dev;
1070 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1071 struct intel_plane *plane;
1072
1073 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1074 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1075
1076 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1077 switch (plane->base.type) {
1078 int sprite;
1079 case DRM_PLANE_TYPE_CURSOR:
1080 wm_state->wm[level].cursor = plane->wm.fifo_size -
1081 wm_state->wm[level].cursor;
1082 break;
1083 case DRM_PLANE_TYPE_PRIMARY:
1084 wm_state->wm[level].primary = plane->wm.fifo_size -
1085 wm_state->wm[level].primary;
1086 break;
1087 case DRM_PLANE_TYPE_OVERLAY:
1088 sprite = plane->plane;
1089 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1090 wm_state->wm[level].sprite[sprite];
1091 break;
1092 }
1093 }
1094 }
1095}
1096
26e1fe4f 1097static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1098{
1099 struct drm_device *dev = crtc->base.dev;
1100 struct vlv_wm_state *wm_state = &crtc->wm_state;
1101 struct intel_plane *plane;
1102 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1103 int level;
1104
1105 memset(wm_state, 0, sizeof(*wm_state));
1106
852eb00d 1107 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1108 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1109
1110 wm_state->num_active_planes = 0;
262cd2e1 1111
54f1b6e1 1112 vlv_compute_fifo(crtc);
262cd2e1
VS		 1113
1114 if (wm_state->num_active_planes != 1)
1115 wm_state->cxsr = false;
1116
1117 if (wm_state->cxsr) {
1118 for (level = 0; level < wm_state->num_levels; level++) {
1119 wm_state->sr[level].plane = sr_fifo_size;
1120 wm_state->sr[level].cursor = 63;
1121 }
1122 }
1123
1124 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1125 struct intel_plane_state *state =
1126 to_intel_plane_state(plane->base.state);
1127
936e71e3 1128 if (!state->base.visible)
262cd2e1
VS		 1129 continue;
1130
1131 /* normal watermarks */
1132 for (level = 0; level < wm_state->num_levels; level++) {
1133 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1134 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1135
1136 /* hack */
1137 if (WARN_ON(level == 0 && wm > max_wm))
1138 wm = max_wm;
1139
1140 if (wm > plane->wm.fifo_size)
1141 break;
1142
1143 switch (plane->base.type) {
1144 int sprite;
1145 case DRM_PLANE_TYPE_CURSOR:
1146 wm_state->wm[level].cursor = wm;
1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 wm_state->wm[level].primary = wm;
1150 break;
1151 case DRM_PLANE_TYPE_OVERLAY:
1152 sprite = plane->plane;
1153 wm_state->wm[level].sprite[sprite] = wm;
1154 break;
1155 }
1156 }
1157
1158 wm_state->num_levels = level;
1159
1160 if (!wm_state->cxsr)
1161 continue;
1162
1163 /* maxfifo watermarks */
1164 switch (plane->base.type) {
1165 int sprite, level;
1166 case DRM_PLANE_TYPE_CURSOR:
1167 for (level = 0; level < wm_state->num_levels; level++)
1168 wm_state->sr[level].cursor =
5a37ed0a 1169 wm_state->wm[level].cursor;
262cd2e1
VS		 1170 break;
1171 case DRM_PLANE_TYPE_PRIMARY:
1172 for (level = 0; level < wm_state->num_levels; level++)
1173 wm_state->sr[level].plane =
1174 min(wm_state->sr[level].plane,
1175 wm_state->wm[level].primary);
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 for (level = 0; level < wm_state->num_levels; level++)
1180 wm_state->sr[level].plane =
1181 min(wm_state->sr[level].plane,
1182 wm_state->wm[level].sprite[sprite]);
1183 break;
1184 }
1185 }
1186
1187 /* clear any (partially) filled invalid levels */
58590c14 1188 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1189 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1190 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1191 }
1192
1193 vlv_invert_wms(crtc);
1194}
1195
54f1b6e1
VS		 1196#define VLV_FIFO(plane, value) \
1197 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1198
1199static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1200{
1201 struct drm_device *dev = crtc->base.dev;
1202 struct drm_i915_private *dev_priv = to_i915(dev);
1203 struct intel_plane *plane;
1204 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1205
1206 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1207 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1208 WARN_ON(plane->wm.fifo_size != 63);
1209 continue;
1210 }
1211
1212 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1213 sprite0_start = plane->wm.fifo_size;
1214 else if (plane->plane == 0)
1215 sprite1_start = sprite0_start + plane->wm.fifo_size;
1216 else
1217 fifo_size = sprite1_start + plane->wm.fifo_size;
1218 }
1219
1220 WARN_ON(fifo_size != 512 - 1);
1221
1222 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223 pipe_name(crtc->pipe), sprite0_start,
1224 sprite1_start, fifo_size);
1225
1226 switch (crtc->pipe) {
1227 uint32_t dsparb, dsparb2, dsparb3;
1228 case PIPE_A:
1229 dsparb = I915_READ(DSPARB);
1230 dsparb2 = I915_READ(DSPARB2);
1231
1232 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1233 VLV_FIFO(SPRITEB, 0xff));
1234 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1235 VLV_FIFO(SPRITEB, sprite1_start));
1236
1237 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1238 VLV_FIFO(SPRITEB_HI, 0x1));
1239 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1240 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1241
1242 I915_WRITE(DSPARB, dsparb);
1243 I915_WRITE(DSPARB2, dsparb2);
1244 break;
1245 case PIPE_B:
1246 dsparb = I915_READ(DSPARB);
1247 dsparb2 = I915_READ(DSPARB2);
1248
1249 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1250 VLV_FIFO(SPRITED, 0xff));
1251 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1252 VLV_FIFO(SPRITED, sprite1_start));
1253
1254 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1255 VLV_FIFO(SPRITED_HI, 0xff));
1256 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1257 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1258
1259 I915_WRITE(DSPARB, dsparb);
1260 I915_WRITE(DSPARB2, dsparb2);
1261 break;
1262 case PIPE_C:
1263 dsparb3 = I915_READ(DSPARB3);
1264 dsparb2 = I915_READ(DSPARB2);
1265
1266 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1267 VLV_FIFO(SPRITEF, 0xff));
1268 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1269 VLV_FIFO(SPRITEF, sprite1_start));
1270
1271 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1272 VLV_FIFO(SPRITEF_HI, 0xff));
1273 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1274 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1275
1276 I915_WRITE(DSPARB3, dsparb3);
1277 I915_WRITE(DSPARB2, dsparb2);
1278 break;
1279 default:
1280 break;
1281 }
1282}
1283
1284#undef VLV_FIFO
1285
262cd2e1
VS		 1286static void vlv_merge_wm(struct drm_device *dev,
1287 struct vlv_wm_values *wm)
1288{
1289 struct intel_crtc *crtc;
1290 int num_active_crtcs = 0;
1291
58590c14 1292 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1293 wm->cxsr = true;
1294
1295 for_each_intel_crtc(dev, crtc) {
1296 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1297
1298 if (!crtc->active)
1299 continue;
1300
1301 if (!wm_state->cxsr)
1302 wm->cxsr = false;
1303
1304 num_active_crtcs++;
1305 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1306 }
1307
1308 if (num_active_crtcs != 1)
1309 wm->cxsr = false;
1310
6f9c784b
VS		 1311 if (num_active_crtcs > 1)
1312 wm->level = VLV_WM_LEVEL_PM2;
1313
262cd2e1
VS		 1314 for_each_intel_crtc(dev, crtc) {
1315 struct vlv_wm_state *wm_state = &crtc->wm_state;
1316 enum pipe pipe = crtc->pipe;
1317
1318 if (!crtc->active)
1319 continue;
1320
1321 wm->pipe[pipe] = wm_state->wm[wm->level];
1322 if (wm->cxsr)
1323 wm->sr = wm_state->sr[wm->level];
1324
1325 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1327 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1328 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1329 }
1330}
1331
1332static void vlv_update_wm(struct drm_crtc *crtc)
1333{
1334 struct drm_device *dev = crtc->dev;
fac5e23e 1335 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1337 enum pipe pipe = intel_crtc->pipe;
1338 struct vlv_wm_values wm = {};
1339
26e1fe4f 1340 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1341 vlv_merge_wm(dev, &wm);
1342
54f1b6e1
VS		 1343 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1344 /* FIXME should be part of crtc atomic commit */
1345 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1346 return;
54f1b6e1 1347 }
262cd2e1
VS		 1348
1349 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1350 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1351 chv_set_memory_dvfs(dev_priv, false);
1352
1353 if (wm.level < VLV_WM_LEVEL_PM5 &&
1354 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1355 chv_set_memory_pm5(dev_priv, false);
1356
852eb00d 1357 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1358 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1359
54f1b6e1
VS		 1360 /* FIXME should be part of crtc atomic commit */
1361 vlv_pipe_set_fifo_size(intel_crtc);
1362
262cd2e1
VS		 1363 vlv_write_wm_values(intel_crtc, &wm);
1364
1365 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1366 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1367 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1368 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1369 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1370
852eb00d 1371 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1372 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1373
1374 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1375 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1376 chv_set_memory_pm5(dev_priv, true);
1377
1378 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1379 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1380 chv_set_memory_dvfs(dev_priv, true);
1381
1382 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1383}
1384
ae80152d
VS		 1385#define single_plane_enabled(mask) is_power_of_2(mask)
1386
46ba614c 1387static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1388{
46ba614c 1389 struct drm_device *dev = crtc->dev;
b445e3b0 1390 static const int sr_latency_ns = 12000;
fac5e23e 1391 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1392 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1393 int plane_sr, cursor_sr;
1394 unsigned int enabled = 0;
9858425c 1395 bool cxsr_enabled;
b445e3b0 1396
51cea1f4 1397 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1398 &g4x_wm_info, pessimal_latency_ns,
1399 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1400 &planea_wm, &cursora_wm))
51cea1f4 1401 enabled |= 1 << PIPE_A;
b445e3b0 1402
51cea1f4 1403 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1404 &g4x_wm_info, pessimal_latency_ns,
1405 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1406 &planeb_wm, &cursorb_wm))
51cea1f4 1407 enabled |= 1 << PIPE_B;
b445e3b0 1408
b445e3b0
ED		 1409 if (single_plane_enabled(enabled) &&
1410 g4x_compute_srwm(dev, ffs(enabled) - 1,
1411 sr_latency_ns,
1412 &g4x_wm_info,
1413 &g4x_cursor_wm_info,
52bd02d8 1414 &plane_sr, &cursor_sr)) {
9858425c 1415 cxsr_enabled = true;
52bd02d8 1416 } else {
9858425c 1417 cxsr_enabled = false;
5209b1f4 1418 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1419 plane_sr = cursor_sr = 0;
1420 }
b445e3b0 1421
a5043453
VS		 1422 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1423 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1424 planea_wm, cursora_wm,
1425 planeb_wm, cursorb_wm,
1426 plane_sr, cursor_sr);
1427
1428 I915_WRITE(DSPFW1,
f4998963
VS		 1429 FW_WM(plane_sr, SR) |
1430 FW_WM(cursorb_wm, CURSORB) |
1431 FW_WM(planeb_wm, PLANEB) |
1432 FW_WM(planea_wm, PLANEA));
b445e3b0 1433 I915_WRITE(DSPFW2,
8c919b28 1434 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1435 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1436 /* HPLL off in SR has some issues on G4x... disable it */
1437 I915_WRITE(DSPFW3,
8c919b28 1438 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1439 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1440
1441 if (cxsr_enabled)
1442 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1443}
1444
46ba614c 1445static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1446{
46ba614c 1447 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1448 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1449 struct drm_crtc *crtc;
1450 int srwm = 1;
1451 int cursor_sr = 16;
9858425c 1452 bool cxsr_enabled;
b445e3b0
ED		 1453
1454 /* Calc sr entries for one plane configs */
1455 crtc = single_enabled_crtc(dev);
1456 if (crtc) {
1457 /* self-refresh has much higher latency */
1458 static const int sr_latency_ns = 12000;
124abe07 1459 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1460 int clock = adjusted_mode->crtc_clock;
fec8cba3 1461 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1462 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1463 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1464 unsigned long line_time_us;
1465 int entries;
1466
922044c9 1467 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1468
1469 /* Use ns/us then divide to preserve precision */
1470 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1471 cpp * hdisplay;
b445e3b0
ED		 1472 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1473 srwm = I965_FIFO_SIZE - entries;
1474 if (srwm < 0)
1475 srwm = 1;
1476 srwm &= 0x1ff;
1477 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1478 entries, srwm);
1479
1480 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1481 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1482 entries = DIV_ROUND_UP(entries,
1483 i965_cursor_wm_info.cacheline_size);
1484 cursor_sr = i965_cursor_wm_info.fifo_size -
1485 (entries + i965_cursor_wm_info.guard_size);
1486
1487 if (cursor_sr > i965_cursor_wm_info.max_wm)
1488 cursor_sr = i965_cursor_wm_info.max_wm;
1489
1490 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1491 "cursor %d\n", srwm, cursor_sr);
1492
9858425c 1493 cxsr_enabled = true;
b445e3b0 1494 } else {
9858425c 1495 cxsr_enabled = false;
b445e3b0 1496 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1497 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1498 }
1499
1500 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1501 srwm);
1502
1503 /* 965 has limitations... */
f4998963
VS		 1504 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1505 FW_WM(8, CURSORB) |
1506 FW_WM(8, PLANEB) |
1507 FW_WM(8, PLANEA));
1508 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1509 FW_WM(8, PLANEC_OLD));
b445e3b0 1510 /* update cursor SR watermark */
f4998963 1511 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1512
1513 if (cxsr_enabled)
1514 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1515}
1516
f4998963
VS		 1517#undef FW_WM
1518
46ba614c 1519static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1520{
46ba614c 1521 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1522 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1523 const struct intel_watermark_params *wm_info;
1524 uint32_t fwater_lo;
1525 uint32_t fwater_hi;
1526 int cwm, srwm = 1;
1527 int fifo_size;
1528 int planea_wm, planeb_wm;
1529 struct drm_crtc *crtc, *enabled = NULL;
1530
1531 if (IS_I945GM(dev))
1532 wm_info = &i945_wm_info;
5db94019 1533 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1534 wm_info = &i915_wm_info;
1535 else
9d539105 1536 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1539 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1540 if (intel_crtc_active(crtc)) {
241bfc38 1541 const struct drm_display_mode *adjusted_mode;
ac484963 1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1543 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1544 cpp = 4;
1545
6e3c9717 1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1547 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1548 wm_info, fifo_size, cpp,
5aef6003 1549 pessimal_latency_ns);
b445e3b0 1550 enabled = crtc;
9d539105 1551 } else {
b445e3b0 1552 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1553 if (planea_wm > (long)wm_info->max_wm)
1554 planea_wm = wm_info->max_wm;
1555 }
1556
5db94019 1557 if (IS_GEN2(dev_priv))
9d539105 1558 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1559
1560 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1561 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1562 if (intel_crtc_active(crtc)) {
241bfc38 1563 const struct drm_display_mode *adjusted_mode;
ac484963 1564 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
5db94019 1565 if (IS_GEN2(dev_priv))
b9e0bda3
CW		 1566 cpp = 4;
1567
6e3c9717 1568 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1569 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
5aef6003 1571 pessimal_latency_ns);
b445e3b0
ED		 1572 if (enabled == NULL)
1573 enabled = crtc;
1574 else
1575 enabled = NULL;
9d539105 1576 } else {
b445e3b0 1577 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1578 if (planeb_wm > (long)wm_info->max_wm)
1579 planeb_wm = wm_info->max_wm;
1580 }
b445e3b0
ED		 1581
1582 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1583
50a0bc90 1584 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1585 struct drm_i915_gem_object *obj;
2ab1bc9d 1586
59bea882 1587 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1588
1589 /* self-refresh seems busted with untiled */
3e510a8e 1590 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1591 enabled = NULL;
1592 }
1593
b445e3b0
ED		 1594 /*
1595 * Overlay gets an aggressive default since video jitter is bad.
1596 */
1597 cwm = 2;
1598
1599 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1600 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1601
1602 /* Calc sr entries for one plane configs */
1603 if (HAS_FW_BLC(dev) && enabled) {
1604 /* self-refresh has much higher latency */
1605 static const int sr_latency_ns = 6000;
124abe07 1606 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1607 int clock = adjusted_mode->crtc_clock;
fec8cba3 1608 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1609 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1610 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1611 unsigned long line_time_us;
1612 int entries;
1613
50a0bc90 1614 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056
VS		 1615 cpp = 4;
1616
922044c9 1617 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1621 cpp * hdisplay;
b445e3b0
ED		 1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
50a0bc90 1628 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1631 else
b445e3b0
ED		 1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
5209b1f4
ID		 1648 if (enabled)
1649 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1650}
1651
feb56b93 1652static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1653{
46ba614c 1654 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1655 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1656 struct drm_crtc *crtc;
241bfc38 1657 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1658 uint32_t fwater_lo;
1659 int planea_wm;
1660
1661 crtc = single_enabled_crtc(dev);
1662 if (crtc == NULL)
1663 return;
1664
6e3c9717 1665 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1666 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1667 &i845_wm_info,
b445e3b0 1668 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1669 4, pessimal_latency_ns);
b445e3b0
ED		 1670 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1671 fwater_lo |= (3<<8) | planea_wm;
1672
1673 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1674
1675 I915_WRITE(FW_BLC, fwater_lo);
1676}
1677
8cfb3407 1678uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1679{
fd4daa9c 1680 uint32_t pixel_rate;
801bcfff 1681
8cfb3407 1682 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1683
1684 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1685 * adjust the pixel_rate here. */
1686
8cfb3407 1687 if (pipe_config->pch_pfit.enabled) {
801bcfff 1688 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1689 uint32_t pfit_size = pipe_config->pch_pfit.size;
1690
1691 pipe_w = pipe_config->pipe_src_w;
1692 pipe_h = pipe_config->pipe_src_h;
801bcfff 1693
801bcfff
PZ		 1694 pfit_w = (pfit_size >> 16) & 0xFFFF;
1695 pfit_h = pfit_size & 0xFFFF;
1696 if (pipe_w < pfit_w)
1697 pipe_w = pfit_w;
1698 if (pipe_h < pfit_h)
1699 pipe_h = pfit_h;
1700
15126882
MR		 1701 if (WARN_ON(!pfit_w || !pfit_h))
1702 return pixel_rate;
1703
801bcfff
PZ		 1704 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1705 pfit_w * pfit_h);
1706 }
1707
1708 return pixel_rate;
1709}
1710
37126462 1711/* latency must be in 0.1us units. */
ac484963 1712static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1713{
1714 uint64_t ret;
1715
3312ba65
VS		 1716 if (WARN(latency == 0, "Latency value missing\n"))
1717 return UINT_MAX;
1718
ac484963 1719 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1720 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1721
1722 return ret;
1723}
1724
37126462 1725/* latency must be in 0.1us units. */
23297044 1726static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1727 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1728 uint32_t latency)
1729{
1730 uint32_t ret;
1731
3312ba65
VS		 1732 if (WARN(latency == 0, "Latency value missing\n"))
1733 return UINT_MAX;
15126882
MR		 1734 if (WARN_ON(!pipe_htotal))
1735 return UINT_MAX;
3312ba65 1736
801bcfff 1737 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1738 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1739 ret = DIV_ROUND_UP(ret, 64) + 2;
1740 return ret;
1741}
1742
23297044 1743static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1744 uint8_t cpp)
cca32e9a 1745{
15126882
MR		 1746 /*
1747 * Neither of these should be possible since this function shouldn't be
1748 * called if the CRTC is off or the plane is invisible. But let's be
1749 * extra paranoid to avoid a potential divide-by-zero if we screw up
1750 * elsewhere in the driver.
1751 */
ac484963 1752 if (WARN_ON(!cpp))
15126882
MR		 1753 return 0;
1754 if (WARN_ON(!horiz_pixels))
1755 return 0;
1756
ac484963 1757 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1758}
1759
820c1980 1760struct ilk_wm_maximums {
cca32e9a
PZ		 1761 uint16_t pri;
1762 uint16_t spr;
1763 uint16_t cur;
1764 uint16_t fbc;
1765};
1766
37126462
VS		 1767/*
1768 * For both WM_PIPE and WM_LP.
1769 * mem_value must be in 0.1us units.
1770 */
7221fc33 1771static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1772 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1773 uint32_t mem_value,
1774 bool is_lp)
801bcfff 1775{
ac484963
VS		 1776 int cpp = pstate->base.fb ?
1777 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1778 uint32_t method1, method2;
1779
936e71e3 1780 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1781 return 0;
1782
ac484963 1783 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1784
1785 if (!is_lp)
1786 return method1;
1787
7221fc33
MR		 1788 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1790 drm_rect_width(&pstate->base.dst),
ac484963 1791 cpp, mem_value);
cca32e9a
PZ		 1792
1793 return min(method1, method2);
801bcfff
PZ		 1794}
1795
37126462
VS		 1796/*
1797 * For both WM_PIPE and WM_LP.
1798 * mem_value must be in 0.1us units.
1799 */
7221fc33 1800static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1801 const struct intel_plane_state *pstate,
801bcfff
PZ		 1802 uint32_t mem_value)
1803{
ac484963
VS		 1804 int cpp = pstate->base.fb ?
1805 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1806 uint32_t method1, method2;
1807
936e71e3 1808 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1809 return 0;
1810
ac484963 1811 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1812 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1813 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1814 drm_rect_width(&pstate->base.dst),
ac484963 1815 cpp, mem_value);
801bcfff
PZ		 1816 return min(method1, method2);
1817}
1818
37126462
VS		 1819/*
1820 * For both WM_PIPE and WM_LP.
1821 * mem_value must be in 0.1us units.
1822 */
7221fc33 1823static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1824 const struct intel_plane_state *pstate,
801bcfff
PZ		 1825 uint32_t mem_value)
1826{
b2435692
MR		 1827 /*
1828 * We treat the cursor plane as always-on for the purposes of watermark
1829 * calculation. Until we have two-stage watermark programming merged,
1830 * this is necessary to avoid flickering.
1831 */
1832 int cpp = 4;
936e71e3 1833 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1834
b2435692 1835 if (!cstate->base.active)
801bcfff
PZ		 1836 return 0;
1837
7221fc33
MR		 1838 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1839 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1840 width, cpp, mem_value);
801bcfff
PZ		 1841}
1842
cca32e9a 1843/* Only for WM_LP. */
7221fc33 1844static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1845 const struct intel_plane_state *pstate,
1fda9882 1846 uint32_t pri_val)
cca32e9a 1847{
ac484963
VS		 1848 int cpp = pstate->base.fb ?
1849 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1850
936e71e3 1851 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1852 return 0;
1853
936e71e3 1854 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1855}
1856
158ae64f
VS		 1857static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1858{
416f4727
VS		 1859 if (INTEL_INFO(dev)->gen >= 8)
1860 return 3072;
1861 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1862 return 768;
1863 else
1864 return 512;
1865}
1866
4e975081
VS		 1867static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1868 int level, bool is_sprite)
1869{
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 /* BDW primary/sprite plane watermarks */
1872 return level == 0 ? 255 : 2047;
1873 else if (INTEL_INFO(dev)->gen >= 7)
1874 /* IVB/HSW primary/sprite plane watermarks */
1875 return level == 0 ? 127 : 1023;
1876 else if (!is_sprite)
1877 /* ILK/SNB primary plane watermarks */
1878 return level == 0 ? 127 : 511;
1879 else
1880 /* ILK/SNB sprite plane watermarks */
1881 return level == 0 ? 63 : 255;
1882}
1883
1884static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1885 int level)
1886{
1887 if (INTEL_INFO(dev)->gen >= 7)
1888 return level == 0 ? 63 : 255;
1889 else
1890 return level == 0 ? 31 : 63;
1891}
1892
1893static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1894{
1895 if (INTEL_INFO(dev)->gen >= 8)
1896 return 31;
1897 else
1898 return 15;
1899}
1900
158ae64f
VS		 1901/* Calculate the maximum primary/sprite plane watermark */
1902static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1903 int level,
240264f4 1904 const struct intel_wm_config *config,
158ae64f
VS		 1905 enum intel_ddb_partitioning ddb_partitioning,
1906 bool is_sprite)
1907{
1908 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1909
1910 /* if sprites aren't enabled, sprites get nothing */
240264f4 1911 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1912 return 0;
1913
1914 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1915 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1916 fifo_size /= INTEL_INFO(dev)->num_pipes;
1917
1918 /*
1919 * For some reason the non self refresh
1920 * FIFO size is only half of the self
1921 * refresh FIFO size on ILK/SNB.
1922 */
1923 if (INTEL_INFO(dev)->gen <= 6)
1924 fifo_size /= 2;
1925 }
1926
240264f4 1927 if (config->sprites_enabled) {
158ae64f
VS		 1928 /* level 0 is always calculated with 1:1 split */
1929 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1930 if (is_sprite)
1931 fifo_size *= 5;
1932 fifo_size /= 6;
1933 } else {
1934 fifo_size /= 2;
1935 }
1936 }
1937
1938 /* clamp to max that the registers can hold */
4e975081 1939 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1940}
1941
1942/* Calculate the maximum cursor plane watermark */
1943static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1944 int level,
1945 const struct intel_wm_config *config)
158ae64f
VS		 1946{
1947 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1948 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1949 return 64;
1950
1951 /* otherwise just report max that registers can hold */
4e975081 1952 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1953}
1954
d34ff9c6 1955static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1956 int level,
1957 const struct intel_wm_config *config,
1958 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1959 struct ilk_wm_maximums *max)
158ae64f 1960{
240264f4
VS		 1961 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1962 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1963 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1964 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1965}
1966
a3cb4048
VS		 1967static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1968 int level,
1969 struct ilk_wm_maximums *max)
1970{
1971 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1972 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1973 max->cur = ilk_cursor_wm_reg_max(dev, level);
1974 max->fbc = ilk_fbc_wm_reg_max(dev);
1975}
1976
d9395655 1977static bool ilk_validate_wm_level(int level,
820c1980 1978 const struct ilk_wm_maximums *max,
d9395655 1979 struct intel_wm_level *result)
a9786a11
VS		 1980{
1981 bool ret;
1982
1983 /* already determined to be invalid? */
1984 if (!result->enable)
1985 return false;
1986
1987 result->enable = result->pri_val <= max->pri &&
1988 result->spr_val <= max->spr &&
1989 result->cur_val <= max->cur;
1990
1991 ret = result->enable;
1992
1993 /*
1994 * HACK until we can pre-compute everything,
1995 * and thus fail gracefully if LP0 watermarks
1996 * are exceeded...
1997 */
1998 if (level == 0 && !result->enable) {
1999 if (result->pri_val > max->pri)
2000 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2001 level, result->pri_val, max->pri);
2002 if (result->spr_val > max->spr)
2003 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2004 level, result->spr_val, max->spr);
2005 if (result->cur_val > max->cur)
2006 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2007 level, result->cur_val, max->cur);
2008
2009 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2010 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2011 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2012 result->enable = true;
2013 }
2014
a9786a11
VS		 2015 return ret;
2016}
2017
d34ff9c6 2018static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2019 const struct intel_crtc *intel_crtc,
6f5ddd17 2020 int level,
7221fc33 2021 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2022 struct intel_plane_state *pristate,
2023 struct intel_plane_state *sprstate,
2024 struct intel_plane_state *curstate,
1fd527cc 2025 struct intel_wm_level *result)
6f5ddd17
VS		 2026{
2027 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2028 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2029 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2030
2031 /* WM1+ latency values stored in 0.5us units */
2032 if (level > 0) {
2033 pri_latency *= 5;
2034 spr_latency *= 5;
2035 cur_latency *= 5;
2036 }
2037
e3bddded
ML		 2038 if (pristate) {
2039 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2040 pri_latency, level);
2041 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2042 }
2043
2044 if (sprstate)
2045 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2046
2047 if (curstate)
2048 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2049
6f5ddd17
VS		 2050 result->enable = true;
2051}
2052
801bcfff 2053static uint32_t
532f7a7f 2054hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2055{
532f7a7f
VS		 2056 const struct intel_atomic_state *intel_state =
2057 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2058 const struct drm_display_mode *adjusted_mode =
2059 &cstate->base.adjusted_mode;
85a02deb 2060 u32 linetime, ips_linetime;
1f8eeabf 2061
ee91a159
MR		 2062 if (!cstate->base.active)
2063 return 0;
2064 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2065 return 0;
532f7a7f 2066 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2067 return 0;
1011d8c4 2068
1f8eeabf
ED		 2069 /* The WM are computed with base on how long it takes to fill a single
2070 * row at the given clock rate, multiplied by 8.
2071 * */
124abe07
VS		 2072 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073 adjusted_mode->crtc_clock);
2074 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2075 intel_state->cdclk);
1f8eeabf 2076
801bcfff
PZ		 2077 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2078 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2079}
2080
2af30a5c 2081static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2082{
fac5e23e 2083 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2084
5db94019 2085 if (IS_GEN9(dev_priv)) {
2af30a5c 2086 uint32_t val;
4f947386 2087 int ret, i;
5db94019 2088 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2089
2090 /* read the first set of memory latencies[0:3] */
2091 val = 0; /* data0 to be programmed to 0 for first set */
2092 mutex_lock(&dev_priv->rps.hw_lock);
2093 ret = sandybridge_pcode_read(dev_priv,
2094 GEN9_PCODE_READ_MEM_LATENCY,
2095 &val);
2096 mutex_unlock(&dev_priv->rps.hw_lock);
2097
2098 if (ret) {
2099 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2100 return;
2101 }
2102
2103 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2109 GEN9_MEM_LATENCY_LEVEL_MASK;
2110
2111 /* read the second set of memory latencies[4:7] */
2112 val = 1; /* data0 to be programmed to 1 for second set */
2113 mutex_lock(&dev_priv->rps.hw_lock);
2114 ret = sandybridge_pcode_read(dev_priv,
2115 GEN9_PCODE_READ_MEM_LATENCY,
2116 &val);
2117 mutex_unlock(&dev_priv->rps.hw_lock);
2118 if (ret) {
2119 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120 return;
2121 }
2122
2123 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
0727e40a
PZ		 2131 /*
2132 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2133 * need to be disabled. We make sure to sanitize the values out
2134 * of the punit to satisfy this requirement.
2135 */
2136 for (level = 1; level <= max_level; level++) {
2137 if (wm[level] == 0) {
2138 for (i = level + 1; i <= max_level; i++)
2139 wm[i] = 0;
2140 break;
2141 }
2142 }
2143
367294be 2144 /*
6f97235b
DL		 2145 * WaWmMemoryReadLatency:skl
2146 *
367294be 2147 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2148 * to add 2us to the various latency levels we retrieve from the
2149 * punit when level 0 response data us 0us.
367294be 2150 */
0727e40a
PZ		 2151 if (wm[0] == 0) {
2152 wm[0] += 2;
2153 for (level = 1; level <= max_level; level++) {
2154 if (wm[level] == 0)
2155 break;
367294be 2156 wm[level] += 2;
4f947386 2157 }
0727e40a
PZ		 2158 }
2159
8652744b 2160 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2161 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2162
2163 wm[0] = (sskpd >> 56) & 0xFF;
2164 if (wm[0] == 0)
2165 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2166 wm[1] = (sskpd >> 4) & 0xFF;
2167 wm[2] = (sskpd >> 12) & 0xFF;
2168 wm[3] = (sskpd >> 20) & 0x1FF;
2169 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2170 } else if (INTEL_INFO(dev)->gen >= 6) {
2171 uint32_t sskpd = I915_READ(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2174 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2175 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2176 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2177 } else if (INTEL_INFO(dev)->gen >= 5) {
2178 uint32_t mltr = I915_READ(MLTR_ILK);
2179
2180 /* ILK primary LP0 latency is 700 ns */
2181 wm[0] = 7;
2182 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2183 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2184 }
2185}
2186
5db94019
TU		 2187static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2188 uint16_t wm[5])
53615a5e
VS		 2189{
2190 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2191 if (IS_GEN5(dev_priv))
53615a5e
VS		 2192 wm[0] = 13;
2193}
2194
fd6b8f43
TU		 2195static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2196 uint16_t wm[5])
53615a5e
VS		 2197{
2198 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2199 if (IS_GEN5(dev_priv))
53615a5e
VS		 2200 wm[0] = 13;
2201
2202 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2203 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2204 wm[3] *= 2;
2205}
2206
5db94019 2207int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2208{
26ec971e 2209 /* how many WM levels are we expecting */
8652744b 2210 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2211 return 7;
8652744b 2212 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2213 return 4;
8652744b 2214 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2215 return 3;
26ec971e 2216 else
ad0d6dc4
VS		 2217 return 2;
2218}
7526ed79 2219
5db94019 2220static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2221 const char *name,
2af30a5c 2222 const uint16_t wm[8])
ad0d6dc4 2223{
5db94019 2224 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2225
2226 for (level = 0; level <= max_level; level++) {
2227 unsigned int latency = wm[level];
2228
2229 if (latency == 0) {
2230 DRM_ERROR("%s WM%d latency not provided\n",
2231 name, level);
2232 continue;
2233 }
2234
2af30a5c
PB		 2235 /*
2236 * - latencies are in us on gen9.
2237 * - before then, WM1+ latency values are in 0.5us units
2238 */
5db94019 2239 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2240 latency *= 10;
2241 else if (level > 0)
26ec971e
VS		 2242 latency *= 5;
2243
2244 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2245 name, level, wm[level],
2246 latency / 10, latency % 10);
2247 }
2248}
2249
e95a2f75
VS		 2250static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2251 uint16_t wm[5], uint16_t min)
2252{
5db94019 2253 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2254
2255 if (wm[0] >= min)
2256 return false;
2257
2258 wm[0] = max(wm[0], min);
2259 for (level = 1; level <= max_level; level++)
2260 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2261
2262 return true;
2263}
2264
2265static void snb_wm_latency_quirk(struct drm_device *dev)
2266{
fac5e23e 2267 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2268 bool changed;
2269
2270 /*
2271 * The BIOS provided WM memory latency values are often
2272 * inadequate for high resolution displays. Adjust them.
2273 */
2274 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2275 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2276 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2277
2278 if (!changed)
2279 return;
2280
2281 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2282 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2283 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2284 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2285}
2286
fa50ad61 2287static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2288{
fac5e23e 2289 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2290
2291 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2292
2293 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2294 sizeof(dev_priv->wm.pri_latency));
2295 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2296 sizeof(dev_priv->wm.pri_latency));
2297
5db94019 2298 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2299 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2300
5db94019
TU		 2301 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2302 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2303 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2304
5db94019 2305 if (IS_GEN6(dev_priv))
e95a2f75 2306 snb_wm_latency_quirk(dev);
53615a5e
VS		 2307}
2308
2af30a5c
PB		 2309static void skl_setup_wm_latency(struct drm_device *dev)
2310{
fac5e23e 2311 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2312
2313 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
5db94019 2314 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2315}
2316
ed4a6a7c
MR		 2317static bool ilk_validate_pipe_wm(struct drm_device *dev,
2318 struct intel_pipe_wm *pipe_wm)
2319{
2320 /* LP0 watermark maximums depend on this pipe alone */
2321 const struct intel_wm_config config = {
2322 .num_pipes_active = 1,
2323 .sprites_enabled = pipe_wm->sprites_enabled,
2324 .sprites_scaled = pipe_wm->sprites_scaled,
2325 };
2326 struct ilk_wm_maximums max;
2327
2328 /* LP0 watermarks always use 1/2 DDB partitioning */
2329 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2330
2331 /* At least LP0 must be valid */
2332 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2333 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2334 return false;
2335 }
2336
2337 return true;
2338}
2339
0b2ae6d7 2340/* Compute new watermarks for the pipe */
e3bddded 2341static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2342{
e3bddded
ML		 2343 struct drm_atomic_state *state = cstate->base.state;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2345 struct intel_pipe_wm *pipe_wm;
e3bddded 2346 struct drm_device *dev = state->dev;
fac5e23e 2347 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2348 struct intel_plane *intel_plane;
86c8bbbe 2349 struct intel_plane_state *pristate = NULL;
43d59eda 2350 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2351 struct intel_plane_state *curstate = NULL;
5db94019 2352 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2353 struct ilk_wm_maximums max;
0b2ae6d7 2354
e8f1f02e 2355 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2356
43d59eda 2357 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2358 struct intel_plane_state *ps;
2359
2360 ps = intel_atomic_get_existing_plane_state(state,
2361 intel_plane);
2362 if (!ps)
2363 continue;
86c8bbbe
MR		 2364
2365 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2366 pristate = ps;
86c8bbbe 2367 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2368 sprstate = ps;
86c8bbbe 2369 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2370 curstate = ps;
43d59eda
MR		 2371 }
2372
ed4a6a7c 2373 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2374 if (sprstate) {
936e71e3
VS		 2375 pipe_wm->sprites_enabled = sprstate->base.visible;
2376 pipe_wm->sprites_scaled = sprstate->base.visible &&
2377 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2378 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2379 }
2380
d81f04c5
ML		 2381 usable_level = max_level;
2382
7b39a0b7 2383 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2384 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2385 usable_level = 1;
7b39a0b7
VS		 2386
2387 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2388 if (pipe_wm->sprites_scaled)
d81f04c5 2389 usable_level = 0;
7b39a0b7 2390
86c8bbbe 2391 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2392 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2393
2394 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2395 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2396
8652744b 2397 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2398 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2399
ed4a6a7c 2400 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2401 return -EINVAL;
a3cb4048
VS		 2402
2403 ilk_compute_wm_reg_maximums(dev, 1, &max);
2404
2405 for (level = 1; level <= max_level; level++) {
71f0a626 2406 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2407
86c8bbbe 2408 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2409 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2410
2411 /*
2412 * Disable any watermark level that exceeds the
2413 * register maximums since such watermarks are
2414 * always invalid.
2415 */
71f0a626
ML		 2416 if (level > usable_level)
2417 continue;
2418
2419 if (ilk_validate_wm_level(level, &max, wm))
2420 pipe_wm->wm[level] = *wm;
2421 else
d81f04c5 2422 usable_level = level;
a3cb4048
VS		 2423 }
2424
86c8bbbe 2425 return 0;
0b2ae6d7
VS		 2426}
2427
ed4a6a7c
MR		 2428/*
2429 * Build a set of 'intermediate' watermark values that satisfy both the old
2430 * state and the new state. These can be programmed to the hardware
2431 * immediately.
2432 */
2433static int ilk_compute_intermediate_wm(struct drm_device *dev,
2434 struct intel_crtc *intel_crtc,
2435 struct intel_crtc_state *newstate)
2436{
e8f1f02e 2437 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2438 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2439 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2440
2441 /*
2442 * Start with the final, target watermarks, then combine with the
2443 * currently active watermarks to get values that are safe both before
2444 * and after the vblank.
2445 */
e8f1f02e 2446 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2447 a->pipe_enabled |= b->pipe_enabled;
2448 a->sprites_enabled |= b->sprites_enabled;
2449 a->sprites_scaled |= b->sprites_scaled;
2450
2451 for (level = 0; level <= max_level; level++) {
2452 struct intel_wm_level *a_wm = &a->wm[level];
2453 const struct intel_wm_level *b_wm = &b->wm[level];
2454
2455 a_wm->enable &= b_wm->enable;
2456 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2457 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2458 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2459 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2460 }
2461
2462 /*
2463 * We need to make sure that these merged watermark values are
2464 * actually a valid configuration themselves. If they're not,
2465 * there's no safe way to transition from the old state to
2466 * the new state, so we need to fail the atomic transaction.
2467 */
2468 if (!ilk_validate_pipe_wm(dev, a))
2469 return -EINVAL;
2470
2471 /*
2472 * If our intermediate WM are identical to the final WM, then we can
2473 * omit the post-vblank programming; only update if it's different.
2474 */
e8f1f02e 2475 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2476 newstate->wm.need_postvbl_update = false;
2477
2478 return 0;
2479}
2480
0b2ae6d7
VS		 2481/*
2482 * Merge the watermarks from all active pipes for a specific level.
2483 */
2484static void ilk_merge_wm_level(struct drm_device *dev,
2485 int level,
2486 struct intel_wm_level *ret_wm)
2487{
2488 const struct intel_crtc *intel_crtc;
2489
d52fea5b
VS		 2490 ret_wm->enable = true;
2491
d3fcc808 2492 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2493 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2494 const struct intel_wm_level *wm = &active->wm[level];
2495
2496 if (!active->pipe_enabled)
2497 continue;
0b2ae6d7 2498
d52fea5b
VS		 2499 /*
2500 * The watermark values may have been used in the past,
2501 * so we must maintain them in the registers for some
2502 * time even if the level is now disabled.
2503 */
0b2ae6d7 2504 if (!wm->enable)
d52fea5b 2505 ret_wm->enable = false;
0b2ae6d7
VS		 2506
2507 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2508 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2509 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2510 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2511 }
0b2ae6d7
VS		 2512}
2513
2514/*
2515 * Merge all low power watermarks for all active pipes.
2516 */
2517static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2518 const struct intel_wm_config *config,
820c1980 2519 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2520 struct intel_pipe_wm *merged)
2521{
fac5e23e 2522 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2523 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2524 int last_enabled_level = max_level;
0b2ae6d7 2525
0ba22e26 2526 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2527 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2528 config->num_pipes_active > 1)
1204d5ba 2529 last_enabled_level = 0;
0ba22e26 2530
6c8b6c28
VS		 2531 /* ILK: FBC WM must be disabled always */
2532 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2533
2534 /* merge each WM1+ level */
2535 for (level = 1; level <= max_level; level++) {
2536 struct intel_wm_level *wm = &merged->wm[level];
2537
2538 ilk_merge_wm_level(dev, level, wm);
2539
d52fea5b
VS		 2540 if (level > last_enabled_level)
2541 wm->enable = false;
2542 else if (!ilk_validate_wm_level(level, max, wm))
2543 /* make sure all following levels get disabled */
2544 last_enabled_level = level - 1;
0b2ae6d7
VS		 2545
2546 /*
2547 * The spec says it is preferred to disable
2548 * FBC WMs instead of disabling a WM level.
2549 */
2550 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2551 if (wm->enable)
2552 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2553 wm->fbc_val = 0;
2554 }
2555 }
6c8b6c28
VS		 2556
2557 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2558 /*
2559 * FIXME this is racy. FBC might get enabled later.
2560 * What we should check here is whether FBC can be
2561 * enabled sometime later.
2562 */
5db94019 2563 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2564 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2565 for (level = 2; level <= max_level; level++) {
2566 struct intel_wm_level *wm = &merged->wm[level];
2567
2568 wm->enable = false;
2569 }
2570 }
0b2ae6d7
VS		 2571}
2572
b380ca3c
VS		 2573static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2574{
2575 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2576 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2577}
2578
a68d68ee
VS		 2579/* The value we need to program into the WM_LPx latency field */
2580static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2581{
fac5e23e 2582 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2583
8652744b 2584 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2585 return 2 * level;
2586 else
2587 return dev_priv->wm.pri_latency[level];
2588}
2589
820c1980 2590static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2591 const struct intel_pipe_wm *merged,
609cedef 2592 enum intel_ddb_partitioning partitioning,
820c1980 2593 struct ilk_wm_values *results)
801bcfff 2594{
0b2ae6d7
VS		 2595 struct intel_crtc *intel_crtc;
2596 int level, wm_lp;
cca32e9a 2597
0362c781 2598 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2599 results->partitioning = partitioning;
cca32e9a 2600
0b2ae6d7 2601 /* LP1+ register values */
cca32e9a 2602 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2603 const struct intel_wm_level *r;
801bcfff 2604
b380ca3c 2605 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2606
0362c781 2607 r = &merged->wm[level];
cca32e9a 2608
d52fea5b
VS		 2609 /*
2610 * Maintain the watermark values even if the level is
2611 * disabled. Doing otherwise could cause underruns.
2612 */
2613 results->wm_lp[wm_lp - 1] =
a68d68ee 2614 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2615 (r->pri_val << WM1_LP_SR_SHIFT) |
2616 r->cur_val;
2617
d52fea5b
VS		 2618 if (r->enable)
2619 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2620
416f4727
VS		 2621 if (INTEL_INFO(dev)->gen >= 8)
2622 results->wm_lp[wm_lp - 1] |=
2623 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2624 else
2625 results->wm_lp[wm_lp - 1] |=
2626 r->fbc_val << WM1_LP_FBC_SHIFT;
2627
d52fea5b
VS		 2628 /*
2629 * Always set WM1S_LP_EN when spr_val != 0, even if the
2630 * level is disabled. Doing otherwise could cause underruns.
2631 */
6cef2b8a
VS		 2632 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2633 WARN_ON(wm_lp != 1);
2634 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2635 } else
2636 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2637 }
801bcfff 2638
0b2ae6d7 2639 /* LP0 register values */
d3fcc808 2640 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2641 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2642 const struct intel_wm_level *r =
2643 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2644
2645 if (WARN_ON(!r->enable))
2646 continue;
2647
ed4a6a7c 2648 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2649
0b2ae6d7
VS		 2650 results->wm_pipe[pipe] =
2651 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2652 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2653 r->cur_val;
801bcfff
PZ		 2654 }
2655}
2656
861f3389
PZ		 2657/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2658 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2659static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2660 struct intel_pipe_wm *r1,
2661 struct intel_pipe_wm *r2)
861f3389 2662{
5db94019 2663 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2664 int level1 = 0, level2 = 0;
861f3389 2665
198a1e9b
VS		 2666 for (level = 1; level <= max_level; level++) {
2667 if (r1->wm[level].enable)
2668 level1 = level;
2669 if (r2->wm[level].enable)
2670 level2 = level;
861f3389
PZ		 2671 }
2672
198a1e9b
VS		 2673 if (level1 == level2) {
2674 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2675 return r2;
2676 else
2677 return r1;
198a1e9b 2678 } else if (level1 > level2) {
861f3389
PZ		 2679 return r1;
2680 } else {
2681 return r2;
2682 }
2683}
2684
49a687c4
VS		 2685/* dirty bits used to track which watermarks need changes */
2686#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2687#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2688#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2689#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2690#define WM_DIRTY_FBC (1 << 24)
2691#define WM_DIRTY_DDB (1 << 25)
2692
055e393f 2693static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2694 const struct ilk_wm_values *old,
2695 const struct ilk_wm_values *new)
49a687c4
VS		 2696{
2697 unsigned int dirty = 0;
2698 enum pipe pipe;
2699 int wm_lp;
2700
055e393f 2701 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2702 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2703 dirty |= WM_DIRTY_LINETIME(pipe);
2704 /* Must disable LP1+ watermarks too */
2705 dirty |= WM_DIRTY_LP_ALL;
2706 }
2707
2708 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2709 dirty |= WM_DIRTY_PIPE(pipe);
2710 /* Must disable LP1+ watermarks too */
2711 dirty |= WM_DIRTY_LP_ALL;
2712 }
2713 }
2714
2715 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2716 dirty |= WM_DIRTY_FBC;
2717 /* Must disable LP1+ watermarks too */
2718 dirty |= WM_DIRTY_LP_ALL;
2719 }
2720
2721 if (old->partitioning != new->partitioning) {
2722 dirty |= WM_DIRTY_DDB;
2723 /* Must disable LP1+ watermarks too */
2724 dirty |= WM_DIRTY_LP_ALL;
2725 }
2726
2727 /* LP1+ watermarks already deemed dirty, no need to continue */
2728 if (dirty & WM_DIRTY_LP_ALL)
2729 return dirty;
2730
2731 /* Find the lowest numbered LP1+ watermark in need of an update... */
2732 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2733 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2734 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2735 break;
2736 }
2737
2738 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2739 for (; wm_lp <= 3; wm_lp++)
2740 dirty |= WM_DIRTY_LP(wm_lp);
2741
2742 return dirty;
2743}
2744
8553c18e
VS		 2745static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2746 unsigned int dirty)
801bcfff 2747{
820c1980 2748 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2749 bool changed = false;
801bcfff 2750
facd619b
VS		 2751 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2752 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2753 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2754 changed = true;
facd619b
VS		 2755 }
2756 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2757 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2758 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2759 changed = true;
facd619b
VS		 2760 }
2761 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2762 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2763 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2764 changed = true;
facd619b 2765 }
801bcfff 2766
facd619b
VS		 2767 /*
2768 * Don't touch WM1S_LP_EN here.
2769 * Doing so could cause underruns.
2770 */
6cef2b8a 2771
8553c18e
VS		 2772 return changed;
2773}
2774
2775/*
2776 * The spec says we shouldn't write when we don't need, because every write
2777 * causes WMs to be re-evaluated, expending some power.
2778 */
820c1980
ID		 2779static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2780 struct ilk_wm_values *results)
8553c18e 2781{
91c8a326 2782 struct drm_device *dev = &dev_priv->drm;
820c1980 2783 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2784 unsigned int dirty;
2785 uint32_t val;
2786
055e393f 2787 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2788 if (!dirty)
2789 return;
2790
2791 _ilk_disable_lp_wm(dev_priv, dirty);
2792
49a687c4 2793 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2794 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2795 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2796 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2797 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2798 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2799
49a687c4 2800 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2801 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2802 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2803 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2804 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2805 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2806
49a687c4 2807 if (dirty & WM_DIRTY_DDB) {
8652744b 2808 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2809 val = I915_READ(WM_MISC);
2810 if (results->partitioning == INTEL_DDB_PART_1_2)
2811 val &= ~WM_MISC_DATA_PARTITION_5_6;
2812 else
2813 val |= WM_MISC_DATA_PARTITION_5_6;
2814 I915_WRITE(WM_MISC, val);
2815 } else {
2816 val = I915_READ(DISP_ARB_CTL2);
2817 if (results->partitioning == INTEL_DDB_PART_1_2)
2818 val &= ~DISP_DATA_PARTITION_5_6;
2819 else
2820 val |= DISP_DATA_PARTITION_5_6;
2821 I915_WRITE(DISP_ARB_CTL2, val);
2822 }
1011d8c4
PZ		 2823 }
2824
49a687c4 2825 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2826 val = I915_READ(DISP_ARB_CTL);
2827 if (results->enable_fbc_wm)
2828 val &= ~DISP_FBC_WM_DIS;
2829 else
2830 val |= DISP_FBC_WM_DIS;
2831 I915_WRITE(DISP_ARB_CTL, val);
2832 }
2833
954911eb
ID		 2834 if (dirty & WM_DIRTY_LP(1) &&
2835 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2836 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2837
2838 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2839 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2840 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2841 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2842 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2843 }
801bcfff 2844
facd619b 2845 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2846 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2847 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2848 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2849 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2850 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2851
2852 dev_priv->wm.hw = *results;
801bcfff
PZ		 2853}
2854
ed4a6a7c 2855bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2856{
fac5e23e 2857 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2858
2859 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2860}
2861
656d1b89 2862#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2863
024c9045
MR		 2864/*
2865 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2866 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2867 * other universal planes are in indices 1..n. Note that this may leave unused
2868 * indices between the top "sprite" plane and the cursor.
2869 */
2870static int
2871skl_wm_plane_id(const struct intel_plane *plane)
2872{
2873 switch (plane->base.type) {
2874 case DRM_PLANE_TYPE_PRIMARY:
2875 return 0;
2876 case DRM_PLANE_TYPE_CURSOR:
2877 return PLANE_CURSOR;
2878 case DRM_PLANE_TYPE_OVERLAY:
2879 return plane->plane + 1;
2880 default:
2881 MISSING_CASE(plane->base.type);
2882 return plane->plane;
2883 }
2884}
2885
56feca91
PZ		 2886static bool
2887intel_has_sagv(struct drm_i915_private *dev_priv)
2888{
6e3100ec
PZ		 2889 if (IS_KABYLAKE(dev_priv))
2890 return true;
2891
2892 if (IS_SKYLAKE(dev_priv) &&
2893 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2894 return true;
2895
2896 return false;
56feca91
PZ		 2897}
2898
656d1b89
L		 2899/*
2900 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2901 * depending on power and performance requirements. The display engine access
2902 * to system memory is blocked during the adjustment time. Because of the
2903 * blocking time, having this enabled can cause full system hangs and/or pipe
2904 * underruns if we don't meet all of the following requirements:
2905 *
2906 * - <= 1 pipe enabled
2907 * - All planes can enable watermarks for latencies >= SAGV engine block time
2908 * - We're not using an interlaced display configuration
2909 */
2910int
16dcdc4e 2911intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2912{
2913 int ret;
2914
56feca91
PZ		 2915 if (!intel_has_sagv(dev_priv))
2916 return 0;
2917
2918 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2919 return 0;
2920
2921 DRM_DEBUG_KMS("Enabling the SAGV\n");
2922 mutex_lock(&dev_priv->rps.hw_lock);
2923
2924 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2925 GEN9_SAGV_ENABLE);
2926
2927 /* We don't need to wait for the SAGV when enabling */
2928 mutex_unlock(&dev_priv->rps.hw_lock);
2929
2930 /*
2931 * Some skl systems, pre-release machines in particular,
2932 * don't actually have an SAGV.
2933 */
6e3100ec 2934 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2935 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2936 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2937 return 0;
2938 } else if (ret < 0) {
2939 DRM_ERROR("Failed to enable the SAGV\n");
2940 return ret;
2941 }
2942
16dcdc4e 2943 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2944 return 0;
2945}
2946
2947static int
16dcdc4e 2948intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2949{
2950 int ret;
2951 uint32_t temp = GEN9_SAGV_DISABLE;
2952
2953 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2954 &temp);
2955 if (ret)
2956 return ret;
2957 else
2958 return temp & GEN9_SAGV_IS_DISABLED;
2959}
2960
2961int
16dcdc4e 2962intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2963{
2964 int ret, result;
2965
56feca91
PZ		 2966 if (!intel_has_sagv(dev_priv))
2967 return 0;
2968
2969 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2970 return 0;
2971
2972 DRM_DEBUG_KMS("Disabling the SAGV\n");
2973 mutex_lock(&dev_priv->rps.hw_lock);
2974
2975 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2976 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2977 mutex_unlock(&dev_priv->rps.hw_lock);
2978
2979 if (ret == -ETIMEDOUT) {
2980 DRM_ERROR("Request to disable SAGV timed out\n");
2981 return -ETIMEDOUT;
2982 }
2983
2984 /*
2985 * Some skl systems, pre-release machines in particular,
2986 * don't actually have an SAGV.
2987 */
6e3100ec 2988 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 2989 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2990 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2991 return 0;
2992 } else if (result < 0) {
2993 DRM_ERROR("Failed to disable the SAGV\n");
2994 return result;
2995 }
2996
16dcdc4e 2997 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 2998 return 0;
2999}
3000
16dcdc4e 3001bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3002{
3003 struct drm_device *dev = state->dev;
3004 struct drm_i915_private *dev_priv = to_i915(dev);
3005 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3006 struct drm_crtc *crtc;
3007 enum pipe pipe;
3008 int level, plane;
3009
56feca91
PZ		 3010 if (!intel_has_sagv(dev_priv))
3011 return false;
3012
656d1b89
L		 3013 /*
3014 * SKL workaround: bspec recommends we disable the SAGV when we have
3015 * more then one pipe enabled
3016 *
3017 * If there are no active CRTCs, no additional checks need be performed
3018 */
3019 if (hweight32(intel_state->active_crtcs) == 0)
3020 return true;
3021 else if (hweight32(intel_state->active_crtcs) > 1)
3022 return false;
3023
3024 /* Since we're now guaranteed to only have one active CRTC... */
3025 pipe = ffs(intel_state->active_crtcs) - 1;
3026 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3027
3028 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3029 return false;
3030
3031 for_each_plane(dev_priv, pipe, plane) {
3032 /* Skip this plane if it's not enabled */
3033 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3034 continue;
3035
3036 /* Find the highest enabled wm level for this plane */
5db94019 3037 for (level = ilk_wm_max_level(dev_priv);
656d1b89
L		 3038 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3039 { }
3040
3041 /*
3042 * If any of the planes on this pipe don't enable wm levels
3043 * that incur memory latencies higher then 30µs we can't enable
3044 * the SAGV
3045 */
3046 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3047 return false;
3048 }
3049
3050 return true;
3051}
3052
b9cec075
DL		 3053static void
3054skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3055 const struct intel_crtc_state *cstate,
c107acfe
MR		 3056 struct skl_ddb_entry *alloc, /* out */
3057 int *num_active /* out */)
b9cec075 3058{
c107acfe
MR		 3059 struct drm_atomic_state *state = cstate->base.state;
3060 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3061 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3062 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3063 unsigned int pipe_size, ddb_size;
3064 int nth_active_pipe;
c107acfe 3065
a6d3460e 3066 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3067 alloc->start = 0;
3068 alloc->end = 0;
a6d3460e 3069 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3070 return;
3071 }
3072
a6d3460e
MR		 3073 if (intel_state->active_pipe_changes)
3074 *num_active = hweight32(intel_state->active_crtcs);
3075 else
3076 *num_active = hweight32(dev_priv->active_crtcs);
3077
6f3fff60
D		 3078 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3079 WARN_ON(ddb_size == 0);
b9cec075
DL		 3080
3081 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3082
c107acfe 3083 /*
a6d3460e
MR		 3084 * If the state doesn't change the active CRTC's, then there's
3085 * no need to recalculate; the existing pipe allocation limits
3086 * should remain unchanged. Note that we're safe from racing
3087 * commits since any racing commit that changes the active CRTC
3088 * list would need to grab _all_ crtc locks, including the one
3089 * we currently hold.
c107acfe 3090 */
a6d3460e 3091 if (!intel_state->active_pipe_changes) {
ce0ba283 3092 *alloc = to_intel_crtc(for_crtc)->hw_ddb;
a6d3460e 3093 return;
c107acfe 3094 }
a6d3460e
MR		 3095
3096 nth_active_pipe = hweight32(intel_state->active_crtcs &
3097 (drm_crtc_mask(for_crtc) - 1));
3098 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3099 alloc->start = nth_active_pipe * ddb_size / *num_active;
3100 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3101}
3102
c107acfe 3103static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3104{
c107acfe 3105 if (num_active == 1)
b9cec075
DL		 3106 return 32;
3107
3108 return 8;
3109}
3110
a269c583
DL		 3111static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3112{
3113 entry->start = reg & 0x3ff;
3114 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3115 if (entry->end)
3116 entry->end += 1;
a269c583
DL		 3117}
3118
08db6652
DL		 3119void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3120 struct skl_ddb_allocation *ddb /* out */)
a269c583 3121{
a269c583
DL		 3122 enum pipe pipe;
3123 int plane;
3124 u32 val;
3125
b10f1b20
ML		 3126 memset(ddb, 0, sizeof(*ddb));
3127
a269c583 3128 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3129 enum intel_display_power_domain power_domain;
3130
3131 power_domain = POWER_DOMAIN_PIPE(pipe);
3132 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3133 continue;
3134
dd740780 3135 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3136 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3137 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3138 val);
3139 }
3140
3141 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3142 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3143 val);
4d800030
ID		 3144
3145 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3146 }
3147}
3148
9c2f7a9d
KM		 3149/*
3150 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3151 * The bspec defines downscale amount as:
3152 *
3153 * """
3154 * Horizontal down scale amount = maximum[1, Horizontal source size /
3155 * Horizontal destination size]
3156 * Vertical down scale amount = maximum[1, Vertical source size /
3157 * Vertical destination size]
3158 * Total down scale amount = Horizontal down scale amount *
3159 * Vertical down scale amount
3160 * """
3161 *
3162 * Return value is provided in 16.16 fixed point form to retain fractional part.
3163 * Caller should take care of dividing & rounding off the value.
3164 */
3165static uint32_t
3166skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3167{
3168 uint32_t downscale_h, downscale_w;
3169 uint32_t src_w, src_h, dst_w, dst_h;
3170
936e71e3 3171 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3172 return DRM_PLANE_HELPER_NO_SCALING;
3173
3174 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3175 src_w = drm_rect_width(&pstate->base.src);
3176 src_h = drm_rect_height(&pstate->base.src);
3177 dst_w = drm_rect_width(&pstate->base.dst);
3178 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3179 if (intel_rotation_90_or_270(pstate->base.rotation))
3180 swap(dst_w, dst_h);
3181
3182 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3183 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3184
3185 /* Provide result in 16.16 fixed point */
3186 return (uint64_t)downscale_w * downscale_h >> 16;
3187}
3188
b9cec075 3189static unsigned int
024c9045
MR		 3190skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3191 const struct drm_plane_state *pstate,
3192 int y)
b9cec075 3193{
a280f7dd 3194 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3195 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3196 uint32_t down_scale_amount, data_rate;
a280f7dd 3197 uint32_t width = 0, height = 0;
a1de91e5
MR		 3198 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3199
936e71e3 3200 if (!intel_pstate->base.visible)
a1de91e5
MR		 3201 return 0;
3202 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3203 return 0;
3204 if (y && format != DRM_FORMAT_NV12)
3205 return 0;
a280f7dd 3206
936e71e3
VS		 3207 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3208 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3209
3210 if (intel_rotation_90_or_270(pstate->rotation))
3211 swap(width, height);
2cd601c6
CK		 3212
3213 /* for planar format */
a1de91e5 3214 if (format == DRM_FORMAT_NV12) {
2cd601c6 3215 if (y) /* y-plane data rate */
8d19d7d9 3216 data_rate = width * height *
a1de91e5 3217 drm_format_plane_cpp(format, 0);
2cd601c6 3218 else /* uv-plane data rate */
8d19d7d9 3219 data_rate = (width / 2) * (height / 2) *
a1de91e5 3220 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3221 } else {
3222 /* for packed formats */
3223 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3224 }
3225
8d19d7d9
KM		 3226 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3227
3228 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3229}
3230
3231/*
3232 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3233 * a 8192x4096@32bpp framebuffer:
3234 * 3 * 4096 * 8192 * 4 < 2^32
3235 */
3236static unsigned int
9c74d826 3237skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3238{
9c74d826
MR		 3239 struct drm_crtc_state *cstate = &intel_cstate->base;
3240 struct drm_atomic_state *state = cstate->state;
3241 struct drm_crtc *crtc = cstate->crtc;
3242 struct drm_device *dev = crtc->dev;
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3244 const struct drm_plane *plane;
024c9045 3245 const struct intel_plane *intel_plane;
a6d3460e 3246 struct drm_plane_state *pstate;
a1de91e5 3247 unsigned int rate, total_data_rate = 0;
9c74d826 3248 int id;
a6d3460e
MR		 3249 int i;
3250
3251 if (WARN_ON(!state))
3252 return 0;
b9cec075 3253
a1de91e5 3254 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3255 for_each_plane_in_state(state, plane, pstate, i) {
3256 id = skl_wm_plane_id(to_intel_plane(plane));
3257 intel_plane = to_intel_plane(plane);
3258
3259 if (intel_plane->pipe != intel_crtc->pipe)
3260 continue;
3261
3262 /* packed/uv */
3263 rate = skl_plane_relative_data_rate(intel_cstate,
3264 pstate, 0);
3265 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3266
3267 /* y-plane */
3268 rate = skl_plane_relative_data_rate(intel_cstate,
3269 pstate, 1);
3270 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3271 }
024c9045 3272
a1de91e5
MR		 3273 /* Calculate CRTC's total data rate from cached values */
3274 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3275 int id = skl_wm_plane_id(intel_plane);
024c9045 3276
a1de91e5 3277 /* packed/uv */
9c74d826
MR		 3278 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3279 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3280 }
3281
3282 return total_data_rate;
3283}
3284
cbcfd14b
KM		 3285static uint16_t
3286skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3287 const int y)
3288{
3289 struct drm_framebuffer *fb = pstate->fb;
3290 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3291 uint32_t src_w, src_h;
3292 uint32_t min_scanlines = 8;
3293 uint8_t plane_bpp;
3294
3295 if (WARN_ON(!fb))
3296 return 0;
3297
3298 /* For packed formats, no y-plane, return 0 */
3299 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3300 return 0;
3301
3302 /* For Non Y-tile return 8-blocks */
3303 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3304 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3305 return 8;
3306
936e71e3
VS		 3307 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3308 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3309
3310 if (intel_rotation_90_or_270(pstate->rotation))
3311 swap(src_w, src_h);
3312
3313 /* Halve UV plane width and height for NV12 */
3314 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3315 src_w /= 2;
3316 src_h /= 2;
3317 }
3318
3319 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3320 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3321 else
3322 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3323
3324 if (intel_rotation_90_or_270(pstate->rotation)) {
3325 switch (plane_bpp) {
3326 case 1:
3327 min_scanlines = 32;
3328 break;
3329 case 2:
3330 min_scanlines = 16;
3331 break;
3332 case 4:
3333 min_scanlines = 8;
3334 break;
3335 case 8:
3336 min_scanlines = 4;
3337 break;
3338 default:
3339 WARN(1, "Unsupported pixel depth %u for rotation",
3340 plane_bpp);
3341 min_scanlines = 32;
3342 }
3343 }
3344
3345 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3346}
3347
c107acfe 3348static int
024c9045 3349skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3350 struct skl_ddb_allocation *ddb /* out */)
3351{
c107acfe 3352 struct drm_atomic_state *state = cstate->base.state;
024c9045 3353 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3354 struct drm_device *dev = crtc->dev;
3355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3356 struct intel_plane *intel_plane;
c107acfe
MR		 3357 struct drm_plane *plane;
3358 struct drm_plane_state *pstate;
b9cec075 3359 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3360 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
b9cec075 3361 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3362 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3363 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3364 unsigned int total_data_rate;
c107acfe
MR		 3365 int num_active;
3366 int id, i;
b9cec075 3367
5a920b85
PZ		 3368 /* Clear the partitioning for disabled planes. */
3369 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3370 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3371
a6d3460e
MR		 3372 if (WARN_ON(!state))
3373 return 0;
3374
c107acfe 3375 if (!cstate->base.active) {
ce0ba283 3376 alloc->start = alloc->end = 0;
c107acfe
MR		 3377 return 0;
3378 }
3379
a6d3460e 3380 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3381 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3382 if (alloc_size == 0) {
3383 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3384 return 0;
b9cec075
DL		 3385 }
3386
c107acfe 3387 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3388 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3389 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3390
3391 alloc_size -= cursor_blocks;
b9cec075 3392
80958155 3393 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3394 for_each_plane_in_state(state, plane, pstate, i) {
3395 intel_plane = to_intel_plane(plane);
3396 id = skl_wm_plane_id(intel_plane);
c107acfe 3397
a6d3460e
MR		 3398 if (intel_plane->pipe != pipe)
3399 continue;
c107acfe 3400
936e71e3 3401 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3402 minimum[id] = 0;
3403 y_minimum[id] = 0;
3404 continue;
3405 }
3406 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3407 minimum[id] = 0;
3408 y_minimum[id] = 0;
3409 continue;
c107acfe 3410 }
a6d3460e 3411
cbcfd14b
KM		 3412 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3413 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3414 }
80958155 3415
c107acfe
MR		 3416 for (i = 0; i < PLANE_CURSOR; i++) {
3417 alloc_size -= minimum[i];
3418 alloc_size -= y_minimum[i];
80958155
DL		 3419 }
3420
b9cec075 3421 /*
80958155
DL		 3422 * 2. Distribute the remaining space in proportion to the amount of
3423 * data each plane needs to fetch from memory.
b9cec075
DL		 3424 *
3425 * FIXME: we may not allocate every single block here.
3426 */
024c9045 3427 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3428 if (total_data_rate == 0)
c107acfe 3429 return 0;
b9cec075 3430
34bb56af 3431 start = alloc->start;
024c9045 3432 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3433 unsigned int data_rate, y_data_rate;
3434 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3435 int id = skl_wm_plane_id(intel_plane);
b9cec075 3436
a1de91e5 3437 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3438
3439 /*
2cd601c6 3440 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3441 * promote the expression to 64 bits to avoid overflowing, the
3442 * result is < available as data_rate / total_data_rate < 1
3443 */
024c9045 3444 plane_blocks = minimum[id];
80958155
DL		 3445 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3446 total_data_rate);
b9cec075 3447
c107acfe
MR		 3448 /* Leave disabled planes at (0,0) */
3449 if (data_rate) {
3450 ddb->plane[pipe][id].start = start;
3451 ddb->plane[pipe][id].end = start + plane_blocks;
3452 }
b9cec075
DL		 3453
3454 start += plane_blocks;
2cd601c6
CK		 3455
3456 /*
3457 * allocation for y_plane part of planar format:
3458 */
a1de91e5
MR		 3459 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3460
3461 y_plane_blocks = y_minimum[id];
3462 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3463 total_data_rate);
2cd601c6 3464
c107acfe
MR		 3465 if (y_data_rate) {
3466 ddb->y_plane[pipe][id].start = start;
3467 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3468 }
a1de91e5
MR		 3469
3470 start += y_plane_blocks;
b9cec075
DL		 3471 }
3472
c107acfe 3473 return 0;
b9cec075
DL		 3474}
3475
5cec258b 3476static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3477{
3478 /* TODO: Take into account the scalers once we support them */
2d112de7 3479 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3480}
3481
3482/*
3483 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3484 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3485 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3486 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3487*/
ac484963 3488static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3489{
3490 uint32_t wm_intermediate_val, ret;
3491
3492 if (latency == 0)
3493 return UINT_MAX;
3494
ac484963 3495 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3496 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3497
3498 return ret;
3499}
3500
3501static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3502 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3503{
d4c2aa60 3504 uint32_t ret;
d4c2aa60 3505 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3506
3507 if (latency == 0)
3508 return UINT_MAX;
3509
2d41c0b5
PB		 3510 wm_intermediate_val = latency * pixel_rate;
3511 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3512 plane_blocks_per_line;
2d41c0b5
PB		 3513
3514 return ret;
3515}
3516
9c2f7a9d
KM		 3517static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3518 struct intel_plane_state *pstate)
3519{
3520 uint64_t adjusted_pixel_rate;
3521 uint64_t downscale_amount;
3522 uint64_t pixel_rate;
3523
3524 /* Shouldn't reach here on disabled planes... */
936e71e3 3525 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3526 return 0;
3527
3528 /*
3529 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3530 * with additional adjustments for plane-specific scaling.
3531 */
3532 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3533 downscale_amount = skl_plane_downscale_amount(pstate);
3534
3535 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3536 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3537
3538 return pixel_rate;
3539}
3540
55994c2c
MR		 3541static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3542 struct intel_crtc_state *cstate,
3543 struct intel_plane_state *intel_pstate,
3544 uint16_t ddb_allocation,
3545 int level,
3546 uint16_t *out_blocks, /* out */
3547 uint8_t *out_lines, /* out */
3548 bool *enabled /* out */)
2d41c0b5 3549{
33815fa5
MR		 3550 struct drm_plane_state *pstate = &intel_pstate->base;
3551 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3552 uint32_t latency = dev_priv->wm.skl_latency[level];
3553 uint32_t method1, method2;
3554 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3555 uint32_t res_blocks, res_lines;
3556 uint32_t selected_result;
ac484963 3557 uint8_t cpp;
a280f7dd 3558 uint32_t width = 0, height = 0;
9c2f7a9d 3559 uint32_t plane_pixel_rate;
75676ed4 3560 uint32_t y_tile_minimum, y_min_scanlines;
2d41c0b5 3561
936e71e3 3562 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3563 *enabled = false;
3564 return 0;
3565 }
2d41c0b5 3566
936e71e3
VS		 3567 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3568 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3569
33815fa5 3570 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3571 swap(width, height);
3572
ac484963 3573 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3574 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3575
1186fa85
PZ		 3576 if (intel_rotation_90_or_270(pstate->rotation)) {
3577 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3578 drm_format_plane_cpp(fb->pixel_format, 1) :
3579 drm_format_plane_cpp(fb->pixel_format, 0);
3580
3581 switch (cpp) {
3582 case 1:
3583 y_min_scanlines = 16;
3584 break;
3585 case 2:
3586 y_min_scanlines = 8;
3587 break;
1186fa85
PZ		 3588 case 4:
3589 y_min_scanlines = 4;
3590 break;
86a462bc
PZ		 3591 default:
3592 MISSING_CASE(cpp);
3593 return -EINVAL;
1186fa85
PZ		 3594 }
3595 } else {
3596 y_min_scanlines = 4;
3597 }
3598
7a1a8aed
PZ		 3599 plane_bytes_per_line = width * cpp;
3600 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3601 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3602 plane_blocks_per_line =
3603 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3604 plane_blocks_per_line /= y_min_scanlines;
3605 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3606 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3607 + 1;
3608 } else {
3609 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3610 }
3611
9c2f7a9d
KM		 3612 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3613 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3614 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3615 latency,
7a1a8aed 3616 plane_blocks_per_line);
2d41c0b5 3617
75676ed4
PZ		 3618 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3619
024c9045
MR		 3620 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3621 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3622 selected_result = max(method2, y_tile_minimum);
3623 } else {
f1db3eaf
PZ		 3624 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3625 (plane_bytes_per_line / 512 < 1))
3626 selected_result = method2;
3627 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3628 selected_result = min(method1, method2);
3629 else
3630 selected_result = method1;
3631 }
2d41c0b5 3632
d4c2aa60
TU		 3633 res_blocks = selected_result + 1;
3634 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3635
0fda6568 3636 if (level >= 1 && level <= 7) {
024c9045 3637 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3638 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3639 res_blocks += y_tile_minimum;
1186fa85 3640 res_lines += y_min_scanlines;
75676ed4 3641 } else {
0fda6568 3642 res_blocks++;
75676ed4 3643 }
0fda6568 3644 }
e6d66171 3645
55994c2c
MR		 3646 if (res_blocks >= ddb_allocation || res_lines > 31) {
3647 *enabled = false;
6b6bada7
MR		 3648
3649 /*
3650 * If there are no valid level 0 watermarks, then we can't
3651 * support this display configuration.
3652 */
3653 if (level) {
3654 return 0;
3655 } else {
3656 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3657 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3658 to_intel_crtc(cstate->base.crtc)->pipe,
3659 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3660 res_blocks, ddb_allocation, res_lines);
3661
3662 return -EINVAL;
3663 }
55994c2c 3664 }
e6d66171
DL		 3665
3666 *out_blocks = res_blocks;
3667 *out_lines = res_lines;
55994c2c 3668 *enabled = true;
2d41c0b5 3669
55994c2c 3670 return 0;
2d41c0b5
PB		 3671}
3672
f4a96752
MR		 3673static int
3674skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3675 struct skl_ddb_allocation *ddb,
3676 struct intel_crtc_state *cstate,
3677 int level,
3678 struct skl_wm_level *result)
2d41c0b5 3679{
f4a96752 3680 struct drm_atomic_state *state = cstate->base.state;
024c9045 3681 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3682 struct drm_plane *plane;
024c9045 3683 struct intel_plane *intel_plane;
33815fa5 3684 struct intel_plane_state *intel_pstate;
2d41c0b5 3685 uint16_t ddb_blocks;
024c9045 3686 enum pipe pipe = intel_crtc->pipe;
55994c2c 3687 int ret;
024c9045 3688
f4a96752
MR		 3689 /*
3690 * We'll only calculate watermarks for planes that are actually
3691 * enabled, so make sure all other planes are set as disabled.
3692 */
3693 memset(result, 0, sizeof(*result));
3694
91c8a326
CW		 3695 for_each_intel_plane_mask(&dev_priv->drm,
3696 intel_plane,
3697 cstate->base.plane_mask) {
024c9045 3698 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3699
f4a96752
MR		 3700 plane = &intel_plane->base;
3701 intel_pstate = NULL;
3702 if (state)
3703 intel_pstate =
3704 intel_atomic_get_existing_plane_state(state,
3705 intel_plane);
3706
3707 /*
3708 * Note: If we start supporting multiple pending atomic commits
3709 * against the same planes/CRTC's in the future, plane->state
3710 * will no longer be the correct pre-state to use for the
3711 * calculations here and we'll need to change where we get the
3712 * 'unchanged' plane data from.
3713 *
3714 * For now this is fine because we only allow one queued commit
3715 * against a CRTC. Even if the plane isn't modified by this
3716 * transaction and we don't have a plane lock, we still have
3717 * the CRTC's lock, so we know that no other transactions are
3718 * racing with us to update it.
3719 */
3720 if (!intel_pstate)
3721 intel_pstate = to_intel_plane_state(plane->state);
3722
3723 WARN_ON(!intel_pstate->base.fb);
3724
2d41c0b5
PB		 3725 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3726
55994c2c
MR		 3727 ret = skl_compute_plane_wm(dev_priv,
3728 cstate,
3729 intel_pstate,
3730 ddb_blocks,
3731 level,
3732 &result->plane_res_b[i],
3733 &result->plane_res_l[i],
3734 &result->plane_en[i]);
3735 if (ret)
3736 return ret;
2d41c0b5 3737 }
f4a96752
MR		 3738
3739 return 0;
2d41c0b5
PB		 3740}
3741
407b50f3 3742static uint32_t
024c9045 3743skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3744{
024c9045 3745 if (!cstate->base.active)
407b50f3
DL		 3746 return 0;
3747
024c9045 3748 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3749 return 0;
407b50f3 3750
024c9045
MR		 3751 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3752 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3753}
3754
024c9045 3755static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3756 struct skl_wm_level *trans_wm /* out */)
407b50f3 3757{
024c9045 3758 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3760 struct intel_plane *intel_plane;
9414f563 3761
024c9045 3762 if (!cstate->base.active)
407b50f3 3763 return;
9414f563
DL		 3764
3765 /* Until we know more, just disable transition WMs */
024c9045
MR		 3766 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3767 int i = skl_wm_plane_id(intel_plane);
3768
9414f563 3769 trans_wm->plane_en[i] = false;
024c9045 3770 }
407b50f3
DL		 3771}
3772
55994c2c
MR		 3773static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3774 struct skl_ddb_allocation *ddb,
3775 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3776{
024c9045 3777 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3778 const struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3779 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3780 int ret;
2d41c0b5
PB		 3781
3782 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3783 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3784 level, &pipe_wm->wm[level]);
3785 if (ret)
3786 return ret;
2d41c0b5 3787 }
024c9045 3788 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3789
024c9045 3790 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3791
3792 return 0;
2d41c0b5
PB		 3793}
3794
3795static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3796 struct skl_pipe_wm *p_wm,
3797 struct skl_wm_values *r,
3798 struct intel_crtc *intel_crtc)
3799{
5db94019 3800 int level, max_level = ilk_wm_max_level(to_i915(dev));
2d41c0b5 3801 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3802 uint32_t temp;
3803 int i;
2d41c0b5
PB		 3804
3805 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3806 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3807 temp = 0;
2d41c0b5
PB		 3808
3809 temp |= p_wm->wm[level].plane_res_l[i] <<
3810 PLANE_WM_LINES_SHIFT;
3811 temp |= p_wm->wm[level].plane_res_b[i];
3812 if (p_wm->wm[level].plane_en[i])
3813 temp |= PLANE_WM_EN;
3814
3815 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3816 }
3817
3818 temp = 0;
2d41c0b5 3819
4969d33e
MR		 3820 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3821 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3822
4969d33e 3823 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3824 temp |= PLANE_WM_EN;
3825
4969d33e 3826 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3827
3828 }
3829
9414f563
DL		 3830 /* transition WMs */
3831 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3832 temp = 0;
3833 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3834 temp |= p_wm->trans_wm.plane_res_b[i];
3835 if (p_wm->trans_wm.plane_en[i])
3836 temp |= PLANE_WM_EN;
3837
3838 r->plane_trans[pipe][i] = temp;
3839 }
3840
3841 temp = 0;
4969d33e
MR		 3842 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3843 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3844 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3845 temp |= PLANE_WM_EN;
3846
4969d33e 3847 r->plane_trans[pipe][PLANE_CURSOR] = temp;
2d41c0b5
PB		 3848}
3849
f0f59a00
VS		 3850static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3851 i915_reg_t reg,
16160e3d
DL		 3852 const struct skl_ddb_entry *entry)
3853{
3854 if (entry->end)
3855 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3856 else
3857 I915_WRITE(reg, 0);
3858}
3859
62e0fb88
L		 3860void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3861 const struct skl_wm_values *wm,
3862 int plane)
3863{
3864 struct drm_crtc *crtc = &intel_crtc->base;
3865 struct drm_device *dev = crtc->dev;
3866 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3867 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3868 enum pipe pipe = intel_crtc->pipe;
3869
3870 for (level = 0; level <= max_level; level++) {
3871 I915_WRITE(PLANE_WM(pipe, plane, level),
3872 wm->plane[pipe][plane][level]);
3873 }
3874 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
27082493
L		 3875
3876 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3877 &wm->ddb.plane[pipe][plane]);
3878 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3879 &wm->ddb.y_plane[pipe][plane]);
62e0fb88
L		 3880}
3881
3882void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3883 const struct skl_wm_values *wm)
3884{
3885 struct drm_crtc *crtc = &intel_crtc->base;
3886 struct drm_device *dev = crtc->dev;
3887 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3888 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3889 enum pipe pipe = intel_crtc->pipe;
3890
3891 for (level = 0; level <= max_level; level++) {
3892 I915_WRITE(CUR_WM(pipe, level),
3893 wm->plane[pipe][PLANE_CURSOR][level]);
3894 }
3895 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3896
27082493
L		 3897 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3898 &wm->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3899}
3900
27082493
L		 3901static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3902 const struct skl_ddb_entry *b)
0e8fb7ba 3903{
27082493 3904 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3905}
3906
27082493 3907bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
ce0ba283 3908 struct intel_crtc *intel_crtc)
0e8fb7ba 3909{
ce0ba283
L		 3910 struct drm_crtc *other_crtc;
3911 struct drm_crtc_state *other_cstate;
3912 struct intel_crtc *other_intel_crtc;
3913 const struct skl_ddb_entry *ddb =
3914 &to_intel_crtc_state(intel_crtc->base.state)->wm.skl.ddb;
3915 int i;
0e8fb7ba 3916
ce0ba283
L		 3917 for_each_crtc_in_state(state, other_crtc, other_cstate, i) {
3918 other_intel_crtc = to_intel_crtc(other_crtc);
0e8fb7ba 3919
ce0ba283 3920 if (other_intel_crtc == intel_crtc)
0e8fb7ba
DL		 3921 continue;
3922
ce0ba283 3923 if (skl_ddb_entries_overlap(ddb, &other_intel_crtc->hw_ddb))
27082493 3924 return true;
0e8fb7ba
DL		 3925 }
3926
27082493 3927 return false;
0e8fb7ba
DL		 3928}
3929
55994c2c
MR		 3930static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3931 struct skl_ddb_allocation *ddb, /* out */
3932 struct skl_pipe_wm *pipe_wm, /* out */
3933 bool *changed /* out */)
2d41c0b5 3934{
f4a96752
MR		 3935 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3936 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3937 int ret;
2d41c0b5 3938
55994c2c
MR		 3939 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3940 if (ret)
3941 return ret;
2d41c0b5 3942
4e0963c7 3943 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3944 *changed = false;
3945 else
3946 *changed = true;
2d41c0b5 3947
55994c2c 3948 return 0;
2d41c0b5
PB		 3949}
3950
9b613022
MR		 3951static uint32_t
3952pipes_modified(struct drm_atomic_state *state)
3953{
3954 struct drm_crtc *crtc;
3955 struct drm_crtc_state *cstate;
3956 uint32_t i, ret = 0;
3957
3958 for_each_crtc_in_state(state, crtc, cstate, i)
3959 ret |= drm_crtc_mask(crtc);
3960
3961 return ret;
3962}
3963
bb7791bd 3964static int
7f60e200
PZ		 3965skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3966{
3967 struct drm_atomic_state *state = cstate->base.state;
3968 struct drm_device *dev = state->dev;
3969 struct drm_crtc *crtc = cstate->base.crtc;
3970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3971 struct drm_i915_private *dev_priv = to_i915(dev);
3972 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3973 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3974 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3975 struct drm_plane_state *plane_state;
3976 struct drm_plane *plane;
3977 enum pipe pipe = intel_crtc->pipe;
3978 int id;
3979
3980 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3981
3982 drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3983 id = skl_wm_plane_id(to_intel_plane(plane));
3984
3985 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3986 &new_ddb->plane[pipe][id]) &&
3987 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3988 &new_ddb->y_plane[pipe][id]))
3989 continue;
3990
3991 plane_state = drm_atomic_get_plane_state(state, plane);
3992 if (IS_ERR(plane_state))
3993 return PTR_ERR(plane_state);
3994 }
3995
3996 return 0;
3997}
3998
98d39494
MR		 3999static int
4000skl_compute_ddb(struct drm_atomic_state *state)
4001{
4002 struct drm_device *dev = state->dev;
4003 struct drm_i915_private *dev_priv = to_i915(dev);
4004 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4005 struct intel_crtc *intel_crtc;
734fa01f 4006 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4007 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4008 int ret;
4009
4010 /*
4011 * If this is our first atomic update following hardware readout,
4012 * we can't trust the DDB that the BIOS programmed for us. Let's
4013 * pretend that all pipes switched active status so that we'll
4014 * ensure a full DDB recompute.
4015 */
1b54a880
MR		 4016 if (dev_priv->wm.distrust_bios_wm) {
4017 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4018 state->acquire_ctx);
4019 if (ret)
4020 return ret;
4021
98d39494
MR		 4022 intel_state->active_pipe_changes = ~0;
4023
1b54a880
MR		 4024 /*
4025 * We usually only initialize intel_state->active_crtcs if we
4026 * we're doing a modeset; make sure this field is always
4027 * initialized during the sanitization process that happens
4028 * on the first commit too.
4029 */
4030 if (!intel_state->modeset)
4031 intel_state->active_crtcs = dev_priv->active_crtcs;
4032 }
4033
98d39494
MR		 4034 /*
4035 * If the modeset changes which CRTC's are active, we need to
4036 * recompute the DDB allocation for *all* active pipes, even
4037 * those that weren't otherwise being modified in any way by this
4038 * atomic commit. Due to the shrinking of the per-pipe allocations
4039 * when new active CRTC's are added, it's possible for a pipe that
4040 * we were already using and aren't changing at all here to suddenly
4041 * become invalid if its DDB needs exceeds its new allocation.
4042 *
4043 * Note that if we wind up doing a full DDB recompute, we can't let
4044 * any other display updates race with this transaction, so we need
4045 * to grab the lock on *all* CRTC's.
4046 */
734fa01f 4047 if (intel_state->active_pipe_changes) {
98d39494 4048 realloc_pipes = ~0;
734fa01f
MR		 4049 intel_state->wm_results.dirty_pipes = ~0;
4050 }
98d39494 4051
5a920b85
PZ		 4052 /*
4053 * We're not recomputing for the pipes not included in the commit, so
4054 * make sure we start with the current state.
4055 */
4056 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4057
98d39494
MR		 4058 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4059 struct intel_crtc_state *cstate;
4060
4061 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4062 if (IS_ERR(cstate))
4063 return PTR_ERR(cstate);
4064
734fa01f 4065 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4066 if (ret)
4067 return ret;
05a76d3d 4068
7f60e200 4069 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4070 if (ret)
4071 return ret;
98d39494
MR		 4072 }
4073
4074 return 0;
4075}
4076
2722efb9
MR		 4077static void
4078skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4079 struct skl_wm_values *src,
4080 enum pipe pipe)
4081{
2722efb9
MR		 4082 memcpy(dst->plane[pipe], src->plane[pipe],
4083 sizeof(dst->plane[pipe]));
4084 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4085 sizeof(dst->plane_trans[pipe]));
4086
2722efb9
MR		 4087 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4088 sizeof(dst->ddb.y_plane[pipe]));
4089 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4090 sizeof(dst->ddb.plane[pipe]));
4091}
4092
98d39494
MR		 4093static int
4094skl_compute_wm(struct drm_atomic_state *state)
4095{
4096 struct drm_crtc *crtc;
4097 struct drm_crtc_state *cstate;
734fa01f
MR		 4098 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4099 struct skl_wm_values *results = &intel_state->wm_results;
4100 struct skl_pipe_wm *pipe_wm;
98d39494 4101 bool changed = false;
734fa01f 4102 int ret, i;
98d39494
MR		 4103
4104 /*
4105 * If this transaction isn't actually touching any CRTC's, don't
4106 * bother with watermark calculation. Note that if we pass this
4107 * test, we're guaranteed to hold at least one CRTC state mutex,
4108 * which means we can safely use values like dev_priv->active_crtcs
4109 * since any racing commits that want to update them would need to
4110 * hold _all_ CRTC state mutexes.
4111 */
4112 for_each_crtc_in_state(state, crtc, cstate, i)
4113 changed = true;
4114 if (!changed)
4115 return 0;
4116
734fa01f
MR		 4117 /* Clear all dirty flags */
4118 results->dirty_pipes = 0;
4119
98d39494
MR		 4120 ret = skl_compute_ddb(state);
4121 if (ret)
4122 return ret;
4123
734fa01f
MR		 4124 /*
4125 * Calculate WM's for all pipes that are part of this transaction.
4126 * Note that the DDB allocation above may have added more CRTC's that
4127 * weren't otherwise being modified (and set bits in dirty_pipes) if
4128 * pipe allocations had to change.
4129 *
4130 * FIXME: Now that we're doing this in the atomic check phase, we
4131 * should allow skl_update_pipe_wm() to return failure in cases where
4132 * no suitable watermark values can be found.
4133 */
4134 for_each_crtc_in_state(state, crtc, cstate, i) {
4135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4136 struct intel_crtc_state *intel_cstate =
4137 to_intel_crtc_state(cstate);
4138
4139 pipe_wm = &intel_cstate->wm.skl.optimal;
4140 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4141 &changed);
4142 if (ret)
4143 return ret;
4144
4145 if (changed)
4146 results->dirty_pipes |= drm_crtc_mask(crtc);
4147
4148 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4149 /* This pipe's WM's did not change */
4150 continue;
4151
4152 intel_cstate->update_wm_pre = true;
4153 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4154 }
4155
98d39494
MR		 4156 return 0;
4157}
4158
2d41c0b5
PB		 4159static void skl_update_wm(struct drm_crtc *crtc)
4160{
4161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4162 struct drm_device *dev = crtc->dev;
fac5e23e 4163 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4164 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4165 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4166 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4167 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4168 enum pipe pipe = intel_crtc->pipe;
adda50b8 4169
734fa01f 4170 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4171 return;
4172
734fa01f
MR		 4173 intel_crtc->wm.active.skl = *pipe_wm;
4174
4175 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4176
2722efb9 4177 /*
27082493
L		 4178 * If this pipe isn't active already, we're going to be enabling it
4179 * very soon. Since it's safe to update a pipe's ddb allocation while
4180 * the pipe's shut off, just do so here. Already active pipes will have
4181 * their watermarks updated once we update their planes.
2722efb9 4182 */
27082493
L		 4183 if (crtc->state->active_changed) {
4184 int plane;
4185
4186 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4187 skl_write_plane_wm(intel_crtc, results, plane);
4188
4189 skl_write_cursor_wm(intel_crtc, results);
4190 }
4191
4192 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f 4193
ce0ba283
L		 4194 intel_crtc->hw_ddb = cstate->wm.skl.ddb;
4195
734fa01f 4196 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4197}
4198
d890565c
VS		 4199static void ilk_compute_wm_config(struct drm_device *dev,
4200 struct intel_wm_config *config)
4201{
4202 struct intel_crtc *crtc;
4203
4204 /* Compute the currently _active_ config */
4205 for_each_intel_crtc(dev, crtc) {
4206 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4207
4208 if (!wm->pipe_enabled)
4209 continue;
4210
4211 config->sprites_enabled |= wm->sprites_enabled;
4212 config->sprites_scaled |= wm->sprites_scaled;
4213 config->num_pipes_active++;
4214 }
4215}
4216
ed4a6a7c 4217static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4218{
91c8a326 4219 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4220 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4221 struct ilk_wm_maximums max;
d890565c 4222 struct intel_wm_config config = {};
820c1980 4223 struct ilk_wm_values results = {};
77c122bc 4224 enum intel_ddb_partitioning partitioning;
261a27d1 4225
d890565c
VS		 4226 ilk_compute_wm_config(dev, &config);
4227
4228 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4229 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4230
4231 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4232 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4233 config.num_pipes_active == 1 && config.sprites_enabled) {
4234 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4235 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4236
820c1980 4237 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4238 } else {
198a1e9b 4239 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4240 }
4241
198a1e9b 4242 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4243 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4244
820c1980 4245 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4246
820c1980 4247 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4248}
4249
ed4a6a7c 4250static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4251{
ed4a6a7c
MR		 4252 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4253 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4254
ed4a6a7c 4255 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4256 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4257 ilk_program_watermarks(dev_priv);
4258 mutex_unlock(&dev_priv->wm.wm_mutex);
4259}
bf220452 4260
ed4a6a7c
MR		 4261static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4262{
4263 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4264 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4265
ed4a6a7c
MR		 4266 mutex_lock(&dev_priv->wm.wm_mutex);
4267 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4268 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4269 ilk_program_watermarks(dev_priv);
4270 }
4271 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4272}
4273
3078999f
PB		 4274static void skl_pipe_wm_active_state(uint32_t val,
4275 struct skl_pipe_wm *active,
4276 bool is_transwm,
4277 bool is_cursor,
4278 int i,
4279 int level)
4280{
4281 bool is_enabled = (val & PLANE_WM_EN) != 0;
4282
4283 if (!is_transwm) {
4284 if (!is_cursor) {
4285 active->wm[level].plane_en[i] = is_enabled;
4286 active->wm[level].plane_res_b[i] =
4287 val & PLANE_WM_BLOCKS_MASK;
4288 active->wm[level].plane_res_l[i] =
4289 (val >> PLANE_WM_LINES_SHIFT) &
4290 PLANE_WM_LINES_MASK;
4291 } else {
4969d33e
MR		 4292 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4293 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4294 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4295 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4296 (val >> PLANE_WM_LINES_SHIFT) &
4297 PLANE_WM_LINES_MASK;
4298 }
4299 } else {
4300 if (!is_cursor) {
4301 active->trans_wm.plane_en[i] = is_enabled;
4302 active->trans_wm.plane_res_b[i] =
4303 val & PLANE_WM_BLOCKS_MASK;
4304 active->trans_wm.plane_res_l[i] =
4305 (val >> PLANE_WM_LINES_SHIFT) &
4306 PLANE_WM_LINES_MASK;
4307 } else {
4969d33e
MR		 4308 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4309 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4310 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4311 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4312 (val >> PLANE_WM_LINES_SHIFT) &
4313 PLANE_WM_LINES_MASK;
4314 }
4315 }
4316}
4317
4318static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4319{
4320 struct drm_device *dev = crtc->dev;
fac5e23e 4321 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4322 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4324 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4325 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4326 enum pipe pipe = intel_crtc->pipe;
4327 int level, i, max_level;
4328 uint32_t temp;
4329
5db94019 4330 max_level = ilk_wm_max_level(dev_priv);
3078999f 4331
3078999f
PB		 4332 for (level = 0; level <= max_level; level++) {
4333 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4334 hw->plane[pipe][i][level] =
4335 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4336 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4337 }
4338
4339 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4340 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4341 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4342
3ef00284 4343 if (!intel_crtc->active)
3078999f
PB		 4344 return;
4345
2b4b9f35 4346 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f 4347
b707aa50 4348 active->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4349
4350 for (level = 0; level <= max_level; level++) {
4351 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4352 temp = hw->plane[pipe][i][level];
4353 skl_pipe_wm_active_state(temp, active, false,
4354 false, i, level);
4355 }
4969d33e 4356 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4357 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4358 }
4359
4360 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4361 temp = hw->plane_trans[pipe][i];
4362 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4363 }
4364
4969d33e 4365 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4366 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4367
4368 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4369}
4370
4371void skl_wm_get_hw_state(struct drm_device *dev)
4372{
fac5e23e 4373 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4374 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4375 struct drm_crtc *crtc;
4376
a269c583 4377 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4378 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4379 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4380
279e99d7
MR		 4381 if (dev_priv->active_crtcs) {
4382 /* Fully recompute DDB on first atomic commit */
4383 dev_priv->wm.distrust_bios_wm = true;
4384 } else {
4385 /* Easy/common case; just sanitize DDB now if everything off */
4386 memset(ddb, 0, sizeof(*ddb));
4387 }
3078999f
PB		 4388}
4389
243e6a44
VS		 4390static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4391{
4392 struct drm_device *dev = crtc->dev;
fac5e23e 4393 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4394 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4396 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4397 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4398 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4399 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4400 [PIPE_A] = WM0_PIPEA_ILK,
4401 [PIPE_B] = WM0_PIPEB_ILK,
4402 [PIPE_C] = WM0_PIPEC_IVB,
4403 };
4404
4405 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4406 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4407 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4408
15606534
VS		 4409 memset(active, 0, sizeof(*active));
4410
3ef00284 4411 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4412
4413 if (active->pipe_enabled) {
243e6a44
VS		 4414 u32 tmp = hw->wm_pipe[pipe];
4415
4416 /*
4417 * For active pipes LP0 watermark is marked as
4418 * enabled, and LP1+ watermaks as disabled since
4419 * we can't really reverse compute them in case
4420 * multiple pipes are active.
4421 */
4422 active->wm[0].enable = true;
4423 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4424 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4425 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4426 active->linetime = hw->wm_linetime[pipe];
4427 } else {
5db94019 4428 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4429
4430 /*
4431 * For inactive pipes, all watermark levels
4432 * should be marked as enabled but zeroed,
4433 * which is what we'd compute them to.
4434 */
4435 for (level = 0; level <= max_level; level++)
4436 active->wm[level].enable = true;
4437 }
4e0963c7
MR		 4438
4439 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4440}
4441
6eb1a681
VS		 4442#define _FW_WM(value, plane) \
4443 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4444#define _FW_WM_VLV(value, plane) \
4445 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4446
4447static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4448 struct vlv_wm_values *wm)
4449{
4450 enum pipe pipe;
4451 uint32_t tmp;
4452
4453 for_each_pipe(dev_priv, pipe) {
4454 tmp = I915_READ(VLV_DDL(pipe));
4455
4456 wm->ddl[pipe].primary =
4457 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4458 wm->ddl[pipe].cursor =
4459 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4460 wm->ddl[pipe].sprite[0] =
4461 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4462 wm->ddl[pipe].sprite[1] =
4463 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4464 }
4465
4466 tmp = I915_READ(DSPFW1);
4467 wm->sr.plane = _FW_WM(tmp, SR);
4468 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4469 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4470 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4471
4472 tmp = I915_READ(DSPFW2);
4473 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4474 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4475 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4476
4477 tmp = I915_READ(DSPFW3);
4478 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4479
4480 if (IS_CHERRYVIEW(dev_priv)) {
4481 tmp = I915_READ(DSPFW7_CHV);
4482 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4483 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4484
4485 tmp = I915_READ(DSPFW8_CHV);
4486 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4487 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4488
4489 tmp = I915_READ(DSPFW9_CHV);
4490 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4491 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4492
4493 tmp = I915_READ(DSPHOWM);
4494 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4495 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4496 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4497 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4498 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4499 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4500 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4501 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4502 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4503 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4504 } else {
4505 tmp = I915_READ(DSPFW7);
4506 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4507 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4508
4509 tmp = I915_READ(DSPHOWM);
4510 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4511 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4512 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4513 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4514 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4515 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4516 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4517 }
4518}
4519
4520#undef _FW_WM
4521#undef _FW_WM_VLV
4522
4523void vlv_wm_get_hw_state(struct drm_device *dev)
4524{
4525 struct drm_i915_private *dev_priv = to_i915(dev);
4526 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4527 struct intel_plane *plane;
4528 enum pipe pipe;
4529 u32 val;
4530
4531 vlv_read_wm_values(dev_priv, wm);
4532
4533 for_each_intel_plane(dev, plane) {
4534 switch (plane->base.type) {
4535 int sprite;
4536 case DRM_PLANE_TYPE_CURSOR:
4537 plane->wm.fifo_size = 63;
4538 break;
4539 case DRM_PLANE_TYPE_PRIMARY:
4540 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4541 break;
4542 case DRM_PLANE_TYPE_OVERLAY:
4543 sprite = plane->plane;
4544 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4545 break;
4546 }
4547 }
4548
4549 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4550 wm->level = VLV_WM_LEVEL_PM2;
4551
4552 if (IS_CHERRYVIEW(dev_priv)) {
4553 mutex_lock(&dev_priv->rps.hw_lock);
4554
4555 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4556 if (val & DSP_MAXFIFO_PM5_ENABLE)
4557 wm->level = VLV_WM_LEVEL_PM5;
4558
58590c14
VS		 4559 /*
4560 * If DDR DVFS is disabled in the BIOS, Punit
4561 * will never ack the request. So if that happens
4562 * assume we don't have to enable/disable DDR DVFS
4563 * dynamically. To test that just set the REQ_ACK
4564 * bit to poke the Punit, but don't change the
4565 * HIGH/LOW bits so that we don't actually change
4566 * the current state.
4567 */
6eb1a681 4568 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4569 val |= FORCE_DDR_FREQ_REQ_ACK;
4570 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4571
4572 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4573 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4574 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4575 "assuming DDR DVFS is disabled\n");
4576 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4577 } else {
4578 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4579 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4580 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4581 }
6eb1a681
VS		 4582
4583 mutex_unlock(&dev_priv->rps.hw_lock);
4584 }
4585
4586 for_each_pipe(dev_priv, pipe)
4587 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4588 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4589 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4590
4591 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4592 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4593}
4594
243e6a44
VS		 4595void ilk_wm_get_hw_state(struct drm_device *dev)
4596{
fac5e23e 4597 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4598 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4599 struct drm_crtc *crtc;
4600
70e1e0ec 4601 for_each_crtc(dev, crtc)
243e6a44
VS		 4602 ilk_pipe_wm_get_hw_state(crtc);
4603
4604 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4605 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4606 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4607
4608 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4609 if (INTEL_INFO(dev)->gen >= 7) {
4610 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4611 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4612 }
243e6a44 4613
8652744b 4614 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4615 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4616 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4617 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4618 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4619 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4620
4621 hw->enable_fbc_wm =
4622 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4623}
4624
b445e3b0
ED		 4625/**
4626 * intel_update_watermarks - update FIFO watermark values based on current modes
4627 *
4628 * Calculate watermark values for the various WM regs based on current mode
4629 * and plane configuration.
4630 *
4631 * There are several cases to deal with here:
4632 * - normal (i.e. non-self-refresh)
4633 * - self-refresh (SR) mode
4634 * - lines are large relative to FIFO size (buffer can hold up to 2)
4635 * - lines are small relative to FIFO size (buffer can hold more than 2
4636 * lines), so need to account for TLB latency
4637 *
4638 * The normal calculation is:
4639 * watermark = dotclock * bytes per pixel * latency
4640 * where latency is platform & configuration dependent (we assume pessimal
4641 * values here).
4642 *
4643 * The SR calculation is:
4644 * watermark = (trunc(latency/line time)+1) * surface width *
4645 * bytes per pixel
4646 * where
4647 * line time = htotal / dotclock
4648 * surface width = hdisplay for normal plane and 64 for cursor
4649 * and latency is assumed to be high, as above.
4650 *
4651 * The final value programmed to the register should always be rounded up,
4652 * and include an extra 2 entries to account for clock crossings.
4653 *
4654 * We don't use the sprite, so we can ignore that. And on Crestline we have
4655 * to set the non-SR watermarks to 8.
4656 */
46ba614c 4657void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4658{
fac5e23e 4659 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4660
4661 if (dev_priv->display.update_wm)
46ba614c 4662 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4663}
4664
e2828914 4665/*
9270388e 4666 * Lock protecting IPS related data structures
9270388e
DV		 4667 */
4668DEFINE_SPINLOCK(mchdev_lock);
4669
4670/* Global for IPS driver to get at the current i915 device. Protected by
4671 * mchdev_lock. */
4672static struct drm_i915_private *i915_mch_dev;
4673
91d14251 4674bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4675{
2b4e57bd
ED		 4676 u16 rgvswctl;
4677
9270388e
DV		 4678 assert_spin_locked(&mchdev_lock);
4679
2b4e57bd
ED		 4680 rgvswctl = I915_READ16(MEMSWCTL);
4681 if (rgvswctl & MEMCTL_CMD_STS) {
4682 DRM_DEBUG("gpu busy, RCS change rejected\n");
4683 return false; /* still busy with another command */
4684 }
4685
4686 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4687 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4688 I915_WRITE16(MEMSWCTL, rgvswctl);
4689 POSTING_READ16(MEMSWCTL);
4690
4691 rgvswctl |= MEMCTL_CMD_STS;
4692 I915_WRITE16(MEMSWCTL, rgvswctl);
4693
4694 return true;
4695}
4696
91d14251 4697static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4698{
84f1b20f 4699 u32 rgvmodectl;
2b4e57bd
ED		 4700 u8 fmax, fmin, fstart, vstart;
4701
9270388e
DV		 4702 spin_lock_irq(&mchdev_lock);
4703
84f1b20f
TU		 4704 rgvmodectl = I915_READ(MEMMODECTL);
4705
2b4e57bd
ED		 4706 /* Enable temp reporting */
4707 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4708 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4709
4710 /* 100ms RC evaluation intervals */
4711 I915_WRITE(RCUPEI, 100000);
4712 I915_WRITE(RCDNEI, 100000);
4713
4714 /* Set max/min thresholds to 90ms and 80ms respectively */
4715 I915_WRITE(RCBMAXAVG, 90000);
4716 I915_WRITE(RCBMINAVG, 80000);
4717
4718 I915_WRITE(MEMIHYST, 1);
4719
4720 /* Set up min, max, and cur for interrupt handling */
4721 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4722 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4723 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4724 MEMMODE_FSTART_SHIFT;
4725
616847e7 4726 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4727 PXVFREQ_PX_SHIFT;
4728
20e4d407
DV		 4729 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4730 dev_priv->ips.fstart = fstart;
2b4e57bd 4731
20e4d407
DV		 4732 dev_priv->ips.max_delay = fstart;
4733 dev_priv->ips.min_delay = fmin;
4734 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4735
4736 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4737 fmax, fmin, fstart);
4738
4739 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4740
4741 /*
4742 * Interrupts will be enabled in ironlake_irq_postinstall
4743 */
4744
4745 I915_WRITE(VIDSTART, vstart);
4746 POSTING_READ(VIDSTART);
4747
4748 rgvmodectl |= MEMMODE_SWMODE_EN;
4749 I915_WRITE(MEMMODECTL, rgvmodectl);
4750
9270388e 4751 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4752 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4753 mdelay(1);
2b4e57bd 4754
91d14251 4755 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4756
7d81c3e0
VS		 4757 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4758 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4759 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4760 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4761 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4762
4763 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4764}
4765
91d14251 4766static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4767{
9270388e
DV		 4768 u16 rgvswctl;
4769
4770 spin_lock_irq(&mchdev_lock);
4771
4772 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4773
4774 /* Ack interrupts, disable EFC interrupt */
4775 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4776 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4777 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4778 I915_WRITE(DEIIR, DE_PCU_EVENT);
4779 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4780
4781 /* Go back to the starting frequency */
91d14251 4782 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4783 mdelay(1);
2b4e57bd
ED		 4784 rgvswctl |= MEMCTL_CMD_STS;
4785 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4786 mdelay(1);
2b4e57bd 4787
9270388e 4788 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4789}
4790
acbe9475
DV		 4791/* There's a funny hw issue where the hw returns all 0 when reading from
4792 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4793 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4794 * all limits and the gpu stuck at whatever frequency it is at atm).
4795 */
74ef1173 4796static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4797{
7b9e0ae6 4798 u32 limits;
2b4e57bd 4799
20b46e59
DV		 4800 /* Only set the down limit when we've reached the lowest level to avoid
4801 * getting more interrupts, otherwise leave this clear. This prevents a
4802 * race in the hw when coming out of rc6: There's a tiny window where
4803 * the hw runs at the minimal clock before selecting the desired
4804 * frequency, if the down threshold expires in that window we will not
4805 * receive a down interrupt. */
2d1fe073 4806 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4807 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4808 if (val <= dev_priv->rps.min_freq_softlimit)
4809 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4810 } else {
4811 limits = dev_priv->rps.max_freq_softlimit << 24;
4812 if (val <= dev_priv->rps.min_freq_softlimit)
4813 limits |= dev_priv->rps.min_freq_softlimit << 16;
4814 }
20b46e59
DV		 4815
4816 return limits;
4817}
4818
dd75fdc8
CW		 4819static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4820{
4821 int new_power;
8a586437
AG		 4822 u32 threshold_up = 0, threshold_down = 0; /* in % */
4823 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4824
4825 new_power = dev_priv->rps.power;
4826 switch (dev_priv->rps.power) {
4827 case LOW_POWER:
a72b5623
CW		 4828 if (val > dev_priv->rps.efficient_freq + 1 &&
4829 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4830 new_power = BETWEEN;
4831 break;
4832
4833 case BETWEEN:
a72b5623
CW		 4834 if (val <= dev_priv->rps.efficient_freq &&
4835 val < dev_priv->rps.cur_freq)
dd75fdc8 4836 new_power = LOW_POWER;
a72b5623
CW		 4837 else if (val >= dev_priv->rps.rp0_freq &&
4838 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4839 new_power = HIGH_POWER;
4840 break;
4841
4842 case HIGH_POWER:
a72b5623
CW		 4843 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4844 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4845 new_power = BETWEEN;
4846 break;
4847 }
4848 /* Max/min bins are special */
aed242ff 4849 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4850 new_power = LOW_POWER;
aed242ff 4851 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4852 new_power = HIGH_POWER;
4853 if (new_power == dev_priv->rps.power)
4854 return;
4855
4856 /* Note the units here are not exactly 1us, but 1280ns. */
4857 switch (new_power) {
4858 case LOW_POWER:
4859 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4860 ei_up = 16000;
4861 threshold_up = 95;
dd75fdc8
CW		 4862
4863 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4864 ei_down = 32000;
4865 threshold_down = 85;
dd75fdc8
CW		 4866 break;
4867
4868 case BETWEEN:
4869 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4870 ei_up = 13000;
4871 threshold_up = 90;
dd75fdc8
CW		 4872
4873 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4874 ei_down = 32000;
4875 threshold_down = 75;
dd75fdc8
CW		 4876 break;
4877
4878 case HIGH_POWER:
4879 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4880 ei_up = 10000;
4881 threshold_up = 85;
dd75fdc8
CW		 4882
4883 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4884 ei_down = 32000;
4885 threshold_down = 60;
dd75fdc8
CW		 4886 break;
4887 }
4888
8a586437 4889 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4890 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4891 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4892 GT_INTERVAL_FROM_US(dev_priv,
4893 ei_up * threshold_up / 100));
8a586437
AG		 4894
4895 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4896 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4897 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4898 GT_INTERVAL_FROM_US(dev_priv,
4899 ei_down * threshold_down / 100));
4900
4901 I915_WRITE(GEN6_RP_CONTROL,
4902 GEN6_RP_MEDIA_TURBO |
4903 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4904 GEN6_RP_MEDIA_IS_GFX |
4905 GEN6_RP_ENABLE |
4906 GEN6_RP_UP_BUSY_AVG |
4907 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4908
dd75fdc8 4909 dev_priv->rps.power = new_power;
8fb55197
CW		 4910 dev_priv->rps.up_threshold = threshold_up;
4911 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4912 dev_priv->rps.last_adj = 0;
4913}
4914
2876ce73
CW		 4915static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4916{
4917 u32 mask = 0;
4918
4919 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4920 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4921 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4922 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4923
7b3c29f6
CW		 4924 mask &= dev_priv->pm_rps_events;
4925
59d02a1f 4926 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4927}
4928
b8a5ff8d
JM		 4929/* gen6_set_rps is called to update the frequency request, but should also be
4930 * called when the range (min_delay and max_delay) is modified so that we can
4931 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4932static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4933{
23eafea6 4934 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4935 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4936 return;
4937
4fc688ce 4938 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4939 WARN_ON(val > dev_priv->rps.max_freq);
4940 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4941
eb64cad1
CW		 4942 /* min/max delay may still have been modified so be sure to
4943 * write the limits value.
4944 */
4945 if (val != dev_priv->rps.cur_freq) {
4946 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4947
dc97997a 4948 if (IS_GEN9(dev_priv))
5704195c
AG		 4949 I915_WRITE(GEN6_RPNSWREQ,
4950 GEN9_FREQUENCY(val));
dc97997a 4951 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4952 I915_WRITE(GEN6_RPNSWREQ,
4953 HSW_FREQUENCY(val));
4954 else
4955 I915_WRITE(GEN6_RPNSWREQ,
4956 GEN6_FREQUENCY(val) |
4957 GEN6_OFFSET(0) |
4958 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4959 }
7b9e0ae6 4960
7b9e0ae6
CW		 4961 /* Make sure we continue to get interrupts
4962 * until we hit the minimum or maximum frequencies.
4963 */
74ef1173 4964 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4965 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4966
d5570a72
BW		 4967 POSTING_READ(GEN6_RPNSWREQ);
4968
b39fb297 4969 dev_priv->rps.cur_freq = val;
0f94592e 4970 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4971}
4972
dc97997a 4973static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4974{
ffe02b40 4975 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4976 WARN_ON(val > dev_priv->rps.max_freq);
4977 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4978
dc97997a 4979 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4980 "Odd GPU freq value\n"))
4981 val &= ~1;
4982
cd25dd5b
D		 4983 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4984
8fb55197 4985 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4986 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4987 if (!IS_CHERRYVIEW(dev_priv))
4988 gen6_set_rps_thresholds(dev_priv, val);
4989 }
ffe02b40 4990
ffe02b40
VS		 4991 dev_priv->rps.cur_freq = val;
4992 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4993}
4994
a7f6e231 4995/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4996 *
4997 * * If Gfx is Idle, then
a7f6e231
D		 4998 * 1. Forcewake Media well.
4999 * 2. Request idle freq.
5000 * 3. Release Forcewake of Media well.
76c3552f
D		 5001*/
5002static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5003{
aed242ff 5004 u32 val = dev_priv->rps.idle_freq;
5549d25f 5005
aed242ff 5006 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5007 return;
5008
a7f6e231
D		 5009 /* Wake up the media well, as that takes a lot less
5010 * power than the Render well. */
5011 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5012 valleyview_set_rps(dev_priv, val);
a7f6e231 5013 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5014}
5015
43cf3bf0
CW		 5016void gen6_rps_busy(struct drm_i915_private *dev_priv)
5017{
5018 mutex_lock(&dev_priv->rps.hw_lock);
5019 if (dev_priv->rps.enabled) {
5020 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5021 gen6_rps_reset_ei(dev_priv);
5022 I915_WRITE(GEN6_PMINTRMSK,
5023 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5024
c33d247d
CW		 5025 gen6_enable_rps_interrupts(dev_priv);
5026
2b83c4c4
MW		 5027 /* Ensure we start at the user's desired frequency */
5028 intel_set_rps(dev_priv,
5029 clamp(dev_priv->rps.cur_freq,
5030 dev_priv->rps.min_freq_softlimit,
5031 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5032 }
5033 mutex_unlock(&dev_priv->rps.hw_lock);
5034}
5035
b29c19b6
CW		 5036void gen6_rps_idle(struct drm_i915_private *dev_priv)
5037{
c33d247d
CW		 5038 /* Flush our bottom-half so that it does not race with us
5039 * setting the idle frequency and so that it is bounded by
5040 * our rpm wakeref. And then disable the interrupts to stop any
5041 * futher RPS reclocking whilst we are asleep.
5042 */
5043 gen6_disable_rps_interrupts(dev_priv);
5044
b29c19b6 5045 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5046 if (dev_priv->rps.enabled) {
dc97997a 5047 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5048 vlv_set_rps_idle(dev_priv);
7526ed79 5049 else
dc97997a 5050 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5051 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5052 I915_WRITE(GEN6_PMINTRMSK,
5053 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5054 }
8d3afd7d 5055 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5056
8d3afd7d 5057 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5058 while (!list_empty(&dev_priv->rps.clients))
5059 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5060 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5061}
5062
1854d5ca 5063void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5064 struct intel_rps_client *rps,
5065 unsigned long submitted)
b29c19b6 5066{
8d3afd7d
CW		 5067 /* This is intentionally racy! We peek at the state here, then
5068 * validate inside the RPS worker.
5069 */
67d97da3 5070 if (!(dev_priv->gt.awake &&
8d3afd7d 5071 dev_priv->rps.enabled &&
29ecd78d 5072 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5073 return;
43cf3bf0 5074
e61b9958
CW		 5075 /* Force a RPS boost (and don't count it against the client) if
5076 * the GPU is severely congested.
5077 */
d0bc54f2 5078 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5079 rps = NULL;
5080
8d3afd7d
CW		 5081 spin_lock(&dev_priv->rps.client_lock);
5082 if (rps == NULL || list_empty(&rps->link)) {
5083 spin_lock_irq(&dev_priv->irq_lock);
5084 if (dev_priv->rps.interrupts_enabled) {
5085 dev_priv->rps.client_boost = true;
c33d247d 5086 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5087 }
5088 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5089
2e1b8730
CW		 5090 if (rps != NULL) {
5091 list_add(&rps->link, &dev_priv->rps.clients);
5092 rps->boosts++;
1854d5ca
CW		 5093 } else
5094 dev_priv->rps.boosts++;
c0951f0c 5095 }
8d3afd7d 5096 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5097}
5098
dc97997a 5099void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5100{
dc97997a
CW		 5101 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5102 valleyview_set_rps(dev_priv, val);
ffe02b40 5103 else
dc97997a 5104 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5105}
5106
dc97997a 5107static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5108{
20e49366 5109 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5110 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5111}
5112
dc97997a 5113static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5114{
2030d684
AG		 5115 I915_WRITE(GEN6_RP_CONTROL, 0);
5116}
5117
dc97997a 5118static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5119{
d20d4f0c 5120 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5121 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5122 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5123}
5124
dc97997a 5125static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5126{
38807746
D		 5127 I915_WRITE(GEN6_RC_CONTROL, 0);
5128}
5129
dc97997a 5130static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5131{
98a2e5f9
D		 5132 /* we're doing forcewake before Disabling RC6,
5133 * This what the BIOS expects when going into suspend */
59bad947 5134 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5135
44fc7d5c 5136 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5137
59bad947 5138 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5139}
5140
dc97997a 5141static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5142{
dc97997a 5143 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5144 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5145 mode = GEN6_RC_CTL_RC6_ENABLE;
5146 else
5147 mode = 0;
5148 }
dc97997a 5149 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5150 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5151 "RC6 %s RC6p %s RC6pp %s\n",
5152 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5153 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5154 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5155
5156 else
b99d49cc
ID		 5157 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5158 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5159}
5160
dc97997a 5161static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5162{
72e96d64 5163 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5164 bool enable_rc6 = true;
5165 unsigned long rc6_ctx_base;
fc619841
ID		 5166 u32 rc_ctl;
5167 int rc_sw_target;
5168
5169 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5170 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5171 RC_SW_TARGET_STATE_SHIFT;
5172 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5173 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5174 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5175 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5176 rc_sw_target);
274008e8
SAK		 5177
5178 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5179 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5180 enable_rc6 = false;
5181 }
5182
5183 /*
5184 * The exact context size is not known for BXT, so assume a page size
5185 * for this check.
5186 */
5187 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5188 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5189 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5190 ggtt->stolen_reserved_size))) {
b99d49cc 5191 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5192 enable_rc6 = false;
5193 }
5194
5195 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5196 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5197 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5198 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5199 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5200 enable_rc6 = false;
5201 }
5202
fc619841
ID		 5203 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5204 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5205 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5206 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5207 enable_rc6 = false;
5208 }
5209
5210 if (!I915_READ(GEN6_GFXPAUSE)) {
5211 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5212 enable_rc6 = false;
5213 }
5214
5215 if (!I915_READ(GEN8_MISC_CTRL0)) {
5216 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5217 enable_rc6 = false;
5218 }
5219
5220 return enable_rc6;
5221}
5222
dc97997a 5223int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5224{
e7d66d89 5225 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5226 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5227 return 0;
5228
274008e8
SAK		 5229 if (!enable_rc6)
5230 return 0;
5231
dc97997a 5232 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5233 DRM_INFO("RC6 disabled by BIOS\n");
5234 return 0;
5235 }
5236
456470eb 5237 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5238 if (enable_rc6 >= 0) {
5239 int mask;
5240
dc97997a 5241 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5242 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5243 INTEL_RC6pp_ENABLE;
5244 else
5245 mask = INTEL_RC6_ENABLE;
5246
5247 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5248 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5249 "(requested %d, valid %d)\n",
5250 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5251
5252 return enable_rc6 & mask;
5253 }
2b4e57bd 5254
dc97997a 5255 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5256 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5257
5258 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5259}
5260
dc97997a 5261static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5262{
5263 /* All of these values are in units of 50MHz */
773ea9a8 5264
93ee2920 5265 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5266 if (IS_BROXTON(dev_priv)) {
773ea9a8 5267 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5268 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5269 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5270 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5271 } else {
773ea9a8 5272 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5273 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5274 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5275 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5276 }
3280e8b0 5277 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5278 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5279
93ee2920 5280 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5281 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5282 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5283 u32 ddcc_status = 0;
5284
5285 if (sandybridge_pcode_read(dev_priv,
5286 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5287 &ddcc_status) == 0)
93ee2920 5288 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5289 clamp_t(u8,
5290 ((ddcc_status >> 8) & 0xff),
5291 dev_priv->rps.min_freq,
5292 dev_priv->rps.max_freq);
93ee2920
TR		 5293 }
5294
dc97997a 5295 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5296 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5297 * the natural hardware unit for SKL
5298 */
c5e0688c
AG		 5299 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5300 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5301 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5302 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5303 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5304 }
3280e8b0
BW		 5305}
5306
3a45b05c
CW		 5307static void reset_rps(struct drm_i915_private *dev_priv,
5308 void (*set)(struct drm_i915_private *, u8))
5309{
5310 u8 freq = dev_priv->rps.cur_freq;
5311
5312 /* force a reset */
5313 dev_priv->rps.power = -1;
5314 dev_priv->rps.cur_freq = -1;
5315
5316 set(dev_priv, freq);
5317}
5318
b6fef0ef 5319/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5320static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5321{
b6fef0ef
JB		 5322 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5323
23eafea6 5324 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5325 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5326 /*
5327 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5328 * clear out the Control register just to avoid inconsitency
5329 * with debugfs interface, which will show Turbo as enabled
5330 * only and that is not expected by the User after adding the
5331 * WaGsvDisableTurbo. Apart from this there is no problem even
5332 * if the Turbo is left enabled in the Control register, as the
5333 * Up/Down interrupts would remain masked.
5334 */
dc97997a 5335 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5336 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5337 return;
5338 }
5339
0beb059a
AG		 5340 /* Program defaults and thresholds for RPS*/
5341 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5342 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5343
5344 /* 1 second timeout*/
5345 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5346 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5347
b6fef0ef 5348 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5349
0beb059a
AG		 5350 /* Leaning on the below call to gen6_set_rps to program/setup the
5351 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5352 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5353 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5354
5355 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5356}
5357
dc97997a 5358static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5359{
e2f80391 5360 struct intel_engine_cs *engine;
3b3f1650 5361 enum intel_engine_id id;
20e49366 5362 uint32_t rc6_mask = 0;
20e49366
ZW		 5363
5364 /* 1a: Software RC state - RC0 */
5365 I915_WRITE(GEN6_RC_STATE, 0);
5366
5367 /* 1b: Get forcewake during program sequence. Although the driver
5368 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5369 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5370
5371 /* 2a: Disable RC states. */
5372 I915_WRITE(GEN6_RC_CONTROL, 0);
5373
5374 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5375
5376 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5377 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5378 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5379 else
5380 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5381 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5382 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5383 for_each_engine(engine, dev_priv, id)
e2f80391 5384 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5385
1a3d1898 5386 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5387 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5388
20e49366 5389 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5390
38c23527
ZW		 5391 /* 2c: Program Coarse Power Gating Policies. */
5392 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5393 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5394
20e49366 5395 /* 3a: Enable RC6 */
dc97997a 5396 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5397 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5398 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5399 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5400 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5401 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5402 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5403 GEN7_RC_CTL_TO_MODE |
5404 rc6_mask);
3e7732a0
SAK		 5405 } else {
5406 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5407 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5408 GEN6_RC_CTL_EI_MODE(1) |
5409 rc6_mask);
3e7732a0 5410 }
20e49366 5411
cb07bae0
SK		 5412 /*
5413 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5414 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5415 */
dc97997a 5416 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5417 I915_WRITE(GEN9_PG_ENABLE, 0);
5418 else
5419 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5420 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5421
59bad947 5422 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5423}
5424
dc97997a 5425static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5426{
e2f80391 5427 struct intel_engine_cs *engine;
3b3f1650 5428 enum intel_engine_id id;
93ee2920 5429 uint32_t rc6_mask = 0;
6edee7f3
BW		 5430
5431 /* 1a: Software RC state - RC0 */
5432 I915_WRITE(GEN6_RC_STATE, 0);
5433
5434 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5435 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5436 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5437
5438 /* 2a: Disable RC states. */
5439 I915_WRITE(GEN6_RC_CONTROL, 0);
5440
6edee7f3
BW		 5441 /* 2b: Program RC6 thresholds.*/
5442 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5443 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5444 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5445 for_each_engine(engine, dev_priv, id)
e2f80391 5446 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5447 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5448 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5449 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5450 else
5451 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5452
5453 /* 3: Enable RC6 */
dc97997a 5454 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5455 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5456 intel_print_rc6_info(dev_priv, rc6_mask);
5457 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5458 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5459 GEN7_RC_CTL_TO_MODE |
5460 rc6_mask);
5461 else
5462 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5463 GEN6_RC_CTL_EI_MODE(1) |
5464 rc6_mask);
6edee7f3
BW		 5465
5466 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5467 I915_WRITE(GEN6_RPNSWREQ,
5468 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5469 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5470 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5471 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5472 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5473
5474 /* Docs recommend 900MHz, and 300 MHz respectively */
5475 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5476 dev_priv->rps.max_freq_softlimit << 24 |
5477 dev_priv->rps.min_freq_softlimit << 16);
5478
5479 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5480 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5481 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5482 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5483
5484 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5485
5486 /* 5: Enable RPS */
7526ed79
DV		 5487 I915_WRITE(GEN6_RP_CONTROL,
5488 GEN6_RP_MEDIA_TURBO |
5489 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5490 GEN6_RP_MEDIA_IS_GFX |
5491 GEN6_RP_ENABLE |
5492 GEN6_RP_UP_BUSY_AVG |
5493 GEN6_RP_DOWN_IDLE_AVG);
5494
5495 /* 6: Ring frequency + overclocking (our driver does this later */
5496
3a45b05c 5497 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5498
59bad947 5499 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5500}
5501
dc97997a 5502static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5503{
e2f80391 5504 struct intel_engine_cs *engine;
3b3f1650 5505 enum intel_engine_id id;
99ac9612 5506 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5507 u32 gtfifodbg;
2b4e57bd 5508 int rc6_mode;
b4ac5afc 5509 int ret;
2b4e57bd 5510
4fc688ce 5511 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5512
2b4e57bd
ED		 5513 /* Here begins a magic sequence of register writes to enable
5514 * auto-downclocking.
5515 *
5516 * Perhaps there might be some value in exposing these to
5517 * userspace...
5518 */
5519 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5520
5521 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5522 gtfifodbg = I915_READ(GTFIFODBG);
5523 if (gtfifodbg) {
2b4e57bd
ED		 5524 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5525 I915_WRITE(GTFIFODBG, gtfifodbg);
5526 }
5527
59bad947 5528 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5529
5530 /* disable the counters and set deterministic thresholds */
5531 I915_WRITE(GEN6_RC_CONTROL, 0);
5532
5533 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5534 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5535 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5536 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5537 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5538
3b3f1650 5539 for_each_engine(engine, dev_priv, id)
e2f80391 5540 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5541
5542 I915_WRITE(GEN6_RC_SLEEP, 0);
5543 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5544 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5545 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5546 else
5547 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5548 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5549 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5550
5a7dc92a 5551 /* Check if we are enabling RC6 */
dc97997a 5552 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5553 if (rc6_mode & INTEL_RC6_ENABLE)
5554 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5555
5a7dc92a 5556 /* We don't use those on Haswell */
dc97997a 5557 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5558 if (rc6_mode & INTEL_RC6p_ENABLE)
5559 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5560
5a7dc92a
ED		 5561 if (rc6_mode & INTEL_RC6pp_ENABLE)
5562 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5563 }
2b4e57bd 5564
dc97997a 5565 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5566
5567 I915_WRITE(GEN6_RC_CONTROL,
5568 rc6_mask |
5569 GEN6_RC_CTL_EI_MODE(1) |
5570 GEN6_RC_CTL_HW_ENABLE);
5571
dd75fdc8
CW		 5572 /* Power down if completely idle for over 50ms */
5573 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5574 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5575
42c0526c 5576 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5577 if (ret)
42c0526c 5578 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5579
3a45b05c 5580 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5581
31643d54
BW		 5582 rc6vids = 0;
5583 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5584 if (IS_GEN6(dev_priv) && ret) {
31643d54 5585 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5586 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5587 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5588 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5589 rc6vids &= 0xffff00;
5590 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5591 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5592 if (ret)
5593 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5594 }
5595
59bad947 5596 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5597}
5598
fb7404e8 5599static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5600{
5601 int min_freq = 15;
3ebecd07
CW		 5602 unsigned int gpu_freq;
5603 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5604 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5605 int scaling_factor = 180;
eda79642 5606 struct cpufreq_policy *policy;
2b4e57bd 5607
4fc688ce 5608 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5609
eda79642
BW		 5610 policy = cpufreq_cpu_get(0);
5611 if (policy) {
5612 max_ia_freq = policy->cpuinfo.max_freq;
5613 cpufreq_cpu_put(policy);
5614 } else {
5615 /*
5616 * Default to measured freq if none found, PCU will ensure we
5617 * don't go over
5618 */
2b4e57bd 5619 max_ia_freq = tsc_khz;
eda79642 5620 }
2b4e57bd
ED		 5621
5622 /* Convert from kHz to MHz */
5623 max_ia_freq /= 1000;
5624
153b4b95 5625 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5626 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5627 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5628
dc97997a 5629 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5630 /* Convert GT frequency to 50 HZ units */
5631 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5632 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5633 } else {
5634 min_gpu_freq = dev_priv->rps.min_freq;
5635 max_gpu_freq = dev_priv->rps.max_freq;
5636 }
5637
2b4e57bd
ED		 5638 /*
5639 * For each potential GPU frequency, load a ring frequency we'd like
5640 * to use for memory access. We do this by specifying the IA frequency
5641 * the PCU should use as a reference to determine the ring frequency.
5642 */
4c8c7743
AG		 5643 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5644 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5645 unsigned int ia_freq = 0, ring_freq = 0;
5646
dc97997a 5647 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5648 /*
5649 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5650 * No floor required for ring frequency on SKL.
5651 */
5652 ring_freq = gpu_freq;
dc97997a 5653 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5654 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5655 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5656 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5657 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5658 ring_freq = max(min_ring_freq, ring_freq);
5659 /* leave ia_freq as the default, chosen by cpufreq */
5660 } else {
5661 /* On older processors, there is no separate ring
5662 * clock domain, so in order to boost the bandwidth
5663 * of the ring, we need to upclock the CPU (ia_freq).
5664 *
5665 * For GPU frequencies less than 750MHz,
5666 * just use the lowest ring freq.
5667 */
5668 if (gpu_freq < min_freq)
5669 ia_freq = 800;
5670 else
5671 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5672 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5673 }
2b4e57bd 5674
42c0526c
BW		 5675 sandybridge_pcode_write(dev_priv,
5676 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5677 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5678 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5679 gpu_freq);
2b4e57bd 5680 }
2b4e57bd
ED		 5681}
5682
03af2045 5683static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5684{
5685 u32 val, rp0;
5686
5b5929cb 5687 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5688
43b67998 5689 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5690 case 8:
5691 /* (2 * 4) config */
5692 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5693 break;
5694 case 12:
5695 /* (2 * 6) config */
5696 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5697 break;
5698 case 16:
5699 /* (2 * 8) config */
5700 default:
5701 /* Setting (2 * 8) Min RP0 for any other combination */
5702 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5703 break;
095acd5f 5704 }
5b5929cb
JN		 5705
5706 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5707
2b6b3a09
D		 5708 return rp0;
5709}
5710
5711static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5712{
5713 u32 val, rpe;
5714
5715 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5716 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5717
5718 return rpe;
5719}
5720
7707df4a
D		 5721static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5722{
5723 u32 val, rp1;
5724
5b5929cb
JN		 5725 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5726 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5727
7707df4a
D		 5728 return rp1;
5729}
5730
f8f2b001
D		 5731static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5732{
5733 u32 val, rp1;
5734
5735 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5736
5737 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5738
5739 return rp1;
5740}
5741
03af2045 5742static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5743{
5744 u32 val, rp0;
5745
64936258 5746 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5747
5748 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5749 /* Clamp to max */
5750 rp0 = min_t(u32, rp0, 0xea);
5751
5752 return rp0;
5753}
5754
5755static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5756{
5757 u32 val, rpe;
5758
64936258 5759 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5760 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5761 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5762 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5763
5764 return rpe;
5765}
5766
03af2045 5767static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5768{
36146035
ID		 5769 u32 val;
5770
5771 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5772 /*
5773 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5774 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5775 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5776 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5777 * to make sure it matches what Punit accepts.
5778 */
5779 return max_t(u32, val, 0xc0);
0a073b84
JB		 5780}
5781
ae48434c
ID		 5782/* Check that the pctx buffer wasn't move under us. */
5783static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5784{
5785 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5786
5787 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5788 dev_priv->vlv_pctx->stolen->start);
5789}
5790
38807746
D		 5791
5792/* Check that the pcbr address is not empty. */
5793static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5794{
5795 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5796
5797 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5798}
5799
dc97997a 5800static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5801{
62106b4f 5802 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5803 unsigned long pctx_paddr, paddr;
38807746
D		 5804 u32 pcbr;
5805 int pctx_size = 32*1024;
5806
38807746
D		 5807 pcbr = I915_READ(VLV_PCBR);
5808 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5809 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5810 paddr = (dev_priv->mm.stolen_base +
62106b4f 5811 (ggtt->stolen_size - pctx_size));
38807746
D		 5812
5813 pctx_paddr = (paddr & (~4095));
5814 I915_WRITE(VLV_PCBR, pctx_paddr);
5815 }
ce611ef8
VS		 5816
5817 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5818}
5819
dc97997a 5820static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5821{
c9cddffc
JB		 5822 struct drm_i915_gem_object *pctx;
5823 unsigned long pctx_paddr;
5824 u32 pcbr;
5825 int pctx_size = 24*1024;
5826
5827 pcbr = I915_READ(VLV_PCBR);
5828 if (pcbr) {
5829 /* BIOS set it up already, grab the pre-alloc'd space */
5830 int pcbr_offset;
5831
5832 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5833 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5834 pcbr_offset,
190d6cd5 5835 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5836 pctx_size);
5837 goto out;
5838 }
5839
ce611ef8
VS		 5840 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5841
c9cddffc
JB		 5842 /*
5843 * From the Gunit register HAS:
5844 * The Gfx driver is expected to program this register and ensure
5845 * proper allocation within Gfx stolen memory. For example, this
5846 * register should be programmed such than the PCBR range does not
5847 * overlap with other ranges, such as the frame buffer, protected
5848 * memory, or any other relevant ranges.
5849 */
91c8a326 5850 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5851 if (!pctx) {
5852 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5853 goto out;
c9cddffc
JB		 5854 }
5855
5856 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5857 I915_WRITE(VLV_PCBR, pctx_paddr);
5858
5859out:
ce611ef8 5860 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5861 dev_priv->vlv_pctx = pctx;
5862}
5863
dc97997a 5864static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5865{
ae48434c
ID		 5866 if (WARN_ON(!dev_priv->vlv_pctx))
5867 return;
5868
34911fd3 5869 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5870 dev_priv->vlv_pctx = NULL;
5871}
5872
c30fec65
VS		 5873static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5874{
5875 dev_priv->rps.gpll_ref_freq =
5876 vlv_get_cck_clock(dev_priv, "GPLL ref",
5877 CCK_GPLL_CLOCK_CONTROL,
5878 dev_priv->czclk_freq);
5879
5880 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5881 dev_priv->rps.gpll_ref_freq);
5882}
5883
dc97997a 5884static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5885{
2bb25c17 5886 u32 val;
4e80519e 5887
dc97997a 5888 valleyview_setup_pctx(dev_priv);
4e80519e 5889
c30fec65
VS		 5890 vlv_init_gpll_ref_freq(dev_priv);
5891
2bb25c17
VS		 5892 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5893 switch ((val >> 6) & 3) {
5894 case 0:
5895 case 1:
5896 dev_priv->mem_freq = 800;
5897 break;
5898 case 2:
5899 dev_priv->mem_freq = 1066;
5900 break;
5901 case 3:
5902 dev_priv->mem_freq = 1333;
5903 break;
5904 }
80b83b62 5905 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5906
4e80519e
ID		 5907 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5908 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5909 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5910 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5911 dev_priv->rps.max_freq);
5912
5913 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5914 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5915 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5916 dev_priv->rps.efficient_freq);
5917
f8f2b001
D		 5918 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5919 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5920 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5921 dev_priv->rps.rp1_freq);
5922
4e80519e
ID		 5923 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5924 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5925 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5926 dev_priv->rps.min_freq);
4e80519e
ID		 5927}
5928
dc97997a 5929static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5930{
2bb25c17 5931 u32 val;
2b6b3a09 5932
dc97997a 5933 cherryview_setup_pctx(dev_priv);
2b6b3a09 5934
c30fec65
VS		 5935 vlv_init_gpll_ref_freq(dev_priv);
5936
a580516d 5937 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5938 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5939 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5940
2bb25c17 5941 switch ((val >> 2) & 0x7) {
2bb25c17 5942 case 3:
2bb25c17
VS		 5943 dev_priv->mem_freq = 2000;
5944 break;
bfa7df01 5945 default:
2bb25c17
VS		 5946 dev_priv->mem_freq = 1600;
5947 break;
5948 }
80b83b62 5949 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5950
2b6b3a09
D		 5951 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5952 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5953 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5954 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5955 dev_priv->rps.max_freq);
5956
5957 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5958 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5959 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5960 dev_priv->rps.efficient_freq);
5961
7707df4a
D		 5962 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5963 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5964 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5965 dev_priv->rps.rp1_freq);
5966
5b7c91b7
D		 5967 /* PUnit validated range is only [RPe, RP0] */
5968 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5969 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5970 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5971 dev_priv->rps.min_freq);
5972
1c14762d
VS		 5973 WARN_ONCE((dev_priv->rps.max_freq |
5974 dev_priv->rps.efficient_freq |
5975 dev_priv->rps.rp1_freq |
5976 dev_priv->rps.min_freq) & 1,
5977 "Odd GPU freq values\n");
38807746
D		 5978}
5979
dc97997a 5980static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5981{
dc97997a 5982 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5983}
5984
dc97997a 5985static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5986{
e2f80391 5987 struct intel_engine_cs *engine;
3b3f1650 5988 enum intel_engine_id id;
2b6b3a09 5989 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5990
5991 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5992
297b32ec
VS		 5993 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5994 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5995 if (gtfifodbg) {
5996 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5997 gtfifodbg);
5998 I915_WRITE(GTFIFODBG, gtfifodbg);
5999 }
6000
6001 cherryview_check_pctx(dev_priv);
6002
6003 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6004 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6005 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6006
160614a2
VS		 6007 /* Disable RC states. */
6008 I915_WRITE(GEN6_RC_CONTROL, 0);
6009
38807746
D		 6010 /* 2a: Program RC6 thresholds.*/
6011 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6012 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6013 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6014
3b3f1650 6015 for_each_engine(engine, dev_priv, id)
e2f80391 6016 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6017 I915_WRITE(GEN6_RC_SLEEP, 0);
6018
f4f71c7d
D		 6019 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6020 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6021
6022 /* allows RC6 residency counter to work */
6023 I915_WRITE(VLV_COUNTER_CONTROL,
6024 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6025 VLV_MEDIA_RC6_COUNT_EN |
6026 VLV_RENDER_RC6_COUNT_EN));
6027
6028 /* For now we assume BIOS is allocating and populating the PCBR */
6029 pcbr = I915_READ(VLV_PCBR);
6030
38807746 6031 /* 3: Enable RC6 */
dc97997a
CW		 6032 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6033 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6034 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6035
6036 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6037
2b6b3a09 6038 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6039 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6040 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6041 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6042 I915_WRITE(GEN6_RP_UP_EI, 66000);
6043 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6044
6045 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6046
6047 /* 5: Enable RPS */
6048 I915_WRITE(GEN6_RP_CONTROL,
6049 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6050 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6051 GEN6_RP_ENABLE |
6052 GEN6_RP_UP_BUSY_AVG |
6053 GEN6_RP_DOWN_IDLE_AVG);
6054
3ef62342
D		 6055 /* Setting Fixed Bias */
6056 val = VLV_OVERRIDE_EN |
6057 VLV_SOC_TDP_EN |
6058 CHV_BIAS_CPU_50_SOC_50;
6059 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6060
2b6b3a09
D		 6061 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6062
8d40c3ae
VS		 6063 /* RPS code assumes GPLL is used */
6064 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6065
742f491d 6066 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6067 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6068
3a45b05c 6069 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6070
59bad947 6071 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6072}
6073
dc97997a 6074static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6075{
e2f80391 6076 struct intel_engine_cs *engine;
3b3f1650 6077 enum intel_engine_id id;
2a5913a8 6078 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6079
6080 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6081
ae48434c
ID		 6082 valleyview_check_pctx(dev_priv);
6083
297b32ec
VS		 6084 gtfifodbg = I915_READ(GTFIFODBG);
6085 if (gtfifodbg) {
f7d85c1e
JB		 6086 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6087 gtfifodbg);
0a073b84
JB		 6088 I915_WRITE(GTFIFODBG, gtfifodbg);
6089 }
6090
c8d9a590 6091 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6092 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6093
160614a2
VS		 6094 /* Disable RC states. */
6095 I915_WRITE(GEN6_RC_CONTROL, 0);
6096
cad725fe 6097 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6098 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6099 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6100 I915_WRITE(GEN6_RP_UP_EI, 66000);
6101 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6102
6103 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6104
6105 I915_WRITE(GEN6_RP_CONTROL,
6106 GEN6_RP_MEDIA_TURBO |
6107 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6108 GEN6_RP_MEDIA_IS_GFX |
6109 GEN6_RP_ENABLE |
6110 GEN6_RP_UP_BUSY_AVG |
6111 GEN6_RP_DOWN_IDLE_CONT);
6112
6113 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6114 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6115 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6116
3b3f1650 6117 for_each_engine(engine, dev_priv, id)
e2f80391 6118 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6119
2f0aa304 6120 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6121
6122 /* allows RC6 residency counter to work */
49798eb2 6123 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6124 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6125 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6126 VLV_MEDIA_RC6_COUNT_EN |
6127 VLV_RENDER_RC6_COUNT_EN));
31685c25 6128
dc97997a 6129 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6130 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6131
dc97997a 6132 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6133
a2b23fe0 6134 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6135
3ef62342
D		 6136 /* Setting Fixed Bias */
6137 val = VLV_OVERRIDE_EN |
6138 VLV_SOC_TDP_EN |
6139 VLV_BIAS_CPU_125_SOC_875;
6140 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6141
64936258 6142 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6143
8d40c3ae
VS		 6144 /* RPS code assumes GPLL is used */
6145 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6146
742f491d 6147 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6148 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6149
3a45b05c 6150 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6151
59bad947 6152 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6153}
6154
dde18883
ED		 6155static unsigned long intel_pxfreq(u32 vidfreq)
6156{
6157 unsigned long freq;
6158 int div = (vidfreq & 0x3f0000) >> 16;
6159 int post = (vidfreq & 0x3000) >> 12;
6160 int pre = (vidfreq & 0x7);
6161
6162 if (!pre)
6163 return 0;
6164
6165 freq = ((div * 133333) / ((1<<post) * pre));
6166
6167 return freq;
6168}
6169
eb48eb00
DV		 6170static const struct cparams {
6171 u16 i;
6172 u16 t;
6173 u16 m;
6174 u16 c;
6175} cparams[] = {
6176 { 1, 1333, 301, 28664 },
6177 { 1, 1066, 294, 24460 },
6178 { 1, 800, 294, 25192 },
6179 { 0, 1333, 276, 27605 },
6180 { 0, 1066, 276, 27605 },
6181 { 0, 800, 231, 23784 },
6182};
6183
f531dcb2 6184static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6185{
6186 u64 total_count, diff, ret;
6187 u32 count1, count2, count3, m = 0, c = 0;
6188 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6189 int i;
6190
02d71956
DV		 6191 assert_spin_locked(&mchdev_lock);
6192
20e4d407 6193 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6194
6195 /* Prevent division-by-zero if we are asking too fast.
6196 * Also, we don't get interesting results if we are polling
6197 * faster than once in 10ms, so just return the saved value
6198 * in such cases.
6199 */
6200 if (diff1 <= 10)
20e4d407 6201 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6202
6203 count1 = I915_READ(DMIEC);
6204 count2 = I915_READ(DDREC);
6205 count3 = I915_READ(CSIEC);
6206
6207 total_count = count1 + count2 + count3;
6208
6209 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6210 if (total_count < dev_priv->ips.last_count1) {
6211 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6212 diff += total_count;
6213 } else {
20e4d407 6214 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6215 }
6216
6217 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6218 if (cparams[i].i == dev_priv->ips.c_m &&
6219 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6220 m = cparams[i].m;
6221 c = cparams[i].c;
6222 break;
6223 }
6224 }
6225
6226 diff = div_u64(diff, diff1);
6227 ret = ((m * diff) + c);
6228 ret = div_u64(ret, 10);
6229
20e4d407
DV		 6230 dev_priv->ips.last_count1 = total_count;
6231 dev_priv->ips.last_time1 = now;
eb48eb00 6232
20e4d407 6233 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6234
6235 return ret;
6236}
6237
f531dcb2
CW		 6238unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6239{
6240 unsigned long val;
6241
dc97997a 6242 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6243 return 0;
6244
6245 spin_lock_irq(&mchdev_lock);
6246
6247 val = __i915_chipset_val(dev_priv);
6248
6249 spin_unlock_irq(&mchdev_lock);
6250
6251 return val;
6252}
6253
eb48eb00
DV		 6254unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6255{
6256 unsigned long m, x, b;
6257 u32 tsfs;
6258
6259 tsfs = I915_READ(TSFS);
6260
6261 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6262 x = I915_READ8(TR1);
6263
6264 b = tsfs & TSFS_INTR_MASK;
6265
6266 return ((m * x) / 127) - b;
6267}
6268
d972d6ee
MK		 6269static int _pxvid_to_vd(u8 pxvid)
6270{
6271 if (pxvid == 0)
6272 return 0;
6273
6274 if (pxvid >= 8 && pxvid < 31)
6275 pxvid = 31;
6276
6277 return (pxvid + 2) * 125;
6278}
6279
6280static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6281{
d972d6ee
MK		 6282 const int vd = _pxvid_to_vd(pxvid);
6283 const int vm = vd - 1125;
6284
dc97997a 6285 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6286 return vm > 0 ? vm : 0;
6287
6288 return vd;
eb48eb00
DV		 6289}
6290
02d71956 6291static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6292{
5ed0bdf2 6293 u64 now, diff, diffms;
eb48eb00
DV		 6294 u32 count;
6295
02d71956 6296 assert_spin_locked(&mchdev_lock);
eb48eb00 6297
5ed0bdf2
TG		 6298 now = ktime_get_raw_ns();
6299 diffms = now - dev_priv->ips.last_time2;
6300 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6301
6302 /* Don't divide by 0 */
eb48eb00
DV		 6303 if (!diffms)
6304 return;
6305
6306 count = I915_READ(GFXEC);
6307
20e4d407
DV		 6308 if (count < dev_priv->ips.last_count2) {
6309 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6310 diff += count;
6311 } else {
20e4d407 6312 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6313 }
6314
20e4d407
DV		 6315 dev_priv->ips.last_count2 = count;
6316 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6317
6318 /* More magic constants... */
6319 diff = diff * 1181;
6320 diff = div_u64(diff, diffms * 10);
20e4d407 6321 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6322}
6323
02d71956
DV		 6324void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6325{
dc97997a 6326 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6327 return;
6328
9270388e 6329 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6330
6331 __i915_update_gfx_val(dev_priv);
6332
9270388e 6333 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6334}
6335
f531dcb2 6336static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6337{
6338 unsigned long t, corr, state1, corr2, state2;
6339 u32 pxvid, ext_v;
6340
02d71956
DV		 6341 assert_spin_locked(&mchdev_lock);
6342
616847e7 6343 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6344 pxvid = (pxvid >> 24) & 0x7f;
6345 ext_v = pvid_to_extvid(dev_priv, pxvid);
6346
6347 state1 = ext_v;
6348
6349 t = i915_mch_val(dev_priv);
6350
6351 /* Revel in the empirically derived constants */
6352
6353 /* Correction factor in 1/100000 units */
6354 if (t > 80)
6355 corr = ((t * 2349) + 135940);
6356 else if (t >= 50)
6357 corr = ((t * 964) + 29317);
6358 else /* < 50 */
6359 corr = ((t * 301) + 1004);
6360
6361 corr = corr * ((150142 * state1) / 10000 - 78642);
6362 corr /= 100000;
20e4d407 6363 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6364
6365 state2 = (corr2 * state1) / 10000;
6366 state2 /= 100; /* convert to mW */
6367
02d71956 6368 __i915_update_gfx_val(dev_priv);
eb48eb00 6369
20e4d407 6370 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6371}
6372
f531dcb2
CW		 6373unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6374{
6375 unsigned long val;
6376
dc97997a 6377 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6378 return 0;
6379
6380 spin_lock_irq(&mchdev_lock);
6381
6382 val = __i915_gfx_val(dev_priv);
6383
6384 spin_unlock_irq(&mchdev_lock);
6385
6386 return val;
6387}
6388
eb48eb00
DV		 6389/**
6390 * i915_read_mch_val - return value for IPS use
6391 *
6392 * Calculate and return a value for the IPS driver to use when deciding whether
6393 * we have thermal and power headroom to increase CPU or GPU power budget.
6394 */
6395unsigned long i915_read_mch_val(void)
6396{
6397 struct drm_i915_private *dev_priv;
6398 unsigned long chipset_val, graphics_val, ret = 0;
6399
9270388e 6400 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6401 if (!i915_mch_dev)
6402 goto out_unlock;
6403 dev_priv = i915_mch_dev;
6404
f531dcb2
CW		 6405 chipset_val = __i915_chipset_val(dev_priv);
6406 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6407
6408 ret = chipset_val + graphics_val;
6409
6410out_unlock:
9270388e 6411 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6412
6413 return ret;
6414}
6415EXPORT_SYMBOL_GPL(i915_read_mch_val);
6416
6417/**
6418 * i915_gpu_raise - raise GPU frequency limit
6419 *
6420 * Raise the limit; IPS indicates we have thermal headroom.
6421 */
6422bool i915_gpu_raise(void)
6423{
6424 struct drm_i915_private *dev_priv;
6425 bool ret = true;
6426
9270388e 6427 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6428 if (!i915_mch_dev) {
6429 ret = false;
6430 goto out_unlock;
6431 }
6432 dev_priv = i915_mch_dev;
6433
20e4d407
DV		 6434 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6435 dev_priv->ips.max_delay--;
eb48eb00
DV		 6436
6437out_unlock:
9270388e 6438 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6439
6440 return ret;
6441}
6442EXPORT_SYMBOL_GPL(i915_gpu_raise);
6443
6444/**
6445 * i915_gpu_lower - lower GPU frequency limit
6446 *
6447 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6448 * frequency maximum.
6449 */
6450bool i915_gpu_lower(void)
6451{
6452 struct drm_i915_private *dev_priv;
6453 bool ret = true;
6454
9270388e 6455 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6456 if (!i915_mch_dev) {
6457 ret = false;
6458 goto out_unlock;
6459 }
6460 dev_priv = i915_mch_dev;
6461
20e4d407
DV		 6462 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6463 dev_priv->ips.max_delay++;
eb48eb00
DV		 6464
6465out_unlock:
9270388e 6466 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6467
6468 return ret;
6469}
6470EXPORT_SYMBOL_GPL(i915_gpu_lower);
6471
6472/**
6473 * i915_gpu_busy - indicate GPU business to IPS
6474 *
6475 * Tell the IPS driver whether or not the GPU is busy.
6476 */
6477bool i915_gpu_busy(void)
6478{
eb48eb00
DV		 6479 bool ret = false;
6480
9270388e 6481 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6482 if (i915_mch_dev)
6483 ret = i915_mch_dev->gt.awake;
9270388e 6484 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6485
6486 return ret;
6487}
6488EXPORT_SYMBOL_GPL(i915_gpu_busy);
6489
6490/**
6491 * i915_gpu_turbo_disable - disable graphics turbo
6492 *
6493 * Disable graphics turbo by resetting the max frequency and setting the
6494 * current frequency to the default.
6495 */
6496bool i915_gpu_turbo_disable(void)
6497{
6498 struct drm_i915_private *dev_priv;
6499 bool ret = true;
6500
9270388e 6501 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6502 if (!i915_mch_dev) {
6503 ret = false;
6504 goto out_unlock;
6505 }
6506 dev_priv = i915_mch_dev;
6507
20e4d407 6508 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6509
91d14251 6510 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6511 ret = false;
6512
6513out_unlock:
9270388e 6514 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6515
6516 return ret;
6517}
6518EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6519
6520/**
6521 * Tells the intel_ips driver that the i915 driver is now loaded, if
6522 * IPS got loaded first.
6523 *
6524 * This awkward dance is so that neither module has to depend on the
6525 * other in order for IPS to do the appropriate communication of
6526 * GPU turbo limits to i915.
6527 */
6528static void
6529ips_ping_for_i915_load(void)
6530{
6531 void (*link)(void);
6532
6533 link = symbol_get(ips_link_to_i915_driver);
6534 if (link) {
6535 link();
6536 symbol_put(ips_link_to_i915_driver);
6537 }
6538}
6539
6540void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6541{
02d71956
DV		 6542 /* We only register the i915 ips part with intel-ips once everything is
6543 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6544 spin_lock_irq(&mchdev_lock);
eb48eb00 6545 i915_mch_dev = dev_priv;
9270388e 6546 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6547
6548 ips_ping_for_i915_load();
6549}
6550
6551void intel_gpu_ips_teardown(void)
6552{
9270388e 6553 spin_lock_irq(&mchdev_lock);
eb48eb00 6554 i915_mch_dev = NULL;
9270388e 6555 spin_unlock_irq(&mchdev_lock);
eb48eb00 6556}
76c3552f 6557
dc97997a 6558static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6559{
dde18883
ED		 6560 u32 lcfuse;
6561 u8 pxw[16];
6562 int i;
6563
6564 /* Disable to program */
6565 I915_WRITE(ECR, 0);
6566 POSTING_READ(ECR);
6567
6568 /* Program energy weights for various events */
6569 I915_WRITE(SDEW, 0x15040d00);
6570 I915_WRITE(CSIEW0, 0x007f0000);
6571 I915_WRITE(CSIEW1, 0x1e220004);
6572 I915_WRITE(CSIEW2, 0x04000004);
6573
6574 for (i = 0; i < 5; i++)
616847e7 6575 I915_WRITE(PEW(i), 0);
dde18883 6576 for (i = 0; i < 3; i++)
616847e7 6577 I915_WRITE(DEW(i), 0);
dde18883
ED		 6578
6579 /* Program P-state weights to account for frequency power adjustment */
6580 for (i = 0; i < 16; i++) {
616847e7 6581 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6582 unsigned long freq = intel_pxfreq(pxvidfreq);
6583 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6584 PXVFREQ_PX_SHIFT;
6585 unsigned long val;
6586
6587 val = vid * vid;
6588 val *= (freq / 1000);
6589 val *= 255;
6590 val /= (127*127*900);
6591 if (val > 0xff)
6592 DRM_ERROR("bad pxval: %ld\n", val);
6593 pxw[i] = val;
6594 }
6595 /* Render standby states get 0 weight */
6596 pxw[14] = 0;
6597 pxw[15] = 0;
6598
6599 for (i = 0; i < 4; i++) {
6600 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6601 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6602 I915_WRITE(PXW(i), val);
dde18883
ED		 6603 }
6604
6605 /* Adjust magic regs to magic values (more experimental results) */
6606 I915_WRITE(OGW0, 0);
6607 I915_WRITE(OGW1, 0);
6608 I915_WRITE(EG0, 0x00007f00);
6609 I915_WRITE(EG1, 0x0000000e);
6610 I915_WRITE(EG2, 0x000e0000);
6611 I915_WRITE(EG3, 0x68000300);
6612 I915_WRITE(EG4, 0x42000000);
6613 I915_WRITE(EG5, 0x00140031);
6614 I915_WRITE(EG6, 0);
6615 I915_WRITE(EG7, 0);
6616
6617 for (i = 0; i < 8; i++)
616847e7 6618 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6619
6620 /* Enable PMON + select events */
6621 I915_WRITE(ECR, 0x80000019);
6622
6623 lcfuse = I915_READ(LCFUSE02);
6624
20e4d407 6625 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6626}
6627
dc97997a 6628void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6629{
b268c699
ID		 6630 /*
6631 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6632 * requirement.
6633 */
6634 if (!i915.enable_rc6) {
6635 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6636 intel_runtime_pm_get(dev_priv);
6637 }
e6069ca8 6638
b5163dbb 6639 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6640 mutex_lock(&dev_priv->rps.hw_lock);
6641
6642 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6643 if (IS_CHERRYVIEW(dev_priv))
6644 cherryview_init_gt_powersave(dev_priv);
6645 else if (IS_VALLEYVIEW(dev_priv))
6646 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6647 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6648 gen6_init_rps_frequencies(dev_priv);
6649
6650 /* Derive initial user preferences/limits from the hardware limits */
6651 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6652 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6653
6654 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6655 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6656
6657 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6658 dev_priv->rps.min_freq_softlimit =
6659 max_t(int,
6660 dev_priv->rps.efficient_freq,
6661 intel_freq_opcode(dev_priv, 450));
6662
99ac9612
CW		 6663 /* After setting max-softlimit, find the overclock max freq */
6664 if (IS_GEN6(dev_priv) ||
6665 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6666 u32 params = 0;
6667
6668 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6669 if (params & BIT(31)) { /* OC supported */
6670 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6671 (dev_priv->rps.max_freq & 0xff) * 50,
6672 (params & 0xff) * 50);
6673 dev_priv->rps.max_freq = params & 0xff;
6674 }
6675 }
6676
29ecd78d
CW		 6677 /* Finally allow us to boost to max by default */
6678 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6679
773ea9a8 6680 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6681 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6682
6683 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6684}
6685
dc97997a 6686void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6687{
8dac1e1f 6688 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6689 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6690
6691 if (!i915.enable_rc6)
6692 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6693}
6694
54b4f68f
CW		 6695/**
6696 * intel_suspend_gt_powersave - suspend PM work and helper threads
6697 * @dev_priv: i915 device
6698 *
6699 * We don't want to disable RC6 or other features here, we just want
6700 * to make sure any work we've queued has finished and won't bother
6701 * us while we're suspended.
6702 */
6703void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6704{
6705 if (INTEL_GEN(dev_priv) < 6)
6706 return;
6707
6708 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6709 intel_runtime_pm_put(dev_priv);
6710
6711 /* gen6_rps_idle() will be called later to disable interrupts */
6712}
6713
b7137e0c
CW		 6714void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6715{
6716 dev_priv->rps.enabled = true; /* force disabling */
6717 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6718
6719 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6720}
6721
dc97997a 6722void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6723{
b7137e0c
CW		 6724 if (!READ_ONCE(dev_priv->rps.enabled))
6725 return;
e494837a 6726
b7137e0c 6727 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6728
b7137e0c
CW		 6729 if (INTEL_GEN(dev_priv) >= 9) {
6730 gen9_disable_rc6(dev_priv);
6731 gen9_disable_rps(dev_priv);
6732 } else if (IS_CHERRYVIEW(dev_priv)) {
6733 cherryview_disable_rps(dev_priv);
6734 } else if (IS_VALLEYVIEW(dev_priv)) {
6735 valleyview_disable_rps(dev_priv);
6736 } else if (INTEL_GEN(dev_priv) >= 6) {
6737 gen6_disable_rps(dev_priv);
6738 } else if (IS_IRONLAKE_M(dev_priv)) {
6739 ironlake_disable_drps(dev_priv);
930ebb46 6740 }
b7137e0c
CW		 6741
6742 dev_priv->rps.enabled = false;
6743 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6744}
6745
b7137e0c 6746void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6747{
54b4f68f
CW		 6748 /* We shouldn't be disabling as we submit, so this should be less
6749 * racy than it appears!
6750 */
b7137e0c
CW		 6751 if (READ_ONCE(dev_priv->rps.enabled))
6752 return;
1a01ab3b 6753
b7137e0c
CW		 6754 /* Powersaving is controlled by the host when inside a VM */
6755 if (intel_vgpu_active(dev_priv))
6756 return;
0a073b84 6757
b7137e0c 6758 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6759
6760 if (IS_CHERRYVIEW(dev_priv)) {
6761 cherryview_enable_rps(dev_priv);
6762 } else if (IS_VALLEYVIEW(dev_priv)) {
6763 valleyview_enable_rps(dev_priv);
b7137e0c 6764 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6765 gen9_enable_rc6(dev_priv);
6766 gen9_enable_rps(dev_priv);
6767 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6768 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6769 } else if (IS_BROADWELL(dev_priv)) {
6770 gen8_enable_rps(dev_priv);
fb7404e8 6771 gen6_update_ring_freq(dev_priv);
b7137e0c 6772 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6773 gen6_enable_rps(dev_priv);
fb7404e8 6774 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6775 } else if (IS_IRONLAKE_M(dev_priv)) {
6776 ironlake_enable_drps(dev_priv);
6777 intel_init_emon(dev_priv);
0a073b84 6778 }
aed242ff
CW		 6779
6780 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6781 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6782
6783 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6784 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6785
54b4f68f 6786 dev_priv->rps.enabled = true;
b7137e0c
CW		 6787 mutex_unlock(&dev_priv->rps.hw_lock);
6788}
3cc134e3 6789
54b4f68f
CW		 6790static void __intel_autoenable_gt_powersave(struct work_struct *work)
6791{
6792 struct drm_i915_private *dev_priv =
6793 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6794 struct intel_engine_cs *rcs;
6795 struct drm_i915_gem_request *req;
6796
6797 if (READ_ONCE(dev_priv->rps.enabled))
6798 goto out;
6799
3b3f1650 6800 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6801 if (rcs->last_context)
6802 goto out;
6803
6804 if (!rcs->init_context)
6805 goto out;
6806
6807 mutex_lock(&dev_priv->drm.struct_mutex);
6808
6809 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6810 if (IS_ERR(req))
6811 goto unlock;
6812
6813 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6814 rcs->init_context(req);
6815
6816 /* Mark the device busy, calling intel_enable_gt_powersave() */
6817 i915_add_request_no_flush(req);
6818
6819unlock:
6820 mutex_unlock(&dev_priv->drm.struct_mutex);
6821out:
6822 intel_runtime_pm_put(dev_priv);
6823}
6824
6825void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6826{
6827 if (READ_ONCE(dev_priv->rps.enabled))
6828 return;
6829
6830 if (IS_IRONLAKE_M(dev_priv)) {
6831 ironlake_enable_drps(dev_priv);
54b4f68f 6832 intel_init_emon(dev_priv);
54b4f68f
CW		 6833 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6834 /*
6835 * PCU communication is slow and this doesn't need to be
6836 * done at any specific time, so do this out of our fast path
6837 * to make resume and init faster.
6838 *
6839 * We depend on the HW RC6 power context save/restore
6840 * mechanism when entering D3 through runtime PM suspend. So
6841 * disable RPM until RPS/RC6 is properly setup. We can only
6842 * get here via the driver load/system resume/runtime resume
6843 * paths, so the _noresume version is enough (and in case of
6844 * runtime resume it's necessary).
6845 */
6846 if (queue_delayed_work(dev_priv->wq,
6847 &dev_priv->rps.autoenable_work,
6848 round_jiffies_up_relative(HZ)))
6849 intel_runtime_pm_get_noresume(dev_priv);
6850 }
6851}
6852
3107bd48
DV		 6853static void ibx_init_clock_gating(struct drm_device *dev)
6854{
fac5e23e 6855 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6856
6857 /*
6858 * On Ibex Peak and Cougar Point, we need to disable clock
6859 * gating for the panel power sequencer or it will fail to
6860 * start up when no ports are active.
6861 */
6862 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6863}
6864
0e088b8f
VS		 6865static void g4x_disable_trickle_feed(struct drm_device *dev)
6866{
fac5e23e 6867 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6868 enum pipe pipe;
0e088b8f 6869
055e393f 6870 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6871 I915_WRITE(DSPCNTR(pipe),
6872 I915_READ(DSPCNTR(pipe)) |
6873 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6874
6875 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6876 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6877 }
6878}
6879
017636cc
VS		 6880static void ilk_init_lp_watermarks(struct drm_device *dev)
6881{
fac5e23e 6882 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6883
6884 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6885 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6886 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6887
6888 /*
6889 * Don't touch WM1S_LP_EN here.
6890 * Doing so could cause underruns.
6891 */
6892}
6893
1fa61106 6894static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6895{
fac5e23e 6896 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6897 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6898
f1e8fa56
DL		 6899 /*
6900 * Required for FBC
6901 * WaFbcDisableDpfcClockGating:ilk
6902 */
4d47e4f5
DL		 6903 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6904 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6905 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6906
6907 I915_WRITE(PCH_3DCGDIS0,
6908 MARIUNIT_CLOCK_GATE_DISABLE |
6909 SVSMUNIT_CLOCK_GATE_DISABLE);
6910 I915_WRITE(PCH_3DCGDIS1,
6911 VFMUNIT_CLOCK_GATE_DISABLE);
6912
6f1d69b0
ED		 6913 /*
6914 * According to the spec the following bits should be set in
6915 * order to enable memory self-refresh
6916 * The bit 22/21 of 0x42004
6917 * The bit 5 of 0x42020
6918 * The bit 15 of 0x45000
6919 */
6920 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6921 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6922 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6923 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6924 I915_WRITE(DISP_ARB_CTL,
6925 (I915_READ(DISP_ARB_CTL) |
6926 DISP_FBC_WM_DIS));
017636cc
VS		 6927
6928 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6929
6930 /*
6931 * Based on the document from hardware guys the following bits
6932 * should be set unconditionally in order to enable FBC.
6933 * The bit 22 of 0x42000
6934 * The bit 22 of 0x42004
6935 * The bit 7,8,9 of 0x42020.
6936 */
50a0bc90 6937 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6938 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6939 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6940 I915_READ(ILK_DISPLAY_CHICKEN1) |
6941 ILK_FBCQ_DIS);
6942 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6943 I915_READ(ILK_DISPLAY_CHICKEN2) |
6944 ILK_DPARB_GATE);
6f1d69b0
ED		 6945 }
6946
4d47e4f5
DL		 6947 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6948
6f1d69b0
ED		 6949 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6950 I915_READ(ILK_DISPLAY_CHICKEN2) |
6951 ILK_ELPIN_409_SELECT);
6952 I915_WRITE(_3D_CHICKEN2,
6953 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6954 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6955
ecdb4eb7 6956 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6957 I915_WRITE(CACHE_MODE_0,
6958 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6959
4e04632e
AG		 6960 /* WaDisable_RenderCache_OperationalFlush:ilk */
6961 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6962
0e088b8f 6963 g4x_disable_trickle_feed(dev);
bdad2b2f 6964
3107bd48
DV		 6965 ibx_init_clock_gating(dev);
6966}
6967
6968static void cpt_init_clock_gating(struct drm_device *dev)
6969{
fac5e23e 6970 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6971 int pipe;
3f704fa2 6972 uint32_t val;
3107bd48
DV		 6973
6974 /*
6975 * On Ibex Peak and Cougar Point, we need to disable clock
6976 * gating for the panel power sequencer or it will fail to
6977 * start up when no ports are active.
6978 */
cd664078
JB		 6979 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6980 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6981 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6982 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6983 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6984 /* The below fixes the weird display corruption, a few pixels shifted
6985 * downward, on (only) LVDS of some HP laptops with IVY.
6986 */
055e393f 6987 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6988 val = I915_READ(TRANS_CHICKEN2(pipe));
6989 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6990 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6991 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6992 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6993 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6994 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6995 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6996 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6997 }
3107bd48 6998 /* WADP0ClockGatingDisable */
055e393f 6999 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7000 I915_WRITE(TRANS_CHICKEN1(pipe),
7001 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7002 }
6f1d69b0
ED		 7003}
7004
1d7aaa0c
DV		 7005static void gen6_check_mch_setup(struct drm_device *dev)
7006{
fac5e23e 7007 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7008 uint32_t tmp;
7009
7010 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7011 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7012 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7013 tmp);
1d7aaa0c
DV		 7014}
7015
1fa61106 7016static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7017{
fac5e23e 7018 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7019 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7020
231e54f6 7021 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7022
7023 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7024 I915_READ(ILK_DISPLAY_CHICKEN2) |
7025 ILK_ELPIN_409_SELECT);
7026
ecdb4eb7 7027 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7028 I915_WRITE(_3D_CHICKEN,
7029 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7030
4e04632e
AG		 7031 /* WaDisable_RenderCache_OperationalFlush:snb */
7032 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7033
8d85d272
VS		 7034 /*
7035 * BSpec recoomends 8x4 when MSAA is used,
7036 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7037 *
7038 * Note that PS/WM thread counts depend on the WIZ hashing
7039 * disable bit, which we don't touch here, but it's good
7040 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7041 */
7042 I915_WRITE(GEN6_GT_MODE,
98533251 7043 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7044
017636cc 7045 ilk_init_lp_watermarks(dev);
6f1d69b0 7046
6f1d69b0 7047 I915_WRITE(CACHE_MODE_0,
50743298 7048 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7049
7050 I915_WRITE(GEN6_UCGCTL1,
7051 I915_READ(GEN6_UCGCTL1) |
7052 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7053 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7054
7055 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7056 * gating disable must be set. Failure to set it results in
7057 * flickering pixels due to Z write ordering failures after
7058 * some amount of runtime in the Mesa "fire" demo, and Unigine
7059 * Sanctuary and Tropics, and apparently anything else with
7060 * alpha test or pixel discard.
7061 *
7062 * According to the spec, bit 11 (RCCUNIT) must also be set,
7063 * but we didn't debug actual testcases to find it out.
0f846f81 7064 *
ef59318c
VS		 7065 * WaDisableRCCUnitClockGating:snb
7066 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7067 */
7068 I915_WRITE(GEN6_UCGCTL2,
7069 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7070 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7071
5eb146dd 7072 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7073 I915_WRITE(_3D_CHICKEN3,
7074 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7075
e927ecde
VS		 7076 /*
7077 * Bspec says:
7078 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7079 * 3DSTATE_SF number of SF output attributes is more than 16."
7080 */
7081 I915_WRITE(_3D_CHICKEN3,
7082 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7083
6f1d69b0
ED		 7084 /*
7085 * According to the spec the following bits should be
7086 * set in order to enable memory self-refresh and fbc:
7087 * The bit21 and bit22 of 0x42000
7088 * The bit21 and bit22 of 0x42004
7089 * The bit5 and bit7 of 0x42020
7090 * The bit14 of 0x70180
7091 * The bit14 of 0x71180
4bb35334
DL		 7092 *
7093 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7094 */
7095 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7096 I915_READ(ILK_DISPLAY_CHICKEN1) |
7097 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7098 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7099 I915_READ(ILK_DISPLAY_CHICKEN2) |
7100 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7101 I915_WRITE(ILK_DSPCLK_GATE_D,
7102 I915_READ(ILK_DSPCLK_GATE_D) |
7103 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7104 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7105
0e088b8f 7106 g4x_disable_trickle_feed(dev);
f8f2ac9a 7107
3107bd48 7108 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7109
7110 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7111}
7112
7113static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7114{
7115 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7116
3aad9059 7117 /*
46680e0a 7118 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7119 *
7120 * This actually overrides the dispatch
7121 * mode for all thread types.
7122 */
6f1d69b0
ED		 7123 reg &= ~GEN7_FF_SCHED_MASK;
7124 reg |= GEN7_FF_TS_SCHED_HW;
7125 reg |= GEN7_FF_VS_SCHED_HW;
7126 reg |= GEN7_FF_DS_SCHED_HW;
7127
7128 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7129}
7130
17a303ec
PZ		 7131static void lpt_init_clock_gating(struct drm_device *dev)
7132{
fac5e23e 7133 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7134
7135 /*
7136 * TODO: this bit should only be enabled when really needed, then
7137 * disabled when not needed anymore in order to save power.
7138 */
4f8036a2 7139 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7140 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7141 I915_READ(SOUTH_DSPCLK_GATE_D) |
7142 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7143
7144 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7145 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7146 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7147 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7148}
7149
7d708ee4
ID		 7150static void lpt_suspend_hw(struct drm_device *dev)
7151{
fac5e23e 7152 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7153
4f8036a2 7154 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7155 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7156
7157 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7158 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7159 }
7160}
7161
450174fe
ID		 7162static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7163 int general_prio_credits,
7164 int high_prio_credits)
7165{
7166 u32 misccpctl;
7167
7168 /* WaTempDisableDOPClkGating:bdw */
7169 misccpctl = I915_READ(GEN7_MISCCPCTL);
7170 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7171
7172 I915_WRITE(GEN8_L3SQCREG1,
7173 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7174 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7175
7176 /*
7177 * Wait at least 100 clocks before re-enabling clock gating.
7178 * See the definition of L3SQCREG1 in BSpec.
7179 */
7180 POSTING_READ(GEN8_L3SQCREG1);
7181 udelay(1);
7182 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7183}
7184
9498dba7
MK		 7185static void kabylake_init_clock_gating(struct drm_device *dev)
7186{
9146f308 7187 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7188
b033bb6d 7189 gen9_init_clock_gating(dev);
9498dba7
MK		 7190
7191 /* WaDisableSDEUnitClockGating:kbl */
7192 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7193 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7194 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7195
7196 /* WaDisableGamClockGating:kbl */
7197 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7198 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7199 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7200
7201 /* WaFbcNukeOnHostModify:kbl */
7202 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7203 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7204}
7205
dc00b6a0
DV		 7206static void skylake_init_clock_gating(struct drm_device *dev)
7207{
c584e2d3 7208 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7209
b033bb6d 7210 gen9_init_clock_gating(dev);
44fff99f
MK		 7211
7212 /* WAC6entrylatency:skl */
7213 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7214 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7215
7216 /* WaFbcNukeOnHostModify:skl */
7217 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7218 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7219}
7220
47c2bd97 7221static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7222{
fac5e23e 7223 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7224 enum pipe pipe;
1020a5c2 7225
7ad0dbab 7226 ilk_init_lp_watermarks(dev);
50ed5fbd 7227
ab57fff1 7228 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7229 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7230
ab57fff1 7231 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7232 I915_WRITE(CHICKEN_PAR1_1,
7233 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7234
ab57fff1 7235 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7236 for_each_pipe(dev_priv, pipe) {
07d27e20 7237 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7238 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7239 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7240 }
63801f21 7241
ab57fff1
BW		 7242 /* WaVSRefCountFullforceMissDisable:bdw */
7243 /* WaDSRefCountFullforceMissDisable:bdw */
7244 I915_WRITE(GEN7_FF_THREAD_MODE,
7245 I915_READ(GEN7_FF_THREAD_MODE) &
7246 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7247
295e8bb7
VS		 7248 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7249 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7250
7251 /* WaDisableSDEUnitClockGating:bdw */
7252 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7253 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7254
450174fe
ID		 7255 /* WaProgramL3SqcReg1Default:bdw */
7256 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7257
6d50b065
VS		 7258 /*
7259 * WaGttCachingOffByDefault:bdw
7260 * GTT cache may not work with big pages, so if those
7261 * are ever enabled GTT cache may need to be disabled.
7262 */
7263 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7264
17e0adf0
MK		 7265 /* WaKVMNotificationOnConfigChange:bdw */
7266 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7267 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7268
89d6b2b8 7269 lpt_init_clock_gating(dev);
1020a5c2
BW		 7270}
7271
cad2a2d7
ED		 7272static void haswell_init_clock_gating(struct drm_device *dev)
7273{
fac5e23e 7274 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7275
017636cc 7276 ilk_init_lp_watermarks(dev);
cad2a2d7 7277
f3fc4884
FJ		 7278 /* L3 caching of data atomics doesn't work -- disable it. */
7279 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7280 I915_WRITE(HSW_ROW_CHICKEN3,
7281 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7282
ecdb4eb7 7283 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7284 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7285 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7286 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7287
e36ea7ff
VS		 7288 /* WaVSRefCountFullforceMissDisable:hsw */
7289 I915_WRITE(GEN7_FF_THREAD_MODE,
7290 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7291
4e04632e
AG		 7292 /* WaDisable_RenderCache_OperationalFlush:hsw */
7293 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7294
fe27c606
CW		 7295 /* enable HiZ Raw Stall Optimization */
7296 I915_WRITE(CACHE_MODE_0_GEN7,
7297 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7298
ecdb4eb7 7299 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7300 I915_WRITE(CACHE_MODE_1,
7301 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7302
a12c4967
VS		 7303 /*
7304 * BSpec recommends 8x4 when MSAA is used,
7305 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7306 *
7307 * Note that PS/WM thread counts depend on the WIZ hashing
7308 * disable bit, which we don't touch here, but it's good
7309 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7310 */
7311 I915_WRITE(GEN7_GT_MODE,
98533251 7312 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7313
94411593
KG		 7314 /* WaSampleCChickenBitEnable:hsw */
7315 I915_WRITE(HALF_SLICE_CHICKEN3,
7316 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7317
ecdb4eb7 7318 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7319 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7320
90a88643
PZ		 7321 /* WaRsPkgCStateDisplayPMReq:hsw */
7322 I915_WRITE(CHICKEN_PAR1_1,
7323 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7324
17a303ec 7325 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7326}
7327
1fa61106 7328static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7329{
fac5e23e 7330 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7331 uint32_t snpcr;
6f1d69b0 7332
017636cc 7333 ilk_init_lp_watermarks(dev);
6f1d69b0 7334
231e54f6 7335 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7336
ecdb4eb7 7337 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7338 I915_WRITE(_3D_CHICKEN3,
7339 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7340
ecdb4eb7 7341 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7342 I915_WRITE(IVB_CHICKEN3,
7343 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7344 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7345
ecdb4eb7 7346 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7347 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7348 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7349 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7350
4e04632e
AG		 7351 /* WaDisable_RenderCache_OperationalFlush:ivb */
7352 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7353
ecdb4eb7 7354 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7355 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7356 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7357
ecdb4eb7 7358 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7359 I915_WRITE(GEN7_L3CNTLREG1,
7360 GEN7_WA_FOR_GEN7_L3_CONTROL);
7361 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7362 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7363 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7364 I915_WRITE(GEN7_ROW_CHICKEN2,
7365 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7366 else {
7367 /* must write both registers */
7368 I915_WRITE(GEN7_ROW_CHICKEN2,
7369 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7370 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7371 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7372 }
6f1d69b0 7373
ecdb4eb7 7374 /* WaForceL3Serialization:ivb */
61939d97
JB		 7375 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7376 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7377
1b80a19a 7378 /*
0f846f81 7379 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7380 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7381 */
7382 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7383 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7384
ecdb4eb7 7385 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7386 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7387 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7388 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7389
0e088b8f 7390 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7391
7392 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7393
22721343
CW		 7394 if (0) { /* causes HiZ corruption on ivb:gt1 */
7395 /* enable HiZ Raw Stall Optimization */
7396 I915_WRITE(CACHE_MODE_0_GEN7,
7397 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7398 }
116f2b6d 7399
ecdb4eb7 7400 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7401 I915_WRITE(CACHE_MODE_1,
7402 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7403
a607c1a4
VS		 7404 /*
7405 * BSpec recommends 8x4 when MSAA is used,
7406 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7407 *
7408 * Note that PS/WM thread counts depend on the WIZ hashing
7409 * disable bit, which we don't touch here, but it's good
7410 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7411 */
7412 I915_WRITE(GEN7_GT_MODE,
98533251 7413 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7414
20848223
BW		 7415 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7416 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7417 snpcr |= GEN6_MBC_SNPCR_MED;
7418 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7419
6e266956 7420 if (!HAS_PCH_NOP(dev_priv))
ab5c608b 7421 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7422
7423 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7424}
7425
1fa61106 7426static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7427{
fac5e23e 7428 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7429
ecdb4eb7 7430 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7431 I915_WRITE(_3D_CHICKEN3,
7432 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7433
ecdb4eb7 7434 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7435 I915_WRITE(IVB_CHICKEN3,
7436 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7437 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7438
fad7d36e 7439 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7440 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7441 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7442 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7443 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7444
4e04632e
AG		 7445 /* WaDisable_RenderCache_OperationalFlush:vlv */
7446 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7447
ecdb4eb7 7448 /* WaForceL3Serialization:vlv */
61939d97
JB		 7449 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7450 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7451
ecdb4eb7 7452 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7453 I915_WRITE(GEN7_ROW_CHICKEN2,
7454 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7455
ecdb4eb7 7456 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7457 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7458 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7459 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7460
46680e0a
VS		 7461 gen7_setup_fixed_func_scheduler(dev_priv);
7462
3c0edaeb 7463 /*
0f846f81 7464 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7465 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7466 */
7467 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7468 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7469
c98f5062
AG		 7470 /* WaDisableL3Bank2xClockGate:vlv
7471 * Disabling L3 clock gating- MMIO 940c[25] = 1
7472 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7473 I915_WRITE(GEN7_UCGCTL4,
7474 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7475
afd58e79
VS		 7476 /*
7477 * BSpec says this must be set, even though
7478 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7479 */
6b26c86d
DV		 7480 I915_WRITE(CACHE_MODE_1,
7481 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7482
da2518f9
VS		 7483 /*
7484 * BSpec recommends 8x4 when MSAA is used,
7485 * however in practice 16x4 seems fastest.
7486 *
7487 * Note that PS/WM thread counts depend on the WIZ hashing
7488 * disable bit, which we don't touch here, but it's good
7489 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7490 */
7491 I915_WRITE(GEN7_GT_MODE,
7492 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7493
031994ee
VS		 7494 /*
7495 * WaIncreaseL3CreditsForVLVB0:vlv
7496 * This is the hardware default actually.
7497 */
7498 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7499
2d809570 7500 /*
ecdb4eb7 7501 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7502 * Disable clock gating on th GCFG unit to prevent a delay
7503 * in the reporting of vblank events.
7504 */
7a0d1eed 7505 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7506}
7507
a4565da8
VS		 7508static void cherryview_init_clock_gating(struct drm_device *dev)
7509{
fac5e23e 7510 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7511
232ce337
VS		 7512 /* WaVSRefCountFullforceMissDisable:chv */
7513 /* WaDSRefCountFullforceMissDisable:chv */
7514 I915_WRITE(GEN7_FF_THREAD_MODE,
7515 I915_READ(GEN7_FF_THREAD_MODE) &
7516 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7517
7518 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7519 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7520 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7521
7522 /* WaDisableCSUnitClockGating:chv */
7523 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7524 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7525
7526 /* WaDisableSDEUnitClockGating:chv */
7527 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7528 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7529
450174fe
ID		 7530 /*
7531 * WaProgramL3SqcReg1Default:chv
7532 * See gfxspecs/Related Documents/Performance Guide/
7533 * LSQC Setting Recommendations.
7534 */
7535 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7536
6d50b065
VS		 7537 /*
7538 * GTT cache may not work with big pages, so if those
7539 * are ever enabled GTT cache may need to be disabled.
7540 */
7541 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7542}
7543
1fa61106 7544static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7545{
fac5e23e 7546 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7547 uint32_t dspclk_gate;
7548
7549 I915_WRITE(RENCLK_GATE_D1, 0);
7550 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7551 GS_UNIT_CLOCK_GATE_DISABLE |
7552 CL_UNIT_CLOCK_GATE_DISABLE);
7553 I915_WRITE(RAMCLK_GATE_D, 0);
7554 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7555 OVRUNIT_CLOCK_GATE_DISABLE |
7556 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7557 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7558 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7559 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7560
7561 /* WaDisableRenderCachePipelinedFlush */
7562 I915_WRITE(CACHE_MODE_0,
7563 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7564
4e04632e
AG		 7565 /* WaDisable_RenderCache_OperationalFlush:g4x */
7566 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7567
0e088b8f 7568 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7569}
7570
1fa61106 7571static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7572{
fac5e23e 7573 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7574
7575 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7576 I915_WRITE(RENCLK_GATE_D2, 0);
7577 I915_WRITE(DSPCLK_GATE_D, 0);
7578 I915_WRITE(RAMCLK_GATE_D, 0);
7579 I915_WRITE16(DEUC, 0);
20f94967
VS		 7580 I915_WRITE(MI_ARB_STATE,
7581 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7582
7583 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7584 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7585}
7586
1fa61106 7587static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7588{
fac5e23e 7589 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7590
7591 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7592 I965_RCC_CLOCK_GATE_DISABLE |
7593 I965_RCPB_CLOCK_GATE_DISABLE |
7594 I965_ISC_CLOCK_GATE_DISABLE |
7595 I965_FBC_CLOCK_GATE_DISABLE);
7596 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7597 I915_WRITE(MI_ARB_STATE,
7598 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7599
7600 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7601 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7602}
7603
1fa61106 7604static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7605{
fac5e23e 7606 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7607 u32 dstate = I915_READ(D_STATE);
7608
7609 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7610 DSTATE_DOT_CLOCK_GATING;
7611 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7612
7613 if (IS_PINEVIEW(dev))
7614 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7615
7616 /* IIR "flip pending" means done if this bit is set */
7617 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7618
7619 /* interrupts should cause a wake up from C3 */
3299254f 7620 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7621
7622 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7623 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7624
7625 I915_WRITE(MI_ARB_STATE,
7626 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7627}
7628
1fa61106 7629static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7630{
fac5e23e 7631 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7632
7633 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7634
7635 /* interrupts should cause a wake up from C3 */
7636 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7637 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7638
7639 I915_WRITE(MEM_MODE,
7640 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7641}
7642
1fa61106 7643static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7644{
fac5e23e 7645 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7646
7647 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7648
7649 I915_WRITE(MEM_MODE,
7650 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7651 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7652}
7653
6f1d69b0
ED		 7654void intel_init_clock_gating(struct drm_device *dev)
7655{
fac5e23e 7656 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7657
bb400da9 7658 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7659}
7660
7d708ee4
ID		 7661void intel_suspend_hw(struct drm_device *dev)
7662{
6e266956 7663 if (HAS_PCH_LPT(to_i915(dev)))
7d708ee4
ID		 7664 lpt_suspend_hw(dev);
7665}
7666
bb400da9
ID		 7667static void nop_init_clock_gating(struct drm_device *dev)
7668{
7669 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7670}
7671
7672/**
7673 * intel_init_clock_gating_hooks - setup the clock gating hooks
7674 * @dev_priv: device private
7675 *
7676 * Setup the hooks that configure which clocks of a given platform can be
7677 * gated and also apply various GT and display specific workarounds for these
7678 * platforms. Note that some GT specific workarounds are applied separately
7679 * when GPU contexts or batchbuffers start their execution.
7680 */
7681void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7682{
7683 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7684 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7685 else if (IS_KABYLAKE(dev_priv))
9498dba7 7686 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7687 else if (IS_BROXTON(dev_priv))
7688 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7689 else if (IS_BROADWELL(dev_priv))
7690 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7691 else if (IS_CHERRYVIEW(dev_priv))
7692 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7693 else if (IS_HASWELL(dev_priv))
7694 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7695 else if (IS_IVYBRIDGE(dev_priv))
7696 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7697 else if (IS_VALLEYVIEW(dev_priv))
7698 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7699 else if (IS_GEN6(dev_priv))
7700 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7701 else if (IS_GEN5(dev_priv))
7702 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7703 else if (IS_G4X(dev_priv))
7704 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7705 else if (IS_CRESTLINE(dev_priv))
7706 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7707 else if (IS_BROADWATER(dev_priv))
7708 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7709 else if (IS_GEN3(dev_priv))
7710 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7711 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7712 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7713 else if (IS_GEN2(dev_priv))
7714 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7715 else {
7716 MISSING_CASE(INTEL_DEVID(dev_priv));
7717 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7718 }
7719}
7720
1fa61106
ED		 7721/* Set up chip specific power management-related functions */
7722void intel_init_pm(struct drm_device *dev)
7723{
fac5e23e 7724 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7725
7ff0ebcc 7726 intel_fbc_init(dev_priv);
1fa61106 7727
c921aba8
DV		 7728 /* For cxsr */
7729 if (IS_PINEVIEW(dev))
7730 i915_pineview_get_mem_freq(dev);
5db94019 7731 else if (IS_GEN5(dev_priv))
c921aba8
DV		 7732 i915_ironlake_get_mem_freq(dev);
7733
1fa61106 7734 /* For FIFO watermark updates */
f5ed50cb 7735 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7736 skl_setup_wm_latency(dev);
2d41c0b5 7737 dev_priv->display.update_wm = skl_update_wm;
98d39494 7738 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7739 } else if (HAS_PCH_SPLIT(dev_priv)) {
fa50ad61 7740 ilk_setup_wm_latency(dev);
53615a5e 7741
5db94019 7742 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7743 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7744 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7745 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7746 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7747 dev_priv->display.compute_intermediate_wm =
7748 ilk_compute_intermediate_wm;
7749 dev_priv->display.initial_watermarks =
7750 ilk_initial_watermarks;
7751 dev_priv->display.optimize_watermarks =
7752 ilk_optimize_watermarks;
bd602544
VS		 7753 } else {
7754 DRM_DEBUG_KMS("Failed to read display plane latency. "
7755 "Disable CxSR\n");
7756 }
920a14b2 7757 } else if (IS_CHERRYVIEW(dev_priv)) {
262cd2e1 7758 vlv_setup_wm_latency(dev);
262cd2e1 7759 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7760 } else if (IS_VALLEYVIEW(dev_priv)) {
26e1fe4f 7761 vlv_setup_wm_latency(dev);
26e1fe4f 7762 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7763 } else if (IS_PINEVIEW(dev)) {
50a0bc90 7764 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7765 dev_priv->is_ddr3,
7766 dev_priv->fsb_freq,
7767 dev_priv->mem_freq)) {
7768 DRM_INFO("failed to find known CxSR latency "
7769 "(found ddr%s fsb freq %d, mem freq %d), "
7770 "disabling CxSR\n",
7771 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7772 dev_priv->fsb_freq, dev_priv->mem_freq);
7773 /* Disable CxSR and never update its watermark again */
5209b1f4 7774 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7775 dev_priv->display.update_wm = NULL;
7776 } else
7777 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7778 } else if (IS_G4X(dev_priv)) {
1fa61106 7779 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7780 } else if (IS_GEN4(dev_priv)) {
1fa61106 7781 dev_priv->display.update_wm = i965_update_wm;
5db94019 7782 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7783 dev_priv->display.update_wm = i9xx_update_wm;
7784 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7785 } else if (IS_GEN2(dev_priv)) {
feb56b93
DV		 7786 if (INTEL_INFO(dev)->num_pipes == 1) {
7787 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7788 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7789 } else {
7790 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7791 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7792 }
feb56b93
DV		 7793 } else {
7794 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7795 }
7796}
7797
87660502
L		 7798static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7799{
7800 uint32_t flags =
7801 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7802
7803 switch (flags) {
7804 case GEN6_PCODE_SUCCESS:
7805 return 0;
7806 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7807 case GEN6_PCODE_ILLEGAL_CMD:
7808 return -ENXIO;
7809 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7810 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7811 return -EOVERFLOW;
7812 case GEN6_PCODE_TIMEOUT:
7813 return -ETIMEDOUT;
7814 default:
7815 MISSING_CASE(flags)
7816 return 0;
7817 }
7818}
7819
7820static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7821{
7822 uint32_t flags =
7823 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7824
7825 switch (flags) {
7826 case GEN6_PCODE_SUCCESS:
7827 return 0;
7828 case GEN6_PCODE_ILLEGAL_CMD:
7829 return -ENXIO;
7830 case GEN7_PCODE_TIMEOUT:
7831 return -ETIMEDOUT;
7832 case GEN7_PCODE_ILLEGAL_DATA:
7833 return -EINVAL;
7834 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7835 return -EOVERFLOW;
7836 default:
7837 MISSING_CASE(flags);
7838 return 0;
7839 }
7840}
7841
151a49d0 7842int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7843{
87660502
L		 7844 int status;
7845
4fc688ce 7846 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7847
3f5582dd
CW		 7848 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7849 * use te fw I915_READ variants to reduce the amount of work
7850 * required when reading/writing.
7851 */
7852
7853 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7854 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7855 return -EAGAIN;
7856 }
7857
3f5582dd
CW		 7858 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7859 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7860 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7861
3f5582dd
CW		 7862 if (intel_wait_for_register_fw(dev_priv,
7863 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7864 500)) {
42c0526c
BW		 7865 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7866 return -ETIMEDOUT;
7867 }
7868
3f5582dd
CW		 7869 *val = I915_READ_FW(GEN6_PCODE_DATA);
7870 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7871
87660502
L		 7872 if (INTEL_GEN(dev_priv) > 6)
7873 status = gen7_check_mailbox_status(dev_priv);
7874 else
7875 status = gen6_check_mailbox_status(dev_priv);
7876
7877 if (status) {
7878 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7879 status);
7880 return status;
7881 }
7882
42c0526c
BW		 7883 return 0;
7884}
7885
3f5582dd 7886int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7887 u32 mbox, u32 val)
42c0526c 7888{
87660502
L		 7889 int status;
7890
4fc688ce 7891 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7892
3f5582dd
CW		 7893 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7894 * use te fw I915_READ variants to reduce the amount of work
7895 * required when reading/writing.
7896 */
7897
7898 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7899 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7900 return -EAGAIN;
7901 }
7902
3f5582dd
CW		 7903 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7904 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7905
3f5582dd
CW		 7906 if (intel_wait_for_register_fw(dev_priv,
7907 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7908 500)) {
42c0526c
BW		 7909 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7910 return -ETIMEDOUT;
7911 }
7912
3f5582dd 7913 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7914
87660502
L		 7915 if (INTEL_GEN(dev_priv) > 6)
7916 status = gen7_check_mailbox_status(dev_priv);
7917 else
7918 status = gen6_check_mailbox_status(dev_priv);
7919
7920 if (status) {
7921 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7922 status);
7923 return status;
7924 }
7925
42c0526c
BW		 7926 return 0;
7927}
a0e4e199 7928
dd06f88c
VS		 7929static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7930{
c30fec65
VS		 7931 /*
7932 * N = val - 0xb7
7933 * Slow = Fast = GPLL ref * N
7934 */
7935 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7936}
7937
b55dd647 7938static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7939{
c30fec65 7940 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7941}
7942
b55dd647 7943static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7944{
c30fec65
VS		 7945 /*
7946 * N = val / 2
7947 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7948 */
7949 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7950}
7951
b55dd647 7952static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7953{
1c14762d 7954 /* CHV needs even values */
c30fec65 7955 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7956}
7957
616bc820 7958int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7959{
2d1fe073 7960 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7961 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7962 GEN9_FREQ_SCALER);
2d1fe073 7963 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7964 return chv_gpu_freq(dev_priv, val);
2d1fe073 7965 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7966 return byt_gpu_freq(dev_priv, val);
7967 else
7968 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7969}
7970
616bc820
VS		 7971int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7972{
2d1fe073 7973 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7974 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7975 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7976 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7977 return chv_freq_opcode(dev_priv, val);
2d1fe073 7978 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7979 return byt_freq_opcode(dev_priv, val);
7980 else
500a3d2e 7981 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7982}
22b1b2f8 7983
6ad790c0
CW		 7984struct request_boost {
7985 struct work_struct work;
eed29a5b 7986 struct drm_i915_gem_request *req;
6ad790c0
CW		 7987};
7988
7989static void __intel_rps_boost_work(struct work_struct *work)
7990{
7991 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7992 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7993
f69a02c9 7994 if (!i915_gem_request_completed(req))
c033666a 7995 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7996
e8a261ea 7997 i915_gem_request_put(req);
6ad790c0
CW		 7998 kfree(boost);
7999}
8000
91d14251 8001void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8002{
8003 struct request_boost *boost;
8004
91d14251 8005 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8006 return;
8007
f69a02c9 8008 if (i915_gem_request_completed(req))
e61b9958
CW		 8009 return;
8010
6ad790c0
CW		 8011 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8012 if (boost == NULL)
8013 return;
8014
e8a261ea 8015 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8016
8017 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8018 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8019}
8020
f742a552 8021void intel_pm_setup(struct drm_device *dev)
907b28c5 8022{
fac5e23e 8023 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8024
f742a552 8025 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8026 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8027
54b4f68f
CW		 8028 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8029 __intel_autoenable_gt_powersave);
1854d5ca 8030 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8031
33688d95 8032 dev_priv->pm.suspended = false;
1f814dac 8033 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 8034 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 8035}
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