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drm/i915: Refactor ilk_update_wm (v3)
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
a82abe43
ID		 55static void bxt_init_clock_gating(struct drm_device *dev)
56{
32608ca2
ID		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
a7546159
NH		 59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
32608ca2
ID		 63 /*
64 * FIXME:
868434c5 65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 66 */
32608ca2 67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
a82abe43
ID		 69}
70
c921aba8
DV		 71static void i915_pineview_get_mem_freq(struct drm_device *dev)
72{
50227e1c 73 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 74 u32 tmp;
75
76 tmp = I915_READ(CLKCFG);
77
78 switch (tmp & CLKCFG_FSB_MASK) {
79 case CLKCFG_FSB_533:
80 dev_priv->fsb_freq = 533; /* 133*4 */
81 break;
82 case CLKCFG_FSB_800:
83 dev_priv->fsb_freq = 800; /* 200*4 */
84 break;
85 case CLKCFG_FSB_667:
86 dev_priv->fsb_freq = 667; /* 167*4 */
87 break;
88 case CLKCFG_FSB_400:
89 dev_priv->fsb_freq = 400; /* 100*4 */
90 break;
91 }
92
93 switch (tmp & CLKCFG_MEM_MASK) {
94 case CLKCFG_MEM_533:
95 dev_priv->mem_freq = 533;
96 break;
97 case CLKCFG_MEM_667:
98 dev_priv->mem_freq = 667;
99 break;
100 case CLKCFG_MEM_800:
101 dev_priv->mem_freq = 800;
102 break;
103 }
104
105 /* detect pineview DDR3 setting */
106 tmp = I915_READ(CSHRDDR3CTL);
107 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
108}
109
110static void i915_ironlake_get_mem_freq(struct drm_device *dev)
111{
50227e1c 112 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 113 u16 ddrpll, csipll;
114
115 ddrpll = I915_READ16(DDRMPLL1);
116 csipll = I915_READ16(CSIPLL0);
117
118 switch (ddrpll & 0xff) {
119 case 0xc:
120 dev_priv->mem_freq = 800;
121 break;
122 case 0x10:
123 dev_priv->mem_freq = 1066;
124 break;
125 case 0x14:
126 dev_priv->mem_freq = 1333;
127 break;
128 case 0x18:
129 dev_priv->mem_freq = 1600;
130 break;
131 default:
132 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
133 ddrpll & 0xff);
134 dev_priv->mem_freq = 0;
135 break;
136 }
137
20e4d407 138 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 139
140 switch (csipll & 0x3ff) {
141 case 0x00c:
142 dev_priv->fsb_freq = 3200;
143 break;
144 case 0x00e:
145 dev_priv->fsb_freq = 3733;
146 break;
147 case 0x010:
148 dev_priv->fsb_freq = 4266;
149 break;
150 case 0x012:
151 dev_priv->fsb_freq = 4800;
152 break;
153 case 0x014:
154 dev_priv->fsb_freq = 5333;
155 break;
156 case 0x016:
157 dev_priv->fsb_freq = 5866;
158 break;
159 case 0x018:
160 dev_priv->fsb_freq = 6400;
161 break;
162 default:
163 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
164 csipll & 0x3ff);
165 dev_priv->fsb_freq = 0;
166 break;
167 }
168
169 if (dev_priv->fsb_freq == 3200) {
20e4d407 170 dev_priv->ips.c_m = 0;
c921aba8 171 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 172 dev_priv->ips.c_m = 1;
c921aba8 173 } else {
20e4d407 174 dev_priv->ips.c_m = 2;
c921aba8
DV		 175 }
176}
177
b445e3b0
ED		 178static const struct cxsr_latency cxsr_latency_table[] = {
179 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
180 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
181 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
182 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
183 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
184
185 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
186 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
187 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
188 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
189 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
190
191 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
192 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
193 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
194 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
195 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
196
197 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
198 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
199 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
200 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
201 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
202
203 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
204 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
205 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
206 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
207 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
208
209 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
210 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
211 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
212 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
213 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
214};
215
63c62275 216static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 217 int is_ddr3,
218 int fsb,
219 int mem)
220{
221 const struct cxsr_latency *latency;
222 int i;
223
224 if (fsb == 0 || mem == 0)
225 return NULL;
226
227 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
228 latency = &cxsr_latency_table[i];
229 if (is_desktop == latency->is_desktop &&
230 is_ddr3 == latency->is_ddr3 &&
231 fsb == latency->fsb_freq && mem == latency->mem_freq)
232 return latency;
233 }
234
235 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
236
237 return NULL;
238}
239
fc1ac8de
VS		 240static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
241{
242 u32 val;
243
244 mutex_lock(&dev_priv->rps.hw_lock);
245
246 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
247 if (enable)
248 val &= ~FORCE_DDR_HIGH_FREQ;
249 else
250 val |= FORCE_DDR_HIGH_FREQ;
251 val &= ~FORCE_DDR_LOW_FREQ;
252 val |= FORCE_DDR_FREQ_REQ_ACK;
253 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
254
255 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
256 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
257 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
258
259 mutex_unlock(&dev_priv->rps.hw_lock);
260}
261
cfb41411
VS		 262static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
263{
264 u32 val;
265
266 mutex_lock(&dev_priv->rps.hw_lock);
267
268 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
269 if (enable)
270 val |= DSP_MAXFIFO_PM5_ENABLE;
271 else
272 val &= ~DSP_MAXFIFO_PM5_ENABLE;
273 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
274
275 mutex_unlock(&dev_priv->rps.hw_lock);
276}
277
f4998963
VS		 278#define FW_WM(value, plane) \
279 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
280
5209b1f4 281void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 282{
5209b1f4
ID		 283 struct drm_device *dev = dev_priv->dev;
284 u32 val;
b445e3b0 285
5209b1f4
ID		 286 if (IS_VALLEYVIEW(dev)) {
287 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 288 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 289 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 290 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
291 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 292 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 293 } else if (IS_PINEVIEW(dev)) {
294 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
295 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
296 I915_WRITE(DSPFW3, val);
a7a6c498 297 POSTING_READ(DSPFW3);
5209b1f4
ID		 298 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
299 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
300 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
301 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_I915GM(dev)) {
304 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
305 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
306 I915_WRITE(INSTPM, val);
a7a6c498 307 POSTING_READ(INSTPM);
5209b1f4
ID		 308 } else {
309 return;
310 }
b445e3b0 311
5209b1f4
ID		 312 DRM_DEBUG_KMS("memory self-refresh is %s\n",
313 enable ? "enabled" : "disabled");
b445e3b0
ED		 314}
315
fc1ac8de 316
b445e3b0
ED		 317/*
318 * Latency for FIFO fetches is dependent on several factors:
319 * - memory configuration (speed, channels)
320 * - chipset
321 * - current MCH state
322 * It can be fairly high in some situations, so here we assume a fairly
323 * pessimal value. It's a tradeoff between extra memory fetches (if we
324 * set this value too high, the FIFO will fetch frequently to stay full)
325 * and power consumption (set it too low to save power and we might see
326 * FIFO underruns and display "flicker").
327 *
328 * A value of 5us seems to be a good balance; safe for very low end
329 * platforms but not overly aggressive on lower latency configs.
330 */
5aef6003 331static const int pessimal_latency_ns = 5000;
b445e3b0 332
b5004720
VS		 333#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
334 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
335
336static int vlv_get_fifo_size(struct drm_device *dev,
337 enum pipe pipe, int plane)
338{
339 struct drm_i915_private *dev_priv = dev->dev_private;
340 int sprite0_start, sprite1_start, size;
341
342 switch (pipe) {
343 uint32_t dsparb, dsparb2, dsparb3;
344 case PIPE_A:
345 dsparb = I915_READ(DSPARB);
346 dsparb2 = I915_READ(DSPARB2);
347 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
348 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
349 break;
350 case PIPE_B:
351 dsparb = I915_READ(DSPARB);
352 dsparb2 = I915_READ(DSPARB2);
353 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
354 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
355 break;
356 case PIPE_C:
357 dsparb2 = I915_READ(DSPARB2);
358 dsparb3 = I915_READ(DSPARB3);
359 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
360 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
361 break;
362 default:
363 return 0;
364 }
365
366 switch (plane) {
367 case 0:
368 size = sprite0_start;
369 break;
370 case 1:
371 size = sprite1_start - sprite0_start;
372 break;
373 case 2:
374 size = 512 - 1 - sprite1_start;
375 break;
376 default:
377 return 0;
378 }
379
380 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
381 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
382 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
383 size);
384
385 return size;
386}
387
1fa61106 388static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 389{
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 uint32_t dsparb = I915_READ(DSPARB);
392 int size;
393
394 size = dsparb & 0x7f;
395 if (plane)
396 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
397
398 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
399 plane ? "B" : "A", size);
400
401 return size;
402}
403
feb56b93 404static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 405{
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 uint32_t dsparb = I915_READ(DSPARB);
408 int size;
409
410 size = dsparb & 0x1ff;
411 if (plane)
412 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
413 size >>= 1; /* Convert to cachelines */
414
415 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
416 plane ? "B" : "A", size);
417
418 return size;
419}
420
1fa61106 421static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 422{
423 struct drm_i915_private *dev_priv = dev->dev_private;
424 uint32_t dsparb = I915_READ(DSPARB);
425 int size;
426
427 size = dsparb & 0x7f;
428 size >>= 2; /* Convert to cachelines */
429
430 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
431 plane ? "B" : "A",
432 size);
433
434 return size;
435}
436
b445e3b0
ED		 437/* Pineview has different values for various configs */
438static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 439 .fifo_size = PINEVIEW_DISPLAY_FIFO,
440 .max_wm = PINEVIEW_MAX_WM,
441 .default_wm = PINEVIEW_DFT_WM,
442 .guard_size = PINEVIEW_GUARD_WM,
443 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 444};
445static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 446 .fifo_size = PINEVIEW_DISPLAY_FIFO,
447 .max_wm = PINEVIEW_MAX_WM,
448 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
449 .guard_size = PINEVIEW_GUARD_WM,
450 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 451};
452static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 453 .fifo_size = PINEVIEW_CURSOR_FIFO,
454 .max_wm = PINEVIEW_CURSOR_MAX_WM,
455 .default_wm = PINEVIEW_CURSOR_DFT_WM,
456 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
457 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 458};
459static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 460 .fifo_size = PINEVIEW_CURSOR_FIFO,
461 .max_wm = PINEVIEW_CURSOR_MAX_WM,
462 .default_wm = PINEVIEW_CURSOR_DFT_WM,
463 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
464 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 465};
466static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 467 .fifo_size = G4X_FIFO_SIZE,
468 .max_wm = G4X_MAX_WM,
469 .default_wm = G4X_MAX_WM,
470 .guard_size = 2,
471 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 472};
473static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 474 .fifo_size = I965_CURSOR_FIFO,
475 .max_wm = I965_CURSOR_MAX_WM,
476 .default_wm = I965_CURSOR_DFT_WM,
477 .guard_size = 2,
478 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 479};
480static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 481 .fifo_size = VALLEYVIEW_FIFO_SIZE,
482 .max_wm = VALLEYVIEW_MAX_WM,
483 .default_wm = VALLEYVIEW_MAX_WM,
484 .guard_size = 2,
485 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 486};
487static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 488 .fifo_size = I965_CURSOR_FIFO,
489 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
490 .default_wm = I965_CURSOR_DFT_WM,
491 .guard_size = 2,
492 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 493};
494static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 495 .fifo_size = I965_CURSOR_FIFO,
496 .max_wm = I965_CURSOR_MAX_WM,
497 .default_wm = I965_CURSOR_DFT_WM,
498 .guard_size = 2,
499 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 500};
501static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 502 .fifo_size = I945_FIFO_SIZE,
503 .max_wm = I915_MAX_WM,
504 .default_wm = 1,
505 .guard_size = 2,
506 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 507};
508static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 509 .fifo_size = I915_FIFO_SIZE,
510 .max_wm = I915_MAX_WM,
511 .default_wm = 1,
512 .guard_size = 2,
513 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 514};
9d539105 515static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 516 .fifo_size = I855GM_FIFO_SIZE,
517 .max_wm = I915_MAX_WM,
518 .default_wm = 1,
519 .guard_size = 2,
520 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 521};
9d539105
VS		 522static const struct intel_watermark_params i830_bc_wm_info = {
523 .fifo_size = I855GM_FIFO_SIZE,
524 .max_wm = I915_MAX_WM/2,
525 .default_wm = 1,
526 .guard_size = 2,
527 .cacheline_size = I830_FIFO_LINE_SIZE,
528};
feb56b93 529static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 530 .fifo_size = I830_FIFO_SIZE,
531 .max_wm = I915_MAX_WM,
532 .default_wm = 1,
533 .guard_size = 2,
534 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 535};
536
b445e3b0
ED		 537/**
538 * intel_calculate_wm - calculate watermark level
539 * @clock_in_khz: pixel clock
540 * @wm: chip FIFO params
541 * @pixel_size: display pixel size
542 * @latency_ns: memory latency for the platform
543 *
544 * Calculate the watermark level (the level at which the display plane will
545 * start fetching from memory again). Each chip has a different display
546 * FIFO size and allocation, so the caller needs to figure that out and pass
547 * in the correct intel_watermark_params structure.
548 *
549 * As the pixel clock runs, the FIFO will be drained at a rate that depends
550 * on the pixel size. When it reaches the watermark level, it'll start
551 * fetching FIFO line sized based chunks from memory until the FIFO fills
552 * past the watermark point. If the FIFO drains completely, a FIFO underrun
553 * will occur, and a display engine hang could result.
554 */
555static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
556 const struct intel_watermark_params *wm,
557 int fifo_size,
558 int pixel_size,
559 unsigned long latency_ns)
560{
561 long entries_required, wm_size;
562
563 /*
564 * Note: we need to make sure we don't overflow for various clock &
565 * latency values.
566 * clocks go from a few thousand to several hundred thousand.
567 * latency is usually a few thousand
568 */
569 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
570 1000;
571 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
572
573 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
574
575 wm_size = fifo_size - (entries_required + wm->guard_size);
576
577 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
578
579 /* Don't promote wm_size to unsigned... */
580 if (wm_size > (long)wm->max_wm)
581 wm_size = wm->max_wm;
582 if (wm_size <= 0)
583 wm_size = wm->default_wm;
d6feb196
VS		 584
585 /*
586 * Bspec seems to indicate that the value shouldn't be lower than
587 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
588 * Lets go for 8 which is the burst size since certain platforms
589 * already use a hardcoded 8 (which is what the spec says should be
590 * done).
591 */
592 if (wm_size <= 8)
593 wm_size = 8;
594
b445e3b0
ED		 595 return wm_size;
596}
597
598static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
599{
600 struct drm_crtc *crtc, *enabled = NULL;
601
70e1e0ec 602 for_each_crtc(dev, crtc) {
3490ea5d 603 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 604 if (enabled)
605 return NULL;
606 enabled = crtc;
607 }
608 }
609
610 return enabled;
611}
612
46ba614c 613static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 614{
46ba614c 615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 616 struct drm_i915_private *dev_priv = dev->dev_private;
617 struct drm_crtc *crtc;
618 const struct cxsr_latency *latency;
619 u32 reg;
620 unsigned long wm;
621
622 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
623 dev_priv->fsb_freq, dev_priv->mem_freq);
624 if (!latency) {
625 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 626 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 627 return;
628 }
629
630 crtc = single_enabled_crtc(dev);
631 if (crtc) {
7c5f93b0 632 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 633 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 634 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 635
636 /* Display SR */
637 wm = intel_calculate_wm(clock, &pineview_display_wm,
638 pineview_display_wm.fifo_size,
639 pixel_size, latency->display_sr);
640 reg = I915_READ(DSPFW1);
641 reg &= ~DSPFW_SR_MASK;
f4998963 642 reg |= FW_WM(wm, SR);
b445e3b0
ED		 643 I915_WRITE(DSPFW1, reg);
644 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
645
646 /* cursor SR */
647 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
648 pineview_display_wm.fifo_size,
649 pixel_size, latency->cursor_sr);
650 reg = I915_READ(DSPFW3);
651 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 652 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 653 I915_WRITE(DSPFW3, reg);
654
655 /* Display HPLL off SR */
656 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
657 pineview_display_hplloff_wm.fifo_size,
658 pixel_size, latency->display_hpll_disable);
659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 661 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 662 I915_WRITE(DSPFW3, reg);
663
664 /* cursor HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
667 pixel_size, latency->cursor_hpll_disable);
668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 670 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 671 I915_WRITE(DSPFW3, reg);
672 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
673
5209b1f4 674 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 675 } else {
5209b1f4 676 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 677 }
678}
679
680static bool g4x_compute_wm0(struct drm_device *dev,
681 int plane,
682 const struct intel_watermark_params *display,
683 int display_latency_ns,
684 const struct intel_watermark_params *cursor,
685 int cursor_latency_ns,
686 int *plane_wm,
687 int *cursor_wm)
688{
689 struct drm_crtc *crtc;
4fe8590a 690 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 691 int htotal, hdisplay, clock, pixel_size;
692 int line_time_us, line_count;
693 int entries, tlb_miss;
694
695 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 696 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 697 *cursor_wm = cursor->guard_size;
698 *plane_wm = display->guard_size;
699 return false;
700 }
701
6e3c9717 702 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 703 clock = adjusted_mode->crtc_clock;
fec8cba3 704 htotal = adjusted_mode->crtc_htotal;
6e3c9717 705 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 706 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 707
708 /* Use the small buffer method to calculate plane watermark */
709 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
710 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
711 if (tlb_miss > 0)
712 entries += tlb_miss;
713 entries = DIV_ROUND_UP(entries, display->cacheline_size);
714 *plane_wm = entries + display->guard_size;
715 if (*plane_wm > (int)display->max_wm)
716 *plane_wm = display->max_wm;
717
718 /* Use the large buffer method to calculate cursor watermark */
922044c9 719 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 720 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 721 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 722 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
723 if (tlb_miss > 0)
724 entries += tlb_miss;
725 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
726 *cursor_wm = entries + cursor->guard_size;
727 if (*cursor_wm > (int)cursor->max_wm)
728 *cursor_wm = (int)cursor->max_wm;
729
730 return true;
731}
732
733/*
734 * Check the wm result.
735 *
736 * If any calculated watermark values is larger than the maximum value that
737 * can be programmed into the associated watermark register, that watermark
738 * must be disabled.
739 */
740static bool g4x_check_srwm(struct drm_device *dev,
741 int display_wm, int cursor_wm,
742 const struct intel_watermark_params *display,
743 const struct intel_watermark_params *cursor)
744{
745 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
746 display_wm, cursor_wm);
747
748 if (display_wm > display->max_wm) {
749 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
750 display_wm, display->max_wm);
751 return false;
752 }
753
754 if (cursor_wm > cursor->max_wm) {
755 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
756 cursor_wm, cursor->max_wm);
757 return false;
758 }
759
760 if (!(display_wm || cursor_wm)) {
761 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
762 return false;
763 }
764
765 return true;
766}
767
768static bool g4x_compute_srwm(struct drm_device *dev,
769 int plane,
770 int latency_ns,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor,
773 int *display_wm, int *cursor_wm)
774{
775 struct drm_crtc *crtc;
4fe8590a 776 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 777 int hdisplay, htotal, pixel_size, clock;
778 unsigned long line_time_us;
779 int line_count, line_size;
780 int small, large;
781 int entries;
782
783 if (!latency_ns) {
784 *display_wm = *cursor_wm = 0;
785 return false;
786 }
787
788 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 789 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 790 clock = adjusted_mode->crtc_clock;
fec8cba3 791 htotal = adjusted_mode->crtc_htotal;
6e3c9717 792 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 793 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 794
922044c9 795 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 796 line_count = (latency_ns / line_time_us + 1000) / 1000;
797 line_size = hdisplay * pixel_size;
798
799 /* Use the minimum of the small and large buffer method for primary */
800 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
801 large = line_count * line_size;
802
803 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
804 *display_wm = entries + display->guard_size;
805
806 /* calculate the self-refresh watermark for display cursor */
3dd512fb 807 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 808 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
809 *cursor_wm = entries + cursor->guard_size;
810
811 return g4x_check_srwm(dev,
812 *display_wm, *cursor_wm,
813 display, cursor);
814}
815
15665979
VS		 816#define FW_WM_VLV(value, plane) \
817 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
818
0018fda1
VS		 819static void vlv_write_wm_values(struct intel_crtc *crtc,
820 const struct vlv_wm_values *wm)
821{
822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
823 enum pipe pipe = crtc->pipe;
824
825 I915_WRITE(VLV_DDL(pipe),
826 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
827 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
828 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
829 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
830
ae80152d 831 I915_WRITE(DSPFW1,
15665979
VS		 832 FW_WM(wm->sr.plane, SR) |
833 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
834 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 836 I915_WRITE(DSPFW2,
15665979
VS		 837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 840 I915_WRITE(DSPFW3,
15665979 841 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 842
843 if (IS_CHERRYVIEW(dev_priv)) {
844 I915_WRITE(DSPFW7_CHV,
15665979
VS		 845 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
846 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 847 I915_WRITE(DSPFW8_CHV,
15665979
VS		 848 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
849 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 850 I915_WRITE(DSPFW9_CHV,
15665979
VS		 851 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
852 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 853 I915_WRITE(DSPHOWM,
15665979
VS		 854 FW_WM(wm->sr.plane >> 9, SR_HI) |
855 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
856 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
857 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
858 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
859 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
860 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 864 } else {
865 I915_WRITE(DSPFW7,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
867 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 868 I915_WRITE(DSPHOWM,
15665979
VS		 869 FW_WM(wm->sr.plane >> 9, SR_HI) |
870 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
871 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
872 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 876 }
877
2cb389b7
VS		 878 /* zero (unused) WM1 watermarks */
879 I915_WRITE(DSPFW4, 0);
880 I915_WRITE(DSPFW5, 0);
881 I915_WRITE(DSPFW6, 0);
882 I915_WRITE(DSPHOWM1, 0);
883
ae80152d 884 POSTING_READ(DSPFW1);
0018fda1
VS		 885}
886
15665979
VS		 887#undef FW_WM_VLV
888
6eb1a681
VS		 889enum vlv_wm_level {
890 VLV_WM_LEVEL_PM2,
891 VLV_WM_LEVEL_PM5,
892 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 893};
894
262cd2e1
VS		 895/* latency must be in 0.1us units. */
896static unsigned int vlv_wm_method2(unsigned int pixel_rate,
897 unsigned int pipe_htotal,
898 unsigned int horiz_pixels,
899 unsigned int bytes_per_pixel,
900 unsigned int latency)
901{
902 unsigned int ret;
903
904 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
905 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
906 ret = DIV_ROUND_UP(ret, 64);
907
908 return ret;
909}
910
911static void vlv_setup_wm_latency(struct drm_device *dev)
912{
913 struct drm_i915_private *dev_priv = dev->dev_private;
914
915 /* all latencies in usec */
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
917
58590c14
VS		 918 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
919
262cd2e1
VS		 920 if (IS_CHERRYVIEW(dev_priv)) {
921 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
922 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 923
924 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 925 }
926}
927
928static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
929 struct intel_crtc *crtc,
930 const struct intel_plane_state *state,
931 int level)
932{
933 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
934 int clock, htotal, pixel_size, width, wm;
935
936 if (dev_priv->wm.pri_latency[level] == 0)
937 return USHRT_MAX;
938
939 if (!state->visible)
940 return 0;
941
942 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
943 clock = crtc->config->base.adjusted_mode.crtc_clock;
944 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
945 width = crtc->config->pipe_src_w;
946 if (WARN_ON(htotal == 0))
947 htotal = 1;
948
949 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
950 /*
951 * FIXME the formula gives values that are
952 * too big for the cursor FIFO, and hence we
953 * would never be able to use cursors. For
954 * now just hardcode the watermark.
955 */
956 wm = 63;
957 } else {
958 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
959 dev_priv->wm.pri_latency[level] * 10);
960 }
961
962 return min_t(int, wm, USHRT_MAX);
963}
964
54f1b6e1
VS		 965static void vlv_compute_fifo(struct intel_crtc *crtc)
966{
967 struct drm_device *dev = crtc->base.dev;
968 struct vlv_wm_state *wm_state = &crtc->wm_state;
969 struct intel_plane *plane;
970 unsigned int total_rate = 0;
971 const int fifo_size = 512 - 1;
972 int fifo_extra, fifo_left = fifo_size;
973
974 for_each_intel_plane_on_crtc(dev, crtc, plane) {
975 struct intel_plane_state *state =
976 to_intel_plane_state(plane->base.state);
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
979 continue;
980
981 if (state->visible) {
982 wm_state->num_active_planes++;
983 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
984 }
985 }
986
987 for_each_intel_plane_on_crtc(dev, crtc, plane) {
988 struct intel_plane_state *state =
989 to_intel_plane_state(plane->base.state);
990 unsigned int rate;
991
992 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
993 plane->wm.fifo_size = 63;
994 continue;
995 }
996
997 if (!state->visible) {
998 plane->wm.fifo_size = 0;
999 continue;
1000 }
1001
1002 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004 fifo_left -= plane->wm.fifo_size;
1005 }
1006
1007 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009 /* spread the remainder evenly */
1010 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011 int plane_extra;
1012
1013 if (fifo_left == 0)
1014 break;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017 continue;
1018
1019 /* give it all to the first plane if none are active */
1020 if (plane->wm.fifo_size == 0 &&
1021 wm_state->num_active_planes)
1022 continue;
1023
1024 plane_extra = min(fifo_extra, fifo_left);
1025 plane->wm.fifo_size += plane_extra;
1026 fifo_left -= plane_extra;
1027 }
1028
1029 WARN_ON(fifo_left != 0);
1030}
1031
262cd2e1
VS		 1032static void vlv_invert_wms(struct intel_crtc *crtc)
1033{
1034 struct vlv_wm_state *wm_state = &crtc->wm_state;
1035 int level;
1036
1037 for (level = 0; level < wm_state->num_levels; level++) {
1038 struct drm_device *dev = crtc->base.dev;
1039 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040 struct intel_plane *plane;
1041
1042 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046 switch (plane->base.type) {
1047 int sprite;
1048 case DRM_PLANE_TYPE_CURSOR:
1049 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050 wm_state->wm[level].cursor;
1051 break;
1052 case DRM_PLANE_TYPE_PRIMARY:
1053 wm_state->wm[level].primary = plane->wm.fifo_size -
1054 wm_state->wm[level].primary;
1055 break;
1056 case DRM_PLANE_TYPE_OVERLAY:
1057 sprite = plane->plane;
1058 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059 wm_state->wm[level].sprite[sprite];
1060 break;
1061 }
1062 }
1063 }
1064}
1065
26e1fe4f 1066static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1067{
1068 struct drm_device *dev = crtc->base.dev;
1069 struct vlv_wm_state *wm_state = &crtc->wm_state;
1070 struct intel_plane *plane;
1071 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072 int level;
1073
1074 memset(wm_state, 0, sizeof(*wm_state));
1075
852eb00d 1076 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1077 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1078
1079 wm_state->num_active_planes = 0;
262cd2e1 1080
54f1b6e1 1081 vlv_compute_fifo(crtc);
262cd2e1
VS		 1082
1083 if (wm_state->num_active_planes != 1)
1084 wm_state->cxsr = false;
1085
1086 if (wm_state->cxsr) {
1087 for (level = 0; level < wm_state->num_levels; level++) {
1088 wm_state->sr[level].plane = sr_fifo_size;
1089 wm_state->sr[level].cursor = 63;
1090 }
1091 }
1092
1093 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094 struct intel_plane_state *state =
1095 to_intel_plane_state(plane->base.state);
1096
1097 if (!state->visible)
1098 continue;
1099
1100 /* normal watermarks */
1101 for (level = 0; level < wm_state->num_levels; level++) {
1102 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105 /* hack */
1106 if (WARN_ON(level == 0 && wm > max_wm))
1107 wm = max_wm;
1108
1109 if (wm > plane->wm.fifo_size)
1110 break;
1111
1112 switch (plane->base.type) {
1113 int sprite;
1114 case DRM_PLANE_TYPE_CURSOR:
1115 wm_state->wm[level].cursor = wm;
1116 break;
1117 case DRM_PLANE_TYPE_PRIMARY:
1118 wm_state->wm[level].primary = wm;
1119 break;
1120 case DRM_PLANE_TYPE_OVERLAY:
1121 sprite = plane->plane;
1122 wm_state->wm[level].sprite[sprite] = wm;
1123 break;
1124 }
1125 }
1126
1127 wm_state->num_levels = level;
1128
1129 if (!wm_state->cxsr)
1130 continue;
1131
1132 /* maxfifo watermarks */
1133 switch (plane->base.type) {
1134 int sprite, level;
1135 case DRM_PLANE_TYPE_CURSOR:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].cursor =
1138 wm_state->sr[level].cursor;
1139 break;
1140 case DRM_PLANE_TYPE_PRIMARY:
1141 for (level = 0; level < wm_state->num_levels; level++)
1142 wm_state->sr[level].plane =
1143 min(wm_state->sr[level].plane,
1144 wm_state->wm[level].primary);
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 for (level = 0; level < wm_state->num_levels; level++)
1149 wm_state->sr[level].plane =
1150 min(wm_state->sr[level].plane,
1151 wm_state->wm[level].sprite[sprite]);
1152 break;
1153 }
1154 }
1155
1156 /* clear any (partially) filled invalid levels */
58590c14 1157 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1158 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160 }
1161
1162 vlv_invert_wms(crtc);
1163}
1164
54f1b6e1
VS		 1165#define VLV_FIFO(plane, value) \
1166 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169{
1170 struct drm_device *dev = crtc->base.dev;
1171 struct drm_i915_private *dev_priv = to_i915(dev);
1172 struct intel_plane *plane;
1173 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177 WARN_ON(plane->wm.fifo_size != 63);
1178 continue;
1179 }
1180
1181 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182 sprite0_start = plane->wm.fifo_size;
1183 else if (plane->plane == 0)
1184 sprite1_start = sprite0_start + plane->wm.fifo_size;
1185 else
1186 fifo_size = sprite1_start + plane->wm.fifo_size;
1187 }
1188
1189 WARN_ON(fifo_size != 512 - 1);
1190
1191 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192 pipe_name(crtc->pipe), sprite0_start,
1193 sprite1_start, fifo_size);
1194
1195 switch (crtc->pipe) {
1196 uint32_t dsparb, dsparb2, dsparb3;
1197 case PIPE_A:
1198 dsparb = I915_READ(DSPARB);
1199 dsparb2 = I915_READ(DSPARB2);
1200
1201 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202 VLV_FIFO(SPRITEB, 0xff));
1203 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204 VLV_FIFO(SPRITEB, sprite1_start));
1205
1206 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207 VLV_FIFO(SPRITEB_HI, 0x1));
1208 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211 I915_WRITE(DSPARB, dsparb);
1212 I915_WRITE(DSPARB2, dsparb2);
1213 break;
1214 case PIPE_B:
1215 dsparb = I915_READ(DSPARB);
1216 dsparb2 = I915_READ(DSPARB2);
1217
1218 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219 VLV_FIFO(SPRITED, 0xff));
1220 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221 VLV_FIFO(SPRITED, sprite1_start));
1222
1223 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224 VLV_FIFO(SPRITED_HI, 0xff));
1225 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228 I915_WRITE(DSPARB, dsparb);
1229 I915_WRITE(DSPARB2, dsparb2);
1230 break;
1231 case PIPE_C:
1232 dsparb3 = I915_READ(DSPARB3);
1233 dsparb2 = I915_READ(DSPARB2);
1234
1235 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236 VLV_FIFO(SPRITEF, 0xff));
1237 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238 VLV_FIFO(SPRITEF, sprite1_start));
1239
1240 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241 VLV_FIFO(SPRITEF_HI, 0xff));
1242 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245 I915_WRITE(DSPARB3, dsparb3);
1246 I915_WRITE(DSPARB2, dsparb2);
1247 break;
1248 default:
1249 break;
1250 }
1251}
1252
1253#undef VLV_FIFO
1254
262cd2e1
VS		 1255static void vlv_merge_wm(struct drm_device *dev,
1256 struct vlv_wm_values *wm)
1257{
1258 struct intel_crtc *crtc;
1259 int num_active_crtcs = 0;
1260
58590c14 1261 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1262 wm->cxsr = true;
1263
1264 for_each_intel_crtc(dev, crtc) {
1265 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267 if (!crtc->active)
1268 continue;
1269
1270 if (!wm_state->cxsr)
1271 wm->cxsr = false;
1272
1273 num_active_crtcs++;
1274 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275 }
1276
1277 if (num_active_crtcs != 1)
1278 wm->cxsr = false;
1279
6f9c784b
VS		 1280 if (num_active_crtcs > 1)
1281 wm->level = VLV_WM_LEVEL_PM2;
1282
262cd2e1
VS		 1283 for_each_intel_crtc(dev, crtc) {
1284 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285 enum pipe pipe = crtc->pipe;
1286
1287 if (!crtc->active)
1288 continue;
1289
1290 wm->pipe[pipe] = wm_state->wm[wm->level];
1291 if (wm->cxsr)
1292 wm->sr = wm_state->sr[wm->level];
1293
1294 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298 }
1299}
1300
1301static void vlv_update_wm(struct drm_crtc *crtc)
1302{
1303 struct drm_device *dev = crtc->dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306 enum pipe pipe = intel_crtc->pipe;
1307 struct vlv_wm_values wm = {};
1308
26e1fe4f 1309 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1310 vlv_merge_wm(dev, &wm);
1311
54f1b6e1
VS		 1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313 /* FIXME should be part of crtc atomic commit */
1314 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1315 return;
54f1b6e1 1316 }
262cd2e1
VS		 1317
1318 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320 chv_set_memory_dvfs(dev_priv, false);
1321
1322 if (wm.level < VLV_WM_LEVEL_PM5 &&
1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324 chv_set_memory_pm5(dev_priv, false);
1325
852eb00d 1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1327 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1328
54f1b6e1
VS		 1329 /* FIXME should be part of crtc atomic commit */
1330 vlv_pipe_set_fifo_size(intel_crtc);
1331
262cd2e1
VS		 1332 vlv_write_wm_values(intel_crtc, &wm);
1333
1334 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
852eb00d 1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1341 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1342
1343 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345 chv_set_memory_pm5(dev_priv, true);
1346
1347 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, true);
1350
1351 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1352}
1353
ae80152d
VS		 1354#define single_plane_enabled(mask) is_power_of_2(mask)
1355
46ba614c 1356static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1357{
46ba614c 1358 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1359 static const int sr_latency_ns = 12000;
1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362 int plane_sr, cursor_sr;
1363 unsigned int enabled = 0;
9858425c 1364 bool cxsr_enabled;
b445e3b0 1365
51cea1f4 1366 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1367 &g4x_wm_info, pessimal_latency_ns,
1368 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1369 &planea_wm, &cursora_wm))
51cea1f4 1370 enabled |= 1 << PIPE_A;
b445e3b0 1371
51cea1f4 1372 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1373 &g4x_wm_info, pessimal_latency_ns,
1374 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1375 &planeb_wm, &cursorb_wm))
51cea1f4 1376 enabled |= 1 << PIPE_B;
b445e3b0 1377
b445e3b0
ED		 1378 if (single_plane_enabled(enabled) &&
1379 g4x_compute_srwm(dev, ffs(enabled) - 1,
1380 sr_latency_ns,
1381 &g4x_wm_info,
1382 &g4x_cursor_wm_info,
52bd02d8 1383 &plane_sr, &cursor_sr)) {
9858425c 1384 cxsr_enabled = true;
52bd02d8 1385 } else {
9858425c 1386 cxsr_enabled = false;
5209b1f4 1387 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1388 plane_sr = cursor_sr = 0;
1389 }
b445e3b0 1390
a5043453
VS		 1391 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1393 planea_wm, cursora_wm,
1394 planeb_wm, cursorb_wm,
1395 plane_sr, cursor_sr);
1396
1397 I915_WRITE(DSPFW1,
f4998963
VS		 1398 FW_WM(plane_sr, SR) |
1399 FW_WM(cursorb_wm, CURSORB) |
1400 FW_WM(planeb_wm, PLANEB) |
1401 FW_WM(planea_wm, PLANEA));
b445e3b0 1402 I915_WRITE(DSPFW2,
8c919b28 1403 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1404 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1405 /* HPLL off in SR has some issues on G4x... disable it */
1406 I915_WRITE(DSPFW3,
8c919b28 1407 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1408 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1409
1410 if (cxsr_enabled)
1411 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1412}
1413
46ba614c 1414static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1415{
46ba614c 1416 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 struct drm_crtc *crtc;
1419 int srwm = 1;
1420 int cursor_sr = 16;
9858425c 1421 bool cxsr_enabled;
b445e3b0
ED		 1422
1423 /* Calc sr entries for one plane configs */
1424 crtc = single_enabled_crtc(dev);
1425 if (crtc) {
1426 /* self-refresh has much higher latency */
1427 static const int sr_latency_ns = 12000;
124abe07 1428 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1429 int clock = adjusted_mode->crtc_clock;
fec8cba3 1430 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1431 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1432 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1433 unsigned long line_time_us;
1434 int entries;
1435
922044c9 1436 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1437
1438 /* Use ns/us then divide to preserve precision */
1439 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440 pixel_size * hdisplay;
1441 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442 srwm = I965_FIFO_SIZE - entries;
1443 if (srwm < 0)
1444 srwm = 1;
1445 srwm &= 0x1ff;
1446 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447 entries, srwm);
1448
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1450 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1451 entries = DIV_ROUND_UP(entries,
1452 i965_cursor_wm_info.cacheline_size);
1453 cursor_sr = i965_cursor_wm_info.fifo_size -
1454 (entries + i965_cursor_wm_info.guard_size);
1455
1456 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457 cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460 "cursor %d\n", srwm, cursor_sr);
1461
9858425c 1462 cxsr_enabled = true;
b445e3b0 1463 } else {
9858425c 1464 cxsr_enabled = false;
b445e3b0 1465 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1466 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1467 }
1468
1469 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470 srwm);
1471
1472 /* 965 has limitations... */
f4998963
VS		 1473 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474 FW_WM(8, CURSORB) |
1475 FW_WM(8, PLANEB) |
1476 FW_WM(8, PLANEA));
1477 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478 FW_WM(8, PLANEC_OLD));
b445e3b0 1479 /* update cursor SR watermark */
f4998963 1480 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1481
1482 if (cxsr_enabled)
1483 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1484}
1485
f4998963
VS		 1486#undef FW_WM
1487
46ba614c 1488static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1489{
46ba614c 1490 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 const struct intel_watermark_params *wm_info;
1493 uint32_t fwater_lo;
1494 uint32_t fwater_hi;
1495 int cwm, srwm = 1;
1496 int fifo_size;
1497 int planea_wm, planeb_wm;
1498 struct drm_crtc *crtc, *enabled = NULL;
1499
1500 if (IS_I945GM(dev))
1501 wm_info = &i945_wm_info;
1502 else if (!IS_GEN2(dev))
1503 wm_info = &i915_wm_info;
1504 else
9d539105 1505 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1506
1507 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1509 if (intel_crtc_active(crtc)) {
241bfc38 1510 const struct drm_display_mode *adjusted_mode;
59bea882 1511 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1512 if (IS_GEN2(dev))
1513 cpp = 4;
1514
6e3c9717 1515 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1516 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1517 wm_info, fifo_size, cpp,
5aef6003 1518 pessimal_latency_ns);
b445e3b0 1519 enabled = crtc;
9d539105 1520 } else {
b445e3b0 1521 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1522 if (planea_wm > (long)wm_info->max_wm)
1523 planea_wm = wm_info->max_wm;
1524 }
1525
1526 if (IS_GEN2(dev))
1527 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1528
1529 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1531 if (intel_crtc_active(crtc)) {
241bfc38 1532 const struct drm_display_mode *adjusted_mode;
59bea882 1533 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1534 if (IS_GEN2(dev))
1535 cpp = 4;
1536
6e3c9717 1537 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1538 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1539 wm_info, fifo_size, cpp,
5aef6003 1540 pessimal_latency_ns);
b445e3b0
ED		 1541 if (enabled == NULL)
1542 enabled = crtc;
1543 else
1544 enabled = NULL;
9d539105 1545 } else {
b445e3b0 1546 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1547 if (planeb_wm > (long)wm_info->max_wm)
1548 planeb_wm = wm_info->max_wm;
1549 }
b445e3b0
ED		 1550
1551 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
2ab1bc9d 1553 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1554 struct drm_i915_gem_object *obj;
2ab1bc9d 1555
59bea882 1556 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1557
1558 /* self-refresh seems busted with untiled */
2ff8fde1 1559 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1560 enabled = NULL;
1561 }
1562
b445e3b0
ED		 1563 /*
1564 * Overlay gets an aggressive default since video jitter is bad.
1565 */
1566 cwm = 2;
1567
1568 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1569 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1570
1571 /* Calc sr entries for one plane configs */
1572 if (HAS_FW_BLC(dev) && enabled) {
1573 /* self-refresh has much higher latency */
1574 static const int sr_latency_ns = 6000;
124abe07 1575 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1576 int clock = adjusted_mode->crtc_clock;
fec8cba3 1577 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1578 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1579 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1580 unsigned long line_time_us;
1581 int entries;
1582
922044c9 1583 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1584
1585 /* Use ns/us then divide to preserve precision */
1586 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587 pixel_size * hdisplay;
1588 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590 srwm = wm_info->fifo_size - entries;
1591 if (srwm < 0)
1592 srwm = 1;
1593
1594 if (IS_I945G(dev) || IS_I945GM(dev))
1595 I915_WRITE(FW_BLC_SELF,
1596 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597 else if (IS_I915GM(dev))
1598 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599 }
1600
1601 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602 planea_wm, planeb_wm, cwm, srwm);
1603
1604 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605 fwater_hi = (cwm & 0x1f);
1606
1607 /* Set request length to 8 cachelines per fetch */
1608 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609 fwater_hi = fwater_hi | (1 << 8);
1610
1611 I915_WRITE(FW_BLC, fwater_lo);
1612 I915_WRITE(FW_BLC2, fwater_hi);
1613
5209b1f4
ID		 1614 if (enabled)
1615 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1616}
1617
feb56b93 1618static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1619{
46ba614c 1620 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 struct drm_crtc *crtc;
241bfc38 1623 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1624 uint32_t fwater_lo;
1625 int planea_wm;
1626
1627 crtc = single_enabled_crtc(dev);
1628 if (crtc == NULL)
1629 return;
1630
6e3c9717 1631 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1632 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1633 &i845_wm_info,
b445e3b0 1634 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1635 4, pessimal_latency_ns);
b445e3b0
ED		 1636 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637 fwater_lo |= (3<<8) | planea_wm;
1638
1639 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641 I915_WRITE(FW_BLC, fwater_lo);
1642}
1643
8cfb3407 1644uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1645{
fd4daa9c 1646 uint32_t pixel_rate;
801bcfff 1647
8cfb3407 1648 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1649
1650 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651 * adjust the pixel_rate here. */
1652
8cfb3407 1653 if (pipe_config->pch_pfit.enabled) {
801bcfff 1654 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1655 uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657 pipe_w = pipe_config->pipe_src_w;
1658 pipe_h = pipe_config->pipe_src_h;
801bcfff 1659
801bcfff
PZ		 1660 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661 pfit_h = pfit_size & 0xFFFF;
1662 if (pipe_w < pfit_w)
1663 pipe_w = pfit_w;
1664 if (pipe_h < pfit_h)
1665 pipe_h = pfit_h;
1666
1667 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1668 pfit_w * pfit_h);
1669 }
1670
1671 return pixel_rate;
1672}
1673
37126462 1674/* latency must be in 0.1us units. */
23297044 1675static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1676 uint32_t latency)
1677{
1678 uint64_t ret;
1679
3312ba65
VS		 1680 if (WARN(latency == 0, "Latency value missing\n"))
1681 return UINT_MAX;
1682
801bcfff
PZ		 1683 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1684 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1685
1686 return ret;
1687}
1688
37126462 1689/* latency must be in 0.1us units. */
23297044 1690static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1691 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1692 uint32_t latency)
1693{
1694 uint32_t ret;
1695
3312ba65
VS		 1696 if (WARN(latency == 0, "Latency value missing\n"))
1697 return UINT_MAX;
1698
801bcfff
PZ		 1699 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1700 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1701 ret = DIV_ROUND_UP(ret, 64) + 2;
1702 return ret;
1703}
1704
23297044 1705static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1706 uint8_t bytes_per_pixel)
1707{
1708 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1709}
1710
820c1980 1711struct ilk_wm_maximums {
cca32e9a
PZ		 1712 uint16_t pri;
1713 uint16_t spr;
1714 uint16_t cur;
1715 uint16_t fbc;
1716};
1717
261a27d1
MR		 1718/* used in computing the new watermarks state */
1719struct intel_wm_config {
1720 unsigned int num_pipes_active;
1721 bool sprites_enabled;
1722 bool sprites_scaled;
1723};
1724
37126462
VS		 1725/*
1726 * For both WM_PIPE and WM_LP.
1727 * mem_value must be in 0.1us units.
1728 */
7221fc33 1729static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1730 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1731 uint32_t mem_value,
1732 bool is_lp)
801bcfff 1733{
43d59eda 1734 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
cca32e9a
PZ		 1735 uint32_t method1, method2;
1736
7221fc33 1737 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1738 return 0;
1739
7221fc33 1740 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
cca32e9a
PZ		 1741
1742 if (!is_lp)
1743 return method1;
1744
7221fc33
MR		 1745 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1746 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1747 drm_rect_width(&pstate->dst),
1748 bpp,
cca32e9a
PZ		 1749 mem_value);
1750
1751 return min(method1, method2);
801bcfff
PZ		 1752}
1753
37126462
VS		 1754/*
1755 * For both WM_PIPE and WM_LP.
1756 * mem_value must be in 0.1us units.
1757 */
7221fc33 1758static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1759 const struct intel_plane_state *pstate,
801bcfff
PZ		 1760 uint32_t mem_value)
1761{
43d59eda 1762 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
801bcfff
PZ		 1763 uint32_t method1, method2;
1764
7221fc33 1765 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1766 return 0;
1767
7221fc33
MR		 1768 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1769 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1770 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1771 drm_rect_width(&pstate->dst),
1772 bpp,
801bcfff
PZ		 1773 mem_value);
1774 return min(method1, method2);
1775}
1776
37126462
VS		 1777/*
1778 * For both WM_PIPE and WM_LP.
1779 * mem_value must be in 0.1us units.
1780 */
7221fc33 1781static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1782 const struct intel_plane_state *pstate,
801bcfff
PZ		 1783 uint32_t mem_value)
1784{
43d59eda
MR		 1785 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1786
7221fc33 1787 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1788 return 0;
1789
7221fc33
MR		 1790 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1791 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1792 drm_rect_width(&pstate->dst),
1793 bpp,
801bcfff
PZ		 1794 mem_value);
1795}
1796
cca32e9a 1797/* Only for WM_LP. */
7221fc33 1798static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
1fda9882 1800 uint32_t pri_val)
cca32e9a 1801{
43d59eda
MR		 1802 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1803
7221fc33 1804 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1805 return 0;
1806
43d59eda 1807 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
cca32e9a
PZ		 1808}
1809
158ae64f
VS		 1810static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1811{
416f4727
VS		 1812 if (INTEL_INFO(dev)->gen >= 8)
1813 return 3072;
1814 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1815 return 768;
1816 else
1817 return 512;
1818}
1819
4e975081
VS		 1820static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1821 int level, bool is_sprite)
1822{
1823 if (INTEL_INFO(dev)->gen >= 8)
1824 /* BDW primary/sprite plane watermarks */
1825 return level == 0 ? 255 : 2047;
1826 else if (INTEL_INFO(dev)->gen >= 7)
1827 /* IVB/HSW primary/sprite plane watermarks */
1828 return level == 0 ? 127 : 1023;
1829 else if (!is_sprite)
1830 /* ILK/SNB primary plane watermarks */
1831 return level == 0 ? 127 : 511;
1832 else
1833 /* ILK/SNB sprite plane watermarks */
1834 return level == 0 ? 63 : 255;
1835}
1836
1837static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1838 int level)
1839{
1840 if (INTEL_INFO(dev)->gen >= 7)
1841 return level == 0 ? 63 : 255;
1842 else
1843 return level == 0 ? 31 : 63;
1844}
1845
1846static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1847{
1848 if (INTEL_INFO(dev)->gen >= 8)
1849 return 31;
1850 else
1851 return 15;
1852}
1853
158ae64f
VS		 1854/* Calculate the maximum primary/sprite plane watermark */
1855static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1856 int level,
240264f4 1857 const struct intel_wm_config *config,
158ae64f
VS		 1858 enum intel_ddb_partitioning ddb_partitioning,
1859 bool is_sprite)
1860{
1861 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1862
1863 /* if sprites aren't enabled, sprites get nothing */
240264f4 1864 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1865 return 0;
1866
1867 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1868 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1869 fifo_size /= INTEL_INFO(dev)->num_pipes;
1870
1871 /*
1872 * For some reason the non self refresh
1873 * FIFO size is only half of the self
1874 * refresh FIFO size on ILK/SNB.
1875 */
1876 if (INTEL_INFO(dev)->gen <= 6)
1877 fifo_size /= 2;
1878 }
1879
240264f4 1880 if (config->sprites_enabled) {
158ae64f
VS		 1881 /* level 0 is always calculated with 1:1 split */
1882 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1883 if (is_sprite)
1884 fifo_size *= 5;
1885 fifo_size /= 6;
1886 } else {
1887 fifo_size /= 2;
1888 }
1889 }
1890
1891 /* clamp to max that the registers can hold */
4e975081 1892 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1893}
1894
1895/* Calculate the maximum cursor plane watermark */
1896static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1897 int level,
1898 const struct intel_wm_config *config)
158ae64f
VS		 1899{
1900 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1901 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1902 return 64;
1903
1904 /* otherwise just report max that registers can hold */
4e975081 1905 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1906}
1907
d34ff9c6 1908static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1909 int level,
1910 const struct intel_wm_config *config,
1911 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1912 struct ilk_wm_maximums *max)
158ae64f 1913{
240264f4
VS		 1914 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1915 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1916 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1917 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1918}
1919
a3cb4048
VS		 1920static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1921 int level,
1922 struct ilk_wm_maximums *max)
1923{
1924 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1925 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1926 max->cur = ilk_cursor_wm_reg_max(dev, level);
1927 max->fbc = ilk_fbc_wm_reg_max(dev);
1928}
1929
d9395655 1930static bool ilk_validate_wm_level(int level,
820c1980 1931 const struct ilk_wm_maximums *max,
d9395655 1932 struct intel_wm_level *result)
a9786a11
VS		 1933{
1934 bool ret;
1935
1936 /* already determined to be invalid? */
1937 if (!result->enable)
1938 return false;
1939
1940 result->enable = result->pri_val <= max->pri &&
1941 result->spr_val <= max->spr &&
1942 result->cur_val <= max->cur;
1943
1944 ret = result->enable;
1945
1946 /*
1947 * HACK until we can pre-compute everything,
1948 * and thus fail gracefully if LP0 watermarks
1949 * are exceeded...
1950 */
1951 if (level == 0 && !result->enable) {
1952 if (result->pri_val > max->pri)
1953 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1954 level, result->pri_val, max->pri);
1955 if (result->spr_val > max->spr)
1956 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1957 level, result->spr_val, max->spr);
1958 if (result->cur_val > max->cur)
1959 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1960 level, result->cur_val, max->cur);
1961
1962 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1963 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1964 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1965 result->enable = true;
1966 }
1967
a9786a11
VS		 1968 return ret;
1969}
1970
d34ff9c6 1971static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1972 const struct intel_crtc *intel_crtc,
6f5ddd17 1973 int level,
7221fc33 1974 struct intel_crtc_state *cstate,
1fd527cc 1975 struct intel_wm_level *result)
6f5ddd17 1976{
261a27d1 1977 struct intel_plane *intel_plane;
6f5ddd17
VS		 1978 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1979 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1980 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1981
1982 /* WM1+ latency values stored in 0.5us units */
1983 if (level > 0) {
1984 pri_latency *= 5;
1985 spr_latency *= 5;
1986 cur_latency *= 5;
1987 }
1988
261a27d1
MR		 1989 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
1990 struct intel_plane_state *pstate =
1991 to_intel_plane_state(intel_plane->base.state);
1992
1993 switch (intel_plane->base.type) {
1994 case DRM_PLANE_TYPE_PRIMARY:
1995 result->pri_val = ilk_compute_pri_wm(cstate, pstate,
1996 pri_latency,
1997 level);
1998 result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
1999 result->pri_val);
2000 break;
2001 case DRM_PLANE_TYPE_OVERLAY:
2002 result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2003 spr_latency);
2004 break;
2005 case DRM_PLANE_TYPE_CURSOR:
2006 result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2007 cur_latency);
2008 break;
2009 }
2010 }
2011
6f5ddd17
VS		 2012 result->enable = true;
2013}
2014
801bcfff
PZ		 2015static uint32_t
2016hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2017{
2018 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7c5f93b0 2020 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2021 u32 linetime, ips_linetime;
1f8eeabf 2022
3ef00284 2023 if (!intel_crtc->active)
801bcfff 2024 return 0;
1011d8c4 2025
1f8eeabf
ED		 2026 /* The WM are computed with base on how long it takes to fill a single
2027 * row at the given clock rate, multiplied by 8.
2028 * */
124abe07
VS		 2029 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2030 adjusted_mode->crtc_clock);
2031 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2032 dev_priv->cdclk_freq);
1f8eeabf 2033
801bcfff
PZ		 2034 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2035 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2036}
2037
2af30a5c 2038static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2039{
2040 struct drm_i915_private *dev_priv = dev->dev_private;
2041
2af30a5c
PB		 2042 if (IS_GEN9(dev)) {
2043 uint32_t val;
4f947386 2044 int ret, i;
367294be 2045 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2046
2047 /* read the first set of memory latencies[0:3] */
2048 val = 0; /* data0 to be programmed to 0 for first set */
2049 mutex_lock(&dev_priv->rps.hw_lock);
2050 ret = sandybridge_pcode_read(dev_priv,
2051 GEN9_PCODE_READ_MEM_LATENCY,
2052 &val);
2053 mutex_unlock(&dev_priv->rps.hw_lock);
2054
2055 if (ret) {
2056 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2057 return;
2058 }
2059
2060 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2061 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2062 GEN9_MEM_LATENCY_LEVEL_MASK;
2063 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2064 GEN9_MEM_LATENCY_LEVEL_MASK;
2065 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK;
2067
2068 /* read the second set of memory latencies[4:7] */
2069 val = 1; /* data0 to be programmed to 1 for second set */
2070 mutex_lock(&dev_priv->rps.hw_lock);
2071 ret = sandybridge_pcode_read(dev_priv,
2072 GEN9_PCODE_READ_MEM_LATENCY,
2073 &val);
2074 mutex_unlock(&dev_priv->rps.hw_lock);
2075 if (ret) {
2076 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2077 return;
2078 }
2079
2080 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2081 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2082 GEN9_MEM_LATENCY_LEVEL_MASK;
2083 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2084 GEN9_MEM_LATENCY_LEVEL_MASK;
2085 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK;
2087
367294be 2088 /*
6f97235b
DL		 2089 * WaWmMemoryReadLatency:skl
2090 *
367294be
VK		 2091 * punit doesn't take into account the read latency so we need
2092 * to add 2us to the various latency levels we retrieve from
2093 * the punit.
2094 * - W0 is a bit special in that it's the only level that
2095 * can't be disabled if we want to have display working, so
2096 * we always add 2us there.
2097 * - For levels >=1, punit returns 0us latency when they are
2098 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2099 *
2100 * Additionally, if a level n (n > 1) has a 0us latency, all
2101 * levels m (m >= n) need to be disabled. We make sure to
2102 * sanitize the values out of the punit to satisfy this
2103 * requirement.
367294be
VK		 2104 */
2105 wm[0] += 2;
2106 for (level = 1; level <= max_level; level++)
2107 if (wm[level] != 0)
2108 wm[level] += 2;
4f947386
VK		 2109 else {
2110 for (i = level + 1; i <= max_level; i++)
2111 wm[i] = 0;
367294be 2112
4f947386
VK		 2113 break;
2114 }
2af30a5c 2115 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2116 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2117
2118 wm[0] = (sskpd >> 56) & 0xFF;
2119 if (wm[0] == 0)
2120 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2121 wm[1] = (sskpd >> 4) & 0xFF;
2122 wm[2] = (sskpd >> 12) & 0xFF;
2123 wm[3] = (sskpd >> 20) & 0x1FF;
2124 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2125 } else if (INTEL_INFO(dev)->gen >= 6) {
2126 uint32_t sskpd = I915_READ(MCH_SSKPD);
2127
2128 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2129 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2130 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2131 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2132 } else if (INTEL_INFO(dev)->gen >= 5) {
2133 uint32_t mltr = I915_READ(MLTR_ILK);
2134
2135 /* ILK primary LP0 latency is 700 ns */
2136 wm[0] = 7;
2137 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2138 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2139 }
2140}
2141
53615a5e
VS		 2142static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2143{
2144 /* ILK sprite LP0 latency is 1300 ns */
2145 if (INTEL_INFO(dev)->gen == 5)
2146 wm[0] = 13;
2147}
2148
2149static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2150{
2151 /* ILK cursor LP0 latency is 1300 ns */
2152 if (INTEL_INFO(dev)->gen == 5)
2153 wm[0] = 13;
2154
2155 /* WaDoubleCursorLP3Latency:ivb */
2156 if (IS_IVYBRIDGE(dev))
2157 wm[3] *= 2;
2158}
2159
546c81fd 2160int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2161{
26ec971e 2162 /* how many WM levels are we expecting */
b6e742f6 2163 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2164 return 7;
2165 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2166 return 4;
26ec971e 2167 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2168 return 3;
26ec971e 2169 else
ad0d6dc4
VS		 2170 return 2;
2171}
7526ed79 2172
ad0d6dc4
VS		 2173static void intel_print_wm_latency(struct drm_device *dev,
2174 const char *name,
2af30a5c 2175 const uint16_t wm[8])
ad0d6dc4
VS		 2176{
2177 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2178
2179 for (level = 0; level <= max_level; level++) {
2180 unsigned int latency = wm[level];
2181
2182 if (latency == 0) {
2183 DRM_ERROR("%s WM%d latency not provided\n",
2184 name, level);
2185 continue;
2186 }
2187
2af30a5c
PB		 2188 /*
2189 * - latencies are in us on gen9.
2190 * - before then, WM1+ latency values are in 0.5us units
2191 */
2192 if (IS_GEN9(dev))
2193 latency *= 10;
2194 else if (level > 0)
26ec971e
VS		 2195 latency *= 5;
2196
2197 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2198 name, level, wm[level],
2199 latency / 10, latency % 10);
2200 }
2201}
2202
e95a2f75
VS		 2203static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2204 uint16_t wm[5], uint16_t min)
2205{
2206 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2207
2208 if (wm[0] >= min)
2209 return false;
2210
2211 wm[0] = max(wm[0], min);
2212 for (level = 1; level <= max_level; level++)
2213 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2214
2215 return true;
2216}
2217
2218static void snb_wm_latency_quirk(struct drm_device *dev)
2219{
2220 struct drm_i915_private *dev_priv = dev->dev_private;
2221 bool changed;
2222
2223 /*
2224 * The BIOS provided WM memory latency values are often
2225 * inadequate for high resolution displays. Adjust them.
2226 */
2227 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2228 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2229 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2230
2231 if (!changed)
2232 return;
2233
2234 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2235 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2236 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2237 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2238}
2239
fa50ad61 2240static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2241{
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243
2244 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2245
2246 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2247 sizeof(dev_priv->wm.pri_latency));
2248 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2249 sizeof(dev_priv->wm.pri_latency));
2250
2251 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2252 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2253
2254 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2255 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2256 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2257
2258 if (IS_GEN6(dev))
2259 snb_wm_latency_quirk(dev);
53615a5e
VS		 2260}
2261
2af30a5c
PB		 2262static void skl_setup_wm_latency(struct drm_device *dev)
2263{
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265
2266 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2267 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2268}
2269
261a27d1
MR		 2270static void ilk_compute_wm_config(struct drm_device *dev,
2271 struct intel_wm_config *config)
2272{
2273 struct intel_crtc *intel_crtc;
2274
2275 /* Compute the currently _active_ config */
2276 for_each_intel_crtc(dev, intel_crtc) {
2277 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2278
2279 if (!wm->pipe_enabled)
2280 continue;
2281
2282 config->sprites_enabled |= wm->sprites_enabled;
2283 config->sprites_scaled |= wm->sprites_scaled;
2284 config->num_pipes_active++;
2285 }
2286}
2287
0b2ae6d7 2288/* Compute new watermarks for the pipe */
261a27d1
MR		 2289static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2290 struct intel_pipe_wm *pipe_wm)
0b2ae6d7 2291{
261a27d1
MR		 2292 struct drm_crtc *crtc = cstate->base.crtc;
2293 struct drm_device *dev = crtc->dev;
d34ff9c6 2294 const struct drm_i915_private *dev_priv = dev->dev_private;
261a27d1 2295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
43d59eda
MR		 2296 struct intel_plane *intel_plane;
2297 struct intel_plane_state *sprstate = NULL;
0b2ae6d7
VS		 2298 int level, max_level = ilk_wm_max_level(dev);
2299 /* LP0 watermark maximums depend on this pipe alone */
2300 struct intel_wm_config config = {
2301 .num_pipes_active = 1,
0b2ae6d7 2302 };
820c1980 2303 struct ilk_wm_maximums max;
0b2ae6d7 2304
43d59eda 2305 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
261a27d1
MR		 2306 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2307 sprstate = to_intel_plane_state(intel_plane->base.state);
2308 break;
2309 }
43d59eda
MR		 2310 }
2311
2312 config.sprites_enabled = sprstate->visible;
2313 config.sprites_scaled = sprstate->visible &&
2314 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2315 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2316
7221fc33 2317 pipe_wm->pipe_enabled = cstate->base.active;
261a27d1 2318 pipe_wm->sprites_enabled = sprstate->visible;
43d59eda 2319 pipe_wm->sprites_scaled = config.sprites_scaled;
2a44b76b 2320
7b39a0b7 2321 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2322 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2323 max_level = 1;
2324
2325 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
43d59eda 2326 if (config.sprites_scaled)
7b39a0b7
VS		 2327 max_level = 0;
2328
261a27d1 2329 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
0b2ae6d7 2330
a42a5719 2331 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
261a27d1 2332 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2333
a3cb4048
VS		 2334 /* LP0 watermarks always use 1/2 DDB partitioning */
2335 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2336
0b2ae6d7 2337 /* At least LP0 must be valid */
a3cb4048 2338 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
261a27d1 2339 return false;
a3cb4048
VS		 2340
2341 ilk_compute_wm_reg_maximums(dev, 1, &max);
2342
2343 for (level = 1; level <= max_level; level++) {
2344 struct intel_wm_level wm = {};
2345
261a27d1 2346 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
a3cb4048
VS		 2347
2348 /*
2349 * Disable any watermark level that exceeds the
2350 * register maximums since such watermarks are
2351 * always invalid.
2352 */
2353 if (!ilk_validate_wm_level(level, &max, &wm))
2354 break;
2355
2356 pipe_wm->wm[level] = wm;
2357 }
2358
261a27d1 2359 return true;
0b2ae6d7
VS		 2360}
2361
2362/*
2363 * Merge the watermarks from all active pipes for a specific level.
2364 */
2365static void ilk_merge_wm_level(struct drm_device *dev,
2366 int level,
2367 struct intel_wm_level *ret_wm)
2368{
2369 const struct intel_crtc *intel_crtc;
2370
d52fea5b
VS		 2371 ret_wm->enable = true;
2372
d3fcc808 2373 for_each_intel_crtc(dev, intel_crtc) {
261a27d1 2374 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
fe392efd
VS		 2375 const struct intel_wm_level *wm = &active->wm[level];
2376
2377 if (!active->pipe_enabled)
2378 continue;
0b2ae6d7 2379
d52fea5b
VS		 2380 /*
2381 * The watermark values may have been used in the past,
2382 * so we must maintain them in the registers for some
2383 * time even if the level is now disabled.
2384 */
0b2ae6d7 2385 if (!wm->enable)
d52fea5b 2386 ret_wm->enable = false;
0b2ae6d7
VS		 2387
2388 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2389 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2390 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2391 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2392 }
0b2ae6d7
VS		 2393}
2394
2395/*
2396 * Merge all low power watermarks for all active pipes.
2397 */
2398static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2399 const struct intel_wm_config *config,
820c1980 2400 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2401 struct intel_pipe_wm *merged)
2402{
7733b49b 2403 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2404 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2405 int last_enabled_level = max_level;
0b2ae6d7 2406
0ba22e26
VS		 2407 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2408 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2409 config->num_pipes_active > 1)
2410 return;
2411
6c8b6c28
VS		 2412 /* ILK: FBC WM must be disabled always */
2413 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2414
2415 /* merge each WM1+ level */
2416 for (level = 1; level <= max_level; level++) {
2417 struct intel_wm_level *wm = &merged->wm[level];
2418
2419 ilk_merge_wm_level(dev, level, wm);
2420
d52fea5b
VS		 2421 if (level > last_enabled_level)
2422 wm->enable = false;
2423 else if (!ilk_validate_wm_level(level, max, wm))
2424 /* make sure all following levels get disabled */
2425 last_enabled_level = level - 1;
0b2ae6d7
VS		 2426
2427 /*
2428 * The spec says it is preferred to disable
2429 * FBC WMs instead of disabling a WM level.
2430 */
2431 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2432 if (wm->enable)
2433 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2434 wm->fbc_val = 0;
2435 }
2436 }
6c8b6c28
VS		 2437
2438 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2439 /*
2440 * FIXME this is racy. FBC might get enabled later.
2441 * What we should check here is whether FBC can be
2442 * enabled sometime later.
2443 */
7733b49b
PZ		 2444 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2445 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2446 for (level = 2; level <= max_level; level++) {
2447 struct intel_wm_level *wm = &merged->wm[level];
2448
2449 wm->enable = false;
2450 }
2451 }
0b2ae6d7
VS		 2452}
2453
b380ca3c
VS		 2454static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2455{
2456 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2457 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2458}
2459
a68d68ee
VS		 2460/* The value we need to program into the WM_LPx latency field */
2461static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2462{
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464
a42a5719 2465 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2466 return 2 * level;
2467 else
2468 return dev_priv->wm.pri_latency[level];
2469}
2470
820c1980 2471static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2472 const struct intel_pipe_wm *merged,
609cedef 2473 enum intel_ddb_partitioning partitioning,
820c1980 2474 struct ilk_wm_values *results)
801bcfff 2475{
0b2ae6d7
VS		 2476 struct intel_crtc *intel_crtc;
2477 int level, wm_lp;
cca32e9a 2478
0362c781 2479 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2480 results->partitioning = partitioning;
cca32e9a 2481
0b2ae6d7 2482 /* LP1+ register values */
cca32e9a 2483 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2484 const struct intel_wm_level *r;
801bcfff 2485
b380ca3c 2486 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2487
0362c781 2488 r = &merged->wm[level];
cca32e9a 2489
d52fea5b
VS		 2490 /*
2491 * Maintain the watermark values even if the level is
2492 * disabled. Doing otherwise could cause underruns.
2493 */
2494 results->wm_lp[wm_lp - 1] =
a68d68ee 2495 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2496 (r->pri_val << WM1_LP_SR_SHIFT) |
2497 r->cur_val;
2498
d52fea5b
VS		 2499 if (r->enable)
2500 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2501
416f4727
VS		 2502 if (INTEL_INFO(dev)->gen >= 8)
2503 results->wm_lp[wm_lp - 1] |=
2504 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2505 else
2506 results->wm_lp[wm_lp - 1] |=
2507 r->fbc_val << WM1_LP_FBC_SHIFT;
2508
d52fea5b
VS		 2509 /*
2510 * Always set WM1S_LP_EN when spr_val != 0, even if the
2511 * level is disabled. Doing otherwise could cause underruns.
2512 */
6cef2b8a
VS		 2513 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2514 WARN_ON(wm_lp != 1);
2515 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2516 } else
2517 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2518 }
801bcfff 2519
0b2ae6d7 2520 /* LP0 register values */
d3fcc808 2521 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2522 enum pipe pipe = intel_crtc->pipe;
261a27d1
MR		 2523 const struct intel_wm_level *r =
2524 &intel_crtc->wm.active.wm[0];
0b2ae6d7
VS		 2525
2526 if (WARN_ON(!r->enable))
2527 continue;
2528
261a27d1 2529 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2530
0b2ae6d7
VS		 2531 results->wm_pipe[pipe] =
2532 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2533 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2534 r->cur_val;
801bcfff
PZ		 2535 }
2536}
2537
861f3389
PZ		 2538/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2539 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2540static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2541 struct intel_pipe_wm *r1,
2542 struct intel_pipe_wm *r2)
861f3389 2543{
198a1e9b
VS		 2544 int level, max_level = ilk_wm_max_level(dev);
2545 int level1 = 0, level2 = 0;
861f3389 2546
198a1e9b
VS		 2547 for (level = 1; level <= max_level; level++) {
2548 if (r1->wm[level].enable)
2549 level1 = level;
2550 if (r2->wm[level].enable)
2551 level2 = level;
861f3389
PZ		 2552 }
2553
198a1e9b
VS		 2554 if (level1 == level2) {
2555 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2556 return r2;
2557 else
2558 return r1;
198a1e9b 2559 } else if (level1 > level2) {
861f3389
PZ		 2560 return r1;
2561 } else {
2562 return r2;
2563 }
2564}
2565
49a687c4
VS		 2566/* dirty bits used to track which watermarks need changes */
2567#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2568#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2569#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2570#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2571#define WM_DIRTY_FBC (1 << 24)
2572#define WM_DIRTY_DDB (1 << 25)
2573
055e393f 2574static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2575 const struct ilk_wm_values *old,
2576 const struct ilk_wm_values *new)
49a687c4
VS		 2577{
2578 unsigned int dirty = 0;
2579 enum pipe pipe;
2580 int wm_lp;
2581
055e393f 2582 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2583 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2584 dirty |= WM_DIRTY_LINETIME(pipe);
2585 /* Must disable LP1+ watermarks too */
2586 dirty |= WM_DIRTY_LP_ALL;
2587 }
2588
2589 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2590 dirty |= WM_DIRTY_PIPE(pipe);
2591 /* Must disable LP1+ watermarks too */
2592 dirty |= WM_DIRTY_LP_ALL;
2593 }
2594 }
2595
2596 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2597 dirty |= WM_DIRTY_FBC;
2598 /* Must disable LP1+ watermarks too */
2599 dirty |= WM_DIRTY_LP_ALL;
2600 }
2601
2602 if (old->partitioning != new->partitioning) {
2603 dirty |= WM_DIRTY_DDB;
2604 /* Must disable LP1+ watermarks too */
2605 dirty |= WM_DIRTY_LP_ALL;
2606 }
2607
2608 /* LP1+ watermarks already deemed dirty, no need to continue */
2609 if (dirty & WM_DIRTY_LP_ALL)
2610 return dirty;
2611
2612 /* Find the lowest numbered LP1+ watermark in need of an update... */
2613 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2614 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2615 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2616 break;
2617 }
2618
2619 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2620 for (; wm_lp <= 3; wm_lp++)
2621 dirty |= WM_DIRTY_LP(wm_lp);
2622
2623 return dirty;
2624}
2625
8553c18e
VS		 2626static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2627 unsigned int dirty)
801bcfff 2628{
820c1980 2629 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2630 bool changed = false;
801bcfff 2631
facd619b
VS		 2632 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2633 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2634 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2635 changed = true;
facd619b
VS		 2636 }
2637 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2638 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2639 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2640 changed = true;
facd619b
VS		 2641 }
2642 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2643 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2644 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2645 changed = true;
facd619b 2646 }
801bcfff 2647
facd619b
VS		 2648 /*
2649 * Don't touch WM1S_LP_EN here.
2650 * Doing so could cause underruns.
2651 */
6cef2b8a 2652
8553c18e
VS		 2653 return changed;
2654}
2655
2656/*
2657 * The spec says we shouldn't write when we don't need, because every write
2658 * causes WMs to be re-evaluated, expending some power.
2659 */
820c1980
ID		 2660static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2661 struct ilk_wm_values *results)
8553c18e
VS		 2662{
2663 struct drm_device *dev = dev_priv->dev;
820c1980 2664 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2665 unsigned int dirty;
2666 uint32_t val;
2667
055e393f 2668 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2669 if (!dirty)
2670 return;
2671
2672 _ilk_disable_lp_wm(dev_priv, dirty);
2673
49a687c4 2674 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2675 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2676 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2677 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2678 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2679 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2680
49a687c4 2681 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2682 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2683 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2684 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2685 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2686 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2687
49a687c4 2688 if (dirty & WM_DIRTY_DDB) {
a42a5719 2689 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2690 val = I915_READ(WM_MISC);
2691 if (results->partitioning == INTEL_DDB_PART_1_2)
2692 val &= ~WM_MISC_DATA_PARTITION_5_6;
2693 else
2694 val |= WM_MISC_DATA_PARTITION_5_6;
2695 I915_WRITE(WM_MISC, val);
2696 } else {
2697 val = I915_READ(DISP_ARB_CTL2);
2698 if (results->partitioning == INTEL_DDB_PART_1_2)
2699 val &= ~DISP_DATA_PARTITION_5_6;
2700 else
2701 val |= DISP_DATA_PARTITION_5_6;
2702 I915_WRITE(DISP_ARB_CTL2, val);
2703 }
1011d8c4
PZ		 2704 }
2705
49a687c4 2706 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2707 val = I915_READ(DISP_ARB_CTL);
2708 if (results->enable_fbc_wm)
2709 val &= ~DISP_FBC_WM_DIS;
2710 else
2711 val |= DISP_FBC_WM_DIS;
2712 I915_WRITE(DISP_ARB_CTL, val);
2713 }
2714
954911eb
ID		 2715 if (dirty & WM_DIRTY_LP(1) &&
2716 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2717 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2718
2719 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2720 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2721 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2722 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2723 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2724 }
801bcfff 2725
facd619b 2726 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2727 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2728 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2729 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2730 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2731 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2732
2733 dev_priv->wm.hw = *results;
801bcfff
PZ		 2734}
2735
8553c18e
VS		 2736static bool ilk_disable_lp_wm(struct drm_device *dev)
2737{
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739
2740 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2741}
2742
b9cec075
DL		 2743/*
2744 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2745 * different active planes.
2746 */
2747
2748#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2749#define BXT_DDB_SIZE 512
b9cec075 2750
024c9045
MR		 2751/*
2752 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2753 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2754 * other universal planes are in indices 1..n. Note that this may leave unused
2755 * indices between the top "sprite" plane and the cursor.
2756 */
2757static int
2758skl_wm_plane_id(const struct intel_plane *plane)
2759{
2760 switch (plane->base.type) {
2761 case DRM_PLANE_TYPE_PRIMARY:
2762 return 0;
2763 case DRM_PLANE_TYPE_CURSOR:
2764 return PLANE_CURSOR;
2765 case DRM_PLANE_TYPE_OVERLAY:
2766 return plane->plane + 1;
2767 default:
2768 MISSING_CASE(plane->base.type);
2769 return plane->plane;
2770 }
2771}
2772
b9cec075
DL		 2773static void
2774skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2775 const struct intel_crtc_state *cstate,
b9cec075 2776 const struct intel_wm_config *config,
b9cec075
DL		 2777 struct skl_ddb_entry *alloc /* out */)
2778{
024c9045 2779 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2780 struct drm_crtc *crtc;
2781 unsigned int pipe_size, ddb_size;
2782 int nth_active_pipe;
2783
024c9045 2784 if (!cstate->base.active) {
b9cec075
DL		 2785 alloc->start = 0;
2786 alloc->end = 0;
2787 return;
2788 }
2789
43d735a6
DL		 2790 if (IS_BROXTON(dev))
2791 ddb_size = BXT_DDB_SIZE;
2792 else
2793 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2794
2795 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2796
2797 nth_active_pipe = 0;
2798 for_each_crtc(dev, crtc) {
3ef00284 2799 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2800 continue;
2801
2802 if (crtc == for_crtc)
2803 break;
2804
2805 nth_active_pipe++;
2806 }
2807
2808 pipe_size = ddb_size / config->num_pipes_active;
2809 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2810 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2811}
2812
2813static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2814{
2815 if (config->num_pipes_active == 1)
2816 return 32;
2817
2818 return 8;
2819}
2820
a269c583
DL		 2821static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2822{
2823 entry->start = reg & 0x3ff;
2824 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2825 if (entry->end)
2826 entry->end += 1;
a269c583
DL		 2827}
2828
08db6652
DL		 2829void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2830 struct skl_ddb_allocation *ddb /* out */)
a269c583 2831{
a269c583
DL		 2832 enum pipe pipe;
2833 int plane;
2834 u32 val;
2835
2836 for_each_pipe(dev_priv, pipe) {
dd740780 2837 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2838 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2839 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2840 val);
2841 }
2842
2843 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2844 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2845 val);
a269c583
DL		 2846 }
2847}
2848
b9cec075 2849static unsigned int
024c9045
MR		 2850skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2851 const struct drm_plane_state *pstate,
2852 int y)
b9cec075 2853{
024c9045
MR		 2854 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2855 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2856
2857 /* for planar format */
024c9045 2858 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2859 if (y) /* y-plane data rate */
024c9045
MR		 2860 return intel_crtc->config->pipe_src_w *
2861 intel_crtc->config->pipe_src_h *
2862 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2863 else /* uv-plane data rate */
024c9045
MR		 2864 return (intel_crtc->config->pipe_src_w/2) *
2865 (intel_crtc->config->pipe_src_h/2) *
2866 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2867 }
2868
2869 /* for packed formats */
024c9045
MR		 2870 return intel_crtc->config->pipe_src_w *
2871 intel_crtc->config->pipe_src_h *
2872 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2873}
2874
2875/*
2876 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2877 * a 8192x4096@32bpp framebuffer:
2878 * 3 * 4096 * 8192 * 4 < 2^32
2879 */
2880static unsigned int
024c9045 2881skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2882{
024c9045
MR		 2883 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2884 struct drm_device *dev = intel_crtc->base.dev;
2885 const struct intel_plane *intel_plane;
b9cec075 2886 unsigned int total_data_rate = 0;
b9cec075 2887
024c9045
MR		 2888 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2889 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2890
024c9045 2891 if (pstate->fb == NULL)
b9cec075
DL		 2892 continue;
2893
024c9045
MR		 2894 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2895 continue;
2896
2897 /* packed/uv */
2898 total_data_rate += skl_plane_relative_data_rate(cstate,
2899 pstate,
2900 0);
2901
2902 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2903 /* y-plane */
2904 total_data_rate += skl_plane_relative_data_rate(cstate,
2905 pstate,
2906 1);
b9cec075
DL		 2907 }
2908
2909 return total_data_rate;
2910}
2911
2912static void
024c9045 2913skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
261a27d1 2914 const struct intel_wm_config *config,
b9cec075
DL		 2915 struct skl_ddb_allocation *ddb /* out */)
2916{
024c9045 2917 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 2918 struct drm_device *dev = crtc->dev;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2920 struct intel_plane *intel_plane;
b9cec075 2921 enum pipe pipe = intel_crtc->pipe;
34bb56af 2922 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2923 uint16_t alloc_size, start, cursor_blocks;
80958155 2924 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2925 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2926 unsigned int total_data_rate;
b9cec075 2927
024c9045 2928 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2929 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2930 if (alloc_size == 0) {
2931 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2932 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2933 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2934 return;
2935 }
2936
2937 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2938 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2939 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2940
2941 alloc_size -= cursor_blocks;
34bb56af 2942 alloc->end -= cursor_blocks;
b9cec075 2943
80958155 2944 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 2945 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2946 struct drm_plane *plane = &intel_plane->base;
2947 struct drm_framebuffer *fb = plane->state->fb;
2948 int id = skl_wm_plane_id(intel_plane);
80958155 2949
024c9045
MR		 2950 if (fb == NULL)
2951 continue;
2952 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2953 continue;
2954
024c9045
MR		 2955 minimum[id] = 8;
2956 alloc_size -= minimum[id];
2957 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2958 alloc_size -= y_minimum[id];
80958155
DL		 2959 }
2960
b9cec075 2961 /*
80958155
DL		 2962 * 2. Distribute the remaining space in proportion to the amount of
2963 * data each plane needs to fetch from memory.
b9cec075
DL		 2964 *
2965 * FIXME: we may not allocate every single block here.
2966 */
024c9045 2967 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 2968
34bb56af 2969 start = alloc->start;
024c9045
MR		 2970 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2971 struct drm_plane *plane = &intel_plane->base;
2972 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 2973 unsigned int data_rate, y_data_rate;
2974 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 2975 int id = skl_wm_plane_id(intel_plane);
b9cec075 2976
024c9045
MR		 2977 if (pstate->fb == NULL)
2978 continue;
2979 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 2980 continue;
2981
024c9045 2982 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 2983
2984 /*
2cd601c6 2985 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 2986 * promote the expression to 64 bits to avoid overflowing, the
2987 * result is < available as data_rate / total_data_rate < 1
2988 */
024c9045 2989 plane_blocks = minimum[id];
80958155
DL		 2990 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2991 total_data_rate);
b9cec075 2992
024c9045
MR		 2993 ddb->plane[pipe][id].start = start;
2994 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 2995
2996 start += plane_blocks;
2cd601c6
CK		 2997
2998 /*
2999 * allocation for y_plane part of planar format:
3000 */
024c9045
MR		 3001 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3002 y_data_rate = skl_plane_relative_data_rate(cstate,
3003 pstate,
3004 1);
3005 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3006 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3007 total_data_rate);
3008
024c9045
MR		 3009 ddb->y_plane[pipe][id].start = start;
3010 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3011
3012 start += y_plane_blocks;
3013 }
3014
b9cec075
DL		 3015 }
3016
3017}
3018
5cec258b 3019static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3020{
3021 /* TODO: Take into account the scalers once we support them */
2d112de7 3022 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3023}
3024
3025/*
3026 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3027 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3028 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3029 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3030*/
3031static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3032 uint32_t latency)
3033{
3034 uint32_t wm_intermediate_val, ret;
3035
3036 if (latency == 0)
3037 return UINT_MAX;
3038
d4c2aa60 3039 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3040 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3041
3042 return ret;
3043}
3044
3045static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3046 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3047 uint64_t tiling, uint32_t latency)
2d41c0b5 3048{
d4c2aa60
TU		 3049 uint32_t ret;
3050 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3051 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3052
3053 if (latency == 0)
3054 return UINT_MAX;
3055
3056 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3057
3058 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3059 tiling == I915_FORMAT_MOD_Yf_TILED) {
3060 plane_bytes_per_line *= 4;
3061 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3062 plane_blocks_per_line /= 4;
3063 } else {
3064 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3065 }
3066
2d41c0b5
PB		 3067 wm_intermediate_val = latency * pixel_rate;
3068 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3069 plane_blocks_per_line;
2d41c0b5
PB		 3070
3071 return ret;
3072}
3073
2d41c0b5
PB		 3074static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3075 const struct intel_crtc *intel_crtc)
3076{
3077 struct drm_device *dev = intel_crtc->base.dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3080 enum pipe pipe = intel_crtc->pipe;
3081
3082 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3083 sizeof(new_ddb->plane[pipe])))
3084 return true;
3085
4969d33e
MR		 3086 if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3087 sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
2d41c0b5
PB		 3088 return true;
3089
3090 return false;
3091}
3092
261a27d1
MR		 3093static void skl_compute_wm_global_parameters(struct drm_device *dev,
3094 struct intel_wm_config *config)
3095{
3096 struct drm_crtc *crtc;
3097
3098 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3099 config->num_pipes_active += to_intel_crtc(crtc)->active;
2791a16c
PZ		 3100}
3101
d4c2aa60 3102static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3103 struct intel_crtc_state *cstate,
3104 struct intel_plane *intel_plane,
afb024aa 3105 uint16_t ddb_allocation,
d4c2aa60 3106 int level,
afb024aa
DL		 3107 uint16_t *out_blocks, /* out */
3108 uint8_t *out_lines /* out */)
2d41c0b5 3109{
024c9045
MR		 3110 struct drm_plane *plane = &intel_plane->base;
3111 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3112 uint32_t latency = dev_priv->wm.skl_latency[level];
3113 uint32_t method1, method2;
3114 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3115 uint32_t res_blocks, res_lines;
3116 uint32_t selected_result;
2cd601c6 3117 uint8_t bytes_per_pixel;
2d41c0b5 3118
024c9045 3119 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3120 return false;
3121
024c9045
MR		 3122 bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3123 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
2cd601c6 3124 bytes_per_pixel,
d4c2aa60 3125 latency);
024c9045
MR		 3126 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3127 cstate->base.adjusted_mode.crtc_htotal,
3128 cstate->pipe_src_w,
2cd601c6 3129 bytes_per_pixel,
024c9045 3130 fb->modifier[0],
d4c2aa60 3131 latency);
2d41c0b5 3132
024c9045 3133 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
d4c2aa60 3134 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3135
024c9045
MR		 3136 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3137 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3138 uint32_t min_scanlines = 4;
3139 uint32_t y_tile_minimum;
024c9045
MR		 3140 if (intel_rotation_90_or_270(plane->state->rotation)) {
3141 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3142 drm_format_plane_cpp(fb->pixel_format, 1) :
3143 drm_format_plane_cpp(fb->pixel_format, 0);
3144
3145 switch (bpp) {
1fc0a8f7
TU		 3146 case 1:
3147 min_scanlines = 16;
3148 break;
3149 case 2:
3150 min_scanlines = 8;
3151 break;
3152 case 8:
3153 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3154 }
1fc0a8f7
TU		 3155 }
3156 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3157 selected_result = max(method2, y_tile_minimum);
3158 } else {
3159 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3160 selected_result = min(method1, method2);
3161 else
3162 selected_result = method1;
3163 }
2d41c0b5 3164
d4c2aa60
TU		 3165 res_blocks = selected_result + 1;
3166 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3167
0fda6568 3168 if (level >= 1 && level <= 7) {
024c9045
MR		 3169 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3170 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3171 res_lines += 4;
3172 else
3173 res_blocks++;
3174 }
e6d66171 3175
d4c2aa60 3176 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3177 return false;
3178
3179 *out_blocks = res_blocks;
3180 *out_lines = res_lines;
2d41c0b5
PB		 3181
3182 return true;
3183}
3184
3185static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3186 struct skl_ddb_allocation *ddb,
024c9045 3187 struct intel_crtc_state *cstate,
2d41c0b5 3188 int level,
2d41c0b5
PB		 3189 struct skl_wm_level *result)
3190{
024c9045
MR		 3191 struct drm_device *dev = dev_priv->dev;
3192 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3193 struct intel_plane *intel_plane;
2d41c0b5 3194 uint16_t ddb_blocks;
024c9045
MR		 3195 enum pipe pipe = intel_crtc->pipe;
3196
3197 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3198 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3199
2d41c0b5
PB		 3200 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3201
d4c2aa60 3202 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3203 cstate,
3204 intel_plane,
2d41c0b5 3205 ddb_blocks,
d4c2aa60 3206 level,
2d41c0b5
PB		 3207 &result->plane_res_b[i],
3208 &result->plane_res_l[i]);
3209 }
2d41c0b5
PB		 3210}
3211
407b50f3 3212static uint32_t
024c9045 3213skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3214{
024c9045 3215 if (!cstate->base.active)
407b50f3
DL		 3216 return 0;
3217
024c9045 3218 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3219 return 0;
407b50f3 3220
024c9045
MR		 3221 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3222 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3223}
3224
024c9045 3225static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3226 struct skl_wm_level *trans_wm /* out */)
407b50f3 3227{
024c9045 3228 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3230 struct intel_plane *intel_plane;
9414f563 3231
024c9045 3232 if (!cstate->base.active)
407b50f3 3233 return;
9414f563
DL		 3234
3235 /* Until we know more, just disable transition WMs */
024c9045
MR		 3236 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3237 int i = skl_wm_plane_id(intel_plane);
3238
9414f563 3239 trans_wm->plane_en[i] = false;
024c9045 3240 }
407b50f3
DL		 3241}
3242
024c9045 3243static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3244 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3245 struct skl_pipe_wm *pipe_wm)
3246{
024c9045 3247 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3248 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3249 int level, max_level = ilk_wm_max_level(dev);
3250
3251 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3252 skl_compute_wm_level(dev_priv, ddb, cstate,
3253 level, &pipe_wm->wm[level]);
2d41c0b5 3254 }
024c9045 3255 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3256
024c9045 3257 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3258}
3259
3260static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3261 struct skl_pipe_wm *p_wm,
3262 struct skl_wm_values *r,
3263 struct intel_crtc *intel_crtc)
3264{
3265 int level, max_level = ilk_wm_max_level(dev);
3266 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3267 uint32_t temp;
3268 int i;
2d41c0b5
PB		 3269
3270 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3271 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3272 temp = 0;
2d41c0b5
PB		 3273
3274 temp |= p_wm->wm[level].plane_res_l[i] <<
3275 PLANE_WM_LINES_SHIFT;
3276 temp |= p_wm->wm[level].plane_res_b[i];
3277 if (p_wm->wm[level].plane_en[i])
3278 temp |= PLANE_WM_EN;
3279
3280 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3281 }
3282
3283 temp = 0;
2d41c0b5 3284
4969d33e
MR		 3285 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3286 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3287
4969d33e 3288 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3289 temp |= PLANE_WM_EN;
3290
4969d33e 3291 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3292
3293 }
3294
9414f563
DL		 3295 /* transition WMs */
3296 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3297 temp = 0;
3298 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3299 temp |= p_wm->trans_wm.plane_res_b[i];
3300 if (p_wm->trans_wm.plane_en[i])
3301 temp |= PLANE_WM_EN;
3302
3303 r->plane_trans[pipe][i] = temp;
3304 }
3305
3306 temp = 0;
4969d33e
MR		 3307 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3308 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3309 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3310 temp |= PLANE_WM_EN;
3311
4969d33e 3312 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3313
2d41c0b5
PB		 3314 r->wm_linetime[pipe] = p_wm->linetime;
3315}
3316
16160e3d
DL		 3317static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3318 const struct skl_ddb_entry *entry)
3319{
3320 if (entry->end)
3321 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3322 else
3323 I915_WRITE(reg, 0);
3324}
3325
2d41c0b5
PB		 3326static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3327 const struct skl_wm_values *new)
3328{
3329 struct drm_device *dev = dev_priv->dev;
3330 struct intel_crtc *crtc;
3331
3332 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3333 int i, level, max_level = ilk_wm_max_level(dev);
3334 enum pipe pipe = crtc->pipe;
3335
5d374d96
DL		 3336 if (!new->dirty[pipe])
3337 continue;
8211bd5b 3338
5d374d96 3339 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3340
5d374d96
DL		 3341 for (level = 0; level <= max_level; level++) {
3342 for (i = 0; i < intel_num_planes(crtc); i++)
3343 I915_WRITE(PLANE_WM(pipe, i, level),
3344 new->plane[pipe][i][level]);
3345 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3346 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3347 }
5d374d96
DL		 3348 for (i = 0; i < intel_num_planes(crtc); i++)
3349 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3350 new->plane_trans[pipe][i]);
4969d33e
MR		 3351 I915_WRITE(CUR_WM_TRANS(pipe),
3352 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3353
2cd601c6 3354 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3355 skl_ddb_entry_write(dev_priv,
3356 PLANE_BUF_CFG(pipe, i),
3357 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3358 skl_ddb_entry_write(dev_priv,
3359 PLANE_NV12_BUF_CFG(pipe, i),
3360 &new->ddb.y_plane[pipe][i]);
3361 }
5d374d96
DL		 3362
3363 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3364 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3365 }
2d41c0b5
PB		 3366}
3367
0e8fb7ba
DL		 3368/*
3369 * When setting up a new DDB allocation arrangement, we need to correctly
3370 * sequence the times at which the new allocations for the pipes are taken into
3371 * account or we'll have pipes fetching from space previously allocated to
3372 * another pipe.
3373 *
3374 * Roughly the sequence looks like:
3375 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3376 * overlapping with a previous light-up pipe (another way to put it is:
3377 * pipes with their new allocation strickly included into their old ones).
3378 * 2. re-allocate the other pipes that get their allocation reduced
3379 * 3. allocate the pipes having their allocation increased
3380 *
3381 * Steps 1. and 2. are here to take care of the following case:
3382 * - Initially DDB looks like this:
3383 * | B | C |
3384 * - enable pipe A.
3385 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3386 * allocation
3387 * | A | B | C |
3388 *
3389 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3390 */
3391
d21b795c
DL		 3392static void
3393skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3394{
0e8fb7ba
DL		 3395 int plane;
3396
d21b795c
DL		 3397 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3398
dd740780 3399 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3400 I915_WRITE(PLANE_SURF(pipe, plane),
3401 I915_READ(PLANE_SURF(pipe, plane)));
3402 }
3403 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3404}
3405
3406static bool
3407skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3408 const struct skl_ddb_allocation *new,
3409 enum pipe pipe)
3410{
3411 uint16_t old_size, new_size;
3412
3413 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3414 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3415
3416 return old_size != new_size &&
3417 new->pipe[pipe].start >= old->pipe[pipe].start &&
3418 new->pipe[pipe].end <= old->pipe[pipe].end;
3419}
3420
3421static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3422 struct skl_wm_values *new_values)
3423{
3424 struct drm_device *dev = dev_priv->dev;
3425 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3426 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3427 struct intel_crtc *crtc;
3428 enum pipe pipe;
3429
3430 new_ddb = &new_values->ddb;
3431 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3432
3433 /*
3434 * First pass: flush the pipes with the new allocation contained into
3435 * the old space.
3436 *
3437 * We'll wait for the vblank on those pipes to ensure we can safely
3438 * re-allocate the freed space without this pipe fetching from it.
3439 */
3440 for_each_intel_crtc(dev, crtc) {
3441 if (!crtc->active)
3442 continue;
3443
3444 pipe = crtc->pipe;
3445
3446 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3447 continue;
3448
d21b795c 3449 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3450 intel_wait_for_vblank(dev, pipe);
3451
3452 reallocated[pipe] = true;
3453 }
3454
3455
3456 /*
3457 * Second pass: flush the pipes that are having their allocation
3458 * reduced, but overlapping with a previous allocation.
3459 *
3460 * Here as well we need to wait for the vblank to make sure the freed
3461 * space is not used anymore.
3462 */
3463 for_each_intel_crtc(dev, crtc) {
3464 if (!crtc->active)
3465 continue;
3466
3467 pipe = crtc->pipe;
3468
3469 if (reallocated[pipe])
3470 continue;
3471
3472 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3473 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3474 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3475 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3476 reallocated[pipe] = true;
0e8fb7ba 3477 }
0e8fb7ba
DL		 3478 }
3479
3480 /*
3481 * Third pass: flush the pipes that got more space allocated.
3482 *
3483 * We don't need to actively wait for the update here, next vblank
3484 * will just get more DDB space with the correct WM values.
3485 */
3486 for_each_intel_crtc(dev, crtc) {
3487 if (!crtc->active)
3488 continue;
3489
3490 pipe = crtc->pipe;
3491
3492 /*
3493 * At this point, only the pipes more space than before are
3494 * left to re-allocate.
3495 */
3496 if (reallocated[pipe])
3497 continue;
3498
d21b795c 3499 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3500 }
3501}
3502
2d41c0b5 3503static bool skl_update_pipe_wm(struct drm_crtc *crtc,
261a27d1 3504 struct intel_wm_config *config,
2d41c0b5
PB		 3505 struct skl_ddb_allocation *ddb, /* out */
3506 struct skl_pipe_wm *pipe_wm /* out */)
3507{
3508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3509 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3510
024c9045
MR		 3511 skl_allocate_pipe_ddb(cstate, config, ddb);
3512 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3513
261a27d1 3514 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3515 return false;
3516
261a27d1 3517 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3518
2d41c0b5
PB		 3519 return true;
3520}
3521
3522static void skl_update_other_pipe_wm(struct drm_device *dev,
3523 struct drm_crtc *crtc,
261a27d1 3524 struct intel_wm_config *config,
2d41c0b5
PB		 3525 struct skl_wm_values *r)
3526{
3527 struct intel_crtc *intel_crtc;
3528 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3529
3530 /*
3531 * If the WM update hasn't changed the allocation for this_crtc (the
3532 * crtc we are currently computing the new WM values for), other
3533 * enabled crtcs will keep the same allocation and we don't need to
3534 * recompute anything for them.
3535 */
3536 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3537 return;
3538
3539 /*
3540 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3541 * other active pipes need new DDB allocation and WM values.
3542 */
3543 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3544 base.head) {
2d41c0b5
PB		 3545 struct skl_pipe_wm pipe_wm = {};
3546 bool wm_changed;
3547
3548 if (this_crtc->pipe == intel_crtc->pipe)
3549 continue;
3550
3551 if (!intel_crtc->active)
3552 continue;
3553
024c9045 3554 wm_changed = skl_update_pipe_wm(&intel_crtc->base, config,
2d41c0b5
PB		 3555 &r->ddb, &pipe_wm);
3556
3557 /*
3558 * If we end up re-computing the other pipe WM values, it's
3559 * because it was really needed, so we expect the WM values to
3560 * be different.
3561 */
3562 WARN_ON(!wm_changed);
3563
024c9045 3564 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3565 r->dirty[intel_crtc->pipe] = true;
3566 }
3567}
3568
adda50b8
BP		 3569static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3570{
3571 watermarks->wm_linetime[pipe] = 0;
3572 memset(watermarks->plane[pipe], 0,
3573 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3574 memset(watermarks->plane_trans[pipe],
3575 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3576 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3577
3578 /* Clear ddb entries for pipe */
3579 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3580 memset(&watermarks->ddb.plane[pipe], 0,
3581 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3582 memset(&watermarks->ddb.y_plane[pipe], 0,
3583 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3584 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3585 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3586
3587}
3588
2d41c0b5
PB		 3589static void skl_update_wm(struct drm_crtc *crtc)
3590{
3591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3592 struct drm_device *dev = crtc->dev;
3593 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3594 struct skl_wm_values *results = &dev_priv->wm.skl_results;
261a27d1
MR		 3595 struct skl_pipe_wm pipe_wm = {};
3596 struct intel_wm_config config = {};
2d41c0b5 3597
adda50b8
BP		 3598
3599 /* Clear all dirty flags */
3600 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3601
3602 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3603
261a27d1
MR		 3604 skl_compute_wm_global_parameters(dev, &config);
3605
024c9045 3606 if (!skl_update_pipe_wm(crtc, &config, &results->ddb, &pipe_wm))
2d41c0b5
PB		 3607 return;
3608
024c9045 3609 skl_compute_wm_results(dev, &pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3610 results->dirty[intel_crtc->pipe] = true;
3611
261a27d1 3612 skl_update_other_pipe_wm(dev, crtc, &config, results);
2d41c0b5 3613 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3614 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3615
3616 /* store the new configuration */
3617 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3618}
3619
b9d5c839 3620static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3621{
b9d5c839
VS		 3622 struct drm_device *dev = dev_priv->dev;
3623 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3624 struct ilk_wm_maximums max;
b9d5c839 3625 struct intel_wm_config config = {};
820c1980 3626 struct ilk_wm_values results = {};
77c122bc 3627 enum intel_ddb_partitioning partitioning;
261a27d1
MR		 3628
3629 ilk_compute_wm_config(dev, &config);
3630
3631 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3632 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3633
3634 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3635 if (INTEL_INFO(dev)->gen >= 7 &&
261a27d1
MR		 3636 config.num_pipes_active == 1 && config.sprites_enabled) {
3637 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3638 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3639
820c1980 3640 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3641 } else {
198a1e9b 3642 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3643 }
3644
198a1e9b 3645 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3646 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3647
820c1980 3648 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3649
820c1980 3650 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3651}
3652
b9d5c839
VS		 3653static void ilk_update_wm(struct drm_crtc *crtc)
3654{
3655 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3658 struct intel_pipe_wm pipe_wm = {};
3659
3660 WARN_ON(cstate->base.active != intel_crtc->active);
3661
3662 /*
3663 * IVB workaround: must disable low power watermarks for at least
3664 * one frame before enabling scaling. LP watermarks can be re-enabled
3665 * when scaling is disabled.
3666 *
3667 * WaCxSRDisabledForSpriteScaling:ivb
3668 */
3669 if (cstate->disable_lp_wm) {
3670 ilk_disable_lp_wm(crtc->dev);
3671 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3672 }
3673
3674 intel_compute_pipe_wm(cstate, &pipe_wm);
3675
3676 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3677 return;
3678
3679 intel_crtc->wm.active = pipe_wm;
3680
3681 ilk_program_watermarks(dev_priv);
3682}
3683
3078999f
PB		 3684static void skl_pipe_wm_active_state(uint32_t val,
3685 struct skl_pipe_wm *active,
3686 bool is_transwm,
3687 bool is_cursor,
3688 int i,
3689 int level)
3690{
3691 bool is_enabled = (val & PLANE_WM_EN) != 0;
3692
3693 if (!is_transwm) {
3694 if (!is_cursor) {
3695 active->wm[level].plane_en[i] = is_enabled;
3696 active->wm[level].plane_res_b[i] =
3697 val & PLANE_WM_BLOCKS_MASK;
3698 active->wm[level].plane_res_l[i] =
3699 (val >> PLANE_WM_LINES_SHIFT) &
3700 PLANE_WM_LINES_MASK;
3701 } else {
4969d33e
MR		 3702 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3703 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3704 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3705 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3706 (val >> PLANE_WM_LINES_SHIFT) &
3707 PLANE_WM_LINES_MASK;
3708 }
3709 } else {
3710 if (!is_cursor) {
3711 active->trans_wm.plane_en[i] = is_enabled;
3712 active->trans_wm.plane_res_b[i] =
3713 val & PLANE_WM_BLOCKS_MASK;
3714 active->trans_wm.plane_res_l[i] =
3715 (val >> PLANE_WM_LINES_SHIFT) &
3716 PLANE_WM_LINES_MASK;
3717 } else {
4969d33e
MR		 3718 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3719 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3720 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3721 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3722 (val >> PLANE_WM_LINES_SHIFT) &
3723 PLANE_WM_LINES_MASK;
3724 }
3725 }
3726}
3727
3728static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3729{
3730 struct drm_device *dev = crtc->dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
261a27d1 3734 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3078999f
PB		 3735 enum pipe pipe = intel_crtc->pipe;
3736 int level, i, max_level;
3737 uint32_t temp;
3738
3739 max_level = ilk_wm_max_level(dev);
3740
3741 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3742
3743 for (level = 0; level <= max_level; level++) {
3744 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3745 hw->plane[pipe][i][level] =
3746 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3747 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3748 }
3749
3750 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3751 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3752 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3753
3ef00284 3754 if (!intel_crtc->active)
3078999f
PB		 3755 return;
3756
3757 hw->dirty[pipe] = true;
3758
3759 active->linetime = hw->wm_linetime[pipe];
3760
3761 for (level = 0; level <= max_level; level++) {
3762 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3763 temp = hw->plane[pipe][i][level];
3764 skl_pipe_wm_active_state(temp, active, false,
3765 false, i, level);
3766 }
4969d33e 3767 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3768 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3769 }
3770
3771 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3772 temp = hw->plane_trans[pipe][i];
3773 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3774 }
3775
4969d33e 3776 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f
PB		 3777 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3778}
3779
3780void skl_wm_get_hw_state(struct drm_device *dev)
3781{
a269c583
DL		 3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3784 struct drm_crtc *crtc;
3785
a269c583 3786 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3787 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3788 skl_pipe_wm_get_hw_state(crtc);
3789}
3790
243e6a44
VS		 3791static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3792{
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3795 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
261a27d1 3797 struct intel_pipe_wm *active = &intel_crtc->wm.active;
243e6a44
VS		 3798 enum pipe pipe = intel_crtc->pipe;
3799 static const unsigned int wm0_pipe_reg[] = {
3800 [PIPE_A] = WM0_PIPEA_ILK,
3801 [PIPE_B] = WM0_PIPEB_ILK,
3802 [PIPE_C] = WM0_PIPEC_IVB,
3803 };
3804
3805 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3806 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3807 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3808
3ef00284 3809 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3810
3811 if (active->pipe_enabled) {
243e6a44
VS		 3812 u32 tmp = hw->wm_pipe[pipe];
3813
3814 /*
3815 * For active pipes LP0 watermark is marked as
3816 * enabled, and LP1+ watermaks as disabled since
3817 * we can't really reverse compute them in case
3818 * multiple pipes are active.
3819 */
3820 active->wm[0].enable = true;
3821 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3822 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3823 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3824 active->linetime = hw->wm_linetime[pipe];
3825 } else {
3826 int level, max_level = ilk_wm_max_level(dev);
3827
3828 /*
3829 * For inactive pipes, all watermark levels
3830 * should be marked as enabled but zeroed,
3831 * which is what we'd compute them to.
3832 */
3833 for (level = 0; level <= max_level; level++)
3834 active->wm[level].enable = true;
3835 }
3836}
3837
6eb1a681
VS		 3838#define _FW_WM(value, plane) \
3839 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3840#define _FW_WM_VLV(value, plane) \
3841 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3842
3843static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3844 struct vlv_wm_values *wm)
3845{
3846 enum pipe pipe;
3847 uint32_t tmp;
3848
3849 for_each_pipe(dev_priv, pipe) {
3850 tmp = I915_READ(VLV_DDL(pipe));
3851
3852 wm->ddl[pipe].primary =
3853 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3854 wm->ddl[pipe].cursor =
3855 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3856 wm->ddl[pipe].sprite[0] =
3857 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3858 wm->ddl[pipe].sprite[1] =
3859 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3860 }
3861
3862 tmp = I915_READ(DSPFW1);
3863 wm->sr.plane = _FW_WM(tmp, SR);
3864 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3865 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3866 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3867
3868 tmp = I915_READ(DSPFW2);
3869 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3870 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3871 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3872
3873 tmp = I915_READ(DSPFW3);
3874 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3875
3876 if (IS_CHERRYVIEW(dev_priv)) {
3877 tmp = I915_READ(DSPFW7_CHV);
3878 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3879 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3880
3881 tmp = I915_READ(DSPFW8_CHV);
3882 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3883 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3884
3885 tmp = I915_READ(DSPFW9_CHV);
3886 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3887 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3888
3889 tmp = I915_READ(DSPHOWM);
3890 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3891 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3892 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3893 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3894 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3895 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3896 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3897 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3898 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3899 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3900 } else {
3901 tmp = I915_READ(DSPFW7);
3902 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3903 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3904
3905 tmp = I915_READ(DSPHOWM);
3906 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3907 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3908 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3909 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3910 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3911 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3912 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3913 }
3914}
3915
3916#undef _FW_WM
3917#undef _FW_WM_VLV
3918
3919void vlv_wm_get_hw_state(struct drm_device *dev)
3920{
3921 struct drm_i915_private *dev_priv = to_i915(dev);
3922 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3923 struct intel_plane *plane;
3924 enum pipe pipe;
3925 u32 val;
3926
3927 vlv_read_wm_values(dev_priv, wm);
3928
3929 for_each_intel_plane(dev, plane) {
3930 switch (plane->base.type) {
3931 int sprite;
3932 case DRM_PLANE_TYPE_CURSOR:
3933 plane->wm.fifo_size = 63;
3934 break;
3935 case DRM_PLANE_TYPE_PRIMARY:
3936 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3937 break;
3938 case DRM_PLANE_TYPE_OVERLAY:
3939 sprite = plane->plane;
3940 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3941 break;
3942 }
3943 }
3944
3945 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3946 wm->level = VLV_WM_LEVEL_PM2;
3947
3948 if (IS_CHERRYVIEW(dev_priv)) {
3949 mutex_lock(&dev_priv->rps.hw_lock);
3950
3951 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3952 if (val & DSP_MAXFIFO_PM5_ENABLE)
3953 wm->level = VLV_WM_LEVEL_PM5;
3954
58590c14
VS		 3955 /*
3956 * If DDR DVFS is disabled in the BIOS, Punit
3957 * will never ack the request. So if that happens
3958 * assume we don't have to enable/disable DDR DVFS
3959 * dynamically. To test that just set the REQ_ACK
3960 * bit to poke the Punit, but don't change the
3961 * HIGH/LOW bits so that we don't actually change
3962 * the current state.
3963 */
6eb1a681 3964 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3965 val |= FORCE_DDR_FREQ_REQ_ACK;
3966 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3967
3968 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3969 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3970 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3971 "assuming DDR DVFS is disabled\n");
3972 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3973 } else {
3974 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3975 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3976 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3977 }
6eb1a681
VS		 3978
3979 mutex_unlock(&dev_priv->rps.hw_lock);
3980 }
3981
3982 for_each_pipe(dev_priv, pipe)
3983 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3984 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
3985 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
3986
3987 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3988 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3989}
3990
243e6a44
VS		 3991void ilk_wm_get_hw_state(struct drm_device *dev)
3992{
3993 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3994 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3995 struct drm_crtc *crtc;
3996
70e1e0ec 3997 for_each_crtc(dev, crtc)
243e6a44
VS		 3998 ilk_pipe_wm_get_hw_state(crtc);
3999
4000 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4001 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4002 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4003
4004 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4005 if (INTEL_INFO(dev)->gen >= 7) {
4006 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4007 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4008 }
243e6a44 4009
a42a5719 4010 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4011 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4012 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4013 else if (IS_IVYBRIDGE(dev))
4014 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4015 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4016
4017 hw->enable_fbc_wm =
4018 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4019}
4020
b445e3b0
ED		 4021/**
4022 * intel_update_watermarks - update FIFO watermark values based on current modes
4023 *
4024 * Calculate watermark values for the various WM regs based on current mode
4025 * and plane configuration.
4026 *
4027 * There are several cases to deal with here:
4028 * - normal (i.e. non-self-refresh)
4029 * - self-refresh (SR) mode
4030 * - lines are large relative to FIFO size (buffer can hold up to 2)
4031 * - lines are small relative to FIFO size (buffer can hold more than 2
4032 * lines), so need to account for TLB latency
4033 *
4034 * The normal calculation is:
4035 * watermark = dotclock * bytes per pixel * latency
4036 * where latency is platform & configuration dependent (we assume pessimal
4037 * values here).
4038 *
4039 * The SR calculation is:
4040 * watermark = (trunc(latency/line time)+1) * surface width *
4041 * bytes per pixel
4042 * where
4043 * line time = htotal / dotclock
4044 * surface width = hdisplay for normal plane and 64 for cursor
4045 * and latency is assumed to be high, as above.
4046 *
4047 * The final value programmed to the register should always be rounded up,
4048 * and include an extra 2 entries to account for clock crossings.
4049 *
4050 * We don't use the sprite, so we can ignore that. And on Crestline we have
4051 * to set the non-SR watermarks to 8.
4052 */
46ba614c 4053void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4054{
46ba614c 4055 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4056
4057 if (dev_priv->display.update_wm)
46ba614c 4058 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4059}
4060
9270388e
DV		 4061/**
4062 * Lock protecting IPS related data structures
9270388e
DV		 4063 */
4064DEFINE_SPINLOCK(mchdev_lock);
4065
4066/* Global for IPS driver to get at the current i915 device. Protected by
4067 * mchdev_lock. */
4068static struct drm_i915_private *i915_mch_dev;
4069
2b4e57bd
ED		 4070bool ironlake_set_drps(struct drm_device *dev, u8 val)
4071{
4072 struct drm_i915_private *dev_priv = dev->dev_private;
4073 u16 rgvswctl;
4074
9270388e
DV		 4075 assert_spin_locked(&mchdev_lock);
4076
2b4e57bd
ED		 4077 rgvswctl = I915_READ16(MEMSWCTL);
4078 if (rgvswctl & MEMCTL_CMD_STS) {
4079 DRM_DEBUG("gpu busy, RCS change rejected\n");
4080 return false; /* still busy with another command */
4081 }
4082
4083 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4084 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4085 I915_WRITE16(MEMSWCTL, rgvswctl);
4086 POSTING_READ16(MEMSWCTL);
4087
4088 rgvswctl |= MEMCTL_CMD_STS;
4089 I915_WRITE16(MEMSWCTL, rgvswctl);
4090
4091 return true;
4092}
4093
8090c6b9 4094static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4095{
4096 struct drm_i915_private *dev_priv = dev->dev_private;
4097 u32 rgvmodectl = I915_READ(MEMMODECTL);
4098 u8 fmax, fmin, fstart, vstart;
4099
9270388e
DV		 4100 spin_lock_irq(&mchdev_lock);
4101
2b4e57bd
ED		 4102 /* Enable temp reporting */
4103 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4104 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4105
4106 /* 100ms RC evaluation intervals */
4107 I915_WRITE(RCUPEI, 100000);
4108 I915_WRITE(RCDNEI, 100000);
4109
4110 /* Set max/min thresholds to 90ms and 80ms respectively */
4111 I915_WRITE(RCBMAXAVG, 90000);
4112 I915_WRITE(RCBMINAVG, 80000);
4113
4114 I915_WRITE(MEMIHYST, 1);
4115
4116 /* Set up min, max, and cur for interrupt handling */
4117 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4118 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4119 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4120 MEMMODE_FSTART_SHIFT;
4121
616847e7 4122 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4123 PXVFREQ_PX_SHIFT;
4124
20e4d407
DV		 4125 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4126 dev_priv->ips.fstart = fstart;
2b4e57bd 4127
20e4d407
DV		 4128 dev_priv->ips.max_delay = fstart;
4129 dev_priv->ips.min_delay = fmin;
4130 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4131
4132 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4133 fmax, fmin, fstart);
4134
4135 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4136
4137 /*
4138 * Interrupts will be enabled in ironlake_irq_postinstall
4139 */
4140
4141 I915_WRITE(VIDSTART, vstart);
4142 POSTING_READ(VIDSTART);
4143
4144 rgvmodectl |= MEMMODE_SWMODE_EN;
4145 I915_WRITE(MEMMODECTL, rgvmodectl);
4146
9270388e 4147 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4148 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4149 mdelay(1);
2b4e57bd
ED		 4150
4151 ironlake_set_drps(dev, fstart);
4152
7d81c3e0
VS		 4153 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4154 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4155 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4156 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4157 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4158
4159 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4160}
4161
8090c6b9 4162static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4163{
4164 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4165 u16 rgvswctl;
4166
4167 spin_lock_irq(&mchdev_lock);
4168
4169 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4170
4171 /* Ack interrupts, disable EFC interrupt */
4172 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4173 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4174 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4175 I915_WRITE(DEIIR, DE_PCU_EVENT);
4176 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4177
4178 /* Go back to the starting frequency */
20e4d407 4179 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4180 mdelay(1);
2b4e57bd
ED		 4181 rgvswctl |= MEMCTL_CMD_STS;
4182 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4183 mdelay(1);
2b4e57bd 4184
9270388e 4185 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4186}
4187
acbe9475
DV		 4188/* There's a funny hw issue where the hw returns all 0 when reading from
4189 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4190 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4191 * all limits and the gpu stuck at whatever frequency it is at atm).
4192 */
74ef1173 4193static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4194{
7b9e0ae6 4195 u32 limits;
2b4e57bd 4196
20b46e59
DV		 4197 /* Only set the down limit when we've reached the lowest level to avoid
4198 * getting more interrupts, otherwise leave this clear. This prevents a
4199 * race in the hw when coming out of rc6: There's a tiny window where
4200 * the hw runs at the minimal clock before selecting the desired
4201 * frequency, if the down threshold expires in that window we will not
4202 * receive a down interrupt. */
74ef1173
AG		 4203 if (IS_GEN9(dev_priv->dev)) {
4204 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4205 if (val <= dev_priv->rps.min_freq_softlimit)
4206 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4207 } else {
4208 limits = dev_priv->rps.max_freq_softlimit << 24;
4209 if (val <= dev_priv->rps.min_freq_softlimit)
4210 limits |= dev_priv->rps.min_freq_softlimit << 16;
4211 }
20b46e59
DV		 4212
4213 return limits;
4214}
4215
dd75fdc8
CW		 4216static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4217{
4218 int new_power;
8a586437
AG		 4219 u32 threshold_up = 0, threshold_down = 0; /* in % */
4220 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4221
4222 new_power = dev_priv->rps.power;
4223 switch (dev_priv->rps.power) {
4224 case LOW_POWER:
b39fb297 4225 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4226 new_power = BETWEEN;
4227 break;
4228
4229 case BETWEEN:
b39fb297 4230 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4231 new_power = LOW_POWER;
b39fb297 4232 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4233 new_power = HIGH_POWER;
4234 break;
4235
4236 case HIGH_POWER:
b39fb297 4237 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4238 new_power = BETWEEN;
4239 break;
4240 }
4241 /* Max/min bins are special */
aed242ff 4242 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4243 new_power = LOW_POWER;
aed242ff 4244 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4245 new_power = HIGH_POWER;
4246 if (new_power == dev_priv->rps.power)
4247 return;
4248
4249 /* Note the units here are not exactly 1us, but 1280ns. */
4250 switch (new_power) {
4251 case LOW_POWER:
4252 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4253 ei_up = 16000;
4254 threshold_up = 95;
dd75fdc8
CW		 4255
4256 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4257 ei_down = 32000;
4258 threshold_down = 85;
dd75fdc8
CW		 4259 break;
4260
4261 case BETWEEN:
4262 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4263 ei_up = 13000;
4264 threshold_up = 90;
dd75fdc8
CW		 4265
4266 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4267 ei_down = 32000;
4268 threshold_down = 75;
dd75fdc8
CW		 4269 break;
4270
4271 case HIGH_POWER:
4272 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4273 ei_up = 10000;
4274 threshold_up = 85;
dd75fdc8
CW		 4275
4276 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4277 ei_down = 32000;
4278 threshold_down = 60;
dd75fdc8
CW		 4279 break;
4280 }
4281
8a586437
AG		 4282 I915_WRITE(GEN6_RP_UP_EI,
4283 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4284 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4285 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4286
4287 I915_WRITE(GEN6_RP_DOWN_EI,
4288 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4289 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4290 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4291
4292 I915_WRITE(GEN6_RP_CONTROL,
4293 GEN6_RP_MEDIA_TURBO |
4294 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4295 GEN6_RP_MEDIA_IS_GFX |
4296 GEN6_RP_ENABLE |
4297 GEN6_RP_UP_BUSY_AVG |
4298 GEN6_RP_DOWN_IDLE_AVG);
4299
dd75fdc8 4300 dev_priv->rps.power = new_power;
8fb55197
CW		 4301 dev_priv->rps.up_threshold = threshold_up;
4302 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4303 dev_priv->rps.last_adj = 0;
4304}
4305
2876ce73
CW		 4306static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4307{
4308 u32 mask = 0;
4309
4310 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4311 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4312 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4313 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4314
7b3c29f6
CW		 4315 mask &= dev_priv->pm_rps_events;
4316
59d02a1f 4317 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4318}
4319
b8a5ff8d
JM		 4320/* gen6_set_rps is called to update the frequency request, but should also be
4321 * called when the range (min_delay and max_delay) is modified so that we can
4322 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4323static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4324{
4325 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4326
23eafea6 4327 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4328 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4329 return;
4330
4fc688ce 4331 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4332 WARN_ON(val > dev_priv->rps.max_freq);
4333 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4334
eb64cad1
CW		 4335 /* min/max delay may still have been modified so be sure to
4336 * write the limits value.
4337 */
4338 if (val != dev_priv->rps.cur_freq) {
4339 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4340
5704195c
AG		 4341 if (IS_GEN9(dev))
4342 I915_WRITE(GEN6_RPNSWREQ,
4343 GEN9_FREQUENCY(val));
4344 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4345 I915_WRITE(GEN6_RPNSWREQ,
4346 HSW_FREQUENCY(val));
4347 else
4348 I915_WRITE(GEN6_RPNSWREQ,
4349 GEN6_FREQUENCY(val) |
4350 GEN6_OFFSET(0) |
4351 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4352 }
7b9e0ae6 4353
7b9e0ae6
CW		 4354 /* Make sure we continue to get interrupts
4355 * until we hit the minimum or maximum frequencies.
4356 */
74ef1173 4357 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4358 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4359
d5570a72
BW		 4360 POSTING_READ(GEN6_RPNSWREQ);
4361
b39fb297 4362 dev_priv->rps.cur_freq = val;
be2cde9a 4363 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4364}
4365
ffe02b40
VS		 4366static void valleyview_set_rps(struct drm_device *dev, u8 val)
4367{
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369
4370 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4371 WARN_ON(val > dev_priv->rps.max_freq);
4372 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4373
4374 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4375 "Odd GPU freq value\n"))
4376 val &= ~1;
4377
cd25dd5b
D		 4378 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4379
8fb55197 4380 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4381 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4382 if (!IS_CHERRYVIEW(dev_priv))
4383 gen6_set_rps_thresholds(dev_priv, val);
4384 }
ffe02b40 4385
ffe02b40
VS		 4386 dev_priv->rps.cur_freq = val;
4387 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4388}
4389
a7f6e231 4390/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4391 *
4392 * * If Gfx is Idle, then
a7f6e231
D		 4393 * 1. Forcewake Media well.
4394 * 2. Request idle freq.
4395 * 3. Release Forcewake of Media well.
76c3552f
D		 4396*/
4397static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4398{
aed242ff 4399 u32 val = dev_priv->rps.idle_freq;
5549d25f 4400
aed242ff 4401 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4402 return;
4403
a7f6e231
D		 4404 /* Wake up the media well, as that takes a lot less
4405 * power than the Render well. */
4406 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4407 valleyview_set_rps(dev_priv->dev, val);
4408 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4409}
4410
43cf3bf0
CW		 4411void gen6_rps_busy(struct drm_i915_private *dev_priv)
4412{
4413 mutex_lock(&dev_priv->rps.hw_lock);
4414 if (dev_priv->rps.enabled) {
4415 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4416 gen6_rps_reset_ei(dev_priv);
4417 I915_WRITE(GEN6_PMINTRMSK,
4418 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4419 }
4420 mutex_unlock(&dev_priv->rps.hw_lock);
4421}
4422
b29c19b6
CW		 4423void gen6_rps_idle(struct drm_i915_private *dev_priv)
4424{
691bb717
DL		 4425 struct drm_device *dev = dev_priv->dev;
4426
b29c19b6 4427 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4428 if (dev_priv->rps.enabled) {
21a11fff 4429 if (IS_VALLEYVIEW(dev))
76c3552f 4430 vlv_set_rps_idle(dev_priv);
7526ed79 4431 else
aed242ff 4432 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4433 dev_priv->rps.last_adj = 0;
43cf3bf0 4434 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4435 }
8d3afd7d 4436 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4437
8d3afd7d 4438 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4439 while (!list_empty(&dev_priv->rps.clients))
4440 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4441 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4442}
4443
1854d5ca 4444void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4445 struct intel_rps_client *rps,
4446 unsigned long submitted)
b29c19b6 4447{
8d3afd7d
CW		 4448 /* This is intentionally racy! We peek at the state here, then
4449 * validate inside the RPS worker.
4450 */
4451 if (!(dev_priv->mm.busy &&
4452 dev_priv->rps.enabled &&
4453 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4454 return;
43cf3bf0 4455
e61b9958
CW		 4456 /* Force a RPS boost (and don't count it against the client) if
4457 * the GPU is severely congested.
4458 */
d0bc54f2 4459 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4460 rps = NULL;
4461
8d3afd7d
CW		 4462 spin_lock(&dev_priv->rps.client_lock);
4463 if (rps == NULL || list_empty(&rps->link)) {
4464 spin_lock_irq(&dev_priv->irq_lock);
4465 if (dev_priv->rps.interrupts_enabled) {
4466 dev_priv->rps.client_boost = true;
4467 queue_work(dev_priv->wq, &dev_priv->rps.work);
4468 }
4469 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4470
2e1b8730
CW		 4471 if (rps != NULL) {
4472 list_add(&rps->link, &dev_priv->rps.clients);
4473 rps->boosts++;
1854d5ca
CW		 4474 } else
4475 dev_priv->rps.boosts++;
c0951f0c 4476 }
8d3afd7d 4477 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4478}
4479
ffe02b40 4480void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4481{
ffe02b40
VS		 4482 if (IS_VALLEYVIEW(dev))
4483 valleyview_set_rps(dev, val);
4484 else
4485 gen6_set_rps(dev, val);
0a073b84
JB		 4486}
4487
20e49366
ZW		 4488static void gen9_disable_rps(struct drm_device *dev)
4489{
4490 struct drm_i915_private *dev_priv = dev->dev_private;
4491
4492 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4493 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4494}
4495
44fc7d5c 4496static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4497{
4498 struct drm_i915_private *dev_priv = dev->dev_private;
4499
4500 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4501 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4502}
4503
38807746
D		 4504static void cherryview_disable_rps(struct drm_device *dev)
4505{
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507
4508 I915_WRITE(GEN6_RC_CONTROL, 0);
4509}
4510
44fc7d5c
DV		 4511static void valleyview_disable_rps(struct drm_device *dev)
4512{
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514
98a2e5f9
D		 4515 /* we're doing forcewake before Disabling RC6,
4516 * This what the BIOS expects when going into suspend */
59bad947 4517 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4518
44fc7d5c 4519 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4520
59bad947 4521 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4522}
4523
dc39fff7
BW		 4524static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4525{
91ca689a
ID		 4526 if (IS_VALLEYVIEW(dev)) {
4527 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4528 mode = GEN6_RC_CTL_RC6_ENABLE;
4529 else
4530 mode = 0;
4531 }
58abf1da
RV		 4532 if (HAS_RC6p(dev))
4533 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4534 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4535 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4536 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4537
4538 else
4539 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4540 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4541}
4542
e6069ca8 4543static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4544{
e7d66d89
DV		 4545 /* No RC6 before Ironlake and code is gone for ilk. */
4546 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4547 return 0;
4548
456470eb 4549 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4550 if (enable_rc6 >= 0) {
4551 int mask;
4552
58abf1da 4553 if (HAS_RC6p(dev))
e6069ca8
ID		 4554 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4555 INTEL_RC6pp_ENABLE;
4556 else
4557 mask = INTEL_RC6_ENABLE;
4558
4559 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4560 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4561 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4562
4563 return enable_rc6 & mask;
4564 }
2b4e57bd 4565
8bade1ad 4566 if (IS_IVYBRIDGE(dev))
cca84a1f 4567 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4568
4569 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4570}
4571
e6069ca8
ID		 4572int intel_enable_rc6(const struct drm_device *dev)
4573{
4574 return i915.enable_rc6;
4575}
4576
93ee2920 4577static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4578{
93ee2920
TR		 4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580 uint32_t rp_state_cap;
4581 u32 ddcc_status = 0;
4582 int ret;
4583
3280e8b0
BW		 4584 /* All of these values are in units of 50MHz */
4585 dev_priv->rps.cur_freq = 0;
93ee2920 4586 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4587 if (IS_BROXTON(dev)) {
4588 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4589 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4590 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4591 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4592 } else {
4593 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4594 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4595 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4596 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4597 }
4598
3280e8b0
BW		 4599 /* hw_max = RP0 until we check for overclocking */
4600 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4601
93ee2920 4602 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4603 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4604 ret = sandybridge_pcode_read(dev_priv,
4605 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4606 &ddcc_status);
4607 if (0 == ret)
4608 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4609 clamp_t(u8,
4610 ((ddcc_status >> 8) & 0xff),
4611 dev_priv->rps.min_freq,
4612 dev_priv->rps.max_freq);
93ee2920
TR		 4613 }
4614
c5e0688c
AG		 4615 if (IS_SKYLAKE(dev)) {
4616 /* Store the frequency values in 16.66 MHZ units, which is
4617 the natural hardware unit for SKL */
4618 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4619 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4620 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4621 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4622 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4623 }
4624
aed242ff
CW		 4625 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4626
3280e8b0
BW		 4627 /* Preserve min/max settings in case of re-init */
4628 if (dev_priv->rps.max_freq_softlimit == 0)
4629 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4630
93ee2920
TR		 4631 if (dev_priv->rps.min_freq_softlimit == 0) {
4632 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4633 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4634 max_t(int, dev_priv->rps.efficient_freq,
4635 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4636 else
4637 dev_priv->rps.min_freq_softlimit =
4638 dev_priv->rps.min_freq;
4639 }
3280e8b0
BW		 4640}
4641
b6fef0ef 4642/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4643static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4644{
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646
4647 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4648
ba1c554c
DL		 4649 gen6_init_rps_frequencies(dev);
4650
23eafea6 4651 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4652 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4653 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4654 return;
4655 }
4656
0beb059a
AG		 4657 /* Program defaults and thresholds for RPS*/
4658 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4659 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4660
4661 /* 1 second timeout*/
4662 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4663 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4664
b6fef0ef 4665 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4666
0beb059a
AG		 4667 /* Leaning on the below call to gen6_set_rps to program/setup the
4668 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4669 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4670 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4671 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4672
4673 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4674}
4675
4676static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4677{
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679 struct intel_engine_cs *ring;
4680 uint32_t rc6_mask = 0;
4681 int unused;
4682
4683 /* 1a: Software RC state - RC0 */
4684 I915_WRITE(GEN6_RC_STATE, 0);
4685
4686 /* 1b: Get forcewake during program sequence. Although the driver
4687 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4688 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4689
4690 /* 2a: Disable RC states. */
4691 I915_WRITE(GEN6_RC_CONTROL, 0);
4692
4693 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4694
4695 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4696 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
e87a005d 4697 IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
63a4dec2
SAK		 4698 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4699 else
4700 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4701 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4702 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4703 for_each_ring(ring, dev_priv, unused)
4704 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4705
4706 if (HAS_GUC_UCODE(dev))
4707 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4708
20e49366 4709 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4710
38c23527
ZW		 4711 /* 2c: Program Coarse Power Gating Policies. */
4712 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4713 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4714
20e49366
ZW		 4715 /* 3a: Enable RC6 */
4716 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4717 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4718 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4719 "on" : "off");
3e7732a0 4720 /* WaRsUseTimeoutMode */
e87a005d
JN		 4721 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4722 IS_BXT_REVID(dev, 0, BXT_REVID_A0)) {
3e7732a0 4723 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4724 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4725 GEN7_RC_CTL_TO_MODE |
4726 rc6_mask);
3e7732a0
SAK		 4727 } else {
4728 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4729 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4730 GEN6_RC_CTL_EI_MODE(1) |
4731 rc6_mask);
3e7732a0 4732 }
20e49366 4733
cb07bae0
SK		 4734 /*
4735 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4736 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4737 */
e87a005d
JN		 4738 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
4739 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4740 IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
f2d2fe95
SAK		 4741 I915_WRITE(GEN9_PG_ENABLE, 0);
4742 else
4743 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4744 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4745
59bad947 4746 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4747
4748}
4749
6edee7f3
BW		 4750static void gen8_enable_rps(struct drm_device *dev)
4751{
4752 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4753 struct intel_engine_cs *ring;
93ee2920 4754 uint32_t rc6_mask = 0;
6edee7f3
BW		 4755 int unused;
4756
4757 /* 1a: Software RC state - RC0 */
4758 I915_WRITE(GEN6_RC_STATE, 0);
4759
4760 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4761 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4762 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4763
4764 /* 2a: Disable RC states. */
4765 I915_WRITE(GEN6_RC_CONTROL, 0);
4766
93ee2920
TR		 4767 /* Initialize rps frequencies */
4768 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4769
4770 /* 2b: Program RC6 thresholds.*/
4771 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4772 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4773 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4774 for_each_ring(ring, dev_priv, unused)
4775 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4776 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4777 if (IS_BROADWELL(dev))
4778 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4779 else
4780 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4781
4782 /* 3: Enable RC6 */
4783 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4784 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4785 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4786 if (IS_BROADWELL(dev))
4787 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4788 GEN7_RC_CTL_TO_MODE |
4789 rc6_mask);
4790 else
4791 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4792 GEN6_RC_CTL_EI_MODE(1) |
4793 rc6_mask);
6edee7f3
BW		 4794
4795 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4796 I915_WRITE(GEN6_RPNSWREQ,
4797 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4798 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4799 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4800 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4801 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4802
4803 /* Docs recommend 900MHz, and 300 MHz respectively */
4804 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4805 dev_priv->rps.max_freq_softlimit << 24 |
4806 dev_priv->rps.min_freq_softlimit << 16);
4807
4808 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4809 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4810 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4811 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4812
4813 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4814
4815 /* 5: Enable RPS */
7526ed79
DV		 4816 I915_WRITE(GEN6_RP_CONTROL,
4817 GEN6_RP_MEDIA_TURBO |
4818 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4819 GEN6_RP_MEDIA_IS_GFX |
4820 GEN6_RP_ENABLE |
4821 GEN6_RP_UP_BUSY_AVG |
4822 GEN6_RP_DOWN_IDLE_AVG);
4823
4824 /* 6: Ring frequency + overclocking (our driver does this later */
4825
c7f3153a 4826 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4827 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4828
59bad947 4829 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4830}
4831
79f5b2c7 4832static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4833{
79f5b2c7 4834 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4835 struct intel_engine_cs *ring;
d060c169 4836 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4837 u32 gtfifodbg;
2b4e57bd 4838 int rc6_mode;
42c0526c 4839 int i, ret;
2b4e57bd 4840
4fc688ce 4841 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4842
2b4e57bd
ED		 4843 /* Here begins a magic sequence of register writes to enable
4844 * auto-downclocking.
4845 *
4846 * Perhaps there might be some value in exposing these to
4847 * userspace...
4848 */
4849 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4850
4851 /* Clear the DBG now so we don't confuse earlier errors */
4852 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4853 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4854 I915_WRITE(GTFIFODBG, gtfifodbg);
4855 }
4856
59bad947 4857 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4858
93ee2920
TR		 4859 /* Initialize rps frequencies */
4860 gen6_init_rps_frequencies(dev);
dd0a1aa1 4861
2b4e57bd
ED		 4862 /* disable the counters and set deterministic thresholds */
4863 I915_WRITE(GEN6_RC_CONTROL, 0);
4864
4865 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4866 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4867 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4868 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4869 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4870
b4519513
CW		 4871 for_each_ring(ring, dev_priv, i)
4872 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4873
4874 I915_WRITE(GEN6_RC_SLEEP, 0);
4875 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4876 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4877 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4878 else
4879 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4880 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4881 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4882
5a7dc92a 4883 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4884 rc6_mode = intel_enable_rc6(dev_priv->dev);
4885 if (rc6_mode & INTEL_RC6_ENABLE)
4886 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4887
5a7dc92a
ED		 4888 /* We don't use those on Haswell */
4889 if (!IS_HASWELL(dev)) {
4890 if (rc6_mode & INTEL_RC6p_ENABLE)
4891 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4892
5a7dc92a
ED		 4893 if (rc6_mode & INTEL_RC6pp_ENABLE)
4894 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4895 }
2b4e57bd 4896
dc39fff7 4897 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4898
4899 I915_WRITE(GEN6_RC_CONTROL,
4900 rc6_mask |
4901 GEN6_RC_CTL_EI_MODE(1) |
4902 GEN6_RC_CTL_HW_ENABLE);
4903
dd75fdc8
CW		 4904 /* Power down if completely idle for over 50ms */
4905 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4906 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4907
42c0526c 4908 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4909 if (ret)
42c0526c 4910 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4911
4912 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4913 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4914 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4915 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4916 (pcu_mbox & 0xff) * 50);
b39fb297 4917 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4918 }
4919
dd75fdc8 4920 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4921 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4922
31643d54
BW		 4923 rc6vids = 0;
4924 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4925 if (IS_GEN6(dev) && ret) {
4926 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4927 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4928 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4929 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4930 rc6vids &= 0xffff00;
4931 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4932 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4933 if (ret)
4934 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4935 }
4936
59bad947 4937 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4938}
4939
c2bc2fc5 4940static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4941{
79f5b2c7 4942 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4943 int min_freq = 15;
3ebecd07
CW		 4944 unsigned int gpu_freq;
4945 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 4946 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 4947 int scaling_factor = 180;
eda79642 4948 struct cpufreq_policy *policy;
2b4e57bd 4949
4fc688ce 4950 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4951
eda79642
BW		 4952 policy = cpufreq_cpu_get(0);
4953 if (policy) {
4954 max_ia_freq = policy->cpuinfo.max_freq;
4955 cpufreq_cpu_put(policy);
4956 } else {
4957 /*
4958 * Default to measured freq if none found, PCU will ensure we
4959 * don't go over
4960 */
2b4e57bd 4961 max_ia_freq = tsc_khz;
eda79642 4962 }
2b4e57bd
ED		 4963
4964 /* Convert from kHz to MHz */
4965 max_ia_freq /= 1000;
4966
153b4b95 4967 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4968 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4969 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4970
4c8c7743
AG		 4971 if (IS_SKYLAKE(dev)) {
4972 /* Convert GT frequency to 50 HZ units */
4973 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4974 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4975 } else {
4976 min_gpu_freq = dev_priv->rps.min_freq;
4977 max_gpu_freq = dev_priv->rps.max_freq;
4978 }
4979
2b4e57bd
ED		 4980 /*
4981 * For each potential GPU frequency, load a ring frequency we'd like
4982 * to use for memory access. We do this by specifying the IA frequency
4983 * the PCU should use as a reference to determine the ring frequency.
4984 */
4c8c7743
AG		 4985 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
4986 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 4987 unsigned int ia_freq = 0, ring_freq = 0;
4988
4c8c7743
AG		 4989 if (IS_SKYLAKE(dev)) {
4990 /*
4991 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4992 * No floor required for ring frequency on SKL.
4993 */
4994 ring_freq = gpu_freq;
4995 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 4996 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4997 ring_freq = max(min_ring_freq, gpu_freq);
4998 } else if (IS_HASWELL(dev)) {
f6aca45c 4999 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5000 ring_freq = max(min_ring_freq, ring_freq);
5001 /* leave ia_freq as the default, chosen by cpufreq */
5002 } else {
5003 /* On older processors, there is no separate ring
5004 * clock domain, so in order to boost the bandwidth
5005 * of the ring, we need to upclock the CPU (ia_freq).
5006 *
5007 * For GPU frequencies less than 750MHz,
5008 * just use the lowest ring freq.
5009 */
5010 if (gpu_freq < min_freq)
5011 ia_freq = 800;
5012 else
5013 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5014 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5015 }
2b4e57bd 5016
42c0526c
BW		 5017 sandybridge_pcode_write(dev_priv,
5018 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5019 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5020 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5021 gpu_freq);
2b4e57bd 5022 }
2b4e57bd
ED		 5023}
5024
c2bc2fc5
ID		 5025void gen6_update_ring_freq(struct drm_device *dev)
5026{
5027 struct drm_i915_private *dev_priv = dev->dev_private;
5028
97d3308a 5029 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5030 return;
5031
5032 mutex_lock(&dev_priv->rps.hw_lock);
5033 __gen6_update_ring_freq(dev);
5034 mutex_unlock(&dev_priv->rps.hw_lock);
5035}
5036
03af2045 5037static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5038{
095acd5f 5039 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5040 u32 val, rp0;
5041
5b5929cb 5042 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5043
5b5929cb
JN		 5044 switch (INTEL_INFO(dev)->eu_total) {
5045 case 8:
5046 /* (2 * 4) config */
5047 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5048 break;
5049 case 12:
5050 /* (2 * 6) config */
5051 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5052 break;
5053 case 16:
5054 /* (2 * 8) config */
5055 default:
5056 /* Setting (2 * 8) Min RP0 for any other combination */
5057 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5058 break;
095acd5f 5059 }
5b5929cb
JN		 5060
5061 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5062
2b6b3a09
D		 5063 return rp0;
5064}
5065
5066static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5067{
5068 u32 val, rpe;
5069
5070 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5071 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5072
5073 return rpe;
5074}
5075
7707df4a
D		 5076static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5077{
5078 u32 val, rp1;
5079
5b5929cb
JN		 5080 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5081 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5082
7707df4a
D		 5083 return rp1;
5084}
5085
f8f2b001
D		 5086static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5087{
5088 u32 val, rp1;
5089
5090 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5091
5092 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5093
5094 return rp1;
5095}
5096
03af2045 5097static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5098{
5099 u32 val, rp0;
5100
64936258 5101 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5102
5103 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5104 /* Clamp to max */
5105 rp0 = min_t(u32, rp0, 0xea);
5106
5107 return rp0;
5108}
5109
5110static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5111{
5112 u32 val, rpe;
5113
64936258 5114 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5115 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5116 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5117 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5118
5119 return rpe;
5120}
5121
03af2045 5122static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5123{
64936258 5124 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5125}
5126
ae48434c
ID		 5127/* Check that the pctx buffer wasn't move under us. */
5128static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5129{
5130 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5131
5132 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5133 dev_priv->vlv_pctx->stolen->start);
5134}
5135
38807746
D		 5136
5137/* Check that the pcbr address is not empty. */
5138static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5139{
5140 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5141
5142 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5143}
5144
5145static void cherryview_setup_pctx(struct drm_device *dev)
5146{
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148 unsigned long pctx_paddr, paddr;
5149 struct i915_gtt *gtt = &dev_priv->gtt;
5150 u32 pcbr;
5151 int pctx_size = 32*1024;
5152
5153 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5154
5155 pcbr = I915_READ(VLV_PCBR);
5156 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5157 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5158 paddr = (dev_priv->mm.stolen_base +
5159 (gtt->stolen_size - pctx_size));
5160
5161 pctx_paddr = (paddr & (~4095));
5162 I915_WRITE(VLV_PCBR, pctx_paddr);
5163 }
ce611ef8
VS		 5164
5165 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5166}
5167
c9cddffc
JB		 5168static void valleyview_setup_pctx(struct drm_device *dev)
5169{
5170 struct drm_i915_private *dev_priv = dev->dev_private;
5171 struct drm_i915_gem_object *pctx;
5172 unsigned long pctx_paddr;
5173 u32 pcbr;
5174 int pctx_size = 24*1024;
5175
17b0c1f7
ID		 5176 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5177
c9cddffc
JB		 5178 pcbr = I915_READ(VLV_PCBR);
5179 if (pcbr) {
5180 /* BIOS set it up already, grab the pre-alloc'd space */
5181 int pcbr_offset;
5182
5183 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5184 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5185 pcbr_offset,
190d6cd5 5186 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5187 pctx_size);
5188 goto out;
5189 }
5190
ce611ef8
VS		 5191 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5192
c9cddffc
JB		 5193 /*
5194 * From the Gunit register HAS:
5195 * The Gfx driver is expected to program this register and ensure
5196 * proper allocation within Gfx stolen memory. For example, this
5197 * register should be programmed such than the PCBR range does not
5198 * overlap with other ranges, such as the frame buffer, protected
5199 * memory, or any other relevant ranges.
5200 */
5201 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5202 if (!pctx) {
5203 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5204 return;
5205 }
5206
5207 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5208 I915_WRITE(VLV_PCBR, pctx_paddr);
5209
5210out:
ce611ef8 5211 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5212 dev_priv->vlv_pctx = pctx;
5213}
5214
ae48434c
ID		 5215static void valleyview_cleanup_pctx(struct drm_device *dev)
5216{
5217 struct drm_i915_private *dev_priv = dev->dev_private;
5218
5219 if (WARN_ON(!dev_priv->vlv_pctx))
5220 return;
5221
5222 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5223 dev_priv->vlv_pctx = NULL;
5224}
5225
4e80519e
ID		 5226static void valleyview_init_gt_powersave(struct drm_device *dev)
5227{
5228 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5229 u32 val;
4e80519e
ID		 5230
5231 valleyview_setup_pctx(dev);
5232
5233 mutex_lock(&dev_priv->rps.hw_lock);
5234
2bb25c17
VS		 5235 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5236 switch ((val >> 6) & 3) {
5237 case 0:
5238 case 1:
5239 dev_priv->mem_freq = 800;
5240 break;
5241 case 2:
5242 dev_priv->mem_freq = 1066;
5243 break;
5244 case 3:
5245 dev_priv->mem_freq = 1333;
5246 break;
5247 }
80b83b62 5248 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5249
4e80519e
ID		 5250 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5251 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5252 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5253 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5254 dev_priv->rps.max_freq);
5255
5256 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5257 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5258 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5259 dev_priv->rps.efficient_freq);
5260
f8f2b001
D		 5261 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5262 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5263 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5264 dev_priv->rps.rp1_freq);
5265
4e80519e
ID		 5266 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5267 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5268 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5269 dev_priv->rps.min_freq);
5270
aed242ff
CW		 5271 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5272
4e80519e
ID		 5273 /* Preserve min/max settings in case of re-init */
5274 if (dev_priv->rps.max_freq_softlimit == 0)
5275 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5276
5277 if (dev_priv->rps.min_freq_softlimit == 0)
5278 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5279
5280 mutex_unlock(&dev_priv->rps.hw_lock);
5281}
5282
38807746
D		 5283static void cherryview_init_gt_powersave(struct drm_device *dev)
5284{
2b6b3a09 5285 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5286 u32 val;
2b6b3a09 5287
38807746 5288 cherryview_setup_pctx(dev);
2b6b3a09
D		 5289
5290 mutex_lock(&dev_priv->rps.hw_lock);
5291
a580516d 5292 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5293 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5294 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5295
2bb25c17 5296 switch ((val >> 2) & 0x7) {
2bb25c17 5297 case 3:
2bb25c17
VS		 5298 dev_priv->mem_freq = 2000;
5299 break;
bfa7df01 5300 default:
2bb25c17
VS		 5301 dev_priv->mem_freq = 1600;
5302 break;
5303 }
80b83b62 5304 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5305
2b6b3a09
D		 5306 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5307 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5308 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5309 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5310 dev_priv->rps.max_freq);
5311
5312 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5313 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5314 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5315 dev_priv->rps.efficient_freq);
5316
7707df4a
D		 5317 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5318 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5319 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5320 dev_priv->rps.rp1_freq);
5321
5b7c91b7
D		 5322 /* PUnit validated range is only [RPe, RP0] */
5323 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5324 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5325 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5326 dev_priv->rps.min_freq);
5327
1c14762d
VS		 5328 WARN_ONCE((dev_priv->rps.max_freq |
5329 dev_priv->rps.efficient_freq |
5330 dev_priv->rps.rp1_freq |
5331 dev_priv->rps.min_freq) & 1,
5332 "Odd GPU freq values\n");
5333
aed242ff
CW		 5334 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5335
2b6b3a09
D		 5336 /* Preserve min/max settings in case of re-init */
5337 if (dev_priv->rps.max_freq_softlimit == 0)
5338 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5339
5340 if (dev_priv->rps.min_freq_softlimit == 0)
5341 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5342
5343 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5344}
5345
4e80519e
ID		 5346static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5347{
5348 valleyview_cleanup_pctx(dev);
5349}
5350
38807746
D		 5351static void cherryview_enable_rps(struct drm_device *dev)
5352{
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 struct intel_engine_cs *ring;
2b6b3a09 5355 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5356 int i;
5357
5358 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5359
5360 gtfifodbg = I915_READ(GTFIFODBG);
5361 if (gtfifodbg) {
5362 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5363 gtfifodbg);
5364 I915_WRITE(GTFIFODBG, gtfifodbg);
5365 }
5366
5367 cherryview_check_pctx(dev_priv);
5368
5369 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5370 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5371 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5372
160614a2
VS		 5373 /* Disable RC states. */
5374 I915_WRITE(GEN6_RC_CONTROL, 0);
5375
38807746
D		 5376 /* 2a: Program RC6 thresholds.*/
5377 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5378 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5379 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5380
5381 for_each_ring(ring, dev_priv, i)
5382 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5383 I915_WRITE(GEN6_RC_SLEEP, 0);
5384
f4f71c7d
D		 5385 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5386 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5387
5388 /* allows RC6 residency counter to work */
5389 I915_WRITE(VLV_COUNTER_CONTROL,
5390 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5391 VLV_MEDIA_RC6_COUNT_EN |
5392 VLV_RENDER_RC6_COUNT_EN));
5393
5394 /* For now we assume BIOS is allocating and populating the PCBR */
5395 pcbr = I915_READ(VLV_PCBR);
5396
38807746
D		 5397 /* 3: Enable RC6 */
5398 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5399 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5400 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5401
5402 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5403
2b6b3a09 5404 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5405 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5406 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5407 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5408 I915_WRITE(GEN6_RP_UP_EI, 66000);
5409 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5410
5411 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5412
5413 /* 5: Enable RPS */
5414 I915_WRITE(GEN6_RP_CONTROL,
5415 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5416 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5417 GEN6_RP_ENABLE |
5418 GEN6_RP_UP_BUSY_AVG |
5419 GEN6_RP_DOWN_IDLE_AVG);
5420
3ef62342
D		 5421 /* Setting Fixed Bias */
5422 val = VLV_OVERRIDE_EN |
5423 VLV_SOC_TDP_EN |
5424 CHV_BIAS_CPU_50_SOC_50;
5425 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5426
2b6b3a09
D		 5427 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5428
8d40c3ae
VS		 5429 /* RPS code assumes GPLL is used */
5430 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5431
742f491d 5432 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5433 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5434
5435 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5436 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5437 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5438 dev_priv->rps.cur_freq);
5439
5440 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5441 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5442 dev_priv->rps.efficient_freq);
5443
5444 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5445
59bad947 5446 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5447}
5448
0a073b84
JB		 5449static void valleyview_enable_rps(struct drm_device *dev)
5450{
5451 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5452 struct intel_engine_cs *ring;
2a5913a8 5453 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5454 int i;
5455
5456 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5457
ae48434c
ID		 5458 valleyview_check_pctx(dev_priv);
5459
0a073b84 5460 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5461 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5462 gtfifodbg);
0a073b84
JB		 5463 I915_WRITE(GTFIFODBG, gtfifodbg);
5464 }
5465
c8d9a590 5466 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5467 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5468
160614a2
VS		 5469 /* Disable RC states. */
5470 I915_WRITE(GEN6_RC_CONTROL, 0);
5471
cad725fe 5472 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5473 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5474 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5475 I915_WRITE(GEN6_RP_UP_EI, 66000);
5476 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5477
5478 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5479
5480 I915_WRITE(GEN6_RP_CONTROL,
5481 GEN6_RP_MEDIA_TURBO |
5482 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5483 GEN6_RP_MEDIA_IS_GFX |
5484 GEN6_RP_ENABLE |
5485 GEN6_RP_UP_BUSY_AVG |
5486 GEN6_RP_DOWN_IDLE_CONT);
5487
5488 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5489 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5490 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5491
5492 for_each_ring(ring, dev_priv, i)
5493 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5494
2f0aa304 5495 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5496
5497 /* allows RC6 residency counter to work */
49798eb2 5498 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5499 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5500 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5501 VLV_MEDIA_RC6_COUNT_EN |
5502 VLV_RENDER_RC6_COUNT_EN));
31685c25 5503
a2b23fe0 5504 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5505 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5506
5507 intel_print_rc6_info(dev, rc6_mode);
5508
a2b23fe0 5509 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5510
3ef62342
D		 5511 /* Setting Fixed Bias */
5512 val = VLV_OVERRIDE_EN |
5513 VLV_SOC_TDP_EN |
5514 VLV_BIAS_CPU_125_SOC_875;
5515 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5516
64936258 5517 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5518
8d40c3ae
VS		 5519 /* RPS code assumes GPLL is used */
5520 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5521
742f491d 5522 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5523 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5524
b39fb297 5525 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5526 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5527 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5528 dev_priv->rps.cur_freq);
0a073b84 5529
73008b98 5530 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5531 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5532 dev_priv->rps.efficient_freq);
0a073b84 5533
b39fb297 5534 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5535
59bad947 5536 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5537}
5538
dde18883
ED		 5539static unsigned long intel_pxfreq(u32 vidfreq)
5540{
5541 unsigned long freq;
5542 int div = (vidfreq & 0x3f0000) >> 16;
5543 int post = (vidfreq & 0x3000) >> 12;
5544 int pre = (vidfreq & 0x7);
5545
5546 if (!pre)
5547 return 0;
5548
5549 freq = ((div * 133333) / ((1<<post) * pre));
5550
5551 return freq;
5552}
5553
eb48eb00
DV		 5554static const struct cparams {
5555 u16 i;
5556 u16 t;
5557 u16 m;
5558 u16 c;
5559} cparams[] = {
5560 { 1, 1333, 301, 28664 },
5561 { 1, 1066, 294, 24460 },
5562 { 1, 800, 294, 25192 },
5563 { 0, 1333, 276, 27605 },
5564 { 0, 1066, 276, 27605 },
5565 { 0, 800, 231, 23784 },
5566};
5567
f531dcb2 5568static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5569{
5570 u64 total_count, diff, ret;
5571 u32 count1, count2, count3, m = 0, c = 0;
5572 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5573 int i;
5574
02d71956
DV		 5575 assert_spin_locked(&mchdev_lock);
5576
20e4d407 5577 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5578
5579 /* Prevent division-by-zero if we are asking too fast.
5580 * Also, we don't get interesting results if we are polling
5581 * faster than once in 10ms, so just return the saved value
5582 * in such cases.
5583 */
5584 if (diff1 <= 10)
20e4d407 5585 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5586
5587 count1 = I915_READ(DMIEC);
5588 count2 = I915_READ(DDREC);
5589 count3 = I915_READ(CSIEC);
5590
5591 total_count = count1 + count2 + count3;
5592
5593 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5594 if (total_count < dev_priv->ips.last_count1) {
5595 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5596 diff += total_count;
5597 } else {
20e4d407 5598 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5599 }
5600
5601 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5602 if (cparams[i].i == dev_priv->ips.c_m &&
5603 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5604 m = cparams[i].m;
5605 c = cparams[i].c;
5606 break;
5607 }
5608 }
5609
5610 diff = div_u64(diff, diff1);
5611 ret = ((m * diff) + c);
5612 ret = div_u64(ret, 10);
5613
20e4d407
DV		 5614 dev_priv->ips.last_count1 = total_count;
5615 dev_priv->ips.last_time1 = now;
eb48eb00 5616
20e4d407 5617 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5618
5619 return ret;
5620}
5621
f531dcb2
CW		 5622unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5623{
3d13ef2e 5624 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5625 unsigned long val;
5626
3d13ef2e 5627 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5628 return 0;
5629
5630 spin_lock_irq(&mchdev_lock);
5631
5632 val = __i915_chipset_val(dev_priv);
5633
5634 spin_unlock_irq(&mchdev_lock);
5635
5636 return val;
5637}
5638
eb48eb00
DV		 5639unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5640{
5641 unsigned long m, x, b;
5642 u32 tsfs;
5643
5644 tsfs = I915_READ(TSFS);
5645
5646 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5647 x = I915_READ8(TR1);
5648
5649 b = tsfs & TSFS_INTR_MASK;
5650
5651 return ((m * x) / 127) - b;
5652}
5653
d972d6ee
MK		 5654static int _pxvid_to_vd(u8 pxvid)
5655{
5656 if (pxvid == 0)
5657 return 0;
5658
5659 if (pxvid >= 8 && pxvid < 31)
5660 pxvid = 31;
5661
5662 return (pxvid + 2) * 125;
5663}
5664
5665static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5666{
3d13ef2e 5667 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5668 const int vd = _pxvid_to_vd(pxvid);
5669 const int vm = vd - 1125;
5670
3d13ef2e 5671 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5672 return vm > 0 ? vm : 0;
5673
5674 return vd;
eb48eb00
DV		 5675}
5676
02d71956 5677static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5678{
5ed0bdf2 5679 u64 now, diff, diffms;
eb48eb00
DV		 5680 u32 count;
5681
02d71956 5682 assert_spin_locked(&mchdev_lock);
eb48eb00 5683
5ed0bdf2
TG		 5684 now = ktime_get_raw_ns();
5685 diffms = now - dev_priv->ips.last_time2;
5686 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5687
5688 /* Don't divide by 0 */
eb48eb00
DV		 5689 if (!diffms)
5690 return;
5691
5692 count = I915_READ(GFXEC);
5693
20e4d407
DV		 5694 if (count < dev_priv->ips.last_count2) {
5695 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5696 diff += count;
5697 } else {
20e4d407 5698 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5699 }
5700
20e4d407
DV		 5701 dev_priv->ips.last_count2 = count;
5702 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5703
5704 /* More magic constants... */
5705 diff = diff * 1181;
5706 diff = div_u64(diff, diffms * 10);
20e4d407 5707 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5708}
5709
02d71956
DV		 5710void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5711{
3d13ef2e
DL		 5712 struct drm_device *dev = dev_priv->dev;
5713
5714 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5715 return;
5716
9270388e 5717 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5718
5719 __i915_update_gfx_val(dev_priv);
5720
9270388e 5721 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5722}
5723
f531dcb2 5724static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5725{
5726 unsigned long t, corr, state1, corr2, state2;
5727 u32 pxvid, ext_v;
5728
02d71956
DV		 5729 assert_spin_locked(&mchdev_lock);
5730
616847e7 5731 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5732 pxvid = (pxvid >> 24) & 0x7f;
5733 ext_v = pvid_to_extvid(dev_priv, pxvid);
5734
5735 state1 = ext_v;
5736
5737 t = i915_mch_val(dev_priv);
5738
5739 /* Revel in the empirically derived constants */
5740
5741 /* Correction factor in 1/100000 units */
5742 if (t > 80)
5743 corr = ((t * 2349) + 135940);
5744 else if (t >= 50)
5745 corr = ((t * 964) + 29317);
5746 else /* < 50 */
5747 corr = ((t * 301) + 1004);
5748
5749 corr = corr * ((150142 * state1) / 10000 - 78642);
5750 corr /= 100000;
20e4d407 5751 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5752
5753 state2 = (corr2 * state1) / 10000;
5754 state2 /= 100; /* convert to mW */
5755
02d71956 5756 __i915_update_gfx_val(dev_priv);
eb48eb00 5757
20e4d407 5758 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5759}
5760
f531dcb2
CW		 5761unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5762{
3d13ef2e 5763 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5764 unsigned long val;
5765
3d13ef2e 5766 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5767 return 0;
5768
5769 spin_lock_irq(&mchdev_lock);
5770
5771 val = __i915_gfx_val(dev_priv);
5772
5773 spin_unlock_irq(&mchdev_lock);
5774
5775 return val;
5776}
5777
eb48eb00
DV		 5778/**
5779 * i915_read_mch_val - return value for IPS use
5780 *
5781 * Calculate and return a value for the IPS driver to use when deciding whether
5782 * we have thermal and power headroom to increase CPU or GPU power budget.
5783 */
5784unsigned long i915_read_mch_val(void)
5785{
5786 struct drm_i915_private *dev_priv;
5787 unsigned long chipset_val, graphics_val, ret = 0;
5788
9270388e 5789 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5790 if (!i915_mch_dev)
5791 goto out_unlock;
5792 dev_priv = i915_mch_dev;
5793
f531dcb2
CW		 5794 chipset_val = __i915_chipset_val(dev_priv);
5795 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5796
5797 ret = chipset_val + graphics_val;
5798
5799out_unlock:
9270388e 5800 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5801
5802 return ret;
5803}
5804EXPORT_SYMBOL_GPL(i915_read_mch_val);
5805
5806/**
5807 * i915_gpu_raise - raise GPU frequency limit
5808 *
5809 * Raise the limit; IPS indicates we have thermal headroom.
5810 */
5811bool i915_gpu_raise(void)
5812{
5813 struct drm_i915_private *dev_priv;
5814 bool ret = true;
5815
9270388e 5816 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5817 if (!i915_mch_dev) {
5818 ret = false;
5819 goto out_unlock;
5820 }
5821 dev_priv = i915_mch_dev;
5822
20e4d407
DV		 5823 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5824 dev_priv->ips.max_delay--;
eb48eb00
DV		 5825
5826out_unlock:
9270388e 5827 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5828
5829 return ret;
5830}
5831EXPORT_SYMBOL_GPL(i915_gpu_raise);
5832
5833/**
5834 * i915_gpu_lower - lower GPU frequency limit
5835 *
5836 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5837 * frequency maximum.
5838 */
5839bool i915_gpu_lower(void)
5840{
5841 struct drm_i915_private *dev_priv;
5842 bool ret = true;
5843
9270388e 5844 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5845 if (!i915_mch_dev) {
5846 ret = false;
5847 goto out_unlock;
5848 }
5849 dev_priv = i915_mch_dev;
5850
20e4d407
DV		 5851 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5852 dev_priv->ips.max_delay++;
eb48eb00
DV		 5853
5854out_unlock:
9270388e 5855 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5856
5857 return ret;
5858}
5859EXPORT_SYMBOL_GPL(i915_gpu_lower);
5860
5861/**
5862 * i915_gpu_busy - indicate GPU business to IPS
5863 *
5864 * Tell the IPS driver whether or not the GPU is busy.
5865 */
5866bool i915_gpu_busy(void)
5867{
5868 struct drm_i915_private *dev_priv;
a4872ba6 5869 struct intel_engine_cs *ring;
eb48eb00 5870 bool ret = false;
f047e395 5871 int i;
eb48eb00 5872
9270388e 5873 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5874 if (!i915_mch_dev)
5875 goto out_unlock;
5876 dev_priv = i915_mch_dev;
5877
f047e395
CW		 5878 for_each_ring(ring, dev_priv, i)
5879 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5880
5881out_unlock:
9270388e 5882 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5883
5884 return ret;
5885}
5886EXPORT_SYMBOL_GPL(i915_gpu_busy);
5887
5888/**
5889 * i915_gpu_turbo_disable - disable graphics turbo
5890 *
5891 * Disable graphics turbo by resetting the max frequency and setting the
5892 * current frequency to the default.
5893 */
5894bool i915_gpu_turbo_disable(void)
5895{
5896 struct drm_i915_private *dev_priv;
5897 bool ret = true;
5898
9270388e 5899 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5900 if (!i915_mch_dev) {
5901 ret = false;
5902 goto out_unlock;
5903 }
5904 dev_priv = i915_mch_dev;
5905
20e4d407 5906 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5907
20e4d407 5908 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5909 ret = false;
5910
5911out_unlock:
9270388e 5912 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5913
5914 return ret;
5915}
5916EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5917
5918/**
5919 * Tells the intel_ips driver that the i915 driver is now loaded, if
5920 * IPS got loaded first.
5921 *
5922 * This awkward dance is so that neither module has to depend on the
5923 * other in order for IPS to do the appropriate communication of
5924 * GPU turbo limits to i915.
5925 */
5926static void
5927ips_ping_for_i915_load(void)
5928{
5929 void (*link)(void);
5930
5931 link = symbol_get(ips_link_to_i915_driver);
5932 if (link) {
5933 link();
5934 symbol_put(ips_link_to_i915_driver);
5935 }
5936}
5937
5938void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5939{
02d71956
DV		 5940 /* We only register the i915 ips part with intel-ips once everything is
5941 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5942 spin_lock_irq(&mchdev_lock);
eb48eb00 5943 i915_mch_dev = dev_priv;
9270388e 5944 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5945
5946 ips_ping_for_i915_load();
5947}
5948
5949void intel_gpu_ips_teardown(void)
5950{
9270388e 5951 spin_lock_irq(&mchdev_lock);
eb48eb00 5952 i915_mch_dev = NULL;
9270388e 5953 spin_unlock_irq(&mchdev_lock);
eb48eb00 5954}
76c3552f 5955
8090c6b9 5956static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5957{
5958 struct drm_i915_private *dev_priv = dev->dev_private;
5959 u32 lcfuse;
5960 u8 pxw[16];
5961 int i;
5962
5963 /* Disable to program */
5964 I915_WRITE(ECR, 0);
5965 POSTING_READ(ECR);
5966
5967 /* Program energy weights for various events */
5968 I915_WRITE(SDEW, 0x15040d00);
5969 I915_WRITE(CSIEW0, 0x007f0000);
5970 I915_WRITE(CSIEW1, 0x1e220004);
5971 I915_WRITE(CSIEW2, 0x04000004);
5972
5973 for (i = 0; i < 5; i++)
616847e7 5974 I915_WRITE(PEW(i), 0);
dde18883 5975 for (i = 0; i < 3; i++)
616847e7 5976 I915_WRITE(DEW(i), 0);
dde18883
ED		 5977
5978 /* Program P-state weights to account for frequency power adjustment */
5979 for (i = 0; i < 16; i++) {
616847e7 5980 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 5981 unsigned long freq = intel_pxfreq(pxvidfreq);
5982 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5983 PXVFREQ_PX_SHIFT;
5984 unsigned long val;
5985
5986 val = vid * vid;
5987 val *= (freq / 1000);
5988 val *= 255;
5989 val /= (127*127*900);
5990 if (val > 0xff)
5991 DRM_ERROR("bad pxval: %ld\n", val);
5992 pxw[i] = val;
5993 }
5994 /* Render standby states get 0 weight */
5995 pxw[14] = 0;
5996 pxw[15] = 0;
5997
5998 for (i = 0; i < 4; i++) {
5999 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6000 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6001 I915_WRITE(PXW(i), val);
dde18883
ED		 6002 }
6003
6004 /* Adjust magic regs to magic values (more experimental results) */
6005 I915_WRITE(OGW0, 0);
6006 I915_WRITE(OGW1, 0);
6007 I915_WRITE(EG0, 0x00007f00);
6008 I915_WRITE(EG1, 0x0000000e);
6009 I915_WRITE(EG2, 0x000e0000);
6010 I915_WRITE(EG3, 0x68000300);
6011 I915_WRITE(EG4, 0x42000000);
6012 I915_WRITE(EG5, 0x00140031);
6013 I915_WRITE(EG6, 0);
6014 I915_WRITE(EG7, 0);
6015
6016 for (i = 0; i < 8; i++)
616847e7 6017 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6018
6019 /* Enable PMON + select events */
6020 I915_WRITE(ECR, 0x80000019);
6021
6022 lcfuse = I915_READ(LCFUSE02);
6023
20e4d407 6024 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6025}
6026
ae48434c
ID		 6027void intel_init_gt_powersave(struct drm_device *dev)
6028{
e6069ca8
ID		 6029 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6030
38807746
D		 6031 if (IS_CHERRYVIEW(dev))
6032 cherryview_init_gt_powersave(dev);
6033 else if (IS_VALLEYVIEW(dev))
4e80519e 6034 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6035}
6036
6037void intel_cleanup_gt_powersave(struct drm_device *dev)
6038{
38807746
D		 6039 if (IS_CHERRYVIEW(dev))
6040 return;
6041 else if (IS_VALLEYVIEW(dev))
4e80519e 6042 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6043}
6044
dbea3cea
ID		 6045static void gen6_suspend_rps(struct drm_device *dev)
6046{
6047 struct drm_i915_private *dev_priv = dev->dev_private;
6048
6049 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6050
4c2a8897 6051 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6052}
6053
156c7ca0
JB		 6054/**
6055 * intel_suspend_gt_powersave - suspend PM work and helper threads
6056 * @dev: drm device
6057 *
6058 * We don't want to disable RC6 or other features here, we just want
6059 * to make sure any work we've queued has finished and won't bother
6060 * us while we're suspended.
6061 */
6062void intel_suspend_gt_powersave(struct drm_device *dev)
6063{
6064 struct drm_i915_private *dev_priv = dev->dev_private;
6065
d4d70aa5
ID		 6066 if (INTEL_INFO(dev)->gen < 6)
6067 return;
6068
dbea3cea 6069 gen6_suspend_rps(dev);
b47adc17
D		 6070
6071 /* Force GPU to min freq during suspend */
6072 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6073}
6074
8090c6b9
DV		 6075void intel_disable_gt_powersave(struct drm_device *dev)
6076{
1a01ab3b
JB		 6077 struct drm_i915_private *dev_priv = dev->dev_private;
6078
930ebb46 6079 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6080 ironlake_disable_drps(dev);
38807746 6081 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6082 intel_suspend_gt_powersave(dev);
e494837a 6083
4fc688ce 6084 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6085 if (INTEL_INFO(dev)->gen >= 9)
6086 gen9_disable_rps(dev);
6087 else if (IS_CHERRYVIEW(dev))
38807746
D		 6088 cherryview_disable_rps(dev);
6089 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6090 valleyview_disable_rps(dev);
6091 else
6092 gen6_disable_rps(dev);
e534770a 6093
c0951f0c 6094 dev_priv->rps.enabled = false;
4fc688ce 6095 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6096 }
8090c6b9
DV		 6097}
6098
1a01ab3b
JB		 6099static void intel_gen6_powersave_work(struct work_struct *work)
6100{
6101 struct drm_i915_private *dev_priv =
6102 container_of(work, struct drm_i915_private,
6103 rps.delayed_resume_work.work);
6104 struct drm_device *dev = dev_priv->dev;
6105
4fc688ce 6106 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6107
4c2a8897 6108 gen6_reset_rps_interrupts(dev);
3cc134e3 6109
38807746
D		 6110 if (IS_CHERRYVIEW(dev)) {
6111 cherryview_enable_rps(dev);
6112 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6113 valleyview_enable_rps(dev);
20e49366 6114 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6115 gen9_enable_rc6(dev);
20e49366 6116 gen9_enable_rps(dev);
cc017fb4
AG		 6117 if (IS_SKYLAKE(dev))
6118 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6119 } else if (IS_BROADWELL(dev)) {
6120 gen8_enable_rps(dev);
c2bc2fc5 6121 __gen6_update_ring_freq(dev);
0a073b84
JB		 6122 } else {
6123 gen6_enable_rps(dev);
c2bc2fc5 6124 __gen6_update_ring_freq(dev);
0a073b84 6125 }
aed242ff
CW		 6126
6127 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6128 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6129
6130 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6131 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6132
c0951f0c 6133 dev_priv->rps.enabled = true;
3cc134e3 6134
4c2a8897 6135 gen6_enable_rps_interrupts(dev);
3cc134e3 6136
4fc688ce 6137 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6138
6139 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6140}
6141
8090c6b9
DV		 6142void intel_enable_gt_powersave(struct drm_device *dev)
6143{
1a01ab3b
JB		 6144 struct drm_i915_private *dev_priv = dev->dev_private;
6145
f61018b1
YZ		 6146 /* Powersaving is controlled by the host when inside a VM */
6147 if (intel_vgpu_active(dev))
6148 return;
6149
8090c6b9 6150 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6151 mutex_lock(&dev->struct_mutex);
8090c6b9 6152 ironlake_enable_drps(dev);
8090c6b9 6153 intel_init_emon(dev);
dc1d0136 6154 mutex_unlock(&dev->struct_mutex);
38807746 6155 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6156 /*
6157 * PCU communication is slow and this doesn't need to be
6158 * done at any specific time, so do this out of our fast path
6159 * to make resume and init faster.
c6df39b5
ID		 6160 *
6161 * We depend on the HW RC6 power context save/restore
6162 * mechanism when entering D3 through runtime PM suspend. So
6163 * disable RPM until RPS/RC6 is properly setup. We can only
6164 * get here via the driver load/system resume/runtime resume
6165 * paths, so the _noresume version is enough (and in case of
6166 * runtime resume it's necessary).
1a01ab3b 6167 */
c6df39b5
ID		 6168 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6169 round_jiffies_up_relative(HZ)))
6170 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6171 }
6172}
6173
c6df39b5
ID		 6174void intel_reset_gt_powersave(struct drm_device *dev)
6175{
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177
dbea3cea
ID		 6178 if (INTEL_INFO(dev)->gen < 6)
6179 return;
6180
6181 gen6_suspend_rps(dev);
c6df39b5 6182 dev_priv->rps.enabled = false;
c6df39b5
ID		 6183}
6184
3107bd48
DV		 6185static void ibx_init_clock_gating(struct drm_device *dev)
6186{
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188
6189 /*
6190 * On Ibex Peak and Cougar Point, we need to disable clock
6191 * gating for the panel power sequencer or it will fail to
6192 * start up when no ports are active.
6193 */
6194 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6195}
6196
0e088b8f
VS		 6197static void g4x_disable_trickle_feed(struct drm_device *dev)
6198{
6199 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6200 enum pipe pipe;
0e088b8f 6201
055e393f 6202 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6203 I915_WRITE(DSPCNTR(pipe),
6204 I915_READ(DSPCNTR(pipe)) |
6205 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6206
6207 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6208 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6209 }
6210}
6211
017636cc
VS		 6212static void ilk_init_lp_watermarks(struct drm_device *dev)
6213{
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215
6216 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6217 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6218 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6219
6220 /*
6221 * Don't touch WM1S_LP_EN here.
6222 * Doing so could cause underruns.
6223 */
6224}
6225
1fa61106 6226static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6227{
6228 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6229 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6230
f1e8fa56
DL		 6231 /*
6232 * Required for FBC
6233 * WaFbcDisableDpfcClockGating:ilk
6234 */
4d47e4f5
DL		 6235 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6236 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6237 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6238
6239 I915_WRITE(PCH_3DCGDIS0,
6240 MARIUNIT_CLOCK_GATE_DISABLE |
6241 SVSMUNIT_CLOCK_GATE_DISABLE);
6242 I915_WRITE(PCH_3DCGDIS1,
6243 VFMUNIT_CLOCK_GATE_DISABLE);
6244
6f1d69b0
ED		 6245 /*
6246 * According to the spec the following bits should be set in
6247 * order to enable memory self-refresh
6248 * The bit 22/21 of 0x42004
6249 * The bit 5 of 0x42020
6250 * The bit 15 of 0x45000
6251 */
6252 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6253 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6254 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6255 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6256 I915_WRITE(DISP_ARB_CTL,
6257 (I915_READ(DISP_ARB_CTL) |
6258 DISP_FBC_WM_DIS));
017636cc
VS		 6259
6260 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6261
6262 /*
6263 * Based on the document from hardware guys the following bits
6264 * should be set unconditionally in order to enable FBC.
6265 * The bit 22 of 0x42000
6266 * The bit 22 of 0x42004
6267 * The bit 7,8,9 of 0x42020.
6268 */
6269 if (IS_IRONLAKE_M(dev)) {
4bb35334 6270 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6271 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6272 I915_READ(ILK_DISPLAY_CHICKEN1) |
6273 ILK_FBCQ_DIS);
6274 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6275 I915_READ(ILK_DISPLAY_CHICKEN2) |
6276 ILK_DPARB_GATE);
6f1d69b0
ED		 6277 }
6278
4d47e4f5
DL		 6279 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6280
6f1d69b0
ED		 6281 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6282 I915_READ(ILK_DISPLAY_CHICKEN2) |
6283 ILK_ELPIN_409_SELECT);
6284 I915_WRITE(_3D_CHICKEN2,
6285 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6286 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6287
ecdb4eb7 6288 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6289 I915_WRITE(CACHE_MODE_0,
6290 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6291
4e04632e
AG		 6292 /* WaDisable_RenderCache_OperationalFlush:ilk */
6293 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6294
0e088b8f 6295 g4x_disable_trickle_feed(dev);
bdad2b2f 6296
3107bd48
DV		 6297 ibx_init_clock_gating(dev);
6298}
6299
6300static void cpt_init_clock_gating(struct drm_device *dev)
6301{
6302 struct drm_i915_private *dev_priv = dev->dev_private;
6303 int pipe;
3f704fa2 6304 uint32_t val;
3107bd48
DV		 6305
6306 /*
6307 * On Ibex Peak and Cougar Point, we need to disable clock
6308 * gating for the panel power sequencer or it will fail to
6309 * start up when no ports are active.
6310 */
cd664078
JB		 6311 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6312 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6313 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6314 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6315 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6316 /* The below fixes the weird display corruption, a few pixels shifted
6317 * downward, on (only) LVDS of some HP laptops with IVY.
6318 */
055e393f 6319 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6320 val = I915_READ(TRANS_CHICKEN2(pipe));
6321 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6322 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6323 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6324 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6325 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6326 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6327 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6328 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6329 }
3107bd48 6330 /* WADP0ClockGatingDisable */
055e393f 6331 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6332 I915_WRITE(TRANS_CHICKEN1(pipe),
6333 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6334 }
6f1d69b0
ED		 6335}
6336
1d7aaa0c
DV		 6337static void gen6_check_mch_setup(struct drm_device *dev)
6338{
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 uint32_t tmp;
6341
6342 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6343 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6344 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6345 tmp);
1d7aaa0c
DV		 6346}
6347
1fa61106 6348static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6349{
6350 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6351 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6352
231e54f6 6353 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6354
6355 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6356 I915_READ(ILK_DISPLAY_CHICKEN2) |
6357 ILK_ELPIN_409_SELECT);
6358
ecdb4eb7 6359 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6360 I915_WRITE(_3D_CHICKEN,
6361 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6362
4e04632e
AG		 6363 /* WaDisable_RenderCache_OperationalFlush:snb */
6364 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6365
8d85d272
VS		 6366 /*
6367 * BSpec recoomends 8x4 when MSAA is used,
6368 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6369 *
6370 * Note that PS/WM thread counts depend on the WIZ hashing
6371 * disable bit, which we don't touch here, but it's good
6372 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6373 */
6374 I915_WRITE(GEN6_GT_MODE,
98533251 6375 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6376
017636cc 6377 ilk_init_lp_watermarks(dev);
6f1d69b0 6378
6f1d69b0 6379 I915_WRITE(CACHE_MODE_0,
50743298 6380 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6381
6382 I915_WRITE(GEN6_UCGCTL1,
6383 I915_READ(GEN6_UCGCTL1) |
6384 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6385 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6386
6387 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6388 * gating disable must be set. Failure to set it results in
6389 * flickering pixels due to Z write ordering failures after
6390 * some amount of runtime in the Mesa "fire" demo, and Unigine
6391 * Sanctuary and Tropics, and apparently anything else with
6392 * alpha test or pixel discard.
6393 *
6394 * According to the spec, bit 11 (RCCUNIT) must also be set,
6395 * but we didn't debug actual testcases to find it out.
0f846f81 6396 *
ef59318c
VS		 6397 * WaDisableRCCUnitClockGating:snb
6398 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6399 */
6400 I915_WRITE(GEN6_UCGCTL2,
6401 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6402 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6403
5eb146dd 6404 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6405 I915_WRITE(_3D_CHICKEN3,
6406 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6407
e927ecde
VS		 6408 /*
6409 * Bspec says:
6410 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6411 * 3DSTATE_SF number of SF output attributes is more than 16."
6412 */
6413 I915_WRITE(_3D_CHICKEN3,
6414 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6415
6f1d69b0
ED		 6416 /*
6417 * According to the spec the following bits should be
6418 * set in order to enable memory self-refresh and fbc:
6419 * The bit21 and bit22 of 0x42000
6420 * The bit21 and bit22 of 0x42004
6421 * The bit5 and bit7 of 0x42020
6422 * The bit14 of 0x70180
6423 * The bit14 of 0x71180
4bb35334
DL		 6424 *
6425 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6426 */
6427 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6428 I915_READ(ILK_DISPLAY_CHICKEN1) |
6429 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6430 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6431 I915_READ(ILK_DISPLAY_CHICKEN2) |
6432 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6433 I915_WRITE(ILK_DSPCLK_GATE_D,
6434 I915_READ(ILK_DSPCLK_GATE_D) |
6435 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6436 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6437
0e088b8f 6438 g4x_disable_trickle_feed(dev);
f8f2ac9a 6439
3107bd48 6440 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6441
6442 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6443}
6444
6445static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6446{
6447 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6448
3aad9059 6449 /*
46680e0a 6450 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6451 *
6452 * This actually overrides the dispatch
6453 * mode for all thread types.
6454 */
6f1d69b0
ED		 6455 reg &= ~GEN7_FF_SCHED_MASK;
6456 reg |= GEN7_FF_TS_SCHED_HW;
6457 reg |= GEN7_FF_VS_SCHED_HW;
6458 reg |= GEN7_FF_DS_SCHED_HW;
6459
6460 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6461}
6462
17a303ec
PZ		 6463static void lpt_init_clock_gating(struct drm_device *dev)
6464{
6465 struct drm_i915_private *dev_priv = dev->dev_private;
6466
6467 /*
6468 * TODO: this bit should only be enabled when really needed, then
6469 * disabled when not needed anymore in order to save power.
6470 */
c2699524 6471 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6472 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6473 I915_READ(SOUTH_DSPCLK_GATE_D) |
6474 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6475
6476 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6477 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6478 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6479 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6480}
6481
7d708ee4
ID		 6482static void lpt_suspend_hw(struct drm_device *dev)
6483{
6484 struct drm_i915_private *dev_priv = dev->dev_private;
6485
c2699524 6486 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6487 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6488
6489 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6490 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6491 }
6492}
6493
47c2bd97 6494static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6495{
6496 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6497 enum pipe pipe;
4d487cff 6498 uint32_t misccpctl;
1020a5c2 6499
7ad0dbab 6500 ilk_init_lp_watermarks(dev);
50ed5fbd 6501
ab57fff1 6502 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6503 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6504
ab57fff1 6505 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6506 I915_WRITE(CHICKEN_PAR1_1,
6507 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6508
ab57fff1 6509 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6510 for_each_pipe(dev_priv, pipe) {
07d27e20 6511 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6512 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6513 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6514 }
63801f21 6515
ab57fff1
BW		 6516 /* WaVSRefCountFullforceMissDisable:bdw */
6517 /* WaDSRefCountFullforceMissDisable:bdw */
6518 I915_WRITE(GEN7_FF_THREAD_MODE,
6519 I915_READ(GEN7_FF_THREAD_MODE) &
6520 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6521
295e8bb7
VS		 6522 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6523 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6524
6525 /* WaDisableSDEUnitClockGating:bdw */
6526 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6527 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6528
4d487cff
VS		 6529 /*
6530 * WaProgramL3SqcReg1Default:bdw
6531 * WaTempDisableDOPClkGating:bdw
6532 */
6533 misccpctl = I915_READ(GEN7_MISCCPCTL);
6534 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6535 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6536 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6537
6d50b065
VS		 6538 /*
6539 * WaGttCachingOffByDefault:bdw
6540 * GTT cache may not work with big pages, so if those
6541 * are ever enabled GTT cache may need to be disabled.
6542 */
6543 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6544
89d6b2b8 6545 lpt_init_clock_gating(dev);
1020a5c2
BW		 6546}
6547
cad2a2d7
ED		 6548static void haswell_init_clock_gating(struct drm_device *dev)
6549{
6550 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6551
017636cc 6552 ilk_init_lp_watermarks(dev);
cad2a2d7 6553
f3fc4884
FJ		 6554 /* L3 caching of data atomics doesn't work -- disable it. */
6555 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6556 I915_WRITE(HSW_ROW_CHICKEN3,
6557 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6558
ecdb4eb7 6559 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6560 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6561 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6562 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6563
e36ea7ff
VS		 6564 /* WaVSRefCountFullforceMissDisable:hsw */
6565 I915_WRITE(GEN7_FF_THREAD_MODE,
6566 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6567
4e04632e
AG		 6568 /* WaDisable_RenderCache_OperationalFlush:hsw */
6569 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6570
fe27c606
CW		 6571 /* enable HiZ Raw Stall Optimization */
6572 I915_WRITE(CACHE_MODE_0_GEN7,
6573 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6574
ecdb4eb7 6575 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6576 I915_WRITE(CACHE_MODE_1,
6577 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6578
a12c4967
VS		 6579 /*
6580 * BSpec recommends 8x4 when MSAA is used,
6581 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6582 *
6583 * Note that PS/WM thread counts depend on the WIZ hashing
6584 * disable bit, which we don't touch here, but it's good
6585 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6586 */
6587 I915_WRITE(GEN7_GT_MODE,
98533251 6588 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6589
94411593
KG		 6590 /* WaSampleCChickenBitEnable:hsw */
6591 I915_WRITE(HALF_SLICE_CHICKEN3,
6592 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6593
ecdb4eb7 6594 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6595 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6596
90a88643
PZ		 6597 /* WaRsPkgCStateDisplayPMReq:hsw */
6598 I915_WRITE(CHICKEN_PAR1_1,
6599 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6600
17a303ec 6601 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6602}
6603
1fa61106 6604static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6605{
6606 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6607 uint32_t snpcr;
6f1d69b0 6608
017636cc 6609 ilk_init_lp_watermarks(dev);
6f1d69b0 6610
231e54f6 6611 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6612
ecdb4eb7 6613 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6614 I915_WRITE(_3D_CHICKEN3,
6615 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6616
ecdb4eb7 6617 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6618 I915_WRITE(IVB_CHICKEN3,
6619 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6620 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6621
ecdb4eb7 6622 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6623 if (IS_IVB_GT1(dev))
6624 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6625 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6626
4e04632e
AG		 6627 /* WaDisable_RenderCache_OperationalFlush:ivb */
6628 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6629
ecdb4eb7 6630 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6631 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6632 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6633
ecdb4eb7 6634 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6635 I915_WRITE(GEN7_L3CNTLREG1,
6636 GEN7_WA_FOR_GEN7_L3_CONTROL);
6637 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6638 GEN7_WA_L3_CHICKEN_MODE);
6639 if (IS_IVB_GT1(dev))
6640 I915_WRITE(GEN7_ROW_CHICKEN2,
6641 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6642 else {
6643 /* must write both registers */
6644 I915_WRITE(GEN7_ROW_CHICKEN2,
6645 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6646 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6647 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6648 }
6f1d69b0 6649
ecdb4eb7 6650 /* WaForceL3Serialization:ivb */
61939d97
JB		 6651 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6652 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6653
1b80a19a 6654 /*
0f846f81 6655 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6656 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6657 */
6658 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6659 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6660
ecdb4eb7 6661 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6662 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6663 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6664 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6665
0e088b8f 6666 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6667
6668 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6669
22721343
CW		 6670 if (0) { /* causes HiZ corruption on ivb:gt1 */
6671 /* enable HiZ Raw Stall Optimization */
6672 I915_WRITE(CACHE_MODE_0_GEN7,
6673 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6674 }
116f2b6d 6675
ecdb4eb7 6676 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6677 I915_WRITE(CACHE_MODE_1,
6678 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6679
a607c1a4
VS		 6680 /*
6681 * BSpec recommends 8x4 when MSAA is used,
6682 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6683 *
6684 * Note that PS/WM thread counts depend on the WIZ hashing
6685 * disable bit, which we don't touch here, but it's good
6686 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6687 */
6688 I915_WRITE(GEN7_GT_MODE,
98533251 6689 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6690
20848223
BW		 6691 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6692 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6693 snpcr |= GEN6_MBC_SNPCR_MED;
6694 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6695
ab5c608b
BW		 6696 if (!HAS_PCH_NOP(dev))
6697 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6698
6699 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6700}
6701
c6beb13e
VS		 6702static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6703{
6704 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6705
6706 /*
6707 * Disable trickle feed and enable pnd deadline calculation
6708 */
6709 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6710 I915_WRITE(CBR1_VLV, 0);
6711}
6712
1fa61106 6713static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6714{
6715 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6716
c6beb13e 6717 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6718
ecdb4eb7 6719 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6720 I915_WRITE(_3D_CHICKEN3,
6721 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6722
ecdb4eb7 6723 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6724 I915_WRITE(IVB_CHICKEN3,
6725 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6726 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6727
fad7d36e 6728 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6729 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6730 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6731 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6732 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6733
4e04632e
AG		 6734 /* WaDisable_RenderCache_OperationalFlush:vlv */
6735 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6736
ecdb4eb7 6737 /* WaForceL3Serialization:vlv */
61939d97
JB		 6738 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6739 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6740
ecdb4eb7 6741 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6742 I915_WRITE(GEN7_ROW_CHICKEN2,
6743 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6744
ecdb4eb7 6745 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6746 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6747 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6748 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6749
46680e0a
VS		 6750 gen7_setup_fixed_func_scheduler(dev_priv);
6751
3c0edaeb 6752 /*
0f846f81 6753 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6754 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6755 */
6756 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6757 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6758
c98f5062
AG		 6759 /* WaDisableL3Bank2xClockGate:vlv
6760 * Disabling L3 clock gating- MMIO 940c[25] = 1
6761 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6762 I915_WRITE(GEN7_UCGCTL4,
6763 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6764
afd58e79
VS		 6765 /*
6766 * BSpec says this must be set, even though
6767 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6768 */
6b26c86d
DV		 6769 I915_WRITE(CACHE_MODE_1,
6770 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6771
da2518f9
VS		 6772 /*
6773 * BSpec recommends 8x4 when MSAA is used,
6774 * however in practice 16x4 seems fastest.
6775 *
6776 * Note that PS/WM thread counts depend on the WIZ hashing
6777 * disable bit, which we don't touch here, but it's good
6778 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6779 */
6780 I915_WRITE(GEN7_GT_MODE,
6781 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6782
031994ee
VS		 6783 /*
6784 * WaIncreaseL3CreditsForVLVB0:vlv
6785 * This is the hardware default actually.
6786 */
6787 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6788
2d809570 6789 /*
ecdb4eb7 6790 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6791 * Disable clock gating on th GCFG unit to prevent a delay
6792 * in the reporting of vblank events.
6793 */
7a0d1eed 6794 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6795}
6796
a4565da8
VS		 6797static void cherryview_init_clock_gating(struct drm_device *dev)
6798{
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6800
c6beb13e 6801 vlv_init_display_clock_gating(dev_priv);
dd811e70 6802
232ce337
VS		 6803 /* WaVSRefCountFullforceMissDisable:chv */
6804 /* WaDSRefCountFullforceMissDisable:chv */
6805 I915_WRITE(GEN7_FF_THREAD_MODE,
6806 I915_READ(GEN7_FF_THREAD_MODE) &
6807 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6808
6809 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6810 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6811 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6812
6813 /* WaDisableCSUnitClockGating:chv */
6814 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6815 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6816
6817 /* WaDisableSDEUnitClockGating:chv */
6818 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6819 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6820
6821 /*
6822 * GTT cache may not work with big pages, so if those
6823 * are ever enabled GTT cache may need to be disabled.
6824 */
6825 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6826}
6827
1fa61106 6828static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6829{
6830 struct drm_i915_private *dev_priv = dev->dev_private;
6831 uint32_t dspclk_gate;
6832
6833 I915_WRITE(RENCLK_GATE_D1, 0);
6834 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6835 GS_UNIT_CLOCK_GATE_DISABLE |
6836 CL_UNIT_CLOCK_GATE_DISABLE);
6837 I915_WRITE(RAMCLK_GATE_D, 0);
6838 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6839 OVRUNIT_CLOCK_GATE_DISABLE |
6840 OVCUNIT_CLOCK_GATE_DISABLE;
6841 if (IS_GM45(dev))
6842 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6843 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6844
6845 /* WaDisableRenderCachePipelinedFlush */
6846 I915_WRITE(CACHE_MODE_0,
6847 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6848
4e04632e
AG		 6849 /* WaDisable_RenderCache_OperationalFlush:g4x */
6850 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6851
0e088b8f 6852 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6853}
6854
1fa61106 6855static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6856{
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858
6859 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6860 I915_WRITE(RENCLK_GATE_D2, 0);
6861 I915_WRITE(DSPCLK_GATE_D, 0);
6862 I915_WRITE(RAMCLK_GATE_D, 0);
6863 I915_WRITE16(DEUC, 0);
20f94967
VS		 6864 I915_WRITE(MI_ARB_STATE,
6865 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6866
6867 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6868 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6869}
6870
1fa61106 6871static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6872{
6873 struct drm_i915_private *dev_priv = dev->dev_private;
6874
6875 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6876 I965_RCC_CLOCK_GATE_DISABLE |
6877 I965_RCPB_CLOCK_GATE_DISABLE |
6878 I965_ISC_CLOCK_GATE_DISABLE |
6879 I965_FBC_CLOCK_GATE_DISABLE);
6880 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6881 I915_WRITE(MI_ARB_STATE,
6882 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6883
6884 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6885 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6886}
6887
1fa61106 6888static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6889{
6890 struct drm_i915_private *dev_priv = dev->dev_private;
6891 u32 dstate = I915_READ(D_STATE);
6892
6893 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6894 DSTATE_DOT_CLOCK_GATING;
6895 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6896
6897 if (IS_PINEVIEW(dev))
6898 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6899
6900 /* IIR "flip pending" means done if this bit is set */
6901 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6902
6903 /* interrupts should cause a wake up from C3 */
3299254f 6904 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6905
6906 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6907 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6908
6909 I915_WRITE(MI_ARB_STATE,
6910 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6911}
6912
1fa61106 6913static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6914{
6915 struct drm_i915_private *dev_priv = dev->dev_private;
6916
6917 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6918
6919 /* interrupts should cause a wake up from C3 */
6920 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6921 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6922
6923 I915_WRITE(MEM_MODE,
6924 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6925}
6926
1fa61106 6927static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6928{
6929 struct drm_i915_private *dev_priv = dev->dev_private;
6930
6931 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6932
6933 I915_WRITE(MEM_MODE,
6934 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6935 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6936}
6937
6f1d69b0
ED		 6938void intel_init_clock_gating(struct drm_device *dev)
6939{
6940 struct drm_i915_private *dev_priv = dev->dev_private;
6941
c57e3551
DL		 6942 if (dev_priv->display.init_clock_gating)
6943 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6944}
6945
7d708ee4
ID		 6946void intel_suspend_hw(struct drm_device *dev)
6947{
6948 if (HAS_PCH_LPT(dev))
6949 lpt_suspend_hw(dev);
6950}
6951
1fa61106
ED		 6952/* Set up chip specific power management-related functions */
6953void intel_init_pm(struct drm_device *dev)
6954{
6955 struct drm_i915_private *dev_priv = dev->dev_private;
6956
7ff0ebcc 6957 intel_fbc_init(dev_priv);
1fa61106 6958
c921aba8
DV		 6959 /* For cxsr */
6960 if (IS_PINEVIEW(dev))
6961 i915_pineview_get_mem_freq(dev);
6962 else if (IS_GEN5(dev))
6963 i915_ironlake_get_mem_freq(dev);
6964
1fa61106 6965 /* For FIFO watermark updates */
f5ed50cb 6966 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6967 skl_setup_wm_latency(dev);
6968
a82abe43
ID		 6969 if (IS_BROXTON(dev))
6970 dev_priv->display.init_clock_gating =
6971 bxt_init_clock_gating;
2d41c0b5 6972 dev_priv->display.update_wm = skl_update_wm;
c83155a6 6973 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6974 ilk_setup_wm_latency(dev);
53615a5e 6975
bd602544
VS		 6976 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6977 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6978 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6979 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6980 dev_priv->display.update_wm = ilk_update_wm;
bd602544
VS		 6981 } else {
6982 DRM_DEBUG_KMS("Failed to read display plane latency. "
6983 "Disable CxSR\n");
6984 }
6985
6986 if (IS_GEN5(dev))
1fa61106 6987 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6988 else if (IS_GEN6(dev))
1fa61106 6989 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6990 else if (IS_IVYBRIDGE(dev))
1fa61106 6991 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6992 else if (IS_HASWELL(dev))
cad2a2d7 6993 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6994 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6995 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6996 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 6997 vlv_setup_wm_latency(dev);
6998
6999 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7000 dev_priv->display.init_clock_gating =
7001 cherryview_init_clock_gating;
1fa61106 7002 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7003 vlv_setup_wm_latency(dev);
7004
7005 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7006 dev_priv->display.init_clock_gating =
7007 valleyview_init_clock_gating;
1fa61106
ED		 7008 } else if (IS_PINEVIEW(dev)) {
7009 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7010 dev_priv->is_ddr3,
7011 dev_priv->fsb_freq,
7012 dev_priv->mem_freq)) {
7013 DRM_INFO("failed to find known CxSR latency "
7014 "(found ddr%s fsb freq %d, mem freq %d), "
7015 "disabling CxSR\n",
7016 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7017 dev_priv->fsb_freq, dev_priv->mem_freq);
7018 /* Disable CxSR and never update its watermark again */
5209b1f4 7019 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7020 dev_priv->display.update_wm = NULL;
7021 } else
7022 dev_priv->display.update_wm = pineview_update_wm;
7023 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7024 } else if (IS_G4X(dev)) {
7025 dev_priv->display.update_wm = g4x_update_wm;
7026 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7027 } else if (IS_GEN4(dev)) {
7028 dev_priv->display.update_wm = i965_update_wm;
7029 if (IS_CRESTLINE(dev))
7030 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7031 else if (IS_BROADWATER(dev))
7032 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7033 } else if (IS_GEN3(dev)) {
7034 dev_priv->display.update_wm = i9xx_update_wm;
7035 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7036 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7037 } else if (IS_GEN2(dev)) {
7038 if (INTEL_INFO(dev)->num_pipes == 1) {
7039 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7040 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7041 } else {
7042 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7043 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7044 }
7045
7046 if (IS_I85X(dev) || IS_I865G(dev))
7047 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7048 else
7049 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7050 } else {
7051 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7052 }
7053}
7054
151a49d0 7055int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7056{
4fc688ce 7057 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7058
7059 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7060 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7061 return -EAGAIN;
7062 }
7063
7064 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7065 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7066 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7067
7068 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7069 500)) {
7070 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7071 return -ETIMEDOUT;
7072 }
7073
7074 *val = I915_READ(GEN6_PCODE_DATA);
7075 I915_WRITE(GEN6_PCODE_DATA, 0);
7076
7077 return 0;
7078}
7079
151a49d0 7080int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7081{
4fc688ce 7082 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7083
7084 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7085 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7086 return -EAGAIN;
7087 }
7088
7089 I915_WRITE(GEN6_PCODE_DATA, val);
7090 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7091
7092 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7093 500)) {
7094 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7095 return -ETIMEDOUT;
7096 }
7097
7098 I915_WRITE(GEN6_PCODE_DATA, 0);
7099
7100 return 0;
7101}
a0e4e199 7102
dd06f88c 7103static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7104{
dd06f88c
VS		 7105 switch (czclk_freq) {
7106 case 200:
7107 return 10;
7108 case 267:
7109 return 12;
7110 case 320:
7111 case 333:
dd06f88c 7112 return 16;
ab3fb157
VS		 7113 case 400:
7114 return 20;
855ba3be
JB		 7115 default:
7116 return -1;
7117 }
dd06f88c 7118}
855ba3be 7119
dd06f88c
VS		 7120static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7121{
bfa7df01 7122 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7123
7124 div = vlv_gpu_freq_div(czclk_freq);
7125 if (div < 0)
7126 return div;
7127
7128 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7129}
7130
b55dd647 7131static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7132{
bfa7df01 7133 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7134
dd06f88c
VS		 7135 mul = vlv_gpu_freq_div(czclk_freq);
7136 if (mul < 0)
7137 return mul;
855ba3be 7138
dd06f88c 7139 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7140}
7141
b55dd647 7142static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7143{
bfa7df01 7144 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7145
dd06f88c
VS		 7146 div = vlv_gpu_freq_div(czclk_freq) / 2;
7147 if (div < 0)
7148 return div;
22b1b2f8 7149
dd06f88c 7150 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7151}
7152
b55dd647 7153static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7154{
bfa7df01 7155 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7156
dd06f88c
VS		 7157 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7158 if (mul < 0)
7159 return mul;
22b1b2f8 7160
1c14762d 7161 /* CHV needs even values */
dd06f88c 7162 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7163}
7164
616bc820 7165int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7166{
80b6dda4
AG		 7167 if (IS_GEN9(dev_priv->dev))
7168 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7169 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7170 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7171 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7172 return byt_gpu_freq(dev_priv, val);
7173 else
7174 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7175}
7176
616bc820
VS		 7177int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7178{
80b6dda4
AG		 7179 if (IS_GEN9(dev_priv->dev))
7180 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7181 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7182 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7183 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7184 return byt_freq_opcode(dev_priv, val);
7185 else
7186 return val / GT_FREQUENCY_MULTIPLIER;
7187}
22b1b2f8 7188
6ad790c0
CW		 7189struct request_boost {
7190 struct work_struct work;
eed29a5b 7191 struct drm_i915_gem_request *req;
6ad790c0
CW		 7192};
7193
7194static void __intel_rps_boost_work(struct work_struct *work)
7195{
7196 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7197 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7198
e61b9958
CW		 7199 if (!i915_gem_request_completed(req, true))
7200 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7201 req->emitted_jiffies);
6ad790c0 7202
e61b9958 7203 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7204 kfree(boost);
7205}
7206
7207void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7208 struct drm_i915_gem_request *req)
6ad790c0
CW		 7209{
7210 struct request_boost *boost;
7211
eed29a5b 7212 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7213 return;
7214
e61b9958
CW		 7215 if (i915_gem_request_completed(req, true))
7216 return;
7217
6ad790c0
CW		 7218 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7219 if (boost == NULL)
7220 return;
7221
eed29a5b
DV		 7222 i915_gem_request_reference(req);
7223 boost->req = req;
6ad790c0
CW		 7224
7225 INIT_WORK(&boost->work, __intel_rps_boost_work);
7226 queue_work(to_i915(dev)->wq, &boost->work);
7227}
7228
f742a552 7229void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7230{
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232
f742a552 7233 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7234 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7235
907b28c5
CW		 7236 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7237 intel_gen6_powersave_work);
1854d5ca 7238 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7239 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7240 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7241
33688d95 7242 dev_priv->pm.suspended = false;
907b28c5 7243}
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