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drm/i915/gen9: Allow skl_allocate_pipe_ddb() to operate on in-flight state (v3)
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
a82abe43
ID		 57static void bxt_init_clock_gating(struct drm_device *dev)
58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
a7546159
NH		 61 /* WaDisableSDEUnitClockGating:bxt */
62 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
63 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
64
32608ca2
ID		 65 /*
66 * FIXME:
868434c5 67 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 68 */
32608ca2 69 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 70 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 71
72 /*
73 * Wa: Backlight PWM may stop in the asserted state, causing backlight
74 * to stay fully on.
75 */
76 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
77 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
78 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 79}
80
c921aba8
DV		 81static void i915_pineview_get_mem_freq(struct drm_device *dev)
82{
50227e1c 83 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 84 u32 tmp;
85
86 tmp = I915_READ(CLKCFG);
87
88 switch (tmp & CLKCFG_FSB_MASK) {
89 case CLKCFG_FSB_533:
90 dev_priv->fsb_freq = 533; /* 133*4 */
91 break;
92 case CLKCFG_FSB_800:
93 dev_priv->fsb_freq = 800; /* 200*4 */
94 break;
95 case CLKCFG_FSB_667:
96 dev_priv->fsb_freq = 667; /* 167*4 */
97 break;
98 case CLKCFG_FSB_400:
99 dev_priv->fsb_freq = 400; /* 100*4 */
100 break;
101 }
102
103 switch (tmp & CLKCFG_MEM_MASK) {
104 case CLKCFG_MEM_533:
105 dev_priv->mem_freq = 533;
106 break;
107 case CLKCFG_MEM_667:
108 dev_priv->mem_freq = 667;
109 break;
110 case CLKCFG_MEM_800:
111 dev_priv->mem_freq = 800;
112 break;
113 }
114
115 /* detect pineview DDR3 setting */
116 tmp = I915_READ(CSHRDDR3CTL);
117 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
118}
119
120static void i915_ironlake_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 123 u16 ddrpll, csipll;
124
125 ddrpll = I915_READ16(DDRMPLL1);
126 csipll = I915_READ16(CSIPLL0);
127
128 switch (ddrpll & 0xff) {
129 case 0xc:
130 dev_priv->mem_freq = 800;
131 break;
132 case 0x10:
133 dev_priv->mem_freq = 1066;
134 break;
135 case 0x14:
136 dev_priv->mem_freq = 1333;
137 break;
138 case 0x18:
139 dev_priv->mem_freq = 1600;
140 break;
141 default:
142 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
143 ddrpll & 0xff);
144 dev_priv->mem_freq = 0;
145 break;
146 }
147
20e4d407 148 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 149
150 switch (csipll & 0x3ff) {
151 case 0x00c:
152 dev_priv->fsb_freq = 3200;
153 break;
154 case 0x00e:
155 dev_priv->fsb_freq = 3733;
156 break;
157 case 0x010:
158 dev_priv->fsb_freq = 4266;
159 break;
160 case 0x012:
161 dev_priv->fsb_freq = 4800;
162 break;
163 case 0x014:
164 dev_priv->fsb_freq = 5333;
165 break;
166 case 0x016:
167 dev_priv->fsb_freq = 5866;
168 break;
169 case 0x018:
170 dev_priv->fsb_freq = 6400;
171 break;
172 default:
173 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
174 csipll & 0x3ff);
175 dev_priv->fsb_freq = 0;
176 break;
177 }
178
179 if (dev_priv->fsb_freq == 3200) {
20e4d407 180 dev_priv->ips.c_m = 0;
c921aba8 181 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 182 dev_priv->ips.c_m = 1;
c921aba8 183 } else {
20e4d407 184 dev_priv->ips.c_m = 2;
c921aba8
DV		 185 }
186}
187
b445e3b0
ED		 188static const struct cxsr_latency cxsr_latency_table[] = {
189 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
190 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
191 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
192 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
193 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
194
195 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
196 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
197 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
198 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
199 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
200
201 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
202 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
203 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
204 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
205 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
206
207 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
208 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
209 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
210 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
211 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
212
213 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
214 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
215 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
216 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
217 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
218
219 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
220 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
221 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
222 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
223 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
224};
225
63c62275 226static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 227 int is_ddr3,
228 int fsb,
229 int mem)
230{
231 const struct cxsr_latency *latency;
232 int i;
233
234 if (fsb == 0 || mem == 0)
235 return NULL;
236
237 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
238 latency = &cxsr_latency_table[i];
239 if (is_desktop == latency->is_desktop &&
240 is_ddr3 == latency->is_ddr3 &&
241 fsb == latency->fsb_freq && mem == latency->mem_freq)
242 return latency;
243 }
244
245 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
246
247 return NULL;
248}
249
fc1ac8de
VS		 250static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
251{
252 u32 val;
253
254 mutex_lock(&dev_priv->rps.hw_lock);
255
256 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
257 if (enable)
258 val &= ~FORCE_DDR_HIGH_FREQ;
259 else
260 val |= FORCE_DDR_HIGH_FREQ;
261 val &= ~FORCE_DDR_LOW_FREQ;
262 val |= FORCE_DDR_FREQ_REQ_ACK;
263 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
264
265 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
266 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
267 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
268
269 mutex_unlock(&dev_priv->rps.hw_lock);
270}
271
cfb41411
VS		 272static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
273{
274 u32 val;
275
276 mutex_lock(&dev_priv->rps.hw_lock);
277
278 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
279 if (enable)
280 val |= DSP_MAXFIFO_PM5_ENABLE;
281 else
282 val &= ~DSP_MAXFIFO_PM5_ENABLE;
283 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
284
285 mutex_unlock(&dev_priv->rps.hw_lock);
286}
287
f4998963
VS		 288#define FW_WM(value, plane) \
289 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
290
5209b1f4 291void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 292{
5209b1f4
ID		 293 struct drm_device *dev = dev_priv->dev;
294 u32 val;
b445e3b0 295
666a4537 296 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 297 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 298 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 299 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 300 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
301 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 302 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 303 } else if (IS_PINEVIEW(dev)) {
304 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
305 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
306 I915_WRITE(DSPFW3, val);
a7a6c498 307 POSTING_READ(DSPFW3);
5209b1f4
ID		 308 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
309 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
310 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
311 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 312 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 313 } else if (IS_I915GM(dev)) {
314 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
315 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
316 I915_WRITE(INSTPM, val);
a7a6c498 317 POSTING_READ(INSTPM);
5209b1f4
ID		 318 } else {
319 return;
320 }
b445e3b0 321
5209b1f4
ID		 322 DRM_DEBUG_KMS("memory self-refresh is %s\n",
323 enable ? "enabled" : "disabled");
b445e3b0
ED		 324}
325
fc1ac8de 326
b445e3b0
ED		 327/*
328 * Latency for FIFO fetches is dependent on several factors:
329 * - memory configuration (speed, channels)
330 * - chipset
331 * - current MCH state
332 * It can be fairly high in some situations, so here we assume a fairly
333 * pessimal value. It's a tradeoff between extra memory fetches (if we
334 * set this value too high, the FIFO will fetch frequently to stay full)
335 * and power consumption (set it too low to save power and we might see
336 * FIFO underruns and display "flicker").
337 *
338 * A value of 5us seems to be a good balance; safe for very low end
339 * platforms but not overly aggressive on lower latency configs.
340 */
5aef6003 341static const int pessimal_latency_ns = 5000;
b445e3b0 342
b5004720
VS		 343#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
344 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
345
346static int vlv_get_fifo_size(struct drm_device *dev,
347 enum pipe pipe, int plane)
348{
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int sprite0_start, sprite1_start, size;
351
352 switch (pipe) {
353 uint32_t dsparb, dsparb2, dsparb3;
354 case PIPE_A:
355 dsparb = I915_READ(DSPARB);
356 dsparb2 = I915_READ(DSPARB2);
357 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
358 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
359 break;
360 case PIPE_B:
361 dsparb = I915_READ(DSPARB);
362 dsparb2 = I915_READ(DSPARB2);
363 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
364 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
365 break;
366 case PIPE_C:
367 dsparb2 = I915_READ(DSPARB2);
368 dsparb3 = I915_READ(DSPARB3);
369 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
370 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
371 break;
372 default:
373 return 0;
374 }
375
376 switch (plane) {
377 case 0:
378 size = sprite0_start;
379 break;
380 case 1:
381 size = sprite1_start - sprite0_start;
382 break;
383 case 2:
384 size = 512 - 1 - sprite1_start;
385 break;
386 default:
387 return 0;
388 }
389
390 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
391 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
392 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
393 size);
394
395 return size;
396}
397
1fa61106 398static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t dsparb = I915_READ(DSPARB);
402 int size;
403
404 size = dsparb & 0x7f;
405 if (plane)
406 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
407
408 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
409 plane ? "B" : "A", size);
410
411 return size;
412}
413
feb56b93 414static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 415{
416 struct drm_i915_private *dev_priv = dev->dev_private;
417 uint32_t dsparb = I915_READ(DSPARB);
418 int size;
419
420 size = dsparb & 0x1ff;
421 if (plane)
422 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
423 size >>= 1; /* Convert to cachelines */
424
425 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
426 plane ? "B" : "A", size);
427
428 return size;
429}
430
1fa61106 431static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 432{
433 struct drm_i915_private *dev_priv = dev->dev_private;
434 uint32_t dsparb = I915_READ(DSPARB);
435 int size;
436
437 size = dsparb & 0x7f;
438 size >>= 2; /* Convert to cachelines */
439
440 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
441 plane ? "B" : "A",
442 size);
443
444 return size;
445}
446
b445e3b0
ED		 447/* Pineview has different values for various configs */
448static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 449 .fifo_size = PINEVIEW_DISPLAY_FIFO,
450 .max_wm = PINEVIEW_MAX_WM,
451 .default_wm = PINEVIEW_DFT_WM,
452 .guard_size = PINEVIEW_GUARD_WM,
453 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 454};
455static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 456 .fifo_size = PINEVIEW_DISPLAY_FIFO,
457 .max_wm = PINEVIEW_MAX_WM,
458 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
459 .guard_size = PINEVIEW_GUARD_WM,
460 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 461};
462static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_CURSOR_FIFO,
464 .max_wm = PINEVIEW_CURSOR_MAX_WM,
465 .default_wm = PINEVIEW_CURSOR_DFT_WM,
466 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_CURSOR_FIFO,
471 .max_wm = PINEVIEW_CURSOR_MAX_WM,
472 .default_wm = PINEVIEW_CURSOR_DFT_WM,
473 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 477 .fifo_size = G4X_FIFO_SIZE,
478 .max_wm = G4X_MAX_WM,
479 .default_wm = G4X_MAX_WM,
480 .guard_size = 2,
481 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 484 .fifo_size = I965_CURSOR_FIFO,
485 .max_wm = I965_CURSOR_MAX_WM,
486 .default_wm = I965_CURSOR_DFT_WM,
487 .guard_size = 2,
488 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 489};
b445e3b0 490static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 491 .fifo_size = I965_CURSOR_FIFO,
492 .max_wm = I965_CURSOR_MAX_WM,
493 .default_wm = I965_CURSOR_DFT_WM,
494 .guard_size = 2,
495 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 498 .fifo_size = I945_FIFO_SIZE,
499 .max_wm = I915_MAX_WM,
500 .default_wm = 1,
501 .guard_size = 2,
502 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 503};
504static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 505 .fifo_size = I915_FIFO_SIZE,
506 .max_wm = I915_MAX_WM,
507 .default_wm = 1,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 510};
9d539105 511static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 512 .fifo_size = I855GM_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 517};
9d539105
VS		 518static const struct intel_watermark_params i830_bc_wm_info = {
519 .fifo_size = I855GM_FIFO_SIZE,
520 .max_wm = I915_MAX_WM/2,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I830_FIFO_LINE_SIZE,
524};
feb56b93 525static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 526 .fifo_size = I830_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 531};
532
b445e3b0
ED		 533/**
534 * intel_calculate_wm - calculate watermark level
535 * @clock_in_khz: pixel clock
536 * @wm: chip FIFO params
ac484963 537 * @cpp: bytes per pixel
b445e3b0
ED		 538 * @latency_ns: memory latency for the platform
539 *
540 * Calculate the watermark level (the level at which the display plane will
541 * start fetching from memory again). Each chip has a different display
542 * FIFO size and allocation, so the caller needs to figure that out and pass
543 * in the correct intel_watermark_params structure.
544 *
545 * As the pixel clock runs, the FIFO will be drained at a rate that depends
546 * on the pixel size. When it reaches the watermark level, it'll start
547 * fetching FIFO line sized based chunks from memory until the FIFO fills
548 * past the watermark point. If the FIFO drains completely, a FIFO underrun
549 * will occur, and a display engine hang could result.
550 */
551static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
552 const struct intel_watermark_params *wm,
ac484963 553 int fifo_size, int cpp,
b445e3b0
ED		 554 unsigned long latency_ns)
555{
556 long entries_required, wm_size;
557
558 /*
559 * Note: we need to make sure we don't overflow for various clock &
560 * latency values.
561 * clocks go from a few thousand to several hundred thousand.
562 * latency is usually a few thousand
563 */
ac484963 564 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 565 1000;
566 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
567
568 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
569
570 wm_size = fifo_size - (entries_required + wm->guard_size);
571
572 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
573
574 /* Don't promote wm_size to unsigned... */
575 if (wm_size > (long)wm->max_wm)
576 wm_size = wm->max_wm;
577 if (wm_size <= 0)
578 wm_size = wm->default_wm;
d6feb196
VS		 579
580 /*
581 * Bspec seems to indicate that the value shouldn't be lower than
582 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
583 * Lets go for 8 which is the burst size since certain platforms
584 * already use a hardcoded 8 (which is what the spec says should be
585 * done).
586 */
587 if (wm_size <= 8)
588 wm_size = 8;
589
b445e3b0
ED		 590 return wm_size;
591}
592
593static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
594{
595 struct drm_crtc *crtc, *enabled = NULL;
596
70e1e0ec 597 for_each_crtc(dev, crtc) {
3490ea5d 598 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 599 if (enabled)
600 return NULL;
601 enabled = crtc;
602 }
603 }
604
605 return enabled;
606}
607
46ba614c 608static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 609{
46ba614c 610 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 611 struct drm_i915_private *dev_priv = dev->dev_private;
612 struct drm_crtc *crtc;
613 const struct cxsr_latency *latency;
614 u32 reg;
615 unsigned long wm;
616
617 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
618 dev_priv->fsb_freq, dev_priv->mem_freq);
619 if (!latency) {
620 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 621 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 622 return;
623 }
624
625 crtc = single_enabled_crtc(dev);
626 if (crtc) {
7c5f93b0 627 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 628 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 629 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 630
631 /* Display SR */
632 wm = intel_calculate_wm(clock, &pineview_display_wm,
633 pineview_display_wm.fifo_size,
ac484963 634 cpp, latency->display_sr);
b445e3b0
ED		 635 reg = I915_READ(DSPFW1);
636 reg &= ~DSPFW_SR_MASK;
f4998963 637 reg |= FW_WM(wm, SR);
b445e3b0
ED		 638 I915_WRITE(DSPFW1, reg);
639 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
640
641 /* cursor SR */
642 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
643 pineview_display_wm.fifo_size,
ac484963 644 cpp, latency->cursor_sr);
b445e3b0
ED		 645 reg = I915_READ(DSPFW3);
646 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 647 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 648 I915_WRITE(DSPFW3, reg);
649
650 /* Display HPLL off SR */
651 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
652 pineview_display_hplloff_wm.fifo_size,
ac484963 653 cpp, latency->display_hpll_disable);
b445e3b0
ED		 654 reg = I915_READ(DSPFW3);
655 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 656 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 657 I915_WRITE(DSPFW3, reg);
658
659 /* cursor HPLL off SR */
660 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
661 pineview_display_hplloff_wm.fifo_size,
ac484963 662 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 663 reg = I915_READ(DSPFW3);
664 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 665 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 666 I915_WRITE(DSPFW3, reg);
667 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
668
5209b1f4 669 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 670 } else {
5209b1f4 671 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 672 }
673}
674
675static bool g4x_compute_wm0(struct drm_device *dev,
676 int plane,
677 const struct intel_watermark_params *display,
678 int display_latency_ns,
679 const struct intel_watermark_params *cursor,
680 int cursor_latency_ns,
681 int *plane_wm,
682 int *cursor_wm)
683{
684 struct drm_crtc *crtc;
4fe8590a 685 const struct drm_display_mode *adjusted_mode;
ac484963 686 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 687 int line_time_us, line_count;
688 int entries, tlb_miss;
689
690 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 691 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 692 *cursor_wm = cursor->guard_size;
693 *plane_wm = display->guard_size;
694 return false;
695 }
696
6e3c9717 697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 698 clock = adjusted_mode->crtc_clock;
fec8cba3 699 htotal = adjusted_mode->crtc_htotal;
6e3c9717 700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 701 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 702
703 /* Use the small buffer method to calculate plane watermark */
ac484963 704 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 705 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
706 if (tlb_miss > 0)
707 entries += tlb_miss;
708 entries = DIV_ROUND_UP(entries, display->cacheline_size);
709 *plane_wm = entries + display->guard_size;
710 if (*plane_wm > (int)display->max_wm)
711 *plane_wm = display->max_wm;
712
713 /* Use the large buffer method to calculate cursor watermark */
922044c9 714 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 715 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 716 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 717 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
718 if (tlb_miss > 0)
719 entries += tlb_miss;
720 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
721 *cursor_wm = entries + cursor->guard_size;
722 if (*cursor_wm > (int)cursor->max_wm)
723 *cursor_wm = (int)cursor->max_wm;
724
725 return true;
726}
727
728/*
729 * Check the wm result.
730 *
731 * If any calculated watermark values is larger than the maximum value that
732 * can be programmed into the associated watermark register, that watermark
733 * must be disabled.
734 */
735static bool g4x_check_srwm(struct drm_device *dev,
736 int display_wm, int cursor_wm,
737 const struct intel_watermark_params *display,
738 const struct intel_watermark_params *cursor)
739{
740 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
741 display_wm, cursor_wm);
742
743 if (display_wm > display->max_wm) {
744 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
745 display_wm, display->max_wm);
746 return false;
747 }
748
749 if (cursor_wm > cursor->max_wm) {
750 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
751 cursor_wm, cursor->max_wm);
752 return false;
753 }
754
755 if (!(display_wm || cursor_wm)) {
756 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
757 return false;
758 }
759
760 return true;
761}
762
763static bool g4x_compute_srwm(struct drm_device *dev,
764 int plane,
765 int latency_ns,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor,
768 int *display_wm, int *cursor_wm)
769{
770 struct drm_crtc *crtc;
4fe8590a 771 const struct drm_display_mode *adjusted_mode;
ac484963 772 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 773 unsigned long line_time_us;
774 int line_count, line_size;
775 int small, large;
776 int entries;
777
778 if (!latency_ns) {
779 *display_wm = *cursor_wm = 0;
780 return false;
781 }
782
783 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 784 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 785 clock = adjusted_mode->crtc_clock;
fec8cba3 786 htotal = adjusted_mode->crtc_htotal;
6e3c9717 787 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 788 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 789
922044c9 790 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 791 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 792 line_size = hdisplay * cpp;
b445e3b0
ED		 793
794 /* Use the minimum of the small and large buffer method for primary */
ac484963 795 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 796 large = line_count * line_size;
797
798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
799 *display_wm = entries + display->guard_size;
800
801 /* calculate the self-refresh watermark for display cursor */
ac484963 802 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 803 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
804 *cursor_wm = entries + cursor->guard_size;
805
806 return g4x_check_srwm(dev,
807 *display_wm, *cursor_wm,
808 display, cursor);
809}
810
15665979
VS		 811#define FW_WM_VLV(value, plane) \
812 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
813
0018fda1
VS		 814static void vlv_write_wm_values(struct intel_crtc *crtc,
815 const struct vlv_wm_values *wm)
816{
817 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
818 enum pipe pipe = crtc->pipe;
819
820 I915_WRITE(VLV_DDL(pipe),
821 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
822 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
823 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
824 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
825
ae80152d 826 I915_WRITE(DSPFW1,
15665979
VS		 827 FW_WM(wm->sr.plane, SR) |
828 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
829 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
830 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 831 I915_WRITE(DSPFW2,
15665979
VS		 832 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
833 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
834 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 835 I915_WRITE(DSPFW3,
15665979 836 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 837
838 if (IS_CHERRYVIEW(dev_priv)) {
839 I915_WRITE(DSPFW7_CHV,
15665979
VS		 840 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
841 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 842 I915_WRITE(DSPFW8_CHV,
15665979
VS		 843 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
844 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 845 I915_WRITE(DSPFW9_CHV,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
847 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 848 I915_WRITE(DSPHOWM,
15665979
VS		 849 FW_WM(wm->sr.plane >> 9, SR_HI) |
850 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
851 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
852 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
853 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
854 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
855 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
856 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
857 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
858 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 859 } else {
860 I915_WRITE(DSPFW7,
15665979
VS		 861 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
862 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 863 I915_WRITE(DSPHOWM,
15665979
VS		 864 FW_WM(wm->sr.plane >> 9, SR_HI) |
865 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
868 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
870 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 871 }
872
2cb389b7
VS		 873 /* zero (unused) WM1 watermarks */
874 I915_WRITE(DSPFW4, 0);
875 I915_WRITE(DSPFW5, 0);
876 I915_WRITE(DSPFW6, 0);
877 I915_WRITE(DSPHOWM1, 0);
878
ae80152d 879 POSTING_READ(DSPFW1);
0018fda1
VS		 880}
881
15665979
VS		 882#undef FW_WM_VLV
883
6eb1a681
VS		 884enum vlv_wm_level {
885 VLV_WM_LEVEL_PM2,
886 VLV_WM_LEVEL_PM5,
887 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 888};
889
262cd2e1
VS		 890/* latency must be in 0.1us units. */
891static unsigned int vlv_wm_method2(unsigned int pixel_rate,
892 unsigned int pipe_htotal,
893 unsigned int horiz_pixels,
ac484963 894 unsigned int cpp,
262cd2e1
VS		 895 unsigned int latency)
896{
897 unsigned int ret;
898
899 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 900 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 901 ret = DIV_ROUND_UP(ret, 64);
902
903 return ret;
904}
905
906static void vlv_setup_wm_latency(struct drm_device *dev)
907{
908 struct drm_i915_private *dev_priv = dev->dev_private;
909
910 /* all latencies in usec */
911 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
912
58590c14
VS		 913 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
914
262cd2e1
VS		 915 if (IS_CHERRYVIEW(dev_priv)) {
916 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
917 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 918
919 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 920 }
921}
922
923static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
924 struct intel_crtc *crtc,
925 const struct intel_plane_state *state,
926 int level)
927{
928 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 929 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 930
931 if (dev_priv->wm.pri_latency[level] == 0)
932 return USHRT_MAX;
933
934 if (!state->visible)
935 return 0;
936
ac484963 937 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 938 clock = crtc->config->base.adjusted_mode.crtc_clock;
939 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
940 width = crtc->config->pipe_src_w;
941 if (WARN_ON(htotal == 0))
942 htotal = 1;
943
944 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
945 /*
946 * FIXME the formula gives values that are
947 * too big for the cursor FIFO, and hence we
948 * would never be able to use cursors. For
949 * now just hardcode the watermark.
950 */
951 wm = 63;
952 } else {
ac484963 953 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 954 dev_priv->wm.pri_latency[level] * 10);
955 }
956
957 return min_t(int, wm, USHRT_MAX);
958}
959
54f1b6e1
VS		 960static void vlv_compute_fifo(struct intel_crtc *crtc)
961{
962 struct drm_device *dev = crtc->base.dev;
963 struct vlv_wm_state *wm_state = &crtc->wm_state;
964 struct intel_plane *plane;
965 unsigned int total_rate = 0;
966 const int fifo_size = 512 - 1;
967 int fifo_extra, fifo_left = fifo_size;
968
969 for_each_intel_plane_on_crtc(dev, crtc, plane) {
970 struct intel_plane_state *state =
971 to_intel_plane_state(plane->base.state);
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
974 continue;
975
976 if (state->visible) {
977 wm_state->num_active_planes++;
978 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
979 }
980 }
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985 unsigned int rate;
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
988 plane->wm.fifo_size = 63;
989 continue;
990 }
991
992 if (!state->visible) {
993 plane->wm.fifo_size = 0;
994 continue;
995 }
996
997 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
998 plane->wm.fifo_size = fifo_size * rate / total_rate;
999 fifo_left -= plane->wm.fifo_size;
1000 }
1001
1002 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004 /* spread the remainder evenly */
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 int plane_extra;
1007
1008 if (fifo_left == 0)
1009 break;
1010
1011 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012 continue;
1013
1014 /* give it all to the first plane if none are active */
1015 if (plane->wm.fifo_size == 0 &&
1016 wm_state->num_active_planes)
1017 continue;
1018
1019 plane_extra = min(fifo_extra, fifo_left);
1020 plane->wm.fifo_size += plane_extra;
1021 fifo_left -= plane_extra;
1022 }
1023
1024 WARN_ON(fifo_left != 0);
1025}
1026
262cd2e1
VS		 1027static void vlv_invert_wms(struct intel_crtc *crtc)
1028{
1029 struct vlv_wm_state *wm_state = &crtc->wm_state;
1030 int level;
1031
1032 for (level = 0; level < wm_state->num_levels; level++) {
1033 struct drm_device *dev = crtc->base.dev;
1034 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035 struct intel_plane *plane;
1036
1037 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041 switch (plane->base.type) {
1042 int sprite;
1043 case DRM_PLANE_TYPE_CURSOR:
1044 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045 wm_state->wm[level].cursor;
1046 break;
1047 case DRM_PLANE_TYPE_PRIMARY:
1048 wm_state->wm[level].primary = plane->wm.fifo_size -
1049 wm_state->wm[level].primary;
1050 break;
1051 case DRM_PLANE_TYPE_OVERLAY:
1052 sprite = plane->plane;
1053 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054 wm_state->wm[level].sprite[sprite];
1055 break;
1056 }
1057 }
1058 }
1059}
1060
26e1fe4f 1061static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1062{
1063 struct drm_device *dev = crtc->base.dev;
1064 struct vlv_wm_state *wm_state = &crtc->wm_state;
1065 struct intel_plane *plane;
1066 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067 int level;
1068
1069 memset(wm_state, 0, sizeof(*wm_state));
1070
852eb00d 1071 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1072 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1073
1074 wm_state->num_active_planes = 0;
262cd2e1 1075
54f1b6e1 1076 vlv_compute_fifo(crtc);
262cd2e1
VS		 1077
1078 if (wm_state->num_active_planes != 1)
1079 wm_state->cxsr = false;
1080
1081 if (wm_state->cxsr) {
1082 for (level = 0; level < wm_state->num_levels; level++) {
1083 wm_state->sr[level].plane = sr_fifo_size;
1084 wm_state->sr[level].cursor = 63;
1085 }
1086 }
1087
1088 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089 struct intel_plane_state *state =
1090 to_intel_plane_state(plane->base.state);
1091
1092 if (!state->visible)
1093 continue;
1094
1095 /* normal watermarks */
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100 /* hack */
1101 if (WARN_ON(level == 0 && wm > max_wm))
1102 wm = max_wm;
1103
1104 if (wm > plane->wm.fifo_size)
1105 break;
1106
1107 switch (plane->base.type) {
1108 int sprite;
1109 case DRM_PLANE_TYPE_CURSOR:
1110 wm_state->wm[level].cursor = wm;
1111 break;
1112 case DRM_PLANE_TYPE_PRIMARY:
1113 wm_state->wm[level].primary = wm;
1114 break;
1115 case DRM_PLANE_TYPE_OVERLAY:
1116 sprite = plane->plane;
1117 wm_state->wm[level].sprite[sprite] = wm;
1118 break;
1119 }
1120 }
1121
1122 wm_state->num_levels = level;
1123
1124 if (!wm_state->cxsr)
1125 continue;
1126
1127 /* maxfifo watermarks */
1128 switch (plane->base.type) {
1129 int sprite, level;
1130 case DRM_PLANE_TYPE_CURSOR:
1131 for (level = 0; level < wm_state->num_levels; level++)
1132 wm_state->sr[level].cursor =
5a37ed0a 1133 wm_state->wm[level].cursor;
262cd2e1
VS		 1134 break;
1135 case DRM_PLANE_TYPE_PRIMARY:
1136 for (level = 0; level < wm_state->num_levels; level++)
1137 wm_state->sr[level].plane =
1138 min(wm_state->sr[level].plane,
1139 wm_state->wm[level].primary);
1140 break;
1141 case DRM_PLANE_TYPE_OVERLAY:
1142 sprite = plane->plane;
1143 for (level = 0; level < wm_state->num_levels; level++)
1144 wm_state->sr[level].plane =
1145 min(wm_state->sr[level].plane,
1146 wm_state->wm[level].sprite[sprite]);
1147 break;
1148 }
1149 }
1150
1151 /* clear any (partially) filled invalid levels */
58590c14 1152 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1153 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155 }
1156
1157 vlv_invert_wms(crtc);
1158}
1159
54f1b6e1
VS		 1160#define VLV_FIFO(plane, value) \
1161 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164{
1165 struct drm_device *dev = crtc->base.dev;
1166 struct drm_i915_private *dev_priv = to_i915(dev);
1167 struct intel_plane *plane;
1168 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172 WARN_ON(plane->wm.fifo_size != 63);
1173 continue;
1174 }
1175
1176 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177 sprite0_start = plane->wm.fifo_size;
1178 else if (plane->plane == 0)
1179 sprite1_start = sprite0_start + plane->wm.fifo_size;
1180 else
1181 fifo_size = sprite1_start + plane->wm.fifo_size;
1182 }
1183
1184 WARN_ON(fifo_size != 512 - 1);
1185
1186 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187 pipe_name(crtc->pipe), sprite0_start,
1188 sprite1_start, fifo_size);
1189
1190 switch (crtc->pipe) {
1191 uint32_t dsparb, dsparb2, dsparb3;
1192 case PIPE_A:
1193 dsparb = I915_READ(DSPARB);
1194 dsparb2 = I915_READ(DSPARB2);
1195
1196 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197 VLV_FIFO(SPRITEB, 0xff));
1198 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199 VLV_FIFO(SPRITEB, sprite1_start));
1200
1201 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202 VLV_FIFO(SPRITEB_HI, 0x1));
1203 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206 I915_WRITE(DSPARB, dsparb);
1207 I915_WRITE(DSPARB2, dsparb2);
1208 break;
1209 case PIPE_B:
1210 dsparb = I915_READ(DSPARB);
1211 dsparb2 = I915_READ(DSPARB2);
1212
1213 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214 VLV_FIFO(SPRITED, 0xff));
1215 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216 VLV_FIFO(SPRITED, sprite1_start));
1217
1218 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219 VLV_FIFO(SPRITED_HI, 0xff));
1220 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223 I915_WRITE(DSPARB, dsparb);
1224 I915_WRITE(DSPARB2, dsparb2);
1225 break;
1226 case PIPE_C:
1227 dsparb3 = I915_READ(DSPARB3);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231 VLV_FIFO(SPRITEF, 0xff));
1232 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233 VLV_FIFO(SPRITEF, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236 VLV_FIFO(SPRITEF_HI, 0xff));
1237 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB3, dsparb3);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 default:
1244 break;
1245 }
1246}
1247
1248#undef VLV_FIFO
1249
262cd2e1
VS		 1250static void vlv_merge_wm(struct drm_device *dev,
1251 struct vlv_wm_values *wm)
1252{
1253 struct intel_crtc *crtc;
1254 int num_active_crtcs = 0;
1255
58590c14 1256 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1257 wm->cxsr = true;
1258
1259 for_each_intel_crtc(dev, crtc) {
1260 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262 if (!crtc->active)
1263 continue;
1264
1265 if (!wm_state->cxsr)
1266 wm->cxsr = false;
1267
1268 num_active_crtcs++;
1269 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270 }
1271
1272 if (num_active_crtcs != 1)
1273 wm->cxsr = false;
1274
6f9c784b
VS		 1275 if (num_active_crtcs > 1)
1276 wm->level = VLV_WM_LEVEL_PM2;
1277
262cd2e1
VS		 1278 for_each_intel_crtc(dev, crtc) {
1279 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280 enum pipe pipe = crtc->pipe;
1281
1282 if (!crtc->active)
1283 continue;
1284
1285 wm->pipe[pipe] = wm_state->wm[wm->level];
1286 if (wm->cxsr)
1287 wm->sr = wm_state->sr[wm->level];
1288
1289 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293 }
1294}
1295
1296static void vlv_update_wm(struct drm_crtc *crtc)
1297{
1298 struct drm_device *dev = crtc->dev;
1299 struct drm_i915_private *dev_priv = dev->dev_private;
1300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301 enum pipe pipe = intel_crtc->pipe;
1302 struct vlv_wm_values wm = {};
1303
26e1fe4f 1304 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1305 vlv_merge_wm(dev, &wm);
1306
54f1b6e1
VS		 1307 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308 /* FIXME should be part of crtc atomic commit */
1309 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1310 return;
54f1b6e1 1311 }
262cd2e1
VS		 1312
1313 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315 chv_set_memory_dvfs(dev_priv, false);
1316
1317 if (wm.level < VLV_WM_LEVEL_PM5 &&
1318 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319 chv_set_memory_pm5(dev_priv, false);
1320
852eb00d 1321 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1322 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1323
54f1b6e1
VS		 1324 /* FIXME should be part of crtc atomic commit */
1325 vlv_pipe_set_fifo_size(intel_crtc);
1326
262cd2e1
VS		 1327 vlv_write_wm_values(intel_crtc, &wm);
1328
1329 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
852eb00d 1335 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1337
1338 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340 chv_set_memory_pm5(dev_priv, true);
1341
1342 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344 chv_set_memory_dvfs(dev_priv, true);
1345
1346 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1347}
1348
ae80152d
VS		 1349#define single_plane_enabled(mask) is_power_of_2(mask)
1350
46ba614c 1351static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1352{
46ba614c 1353 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
9858425c 1359 bool cxsr_enabled;
b445e3b0 1360
51cea1f4 1361 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1362 &g4x_wm_info, pessimal_latency_ns,
1363 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1364 &planea_wm, &cursora_wm))
51cea1f4 1365 enabled |= 1 << PIPE_A;
b445e3b0 1366
51cea1f4 1367 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1368 &g4x_wm_info, pessimal_latency_ns,
1369 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1370 &planeb_wm, &cursorb_wm))
51cea1f4 1371 enabled |= 1 << PIPE_B;
b445e3b0 1372
b445e3b0
ED		 1373 if (single_plane_enabled(enabled) &&
1374 g4x_compute_srwm(dev, ffs(enabled) - 1,
1375 sr_latency_ns,
1376 &g4x_wm_info,
1377 &g4x_cursor_wm_info,
52bd02d8 1378 &plane_sr, &cursor_sr)) {
9858425c 1379 cxsr_enabled = true;
52bd02d8 1380 } else {
9858425c 1381 cxsr_enabled = false;
5209b1f4 1382 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1383 plane_sr = cursor_sr = 0;
1384 }
b445e3b0 1385
a5043453
VS		 1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1388 planea_wm, cursora_wm,
1389 planeb_wm, cursorb_wm,
1390 plane_sr, cursor_sr);
1391
1392 I915_WRITE(DSPFW1,
f4998963
VS		 1393 FW_WM(plane_sr, SR) |
1394 FW_WM(cursorb_wm, CURSORB) |
1395 FW_WM(planeb_wm, PLANEB) |
1396 FW_WM(planea_wm, PLANEA));
b445e3b0 1397 I915_WRITE(DSPFW2,
8c919b28 1398 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1399 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1400 /* HPLL off in SR has some issues on G4x... disable it */
1401 I915_WRITE(DSPFW3,
8c919b28 1402 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1403 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1404
1405 if (cxsr_enabled)
1406 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1407}
1408
46ba614c 1409static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1410{
46ba614c 1411 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 struct drm_crtc *crtc;
1414 int srwm = 1;
1415 int cursor_sr = 16;
9858425c 1416 bool cxsr_enabled;
b445e3b0
ED		 1417
1418 /* Calc sr entries for one plane configs */
1419 crtc = single_enabled_crtc(dev);
1420 if (crtc) {
1421 /* self-refresh has much higher latency */
1422 static const int sr_latency_ns = 12000;
124abe07 1423 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1424 int clock = adjusted_mode->crtc_clock;
fec8cba3 1425 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1426 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1427 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1428 unsigned long line_time_us;
1429 int entries;
1430
922044c9 1431 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1432
1433 /* Use ns/us then divide to preserve precision */
1434 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1435 cpp * hdisplay;
b445e3b0
ED		 1436 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437 srwm = I965_FIFO_SIZE - entries;
1438 if (srwm < 0)
1439 srwm = 1;
1440 srwm &= 0x1ff;
1441 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442 entries, srwm);
1443
1444 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1445 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1446 entries = DIV_ROUND_UP(entries,
1447 i965_cursor_wm_info.cacheline_size);
1448 cursor_sr = i965_cursor_wm_info.fifo_size -
1449 (entries + i965_cursor_wm_info.guard_size);
1450
1451 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452 cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455 "cursor %d\n", srwm, cursor_sr);
1456
9858425c 1457 cxsr_enabled = true;
b445e3b0 1458 } else {
9858425c 1459 cxsr_enabled = false;
b445e3b0 1460 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1461 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1462 }
1463
1464 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465 srwm);
1466
1467 /* 965 has limitations... */
f4998963
VS		 1468 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469 FW_WM(8, CURSORB) |
1470 FW_WM(8, PLANEB) |
1471 FW_WM(8, PLANEA));
1472 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473 FW_WM(8, PLANEC_OLD));
b445e3b0 1474 /* update cursor SR watermark */
f4998963 1475 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1476
1477 if (cxsr_enabled)
1478 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1479}
1480
f4998963
VS		 1481#undef FW_WM
1482
46ba614c 1483static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1484{
46ba614c 1485 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 const struct intel_watermark_params *wm_info;
1488 uint32_t fwater_lo;
1489 uint32_t fwater_hi;
1490 int cwm, srwm = 1;
1491 int fifo_size;
1492 int planea_wm, planeb_wm;
1493 struct drm_crtc *crtc, *enabled = NULL;
1494
1495 if (IS_I945GM(dev))
1496 wm_info = &i945_wm_info;
1497 else if (!IS_GEN2(dev))
1498 wm_info = &i915_wm_info;
1499 else
9d539105 1500 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1501
1502 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1504 if (intel_crtc_active(crtc)) {
241bfc38 1505 const struct drm_display_mode *adjusted_mode;
ac484963 1506 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1507 if (IS_GEN2(dev))
1508 cpp = 4;
1509
6e3c9717 1510 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1511 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1512 wm_info, fifo_size, cpp,
5aef6003 1513 pessimal_latency_ns);
b445e3b0 1514 enabled = crtc;
9d539105 1515 } else {
b445e3b0 1516 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1517 if (planea_wm > (long)wm_info->max_wm)
1518 planea_wm = wm_info->max_wm;
1519 }
1520
1521 if (IS_GEN2(dev))
1522 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1523
1524 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1526 if (intel_crtc_active(crtc)) {
241bfc38 1527 const struct drm_display_mode *adjusted_mode;
ac484963 1528 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1529 if (IS_GEN2(dev))
1530 cpp = 4;
1531
6e3c9717 1532 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1533 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1534 wm_info, fifo_size, cpp,
5aef6003 1535 pessimal_latency_ns);
b445e3b0
ED		 1536 if (enabled == NULL)
1537 enabled = crtc;
1538 else
1539 enabled = NULL;
9d539105 1540 } else {
b445e3b0 1541 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1542 if (planeb_wm > (long)wm_info->max_wm)
1543 planeb_wm = wm_info->max_wm;
1544 }
b445e3b0
ED		 1545
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
2ab1bc9d 1548 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1549 struct drm_i915_gem_object *obj;
2ab1bc9d 1550
59bea882 1551 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1552
1553 /* self-refresh seems busted with untiled */
2ff8fde1 1554 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1555 enabled = NULL;
1556 }
1557
b445e3b0
ED		 1558 /*
1559 * Overlay gets an aggressive default since video jitter is bad.
1560 */
1561 cwm = 2;
1562
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1564 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1565
1566 /* Calc sr entries for one plane configs */
1567 if (HAS_FW_BLC(dev) && enabled) {
1568 /* self-refresh has much higher latency */
1569 static const int sr_latency_ns = 6000;
124abe07 1570 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1571 int clock = adjusted_mode->crtc_clock;
fec8cba3 1572 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1573 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1574 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1575 unsigned long line_time_us;
1576 int entries;
1577
922044c9 1578 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1579
1580 /* Use ns/us then divide to preserve precision */
1581 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1582 cpp * hdisplay;
b445e3b0
ED		 1583 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585 srwm = wm_info->fifo_size - entries;
1586 if (srwm < 0)
1587 srwm = 1;
1588
1589 if (IS_I945G(dev) || IS_I945GM(dev))
1590 I915_WRITE(FW_BLC_SELF,
1591 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592 else if (IS_I915GM(dev))
1593 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594 }
1595
1596 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597 planea_wm, planeb_wm, cwm, srwm);
1598
1599 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600 fwater_hi = (cwm & 0x1f);
1601
1602 /* Set request length to 8 cachelines per fetch */
1603 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604 fwater_hi = fwater_hi | (1 << 8);
1605
1606 I915_WRITE(FW_BLC, fwater_lo);
1607 I915_WRITE(FW_BLC2, fwater_hi);
1608
5209b1f4
ID		 1609 if (enabled)
1610 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1611}
1612
feb56b93 1613static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1614{
46ba614c 1615 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 struct drm_crtc *crtc;
241bfc38 1618 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1619 uint32_t fwater_lo;
1620 int planea_wm;
1621
1622 crtc = single_enabled_crtc(dev);
1623 if (crtc == NULL)
1624 return;
1625
6e3c9717 1626 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1627 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1628 &i845_wm_info,
b445e3b0 1629 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1630 4, pessimal_latency_ns);
b445e3b0
ED		 1631 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632 fwater_lo |= (3<<8) | planea_wm;
1633
1634 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636 I915_WRITE(FW_BLC, fwater_lo);
1637}
1638
8cfb3407 1639uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1640{
fd4daa9c 1641 uint32_t pixel_rate;
801bcfff 1642
8cfb3407 1643 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1644
1645 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646 * adjust the pixel_rate here. */
1647
8cfb3407 1648 if (pipe_config->pch_pfit.enabled) {
801bcfff 1649 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1650 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652 pipe_w = pipe_config->pipe_src_w;
1653 pipe_h = pipe_config->pipe_src_h;
801bcfff 1654
801bcfff
PZ		 1655 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656 pfit_h = pfit_size & 0xFFFF;
1657 if (pipe_w < pfit_w)
1658 pipe_w = pfit_w;
1659 if (pipe_h < pfit_h)
1660 pipe_h = pfit_h;
1661
15126882
MR		 1662 if (WARN_ON(!pfit_w || !pfit_h))
1663 return pixel_rate;
1664
801bcfff
PZ		 1665 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666 pfit_w * pfit_h);
1667 }
1668
1669 return pixel_rate;
1670}
1671
37126462 1672/* latency must be in 0.1us units. */
ac484963 1673static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1674{
1675 uint64_t ret;
1676
3312ba65
VS		 1677 if (WARN(latency == 0, "Latency value missing\n"))
1678 return UINT_MAX;
1679
ac484963 1680 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1681 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683 return ret;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
23297044 1687static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1688 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1689 uint32_t latency)
1690{
1691 uint32_t ret;
1692
3312ba65
VS		 1693 if (WARN(latency == 0, "Latency value missing\n"))
1694 return UINT_MAX;
15126882
MR		 1695 if (WARN_ON(!pipe_htotal))
1696 return UINT_MAX;
3312ba65 1697
801bcfff 1698 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1699 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1700 ret = DIV_ROUND_UP(ret, 64) + 2;
1701 return ret;
1702}
1703
23297044 1704static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1705 uint8_t cpp)
cca32e9a 1706{
15126882
MR		 1707 /*
1708 * Neither of these should be possible since this function shouldn't be
1709 * called if the CRTC is off or the plane is invisible. But let's be
1710 * extra paranoid to avoid a potential divide-by-zero if we screw up
1711 * elsewhere in the driver.
1712 */
ac484963 1713 if (WARN_ON(!cpp))
15126882
MR		 1714 return 0;
1715 if (WARN_ON(!horiz_pixels))
1716 return 0;
1717
ac484963 1718 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1719}
1720
820c1980 1721struct ilk_wm_maximums {
cca32e9a
PZ		 1722 uint16_t pri;
1723 uint16_t spr;
1724 uint16_t cur;
1725 uint16_t fbc;
1726};
1727
37126462
VS		 1728/*
1729 * For both WM_PIPE and WM_LP.
1730 * mem_value must be in 0.1us units.
1731 */
7221fc33 1732static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1733 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1734 uint32_t mem_value,
1735 bool is_lp)
801bcfff 1736{
ac484963
VS		 1737 int cpp = pstate->base.fb ?
1738 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1739 uint32_t method1, method2;
1740
7221fc33 1741 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1742 return 0;
1743
ac484963 1744 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1745
1746 if (!is_lp)
1747 return method1;
1748
7221fc33
MR		 1749 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1751 drm_rect_width(&pstate->dst),
ac484963 1752 cpp, mem_value);
cca32e9a
PZ		 1753
1754 return min(method1, method2);
801bcfff
PZ		 1755}
1756
37126462
VS		 1757/*
1758 * For both WM_PIPE and WM_LP.
1759 * mem_value must be in 0.1us units.
1760 */
7221fc33 1761static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1762 const struct intel_plane_state *pstate,
801bcfff
PZ		 1763 uint32_t mem_value)
1764{
ac484963
VS		 1765 int cpp = pstate->base.fb ?
1766 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1767 uint32_t method1, method2;
1768
7221fc33 1769 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1770 return 0;
1771
ac484963 1772 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1773 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1775 drm_rect_width(&pstate->dst),
ac484963 1776 cpp, mem_value);
801bcfff
PZ		 1777 return min(method1, method2);
1778}
1779
37126462
VS		 1780/*
1781 * For both WM_PIPE and WM_LP.
1782 * mem_value must be in 0.1us units.
1783 */
7221fc33 1784static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1785 const struct intel_plane_state *pstate,
801bcfff
PZ		 1786 uint32_t mem_value)
1787{
b2435692
MR		 1788 /*
1789 * We treat the cursor plane as always-on for the purposes of watermark
1790 * calculation. Until we have two-stage watermark programming merged,
1791 * this is necessary to avoid flickering.
1792 */
1793 int cpp = 4;
1794 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1795
b2435692 1796 if (!cstate->base.active)
801bcfff
PZ		 1797 return 0;
1798
7221fc33
MR		 1799 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1801 width, cpp, mem_value);
801bcfff
PZ		 1802}
1803
cca32e9a 1804/* Only for WM_LP. */
7221fc33 1805static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1806 const struct intel_plane_state *pstate,
1fda9882 1807 uint32_t pri_val)
cca32e9a 1808{
ac484963
VS		 1809 int cpp = pstate->base.fb ?
1810 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1811
7221fc33 1812 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1813 return 0;
1814
ac484963 1815 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1816}
1817
158ae64f
VS		 1818static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819{
416f4727
VS		 1820 if (INTEL_INFO(dev)->gen >= 8)
1821 return 3072;
1822 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1823 return 768;
1824 else
1825 return 512;
1826}
1827
4e975081
VS		 1828static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829 int level, bool is_sprite)
1830{
1831 if (INTEL_INFO(dev)->gen >= 8)
1832 /* BDW primary/sprite plane watermarks */
1833 return level == 0 ? 255 : 2047;
1834 else if (INTEL_INFO(dev)->gen >= 7)
1835 /* IVB/HSW primary/sprite plane watermarks */
1836 return level == 0 ? 127 : 1023;
1837 else if (!is_sprite)
1838 /* ILK/SNB primary plane watermarks */
1839 return level == 0 ? 127 : 511;
1840 else
1841 /* ILK/SNB sprite plane watermarks */
1842 return level == 0 ? 63 : 255;
1843}
1844
1845static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846 int level)
1847{
1848 if (INTEL_INFO(dev)->gen >= 7)
1849 return level == 0 ? 63 : 255;
1850 else
1851 return level == 0 ? 31 : 63;
1852}
1853
1854static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855{
1856 if (INTEL_INFO(dev)->gen >= 8)
1857 return 31;
1858 else
1859 return 15;
1860}
1861
158ae64f
VS		 1862/* Calculate the maximum primary/sprite plane watermark */
1863static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864 int level,
240264f4 1865 const struct intel_wm_config *config,
158ae64f
VS		 1866 enum intel_ddb_partitioning ddb_partitioning,
1867 bool is_sprite)
1868{
1869 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1870
1871 /* if sprites aren't enabled, sprites get nothing */
240264f4 1872 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1873 return 0;
1874
1875 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1876 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1877 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879 /*
1880 * For some reason the non self refresh
1881 * FIFO size is only half of the self
1882 * refresh FIFO size on ILK/SNB.
1883 */
1884 if (INTEL_INFO(dev)->gen <= 6)
1885 fifo_size /= 2;
1886 }
1887
240264f4 1888 if (config->sprites_enabled) {
158ae64f
VS		 1889 /* level 0 is always calculated with 1:1 split */
1890 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891 if (is_sprite)
1892 fifo_size *= 5;
1893 fifo_size /= 6;
1894 } else {
1895 fifo_size /= 2;
1896 }
1897 }
1898
1899 /* clamp to max that the registers can hold */
4e975081 1900 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1901}
1902
1903/* Calculate the maximum cursor plane watermark */
1904static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1905 int level,
1906 const struct intel_wm_config *config)
158ae64f
VS		 1907{
1908 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1909 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1910 return 64;
1911
1912 /* otherwise just report max that registers can hold */
4e975081 1913 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1914}
1915
d34ff9c6 1916static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1917 int level,
1918 const struct intel_wm_config *config,
1919 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1920 struct ilk_wm_maximums *max)
158ae64f 1921{
240264f4
VS		 1922 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1925 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1926}
1927
a3cb4048
VS		 1928static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929 int level,
1930 struct ilk_wm_maximums *max)
1931{
1932 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934 max->cur = ilk_cursor_wm_reg_max(dev, level);
1935 max->fbc = ilk_fbc_wm_reg_max(dev);
1936}
1937
d9395655 1938static bool ilk_validate_wm_level(int level,
820c1980 1939 const struct ilk_wm_maximums *max,
d9395655 1940 struct intel_wm_level *result)
a9786a11
VS		 1941{
1942 bool ret;
1943
1944 /* already determined to be invalid? */
1945 if (!result->enable)
1946 return false;
1947
1948 result->enable = result->pri_val <= max->pri &&
1949 result->spr_val <= max->spr &&
1950 result->cur_val <= max->cur;
1951
1952 ret = result->enable;
1953
1954 /*
1955 * HACK until we can pre-compute everything,
1956 * and thus fail gracefully if LP0 watermarks
1957 * are exceeded...
1958 */
1959 if (level == 0 && !result->enable) {
1960 if (result->pri_val > max->pri)
1961 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962 level, result->pri_val, max->pri);
1963 if (result->spr_val > max->spr)
1964 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965 level, result->spr_val, max->spr);
1966 if (result->cur_val > max->cur)
1967 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968 level, result->cur_val, max->cur);
1969
1970 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973 result->enable = true;
1974 }
1975
a9786a11
VS		 1976 return ret;
1977}
1978
d34ff9c6 1979static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1980 const struct intel_crtc *intel_crtc,
6f5ddd17 1981 int level,
7221fc33 1982 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1983 struct intel_plane_state *pristate,
1984 struct intel_plane_state *sprstate,
1985 struct intel_plane_state *curstate,
1fd527cc 1986 struct intel_wm_level *result)
6f5ddd17
VS		 1987{
1988 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992 /* WM1+ latency values stored in 0.5us units */
1993 if (level > 0) {
1994 pri_latency *= 5;
1995 spr_latency *= 5;
1996 cur_latency *= 5;
1997 }
1998
e3bddded
ML		 1999 if (pristate) {
2000 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001 pri_latency, level);
2002 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003 }
2004
2005 if (sprstate)
2006 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008 if (curstate)
2009 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
6f5ddd17
VS		 2011 result->enable = true;
2012}
2013
801bcfff 2014static uint32_t
532f7a7f 2015hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2016{
532f7a7f
VS		 2017 const struct intel_atomic_state *intel_state =
2018 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2019 const struct drm_display_mode *adjusted_mode =
2020 &cstate->base.adjusted_mode;
85a02deb 2021 u32 linetime, ips_linetime;
1f8eeabf 2022
ee91a159
MR		 2023 if (!cstate->base.active)
2024 return 0;
2025 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026 return 0;
532f7a7f 2027 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2028 return 0;
1011d8c4 2029
1f8eeabf
ED		 2030 /* The WM are computed with base on how long it takes to fill a single
2031 * row at the given clock rate, multiplied by 8.
2032 * */
124abe07
VS		 2033 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034 adjusted_mode->crtc_clock);
2035 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2036 intel_state->cdclk);
1f8eeabf 2037
801bcfff
PZ		 2038 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2040}
2041
2af30a5c 2042static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2043{
2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045
2af30a5c
PB		 2046 if (IS_GEN9(dev)) {
2047 uint32_t val;
4f947386 2048 int ret, i;
367294be 2049 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2050
2051 /* read the first set of memory latencies[0:3] */
2052 val = 0; /* data0 to be programmed to 0 for first set */
2053 mutex_lock(&dev_priv->rps.hw_lock);
2054 ret = sandybridge_pcode_read(dev_priv,
2055 GEN9_PCODE_READ_MEM_LATENCY,
2056 &val);
2057 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059 if (ret) {
2060 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061 return;
2062 }
2063
2064 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066 GEN9_MEM_LATENCY_LEVEL_MASK;
2067 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068 GEN9_MEM_LATENCY_LEVEL_MASK;
2069 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072 /* read the second set of memory latencies[4:7] */
2073 val = 1; /* data0 to be programmed to 1 for second set */
2074 mutex_lock(&dev_priv->rps.hw_lock);
2075 ret = sandybridge_pcode_read(dev_priv,
2076 GEN9_PCODE_READ_MEM_LATENCY,
2077 &val);
2078 mutex_unlock(&dev_priv->rps.hw_lock);
2079 if (ret) {
2080 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081 return;
2082 }
2083
2084 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086 GEN9_MEM_LATENCY_LEVEL_MASK;
2087 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088 GEN9_MEM_LATENCY_LEVEL_MASK;
2089 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
367294be 2092 /*
6f97235b
DL		 2093 * WaWmMemoryReadLatency:skl
2094 *
367294be
VK		 2095 * punit doesn't take into account the read latency so we need
2096 * to add 2us to the various latency levels we retrieve from
2097 * the punit.
2098 * - W0 is a bit special in that it's the only level that
2099 * can't be disabled if we want to have display working, so
2100 * we always add 2us there.
2101 * - For levels >=1, punit returns 0us latency when they are
2102 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2103 *
2104 * Additionally, if a level n (n > 1) has a 0us latency, all
2105 * levels m (m >= n) need to be disabled. We make sure to
2106 * sanitize the values out of the punit to satisfy this
2107 * requirement.
367294be
VK		 2108 */
2109 wm[0] += 2;
2110 for (level = 1; level <= max_level; level++)
2111 if (wm[level] != 0)
2112 wm[level] += 2;
4f947386
VK		 2113 else {
2114 for (i = level + 1; i <= max_level; i++)
2115 wm[i] = 0;
367294be 2116
4f947386
VK		 2117 break;
2118 }
2af30a5c 2119 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2120 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122 wm[0] = (sskpd >> 56) & 0xFF;
2123 if (wm[0] == 0)
2124 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2125 wm[1] = (sskpd >> 4) & 0xFF;
2126 wm[2] = (sskpd >> 12) & 0xFF;
2127 wm[3] = (sskpd >> 20) & 0x1FF;
2128 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2129 } else if (INTEL_INFO(dev)->gen >= 6) {
2130 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2136 } else if (INTEL_INFO(dev)->gen >= 5) {
2137 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139 /* ILK primary LP0 latency is 700 ns */
2140 wm[0] = 7;
2141 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2143 }
2144}
2145
53615a5e
VS		 2146static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147{
2148 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2149 if (IS_GEN5(dev))
53615a5e
VS		 2150 wm[0] = 13;
2151}
2152
2153static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154{
2155 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2156 if (IS_GEN5(dev))
53615a5e
VS		 2157 wm[0] = 13;
2158
2159 /* WaDoubleCursorLP3Latency:ivb */
2160 if (IS_IVYBRIDGE(dev))
2161 wm[3] *= 2;
2162}
2163
546c81fd 2164int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2165{
26ec971e 2166 /* how many WM levels are we expecting */
b6e742f6 2167 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2168 return 7;
2169 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2170 return 4;
26ec971e 2171 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2172 return 3;
26ec971e 2173 else
ad0d6dc4
VS		 2174 return 2;
2175}
7526ed79 2176
ad0d6dc4
VS		 2177static void intel_print_wm_latency(struct drm_device *dev,
2178 const char *name,
2af30a5c 2179 const uint16_t wm[8])
ad0d6dc4
VS		 2180{
2181 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2182
2183 for (level = 0; level <= max_level; level++) {
2184 unsigned int latency = wm[level];
2185
2186 if (latency == 0) {
2187 DRM_ERROR("%s WM%d latency not provided\n",
2188 name, level);
2189 continue;
2190 }
2191
2af30a5c
PB		 2192 /*
2193 * - latencies are in us on gen9.
2194 * - before then, WM1+ latency values are in 0.5us units
2195 */
2196 if (IS_GEN9(dev))
2197 latency *= 10;
2198 else if (level > 0)
26ec971e
VS		 2199 latency *= 5;
2200
2201 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202 name, level, wm[level],
2203 latency / 10, latency % 10);
2204 }
2205}
2206
e95a2f75
VS		 2207static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208 uint16_t wm[5], uint16_t min)
2209{
2210 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212 if (wm[0] >= min)
2213 return false;
2214
2215 wm[0] = max(wm[0], min);
2216 for (level = 1; level <= max_level; level++)
2217 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219 return true;
2220}
2221
2222static void snb_wm_latency_quirk(struct drm_device *dev)
2223{
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 bool changed;
2226
2227 /*
2228 * The BIOS provided WM memory latency values are often
2229 * inadequate for high resolution displays. Adjust them.
2230 */
2231 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235 if (!changed)
2236 return;
2237
2238 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242}
2243
fa50ad61 2244static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2245{
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251 sizeof(dev_priv->wm.pri_latency));
2252 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253 sizeof(dev_priv->wm.pri_latency));
2254
2255 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2257
2258 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2261
2262 if (IS_GEN6(dev))
2263 snb_wm_latency_quirk(dev);
53615a5e
VS		 2264}
2265
2af30a5c
PB		 2266static void skl_setup_wm_latency(struct drm_device *dev)
2267{
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272}
2273
ed4a6a7c
MR		 2274static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275 struct intel_pipe_wm *pipe_wm)
2276{
2277 /* LP0 watermark maximums depend on this pipe alone */
2278 const struct intel_wm_config config = {
2279 .num_pipes_active = 1,
2280 .sprites_enabled = pipe_wm->sprites_enabled,
2281 .sprites_scaled = pipe_wm->sprites_scaled,
2282 };
2283 struct ilk_wm_maximums max;
2284
2285 /* LP0 watermarks always use 1/2 DDB partitioning */
2286 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288 /* At least LP0 must be valid */
2289 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291 return false;
2292 }
2293
2294 return true;
2295}
2296
0b2ae6d7 2297/* Compute new watermarks for the pipe */
e3bddded 2298static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2299{
e3bddded
ML		 2300 struct drm_atomic_state *state = cstate->base.state;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2302 struct intel_pipe_wm *pipe_wm;
e3bddded 2303 struct drm_device *dev = state->dev;
d34ff9c6 2304 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2305 struct intel_plane *intel_plane;
86c8bbbe 2306 struct intel_plane_state *pristate = NULL;
43d59eda 2307 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2308 struct intel_plane_state *curstate = NULL;
d81f04c5 2309 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2310 struct ilk_wm_maximums max;
0b2ae6d7 2311
e8f1f02e 2312 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2313
43d59eda 2314 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2315 struct intel_plane_state *ps;
2316
2317 ps = intel_atomic_get_existing_plane_state(state,
2318 intel_plane);
2319 if (!ps)
2320 continue;
86c8bbbe
MR		 2321
2322 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2323 pristate = ps;
86c8bbbe 2324 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2325 sprstate = ps;
86c8bbbe 2326 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2327 curstate = ps;
43d59eda
MR		 2328 }
2329
ed4a6a7c 2330 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2331 if (sprstate) {
2332 pipe_wm->sprites_enabled = sprstate->visible;
2333 pipe_wm->sprites_scaled = sprstate->visible &&
2334 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336 }
2337
d81f04c5
ML		 2338 usable_level = max_level;
2339
7b39a0b7 2340 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2341 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2342 usable_level = 1;
7b39a0b7
VS		 2343
2344 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2345 if (pipe_wm->sprites_scaled)
d81f04c5 2346 usable_level = 0;
7b39a0b7 2347
86c8bbbe 2348 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2349 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2353
a42a5719 2354 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2355 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2356
ed4a6a7c 2357 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2358 return -EINVAL;
a3cb4048
VS		 2359
2360 ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362 for (level = 1; level <= max_level; level++) {
71f0a626 2363 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2364
86c8bbbe 2365 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2366 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2367
2368 /*
2369 * Disable any watermark level that exceeds the
2370 * register maximums since such watermarks are
2371 * always invalid.
2372 */
71f0a626
ML		 2373 if (level > usable_level)
2374 continue;
2375
2376 if (ilk_validate_wm_level(level, &max, wm))
2377 pipe_wm->wm[level] = *wm;
2378 else
d81f04c5 2379 usable_level = level;
a3cb4048
VS		 2380 }
2381
86c8bbbe 2382 return 0;
0b2ae6d7
VS		 2383}
2384
ed4a6a7c
MR		 2385/*
2386 * Build a set of 'intermediate' watermark values that satisfy both the old
2387 * state and the new state. These can be programmed to the hardware
2388 * immediately.
2389 */
2390static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391 struct intel_crtc *intel_crtc,
2392 struct intel_crtc_state *newstate)
2393{
e8f1f02e 2394 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2395 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396 int level, max_level = ilk_wm_max_level(dev);
2397
2398 /*
2399 * Start with the final, target watermarks, then combine with the
2400 * currently active watermarks to get values that are safe both before
2401 * and after the vblank.
2402 */
e8f1f02e 2403 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2404 a->pipe_enabled |= b->pipe_enabled;
2405 a->sprites_enabled |= b->sprites_enabled;
2406 a->sprites_scaled |= b->sprites_scaled;
2407
2408 for (level = 0; level <= max_level; level++) {
2409 struct intel_wm_level *a_wm = &a->wm[level];
2410 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412 a_wm->enable &= b_wm->enable;
2413 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417 }
2418
2419 /*
2420 * We need to make sure that these merged watermark values are
2421 * actually a valid configuration themselves. If they're not,
2422 * there's no safe way to transition from the old state to
2423 * the new state, so we need to fail the atomic transaction.
2424 */
2425 if (!ilk_validate_pipe_wm(dev, a))
2426 return -EINVAL;
2427
2428 /*
2429 * If our intermediate WM are identical to the final WM, then we can
2430 * omit the post-vblank programming; only update if it's different.
2431 */
e8f1f02e 2432 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2433 newstate->wm.need_postvbl_update = false;
2434
2435 return 0;
2436}
2437
0b2ae6d7
VS		 2438/*
2439 * Merge the watermarks from all active pipes for a specific level.
2440 */
2441static void ilk_merge_wm_level(struct drm_device *dev,
2442 int level,
2443 struct intel_wm_level *ret_wm)
2444{
2445 const struct intel_crtc *intel_crtc;
2446
d52fea5b
VS		 2447 ret_wm->enable = true;
2448
d3fcc808 2449 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2450 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2451 const struct intel_wm_level *wm = &active->wm[level];
2452
2453 if (!active->pipe_enabled)
2454 continue;
0b2ae6d7 2455
d52fea5b
VS		 2456 /*
2457 * The watermark values may have been used in the past,
2458 * so we must maintain them in the registers for some
2459 * time even if the level is now disabled.
2460 */
0b2ae6d7 2461 if (!wm->enable)
d52fea5b 2462 ret_wm->enable = false;
0b2ae6d7
VS		 2463
2464 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468 }
0b2ae6d7
VS		 2469}
2470
2471/*
2472 * Merge all low power watermarks for all active pipes.
2473 */
2474static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2475 const struct intel_wm_config *config,
820c1980 2476 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2477 struct intel_pipe_wm *merged)
2478{
7733b49b 2479 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2480 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2481 int last_enabled_level = max_level;
0b2ae6d7 2482
0ba22e26
VS		 2483 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485 config->num_pipes_active > 1)
1204d5ba 2486 last_enabled_level = 0;
0ba22e26 2487
6c8b6c28
VS		 2488 /* ILK: FBC WM must be disabled always */
2489 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2490
2491 /* merge each WM1+ level */
2492 for (level = 1; level <= max_level; level++) {
2493 struct intel_wm_level *wm = &merged->wm[level];
2494
2495 ilk_merge_wm_level(dev, level, wm);
2496
d52fea5b
VS		 2497 if (level > last_enabled_level)
2498 wm->enable = false;
2499 else if (!ilk_validate_wm_level(level, max, wm))
2500 /* make sure all following levels get disabled */
2501 last_enabled_level = level - 1;
0b2ae6d7
VS		 2502
2503 /*
2504 * The spec says it is preferred to disable
2505 * FBC WMs instead of disabling a WM level.
2506 */
2507 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2508 if (wm->enable)
2509 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2510 wm->fbc_val = 0;
2511 }
2512 }
6c8b6c28
VS		 2513
2514 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515 /*
2516 * FIXME this is racy. FBC might get enabled later.
2517 * What we should check here is whether FBC can be
2518 * enabled sometime later.
2519 */
7733b49b 2520 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2521 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2522 for (level = 2; level <= max_level; level++) {
2523 struct intel_wm_level *wm = &merged->wm[level];
2524
2525 wm->enable = false;
2526 }
2527 }
0b2ae6d7
VS		 2528}
2529
b380ca3c
VS		 2530static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531{
2532 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534}
2535
a68d68ee
VS		 2536/* The value we need to program into the WM_LPx latency field */
2537static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538{
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540
a42a5719 2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2542 return 2 * level;
2543 else
2544 return dev_priv->wm.pri_latency[level];
2545}
2546
820c1980 2547static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2548 const struct intel_pipe_wm *merged,
609cedef 2549 enum intel_ddb_partitioning partitioning,
820c1980 2550 struct ilk_wm_values *results)
801bcfff 2551{
0b2ae6d7
VS		 2552 struct intel_crtc *intel_crtc;
2553 int level, wm_lp;
cca32e9a 2554
0362c781 2555 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2556 results->partitioning = partitioning;
cca32e9a 2557
0b2ae6d7 2558 /* LP1+ register values */
cca32e9a 2559 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2560 const struct intel_wm_level *r;
801bcfff 2561
b380ca3c 2562 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2563
0362c781 2564 r = &merged->wm[level];
cca32e9a 2565
d52fea5b
VS		 2566 /*
2567 * Maintain the watermark values even if the level is
2568 * disabled. Doing otherwise could cause underruns.
2569 */
2570 results->wm_lp[wm_lp - 1] =
a68d68ee 2571 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2572 (r->pri_val << WM1_LP_SR_SHIFT) |
2573 r->cur_val;
2574
d52fea5b
VS		 2575 if (r->enable)
2576 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
416f4727
VS		 2578 if (INTEL_INFO(dev)->gen >= 8)
2579 results->wm_lp[wm_lp - 1] |=
2580 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581 else
2582 results->wm_lp[wm_lp - 1] |=
2583 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
d52fea5b
VS		 2585 /*
2586 * Always set WM1S_LP_EN when spr_val != 0, even if the
2587 * level is disabled. Doing otherwise could cause underruns.
2588 */
6cef2b8a
VS		 2589 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590 WARN_ON(wm_lp != 1);
2591 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592 } else
2593 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2594 }
801bcfff 2595
0b2ae6d7 2596 /* LP0 register values */
d3fcc808 2597 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2598 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2599 const struct intel_wm_level *r =
2600 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2601
2602 if (WARN_ON(!r->enable))
2603 continue;
2604
ed4a6a7c 2605 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2606
0b2ae6d7
VS		 2607 results->wm_pipe[pipe] =
2608 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610 r->cur_val;
801bcfff
PZ		 2611 }
2612}
2613
861f3389
PZ		 2614/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2616static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2617 struct intel_pipe_wm *r1,
2618 struct intel_pipe_wm *r2)
861f3389 2619{
198a1e9b
VS		 2620 int level, max_level = ilk_wm_max_level(dev);
2621 int level1 = 0, level2 = 0;
861f3389 2622
198a1e9b
VS		 2623 for (level = 1; level <= max_level; level++) {
2624 if (r1->wm[level].enable)
2625 level1 = level;
2626 if (r2->wm[level].enable)
2627 level2 = level;
861f3389
PZ		 2628 }
2629
198a1e9b
VS		 2630 if (level1 == level2) {
2631 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2632 return r2;
2633 else
2634 return r1;
198a1e9b 2635 } else if (level1 > level2) {
861f3389
PZ		 2636 return r1;
2637 } else {
2638 return r2;
2639 }
2640}
2641
49a687c4
VS		 2642/* dirty bits used to track which watermarks need changes */
2643#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647#define WM_DIRTY_FBC (1 << 24)
2648#define WM_DIRTY_DDB (1 << 25)
2649
055e393f 2650static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2651 const struct ilk_wm_values *old,
2652 const struct ilk_wm_values *new)
49a687c4
VS		 2653{
2654 unsigned int dirty = 0;
2655 enum pipe pipe;
2656 int wm_lp;
2657
055e393f 2658 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2659 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660 dirty |= WM_DIRTY_LINETIME(pipe);
2661 /* Must disable LP1+ watermarks too */
2662 dirty |= WM_DIRTY_LP_ALL;
2663 }
2664
2665 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666 dirty |= WM_DIRTY_PIPE(pipe);
2667 /* Must disable LP1+ watermarks too */
2668 dirty |= WM_DIRTY_LP_ALL;
2669 }
2670 }
2671
2672 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673 dirty |= WM_DIRTY_FBC;
2674 /* Must disable LP1+ watermarks too */
2675 dirty |= WM_DIRTY_LP_ALL;
2676 }
2677
2678 if (old->partitioning != new->partitioning) {
2679 dirty |= WM_DIRTY_DDB;
2680 /* Must disable LP1+ watermarks too */
2681 dirty |= WM_DIRTY_LP_ALL;
2682 }
2683
2684 /* LP1+ watermarks already deemed dirty, no need to continue */
2685 if (dirty & WM_DIRTY_LP_ALL)
2686 return dirty;
2687
2688 /* Find the lowest numbered LP1+ watermark in need of an update... */
2689 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692 break;
2693 }
2694
2695 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696 for (; wm_lp <= 3; wm_lp++)
2697 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699 return dirty;
2700}
2701
8553c18e
VS		 2702static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703 unsigned int dirty)
801bcfff 2704{
820c1980 2705 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2706 bool changed = false;
801bcfff 2707
facd619b
VS		 2708 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2711 changed = true;
facd619b
VS		 2712 }
2713 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2716 changed = true;
facd619b
VS		 2717 }
2718 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2721 changed = true;
facd619b 2722 }
801bcfff 2723
facd619b
VS		 2724 /*
2725 * Don't touch WM1S_LP_EN here.
2726 * Doing so could cause underruns.
2727 */
6cef2b8a 2728
8553c18e
VS		 2729 return changed;
2730}
2731
2732/*
2733 * The spec says we shouldn't write when we don't need, because every write
2734 * causes WMs to be re-evaluated, expending some power.
2735 */
820c1980
ID		 2736static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737 struct ilk_wm_values *results)
8553c18e
VS		 2738{
2739 struct drm_device *dev = dev_priv->dev;
820c1980 2740 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2741 unsigned int dirty;
2742 uint32_t val;
2743
055e393f 2744 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2745 if (!dirty)
2746 return;
2747
2748 _ilk_disable_lp_wm(dev_priv, dirty);
2749
49a687c4 2750 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2751 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2752 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2753 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2754 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2755 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
49a687c4 2757 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2758 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2759 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2760 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2761 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2762 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
49a687c4 2764 if (dirty & WM_DIRTY_DDB) {
a42a5719 2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2766 val = I915_READ(WM_MISC);
2767 if (results->partitioning == INTEL_DDB_PART_1_2)
2768 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769 else
2770 val |= WM_MISC_DATA_PARTITION_5_6;
2771 I915_WRITE(WM_MISC, val);
2772 } else {
2773 val = I915_READ(DISP_ARB_CTL2);
2774 if (results->partitioning == INTEL_DDB_PART_1_2)
2775 val &= ~DISP_DATA_PARTITION_5_6;
2776 else
2777 val |= DISP_DATA_PARTITION_5_6;
2778 I915_WRITE(DISP_ARB_CTL2, val);
2779 }
1011d8c4
PZ		 2780 }
2781
49a687c4 2782 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2783 val = I915_READ(DISP_ARB_CTL);
2784 if (results->enable_fbc_wm)
2785 val &= ~DISP_FBC_WM_DIS;
2786 else
2787 val |= DISP_FBC_WM_DIS;
2788 I915_WRITE(DISP_ARB_CTL, val);
2789 }
2790
954911eb
ID		 2791 if (dirty & WM_DIRTY_LP(1) &&
2792 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2796 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800 }
801bcfff 2801
facd619b 2802 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2803 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2804 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2805 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2806 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2807 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2808
2809 dev_priv->wm.hw = *results;
801bcfff
PZ		 2810}
2811
ed4a6a7c 2812bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2813{
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817}
2818
b9cec075
DL		 2819/*
2820 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821 * different active planes.
2822 */
2823
2824#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2825#define BXT_DDB_SIZE 512
b9cec075 2826
024c9045
MR		 2827/*
2828 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2829 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830 * other universal planes are in indices 1..n. Note that this may leave unused
2831 * indices between the top "sprite" plane and the cursor.
2832 */
2833static int
2834skl_wm_plane_id(const struct intel_plane *plane)
2835{
2836 switch (plane->base.type) {
2837 case DRM_PLANE_TYPE_PRIMARY:
2838 return 0;
2839 case DRM_PLANE_TYPE_CURSOR:
2840 return PLANE_CURSOR;
2841 case DRM_PLANE_TYPE_OVERLAY:
2842 return plane->plane + 1;
2843 default:
2844 MISSING_CASE(plane->base.type);
2845 return plane->plane;
2846 }
2847}
2848
b9cec075
DL		 2849static void
2850skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2851 const struct intel_crtc_state *cstate,
c107acfe
MR		 2852 struct intel_wm_config *config,
2853 struct skl_ddb_entry *alloc, /* out */
2854 int *num_active /* out */)
b9cec075 2855{
c107acfe
MR		 2856 struct drm_atomic_state *state = cstate->base.state;
2857 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2858 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 2859 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2860 struct drm_crtc *crtc;
2861 unsigned int pipe_size, ddb_size;
2862 int nth_active_pipe;
c107acfe
MR		 2863 int pipe = to_intel_crtc(for_crtc)->pipe;
2864
2865 if (intel_state && intel_state->active_pipe_changes)
2866 *num_active = hweight32(intel_state->active_crtcs);
2867 else if (intel_state)
2868 *num_active = hweight32(dev_priv->active_crtcs);
2869 else
2870 *num_active = config->num_pipes_active;
b9cec075 2871
024c9045 2872 if (!cstate->base.active) {
b9cec075
DL		 2873 alloc->start = 0;
2874 alloc->end = 0;
2875 return;
2876 }
2877
43d735a6
DL		 2878 if (IS_BROXTON(dev))
2879 ddb_size = BXT_DDB_SIZE;
2880 else
2881 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2882
2883 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2884
c107acfe
MR		 2885 /*
2886 * FIXME: At the moment we may be called on either in-flight or fully
2887 * committed cstate's. Once we fully move DDB allocation in the check
2888 * phase, we'll only be called on in-flight states and the 'else'
2889 * branch here will go away.
2890 *
2891 * The 'else' branch is slightly racy here, but it was racy to begin
2892 * with; since it's going away soon, no effort is made to address that.
2893 */
2894 if (state) {
2895 /*
2896 * If the state doesn't change the active CRTC's, then there's
2897 * no need to recalculate; the existing pipe allocation limits
2898 * should remain unchanged. Note that we're safe from racing
2899 * commits since any racing commit that changes the active CRTC
2900 * list would need to grab _all_ crtc locks, including the one
2901 * we currently hold.
2902 */
2903 if (!intel_state->active_pipe_changes) {
2904 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
2905 return;
2906 }
b9cec075 2907
c107acfe
MR		 2908 nth_active_pipe = hweight32(intel_state->active_crtcs &
2909 (drm_crtc_mask(for_crtc) - 1));
2910 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
2911 alloc->start = nth_active_pipe * ddb_size / *num_active;
2912 alloc->end = alloc->start + pipe_size;
2913 } else {
2914 nth_active_pipe = 0;
2915 for_each_crtc(dev, crtc) {
2916 if (!to_intel_crtc(crtc)->active)
2917 continue;
b9cec075 2918
c107acfe
MR		 2919 if (crtc == for_crtc)
2920 break;
b9cec075 2921
c107acfe
MR		 2922 nth_active_pipe++;
2923 }
2924
2925 pipe_size = ddb_size / config->num_pipes_active;
2926 alloc->start = nth_active_pipe * ddb_size /
2927 config->num_pipes_active;
2928 alloc->end = alloc->start + pipe_size;
2929 }
b9cec075
DL		 2930}
2931
c107acfe 2932static unsigned int skl_cursor_allocation(int num_active)
b9cec075 2933{
c107acfe 2934 if (num_active == 1)
b9cec075
DL		 2935 return 32;
2936
2937 return 8;
2938}
2939
a269c583
DL		 2940static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2941{
2942 entry->start = reg & 0x3ff;
2943 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2944 if (entry->end)
2945 entry->end += 1;
a269c583
DL		 2946}
2947
08db6652
DL		 2948void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2949 struct skl_ddb_allocation *ddb /* out */)
a269c583 2950{
a269c583
DL		 2951 enum pipe pipe;
2952 int plane;
2953 u32 val;
2954
b10f1b20
ML		 2955 memset(ddb, 0, sizeof(*ddb));
2956
a269c583 2957 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2958 enum intel_display_power_domain power_domain;
2959
2960 power_domain = POWER_DOMAIN_PIPE(pipe);
2961 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2962 continue;
2963
dd740780 2964 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2965 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2966 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2967 val);
2968 }
2969
2970 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2971 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2972 val);
4d800030
ID		 2973
2974 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2975 }
2976}
2977
b9cec075 2978static unsigned int
024c9045
MR		 2979skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2980 const struct drm_plane_state *pstate,
2981 int y)
b9cec075 2982{
a280f7dd 2983 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 2984 struct drm_framebuffer *fb = pstate->fb;
a280f7dd 2985 uint32_t width = 0, height = 0;
a1de91e5
MR		 2986 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
2987
2988 if (!intel_pstate->visible)
2989 return 0;
2990 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
2991 return 0;
2992 if (y && format != DRM_FORMAT_NV12)
2993 return 0;
a280f7dd
KM		 2994
2995 width = drm_rect_width(&intel_pstate->src) >> 16;
2996 height = drm_rect_height(&intel_pstate->src) >> 16;
2997
2998 if (intel_rotation_90_or_270(pstate->rotation))
2999 swap(width, height);
2cd601c6
CK		 3000
3001 /* for planar format */
a1de91e5 3002 if (format == DRM_FORMAT_NV12) {
2cd601c6 3003 if (y) /* y-plane data rate */
a280f7dd 3004 return width * height *
a1de91e5 3005 drm_format_plane_cpp(format, 0);
2cd601c6 3006 else /* uv-plane data rate */
a280f7dd 3007 return (width / 2) * (height / 2) *
a1de91e5 3008 drm_format_plane_cpp(format, 1);
2cd601c6
CK		 3009 }
3010
3011 /* for packed formats */
a1de91e5 3012 return width * height * drm_format_plane_cpp(format, 0);
b9cec075
DL		 3013}
3014
3015/*
3016 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3017 * a 8192x4096@32bpp framebuffer:
3018 * 3 * 4096 * 8192 * 4 < 2^32
3019 */
3020static unsigned int
9c74d826 3021skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3022{
9c74d826
MR		 3023 struct drm_crtc_state *cstate = &intel_cstate->base;
3024 struct drm_atomic_state *state = cstate->state;
3025 struct drm_crtc *crtc = cstate->crtc;
3026 struct drm_device *dev = crtc->dev;
3027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3028 const struct intel_plane *intel_plane;
a1de91e5 3029 unsigned int rate, total_data_rate = 0;
9c74d826 3030 int id;
b9cec075 3031
a1de91e5 3032 /* Calculate and cache data rate for each plane */
9c74d826
MR		 3033 /*
3034 * FIXME: At the moment this function can be called on either an
3035 * in-flight or a committed state object. If it's in-flight then we
3036 * only want to re-calculate the plane data rate for planes that are
3037 * part of the transaction (i.e., we don't want to grab any additional
3038 * plane states if we don't have to). If we're operating on committed
3039 * state, we'll just go ahead and recalculate the plane data rate for
3040 * all planes.
3041 *
3042 * Once we finish moving our DDB allocation to the atomic check phase,
3043 * we'll only be calling this function on in-flight state objects, so
3044 * the 'else' branch here will go away.
3045 */
3046 if (state) {
3047 struct drm_plane *plane;
3048 struct drm_plane_state *pstate;
3049 int i;
3050
3051 for_each_plane_in_state(state, plane, pstate, i) {
3052 intel_plane = to_intel_plane(plane);
3053 id = skl_wm_plane_id(intel_plane);
3054
3055 if (intel_plane->pipe != intel_crtc->pipe)
3056 continue;
3057
3058 /* packed/uv */
3059 rate = skl_plane_relative_data_rate(intel_cstate,
3060 pstate, 0);
3061 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3062
3063 /* y-plane */
3064 rate = skl_plane_relative_data_rate(intel_cstate,
3065 pstate, 1);
3066 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3067 }
3068 } else {
3069 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3070 const struct drm_plane_state *pstate =
3071 intel_plane->base.state;
3072 int id = skl_wm_plane_id(intel_plane);
3073
3074 /* packed/uv */
3075 rate = skl_plane_relative_data_rate(intel_cstate,
3076 pstate, 0);
3077 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3078
3079 /* y-plane */
3080 rate = skl_plane_relative_data_rate(intel_cstate,
3081 pstate, 1);
3082 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3083 }
a1de91e5 3084 }
024c9045 3085
a1de91e5
MR		 3086 /* Calculate CRTC's total data rate from cached values */
3087 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3088 int id = skl_wm_plane_id(intel_plane);
024c9045 3089
a1de91e5 3090 /* packed/uv */
9c74d826
MR		 3091 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3092 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3093 }
3094
9c74d826
MR		 3095 WARN_ON(cstate->plane_mask && total_data_rate == 0);
3096
b9cec075
DL		 3097 return total_data_rate;
3098}
3099
c107acfe 3100static int
024c9045 3101skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3102 struct skl_ddb_allocation *ddb /* out */)
3103{
c107acfe 3104 struct drm_atomic_state *state = cstate->base.state;
024c9045 3105 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 3106 struct drm_device *dev = crtc->dev;
aa363136
MR		 3107 struct drm_i915_private *dev_priv = to_i915(dev);
3108 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 3109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3110 struct intel_plane *intel_plane;
c107acfe
MR		 3111 struct drm_plane *plane;
3112 struct drm_plane_state *pstate;
b9cec075 3113 enum pipe pipe = intel_crtc->pipe;
34bb56af 3114 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3115 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3116 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3117 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3118 unsigned int total_data_rate;
c107acfe
MR		 3119 int num_active;
3120 int id, i;
b9cec075 3121
c107acfe
MR		 3122 if (!cstate->base.active) {
3123 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3124 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3125 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3126 return 0;
3127 }
3128
3129 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc,
3130 &num_active);
34bb56af 3131 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3132 if (alloc_size == 0) {
3133 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3134 return 0;
b9cec075
DL		 3135 }
3136
c107acfe 3137 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3138 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3139 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3140
3141 alloc_size -= cursor_blocks;
34bb56af 3142 alloc->end -= cursor_blocks;
b9cec075 3143
80958155 3144 /* 1. Allocate the mininum required blocks for each active plane */
c107acfe
MR		 3145 /*
3146 * TODO: Remove support for already-committed state once we
3147 * only allocate DDB on in-flight states.
3148 */
3149 if (state) {
3150 for_each_plane_in_state(state, plane, pstate, i) {
3151 intel_plane = to_intel_plane(plane);
3152 id = skl_wm_plane_id(intel_plane);
80958155 3153
c107acfe
MR		 3154 if (intel_plane->pipe != pipe)
3155 continue;
a280f7dd 3156
c107acfe
MR		 3157 if (!to_intel_plane_state(pstate)->visible) {
3158 minimum[id] = 0;
3159 y_minimum[id] = 0;
3160 continue;
3161 }
3162 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3163 minimum[id] = 0;
3164 y_minimum[id] = 0;
3165 continue;
3166 }
3167
3168 minimum[id] = 8;
3169 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
3170 y_minimum[id] = 8;
3171 else
3172 y_minimum[id] = 0;
3173 }
3174 } else {
3175 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3176 struct drm_plane *plane = &intel_plane->base;
3177 struct drm_framebuffer *fb = plane->state->fb;
3178 int id = skl_wm_plane_id(intel_plane);
3179
3180 if (!to_intel_plane_state(plane->state)->visible)
3181 continue;
3182
3183 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3184 continue;
3185
3186 minimum[id] = 8;
3187 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3188 }
3189 }
80958155 3190
c107acfe
MR		 3191 for (i = 0; i < PLANE_CURSOR; i++) {
3192 alloc_size -= minimum[i];
3193 alloc_size -= y_minimum[i];
80958155
DL		 3194 }
3195
b9cec075 3196 /*
80958155
DL		 3197 * 2. Distribute the remaining space in proportion to the amount of
3198 * data each plane needs to fetch from memory.
b9cec075
DL		 3199 *
3200 * FIXME: we may not allocate every single block here.
3201 */
024c9045 3202 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3203 if (total_data_rate == 0)
c107acfe 3204 return 0;
b9cec075 3205
34bb56af 3206 start = alloc->start;
024c9045 3207 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3208 unsigned int data_rate, y_data_rate;
3209 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3210 int id = skl_wm_plane_id(intel_plane);
b9cec075 3211
a1de91e5 3212 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3213
3214 /*
2cd601c6 3215 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3216 * promote the expression to 64 bits to avoid overflowing, the
3217 * result is < available as data_rate / total_data_rate < 1
3218 */
024c9045 3219 plane_blocks = minimum[id];
80958155
DL		 3220 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3221 total_data_rate);
b9cec075 3222
c107acfe
MR		 3223 /* Leave disabled planes at (0,0) */
3224 if (data_rate) {
3225 ddb->plane[pipe][id].start = start;
3226 ddb->plane[pipe][id].end = start + plane_blocks;
3227 }
b9cec075
DL		 3228
3229 start += plane_blocks;
2cd601c6
CK		 3230
3231 /*
3232 * allocation for y_plane part of planar format:
3233 */
a1de91e5
MR		 3234 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3235
3236 y_plane_blocks = y_minimum[id];
3237 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3238 total_data_rate);
2cd601c6 3239
c107acfe
MR		 3240 if (y_data_rate) {
3241 ddb->y_plane[pipe][id].start = start;
3242 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3243 }
a1de91e5
MR		 3244
3245 start += y_plane_blocks;
b9cec075
DL		 3246 }
3247
c107acfe 3248 return 0;
b9cec075
DL		 3249}
3250
5cec258b 3251static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3252{
3253 /* TODO: Take into account the scalers once we support them */
2d112de7 3254 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3255}
3256
3257/*
3258 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3259 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3260 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3261 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3262*/
ac484963 3263static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3264{
3265 uint32_t wm_intermediate_val, ret;
3266
3267 if (latency == 0)
3268 return UINT_MAX;
3269
ac484963 3270 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3271 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3272
3273 return ret;
3274}
3275
3276static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3277 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3278 uint64_t tiling, uint32_t latency)
2d41c0b5 3279{
d4c2aa60
TU		 3280 uint32_t ret;
3281 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3282 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3283
3284 if (latency == 0)
3285 return UINT_MAX;
3286
ac484963 3287 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3288
3289 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3290 tiling == I915_FORMAT_MOD_Yf_TILED) {
3291 plane_bytes_per_line *= 4;
3292 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3293 plane_blocks_per_line /= 4;
3294 } else {
3295 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3296 }
3297
2d41c0b5
PB		 3298 wm_intermediate_val = latency * pixel_rate;
3299 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3300 plane_blocks_per_line;
2d41c0b5
PB		 3301
3302 return ret;
3303}
3304
2d41c0b5
PB		 3305static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3306 const struct intel_crtc *intel_crtc)
3307{
3308 struct drm_device *dev = intel_crtc->base.dev;
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3311
e6d90023
KM		 3312 /*
3313 * If ddb allocation of pipes changed, it may require recalculation of
3314 * watermarks
3315 */
3316 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3317 return true;
3318
3319 return false;
3320}
3321
d4c2aa60 3322static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3323 struct intel_crtc_state *cstate,
3324 struct intel_plane *intel_plane,
afb024aa 3325 uint16_t ddb_allocation,
d4c2aa60 3326 int level,
afb024aa
DL		 3327 uint16_t *out_blocks, /* out */
3328 uint8_t *out_lines /* out */)
2d41c0b5 3329{
024c9045
MR		 3330 struct drm_plane *plane = &intel_plane->base;
3331 struct drm_framebuffer *fb = plane->state->fb;
a280f7dd
KM		 3332 struct intel_plane_state *intel_pstate =
3333 to_intel_plane_state(plane->state);
d4c2aa60
TU		 3334 uint32_t latency = dev_priv->wm.skl_latency[level];
3335 uint32_t method1, method2;
3336 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3337 uint32_t res_blocks, res_lines;
3338 uint32_t selected_result;
ac484963 3339 uint8_t cpp;
a280f7dd 3340 uint32_t width = 0, height = 0;
2d41c0b5 3341
a280f7dd 3342 if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
2d41c0b5
PB		 3343 return false;
3344
a280f7dd
KM		 3345 width = drm_rect_width(&intel_pstate->src) >> 16;
3346 height = drm_rect_height(&intel_pstate->src) >> 16;
3347
3348 if (intel_rotation_90_or_270(plane->state->rotation))
3349 swap(width, height);
3350
ac484963 3351 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3352 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3353 cpp, latency);
024c9045
MR		 3354 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3355 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3356 width,
3357 cpp,
3358 fb->modifier[0],
d4c2aa60 3359 latency);
2d41c0b5 3360
a280f7dd 3361 plane_bytes_per_line = width * cpp;
d4c2aa60 3362 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3363
024c9045
MR		 3364 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3365 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3366 uint32_t min_scanlines = 4;
3367 uint32_t y_tile_minimum;
024c9045 3368 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3369 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3370 drm_format_plane_cpp(fb->pixel_format, 1) :
3371 drm_format_plane_cpp(fb->pixel_format, 0);
3372
ac484963 3373 switch (cpp) {
1fc0a8f7
TU		 3374 case 1:
3375 min_scanlines = 16;
3376 break;
3377 case 2:
3378 min_scanlines = 8;
3379 break;
3380 case 8:
3381 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3382 }
1fc0a8f7
TU		 3383 }
3384 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3385 selected_result = max(method2, y_tile_minimum);
3386 } else {
3387 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3388 selected_result = min(method1, method2);
3389 else
3390 selected_result = method1;
3391 }
2d41c0b5 3392
d4c2aa60
TU		 3393 res_blocks = selected_result + 1;
3394 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3395
0fda6568 3396 if (level >= 1 && level <= 7) {
024c9045
MR		 3397 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3398 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3399 res_lines += 4;
3400 else
3401 res_blocks++;
3402 }
e6d66171 3403
d4c2aa60 3404 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3405 return false;
3406
3407 *out_blocks = res_blocks;
3408 *out_lines = res_lines;
2d41c0b5
PB		 3409
3410 return true;
3411}
3412
3413static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3414 struct skl_ddb_allocation *ddb,
024c9045 3415 struct intel_crtc_state *cstate,
2d41c0b5 3416 int level,
2d41c0b5
PB		 3417 struct skl_wm_level *result)
3418{
024c9045
MR		 3419 struct drm_device *dev = dev_priv->dev;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3421 struct intel_plane *intel_plane;
2d41c0b5 3422 uint16_t ddb_blocks;
024c9045
MR		 3423 enum pipe pipe = intel_crtc->pipe;
3424
3425 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3426 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3427
2d41c0b5
PB		 3428 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3429
d4c2aa60 3430 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3431 cstate,
3432 intel_plane,
2d41c0b5 3433 ddb_blocks,
d4c2aa60 3434 level,
2d41c0b5
PB		 3435 &result->plane_res_b[i],
3436 &result->plane_res_l[i]);
3437 }
2d41c0b5
PB		 3438}
3439
407b50f3 3440static uint32_t
024c9045 3441skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3442{
024c9045 3443 if (!cstate->base.active)
407b50f3
DL		 3444 return 0;
3445
024c9045 3446 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3447 return 0;
407b50f3 3448
024c9045
MR		 3449 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3450 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3451}
3452
024c9045 3453static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3454 struct skl_wm_level *trans_wm /* out */)
407b50f3 3455{
024c9045 3456 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3458 struct intel_plane *intel_plane;
9414f563 3459
024c9045 3460 if (!cstate->base.active)
407b50f3 3461 return;
9414f563
DL		 3462
3463 /* Until we know more, just disable transition WMs */
024c9045
MR		 3464 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3465 int i = skl_wm_plane_id(intel_plane);
3466
9414f563 3467 trans_wm->plane_en[i] = false;
024c9045 3468 }
407b50f3
DL		 3469}
3470
e7649b54
MR		 3471static void skl_build_pipe_wm(struct intel_crtc_state *cstate,
3472 struct skl_ddb_allocation *ddb,
3473 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3474{
024c9045 3475 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3476 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3477 int level, max_level = ilk_wm_max_level(dev);
3478
3479 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3480 skl_compute_wm_level(dev_priv, ddb, cstate,
3481 level, &pipe_wm->wm[level]);
2d41c0b5 3482 }
024c9045 3483 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3484
024c9045 3485 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3486}
3487
3488static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3489 struct skl_pipe_wm *p_wm,
3490 struct skl_wm_values *r,
3491 struct intel_crtc *intel_crtc)
3492{
3493 int level, max_level = ilk_wm_max_level(dev);
3494 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3495 uint32_t temp;
3496 int i;
2d41c0b5
PB		 3497
3498 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3499 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3500 temp = 0;
2d41c0b5
PB		 3501
3502 temp |= p_wm->wm[level].plane_res_l[i] <<
3503 PLANE_WM_LINES_SHIFT;
3504 temp |= p_wm->wm[level].plane_res_b[i];
3505 if (p_wm->wm[level].plane_en[i])
3506 temp |= PLANE_WM_EN;
3507
3508 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3509 }
3510
3511 temp = 0;
2d41c0b5 3512
4969d33e
MR		 3513 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3514 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3515
4969d33e 3516 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3517 temp |= PLANE_WM_EN;
3518
4969d33e 3519 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3520
3521 }
3522
9414f563
DL		 3523 /* transition WMs */
3524 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3525 temp = 0;
3526 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3527 temp |= p_wm->trans_wm.plane_res_b[i];
3528 if (p_wm->trans_wm.plane_en[i])
3529 temp |= PLANE_WM_EN;
3530
3531 r->plane_trans[pipe][i] = temp;
3532 }
3533
3534 temp = 0;
4969d33e
MR		 3535 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3536 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3537 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3538 temp |= PLANE_WM_EN;
3539
4969d33e 3540 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3541
2d41c0b5
PB		 3542 r->wm_linetime[pipe] = p_wm->linetime;
3543}
3544
f0f59a00
VS		 3545static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3546 i915_reg_t reg,
16160e3d
DL		 3547 const struct skl_ddb_entry *entry)
3548{
3549 if (entry->end)
3550 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3551 else
3552 I915_WRITE(reg, 0);
3553}
3554
2d41c0b5
PB		 3555static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3556 const struct skl_wm_values *new)
3557{
3558 struct drm_device *dev = dev_priv->dev;
3559 struct intel_crtc *crtc;
3560
19c8054c 3561 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3562 int i, level, max_level = ilk_wm_max_level(dev);
3563 enum pipe pipe = crtc->pipe;
3564
5d374d96
DL		 3565 if (!new->dirty[pipe])
3566 continue;
8211bd5b 3567
5d374d96 3568 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3569
5d374d96
DL		 3570 for (level = 0; level <= max_level; level++) {
3571 for (i = 0; i < intel_num_planes(crtc); i++)
3572 I915_WRITE(PLANE_WM(pipe, i, level),
3573 new->plane[pipe][i][level]);
3574 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3575 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3576 }
5d374d96
DL		 3577 for (i = 0; i < intel_num_planes(crtc); i++)
3578 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3579 new->plane_trans[pipe][i]);
4969d33e
MR		 3580 I915_WRITE(CUR_WM_TRANS(pipe),
3581 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3582
2cd601c6 3583 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3584 skl_ddb_entry_write(dev_priv,
3585 PLANE_BUF_CFG(pipe, i),
3586 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3587 skl_ddb_entry_write(dev_priv,
3588 PLANE_NV12_BUF_CFG(pipe, i),
3589 &new->ddb.y_plane[pipe][i]);
3590 }
5d374d96
DL		 3591
3592 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3593 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3594 }
2d41c0b5
PB		 3595}
3596
0e8fb7ba
DL		 3597/*
3598 * When setting up a new DDB allocation arrangement, we need to correctly
3599 * sequence the times at which the new allocations for the pipes are taken into
3600 * account or we'll have pipes fetching from space previously allocated to
3601 * another pipe.
3602 *
3603 * Roughly the sequence looks like:
3604 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3605 * overlapping with a previous light-up pipe (another way to put it is:
3606 * pipes with their new allocation strickly included into their old ones).
3607 * 2. re-allocate the other pipes that get their allocation reduced
3608 * 3. allocate the pipes having their allocation increased
3609 *
3610 * Steps 1. and 2. are here to take care of the following case:
3611 * - Initially DDB looks like this:
3612 * | B | C |
3613 * - enable pipe A.
3614 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3615 * allocation
3616 * | A | B | C |
3617 *
3618 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3619 */
3620
d21b795c
DL		 3621static void
3622skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3623{
0e8fb7ba
DL		 3624 int plane;
3625
d21b795c
DL		 3626 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3627
dd740780 3628 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3629 I915_WRITE(PLANE_SURF(pipe, plane),
3630 I915_READ(PLANE_SURF(pipe, plane)));
3631 }
3632 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3633}
3634
3635static bool
3636skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3637 const struct skl_ddb_allocation *new,
3638 enum pipe pipe)
3639{
3640 uint16_t old_size, new_size;
3641
3642 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3643 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3644
3645 return old_size != new_size &&
3646 new->pipe[pipe].start >= old->pipe[pipe].start &&
3647 new->pipe[pipe].end <= old->pipe[pipe].end;
3648}
3649
3650static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3651 struct skl_wm_values *new_values)
3652{
3653 struct drm_device *dev = dev_priv->dev;
3654 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3655 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3656 struct intel_crtc *crtc;
3657 enum pipe pipe;
3658
3659 new_ddb = &new_values->ddb;
3660 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3661
3662 /*
3663 * First pass: flush the pipes with the new allocation contained into
3664 * the old space.
3665 *
3666 * We'll wait for the vblank on those pipes to ensure we can safely
3667 * re-allocate the freed space without this pipe fetching from it.
3668 */
3669 for_each_intel_crtc(dev, crtc) {
3670 if (!crtc->active)
3671 continue;
3672
3673 pipe = crtc->pipe;
3674
3675 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3676 continue;
3677
d21b795c 3678 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3679 intel_wait_for_vblank(dev, pipe);
3680
3681 reallocated[pipe] = true;
3682 }
3683
3684
3685 /*
3686 * Second pass: flush the pipes that are having their allocation
3687 * reduced, but overlapping with a previous allocation.
3688 *
3689 * Here as well we need to wait for the vblank to make sure the freed
3690 * space is not used anymore.
3691 */
3692 for_each_intel_crtc(dev, crtc) {
3693 if (!crtc->active)
3694 continue;
3695
3696 pipe = crtc->pipe;
3697
3698 if (reallocated[pipe])
3699 continue;
3700
3701 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3702 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3703 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3704 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3705 reallocated[pipe] = true;
0e8fb7ba 3706 }
0e8fb7ba
DL		 3707 }
3708
3709 /*
3710 * Third pass: flush the pipes that got more space allocated.
3711 *
3712 * We don't need to actively wait for the update here, next vblank
3713 * will just get more DDB space with the correct WM values.
3714 */
3715 for_each_intel_crtc(dev, crtc) {
3716 if (!crtc->active)
3717 continue;
3718
3719 pipe = crtc->pipe;
3720
3721 /*
3722 * At this point, only the pipes more space than before are
3723 * left to re-allocate.
3724 */
3725 if (reallocated[pipe])
3726 continue;
3727
d21b795c 3728 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3729 }
3730}
3731
2d41c0b5 3732static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3733 struct skl_ddb_allocation *ddb, /* out */
3734 struct skl_pipe_wm *pipe_wm /* out */)
3735{
3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3737 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3738
c107acfe 3739 WARN_ON(skl_allocate_pipe_ddb(cstate, ddb) != 0);
e7649b54 3740 skl_build_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3741
4e0963c7 3742 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3743 return false;
3744
4e0963c7 3745 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3746
2d41c0b5
PB		 3747 return true;
3748}
3749
3750static void skl_update_other_pipe_wm(struct drm_device *dev,
3751 struct drm_crtc *crtc,
2d41c0b5
PB		 3752 struct skl_wm_values *r)
3753{
3754 struct intel_crtc *intel_crtc;
3755 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3756
3757 /*
3758 * If the WM update hasn't changed the allocation for this_crtc (the
3759 * crtc we are currently computing the new WM values for), other
3760 * enabled crtcs will keep the same allocation and we don't need to
3761 * recompute anything for them.
3762 */
3763 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3764 return;
3765
3766 /*
3767 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3768 * other active pipes need new DDB allocation and WM values.
3769 */
19c8054c 3770 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3771 struct skl_pipe_wm pipe_wm = {};
3772 bool wm_changed;
3773
3774 if (this_crtc->pipe == intel_crtc->pipe)
3775 continue;
3776
3777 if (!intel_crtc->active)
3778 continue;
3779
aa363136 3780 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3781 &r->ddb, &pipe_wm);
3782
3783 /*
3784 * If we end up re-computing the other pipe WM values, it's
3785 * because it was really needed, so we expect the WM values to
3786 * be different.
3787 */
3788 WARN_ON(!wm_changed);
3789
024c9045 3790 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3791 r->dirty[intel_crtc->pipe] = true;
3792 }
3793}
3794
adda50b8
BP		 3795static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3796{
3797 watermarks->wm_linetime[pipe] = 0;
3798 memset(watermarks->plane[pipe], 0,
3799 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3800 memset(watermarks->plane_trans[pipe],
3801 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3802 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3803
3804 /* Clear ddb entries for pipe */
3805 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3806 memset(&watermarks->ddb.plane[pipe], 0,
3807 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3808 memset(&watermarks->ddb.y_plane[pipe], 0,
3809 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3810 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3811 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3812
3813}
3814
2d41c0b5
PB		 3815static void skl_update_wm(struct drm_crtc *crtc)
3816{
3817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3818 struct drm_device *dev = crtc->dev;
3819 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3820 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7 3821 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 3822 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
2d41c0b5 3823
adda50b8
BP		 3824
3825 /* Clear all dirty flags */
3826 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3827
3828 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3829
aa363136 3830 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3831 return;
3832
4e0963c7 3833 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3834 results->dirty[intel_crtc->pipe] = true;
3835
aa363136 3836 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3837 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3838 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3839
3840 /* store the new configuration */
3841 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3842}
3843
d890565c
VS		 3844static void ilk_compute_wm_config(struct drm_device *dev,
3845 struct intel_wm_config *config)
3846{
3847 struct intel_crtc *crtc;
3848
3849 /* Compute the currently _active_ config */
3850 for_each_intel_crtc(dev, crtc) {
3851 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3852
3853 if (!wm->pipe_enabled)
3854 continue;
3855
3856 config->sprites_enabled |= wm->sprites_enabled;
3857 config->sprites_scaled |= wm->sprites_scaled;
3858 config->num_pipes_active++;
3859 }
3860}
3861
ed4a6a7c 3862static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3863{
ed4a6a7c 3864 struct drm_device *dev = dev_priv->dev;
b9d5c839 3865 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3866 struct ilk_wm_maximums max;
d890565c 3867 struct intel_wm_config config = {};
820c1980 3868 struct ilk_wm_values results = {};
77c122bc 3869 enum intel_ddb_partitioning partitioning;
261a27d1 3870
d890565c
VS		 3871 ilk_compute_wm_config(dev, &config);
3872
3873 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3874 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3875
3876 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3877 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3878 config.num_pipes_active == 1 && config.sprites_enabled) {
3879 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3880 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3881
820c1980 3882 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3883 } else {
198a1e9b 3884 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3885 }
3886
198a1e9b 3887 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3888 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3889
820c1980 3890 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3891
820c1980 3892 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3893}
3894
ed4a6a7c 3895static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 3896{
ed4a6a7c
MR		 3897 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3898 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3899
ed4a6a7c 3900 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 3901 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 3902 ilk_program_watermarks(dev_priv);
3903 mutex_unlock(&dev_priv->wm.wm_mutex);
3904}
bf220452 3905
ed4a6a7c
MR		 3906static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3907{
3908 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3909 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 3910
ed4a6a7c
MR		 3911 mutex_lock(&dev_priv->wm.wm_mutex);
3912 if (cstate->wm.need_postvbl_update) {
e8f1f02e 3913 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 3914 ilk_program_watermarks(dev_priv);
3915 }
3916 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 3917}
3918
3078999f
PB		 3919static void skl_pipe_wm_active_state(uint32_t val,
3920 struct skl_pipe_wm *active,
3921 bool is_transwm,
3922 bool is_cursor,
3923 int i,
3924 int level)
3925{
3926 bool is_enabled = (val & PLANE_WM_EN) != 0;
3927
3928 if (!is_transwm) {
3929 if (!is_cursor) {
3930 active->wm[level].plane_en[i] = is_enabled;
3931 active->wm[level].plane_res_b[i] =
3932 val & PLANE_WM_BLOCKS_MASK;
3933 active->wm[level].plane_res_l[i] =
3934 (val >> PLANE_WM_LINES_SHIFT) &
3935 PLANE_WM_LINES_MASK;
3936 } else {
4969d33e
MR		 3937 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3938 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3939 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3940 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3941 (val >> PLANE_WM_LINES_SHIFT) &
3942 PLANE_WM_LINES_MASK;
3943 }
3944 } else {
3945 if (!is_cursor) {
3946 active->trans_wm.plane_en[i] = is_enabled;
3947 active->trans_wm.plane_res_b[i] =
3948 val & PLANE_WM_BLOCKS_MASK;
3949 active->trans_wm.plane_res_l[i] =
3950 (val >> PLANE_WM_LINES_SHIFT) &
3951 PLANE_WM_LINES_MASK;
3952 } else {
4969d33e
MR		 3953 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3954 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3955 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3956 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3957 (val >> PLANE_WM_LINES_SHIFT) &
3958 PLANE_WM_LINES_MASK;
3959 }
3960 }
3961}
3962
3963static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3964{
3965 struct drm_device *dev = crtc->dev;
3966 struct drm_i915_private *dev_priv = dev->dev_private;
3967 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 3969 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 3970 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 3971 enum pipe pipe = intel_crtc->pipe;
3972 int level, i, max_level;
3973 uint32_t temp;
3974
3975 max_level = ilk_wm_max_level(dev);
3976
3977 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3978
3979 for (level = 0; level <= max_level; level++) {
3980 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3981 hw->plane[pipe][i][level] =
3982 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3983 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3984 }
3985
3986 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3987 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3988 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3989
3ef00284 3990 if (!intel_crtc->active)
3078999f
PB		 3991 return;
3992
3993 hw->dirty[pipe] = true;
3994
3995 active->linetime = hw->wm_linetime[pipe];
3996
3997 for (level = 0; level <= max_level; level++) {
3998 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3999 temp = hw->plane[pipe][i][level];
4000 skl_pipe_wm_active_state(temp, active, false,
4001 false, i, level);
4002 }
4969d33e 4003 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4004 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4005 }
4006
4007 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4008 temp = hw->plane_trans[pipe][i];
4009 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4010 }
4011
4969d33e 4012 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4013 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4014
4015 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4016}
4017
4018void skl_wm_get_hw_state(struct drm_device *dev)
4019{
a269c583
DL		 4020 struct drm_i915_private *dev_priv = dev->dev_private;
4021 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4022 struct drm_crtc *crtc;
a1de91e5 4023 struct intel_crtc *intel_crtc;
3078999f 4024
a269c583 4025 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4026 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4027 skl_pipe_wm_get_hw_state(crtc);
a1de91e5
MR		 4028
4029 /* Calculate plane data rates */
4030 for_each_intel_crtc(dev, intel_crtc) {
4031 struct intel_crtc_state *cstate = intel_crtc->config;
4032 struct intel_plane *intel_plane;
4033
4034 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4035 const struct drm_plane_state *pstate =
4036 intel_plane->base.state;
4037 int id = skl_wm_plane_id(intel_plane);
4038
4039 cstate->wm.skl.plane_data_rate[id] =
4040 skl_plane_relative_data_rate(cstate, pstate, 0);
4041 cstate->wm.skl.plane_y_data_rate[id] =
4042 skl_plane_relative_data_rate(cstate, pstate, 1);
4043 }
4044 }
3078999f
PB		 4045}
4046
243e6a44
VS		 4047static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4048{
4049 struct drm_device *dev = crtc->dev;
4050 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4051 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4053 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4054 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4055 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4056 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4057 [PIPE_A] = WM0_PIPEA_ILK,
4058 [PIPE_B] = WM0_PIPEB_ILK,
4059 [PIPE_C] = WM0_PIPEC_IVB,
4060 };
4061
4062 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4063 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4064 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4065
3ef00284 4066 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4067
4068 if (active->pipe_enabled) {
243e6a44
VS		 4069 u32 tmp = hw->wm_pipe[pipe];
4070
4071 /*
4072 * For active pipes LP0 watermark is marked as
4073 * enabled, and LP1+ watermaks as disabled since
4074 * we can't really reverse compute them in case
4075 * multiple pipes are active.
4076 */
4077 active->wm[0].enable = true;
4078 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4079 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4080 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4081 active->linetime = hw->wm_linetime[pipe];
4082 } else {
4083 int level, max_level = ilk_wm_max_level(dev);
4084
4085 /*
4086 * For inactive pipes, all watermark levels
4087 * should be marked as enabled but zeroed,
4088 * which is what we'd compute them to.
4089 */
4090 for (level = 0; level <= max_level; level++)
4091 active->wm[level].enable = true;
4092 }
4e0963c7
MR		 4093
4094 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4095}
4096
6eb1a681
VS		 4097#define _FW_WM(value, plane) \
4098 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4099#define _FW_WM_VLV(value, plane) \
4100 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4101
4102static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4103 struct vlv_wm_values *wm)
4104{
4105 enum pipe pipe;
4106 uint32_t tmp;
4107
4108 for_each_pipe(dev_priv, pipe) {
4109 tmp = I915_READ(VLV_DDL(pipe));
4110
4111 wm->ddl[pipe].primary =
4112 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4113 wm->ddl[pipe].cursor =
4114 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4115 wm->ddl[pipe].sprite[0] =
4116 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4117 wm->ddl[pipe].sprite[1] =
4118 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4119 }
4120
4121 tmp = I915_READ(DSPFW1);
4122 wm->sr.plane = _FW_WM(tmp, SR);
4123 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4124 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4125 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4126
4127 tmp = I915_READ(DSPFW2);
4128 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4129 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4130 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4131
4132 tmp = I915_READ(DSPFW3);
4133 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4134
4135 if (IS_CHERRYVIEW(dev_priv)) {
4136 tmp = I915_READ(DSPFW7_CHV);
4137 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4138 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4139
4140 tmp = I915_READ(DSPFW8_CHV);
4141 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4142 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4143
4144 tmp = I915_READ(DSPFW9_CHV);
4145 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4146 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4147
4148 tmp = I915_READ(DSPHOWM);
4149 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4150 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4151 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4152 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4153 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4154 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4155 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4156 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4157 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4158 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4159 } else {
4160 tmp = I915_READ(DSPFW7);
4161 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4162 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4163
4164 tmp = I915_READ(DSPHOWM);
4165 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4166 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4167 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4168 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4169 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4170 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4171 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4172 }
4173}
4174
4175#undef _FW_WM
4176#undef _FW_WM_VLV
4177
4178void vlv_wm_get_hw_state(struct drm_device *dev)
4179{
4180 struct drm_i915_private *dev_priv = to_i915(dev);
4181 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4182 struct intel_plane *plane;
4183 enum pipe pipe;
4184 u32 val;
4185
4186 vlv_read_wm_values(dev_priv, wm);
4187
4188 for_each_intel_plane(dev, plane) {
4189 switch (plane->base.type) {
4190 int sprite;
4191 case DRM_PLANE_TYPE_CURSOR:
4192 plane->wm.fifo_size = 63;
4193 break;
4194 case DRM_PLANE_TYPE_PRIMARY:
4195 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4196 break;
4197 case DRM_PLANE_TYPE_OVERLAY:
4198 sprite = plane->plane;
4199 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4200 break;
4201 }
4202 }
4203
4204 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4205 wm->level = VLV_WM_LEVEL_PM2;
4206
4207 if (IS_CHERRYVIEW(dev_priv)) {
4208 mutex_lock(&dev_priv->rps.hw_lock);
4209
4210 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4211 if (val & DSP_MAXFIFO_PM5_ENABLE)
4212 wm->level = VLV_WM_LEVEL_PM5;
4213
58590c14
VS		 4214 /*
4215 * If DDR DVFS is disabled in the BIOS, Punit
4216 * will never ack the request. So if that happens
4217 * assume we don't have to enable/disable DDR DVFS
4218 * dynamically. To test that just set the REQ_ACK
4219 * bit to poke the Punit, but don't change the
4220 * HIGH/LOW bits so that we don't actually change
4221 * the current state.
4222 */
6eb1a681 4223 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4224 val |= FORCE_DDR_FREQ_REQ_ACK;
4225 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4226
4227 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4228 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4229 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4230 "assuming DDR DVFS is disabled\n");
4231 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4232 } else {
4233 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4234 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4235 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4236 }
6eb1a681
VS		 4237
4238 mutex_unlock(&dev_priv->rps.hw_lock);
4239 }
4240
4241 for_each_pipe(dev_priv, pipe)
4242 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4243 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4244 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4245
4246 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4247 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4248}
4249
243e6a44
VS		 4250void ilk_wm_get_hw_state(struct drm_device *dev)
4251{
4252 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4253 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4254 struct drm_crtc *crtc;
4255
70e1e0ec 4256 for_each_crtc(dev, crtc)
243e6a44
VS		 4257 ilk_pipe_wm_get_hw_state(crtc);
4258
4259 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4260 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4261 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4262
4263 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4264 if (INTEL_INFO(dev)->gen >= 7) {
4265 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4266 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4267 }
243e6a44 4268
a42a5719 4269 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4270 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4271 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4272 else if (IS_IVYBRIDGE(dev))
4273 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4274 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4275
4276 hw->enable_fbc_wm =
4277 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4278}
4279
b445e3b0
ED		 4280/**
4281 * intel_update_watermarks - update FIFO watermark values based on current modes
4282 *
4283 * Calculate watermark values for the various WM regs based on current mode
4284 * and plane configuration.
4285 *
4286 * There are several cases to deal with here:
4287 * - normal (i.e. non-self-refresh)
4288 * - self-refresh (SR) mode
4289 * - lines are large relative to FIFO size (buffer can hold up to 2)
4290 * - lines are small relative to FIFO size (buffer can hold more than 2
4291 * lines), so need to account for TLB latency
4292 *
4293 * The normal calculation is:
4294 * watermark = dotclock * bytes per pixel * latency
4295 * where latency is platform & configuration dependent (we assume pessimal
4296 * values here).
4297 *
4298 * The SR calculation is:
4299 * watermark = (trunc(latency/line time)+1) * surface width *
4300 * bytes per pixel
4301 * where
4302 * line time = htotal / dotclock
4303 * surface width = hdisplay for normal plane and 64 for cursor
4304 * and latency is assumed to be high, as above.
4305 *
4306 * The final value programmed to the register should always be rounded up,
4307 * and include an extra 2 entries to account for clock crossings.
4308 *
4309 * We don't use the sprite, so we can ignore that. And on Crestline we have
4310 * to set the non-SR watermarks to 8.
4311 */
46ba614c 4312void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4313{
46ba614c 4314 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4315
4316 if (dev_priv->display.update_wm)
46ba614c 4317 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4318}
4319
e2828914 4320/*
9270388e 4321 * Lock protecting IPS related data structures
9270388e
DV		 4322 */
4323DEFINE_SPINLOCK(mchdev_lock);
4324
4325/* Global for IPS driver to get at the current i915 device. Protected by
4326 * mchdev_lock. */
4327static struct drm_i915_private *i915_mch_dev;
4328
91d14251 4329bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4330{
2b4e57bd
ED		 4331 u16 rgvswctl;
4332
9270388e
DV		 4333 assert_spin_locked(&mchdev_lock);
4334
2b4e57bd
ED		 4335 rgvswctl = I915_READ16(MEMSWCTL);
4336 if (rgvswctl & MEMCTL_CMD_STS) {
4337 DRM_DEBUG("gpu busy, RCS change rejected\n");
4338 return false; /* still busy with another command */
4339 }
4340
4341 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4342 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4343 I915_WRITE16(MEMSWCTL, rgvswctl);
4344 POSTING_READ16(MEMSWCTL);
4345
4346 rgvswctl |= MEMCTL_CMD_STS;
4347 I915_WRITE16(MEMSWCTL, rgvswctl);
4348
4349 return true;
4350}
4351
91d14251 4352static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4353{
84f1b20f 4354 u32 rgvmodectl;
2b4e57bd
ED		 4355 u8 fmax, fmin, fstart, vstart;
4356
9270388e
DV		 4357 spin_lock_irq(&mchdev_lock);
4358
84f1b20f
TU		 4359 rgvmodectl = I915_READ(MEMMODECTL);
4360
2b4e57bd
ED		 4361 /* Enable temp reporting */
4362 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4363 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4364
4365 /* 100ms RC evaluation intervals */
4366 I915_WRITE(RCUPEI, 100000);
4367 I915_WRITE(RCDNEI, 100000);
4368
4369 /* Set max/min thresholds to 90ms and 80ms respectively */
4370 I915_WRITE(RCBMAXAVG, 90000);
4371 I915_WRITE(RCBMINAVG, 80000);
4372
4373 I915_WRITE(MEMIHYST, 1);
4374
4375 /* Set up min, max, and cur for interrupt handling */
4376 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4377 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4378 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4379 MEMMODE_FSTART_SHIFT;
4380
616847e7 4381 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4382 PXVFREQ_PX_SHIFT;
4383
20e4d407
DV		 4384 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4385 dev_priv->ips.fstart = fstart;
2b4e57bd 4386
20e4d407
DV		 4387 dev_priv->ips.max_delay = fstart;
4388 dev_priv->ips.min_delay = fmin;
4389 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4390
4391 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4392 fmax, fmin, fstart);
4393
4394 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4395
4396 /*
4397 * Interrupts will be enabled in ironlake_irq_postinstall
4398 */
4399
4400 I915_WRITE(VIDSTART, vstart);
4401 POSTING_READ(VIDSTART);
4402
4403 rgvmodectl |= MEMMODE_SWMODE_EN;
4404 I915_WRITE(MEMMODECTL, rgvmodectl);
4405
9270388e 4406 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4407 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4408 mdelay(1);
2b4e57bd 4409
91d14251 4410 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4411
7d81c3e0
VS		 4412 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4413 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4414 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4415 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4416 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4417
4418 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4419}
4420
91d14251 4421static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4422{
9270388e
DV		 4423 u16 rgvswctl;
4424
4425 spin_lock_irq(&mchdev_lock);
4426
4427 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4428
4429 /* Ack interrupts, disable EFC interrupt */
4430 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4431 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4432 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4433 I915_WRITE(DEIIR, DE_PCU_EVENT);
4434 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4435
4436 /* Go back to the starting frequency */
91d14251 4437 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4438 mdelay(1);
2b4e57bd
ED		 4439 rgvswctl |= MEMCTL_CMD_STS;
4440 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4441 mdelay(1);
2b4e57bd 4442
9270388e 4443 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4444}
4445
acbe9475
DV		 4446/* There's a funny hw issue where the hw returns all 0 when reading from
4447 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4448 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4449 * all limits and the gpu stuck at whatever frequency it is at atm).
4450 */
74ef1173 4451static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4452{
7b9e0ae6 4453 u32 limits;
2b4e57bd 4454
20b46e59
DV		 4455 /* Only set the down limit when we've reached the lowest level to avoid
4456 * getting more interrupts, otherwise leave this clear. This prevents a
4457 * race in the hw when coming out of rc6: There's a tiny window where
4458 * the hw runs at the minimal clock before selecting the desired
4459 * frequency, if the down threshold expires in that window we will not
4460 * receive a down interrupt. */
2d1fe073 4461 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4462 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4463 if (val <= dev_priv->rps.min_freq_softlimit)
4464 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4465 } else {
4466 limits = dev_priv->rps.max_freq_softlimit << 24;
4467 if (val <= dev_priv->rps.min_freq_softlimit)
4468 limits |= dev_priv->rps.min_freq_softlimit << 16;
4469 }
20b46e59
DV		 4470
4471 return limits;
4472}
4473
dd75fdc8
CW		 4474static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4475{
4476 int new_power;
8a586437
AG		 4477 u32 threshold_up = 0, threshold_down = 0; /* in % */
4478 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4479
4480 new_power = dev_priv->rps.power;
4481 switch (dev_priv->rps.power) {
4482 case LOW_POWER:
b39fb297 4483 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4484 new_power = BETWEEN;
4485 break;
4486
4487 case BETWEEN:
b39fb297 4488 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4489 new_power = LOW_POWER;
b39fb297 4490 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4491 new_power = HIGH_POWER;
4492 break;
4493
4494 case HIGH_POWER:
b39fb297 4495 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4496 new_power = BETWEEN;
4497 break;
4498 }
4499 /* Max/min bins are special */
aed242ff 4500 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4501 new_power = LOW_POWER;
aed242ff 4502 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4503 new_power = HIGH_POWER;
4504 if (new_power == dev_priv->rps.power)
4505 return;
4506
4507 /* Note the units here are not exactly 1us, but 1280ns. */
4508 switch (new_power) {
4509 case LOW_POWER:
4510 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4511 ei_up = 16000;
4512 threshold_up = 95;
dd75fdc8
CW		 4513
4514 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4515 ei_down = 32000;
4516 threshold_down = 85;
dd75fdc8
CW		 4517 break;
4518
4519 case BETWEEN:
4520 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4521 ei_up = 13000;
4522 threshold_up = 90;
dd75fdc8
CW		 4523
4524 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4525 ei_down = 32000;
4526 threshold_down = 75;
dd75fdc8
CW		 4527 break;
4528
4529 case HIGH_POWER:
4530 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4531 ei_up = 10000;
4532 threshold_up = 85;
dd75fdc8
CW		 4533
4534 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4535 ei_down = 32000;
4536 threshold_down = 60;
dd75fdc8
CW		 4537 break;
4538 }
4539
8a586437
AG		 4540 I915_WRITE(GEN6_RP_UP_EI,
4541 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4542 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4543 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4544
4545 I915_WRITE(GEN6_RP_DOWN_EI,
4546 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4547 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4548 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4549
4550 I915_WRITE(GEN6_RP_CONTROL,
4551 GEN6_RP_MEDIA_TURBO |
4552 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4553 GEN6_RP_MEDIA_IS_GFX |
4554 GEN6_RP_ENABLE |
4555 GEN6_RP_UP_BUSY_AVG |
4556 GEN6_RP_DOWN_IDLE_AVG);
4557
dd75fdc8 4558 dev_priv->rps.power = new_power;
8fb55197
CW		 4559 dev_priv->rps.up_threshold = threshold_up;
4560 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4561 dev_priv->rps.last_adj = 0;
4562}
4563
2876ce73
CW		 4564static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4565{
4566 u32 mask = 0;
4567
4568 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4569 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4570 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4571 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4572
7b3c29f6
CW		 4573 mask &= dev_priv->pm_rps_events;
4574
59d02a1f 4575 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4576}
4577
b8a5ff8d
JM		 4578/* gen6_set_rps is called to update the frequency request, but should also be
4579 * called when the range (min_delay and max_delay) is modified so that we can
4580 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4581static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4582{
23eafea6 4583 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4584 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4585 return;
4586
4fc688ce 4587 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4588 WARN_ON(val > dev_priv->rps.max_freq);
4589 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4590
eb64cad1
CW		 4591 /* min/max delay may still have been modified so be sure to
4592 * write the limits value.
4593 */
4594 if (val != dev_priv->rps.cur_freq) {
4595 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4596
dc97997a 4597 if (IS_GEN9(dev_priv))
5704195c
AG		 4598 I915_WRITE(GEN6_RPNSWREQ,
4599 GEN9_FREQUENCY(val));
dc97997a 4600 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4601 I915_WRITE(GEN6_RPNSWREQ,
4602 HSW_FREQUENCY(val));
4603 else
4604 I915_WRITE(GEN6_RPNSWREQ,
4605 GEN6_FREQUENCY(val) |
4606 GEN6_OFFSET(0) |
4607 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4608 }
7b9e0ae6 4609
7b9e0ae6
CW		 4610 /* Make sure we continue to get interrupts
4611 * until we hit the minimum or maximum frequencies.
4612 */
74ef1173 4613 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4614 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4615
d5570a72
BW		 4616 POSTING_READ(GEN6_RPNSWREQ);
4617
b39fb297 4618 dev_priv->rps.cur_freq = val;
0f94592e 4619 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4620}
4621
dc97997a 4622static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4623{
ffe02b40 4624 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4625 WARN_ON(val > dev_priv->rps.max_freq);
4626 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4627
dc97997a 4628 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4629 "Odd GPU freq value\n"))
4630 val &= ~1;
4631
cd25dd5b
D		 4632 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4633
8fb55197 4634 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4635 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4636 if (!IS_CHERRYVIEW(dev_priv))
4637 gen6_set_rps_thresholds(dev_priv, val);
4638 }
ffe02b40 4639
ffe02b40
VS		 4640 dev_priv->rps.cur_freq = val;
4641 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4642}
4643
a7f6e231 4644/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4645 *
4646 * * If Gfx is Idle, then
a7f6e231
D		 4647 * 1. Forcewake Media well.
4648 * 2. Request idle freq.
4649 * 3. Release Forcewake of Media well.
76c3552f
D		 4650*/
4651static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4652{
aed242ff 4653 u32 val = dev_priv->rps.idle_freq;
5549d25f 4654
aed242ff 4655 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4656 return;
4657
a7f6e231
D		 4658 /* Wake up the media well, as that takes a lot less
4659 * power than the Render well. */
4660 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4661 valleyview_set_rps(dev_priv, val);
a7f6e231 4662 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4663}
4664
43cf3bf0
CW		 4665void gen6_rps_busy(struct drm_i915_private *dev_priv)
4666{
4667 mutex_lock(&dev_priv->rps.hw_lock);
4668 if (dev_priv->rps.enabled) {
4669 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4670 gen6_rps_reset_ei(dev_priv);
4671 I915_WRITE(GEN6_PMINTRMSK,
4672 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4673 }
4674 mutex_unlock(&dev_priv->rps.hw_lock);
4675}
4676
b29c19b6
CW		 4677void gen6_rps_idle(struct drm_i915_private *dev_priv)
4678{
4679 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4680 if (dev_priv->rps.enabled) {
dc97997a 4681 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 4682 vlv_set_rps_idle(dev_priv);
7526ed79 4683 else
dc97997a 4684 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 4685 dev_priv->rps.last_adj = 0;
43cf3bf0 4686 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4687 }
8d3afd7d 4688 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4689
8d3afd7d 4690 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4691 while (!list_empty(&dev_priv->rps.clients))
4692 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4693 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4694}
4695
1854d5ca 4696void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4697 struct intel_rps_client *rps,
4698 unsigned long submitted)
b29c19b6 4699{
8d3afd7d
CW		 4700 /* This is intentionally racy! We peek at the state here, then
4701 * validate inside the RPS worker.
4702 */
4703 if (!(dev_priv->mm.busy &&
4704 dev_priv->rps.enabled &&
4705 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4706 return;
43cf3bf0 4707
e61b9958
CW		 4708 /* Force a RPS boost (and don't count it against the client) if
4709 * the GPU is severely congested.
4710 */
d0bc54f2 4711 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4712 rps = NULL;
4713
8d3afd7d
CW		 4714 spin_lock(&dev_priv->rps.client_lock);
4715 if (rps == NULL || list_empty(&rps->link)) {
4716 spin_lock_irq(&dev_priv->irq_lock);
4717 if (dev_priv->rps.interrupts_enabled) {
4718 dev_priv->rps.client_boost = true;
4719 queue_work(dev_priv->wq, &dev_priv->rps.work);
4720 }
4721 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4722
2e1b8730
CW		 4723 if (rps != NULL) {
4724 list_add(&rps->link, &dev_priv->rps.clients);
4725 rps->boosts++;
1854d5ca
CW		 4726 } else
4727 dev_priv->rps.boosts++;
c0951f0c 4728 }
8d3afd7d 4729 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4730}
4731
dc97997a 4732void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 4733{
dc97997a
CW		 4734 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4735 valleyview_set_rps(dev_priv, val);
ffe02b40 4736 else
dc97997a 4737 gen6_set_rps(dev_priv, val);
0a073b84
JB		 4738}
4739
dc97997a 4740static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 4741{
20e49366 4742 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4743 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4744}
4745
dc97997a 4746static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 4747{
2030d684
AG		 4748 I915_WRITE(GEN6_RP_CONTROL, 0);
4749}
4750
dc97997a 4751static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 4752{
d20d4f0c 4753 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4754 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4755 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4756}
4757
dc97997a 4758static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 4759{
38807746
D		 4760 I915_WRITE(GEN6_RC_CONTROL, 0);
4761}
4762
dc97997a 4763static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 4764{
98a2e5f9
D		 4765 /* we're doing forcewake before Disabling RC6,
4766 * This what the BIOS expects when going into suspend */
59bad947 4767 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4768
44fc7d5c 4769 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4770
59bad947 4771 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4772}
4773
dc97997a 4774static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 4775{
dc97997a 4776 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 4777 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4778 mode = GEN6_RC_CTL_RC6_ENABLE;
4779 else
4780 mode = 0;
4781 }
dc97997a 4782 if (HAS_RC6p(dev_priv))
58abf1da 4783 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4784 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4785 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4786 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4787
4788 else
4789 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4790 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4791}
4792
dc97997a 4793static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 4794{
72e96d64 4795 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 4796 bool enable_rc6 = true;
4797 unsigned long rc6_ctx_base;
4798
4799 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4800 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4801 enable_rc6 = false;
4802 }
4803
4804 /*
4805 * The exact context size is not known for BXT, so assume a page size
4806 * for this check.
4807 */
4808 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 4809 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4810 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4811 ggtt->stolen_reserved_size))) {
274008e8
SAK		 4812 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4813 enable_rc6 = false;
4814 }
4815
4816 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4817 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4818 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4819 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4820 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4821 enable_rc6 = false;
4822 }
4823
4824 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4825 GEN6_RC_CTL_HW_ENABLE)) &&
4826 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4827 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4828 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4829 enable_rc6 = false;
4830 }
4831
4832 return enable_rc6;
4833}
4834
dc97997a 4835int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 4836{
e7d66d89 4837 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 4838 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 4839 return 0;
4840
274008e8
SAK		 4841 if (!enable_rc6)
4842 return 0;
4843
dc97997a 4844 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 4845 DRM_INFO("RC6 disabled by BIOS\n");
4846 return 0;
4847 }
4848
456470eb 4849 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4850 if (enable_rc6 >= 0) {
4851 int mask;
4852
dc97997a 4853 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 4854 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4855 INTEL_RC6pp_ENABLE;
4856 else
4857 mask = INTEL_RC6_ENABLE;
4858
4859 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4860 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4861 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4862
4863 return enable_rc6 & mask;
4864 }
2b4e57bd 4865
dc97997a 4866 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 4867 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4868
4869 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4870}
4871
dc97997a 4872static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0 4873{
93ee2920
TR		 4874 uint32_t rp_state_cap;
4875 u32 ddcc_status = 0;
4876 int ret;
4877
3280e8b0
BW		 4878 /* All of these values are in units of 50MHz */
4879 dev_priv->rps.cur_freq = 0;
93ee2920 4880 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 4881 if (IS_BROXTON(dev_priv)) {
35040562
BP		 4882 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4883 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4884 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4885 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4886 } else {
4887 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4888 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4889 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4890 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4891 }
4892
3280e8b0
BW		 4893 /* hw_max = RP0 until we check for overclocking */
4894 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4895
93ee2920 4896 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 4897 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
4898 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
93ee2920
TR		 4899 ret = sandybridge_pcode_read(dev_priv,
4900 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4901 &ddcc_status);
4902 if (0 == ret)
4903 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4904 clamp_t(u8,
4905 ((ddcc_status >> 8) & 0xff),
4906 dev_priv->rps.min_freq,
4907 dev_priv->rps.max_freq);
93ee2920
TR		 4908 }
4909
dc97997a 4910 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c
AG		 4911 /* Store the frequency values in 16.66 MHZ units, which is
4912 the natural hardware unit for SKL */
4913 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4914 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4915 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4916 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4917 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4918 }
4919
aed242ff
CW		 4920 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4921
3280e8b0
BW		 4922 /* Preserve min/max settings in case of re-init */
4923 if (dev_priv->rps.max_freq_softlimit == 0)
4924 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4925
93ee2920 4926 if (dev_priv->rps.min_freq_softlimit == 0) {
dc97997a 4927 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
93ee2920 4928 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4929 max_t(int, dev_priv->rps.efficient_freq,
4930 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4931 else
4932 dev_priv->rps.min_freq_softlimit =
4933 dev_priv->rps.min_freq;
4934 }
3280e8b0
BW		 4935}
4936
b6fef0ef 4937/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 4938static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 4939{
b6fef0ef
JB		 4940 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4941
dc97997a 4942 gen6_init_rps_frequencies(dev_priv);
ba1c554c 4943
23eafea6 4944 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4945 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 4946 /*
4947 * BIOS could leave the Hw Turbo enabled, so need to explicitly
4948 * clear out the Control register just to avoid inconsitency
4949 * with debugfs interface, which will show Turbo as enabled
4950 * only and that is not expected by the User after adding the
4951 * WaGsvDisableTurbo. Apart from this there is no problem even
4952 * if the Turbo is left enabled in the Control register, as the
4953 * Up/Down interrupts would remain masked.
4954 */
dc97997a 4955 gen9_disable_rps(dev_priv);
23eafea6
SAK		 4956 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4957 return;
4958 }
4959
0beb059a
AG		 4960 /* Program defaults and thresholds for RPS*/
4961 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4962 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4963
4964 /* 1 second timeout*/
4965 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4966 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4967
b6fef0ef 4968 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4969
0beb059a
AG		 4970 /* Leaning on the below call to gen6_set_rps to program/setup the
4971 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4972 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4973 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 4974 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
b6fef0ef
JB		 4975
4976 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4977}
4978
dc97997a 4979static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 4980{
e2f80391 4981 struct intel_engine_cs *engine;
20e49366 4982 uint32_t rc6_mask = 0;
20e49366
ZW		 4983
4984 /* 1a: Software RC state - RC0 */
4985 I915_WRITE(GEN6_RC_STATE, 0);
4986
4987 /* 1b: Get forcewake during program sequence. Although the driver
4988 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4989 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4990
4991 /* 2a: Disable RC states. */
4992 I915_WRITE(GEN6_RC_CONTROL, 0);
4993
4994 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4995
4996 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 4997 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 4998 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4999 else
5000 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5001 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5002 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5003 for_each_engine(engine, dev_priv)
e2f80391 5004 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5005
dc97997a 5006 if (HAS_GUC_UCODE(dev_priv))
97c322e7
SAK		 5007 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5008
20e49366 5009 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5010
38c23527
ZW		 5011 /* 2c: Program Coarse Power Gating Policies. */
5012 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5013 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5014
20e49366 5015 /* 3a: Enable RC6 */
dc97997a 5016 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5017 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5018 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5019 /* WaRsUseTimeoutMode */
dc97997a
CW		 5020 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5021 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5022 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5023 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5024 GEN7_RC_CTL_TO_MODE |
5025 rc6_mask);
3e7732a0
SAK		 5026 } else {
5027 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5028 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5029 GEN6_RC_CTL_EI_MODE(1) |
5030 rc6_mask);
3e7732a0 5031 }
20e49366 5032
cb07bae0
SK		 5033 /*
5034 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5035 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5036 */
dc97997a 5037 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5038 I915_WRITE(GEN9_PG_ENABLE, 0);
5039 else
5040 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5041 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5042
59bad947 5043 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5044}
5045
dc97997a 5046static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5047{
e2f80391 5048 struct intel_engine_cs *engine;
93ee2920 5049 uint32_t rc6_mask = 0;
6edee7f3
BW		 5050
5051 /* 1a: Software RC state - RC0 */
5052 I915_WRITE(GEN6_RC_STATE, 0);
5053
5054 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5055 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5056 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5057
5058 /* 2a: Disable RC states. */
5059 I915_WRITE(GEN6_RC_CONTROL, 0);
5060
93ee2920 5061 /* Initialize rps frequencies */
dc97997a 5062 gen6_init_rps_frequencies(dev_priv);
6edee7f3
BW		 5063
5064 /* 2b: Program RC6 thresholds.*/
5065 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5066 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5067 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5068 for_each_engine(engine, dev_priv)
e2f80391 5069 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5070 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5071 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5072 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5073 else
5074 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5075
5076 /* 3: Enable RC6 */
dc97997a 5077 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5078 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5079 intel_print_rc6_info(dev_priv, rc6_mask);
5080 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5081 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5082 GEN7_RC_CTL_TO_MODE |
5083 rc6_mask);
5084 else
5085 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5086 GEN6_RC_CTL_EI_MODE(1) |
5087 rc6_mask);
6edee7f3
BW		 5088
5089 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5090 I915_WRITE(GEN6_RPNSWREQ,
5091 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5092 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5093 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5094 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5095 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5096
5097 /* Docs recommend 900MHz, and 300 MHz respectively */
5098 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5099 dev_priv->rps.max_freq_softlimit << 24 |
5100 dev_priv->rps.min_freq_softlimit << 16);
5101
5102 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5103 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5104 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5105 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5106
5107 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5108
5109 /* 5: Enable RPS */
7526ed79
DV		 5110 I915_WRITE(GEN6_RP_CONTROL,
5111 GEN6_RP_MEDIA_TURBO |
5112 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5113 GEN6_RP_MEDIA_IS_GFX |
5114 GEN6_RP_ENABLE |
5115 GEN6_RP_UP_BUSY_AVG |
5116 GEN6_RP_DOWN_IDLE_AVG);
5117
5118 /* 6: Ring frequency + overclocking (our driver does this later */
5119
c7f3153a 5120 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5121 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
7526ed79 5122
59bad947 5123 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5124}
5125
dc97997a 5126static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5127{
e2f80391 5128 struct intel_engine_cs *engine;
d060c169 5129 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5130 u32 gtfifodbg;
2b4e57bd 5131 int rc6_mode;
b4ac5afc 5132 int ret;
2b4e57bd 5133
4fc688ce 5134 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5135
2b4e57bd
ED		 5136 /* Here begins a magic sequence of register writes to enable
5137 * auto-downclocking.
5138 *
5139 * Perhaps there might be some value in exposing these to
5140 * userspace...
5141 */
5142 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5143
5144 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5145 gtfifodbg = I915_READ(GTFIFODBG);
5146 if (gtfifodbg) {
2b4e57bd
ED		 5147 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5148 I915_WRITE(GTFIFODBG, gtfifodbg);
5149 }
5150
59bad947 5151 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5152
93ee2920 5153 /* Initialize rps frequencies */
dc97997a 5154 gen6_init_rps_frequencies(dev_priv);
dd0a1aa1 5155
2b4e57bd
ED		 5156 /* disable the counters and set deterministic thresholds */
5157 I915_WRITE(GEN6_RC_CONTROL, 0);
5158
5159 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5160 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5161 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5162 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5163 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5164
b4ac5afc 5165 for_each_engine(engine, dev_priv)
e2f80391 5166 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5167
5168 I915_WRITE(GEN6_RC_SLEEP, 0);
5169 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5170 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5171 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5172 else
5173 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5174 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5175 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5176
5a7dc92a 5177 /* Check if we are enabling RC6 */
dc97997a 5178 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5179 if (rc6_mode & INTEL_RC6_ENABLE)
5180 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5181
5a7dc92a 5182 /* We don't use those on Haswell */
dc97997a 5183 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5184 if (rc6_mode & INTEL_RC6p_ENABLE)
5185 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5186
5a7dc92a
ED		 5187 if (rc6_mode & INTEL_RC6pp_ENABLE)
5188 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5189 }
2b4e57bd 5190
dc97997a 5191 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5192
5193 I915_WRITE(GEN6_RC_CONTROL,
5194 rc6_mask |
5195 GEN6_RC_CTL_EI_MODE(1) |
5196 GEN6_RC_CTL_HW_ENABLE);
5197
dd75fdc8
CW		 5198 /* Power down if completely idle for over 50ms */
5199 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5200 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5201
42c0526c 5202 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5203 if (ret)
42c0526c 5204 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5205
5206 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5207 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5208 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5209 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5210 (pcu_mbox & 0xff) * 50);
b39fb297 5211 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5212 }
5213
dd75fdc8 5214 dev_priv->rps.power = HIGH_POWER; /* force a reset */
dc97997a 5215 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b4e57bd 5216
31643d54
BW		 5217 rc6vids = 0;
5218 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5219 if (IS_GEN6(dev_priv) && ret) {
31643d54 5220 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5221 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5222 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5223 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5224 rc6vids &= 0xffff00;
5225 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5226 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5227 if (ret)
5228 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5229 }
5230
59bad947 5231 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5232}
5233
dc97997a 5234static void __gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5235{
5236 int min_freq = 15;
3ebecd07
CW		 5237 unsigned int gpu_freq;
5238 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5239 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5240 int scaling_factor = 180;
eda79642 5241 struct cpufreq_policy *policy;
2b4e57bd 5242
4fc688ce 5243 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5244
eda79642
BW		 5245 policy = cpufreq_cpu_get(0);
5246 if (policy) {
5247 max_ia_freq = policy->cpuinfo.max_freq;
5248 cpufreq_cpu_put(policy);
5249 } else {
5250 /*
5251 * Default to measured freq if none found, PCU will ensure we
5252 * don't go over
5253 */
2b4e57bd 5254 max_ia_freq = tsc_khz;
eda79642 5255 }
2b4e57bd
ED		 5256
5257 /* Convert from kHz to MHz */
5258 max_ia_freq /= 1000;
5259
153b4b95 5260 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5261 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5262 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5263
dc97997a 5264 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5265 /* Convert GT frequency to 50 HZ units */
5266 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5267 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5268 } else {
5269 min_gpu_freq = dev_priv->rps.min_freq;
5270 max_gpu_freq = dev_priv->rps.max_freq;
5271 }
5272
2b4e57bd
ED		 5273 /*
5274 * For each potential GPU frequency, load a ring frequency we'd like
5275 * to use for memory access. We do this by specifying the IA frequency
5276 * the PCU should use as a reference to determine the ring frequency.
5277 */
4c8c7743
AG		 5278 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5279 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5280 unsigned int ia_freq = 0, ring_freq = 0;
5281
dc97997a 5282 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5283 /*
5284 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5285 * No floor required for ring frequency on SKL.
5286 */
5287 ring_freq = gpu_freq;
dc97997a 5288 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5289 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5290 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5291 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5292 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5293 ring_freq = max(min_ring_freq, ring_freq);
5294 /* leave ia_freq as the default, chosen by cpufreq */
5295 } else {
5296 /* On older processors, there is no separate ring
5297 * clock domain, so in order to boost the bandwidth
5298 * of the ring, we need to upclock the CPU (ia_freq).
5299 *
5300 * For GPU frequencies less than 750MHz,
5301 * just use the lowest ring freq.
5302 */
5303 if (gpu_freq < min_freq)
5304 ia_freq = 800;
5305 else
5306 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5307 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5308 }
2b4e57bd 5309
42c0526c
BW		 5310 sandybridge_pcode_write(dev_priv,
5311 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5312 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5313 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5314 gpu_freq);
2b4e57bd 5315 }
2b4e57bd
ED		 5316}
5317
dc97997a 5318void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
c2bc2fc5 5319{
dc97997a 5320 if (!HAS_CORE_RING_FREQ(dev_priv))
c2bc2fc5
ID		 5321 return;
5322
5323 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a 5324 __gen6_update_ring_freq(dev_priv);
c2bc2fc5
ID		 5325 mutex_unlock(&dev_priv->rps.hw_lock);
5326}
5327
03af2045 5328static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5329{
5330 u32 val, rp0;
5331
5b5929cb 5332 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5333
dc97997a 5334 switch (INTEL_INFO(dev_priv)->eu_total) {
5b5929cb
JN		 5335 case 8:
5336 /* (2 * 4) config */
5337 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5338 break;
5339 case 12:
5340 /* (2 * 6) config */
5341 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5342 break;
5343 case 16:
5344 /* (2 * 8) config */
5345 default:
5346 /* Setting (2 * 8) Min RP0 for any other combination */
5347 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5348 break;
095acd5f 5349 }
5b5929cb
JN		 5350
5351 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5352
2b6b3a09
D		 5353 return rp0;
5354}
5355
5356static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5357{
5358 u32 val, rpe;
5359
5360 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5361 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5362
5363 return rpe;
5364}
5365
7707df4a
D		 5366static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5367{
5368 u32 val, rp1;
5369
5b5929cb
JN		 5370 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5371 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5372
7707df4a
D		 5373 return rp1;
5374}
5375
f8f2b001
D		 5376static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5377{
5378 u32 val, rp1;
5379
5380 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5381
5382 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5383
5384 return rp1;
5385}
5386
03af2045 5387static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5388{
5389 u32 val, rp0;
5390
64936258 5391 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5392
5393 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5394 /* Clamp to max */
5395 rp0 = min_t(u32, rp0, 0xea);
5396
5397 return rp0;
5398}
5399
5400static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5401{
5402 u32 val, rpe;
5403
64936258 5404 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5405 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5406 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5407 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5408
5409 return rpe;
5410}
5411
03af2045 5412static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5413{
36146035
ID		 5414 u32 val;
5415
5416 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5417 /*
5418 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5419 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5420 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5421 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5422 * to make sure it matches what Punit accepts.
5423 */
5424 return max_t(u32, val, 0xc0);
0a073b84
JB		 5425}
5426
ae48434c
ID		 5427/* Check that the pctx buffer wasn't move under us. */
5428static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5429{
5430 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5431
5432 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5433 dev_priv->vlv_pctx->stolen->start);
5434}
5435
38807746
D		 5436
5437/* Check that the pcbr address is not empty. */
5438static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5439{
5440 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5441
5442 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5443}
5444
dc97997a 5445static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5446{
62106b4f 5447 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5448 unsigned long pctx_paddr, paddr;
38807746
D		 5449 u32 pcbr;
5450 int pctx_size = 32*1024;
5451
38807746
D		 5452 pcbr = I915_READ(VLV_PCBR);
5453 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5454 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5455 paddr = (dev_priv->mm.stolen_base +
62106b4f 5456 (ggtt->stolen_size - pctx_size));
38807746
D		 5457
5458 pctx_paddr = (paddr & (~4095));
5459 I915_WRITE(VLV_PCBR, pctx_paddr);
5460 }
ce611ef8
VS		 5461
5462 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5463}
5464
dc97997a 5465static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5466{
c9cddffc
JB		 5467 struct drm_i915_gem_object *pctx;
5468 unsigned long pctx_paddr;
5469 u32 pcbr;
5470 int pctx_size = 24*1024;
5471
dc97997a 5472 mutex_lock(&dev_priv->dev->struct_mutex);
17b0c1f7 5473
c9cddffc
JB		 5474 pcbr = I915_READ(VLV_PCBR);
5475 if (pcbr) {
5476 /* BIOS set it up already, grab the pre-alloc'd space */
5477 int pcbr_offset;
5478
5479 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5480 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5481 pcbr_offset,
190d6cd5 5482 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5483 pctx_size);
5484 goto out;
5485 }
5486
ce611ef8
VS		 5487 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5488
c9cddffc
JB		 5489 /*
5490 * From the Gunit register HAS:
5491 * The Gfx driver is expected to program this register and ensure
5492 * proper allocation within Gfx stolen memory. For example, this
5493 * register should be programmed such than the PCBR range does not
5494 * overlap with other ranges, such as the frame buffer, protected
5495 * memory, or any other relevant ranges.
5496 */
dc97997a 5497 pctx = i915_gem_object_create_stolen(dev_priv->dev, pctx_size);
c9cddffc
JB		 5498 if (!pctx) {
5499 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5500 goto out;
c9cddffc
JB		 5501 }
5502
5503 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5504 I915_WRITE(VLV_PCBR, pctx_paddr);
5505
5506out:
ce611ef8 5507 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5508 dev_priv->vlv_pctx = pctx;
dc97997a 5509 mutex_unlock(&dev_priv->dev->struct_mutex);
c9cddffc
JB		 5510}
5511
dc97997a 5512static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5513{
ae48434c
ID		 5514 if (WARN_ON(!dev_priv->vlv_pctx))
5515 return;
5516
ee504898 5517 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5518 dev_priv->vlv_pctx = NULL;
5519}
5520
c30fec65
VS		 5521static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5522{
5523 dev_priv->rps.gpll_ref_freq =
5524 vlv_get_cck_clock(dev_priv, "GPLL ref",
5525 CCK_GPLL_CLOCK_CONTROL,
5526 dev_priv->czclk_freq);
5527
5528 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5529 dev_priv->rps.gpll_ref_freq);
5530}
5531
dc97997a 5532static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5533{
2bb25c17 5534 u32 val;
4e80519e 5535
dc97997a 5536 valleyview_setup_pctx(dev_priv);
4e80519e 5537
c30fec65
VS		 5538 vlv_init_gpll_ref_freq(dev_priv);
5539
4e80519e
ID		 5540 mutex_lock(&dev_priv->rps.hw_lock);
5541
2bb25c17
VS		 5542 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5543 switch ((val >> 6) & 3) {
5544 case 0:
5545 case 1:
5546 dev_priv->mem_freq = 800;
5547 break;
5548 case 2:
5549 dev_priv->mem_freq = 1066;
5550 break;
5551 case 3:
5552 dev_priv->mem_freq = 1333;
5553 break;
5554 }
80b83b62 5555 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5556
4e80519e
ID		 5557 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5558 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5559 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5560 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5561 dev_priv->rps.max_freq);
5562
5563 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5564 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5565 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5566 dev_priv->rps.efficient_freq);
5567
f8f2b001
D		 5568 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5569 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5570 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5571 dev_priv->rps.rp1_freq);
5572
4e80519e
ID		 5573 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5574 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5575 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5576 dev_priv->rps.min_freq);
5577
aed242ff
CW		 5578 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5579
4e80519e
ID		 5580 /* Preserve min/max settings in case of re-init */
5581 if (dev_priv->rps.max_freq_softlimit == 0)
5582 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5583
5584 if (dev_priv->rps.min_freq_softlimit == 0)
5585 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5586
5587 mutex_unlock(&dev_priv->rps.hw_lock);
5588}
5589
dc97997a 5590static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5591{
2bb25c17 5592 u32 val;
2b6b3a09 5593
dc97997a 5594 cherryview_setup_pctx(dev_priv);
2b6b3a09 5595
c30fec65
VS		 5596 vlv_init_gpll_ref_freq(dev_priv);
5597
2b6b3a09
D		 5598 mutex_lock(&dev_priv->rps.hw_lock);
5599
a580516d 5600 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5601 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5602 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5603
2bb25c17 5604 switch ((val >> 2) & 0x7) {
2bb25c17 5605 case 3:
2bb25c17
VS		 5606 dev_priv->mem_freq = 2000;
5607 break;
bfa7df01 5608 default:
2bb25c17
VS		 5609 dev_priv->mem_freq = 1600;
5610 break;
5611 }
80b83b62 5612 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5613
2b6b3a09
D		 5614 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5615 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5616 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5617 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5618 dev_priv->rps.max_freq);
5619
5620 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5621 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5622 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5623 dev_priv->rps.efficient_freq);
5624
7707df4a
D		 5625 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5626 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5627 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5628 dev_priv->rps.rp1_freq);
5629
5b7c91b7
D		 5630 /* PUnit validated range is only [RPe, RP0] */
5631 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5632 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5633 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5634 dev_priv->rps.min_freq);
5635
1c14762d
VS		 5636 WARN_ONCE((dev_priv->rps.max_freq |
5637 dev_priv->rps.efficient_freq |
5638 dev_priv->rps.rp1_freq |
5639 dev_priv->rps.min_freq) & 1,
5640 "Odd GPU freq values\n");
5641
aed242ff
CW		 5642 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5643
2b6b3a09
D		 5644 /* Preserve min/max settings in case of re-init */
5645 if (dev_priv->rps.max_freq_softlimit == 0)
5646 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5647
5648 if (dev_priv->rps.min_freq_softlimit == 0)
5649 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5650
5651 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5652}
5653
dc97997a 5654static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5655{
dc97997a 5656 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5657}
5658
dc97997a 5659static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5660{
e2f80391 5661 struct intel_engine_cs *engine;
2b6b3a09 5662 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5663
5664 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5665
297b32ec
VS		 5666 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5667 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5668 if (gtfifodbg) {
5669 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5670 gtfifodbg);
5671 I915_WRITE(GTFIFODBG, gtfifodbg);
5672 }
5673
5674 cherryview_check_pctx(dev_priv);
5675
5676 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5677 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5678 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5679
160614a2
VS		 5680 /* Disable RC states. */
5681 I915_WRITE(GEN6_RC_CONTROL, 0);
5682
38807746
D		 5683 /* 2a: Program RC6 thresholds.*/
5684 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5685 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5686 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5687
b4ac5afc 5688 for_each_engine(engine, dev_priv)
e2f80391 5689 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5690 I915_WRITE(GEN6_RC_SLEEP, 0);
5691
f4f71c7d
D		 5692 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5693 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5694
5695 /* allows RC6 residency counter to work */
5696 I915_WRITE(VLV_COUNTER_CONTROL,
5697 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5698 VLV_MEDIA_RC6_COUNT_EN |
5699 VLV_RENDER_RC6_COUNT_EN));
5700
5701 /* For now we assume BIOS is allocating and populating the PCBR */
5702 pcbr = I915_READ(VLV_PCBR);
5703
38807746 5704 /* 3: Enable RC6 */
dc97997a
CW		 5705 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5706 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5707 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5708
5709 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5710
2b6b3a09 5711 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5712 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5713 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5714 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5715 I915_WRITE(GEN6_RP_UP_EI, 66000);
5716 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5717
5718 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5719
5720 /* 5: Enable RPS */
5721 I915_WRITE(GEN6_RP_CONTROL,
5722 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5723 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5724 GEN6_RP_ENABLE |
5725 GEN6_RP_UP_BUSY_AVG |
5726 GEN6_RP_DOWN_IDLE_AVG);
5727
3ef62342
D		 5728 /* Setting Fixed Bias */
5729 val = VLV_OVERRIDE_EN |
5730 VLV_SOC_TDP_EN |
5731 CHV_BIAS_CPU_50_SOC_50;
5732 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5733
2b6b3a09
D		 5734 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5735
8d40c3ae
VS		 5736 /* RPS code assumes GPLL is used */
5737 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5738
742f491d 5739 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5740 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5741
5742 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5743 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5744 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5745 dev_priv->rps.cur_freq);
5746
5747 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5748 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5749 dev_priv->rps.idle_freq);
2b6b3a09 5750
dc97997a 5751 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
2b6b3a09 5752
59bad947 5753 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5754}
5755
dc97997a 5756static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 5757{
e2f80391 5758 struct intel_engine_cs *engine;
2a5913a8 5759 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5760
5761 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5762
ae48434c
ID		 5763 valleyview_check_pctx(dev_priv);
5764
297b32ec
VS		 5765 gtfifodbg = I915_READ(GTFIFODBG);
5766 if (gtfifodbg) {
f7d85c1e
JB		 5767 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5768 gtfifodbg);
0a073b84
JB		 5769 I915_WRITE(GTFIFODBG, gtfifodbg);
5770 }
5771
c8d9a590 5772 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5773 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5774
160614a2
VS		 5775 /* Disable RC states. */
5776 I915_WRITE(GEN6_RC_CONTROL, 0);
5777
cad725fe 5778 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5779 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5780 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5781 I915_WRITE(GEN6_RP_UP_EI, 66000);
5782 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5783
5784 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5785
5786 I915_WRITE(GEN6_RP_CONTROL,
5787 GEN6_RP_MEDIA_TURBO |
5788 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5789 GEN6_RP_MEDIA_IS_GFX |
5790 GEN6_RP_ENABLE |
5791 GEN6_RP_UP_BUSY_AVG |
5792 GEN6_RP_DOWN_IDLE_CONT);
5793
5794 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5795 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5796 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5797
b4ac5afc 5798 for_each_engine(engine, dev_priv)
e2f80391 5799 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5800
2f0aa304 5801 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5802
5803 /* allows RC6 residency counter to work */
49798eb2 5804 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5805 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5806 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5807 VLV_MEDIA_RC6_COUNT_EN |
5808 VLV_RENDER_RC6_COUNT_EN));
31685c25 5809
dc97997a 5810 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 5811 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 5812
dc97997a 5813 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 5814
a2b23fe0 5815 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5816
3ef62342
D		 5817 /* Setting Fixed Bias */
5818 val = VLV_OVERRIDE_EN |
5819 VLV_SOC_TDP_EN |
5820 VLV_BIAS_CPU_125_SOC_875;
5821 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5822
64936258 5823 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5824
8d40c3ae
VS		 5825 /* RPS code assumes GPLL is used */
5826 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5827
742f491d 5828 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5829 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5830
b39fb297 5831 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5832 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5833 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5834 dev_priv->rps.cur_freq);
0a073b84 5835
73008b98 5836 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5837 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5838 dev_priv->rps.idle_freq);
0a073b84 5839
dc97997a 5840 valleyview_set_rps(dev_priv, dev_priv->rps.idle_freq);
0a073b84 5841
59bad947 5842 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5843}
5844
dde18883
ED		 5845static unsigned long intel_pxfreq(u32 vidfreq)
5846{
5847 unsigned long freq;
5848 int div = (vidfreq & 0x3f0000) >> 16;
5849 int post = (vidfreq & 0x3000) >> 12;
5850 int pre = (vidfreq & 0x7);
5851
5852 if (!pre)
5853 return 0;
5854
5855 freq = ((div * 133333) / ((1<<post) * pre));
5856
5857 return freq;
5858}
5859
eb48eb00
DV		 5860static const struct cparams {
5861 u16 i;
5862 u16 t;
5863 u16 m;
5864 u16 c;
5865} cparams[] = {
5866 { 1, 1333, 301, 28664 },
5867 { 1, 1066, 294, 24460 },
5868 { 1, 800, 294, 25192 },
5869 { 0, 1333, 276, 27605 },
5870 { 0, 1066, 276, 27605 },
5871 { 0, 800, 231, 23784 },
5872};
5873
f531dcb2 5874static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5875{
5876 u64 total_count, diff, ret;
5877 u32 count1, count2, count3, m = 0, c = 0;
5878 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5879 int i;
5880
02d71956
DV		 5881 assert_spin_locked(&mchdev_lock);
5882
20e4d407 5883 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5884
5885 /* Prevent division-by-zero if we are asking too fast.
5886 * Also, we don't get interesting results if we are polling
5887 * faster than once in 10ms, so just return the saved value
5888 * in such cases.
5889 */
5890 if (diff1 <= 10)
20e4d407 5891 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5892
5893 count1 = I915_READ(DMIEC);
5894 count2 = I915_READ(DDREC);
5895 count3 = I915_READ(CSIEC);
5896
5897 total_count = count1 + count2 + count3;
5898
5899 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5900 if (total_count < dev_priv->ips.last_count1) {
5901 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5902 diff += total_count;
5903 } else {
20e4d407 5904 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5905 }
5906
5907 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5908 if (cparams[i].i == dev_priv->ips.c_m &&
5909 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5910 m = cparams[i].m;
5911 c = cparams[i].c;
5912 break;
5913 }
5914 }
5915
5916 diff = div_u64(diff, diff1);
5917 ret = ((m * diff) + c);
5918 ret = div_u64(ret, 10);
5919
20e4d407
DV		 5920 dev_priv->ips.last_count1 = total_count;
5921 dev_priv->ips.last_time1 = now;
eb48eb00 5922
20e4d407 5923 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5924
5925 return ret;
5926}
5927
f531dcb2
CW		 5928unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5929{
5930 unsigned long val;
5931
dc97997a 5932 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 5933 return 0;
5934
5935 spin_lock_irq(&mchdev_lock);
5936
5937 val = __i915_chipset_val(dev_priv);
5938
5939 spin_unlock_irq(&mchdev_lock);
5940
5941 return val;
5942}
5943
eb48eb00
DV		 5944unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5945{
5946 unsigned long m, x, b;
5947 u32 tsfs;
5948
5949 tsfs = I915_READ(TSFS);
5950
5951 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5952 x = I915_READ8(TR1);
5953
5954 b = tsfs & TSFS_INTR_MASK;
5955
5956 return ((m * x) / 127) - b;
5957}
5958
d972d6ee
MK		 5959static int _pxvid_to_vd(u8 pxvid)
5960{
5961 if (pxvid == 0)
5962 return 0;
5963
5964 if (pxvid >= 8 && pxvid < 31)
5965 pxvid = 31;
5966
5967 return (pxvid + 2) * 125;
5968}
5969
5970static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5971{
d972d6ee
MK		 5972 const int vd = _pxvid_to_vd(pxvid);
5973 const int vm = vd - 1125;
5974
dc97997a 5975 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 5976 return vm > 0 ? vm : 0;
5977
5978 return vd;
eb48eb00
DV		 5979}
5980
02d71956 5981static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5982{
5ed0bdf2 5983 u64 now, diff, diffms;
eb48eb00
DV		 5984 u32 count;
5985
02d71956 5986 assert_spin_locked(&mchdev_lock);
eb48eb00 5987
5ed0bdf2
TG		 5988 now = ktime_get_raw_ns();
5989 diffms = now - dev_priv->ips.last_time2;
5990 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5991
5992 /* Don't divide by 0 */
eb48eb00
DV		 5993 if (!diffms)
5994 return;
5995
5996 count = I915_READ(GFXEC);
5997
20e4d407
DV		 5998 if (count < dev_priv->ips.last_count2) {
5999 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6000 diff += count;
6001 } else {
20e4d407 6002 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6003 }
6004
20e4d407
DV		 6005 dev_priv->ips.last_count2 = count;
6006 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6007
6008 /* More magic constants... */
6009 diff = diff * 1181;
6010 diff = div_u64(diff, diffms * 10);
20e4d407 6011 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6012}
6013
02d71956
DV		 6014void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6015{
dc97997a 6016 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6017 return;
6018
9270388e 6019 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6020
6021 __i915_update_gfx_val(dev_priv);
6022
9270388e 6023 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6024}
6025
f531dcb2 6026static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6027{
6028 unsigned long t, corr, state1, corr2, state2;
6029 u32 pxvid, ext_v;
6030
02d71956
DV		 6031 assert_spin_locked(&mchdev_lock);
6032
616847e7 6033 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6034 pxvid = (pxvid >> 24) & 0x7f;
6035 ext_v = pvid_to_extvid(dev_priv, pxvid);
6036
6037 state1 = ext_v;
6038
6039 t = i915_mch_val(dev_priv);
6040
6041 /* Revel in the empirically derived constants */
6042
6043 /* Correction factor in 1/100000 units */
6044 if (t > 80)
6045 corr = ((t * 2349) + 135940);
6046 else if (t >= 50)
6047 corr = ((t * 964) + 29317);
6048 else /* < 50 */
6049 corr = ((t * 301) + 1004);
6050
6051 corr = corr * ((150142 * state1) / 10000 - 78642);
6052 corr /= 100000;
20e4d407 6053 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6054
6055 state2 = (corr2 * state1) / 10000;
6056 state2 /= 100; /* convert to mW */
6057
02d71956 6058 __i915_update_gfx_val(dev_priv);
eb48eb00 6059
20e4d407 6060 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6061}
6062
f531dcb2
CW		 6063unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6064{
6065 unsigned long val;
6066
dc97997a 6067 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6068 return 0;
6069
6070 spin_lock_irq(&mchdev_lock);
6071
6072 val = __i915_gfx_val(dev_priv);
6073
6074 spin_unlock_irq(&mchdev_lock);
6075
6076 return val;
6077}
6078
eb48eb00
DV		 6079/**
6080 * i915_read_mch_val - return value for IPS use
6081 *
6082 * Calculate and return a value for the IPS driver to use when deciding whether
6083 * we have thermal and power headroom to increase CPU or GPU power budget.
6084 */
6085unsigned long i915_read_mch_val(void)
6086{
6087 struct drm_i915_private *dev_priv;
6088 unsigned long chipset_val, graphics_val, ret = 0;
6089
9270388e 6090 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6091 if (!i915_mch_dev)
6092 goto out_unlock;
6093 dev_priv = i915_mch_dev;
6094
f531dcb2
CW		 6095 chipset_val = __i915_chipset_val(dev_priv);
6096 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6097
6098 ret = chipset_val + graphics_val;
6099
6100out_unlock:
9270388e 6101 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6102
6103 return ret;
6104}
6105EXPORT_SYMBOL_GPL(i915_read_mch_val);
6106
6107/**
6108 * i915_gpu_raise - raise GPU frequency limit
6109 *
6110 * Raise the limit; IPS indicates we have thermal headroom.
6111 */
6112bool i915_gpu_raise(void)
6113{
6114 struct drm_i915_private *dev_priv;
6115 bool ret = true;
6116
9270388e 6117 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6118 if (!i915_mch_dev) {
6119 ret = false;
6120 goto out_unlock;
6121 }
6122 dev_priv = i915_mch_dev;
6123
20e4d407
DV		 6124 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6125 dev_priv->ips.max_delay--;
eb48eb00
DV		 6126
6127out_unlock:
9270388e 6128 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6129
6130 return ret;
6131}
6132EXPORT_SYMBOL_GPL(i915_gpu_raise);
6133
6134/**
6135 * i915_gpu_lower - lower GPU frequency limit
6136 *
6137 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6138 * frequency maximum.
6139 */
6140bool i915_gpu_lower(void)
6141{
6142 struct drm_i915_private *dev_priv;
6143 bool ret = true;
6144
9270388e 6145 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6146 if (!i915_mch_dev) {
6147 ret = false;
6148 goto out_unlock;
6149 }
6150 dev_priv = i915_mch_dev;
6151
20e4d407
DV		 6152 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6153 dev_priv->ips.max_delay++;
eb48eb00
DV		 6154
6155out_unlock:
9270388e 6156 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6157
6158 return ret;
6159}
6160EXPORT_SYMBOL_GPL(i915_gpu_lower);
6161
6162/**
6163 * i915_gpu_busy - indicate GPU business to IPS
6164 *
6165 * Tell the IPS driver whether or not the GPU is busy.
6166 */
6167bool i915_gpu_busy(void)
6168{
6169 struct drm_i915_private *dev_priv;
e2f80391 6170 struct intel_engine_cs *engine;
eb48eb00
DV		 6171 bool ret = false;
6172
9270388e 6173 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6174 if (!i915_mch_dev)
6175 goto out_unlock;
6176 dev_priv = i915_mch_dev;
6177
b4ac5afc 6178 for_each_engine(engine, dev_priv)
e2f80391 6179 ret |= !list_empty(&engine->request_list);
eb48eb00
DV		 6180
6181out_unlock:
9270388e 6182 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6183
6184 return ret;
6185}
6186EXPORT_SYMBOL_GPL(i915_gpu_busy);
6187
6188/**
6189 * i915_gpu_turbo_disable - disable graphics turbo
6190 *
6191 * Disable graphics turbo by resetting the max frequency and setting the
6192 * current frequency to the default.
6193 */
6194bool i915_gpu_turbo_disable(void)
6195{
6196 struct drm_i915_private *dev_priv;
6197 bool ret = true;
6198
9270388e 6199 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6200 if (!i915_mch_dev) {
6201 ret = false;
6202 goto out_unlock;
6203 }
6204 dev_priv = i915_mch_dev;
6205
20e4d407 6206 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6207
91d14251 6208 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6209 ret = false;
6210
6211out_unlock:
9270388e 6212 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6213
6214 return ret;
6215}
6216EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6217
6218/**
6219 * Tells the intel_ips driver that the i915 driver is now loaded, if
6220 * IPS got loaded first.
6221 *
6222 * This awkward dance is so that neither module has to depend on the
6223 * other in order for IPS to do the appropriate communication of
6224 * GPU turbo limits to i915.
6225 */
6226static void
6227ips_ping_for_i915_load(void)
6228{
6229 void (*link)(void);
6230
6231 link = symbol_get(ips_link_to_i915_driver);
6232 if (link) {
6233 link();
6234 symbol_put(ips_link_to_i915_driver);
6235 }
6236}
6237
6238void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6239{
02d71956
DV		 6240 /* We only register the i915 ips part with intel-ips once everything is
6241 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6242 spin_lock_irq(&mchdev_lock);
eb48eb00 6243 i915_mch_dev = dev_priv;
9270388e 6244 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6245
6246 ips_ping_for_i915_load();
6247}
6248
6249void intel_gpu_ips_teardown(void)
6250{
9270388e 6251 spin_lock_irq(&mchdev_lock);
eb48eb00 6252 i915_mch_dev = NULL;
9270388e 6253 spin_unlock_irq(&mchdev_lock);
eb48eb00 6254}
76c3552f 6255
dc97997a 6256static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6257{
dde18883
ED		 6258 u32 lcfuse;
6259 u8 pxw[16];
6260 int i;
6261
6262 /* Disable to program */
6263 I915_WRITE(ECR, 0);
6264 POSTING_READ(ECR);
6265
6266 /* Program energy weights for various events */
6267 I915_WRITE(SDEW, 0x15040d00);
6268 I915_WRITE(CSIEW0, 0x007f0000);
6269 I915_WRITE(CSIEW1, 0x1e220004);
6270 I915_WRITE(CSIEW2, 0x04000004);
6271
6272 for (i = 0; i < 5; i++)
616847e7 6273 I915_WRITE(PEW(i), 0);
dde18883 6274 for (i = 0; i < 3; i++)
616847e7 6275 I915_WRITE(DEW(i), 0);
dde18883
ED		 6276
6277 /* Program P-state weights to account for frequency power adjustment */
6278 for (i = 0; i < 16; i++) {
616847e7 6279 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6280 unsigned long freq = intel_pxfreq(pxvidfreq);
6281 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6282 PXVFREQ_PX_SHIFT;
6283 unsigned long val;
6284
6285 val = vid * vid;
6286 val *= (freq / 1000);
6287 val *= 255;
6288 val /= (127*127*900);
6289 if (val > 0xff)
6290 DRM_ERROR("bad pxval: %ld\n", val);
6291 pxw[i] = val;
6292 }
6293 /* Render standby states get 0 weight */
6294 pxw[14] = 0;
6295 pxw[15] = 0;
6296
6297 for (i = 0; i < 4; i++) {
6298 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6299 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6300 I915_WRITE(PXW(i), val);
dde18883
ED		 6301 }
6302
6303 /* Adjust magic regs to magic values (more experimental results) */
6304 I915_WRITE(OGW0, 0);
6305 I915_WRITE(OGW1, 0);
6306 I915_WRITE(EG0, 0x00007f00);
6307 I915_WRITE(EG1, 0x0000000e);
6308 I915_WRITE(EG2, 0x000e0000);
6309 I915_WRITE(EG3, 0x68000300);
6310 I915_WRITE(EG4, 0x42000000);
6311 I915_WRITE(EG5, 0x00140031);
6312 I915_WRITE(EG6, 0);
6313 I915_WRITE(EG7, 0);
6314
6315 for (i = 0; i < 8; i++)
616847e7 6316 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6317
6318 /* Enable PMON + select events */
6319 I915_WRITE(ECR, 0x80000019);
6320
6321 lcfuse = I915_READ(LCFUSE02);
6322
20e4d407 6323 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6324}
6325
dc97997a 6326void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6327{
b268c699
ID		 6328 /*
6329 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6330 * requirement.
6331 */
6332 if (!i915.enable_rc6) {
6333 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6334 intel_runtime_pm_get(dev_priv);
6335 }
e6069ca8 6336
dc97997a
CW		 6337 if (IS_CHERRYVIEW(dev_priv))
6338 cherryview_init_gt_powersave(dev_priv);
6339 else if (IS_VALLEYVIEW(dev_priv))
6340 valleyview_init_gt_powersave(dev_priv);
ae48434c
ID		 6341}
6342
dc97997a 6343void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6344{
dc97997a 6345 if (IS_CHERRYVIEW(dev_priv))
38807746 6346 return;
dc97997a
CW		 6347 else if (IS_VALLEYVIEW(dev_priv))
6348 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6349
6350 if (!i915.enable_rc6)
6351 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6352}
6353
91d14251 6354static void gen6_suspend_rps(struct drm_i915_private *dev_priv)
dbea3cea 6355{
dbea3cea
ID		 6356 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6357
91d14251 6358 gen6_disable_rps_interrupts(dev_priv);
dbea3cea
ID		 6359}
6360
156c7ca0
JB		 6361/**
6362 * intel_suspend_gt_powersave - suspend PM work and helper threads
dc97997a 6363 * @dev_priv: i915 device
156c7ca0
JB		 6364 *
6365 * We don't want to disable RC6 or other features here, we just want
6366 * to make sure any work we've queued has finished and won't bother
6367 * us while we're suspended.
6368 */
dc97997a 6369void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
156c7ca0 6370{
91d14251 6371 if (INTEL_GEN(dev_priv) < 6)
d4d70aa5
ID		 6372 return;
6373
91d14251 6374 gen6_suspend_rps(dev_priv);
b47adc17
D		 6375
6376 /* Force GPU to min freq during suspend */
6377 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6378}
6379
dc97997a 6380void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6381{
dc97997a 6382 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6383 ironlake_disable_drps(dev_priv);
dc97997a
CW		 6384 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6385 intel_suspend_gt_powersave(dev_priv);
e494837a 6386
4fc688ce 6387 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6388 if (INTEL_INFO(dev_priv)->gen >= 9) {
6389 gen9_disable_rc6(dev_priv);
6390 gen9_disable_rps(dev_priv);
6391 } else if (IS_CHERRYVIEW(dev_priv))
6392 cherryview_disable_rps(dev_priv);
6393 else if (IS_VALLEYVIEW(dev_priv))
6394 valleyview_disable_rps(dev_priv);
d20d4f0c 6395 else
dc97997a 6396 gen6_disable_rps(dev_priv);
e534770a 6397
c0951f0c 6398 dev_priv->rps.enabled = false;
4fc688ce 6399 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6400 }
8090c6b9
DV		 6401}
6402
1a01ab3b
JB		 6403static void intel_gen6_powersave_work(struct work_struct *work)
6404{
6405 struct drm_i915_private *dev_priv =
6406 container_of(work, struct drm_i915_private,
6407 rps.delayed_resume_work.work);
1a01ab3b 6408
4fc688ce 6409 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6410
dc97997a
CW		 6411 gen6_reset_rps_interrupts(dev_priv);
6412
6413 if (IS_CHERRYVIEW(dev_priv)) {
6414 cherryview_enable_rps(dev_priv);
6415 } else if (IS_VALLEYVIEW(dev_priv)) {
6416 valleyview_enable_rps(dev_priv);
6417 } else if (INTEL_INFO(dev_priv)->gen >= 9) {
6418 gen9_enable_rc6(dev_priv);
6419 gen9_enable_rps(dev_priv);
6420 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6421 __gen6_update_ring_freq(dev_priv);
6422 } else if (IS_BROADWELL(dev_priv)) {
6423 gen8_enable_rps(dev_priv);
6424 __gen6_update_ring_freq(dev_priv);
0a073b84 6425 } else {
dc97997a
CW		 6426 gen6_enable_rps(dev_priv);
6427 __gen6_update_ring_freq(dev_priv);
0a073b84 6428 }
aed242ff
CW		 6429
6430 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6431 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6432
6433 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6434 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6435
c0951f0c 6436 dev_priv->rps.enabled = true;
3cc134e3 6437
91d14251 6438 gen6_enable_rps_interrupts(dev_priv);
3cc134e3 6439
4fc688ce 6440 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6441
6442 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6443}
6444
dc97997a 6445void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6446{
f61018b1 6447 /* Powersaving is controlled by the host when inside a VM */
c033666a 6448 if (intel_vgpu_active(dev_priv))
f61018b1
YZ		 6449 return;
6450
dc97997a 6451 if (IS_IRONLAKE_M(dev_priv)) {
91d14251 6452 ironlake_enable_drps(dev_priv);
dc97997a
CW		 6453 mutex_lock(&dev_priv->dev->struct_mutex);
6454 intel_init_emon(dev_priv);
6455 mutex_unlock(&dev_priv->dev->struct_mutex);
6456 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
1a01ab3b
JB		 6457 /*
6458 * PCU communication is slow and this doesn't need to be
6459 * done at any specific time, so do this out of our fast path
6460 * to make resume and init faster.
c6df39b5
ID		 6461 *
6462 * We depend on the HW RC6 power context save/restore
6463 * mechanism when entering D3 through runtime PM suspend. So
6464 * disable RPM until RPS/RC6 is properly setup. We can only
6465 * get here via the driver load/system resume/runtime resume
6466 * paths, so the _noresume version is enough (and in case of
6467 * runtime resume it's necessary).
1a01ab3b 6468 */
c6df39b5
ID		 6469 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6470 round_jiffies_up_relative(HZ)))
6471 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6472 }
6473}
6474
dc97997a 6475void intel_reset_gt_powersave(struct drm_i915_private *dev_priv)
c6df39b5 6476{
dc97997a 6477 if (INTEL_INFO(dev_priv)->gen < 6)
dbea3cea
ID		 6478 return;
6479
91d14251 6480 gen6_suspend_rps(dev_priv);
c6df39b5 6481 dev_priv->rps.enabled = false;
c6df39b5
ID		 6482}
6483
3107bd48
DV		 6484static void ibx_init_clock_gating(struct drm_device *dev)
6485{
6486 struct drm_i915_private *dev_priv = dev->dev_private;
6487
6488 /*
6489 * On Ibex Peak and Cougar Point, we need to disable clock
6490 * gating for the panel power sequencer or it will fail to
6491 * start up when no ports are active.
6492 */
6493 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6494}
6495
0e088b8f
VS		 6496static void g4x_disable_trickle_feed(struct drm_device *dev)
6497{
6498 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6499 enum pipe pipe;
0e088b8f 6500
055e393f 6501 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6502 I915_WRITE(DSPCNTR(pipe),
6503 I915_READ(DSPCNTR(pipe)) |
6504 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6505
6506 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6507 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6508 }
6509}
6510
017636cc
VS		 6511static void ilk_init_lp_watermarks(struct drm_device *dev)
6512{
6513 struct drm_i915_private *dev_priv = dev->dev_private;
6514
6515 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6516 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6517 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6518
6519 /*
6520 * Don't touch WM1S_LP_EN here.
6521 * Doing so could cause underruns.
6522 */
6523}
6524
1fa61106 6525static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6526{
6527 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6528 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6529
f1e8fa56
DL		 6530 /*
6531 * Required for FBC
6532 * WaFbcDisableDpfcClockGating:ilk
6533 */
4d47e4f5
DL		 6534 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6535 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6536 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6537
6538 I915_WRITE(PCH_3DCGDIS0,
6539 MARIUNIT_CLOCK_GATE_DISABLE |
6540 SVSMUNIT_CLOCK_GATE_DISABLE);
6541 I915_WRITE(PCH_3DCGDIS1,
6542 VFMUNIT_CLOCK_GATE_DISABLE);
6543
6f1d69b0
ED		 6544 /*
6545 * According to the spec the following bits should be set in
6546 * order to enable memory self-refresh
6547 * The bit 22/21 of 0x42004
6548 * The bit 5 of 0x42020
6549 * The bit 15 of 0x45000
6550 */
6551 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6552 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6553 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6554 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6555 I915_WRITE(DISP_ARB_CTL,
6556 (I915_READ(DISP_ARB_CTL) |
6557 DISP_FBC_WM_DIS));
017636cc
VS		 6558
6559 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6560
6561 /*
6562 * Based on the document from hardware guys the following bits
6563 * should be set unconditionally in order to enable FBC.
6564 * The bit 22 of 0x42000
6565 * The bit 22 of 0x42004
6566 * The bit 7,8,9 of 0x42020.
6567 */
6568 if (IS_IRONLAKE_M(dev)) {
4bb35334 6569 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6570 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6571 I915_READ(ILK_DISPLAY_CHICKEN1) |
6572 ILK_FBCQ_DIS);
6573 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6574 I915_READ(ILK_DISPLAY_CHICKEN2) |
6575 ILK_DPARB_GATE);
6f1d69b0
ED		 6576 }
6577
4d47e4f5
DL		 6578 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6579
6f1d69b0
ED		 6580 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6581 I915_READ(ILK_DISPLAY_CHICKEN2) |
6582 ILK_ELPIN_409_SELECT);
6583 I915_WRITE(_3D_CHICKEN2,
6584 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6585 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6586
ecdb4eb7 6587 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6588 I915_WRITE(CACHE_MODE_0,
6589 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6590
4e04632e
AG		 6591 /* WaDisable_RenderCache_OperationalFlush:ilk */
6592 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6593
0e088b8f 6594 g4x_disable_trickle_feed(dev);
bdad2b2f 6595
3107bd48
DV		 6596 ibx_init_clock_gating(dev);
6597}
6598
6599static void cpt_init_clock_gating(struct drm_device *dev)
6600{
6601 struct drm_i915_private *dev_priv = dev->dev_private;
6602 int pipe;
3f704fa2 6603 uint32_t val;
3107bd48
DV		 6604
6605 /*
6606 * On Ibex Peak and Cougar Point, we need to disable clock
6607 * gating for the panel power sequencer or it will fail to
6608 * start up when no ports are active.
6609 */
cd664078
JB		 6610 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6611 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6612 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6613 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6614 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6615 /* The below fixes the weird display corruption, a few pixels shifted
6616 * downward, on (only) LVDS of some HP laptops with IVY.
6617 */
055e393f 6618 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6619 val = I915_READ(TRANS_CHICKEN2(pipe));
6620 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6621 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6622 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6623 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6624 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6625 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6626 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6627 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6628 }
3107bd48 6629 /* WADP0ClockGatingDisable */
055e393f 6630 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6631 I915_WRITE(TRANS_CHICKEN1(pipe),
6632 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6633 }
6f1d69b0
ED		 6634}
6635
1d7aaa0c
DV		 6636static void gen6_check_mch_setup(struct drm_device *dev)
6637{
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639 uint32_t tmp;
6640
6641 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6642 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6643 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6644 tmp);
1d7aaa0c
DV		 6645}
6646
1fa61106 6647static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6648{
6649 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6650 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6651
231e54f6 6652 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6653
6654 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6655 I915_READ(ILK_DISPLAY_CHICKEN2) |
6656 ILK_ELPIN_409_SELECT);
6657
ecdb4eb7 6658 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6659 I915_WRITE(_3D_CHICKEN,
6660 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6661
4e04632e
AG		 6662 /* WaDisable_RenderCache_OperationalFlush:snb */
6663 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6664
8d85d272
VS		 6665 /*
6666 * BSpec recoomends 8x4 when MSAA is used,
6667 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6668 *
6669 * Note that PS/WM thread counts depend on the WIZ hashing
6670 * disable bit, which we don't touch here, but it's good
6671 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6672 */
6673 I915_WRITE(GEN6_GT_MODE,
98533251 6674 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6675
017636cc 6676 ilk_init_lp_watermarks(dev);
6f1d69b0 6677
6f1d69b0 6678 I915_WRITE(CACHE_MODE_0,
50743298 6679 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6680
6681 I915_WRITE(GEN6_UCGCTL1,
6682 I915_READ(GEN6_UCGCTL1) |
6683 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6684 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6685
6686 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6687 * gating disable must be set. Failure to set it results in
6688 * flickering pixels due to Z write ordering failures after
6689 * some amount of runtime in the Mesa "fire" demo, and Unigine
6690 * Sanctuary and Tropics, and apparently anything else with
6691 * alpha test or pixel discard.
6692 *
6693 * According to the spec, bit 11 (RCCUNIT) must also be set,
6694 * but we didn't debug actual testcases to find it out.
0f846f81 6695 *
ef59318c
VS		 6696 * WaDisableRCCUnitClockGating:snb
6697 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6698 */
6699 I915_WRITE(GEN6_UCGCTL2,
6700 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6701 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6702
5eb146dd 6703 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6704 I915_WRITE(_3D_CHICKEN3,
6705 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6706
e927ecde
VS		 6707 /*
6708 * Bspec says:
6709 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6710 * 3DSTATE_SF number of SF output attributes is more than 16."
6711 */
6712 I915_WRITE(_3D_CHICKEN3,
6713 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6714
6f1d69b0
ED		 6715 /*
6716 * According to the spec the following bits should be
6717 * set in order to enable memory self-refresh and fbc:
6718 * The bit21 and bit22 of 0x42000
6719 * The bit21 and bit22 of 0x42004
6720 * The bit5 and bit7 of 0x42020
6721 * The bit14 of 0x70180
6722 * The bit14 of 0x71180
4bb35334
DL		 6723 *
6724 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6725 */
6726 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6727 I915_READ(ILK_DISPLAY_CHICKEN1) |
6728 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6729 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6730 I915_READ(ILK_DISPLAY_CHICKEN2) |
6731 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6732 I915_WRITE(ILK_DSPCLK_GATE_D,
6733 I915_READ(ILK_DSPCLK_GATE_D) |
6734 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6735 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6736
0e088b8f 6737 g4x_disable_trickle_feed(dev);
f8f2ac9a 6738
3107bd48 6739 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6740
6741 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6742}
6743
6744static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6745{
6746 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6747
3aad9059 6748 /*
46680e0a 6749 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6750 *
6751 * This actually overrides the dispatch
6752 * mode for all thread types.
6753 */
6f1d69b0
ED		 6754 reg &= ~GEN7_FF_SCHED_MASK;
6755 reg |= GEN7_FF_TS_SCHED_HW;
6756 reg |= GEN7_FF_VS_SCHED_HW;
6757 reg |= GEN7_FF_DS_SCHED_HW;
6758
6759 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6760}
6761
17a303ec
PZ		 6762static void lpt_init_clock_gating(struct drm_device *dev)
6763{
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765
6766 /*
6767 * TODO: this bit should only be enabled when really needed, then
6768 * disabled when not needed anymore in order to save power.
6769 */
c2699524 6770 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6771 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6772 I915_READ(SOUTH_DSPCLK_GATE_D) |
6773 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6774
6775 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6776 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6777 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6778 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6779}
6780
7d708ee4
ID		 6781static void lpt_suspend_hw(struct drm_device *dev)
6782{
6783 struct drm_i915_private *dev_priv = dev->dev_private;
6784
c2699524 6785 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6786 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6787
6788 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6789 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6790 }
6791}
6792
450174fe
ID		 6793static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
6794 int general_prio_credits,
6795 int high_prio_credits)
6796{
6797 u32 misccpctl;
6798
6799 /* WaTempDisableDOPClkGating:bdw */
6800 misccpctl = I915_READ(GEN7_MISCCPCTL);
6801 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6802
6803 I915_WRITE(GEN8_L3SQCREG1,
6804 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
6805 L3_HIGH_PRIO_CREDITS(high_prio_credits));
6806
6807 /*
6808 * Wait at least 100 clocks before re-enabling clock gating.
6809 * See the definition of L3SQCREG1 in BSpec.
6810 */
6811 POSTING_READ(GEN8_L3SQCREG1);
6812 udelay(1);
6813 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6814}
6815
47c2bd97 6816static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6817{
6818 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6819 enum pipe pipe;
1020a5c2 6820
7ad0dbab 6821 ilk_init_lp_watermarks(dev);
50ed5fbd 6822
ab57fff1 6823 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6824 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6825
ab57fff1 6826 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6827 I915_WRITE(CHICKEN_PAR1_1,
6828 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6829
ab57fff1 6830 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6831 for_each_pipe(dev_priv, pipe) {
07d27e20 6832 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6833 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6834 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6835 }
63801f21 6836
ab57fff1
BW		 6837 /* WaVSRefCountFullforceMissDisable:bdw */
6838 /* WaDSRefCountFullforceMissDisable:bdw */
6839 I915_WRITE(GEN7_FF_THREAD_MODE,
6840 I915_READ(GEN7_FF_THREAD_MODE) &
6841 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6842
295e8bb7
VS		 6843 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6844 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6845
6846 /* WaDisableSDEUnitClockGating:bdw */
6847 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6848 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6849
450174fe
ID		 6850 /* WaProgramL3SqcReg1Default:bdw */
6851 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 6852
6d50b065
VS		 6853 /*
6854 * WaGttCachingOffByDefault:bdw
6855 * GTT cache may not work with big pages, so if those
6856 * are ever enabled GTT cache may need to be disabled.
6857 */
6858 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6859
89d6b2b8 6860 lpt_init_clock_gating(dev);
1020a5c2
BW		 6861}
6862
cad2a2d7
ED		 6863static void haswell_init_clock_gating(struct drm_device *dev)
6864{
6865 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6866
017636cc 6867 ilk_init_lp_watermarks(dev);
cad2a2d7 6868
f3fc4884
FJ		 6869 /* L3 caching of data atomics doesn't work -- disable it. */
6870 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6871 I915_WRITE(HSW_ROW_CHICKEN3,
6872 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6873
ecdb4eb7 6874 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6875 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6876 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6877 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6878
e36ea7ff
VS		 6879 /* WaVSRefCountFullforceMissDisable:hsw */
6880 I915_WRITE(GEN7_FF_THREAD_MODE,
6881 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6882
4e04632e
AG		 6883 /* WaDisable_RenderCache_OperationalFlush:hsw */
6884 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6885
fe27c606
CW		 6886 /* enable HiZ Raw Stall Optimization */
6887 I915_WRITE(CACHE_MODE_0_GEN7,
6888 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6889
ecdb4eb7 6890 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6891 I915_WRITE(CACHE_MODE_1,
6892 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6893
a12c4967
VS		 6894 /*
6895 * BSpec recommends 8x4 when MSAA is used,
6896 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6897 *
6898 * Note that PS/WM thread counts depend on the WIZ hashing
6899 * disable bit, which we don't touch here, but it's good
6900 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6901 */
6902 I915_WRITE(GEN7_GT_MODE,
98533251 6903 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6904
94411593
KG		 6905 /* WaSampleCChickenBitEnable:hsw */
6906 I915_WRITE(HALF_SLICE_CHICKEN3,
6907 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6908
ecdb4eb7 6909 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6910 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6911
90a88643
PZ		 6912 /* WaRsPkgCStateDisplayPMReq:hsw */
6913 I915_WRITE(CHICKEN_PAR1_1,
6914 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6915
17a303ec 6916 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6917}
6918
1fa61106 6919static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6920{
6921 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6922 uint32_t snpcr;
6f1d69b0 6923
017636cc 6924 ilk_init_lp_watermarks(dev);
6f1d69b0 6925
231e54f6 6926 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6927
ecdb4eb7 6928 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6929 I915_WRITE(_3D_CHICKEN3,
6930 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6931
ecdb4eb7 6932 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6933 I915_WRITE(IVB_CHICKEN3,
6934 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6935 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6936
ecdb4eb7 6937 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6938 if (IS_IVB_GT1(dev))
6939 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6940 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6941
4e04632e
AG		 6942 /* WaDisable_RenderCache_OperationalFlush:ivb */
6943 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6944
ecdb4eb7 6945 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6946 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6947 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6948
ecdb4eb7 6949 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6950 I915_WRITE(GEN7_L3CNTLREG1,
6951 GEN7_WA_FOR_GEN7_L3_CONTROL);
6952 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6953 GEN7_WA_L3_CHICKEN_MODE);
6954 if (IS_IVB_GT1(dev))
6955 I915_WRITE(GEN7_ROW_CHICKEN2,
6956 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6957 else {
6958 /* must write both registers */
6959 I915_WRITE(GEN7_ROW_CHICKEN2,
6960 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6961 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6962 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6963 }
6f1d69b0 6964
ecdb4eb7 6965 /* WaForceL3Serialization:ivb */
61939d97
JB		 6966 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6967 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6968
1b80a19a 6969 /*
0f846f81 6970 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6971 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6972 */
6973 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6974 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6975
ecdb4eb7 6976 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6977 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6978 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6979 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6980
0e088b8f 6981 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6982
6983 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6984
22721343
CW		 6985 if (0) { /* causes HiZ corruption on ivb:gt1 */
6986 /* enable HiZ Raw Stall Optimization */
6987 I915_WRITE(CACHE_MODE_0_GEN7,
6988 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6989 }
116f2b6d 6990
ecdb4eb7 6991 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6992 I915_WRITE(CACHE_MODE_1,
6993 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6994
a607c1a4
VS		 6995 /*
6996 * BSpec recommends 8x4 when MSAA is used,
6997 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6998 *
6999 * Note that PS/WM thread counts depend on the WIZ hashing
7000 * disable bit, which we don't touch here, but it's good
7001 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7002 */
7003 I915_WRITE(GEN7_GT_MODE,
98533251 7004 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7005
20848223
BW		 7006 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7007 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7008 snpcr |= GEN6_MBC_SNPCR_MED;
7009 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7010
ab5c608b
BW		 7011 if (!HAS_PCH_NOP(dev))
7012 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7013
7014 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7015}
7016
1fa61106 7017static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7018{
7019 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 7020
ecdb4eb7 7021 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7022 I915_WRITE(_3D_CHICKEN3,
7023 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7024
ecdb4eb7 7025 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7026 I915_WRITE(IVB_CHICKEN3,
7027 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7028 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7029
fad7d36e 7030 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7031 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7032 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7033 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7034 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7035
4e04632e
AG		 7036 /* WaDisable_RenderCache_OperationalFlush:vlv */
7037 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7038
ecdb4eb7 7039 /* WaForceL3Serialization:vlv */
61939d97
JB		 7040 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7041 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7042
ecdb4eb7 7043 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7044 I915_WRITE(GEN7_ROW_CHICKEN2,
7045 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7046
ecdb4eb7 7047 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7048 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7049 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7050 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7051
46680e0a
VS		 7052 gen7_setup_fixed_func_scheduler(dev_priv);
7053
3c0edaeb 7054 /*
0f846f81 7055 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7056 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7057 */
7058 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7059 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7060
c98f5062
AG		 7061 /* WaDisableL3Bank2xClockGate:vlv
7062 * Disabling L3 clock gating- MMIO 940c[25] = 1
7063 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7064 I915_WRITE(GEN7_UCGCTL4,
7065 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7066
afd58e79
VS		 7067 /*
7068 * BSpec says this must be set, even though
7069 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7070 */
6b26c86d
DV		 7071 I915_WRITE(CACHE_MODE_1,
7072 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7073
da2518f9
VS		 7074 /*
7075 * BSpec recommends 8x4 when MSAA is used,
7076 * however in practice 16x4 seems fastest.
7077 *
7078 * Note that PS/WM thread counts depend on the WIZ hashing
7079 * disable bit, which we don't touch here, but it's good
7080 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7081 */
7082 I915_WRITE(GEN7_GT_MODE,
7083 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7084
031994ee
VS		 7085 /*
7086 * WaIncreaseL3CreditsForVLVB0:vlv
7087 * This is the hardware default actually.
7088 */
7089 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7090
2d809570 7091 /*
ecdb4eb7 7092 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7093 * Disable clock gating on th GCFG unit to prevent a delay
7094 * in the reporting of vblank events.
7095 */
7a0d1eed 7096 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7097}
7098
a4565da8
VS		 7099static void cherryview_init_clock_gating(struct drm_device *dev)
7100{
7101 struct drm_i915_private *dev_priv = dev->dev_private;
7102
232ce337
VS		 7103 /* WaVSRefCountFullforceMissDisable:chv */
7104 /* WaDSRefCountFullforceMissDisable:chv */
7105 I915_WRITE(GEN7_FF_THREAD_MODE,
7106 I915_READ(GEN7_FF_THREAD_MODE) &
7107 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7108
7109 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7110 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7111 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7112
7113 /* WaDisableCSUnitClockGating:chv */
7114 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7115 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7116
7117 /* WaDisableSDEUnitClockGating:chv */
7118 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7119 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7120
450174fe
ID		 7121 /*
7122 * WaProgramL3SqcReg1Default:chv
7123 * See gfxspecs/Related Documents/Performance Guide/
7124 * LSQC Setting Recommendations.
7125 */
7126 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7127
6d50b065
VS		 7128 /*
7129 * GTT cache may not work with big pages, so if those
7130 * are ever enabled GTT cache may need to be disabled.
7131 */
7132 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7133}
7134
1fa61106 7135static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7136{
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 uint32_t dspclk_gate;
7139
7140 I915_WRITE(RENCLK_GATE_D1, 0);
7141 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7142 GS_UNIT_CLOCK_GATE_DISABLE |
7143 CL_UNIT_CLOCK_GATE_DISABLE);
7144 I915_WRITE(RAMCLK_GATE_D, 0);
7145 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7146 OVRUNIT_CLOCK_GATE_DISABLE |
7147 OVCUNIT_CLOCK_GATE_DISABLE;
7148 if (IS_GM45(dev))
7149 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7150 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7151
7152 /* WaDisableRenderCachePipelinedFlush */
7153 I915_WRITE(CACHE_MODE_0,
7154 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7155
4e04632e
AG		 7156 /* WaDisable_RenderCache_OperationalFlush:g4x */
7157 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7158
0e088b8f 7159 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7160}
7161
1fa61106 7162static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7163{
7164 struct drm_i915_private *dev_priv = dev->dev_private;
7165
7166 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7167 I915_WRITE(RENCLK_GATE_D2, 0);
7168 I915_WRITE(DSPCLK_GATE_D, 0);
7169 I915_WRITE(RAMCLK_GATE_D, 0);
7170 I915_WRITE16(DEUC, 0);
20f94967
VS		 7171 I915_WRITE(MI_ARB_STATE,
7172 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7173
7174 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7175 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7176}
7177
1fa61106 7178static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7179{
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181
7182 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7183 I965_RCC_CLOCK_GATE_DISABLE |
7184 I965_RCPB_CLOCK_GATE_DISABLE |
7185 I965_ISC_CLOCK_GATE_DISABLE |
7186 I965_FBC_CLOCK_GATE_DISABLE);
7187 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7188 I915_WRITE(MI_ARB_STATE,
7189 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7190
7191 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7192 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7193}
7194
1fa61106 7195static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7196{
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 u32 dstate = I915_READ(D_STATE);
7199
7200 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7201 DSTATE_DOT_CLOCK_GATING;
7202 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7203
7204 if (IS_PINEVIEW(dev))
7205 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7206
7207 /* IIR "flip pending" means done if this bit is set */
7208 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7209
7210 /* interrupts should cause a wake up from C3 */
3299254f 7211 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7212
7213 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7214 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7215
7216 I915_WRITE(MI_ARB_STATE,
7217 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7218}
7219
1fa61106 7220static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7221{
7222 struct drm_i915_private *dev_priv = dev->dev_private;
7223
7224 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7225
7226 /* interrupts should cause a wake up from C3 */
7227 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7228 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7229
7230 I915_WRITE(MEM_MODE,
7231 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7232}
7233
1fa61106 7234static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7235{
7236 struct drm_i915_private *dev_priv = dev->dev_private;
7237
7238 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7239
7240 I915_WRITE(MEM_MODE,
7241 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7242 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7243}
7244
6f1d69b0
ED		 7245void intel_init_clock_gating(struct drm_device *dev)
7246{
7247 struct drm_i915_private *dev_priv = dev->dev_private;
7248
bb400da9 7249 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7250}
7251
7d708ee4
ID		 7252void intel_suspend_hw(struct drm_device *dev)
7253{
7254 if (HAS_PCH_LPT(dev))
7255 lpt_suspend_hw(dev);
7256}
7257
bb400da9
ID		 7258static void nop_init_clock_gating(struct drm_device *dev)
7259{
7260 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7261}
7262
7263/**
7264 * intel_init_clock_gating_hooks - setup the clock gating hooks
7265 * @dev_priv: device private
7266 *
7267 * Setup the hooks that configure which clocks of a given platform can be
7268 * gated and also apply various GT and display specific workarounds for these
7269 * platforms. Note that some GT specific workarounds are applied separately
7270 * when GPU contexts or batchbuffers start their execution.
7271 */
7272void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7273{
7274 if (IS_SKYLAKE(dev_priv))
7275 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7276 else if (IS_KABYLAKE(dev_priv))
7277 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7278 else if (IS_BROXTON(dev_priv))
7279 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7280 else if (IS_BROADWELL(dev_priv))
7281 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7282 else if (IS_CHERRYVIEW(dev_priv))
7283 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7284 else if (IS_HASWELL(dev_priv))
7285 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7286 else if (IS_IVYBRIDGE(dev_priv))
7287 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7288 else if (IS_VALLEYVIEW(dev_priv))
7289 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7290 else if (IS_GEN6(dev_priv))
7291 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7292 else if (IS_GEN5(dev_priv))
7293 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7294 else if (IS_G4X(dev_priv))
7295 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7296 else if (IS_CRESTLINE(dev_priv))
7297 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7298 else if (IS_BROADWATER(dev_priv))
7299 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7300 else if (IS_GEN3(dev_priv))
7301 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7302 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7303 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7304 else if (IS_GEN2(dev_priv))
7305 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7306 else {
7307 MISSING_CASE(INTEL_DEVID(dev_priv));
7308 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7309 }
7310}
7311
1fa61106
ED		 7312/* Set up chip specific power management-related functions */
7313void intel_init_pm(struct drm_device *dev)
7314{
7315 struct drm_i915_private *dev_priv = dev->dev_private;
7316
7ff0ebcc 7317 intel_fbc_init(dev_priv);
1fa61106 7318
c921aba8
DV		 7319 /* For cxsr */
7320 if (IS_PINEVIEW(dev))
7321 i915_pineview_get_mem_freq(dev);
7322 else if (IS_GEN5(dev))
7323 i915_ironlake_get_mem_freq(dev);
7324
1fa61106 7325 /* For FIFO watermark updates */
f5ed50cb 7326 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7327 skl_setup_wm_latency(dev);
2d41c0b5 7328 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7329 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7330 ilk_setup_wm_latency(dev);
53615a5e 7331
bd602544
VS		 7332 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7333 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7334 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7335 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7336 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7337 dev_priv->display.compute_intermediate_wm =
7338 ilk_compute_intermediate_wm;
7339 dev_priv->display.initial_watermarks =
7340 ilk_initial_watermarks;
7341 dev_priv->display.optimize_watermarks =
7342 ilk_optimize_watermarks;
bd602544
VS		 7343 } else {
7344 DRM_DEBUG_KMS("Failed to read display plane latency. "
7345 "Disable CxSR\n");
7346 }
a4565da8 7347 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7348 vlv_setup_wm_latency(dev);
262cd2e1 7349 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7350 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7351 vlv_setup_wm_latency(dev);
26e1fe4f 7352 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7353 } else if (IS_PINEVIEW(dev)) {
7354 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7355 dev_priv->is_ddr3,
7356 dev_priv->fsb_freq,
7357 dev_priv->mem_freq)) {
7358 DRM_INFO("failed to find known CxSR latency "
7359 "(found ddr%s fsb freq %d, mem freq %d), "
7360 "disabling CxSR\n",
7361 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7362 dev_priv->fsb_freq, dev_priv->mem_freq);
7363 /* Disable CxSR and never update its watermark again */
5209b1f4 7364 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7365 dev_priv->display.update_wm = NULL;
7366 } else
7367 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7368 } else if (IS_G4X(dev)) {
7369 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7370 } else if (IS_GEN4(dev)) {
7371 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7372 } else if (IS_GEN3(dev)) {
7373 dev_priv->display.update_wm = i9xx_update_wm;
7374 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7375 } else if (IS_GEN2(dev)) {
7376 if (INTEL_INFO(dev)->num_pipes == 1) {
7377 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7378 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7379 } else {
7380 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7381 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7382 }
feb56b93
DV		 7383 } else {
7384 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7385 }
7386}
7387
151a49d0 7388int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7389{
4fc688ce 7390 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7391
7392 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7393 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7394 return -EAGAIN;
7395 }
7396
7397 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7398 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7399 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7400
7401 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7402 500)) {
7403 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7404 return -ETIMEDOUT;
7405 }
7406
7407 *val = I915_READ(GEN6_PCODE_DATA);
7408 I915_WRITE(GEN6_PCODE_DATA, 0);
7409
7410 return 0;
7411}
7412
151a49d0 7413int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7414{
4fc688ce 7415 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7416
7417 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7418 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7419 return -EAGAIN;
7420 }
7421
7422 I915_WRITE(GEN6_PCODE_DATA, val);
7423 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7424
7425 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7426 500)) {
7427 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7428 return -ETIMEDOUT;
7429 }
7430
7431 I915_WRITE(GEN6_PCODE_DATA, 0);
7432
7433 return 0;
7434}
a0e4e199 7435
dd06f88c
VS		 7436static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7437{
c30fec65
VS		 7438 /*
7439 * N = val - 0xb7
7440 * Slow = Fast = GPLL ref * N
7441 */
7442 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7443}
7444
b55dd647 7445static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7446{
c30fec65 7447 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7448}
7449
b55dd647 7450static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7451{
c30fec65
VS		 7452 /*
7453 * N = val / 2
7454 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7455 */
7456 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7457}
7458
b55dd647 7459static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7460{
1c14762d 7461 /* CHV needs even values */
c30fec65 7462 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7463}
7464
616bc820 7465int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7466{
2d1fe073 7467 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7468 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7469 GEN9_FREQ_SCALER);
2d1fe073 7470 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7471 return chv_gpu_freq(dev_priv, val);
2d1fe073 7472 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7473 return byt_gpu_freq(dev_priv, val);
7474 else
7475 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7476}
7477
616bc820
VS		 7478int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7479{
2d1fe073 7480 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7481 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7482 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7483 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7484 return chv_freq_opcode(dev_priv, val);
2d1fe073 7485 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7486 return byt_freq_opcode(dev_priv, val);
7487 else
500a3d2e 7488 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7489}
22b1b2f8 7490
6ad790c0
CW		 7491struct request_boost {
7492 struct work_struct work;
eed29a5b 7493 struct drm_i915_gem_request *req;
6ad790c0
CW		 7494};
7495
7496static void __intel_rps_boost_work(struct work_struct *work)
7497{
7498 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7499 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7500
e61b9958 7501 if (!i915_gem_request_completed(req, true))
c033666a 7502 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7503
73db04cf 7504 i915_gem_request_unreference(req);
6ad790c0
CW		 7505 kfree(boost);
7506}
7507
91d14251 7508void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7509{
7510 struct request_boost *boost;
7511
91d14251 7512 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7513 return;
7514
e61b9958
CW		 7515 if (i915_gem_request_completed(req, true))
7516 return;
7517
6ad790c0
CW		 7518 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7519 if (boost == NULL)
7520 return;
7521
eed29a5b
DV		 7522 i915_gem_request_reference(req);
7523 boost->req = req;
6ad790c0
CW		 7524
7525 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7526 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7527}
7528
f742a552 7529void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7530{
7531 struct drm_i915_private *dev_priv = dev->dev_private;
7532
f742a552 7533 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7534 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7535
907b28c5
CW		 7536 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7537 intel_gen6_powersave_work);
1854d5ca 7538 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7539 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7540 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7541
33688d95 7542 dev_priv->pm.suspended = false;
1f814dac 7543 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7544 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7545}
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