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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
9c2f7a9d | 29 | #include <drm/drm_plane_helper.h> |
85208be0 ED |
30 | #include "i915_drv.h" |
31 | #include "intel_drv.h" | |
eb48eb00 DV |
32 | #include "../../../platform/x86/intel_ips.h" |
33 | #include <linux/module.h> | |
c8fe32c1 | 34 | #include <drm/drm_atomic_helper.h> |
85208be0 | 35 | |
dc39fff7 | 36 | /** |
18afd443 JN |
37 | * DOC: RC6 |
38 | * | |
dc39fff7 BW |
39 | * RC6 is a special power stage which allows the GPU to enter an very |
40 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
41 | * stage is entered automatically when the GPU is idle when RC6 support is | |
42 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
43 | * | |
44 | * There are different RC6 modes available in Intel GPU, which differentiate | |
45 | * among each other with the latency required to enter and leave RC6 and | |
46 | * voltage consumed by the GPU in different states. | |
47 | * | |
48 | * The combination of the following flags define which states GPU is allowed | |
49 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
50 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
51 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
52 | * which brings the most power savings; deeper states save more power, but | |
53 | * require higher latency to switch to and wake up. | |
54 | */ | |
55 | #define INTEL_RC6_ENABLE (1<<0) | |
56 | #define INTEL_RC6p_ENABLE (1<<1) | |
57 | #define INTEL_RC6pp_ENABLE (1<<2) | |
58 | ||
46f16e63 | 59 | static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) |
a82abe43 | 60 | { |
b033bb6d | 61 | /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */ |
dc00b6a0 DV |
62 | I915_WRITE(CHICKEN_PAR1_1, |
63 | I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); | |
64 | ||
b033bb6d MK |
65 | I915_WRITE(GEN8_CONFIG0, |
66 | I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); | |
590e8ff0 | 67 | |
9fb5026f | 68 | /* WaEnableChickenDCPR:skl,bxt,kbl,glk */ |
590e8ff0 MK |
69 | I915_WRITE(GEN8_CHICKEN_DCPR_1, |
70 | I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); | |
0f78dee6 MK |
71 | |
72 | /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */ | |
9fb5026f | 73 | /* WaFbcWakeMemOn:skl,bxt,kbl,glk */ |
303d4ea5 MK |
74 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
75 | DISP_FBC_WM_DIS | | |
76 | DISP_FBC_MEMORY_WAKE); | |
d1b4eefd MK |
77 | |
78 | /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */ | |
79 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
80 | ILK_DPFC_DISABLE_DUMMY0); | |
b033bb6d MK |
81 | } |
82 | ||
46f16e63 | 83 | static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) |
b033bb6d | 84 | { |
46f16e63 | 85 | gen9_init_clock_gating(dev_priv); |
b033bb6d | 86 | |
a7546159 NH |
87 | /* WaDisableSDEUnitClockGating:bxt */ |
88 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
89 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
90 | ||
32608ca2 ID |
91 | /* |
92 | * FIXME: | |
868434c5 | 93 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
32608ca2 | 94 | */ |
32608ca2 | 95 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
868434c5 | 96 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
d965e7ac ID |
97 | |
98 | /* | |
99 | * Wa: Backlight PWM may stop in the asserted state, causing backlight | |
100 | * to stay fully on. | |
101 | */ | |
8aeaf64c JN |
102 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | |
103 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
a82abe43 ID |
104 | } |
105 | ||
9fb5026f ACO |
106 | static void glk_init_clock_gating(struct drm_i915_private *dev_priv) |
107 | { | |
108 | gen9_init_clock_gating(dev_priv); | |
109 | ||
110 | /* | |
111 | * WaDisablePWMClockGating:glk | |
112 | * Backlight PWM may stop in the asserted state, causing backlight | |
113 | * to stay fully on. | |
114 | */ | |
115 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | | |
116 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
f4f4b59b ACO |
117 | |
118 | /* WaDDIIOTimeout:glk */ | |
119 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { | |
120 | u32 val = I915_READ(CHICKEN_MISC_2); | |
121 | val &= ~(GLK_CL0_PWR_DOWN | | |
122 | GLK_CL1_PWR_DOWN | | |
123 | GLK_CL2_PWR_DOWN); | |
124 | I915_WRITE(CHICKEN_MISC_2, val); | |
125 | } | |
126 | ||
9fb5026f ACO |
127 | } |
128 | ||
148ac1f3 | 129 | static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 130 | { |
c921aba8 DV |
131 | u32 tmp; |
132 | ||
133 | tmp = I915_READ(CLKCFG); | |
134 | ||
135 | switch (tmp & CLKCFG_FSB_MASK) { | |
136 | case CLKCFG_FSB_533: | |
137 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
138 | break; | |
139 | case CLKCFG_FSB_800: | |
140 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
141 | break; | |
142 | case CLKCFG_FSB_667: | |
143 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
144 | break; | |
145 | case CLKCFG_FSB_400: | |
146 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
147 | break; | |
148 | } | |
149 | ||
150 | switch (tmp & CLKCFG_MEM_MASK) { | |
151 | case CLKCFG_MEM_533: | |
152 | dev_priv->mem_freq = 533; | |
153 | break; | |
154 | case CLKCFG_MEM_667: | |
155 | dev_priv->mem_freq = 667; | |
156 | break; | |
157 | case CLKCFG_MEM_800: | |
158 | dev_priv->mem_freq = 800; | |
159 | break; | |
160 | } | |
161 | ||
162 | /* detect pineview DDR3 setting */ | |
163 | tmp = I915_READ(CSHRDDR3CTL); | |
164 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
165 | } | |
166 | ||
148ac1f3 | 167 | static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 168 | { |
c921aba8 DV |
169 | u16 ddrpll, csipll; |
170 | ||
171 | ddrpll = I915_READ16(DDRMPLL1); | |
172 | csipll = I915_READ16(CSIPLL0); | |
173 | ||
174 | switch (ddrpll & 0xff) { | |
175 | case 0xc: | |
176 | dev_priv->mem_freq = 800; | |
177 | break; | |
178 | case 0x10: | |
179 | dev_priv->mem_freq = 1066; | |
180 | break; | |
181 | case 0x14: | |
182 | dev_priv->mem_freq = 1333; | |
183 | break; | |
184 | case 0x18: | |
185 | dev_priv->mem_freq = 1600; | |
186 | break; | |
187 | default: | |
188 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
189 | ddrpll & 0xff); | |
190 | dev_priv->mem_freq = 0; | |
191 | break; | |
192 | } | |
193 | ||
20e4d407 | 194 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
195 | |
196 | switch (csipll & 0x3ff) { | |
197 | case 0x00c: | |
198 | dev_priv->fsb_freq = 3200; | |
199 | break; | |
200 | case 0x00e: | |
201 | dev_priv->fsb_freq = 3733; | |
202 | break; | |
203 | case 0x010: | |
204 | dev_priv->fsb_freq = 4266; | |
205 | break; | |
206 | case 0x012: | |
207 | dev_priv->fsb_freq = 4800; | |
208 | break; | |
209 | case 0x014: | |
210 | dev_priv->fsb_freq = 5333; | |
211 | break; | |
212 | case 0x016: | |
213 | dev_priv->fsb_freq = 5866; | |
214 | break; | |
215 | case 0x018: | |
216 | dev_priv->fsb_freq = 6400; | |
217 | break; | |
218 | default: | |
219 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
220 | csipll & 0x3ff); | |
221 | dev_priv->fsb_freq = 0; | |
222 | break; | |
223 | } | |
224 | ||
225 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 226 | dev_priv->ips.c_m = 0; |
c921aba8 | 227 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 228 | dev_priv->ips.c_m = 1; |
c921aba8 | 229 | } else { |
20e4d407 | 230 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
231 | } |
232 | } | |
233 | ||
b445e3b0 ED |
234 | static const struct cxsr_latency cxsr_latency_table[] = { |
235 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
236 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
237 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
238 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
239 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
240 | ||
241 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
242 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
243 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
244 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
245 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
246 | ||
247 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
248 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
249 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
250 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
251 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
252 | ||
253 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
254 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
255 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
256 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
257 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
258 | ||
259 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
260 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
261 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
262 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
263 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
264 | ||
265 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
266 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
267 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
268 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
269 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
270 | }; | |
271 | ||
44a655ca TU |
272 | static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop, |
273 | bool is_ddr3, | |
b445e3b0 ED |
274 | int fsb, |
275 | int mem) | |
276 | { | |
277 | const struct cxsr_latency *latency; | |
278 | int i; | |
279 | ||
280 | if (fsb == 0 || mem == 0) | |
281 | return NULL; | |
282 | ||
283 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
284 | latency = &cxsr_latency_table[i]; | |
285 | if (is_desktop == latency->is_desktop && | |
286 | is_ddr3 == latency->is_ddr3 && | |
287 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
288 | return latency; | |
289 | } | |
290 | ||
291 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
292 | ||
293 | return NULL; | |
294 | } | |
295 | ||
fc1ac8de VS |
296 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
297 | { | |
298 | u32 val; | |
299 | ||
300 | mutex_lock(&dev_priv->rps.hw_lock); | |
301 | ||
302 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
303 | if (enable) | |
304 | val &= ~FORCE_DDR_HIGH_FREQ; | |
305 | else | |
306 | val |= FORCE_DDR_HIGH_FREQ; | |
307 | val &= ~FORCE_DDR_LOW_FREQ; | |
308 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
309 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
310 | ||
311 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
312 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
313 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
314 | ||
315 | mutex_unlock(&dev_priv->rps.hw_lock); | |
316 | } | |
317 | ||
cfb41411 VS |
318 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
319 | { | |
320 | u32 val; | |
321 | ||
322 | mutex_lock(&dev_priv->rps.hw_lock); | |
323 | ||
324 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
325 | if (enable) | |
326 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
327 | else | |
328 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
329 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
330 | ||
331 | mutex_unlock(&dev_priv->rps.hw_lock); | |
332 | } | |
333 | ||
f4998963 VS |
334 | #define FW_WM(value, plane) \ |
335 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
336 | ||
11a85d6a | 337 | static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 338 | { |
11a85d6a | 339 | bool was_enabled; |
5209b1f4 | 340 | u32 val; |
b445e3b0 | 341 | |
920a14b2 | 342 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
11a85d6a | 343 | was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
5209b1f4 | 344 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
a7a6c498 | 345 | POSTING_READ(FW_BLC_SELF_VLV); |
c0f86832 | 346 | } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { |
11a85d6a | 347 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 | 348 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
a7a6c498 | 349 | POSTING_READ(FW_BLC_SELF); |
9b1e14f4 | 350 | } else if (IS_PINEVIEW(dev_priv)) { |
11a85d6a VS |
351 | val = I915_READ(DSPFW3); |
352 | was_enabled = val & PINEVIEW_SELF_REFRESH_EN; | |
353 | if (enable) | |
354 | val |= PINEVIEW_SELF_REFRESH_EN; | |
355 | else | |
356 | val &= ~PINEVIEW_SELF_REFRESH_EN; | |
5209b1f4 | 357 | I915_WRITE(DSPFW3, val); |
a7a6c498 | 358 | POSTING_READ(DSPFW3); |
50a0bc90 | 359 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { |
11a85d6a | 360 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 ID |
361 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
362 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
363 | I915_WRITE(FW_BLC_SELF, val); | |
a7a6c498 | 364 | POSTING_READ(FW_BLC_SELF); |
50a0bc90 | 365 | } else if (IS_I915GM(dev_priv)) { |
acb91359 VS |
366 | /* |
367 | * FIXME can't find a bit like this for 915G, and | |
368 | * and yet it does have the related watermark in | |
369 | * FW_BLC_SELF. What's going on? | |
370 | */ | |
11a85d6a | 371 | was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
5209b1f4 ID |
372 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
373 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
374 | I915_WRITE(INSTPM, val); | |
a7a6c498 | 375 | POSTING_READ(INSTPM); |
5209b1f4 | 376 | } else { |
11a85d6a | 377 | return false; |
5209b1f4 | 378 | } |
b445e3b0 | 379 | |
1489bba8 VS |
380 | trace_intel_memory_cxsr(dev_priv, was_enabled, enable); |
381 | ||
11a85d6a VS |
382 | DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n", |
383 | enableddisabled(enable), | |
384 | enableddisabled(was_enabled)); | |
385 | ||
386 | return was_enabled; | |
b445e3b0 ED |
387 | } |
388 | ||
11a85d6a | 389 | bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
3d90e649 | 390 | { |
11a85d6a VS |
391 | bool ret; |
392 | ||
3d90e649 | 393 | mutex_lock(&dev_priv->wm.wm_mutex); |
11a85d6a | 394 | ret = _intel_set_memory_cxsr(dev_priv, enable); |
3d90e649 VS |
395 | dev_priv->wm.vlv.cxsr = enable; |
396 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
11a85d6a VS |
397 | |
398 | return ret; | |
3d90e649 | 399 | } |
fc1ac8de | 400 | |
b445e3b0 ED |
401 | /* |
402 | * Latency for FIFO fetches is dependent on several factors: | |
403 | * - memory configuration (speed, channels) | |
404 | * - chipset | |
405 | * - current MCH state | |
406 | * It can be fairly high in some situations, so here we assume a fairly | |
407 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
408 | * set this value too high, the FIFO will fetch frequently to stay full) | |
409 | * and power consumption (set it too low to save power and we might see | |
410 | * FIFO underruns and display "flicker"). | |
411 | * | |
412 | * A value of 5us seems to be a good balance; safe for very low end | |
413 | * platforms but not overly aggressive on lower latency configs. | |
414 | */ | |
5aef6003 | 415 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 416 | |
b5004720 VS |
417 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
418 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
419 | ||
814e7f0b | 420 | static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) |
b5004720 | 421 | { |
814e7f0b | 422 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 423 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b | 424 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
f07d43d2 VS |
425 | enum pipe pipe = crtc->pipe; |
426 | int sprite0_start, sprite1_start; | |
49845a23 | 427 | |
f07d43d2 | 428 | switch (pipe) { |
b5004720 VS |
429 | uint32_t dsparb, dsparb2, dsparb3; |
430 | case PIPE_A: | |
431 | dsparb = I915_READ(DSPARB); | |
432 | dsparb2 = I915_READ(DSPARB2); | |
433 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
434 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
435 | break; | |
436 | case PIPE_B: | |
437 | dsparb = I915_READ(DSPARB); | |
438 | dsparb2 = I915_READ(DSPARB2); | |
439 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
440 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
441 | break; | |
442 | case PIPE_C: | |
443 | dsparb2 = I915_READ(DSPARB2); | |
444 | dsparb3 = I915_READ(DSPARB3); | |
445 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
446 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
447 | break; | |
448 | default: | |
f07d43d2 VS |
449 | MISSING_CASE(pipe); |
450 | return; | |
b5004720 VS |
451 | } |
452 | ||
f07d43d2 VS |
453 | fifo_state->plane[PLANE_PRIMARY] = sprite0_start; |
454 | fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start; | |
455 | fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start; | |
456 | fifo_state->plane[PLANE_CURSOR] = 63; | |
457 | ||
458 | DRM_DEBUG_KMS("Pipe %c FIFO size: %d/%d/%d/%d\n", | |
459 | pipe_name(pipe), | |
460 | fifo_state->plane[PLANE_PRIMARY], | |
461 | fifo_state->plane[PLANE_SPRITE0], | |
462 | fifo_state->plane[PLANE_SPRITE1], | |
463 | fifo_state->plane[PLANE_CURSOR]); | |
b5004720 VS |
464 | } |
465 | ||
ef0f5e93 | 466 | static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 467 | { |
b445e3b0 ED |
468 | uint32_t dsparb = I915_READ(DSPARB); |
469 | int size; | |
470 | ||
471 | size = dsparb & 0x7f; | |
472 | if (plane) | |
473 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
474 | ||
475 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
476 | plane ? "B" : "A", size); | |
477 | ||
478 | return size; | |
479 | } | |
480 | ||
ef0f5e93 | 481 | static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 482 | { |
b445e3b0 ED |
483 | uint32_t dsparb = I915_READ(DSPARB); |
484 | int size; | |
485 | ||
486 | size = dsparb & 0x1ff; | |
487 | if (plane) | |
488 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
489 | size >>= 1; /* Convert to cachelines */ | |
490 | ||
491 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
492 | plane ? "B" : "A", size); | |
493 | ||
494 | return size; | |
495 | } | |
496 | ||
ef0f5e93 | 497 | static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 498 | { |
b445e3b0 ED |
499 | uint32_t dsparb = I915_READ(DSPARB); |
500 | int size; | |
501 | ||
502 | size = dsparb & 0x7f; | |
503 | size >>= 2; /* Convert to cachelines */ | |
504 | ||
505 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
506 | plane ? "B" : "A", | |
507 | size); | |
508 | ||
509 | return size; | |
510 | } | |
511 | ||
b445e3b0 ED |
512 | /* Pineview has different values for various configs */ |
513 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
514 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
515 | .max_wm = PINEVIEW_MAX_WM, | |
516 | .default_wm = PINEVIEW_DFT_WM, | |
517 | .guard_size = PINEVIEW_GUARD_WM, | |
518 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
519 | }; |
520 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
521 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
522 | .max_wm = PINEVIEW_MAX_WM, | |
523 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
524 | .guard_size = PINEVIEW_GUARD_WM, | |
525 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
526 | }; |
527 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
528 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
529 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
530 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
531 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
532 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
533 | }; |
534 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
535 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
536 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
537 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
538 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
539 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
540 | }; |
541 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
542 | .fifo_size = G4X_FIFO_SIZE, |
543 | .max_wm = G4X_MAX_WM, | |
544 | .default_wm = G4X_MAX_WM, | |
545 | .guard_size = 2, | |
546 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
547 | }; |
548 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
549 | .fifo_size = I965_CURSOR_FIFO, |
550 | .max_wm = I965_CURSOR_MAX_WM, | |
551 | .default_wm = I965_CURSOR_DFT_WM, | |
552 | .guard_size = 2, | |
553 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 | 554 | }; |
b445e3b0 | 555 | static const struct intel_watermark_params i965_cursor_wm_info = { |
e0f0273e VS |
556 | .fifo_size = I965_CURSOR_FIFO, |
557 | .max_wm = I965_CURSOR_MAX_WM, | |
558 | .default_wm = I965_CURSOR_DFT_WM, | |
559 | .guard_size = 2, | |
560 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
561 | }; |
562 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
563 | .fifo_size = I945_FIFO_SIZE, |
564 | .max_wm = I915_MAX_WM, | |
565 | .default_wm = 1, | |
566 | .guard_size = 2, | |
567 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
568 | }; |
569 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
570 | .fifo_size = I915_FIFO_SIZE, |
571 | .max_wm = I915_MAX_WM, | |
572 | .default_wm = 1, | |
573 | .guard_size = 2, | |
574 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 575 | }; |
9d539105 | 576 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
577 | .fifo_size = I855GM_FIFO_SIZE, |
578 | .max_wm = I915_MAX_WM, | |
579 | .default_wm = 1, | |
580 | .guard_size = 2, | |
581 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 582 | }; |
9d539105 VS |
583 | static const struct intel_watermark_params i830_bc_wm_info = { |
584 | .fifo_size = I855GM_FIFO_SIZE, | |
585 | .max_wm = I915_MAX_WM/2, | |
586 | .default_wm = 1, | |
587 | .guard_size = 2, | |
588 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
589 | }; | |
feb56b93 | 590 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
591 | .fifo_size = I830_FIFO_SIZE, |
592 | .max_wm = I915_MAX_WM, | |
593 | .default_wm = 1, | |
594 | .guard_size = 2, | |
595 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
596 | }; |
597 | ||
b445e3b0 ED |
598 | /** |
599 | * intel_calculate_wm - calculate watermark level | |
600 | * @clock_in_khz: pixel clock | |
601 | * @wm: chip FIFO params | |
ac484963 | 602 | * @cpp: bytes per pixel |
b445e3b0 ED |
603 | * @latency_ns: memory latency for the platform |
604 | * | |
605 | * Calculate the watermark level (the level at which the display plane will | |
606 | * start fetching from memory again). Each chip has a different display | |
607 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
608 | * in the correct intel_watermark_params structure. | |
609 | * | |
610 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
611 | * on the pixel size. When it reaches the watermark level, it'll start | |
612 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
613 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
614 | * will occur, and a display engine hang could result. | |
615 | */ | |
616 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
617 | const struct intel_watermark_params *wm, | |
ac484963 | 618 | int fifo_size, int cpp, |
b445e3b0 ED |
619 | unsigned long latency_ns) |
620 | { | |
621 | long entries_required, wm_size; | |
622 | ||
623 | /* | |
624 | * Note: we need to make sure we don't overflow for various clock & | |
625 | * latency values. | |
626 | * clocks go from a few thousand to several hundred thousand. | |
627 | * latency is usually a few thousand | |
628 | */ | |
ac484963 | 629 | entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) / |
b445e3b0 ED |
630 | 1000; |
631 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
632 | ||
633 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
634 | ||
635 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
636 | ||
637 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
638 | ||
639 | /* Don't promote wm_size to unsigned... */ | |
640 | if (wm_size > (long)wm->max_wm) | |
641 | wm_size = wm->max_wm; | |
642 | if (wm_size <= 0) | |
643 | wm_size = wm->default_wm; | |
d6feb196 VS |
644 | |
645 | /* | |
646 | * Bspec seems to indicate that the value shouldn't be lower than | |
647 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
648 | * Lets go for 8 which is the burst size since certain platforms | |
649 | * already use a hardcoded 8 (which is what the spec says should be | |
650 | * done). | |
651 | */ | |
652 | if (wm_size <= 8) | |
653 | wm_size = 8; | |
654 | ||
b445e3b0 ED |
655 | return wm_size; |
656 | } | |
657 | ||
ffc7a76b | 658 | static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv) |
b445e3b0 | 659 | { |
efc2611e | 660 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 661 | |
ffc7a76b | 662 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
efc2611e | 663 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
664 | if (enabled) |
665 | return NULL; | |
666 | enabled = crtc; | |
667 | } | |
668 | } | |
669 | ||
670 | return enabled; | |
671 | } | |
672 | ||
432081bc | 673 | static void pineview_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 674 | { |
ffc7a76b | 675 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 676 | struct intel_crtc *crtc; |
b445e3b0 ED |
677 | const struct cxsr_latency *latency; |
678 | u32 reg; | |
679 | unsigned long wm; | |
680 | ||
50a0bc90 TU |
681 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
682 | dev_priv->is_ddr3, | |
683 | dev_priv->fsb_freq, | |
684 | dev_priv->mem_freq); | |
b445e3b0 ED |
685 | if (!latency) { |
686 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 687 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
688 | return; |
689 | } | |
690 | ||
ffc7a76b | 691 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 | 692 | if (crtc) { |
efc2611e VS |
693 | const struct drm_display_mode *adjusted_mode = |
694 | &crtc->config->base.adjusted_mode; | |
695 | const struct drm_framebuffer *fb = | |
696 | crtc->base.primary->state->fb; | |
353c8598 | 697 | int cpp = fb->format->cpp[0]; |
7c5f93b0 | 698 | int clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
699 | |
700 | /* Display SR */ | |
701 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
702 | pineview_display_wm.fifo_size, | |
ac484963 | 703 | cpp, latency->display_sr); |
b445e3b0 ED |
704 | reg = I915_READ(DSPFW1); |
705 | reg &= ~DSPFW_SR_MASK; | |
f4998963 | 706 | reg |= FW_WM(wm, SR); |
b445e3b0 ED |
707 | I915_WRITE(DSPFW1, reg); |
708 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
709 | ||
710 | /* cursor SR */ | |
711 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
712 | pineview_display_wm.fifo_size, | |
ac484963 | 713 | cpp, latency->cursor_sr); |
b445e3b0 ED |
714 | reg = I915_READ(DSPFW3); |
715 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
f4998963 | 716 | reg |= FW_WM(wm, CURSOR_SR); |
b445e3b0 ED |
717 | I915_WRITE(DSPFW3, reg); |
718 | ||
719 | /* Display HPLL off SR */ | |
720 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
721 | pineview_display_hplloff_wm.fifo_size, | |
ac484963 | 722 | cpp, latency->display_hpll_disable); |
b445e3b0 ED |
723 | reg = I915_READ(DSPFW3); |
724 | reg &= ~DSPFW_HPLL_SR_MASK; | |
f4998963 | 725 | reg |= FW_WM(wm, HPLL_SR); |
b445e3b0 ED |
726 | I915_WRITE(DSPFW3, reg); |
727 | ||
728 | /* cursor HPLL off SR */ | |
729 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
730 | pineview_display_hplloff_wm.fifo_size, | |
ac484963 | 731 | cpp, latency->cursor_hpll_disable); |
b445e3b0 ED |
732 | reg = I915_READ(DSPFW3); |
733 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
f4998963 | 734 | reg |= FW_WM(wm, HPLL_CURSOR); |
b445e3b0 ED |
735 | I915_WRITE(DSPFW3, reg); |
736 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
737 | ||
5209b1f4 | 738 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 739 | } else { |
5209b1f4 | 740 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
741 | } |
742 | } | |
743 | ||
f0ce2310 | 744 | static bool g4x_compute_wm0(struct drm_i915_private *dev_priv, |
b445e3b0 ED |
745 | int plane, |
746 | const struct intel_watermark_params *display, | |
747 | int display_latency_ns, | |
748 | const struct intel_watermark_params *cursor, | |
749 | int cursor_latency_ns, | |
750 | int *plane_wm, | |
751 | int *cursor_wm) | |
752 | { | |
efc2611e | 753 | struct intel_crtc *crtc; |
4fe8590a | 754 | const struct drm_display_mode *adjusted_mode; |
efc2611e | 755 | const struct drm_framebuffer *fb; |
ac484963 | 756 | int htotal, hdisplay, clock, cpp; |
b445e3b0 ED |
757 | int line_time_us, line_count; |
758 | int entries, tlb_miss; | |
759 | ||
b91eb5cc | 760 | crtc = intel_get_crtc_for_plane(dev_priv, plane); |
efc2611e | 761 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
762 | *cursor_wm = cursor->guard_size; |
763 | *plane_wm = display->guard_size; | |
764 | return false; | |
765 | } | |
766 | ||
efc2611e VS |
767 | adjusted_mode = &crtc->config->base.adjusted_mode; |
768 | fb = crtc->base.primary->state->fb; | |
241bfc38 | 769 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 770 | htotal = adjusted_mode->crtc_htotal; |
efc2611e | 771 | hdisplay = crtc->config->pipe_src_w; |
353c8598 | 772 | cpp = fb->format->cpp[0]; |
b445e3b0 ED |
773 | |
774 | /* Use the small buffer method to calculate plane watermark */ | |
ac484963 | 775 | entries = ((clock * cpp / 1000) * display_latency_ns) / 1000; |
b445e3b0 ED |
776 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
777 | if (tlb_miss > 0) | |
778 | entries += tlb_miss; | |
779 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
780 | *plane_wm = entries + display->guard_size; | |
781 | if (*plane_wm > (int)display->max_wm) | |
782 | *plane_wm = display->max_wm; | |
783 | ||
784 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 785 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 786 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
efc2611e | 787 | entries = line_count * crtc->base.cursor->state->crtc_w * cpp; |
b445e3b0 ED |
788 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
789 | if (tlb_miss > 0) | |
790 | entries += tlb_miss; | |
791 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
792 | *cursor_wm = entries + cursor->guard_size; | |
793 | if (*cursor_wm > (int)cursor->max_wm) | |
794 | *cursor_wm = (int)cursor->max_wm; | |
795 | ||
796 | return true; | |
797 | } | |
798 | ||
799 | /* | |
800 | * Check the wm result. | |
801 | * | |
802 | * If any calculated watermark values is larger than the maximum value that | |
803 | * can be programmed into the associated watermark register, that watermark | |
804 | * must be disabled. | |
805 | */ | |
f0ce2310 | 806 | static bool g4x_check_srwm(struct drm_i915_private *dev_priv, |
b445e3b0 ED |
807 | int display_wm, int cursor_wm, |
808 | const struct intel_watermark_params *display, | |
809 | const struct intel_watermark_params *cursor) | |
810 | { | |
811 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
812 | display_wm, cursor_wm); | |
813 | ||
814 | if (display_wm > display->max_wm) { | |
ae9400ca | 815 | DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n", |
b445e3b0 ED |
816 | display_wm, display->max_wm); |
817 | return false; | |
818 | } | |
819 | ||
820 | if (cursor_wm > cursor->max_wm) { | |
ae9400ca | 821 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n", |
b445e3b0 ED |
822 | cursor_wm, cursor->max_wm); |
823 | return false; | |
824 | } | |
825 | ||
826 | if (!(display_wm || cursor_wm)) { | |
827 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
828 | return false; | |
829 | } | |
830 | ||
831 | return true; | |
832 | } | |
833 | ||
f0ce2310 | 834 | static bool g4x_compute_srwm(struct drm_i915_private *dev_priv, |
b445e3b0 ED |
835 | int plane, |
836 | int latency_ns, | |
837 | const struct intel_watermark_params *display, | |
838 | const struct intel_watermark_params *cursor, | |
839 | int *display_wm, int *cursor_wm) | |
840 | { | |
efc2611e | 841 | struct intel_crtc *crtc; |
4fe8590a | 842 | const struct drm_display_mode *adjusted_mode; |
efc2611e | 843 | const struct drm_framebuffer *fb; |
ac484963 | 844 | int hdisplay, htotal, cpp, clock; |
b445e3b0 ED |
845 | unsigned long line_time_us; |
846 | int line_count, line_size; | |
847 | int small, large; | |
848 | int entries; | |
849 | ||
850 | if (!latency_ns) { | |
851 | *display_wm = *cursor_wm = 0; | |
852 | return false; | |
853 | } | |
854 | ||
b91eb5cc | 855 | crtc = intel_get_crtc_for_plane(dev_priv, plane); |
efc2611e VS |
856 | adjusted_mode = &crtc->config->base.adjusted_mode; |
857 | fb = crtc->base.primary->state->fb; | |
241bfc38 | 858 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 859 | htotal = adjusted_mode->crtc_htotal; |
efc2611e | 860 | hdisplay = crtc->config->pipe_src_w; |
353c8598 | 861 | cpp = fb->format->cpp[0]; |
b445e3b0 | 862 | |
922044c9 | 863 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 864 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
ac484963 | 865 | line_size = hdisplay * cpp; |
b445e3b0 ED |
866 | |
867 | /* Use the minimum of the small and large buffer method for primary */ | |
ac484963 | 868 | small = ((clock * cpp / 1000) * latency_ns) / 1000; |
b445e3b0 ED |
869 | large = line_count * line_size; |
870 | ||
871 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
872 | *display_wm = entries + display->guard_size; | |
873 | ||
874 | /* calculate the self-refresh watermark for display cursor */ | |
efc2611e | 875 | entries = line_count * cpp * crtc->base.cursor->state->crtc_w; |
b445e3b0 ED |
876 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
877 | *cursor_wm = entries + cursor->guard_size; | |
878 | ||
f0ce2310 | 879 | return g4x_check_srwm(dev_priv, |
b445e3b0 ED |
880 | *display_wm, *cursor_wm, |
881 | display, cursor); | |
882 | } | |
883 | ||
15665979 VS |
884 | #define FW_WM_VLV(value, plane) \ |
885 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
886 | ||
50f4caef | 887 | static void vlv_write_wm_values(struct drm_i915_private *dev_priv, |
0018fda1 VS |
888 | const struct vlv_wm_values *wm) |
889 | { | |
50f4caef VS |
890 | enum pipe pipe; |
891 | ||
892 | for_each_pipe(dev_priv, pipe) { | |
c137d660 VS |
893 | trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); |
894 | ||
50f4caef VS |
895 | I915_WRITE(VLV_DDL(pipe), |
896 | (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | | |
897 | (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | | |
898 | (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | | |
899 | (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); | |
900 | } | |
0018fda1 | 901 | |
6fe6a7ff VS |
902 | /* |
903 | * Zero the (unused) WM1 watermarks, and also clear all the | |
904 | * high order bits so that there are no out of bounds values | |
905 | * present in the registers during the reprogramming. | |
906 | */ | |
907 | I915_WRITE(DSPHOWM, 0); | |
908 | I915_WRITE(DSPHOWM1, 0); | |
909 | I915_WRITE(DSPFW4, 0); | |
910 | I915_WRITE(DSPFW5, 0); | |
911 | I915_WRITE(DSPFW6, 0); | |
912 | ||
ae80152d | 913 | I915_WRITE(DSPFW1, |
15665979 | 914 | FW_WM(wm->sr.plane, SR) | |
1b31389c VS |
915 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | |
916 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | | |
917 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); | |
ae80152d | 918 | I915_WRITE(DSPFW2, |
1b31389c VS |
919 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | |
920 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | | |
921 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); | |
ae80152d | 922 | I915_WRITE(DSPFW3, |
15665979 | 923 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
924 | |
925 | if (IS_CHERRYVIEW(dev_priv)) { | |
926 | I915_WRITE(DSPFW7_CHV, | |
1b31389c VS |
927 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
928 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 929 | I915_WRITE(DSPFW8_CHV, |
1b31389c VS |
930 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | |
931 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); | |
ae80152d | 932 | I915_WRITE(DSPFW9_CHV, |
1b31389c VS |
933 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | |
934 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); | |
ae80152d | 935 | I915_WRITE(DSPHOWM, |
15665979 | 936 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
937 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | |
938 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | | |
939 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | | |
940 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | | |
941 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
942 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
943 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
944 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
945 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
946 | } else { |
947 | I915_WRITE(DSPFW7, | |
1b31389c VS |
948 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
949 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 950 | I915_WRITE(DSPHOWM, |
15665979 | 951 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
952 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | |
953 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
954 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
955 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
956 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
957 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
958 | } |
959 | ||
960 | POSTING_READ(DSPFW1); | |
0018fda1 VS |
961 | } |
962 | ||
15665979 VS |
963 | #undef FW_WM_VLV |
964 | ||
262cd2e1 VS |
965 | /* latency must be in 0.1us units. */ |
966 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, | |
967 | unsigned int pipe_htotal, | |
968 | unsigned int horiz_pixels, | |
ac484963 | 969 | unsigned int cpp, |
262cd2e1 VS |
970 | unsigned int latency) |
971 | { | |
972 | unsigned int ret; | |
973 | ||
974 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); | |
ac484963 | 975 | ret = (ret + 1) * horiz_pixels * cpp; |
262cd2e1 VS |
976 | ret = DIV_ROUND_UP(ret, 64); |
977 | ||
978 | return ret; | |
979 | } | |
980 | ||
bb726519 | 981 | static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv) |
262cd2e1 | 982 | { |
262cd2e1 VS |
983 | /* all latencies in usec */ |
984 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; | |
985 | ||
58590c14 VS |
986 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
987 | ||
262cd2e1 VS |
988 | if (IS_CHERRYVIEW(dev_priv)) { |
989 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; | |
990 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; | |
58590c14 VS |
991 | |
992 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; | |
262cd2e1 VS |
993 | } |
994 | } | |
995 | ||
e339d67e VS |
996 | static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, |
997 | const struct intel_plane_state *plane_state, | |
262cd2e1 VS |
998 | int level) |
999 | { | |
e339d67e | 1000 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
262cd2e1 | 1001 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
e339d67e VS |
1002 | const struct drm_display_mode *adjusted_mode = |
1003 | &crtc_state->base.adjusted_mode; | |
ac484963 | 1004 | int clock, htotal, cpp, width, wm; |
262cd2e1 VS |
1005 | |
1006 | if (dev_priv->wm.pri_latency[level] == 0) | |
1007 | return USHRT_MAX; | |
1008 | ||
e339d67e | 1009 | if (!plane_state->base.visible) |
262cd2e1 VS |
1010 | return 0; |
1011 | ||
ef426c10 | 1012 | cpp = plane_state->base.fb->format->cpp[0]; |
e339d67e VS |
1013 | clock = adjusted_mode->crtc_clock; |
1014 | htotal = adjusted_mode->crtc_htotal; | |
1015 | width = crtc_state->pipe_src_w; | |
262cd2e1 VS |
1016 | if (WARN_ON(htotal == 0)) |
1017 | htotal = 1; | |
1018 | ||
1019 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { | |
1020 | /* | |
1021 | * FIXME the formula gives values that are | |
1022 | * too big for the cursor FIFO, and hence we | |
1023 | * would never be able to use cursors. For | |
1024 | * now just hardcode the watermark. | |
1025 | */ | |
1026 | wm = 63; | |
1027 | } else { | |
ac484963 | 1028 | wm = vlv_wm_method2(clock, htotal, width, cpp, |
262cd2e1 VS |
1029 | dev_priv->wm.pri_latency[level] * 10); |
1030 | } | |
1031 | ||
1032 | return min_t(int, wm, USHRT_MAX); | |
1033 | } | |
1034 | ||
1a10ae6b VS |
1035 | static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes) |
1036 | { | |
1037 | return (active_planes & (BIT(PLANE_SPRITE0) | | |
1038 | BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1); | |
1039 | } | |
1040 | ||
5012e604 | 1041 | static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) |
54f1b6e1 | 1042 | { |
855c79f5 | 1043 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
5012e604 VS |
1044 | const struct vlv_pipe_wm *raw = |
1045 | &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; | |
814e7f0b | 1046 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
5012e604 VS |
1047 | unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); |
1048 | int num_active_planes = hweight32(active_planes); | |
1049 | const int fifo_size = 511; | |
54f1b6e1 | 1050 | int fifo_extra, fifo_left = fifo_size; |
1a10ae6b | 1051 | int sprite0_fifo_extra = 0; |
5012e604 VS |
1052 | unsigned int total_rate; |
1053 | enum plane_id plane_id; | |
54f1b6e1 | 1054 | |
1a10ae6b VS |
1055 | /* |
1056 | * When enabling sprite0 after sprite1 has already been enabled | |
1057 | * we tend to get an underrun unless sprite0 already has some | |
1058 | * FIFO space allcoated. Hence we always allocate at least one | |
1059 | * cacheline for sprite0 whenever sprite1 is enabled. | |
1060 | * | |
1061 | * All other plane enable sequences appear immune to this problem. | |
1062 | */ | |
1063 | if (vlv_need_sprite0_fifo_workaround(active_planes)) | |
1064 | sprite0_fifo_extra = 1; | |
1065 | ||
5012e604 VS |
1066 | total_rate = raw->plane[PLANE_PRIMARY] + |
1067 | raw->plane[PLANE_SPRITE0] + | |
1a10ae6b VS |
1068 | raw->plane[PLANE_SPRITE1] + |
1069 | sprite0_fifo_extra; | |
54f1b6e1 | 1070 | |
5012e604 VS |
1071 | if (total_rate > fifo_size) |
1072 | return -EINVAL; | |
54f1b6e1 | 1073 | |
5012e604 VS |
1074 | if (total_rate == 0) |
1075 | total_rate = 1; | |
54f1b6e1 | 1076 | |
5012e604 | 1077 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1078 | unsigned int rate; |
1079 | ||
5012e604 VS |
1080 | if ((active_planes & BIT(plane_id)) == 0) { |
1081 | fifo_state->plane[plane_id] = 0; | |
54f1b6e1 VS |
1082 | continue; |
1083 | } | |
1084 | ||
5012e604 VS |
1085 | rate = raw->plane[plane_id]; |
1086 | fifo_state->plane[plane_id] = fifo_size * rate / total_rate; | |
1087 | fifo_left -= fifo_state->plane[plane_id]; | |
54f1b6e1 VS |
1088 | } |
1089 | ||
1a10ae6b VS |
1090 | fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra; |
1091 | fifo_left -= sprite0_fifo_extra; | |
1092 | ||
5012e604 VS |
1093 | fifo_state->plane[PLANE_CURSOR] = 63; |
1094 | ||
1095 | fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1); | |
54f1b6e1 VS |
1096 | |
1097 | /* spread the remainder evenly */ | |
5012e604 | 1098 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1099 | int plane_extra; |
1100 | ||
1101 | if (fifo_left == 0) | |
1102 | break; | |
1103 | ||
5012e604 | 1104 | if ((active_planes & BIT(plane_id)) == 0) |
54f1b6e1 VS |
1105 | continue; |
1106 | ||
1107 | plane_extra = min(fifo_extra, fifo_left); | |
5012e604 | 1108 | fifo_state->plane[plane_id] += plane_extra; |
54f1b6e1 VS |
1109 | fifo_left -= plane_extra; |
1110 | } | |
1111 | ||
5012e604 VS |
1112 | WARN_ON(active_planes != 0 && fifo_left != 0); |
1113 | ||
1114 | /* give it all to the first plane if none are active */ | |
1115 | if (active_planes == 0) { | |
1116 | WARN_ON(fifo_left != fifo_size); | |
1117 | fifo_state->plane[PLANE_PRIMARY] = fifo_left; | |
1118 | } | |
1119 | ||
1120 | return 0; | |
54f1b6e1 VS |
1121 | } |
1122 | ||
ff32c54e VS |
1123 | static int vlv_num_wm_levels(struct drm_i915_private *dev_priv) |
1124 | { | |
1125 | return dev_priv->wm.max_level + 1; | |
1126 | } | |
1127 | ||
1128 | /* mark all levels starting from 'level' as invalid */ | |
1129 | static void vlv_invalidate_wms(struct intel_crtc *crtc, | |
1130 | struct vlv_wm_state *wm_state, int level) | |
1131 | { | |
1132 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1133 | ||
1134 | for (; level < vlv_num_wm_levels(dev_priv); level++) { | |
1135 | enum plane_id plane_id; | |
1136 | ||
1137 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1138 | wm_state->wm[level].plane[plane_id] = USHRT_MAX; | |
1139 | ||
1140 | wm_state->sr[level].cursor = USHRT_MAX; | |
1141 | wm_state->sr[level].plane = USHRT_MAX; | |
1142 | } | |
1143 | } | |
1144 | ||
26cca0e5 VS |
1145 | static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) |
1146 | { | |
1147 | if (wm > fifo_size) | |
1148 | return USHRT_MAX; | |
1149 | else | |
1150 | return fifo_size - wm; | |
1151 | } | |
1152 | ||
ff32c54e VS |
1153 | /* |
1154 | * Starting from 'level' set all higher | |
1155 | * levels to 'value' in the "raw" watermarks. | |
1156 | */ | |
236c48e6 | 1157 | static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state, |
ff32c54e | 1158 | int level, enum plane_id plane_id, u16 value) |
262cd2e1 | 1159 | { |
ff32c54e VS |
1160 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
1161 | int num_levels = vlv_num_wm_levels(dev_priv); | |
236c48e6 | 1162 | bool dirty = false; |
262cd2e1 | 1163 | |
ff32c54e VS |
1164 | for (; level < num_levels; level++) { |
1165 | struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; | |
262cd2e1 | 1166 | |
236c48e6 | 1167 | dirty |= raw->plane[plane_id] != value; |
ff32c54e | 1168 | raw->plane[plane_id] = value; |
262cd2e1 | 1169 | } |
236c48e6 VS |
1170 | |
1171 | return dirty; | |
262cd2e1 VS |
1172 | } |
1173 | ||
236c48e6 | 1174 | static bool vlv_plane_wm_compute(struct intel_crtc_state *crtc_state, |
ff32c54e | 1175 | const struct intel_plane_state *plane_state) |
262cd2e1 | 1176 | { |
ff32c54e VS |
1177 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
1178 | enum plane_id plane_id = plane->id; | |
1179 | int num_levels = vlv_num_wm_levels(to_i915(plane->base.dev)); | |
262cd2e1 | 1180 | int level; |
236c48e6 | 1181 | bool dirty = false; |
262cd2e1 | 1182 | |
ff32c54e | 1183 | if (!plane_state->base.visible) { |
236c48e6 VS |
1184 | dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0); |
1185 | goto out; | |
ff32c54e | 1186 | } |
262cd2e1 | 1187 | |
ff32c54e VS |
1188 | for (level = 0; level < num_levels; level++) { |
1189 | struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; | |
1190 | int wm = vlv_compute_wm_level(crtc_state, plane_state, level); | |
1191 | int max_wm = plane_id == PLANE_CURSOR ? 63 : 511; | |
262cd2e1 | 1192 | |
ff32c54e VS |
1193 | if (wm > max_wm) |
1194 | break; | |
262cd2e1 | 1195 | |
236c48e6 | 1196 | dirty |= raw->plane[plane_id] != wm; |
ff32c54e VS |
1197 | raw->plane[plane_id] = wm; |
1198 | } | |
262cd2e1 | 1199 | |
ff32c54e | 1200 | /* mark all higher levels as invalid */ |
236c48e6 | 1201 | dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); |
262cd2e1 | 1202 | |
236c48e6 VS |
1203 | out: |
1204 | if (dirty) | |
1205 | DRM_DEBUG_KMS("%s wms: [0]=%d,[1]=%d,[2]=%d\n", | |
1206 | plane->base.name, | |
1207 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], | |
1208 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], | |
1209 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); | |
1210 | ||
1211 | return dirty; | |
ff32c54e | 1212 | } |
262cd2e1 | 1213 | |
ff32c54e VS |
1214 | static bool vlv_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, |
1215 | enum plane_id plane_id, int level) | |
1216 | { | |
1217 | const struct vlv_pipe_wm *raw = | |
1218 | &crtc_state->wm.vlv.raw[level]; | |
1219 | const struct vlv_fifo_state *fifo_state = | |
1220 | &crtc_state->wm.vlv.fifo_state; | |
262cd2e1 | 1221 | |
ff32c54e VS |
1222 | return raw->plane[plane_id] <= fifo_state->plane[plane_id]; |
1223 | } | |
262cd2e1 | 1224 | |
ff32c54e VS |
1225 | static bool vlv_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level) |
1226 | { | |
1227 | return vlv_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && | |
1228 | vlv_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && | |
1229 | vlv_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) && | |
1230 | vlv_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); | |
1231 | } | |
1232 | ||
1233 | static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) | |
1234 | { | |
1235 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1236 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1237 | struct intel_atomic_state *state = | |
1238 | to_intel_atomic_state(crtc_state->base.state); | |
1239 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
1240 | const struct vlv_fifo_state *fifo_state = | |
1241 | &crtc_state->wm.vlv.fifo_state; | |
1242 | int num_active_planes = hweight32(crtc_state->active_planes & | |
1243 | ~BIT(PLANE_CURSOR)); | |
236c48e6 | 1244 | bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); |
ff32c54e VS |
1245 | struct intel_plane_state *plane_state; |
1246 | struct intel_plane *plane; | |
1247 | enum plane_id plane_id; | |
1248 | int level, ret, i; | |
236c48e6 | 1249 | unsigned int dirty = 0; |
ff32c54e VS |
1250 | |
1251 | for_each_intel_plane_in_state(state, plane, plane_state, i) { | |
1252 | const struct intel_plane_state *old_plane_state = | |
1253 | to_intel_plane_state(plane->base.state); | |
1254 | ||
1255 | if (plane_state->base.crtc != &crtc->base && | |
1256 | old_plane_state->base.crtc != &crtc->base) | |
1257 | continue; | |
262cd2e1 | 1258 | |
236c48e6 VS |
1259 | if (vlv_plane_wm_compute(crtc_state, plane_state)) |
1260 | dirty |= BIT(plane->id); | |
1261 | } | |
1262 | ||
1263 | /* | |
1264 | * DSPARB registers may have been reset due to the | |
1265 | * power well being turned off. Make sure we restore | |
1266 | * them to a consistent state even if no primary/sprite | |
1267 | * planes are initially active. | |
1268 | */ | |
1269 | if (needs_modeset) | |
1270 | crtc_state->fifo_changed = true; | |
1271 | ||
1272 | if (!dirty) | |
1273 | return 0; | |
1274 | ||
1275 | /* cursor changes don't warrant a FIFO recompute */ | |
1276 | if (dirty & ~BIT(PLANE_CURSOR)) { | |
1277 | const struct intel_crtc_state *old_crtc_state = | |
1278 | to_intel_crtc_state(crtc->base.state); | |
1279 | const struct vlv_fifo_state *old_fifo_state = | |
1280 | &old_crtc_state->wm.vlv.fifo_state; | |
1281 | ||
1282 | ret = vlv_compute_fifo(crtc_state); | |
1283 | if (ret) | |
1284 | return ret; | |
1285 | ||
1286 | if (needs_modeset || | |
1287 | memcmp(old_fifo_state, fifo_state, | |
1288 | sizeof(*fifo_state)) != 0) | |
1289 | crtc_state->fifo_changed = true; | |
5012e604 | 1290 | } |
262cd2e1 | 1291 | |
ff32c54e VS |
1292 | /* initially allow all levels */ |
1293 | wm_state->num_levels = vlv_num_wm_levels(dev_priv); | |
1294 | /* | |
1295 | * Note that enabling cxsr with no primary/sprite planes | |
1296 | * enabled can wedge the pipe. Hence we only allow cxsr | |
1297 | * with exactly one enabled primary/sprite plane. | |
1298 | */ | |
5eeb798b | 1299 | wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; |
ff32c54e | 1300 | |
5012e604 | 1301 | for (level = 0; level < wm_state->num_levels; level++) { |
ff32c54e VS |
1302 | const struct vlv_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
1303 | const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; | |
5012e604 | 1304 | |
ff32c54e VS |
1305 | if (!vlv_crtc_wm_is_valid(crtc_state, level)) |
1306 | break; | |
5012e604 | 1307 | |
ff32c54e VS |
1308 | for_each_plane_id_on_crtc(crtc, plane_id) { |
1309 | wm_state->wm[level].plane[plane_id] = | |
1310 | vlv_invert_wm_value(raw->plane[plane_id], | |
1311 | fifo_state->plane[plane_id]); | |
1312 | } | |
1313 | ||
1314 | wm_state->sr[level].plane = | |
1315 | vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY], | |
5012e604 | 1316 | raw->plane[PLANE_SPRITE0], |
ff32c54e VS |
1317 | raw->plane[PLANE_SPRITE1]), |
1318 | sr_fifo_size); | |
262cd2e1 | 1319 | |
ff32c54e VS |
1320 | wm_state->sr[level].cursor = |
1321 | vlv_invert_wm_value(raw->plane[PLANE_CURSOR], | |
1322 | 63); | |
262cd2e1 VS |
1323 | } |
1324 | ||
ff32c54e VS |
1325 | if (level == 0) |
1326 | return -EINVAL; | |
1327 | ||
1328 | /* limit to only levels we can actually handle */ | |
1329 | wm_state->num_levels = level; | |
1330 | ||
1331 | /* invalidate the higher levels */ | |
1332 | vlv_invalidate_wms(crtc, wm_state, level); | |
1333 | ||
1334 | return 0; | |
262cd2e1 VS |
1335 | } |
1336 | ||
54f1b6e1 VS |
1337 | #define VLV_FIFO(plane, value) \ |
1338 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) | |
1339 | ||
ff32c54e VS |
1340 | static void vlv_atomic_update_fifo(struct intel_atomic_state *state, |
1341 | struct intel_crtc_state *crtc_state) | |
54f1b6e1 | 1342 | { |
814e7f0b | 1343 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 1344 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b VS |
1345 | const struct vlv_fifo_state *fifo_state = |
1346 | &crtc_state->wm.vlv.fifo_state; | |
f07d43d2 | 1347 | int sprite0_start, sprite1_start, fifo_size; |
54f1b6e1 | 1348 | |
236c48e6 VS |
1349 | if (!crtc_state->fifo_changed) |
1350 | return; | |
1351 | ||
f07d43d2 VS |
1352 | sprite0_start = fifo_state->plane[PLANE_PRIMARY]; |
1353 | sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start; | |
1354 | fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start; | |
54f1b6e1 | 1355 | |
f07d43d2 VS |
1356 | WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63); |
1357 | WARN_ON(fifo_size != 511); | |
54f1b6e1 | 1358 | |
c137d660 VS |
1359 | trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size); |
1360 | ||
44e921d4 VS |
1361 | /* |
1362 | * uncore.lock serves a double purpose here. It allows us to | |
1363 | * use the less expensive I915_{READ,WRITE}_FW() functions, and | |
1364 | * it protects the DSPARB registers from getting clobbered by | |
1365 | * parallel updates from multiple pipes. | |
1366 | * | |
1367 | * intel_pipe_update_start() has already disabled interrupts | |
1368 | * for us, so a plain spin_lock() is sufficient here. | |
1369 | */ | |
1370 | spin_lock(&dev_priv->uncore.lock); | |
467a14d9 | 1371 | |
54f1b6e1 VS |
1372 | switch (crtc->pipe) { |
1373 | uint32_t dsparb, dsparb2, dsparb3; | |
1374 | case PIPE_A: | |
44e921d4 VS |
1375 | dsparb = I915_READ_FW(DSPARB); |
1376 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1377 | |
1378 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | | |
1379 | VLV_FIFO(SPRITEB, 0xff)); | |
1380 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | | |
1381 | VLV_FIFO(SPRITEB, sprite1_start)); | |
1382 | ||
1383 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | | |
1384 | VLV_FIFO(SPRITEB_HI, 0x1)); | |
1385 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | | |
1386 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); | |
1387 | ||
44e921d4 VS |
1388 | I915_WRITE_FW(DSPARB, dsparb); |
1389 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1390 | break; |
1391 | case PIPE_B: | |
44e921d4 VS |
1392 | dsparb = I915_READ_FW(DSPARB); |
1393 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1394 | |
1395 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | | |
1396 | VLV_FIFO(SPRITED, 0xff)); | |
1397 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | | |
1398 | VLV_FIFO(SPRITED, sprite1_start)); | |
1399 | ||
1400 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | | |
1401 | VLV_FIFO(SPRITED_HI, 0xff)); | |
1402 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | | |
1403 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); | |
1404 | ||
44e921d4 VS |
1405 | I915_WRITE_FW(DSPARB, dsparb); |
1406 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1407 | break; |
1408 | case PIPE_C: | |
44e921d4 VS |
1409 | dsparb3 = I915_READ_FW(DSPARB3); |
1410 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1411 | |
1412 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | | |
1413 | VLV_FIFO(SPRITEF, 0xff)); | |
1414 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | | |
1415 | VLV_FIFO(SPRITEF, sprite1_start)); | |
1416 | ||
1417 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | | |
1418 | VLV_FIFO(SPRITEF_HI, 0xff)); | |
1419 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | | |
1420 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); | |
1421 | ||
44e921d4 VS |
1422 | I915_WRITE_FW(DSPARB3, dsparb3); |
1423 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1424 | break; |
1425 | default: | |
1426 | break; | |
1427 | } | |
467a14d9 | 1428 | |
44e921d4 | 1429 | POSTING_READ_FW(DSPARB); |
467a14d9 | 1430 | |
44e921d4 | 1431 | spin_unlock(&dev_priv->uncore.lock); |
54f1b6e1 VS |
1432 | } |
1433 | ||
1434 | #undef VLV_FIFO | |
1435 | ||
4841da51 VS |
1436 | static int vlv_compute_intermediate_wm(struct drm_device *dev, |
1437 | struct intel_crtc *crtc, | |
1438 | struct intel_crtc_state *crtc_state) | |
1439 | { | |
1440 | struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate; | |
1441 | const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal; | |
1442 | const struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
1443 | int level; | |
1444 | ||
1445 | intermediate->num_levels = min(optimal->num_levels, active->num_levels); | |
5eeb798b VS |
1446 | intermediate->cxsr = optimal->cxsr && active->cxsr && |
1447 | !crtc_state->disable_cxsr; | |
4841da51 VS |
1448 | |
1449 | for (level = 0; level < intermediate->num_levels; level++) { | |
1450 | enum plane_id plane_id; | |
1451 | ||
1452 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
1453 | intermediate->wm[level].plane[plane_id] = | |
1454 | min(optimal->wm[level].plane[plane_id], | |
1455 | active->wm[level].plane[plane_id]); | |
1456 | } | |
1457 | ||
1458 | intermediate->sr[level].plane = min(optimal->sr[level].plane, | |
1459 | active->sr[level].plane); | |
1460 | intermediate->sr[level].cursor = min(optimal->sr[level].cursor, | |
1461 | active->sr[level].cursor); | |
1462 | } | |
1463 | ||
1464 | vlv_invalidate_wms(crtc, intermediate, level); | |
1465 | ||
1466 | /* | |
1467 | * If our intermediate WM are identical to the final WM, then we can | |
1468 | * omit the post-vblank programming; only update if it's different. | |
1469 | */ | |
5eeb798b VS |
1470 | if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0) |
1471 | crtc_state->wm.need_postvbl_update = true; | |
4841da51 VS |
1472 | |
1473 | return 0; | |
1474 | } | |
1475 | ||
7c951c00 | 1476 | static void vlv_merge_wm(struct drm_i915_private *dev_priv, |
262cd2e1 VS |
1477 | struct vlv_wm_values *wm) |
1478 | { | |
1479 | struct intel_crtc *crtc; | |
1480 | int num_active_crtcs = 0; | |
1481 | ||
7c951c00 | 1482 | wm->level = dev_priv->wm.max_level; |
262cd2e1 VS |
1483 | wm->cxsr = true; |
1484 | ||
7c951c00 | 1485 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 1486 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
1487 | |
1488 | if (!crtc->active) | |
1489 | continue; | |
1490 | ||
1491 | if (!wm_state->cxsr) | |
1492 | wm->cxsr = false; | |
1493 | ||
1494 | num_active_crtcs++; | |
1495 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); | |
1496 | } | |
1497 | ||
1498 | if (num_active_crtcs != 1) | |
1499 | wm->cxsr = false; | |
1500 | ||
6f9c784b VS |
1501 | if (num_active_crtcs > 1) |
1502 | wm->level = VLV_WM_LEVEL_PM2; | |
1503 | ||
7c951c00 | 1504 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 1505 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
1506 | enum pipe pipe = crtc->pipe; |
1507 | ||
262cd2e1 | 1508 | wm->pipe[pipe] = wm_state->wm[wm->level]; |
ff32c54e | 1509 | if (crtc->active && wm->cxsr) |
262cd2e1 VS |
1510 | wm->sr = wm_state->sr[wm->level]; |
1511 | ||
1b31389c VS |
1512 | wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; |
1513 | wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; | |
1514 | wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; | |
1515 | wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; | |
262cd2e1 VS |
1516 | } |
1517 | } | |
1518 | ||
fa292a4b VS |
1519 | static bool is_disabling(int old, int new, int threshold) |
1520 | { | |
1521 | return old >= threshold && new < threshold; | |
1522 | } | |
1523 | ||
1524 | static bool is_enabling(int old, int new, int threshold) | |
1525 | { | |
1526 | return old < threshold && new >= threshold; | |
1527 | } | |
1528 | ||
ff32c54e | 1529 | static void vlv_program_watermarks(struct drm_i915_private *dev_priv) |
262cd2e1 | 1530 | { |
fa292a4b VS |
1531 | struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; |
1532 | struct vlv_wm_values new_wm = {}; | |
262cd2e1 | 1533 | |
fa292a4b | 1534 | vlv_merge_wm(dev_priv, &new_wm); |
262cd2e1 | 1535 | |
ff32c54e | 1536 | if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) |
262cd2e1 VS |
1537 | return; |
1538 | ||
fa292a4b | 1539 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
1540 | chv_set_memory_dvfs(dev_priv, false); |
1541 | ||
fa292a4b | 1542 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
1543 | chv_set_memory_pm5(dev_priv, false); |
1544 | ||
fa292a4b | 1545 | if (is_disabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 1546 | _intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 1547 | |
fa292a4b | 1548 | vlv_write_wm_values(dev_priv, &new_wm); |
262cd2e1 | 1549 | |
fa292a4b | 1550 | if (is_enabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 1551 | _intel_set_memory_cxsr(dev_priv, true); |
262cd2e1 | 1552 | |
fa292a4b | 1553 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
1554 | chv_set_memory_pm5(dev_priv, true); |
1555 | ||
fa292a4b | 1556 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
1557 | chv_set_memory_dvfs(dev_priv, true); |
1558 | ||
fa292a4b | 1559 | *old_wm = new_wm; |
3c2777fd VS |
1560 | } |
1561 | ||
ff32c54e VS |
1562 | static void vlv_initial_watermarks(struct intel_atomic_state *state, |
1563 | struct intel_crtc_state *crtc_state) | |
1564 | { | |
1565 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1566 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1567 | ||
1568 | mutex_lock(&dev_priv->wm.wm_mutex); | |
4841da51 VS |
1569 | crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; |
1570 | vlv_program_watermarks(dev_priv); | |
1571 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1572 | } | |
1573 | ||
1574 | static void vlv_optimize_watermarks(struct intel_atomic_state *state, | |
1575 | struct intel_crtc_state *crtc_state) | |
1576 | { | |
1577 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1578 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
1579 | ||
1580 | if (!crtc_state->wm.need_postvbl_update) | |
1581 | return; | |
1582 | ||
1583 | mutex_lock(&dev_priv->wm.wm_mutex); | |
1584 | intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
ff32c54e VS |
1585 | vlv_program_watermarks(dev_priv); |
1586 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1587 | } | |
1588 | ||
ae80152d VS |
1589 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1590 | ||
432081bc | 1591 | static void g4x_update_wm(struct intel_crtc *crtc) |
b445e3b0 | 1592 | { |
b91eb5cc | 1593 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b445e3b0 | 1594 | static const int sr_latency_ns = 12000; |
b445e3b0 ED |
1595 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
1596 | int plane_sr, cursor_sr; | |
1597 | unsigned int enabled = 0; | |
9858425c | 1598 | bool cxsr_enabled; |
b445e3b0 | 1599 | |
f0ce2310 | 1600 | if (g4x_compute_wm0(dev_priv, PIPE_A, |
5aef6003 CW |
1601 | &g4x_wm_info, pessimal_latency_ns, |
1602 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1603 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1604 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1605 | |
f0ce2310 | 1606 | if (g4x_compute_wm0(dev_priv, PIPE_B, |
5aef6003 CW |
1607 | &g4x_wm_info, pessimal_latency_ns, |
1608 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1609 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1610 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1611 | |
b445e3b0 | 1612 | if (single_plane_enabled(enabled) && |
f0ce2310 | 1613 | g4x_compute_srwm(dev_priv, ffs(enabled) - 1, |
b445e3b0 ED |
1614 | sr_latency_ns, |
1615 | &g4x_wm_info, | |
1616 | &g4x_cursor_wm_info, | |
52bd02d8 | 1617 | &plane_sr, &cursor_sr)) { |
9858425c | 1618 | cxsr_enabled = true; |
52bd02d8 | 1619 | } else { |
9858425c | 1620 | cxsr_enabled = false; |
5209b1f4 | 1621 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1622 | plane_sr = cursor_sr = 0; |
1623 | } | |
b445e3b0 | 1624 | |
a5043453 VS |
1625 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1626 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1627 | planea_wm, cursora_wm, |
1628 | planeb_wm, cursorb_wm, | |
1629 | plane_sr, cursor_sr); | |
1630 | ||
1631 | I915_WRITE(DSPFW1, | |
f4998963 VS |
1632 | FW_WM(plane_sr, SR) | |
1633 | FW_WM(cursorb_wm, CURSORB) | | |
1634 | FW_WM(planeb_wm, PLANEB) | | |
1635 | FW_WM(planea_wm, PLANEA)); | |
b445e3b0 | 1636 | I915_WRITE(DSPFW2, |
8c919b28 | 1637 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
f4998963 | 1638 | FW_WM(cursora_wm, CURSORA)); |
b445e3b0 ED |
1639 | /* HPLL off in SR has some issues on G4x... disable it */ |
1640 | I915_WRITE(DSPFW3, | |
8c919b28 | 1641 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
f4998963 | 1642 | FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1643 | |
1644 | if (cxsr_enabled) | |
1645 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1646 | } |
1647 | ||
432081bc | 1648 | static void i965_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 1649 | { |
ffc7a76b | 1650 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 1651 | struct intel_crtc *crtc; |
b445e3b0 ED |
1652 | int srwm = 1; |
1653 | int cursor_sr = 16; | |
9858425c | 1654 | bool cxsr_enabled; |
b445e3b0 ED |
1655 | |
1656 | /* Calc sr entries for one plane configs */ | |
ffc7a76b | 1657 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
1658 | if (crtc) { |
1659 | /* self-refresh has much higher latency */ | |
1660 | static const int sr_latency_ns = 12000; | |
efc2611e VS |
1661 | const struct drm_display_mode *adjusted_mode = |
1662 | &crtc->config->base.adjusted_mode; | |
1663 | const struct drm_framebuffer *fb = | |
1664 | crtc->base.primary->state->fb; | |
241bfc38 | 1665 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1666 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e | 1667 | int hdisplay = crtc->config->pipe_src_w; |
353c8598 | 1668 | int cpp = fb->format->cpp[0]; |
b445e3b0 ED |
1669 | unsigned long line_time_us; |
1670 | int entries; | |
1671 | ||
922044c9 | 1672 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1673 | |
1674 | /* Use ns/us then divide to preserve precision */ | |
1675 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
ac484963 | 1676 | cpp * hdisplay; |
b445e3b0 ED |
1677 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
1678 | srwm = I965_FIFO_SIZE - entries; | |
1679 | if (srwm < 0) | |
1680 | srwm = 1; | |
1681 | srwm &= 0x1ff; | |
1682 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1683 | entries, srwm); | |
1684 | ||
1685 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
efc2611e | 1686 | cpp * crtc->base.cursor->state->crtc_w; |
b445e3b0 ED |
1687 | entries = DIV_ROUND_UP(entries, |
1688 | i965_cursor_wm_info.cacheline_size); | |
1689 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1690 | (entries + i965_cursor_wm_info.guard_size); | |
1691 | ||
1692 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1693 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1694 | ||
1695 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1696 | "cursor %d\n", srwm, cursor_sr); | |
1697 | ||
9858425c | 1698 | cxsr_enabled = true; |
b445e3b0 | 1699 | } else { |
9858425c | 1700 | cxsr_enabled = false; |
b445e3b0 | 1701 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1702 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1703 | } |
1704 | ||
1705 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1706 | srwm); | |
1707 | ||
1708 | /* 965 has limitations... */ | |
f4998963 VS |
1709 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
1710 | FW_WM(8, CURSORB) | | |
1711 | FW_WM(8, PLANEB) | | |
1712 | FW_WM(8, PLANEA)); | |
1713 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | | |
1714 | FW_WM(8, PLANEC_OLD)); | |
b445e3b0 | 1715 | /* update cursor SR watermark */ |
f4998963 | 1716 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
1717 | |
1718 | if (cxsr_enabled) | |
1719 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1720 | } |
1721 | ||
f4998963 VS |
1722 | #undef FW_WM |
1723 | ||
432081bc | 1724 | static void i9xx_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 1725 | { |
ffc7a76b | 1726 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
b445e3b0 ED |
1727 | const struct intel_watermark_params *wm_info; |
1728 | uint32_t fwater_lo; | |
1729 | uint32_t fwater_hi; | |
1730 | int cwm, srwm = 1; | |
1731 | int fifo_size; | |
1732 | int planea_wm, planeb_wm; | |
efc2611e | 1733 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 1734 | |
a9097be4 | 1735 | if (IS_I945GM(dev_priv)) |
b445e3b0 | 1736 | wm_info = &i945_wm_info; |
5db94019 | 1737 | else if (!IS_GEN2(dev_priv)) |
b445e3b0 ED |
1738 | wm_info = &i915_wm_info; |
1739 | else | |
9d539105 | 1740 | wm_info = &i830_a_wm_info; |
b445e3b0 | 1741 | |
ef0f5e93 | 1742 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0); |
b91eb5cc | 1743 | crtc = intel_get_crtc_for_plane(dev_priv, 0); |
efc2611e VS |
1744 | if (intel_crtc_active(crtc)) { |
1745 | const struct drm_display_mode *adjusted_mode = | |
1746 | &crtc->config->base.adjusted_mode; | |
1747 | const struct drm_framebuffer *fb = | |
1748 | crtc->base.primary->state->fb; | |
1749 | int cpp; | |
1750 | ||
5db94019 | 1751 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 1752 | cpp = 4; |
efc2611e | 1753 | else |
353c8598 | 1754 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 1755 | |
241bfc38 | 1756 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1757 | wm_info, fifo_size, cpp, |
5aef6003 | 1758 | pessimal_latency_ns); |
b445e3b0 | 1759 | enabled = crtc; |
9d539105 | 1760 | } else { |
b445e3b0 | 1761 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1762 | if (planea_wm > (long)wm_info->max_wm) |
1763 | planea_wm = wm_info->max_wm; | |
1764 | } | |
1765 | ||
5db94019 | 1766 | if (IS_GEN2(dev_priv)) |
9d539105 | 1767 | wm_info = &i830_bc_wm_info; |
b445e3b0 | 1768 | |
ef0f5e93 | 1769 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1); |
b91eb5cc | 1770 | crtc = intel_get_crtc_for_plane(dev_priv, 1); |
efc2611e VS |
1771 | if (intel_crtc_active(crtc)) { |
1772 | const struct drm_display_mode *adjusted_mode = | |
1773 | &crtc->config->base.adjusted_mode; | |
1774 | const struct drm_framebuffer *fb = | |
1775 | crtc->base.primary->state->fb; | |
1776 | int cpp; | |
1777 | ||
5db94019 | 1778 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 1779 | cpp = 4; |
efc2611e | 1780 | else |
353c8598 | 1781 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 1782 | |
241bfc38 | 1783 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1784 | wm_info, fifo_size, cpp, |
5aef6003 | 1785 | pessimal_latency_ns); |
b445e3b0 ED |
1786 | if (enabled == NULL) |
1787 | enabled = crtc; | |
1788 | else | |
1789 | enabled = NULL; | |
9d539105 | 1790 | } else { |
b445e3b0 | 1791 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1792 | if (planeb_wm > (long)wm_info->max_wm) |
1793 | planeb_wm = wm_info->max_wm; | |
1794 | } | |
b445e3b0 ED |
1795 | |
1796 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1797 | ||
50a0bc90 | 1798 | if (IS_I915GM(dev_priv) && enabled) { |
2ff8fde1 | 1799 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1800 | |
efc2611e | 1801 | obj = intel_fb_obj(enabled->base.primary->state->fb); |
2ab1bc9d DV |
1802 | |
1803 | /* self-refresh seems busted with untiled */ | |
3e510a8e | 1804 | if (!i915_gem_object_is_tiled(obj)) |
2ab1bc9d DV |
1805 | enabled = NULL; |
1806 | } | |
1807 | ||
b445e3b0 ED |
1808 | /* |
1809 | * Overlay gets an aggressive default since video jitter is bad. | |
1810 | */ | |
1811 | cwm = 2; | |
1812 | ||
1813 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1814 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1815 | |
1816 | /* Calc sr entries for one plane configs */ | |
03427fcb | 1817 | if (HAS_FW_BLC(dev_priv) && enabled) { |
b445e3b0 ED |
1818 | /* self-refresh has much higher latency */ |
1819 | static const int sr_latency_ns = 6000; | |
efc2611e VS |
1820 | const struct drm_display_mode *adjusted_mode = |
1821 | &enabled->config->base.adjusted_mode; | |
1822 | const struct drm_framebuffer *fb = | |
1823 | enabled->base.primary->state->fb; | |
241bfc38 | 1824 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1825 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e VS |
1826 | int hdisplay = enabled->config->pipe_src_w; |
1827 | int cpp; | |
b445e3b0 ED |
1828 | unsigned long line_time_us; |
1829 | int entries; | |
1830 | ||
50a0bc90 | 1831 | if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) |
2d1b5056 | 1832 | cpp = 4; |
efc2611e | 1833 | else |
353c8598 | 1834 | cpp = fb->format->cpp[0]; |
2d1b5056 | 1835 | |
922044c9 | 1836 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1837 | |
1838 | /* Use ns/us then divide to preserve precision */ | |
1839 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
ac484963 | 1840 | cpp * hdisplay; |
b445e3b0 ED |
1841 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
1842 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1843 | srwm = wm_info->fifo_size - entries; | |
1844 | if (srwm < 0) | |
1845 | srwm = 1; | |
1846 | ||
50a0bc90 | 1847 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
b445e3b0 ED |
1848 | I915_WRITE(FW_BLC_SELF, |
1849 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
acb91359 | 1850 | else |
b445e3b0 ED |
1851 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
1852 | } | |
1853 | ||
1854 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1855 | planea_wm, planeb_wm, cwm, srwm); | |
1856 | ||
1857 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1858 | fwater_hi = (cwm & 0x1f); | |
1859 | ||
1860 | /* Set request length to 8 cachelines per fetch */ | |
1861 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1862 | fwater_hi = fwater_hi | (1 << 8); | |
1863 | ||
1864 | I915_WRITE(FW_BLC, fwater_lo); | |
1865 | I915_WRITE(FW_BLC2, fwater_hi); | |
1866 | ||
5209b1f4 ID |
1867 | if (enabled) |
1868 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1869 | } |
1870 | ||
432081bc | 1871 | static void i845_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 1872 | { |
ffc7a76b | 1873 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 1874 | struct intel_crtc *crtc; |
241bfc38 | 1875 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1876 | uint32_t fwater_lo; |
1877 | int planea_wm; | |
1878 | ||
ffc7a76b | 1879 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
1880 | if (crtc == NULL) |
1881 | return; | |
1882 | ||
efc2611e | 1883 | adjusted_mode = &crtc->config->base.adjusted_mode; |
241bfc38 | 1884 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 1885 | &i845_wm_info, |
ef0f5e93 | 1886 | dev_priv->display.get_fifo_size(dev_priv, 0), |
5aef6003 | 1887 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1888 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1889 | fwater_lo |= (3<<8) | planea_wm; | |
1890 | ||
1891 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1892 | ||
1893 | I915_WRITE(FW_BLC, fwater_lo); | |
1894 | } | |
1895 | ||
37126462 | 1896 | /* latency must be in 0.1us units. */ |
ac484963 | 1897 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) |
801bcfff PZ |
1898 | { |
1899 | uint64_t ret; | |
1900 | ||
3312ba65 VS |
1901 | if (WARN(latency == 0, "Latency value missing\n")) |
1902 | return UINT_MAX; | |
1903 | ||
ac484963 | 1904 | ret = (uint64_t) pixel_rate * cpp * latency; |
801bcfff PZ |
1905 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
1906 | ||
1907 | return ret; | |
1908 | } | |
1909 | ||
37126462 | 1910 | /* latency must be in 0.1us units. */ |
23297044 | 1911 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
ac484963 | 1912 | uint32_t horiz_pixels, uint8_t cpp, |
801bcfff PZ |
1913 | uint32_t latency) |
1914 | { | |
1915 | uint32_t ret; | |
1916 | ||
3312ba65 VS |
1917 | if (WARN(latency == 0, "Latency value missing\n")) |
1918 | return UINT_MAX; | |
15126882 MR |
1919 | if (WARN_ON(!pipe_htotal)) |
1920 | return UINT_MAX; | |
3312ba65 | 1921 | |
801bcfff | 1922 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
ac484963 | 1923 | ret = (ret + 1) * horiz_pixels * cpp; |
801bcfff PZ |
1924 | ret = DIV_ROUND_UP(ret, 64) + 2; |
1925 | return ret; | |
1926 | } | |
1927 | ||
23297044 | 1928 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
ac484963 | 1929 | uint8_t cpp) |
cca32e9a | 1930 | { |
15126882 MR |
1931 | /* |
1932 | * Neither of these should be possible since this function shouldn't be | |
1933 | * called if the CRTC is off or the plane is invisible. But let's be | |
1934 | * extra paranoid to avoid a potential divide-by-zero if we screw up | |
1935 | * elsewhere in the driver. | |
1936 | */ | |
ac484963 | 1937 | if (WARN_ON(!cpp)) |
15126882 MR |
1938 | return 0; |
1939 | if (WARN_ON(!horiz_pixels)) | |
1940 | return 0; | |
1941 | ||
ac484963 | 1942 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2; |
cca32e9a PZ |
1943 | } |
1944 | ||
820c1980 | 1945 | struct ilk_wm_maximums { |
cca32e9a PZ |
1946 | uint16_t pri; |
1947 | uint16_t spr; | |
1948 | uint16_t cur; | |
1949 | uint16_t fbc; | |
1950 | }; | |
1951 | ||
37126462 VS |
1952 | /* |
1953 | * For both WM_PIPE and WM_LP. | |
1954 | * mem_value must be in 0.1us units. | |
1955 | */ | |
7221fc33 | 1956 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1957 | const struct intel_plane_state *pstate, |
cca32e9a PZ |
1958 | uint32_t mem_value, |
1959 | bool is_lp) | |
801bcfff | 1960 | { |
cca32e9a | 1961 | uint32_t method1, method2; |
8305494e | 1962 | int cpp; |
cca32e9a | 1963 | |
936e71e3 | 1964 | if (!cstate->base.active || !pstate->base.visible) |
801bcfff PZ |
1965 | return 0; |
1966 | ||
353c8598 | 1967 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 1968 | |
a7d1b3f4 | 1969 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
cca32e9a PZ |
1970 | |
1971 | if (!is_lp) | |
1972 | return method1; | |
1973 | ||
a7d1b3f4 | 1974 | method2 = ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 1975 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 1976 | drm_rect_width(&pstate->base.dst), |
ac484963 | 1977 | cpp, mem_value); |
cca32e9a PZ |
1978 | |
1979 | return min(method1, method2); | |
801bcfff PZ |
1980 | } |
1981 | ||
37126462 VS |
1982 | /* |
1983 | * For both WM_PIPE and WM_LP. | |
1984 | * mem_value must be in 0.1us units. | |
1985 | */ | |
7221fc33 | 1986 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
43d59eda | 1987 | const struct intel_plane_state *pstate, |
801bcfff PZ |
1988 | uint32_t mem_value) |
1989 | { | |
1990 | uint32_t method1, method2; | |
8305494e | 1991 | int cpp; |
801bcfff | 1992 | |
936e71e3 | 1993 | if (!cstate->base.active || !pstate->base.visible) |
801bcfff PZ |
1994 | return 0; |
1995 | ||
353c8598 | 1996 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 1997 | |
a7d1b3f4 VS |
1998 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
1999 | method2 = ilk_wm_method2(cstate->pixel_rate, | |
7221fc33 | 2000 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 2001 | drm_rect_width(&pstate->base.dst), |
ac484963 | 2002 | cpp, mem_value); |
801bcfff PZ |
2003 | return min(method1, method2); |
2004 | } | |
2005 | ||
37126462 VS |
2006 | /* |
2007 | * For both WM_PIPE and WM_LP. | |
2008 | * mem_value must be in 0.1us units. | |
2009 | */ | |
7221fc33 | 2010 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2011 | const struct intel_plane_state *pstate, |
801bcfff PZ |
2012 | uint32_t mem_value) |
2013 | { | |
a5509abd VS |
2014 | int cpp; |
2015 | ||
b2435692 | 2016 | /* |
a5509abd VS |
2017 | * Treat cursor with fb as always visible since cursor updates |
2018 | * can happen faster than the vrefresh rate, and the current | |
2019 | * watermark code doesn't handle that correctly. Cursor updates | |
2020 | * which set/clear the fb or change the cursor size are going | |
2021 | * to get throttled by intel_legacy_cursor_update() to work | |
2022 | * around this problem with the watermark code. | |
b2435692 | 2023 | */ |
a5509abd | 2024 | if (!cstate->base.active || !pstate->base.fb) |
801bcfff PZ |
2025 | return 0; |
2026 | ||
a5509abd VS |
2027 | cpp = pstate->base.fb->format->cpp[0]; |
2028 | ||
a7d1b3f4 | 2029 | return ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 2030 | cstate->base.adjusted_mode.crtc_htotal, |
a5509abd | 2031 | pstate->base.crtc_w, cpp, mem_value); |
801bcfff PZ |
2032 | } |
2033 | ||
cca32e9a | 2034 | /* Only for WM_LP. */ |
7221fc33 | 2035 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2036 | const struct intel_plane_state *pstate, |
1fda9882 | 2037 | uint32_t pri_val) |
cca32e9a | 2038 | { |
8305494e | 2039 | int cpp; |
43d59eda | 2040 | |
936e71e3 | 2041 | if (!cstate->base.active || !pstate->base.visible) |
cca32e9a PZ |
2042 | return 0; |
2043 | ||
353c8598 | 2044 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2045 | |
936e71e3 | 2046 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp); |
cca32e9a PZ |
2047 | } |
2048 | ||
175fded1 TU |
2049 | static unsigned int |
2050 | ilk_display_fifo_size(const struct drm_i915_private *dev_priv) | |
158ae64f | 2051 | { |
175fded1 | 2052 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 | 2053 | return 3072; |
175fded1 | 2054 | else if (INTEL_GEN(dev_priv) >= 7) |
158ae64f VS |
2055 | return 768; |
2056 | else | |
2057 | return 512; | |
2058 | } | |
2059 | ||
175fded1 TU |
2060 | static unsigned int |
2061 | ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, | |
2062 | int level, bool is_sprite) | |
4e975081 | 2063 | { |
175fded1 | 2064 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2065 | /* BDW primary/sprite plane watermarks */ |
2066 | return level == 0 ? 255 : 2047; | |
175fded1 | 2067 | else if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2068 | /* IVB/HSW primary/sprite plane watermarks */ |
2069 | return level == 0 ? 127 : 1023; | |
2070 | else if (!is_sprite) | |
2071 | /* ILK/SNB primary plane watermarks */ | |
2072 | return level == 0 ? 127 : 511; | |
2073 | else | |
2074 | /* ILK/SNB sprite plane watermarks */ | |
2075 | return level == 0 ? 63 : 255; | |
2076 | } | |
2077 | ||
175fded1 TU |
2078 | static unsigned int |
2079 | ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) | |
4e975081 | 2080 | { |
175fded1 | 2081 | if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2082 | return level == 0 ? 63 : 255; |
2083 | else | |
2084 | return level == 0 ? 31 : 63; | |
2085 | } | |
2086 | ||
175fded1 | 2087 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) |
4e975081 | 2088 | { |
175fded1 | 2089 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2090 | return 31; |
2091 | else | |
2092 | return 15; | |
2093 | } | |
2094 | ||
158ae64f VS |
2095 | /* Calculate the maximum primary/sprite plane watermark */ |
2096 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
2097 | int level, | |
240264f4 | 2098 | const struct intel_wm_config *config, |
158ae64f VS |
2099 | enum intel_ddb_partitioning ddb_partitioning, |
2100 | bool is_sprite) | |
2101 | { | |
175fded1 TU |
2102 | struct drm_i915_private *dev_priv = to_i915(dev); |
2103 | unsigned int fifo_size = ilk_display_fifo_size(dev_priv); | |
158ae64f VS |
2104 | |
2105 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 2106 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
2107 | return 0; |
2108 | ||
2109 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 2110 | if (level == 0 || config->num_pipes_active > 1) { |
175fded1 | 2111 | fifo_size /= INTEL_INFO(dev_priv)->num_pipes; |
158ae64f VS |
2112 | |
2113 | /* | |
2114 | * For some reason the non self refresh | |
2115 | * FIFO size is only half of the self | |
2116 | * refresh FIFO size on ILK/SNB. | |
2117 | */ | |
175fded1 | 2118 | if (INTEL_GEN(dev_priv) <= 6) |
158ae64f VS |
2119 | fifo_size /= 2; |
2120 | } | |
2121 | ||
240264f4 | 2122 | if (config->sprites_enabled) { |
158ae64f VS |
2123 | /* level 0 is always calculated with 1:1 split */ |
2124 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
2125 | if (is_sprite) | |
2126 | fifo_size *= 5; | |
2127 | fifo_size /= 6; | |
2128 | } else { | |
2129 | fifo_size /= 2; | |
2130 | } | |
2131 | } | |
2132 | ||
2133 | /* clamp to max that the registers can hold */ | |
175fded1 | 2134 | return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); |
158ae64f VS |
2135 | } |
2136 | ||
2137 | /* Calculate the maximum cursor plane watermark */ | |
2138 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
2139 | int level, |
2140 | const struct intel_wm_config *config) | |
158ae64f VS |
2141 | { |
2142 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 2143 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
2144 | return 64; |
2145 | ||
2146 | /* otherwise just report max that registers can hold */ | |
175fded1 | 2147 | return ilk_cursor_wm_reg_max(to_i915(dev), level); |
158ae64f VS |
2148 | } |
2149 | ||
d34ff9c6 | 2150 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
2151 | int level, |
2152 | const struct intel_wm_config *config, | |
2153 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 2154 | struct ilk_wm_maximums *max) |
158ae64f | 2155 | { |
240264f4 VS |
2156 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
2157 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
2158 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
175fded1 | 2159 | max->fbc = ilk_fbc_wm_reg_max(to_i915(dev)); |
158ae64f VS |
2160 | } |
2161 | ||
175fded1 | 2162 | static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, |
a3cb4048 VS |
2163 | int level, |
2164 | struct ilk_wm_maximums *max) | |
2165 | { | |
175fded1 TU |
2166 | max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); |
2167 | max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); | |
2168 | max->cur = ilk_cursor_wm_reg_max(dev_priv, level); | |
2169 | max->fbc = ilk_fbc_wm_reg_max(dev_priv); | |
a3cb4048 VS |
2170 | } |
2171 | ||
d9395655 | 2172 | static bool ilk_validate_wm_level(int level, |
820c1980 | 2173 | const struct ilk_wm_maximums *max, |
d9395655 | 2174 | struct intel_wm_level *result) |
a9786a11 VS |
2175 | { |
2176 | bool ret; | |
2177 | ||
2178 | /* already determined to be invalid? */ | |
2179 | if (!result->enable) | |
2180 | return false; | |
2181 | ||
2182 | result->enable = result->pri_val <= max->pri && | |
2183 | result->spr_val <= max->spr && | |
2184 | result->cur_val <= max->cur; | |
2185 | ||
2186 | ret = result->enable; | |
2187 | ||
2188 | /* | |
2189 | * HACK until we can pre-compute everything, | |
2190 | * and thus fail gracefully if LP0 watermarks | |
2191 | * are exceeded... | |
2192 | */ | |
2193 | if (level == 0 && !result->enable) { | |
2194 | if (result->pri_val > max->pri) | |
2195 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
2196 | level, result->pri_val, max->pri); | |
2197 | if (result->spr_val > max->spr) | |
2198 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
2199 | level, result->spr_val, max->spr); | |
2200 | if (result->cur_val > max->cur) | |
2201 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
2202 | level, result->cur_val, max->cur); | |
2203 | ||
2204 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
2205 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
2206 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
2207 | result->enable = true; | |
2208 | } | |
2209 | ||
a9786a11 VS |
2210 | return ret; |
2211 | } | |
2212 | ||
d34ff9c6 | 2213 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
43d59eda | 2214 | const struct intel_crtc *intel_crtc, |
6f5ddd17 | 2215 | int level, |
7221fc33 | 2216 | struct intel_crtc_state *cstate, |
86c8bbbe MR |
2217 | struct intel_plane_state *pristate, |
2218 | struct intel_plane_state *sprstate, | |
2219 | struct intel_plane_state *curstate, | |
1fd527cc | 2220 | struct intel_wm_level *result) |
6f5ddd17 VS |
2221 | { |
2222 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
2223 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
2224 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
2225 | ||
2226 | /* WM1+ latency values stored in 0.5us units */ | |
2227 | if (level > 0) { | |
2228 | pri_latency *= 5; | |
2229 | spr_latency *= 5; | |
2230 | cur_latency *= 5; | |
2231 | } | |
2232 | ||
e3bddded ML |
2233 | if (pristate) { |
2234 | result->pri_val = ilk_compute_pri_wm(cstate, pristate, | |
2235 | pri_latency, level); | |
2236 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); | |
2237 | } | |
2238 | ||
2239 | if (sprstate) | |
2240 | result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency); | |
2241 | ||
2242 | if (curstate) | |
2243 | result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency); | |
2244 | ||
6f5ddd17 VS |
2245 | result->enable = true; |
2246 | } | |
2247 | ||
801bcfff | 2248 | static uint32_t |
532f7a7f | 2249 | hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) |
1f8eeabf | 2250 | { |
532f7a7f VS |
2251 | const struct intel_atomic_state *intel_state = |
2252 | to_intel_atomic_state(cstate->base.state); | |
ee91a159 MR |
2253 | const struct drm_display_mode *adjusted_mode = |
2254 | &cstate->base.adjusted_mode; | |
85a02deb | 2255 | u32 linetime, ips_linetime; |
1f8eeabf | 2256 | |
ee91a159 MR |
2257 | if (!cstate->base.active) |
2258 | return 0; | |
2259 | if (WARN_ON(adjusted_mode->crtc_clock == 0)) | |
2260 | return 0; | |
bb0f4aab | 2261 | if (WARN_ON(intel_state->cdclk.logical.cdclk == 0)) |
801bcfff | 2262 | return 0; |
1011d8c4 | 2263 | |
1f8eeabf ED |
2264 | /* The WM are computed with base on how long it takes to fill a single |
2265 | * row at the given clock rate, multiplied by 8. | |
2266 | * */ | |
124abe07 VS |
2267 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2268 | adjusted_mode->crtc_clock); | |
2269 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, | |
bb0f4aab | 2270 | intel_state->cdclk.logical.cdclk); |
1f8eeabf | 2271 | |
801bcfff PZ |
2272 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2273 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2274 | } |
2275 | ||
bb726519 VS |
2276 | static void intel_read_wm_latency(struct drm_i915_private *dev_priv, |
2277 | uint16_t wm[8]) | |
12b134df | 2278 | { |
5db94019 | 2279 | if (IS_GEN9(dev_priv)) { |
2af30a5c | 2280 | uint32_t val; |
4f947386 | 2281 | int ret, i; |
5db94019 | 2282 | int level, max_level = ilk_wm_max_level(dev_priv); |
2af30a5c PB |
2283 | |
2284 | /* read the first set of memory latencies[0:3] */ | |
2285 | val = 0; /* data0 to be programmed to 0 for first set */ | |
2286 | mutex_lock(&dev_priv->rps.hw_lock); | |
2287 | ret = sandybridge_pcode_read(dev_priv, | |
2288 | GEN9_PCODE_READ_MEM_LATENCY, | |
2289 | &val); | |
2290 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2291 | ||
2292 | if (ret) { | |
2293 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2294 | return; | |
2295 | } | |
2296 | ||
2297 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2298 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2299 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2300 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2301 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2302 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2303 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2304 | ||
2305 | /* read the second set of memory latencies[4:7] */ | |
2306 | val = 1; /* data0 to be programmed to 1 for second set */ | |
2307 | mutex_lock(&dev_priv->rps.hw_lock); | |
2308 | ret = sandybridge_pcode_read(dev_priv, | |
2309 | GEN9_PCODE_READ_MEM_LATENCY, | |
2310 | &val); | |
2311 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2312 | if (ret) { | |
2313 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2314 | return; | |
2315 | } | |
2316 | ||
2317 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2318 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2319 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2320 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2321 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2322 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2323 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2324 | ||
0727e40a PZ |
2325 | /* |
2326 | * If a level n (n > 1) has a 0us latency, all levels m (m >= n) | |
2327 | * need to be disabled. We make sure to sanitize the values out | |
2328 | * of the punit to satisfy this requirement. | |
2329 | */ | |
2330 | for (level = 1; level <= max_level; level++) { | |
2331 | if (wm[level] == 0) { | |
2332 | for (i = level + 1; i <= max_level; i++) | |
2333 | wm[i] = 0; | |
2334 | break; | |
2335 | } | |
2336 | } | |
2337 | ||
367294be | 2338 | /* |
9fb5026f | 2339 | * WaWmMemoryReadLatency:skl,glk |
6f97235b | 2340 | * |
367294be | 2341 | * punit doesn't take into account the read latency so we need |
0727e40a PZ |
2342 | * to add 2us to the various latency levels we retrieve from the |
2343 | * punit when level 0 response data us 0us. | |
367294be | 2344 | */ |
0727e40a PZ |
2345 | if (wm[0] == 0) { |
2346 | wm[0] += 2; | |
2347 | for (level = 1; level <= max_level; level++) { | |
2348 | if (wm[level] == 0) | |
2349 | break; | |
367294be | 2350 | wm[level] += 2; |
4f947386 | 2351 | } |
0727e40a PZ |
2352 | } |
2353 | ||
8652744b | 2354 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
12b134df VS |
2355 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2356 | ||
2357 | wm[0] = (sskpd >> 56) & 0xFF; | |
2358 | if (wm[0] == 0) | |
2359 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2360 | wm[1] = (sskpd >> 4) & 0xFF; |
2361 | wm[2] = (sskpd >> 12) & 0xFF; | |
2362 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2363 | wm[4] = (sskpd >> 32) & 0x1FF; | |
bb726519 | 2364 | } else if (INTEL_GEN(dev_priv) >= 6) { |
63cf9a13 VS |
2365 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
2366 | ||
2367 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2368 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2369 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2370 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
bb726519 | 2371 | } else if (INTEL_GEN(dev_priv) >= 5) { |
3a88d0ac VS |
2372 | uint32_t mltr = I915_READ(MLTR_ILK); |
2373 | ||
2374 | /* ILK primary LP0 latency is 700 ns */ | |
2375 | wm[0] = 7; | |
2376 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2377 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2378 | } |
2379 | } | |
2380 | ||
5db94019 TU |
2381 | static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, |
2382 | uint16_t wm[5]) | |
53615a5e VS |
2383 | { |
2384 | /* ILK sprite LP0 latency is 1300 ns */ | |
5db94019 | 2385 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2386 | wm[0] = 13; |
2387 | } | |
2388 | ||
fd6b8f43 TU |
2389 | static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, |
2390 | uint16_t wm[5]) | |
53615a5e VS |
2391 | { |
2392 | /* ILK cursor LP0 latency is 1300 ns */ | |
fd6b8f43 | 2393 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2394 | wm[0] = 13; |
2395 | ||
2396 | /* WaDoubleCursorLP3Latency:ivb */ | |
fd6b8f43 | 2397 | if (IS_IVYBRIDGE(dev_priv)) |
53615a5e VS |
2398 | wm[3] *= 2; |
2399 | } | |
2400 | ||
5db94019 | 2401 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv) |
26ec971e | 2402 | { |
26ec971e | 2403 | /* how many WM levels are we expecting */ |
8652744b | 2404 | if (INTEL_GEN(dev_priv) >= 9) |
2af30a5c | 2405 | return 7; |
8652744b | 2406 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ad0d6dc4 | 2407 | return 4; |
8652744b | 2408 | else if (INTEL_GEN(dev_priv) >= 6) |
ad0d6dc4 | 2409 | return 3; |
26ec971e | 2410 | else |
ad0d6dc4 VS |
2411 | return 2; |
2412 | } | |
7526ed79 | 2413 | |
5db94019 | 2414 | static void intel_print_wm_latency(struct drm_i915_private *dev_priv, |
ad0d6dc4 | 2415 | const char *name, |
2af30a5c | 2416 | const uint16_t wm[8]) |
ad0d6dc4 | 2417 | { |
5db94019 | 2418 | int level, max_level = ilk_wm_max_level(dev_priv); |
26ec971e VS |
2419 | |
2420 | for (level = 0; level <= max_level; level++) { | |
2421 | unsigned int latency = wm[level]; | |
2422 | ||
2423 | if (latency == 0) { | |
2424 | DRM_ERROR("%s WM%d latency not provided\n", | |
2425 | name, level); | |
2426 | continue; | |
2427 | } | |
2428 | ||
2af30a5c PB |
2429 | /* |
2430 | * - latencies are in us on gen9. | |
2431 | * - before then, WM1+ latency values are in 0.5us units | |
2432 | */ | |
5db94019 | 2433 | if (IS_GEN9(dev_priv)) |
2af30a5c PB |
2434 | latency *= 10; |
2435 | else if (level > 0) | |
26ec971e VS |
2436 | latency *= 5; |
2437 | ||
2438 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2439 | name, level, wm[level], | |
2440 | latency / 10, latency % 10); | |
2441 | } | |
2442 | } | |
2443 | ||
e95a2f75 VS |
2444 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2445 | uint16_t wm[5], uint16_t min) | |
2446 | { | |
5db94019 | 2447 | int level, max_level = ilk_wm_max_level(dev_priv); |
e95a2f75 VS |
2448 | |
2449 | if (wm[0] >= min) | |
2450 | return false; | |
2451 | ||
2452 | wm[0] = max(wm[0], min); | |
2453 | for (level = 1; level <= max_level; level++) | |
2454 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2455 | ||
2456 | return true; | |
2457 | } | |
2458 | ||
bb726519 | 2459 | static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) |
e95a2f75 | 2460 | { |
e95a2f75 VS |
2461 | bool changed; |
2462 | ||
2463 | /* | |
2464 | * The BIOS provided WM memory latency values are often | |
2465 | * inadequate for high resolution displays. Adjust them. | |
2466 | */ | |
2467 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2468 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2469 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2470 | ||
2471 | if (!changed) | |
2472 | return; | |
2473 | ||
2474 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
5db94019 TU |
2475 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2476 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2477 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2478 | } |
2479 | ||
bb726519 | 2480 | static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) |
53615a5e | 2481 | { |
bb726519 | 2482 | intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); |
53615a5e VS |
2483 | |
2484 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2485 | sizeof(dev_priv->wm.pri_latency)); | |
2486 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2487 | sizeof(dev_priv->wm.pri_latency)); | |
2488 | ||
5db94019 | 2489 | intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); |
fd6b8f43 | 2490 | intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); |
26ec971e | 2491 | |
5db94019 TU |
2492 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2493 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2494 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 | 2495 | |
5db94019 | 2496 | if (IS_GEN6(dev_priv)) |
bb726519 | 2497 | snb_wm_latency_quirk(dev_priv); |
53615a5e VS |
2498 | } |
2499 | ||
bb726519 | 2500 | static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) |
2af30a5c | 2501 | { |
bb726519 | 2502 | intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); |
5db94019 | 2503 | intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); |
2af30a5c PB |
2504 | } |
2505 | ||
ed4a6a7c MR |
2506 | static bool ilk_validate_pipe_wm(struct drm_device *dev, |
2507 | struct intel_pipe_wm *pipe_wm) | |
2508 | { | |
2509 | /* LP0 watermark maximums depend on this pipe alone */ | |
2510 | const struct intel_wm_config config = { | |
2511 | .num_pipes_active = 1, | |
2512 | .sprites_enabled = pipe_wm->sprites_enabled, | |
2513 | .sprites_scaled = pipe_wm->sprites_scaled, | |
2514 | }; | |
2515 | struct ilk_wm_maximums max; | |
2516 | ||
2517 | /* LP0 watermarks always use 1/2 DDB partitioning */ | |
2518 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2519 | ||
2520 | /* At least LP0 must be valid */ | |
2521 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { | |
2522 | DRM_DEBUG_KMS("LP0 watermark invalid\n"); | |
2523 | return false; | |
2524 | } | |
2525 | ||
2526 | return true; | |
2527 | } | |
2528 | ||
0b2ae6d7 | 2529 | /* Compute new watermarks for the pipe */ |
e3bddded | 2530 | static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) |
0b2ae6d7 | 2531 | { |
e3bddded ML |
2532 | struct drm_atomic_state *state = cstate->base.state; |
2533 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
86c8bbbe | 2534 | struct intel_pipe_wm *pipe_wm; |
e3bddded | 2535 | struct drm_device *dev = state->dev; |
fac5e23e | 2536 | const struct drm_i915_private *dev_priv = to_i915(dev); |
43d59eda | 2537 | struct intel_plane *intel_plane; |
86c8bbbe | 2538 | struct intel_plane_state *pristate = NULL; |
43d59eda | 2539 | struct intel_plane_state *sprstate = NULL; |
86c8bbbe | 2540 | struct intel_plane_state *curstate = NULL; |
5db94019 | 2541 | int level, max_level = ilk_wm_max_level(dev_priv), usable_level; |
820c1980 | 2542 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2543 | |
e8f1f02e | 2544 | pipe_wm = &cstate->wm.ilk.optimal; |
86c8bbbe | 2545 | |
43d59eda | 2546 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
e3bddded ML |
2547 | struct intel_plane_state *ps; |
2548 | ||
2549 | ps = intel_atomic_get_existing_plane_state(state, | |
2550 | intel_plane); | |
2551 | if (!ps) | |
2552 | continue; | |
86c8bbbe MR |
2553 | |
2554 | if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
e3bddded | 2555 | pristate = ps; |
86c8bbbe | 2556 | else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) |
e3bddded | 2557 | sprstate = ps; |
86c8bbbe | 2558 | else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) |
e3bddded | 2559 | curstate = ps; |
43d59eda MR |
2560 | } |
2561 | ||
ed4a6a7c | 2562 | pipe_wm->pipe_enabled = cstate->base.active; |
e3bddded | 2563 | if (sprstate) { |
936e71e3 VS |
2564 | pipe_wm->sprites_enabled = sprstate->base.visible; |
2565 | pipe_wm->sprites_scaled = sprstate->base.visible && | |
2566 | (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 || | |
2567 | drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16); | |
e3bddded ML |
2568 | } |
2569 | ||
d81f04c5 ML |
2570 | usable_level = max_level; |
2571 | ||
7b39a0b7 | 2572 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
175fded1 | 2573 | if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) |
d81f04c5 | 2574 | usable_level = 1; |
7b39a0b7 VS |
2575 | |
2576 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
ed4a6a7c | 2577 | if (pipe_wm->sprites_scaled) |
d81f04c5 | 2578 | usable_level = 0; |
7b39a0b7 | 2579 | |
86c8bbbe | 2580 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
71f0a626 ML |
2581 | pristate, sprstate, curstate, &pipe_wm->raw_wm[0]); |
2582 | ||
2583 | memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); | |
2584 | pipe_wm->wm[0] = pipe_wm->raw_wm[0]; | |
0b2ae6d7 | 2585 | |
8652744b | 2586 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
532f7a7f | 2587 | pipe_wm->linetime = hsw_compute_linetime_wm(cstate); |
0b2ae6d7 | 2588 | |
ed4a6a7c | 2589 | if (!ilk_validate_pipe_wm(dev, pipe_wm)) |
1a426d61 | 2590 | return -EINVAL; |
a3cb4048 | 2591 | |
175fded1 | 2592 | ilk_compute_wm_reg_maximums(dev_priv, 1, &max); |
a3cb4048 VS |
2593 | |
2594 | for (level = 1; level <= max_level; level++) { | |
71f0a626 | 2595 | struct intel_wm_level *wm = &pipe_wm->raw_wm[level]; |
a3cb4048 | 2596 | |
86c8bbbe | 2597 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, |
d81f04c5 | 2598 | pristate, sprstate, curstate, wm); |
a3cb4048 VS |
2599 | |
2600 | /* | |
2601 | * Disable any watermark level that exceeds the | |
2602 | * register maximums since such watermarks are | |
2603 | * always invalid. | |
2604 | */ | |
71f0a626 ML |
2605 | if (level > usable_level) |
2606 | continue; | |
2607 | ||
2608 | if (ilk_validate_wm_level(level, &max, wm)) | |
2609 | pipe_wm->wm[level] = *wm; | |
2610 | else | |
d81f04c5 | 2611 | usable_level = level; |
a3cb4048 VS |
2612 | } |
2613 | ||
86c8bbbe | 2614 | return 0; |
0b2ae6d7 VS |
2615 | } |
2616 | ||
ed4a6a7c MR |
2617 | /* |
2618 | * Build a set of 'intermediate' watermark values that satisfy both the old | |
2619 | * state and the new state. These can be programmed to the hardware | |
2620 | * immediately. | |
2621 | */ | |
2622 | static int ilk_compute_intermediate_wm(struct drm_device *dev, | |
2623 | struct intel_crtc *intel_crtc, | |
2624 | struct intel_crtc_state *newstate) | |
2625 | { | |
e8f1f02e | 2626 | struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; |
ed4a6a7c | 2627 | struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk; |
5db94019 | 2628 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
ed4a6a7c MR |
2629 | |
2630 | /* | |
2631 | * Start with the final, target watermarks, then combine with the | |
2632 | * currently active watermarks to get values that are safe both before | |
2633 | * and after the vblank. | |
2634 | */ | |
e8f1f02e | 2635 | *a = newstate->wm.ilk.optimal; |
ed4a6a7c MR |
2636 | a->pipe_enabled |= b->pipe_enabled; |
2637 | a->sprites_enabled |= b->sprites_enabled; | |
2638 | a->sprites_scaled |= b->sprites_scaled; | |
2639 | ||
2640 | for (level = 0; level <= max_level; level++) { | |
2641 | struct intel_wm_level *a_wm = &a->wm[level]; | |
2642 | const struct intel_wm_level *b_wm = &b->wm[level]; | |
2643 | ||
2644 | a_wm->enable &= b_wm->enable; | |
2645 | a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val); | |
2646 | a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val); | |
2647 | a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val); | |
2648 | a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val); | |
2649 | } | |
2650 | ||
2651 | /* | |
2652 | * We need to make sure that these merged watermark values are | |
2653 | * actually a valid configuration themselves. If they're not, | |
2654 | * there's no safe way to transition from the old state to | |
2655 | * the new state, so we need to fail the atomic transaction. | |
2656 | */ | |
2657 | if (!ilk_validate_pipe_wm(dev, a)) | |
2658 | return -EINVAL; | |
2659 | ||
2660 | /* | |
2661 | * If our intermediate WM are identical to the final WM, then we can | |
2662 | * omit the post-vblank programming; only update if it's different. | |
2663 | */ | |
5eeb798b VS |
2664 | if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0) |
2665 | newstate->wm.need_postvbl_update = true; | |
ed4a6a7c MR |
2666 | |
2667 | return 0; | |
2668 | } | |
2669 | ||
0b2ae6d7 VS |
2670 | /* |
2671 | * Merge the watermarks from all active pipes for a specific level. | |
2672 | */ | |
2673 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2674 | int level, | |
2675 | struct intel_wm_level *ret_wm) | |
2676 | { | |
2677 | const struct intel_crtc *intel_crtc; | |
2678 | ||
d52fea5b VS |
2679 | ret_wm->enable = true; |
2680 | ||
d3fcc808 | 2681 | for_each_intel_crtc(dev, intel_crtc) { |
ed4a6a7c | 2682 | const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; |
fe392efd VS |
2683 | const struct intel_wm_level *wm = &active->wm[level]; |
2684 | ||
2685 | if (!active->pipe_enabled) | |
2686 | continue; | |
0b2ae6d7 | 2687 | |
d52fea5b VS |
2688 | /* |
2689 | * The watermark values may have been used in the past, | |
2690 | * so we must maintain them in the registers for some | |
2691 | * time even if the level is now disabled. | |
2692 | */ | |
0b2ae6d7 | 2693 | if (!wm->enable) |
d52fea5b | 2694 | ret_wm->enable = false; |
0b2ae6d7 VS |
2695 | |
2696 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2697 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2698 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2699 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2700 | } | |
0b2ae6d7 VS |
2701 | } |
2702 | ||
2703 | /* | |
2704 | * Merge all low power watermarks for all active pipes. | |
2705 | */ | |
2706 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2707 | const struct intel_wm_config *config, |
820c1980 | 2708 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2709 | struct intel_pipe_wm *merged) |
2710 | { | |
fac5e23e | 2711 | struct drm_i915_private *dev_priv = to_i915(dev); |
5db94019 | 2712 | int level, max_level = ilk_wm_max_level(dev_priv); |
d52fea5b | 2713 | int last_enabled_level = max_level; |
0b2ae6d7 | 2714 | |
0ba22e26 | 2715 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
fd6b8f43 | 2716 | if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) && |
0ba22e26 | 2717 | config->num_pipes_active > 1) |
1204d5ba | 2718 | last_enabled_level = 0; |
0ba22e26 | 2719 | |
6c8b6c28 | 2720 | /* ILK: FBC WM must be disabled always */ |
175fded1 | 2721 | merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; |
0b2ae6d7 VS |
2722 | |
2723 | /* merge each WM1+ level */ | |
2724 | for (level = 1; level <= max_level; level++) { | |
2725 | struct intel_wm_level *wm = &merged->wm[level]; | |
2726 | ||
2727 | ilk_merge_wm_level(dev, level, wm); | |
2728 | ||
d52fea5b VS |
2729 | if (level > last_enabled_level) |
2730 | wm->enable = false; | |
2731 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2732 | /* make sure all following levels get disabled */ | |
2733 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2734 | |
2735 | /* | |
2736 | * The spec says it is preferred to disable | |
2737 | * FBC WMs instead of disabling a WM level. | |
2738 | */ | |
2739 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2740 | if (wm->enable) |
2741 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2742 | wm->fbc_val = 0; |
2743 | } | |
2744 | } | |
6c8b6c28 VS |
2745 | |
2746 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2747 | /* | |
2748 | * FIXME this is racy. FBC might get enabled later. | |
2749 | * What we should check here is whether FBC can be | |
2750 | * enabled sometime later. | |
2751 | */ | |
5db94019 | 2752 | if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && |
0e631adc | 2753 | intel_fbc_is_active(dev_priv)) { |
6c8b6c28 VS |
2754 | for (level = 2; level <= max_level; level++) { |
2755 | struct intel_wm_level *wm = &merged->wm[level]; | |
2756 | ||
2757 | wm->enable = false; | |
2758 | } | |
2759 | } | |
0b2ae6d7 VS |
2760 | } |
2761 | ||
b380ca3c VS |
2762 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2763 | { | |
2764 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2765 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2766 | } | |
2767 | ||
a68d68ee VS |
2768 | /* The value we need to program into the WM_LPx latency field */ |
2769 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2770 | { | |
fac5e23e | 2771 | struct drm_i915_private *dev_priv = to_i915(dev); |
a68d68ee | 2772 | |
8652744b | 2773 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
a68d68ee VS |
2774 | return 2 * level; |
2775 | else | |
2776 | return dev_priv->wm.pri_latency[level]; | |
2777 | } | |
2778 | ||
820c1980 | 2779 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2780 | const struct intel_pipe_wm *merged, |
609cedef | 2781 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2782 | struct ilk_wm_values *results) |
801bcfff | 2783 | { |
175fded1 | 2784 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b2ae6d7 VS |
2785 | struct intel_crtc *intel_crtc; |
2786 | int level, wm_lp; | |
cca32e9a | 2787 | |
0362c781 | 2788 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2789 | results->partitioning = partitioning; |
cca32e9a | 2790 | |
0b2ae6d7 | 2791 | /* LP1+ register values */ |
cca32e9a | 2792 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2793 | const struct intel_wm_level *r; |
801bcfff | 2794 | |
b380ca3c | 2795 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2796 | |
0362c781 | 2797 | r = &merged->wm[level]; |
cca32e9a | 2798 | |
d52fea5b VS |
2799 | /* |
2800 | * Maintain the watermark values even if the level is | |
2801 | * disabled. Doing otherwise could cause underruns. | |
2802 | */ | |
2803 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2804 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2805 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2806 | r->cur_val; | |
2807 | ||
d52fea5b VS |
2808 | if (r->enable) |
2809 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2810 | ||
175fded1 | 2811 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 VS |
2812 | results->wm_lp[wm_lp - 1] |= |
2813 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2814 | else | |
2815 | results->wm_lp[wm_lp - 1] |= | |
2816 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2817 | ||
d52fea5b VS |
2818 | /* |
2819 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2820 | * level is disabled. Doing otherwise could cause underruns. | |
2821 | */ | |
175fded1 | 2822 | if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { |
6cef2b8a VS |
2823 | WARN_ON(wm_lp != 1); |
2824 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2825 | } else | |
2826 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2827 | } |
801bcfff | 2828 | |
0b2ae6d7 | 2829 | /* LP0 register values */ |
d3fcc808 | 2830 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 | 2831 | enum pipe pipe = intel_crtc->pipe; |
ed4a6a7c MR |
2832 | const struct intel_wm_level *r = |
2833 | &intel_crtc->wm.active.ilk.wm[0]; | |
0b2ae6d7 VS |
2834 | |
2835 | if (WARN_ON(!r->enable)) | |
2836 | continue; | |
2837 | ||
ed4a6a7c | 2838 | results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; |
1011d8c4 | 2839 | |
0b2ae6d7 VS |
2840 | results->wm_pipe[pipe] = |
2841 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2842 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2843 | r->cur_val; | |
801bcfff PZ |
2844 | } |
2845 | } | |
2846 | ||
861f3389 PZ |
2847 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2848 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2849 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2850 | struct intel_pipe_wm *r1, |
2851 | struct intel_pipe_wm *r2) | |
861f3389 | 2852 | { |
5db94019 | 2853 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
198a1e9b | 2854 | int level1 = 0, level2 = 0; |
861f3389 | 2855 | |
198a1e9b VS |
2856 | for (level = 1; level <= max_level; level++) { |
2857 | if (r1->wm[level].enable) | |
2858 | level1 = level; | |
2859 | if (r2->wm[level].enable) | |
2860 | level2 = level; | |
861f3389 PZ |
2861 | } |
2862 | ||
198a1e9b VS |
2863 | if (level1 == level2) { |
2864 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2865 | return r2; |
2866 | else | |
2867 | return r1; | |
198a1e9b | 2868 | } else if (level1 > level2) { |
861f3389 PZ |
2869 | return r1; |
2870 | } else { | |
2871 | return r2; | |
2872 | } | |
2873 | } | |
2874 | ||
49a687c4 VS |
2875 | /* dirty bits used to track which watermarks need changes */ |
2876 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2877 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2878 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2879 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2880 | #define WM_DIRTY_FBC (1 << 24) | |
2881 | #define WM_DIRTY_DDB (1 << 25) | |
2882 | ||
055e393f | 2883 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2884 | const struct ilk_wm_values *old, |
2885 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2886 | { |
2887 | unsigned int dirty = 0; | |
2888 | enum pipe pipe; | |
2889 | int wm_lp; | |
2890 | ||
055e393f | 2891 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2892 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2893 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2894 | /* Must disable LP1+ watermarks too */ | |
2895 | dirty |= WM_DIRTY_LP_ALL; | |
2896 | } | |
2897 | ||
2898 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2899 | dirty |= WM_DIRTY_PIPE(pipe); | |
2900 | /* Must disable LP1+ watermarks too */ | |
2901 | dirty |= WM_DIRTY_LP_ALL; | |
2902 | } | |
2903 | } | |
2904 | ||
2905 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2906 | dirty |= WM_DIRTY_FBC; | |
2907 | /* Must disable LP1+ watermarks too */ | |
2908 | dirty |= WM_DIRTY_LP_ALL; | |
2909 | } | |
2910 | ||
2911 | if (old->partitioning != new->partitioning) { | |
2912 | dirty |= WM_DIRTY_DDB; | |
2913 | /* Must disable LP1+ watermarks too */ | |
2914 | dirty |= WM_DIRTY_LP_ALL; | |
2915 | } | |
2916 | ||
2917 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2918 | if (dirty & WM_DIRTY_LP_ALL) | |
2919 | return dirty; | |
2920 | ||
2921 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2922 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2923 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2924 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2925 | break; | |
2926 | } | |
2927 | ||
2928 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2929 | for (; wm_lp <= 3; wm_lp++) | |
2930 | dirty |= WM_DIRTY_LP(wm_lp); | |
2931 | ||
2932 | return dirty; | |
2933 | } | |
2934 | ||
8553c18e VS |
2935 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2936 | unsigned int dirty) | |
801bcfff | 2937 | { |
820c1980 | 2938 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2939 | bool changed = false; |
801bcfff | 2940 | |
facd619b VS |
2941 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2942 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2943 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2944 | changed = true; |
facd619b VS |
2945 | } |
2946 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2947 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2948 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2949 | changed = true; |
facd619b VS |
2950 | } |
2951 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2952 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2953 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2954 | changed = true; |
facd619b | 2955 | } |
801bcfff | 2956 | |
facd619b VS |
2957 | /* |
2958 | * Don't touch WM1S_LP_EN here. | |
2959 | * Doing so could cause underruns. | |
2960 | */ | |
6cef2b8a | 2961 | |
8553c18e VS |
2962 | return changed; |
2963 | } | |
2964 | ||
2965 | /* | |
2966 | * The spec says we shouldn't write when we don't need, because every write | |
2967 | * causes WMs to be re-evaluated, expending some power. | |
2968 | */ | |
820c1980 ID |
2969 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2970 | struct ilk_wm_values *results) | |
8553c18e | 2971 | { |
820c1980 | 2972 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2973 | unsigned int dirty; |
2974 | uint32_t val; | |
2975 | ||
055e393f | 2976 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2977 | if (!dirty) |
2978 | return; | |
2979 | ||
2980 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2981 | ||
49a687c4 | 2982 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2983 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2984 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2985 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2986 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2987 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2988 | ||
49a687c4 | 2989 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2990 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2991 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2992 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2993 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2994 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2995 | ||
49a687c4 | 2996 | if (dirty & WM_DIRTY_DDB) { |
8652744b | 2997 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
ac9545fd VS |
2998 | val = I915_READ(WM_MISC); |
2999 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3000 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
3001 | else | |
3002 | val |= WM_MISC_DATA_PARTITION_5_6; | |
3003 | I915_WRITE(WM_MISC, val); | |
3004 | } else { | |
3005 | val = I915_READ(DISP_ARB_CTL2); | |
3006 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3007 | val &= ~DISP_DATA_PARTITION_5_6; | |
3008 | else | |
3009 | val |= DISP_DATA_PARTITION_5_6; | |
3010 | I915_WRITE(DISP_ARB_CTL2, val); | |
3011 | } | |
1011d8c4 PZ |
3012 | } |
3013 | ||
49a687c4 | 3014 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
3015 | val = I915_READ(DISP_ARB_CTL); |
3016 | if (results->enable_fbc_wm) | |
3017 | val &= ~DISP_FBC_WM_DIS; | |
3018 | else | |
3019 | val |= DISP_FBC_WM_DIS; | |
3020 | I915_WRITE(DISP_ARB_CTL, val); | |
3021 | } | |
3022 | ||
954911eb ID |
3023 | if (dirty & WM_DIRTY_LP(1) && |
3024 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
3025 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
3026 | ||
175fded1 | 3027 | if (INTEL_GEN(dev_priv) >= 7) { |
6cef2b8a VS |
3028 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
3029 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
3030 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
3031 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
3032 | } | |
801bcfff | 3033 | |
facd619b | 3034 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 3035 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 3036 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 3037 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 3038 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 3039 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
3040 | |
3041 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
3042 | } |
3043 | ||
ed4a6a7c | 3044 | bool ilk_disable_lp_wm(struct drm_device *dev) |
8553c18e | 3045 | { |
fac5e23e | 3046 | struct drm_i915_private *dev_priv = to_i915(dev); |
8553c18e VS |
3047 | |
3048 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
3049 | } | |
3050 | ||
656d1b89 | 3051 | #define SKL_SAGV_BLOCK_TIME 30 /* µs */ |
b9cec075 | 3052 | |
ee3d532f PZ |
3053 | /* |
3054 | * FIXME: We still don't have the proper code detect if we need to apply the WA, | |
3055 | * so assume we'll always need it in order to avoid underruns. | |
3056 | */ | |
3057 | static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) | |
3058 | { | |
3059 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
3060 | ||
b976dc53 | 3061 | if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) |
ee3d532f PZ |
3062 | return true; |
3063 | ||
3064 | return false; | |
3065 | } | |
3066 | ||
56feca91 PZ |
3067 | static bool |
3068 | intel_has_sagv(struct drm_i915_private *dev_priv) | |
3069 | { | |
6e3100ec PZ |
3070 | if (IS_KABYLAKE(dev_priv)) |
3071 | return true; | |
3072 | ||
3073 | if (IS_SKYLAKE(dev_priv) && | |
3074 | dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED) | |
3075 | return true; | |
3076 | ||
3077 | return false; | |
56feca91 PZ |
3078 | } |
3079 | ||
656d1b89 L |
3080 | /* |
3081 | * SAGV dynamically adjusts the system agent voltage and clock frequencies | |
3082 | * depending on power and performance requirements. The display engine access | |
3083 | * to system memory is blocked during the adjustment time. Because of the | |
3084 | * blocking time, having this enabled can cause full system hangs and/or pipe | |
3085 | * underruns if we don't meet all of the following requirements: | |
3086 | * | |
3087 | * - <= 1 pipe enabled | |
3088 | * - All planes can enable watermarks for latencies >= SAGV engine block time | |
3089 | * - We're not using an interlaced display configuration | |
3090 | */ | |
3091 | int | |
16dcdc4e | 3092 | intel_enable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 L |
3093 | { |
3094 | int ret; | |
3095 | ||
56feca91 PZ |
3096 | if (!intel_has_sagv(dev_priv)) |
3097 | return 0; | |
3098 | ||
3099 | if (dev_priv->sagv_status == I915_SAGV_ENABLED) | |
656d1b89 L |
3100 | return 0; |
3101 | ||
3102 | DRM_DEBUG_KMS("Enabling the SAGV\n"); | |
3103 | mutex_lock(&dev_priv->rps.hw_lock); | |
3104 | ||
3105 | ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, | |
3106 | GEN9_SAGV_ENABLE); | |
3107 | ||
3108 | /* We don't need to wait for the SAGV when enabling */ | |
3109 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3110 | ||
3111 | /* | |
3112 | * Some skl systems, pre-release machines in particular, | |
3113 | * don't actually have an SAGV. | |
3114 | */ | |
6e3100ec | 3115 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3116 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3117 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 L |
3118 | return 0; |
3119 | } else if (ret < 0) { | |
3120 | DRM_ERROR("Failed to enable the SAGV\n"); | |
3121 | return ret; | |
3122 | } | |
3123 | ||
16dcdc4e | 3124 | dev_priv->sagv_status = I915_SAGV_ENABLED; |
656d1b89 L |
3125 | return 0; |
3126 | } | |
3127 | ||
656d1b89 | 3128 | int |
16dcdc4e | 3129 | intel_disable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 | 3130 | { |
b3b8e999 | 3131 | int ret; |
656d1b89 | 3132 | |
56feca91 PZ |
3133 | if (!intel_has_sagv(dev_priv)) |
3134 | return 0; | |
3135 | ||
3136 | if (dev_priv->sagv_status == I915_SAGV_DISABLED) | |
656d1b89 L |
3137 | return 0; |
3138 | ||
3139 | DRM_DEBUG_KMS("Disabling the SAGV\n"); | |
3140 | mutex_lock(&dev_priv->rps.hw_lock); | |
3141 | ||
3142 | /* bspec says to keep retrying for at least 1 ms */ | |
b3b8e999 ID |
3143 | ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL, |
3144 | GEN9_SAGV_DISABLE, | |
3145 | GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, | |
3146 | 1); | |
656d1b89 L |
3147 | mutex_unlock(&dev_priv->rps.hw_lock); |
3148 | ||
656d1b89 L |
3149 | /* |
3150 | * Some skl systems, pre-release machines in particular, | |
3151 | * don't actually have an SAGV. | |
3152 | */ | |
b3b8e999 | 3153 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3154 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3155 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 | 3156 | return 0; |
b3b8e999 ID |
3157 | } else if (ret < 0) { |
3158 | DRM_ERROR("Failed to disable the SAGV (%d)\n", ret); | |
3159 | return ret; | |
656d1b89 L |
3160 | } |
3161 | ||
16dcdc4e | 3162 | dev_priv->sagv_status = I915_SAGV_DISABLED; |
656d1b89 L |
3163 | return 0; |
3164 | } | |
3165 | ||
16dcdc4e | 3166 | bool intel_can_enable_sagv(struct drm_atomic_state *state) |
656d1b89 L |
3167 | { |
3168 | struct drm_device *dev = state->dev; | |
3169 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3170 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
ee3d532f PZ |
3171 | struct intel_crtc *crtc; |
3172 | struct intel_plane *plane; | |
d8c0fafc | 3173 | struct intel_crtc_state *cstate; |
656d1b89 | 3174 | enum pipe pipe; |
d8c0fafc | 3175 | int level, latency; |
656d1b89 | 3176 | |
56feca91 PZ |
3177 | if (!intel_has_sagv(dev_priv)) |
3178 | return false; | |
3179 | ||
656d1b89 L |
3180 | /* |
3181 | * SKL workaround: bspec recommends we disable the SAGV when we have | |
3182 | * more then one pipe enabled | |
3183 | * | |
3184 | * If there are no active CRTCs, no additional checks need be performed | |
3185 | */ | |
3186 | if (hweight32(intel_state->active_crtcs) == 0) | |
3187 | return true; | |
3188 | else if (hweight32(intel_state->active_crtcs) > 1) | |
3189 | return false; | |
3190 | ||
3191 | /* Since we're now guaranteed to only have one active CRTC... */ | |
3192 | pipe = ffs(intel_state->active_crtcs) - 1; | |
98187836 | 3193 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
d8c0fafc | 3194 | cstate = to_intel_crtc_state(crtc->base.state); |
656d1b89 | 3195 | |
c89cadd5 | 3196 | if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
656d1b89 L |
3197 | return false; |
3198 | ||
ee3d532f | 3199 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
d5cdfdf5 VS |
3200 | struct skl_plane_wm *wm = |
3201 | &cstate->wm.skl.optimal.planes[plane->id]; | |
ee3d532f | 3202 | |
656d1b89 | 3203 | /* Skip this plane if it's not enabled */ |
d8c0fafc | 3204 | if (!wm->wm[0].plane_en) |
656d1b89 L |
3205 | continue; |
3206 | ||
3207 | /* Find the highest enabled wm level for this plane */ | |
5db94019 | 3208 | for (level = ilk_wm_max_level(dev_priv); |
d8c0fafc | 3209 | !wm->wm[level].plane_en; --level) |
656d1b89 L |
3210 | { } |
3211 | ||
ee3d532f PZ |
3212 | latency = dev_priv->wm.skl_latency[level]; |
3213 | ||
3214 | if (skl_needs_memory_bw_wa(intel_state) && | |
bae781b2 | 3215 | plane->base.state->fb->modifier == |
ee3d532f PZ |
3216 | I915_FORMAT_MOD_X_TILED) |
3217 | latency += 15; | |
3218 | ||
656d1b89 L |
3219 | /* |
3220 | * If any of the planes on this pipe don't enable wm levels | |
3221 | * that incur memory latencies higher then 30µs we can't enable | |
3222 | * the SAGV | |
3223 | */ | |
ee3d532f | 3224 | if (latency < SKL_SAGV_BLOCK_TIME) |
656d1b89 L |
3225 | return false; |
3226 | } | |
3227 | ||
3228 | return true; | |
3229 | } | |
3230 | ||
b9cec075 DL |
3231 | static void |
3232 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
024c9045 | 3233 | const struct intel_crtc_state *cstate, |
c107acfe MR |
3234 | struct skl_ddb_entry *alloc, /* out */ |
3235 | int *num_active /* out */) | |
b9cec075 | 3236 | { |
c107acfe MR |
3237 | struct drm_atomic_state *state = cstate->base.state; |
3238 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
3239 | struct drm_i915_private *dev_priv = to_i915(dev); | |
024c9045 | 3240 | struct drm_crtc *for_crtc = cstate->base.crtc; |
b9cec075 DL |
3241 | unsigned int pipe_size, ddb_size; |
3242 | int nth_active_pipe; | |
c107acfe | 3243 | |
a6d3460e | 3244 | if (WARN_ON(!state) || !cstate->base.active) { |
b9cec075 DL |
3245 | alloc->start = 0; |
3246 | alloc->end = 0; | |
a6d3460e | 3247 | *num_active = hweight32(dev_priv->active_crtcs); |
b9cec075 DL |
3248 | return; |
3249 | } | |
3250 | ||
a6d3460e MR |
3251 | if (intel_state->active_pipe_changes) |
3252 | *num_active = hweight32(intel_state->active_crtcs); | |
3253 | else | |
3254 | *num_active = hweight32(dev_priv->active_crtcs); | |
3255 | ||
6f3fff60 D |
3256 | ddb_size = INTEL_INFO(dev_priv)->ddb_size; |
3257 | WARN_ON(ddb_size == 0); | |
b9cec075 DL |
3258 | |
3259 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
3260 | ||
c107acfe | 3261 | /* |
a6d3460e MR |
3262 | * If the state doesn't change the active CRTC's, then there's |
3263 | * no need to recalculate; the existing pipe allocation limits | |
3264 | * should remain unchanged. Note that we're safe from racing | |
3265 | * commits since any racing commit that changes the active CRTC | |
3266 | * list would need to grab _all_ crtc locks, including the one | |
3267 | * we currently hold. | |
c107acfe | 3268 | */ |
a6d3460e | 3269 | if (!intel_state->active_pipe_changes) { |
512b5527 ML |
3270 | /* |
3271 | * alloc may be cleared by clear_intel_crtc_state, | |
3272 | * copy from old state to be sure | |
3273 | */ | |
3274 | *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; | |
a6d3460e | 3275 | return; |
c107acfe | 3276 | } |
a6d3460e MR |
3277 | |
3278 | nth_active_pipe = hweight32(intel_state->active_crtcs & | |
3279 | (drm_crtc_mask(for_crtc) - 1)); | |
3280 | pipe_size = ddb_size / hweight32(intel_state->active_crtcs); | |
3281 | alloc->start = nth_active_pipe * ddb_size / *num_active; | |
3282 | alloc->end = alloc->start + pipe_size; | |
b9cec075 DL |
3283 | } |
3284 | ||
c107acfe | 3285 | static unsigned int skl_cursor_allocation(int num_active) |
b9cec075 | 3286 | { |
c107acfe | 3287 | if (num_active == 1) |
b9cec075 DL |
3288 | return 32; |
3289 | ||
3290 | return 8; | |
3291 | } | |
3292 | ||
a269c583 DL |
3293 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
3294 | { | |
3295 | entry->start = reg & 0x3ff; | |
3296 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
3297 | if (entry->end) |
3298 | entry->end += 1; | |
a269c583 DL |
3299 | } |
3300 | ||
08db6652 DL |
3301 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
3302 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 3303 | { |
d5cdfdf5 | 3304 | struct intel_crtc *crtc; |
a269c583 | 3305 | |
b10f1b20 ML |
3306 | memset(ddb, 0, sizeof(*ddb)); |
3307 | ||
d5cdfdf5 | 3308 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
4d800030 | 3309 | enum intel_display_power_domain power_domain; |
d5cdfdf5 VS |
3310 | enum plane_id plane_id; |
3311 | enum pipe pipe = crtc->pipe; | |
4d800030 ID |
3312 | |
3313 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
3314 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b10f1b20 ML |
3315 | continue; |
3316 | ||
d5cdfdf5 VS |
3317 | for_each_plane_id_on_crtc(crtc, plane_id) { |
3318 | u32 val; | |
3319 | ||
3320 | if (plane_id != PLANE_CURSOR) | |
3321 | val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); | |
3322 | else | |
3323 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
a269c583 | 3324 | |
d5cdfdf5 VS |
3325 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val); |
3326 | } | |
4d800030 ID |
3327 | |
3328 | intel_display_power_put(dev_priv, power_domain); | |
a269c583 DL |
3329 | } |
3330 | } | |
3331 | ||
9c2f7a9d KM |
3332 | /* |
3333 | * Determines the downscale amount of a plane for the purposes of watermark calculations. | |
3334 | * The bspec defines downscale amount as: | |
3335 | * | |
3336 | * """ | |
3337 | * Horizontal down scale amount = maximum[1, Horizontal source size / | |
3338 | * Horizontal destination size] | |
3339 | * Vertical down scale amount = maximum[1, Vertical source size / | |
3340 | * Vertical destination size] | |
3341 | * Total down scale amount = Horizontal down scale amount * | |
3342 | * Vertical down scale amount | |
3343 | * """ | |
3344 | * | |
3345 | * Return value is provided in 16.16 fixed point form to retain fractional part. | |
3346 | * Caller should take care of dividing & rounding off the value. | |
3347 | */ | |
3348 | static uint32_t | |
3349 | skl_plane_downscale_amount(const struct intel_plane_state *pstate) | |
3350 | { | |
3351 | uint32_t downscale_h, downscale_w; | |
3352 | uint32_t src_w, src_h, dst_w, dst_h; | |
3353 | ||
936e71e3 | 3354 | if (WARN_ON(!pstate->base.visible)) |
9c2f7a9d KM |
3355 | return DRM_PLANE_HELPER_NO_SCALING; |
3356 | ||
3357 | /* n.b., src is 16.16 fixed point, dst is whole integer */ | |
936e71e3 VS |
3358 | src_w = drm_rect_width(&pstate->base.src); |
3359 | src_h = drm_rect_height(&pstate->base.src); | |
3360 | dst_w = drm_rect_width(&pstate->base.dst); | |
3361 | dst_h = drm_rect_height(&pstate->base.dst); | |
bd2ef25d | 3362 | if (drm_rotation_90_or_270(pstate->base.rotation)) |
9c2f7a9d KM |
3363 | swap(dst_w, dst_h); |
3364 | ||
3365 | downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING); | |
3366 | downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING); | |
3367 | ||
3368 | /* Provide result in 16.16 fixed point */ | |
3369 | return (uint64_t)downscale_w * downscale_h >> 16; | |
3370 | } | |
3371 | ||
b9cec075 | 3372 | static unsigned int |
024c9045 MR |
3373 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
3374 | const struct drm_plane_state *pstate, | |
3375 | int y) | |
b9cec075 | 3376 | { |
a280f7dd | 3377 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); |
8d19d7d9 | 3378 | uint32_t down_scale_amount, data_rate; |
a280f7dd | 3379 | uint32_t width = 0, height = 0; |
8305494e VS |
3380 | struct drm_framebuffer *fb; |
3381 | u32 format; | |
a1de91e5 | 3382 | |
936e71e3 | 3383 | if (!intel_pstate->base.visible) |
a1de91e5 | 3384 | return 0; |
8305494e VS |
3385 | |
3386 | fb = pstate->fb; | |
438b74a5 | 3387 | format = fb->format->format; |
8305494e | 3388 | |
a1de91e5 MR |
3389 | if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR) |
3390 | return 0; | |
3391 | if (y && format != DRM_FORMAT_NV12) | |
3392 | return 0; | |
a280f7dd | 3393 | |
936e71e3 VS |
3394 | width = drm_rect_width(&intel_pstate->base.src) >> 16; |
3395 | height = drm_rect_height(&intel_pstate->base.src) >> 16; | |
a280f7dd | 3396 | |
bd2ef25d | 3397 | if (drm_rotation_90_or_270(pstate->rotation)) |
a280f7dd | 3398 | swap(width, height); |
2cd601c6 CK |
3399 | |
3400 | /* for planar format */ | |
a1de91e5 | 3401 | if (format == DRM_FORMAT_NV12) { |
2cd601c6 | 3402 | if (y) /* y-plane data rate */ |
8d19d7d9 | 3403 | data_rate = width * height * |
353c8598 | 3404 | fb->format->cpp[0]; |
2cd601c6 | 3405 | else /* uv-plane data rate */ |
8d19d7d9 | 3406 | data_rate = (width / 2) * (height / 2) * |
353c8598 | 3407 | fb->format->cpp[1]; |
8d19d7d9 KM |
3408 | } else { |
3409 | /* for packed formats */ | |
353c8598 | 3410 | data_rate = width * height * fb->format->cpp[0]; |
2cd601c6 CK |
3411 | } |
3412 | ||
8d19d7d9 KM |
3413 | down_scale_amount = skl_plane_downscale_amount(intel_pstate); |
3414 | ||
3415 | return (uint64_t)data_rate * down_scale_amount >> 16; | |
b9cec075 DL |
3416 | } |
3417 | ||
3418 | /* | |
3419 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
3420 | * a 8192x4096@32bpp framebuffer: | |
3421 | * 3 * 4096 * 8192 * 4 < 2^32 | |
3422 | */ | |
3423 | static unsigned int | |
1e6ee542 ML |
3424 | skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate, |
3425 | unsigned *plane_data_rate, | |
3426 | unsigned *plane_y_data_rate) | |
b9cec075 | 3427 | { |
9c74d826 MR |
3428 | struct drm_crtc_state *cstate = &intel_cstate->base; |
3429 | struct drm_atomic_state *state = cstate->state; | |
c8fe32c1 | 3430 | struct drm_plane *plane; |
c8fe32c1 | 3431 | const struct drm_plane_state *pstate; |
d5cdfdf5 | 3432 | unsigned int total_data_rate = 0; |
a6d3460e MR |
3433 | |
3434 | if (WARN_ON(!state)) | |
3435 | return 0; | |
b9cec075 | 3436 | |
a1de91e5 | 3437 | /* Calculate and cache data rate for each plane */ |
c8fe32c1 | 3438 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) { |
d5cdfdf5 VS |
3439 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3440 | unsigned int rate; | |
a6d3460e | 3441 | |
a6d3460e MR |
3442 | /* packed/uv */ |
3443 | rate = skl_plane_relative_data_rate(intel_cstate, | |
3444 | pstate, 0); | |
d5cdfdf5 | 3445 | plane_data_rate[plane_id] = rate; |
1e6ee542 ML |
3446 | |
3447 | total_data_rate += rate; | |
a6d3460e MR |
3448 | |
3449 | /* y-plane */ | |
3450 | rate = skl_plane_relative_data_rate(intel_cstate, | |
3451 | pstate, 1); | |
d5cdfdf5 | 3452 | plane_y_data_rate[plane_id] = rate; |
024c9045 | 3453 | |
1e6ee542 | 3454 | total_data_rate += rate; |
b9cec075 DL |
3455 | } |
3456 | ||
3457 | return total_data_rate; | |
3458 | } | |
3459 | ||
cbcfd14b KM |
3460 | static uint16_t |
3461 | skl_ddb_min_alloc(const struct drm_plane_state *pstate, | |
3462 | const int y) | |
3463 | { | |
3464 | struct drm_framebuffer *fb = pstate->fb; | |
3465 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); | |
3466 | uint32_t src_w, src_h; | |
3467 | uint32_t min_scanlines = 8; | |
3468 | uint8_t plane_bpp; | |
3469 | ||
3470 | if (WARN_ON(!fb)) | |
3471 | return 0; | |
3472 | ||
3473 | /* For packed formats, no y-plane, return 0 */ | |
438b74a5 | 3474 | if (y && fb->format->format != DRM_FORMAT_NV12) |
cbcfd14b KM |
3475 | return 0; |
3476 | ||
3477 | /* For Non Y-tile return 8-blocks */ | |
bae781b2 VS |
3478 | if (fb->modifier != I915_FORMAT_MOD_Y_TILED && |
3479 | fb->modifier != I915_FORMAT_MOD_Yf_TILED) | |
cbcfd14b KM |
3480 | return 8; |
3481 | ||
936e71e3 VS |
3482 | src_w = drm_rect_width(&intel_pstate->base.src) >> 16; |
3483 | src_h = drm_rect_height(&intel_pstate->base.src) >> 16; | |
cbcfd14b | 3484 | |
bd2ef25d | 3485 | if (drm_rotation_90_or_270(pstate->rotation)) |
cbcfd14b KM |
3486 | swap(src_w, src_h); |
3487 | ||
3488 | /* Halve UV plane width and height for NV12 */ | |
438b74a5 | 3489 | if (fb->format->format == DRM_FORMAT_NV12 && !y) { |
cbcfd14b KM |
3490 | src_w /= 2; |
3491 | src_h /= 2; | |
3492 | } | |
3493 | ||
438b74a5 | 3494 | if (fb->format->format == DRM_FORMAT_NV12 && !y) |
353c8598 | 3495 | plane_bpp = fb->format->cpp[1]; |
cbcfd14b | 3496 | else |
353c8598 | 3497 | plane_bpp = fb->format->cpp[0]; |
cbcfd14b | 3498 | |
bd2ef25d | 3499 | if (drm_rotation_90_or_270(pstate->rotation)) { |
cbcfd14b KM |
3500 | switch (plane_bpp) { |
3501 | case 1: | |
3502 | min_scanlines = 32; | |
3503 | break; | |
3504 | case 2: | |
3505 | min_scanlines = 16; | |
3506 | break; | |
3507 | case 4: | |
3508 | min_scanlines = 8; | |
3509 | break; | |
3510 | case 8: | |
3511 | min_scanlines = 4; | |
3512 | break; | |
3513 | default: | |
3514 | WARN(1, "Unsupported pixel depth %u for rotation", | |
3515 | plane_bpp); | |
3516 | min_scanlines = 32; | |
3517 | } | |
3518 | } | |
3519 | ||
3520 | return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3; | |
3521 | } | |
3522 | ||
49845a7a ML |
3523 | static void |
3524 | skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active, | |
3525 | uint16_t *minimum, uint16_t *y_minimum) | |
3526 | { | |
3527 | const struct drm_plane_state *pstate; | |
3528 | struct drm_plane *plane; | |
3529 | ||
3530 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) { | |
d5cdfdf5 | 3531 | enum plane_id plane_id = to_intel_plane(plane)->id; |
49845a7a | 3532 | |
d5cdfdf5 | 3533 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
3534 | continue; |
3535 | ||
3536 | if (!pstate->visible) | |
3537 | continue; | |
3538 | ||
d5cdfdf5 VS |
3539 | minimum[plane_id] = skl_ddb_min_alloc(pstate, 0); |
3540 | y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1); | |
49845a7a ML |
3541 | } |
3542 | ||
3543 | minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active); | |
3544 | } | |
3545 | ||
c107acfe | 3546 | static int |
024c9045 | 3547 | skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, |
b9cec075 DL |
3548 | struct skl_ddb_allocation *ddb /* out */) |
3549 | { | |
c107acfe | 3550 | struct drm_atomic_state *state = cstate->base.state; |
024c9045 | 3551 | struct drm_crtc *crtc = cstate->base.crtc; |
b9cec075 DL |
3552 | struct drm_device *dev = crtc->dev; |
3553 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3554 | enum pipe pipe = intel_crtc->pipe; | |
ce0ba283 | 3555 | struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb; |
49845a7a | 3556 | uint16_t alloc_size, start; |
fefdd810 ML |
3557 | uint16_t minimum[I915_MAX_PLANES] = {}; |
3558 | uint16_t y_minimum[I915_MAX_PLANES] = {}; | |
b9cec075 | 3559 | unsigned int total_data_rate; |
d5cdfdf5 | 3560 | enum plane_id plane_id; |
c107acfe | 3561 | int num_active; |
1e6ee542 ML |
3562 | unsigned plane_data_rate[I915_MAX_PLANES] = {}; |
3563 | unsigned plane_y_data_rate[I915_MAX_PLANES] = {}; | |
b9cec075 | 3564 | |
5a920b85 PZ |
3565 | /* Clear the partitioning for disabled planes. */ |
3566 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
3567 | memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe])); | |
3568 | ||
a6d3460e MR |
3569 | if (WARN_ON(!state)) |
3570 | return 0; | |
3571 | ||
c107acfe | 3572 | if (!cstate->base.active) { |
ce0ba283 | 3573 | alloc->start = alloc->end = 0; |
c107acfe MR |
3574 | return 0; |
3575 | } | |
3576 | ||
a6d3460e | 3577 | skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active); |
34bb56af | 3578 | alloc_size = skl_ddb_entry_size(alloc); |
b9cec075 DL |
3579 | if (alloc_size == 0) { |
3580 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
c107acfe | 3581 | return 0; |
b9cec075 DL |
3582 | } |
3583 | ||
49845a7a | 3584 | skl_ddb_calc_min(cstate, num_active, minimum, y_minimum); |
a6d3460e | 3585 | |
49845a7a ML |
3586 | /* |
3587 | * 1. Allocate the mininum required blocks for each active plane | |
3588 | * and allocate the cursor, it doesn't require extra allocation | |
3589 | * proportional to the data rate. | |
3590 | */ | |
80958155 | 3591 | |
d5cdfdf5 VS |
3592 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
3593 | alloc_size -= minimum[plane_id]; | |
3594 | alloc_size -= y_minimum[plane_id]; | |
80958155 DL |
3595 | } |
3596 | ||
49845a7a ML |
3597 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR]; |
3598 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; | |
3599 | ||
b9cec075 | 3600 | /* |
80958155 DL |
3601 | * 2. Distribute the remaining space in proportion to the amount of |
3602 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
3603 | * |
3604 | * FIXME: we may not allocate every single block here. | |
3605 | */ | |
1e6ee542 ML |
3606 | total_data_rate = skl_get_total_relative_data_rate(cstate, |
3607 | plane_data_rate, | |
3608 | plane_y_data_rate); | |
a1de91e5 | 3609 | if (total_data_rate == 0) |
c107acfe | 3610 | return 0; |
b9cec075 | 3611 | |
34bb56af | 3612 | start = alloc->start; |
d5cdfdf5 | 3613 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
2cd601c6 CK |
3614 | unsigned int data_rate, y_data_rate; |
3615 | uint16_t plane_blocks, y_plane_blocks = 0; | |
b9cec075 | 3616 | |
d5cdfdf5 | 3617 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
3618 | continue; |
3619 | ||
d5cdfdf5 | 3620 | data_rate = plane_data_rate[plane_id]; |
b9cec075 DL |
3621 | |
3622 | /* | |
2cd601c6 | 3623 | * allocation for (packed formats) or (uv-plane part of planar format): |
b9cec075 DL |
3624 | * promote the expression to 64 bits to avoid overflowing, the |
3625 | * result is < available as data_rate / total_data_rate < 1 | |
3626 | */ | |
d5cdfdf5 | 3627 | plane_blocks = minimum[plane_id]; |
80958155 DL |
3628 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, |
3629 | total_data_rate); | |
b9cec075 | 3630 | |
c107acfe MR |
3631 | /* Leave disabled planes at (0,0) */ |
3632 | if (data_rate) { | |
d5cdfdf5 VS |
3633 | ddb->plane[pipe][plane_id].start = start; |
3634 | ddb->plane[pipe][plane_id].end = start + plane_blocks; | |
c107acfe | 3635 | } |
b9cec075 DL |
3636 | |
3637 | start += plane_blocks; | |
2cd601c6 CK |
3638 | |
3639 | /* | |
3640 | * allocation for y_plane part of planar format: | |
3641 | */ | |
d5cdfdf5 | 3642 | y_data_rate = plane_y_data_rate[plane_id]; |
a1de91e5 | 3643 | |
d5cdfdf5 | 3644 | y_plane_blocks = y_minimum[plane_id]; |
a1de91e5 MR |
3645 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, |
3646 | total_data_rate); | |
2cd601c6 | 3647 | |
c107acfe | 3648 | if (y_data_rate) { |
d5cdfdf5 VS |
3649 | ddb->y_plane[pipe][plane_id].start = start; |
3650 | ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks; | |
c107acfe | 3651 | } |
a1de91e5 MR |
3652 | |
3653 | start += y_plane_blocks; | |
b9cec075 DL |
3654 | } |
3655 | ||
c107acfe | 3656 | return 0; |
b9cec075 DL |
3657 | } |
3658 | ||
2d41c0b5 PB |
3659 | /* |
3660 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
ac484963 | 3661 | * for the read latency) and cpp should always be <= 8, so that |
2d41c0b5 PB |
3662 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
3663 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
3664 | */ | |
b95320bd MK |
3665 | static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, |
3666 | uint32_t latency) | |
2d41c0b5 | 3667 | { |
b95320bd MK |
3668 | uint32_t wm_intermediate_val; |
3669 | uint_fixed_16_16_t ret; | |
2d41c0b5 PB |
3670 | |
3671 | if (latency == 0) | |
b95320bd | 3672 | return FP_16_16_MAX; |
2d41c0b5 | 3673 | |
b95320bd MK |
3674 | wm_intermediate_val = latency * pixel_rate * cpp; |
3675 | ret = fixed_16_16_div_round_up_u64(wm_intermediate_val, 1000 * 512); | |
2d41c0b5 PB |
3676 | return ret; |
3677 | } | |
3678 | ||
b95320bd MK |
3679 | static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate, |
3680 | uint32_t pipe_htotal, | |
3681 | uint32_t latency, | |
3682 | uint_fixed_16_16_t plane_blocks_per_line) | |
2d41c0b5 | 3683 | { |
d4c2aa60 | 3684 | uint32_t wm_intermediate_val; |
b95320bd | 3685 | uint_fixed_16_16_t ret; |
2d41c0b5 PB |
3686 | |
3687 | if (latency == 0) | |
b95320bd | 3688 | return FP_16_16_MAX; |
2d41c0b5 | 3689 | |
2d41c0b5 | 3690 | wm_intermediate_val = latency * pixel_rate; |
b95320bd MK |
3691 | wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, |
3692 | pipe_htotal * 1000); | |
3693 | ret = mul_u32_fixed_16_16(wm_intermediate_val, plane_blocks_per_line); | |
2d41c0b5 PB |
3694 | return ret; |
3695 | } | |
3696 | ||
9c2f7a9d KM |
3697 | static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, |
3698 | struct intel_plane_state *pstate) | |
3699 | { | |
3700 | uint64_t adjusted_pixel_rate; | |
3701 | uint64_t downscale_amount; | |
3702 | uint64_t pixel_rate; | |
3703 | ||
3704 | /* Shouldn't reach here on disabled planes... */ | |
936e71e3 | 3705 | if (WARN_ON(!pstate->base.visible)) |
9c2f7a9d KM |
3706 | return 0; |
3707 | ||
3708 | /* | |
3709 | * Adjusted plane pixel rate is just the pipe's adjusted pixel rate | |
3710 | * with additional adjustments for plane-specific scaling. | |
3711 | */ | |
a7d1b3f4 | 3712 | adjusted_pixel_rate = cstate->pixel_rate; |
9c2f7a9d KM |
3713 | downscale_amount = skl_plane_downscale_amount(pstate); |
3714 | ||
3715 | pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; | |
3716 | WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0)); | |
3717 | ||
3718 | return pixel_rate; | |
3719 | } | |
3720 | ||
55994c2c MR |
3721 | static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
3722 | struct intel_crtc_state *cstate, | |
3723 | struct intel_plane_state *intel_pstate, | |
3724 | uint16_t ddb_allocation, | |
3725 | int level, | |
3726 | uint16_t *out_blocks, /* out */ | |
3727 | uint8_t *out_lines, /* out */ | |
3728 | bool *enabled /* out */) | |
2d41c0b5 | 3729 | { |
33815fa5 MR |
3730 | struct drm_plane_state *pstate = &intel_pstate->base; |
3731 | struct drm_framebuffer *fb = pstate->fb; | |
d4c2aa60 | 3732 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
b95320bd MK |
3733 | uint_fixed_16_16_t method1, method2; |
3734 | uint_fixed_16_16_t plane_blocks_per_line; | |
3735 | uint_fixed_16_16_t selected_result; | |
3736 | uint32_t interm_pbpl; | |
3737 | uint32_t plane_bytes_per_line; | |
d4c2aa60 | 3738 | uint32_t res_blocks, res_lines; |
ac484963 | 3739 | uint8_t cpp; |
a280f7dd | 3740 | uint32_t width = 0, height = 0; |
9c2f7a9d | 3741 | uint32_t plane_pixel_rate; |
b95320bd MK |
3742 | uint_fixed_16_16_t y_tile_minimum; |
3743 | uint32_t y_min_scanlines; | |
ee3d532f PZ |
3744 | struct intel_atomic_state *state = |
3745 | to_intel_atomic_state(cstate->base.state); | |
3746 | bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); | |
ef8a4fb4 | 3747 | bool y_tiled, x_tiled; |
2d41c0b5 | 3748 | |
936e71e3 | 3749 | if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) { |
55994c2c MR |
3750 | *enabled = false; |
3751 | return 0; | |
3752 | } | |
2d41c0b5 | 3753 | |
ef8a4fb4 MK |
3754 | y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED || |
3755 | fb->modifier == I915_FORMAT_MOD_Yf_TILED; | |
3756 | x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; | |
3757 | ||
4b7b2331 MK |
3758 | /* Display WA #1141: kbl. */ |
3759 | if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled) | |
3760 | latency += 4; | |
3761 | ||
ef8a4fb4 | 3762 | if (apply_memory_bw_wa && x_tiled) |
ee3d532f PZ |
3763 | latency += 15; |
3764 | ||
936e71e3 VS |
3765 | width = drm_rect_width(&intel_pstate->base.src) >> 16; |
3766 | height = drm_rect_height(&intel_pstate->base.src) >> 16; | |
a280f7dd | 3767 | |
bd2ef25d | 3768 | if (drm_rotation_90_or_270(pstate->rotation)) |
a280f7dd KM |
3769 | swap(width, height); |
3770 | ||
353c8598 | 3771 | cpp = fb->format->cpp[0]; |
9c2f7a9d KM |
3772 | plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate); |
3773 | ||
61d0a04d | 3774 | if (drm_rotation_90_or_270(pstate->rotation)) { |
438b74a5 | 3775 | int cpp = (fb->format->format == DRM_FORMAT_NV12) ? |
353c8598 VS |
3776 | fb->format->cpp[1] : |
3777 | fb->format->cpp[0]; | |
1186fa85 PZ |
3778 | |
3779 | switch (cpp) { | |
3780 | case 1: | |
3781 | y_min_scanlines = 16; | |
3782 | break; | |
3783 | case 2: | |
3784 | y_min_scanlines = 8; | |
3785 | break; | |
1186fa85 PZ |
3786 | case 4: |
3787 | y_min_scanlines = 4; | |
3788 | break; | |
86a462bc PZ |
3789 | default: |
3790 | MISSING_CASE(cpp); | |
3791 | return -EINVAL; | |
1186fa85 PZ |
3792 | } |
3793 | } else { | |
3794 | y_min_scanlines = 4; | |
3795 | } | |
3796 | ||
2ef32dee PZ |
3797 | if (apply_memory_bw_wa) |
3798 | y_min_scanlines *= 2; | |
3799 | ||
7a1a8aed | 3800 | plane_bytes_per_line = width * cpp; |
ef8a4fb4 | 3801 | if (y_tiled) { |
b95320bd MK |
3802 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * |
3803 | y_min_scanlines, 512); | |
7a1a8aed | 3804 | plane_blocks_per_line = |
b95320bd | 3805 | fixed_16_16_div_round_up(interm_pbpl, y_min_scanlines); |
ef8a4fb4 | 3806 | } else if (x_tiled) { |
b95320bd MK |
3807 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); |
3808 | plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); | |
ef8a4fb4 | 3809 | } else { |
b95320bd MK |
3810 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1; |
3811 | plane_blocks_per_line = u32_to_fixed_16_16(interm_pbpl); | |
7a1a8aed PZ |
3812 | } |
3813 | ||
9c2f7a9d KM |
3814 | method1 = skl_wm_method1(plane_pixel_rate, cpp, latency); |
3815 | method2 = skl_wm_method2(plane_pixel_rate, | |
024c9045 | 3816 | cstate->base.adjusted_mode.crtc_htotal, |
1186fa85 | 3817 | latency, |
7a1a8aed | 3818 | plane_blocks_per_line); |
2d41c0b5 | 3819 | |
b95320bd MK |
3820 | y_tile_minimum = mul_u32_fixed_16_16(y_min_scanlines, |
3821 | plane_blocks_per_line); | |
75676ed4 | 3822 | |
ef8a4fb4 | 3823 | if (y_tiled) { |
b95320bd | 3824 | selected_result = max_fixed_16_16(method2, y_tile_minimum); |
0fda6568 | 3825 | } else { |
f1db3eaf PZ |
3826 | if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) && |
3827 | (plane_bytes_per_line / 512 < 1)) | |
3828 | selected_result = method2; | |
b95320bd MK |
3829 | else if ((ddb_allocation / |
3830 | fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1) | |
3831 | selected_result = min_fixed_16_16(method1, method2); | |
0fda6568 TU |
3832 | else |
3833 | selected_result = method1; | |
3834 | } | |
2d41c0b5 | 3835 | |
b95320bd MK |
3836 | res_blocks = fixed_16_16_to_u32_round_up(selected_result) + 1; |
3837 | res_lines = DIV_ROUND_UP(selected_result.val, | |
3838 | plane_blocks_per_line.val); | |
e6d66171 | 3839 | |
0fda6568 | 3840 | if (level >= 1 && level <= 7) { |
ef8a4fb4 | 3841 | if (y_tiled) { |
b95320bd | 3842 | res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum); |
1186fa85 | 3843 | res_lines += y_min_scanlines; |
75676ed4 | 3844 | } else { |
0fda6568 | 3845 | res_blocks++; |
75676ed4 | 3846 | } |
0fda6568 | 3847 | } |
e6d66171 | 3848 | |
55994c2c MR |
3849 | if (res_blocks >= ddb_allocation || res_lines > 31) { |
3850 | *enabled = false; | |
6b6bada7 MR |
3851 | |
3852 | /* | |
3853 | * If there are no valid level 0 watermarks, then we can't | |
3854 | * support this display configuration. | |
3855 | */ | |
3856 | if (level) { | |
3857 | return 0; | |
3858 | } else { | |
d5cdfdf5 VS |
3859 | struct drm_plane *plane = pstate->plane; |
3860 | ||
6b6bada7 | 3861 | DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n"); |
d5cdfdf5 VS |
3862 | DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n", |
3863 | plane->base.id, plane->name, | |
6b6bada7 | 3864 | res_blocks, ddb_allocation, res_lines); |
6b6bada7 MR |
3865 | return -EINVAL; |
3866 | } | |
55994c2c | 3867 | } |
e6d66171 DL |
3868 | |
3869 | *out_blocks = res_blocks; | |
3870 | *out_lines = res_lines; | |
55994c2c | 3871 | *enabled = true; |
2d41c0b5 | 3872 | |
55994c2c | 3873 | return 0; |
2d41c0b5 PB |
3874 | } |
3875 | ||
f4a96752 MR |
3876 | static int |
3877 | skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
3878 | struct skl_ddb_allocation *ddb, | |
3879 | struct intel_crtc_state *cstate, | |
a62163e9 | 3880 | struct intel_plane *intel_plane, |
f4a96752 MR |
3881 | int level, |
3882 | struct skl_wm_level *result) | |
2d41c0b5 | 3883 | { |
f4a96752 | 3884 | struct drm_atomic_state *state = cstate->base.state; |
024c9045 | 3885 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
a62163e9 L |
3886 | struct drm_plane *plane = &intel_plane->base; |
3887 | struct intel_plane_state *intel_pstate = NULL; | |
2d41c0b5 | 3888 | uint16_t ddb_blocks; |
024c9045 | 3889 | enum pipe pipe = intel_crtc->pipe; |
55994c2c | 3890 | int ret; |
a62163e9 L |
3891 | |
3892 | if (state) | |
3893 | intel_pstate = | |
3894 | intel_atomic_get_existing_plane_state(state, | |
3895 | intel_plane); | |
024c9045 | 3896 | |
f4a96752 | 3897 | /* |
a62163e9 L |
3898 | * Note: If we start supporting multiple pending atomic commits against |
3899 | * the same planes/CRTC's in the future, plane->state will no longer be | |
3900 | * the correct pre-state to use for the calculations here and we'll | |
3901 | * need to change where we get the 'unchanged' plane data from. | |
3902 | * | |
3903 | * For now this is fine because we only allow one queued commit against | |
3904 | * a CRTC. Even if the plane isn't modified by this transaction and we | |
3905 | * don't have a plane lock, we still have the CRTC's lock, so we know | |
3906 | * that no other transactions are racing with us to update it. | |
f4a96752 | 3907 | */ |
a62163e9 L |
3908 | if (!intel_pstate) |
3909 | intel_pstate = to_intel_plane_state(plane->state); | |
f4a96752 | 3910 | |
a62163e9 | 3911 | WARN_ON(!intel_pstate->base.fb); |
f4a96752 | 3912 | |
d5cdfdf5 | 3913 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); |
2d41c0b5 | 3914 | |
a62163e9 L |
3915 | ret = skl_compute_plane_wm(dev_priv, |
3916 | cstate, | |
3917 | intel_pstate, | |
3918 | ddb_blocks, | |
3919 | level, | |
3920 | &result->plane_res_b, | |
3921 | &result->plane_res_l, | |
3922 | &result->plane_en); | |
3923 | if (ret) | |
3924 | return ret; | |
f4a96752 MR |
3925 | |
3926 | return 0; | |
2d41c0b5 PB |
3927 | } |
3928 | ||
407b50f3 | 3929 | static uint32_t |
024c9045 | 3930 | skl_compute_linetime_wm(struct intel_crtc_state *cstate) |
407b50f3 | 3931 | { |
a3a8986c MK |
3932 | struct drm_atomic_state *state = cstate->base.state; |
3933 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
30d1b5fe | 3934 | uint32_t pixel_rate; |
a3a8986c | 3935 | uint32_t linetime_wm; |
30d1b5fe | 3936 | |
024c9045 | 3937 | if (!cstate->base.active) |
407b50f3 DL |
3938 | return 0; |
3939 | ||
a7d1b3f4 | 3940 | pixel_rate = cstate->pixel_rate; |
30d1b5fe PZ |
3941 | |
3942 | if (WARN_ON(pixel_rate == 0)) | |
661abfc0 | 3943 | return 0; |
407b50f3 | 3944 | |
a3a8986c MK |
3945 | linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * |
3946 | 1000, pixel_rate); | |
3947 | ||
3948 | /* Display WA #1135: bxt. */ | |
3949 | if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled) | |
3950 | linetime_wm = DIV_ROUND_UP(linetime_wm, 2); | |
3951 | ||
3952 | return linetime_wm; | |
407b50f3 DL |
3953 | } |
3954 | ||
024c9045 | 3955 | static void skl_compute_transition_wm(struct intel_crtc_state *cstate, |
9414f563 | 3956 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 3957 | { |
024c9045 | 3958 | if (!cstate->base.active) |
407b50f3 | 3959 | return; |
9414f563 DL |
3960 | |
3961 | /* Until we know more, just disable transition WMs */ | |
a62163e9 | 3962 | trans_wm->plane_en = false; |
407b50f3 DL |
3963 | } |
3964 | ||
55994c2c MR |
3965 | static int skl_build_pipe_wm(struct intel_crtc_state *cstate, |
3966 | struct skl_ddb_allocation *ddb, | |
3967 | struct skl_pipe_wm *pipe_wm) | |
2d41c0b5 | 3968 | { |
024c9045 | 3969 | struct drm_device *dev = cstate->base.crtc->dev; |
fac5e23e | 3970 | const struct drm_i915_private *dev_priv = to_i915(dev); |
a62163e9 L |
3971 | struct intel_plane *intel_plane; |
3972 | struct skl_plane_wm *wm; | |
5db94019 | 3973 | int level, max_level = ilk_wm_max_level(dev_priv); |
55994c2c | 3974 | int ret; |
2d41c0b5 | 3975 | |
a62163e9 L |
3976 | /* |
3977 | * We'll only calculate watermarks for planes that are actually | |
3978 | * enabled, so make sure all other planes are set as disabled. | |
3979 | */ | |
3980 | memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes)); | |
3981 | ||
3982 | for_each_intel_plane_mask(&dev_priv->drm, | |
3983 | intel_plane, | |
3984 | cstate->base.plane_mask) { | |
d5cdfdf5 | 3985 | wm = &pipe_wm->planes[intel_plane->id]; |
a62163e9 L |
3986 | |
3987 | for (level = 0; level <= max_level; level++) { | |
3988 | ret = skl_compute_wm_level(dev_priv, ddb, cstate, | |
3989 | intel_plane, level, | |
3990 | &wm->wm[level]); | |
3991 | if (ret) | |
3992 | return ret; | |
3993 | } | |
3994 | skl_compute_transition_wm(cstate, &wm->trans_wm); | |
2d41c0b5 | 3995 | } |
024c9045 | 3996 | pipe_wm->linetime = skl_compute_linetime_wm(cstate); |
2d41c0b5 | 3997 | |
55994c2c | 3998 | return 0; |
2d41c0b5 PB |
3999 | } |
4000 | ||
f0f59a00 VS |
4001 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, |
4002 | i915_reg_t reg, | |
16160e3d DL |
4003 | const struct skl_ddb_entry *entry) |
4004 | { | |
4005 | if (entry->end) | |
4006 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
4007 | else | |
4008 | I915_WRITE(reg, 0); | |
4009 | } | |
4010 | ||
d8c0fafc | 4011 | static void skl_write_wm_level(struct drm_i915_private *dev_priv, |
4012 | i915_reg_t reg, | |
4013 | const struct skl_wm_level *level) | |
4014 | { | |
4015 | uint32_t val = 0; | |
4016 | ||
4017 | if (level->plane_en) { | |
4018 | val |= PLANE_WM_EN; | |
4019 | val |= level->plane_res_b; | |
4020 | val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; | |
4021 | } | |
4022 | ||
4023 | I915_WRITE(reg, val); | |
4024 | } | |
4025 | ||
d9348dec VS |
4026 | static void skl_write_plane_wm(struct intel_crtc *intel_crtc, |
4027 | const struct skl_plane_wm *wm, | |
4028 | const struct skl_ddb_allocation *ddb, | |
d5cdfdf5 | 4029 | enum plane_id plane_id) |
62e0fb88 L |
4030 | { |
4031 | struct drm_crtc *crtc = &intel_crtc->base; | |
4032 | struct drm_device *dev = crtc->dev; | |
4033 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4034 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4035 | enum pipe pipe = intel_crtc->pipe; |
4036 | ||
4037 | for (level = 0; level <= max_level; level++) { | |
d5cdfdf5 | 4038 | skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), |
d8c0fafc | 4039 | &wm->wm[level]); |
62e0fb88 | 4040 | } |
d5cdfdf5 | 4041 | skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), |
d8c0fafc | 4042 | &wm->trans_wm); |
27082493 | 4043 | |
d5cdfdf5 VS |
4044 | skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), |
4045 | &ddb->plane[pipe][plane_id]); | |
4046 | skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id), | |
4047 | &ddb->y_plane[pipe][plane_id]); | |
62e0fb88 L |
4048 | } |
4049 | ||
d9348dec VS |
4050 | static void skl_write_cursor_wm(struct intel_crtc *intel_crtc, |
4051 | const struct skl_plane_wm *wm, | |
4052 | const struct skl_ddb_allocation *ddb) | |
62e0fb88 L |
4053 | { |
4054 | struct drm_crtc *crtc = &intel_crtc->base; | |
4055 | struct drm_device *dev = crtc->dev; | |
4056 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4057 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4058 | enum pipe pipe = intel_crtc->pipe; |
4059 | ||
4060 | for (level = 0; level <= max_level; level++) { | |
d8c0fafc | 4061 | skl_write_wm_level(dev_priv, CUR_WM(pipe, level), |
4062 | &wm->wm[level]); | |
62e0fb88 | 4063 | } |
d8c0fafc | 4064 | skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); |
5d374d96 | 4065 | |
27082493 | 4066 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
d8c0fafc | 4067 | &ddb->plane[pipe][PLANE_CURSOR]); |
2d41c0b5 PB |
4068 | } |
4069 | ||
45ece230 | 4070 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
4071 | const struct skl_wm_level *l2) | |
4072 | { | |
4073 | if (l1->plane_en != l2->plane_en) | |
4074 | return false; | |
4075 | ||
4076 | /* If both planes aren't enabled, the rest shouldn't matter */ | |
4077 | if (!l1->plane_en) | |
4078 | return true; | |
4079 | ||
4080 | return (l1->plane_res_l == l2->plane_res_l && | |
4081 | l1->plane_res_b == l2->plane_res_b); | |
4082 | } | |
4083 | ||
27082493 L |
4084 | static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, |
4085 | const struct skl_ddb_entry *b) | |
0e8fb7ba | 4086 | { |
27082493 | 4087 | return a->start < b->end && b->start < a->end; |
0e8fb7ba DL |
4088 | } |
4089 | ||
5eff503b ML |
4090 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, |
4091 | const struct skl_ddb_entry *ddb, | |
4092 | int ignore) | |
0e8fb7ba | 4093 | { |
ce0ba283 | 4094 | int i; |
0e8fb7ba | 4095 | |
5eff503b ML |
4096 | for (i = 0; i < I915_MAX_PIPES; i++) |
4097 | if (i != ignore && entries[i] && | |
4098 | skl_ddb_entries_overlap(ddb, entries[i])) | |
27082493 | 4099 | return true; |
0e8fb7ba | 4100 | |
27082493 | 4101 | return false; |
0e8fb7ba DL |
4102 | } |
4103 | ||
55994c2c | 4104 | static int skl_update_pipe_wm(struct drm_crtc_state *cstate, |
03af79e0 | 4105 | const struct skl_pipe_wm *old_pipe_wm, |
55994c2c | 4106 | struct skl_pipe_wm *pipe_wm, /* out */ |
03af79e0 | 4107 | struct skl_ddb_allocation *ddb, /* out */ |
55994c2c | 4108 | bool *changed /* out */) |
2d41c0b5 | 4109 | { |
f4a96752 | 4110 | struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate); |
55994c2c | 4111 | int ret; |
2d41c0b5 | 4112 | |
55994c2c MR |
4113 | ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm); |
4114 | if (ret) | |
4115 | return ret; | |
2d41c0b5 | 4116 | |
03af79e0 | 4117 | if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm))) |
55994c2c MR |
4118 | *changed = false; |
4119 | else | |
4120 | *changed = true; | |
2d41c0b5 | 4121 | |
55994c2c | 4122 | return 0; |
2d41c0b5 PB |
4123 | } |
4124 | ||
9b613022 MR |
4125 | static uint32_t |
4126 | pipes_modified(struct drm_atomic_state *state) | |
4127 | { | |
4128 | struct drm_crtc *crtc; | |
4129 | struct drm_crtc_state *cstate; | |
4130 | uint32_t i, ret = 0; | |
4131 | ||
6ebdb5a0 | 4132 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
9b613022 MR |
4133 | ret |= drm_crtc_mask(crtc); |
4134 | ||
4135 | return ret; | |
4136 | } | |
4137 | ||
bb7791bd | 4138 | static int |
7f60e200 PZ |
4139 | skl_ddb_add_affected_planes(struct intel_crtc_state *cstate) |
4140 | { | |
4141 | struct drm_atomic_state *state = cstate->base.state; | |
4142 | struct drm_device *dev = state->dev; | |
4143 | struct drm_crtc *crtc = cstate->base.crtc; | |
4144 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4145 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4146 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4147 | struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
4148 | struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
4149 | struct drm_plane_state *plane_state; | |
4150 | struct drm_plane *plane; | |
4151 | enum pipe pipe = intel_crtc->pipe; | |
7f60e200 PZ |
4152 | |
4153 | WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc)); | |
4154 | ||
220b0965 | 4155 | drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) { |
d5cdfdf5 | 4156 | enum plane_id plane_id = to_intel_plane(plane)->id; |
7f60e200 | 4157 | |
d5cdfdf5 VS |
4158 | if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id], |
4159 | &new_ddb->plane[pipe][plane_id]) && | |
4160 | skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id], | |
4161 | &new_ddb->y_plane[pipe][plane_id])) | |
7f60e200 PZ |
4162 | continue; |
4163 | ||
4164 | plane_state = drm_atomic_get_plane_state(state, plane); | |
4165 | if (IS_ERR(plane_state)) | |
4166 | return PTR_ERR(plane_state); | |
4167 | } | |
4168 | ||
4169 | return 0; | |
4170 | } | |
4171 | ||
98d39494 MR |
4172 | static int |
4173 | skl_compute_ddb(struct drm_atomic_state *state) | |
4174 | { | |
4175 | struct drm_device *dev = state->dev; | |
4176 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4177 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4178 | struct intel_crtc *intel_crtc; | |
734fa01f | 4179 | struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb; |
9b613022 | 4180 | uint32_t realloc_pipes = pipes_modified(state); |
98d39494 MR |
4181 | int ret; |
4182 | ||
4183 | /* | |
4184 | * If this is our first atomic update following hardware readout, | |
4185 | * we can't trust the DDB that the BIOS programmed for us. Let's | |
4186 | * pretend that all pipes switched active status so that we'll | |
4187 | * ensure a full DDB recompute. | |
4188 | */ | |
1b54a880 MR |
4189 | if (dev_priv->wm.distrust_bios_wm) { |
4190 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, | |
4191 | state->acquire_ctx); | |
4192 | if (ret) | |
4193 | return ret; | |
4194 | ||
98d39494 MR |
4195 | intel_state->active_pipe_changes = ~0; |
4196 | ||
1b54a880 MR |
4197 | /* |
4198 | * We usually only initialize intel_state->active_crtcs if we | |
4199 | * we're doing a modeset; make sure this field is always | |
4200 | * initialized during the sanitization process that happens | |
4201 | * on the first commit too. | |
4202 | */ | |
4203 | if (!intel_state->modeset) | |
4204 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
4205 | } | |
4206 | ||
98d39494 MR |
4207 | /* |
4208 | * If the modeset changes which CRTC's are active, we need to | |
4209 | * recompute the DDB allocation for *all* active pipes, even | |
4210 | * those that weren't otherwise being modified in any way by this | |
4211 | * atomic commit. Due to the shrinking of the per-pipe allocations | |
4212 | * when new active CRTC's are added, it's possible for a pipe that | |
4213 | * we were already using and aren't changing at all here to suddenly | |
4214 | * become invalid if its DDB needs exceeds its new allocation. | |
4215 | * | |
4216 | * Note that if we wind up doing a full DDB recompute, we can't let | |
4217 | * any other display updates race with this transaction, so we need | |
4218 | * to grab the lock on *all* CRTC's. | |
4219 | */ | |
734fa01f | 4220 | if (intel_state->active_pipe_changes) { |
98d39494 | 4221 | realloc_pipes = ~0; |
734fa01f MR |
4222 | intel_state->wm_results.dirty_pipes = ~0; |
4223 | } | |
98d39494 | 4224 | |
5a920b85 PZ |
4225 | /* |
4226 | * We're not recomputing for the pipes not included in the commit, so | |
4227 | * make sure we start with the current state. | |
4228 | */ | |
4229 | memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); | |
4230 | ||
98d39494 MR |
4231 | for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { |
4232 | struct intel_crtc_state *cstate; | |
4233 | ||
4234 | cstate = intel_atomic_get_crtc_state(state, intel_crtc); | |
4235 | if (IS_ERR(cstate)) | |
4236 | return PTR_ERR(cstate); | |
4237 | ||
734fa01f | 4238 | ret = skl_allocate_pipe_ddb(cstate, ddb); |
98d39494 MR |
4239 | if (ret) |
4240 | return ret; | |
05a76d3d | 4241 | |
7f60e200 | 4242 | ret = skl_ddb_add_affected_planes(cstate); |
05a76d3d L |
4243 | if (ret) |
4244 | return ret; | |
98d39494 MR |
4245 | } |
4246 | ||
4247 | return 0; | |
4248 | } | |
4249 | ||
2722efb9 MR |
4250 | static void |
4251 | skl_copy_wm_for_pipe(struct skl_wm_values *dst, | |
4252 | struct skl_wm_values *src, | |
4253 | enum pipe pipe) | |
4254 | { | |
2722efb9 MR |
4255 | memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe], |
4256 | sizeof(dst->ddb.y_plane[pipe])); | |
4257 | memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe], | |
4258 | sizeof(dst->ddb.plane[pipe])); | |
4259 | } | |
4260 | ||
413fc530 | 4261 | static void |
4262 | skl_print_wm_changes(const struct drm_atomic_state *state) | |
4263 | { | |
4264 | const struct drm_device *dev = state->dev; | |
4265 | const struct drm_i915_private *dev_priv = to_i915(dev); | |
4266 | const struct intel_atomic_state *intel_state = | |
4267 | to_intel_atomic_state(state); | |
4268 | const struct drm_crtc *crtc; | |
4269 | const struct drm_crtc_state *cstate; | |
413fc530 | 4270 | const struct intel_plane *intel_plane; |
413fc530 | 4271 | const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; |
4272 | const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
7570498e | 4273 | int i; |
413fc530 | 4274 | |
6ebdb5a0 | 4275 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
7570498e ML |
4276 | const struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4277 | enum pipe pipe = intel_crtc->pipe; | |
413fc530 | 4278 | |
7570498e | 4279 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
d5cdfdf5 | 4280 | enum plane_id plane_id = intel_plane->id; |
413fc530 | 4281 | const struct skl_ddb_entry *old, *new; |
4282 | ||
d5cdfdf5 VS |
4283 | old = &old_ddb->plane[pipe][plane_id]; |
4284 | new = &new_ddb->plane[pipe][plane_id]; | |
413fc530 | 4285 | |
413fc530 | 4286 | if (skl_ddb_entry_equal(old, new)) |
4287 | continue; | |
4288 | ||
7570498e ML |
4289 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n", |
4290 | intel_plane->base.base.id, | |
4291 | intel_plane->base.name, | |
4292 | old->start, old->end, | |
4293 | new->start, new->end); | |
413fc530 | 4294 | } |
4295 | } | |
4296 | } | |
4297 | ||
98d39494 MR |
4298 | static int |
4299 | skl_compute_wm(struct drm_atomic_state *state) | |
4300 | { | |
4301 | struct drm_crtc *crtc; | |
4302 | struct drm_crtc_state *cstate; | |
734fa01f MR |
4303 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
4304 | struct skl_wm_values *results = &intel_state->wm_results; | |
4305 | struct skl_pipe_wm *pipe_wm; | |
98d39494 | 4306 | bool changed = false; |
734fa01f | 4307 | int ret, i; |
98d39494 MR |
4308 | |
4309 | /* | |
4310 | * If this transaction isn't actually touching any CRTC's, don't | |
4311 | * bother with watermark calculation. Note that if we pass this | |
4312 | * test, we're guaranteed to hold at least one CRTC state mutex, | |
4313 | * which means we can safely use values like dev_priv->active_crtcs | |
4314 | * since any racing commits that want to update them would need to | |
4315 | * hold _all_ CRTC state mutexes. | |
4316 | */ | |
6ebdb5a0 | 4317 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
98d39494 MR |
4318 | changed = true; |
4319 | if (!changed) | |
4320 | return 0; | |
4321 | ||
734fa01f MR |
4322 | /* Clear all dirty flags */ |
4323 | results->dirty_pipes = 0; | |
4324 | ||
98d39494 MR |
4325 | ret = skl_compute_ddb(state); |
4326 | if (ret) | |
4327 | return ret; | |
4328 | ||
734fa01f MR |
4329 | /* |
4330 | * Calculate WM's for all pipes that are part of this transaction. | |
4331 | * Note that the DDB allocation above may have added more CRTC's that | |
4332 | * weren't otherwise being modified (and set bits in dirty_pipes) if | |
4333 | * pipe allocations had to change. | |
4334 | * | |
4335 | * FIXME: Now that we're doing this in the atomic check phase, we | |
4336 | * should allow skl_update_pipe_wm() to return failure in cases where | |
4337 | * no suitable watermark values can be found. | |
4338 | */ | |
6ebdb5a0 | 4339 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
734fa01f MR |
4340 | struct intel_crtc_state *intel_cstate = |
4341 | to_intel_crtc_state(cstate); | |
03af79e0 ML |
4342 | const struct skl_pipe_wm *old_pipe_wm = |
4343 | &to_intel_crtc_state(crtc->state)->wm.skl.optimal; | |
734fa01f MR |
4344 | |
4345 | pipe_wm = &intel_cstate->wm.skl.optimal; | |
03af79e0 ML |
4346 | ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, |
4347 | &results->ddb, &changed); | |
734fa01f MR |
4348 | if (ret) |
4349 | return ret; | |
4350 | ||
4351 | if (changed) | |
4352 | results->dirty_pipes |= drm_crtc_mask(crtc); | |
4353 | ||
4354 | if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0) | |
4355 | /* This pipe's WM's did not change */ | |
4356 | continue; | |
4357 | ||
4358 | intel_cstate->update_wm_pre = true; | |
734fa01f MR |
4359 | } |
4360 | ||
413fc530 | 4361 | skl_print_wm_changes(state); |
4362 | ||
98d39494 MR |
4363 | return 0; |
4364 | } | |
4365 | ||
ccf010fb ML |
4366 | static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, |
4367 | struct intel_crtc_state *cstate) | |
4368 | { | |
4369 | struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); | |
4370 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
4371 | struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal; | |
e62929b3 | 4372 | const struct skl_ddb_allocation *ddb = &state->wm_results.ddb; |
ccf010fb | 4373 | enum pipe pipe = crtc->pipe; |
d5cdfdf5 | 4374 | enum plane_id plane_id; |
e62929b3 ML |
4375 | |
4376 | if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base))) | |
4377 | return; | |
ccf010fb ML |
4378 | |
4379 | I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); | |
e62929b3 | 4380 | |
d5cdfdf5 VS |
4381 | for_each_plane_id_on_crtc(crtc, plane_id) { |
4382 | if (plane_id != PLANE_CURSOR) | |
4383 | skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id], | |
4384 | ddb, plane_id); | |
4385 | else | |
4386 | skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id], | |
4387 | ddb); | |
4388 | } | |
ccf010fb ML |
4389 | } |
4390 | ||
e62929b3 ML |
4391 | static void skl_initial_wm(struct intel_atomic_state *state, |
4392 | struct intel_crtc_state *cstate) | |
2d41c0b5 | 4393 | { |
e62929b3 | 4394 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
432081bc | 4395 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4396 | struct drm_i915_private *dev_priv = to_i915(dev); |
e62929b3 | 4397 | struct skl_wm_values *results = &state->wm_results; |
2722efb9 | 4398 | struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw; |
27082493 | 4399 | enum pipe pipe = intel_crtc->pipe; |
adda50b8 | 4400 | |
432081bc | 4401 | if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0) |
2d41c0b5 PB |
4402 | return; |
4403 | ||
734fa01f | 4404 | mutex_lock(&dev_priv->wm.wm_mutex); |
2d41c0b5 | 4405 | |
e62929b3 ML |
4406 | if (cstate->base.active_changed) |
4407 | skl_atomic_update_crtc_wm(state, cstate); | |
27082493 L |
4408 | |
4409 | skl_copy_wm_for_pipe(hw_vals, results, pipe); | |
734fa01f MR |
4410 | |
4411 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2d41c0b5 PB |
4412 | } |
4413 | ||
d890565c VS |
4414 | static void ilk_compute_wm_config(struct drm_device *dev, |
4415 | struct intel_wm_config *config) | |
4416 | { | |
4417 | struct intel_crtc *crtc; | |
4418 | ||
4419 | /* Compute the currently _active_ config */ | |
4420 | for_each_intel_crtc(dev, crtc) { | |
4421 | const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; | |
4422 | ||
4423 | if (!wm->pipe_enabled) | |
4424 | continue; | |
4425 | ||
4426 | config->sprites_enabled |= wm->sprites_enabled; | |
4427 | config->sprites_scaled |= wm->sprites_scaled; | |
4428 | config->num_pipes_active++; | |
4429 | } | |
4430 | } | |
4431 | ||
ed4a6a7c | 4432 | static void ilk_program_watermarks(struct drm_i915_private *dev_priv) |
801bcfff | 4433 | { |
91c8a326 | 4434 | struct drm_device *dev = &dev_priv->drm; |
b9d5c839 | 4435 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
820c1980 | 4436 | struct ilk_wm_maximums max; |
d890565c | 4437 | struct intel_wm_config config = {}; |
820c1980 | 4438 | struct ilk_wm_values results = {}; |
77c122bc | 4439 | enum intel_ddb_partitioning partitioning; |
261a27d1 | 4440 | |
d890565c VS |
4441 | ilk_compute_wm_config(dev, &config); |
4442 | ||
4443 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); | |
4444 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); | |
a485bfb8 VS |
4445 | |
4446 | /* 5/6 split only in single pipe config on IVB+ */ | |
175fded1 | 4447 | if (INTEL_GEN(dev_priv) >= 7 && |
d890565c VS |
4448 | config.num_pipes_active == 1 && config.sprites_enabled) { |
4449 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); | |
4450 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); | |
0362c781 | 4451 | |
820c1980 | 4452 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 4453 | } else { |
198a1e9b | 4454 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
4455 | } |
4456 | ||
198a1e9b | 4457 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 4458 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 4459 | |
820c1980 | 4460 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 4461 | |
820c1980 | 4462 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
4463 | } |
4464 | ||
ccf010fb ML |
4465 | static void ilk_initial_watermarks(struct intel_atomic_state *state, |
4466 | struct intel_crtc_state *cstate) | |
b9d5c839 | 4467 | { |
ed4a6a7c MR |
4468 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); |
4469 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
b9d5c839 | 4470 | |
ed4a6a7c | 4471 | mutex_lock(&dev_priv->wm.wm_mutex); |
e8f1f02e | 4472 | intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate; |
ed4a6a7c MR |
4473 | ilk_program_watermarks(dev_priv); |
4474 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
4475 | } | |
bf220452 | 4476 | |
ccf010fb ML |
4477 | static void ilk_optimize_watermarks(struct intel_atomic_state *state, |
4478 | struct intel_crtc_state *cstate) | |
ed4a6a7c MR |
4479 | { |
4480 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); | |
4481 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
bf220452 | 4482 | |
ed4a6a7c MR |
4483 | mutex_lock(&dev_priv->wm.wm_mutex); |
4484 | if (cstate->wm.need_postvbl_update) { | |
e8f1f02e | 4485 | intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal; |
ed4a6a7c MR |
4486 | ilk_program_watermarks(dev_priv); |
4487 | } | |
4488 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
b9d5c839 VS |
4489 | } |
4490 | ||
d8c0fafc | 4491 | static inline void skl_wm_level_from_reg_val(uint32_t val, |
4492 | struct skl_wm_level *level) | |
3078999f | 4493 | { |
d8c0fafc | 4494 | level->plane_en = val & PLANE_WM_EN; |
4495 | level->plane_res_b = val & PLANE_WM_BLOCKS_MASK; | |
4496 | level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) & | |
4497 | PLANE_WM_LINES_MASK; | |
3078999f PB |
4498 | } |
4499 | ||
bf9d99ad | 4500 | void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, |
4501 | struct skl_pipe_wm *out) | |
3078999f | 4502 | { |
d5cdfdf5 | 4503 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
3078999f | 4504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3078999f | 4505 | enum pipe pipe = intel_crtc->pipe; |
d5cdfdf5 VS |
4506 | int level, max_level; |
4507 | enum plane_id plane_id; | |
d8c0fafc | 4508 | uint32_t val; |
3078999f | 4509 | |
5db94019 | 4510 | max_level = ilk_wm_max_level(dev_priv); |
3078999f | 4511 | |
d5cdfdf5 VS |
4512 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
4513 | struct skl_plane_wm *wm = &out->planes[plane_id]; | |
3078999f | 4514 | |
d8c0fafc | 4515 | for (level = 0; level <= max_level; level++) { |
d5cdfdf5 VS |
4516 | if (plane_id != PLANE_CURSOR) |
4517 | val = I915_READ(PLANE_WM(pipe, plane_id, level)); | |
d8c0fafc | 4518 | else |
4519 | val = I915_READ(CUR_WM(pipe, level)); | |
3078999f | 4520 | |
d8c0fafc | 4521 | skl_wm_level_from_reg_val(val, &wm->wm[level]); |
3078999f | 4522 | } |
3078999f | 4523 | |
d5cdfdf5 VS |
4524 | if (plane_id != PLANE_CURSOR) |
4525 | val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); | |
d8c0fafc | 4526 | else |
4527 | val = I915_READ(CUR_WM_TRANS(pipe)); | |
4528 | ||
4529 | skl_wm_level_from_reg_val(val, &wm->trans_wm); | |
3078999f PB |
4530 | } |
4531 | ||
d8c0fafc | 4532 | if (!intel_crtc->active) |
4533 | return; | |
4e0963c7 | 4534 | |
bf9d99ad | 4535 | out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); |
3078999f PB |
4536 | } |
4537 | ||
4538 | void skl_wm_get_hw_state(struct drm_device *dev) | |
4539 | { | |
fac5e23e | 4540 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf9d99ad | 4541 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
a269c583 | 4542 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
3078999f | 4543 | struct drm_crtc *crtc; |
bf9d99ad | 4544 | struct intel_crtc *intel_crtc; |
4545 | struct intel_crtc_state *cstate; | |
3078999f | 4546 | |
a269c583 | 4547 | skl_ddb_get_hw_state(dev_priv, ddb); |
bf9d99ad | 4548 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
4549 | intel_crtc = to_intel_crtc(crtc); | |
4550 | cstate = to_intel_crtc_state(crtc->state); | |
4551 | ||
4552 | skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal); | |
4553 | ||
03af79e0 | 4554 | if (intel_crtc->active) |
bf9d99ad | 4555 | hw->dirty_pipes |= drm_crtc_mask(crtc); |
bf9d99ad | 4556 | } |
a1de91e5 | 4557 | |
279e99d7 MR |
4558 | if (dev_priv->active_crtcs) { |
4559 | /* Fully recompute DDB on first atomic commit */ | |
4560 | dev_priv->wm.distrust_bios_wm = true; | |
4561 | } else { | |
4562 | /* Easy/common case; just sanitize DDB now if everything off */ | |
4563 | memset(ddb, 0, sizeof(*ddb)); | |
4564 | } | |
3078999f PB |
4565 | } |
4566 | ||
243e6a44 VS |
4567 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
4568 | { | |
4569 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4570 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 4571 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 | 4572 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4e0963c7 | 4573 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
e8f1f02e | 4574 | struct intel_pipe_wm *active = &cstate->wm.ilk.optimal; |
243e6a44 | 4575 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 | 4576 | static const i915_reg_t wm0_pipe_reg[] = { |
243e6a44 VS |
4577 | [PIPE_A] = WM0_PIPEA_ILK, |
4578 | [PIPE_B] = WM0_PIPEB_ILK, | |
4579 | [PIPE_C] = WM0_PIPEC_IVB, | |
4580 | }; | |
4581 | ||
4582 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
8652744b | 4583 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ce0e0713 | 4584 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 4585 | |
15606534 VS |
4586 | memset(active, 0, sizeof(*active)); |
4587 | ||
3ef00284 | 4588 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
4589 | |
4590 | if (active->pipe_enabled) { | |
243e6a44 VS |
4591 | u32 tmp = hw->wm_pipe[pipe]; |
4592 | ||
4593 | /* | |
4594 | * For active pipes LP0 watermark is marked as | |
4595 | * enabled, and LP1+ watermaks as disabled since | |
4596 | * we can't really reverse compute them in case | |
4597 | * multiple pipes are active. | |
4598 | */ | |
4599 | active->wm[0].enable = true; | |
4600 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
4601 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
4602 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
4603 | active->linetime = hw->wm_linetime[pipe]; | |
4604 | } else { | |
5db94019 | 4605 | int level, max_level = ilk_wm_max_level(dev_priv); |
243e6a44 VS |
4606 | |
4607 | /* | |
4608 | * For inactive pipes, all watermark levels | |
4609 | * should be marked as enabled but zeroed, | |
4610 | * which is what we'd compute them to. | |
4611 | */ | |
4612 | for (level = 0; level <= max_level; level++) | |
4613 | active->wm[level].enable = true; | |
4614 | } | |
4e0963c7 MR |
4615 | |
4616 | intel_crtc->wm.active.ilk = *active; | |
243e6a44 VS |
4617 | } |
4618 | ||
6eb1a681 VS |
4619 | #define _FW_WM(value, plane) \ |
4620 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) | |
4621 | #define _FW_WM_VLV(value, plane) \ | |
4622 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) | |
4623 | ||
4624 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, | |
4625 | struct vlv_wm_values *wm) | |
4626 | { | |
4627 | enum pipe pipe; | |
4628 | uint32_t tmp; | |
4629 | ||
4630 | for_each_pipe(dev_priv, pipe) { | |
4631 | tmp = I915_READ(VLV_DDL(pipe)); | |
4632 | ||
1b31389c | 4633 | wm->ddl[pipe].plane[PLANE_PRIMARY] = |
6eb1a681 | 4634 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 4635 | wm->ddl[pipe].plane[PLANE_CURSOR] = |
6eb1a681 | 4636 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 4637 | wm->ddl[pipe].plane[PLANE_SPRITE0] = |
6eb1a681 | 4638 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 4639 | wm->ddl[pipe].plane[PLANE_SPRITE1] = |
6eb1a681 VS |
4640 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
4641 | } | |
4642 | ||
4643 | tmp = I915_READ(DSPFW1); | |
4644 | wm->sr.plane = _FW_WM(tmp, SR); | |
1b31389c VS |
4645 | wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); |
4646 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); | |
4647 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); | |
6eb1a681 VS |
4648 | |
4649 | tmp = I915_READ(DSPFW2); | |
1b31389c VS |
4650 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); |
4651 | wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); | |
4652 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); | |
6eb1a681 VS |
4653 | |
4654 | tmp = I915_READ(DSPFW3); | |
4655 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
4656 | ||
4657 | if (IS_CHERRYVIEW(dev_priv)) { | |
4658 | tmp = I915_READ(DSPFW7_CHV); | |
1b31389c VS |
4659 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
4660 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
4661 | |
4662 | tmp = I915_READ(DSPFW8_CHV); | |
1b31389c VS |
4663 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); |
4664 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); | |
6eb1a681 VS |
4665 | |
4666 | tmp = I915_READ(DSPFW9_CHV); | |
1b31389c VS |
4667 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); |
4668 | wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); | |
6eb1a681 VS |
4669 | |
4670 | tmp = I915_READ(DSPHOWM); | |
4671 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
4672 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; |
4673 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; | |
4674 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; | |
4675 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
4676 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
4677 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
4678 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
4679 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
4680 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
4681 | } else { |
4682 | tmp = I915_READ(DSPFW7); | |
1b31389c VS |
4683 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
4684 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
4685 | |
4686 | tmp = I915_READ(DSPHOWM); | |
4687 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
4688 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
4689 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
4690 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
4691 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
4692 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
4693 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
4694 | } |
4695 | } | |
4696 | ||
4697 | #undef _FW_WM | |
4698 | #undef _FW_WM_VLV | |
4699 | ||
4700 | void vlv_wm_get_hw_state(struct drm_device *dev) | |
4701 | { | |
4702 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4703 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; | |
f07d43d2 | 4704 | struct intel_crtc *crtc; |
6eb1a681 VS |
4705 | u32 val; |
4706 | ||
4707 | vlv_read_wm_values(dev_priv, wm); | |
4708 | ||
6eb1a681 VS |
4709 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
4710 | wm->level = VLV_WM_LEVEL_PM2; | |
4711 | ||
4712 | if (IS_CHERRYVIEW(dev_priv)) { | |
4713 | mutex_lock(&dev_priv->rps.hw_lock); | |
4714 | ||
4715 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4716 | if (val & DSP_MAXFIFO_PM5_ENABLE) | |
4717 | wm->level = VLV_WM_LEVEL_PM5; | |
4718 | ||
58590c14 VS |
4719 | /* |
4720 | * If DDR DVFS is disabled in the BIOS, Punit | |
4721 | * will never ack the request. So if that happens | |
4722 | * assume we don't have to enable/disable DDR DVFS | |
4723 | * dynamically. To test that just set the REQ_ACK | |
4724 | * bit to poke the Punit, but don't change the | |
4725 | * HIGH/LOW bits so that we don't actually change | |
4726 | * the current state. | |
4727 | */ | |
6eb1a681 | 4728 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
58590c14 VS |
4729 | val |= FORCE_DDR_FREQ_REQ_ACK; |
4730 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
4731 | ||
4732 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
4733 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { | |
4734 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " | |
4735 | "assuming DDR DVFS is disabled\n"); | |
4736 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; | |
4737 | } else { | |
4738 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
4739 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) | |
4740 | wm->level = VLV_WM_LEVEL_DDR_DVFS; | |
4741 | } | |
6eb1a681 VS |
4742 | |
4743 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4744 | } | |
4745 | ||
ff32c54e VS |
4746 | for_each_intel_crtc(dev, crtc) { |
4747 | struct intel_crtc_state *crtc_state = | |
4748 | to_intel_crtc_state(crtc->base.state); | |
4749 | struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
4750 | const struct vlv_fifo_state *fifo_state = | |
4751 | &crtc_state->wm.vlv.fifo_state; | |
4752 | enum pipe pipe = crtc->pipe; | |
4753 | enum plane_id plane_id; | |
4754 | int level; | |
4755 | ||
4756 | vlv_get_fifo_size(crtc_state); | |
4757 | ||
4758 | active->num_levels = wm->level + 1; | |
4759 | active->cxsr = wm->cxsr; | |
4760 | ||
ff32c54e VS |
4761 | for (level = 0; level < active->num_levels; level++) { |
4762 | struct vlv_pipe_wm *raw = | |
4763 | &crtc_state->wm.vlv.raw[level]; | |
4764 | ||
4765 | active->sr[level].plane = wm->sr.plane; | |
4766 | active->sr[level].cursor = wm->sr.cursor; | |
4767 | ||
4768 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
4769 | active->wm[level].plane[plane_id] = | |
4770 | wm->pipe[pipe].plane[plane_id]; | |
4771 | ||
4772 | raw->plane[plane_id] = | |
4773 | vlv_invert_wm_value(active->wm[level].plane[plane_id], | |
4774 | fifo_state->plane[plane_id]); | |
4775 | } | |
4776 | } | |
4777 | ||
4778 | for_each_plane_id_on_crtc(crtc, plane_id) | |
4779 | vlv_raw_plane_wm_set(crtc_state, level, | |
4780 | plane_id, USHRT_MAX); | |
4781 | vlv_invalidate_wms(crtc, active, level); | |
4782 | ||
4783 | crtc_state->wm.vlv.optimal = *active; | |
4841da51 | 4784 | crtc_state->wm.vlv.intermediate = *active; |
ff32c54e | 4785 | |
6eb1a681 | 4786 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", |
1b31389c VS |
4787 | pipe_name(pipe), |
4788 | wm->pipe[pipe].plane[PLANE_PRIMARY], | |
4789 | wm->pipe[pipe].plane[PLANE_CURSOR], | |
4790 | wm->pipe[pipe].plane[PLANE_SPRITE0], | |
4791 | wm->pipe[pipe].plane[PLANE_SPRITE1]); | |
ff32c54e | 4792 | } |
6eb1a681 VS |
4793 | |
4794 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", | |
4795 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); | |
4796 | } | |
4797 | ||
602ae835 VS |
4798 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv) |
4799 | { | |
4800 | struct intel_plane *plane; | |
4801 | struct intel_crtc *crtc; | |
4802 | ||
4803 | mutex_lock(&dev_priv->wm.wm_mutex); | |
4804 | ||
4805 | for_each_intel_plane(&dev_priv->drm, plane) { | |
4806 | struct intel_crtc *crtc = | |
4807 | intel_get_crtc_for_pipe(dev_priv, plane->pipe); | |
4808 | struct intel_crtc_state *crtc_state = | |
4809 | to_intel_crtc_state(crtc->base.state); | |
4810 | struct intel_plane_state *plane_state = | |
4811 | to_intel_plane_state(plane->base.state); | |
4812 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
4813 | const struct vlv_fifo_state *fifo_state = | |
4814 | &crtc_state->wm.vlv.fifo_state; | |
4815 | enum plane_id plane_id = plane->id; | |
4816 | int level; | |
4817 | ||
4818 | if (plane_state->base.visible) | |
4819 | continue; | |
4820 | ||
4821 | for (level = 0; level < wm_state->num_levels; level++) { | |
4822 | struct vlv_pipe_wm *raw = | |
4823 | &crtc_state->wm.vlv.raw[level]; | |
4824 | ||
4825 | raw->plane[plane_id] = 0; | |
4826 | ||
4827 | wm_state->wm[level].plane[plane_id] = | |
4828 | vlv_invert_wm_value(raw->plane[plane_id], | |
4829 | fifo_state->plane[plane_id]); | |
4830 | } | |
4831 | } | |
4832 | ||
4833 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
4834 | struct intel_crtc_state *crtc_state = | |
4835 | to_intel_crtc_state(crtc->base.state); | |
4836 | ||
4837 | crtc_state->wm.vlv.intermediate = | |
4838 | crtc_state->wm.vlv.optimal; | |
4839 | crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
4840 | } | |
4841 | ||
4842 | vlv_program_watermarks(dev_priv); | |
4843 | ||
4844 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
4845 | } | |
4846 | ||
243e6a44 VS |
4847 | void ilk_wm_get_hw_state(struct drm_device *dev) |
4848 | { | |
fac5e23e | 4849 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 4850 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
4851 | struct drm_crtc *crtc; |
4852 | ||
70e1e0ec | 4853 | for_each_crtc(dev, crtc) |
243e6a44 VS |
4854 | ilk_pipe_wm_get_hw_state(crtc); |
4855 | ||
4856 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
4857 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
4858 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
4859 | ||
4860 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
175fded1 | 4861 | if (INTEL_GEN(dev_priv) >= 7) { |
cfa7698b VS |
4862 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
4863 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
4864 | } | |
243e6a44 | 4865 | |
8652744b | 4866 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ac9545fd VS |
4867 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
4868 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
fd6b8f43 | 4869 | else if (IS_IVYBRIDGE(dev_priv)) |
ac9545fd VS |
4870 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
4871 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
4872 | |
4873 | hw->enable_fbc_wm = | |
4874 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
4875 | } | |
4876 | ||
b445e3b0 ED |
4877 | /** |
4878 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4879 | * | |
4880 | * Calculate watermark values for the various WM regs based on current mode | |
4881 | * and plane configuration. | |
4882 | * | |
4883 | * There are several cases to deal with here: | |
4884 | * - normal (i.e. non-self-refresh) | |
4885 | * - self-refresh (SR) mode | |
4886 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4887 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4888 | * lines), so need to account for TLB latency | |
4889 | * | |
4890 | * The normal calculation is: | |
4891 | * watermark = dotclock * bytes per pixel * latency | |
4892 | * where latency is platform & configuration dependent (we assume pessimal | |
4893 | * values here). | |
4894 | * | |
4895 | * The SR calculation is: | |
4896 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4897 | * bytes per pixel | |
4898 | * where | |
4899 | * line time = htotal / dotclock | |
4900 | * surface width = hdisplay for normal plane and 64 for cursor | |
4901 | * and latency is assumed to be high, as above. | |
4902 | * | |
4903 | * The final value programmed to the register should always be rounded up, | |
4904 | * and include an extra 2 entries to account for clock crossings. | |
4905 | * | |
4906 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4907 | * to set the non-SR watermarks to 8. | |
4908 | */ | |
432081bc | 4909 | void intel_update_watermarks(struct intel_crtc *crtc) |
b445e3b0 | 4910 | { |
432081bc | 4911 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b445e3b0 ED |
4912 | |
4913 | if (dev_priv->display.update_wm) | |
46ba614c | 4914 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
4915 | } |
4916 | ||
e2828914 | 4917 | /* |
9270388e | 4918 | * Lock protecting IPS related data structures |
9270388e DV |
4919 | */ |
4920 | DEFINE_SPINLOCK(mchdev_lock); | |
4921 | ||
4922 | /* Global for IPS driver to get at the current i915 device. Protected by | |
4923 | * mchdev_lock. */ | |
4924 | static struct drm_i915_private *i915_mch_dev; | |
4925 | ||
91d14251 | 4926 | bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 4927 | { |
2b4e57bd ED |
4928 | u16 rgvswctl; |
4929 | ||
67520415 | 4930 | lockdep_assert_held(&mchdev_lock); |
9270388e | 4931 | |
2b4e57bd ED |
4932 | rgvswctl = I915_READ16(MEMSWCTL); |
4933 | if (rgvswctl & MEMCTL_CMD_STS) { | |
4934 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
4935 | return false; /* still busy with another command */ | |
4936 | } | |
4937 | ||
4938 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
4939 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
4940 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
4941 | POSTING_READ16(MEMSWCTL); | |
4942 | ||
4943 | rgvswctl |= MEMCTL_CMD_STS; | |
4944 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
4945 | ||
4946 | return true; | |
4947 | } | |
4948 | ||
91d14251 | 4949 | static void ironlake_enable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 4950 | { |
84f1b20f | 4951 | u32 rgvmodectl; |
2b4e57bd ED |
4952 | u8 fmax, fmin, fstart, vstart; |
4953 | ||
9270388e DV |
4954 | spin_lock_irq(&mchdev_lock); |
4955 | ||
84f1b20f TU |
4956 | rgvmodectl = I915_READ(MEMMODECTL); |
4957 | ||
2b4e57bd ED |
4958 | /* Enable temp reporting */ |
4959 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
4960 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
4961 | ||
4962 | /* 100ms RC evaluation intervals */ | |
4963 | I915_WRITE(RCUPEI, 100000); | |
4964 | I915_WRITE(RCDNEI, 100000); | |
4965 | ||
4966 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
4967 | I915_WRITE(RCBMAXAVG, 90000); | |
4968 | I915_WRITE(RCBMINAVG, 80000); | |
4969 | ||
4970 | I915_WRITE(MEMIHYST, 1); | |
4971 | ||
4972 | /* Set up min, max, and cur for interrupt handling */ | |
4973 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
4974 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
4975 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
4976 | MEMMODE_FSTART_SHIFT; | |
4977 | ||
616847e7 | 4978 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
2b4e57bd ED |
4979 | PXVFREQ_PX_SHIFT; |
4980 | ||
20e4d407 DV |
4981 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
4982 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 4983 | |
20e4d407 DV |
4984 | dev_priv->ips.max_delay = fstart; |
4985 | dev_priv->ips.min_delay = fmin; | |
4986 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
4987 | |
4988 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
4989 | fmax, fmin, fstart); | |
4990 | ||
4991 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
4992 | ||
4993 | /* | |
4994 | * Interrupts will be enabled in ironlake_irq_postinstall | |
4995 | */ | |
4996 | ||
4997 | I915_WRITE(VIDSTART, vstart); | |
4998 | POSTING_READ(VIDSTART); | |
4999 | ||
5000 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5001 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5002 | ||
9270388e | 5003 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 5004 | DRM_ERROR("stuck trying to change perf mode\n"); |
dd92d8de | 5005 | mdelay(1); |
2b4e57bd | 5006 | |
91d14251 | 5007 | ironlake_set_drps(dev_priv, fstart); |
2b4e57bd | 5008 | |
7d81c3e0 VS |
5009 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
5010 | I915_READ(DDREC) + I915_READ(CSIEC); | |
20e4d407 | 5011 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
7d81c3e0 | 5012 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
5ed0bdf2 | 5013 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
5014 | |
5015 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
5016 | } |
5017 | ||
91d14251 | 5018 | static void ironlake_disable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5019 | { |
9270388e DV |
5020 | u16 rgvswctl; |
5021 | ||
5022 | spin_lock_irq(&mchdev_lock); | |
5023 | ||
5024 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
5025 | |
5026 | /* Ack interrupts, disable EFC interrupt */ | |
5027 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5028 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5029 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5030 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5031 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5032 | ||
5033 | /* Go back to the starting frequency */ | |
91d14251 | 5034 | ironlake_set_drps(dev_priv, dev_priv->ips.fstart); |
dd92d8de | 5035 | mdelay(1); |
2b4e57bd ED |
5036 | rgvswctl |= MEMCTL_CMD_STS; |
5037 | I915_WRITE(MEMSWCTL, rgvswctl); | |
dd92d8de | 5038 | mdelay(1); |
2b4e57bd | 5039 | |
9270388e | 5040 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
5041 | } |
5042 | ||
acbe9475 DV |
5043 | /* There's a funny hw issue where the hw returns all 0 when reading from |
5044 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
5045 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
5046 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
5047 | */ | |
74ef1173 | 5048 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 5049 | { |
7b9e0ae6 | 5050 | u32 limits; |
2b4e57bd | 5051 | |
20b46e59 DV |
5052 | /* Only set the down limit when we've reached the lowest level to avoid |
5053 | * getting more interrupts, otherwise leave this clear. This prevents a | |
5054 | * race in the hw when coming out of rc6: There's a tiny window where | |
5055 | * the hw runs at the minimal clock before selecting the desired | |
5056 | * frequency, if the down threshold expires in that window we will not | |
5057 | * receive a down interrupt. */ | |
2d1fe073 | 5058 | if (IS_GEN9(dev_priv)) { |
74ef1173 AG |
5059 | limits = (dev_priv->rps.max_freq_softlimit) << 23; |
5060 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5061 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; | |
5062 | } else { | |
5063 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
5064 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5065 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
5066 | } | |
20b46e59 DV |
5067 | |
5068 | return limits; | |
5069 | } | |
5070 | ||
dd75fdc8 CW |
5071 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
5072 | { | |
5073 | int new_power; | |
8a586437 AG |
5074 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
5075 | u32 ei_up = 0, ei_down = 0; | |
dd75fdc8 CW |
5076 | |
5077 | new_power = dev_priv->rps.power; | |
5078 | switch (dev_priv->rps.power) { | |
5079 | case LOW_POWER: | |
a72b5623 CW |
5080 | if (val > dev_priv->rps.efficient_freq + 1 && |
5081 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5082 | new_power = BETWEEN; |
5083 | break; | |
5084 | ||
5085 | case BETWEEN: | |
a72b5623 CW |
5086 | if (val <= dev_priv->rps.efficient_freq && |
5087 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 | 5088 | new_power = LOW_POWER; |
a72b5623 CW |
5089 | else if (val >= dev_priv->rps.rp0_freq && |
5090 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5091 | new_power = HIGH_POWER; |
5092 | break; | |
5093 | ||
5094 | case HIGH_POWER: | |
a72b5623 CW |
5095 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && |
5096 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5097 | new_power = BETWEEN; |
5098 | break; | |
5099 | } | |
5100 | /* Max/min bins are special */ | |
aed242ff | 5101 | if (val <= dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 5102 | new_power = LOW_POWER; |
aed242ff | 5103 | if (val >= dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
5104 | new_power = HIGH_POWER; |
5105 | if (new_power == dev_priv->rps.power) | |
5106 | return; | |
5107 | ||
5108 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
5109 | switch (new_power) { | |
5110 | case LOW_POWER: | |
5111 | /* Upclock if more than 95% busy over 16ms */ | |
8a586437 AG |
5112 | ei_up = 16000; |
5113 | threshold_up = 95; | |
dd75fdc8 CW |
5114 | |
5115 | /* Downclock if less than 85% busy over 32ms */ | |
8a586437 AG |
5116 | ei_down = 32000; |
5117 | threshold_down = 85; | |
dd75fdc8 CW |
5118 | break; |
5119 | ||
5120 | case BETWEEN: | |
5121 | /* Upclock if more than 90% busy over 13ms */ | |
8a586437 AG |
5122 | ei_up = 13000; |
5123 | threshold_up = 90; | |
dd75fdc8 CW |
5124 | |
5125 | /* Downclock if less than 75% busy over 32ms */ | |
8a586437 AG |
5126 | ei_down = 32000; |
5127 | threshold_down = 75; | |
dd75fdc8 CW |
5128 | break; |
5129 | ||
5130 | case HIGH_POWER: | |
5131 | /* Upclock if more than 85% busy over 10ms */ | |
8a586437 AG |
5132 | ei_up = 10000; |
5133 | threshold_up = 85; | |
dd75fdc8 CW |
5134 | |
5135 | /* Downclock if less than 60% busy over 32ms */ | |
8a586437 AG |
5136 | ei_down = 32000; |
5137 | threshold_down = 60; | |
dd75fdc8 CW |
5138 | break; |
5139 | } | |
5140 | ||
6067a27d MK |
5141 | /* When byt can survive without system hang with dynamic |
5142 | * sw freq adjustments, this restriction can be lifted. | |
5143 | */ | |
5144 | if (IS_VALLEYVIEW(dev_priv)) | |
5145 | goto skip_hw_write; | |
5146 | ||
8a586437 | 5147 | I915_WRITE(GEN6_RP_UP_EI, |
a72b5623 | 5148 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
8a586437 | 5149 | I915_WRITE(GEN6_RP_UP_THRESHOLD, |
a72b5623 CW |
5150 | GT_INTERVAL_FROM_US(dev_priv, |
5151 | ei_up * threshold_up / 100)); | |
8a586437 AG |
5152 | |
5153 | I915_WRITE(GEN6_RP_DOWN_EI, | |
a72b5623 | 5154 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); |
8a586437 | 5155 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, |
a72b5623 CW |
5156 | GT_INTERVAL_FROM_US(dev_priv, |
5157 | ei_down * threshold_down / 100)); | |
5158 | ||
5159 | I915_WRITE(GEN6_RP_CONTROL, | |
5160 | GEN6_RP_MEDIA_TURBO | | |
5161 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5162 | GEN6_RP_MEDIA_IS_GFX | | |
5163 | GEN6_RP_ENABLE | | |
5164 | GEN6_RP_UP_BUSY_AVG | | |
5165 | GEN6_RP_DOWN_IDLE_AVG); | |
8a586437 | 5166 | |
6067a27d | 5167 | skip_hw_write: |
dd75fdc8 | 5168 | dev_priv->rps.power = new_power; |
8fb55197 CW |
5169 | dev_priv->rps.up_threshold = threshold_up; |
5170 | dev_priv->rps.down_threshold = threshold_down; | |
dd75fdc8 CW |
5171 | dev_priv->rps.last_adj = 0; |
5172 | } | |
5173 | ||
2876ce73 CW |
5174 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
5175 | { | |
5176 | u32 mask = 0; | |
5177 | ||
e0e8c7cb | 5178 | /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ |
2876ce73 | 5179 | if (val > dev_priv->rps.min_freq_softlimit) |
e0e8c7cb | 5180 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
2876ce73 | 5181 | if (val < dev_priv->rps.max_freq_softlimit) |
6f4b12f8 | 5182 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
2876ce73 | 5183 | |
7b3c29f6 CW |
5184 | mask &= dev_priv->pm_rps_events; |
5185 | ||
59d02a1f | 5186 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
5187 | } |
5188 | ||
b8a5ff8d JM |
5189 | /* gen6_set_rps is called to update the frequency request, but should also be |
5190 | * called when the range (min_delay and max_delay) is modified so that we can | |
5191 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
9fcee2f7 | 5192 | static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) |
20b46e59 | 5193 | { |
eb64cad1 CW |
5194 | /* min/max delay may still have been modified so be sure to |
5195 | * write the limits value. | |
5196 | */ | |
5197 | if (val != dev_priv->rps.cur_freq) { | |
5198 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 5199 | |
dc97997a | 5200 | if (IS_GEN9(dev_priv)) |
5704195c AG |
5201 | I915_WRITE(GEN6_RPNSWREQ, |
5202 | GEN9_FREQUENCY(val)); | |
dc97997a | 5203 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
eb64cad1 CW |
5204 | I915_WRITE(GEN6_RPNSWREQ, |
5205 | HSW_FREQUENCY(val)); | |
5206 | else | |
5207 | I915_WRITE(GEN6_RPNSWREQ, | |
5208 | GEN6_FREQUENCY(val) | | |
5209 | GEN6_OFFSET(0) | | |
5210 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 5211 | } |
7b9e0ae6 | 5212 | |
7b9e0ae6 CW |
5213 | /* Make sure we continue to get interrupts |
5214 | * until we hit the minimum or maximum frequencies. | |
5215 | */ | |
74ef1173 | 5216 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
2876ce73 | 5217 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 5218 | |
b39fb297 | 5219 | dev_priv->rps.cur_freq = val; |
0f94592e | 5220 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
9fcee2f7 CW |
5221 | |
5222 | return 0; | |
2b4e57bd ED |
5223 | } |
5224 | ||
9fcee2f7 | 5225 | static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val) |
ffe02b40 | 5226 | { |
9fcee2f7 CW |
5227 | int err; |
5228 | ||
dc97997a | 5229 | if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1), |
ffe02b40 VS |
5230 | "Odd GPU freq value\n")) |
5231 | val &= ~1; | |
5232 | ||
cd25dd5b D |
5233 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
5234 | ||
8fb55197 | 5235 | if (val != dev_priv->rps.cur_freq) { |
9fcee2f7 CW |
5236 | err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
5237 | if (err) | |
5238 | return err; | |
5239 | ||
db4c5e0b | 5240 | gen6_set_rps_thresholds(dev_priv, val); |
8fb55197 | 5241 | } |
ffe02b40 | 5242 | |
ffe02b40 VS |
5243 | dev_priv->rps.cur_freq = val; |
5244 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
9fcee2f7 CW |
5245 | |
5246 | return 0; | |
ffe02b40 VS |
5247 | } |
5248 | ||
a7f6e231 | 5249 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
76c3552f D |
5250 | * |
5251 | * * If Gfx is Idle, then | |
a7f6e231 D |
5252 | * 1. Forcewake Media well. |
5253 | * 2. Request idle freq. | |
5254 | * 3. Release Forcewake of Media well. | |
76c3552f D |
5255 | */ |
5256 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
5257 | { | |
aed242ff | 5258 | u32 val = dev_priv->rps.idle_freq; |
9fcee2f7 | 5259 | int err; |
5549d25f | 5260 | |
aed242ff | 5261 | if (dev_priv->rps.cur_freq <= val) |
76c3552f D |
5262 | return; |
5263 | ||
c9efef7b CW |
5264 | /* The punit delays the write of the frequency and voltage until it |
5265 | * determines the GPU is awake. During normal usage we don't want to | |
5266 | * waste power changing the frequency if the GPU is sleeping (rc6). | |
5267 | * However, the GPU and driver is now idle and we do not want to delay | |
5268 | * switching to minimum voltage (reducing power whilst idle) as we do | |
5269 | * not expect to be woken in the near future and so must flush the | |
5270 | * change by waking the device. | |
5271 | * | |
5272 | * We choose to take the media powerwell (either would do to trick the | |
5273 | * punit into committing the voltage change) as that takes a lot less | |
5274 | * power than the render powerwell. | |
5275 | */ | |
a7f6e231 | 5276 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 | 5277 | err = valleyview_set_rps(dev_priv, val); |
a7f6e231 | 5278 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 CW |
5279 | |
5280 | if (err) | |
5281 | DRM_ERROR("Failed to set RPS for idle\n"); | |
76c3552f D |
5282 | } |
5283 | ||
43cf3bf0 CW |
5284 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
5285 | { | |
5286 | mutex_lock(&dev_priv->rps.hw_lock); | |
5287 | if (dev_priv->rps.enabled) { | |
bd64818d CW |
5288 | u8 freq; |
5289 | ||
e0e8c7cb | 5290 | if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) |
43cf3bf0 CW |
5291 | gen6_rps_reset_ei(dev_priv); |
5292 | I915_WRITE(GEN6_PMINTRMSK, | |
5293 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
2b83c4c4 | 5294 | |
c33d247d CW |
5295 | gen6_enable_rps_interrupts(dev_priv); |
5296 | ||
bd64818d CW |
5297 | /* Use the user's desired frequency as a guide, but for better |
5298 | * performance, jump directly to RPe as our starting frequency. | |
5299 | */ | |
5300 | freq = max(dev_priv->rps.cur_freq, | |
5301 | dev_priv->rps.efficient_freq); | |
5302 | ||
9fcee2f7 | 5303 | if (intel_set_rps(dev_priv, |
bd64818d | 5304 | clamp(freq, |
9fcee2f7 CW |
5305 | dev_priv->rps.min_freq_softlimit, |
5306 | dev_priv->rps.max_freq_softlimit))) | |
5307 | DRM_DEBUG_DRIVER("Failed to set idle frequency\n"); | |
43cf3bf0 CW |
5308 | } |
5309 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5310 | } | |
5311 | ||
b29c19b6 CW |
5312 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
5313 | { | |
c33d247d CW |
5314 | /* Flush our bottom-half so that it does not race with us |
5315 | * setting the idle frequency and so that it is bounded by | |
5316 | * our rpm wakeref. And then disable the interrupts to stop any | |
5317 | * futher RPS reclocking whilst we are asleep. | |
5318 | */ | |
5319 | gen6_disable_rps_interrupts(dev_priv); | |
5320 | ||
b29c19b6 | 5321 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 5322 | if (dev_priv->rps.enabled) { |
dc97997a | 5323 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
76c3552f | 5324 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 5325 | else |
dc97997a | 5326 | gen6_set_rps(dev_priv, dev_priv->rps.idle_freq); |
c0951f0c | 5327 | dev_priv->rps.last_adj = 0; |
12c100bf VS |
5328 | I915_WRITE(GEN6_PMINTRMSK, |
5329 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); | |
c0951f0c | 5330 | } |
8d3afd7d | 5331 | mutex_unlock(&dev_priv->rps.hw_lock); |
1854d5ca | 5332 | |
8d3afd7d | 5333 | spin_lock(&dev_priv->rps.client_lock); |
1854d5ca CW |
5334 | while (!list_empty(&dev_priv->rps.clients)) |
5335 | list_del_init(dev_priv->rps.clients.next); | |
8d3afd7d | 5336 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
5337 | } |
5338 | ||
1854d5ca | 5339 | void gen6_rps_boost(struct drm_i915_private *dev_priv, |
e61b9958 CW |
5340 | struct intel_rps_client *rps, |
5341 | unsigned long submitted) | |
b29c19b6 | 5342 | { |
8d3afd7d CW |
5343 | /* This is intentionally racy! We peek at the state here, then |
5344 | * validate inside the RPS worker. | |
5345 | */ | |
67d97da3 | 5346 | if (!(dev_priv->gt.awake && |
8d3afd7d | 5347 | dev_priv->rps.enabled && |
29ecd78d | 5348 | dev_priv->rps.cur_freq < dev_priv->rps.boost_freq)) |
8d3afd7d | 5349 | return; |
43cf3bf0 | 5350 | |
e61b9958 CW |
5351 | /* Force a RPS boost (and don't count it against the client) if |
5352 | * the GPU is severely congested. | |
5353 | */ | |
d0bc54f2 | 5354 | if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) |
e61b9958 CW |
5355 | rps = NULL; |
5356 | ||
8d3afd7d CW |
5357 | spin_lock(&dev_priv->rps.client_lock); |
5358 | if (rps == NULL || list_empty(&rps->link)) { | |
5359 | spin_lock_irq(&dev_priv->irq_lock); | |
5360 | if (dev_priv->rps.interrupts_enabled) { | |
5361 | dev_priv->rps.client_boost = true; | |
c33d247d | 5362 | schedule_work(&dev_priv->rps.work); |
8d3afd7d CW |
5363 | } |
5364 | spin_unlock_irq(&dev_priv->irq_lock); | |
1854d5ca | 5365 | |
2e1b8730 CW |
5366 | if (rps != NULL) { |
5367 | list_add(&rps->link, &dev_priv->rps.clients); | |
5368 | rps->boosts++; | |
1854d5ca CW |
5369 | } else |
5370 | dev_priv->rps.boosts++; | |
c0951f0c | 5371 | } |
8d3afd7d | 5372 | spin_unlock(&dev_priv->rps.client_lock); |
b29c19b6 CW |
5373 | } |
5374 | ||
9fcee2f7 | 5375 | int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) |
0a073b84 | 5376 | { |
9fcee2f7 CW |
5377 | int err; |
5378 | ||
cfd1c488 CW |
5379 | lockdep_assert_held(&dev_priv->rps.hw_lock); |
5380 | GEM_BUG_ON(val > dev_priv->rps.max_freq); | |
5381 | GEM_BUG_ON(val < dev_priv->rps.min_freq); | |
5382 | ||
76e4e4b5 CW |
5383 | if (!dev_priv->rps.enabled) { |
5384 | dev_priv->rps.cur_freq = val; | |
5385 | return 0; | |
5386 | } | |
5387 | ||
dc97997a | 5388 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
9fcee2f7 | 5389 | err = valleyview_set_rps(dev_priv, val); |
ffe02b40 | 5390 | else |
9fcee2f7 CW |
5391 | err = gen6_set_rps(dev_priv, val); |
5392 | ||
5393 | return err; | |
0a073b84 JB |
5394 | } |
5395 | ||
dc97997a | 5396 | static void gen9_disable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 5397 | { |
20e49366 | 5398 | I915_WRITE(GEN6_RC_CONTROL, 0); |
38c23527 | 5399 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
5400 | } |
5401 | ||
dc97997a | 5402 | static void gen9_disable_rps(struct drm_i915_private *dev_priv) |
2030d684 | 5403 | { |
2030d684 AG |
5404 | I915_WRITE(GEN6_RP_CONTROL, 0); |
5405 | } | |
5406 | ||
dc97997a | 5407 | static void gen6_disable_rps(struct drm_i915_private *dev_priv) |
d20d4f0c | 5408 | { |
d20d4f0c | 5409 | I915_WRITE(GEN6_RC_CONTROL, 0); |
44fc7d5c | 5410 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2030d684 | 5411 | I915_WRITE(GEN6_RP_CONTROL, 0); |
44fc7d5c DV |
5412 | } |
5413 | ||
dc97997a | 5414 | static void cherryview_disable_rps(struct drm_i915_private *dev_priv) |
38807746 | 5415 | { |
38807746 D |
5416 | I915_WRITE(GEN6_RC_CONTROL, 0); |
5417 | } | |
5418 | ||
dc97997a | 5419 | static void valleyview_disable_rps(struct drm_i915_private *dev_priv) |
44fc7d5c | 5420 | { |
98a2e5f9 D |
5421 | /* we're doing forcewake before Disabling RC6, |
5422 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 5423 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 5424 | |
44fc7d5c | 5425 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 5426 | |
59bad947 | 5427 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
5428 | } |
5429 | ||
dc97997a | 5430 | static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) |
dc39fff7 | 5431 | { |
dc97997a | 5432 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
91ca689a ID |
5433 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
5434 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
5435 | else | |
5436 | mode = 0; | |
5437 | } | |
dc97997a | 5438 | if (HAS_RC6p(dev_priv)) |
b99d49cc ID |
5439 | DRM_DEBUG_DRIVER("Enabling RC6 states: " |
5440 | "RC6 %s RC6p %s RC6pp %s\n", | |
5441 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE), | |
5442 | onoff(mode & GEN6_RC_CTL_RC6p_ENABLE), | |
5443 | onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE)); | |
58abf1da RV |
5444 | |
5445 | else | |
b99d49cc ID |
5446 | DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n", |
5447 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE)); | |
dc39fff7 BW |
5448 | } |
5449 | ||
dc97997a | 5450 | static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) |
274008e8 | 5451 | { |
72e96d64 | 5452 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
274008e8 SAK |
5453 | bool enable_rc6 = true; |
5454 | unsigned long rc6_ctx_base; | |
fc619841 ID |
5455 | u32 rc_ctl; |
5456 | int rc_sw_target; | |
5457 | ||
5458 | rc_ctl = I915_READ(GEN6_RC_CONTROL); | |
5459 | rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >> | |
5460 | RC_SW_TARGET_STATE_SHIFT; | |
5461 | DRM_DEBUG_DRIVER("BIOS enabled RC states: " | |
5462 | "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", | |
5463 | onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE), | |
5464 | onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), | |
5465 | rc_sw_target); | |
274008e8 SAK |
5466 | |
5467 | if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { | |
b99d49cc | 5468 | DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n"); |
274008e8 SAK |
5469 | enable_rc6 = false; |
5470 | } | |
5471 | ||
5472 | /* | |
5473 | * The exact context size is not known for BXT, so assume a page size | |
5474 | * for this check. | |
5475 | */ | |
5476 | rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; | |
72e96d64 JL |
5477 | if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) && |
5478 | (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base + | |
5479 | ggtt->stolen_reserved_size))) { | |
b99d49cc | 5480 | DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n"); |
274008e8 SAK |
5481 | enable_rc6 = false; |
5482 | } | |
5483 | ||
5484 | if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && | |
5485 | ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && | |
5486 | ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && | |
5487 | ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { | |
b99d49cc | 5488 | DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n"); |
274008e8 SAK |
5489 | enable_rc6 = false; |
5490 | } | |
5491 | ||
fc619841 ID |
5492 | if (!I915_READ(GEN8_PUSHBUS_CONTROL) || |
5493 | !I915_READ(GEN8_PUSHBUS_ENABLE) || | |
5494 | !I915_READ(GEN8_PUSHBUS_SHIFT)) { | |
5495 | DRM_DEBUG_DRIVER("Pushbus not setup properly.\n"); | |
5496 | enable_rc6 = false; | |
5497 | } | |
5498 | ||
5499 | if (!I915_READ(GEN6_GFXPAUSE)) { | |
5500 | DRM_DEBUG_DRIVER("GFX pause not setup properly.\n"); | |
5501 | enable_rc6 = false; | |
5502 | } | |
5503 | ||
5504 | if (!I915_READ(GEN8_MISC_CTRL0)) { | |
5505 | DRM_DEBUG_DRIVER("GPM control not setup properly.\n"); | |
274008e8 SAK |
5506 | enable_rc6 = false; |
5507 | } | |
5508 | ||
5509 | return enable_rc6; | |
5510 | } | |
5511 | ||
dc97997a | 5512 | int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6) |
2b4e57bd | 5513 | { |
e7d66d89 | 5514 | /* No RC6 before Ironlake and code is gone for ilk. */ |
dc97997a | 5515 | if (INTEL_INFO(dev_priv)->gen < 6) |
e6069ca8 ID |
5516 | return 0; |
5517 | ||
274008e8 SAK |
5518 | if (!enable_rc6) |
5519 | return 0; | |
5520 | ||
cc3f90f0 | 5521 | if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) { |
274008e8 SAK |
5522 | DRM_INFO("RC6 disabled by BIOS\n"); |
5523 | return 0; | |
5524 | } | |
5525 | ||
456470eb | 5526 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
5527 | if (enable_rc6 >= 0) { |
5528 | int mask; | |
5529 | ||
dc97997a | 5530 | if (HAS_RC6p(dev_priv)) |
e6069ca8 ID |
5531 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
5532 | INTEL_RC6pp_ENABLE; | |
5533 | else | |
5534 | mask = INTEL_RC6_ENABLE; | |
5535 | ||
5536 | if ((enable_rc6 & mask) != enable_rc6) | |
b99d49cc ID |
5537 | DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d " |
5538 | "(requested %d, valid %d)\n", | |
5539 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
5540 | |
5541 | return enable_rc6 & mask; | |
5542 | } | |
2b4e57bd | 5543 | |
dc97997a | 5544 | if (IS_IVYBRIDGE(dev_priv)) |
cca84a1f | 5545 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
5546 | |
5547 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
5548 | } |
5549 | ||
dc97997a | 5550 | static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) |
3280e8b0 BW |
5551 | { |
5552 | /* All of these values are in units of 50MHz */ | |
773ea9a8 | 5553 | |
93ee2920 | 5554 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
cc3f90f0 | 5555 | if (IS_GEN9_LP(dev_priv)) { |
773ea9a8 | 5556 | u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
35040562 BP |
5557 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; |
5558 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
5559 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; | |
5560 | } else { | |
773ea9a8 | 5561 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
35040562 BP |
5562 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
5563 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
5564 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
5565 | } | |
3280e8b0 | 5566 | /* hw_max = RP0 until we check for overclocking */ |
773ea9a8 | 5567 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
3280e8b0 | 5568 | |
93ee2920 | 5569 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
dc97997a | 5570 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || |
b976dc53 | 5571 | IS_GEN9_BC(dev_priv)) { |
773ea9a8 CW |
5572 | u32 ddcc_status = 0; |
5573 | ||
5574 | if (sandybridge_pcode_read(dev_priv, | |
5575 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
5576 | &ddcc_status) == 0) | |
93ee2920 | 5577 | dev_priv->rps.efficient_freq = |
46efa4ab TR |
5578 | clamp_t(u8, |
5579 | ((ddcc_status >> 8) & 0xff), | |
5580 | dev_priv->rps.min_freq, | |
5581 | dev_priv->rps.max_freq); | |
93ee2920 TR |
5582 | } |
5583 | ||
b976dc53 | 5584 | if (IS_GEN9_BC(dev_priv)) { |
c5e0688c | 5585 | /* Store the frequency values in 16.66 MHZ units, which is |
773ea9a8 CW |
5586 | * the natural hardware unit for SKL |
5587 | */ | |
c5e0688c AG |
5588 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; |
5589 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; | |
5590 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; | |
5591 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; | |
5592 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; | |
5593 | } | |
3280e8b0 BW |
5594 | } |
5595 | ||
3a45b05c | 5596 | static void reset_rps(struct drm_i915_private *dev_priv, |
9fcee2f7 | 5597 | int (*set)(struct drm_i915_private *, u8)) |
3a45b05c CW |
5598 | { |
5599 | u8 freq = dev_priv->rps.cur_freq; | |
5600 | ||
5601 | /* force a reset */ | |
5602 | dev_priv->rps.power = -1; | |
5603 | dev_priv->rps.cur_freq = -1; | |
5604 | ||
9fcee2f7 CW |
5605 | if (set(dev_priv, freq)) |
5606 | DRM_ERROR("Failed to reset RPS to initial values\n"); | |
3a45b05c CW |
5607 | } |
5608 | ||
b6fef0ef | 5609 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
dc97997a | 5610 | static void gen9_enable_rps(struct drm_i915_private *dev_priv) |
b6fef0ef | 5611 | { |
b6fef0ef JB |
5612 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
5613 | ||
0beb059a AG |
5614 | /* Program defaults and thresholds for RPS*/ |
5615 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
5616 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); | |
5617 | ||
5618 | /* 1 second timeout*/ | |
5619 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, | |
5620 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); | |
5621 | ||
b6fef0ef | 5622 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
b6fef0ef | 5623 | |
0beb059a AG |
5624 | /* Leaning on the below call to gen6_set_rps to program/setup the |
5625 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, | |
5626 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ | |
3a45b05c | 5627 | reset_rps(dev_priv, gen6_set_rps); |
b6fef0ef JB |
5628 | |
5629 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
5630 | } | |
5631 | ||
dc97997a | 5632 | static void gen9_enable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 5633 | { |
e2f80391 | 5634 | struct intel_engine_cs *engine; |
3b3f1650 | 5635 | enum intel_engine_id id; |
20e49366 | 5636 | uint32_t rc6_mask = 0; |
20e49366 ZW |
5637 | |
5638 | /* 1a: Software RC state - RC0 */ | |
5639 | I915_WRITE(GEN6_RC_STATE, 0); | |
5640 | ||
5641 | /* 1b: Get forcewake during program sequence. Although the driver | |
5642 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 5643 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
5644 | |
5645 | /* 2a: Disable RC states. */ | |
5646 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5647 | ||
5648 | /* 2b: Program RC6 thresholds.*/ | |
63a4dec2 SAK |
5649 | |
5650 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ | |
dc97997a | 5651 | if (IS_SKYLAKE(dev_priv)) |
63a4dec2 SAK |
5652 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
5653 | else | |
5654 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
20e49366 ZW |
5655 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
5656 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 5657 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 5658 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
97c322e7 | 5659 | |
1a3d1898 | 5660 | if (HAS_GUC(dev_priv)) |
97c322e7 SAK |
5661 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); |
5662 | ||
20e49366 | 5663 | I915_WRITE(GEN6_RC_SLEEP, 0); |
20e49366 | 5664 | |
38c23527 ZW |
5665 | /* 2c: Program Coarse Power Gating Policies. */ |
5666 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
5667 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
5668 | ||
20e49366 | 5669 | /* 3a: Enable RC6 */ |
dc97997a | 5670 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
20e49366 | 5671 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
87ad3212 | 5672 | DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); |
1c044f9b CW |
5673 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
5674 | I915_WRITE(GEN6_RC_CONTROL, | |
5675 | GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask); | |
20e49366 | 5676 | |
cb07bae0 SK |
5677 | /* |
5678 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. | |
f2d2fe95 | 5679 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
cb07bae0 | 5680 | */ |
dc97997a | 5681 | if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) |
f2d2fe95 SAK |
5682 | I915_WRITE(GEN9_PG_ENABLE, 0); |
5683 | else | |
5684 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
5685 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); | |
38c23527 | 5686 | |
59bad947 | 5687 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
5688 | } |
5689 | ||
dc97997a | 5690 | static void gen8_enable_rps(struct drm_i915_private *dev_priv) |
6edee7f3 | 5691 | { |
e2f80391 | 5692 | struct intel_engine_cs *engine; |
3b3f1650 | 5693 | enum intel_engine_id id; |
93ee2920 | 5694 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
5695 | |
5696 | /* 1a: Software RC state - RC0 */ | |
5697 | I915_WRITE(GEN6_RC_STATE, 0); | |
5698 | ||
5699 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
5700 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 5701 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
5702 | |
5703 | /* 2a: Disable RC states. */ | |
5704 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5705 | ||
6edee7f3 BW |
5706 | /* 2b: Program RC6 thresholds.*/ |
5707 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
5708 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
5709 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 5710 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 5711 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
6edee7f3 | 5712 | I915_WRITE(GEN6_RC_SLEEP, 0); |
dc97997a | 5713 | if (IS_BROADWELL(dev_priv)) |
0d68b25e TR |
5714 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
5715 | else | |
5716 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
5717 | |
5718 | /* 3: Enable RC6 */ | |
dc97997a | 5719 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6edee7f3 | 5720 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
dc97997a CW |
5721 | intel_print_rc6_info(dev_priv, rc6_mask); |
5722 | if (IS_BROADWELL(dev_priv)) | |
0d68b25e TR |
5723 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
5724 | GEN7_RC_CTL_TO_MODE | | |
5725 | rc6_mask); | |
5726 | else | |
5727 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
5728 | GEN6_RC_CTL_EI_MODE(1) | | |
5729 | rc6_mask); | |
6edee7f3 BW |
5730 | |
5731 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
5732 | I915_WRITE(GEN6_RPNSWREQ, |
5733 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
5734 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
5735 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
5736 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
5737 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
5738 | ||
5739 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
5740 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
5741 | dev_priv->rps.max_freq_softlimit << 24 | | |
5742 | dev_priv->rps.min_freq_softlimit << 16); | |
5743 | ||
5744 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
5745 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
5746 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
5747 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
5748 | ||
5749 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
5750 | |
5751 | /* 5: Enable RPS */ | |
7526ed79 DV |
5752 | I915_WRITE(GEN6_RP_CONTROL, |
5753 | GEN6_RP_MEDIA_TURBO | | |
5754 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5755 | GEN6_RP_MEDIA_IS_GFX | | |
5756 | GEN6_RP_ENABLE | | |
5757 | GEN6_RP_UP_BUSY_AVG | | |
5758 | GEN6_RP_DOWN_IDLE_AVG); | |
5759 | ||
5760 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
5761 | ||
3a45b05c | 5762 | reset_rps(dev_priv, gen6_set_rps); |
7526ed79 | 5763 | |
59bad947 | 5764 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
5765 | } |
5766 | ||
dc97997a | 5767 | static void gen6_enable_rps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5768 | { |
e2f80391 | 5769 | struct intel_engine_cs *engine; |
3b3f1650 | 5770 | enum intel_engine_id id; |
99ac9612 | 5771 | u32 rc6vids, rc6_mask = 0; |
2b4e57bd | 5772 | u32 gtfifodbg; |
2b4e57bd | 5773 | int rc6_mode; |
b4ac5afc | 5774 | int ret; |
2b4e57bd | 5775 | |
4fc688ce | 5776 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 5777 | |
2b4e57bd ED |
5778 | /* Here begins a magic sequence of register writes to enable |
5779 | * auto-downclocking. | |
5780 | * | |
5781 | * Perhaps there might be some value in exposing these to | |
5782 | * userspace... | |
5783 | */ | |
5784 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
5785 | |
5786 | /* Clear the DBG now so we don't confuse earlier errors */ | |
297b32ec VS |
5787 | gtfifodbg = I915_READ(GTFIFODBG); |
5788 | if (gtfifodbg) { | |
2b4e57bd ED |
5789 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
5790 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
5791 | } | |
5792 | ||
59bad947 | 5793 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
5794 | |
5795 | /* disable the counters and set deterministic thresholds */ | |
5796 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5797 | ||
5798 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
5799 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
5800 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
5801 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
5802 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
5803 | ||
3b3f1650 | 5804 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 5805 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
2b4e57bd ED |
5806 | |
5807 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
5808 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
dc97997a | 5809 | if (IS_IVYBRIDGE(dev_priv)) |
351aa566 SM |
5810 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
5811 | else | |
5812 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 5813 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
5814 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
5815 | ||
5a7dc92a | 5816 | /* Check if we are enabling RC6 */ |
dc97997a | 5817 | rc6_mode = intel_enable_rc6(); |
2b4e57bd ED |
5818 | if (rc6_mode & INTEL_RC6_ENABLE) |
5819 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
5820 | ||
5a7dc92a | 5821 | /* We don't use those on Haswell */ |
dc97997a | 5822 | if (!IS_HASWELL(dev_priv)) { |
5a7dc92a ED |
5823 | if (rc6_mode & INTEL_RC6p_ENABLE) |
5824 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 5825 | |
5a7dc92a ED |
5826 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
5827 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
5828 | } | |
2b4e57bd | 5829 | |
dc97997a | 5830 | intel_print_rc6_info(dev_priv, rc6_mask); |
2b4e57bd ED |
5831 | |
5832 | I915_WRITE(GEN6_RC_CONTROL, | |
5833 | rc6_mask | | |
5834 | GEN6_RC_CTL_EI_MODE(1) | | |
5835 | GEN6_RC_CTL_HW_ENABLE); | |
5836 | ||
dd75fdc8 CW |
5837 | /* Power down if completely idle for over 50ms */ |
5838 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 5839 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 5840 | |
3a45b05c | 5841 | reset_rps(dev_priv, gen6_set_rps); |
2b4e57bd | 5842 | |
31643d54 BW |
5843 | rc6vids = 0; |
5844 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
dc97997a | 5845 | if (IS_GEN6(dev_priv) && ret) { |
31643d54 | 5846 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
dc97997a | 5847 | } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
31643d54 BW |
5848 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
5849 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
5850 | rc6vids &= 0xffff00; | |
5851 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
5852 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
5853 | if (ret) | |
5854 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
5855 | } | |
5856 | ||
59bad947 | 5857 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
5858 | } |
5859 | ||
fb7404e8 | 5860 | static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
2b4e57bd ED |
5861 | { |
5862 | int min_freq = 15; | |
3ebecd07 CW |
5863 | unsigned int gpu_freq; |
5864 | unsigned int max_ia_freq, min_ring_freq; | |
4c8c7743 | 5865 | unsigned int max_gpu_freq, min_gpu_freq; |
2b4e57bd | 5866 | int scaling_factor = 180; |
eda79642 | 5867 | struct cpufreq_policy *policy; |
2b4e57bd | 5868 | |
4fc688ce | 5869 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 5870 | |
eda79642 BW |
5871 | policy = cpufreq_cpu_get(0); |
5872 | if (policy) { | |
5873 | max_ia_freq = policy->cpuinfo.max_freq; | |
5874 | cpufreq_cpu_put(policy); | |
5875 | } else { | |
5876 | /* | |
5877 | * Default to measured freq if none found, PCU will ensure we | |
5878 | * don't go over | |
5879 | */ | |
2b4e57bd | 5880 | max_ia_freq = tsc_khz; |
eda79642 | 5881 | } |
2b4e57bd ED |
5882 | |
5883 | /* Convert from kHz to MHz */ | |
5884 | max_ia_freq /= 1000; | |
5885 | ||
153b4b95 | 5886 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
5887 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
5888 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 5889 | |
b976dc53 | 5890 | if (IS_GEN9_BC(dev_priv)) { |
4c8c7743 AG |
5891 | /* Convert GT frequency to 50 HZ units */ |
5892 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; | |
5893 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; | |
5894 | } else { | |
5895 | min_gpu_freq = dev_priv->rps.min_freq; | |
5896 | max_gpu_freq = dev_priv->rps.max_freq; | |
5897 | } | |
5898 | ||
2b4e57bd ED |
5899 | /* |
5900 | * For each potential GPU frequency, load a ring frequency we'd like | |
5901 | * to use for memory access. We do this by specifying the IA frequency | |
5902 | * the PCU should use as a reference to determine the ring frequency. | |
5903 | */ | |
4c8c7743 AG |
5904 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
5905 | int diff = max_gpu_freq - gpu_freq; | |
3ebecd07 CW |
5906 | unsigned int ia_freq = 0, ring_freq = 0; |
5907 | ||
b976dc53 | 5908 | if (IS_GEN9_BC(dev_priv)) { |
4c8c7743 AG |
5909 | /* |
5910 | * ring_freq = 2 * GT. ring_freq is in 100MHz units | |
5911 | * No floor required for ring frequency on SKL. | |
5912 | */ | |
5913 | ring_freq = gpu_freq; | |
dc97997a | 5914 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
46c764d4 BW |
5915 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
5916 | ring_freq = max(min_ring_freq, gpu_freq); | |
dc97997a | 5917 | } else if (IS_HASWELL(dev_priv)) { |
f6aca45c | 5918 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
5919 | ring_freq = max(min_ring_freq, ring_freq); |
5920 | /* leave ia_freq as the default, chosen by cpufreq */ | |
5921 | } else { | |
5922 | /* On older processors, there is no separate ring | |
5923 | * clock domain, so in order to boost the bandwidth | |
5924 | * of the ring, we need to upclock the CPU (ia_freq). | |
5925 | * | |
5926 | * For GPU frequencies less than 750MHz, | |
5927 | * just use the lowest ring freq. | |
5928 | */ | |
5929 | if (gpu_freq < min_freq) | |
5930 | ia_freq = 800; | |
5931 | else | |
5932 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
5933 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
5934 | } | |
2b4e57bd | 5935 | |
42c0526c BW |
5936 | sandybridge_pcode_write(dev_priv, |
5937 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
5938 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
5939 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
5940 | gpu_freq); | |
2b4e57bd | 5941 | } |
2b4e57bd ED |
5942 | } |
5943 | ||
03af2045 | 5944 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
5945 | { |
5946 | u32 val, rp0; | |
5947 | ||
5b5929cb | 5948 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
2b6b3a09 | 5949 | |
43b67998 | 5950 | switch (INTEL_INFO(dev_priv)->sseu.eu_total) { |
5b5929cb JN |
5951 | case 8: |
5952 | /* (2 * 4) config */ | |
5953 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
5954 | break; | |
5955 | case 12: | |
5956 | /* (2 * 6) config */ | |
5957 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
5958 | break; | |
5959 | case 16: | |
5960 | /* (2 * 8) config */ | |
5961 | default: | |
5962 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
5963 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
5964 | break; | |
095acd5f | 5965 | } |
5b5929cb JN |
5966 | |
5967 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
5968 | ||
2b6b3a09 D |
5969 | return rp0; |
5970 | } | |
5971 | ||
5972 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
5973 | { | |
5974 | u32 val, rpe; | |
5975 | ||
5976 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
5977 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
5978 | ||
5979 | return rpe; | |
5980 | } | |
5981 | ||
7707df4a D |
5982 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
5983 | { | |
5984 | u32 val, rp1; | |
5985 | ||
5b5929cb JN |
5986 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
5987 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
5988 | ||
7707df4a D |
5989 | return rp1; |
5990 | } | |
5991 | ||
96676fe3 D |
5992 | static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
5993 | { | |
5994 | u32 val, rpn; | |
5995 | ||
5996 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); | |
5997 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & | |
5998 | FB_GFX_FREQ_FUSE_MASK); | |
5999 | ||
6000 | return rpn; | |
6001 | } | |
6002 | ||
f8f2b001 D |
6003 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
6004 | { | |
6005 | u32 val, rp1; | |
6006 | ||
6007 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
6008 | ||
6009 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
6010 | ||
6011 | return rp1; | |
6012 | } | |
6013 | ||
03af2045 | 6014 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
6015 | { |
6016 | u32 val, rp0; | |
6017 | ||
64936258 | 6018 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
6019 | |
6020 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
6021 | /* Clamp to max */ | |
6022 | rp0 = min_t(u32, rp0, 0xea); | |
6023 | ||
6024 | return rp0; | |
6025 | } | |
6026 | ||
6027 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
6028 | { | |
6029 | u32 val, rpe; | |
6030 | ||
64936258 | 6031 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 6032 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 6033 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
6034 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
6035 | ||
6036 | return rpe; | |
6037 | } | |
6038 | ||
03af2045 | 6039 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 6040 | { |
36146035 ID |
6041 | u32 val; |
6042 | ||
6043 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; | |
6044 | /* | |
6045 | * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value | |
6046 | * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on | |
6047 | * a BYT-M B0 the above register contains 0xbf. Moreover when setting | |
6048 | * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 | |
6049 | * to make sure it matches what Punit accepts. | |
6050 | */ | |
6051 | return max_t(u32, val, 0xc0); | |
0a073b84 JB |
6052 | } |
6053 | ||
ae48434c ID |
6054 | /* Check that the pctx buffer wasn't move under us. */ |
6055 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
6056 | { | |
6057 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6058 | ||
6059 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
6060 | dev_priv->vlv_pctx->stolen->start); | |
6061 | } | |
6062 | ||
38807746 D |
6063 | |
6064 | /* Check that the pcbr address is not empty. */ | |
6065 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
6066 | { | |
6067 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6068 | ||
6069 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
6070 | } | |
6071 | ||
dc97997a | 6072 | static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) |
38807746 | 6073 | { |
62106b4f | 6074 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 6075 | unsigned long pctx_paddr, paddr; |
38807746 D |
6076 | u32 pcbr; |
6077 | int pctx_size = 32*1024; | |
6078 | ||
38807746 D |
6079 | pcbr = I915_READ(VLV_PCBR); |
6080 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 6081 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 | 6082 | paddr = (dev_priv->mm.stolen_base + |
62106b4f | 6083 | (ggtt->stolen_size - pctx_size)); |
38807746 D |
6084 | |
6085 | pctx_paddr = (paddr & (~4095)); | |
6086 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6087 | } | |
ce611ef8 VS |
6088 | |
6089 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
6090 | } |
6091 | ||
dc97997a | 6092 | static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) |
c9cddffc | 6093 | { |
c9cddffc JB |
6094 | struct drm_i915_gem_object *pctx; |
6095 | unsigned long pctx_paddr; | |
6096 | u32 pcbr; | |
6097 | int pctx_size = 24*1024; | |
6098 | ||
6099 | pcbr = I915_READ(VLV_PCBR); | |
6100 | if (pcbr) { | |
6101 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
6102 | int pcbr_offset; | |
6103 | ||
6104 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
187685cb | 6105 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
c9cddffc | 6106 | pcbr_offset, |
190d6cd5 | 6107 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
6108 | pctx_size); |
6109 | goto out; | |
6110 | } | |
6111 | ||
ce611ef8 VS |
6112 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
6113 | ||
c9cddffc JB |
6114 | /* |
6115 | * From the Gunit register HAS: | |
6116 | * The Gfx driver is expected to program this register and ensure | |
6117 | * proper allocation within Gfx stolen memory. For example, this | |
6118 | * register should be programmed such than the PCBR range does not | |
6119 | * overlap with other ranges, such as the frame buffer, protected | |
6120 | * memory, or any other relevant ranges. | |
6121 | */ | |
187685cb | 6122 | pctx = i915_gem_object_create_stolen(dev_priv, pctx_size); |
c9cddffc JB |
6123 | if (!pctx) { |
6124 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
ee504898 | 6125 | goto out; |
c9cddffc JB |
6126 | } |
6127 | ||
6128 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
6129 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6130 | ||
6131 | out: | |
ce611ef8 | 6132 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
6133 | dev_priv->vlv_pctx = pctx; |
6134 | } | |
6135 | ||
dc97997a | 6136 | static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv) |
ae48434c | 6137 | { |
ae48434c ID |
6138 | if (WARN_ON(!dev_priv->vlv_pctx)) |
6139 | return; | |
6140 | ||
f0cd5182 | 6141 | i915_gem_object_put(dev_priv->vlv_pctx); |
ae48434c ID |
6142 | dev_priv->vlv_pctx = NULL; |
6143 | } | |
6144 | ||
c30fec65 VS |
6145 | static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv) |
6146 | { | |
6147 | dev_priv->rps.gpll_ref_freq = | |
6148 | vlv_get_cck_clock(dev_priv, "GPLL ref", | |
6149 | CCK_GPLL_CLOCK_CONTROL, | |
6150 | dev_priv->czclk_freq); | |
6151 | ||
6152 | DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n", | |
6153 | dev_priv->rps.gpll_ref_freq); | |
6154 | } | |
6155 | ||
dc97997a | 6156 | static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 6157 | { |
2bb25c17 | 6158 | u32 val; |
4e80519e | 6159 | |
dc97997a | 6160 | valleyview_setup_pctx(dev_priv); |
4e80519e | 6161 | |
c30fec65 VS |
6162 | vlv_init_gpll_ref_freq(dev_priv); |
6163 | ||
2bb25c17 VS |
6164 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
6165 | switch ((val >> 6) & 3) { | |
6166 | case 0: | |
6167 | case 1: | |
6168 | dev_priv->mem_freq = 800; | |
6169 | break; | |
6170 | case 2: | |
6171 | dev_priv->mem_freq = 1066; | |
6172 | break; | |
6173 | case 3: | |
6174 | dev_priv->mem_freq = 1333; | |
6175 | break; | |
6176 | } | |
80b83b62 | 6177 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 6178 | |
4e80519e ID |
6179 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
6180 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
6181 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6182 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
6183 | dev_priv->rps.max_freq); |
6184 | ||
6185 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
6186 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6187 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
6188 | dev_priv->rps.efficient_freq); |
6189 | ||
f8f2b001 D |
6190 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
6191 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6192 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
6193 | dev_priv->rps.rp1_freq); |
6194 | ||
4e80519e ID |
6195 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
6196 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6197 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e | 6198 | dev_priv->rps.min_freq); |
4e80519e ID |
6199 | } |
6200 | ||
dc97997a | 6201 | static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) |
38807746 | 6202 | { |
2bb25c17 | 6203 | u32 val; |
2b6b3a09 | 6204 | |
dc97997a | 6205 | cherryview_setup_pctx(dev_priv); |
2b6b3a09 | 6206 | |
c30fec65 VS |
6207 | vlv_init_gpll_ref_freq(dev_priv); |
6208 | ||
a580516d | 6209 | mutex_lock(&dev_priv->sb_lock); |
c6e8f39d | 6210 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
a580516d | 6211 | mutex_unlock(&dev_priv->sb_lock); |
c6e8f39d | 6212 | |
2bb25c17 | 6213 | switch ((val >> 2) & 0x7) { |
2bb25c17 | 6214 | case 3: |
2bb25c17 VS |
6215 | dev_priv->mem_freq = 2000; |
6216 | break; | |
bfa7df01 | 6217 | default: |
2bb25c17 VS |
6218 | dev_priv->mem_freq = 1600; |
6219 | break; | |
6220 | } | |
80b83b62 | 6221 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 6222 | |
2b6b3a09 D |
6223 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
6224 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
6225 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6226 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
6227 | dev_priv->rps.max_freq); |
6228 | ||
6229 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
6230 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6231 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
6232 | dev_priv->rps.efficient_freq); |
6233 | ||
7707df4a D |
6234 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
6235 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 6236 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
6237 | dev_priv->rps.rp1_freq); |
6238 | ||
96676fe3 | 6239 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
2b6b3a09 | 6240 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 6241 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
6242 | dev_priv->rps.min_freq); |
6243 | ||
1c14762d VS |
6244 | WARN_ONCE((dev_priv->rps.max_freq | |
6245 | dev_priv->rps.efficient_freq | | |
6246 | dev_priv->rps.rp1_freq | | |
6247 | dev_priv->rps.min_freq) & 1, | |
6248 | "Odd GPU freq values\n"); | |
38807746 D |
6249 | } |
6250 | ||
dc97997a | 6251 | static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 6252 | { |
dc97997a | 6253 | valleyview_cleanup_pctx(dev_priv); |
4e80519e ID |
6254 | } |
6255 | ||
dc97997a | 6256 | static void cherryview_enable_rps(struct drm_i915_private *dev_priv) |
38807746 | 6257 | { |
e2f80391 | 6258 | struct intel_engine_cs *engine; |
3b3f1650 | 6259 | enum intel_engine_id id; |
2b6b3a09 | 6260 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
6261 | |
6262 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
6263 | ||
297b32ec VS |
6264 | gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | |
6265 | GT_FIFO_FREE_ENTRIES_CHV); | |
38807746 D |
6266 | if (gtfifodbg) { |
6267 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
6268 | gtfifodbg); | |
6269 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
6270 | } | |
6271 | ||
6272 | cherryview_check_pctx(dev_priv); | |
6273 | ||
6274 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
6275 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 6276 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 6277 | |
160614a2 VS |
6278 | /* Disable RC states. */ |
6279 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6280 | ||
38807746 D |
6281 | /* 2a: Program RC6 thresholds.*/ |
6282 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
6283 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
6284 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
6285 | ||
3b3f1650 | 6286 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6287 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
38807746 D |
6288 | I915_WRITE(GEN6_RC_SLEEP, 0); |
6289 | ||
f4f71c7d D |
6290 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
6291 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); | |
38807746 D |
6292 | |
6293 | /* allows RC6 residency counter to work */ | |
6294 | I915_WRITE(VLV_COUNTER_CONTROL, | |
6295 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
6296 | VLV_MEDIA_RC6_COUNT_EN | | |
6297 | VLV_RENDER_RC6_COUNT_EN)); | |
6298 | ||
6299 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
6300 | pcbr = I915_READ(VLV_PCBR); | |
6301 | ||
38807746 | 6302 | /* 3: Enable RC6 */ |
dc97997a CW |
6303 | if ((intel_enable_rc6() & INTEL_RC6_ENABLE) && |
6304 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 6305 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
6306 | |
6307 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
6308 | ||
2b6b3a09 | 6309 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 6310 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
6311 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
6312 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
6313 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
6314 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
6315 | ||
6316 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6317 | ||
6318 | /* 5: Enable RPS */ | |
6319 | I915_WRITE(GEN6_RP_CONTROL, | |
6320 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 6321 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
6322 | GEN6_RP_ENABLE | |
6323 | GEN6_RP_UP_BUSY_AVG | | |
6324 | GEN6_RP_DOWN_IDLE_AVG); | |
6325 | ||
3ef62342 D |
6326 | /* Setting Fixed Bias */ |
6327 | val = VLV_OVERRIDE_EN | | |
6328 | VLV_SOC_TDP_EN | | |
6329 | CHV_BIAS_CPU_50_SOC_50; | |
6330 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
6331 | ||
2b6b3a09 D |
6332 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
6333 | ||
8d40c3ae VS |
6334 | /* RPS code assumes GPLL is used */ |
6335 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
6336 | ||
742f491d | 6337 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
2b6b3a09 D |
6338 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
6339 | ||
3a45b05c | 6340 | reset_rps(dev_priv, valleyview_set_rps); |
2b6b3a09 | 6341 | |
59bad947 | 6342 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
6343 | } |
6344 | ||
dc97997a | 6345 | static void valleyview_enable_rps(struct drm_i915_private *dev_priv) |
0a073b84 | 6346 | { |
e2f80391 | 6347 | struct intel_engine_cs *engine; |
3b3f1650 | 6348 | enum intel_engine_id id; |
2a5913a8 | 6349 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
6350 | |
6351 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
6352 | ||
ae48434c ID |
6353 | valleyview_check_pctx(dev_priv); |
6354 | ||
297b32ec VS |
6355 | gtfifodbg = I915_READ(GTFIFODBG); |
6356 | if (gtfifodbg) { | |
f7d85c1e JB |
6357 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
6358 | gtfifodbg); | |
0a073b84 JB |
6359 | I915_WRITE(GTFIFODBG, gtfifodbg); |
6360 | } | |
6361 | ||
c8d9a590 | 6362 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 6363 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 6364 | |
160614a2 VS |
6365 | /* Disable RC states. */ |
6366 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6367 | ||
cad725fe | 6368 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
6369 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
6370 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
6371 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
6372 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
6373 | ||
6374 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6375 | ||
6376 | I915_WRITE(GEN6_RP_CONTROL, | |
6377 | GEN6_RP_MEDIA_TURBO | | |
6378 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
6379 | GEN6_RP_MEDIA_IS_GFX | | |
6380 | GEN6_RP_ENABLE | | |
6381 | GEN6_RP_UP_BUSY_AVG | | |
6382 | GEN6_RP_DOWN_IDLE_CONT); | |
6383 | ||
6384 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
6385 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
6386 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
6387 | ||
3b3f1650 | 6388 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6389 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
0a073b84 | 6390 | |
2f0aa304 | 6391 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
6392 | |
6393 | /* allows RC6 residency counter to work */ | |
49798eb2 | 6394 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
6395 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
6396 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
6397 | VLV_MEDIA_RC6_COUNT_EN | |
6398 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 6399 | |
dc97997a | 6400 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6b88f295 | 6401 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 | 6402 | |
dc97997a | 6403 | intel_print_rc6_info(dev_priv, rc6_mode); |
dc39fff7 | 6404 | |
a2b23fe0 | 6405 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 6406 | |
3ef62342 D |
6407 | /* Setting Fixed Bias */ |
6408 | val = VLV_OVERRIDE_EN | | |
6409 | VLV_SOC_TDP_EN | | |
6410 | VLV_BIAS_CPU_125_SOC_875; | |
6411 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
6412 | ||
64936258 | 6413 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 6414 | |
8d40c3ae VS |
6415 | /* RPS code assumes GPLL is used */ |
6416 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
6417 | ||
742f491d | 6418 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
0a073b84 JB |
6419 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
6420 | ||
3a45b05c | 6421 | reset_rps(dev_priv, valleyview_set_rps); |
0a073b84 | 6422 | |
59bad947 | 6423 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
6424 | } |
6425 | ||
dde18883 ED |
6426 | static unsigned long intel_pxfreq(u32 vidfreq) |
6427 | { | |
6428 | unsigned long freq; | |
6429 | int div = (vidfreq & 0x3f0000) >> 16; | |
6430 | int post = (vidfreq & 0x3000) >> 12; | |
6431 | int pre = (vidfreq & 0x7); | |
6432 | ||
6433 | if (!pre) | |
6434 | return 0; | |
6435 | ||
6436 | freq = ((div * 133333) / ((1<<post) * pre)); | |
6437 | ||
6438 | return freq; | |
6439 | } | |
6440 | ||
eb48eb00 DV |
6441 | static const struct cparams { |
6442 | u16 i; | |
6443 | u16 t; | |
6444 | u16 m; | |
6445 | u16 c; | |
6446 | } cparams[] = { | |
6447 | { 1, 1333, 301, 28664 }, | |
6448 | { 1, 1066, 294, 24460 }, | |
6449 | { 1, 800, 294, 25192 }, | |
6450 | { 0, 1333, 276, 27605 }, | |
6451 | { 0, 1066, 276, 27605 }, | |
6452 | { 0, 800, 231, 23784 }, | |
6453 | }; | |
6454 | ||
f531dcb2 | 6455 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
6456 | { |
6457 | u64 total_count, diff, ret; | |
6458 | u32 count1, count2, count3, m = 0, c = 0; | |
6459 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
6460 | int i; | |
6461 | ||
67520415 | 6462 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 6463 | |
20e4d407 | 6464 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
6465 | |
6466 | /* Prevent division-by-zero if we are asking too fast. | |
6467 | * Also, we don't get interesting results if we are polling | |
6468 | * faster than once in 10ms, so just return the saved value | |
6469 | * in such cases. | |
6470 | */ | |
6471 | if (diff1 <= 10) | |
20e4d407 | 6472 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
6473 | |
6474 | count1 = I915_READ(DMIEC); | |
6475 | count2 = I915_READ(DDREC); | |
6476 | count3 = I915_READ(CSIEC); | |
6477 | ||
6478 | total_count = count1 + count2 + count3; | |
6479 | ||
6480 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
6481 | if (total_count < dev_priv->ips.last_count1) { |
6482 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
6483 | diff += total_count; |
6484 | } else { | |
20e4d407 | 6485 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
6486 | } |
6487 | ||
6488 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
6489 | if (cparams[i].i == dev_priv->ips.c_m && |
6490 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
6491 | m = cparams[i].m; |
6492 | c = cparams[i].c; | |
6493 | break; | |
6494 | } | |
6495 | } | |
6496 | ||
6497 | diff = div_u64(diff, diff1); | |
6498 | ret = ((m * diff) + c); | |
6499 | ret = div_u64(ret, 10); | |
6500 | ||
20e4d407 DV |
6501 | dev_priv->ips.last_count1 = total_count; |
6502 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 6503 | |
20e4d407 | 6504 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
6505 | |
6506 | return ret; | |
6507 | } | |
6508 | ||
f531dcb2 CW |
6509 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
6510 | { | |
6511 | unsigned long val; | |
6512 | ||
dc97997a | 6513 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
6514 | return 0; |
6515 | ||
6516 | spin_lock_irq(&mchdev_lock); | |
6517 | ||
6518 | val = __i915_chipset_val(dev_priv); | |
6519 | ||
6520 | spin_unlock_irq(&mchdev_lock); | |
6521 | ||
6522 | return val; | |
6523 | } | |
6524 | ||
eb48eb00 DV |
6525 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
6526 | { | |
6527 | unsigned long m, x, b; | |
6528 | u32 tsfs; | |
6529 | ||
6530 | tsfs = I915_READ(TSFS); | |
6531 | ||
6532 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
6533 | x = I915_READ8(TR1); | |
6534 | ||
6535 | b = tsfs & TSFS_INTR_MASK; | |
6536 | ||
6537 | return ((m * x) / 127) - b; | |
6538 | } | |
6539 | ||
d972d6ee MK |
6540 | static int _pxvid_to_vd(u8 pxvid) |
6541 | { | |
6542 | if (pxvid == 0) | |
6543 | return 0; | |
6544 | ||
6545 | if (pxvid >= 8 && pxvid < 31) | |
6546 | pxvid = 31; | |
6547 | ||
6548 | return (pxvid + 2) * 125; | |
6549 | } | |
6550 | ||
6551 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 6552 | { |
d972d6ee MK |
6553 | const int vd = _pxvid_to_vd(pxvid); |
6554 | const int vm = vd - 1125; | |
6555 | ||
dc97997a | 6556 | if (INTEL_INFO(dev_priv)->is_mobile) |
d972d6ee MK |
6557 | return vm > 0 ? vm : 0; |
6558 | ||
6559 | return vd; | |
eb48eb00 DV |
6560 | } |
6561 | ||
02d71956 | 6562 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 6563 | { |
5ed0bdf2 | 6564 | u64 now, diff, diffms; |
eb48eb00 DV |
6565 | u32 count; |
6566 | ||
67520415 | 6567 | lockdep_assert_held(&mchdev_lock); |
eb48eb00 | 6568 | |
5ed0bdf2 TG |
6569 | now = ktime_get_raw_ns(); |
6570 | diffms = now - dev_priv->ips.last_time2; | |
6571 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
6572 | |
6573 | /* Don't divide by 0 */ | |
eb48eb00 DV |
6574 | if (!diffms) |
6575 | return; | |
6576 | ||
6577 | count = I915_READ(GFXEC); | |
6578 | ||
20e4d407 DV |
6579 | if (count < dev_priv->ips.last_count2) { |
6580 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
6581 | diff += count; |
6582 | } else { | |
20e4d407 | 6583 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
6584 | } |
6585 | ||
20e4d407 DV |
6586 | dev_priv->ips.last_count2 = count; |
6587 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
6588 | |
6589 | /* More magic constants... */ | |
6590 | diff = diff * 1181; | |
6591 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 6592 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
6593 | } |
6594 | ||
02d71956 DV |
6595 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
6596 | { | |
dc97997a | 6597 | if (INTEL_INFO(dev_priv)->gen != 5) |
02d71956 DV |
6598 | return; |
6599 | ||
9270388e | 6600 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
6601 | |
6602 | __i915_update_gfx_val(dev_priv); | |
6603 | ||
9270388e | 6604 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
6605 | } |
6606 | ||
f531dcb2 | 6607 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
6608 | { |
6609 | unsigned long t, corr, state1, corr2, state2; | |
6610 | u32 pxvid, ext_v; | |
6611 | ||
67520415 | 6612 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 6613 | |
616847e7 | 6614 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
eb48eb00 DV |
6615 | pxvid = (pxvid >> 24) & 0x7f; |
6616 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
6617 | ||
6618 | state1 = ext_v; | |
6619 | ||
6620 | t = i915_mch_val(dev_priv); | |
6621 | ||
6622 | /* Revel in the empirically derived constants */ | |
6623 | ||
6624 | /* Correction factor in 1/100000 units */ | |
6625 | if (t > 80) | |
6626 | corr = ((t * 2349) + 135940); | |
6627 | else if (t >= 50) | |
6628 | corr = ((t * 964) + 29317); | |
6629 | else /* < 50 */ | |
6630 | corr = ((t * 301) + 1004); | |
6631 | ||
6632 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
6633 | corr /= 100000; | |
20e4d407 | 6634 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
6635 | |
6636 | state2 = (corr2 * state1) / 10000; | |
6637 | state2 /= 100; /* convert to mW */ | |
6638 | ||
02d71956 | 6639 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 6640 | |
20e4d407 | 6641 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
6642 | } |
6643 | ||
f531dcb2 CW |
6644 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
6645 | { | |
6646 | unsigned long val; | |
6647 | ||
dc97997a | 6648 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
6649 | return 0; |
6650 | ||
6651 | spin_lock_irq(&mchdev_lock); | |
6652 | ||
6653 | val = __i915_gfx_val(dev_priv); | |
6654 | ||
6655 | spin_unlock_irq(&mchdev_lock); | |
6656 | ||
6657 | return val; | |
6658 | } | |
6659 | ||
eb48eb00 DV |
6660 | /** |
6661 | * i915_read_mch_val - return value for IPS use | |
6662 | * | |
6663 | * Calculate and return a value for the IPS driver to use when deciding whether | |
6664 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
6665 | */ | |
6666 | unsigned long i915_read_mch_val(void) | |
6667 | { | |
6668 | struct drm_i915_private *dev_priv; | |
6669 | unsigned long chipset_val, graphics_val, ret = 0; | |
6670 | ||
9270388e | 6671 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6672 | if (!i915_mch_dev) |
6673 | goto out_unlock; | |
6674 | dev_priv = i915_mch_dev; | |
6675 | ||
f531dcb2 CW |
6676 | chipset_val = __i915_chipset_val(dev_priv); |
6677 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
6678 | |
6679 | ret = chipset_val + graphics_val; | |
6680 | ||
6681 | out_unlock: | |
9270388e | 6682 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6683 | |
6684 | return ret; | |
6685 | } | |
6686 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
6687 | ||
6688 | /** | |
6689 | * i915_gpu_raise - raise GPU frequency limit | |
6690 | * | |
6691 | * Raise the limit; IPS indicates we have thermal headroom. | |
6692 | */ | |
6693 | bool i915_gpu_raise(void) | |
6694 | { | |
6695 | struct drm_i915_private *dev_priv; | |
6696 | bool ret = true; | |
6697 | ||
9270388e | 6698 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6699 | if (!i915_mch_dev) { |
6700 | ret = false; | |
6701 | goto out_unlock; | |
6702 | } | |
6703 | dev_priv = i915_mch_dev; | |
6704 | ||
20e4d407 DV |
6705 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
6706 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
6707 | |
6708 | out_unlock: | |
9270388e | 6709 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6710 | |
6711 | return ret; | |
6712 | } | |
6713 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
6714 | ||
6715 | /** | |
6716 | * i915_gpu_lower - lower GPU frequency limit | |
6717 | * | |
6718 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
6719 | * frequency maximum. | |
6720 | */ | |
6721 | bool i915_gpu_lower(void) | |
6722 | { | |
6723 | struct drm_i915_private *dev_priv; | |
6724 | bool ret = true; | |
6725 | ||
9270388e | 6726 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6727 | if (!i915_mch_dev) { |
6728 | ret = false; | |
6729 | goto out_unlock; | |
6730 | } | |
6731 | dev_priv = i915_mch_dev; | |
6732 | ||
20e4d407 DV |
6733 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
6734 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
6735 | |
6736 | out_unlock: | |
9270388e | 6737 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6738 | |
6739 | return ret; | |
6740 | } | |
6741 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
6742 | ||
6743 | /** | |
6744 | * i915_gpu_busy - indicate GPU business to IPS | |
6745 | * | |
6746 | * Tell the IPS driver whether or not the GPU is busy. | |
6747 | */ | |
6748 | bool i915_gpu_busy(void) | |
6749 | { | |
eb48eb00 DV |
6750 | bool ret = false; |
6751 | ||
9270388e | 6752 | spin_lock_irq(&mchdev_lock); |
dcff85c8 CW |
6753 | if (i915_mch_dev) |
6754 | ret = i915_mch_dev->gt.awake; | |
9270388e | 6755 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6756 | |
6757 | return ret; | |
6758 | } | |
6759 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
6760 | ||
6761 | /** | |
6762 | * i915_gpu_turbo_disable - disable graphics turbo | |
6763 | * | |
6764 | * Disable graphics turbo by resetting the max frequency and setting the | |
6765 | * current frequency to the default. | |
6766 | */ | |
6767 | bool i915_gpu_turbo_disable(void) | |
6768 | { | |
6769 | struct drm_i915_private *dev_priv; | |
6770 | bool ret = true; | |
6771 | ||
9270388e | 6772 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
6773 | if (!i915_mch_dev) { |
6774 | ret = false; | |
6775 | goto out_unlock; | |
6776 | } | |
6777 | dev_priv = i915_mch_dev; | |
6778 | ||
20e4d407 | 6779 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 6780 | |
91d14251 | 6781 | if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart)) |
eb48eb00 DV |
6782 | ret = false; |
6783 | ||
6784 | out_unlock: | |
9270388e | 6785 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6786 | |
6787 | return ret; | |
6788 | } | |
6789 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
6790 | ||
6791 | /** | |
6792 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
6793 | * IPS got loaded first. | |
6794 | * | |
6795 | * This awkward dance is so that neither module has to depend on the | |
6796 | * other in order for IPS to do the appropriate communication of | |
6797 | * GPU turbo limits to i915. | |
6798 | */ | |
6799 | static void | |
6800 | ips_ping_for_i915_load(void) | |
6801 | { | |
6802 | void (*link)(void); | |
6803 | ||
6804 | link = symbol_get(ips_link_to_i915_driver); | |
6805 | if (link) { | |
6806 | link(); | |
6807 | symbol_put(ips_link_to_i915_driver); | |
6808 | } | |
6809 | } | |
6810 | ||
6811 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
6812 | { | |
02d71956 DV |
6813 | /* We only register the i915 ips part with intel-ips once everything is |
6814 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 6815 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 6816 | i915_mch_dev = dev_priv; |
9270388e | 6817 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
6818 | |
6819 | ips_ping_for_i915_load(); | |
6820 | } | |
6821 | ||
6822 | void intel_gpu_ips_teardown(void) | |
6823 | { | |
9270388e | 6824 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 6825 | i915_mch_dev = NULL; |
9270388e | 6826 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 6827 | } |
76c3552f | 6828 | |
dc97997a | 6829 | static void intel_init_emon(struct drm_i915_private *dev_priv) |
dde18883 | 6830 | { |
dde18883 ED |
6831 | u32 lcfuse; |
6832 | u8 pxw[16]; | |
6833 | int i; | |
6834 | ||
6835 | /* Disable to program */ | |
6836 | I915_WRITE(ECR, 0); | |
6837 | POSTING_READ(ECR); | |
6838 | ||
6839 | /* Program energy weights for various events */ | |
6840 | I915_WRITE(SDEW, 0x15040d00); | |
6841 | I915_WRITE(CSIEW0, 0x007f0000); | |
6842 | I915_WRITE(CSIEW1, 0x1e220004); | |
6843 | I915_WRITE(CSIEW2, 0x04000004); | |
6844 | ||
6845 | for (i = 0; i < 5; i++) | |
616847e7 | 6846 | I915_WRITE(PEW(i), 0); |
dde18883 | 6847 | for (i = 0; i < 3; i++) |
616847e7 | 6848 | I915_WRITE(DEW(i), 0); |
dde18883 ED |
6849 | |
6850 | /* Program P-state weights to account for frequency power adjustment */ | |
6851 | for (i = 0; i < 16; i++) { | |
616847e7 | 6852 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
dde18883 ED |
6853 | unsigned long freq = intel_pxfreq(pxvidfreq); |
6854 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
6855 | PXVFREQ_PX_SHIFT; | |
6856 | unsigned long val; | |
6857 | ||
6858 | val = vid * vid; | |
6859 | val *= (freq / 1000); | |
6860 | val *= 255; | |
6861 | val /= (127*127*900); | |
6862 | if (val > 0xff) | |
6863 | DRM_ERROR("bad pxval: %ld\n", val); | |
6864 | pxw[i] = val; | |
6865 | } | |
6866 | /* Render standby states get 0 weight */ | |
6867 | pxw[14] = 0; | |
6868 | pxw[15] = 0; | |
6869 | ||
6870 | for (i = 0; i < 4; i++) { | |
6871 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
6872 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
616847e7 | 6873 | I915_WRITE(PXW(i), val); |
dde18883 ED |
6874 | } |
6875 | ||
6876 | /* Adjust magic regs to magic values (more experimental results) */ | |
6877 | I915_WRITE(OGW0, 0); | |
6878 | I915_WRITE(OGW1, 0); | |
6879 | I915_WRITE(EG0, 0x00007f00); | |
6880 | I915_WRITE(EG1, 0x0000000e); | |
6881 | I915_WRITE(EG2, 0x000e0000); | |
6882 | I915_WRITE(EG3, 0x68000300); | |
6883 | I915_WRITE(EG4, 0x42000000); | |
6884 | I915_WRITE(EG5, 0x00140031); | |
6885 | I915_WRITE(EG6, 0); | |
6886 | I915_WRITE(EG7, 0); | |
6887 | ||
6888 | for (i = 0; i < 8; i++) | |
616847e7 | 6889 | I915_WRITE(PXWL(i), 0); |
dde18883 ED |
6890 | |
6891 | /* Enable PMON + select events */ | |
6892 | I915_WRITE(ECR, 0x80000019); | |
6893 | ||
6894 | lcfuse = I915_READ(LCFUSE02); | |
6895 | ||
20e4d407 | 6896 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
6897 | } |
6898 | ||
dc97997a | 6899 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 6900 | { |
b268c699 ID |
6901 | /* |
6902 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
6903 | * requirement. | |
6904 | */ | |
6905 | if (!i915.enable_rc6) { | |
6906 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
6907 | intel_runtime_pm_get(dev_priv); | |
6908 | } | |
e6069ca8 | 6909 | |
b5163dbb | 6910 | mutex_lock(&dev_priv->drm.struct_mutex); |
773ea9a8 CW |
6911 | mutex_lock(&dev_priv->rps.hw_lock); |
6912 | ||
6913 | /* Initialize RPS limits (for userspace) */ | |
dc97997a CW |
6914 | if (IS_CHERRYVIEW(dev_priv)) |
6915 | cherryview_init_gt_powersave(dev_priv); | |
6916 | else if (IS_VALLEYVIEW(dev_priv)) | |
6917 | valleyview_init_gt_powersave(dev_priv); | |
2a13ae79 | 6918 | else if (INTEL_GEN(dev_priv) >= 6) |
773ea9a8 CW |
6919 | gen6_init_rps_frequencies(dev_priv); |
6920 | ||
6921 | /* Derive initial user preferences/limits from the hardware limits */ | |
6922 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; | |
6923 | dev_priv->rps.cur_freq = dev_priv->rps.idle_freq; | |
6924 | ||
6925 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
6926 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
6927 | ||
6928 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
6929 | dev_priv->rps.min_freq_softlimit = | |
6930 | max_t(int, | |
6931 | dev_priv->rps.efficient_freq, | |
6932 | intel_freq_opcode(dev_priv, 450)); | |
6933 | ||
99ac9612 CW |
6934 | /* After setting max-softlimit, find the overclock max freq */ |
6935 | if (IS_GEN6(dev_priv) || | |
6936 | IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { | |
6937 | u32 params = 0; | |
6938 | ||
6939 | sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms); | |
6940 | if (params & BIT(31)) { /* OC supported */ | |
6941 | DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n", | |
6942 | (dev_priv->rps.max_freq & 0xff) * 50, | |
6943 | (params & 0xff) * 50); | |
6944 | dev_priv->rps.max_freq = params & 0xff; | |
6945 | } | |
6946 | } | |
6947 | ||
29ecd78d CW |
6948 | /* Finally allow us to boost to max by default */ |
6949 | dev_priv->rps.boost_freq = dev_priv->rps.max_freq; | |
6950 | ||
773ea9a8 | 6951 | mutex_unlock(&dev_priv->rps.hw_lock); |
b5163dbb | 6952 | mutex_unlock(&dev_priv->drm.struct_mutex); |
54b4f68f CW |
6953 | |
6954 | intel_autoenable_gt_powersave(dev_priv); | |
ae48434c ID |
6955 | } |
6956 | ||
dc97997a | 6957 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 6958 | { |
8dac1e1f | 6959 | if (IS_VALLEYVIEW(dev_priv)) |
dc97997a | 6960 | valleyview_cleanup_gt_powersave(dev_priv); |
b268c699 ID |
6961 | |
6962 | if (!i915.enable_rc6) | |
6963 | intel_runtime_pm_put(dev_priv); | |
ae48434c ID |
6964 | } |
6965 | ||
54b4f68f CW |
6966 | /** |
6967 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
6968 | * @dev_priv: i915 device | |
6969 | * | |
6970 | * We don't want to disable RC6 or other features here, we just want | |
6971 | * to make sure any work we've queued has finished and won't bother | |
6972 | * us while we're suspended. | |
6973 | */ | |
6974 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) | |
6975 | { | |
6976 | if (INTEL_GEN(dev_priv) < 6) | |
6977 | return; | |
6978 | ||
6979 | if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) | |
6980 | intel_runtime_pm_put(dev_priv); | |
6981 | ||
6982 | /* gen6_rps_idle() will be called later to disable interrupts */ | |
6983 | } | |
6984 | ||
b7137e0c CW |
6985 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) |
6986 | { | |
6987 | dev_priv->rps.enabled = true; /* force disabling */ | |
6988 | intel_disable_gt_powersave(dev_priv); | |
54b4f68f CW |
6989 | |
6990 | gen6_reset_rps_interrupts(dev_priv); | |
156c7ca0 JB |
6991 | } |
6992 | ||
dc97997a | 6993 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) |
8090c6b9 | 6994 | { |
b7137e0c CW |
6995 | if (!READ_ONCE(dev_priv->rps.enabled)) |
6996 | return; | |
e494837a | 6997 | |
b7137e0c | 6998 | mutex_lock(&dev_priv->rps.hw_lock); |
e534770a | 6999 | |
b7137e0c CW |
7000 | if (INTEL_GEN(dev_priv) >= 9) { |
7001 | gen9_disable_rc6(dev_priv); | |
7002 | gen9_disable_rps(dev_priv); | |
7003 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
7004 | cherryview_disable_rps(dev_priv); | |
7005 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7006 | valleyview_disable_rps(dev_priv); | |
7007 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
7008 | gen6_disable_rps(dev_priv); | |
7009 | } else if (IS_IRONLAKE_M(dev_priv)) { | |
7010 | ironlake_disable_drps(dev_priv); | |
930ebb46 | 7011 | } |
b7137e0c CW |
7012 | |
7013 | dev_priv->rps.enabled = false; | |
7014 | mutex_unlock(&dev_priv->rps.hw_lock); | |
8090c6b9 DV |
7015 | } |
7016 | ||
b7137e0c | 7017 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) |
1a01ab3b | 7018 | { |
54b4f68f CW |
7019 | /* We shouldn't be disabling as we submit, so this should be less |
7020 | * racy than it appears! | |
7021 | */ | |
b7137e0c CW |
7022 | if (READ_ONCE(dev_priv->rps.enabled)) |
7023 | return; | |
1a01ab3b | 7024 | |
b7137e0c CW |
7025 | /* Powersaving is controlled by the host when inside a VM */ |
7026 | if (intel_vgpu_active(dev_priv)) | |
7027 | return; | |
0a073b84 | 7028 | |
b7137e0c | 7029 | mutex_lock(&dev_priv->rps.hw_lock); |
dc97997a CW |
7030 | |
7031 | if (IS_CHERRYVIEW(dev_priv)) { | |
7032 | cherryview_enable_rps(dev_priv); | |
7033 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7034 | valleyview_enable_rps(dev_priv); | |
b7137e0c | 7035 | } else if (INTEL_GEN(dev_priv) >= 9) { |
dc97997a CW |
7036 | gen9_enable_rc6(dev_priv); |
7037 | gen9_enable_rps(dev_priv); | |
b976dc53 | 7038 | if (IS_GEN9_BC(dev_priv)) |
fb7404e8 | 7039 | gen6_update_ring_freq(dev_priv); |
dc97997a CW |
7040 | } else if (IS_BROADWELL(dev_priv)) { |
7041 | gen8_enable_rps(dev_priv); | |
fb7404e8 | 7042 | gen6_update_ring_freq(dev_priv); |
b7137e0c | 7043 | } else if (INTEL_GEN(dev_priv) >= 6) { |
dc97997a | 7044 | gen6_enable_rps(dev_priv); |
fb7404e8 | 7045 | gen6_update_ring_freq(dev_priv); |
b7137e0c CW |
7046 | } else if (IS_IRONLAKE_M(dev_priv)) { |
7047 | ironlake_enable_drps(dev_priv); | |
7048 | intel_init_emon(dev_priv); | |
0a073b84 | 7049 | } |
aed242ff CW |
7050 | |
7051 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); | |
7052 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); | |
7053 | ||
7054 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); | |
7055 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); | |
7056 | ||
54b4f68f | 7057 | dev_priv->rps.enabled = true; |
b7137e0c CW |
7058 | mutex_unlock(&dev_priv->rps.hw_lock); |
7059 | } | |
3cc134e3 | 7060 | |
54b4f68f CW |
7061 | static void __intel_autoenable_gt_powersave(struct work_struct *work) |
7062 | { | |
7063 | struct drm_i915_private *dev_priv = | |
7064 | container_of(work, typeof(*dev_priv), rps.autoenable_work.work); | |
7065 | struct intel_engine_cs *rcs; | |
7066 | struct drm_i915_gem_request *req; | |
7067 | ||
7068 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7069 | goto out; | |
7070 | ||
3b3f1650 | 7071 | rcs = dev_priv->engine[RCS]; |
e8a9c58f | 7072 | if (rcs->last_retired_context) |
54b4f68f CW |
7073 | goto out; |
7074 | ||
7075 | if (!rcs->init_context) | |
7076 | goto out; | |
7077 | ||
7078 | mutex_lock(&dev_priv->drm.struct_mutex); | |
7079 | ||
7080 | req = i915_gem_request_alloc(rcs, dev_priv->kernel_context); | |
7081 | if (IS_ERR(req)) | |
7082 | goto unlock; | |
7083 | ||
7084 | if (!i915.enable_execlists && i915_switch_context(req) == 0) | |
7085 | rcs->init_context(req); | |
7086 | ||
7087 | /* Mark the device busy, calling intel_enable_gt_powersave() */ | |
7088 | i915_add_request_no_flush(req); | |
7089 | ||
7090 | unlock: | |
7091 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
7092 | out: | |
7093 | intel_runtime_pm_put(dev_priv); | |
7094 | } | |
7095 | ||
7096 | void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv) | |
7097 | { | |
7098 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7099 | return; | |
7100 | ||
7101 | if (IS_IRONLAKE_M(dev_priv)) { | |
7102 | ironlake_enable_drps(dev_priv); | |
54b4f68f | 7103 | intel_init_emon(dev_priv); |
54b4f68f CW |
7104 | } else if (INTEL_INFO(dev_priv)->gen >= 6) { |
7105 | /* | |
7106 | * PCU communication is slow and this doesn't need to be | |
7107 | * done at any specific time, so do this out of our fast path | |
7108 | * to make resume and init faster. | |
7109 | * | |
7110 | * We depend on the HW RC6 power context save/restore | |
7111 | * mechanism when entering D3 through runtime PM suspend. So | |
7112 | * disable RPM until RPS/RC6 is properly setup. We can only | |
7113 | * get here via the driver load/system resume/runtime resume | |
7114 | * paths, so the _noresume version is enough (and in case of | |
7115 | * runtime resume it's necessary). | |
7116 | */ | |
7117 | if (queue_delayed_work(dev_priv->wq, | |
7118 | &dev_priv->rps.autoenable_work, | |
7119 | round_jiffies_up_relative(HZ))) | |
7120 | intel_runtime_pm_get_noresume(dev_priv); | |
7121 | } | |
7122 | } | |
7123 | ||
46f16e63 | 7124 | static void ibx_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 7125 | { |
3107bd48 DV |
7126 | /* |
7127 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7128 | * gating for the panel power sequencer or it will fail to | |
7129 | * start up when no ports are active. | |
7130 | */ | |
7131 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
7132 | } | |
7133 | ||
46f16e63 | 7134 | static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) |
0e088b8f | 7135 | { |
b12ce1d8 | 7136 | enum pipe pipe; |
0e088b8f | 7137 | |
055e393f | 7138 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
7139 | I915_WRITE(DSPCNTR(pipe), |
7140 | I915_READ(DSPCNTR(pipe)) | | |
7141 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
b12ce1d8 VS |
7142 | |
7143 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); | |
7144 | POSTING_READ(DSPSURF(pipe)); | |
0e088b8f VS |
7145 | } |
7146 | } | |
7147 | ||
46f16e63 | 7148 | static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) |
017636cc | 7149 | { |
017636cc VS |
7150 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
7151 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
7152 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
7153 | ||
7154 | /* | |
7155 | * Don't touch WM1S_LP_EN here. | |
7156 | * Doing so could cause underruns. | |
7157 | */ | |
7158 | } | |
7159 | ||
46f16e63 | 7160 | static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7161 | { |
231e54f6 | 7162 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 7163 | |
f1e8fa56 DL |
7164 | /* |
7165 | * Required for FBC | |
7166 | * WaFbcDisableDpfcClockGating:ilk | |
7167 | */ | |
4d47e4f5 DL |
7168 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
7169 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
7170 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
7171 | |
7172 | I915_WRITE(PCH_3DCGDIS0, | |
7173 | MARIUNIT_CLOCK_GATE_DISABLE | | |
7174 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
7175 | I915_WRITE(PCH_3DCGDIS1, | |
7176 | VFMUNIT_CLOCK_GATE_DISABLE); | |
7177 | ||
6f1d69b0 ED |
7178 | /* |
7179 | * According to the spec the following bits should be set in | |
7180 | * order to enable memory self-refresh | |
7181 | * The bit 22/21 of 0x42004 | |
7182 | * The bit 5 of 0x42020 | |
7183 | * The bit 15 of 0x45000 | |
7184 | */ | |
7185 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7186 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7187 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 7188 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
7189 | I915_WRITE(DISP_ARB_CTL, |
7190 | (I915_READ(DISP_ARB_CTL) | | |
7191 | DISP_FBC_WM_DIS)); | |
017636cc | 7192 | |
46f16e63 | 7193 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 ED |
7194 | |
7195 | /* | |
7196 | * Based on the document from hardware guys the following bits | |
7197 | * should be set unconditionally in order to enable FBC. | |
7198 | * The bit 22 of 0x42000 | |
7199 | * The bit 22 of 0x42004 | |
7200 | * The bit 7,8,9 of 0x42020. | |
7201 | */ | |
50a0bc90 | 7202 | if (IS_IRONLAKE_M(dev_priv)) { |
4bb35334 | 7203 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
7204 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
7205 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7206 | ILK_FBCQ_DIS); | |
7207 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7208 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7209 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
7210 | } |
7211 | ||
4d47e4f5 DL |
7212 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
7213 | ||
6f1d69b0 ED |
7214 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
7215 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7216 | ILK_ELPIN_409_SELECT); | |
7217 | I915_WRITE(_3D_CHICKEN2, | |
7218 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
7219 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 7220 | |
ecdb4eb7 | 7221 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
7222 | I915_WRITE(CACHE_MODE_0, |
7223 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 7224 | |
4e04632e AG |
7225 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
7226 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7227 | ||
46f16e63 | 7228 | g4x_disable_trickle_feed(dev_priv); |
bdad2b2f | 7229 | |
46f16e63 | 7230 | ibx_init_clock_gating(dev_priv); |
3107bd48 DV |
7231 | } |
7232 | ||
46f16e63 | 7233 | static void cpt_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 7234 | { |
3107bd48 | 7235 | int pipe; |
3f704fa2 | 7236 | uint32_t val; |
3107bd48 DV |
7237 | |
7238 | /* | |
7239 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7240 | * gating for the panel power sequencer or it will fail to | |
7241 | * start up when no ports are active. | |
7242 | */ | |
cd664078 JB |
7243 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
7244 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
7245 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
7246 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
7247 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
7248 | /* The below fixes the weird display corruption, a few pixels shifted |
7249 | * downward, on (only) LVDS of some HP laptops with IVY. | |
7250 | */ | |
055e393f | 7251 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
7252 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
7253 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
7254 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 7255 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 7256 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
7257 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
7258 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
7259 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
7260 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
7261 | } | |
3107bd48 | 7262 | /* WADP0ClockGatingDisable */ |
055e393f | 7263 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
7264 | I915_WRITE(TRANS_CHICKEN1(pipe), |
7265 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
7266 | } | |
6f1d69b0 ED |
7267 | } |
7268 | ||
46f16e63 | 7269 | static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) |
1d7aaa0c | 7270 | { |
1d7aaa0c DV |
7271 | uint32_t tmp; |
7272 | ||
7273 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
7274 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
7275 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
7276 | tmp); | |
1d7aaa0c DV |
7277 | } |
7278 | ||
46f16e63 | 7279 | static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7280 | { |
231e54f6 | 7281 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 7282 | |
231e54f6 | 7283 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
7284 | |
7285 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7286 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7287 | ILK_ELPIN_409_SELECT); | |
7288 | ||
ecdb4eb7 | 7289 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
7290 | I915_WRITE(_3D_CHICKEN, |
7291 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
7292 | ||
4e04632e AG |
7293 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
7294 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7295 | ||
8d85d272 VS |
7296 | /* |
7297 | * BSpec recoomends 8x4 when MSAA is used, | |
7298 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
7299 | * |
7300 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7301 | * disable bit, which we don't touch here, but it's good | |
7302 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
7303 | */ |
7304 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 7305 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 7306 | |
46f16e63 | 7307 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 7308 | |
6f1d69b0 | 7309 | I915_WRITE(CACHE_MODE_0, |
50743298 | 7310 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
7311 | |
7312 | I915_WRITE(GEN6_UCGCTL1, | |
7313 | I915_READ(GEN6_UCGCTL1) | | |
7314 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
7315 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
7316 | ||
7317 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
7318 | * gating disable must be set. Failure to set it results in | |
7319 | * flickering pixels due to Z write ordering failures after | |
7320 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
7321 | * Sanctuary and Tropics, and apparently anything else with | |
7322 | * alpha test or pixel discard. | |
7323 | * | |
7324 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
7325 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 7326 | * |
ef59318c VS |
7327 | * WaDisableRCCUnitClockGating:snb |
7328 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
7329 | */ |
7330 | I915_WRITE(GEN6_UCGCTL2, | |
7331 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
7332 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
7333 | ||
5eb146dd | 7334 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
7335 | I915_WRITE(_3D_CHICKEN3, |
7336 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 7337 | |
e927ecde VS |
7338 | /* |
7339 | * Bspec says: | |
7340 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
7341 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
7342 | */ | |
7343 | I915_WRITE(_3D_CHICKEN3, | |
7344 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
7345 | ||
6f1d69b0 ED |
7346 | /* |
7347 | * According to the spec the following bits should be | |
7348 | * set in order to enable memory self-refresh and fbc: | |
7349 | * The bit21 and bit22 of 0x42000 | |
7350 | * The bit21 and bit22 of 0x42004 | |
7351 | * The bit5 and bit7 of 0x42020 | |
7352 | * The bit14 of 0x70180 | |
7353 | * The bit14 of 0x71180 | |
4bb35334 DL |
7354 | * |
7355 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
7356 | */ |
7357 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
7358 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
7359 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
7360 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
7361 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
7362 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
7363 | I915_WRITE(ILK_DSPCLK_GATE_D, |
7364 | I915_READ(ILK_DSPCLK_GATE_D) | | |
7365 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
7366 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 7367 | |
46f16e63 | 7368 | g4x_disable_trickle_feed(dev_priv); |
f8f2ac9a | 7369 | |
46f16e63 | 7370 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 7371 | |
46f16e63 | 7372 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
7373 | } |
7374 | ||
7375 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
7376 | { | |
7377 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
7378 | ||
3aad9059 | 7379 | /* |
46680e0a | 7380 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
7381 | * |
7382 | * This actually overrides the dispatch | |
7383 | * mode for all thread types. | |
7384 | */ | |
6f1d69b0 ED |
7385 | reg &= ~GEN7_FF_SCHED_MASK; |
7386 | reg |= GEN7_FF_TS_SCHED_HW; | |
7387 | reg |= GEN7_FF_VS_SCHED_HW; | |
7388 | reg |= GEN7_FF_DS_SCHED_HW; | |
7389 | ||
7390 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
7391 | } | |
7392 | ||
46f16e63 | 7393 | static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) |
17a303ec | 7394 | { |
17a303ec PZ |
7395 | /* |
7396 | * TODO: this bit should only be enabled when really needed, then | |
7397 | * disabled when not needed anymore in order to save power. | |
7398 | */ | |
4f8036a2 | 7399 | if (HAS_PCH_LPT_LP(dev_priv)) |
17a303ec PZ |
7400 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
7401 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
7402 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
7403 | |
7404 | /* WADPOClockGatingDisable:hsw */ | |
36c0d0cf VS |
7405 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
7406 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | | |
0a790cdb | 7407 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
17a303ec PZ |
7408 | } |
7409 | ||
712bf364 | 7410 | static void lpt_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 7411 | { |
4f8036a2 | 7412 | if (HAS_PCH_LPT_LP(dev_priv)) { |
7d708ee4 ID |
7413 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
7414 | ||
7415 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7416 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7417 | } | |
7418 | } | |
7419 | ||
450174fe ID |
7420 | static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, |
7421 | int general_prio_credits, | |
7422 | int high_prio_credits) | |
7423 | { | |
7424 | u32 misccpctl; | |
7425 | ||
7426 | /* WaTempDisableDOPClkGating:bdw */ | |
7427 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
7428 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
7429 | ||
7430 | I915_WRITE(GEN8_L3SQCREG1, | |
7431 | L3_GENERAL_PRIO_CREDITS(general_prio_credits) | | |
7432 | L3_HIGH_PRIO_CREDITS(high_prio_credits)); | |
7433 | ||
7434 | /* | |
7435 | * Wait at least 100 clocks before re-enabling clock gating. | |
7436 | * See the definition of L3SQCREG1 in BSpec. | |
7437 | */ | |
7438 | POSTING_READ(GEN8_L3SQCREG1); | |
7439 | udelay(1); | |
7440 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
7441 | } | |
7442 | ||
46f16e63 | 7443 | static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) |
9498dba7 | 7444 | { |
46f16e63 | 7445 | gen9_init_clock_gating(dev_priv); |
9498dba7 MK |
7446 | |
7447 | /* WaDisableSDEUnitClockGating:kbl */ | |
7448 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
7449 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
7450 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
8aeb7f62 MK |
7451 | |
7452 | /* WaDisableGamClockGating:kbl */ | |
7453 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
7454 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
7455 | GEN6_GAMUNIT_CLOCK_GATE_DISABLE); | |
031cd8c8 MK |
7456 | |
7457 | /* WaFbcNukeOnHostModify:kbl */ | |
7458 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
7459 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
9498dba7 MK |
7460 | } |
7461 | ||
46f16e63 | 7462 | static void skylake_init_clock_gating(struct drm_i915_private *dev_priv) |
dc00b6a0 | 7463 | { |
46f16e63 | 7464 | gen9_init_clock_gating(dev_priv); |
44fff99f MK |
7465 | |
7466 | /* WAC6entrylatency:skl */ | |
7467 | I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | | |
7468 | FBC_LLC_FULLY_OPEN); | |
031cd8c8 MK |
7469 | |
7470 | /* WaFbcNukeOnHostModify:skl */ | |
7471 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
7472 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
dc00b6a0 DV |
7473 | } |
7474 | ||
46f16e63 | 7475 | static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) |
1020a5c2 | 7476 | { |
07d27e20 | 7477 | enum pipe pipe; |
1020a5c2 | 7478 | |
46f16e63 | 7479 | ilk_init_lp_watermarks(dev_priv); |
50ed5fbd | 7480 | |
ab57fff1 | 7481 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 7482 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 7483 | |
ab57fff1 | 7484 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
7485 | I915_WRITE(CHICKEN_PAR1_1, |
7486 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
7487 | ||
ab57fff1 | 7488 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 7489 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 7490 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 7491 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 7492 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 7493 | } |
63801f21 | 7494 | |
ab57fff1 BW |
7495 | /* WaVSRefCountFullforceMissDisable:bdw */ |
7496 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
7497 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
7498 | I915_READ(GEN7_FF_THREAD_MODE) & | |
7499 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 7500 | |
295e8bb7 VS |
7501 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
7502 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
7503 | |
7504 | /* WaDisableSDEUnitClockGating:bdw */ | |
7505 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
7506 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 7507 | |
450174fe ID |
7508 | /* WaProgramL3SqcReg1Default:bdw */ |
7509 | gen8_set_l3sqc_credits(dev_priv, 30, 2); | |
4d487cff | 7510 | |
6d50b065 VS |
7511 | /* |
7512 | * WaGttCachingOffByDefault:bdw | |
7513 | * GTT cache may not work with big pages, so if those | |
7514 | * are ever enabled GTT cache may need to be disabled. | |
7515 | */ | |
7516 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
7517 | ||
17e0adf0 MK |
7518 | /* WaKVMNotificationOnConfigChange:bdw */ |
7519 | I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) | |
7520 | | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); | |
7521 | ||
46f16e63 | 7522 | lpt_init_clock_gating(dev_priv); |
9cc19733 RB |
7523 | |
7524 | /* WaDisableDopClockGating:bdw | |
7525 | * | |
7526 | * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP | |
7527 | * clock gating. | |
7528 | */ | |
7529 | I915_WRITE(GEN6_UCGCTL1, | |
7530 | I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); | |
1020a5c2 BW |
7531 | } |
7532 | ||
46f16e63 | 7533 | static void haswell_init_clock_gating(struct drm_i915_private *dev_priv) |
cad2a2d7 | 7534 | { |
46f16e63 | 7535 | ilk_init_lp_watermarks(dev_priv); |
cad2a2d7 | 7536 | |
f3fc4884 FJ |
7537 | /* L3 caching of data atomics doesn't work -- disable it. */ |
7538 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
7539 | I915_WRITE(HSW_ROW_CHICKEN3, | |
7540 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
7541 | ||
ecdb4eb7 | 7542 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
7543 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
7544 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
7545 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
7546 | ||
e36ea7ff VS |
7547 | /* WaVSRefCountFullforceMissDisable:hsw */ |
7548 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
7549 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 7550 | |
4e04632e AG |
7551 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
7552 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7553 | ||
fe27c606 CW |
7554 | /* enable HiZ Raw Stall Optimization */ |
7555 | I915_WRITE(CACHE_MODE_0_GEN7, | |
7556 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
7557 | ||
ecdb4eb7 | 7558 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
7559 | I915_WRITE(CACHE_MODE_1, |
7560 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 7561 | |
a12c4967 VS |
7562 | /* |
7563 | * BSpec recommends 8x4 when MSAA is used, | |
7564 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
7565 | * |
7566 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7567 | * disable bit, which we don't touch here, but it's good | |
7568 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
7569 | */ |
7570 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 7571 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 7572 | |
94411593 KG |
7573 | /* WaSampleCChickenBitEnable:hsw */ |
7574 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
7575 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
7576 | ||
ecdb4eb7 | 7577 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
7578 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
7579 | ||
90a88643 PZ |
7580 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
7581 | I915_WRITE(CHICKEN_PAR1_1, | |
7582 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 7583 | |
46f16e63 | 7584 | lpt_init_clock_gating(dev_priv); |
cad2a2d7 ED |
7585 | } |
7586 | ||
46f16e63 | 7587 | static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7588 | { |
20848223 | 7589 | uint32_t snpcr; |
6f1d69b0 | 7590 | |
46f16e63 | 7591 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 7592 | |
231e54f6 | 7593 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 7594 | |
ecdb4eb7 | 7595 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
7596 | I915_WRITE(_3D_CHICKEN3, |
7597 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
7598 | ||
ecdb4eb7 | 7599 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
7600 | I915_WRITE(IVB_CHICKEN3, |
7601 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
7602 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
7603 | ||
ecdb4eb7 | 7604 | /* WaDisablePSDDualDispatchEnable:ivb */ |
50a0bc90 | 7605 | if (IS_IVB_GT1(dev_priv)) |
12f3382b JB |
7606 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
7607 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 7608 | |
4e04632e AG |
7609 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
7610 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7611 | ||
ecdb4eb7 | 7612 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
7613 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
7614 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
7615 | ||
ecdb4eb7 | 7616 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
7617 | I915_WRITE(GEN7_L3CNTLREG1, |
7618 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
7619 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 | 7620 | GEN7_WA_L3_CHICKEN_MODE); |
50a0bc90 | 7621 | if (IS_IVB_GT1(dev_priv)) |
8ab43976 JB |
7622 | I915_WRITE(GEN7_ROW_CHICKEN2, |
7623 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
7624 | else { |
7625 | /* must write both registers */ | |
7626 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
7627 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
7628 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
7629 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 7630 | } |
6f1d69b0 | 7631 | |
ecdb4eb7 | 7632 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
7633 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
7634 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
7635 | ||
1b80a19a | 7636 | /* |
0f846f81 | 7637 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 7638 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
7639 | */ |
7640 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 7641 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 7642 | |
ecdb4eb7 | 7643 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
7644 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
7645 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
7646 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
7647 | ||
46f16e63 | 7648 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
7649 | |
7650 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 7651 | |
22721343 CW |
7652 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
7653 | /* enable HiZ Raw Stall Optimization */ | |
7654 | I915_WRITE(CACHE_MODE_0_GEN7, | |
7655 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
7656 | } | |
116f2b6d | 7657 | |
ecdb4eb7 | 7658 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
7659 | I915_WRITE(CACHE_MODE_1, |
7660 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 7661 | |
a607c1a4 VS |
7662 | /* |
7663 | * BSpec recommends 8x4 when MSAA is used, | |
7664 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
7665 | * |
7666 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7667 | * disable bit, which we don't touch here, but it's good | |
7668 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
7669 | */ |
7670 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 7671 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 7672 | |
20848223 BW |
7673 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
7674 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
7675 | snpcr |= GEN6_MBC_SNPCR_MED; | |
7676 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 7677 | |
6e266956 | 7678 | if (!HAS_PCH_NOP(dev_priv)) |
46f16e63 | 7679 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 7680 | |
46f16e63 | 7681 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
7682 | } |
7683 | ||
46f16e63 | 7684 | static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7685 | { |
ecdb4eb7 | 7686 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
7687 | I915_WRITE(_3D_CHICKEN3, |
7688 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
7689 | ||
ecdb4eb7 | 7690 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
7691 | I915_WRITE(IVB_CHICKEN3, |
7692 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
7693 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
7694 | ||
fad7d36e | 7695 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 7696 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 7697 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
7698 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
7699 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 7700 | |
4e04632e AG |
7701 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
7702 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7703 | ||
ecdb4eb7 | 7704 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
7705 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
7706 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
7707 | ||
ecdb4eb7 | 7708 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
7709 | I915_WRITE(GEN7_ROW_CHICKEN2, |
7710 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
7711 | ||
ecdb4eb7 | 7712 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
7713 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
7714 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
7715 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
7716 | ||
46680e0a VS |
7717 | gen7_setup_fixed_func_scheduler(dev_priv); |
7718 | ||
3c0edaeb | 7719 | /* |
0f846f81 | 7720 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 7721 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
7722 | */ |
7723 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 7724 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 7725 | |
c98f5062 AG |
7726 | /* WaDisableL3Bank2xClockGate:vlv |
7727 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
7728 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
7729 | I915_WRITE(GEN7_UCGCTL4, | |
7730 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 7731 | |
afd58e79 VS |
7732 | /* |
7733 | * BSpec says this must be set, even though | |
7734 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
7735 | */ | |
6b26c86d DV |
7736 | I915_WRITE(CACHE_MODE_1, |
7737 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 7738 | |
da2518f9 VS |
7739 | /* |
7740 | * BSpec recommends 8x4 when MSAA is used, | |
7741 | * however in practice 16x4 seems fastest. | |
7742 | * | |
7743 | * Note that PS/WM thread counts depend on the WIZ hashing | |
7744 | * disable bit, which we don't touch here, but it's good | |
7745 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
7746 | */ | |
7747 | I915_WRITE(GEN7_GT_MODE, | |
7748 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
7749 | ||
031994ee VS |
7750 | /* |
7751 | * WaIncreaseL3CreditsForVLVB0:vlv | |
7752 | * This is the hardware default actually. | |
7753 | */ | |
7754 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
7755 | ||
2d809570 | 7756 | /* |
ecdb4eb7 | 7757 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
7758 | * Disable clock gating on th GCFG unit to prevent a delay |
7759 | * in the reporting of vblank events. | |
7760 | */ | |
7a0d1eed | 7761 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
7762 | } |
7763 | ||
46f16e63 | 7764 | static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) |
a4565da8 | 7765 | { |
232ce337 VS |
7766 | /* WaVSRefCountFullforceMissDisable:chv */ |
7767 | /* WaDSRefCountFullforceMissDisable:chv */ | |
7768 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
7769 | I915_READ(GEN7_FF_THREAD_MODE) & | |
7770 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
7771 | |
7772 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
7773 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
7774 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
7775 | |
7776 | /* WaDisableCSUnitClockGating:chv */ | |
7777 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
7778 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
7779 | |
7780 | /* WaDisableSDEUnitClockGating:chv */ | |
7781 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
7782 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6d50b065 | 7783 | |
450174fe ID |
7784 | /* |
7785 | * WaProgramL3SqcReg1Default:chv | |
7786 | * See gfxspecs/Related Documents/Performance Guide/ | |
7787 | * LSQC Setting Recommendations. | |
7788 | */ | |
7789 | gen8_set_l3sqc_credits(dev_priv, 38, 2); | |
7790 | ||
6d50b065 VS |
7791 | /* |
7792 | * GTT cache may not work with big pages, so if those | |
7793 | * are ever enabled GTT cache may need to be disabled. | |
7794 | */ | |
7795 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
a4565da8 VS |
7796 | } |
7797 | ||
46f16e63 | 7798 | static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7799 | { |
6f1d69b0 ED |
7800 | uint32_t dspclk_gate; |
7801 | ||
7802 | I915_WRITE(RENCLK_GATE_D1, 0); | |
7803 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
7804 | GS_UNIT_CLOCK_GATE_DISABLE | | |
7805 | CL_UNIT_CLOCK_GATE_DISABLE); | |
7806 | I915_WRITE(RAMCLK_GATE_D, 0); | |
7807 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
7808 | OVRUNIT_CLOCK_GATE_DISABLE | | |
7809 | OVCUNIT_CLOCK_GATE_DISABLE; | |
50a0bc90 | 7810 | if (IS_GM45(dev_priv)) |
6f1d69b0 ED |
7811 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
7812 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
7813 | |
7814 | /* WaDisableRenderCachePipelinedFlush */ | |
7815 | I915_WRITE(CACHE_MODE_0, | |
7816 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 7817 | |
4e04632e AG |
7818 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
7819 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
7820 | ||
46f16e63 | 7821 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
7822 | } |
7823 | ||
46f16e63 | 7824 | static void crestline_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7825 | { |
6f1d69b0 ED |
7826 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
7827 | I915_WRITE(RENCLK_GATE_D2, 0); | |
7828 | I915_WRITE(DSPCLK_GATE_D, 0); | |
7829 | I915_WRITE(RAMCLK_GATE_D, 0); | |
7830 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
7831 | I915_WRITE(MI_ARB_STATE, |
7832 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
7833 | |
7834 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
7835 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
7836 | } |
7837 | ||
46f16e63 | 7838 | static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7839 | { |
6f1d69b0 ED |
7840 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
7841 | I965_RCC_CLOCK_GATE_DISABLE | | |
7842 | I965_RCPB_CLOCK_GATE_DISABLE | | |
7843 | I965_ISC_CLOCK_GATE_DISABLE | | |
7844 | I965_FBC_CLOCK_GATE_DISABLE); | |
7845 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
7846 | I915_WRITE(MI_ARB_STATE, |
7847 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
7848 | |
7849 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
7850 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
7851 | } |
7852 | ||
46f16e63 | 7853 | static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7854 | { |
6f1d69b0 ED |
7855 | u32 dstate = I915_READ(D_STATE); |
7856 | ||
7857 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
7858 | DSTATE_DOT_CLOCK_GATING; | |
7859 | I915_WRITE(D_STATE, dstate); | |
13a86b85 | 7860 | |
9b1e14f4 | 7861 | if (IS_PINEVIEW(dev_priv)) |
13a86b85 | 7862 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
974a3b0f DV |
7863 | |
7864 | /* IIR "flip pending" means done if this bit is set */ | |
7865 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
7866 | |
7867 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 7868 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
7869 | |
7870 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
7871 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
7872 | |
7873 | I915_WRITE(MI_ARB_STATE, | |
7874 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7875 | } |
7876 | ||
46f16e63 | 7877 | static void i85x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7878 | { |
6f1d69b0 | 7879 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
54e472ae VS |
7880 | |
7881 | /* interrupts should cause a wake up from C3 */ | |
7882 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
7883 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
7884 | |
7885 | I915_WRITE(MEM_MODE, | |
7886 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7887 | } |
7888 | ||
46f16e63 | 7889 | static void i830_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7890 | { |
1038392b VS |
7891 | I915_WRITE(MEM_MODE, |
7892 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
7893 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
7894 | } |
7895 | ||
46f16e63 | 7896 | void intel_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7897 | { |
46f16e63 | 7898 | dev_priv->display.init_clock_gating(dev_priv); |
6f1d69b0 ED |
7899 | } |
7900 | ||
712bf364 | 7901 | void intel_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 7902 | { |
712bf364 VS |
7903 | if (HAS_PCH_LPT(dev_priv)) |
7904 | lpt_suspend_hw(dev_priv); | |
7d708ee4 ID |
7905 | } |
7906 | ||
46f16e63 | 7907 | static void nop_init_clock_gating(struct drm_i915_private *dev_priv) |
bb400da9 ID |
7908 | { |
7909 | DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n"); | |
7910 | } | |
7911 | ||
7912 | /** | |
7913 | * intel_init_clock_gating_hooks - setup the clock gating hooks | |
7914 | * @dev_priv: device private | |
7915 | * | |
7916 | * Setup the hooks that configure which clocks of a given platform can be | |
7917 | * gated and also apply various GT and display specific workarounds for these | |
7918 | * platforms. Note that some GT specific workarounds are applied separately | |
7919 | * when GPU contexts or batchbuffers start their execution. | |
7920 | */ | |
7921 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) | |
7922 | { | |
7923 | if (IS_SKYLAKE(dev_priv)) | |
dc00b6a0 | 7924 | dev_priv->display.init_clock_gating = skylake_init_clock_gating; |
bb400da9 | 7925 | else if (IS_KABYLAKE(dev_priv)) |
9498dba7 | 7926 | dev_priv->display.init_clock_gating = kabylake_init_clock_gating; |
9fb5026f | 7927 | else if (IS_BROXTON(dev_priv)) |
bb400da9 | 7928 | dev_priv->display.init_clock_gating = bxt_init_clock_gating; |
9fb5026f ACO |
7929 | else if (IS_GEMINILAKE(dev_priv)) |
7930 | dev_priv->display.init_clock_gating = glk_init_clock_gating; | |
bb400da9 ID |
7931 | else if (IS_BROADWELL(dev_priv)) |
7932 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; | |
7933 | else if (IS_CHERRYVIEW(dev_priv)) | |
7934 | dev_priv->display.init_clock_gating = cherryview_init_clock_gating; | |
7935 | else if (IS_HASWELL(dev_priv)) | |
7936 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; | |
7937 | else if (IS_IVYBRIDGE(dev_priv)) | |
7938 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; | |
7939 | else if (IS_VALLEYVIEW(dev_priv)) | |
7940 | dev_priv->display.init_clock_gating = valleyview_init_clock_gating; | |
7941 | else if (IS_GEN6(dev_priv)) | |
7942 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; | |
7943 | else if (IS_GEN5(dev_priv)) | |
7944 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; | |
7945 | else if (IS_G4X(dev_priv)) | |
7946 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
c0f86832 | 7947 | else if (IS_I965GM(dev_priv)) |
bb400da9 | 7948 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
c0f86832 | 7949 | else if (IS_I965G(dev_priv)) |
bb400da9 ID |
7950 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
7951 | else if (IS_GEN3(dev_priv)) | |
7952 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
7953 | else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) | |
7954 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
7955 | else if (IS_GEN2(dev_priv)) | |
7956 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
7957 | else { | |
7958 | MISSING_CASE(INTEL_DEVID(dev_priv)); | |
7959 | dev_priv->display.init_clock_gating = nop_init_clock_gating; | |
7960 | } | |
7961 | } | |
7962 | ||
1fa61106 | 7963 | /* Set up chip specific power management-related functions */ |
62d75df7 | 7964 | void intel_init_pm(struct drm_i915_private *dev_priv) |
1fa61106 | 7965 | { |
7ff0ebcc | 7966 | intel_fbc_init(dev_priv); |
1fa61106 | 7967 | |
c921aba8 | 7968 | /* For cxsr */ |
9b1e14f4 | 7969 | if (IS_PINEVIEW(dev_priv)) |
148ac1f3 | 7970 | i915_pineview_get_mem_freq(dev_priv); |
5db94019 | 7971 | else if (IS_GEN5(dev_priv)) |
148ac1f3 | 7972 | i915_ironlake_get_mem_freq(dev_priv); |
c921aba8 | 7973 | |
1fa61106 | 7974 | /* For FIFO watermark updates */ |
62d75df7 | 7975 | if (INTEL_GEN(dev_priv) >= 9) { |
bb726519 | 7976 | skl_setup_wm_latency(dev_priv); |
e62929b3 | 7977 | dev_priv->display.initial_watermarks = skl_initial_wm; |
ccf010fb | 7978 | dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; |
98d39494 | 7979 | dev_priv->display.compute_global_watermarks = skl_compute_wm; |
6e266956 | 7980 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bb726519 | 7981 | ilk_setup_wm_latency(dev_priv); |
53615a5e | 7982 | |
5db94019 | 7983 | if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && |
bd602544 | 7984 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
5db94019 | 7985 | (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && |
bd602544 | 7986 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
86c8bbbe | 7987 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
ed4a6a7c MR |
7988 | dev_priv->display.compute_intermediate_wm = |
7989 | ilk_compute_intermediate_wm; | |
7990 | dev_priv->display.initial_watermarks = | |
7991 | ilk_initial_watermarks; | |
7992 | dev_priv->display.optimize_watermarks = | |
7993 | ilk_optimize_watermarks; | |
bd602544 VS |
7994 | } else { |
7995 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
7996 | "Disable CxSR\n"); | |
7997 | } | |
6b6b3eef | 7998 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bb726519 | 7999 | vlv_setup_wm_latency(dev_priv); |
ff32c54e | 8000 | dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm; |
4841da51 | 8001 | dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm; |
ff32c54e | 8002 | dev_priv->display.initial_watermarks = vlv_initial_watermarks; |
4841da51 | 8003 | dev_priv->display.optimize_watermarks = vlv_optimize_watermarks; |
ff32c54e | 8004 | dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo; |
9b1e14f4 | 8005 | } else if (IS_PINEVIEW(dev_priv)) { |
50a0bc90 | 8006 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
1fa61106 ED |
8007 | dev_priv->is_ddr3, |
8008 | dev_priv->fsb_freq, | |
8009 | dev_priv->mem_freq)) { | |
8010 | DRM_INFO("failed to find known CxSR latency " | |
8011 | "(found ddr%s fsb freq %d, mem freq %d), " | |
8012 | "disabling CxSR\n", | |
8013 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
8014 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
8015 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 8016 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
8017 | dev_priv->display.update_wm = NULL; |
8018 | } else | |
8019 | dev_priv->display.update_wm = pineview_update_wm; | |
9beb5fea | 8020 | } else if (IS_G4X(dev_priv)) { |
1fa61106 | 8021 | dev_priv->display.update_wm = g4x_update_wm; |
5db94019 | 8022 | } else if (IS_GEN4(dev_priv)) { |
1fa61106 | 8023 | dev_priv->display.update_wm = i965_update_wm; |
5db94019 | 8024 | } else if (IS_GEN3(dev_priv)) { |
1fa61106 ED |
8025 | dev_priv->display.update_wm = i9xx_update_wm; |
8026 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
5db94019 | 8027 | } else if (IS_GEN2(dev_priv)) { |
62d75df7 | 8028 | if (INTEL_INFO(dev_priv)->num_pipes == 1) { |
feb56b93 | 8029 | dev_priv->display.update_wm = i845_update_wm; |
1fa61106 | 8030 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
8031 | } else { |
8032 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 8033 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 | 8034 | } |
feb56b93 DV |
8035 | } else { |
8036 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
8037 | } |
8038 | } | |
8039 | ||
87660502 L |
8040 | static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv) |
8041 | { | |
8042 | uint32_t flags = | |
8043 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8044 | ||
8045 | switch (flags) { | |
8046 | case GEN6_PCODE_SUCCESS: | |
8047 | return 0; | |
8048 | case GEN6_PCODE_UNIMPLEMENTED_CMD: | |
8049 | case GEN6_PCODE_ILLEGAL_CMD: | |
8050 | return -ENXIO; | |
8051 | case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
7850d1c3 | 8052 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: |
87660502 L |
8053 | return -EOVERFLOW; |
8054 | case GEN6_PCODE_TIMEOUT: | |
8055 | return -ETIMEDOUT; | |
8056 | default: | |
8057 | MISSING_CASE(flags) | |
8058 | return 0; | |
8059 | } | |
8060 | } | |
8061 | ||
8062 | static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv) | |
8063 | { | |
8064 | uint32_t flags = | |
8065 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8066 | ||
8067 | switch (flags) { | |
8068 | case GEN6_PCODE_SUCCESS: | |
8069 | return 0; | |
8070 | case GEN6_PCODE_ILLEGAL_CMD: | |
8071 | return -ENXIO; | |
8072 | case GEN7_PCODE_TIMEOUT: | |
8073 | return -ETIMEDOUT; | |
8074 | case GEN7_PCODE_ILLEGAL_DATA: | |
8075 | return -EINVAL; | |
8076 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
8077 | return -EOVERFLOW; | |
8078 | default: | |
8079 | MISSING_CASE(flags); | |
8080 | return 0; | |
8081 | } | |
8082 | } | |
8083 | ||
151a49d0 | 8084 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 8085 | { |
87660502 L |
8086 | int status; |
8087 | ||
4fc688ce | 8088 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8089 | |
3f5582dd CW |
8090 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8091 | * use te fw I915_READ variants to reduce the amount of work | |
8092 | * required when reading/writing. | |
8093 | */ | |
8094 | ||
8095 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
42c0526c BW |
8096 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
8097 | return -EAGAIN; | |
8098 | } | |
8099 | ||
3f5582dd CW |
8100 | I915_WRITE_FW(GEN6_PCODE_DATA, *val); |
8101 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); | |
8102 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
42c0526c | 8103 | |
3f5582dd CW |
8104 | if (intel_wait_for_register_fw(dev_priv, |
8105 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
8106 | 500)) { | |
42c0526c BW |
8107 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
8108 | return -ETIMEDOUT; | |
8109 | } | |
8110 | ||
3f5582dd CW |
8111 | *val = I915_READ_FW(GEN6_PCODE_DATA); |
8112 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); | |
42c0526c | 8113 | |
87660502 L |
8114 | if (INTEL_GEN(dev_priv) > 6) |
8115 | status = gen7_check_mailbox_status(dev_priv); | |
8116 | else | |
8117 | status = gen6_check_mailbox_status(dev_priv); | |
8118 | ||
8119 | if (status) { | |
8120 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n", | |
8121 | status); | |
8122 | return status; | |
8123 | } | |
8124 | ||
42c0526c BW |
8125 | return 0; |
8126 | } | |
8127 | ||
3f5582dd | 8128 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, |
87660502 | 8129 | u32 mbox, u32 val) |
42c0526c | 8130 | { |
87660502 L |
8131 | int status; |
8132 | ||
4fc688ce | 8133 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8134 | |
3f5582dd CW |
8135 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8136 | * use te fw I915_READ variants to reduce the amount of work | |
8137 | * required when reading/writing. | |
8138 | */ | |
8139 | ||
8140 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
42c0526c BW |
8141 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
8142 | return -EAGAIN; | |
8143 | } | |
8144 | ||
3f5582dd | 8145 | I915_WRITE_FW(GEN6_PCODE_DATA, val); |
8bf41b72 | 8146 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); |
3f5582dd | 8147 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
42c0526c | 8148 | |
3f5582dd CW |
8149 | if (intel_wait_for_register_fw(dev_priv, |
8150 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
8151 | 500)) { | |
42c0526c BW |
8152 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
8153 | return -ETIMEDOUT; | |
8154 | } | |
8155 | ||
3f5582dd | 8156 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); |
42c0526c | 8157 | |
87660502 L |
8158 | if (INTEL_GEN(dev_priv) > 6) |
8159 | status = gen7_check_mailbox_status(dev_priv); | |
8160 | else | |
8161 | status = gen6_check_mailbox_status(dev_priv); | |
8162 | ||
8163 | if (status) { | |
8164 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n", | |
8165 | status); | |
8166 | return status; | |
8167 | } | |
8168 | ||
42c0526c BW |
8169 | return 0; |
8170 | } | |
a0e4e199 | 8171 | |
a0b8a1fe ID |
8172 | static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox, |
8173 | u32 request, u32 reply_mask, u32 reply, | |
8174 | u32 *status) | |
8175 | { | |
8176 | u32 val = request; | |
8177 | ||
8178 | *status = sandybridge_pcode_read(dev_priv, mbox, &val); | |
8179 | ||
8180 | return *status || ((val & reply_mask) == reply); | |
8181 | } | |
8182 | ||
8183 | /** | |
8184 | * skl_pcode_request - send PCODE request until acknowledgment | |
8185 | * @dev_priv: device private | |
8186 | * @mbox: PCODE mailbox ID the request is targeted for | |
8187 | * @request: request ID | |
8188 | * @reply_mask: mask used to check for request acknowledgment | |
8189 | * @reply: value used to check for request acknowledgment | |
8190 | * @timeout_base_ms: timeout for polling with preemption enabled | |
8191 | * | |
8192 | * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE | |
0129936d | 8193 | * reports an error or an overall timeout of @timeout_base_ms+50 ms expires. |
a0b8a1fe ID |
8194 | * The request is acknowledged once the PCODE reply dword equals @reply after |
8195 | * applying @reply_mask. Polling is first attempted with preemption enabled | |
0129936d | 8196 | * for @timeout_base_ms and if this times out for another 50 ms with |
a0b8a1fe ID |
8197 | * preemption disabled. |
8198 | * | |
8199 | * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some | |
8200 | * other error as reported by PCODE. | |
8201 | */ | |
8202 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, | |
8203 | u32 reply_mask, u32 reply, int timeout_base_ms) | |
8204 | { | |
8205 | u32 status; | |
8206 | int ret; | |
8207 | ||
8208 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
8209 | ||
8210 | #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \ | |
8211 | &status) | |
8212 | ||
8213 | /* | |
8214 | * Prime the PCODE by doing a request first. Normally it guarantees | |
8215 | * that a subsequent request, at most @timeout_base_ms later, succeeds. | |
8216 | * _wait_for() doesn't guarantee when its passed condition is evaluated | |
8217 | * first, so send the first request explicitly. | |
8218 | */ | |
8219 | if (COND) { | |
8220 | ret = 0; | |
8221 | goto out; | |
8222 | } | |
8223 | ret = _wait_for(COND, timeout_base_ms * 1000, 10); | |
8224 | if (!ret) | |
8225 | goto out; | |
8226 | ||
8227 | /* | |
8228 | * The above can time out if the number of requests was low (2 in the | |
8229 | * worst case) _and_ PCODE was busy for some reason even after a | |
8230 | * (queued) request and @timeout_base_ms delay. As a workaround retry | |
8231 | * the poll with preemption disabled to maximize the number of | |
0129936d | 8232 | * requests. Increase the timeout from @timeout_base_ms to 50ms to |
a0b8a1fe | 8233 | * account for interrupts that could reduce the number of these |
0129936d ID |
8234 | * requests, and for any quirks of the PCODE firmware that delays |
8235 | * the request completion. | |
a0b8a1fe ID |
8236 | */ |
8237 | DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n"); | |
8238 | WARN_ON_ONCE(timeout_base_ms > 3); | |
8239 | preempt_disable(); | |
0129936d | 8240 | ret = wait_for_atomic(COND, 50); |
a0b8a1fe ID |
8241 | preempt_enable(); |
8242 | ||
8243 | out: | |
8244 | return ret ? ret : status; | |
8245 | #undef COND | |
8246 | } | |
8247 | ||
dd06f88c VS |
8248 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
8249 | { | |
c30fec65 VS |
8250 | /* |
8251 | * N = val - 0xb7 | |
8252 | * Slow = Fast = GPLL ref * N | |
8253 | */ | |
8254 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000); | |
855ba3be JB |
8255 | } |
8256 | ||
b55dd647 | 8257 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 8258 | { |
c30fec65 | 8259 | return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7; |
855ba3be JB |
8260 | } |
8261 | ||
b55dd647 | 8262 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8263 | { |
c30fec65 VS |
8264 | /* |
8265 | * N = val / 2 | |
8266 | * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 | |
8267 | */ | |
8268 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000); | |
22b1b2f8 D |
8269 | } |
8270 | ||
b55dd647 | 8271 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8272 | { |
1c14762d | 8273 | /* CHV needs even values */ |
c30fec65 | 8274 | return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2; |
22b1b2f8 D |
8275 | } |
8276 | ||
616bc820 | 8277 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 8278 | { |
2d1fe073 | 8279 | if (IS_GEN9(dev_priv)) |
500a3d2e MK |
8280 | return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, |
8281 | GEN9_FREQ_SCALER); | |
2d1fe073 | 8282 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 8283 | return chv_gpu_freq(dev_priv, val); |
2d1fe073 | 8284 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
8285 | return byt_gpu_freq(dev_priv, val); |
8286 | else | |
8287 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
8288 | } |
8289 | ||
616bc820 VS |
8290 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
8291 | { | |
2d1fe073 | 8292 | if (IS_GEN9(dev_priv)) |
500a3d2e MK |
8293 | return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, |
8294 | GT_FREQUENCY_MULTIPLIER); | |
2d1fe073 | 8295 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 8296 | return chv_freq_opcode(dev_priv, val); |
2d1fe073 | 8297 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
8298 | return byt_freq_opcode(dev_priv, val); |
8299 | else | |
500a3d2e | 8300 | return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); |
616bc820 | 8301 | } |
22b1b2f8 | 8302 | |
6ad790c0 CW |
8303 | struct request_boost { |
8304 | struct work_struct work; | |
eed29a5b | 8305 | struct drm_i915_gem_request *req; |
6ad790c0 CW |
8306 | }; |
8307 | ||
8308 | static void __intel_rps_boost_work(struct work_struct *work) | |
8309 | { | |
8310 | struct request_boost *boost = container_of(work, struct request_boost, work); | |
e61b9958 | 8311 | struct drm_i915_gem_request *req = boost->req; |
6ad790c0 | 8312 | |
f69a02c9 | 8313 | if (!i915_gem_request_completed(req)) |
c033666a | 8314 | gen6_rps_boost(req->i915, NULL, req->emitted_jiffies); |
6ad790c0 | 8315 | |
e8a261ea | 8316 | i915_gem_request_put(req); |
6ad790c0 CW |
8317 | kfree(boost); |
8318 | } | |
8319 | ||
91d14251 | 8320 | void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req) |
6ad790c0 CW |
8321 | { |
8322 | struct request_boost *boost; | |
8323 | ||
91d14251 | 8324 | if (req == NULL || INTEL_GEN(req->i915) < 6) |
6ad790c0 CW |
8325 | return; |
8326 | ||
f69a02c9 | 8327 | if (i915_gem_request_completed(req)) |
e61b9958 CW |
8328 | return; |
8329 | ||
6ad790c0 CW |
8330 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
8331 | if (boost == NULL) | |
8332 | return; | |
8333 | ||
e8a261ea | 8334 | boost->req = i915_gem_request_get(req); |
6ad790c0 CW |
8335 | |
8336 | INIT_WORK(&boost->work, __intel_rps_boost_work); | |
91d14251 | 8337 | queue_work(req->i915->wq, &boost->work); |
6ad790c0 CW |
8338 | } |
8339 | ||
192aa181 | 8340 | void intel_pm_setup(struct drm_i915_private *dev_priv) |
907b28c5 | 8341 | { |
f742a552 | 8342 | mutex_init(&dev_priv->rps.hw_lock); |
8d3afd7d | 8343 | spin_lock_init(&dev_priv->rps.client_lock); |
f742a552 | 8344 | |
54b4f68f CW |
8345 | INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work, |
8346 | __intel_autoenable_gt_powersave); | |
1854d5ca | 8347 | INIT_LIST_HEAD(&dev_priv->rps.clients); |
5d584b2e | 8348 | |
33688d95 | 8349 | dev_priv->pm.suspended = false; |
1f814dac | 8350 | atomic_set(&dev_priv->pm.wakeref_count, 0); |
907b28c5 | 8351 | } |
135bafa5 | 8352 | |
c5a0ad11 MK |
8353 | u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
8354 | const i915_reg_t reg) | |
135bafa5 MK |
8355 | { |
8356 | u64 raw_time; /* 32b value may overflow during fixed point math */ | |
c5a0ad11 MK |
8357 | u64 units = 128000ULL, div = 100000ULL; |
8358 | u64 ret; | |
135bafa5 MK |
8359 | |
8360 | if (!intel_enable_rc6()) | |
8361 | return 0; | |
8362 | ||
8363 | intel_runtime_pm_get(dev_priv); | |
8364 | ||
8365 | /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ | |
8366 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
c5a0ad11 | 8367 | units = 1000; |
135bafa5 MK |
8368 | div = dev_priv->czclk_freq; |
8369 | ||
8370 | if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) | |
8371 | units <<= 8; | |
8372 | } else if (IS_GEN9_LP(dev_priv)) { | |
c5a0ad11 | 8373 | units = 1000; |
135bafa5 MK |
8374 | div = 1200; /* 833.33ns */ |
8375 | } | |
8376 | ||
8377 | raw_time = I915_READ(reg) * units; | |
8378 | ret = DIV_ROUND_UP_ULL(raw_time, div); | |
8379 | ||
8380 | intel_runtime_pm_put(dev_priv); | |
8381 | return ret; | |
8382 | } |