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drm/i915: introduce haswell_init_clock_gating
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
f6750b3c
ED		 34/* FBC, or Frame Buffer Compression, is a technique employed to compress the
35 * framebuffer contents in-memory, aiming at reducing the required bandwidth
36 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 37 *
f6750b3c
ED		 38 * The benefits of FBC are mostly visible with solid backgrounds and
39 * variation-less patterns.
85208be0 40 *
f6750b3c
ED		 41 * FBC-related functionality can be enabled by the means of the
42 * i915.i915_enable_fbc parameter
85208be0
ED		 43 */
44
1fa61106 45static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 46{
47 struct drm_i915_private *dev_priv = dev->dev_private;
48 u32 fbc_ctl;
49
50 /* Disable compression */
51 fbc_ctl = I915_READ(FBC_CONTROL);
52 if ((fbc_ctl & FBC_CTL_EN) == 0)
53 return;
54
55 fbc_ctl &= ~FBC_CTL_EN;
56 I915_WRITE(FBC_CONTROL, fbc_ctl);
57
58 /* Wait for compressing bit to clear */
59 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
60 DRM_DEBUG_KMS("FBC idle timed out\n");
61 return;
62 }
63
64 DRM_DEBUG_KMS("disabled FBC\n");
65}
66
1fa61106 67static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 68{
69 struct drm_device *dev = crtc->dev;
70 struct drm_i915_private *dev_priv = dev->dev_private;
71 struct drm_framebuffer *fb = crtc->fb;
72 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
73 struct drm_i915_gem_object *obj = intel_fb->obj;
74 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
75 int cfb_pitch;
76 int plane, i;
77 u32 fbc_ctl, fbc_ctl2;
78
79 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
80 if (fb->pitches[0] < cfb_pitch)
81 cfb_pitch = fb->pitches[0];
82
83 /* FBC_CTL wants 64B units */
84 cfb_pitch = (cfb_pitch / 64) - 1;
85 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
86
87 /* Clear old tags */
88 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
89 I915_WRITE(FBC_TAG + (i * 4), 0);
90
91 /* Set it up... */
92 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
93 fbc_ctl2 |= plane;
94 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
95 I915_WRITE(FBC_FENCE_OFF, crtc->y);
96
97 /* enable it... */
98 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
99 if (IS_I945GM(dev))
100 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
101 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
102 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
103 fbc_ctl |= obj->fence_reg;
104 I915_WRITE(FBC_CONTROL, fbc_ctl);
105
106 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
107 cfb_pitch, crtc->y, intel_crtc->plane);
108}
109
1fa61106 110static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 111{
112 struct drm_i915_private *dev_priv = dev->dev_private;
113
114 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
115}
116
1fa61106 117static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 118{
119 struct drm_device *dev = crtc->dev;
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 struct drm_framebuffer *fb = crtc->fb;
122 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
123 struct drm_i915_gem_object *obj = intel_fb->obj;
124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
125 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
126 unsigned long stall_watermark = 200;
127 u32 dpfc_ctl;
128
129 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
130 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
131 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
132
133 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
134 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
135 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
136 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
137
138 /* enable it... */
139 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
140
141 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
142}
143
1fa61106 144static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 145{
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 u32 dpfc_ctl;
148
149 /* Disable compression */
150 dpfc_ctl = I915_READ(DPFC_CONTROL);
151 if (dpfc_ctl & DPFC_CTL_EN) {
152 dpfc_ctl &= ~DPFC_CTL_EN;
153 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
154
155 DRM_DEBUG_KMS("disabled FBC\n");
156 }
157}
158
1fa61106 159static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 160{
161 struct drm_i915_private *dev_priv = dev->dev_private;
162
163 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
164}
165
166static void sandybridge_blit_fbc_update(struct drm_device *dev)
167{
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 u32 blt_ecoskpd;
170
171 /* Make sure blitter notifies FBC of writes */
172 gen6_gt_force_wake_get(dev_priv);
173 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
174 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
175 GEN6_BLITTER_LOCK_SHIFT;
176 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
177 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
179 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
180 GEN6_BLITTER_LOCK_SHIFT);
181 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
182 POSTING_READ(GEN6_BLITTER_ECOSKPD);
183 gen6_gt_force_wake_put(dev_priv);
184}
185
1fa61106 186static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 187{
188 struct drm_device *dev = crtc->dev;
189 struct drm_i915_private *dev_priv = dev->dev_private;
190 struct drm_framebuffer *fb = crtc->fb;
191 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
192 struct drm_i915_gem_object *obj = intel_fb->obj;
193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
194 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
195 unsigned long stall_watermark = 200;
196 u32 dpfc_ctl;
197
198 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
199 dpfc_ctl &= DPFC_RESERVED;
200 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
201 /* Set persistent mode for front-buffer rendering, ala X. */
202 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
203 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
204 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
205
206 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
207 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
208 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
209 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
210 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
211 /* enable it... */
212 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
213
214 if (IS_GEN6(dev)) {
215 I915_WRITE(SNB_DPFC_CTL_SA,
216 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
217 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
218 sandybridge_blit_fbc_update(dev);
219 }
220
221 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
222}
223
1fa61106 224static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 225{
226 struct drm_i915_private *dev_priv = dev->dev_private;
227 u32 dpfc_ctl;
228
229 /* Disable compression */
230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
231 if (dpfc_ctl & DPFC_CTL_EN) {
232 dpfc_ctl &= ~DPFC_CTL_EN;
233 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
234
235 DRM_DEBUG_KMS("disabled FBC\n");
236 }
237}
238
1fa61106 239static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 240{
241 struct drm_i915_private *dev_priv = dev->dev_private;
242
243 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
244}
245
246bool intel_fbc_enabled(struct drm_device *dev)
247{
248 struct drm_i915_private *dev_priv = dev->dev_private;
249
250 if (!dev_priv->display.fbc_enabled)
251 return false;
252
253 return dev_priv->display.fbc_enabled(dev);
254}
255
256static void intel_fbc_work_fn(struct work_struct *__work)
257{
258 struct intel_fbc_work *work =
259 container_of(to_delayed_work(__work),
260 struct intel_fbc_work, work);
261 struct drm_device *dev = work->crtc->dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263
264 mutex_lock(&dev->struct_mutex);
265 if (work == dev_priv->fbc_work) {
266 /* Double check that we haven't switched fb without cancelling
267 * the prior work.
268 */
269 if (work->crtc->fb == work->fb) {
270 dev_priv->display.enable_fbc(work->crtc,
271 work->interval);
272
273 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
274 dev_priv->cfb_fb = work->crtc->fb->base.id;
275 dev_priv->cfb_y = work->crtc->y;
276 }
277
278 dev_priv->fbc_work = NULL;
279 }
280 mutex_unlock(&dev->struct_mutex);
281
282 kfree(work);
283}
284
285static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
286{
287 if (dev_priv->fbc_work == NULL)
288 return;
289
290 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
291
292 /* Synchronisation is provided by struct_mutex and checking of
293 * dev_priv->fbc_work, so we can perform the cancellation
294 * entirely asynchronously.
295 */
296 if (cancel_delayed_work(&dev_priv->fbc_work->work))
297 /* tasklet was killed before being run, clean up */
298 kfree(dev_priv->fbc_work);
299
300 /* Mark the work as no longer wanted so that if it does
301 * wake-up (because the work was already running and waiting
302 * for our mutex), it will discover that is no longer
303 * necessary to run.
304 */
305 dev_priv->fbc_work = NULL;
306}
307
308void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
309{
310 struct intel_fbc_work *work;
311 struct drm_device *dev = crtc->dev;
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.enable_fbc)
315 return;
316
317 intel_cancel_fbc_work(dev_priv);
318
319 work = kzalloc(sizeof *work, GFP_KERNEL);
320 if (work == NULL) {
321 dev_priv->display.enable_fbc(crtc, interval);
322 return;
323 }
324
325 work->crtc = crtc;
326 work->fb = crtc->fb;
327 work->interval = interval;
328 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
329
330 dev_priv->fbc_work = work;
331
332 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
333
334 /* Delay the actual enabling to let pageflipping cease and the
335 * display to settle before starting the compression. Note that
336 * this delay also serves a second purpose: it allows for a
337 * vblank to pass after disabling the FBC before we attempt
338 * to modify the control registers.
339 *
340 * A more complicated solution would involve tracking vblanks
341 * following the termination of the page-flipping sequence
342 * and indeed performing the enable as a co-routine and not
343 * waiting synchronously upon the vblank.
344 */
345 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
346}
347
348void intel_disable_fbc(struct drm_device *dev)
349{
350 struct drm_i915_private *dev_priv = dev->dev_private;
351
352 intel_cancel_fbc_work(dev_priv);
353
354 if (!dev_priv->display.disable_fbc)
355 return;
356
357 dev_priv->display.disable_fbc(dev);
358 dev_priv->cfb_plane = -1;
359}
360
361/**
362 * intel_update_fbc - enable/disable FBC as needed
363 * @dev: the drm_device
364 *
365 * Set up the framebuffer compression hardware at mode set time. We
366 * enable it if possible:
367 * - plane A only (on pre-965)
368 * - no pixel mulitply/line duplication
369 * - no alpha buffer discard
370 * - no dual wide
371 * - framebuffer <= 2048 in width, 1536 in height
372 *
373 * We can't assume that any compression will take place (worst case),
374 * so the compressed buffer has to be the same size as the uncompressed
375 * one. It also must reside (along with the line length buffer) in
376 * stolen memory.
377 *
378 * We need to enable/disable FBC on a global basis.
379 */
380void intel_update_fbc(struct drm_device *dev)
381{
382 struct drm_i915_private *dev_priv = dev->dev_private;
383 struct drm_crtc *crtc = NULL, *tmp_crtc;
384 struct intel_crtc *intel_crtc;
385 struct drm_framebuffer *fb;
386 struct intel_framebuffer *intel_fb;
387 struct drm_i915_gem_object *obj;
388 int enable_fbc;
389
390 DRM_DEBUG_KMS("\n");
391
392 if (!i915_powersave)
393 return;
394
395 if (!I915_HAS_FBC(dev))
396 return;
397
398 /*
399 * If FBC is already on, we just have to verify that we can
400 * keep it that way...
401 * Need to disable if:
402 * - more than one pipe is active
403 * - changing FBC params (stride, fence, mode)
404 * - new fb is too large to fit in compressed buffer
405 * - going to an unsupported config (interlace, pixel multiply, etc.)
406 */
407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
93314b5b
CW		 408 if (tmp_crtc->enabled &&
409 !to_intel_crtc(tmp_crtc)->primary_disabled &&
410 tmp_crtc->fb) {
85208be0
ED		 411 if (crtc) {
412 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
413 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
414 goto out_disable;
415 }
416 crtc = tmp_crtc;
417 }
418 }
419
420 if (!crtc || crtc->fb == NULL) {
421 DRM_DEBUG_KMS("no output, disabling\n");
422 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
423 goto out_disable;
424 }
425
426 intel_crtc = to_intel_crtc(crtc);
427 fb = crtc->fb;
428 intel_fb = to_intel_framebuffer(fb);
429 obj = intel_fb->obj;
430
431 enable_fbc = i915_enable_fbc;
432 if (enable_fbc < 0) {
433 DRM_DEBUG_KMS("fbc set to per-chip default\n");
434 enable_fbc = 1;
435 if (INTEL_INFO(dev)->gen <= 6)
436 enable_fbc = 0;
437 }
438 if (!enable_fbc) {
439 DRM_DEBUG_KMS("fbc disabled per module param\n");
440 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
441 goto out_disable;
442 }
443 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
444 DRM_DEBUG_KMS("framebuffer too large, disabling "
445 "compression\n");
446 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
447 goto out_disable;
448 }
449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
451 DRM_DEBUG_KMS("mode incompatible with compression, "
452 "disabling\n");
453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
454 goto out_disable;
455 }
456 if ((crtc->mode.hdisplay > 2048) ||
457 (crtc->mode.vdisplay > 1536)) {
458 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
460 goto out_disable;
461 }
462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
463 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
464 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
465 goto out_disable;
466 }
467
468 /* The use of a CPU fence is mandatory in order to detect writes
469 * by the CPU to the scanout and trigger updates to the FBC.
470 */
471 if (obj->tiling_mode != I915_TILING_X ||
472 obj->fence_reg == I915_FENCE_REG_NONE) {
473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
474 dev_priv->no_fbc_reason = FBC_NOT_TILED;
475 goto out_disable;
476 }
477
478 /* If the kernel debugger is active, always disable compression */
479 if (in_dbg_master())
480 goto out_disable;
481
482 /* If the scanout has not changed, don't modify the FBC settings.
483 * Note that we make the fundamental assumption that the fb->obj
484 * cannot be unpinned (and have its GTT offset and fence revoked)
485 * without first being decoupled from the scanout and FBC disabled.
486 */
487 if (dev_priv->cfb_plane == intel_crtc->plane &&
488 dev_priv->cfb_fb == fb->base.id &&
489 dev_priv->cfb_y == crtc->y)
490 return;
491
492 if (intel_fbc_enabled(dev)) {
493 /* We update FBC along two paths, after changing fb/crtc
494 * configuration (modeswitching) and after page-flipping
495 * finishes. For the latter, we know that not only did
496 * we disable the FBC at the start of the page-flip
497 * sequence, but also more than one vblank has passed.
498 *
499 * For the former case of modeswitching, it is possible
500 * to switch between two FBC valid configurations
501 * instantaneously so we do need to disable the FBC
502 * before we can modify its control registers. We also
503 * have to wait for the next vblank for that to take
504 * effect. However, since we delay enabling FBC we can
505 * assume that a vblank has passed since disabling and
506 * that we can safely alter the registers in the deferred
507 * callback.
508 *
509 * In the scenario that we go from a valid to invalid
510 * and then back to valid FBC configuration we have
511 * no strict enforcement that a vblank occurred since
512 * disabling the FBC. However, along all current pipe
513 * disabling paths we do need to wait for a vblank at
514 * some point. And we wait before enabling FBC anyway.
515 */
516 DRM_DEBUG_KMS("disabling active FBC for update\n");
517 intel_disable_fbc(dev);
518 }
519
520 intel_enable_fbc(crtc, 500);
521 return;
522
523out_disable:
524 /* Multiple disables should be harmless */
525 if (intel_fbc_enabled(dev)) {
526 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
527 intel_disable_fbc(dev);
528 }
529}
530
c921aba8
DV		 531static void i915_pineview_get_mem_freq(struct drm_device *dev)
532{
533 drm_i915_private_t *dev_priv = dev->dev_private;
534 u32 tmp;
535
536 tmp = I915_READ(CLKCFG);
537
538 switch (tmp & CLKCFG_FSB_MASK) {
539 case CLKCFG_FSB_533:
540 dev_priv->fsb_freq = 533; /* 133*4 */
541 break;
542 case CLKCFG_FSB_800:
543 dev_priv->fsb_freq = 800; /* 200*4 */
544 break;
545 case CLKCFG_FSB_667:
546 dev_priv->fsb_freq = 667; /* 167*4 */
547 break;
548 case CLKCFG_FSB_400:
549 dev_priv->fsb_freq = 400; /* 100*4 */
550 break;
551 }
552
553 switch (tmp & CLKCFG_MEM_MASK) {
554 case CLKCFG_MEM_533:
555 dev_priv->mem_freq = 533;
556 break;
557 case CLKCFG_MEM_667:
558 dev_priv->mem_freq = 667;
559 break;
560 case CLKCFG_MEM_800:
561 dev_priv->mem_freq = 800;
562 break;
563 }
564
565 /* detect pineview DDR3 setting */
566 tmp = I915_READ(CSHRDDR3CTL);
567 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
568}
569
570static void i915_ironlake_get_mem_freq(struct drm_device *dev)
571{
572 drm_i915_private_t *dev_priv = dev->dev_private;
573 u16 ddrpll, csipll;
574
575 ddrpll = I915_READ16(DDRMPLL1);
576 csipll = I915_READ16(CSIPLL0);
577
578 switch (ddrpll & 0xff) {
579 case 0xc:
580 dev_priv->mem_freq = 800;
581 break;
582 case 0x10:
583 dev_priv->mem_freq = 1066;
584 break;
585 case 0x14:
586 dev_priv->mem_freq = 1333;
587 break;
588 case 0x18:
589 dev_priv->mem_freq = 1600;
590 break;
591 default:
592 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
593 ddrpll & 0xff);
594 dev_priv->mem_freq = 0;
595 break;
596 }
597
598 dev_priv->r_t = dev_priv->mem_freq;
599
600 switch (csipll & 0x3ff) {
601 case 0x00c:
602 dev_priv->fsb_freq = 3200;
603 break;
604 case 0x00e:
605 dev_priv->fsb_freq = 3733;
606 break;
607 case 0x010:
608 dev_priv->fsb_freq = 4266;
609 break;
610 case 0x012:
611 dev_priv->fsb_freq = 4800;
612 break;
613 case 0x014:
614 dev_priv->fsb_freq = 5333;
615 break;
616 case 0x016:
617 dev_priv->fsb_freq = 5866;
618 break;
619 case 0x018:
620 dev_priv->fsb_freq = 6400;
621 break;
622 default:
623 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
624 csipll & 0x3ff);
625 dev_priv->fsb_freq = 0;
626 break;
627 }
628
629 if (dev_priv->fsb_freq == 3200) {
630 dev_priv->c_m = 0;
631 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
632 dev_priv->c_m = 1;
633 } else {
634 dev_priv->c_m = 2;
635 }
636}
637
b445e3b0
ED		 638static const struct cxsr_latency cxsr_latency_table[] = {
639 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
640 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
641 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
642 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
643 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
644
645 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
646 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
647 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
648 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
649 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
650
651 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
652 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
653 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
654 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
655 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
656
657 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
658 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
659 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
660 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
661 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
662
663 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
664 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
665 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
666 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
667 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
668
669 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
670 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
671 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
672 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
673 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
674};
675
63c62275 676static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 677 int is_ddr3,
678 int fsb,
679 int mem)
680{
681 const struct cxsr_latency *latency;
682 int i;
683
684 if (fsb == 0 || mem == 0)
685 return NULL;
686
687 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
688 latency = &cxsr_latency_table[i];
689 if (is_desktop == latency->is_desktop &&
690 is_ddr3 == latency->is_ddr3 &&
691 fsb == latency->fsb_freq && mem == latency->mem_freq)
692 return latency;
693 }
694
695 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
696
697 return NULL;
698}
699
1fa61106 700static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 701{
702 struct drm_i915_private *dev_priv = dev->dev_private;
703
704 /* deactivate cxsr */
705 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
706}
707
708/*
709 * Latency for FIFO fetches is dependent on several factors:
710 * - memory configuration (speed, channels)
711 * - chipset
712 * - current MCH state
713 * It can be fairly high in some situations, so here we assume a fairly
714 * pessimal value. It's a tradeoff between extra memory fetches (if we
715 * set this value too high, the FIFO will fetch frequently to stay full)
716 * and power consumption (set it too low to save power and we might see
717 * FIFO underruns and display "flicker").
718 *
719 * A value of 5us seems to be a good balance; safe for very low end
720 * platforms but not overly aggressive on lower latency configs.
721 */
722static const int latency_ns = 5000;
723
1fa61106 724static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 725{
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t dsparb = I915_READ(DSPARB);
728 int size;
729
730 size = dsparb & 0x7f;
731 if (plane)
732 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
733
734 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
735 plane ? "B" : "A", size);
736
737 return size;
738}
739
1fa61106 740static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 741{
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 uint32_t dsparb = I915_READ(DSPARB);
744 int size;
745
746 size = dsparb & 0x1ff;
747 if (plane)
748 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
749 size >>= 1; /* Convert to cachelines */
750
751 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
752 plane ? "B" : "A", size);
753
754 return size;
755}
756
1fa61106 757static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 uint32_t dsparb = I915_READ(DSPARB);
761 int size;
762
763 size = dsparb & 0x7f;
764 size >>= 2; /* Convert to cachelines */
765
766 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
767 plane ? "B" : "A",
768 size);
769
770 return size;
771}
772
1fa61106 773static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 774{
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 uint32_t dsparb = I915_READ(DSPARB);
777 int size;
778
779 size = dsparb & 0x7f;
780 size >>= 1; /* Convert to cachelines */
781
782 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
783 plane ? "B" : "A", size);
784
785 return size;
786}
787
788/* Pineview has different values for various configs */
789static const struct intel_watermark_params pineview_display_wm = {
790 PINEVIEW_DISPLAY_FIFO,
791 PINEVIEW_MAX_WM,
792 PINEVIEW_DFT_WM,
793 PINEVIEW_GUARD_WM,
794 PINEVIEW_FIFO_LINE_SIZE
795};
796static const struct intel_watermark_params pineview_display_hplloff_wm = {
797 PINEVIEW_DISPLAY_FIFO,
798 PINEVIEW_MAX_WM,
799 PINEVIEW_DFT_HPLLOFF_WM,
800 PINEVIEW_GUARD_WM,
801 PINEVIEW_FIFO_LINE_SIZE
802};
803static const struct intel_watermark_params pineview_cursor_wm = {
804 PINEVIEW_CURSOR_FIFO,
805 PINEVIEW_CURSOR_MAX_WM,
806 PINEVIEW_CURSOR_DFT_WM,
807 PINEVIEW_CURSOR_GUARD_WM,
808 PINEVIEW_FIFO_LINE_SIZE,
809};
810static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
811 PINEVIEW_CURSOR_FIFO,
812 PINEVIEW_CURSOR_MAX_WM,
813 PINEVIEW_CURSOR_DFT_WM,
814 PINEVIEW_CURSOR_GUARD_WM,
815 PINEVIEW_FIFO_LINE_SIZE
816};
817static const struct intel_watermark_params g4x_wm_info = {
818 G4X_FIFO_SIZE,
819 G4X_MAX_WM,
820 G4X_MAX_WM,
821 2,
822 G4X_FIFO_LINE_SIZE,
823};
824static const struct intel_watermark_params g4x_cursor_wm_info = {
825 I965_CURSOR_FIFO,
826 I965_CURSOR_MAX_WM,
827 I965_CURSOR_DFT_WM,
828 2,
829 G4X_FIFO_LINE_SIZE,
830};
831static const struct intel_watermark_params valleyview_wm_info = {
832 VALLEYVIEW_FIFO_SIZE,
833 VALLEYVIEW_MAX_WM,
834 VALLEYVIEW_MAX_WM,
835 2,
836 G4X_FIFO_LINE_SIZE,
837};
838static const struct intel_watermark_params valleyview_cursor_wm_info = {
839 I965_CURSOR_FIFO,
840 VALLEYVIEW_CURSOR_MAX_WM,
841 I965_CURSOR_DFT_WM,
842 2,
843 G4X_FIFO_LINE_SIZE,
844};
845static const struct intel_watermark_params i965_cursor_wm_info = {
846 I965_CURSOR_FIFO,
847 I965_CURSOR_MAX_WM,
848 I965_CURSOR_DFT_WM,
849 2,
850 I915_FIFO_LINE_SIZE,
851};
852static const struct intel_watermark_params i945_wm_info = {
853 I945_FIFO_SIZE,
854 I915_MAX_WM,
855 1,
856 2,
857 I915_FIFO_LINE_SIZE
858};
859static const struct intel_watermark_params i915_wm_info = {
860 I915_FIFO_SIZE,
861 I915_MAX_WM,
862 1,
863 2,
864 I915_FIFO_LINE_SIZE
865};
866static const struct intel_watermark_params i855_wm_info = {
867 I855GM_FIFO_SIZE,
868 I915_MAX_WM,
869 1,
870 2,
871 I830_FIFO_LINE_SIZE
872};
873static const struct intel_watermark_params i830_wm_info = {
874 I830_FIFO_SIZE,
875 I915_MAX_WM,
876 1,
877 2,
878 I830_FIFO_LINE_SIZE
879};
880
881static const struct intel_watermark_params ironlake_display_wm_info = {
882 ILK_DISPLAY_FIFO,
883 ILK_DISPLAY_MAXWM,
884 ILK_DISPLAY_DFTWM,
885 2,
886 ILK_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params ironlake_cursor_wm_info = {
889 ILK_CURSOR_FIFO,
890 ILK_CURSOR_MAXWM,
891 ILK_CURSOR_DFTWM,
892 2,
893 ILK_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params ironlake_display_srwm_info = {
896 ILK_DISPLAY_SR_FIFO,
897 ILK_DISPLAY_MAX_SRWM,
898 ILK_DISPLAY_DFT_SRWM,
899 2,
900 ILK_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params ironlake_cursor_srwm_info = {
903 ILK_CURSOR_SR_FIFO,
904 ILK_CURSOR_MAX_SRWM,
905 ILK_CURSOR_DFT_SRWM,
906 2,
907 ILK_FIFO_LINE_SIZE
908};
909
910static const struct intel_watermark_params sandybridge_display_wm_info = {
911 SNB_DISPLAY_FIFO,
912 SNB_DISPLAY_MAXWM,
913 SNB_DISPLAY_DFTWM,
914 2,
915 SNB_FIFO_LINE_SIZE
916};
917static const struct intel_watermark_params sandybridge_cursor_wm_info = {
918 SNB_CURSOR_FIFO,
919 SNB_CURSOR_MAXWM,
920 SNB_CURSOR_DFTWM,
921 2,
922 SNB_FIFO_LINE_SIZE
923};
924static const struct intel_watermark_params sandybridge_display_srwm_info = {
925 SNB_DISPLAY_SR_FIFO,
926 SNB_DISPLAY_MAX_SRWM,
927 SNB_DISPLAY_DFT_SRWM,
928 2,
929 SNB_FIFO_LINE_SIZE
930};
931static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
932 SNB_CURSOR_SR_FIFO,
933 SNB_CURSOR_MAX_SRWM,
934 SNB_CURSOR_DFT_SRWM,
935 2,
936 SNB_FIFO_LINE_SIZE
937};
938
939
940/**
941 * intel_calculate_wm - calculate watermark level
942 * @clock_in_khz: pixel clock
943 * @wm: chip FIFO params
944 * @pixel_size: display pixel size
945 * @latency_ns: memory latency for the platform
946 *
947 * Calculate the watermark level (the level at which the display plane will
948 * start fetching from memory again). Each chip has a different display
949 * FIFO size and allocation, so the caller needs to figure that out and pass
950 * in the correct intel_watermark_params structure.
951 *
952 * As the pixel clock runs, the FIFO will be drained at a rate that depends
953 * on the pixel size. When it reaches the watermark level, it'll start
954 * fetching FIFO line sized based chunks from memory until the FIFO fills
955 * past the watermark point. If the FIFO drains completely, a FIFO underrun
956 * will occur, and a display engine hang could result.
957 */
958static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
959 const struct intel_watermark_params *wm,
960 int fifo_size,
961 int pixel_size,
962 unsigned long latency_ns)
963{
964 long entries_required, wm_size;
965
966 /*
967 * Note: we need to make sure we don't overflow for various clock &
968 * latency values.
969 * clocks go from a few thousand to several hundred thousand.
970 * latency is usually a few thousand
971 */
972 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
973 1000;
974 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
975
976 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
977
978 wm_size = fifo_size - (entries_required + wm->guard_size);
979
980 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
981
982 /* Don't promote wm_size to unsigned... */
983 if (wm_size > (long)wm->max_wm)
984 wm_size = wm->max_wm;
985 if (wm_size <= 0)
986 wm_size = wm->default_wm;
987 return wm_size;
988}
989
990static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
991{
992 struct drm_crtc *crtc, *enabled = NULL;
993
994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
995 if (crtc->enabled && crtc->fb) {
996 if (enabled)
997 return NULL;
998 enabled = crtc;
999 }
1000 }
1001
1002 return enabled;
1003}
1004
1fa61106 1005static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1006{
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 struct drm_crtc *crtc;
1009 const struct cxsr_latency *latency;
1010 u32 reg;
1011 unsigned long wm;
1012
1013 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014 dev_priv->fsb_freq, dev_priv->mem_freq);
1015 if (!latency) {
1016 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017 pineview_disable_cxsr(dev);
1018 return;
1019 }
1020
1021 crtc = single_enabled_crtc(dev);
1022 if (crtc) {
1023 int clock = crtc->mode.clock;
1024 int pixel_size = crtc->fb->bits_per_pixel / 8;
1025
1026 /* Display SR */
1027 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028 pineview_display_wm.fifo_size,
1029 pixel_size, latency->display_sr);
1030 reg = I915_READ(DSPFW1);
1031 reg &= ~DSPFW_SR_MASK;
1032 reg |= wm << DSPFW_SR_SHIFT;
1033 I915_WRITE(DSPFW1, reg);
1034 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1035
1036 /* cursor SR */
1037 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038 pineview_display_wm.fifo_size,
1039 pixel_size, latency->cursor_sr);
1040 reg = I915_READ(DSPFW3);
1041 reg &= ~DSPFW_CURSOR_SR_MASK;
1042 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043 I915_WRITE(DSPFW3, reg);
1044
1045 /* Display HPLL off SR */
1046 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047 pineview_display_hplloff_wm.fifo_size,
1048 pixel_size, latency->display_hpll_disable);
1049 reg = I915_READ(DSPFW3);
1050 reg &= ~DSPFW_HPLL_SR_MASK;
1051 reg |= wm & DSPFW_HPLL_SR_MASK;
1052 I915_WRITE(DSPFW3, reg);
1053
1054 /* cursor HPLL off SR */
1055 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056 pineview_display_hplloff_wm.fifo_size,
1057 pixel_size, latency->cursor_hpll_disable);
1058 reg = I915_READ(DSPFW3);
1059 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061 I915_WRITE(DSPFW3, reg);
1062 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1063
1064 /* activate cxsr */
1065 I915_WRITE(DSPFW3,
1066 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1068 } else {
1069 pineview_disable_cxsr(dev);
1070 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1071 }
1072}
1073
1074static bool g4x_compute_wm0(struct drm_device *dev,
1075 int plane,
1076 const struct intel_watermark_params *display,
1077 int display_latency_ns,
1078 const struct intel_watermark_params *cursor,
1079 int cursor_latency_ns,
1080 int *plane_wm,
1081 int *cursor_wm)
1082{
1083 struct drm_crtc *crtc;
1084 int htotal, hdisplay, clock, pixel_size;
1085 int line_time_us, line_count;
1086 int entries, tlb_miss;
1087
1088 crtc = intel_get_crtc_for_plane(dev, plane);
1089 if (crtc->fb == NULL || !crtc->enabled) {
1090 *cursor_wm = cursor->guard_size;
1091 *plane_wm = display->guard_size;
1092 return false;
1093 }
1094
1095 htotal = crtc->mode.htotal;
1096 hdisplay = crtc->mode.hdisplay;
1097 clock = crtc->mode.clock;
1098 pixel_size = crtc->fb->bits_per_pixel / 8;
1099
1100 /* Use the small buffer method to calculate plane watermark */
1101 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1103 if (tlb_miss > 0)
1104 entries += tlb_miss;
1105 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106 *plane_wm = entries + display->guard_size;
1107 if (*plane_wm > (int)display->max_wm)
1108 *plane_wm = display->max_wm;
1109
1110 /* Use the large buffer method to calculate cursor watermark */
1111 line_time_us = ((htotal * 1000) / clock);
1112 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113 entries = line_count * 64 * pixel_size;
1114 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1115 if (tlb_miss > 0)
1116 entries += tlb_miss;
1117 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118 *cursor_wm = entries + cursor->guard_size;
1119 if (*cursor_wm > (int)cursor->max_wm)
1120 *cursor_wm = (int)cursor->max_wm;
1121
1122 return true;
1123}
1124
1125/*
1126 * Check the wm result.
1127 *
1128 * If any calculated watermark values is larger than the maximum value that
1129 * can be programmed into the associated watermark register, that watermark
1130 * must be disabled.
1131 */
1132static bool g4x_check_srwm(struct drm_device *dev,
1133 int display_wm, int cursor_wm,
1134 const struct intel_watermark_params *display,
1135 const struct intel_watermark_params *cursor)
1136{
1137 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138 display_wm, cursor_wm);
1139
1140 if (display_wm > display->max_wm) {
1141 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142 display_wm, display->max_wm);
1143 return false;
1144 }
1145
1146 if (cursor_wm > cursor->max_wm) {
1147 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148 cursor_wm, cursor->max_wm);
1149 return false;
1150 }
1151
1152 if (!(display_wm || cursor_wm)) {
1153 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1154 return false;
1155 }
1156
1157 return true;
1158}
1159
1160static bool g4x_compute_srwm(struct drm_device *dev,
1161 int plane,
1162 int latency_ns,
1163 const struct intel_watermark_params *display,
1164 const struct intel_watermark_params *cursor,
1165 int *display_wm, int *cursor_wm)
1166{
1167 struct drm_crtc *crtc;
1168 int hdisplay, htotal, pixel_size, clock;
1169 unsigned long line_time_us;
1170 int line_count, line_size;
1171 int small, large;
1172 int entries;
1173
1174 if (!latency_ns) {
1175 *display_wm = *cursor_wm = 0;
1176 return false;
1177 }
1178
1179 crtc = intel_get_crtc_for_plane(dev, plane);
1180 hdisplay = crtc->mode.hdisplay;
1181 htotal = crtc->mode.htotal;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 line_time_us = (htotal * 1000) / clock;
1186 line_count = (latency_ns / line_time_us + 1000) / 1000;
1187 line_size = hdisplay * pixel_size;
1188
1189 /* Use the minimum of the small and large buffer method for primary */
1190 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191 large = line_count * line_size;
1192
1193 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194 *display_wm = entries + display->guard_size;
1195
1196 /* calculate the self-refresh watermark for display cursor */
1197 entries = line_count * pixel_size * 64;
1198 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199 *cursor_wm = entries + cursor->guard_size;
1200
1201 return g4x_check_srwm(dev,
1202 *display_wm, *cursor_wm,
1203 display, cursor);
1204}
1205
1206static bool vlv_compute_drain_latency(struct drm_device *dev,
1207 int plane,
1208 int *plane_prec_mult,
1209 int *plane_dl,
1210 int *cursor_prec_mult,
1211 int *cursor_dl)
1212{
1213 struct drm_crtc *crtc;
1214 int clock, pixel_size;
1215 int entries;
1216
1217 crtc = intel_get_crtc_for_plane(dev, plane);
1218 if (crtc->fb == NULL || !crtc->enabled)
1219 return false;
1220
1221 clock = crtc->mode.clock; /* VESA DOT Clock */
1222 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1223
1224 entries = (clock / 1000) * pixel_size;
1225 *plane_prec_mult = (entries > 256) ?
1226 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1228 pixel_size);
1229
1230 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1231 *cursor_prec_mult = (entries > 256) ?
1232 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1234
1235 return true;
1236}
1237
1238/*
1239 * Update drain latency registers of memory arbiter
1240 *
1241 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242 * to be programmed. Each plane has a drain latency multiplier and a drain
1243 * latency value.
1244 */
1245
1246static void vlv_update_drain_latency(struct drm_device *dev)
1247{
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1252 either 16 or 32 */
1253
1254 /* For plane A, Cursor A */
1255 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256 &cursor_prec_mult, &cursora_dl)) {
1257 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1261
1262 I915_WRITE(VLV_DDL1, cursora_prec |
1263 (cursora_dl << DDL_CURSORA_SHIFT) |
1264 planea_prec | planea_dl);
1265 }
1266
1267 /* For plane B, Cursor B */
1268 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269 &cursor_prec_mult, &cursorb_dl)) {
1270 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1274
1275 I915_WRITE(VLV_DDL2, cursorb_prec |
1276 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277 planeb_prec | planeb_dl);
1278 }
1279}
1280
1281#define single_plane_enabled(mask) is_power_of_2(mask)
1282
1fa61106 1283static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1284{
1285 static const int sr_latency_ns = 12000;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288 int plane_sr, cursor_sr;
1289 unsigned int enabled = 0;
1290
1291 vlv_update_drain_latency(dev);
1292
1293 if (g4x_compute_wm0(dev, 0,
1294 &valleyview_wm_info, latency_ns,
1295 &valleyview_cursor_wm_info, latency_ns,
1296 &planea_wm, &cursora_wm))
1297 enabled |= 1;
1298
1299 if (g4x_compute_wm0(dev, 1,
1300 &valleyview_wm_info, latency_ns,
1301 &valleyview_cursor_wm_info, latency_ns,
1302 &planeb_wm, &cursorb_wm))
1303 enabled |= 2;
1304
1305 plane_sr = cursor_sr = 0;
1306 if (single_plane_enabled(enabled) &&
1307 g4x_compute_srwm(dev, ffs(enabled) - 1,
1308 sr_latency_ns,
1309 &valleyview_wm_info,
1310 &valleyview_cursor_wm_info,
1311 &plane_sr, &cursor_sr))
1312 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1313 else
1314 I915_WRITE(FW_BLC_SELF_VLV,
1315 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1316
1317 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1318 planea_wm, cursora_wm,
1319 planeb_wm, cursorb_wm,
1320 plane_sr, cursor_sr);
1321
1322 I915_WRITE(DSPFW1,
1323 (plane_sr << DSPFW_SR_SHIFT) |
1324 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1325 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1326 planea_wm);
1327 I915_WRITE(DSPFW2,
1328 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1329 (cursora_wm << DSPFW_CURSORA_SHIFT));
1330 I915_WRITE(DSPFW3,
1331 (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
1332}
1333
1fa61106 1334static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1335{
1336 static const int sr_latency_ns = 12000;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1339 int plane_sr, cursor_sr;
1340 unsigned int enabled = 0;
1341
1342 if (g4x_compute_wm0(dev, 0,
1343 &g4x_wm_info, latency_ns,
1344 &g4x_cursor_wm_info, latency_ns,
1345 &planea_wm, &cursora_wm))
1346 enabled |= 1;
1347
1348 if (g4x_compute_wm0(dev, 1,
1349 &g4x_wm_info, latency_ns,
1350 &g4x_cursor_wm_info, latency_ns,
1351 &planeb_wm, &cursorb_wm))
1352 enabled |= 2;
1353
1354 plane_sr = cursor_sr = 0;
1355 if (single_plane_enabled(enabled) &&
1356 g4x_compute_srwm(dev, ffs(enabled) - 1,
1357 sr_latency_ns,
1358 &g4x_wm_info,
1359 &g4x_cursor_wm_info,
1360 &plane_sr, &cursor_sr))
1361 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1362 else
1363 I915_WRITE(FW_BLC_SELF,
1364 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1365
1366 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1367 planea_wm, cursora_wm,
1368 planeb_wm, cursorb_wm,
1369 plane_sr, cursor_sr);
1370
1371 I915_WRITE(DSPFW1,
1372 (plane_sr << DSPFW_SR_SHIFT) |
1373 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1374 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1375 planea_wm);
1376 I915_WRITE(DSPFW2,
1377 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1378 (cursora_wm << DSPFW_CURSORA_SHIFT));
1379 /* HPLL off in SR has some issues on G4x... disable it */
1380 I915_WRITE(DSPFW3,
1381 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
1382 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1383}
1384
1fa61106 1385static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1386{
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 struct drm_crtc *crtc;
1389 int srwm = 1;
1390 int cursor_sr = 16;
1391
1392 /* Calc sr entries for one plane configs */
1393 crtc = single_enabled_crtc(dev);
1394 if (crtc) {
1395 /* self-refresh has much higher latency */
1396 static const int sr_latency_ns = 12000;
1397 int clock = crtc->mode.clock;
1398 int htotal = crtc->mode.htotal;
1399 int hdisplay = crtc->mode.hdisplay;
1400 int pixel_size = crtc->fb->bits_per_pixel / 8;
1401 unsigned long line_time_us;
1402 int entries;
1403
1404 line_time_us = ((htotal * 1000) / clock);
1405
1406 /* Use ns/us then divide to preserve precision */
1407 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1408 pixel_size * hdisplay;
1409 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1410 srwm = I965_FIFO_SIZE - entries;
1411 if (srwm < 0)
1412 srwm = 1;
1413 srwm &= 0x1ff;
1414 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1415 entries, srwm);
1416
1417 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1418 pixel_size * 64;
1419 entries = DIV_ROUND_UP(entries,
1420 i965_cursor_wm_info.cacheline_size);
1421 cursor_sr = i965_cursor_wm_info.fifo_size -
1422 (entries + i965_cursor_wm_info.guard_size);
1423
1424 if (cursor_sr > i965_cursor_wm_info.max_wm)
1425 cursor_sr = i965_cursor_wm_info.max_wm;
1426
1427 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1428 "cursor %d\n", srwm, cursor_sr);
1429
1430 if (IS_CRESTLINE(dev))
1431 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1432 } else {
1433 /* Turn off self refresh if both pipes are enabled */
1434 if (IS_CRESTLINE(dev))
1435 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1436 & ~FW_BLC_SELF_EN);
1437 }
1438
1439 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1440 srwm);
1441
1442 /* 965 has limitations... */
1443 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1444 (8 << 16) | (8 << 8) | (8 << 0));
1445 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1446 /* update cursor SR watermark */
1447 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1448}
1449
1fa61106 1450static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1451{
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 const struct intel_watermark_params *wm_info;
1454 uint32_t fwater_lo;
1455 uint32_t fwater_hi;
1456 int cwm, srwm = 1;
1457 int fifo_size;
1458 int planea_wm, planeb_wm;
1459 struct drm_crtc *crtc, *enabled = NULL;
1460
1461 if (IS_I945GM(dev))
1462 wm_info = &i945_wm_info;
1463 else if (!IS_GEN2(dev))
1464 wm_info = &i915_wm_info;
1465 else
1466 wm_info = &i855_wm_info;
1467
1468 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1469 crtc = intel_get_crtc_for_plane(dev, 0);
1470 if (crtc->enabled && crtc->fb) {
1471 planea_wm = intel_calculate_wm(crtc->mode.clock,
1472 wm_info, fifo_size,
1473 crtc->fb->bits_per_pixel / 8,
1474 latency_ns);
1475 enabled = crtc;
1476 } else
1477 planea_wm = fifo_size - wm_info->guard_size;
1478
1479 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1480 crtc = intel_get_crtc_for_plane(dev, 1);
1481 if (crtc->enabled && crtc->fb) {
1482 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1483 wm_info, fifo_size,
1484 crtc->fb->bits_per_pixel / 8,
1485 latency_ns);
1486 if (enabled == NULL)
1487 enabled = crtc;
1488 else
1489 enabled = NULL;
1490 } else
1491 planeb_wm = fifo_size - wm_info->guard_size;
1492
1493 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1494
1495 /*
1496 * Overlay gets an aggressive default since video jitter is bad.
1497 */
1498 cwm = 2;
1499
1500 /* Play safe and disable self-refresh before adjusting watermarks. */
1501 if (IS_I945G(dev) || IS_I945GM(dev))
1502 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1503 else if (IS_I915GM(dev))
1504 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1505
1506 /* Calc sr entries for one plane configs */
1507 if (HAS_FW_BLC(dev) && enabled) {
1508 /* self-refresh has much higher latency */
1509 static const int sr_latency_ns = 6000;
1510 int clock = enabled->mode.clock;
1511 int htotal = enabled->mode.htotal;
1512 int hdisplay = enabled->mode.hdisplay;
1513 int pixel_size = enabled->fb->bits_per_pixel / 8;
1514 unsigned long line_time_us;
1515 int entries;
1516
1517 line_time_us = (htotal * 1000) / clock;
1518
1519 /* Use ns/us then divide to preserve precision */
1520 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 pixel_size * hdisplay;
1522 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1523 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1524 srwm = wm_info->fifo_size - entries;
1525 if (srwm < 0)
1526 srwm = 1;
1527
1528 if (IS_I945G(dev) || IS_I945GM(dev))
1529 I915_WRITE(FW_BLC_SELF,
1530 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1531 else if (IS_I915GM(dev))
1532 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1533 }
1534
1535 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1536 planea_wm, planeb_wm, cwm, srwm);
1537
1538 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1539 fwater_hi = (cwm & 0x1f);
1540
1541 /* Set request length to 8 cachelines per fetch */
1542 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1543 fwater_hi = fwater_hi | (1 << 8);
1544
1545 I915_WRITE(FW_BLC, fwater_lo);
1546 I915_WRITE(FW_BLC2, fwater_hi);
1547
1548 if (HAS_FW_BLC(dev)) {
1549 if (enabled) {
1550 if (IS_I945G(dev) || IS_I945GM(dev))
1551 I915_WRITE(FW_BLC_SELF,
1552 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1553 else if (IS_I915GM(dev))
1554 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1555 DRM_DEBUG_KMS("memory self refresh enabled\n");
1556 } else
1557 DRM_DEBUG_KMS("memory self refresh disabled\n");
1558 }
1559}
1560
1fa61106 1561static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1562{
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 struct drm_crtc *crtc;
1565 uint32_t fwater_lo;
1566 int planea_wm;
1567
1568 crtc = single_enabled_crtc(dev);
1569 if (crtc == NULL)
1570 return;
1571
1572 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1573 dev_priv->display.get_fifo_size(dev, 0),
1574 crtc->fb->bits_per_pixel / 8,
1575 latency_ns);
1576 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1577 fwater_lo |= (3<<8) | planea_wm;
1578
1579 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1580
1581 I915_WRITE(FW_BLC, fwater_lo);
1582}
1583
1584#define ILK_LP0_PLANE_LATENCY 700
1585#define ILK_LP0_CURSOR_LATENCY 1300
1586
1587/*
1588 * Check the wm result.
1589 *
1590 * If any calculated watermark values is larger than the maximum value that
1591 * can be programmed into the associated watermark register, that watermark
1592 * must be disabled.
1593 */
1594static bool ironlake_check_srwm(struct drm_device *dev, int level,
1595 int fbc_wm, int display_wm, int cursor_wm,
1596 const struct intel_watermark_params *display,
1597 const struct intel_watermark_params *cursor)
1598{
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1602 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1603
1604 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1605 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1606 fbc_wm, SNB_FBC_MAX_SRWM, level);
1607
1608 /* fbc has it's own way to disable FBC WM */
1609 I915_WRITE(DISP_ARB_CTL,
1610 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1611 return false;
1612 }
1613
1614 if (display_wm > display->max_wm) {
1615 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1616 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1617 return false;
1618 }
1619
1620 if (cursor_wm > cursor->max_wm) {
1621 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1622 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1623 return false;
1624 }
1625
1626 if (!(fbc_wm || display_wm || cursor_wm)) {
1627 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1628 return false;
1629 }
1630
1631 return true;
1632}
1633
1634/*
1635 * Compute watermark values of WM[1-3],
1636 */
1637static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1638 int latency_ns,
1639 const struct intel_watermark_params *display,
1640 const struct intel_watermark_params *cursor,
1641 int *fbc_wm, int *display_wm, int *cursor_wm)
1642{
1643 struct drm_crtc *crtc;
1644 unsigned long line_time_us;
1645 int hdisplay, htotal, pixel_size, clock;
1646 int line_count, line_size;
1647 int small, large;
1648 int entries;
1649
1650 if (!latency_ns) {
1651 *fbc_wm = *display_wm = *cursor_wm = 0;
1652 return false;
1653 }
1654
1655 crtc = intel_get_crtc_for_plane(dev, plane);
1656 hdisplay = crtc->mode.hdisplay;
1657 htotal = crtc->mode.htotal;
1658 clock = crtc->mode.clock;
1659 pixel_size = crtc->fb->bits_per_pixel / 8;
1660
1661 line_time_us = (htotal * 1000) / clock;
1662 line_count = (latency_ns / line_time_us + 1000) / 1000;
1663 line_size = hdisplay * pixel_size;
1664
1665 /* Use the minimum of the small and large buffer method for primary */
1666 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1667 large = line_count * line_size;
1668
1669 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1670 *display_wm = entries + display->guard_size;
1671
1672 /*
1673 * Spec says:
1674 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1675 */
1676 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1677
1678 /* calculate the self-refresh watermark for display cursor */
1679 entries = line_count * pixel_size * 64;
1680 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1681 *cursor_wm = entries + cursor->guard_size;
1682
1683 return ironlake_check_srwm(dev, level,
1684 *fbc_wm, *display_wm, *cursor_wm,
1685 display, cursor);
1686}
1687
1fa61106 1688static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1689{
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int fbc_wm, plane_wm, cursor_wm;
1692 unsigned int enabled;
1693
1694 enabled = 0;
1695 if (g4x_compute_wm0(dev, 0,
1696 &ironlake_display_wm_info,
1697 ILK_LP0_PLANE_LATENCY,
1698 &ironlake_cursor_wm_info,
1699 ILK_LP0_CURSOR_LATENCY,
1700 &plane_wm, &cursor_wm)) {
1701 I915_WRITE(WM0_PIPEA_ILK,
1702 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1703 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1704 " plane %d, " "cursor: %d\n",
1705 plane_wm, cursor_wm);
1706 enabled |= 1;
1707 }
1708
1709 if (g4x_compute_wm0(dev, 1,
1710 &ironlake_display_wm_info,
1711 ILK_LP0_PLANE_LATENCY,
1712 &ironlake_cursor_wm_info,
1713 ILK_LP0_CURSOR_LATENCY,
1714 &plane_wm, &cursor_wm)) {
1715 I915_WRITE(WM0_PIPEB_ILK,
1716 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1717 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1718 " plane %d, cursor: %d\n",
1719 plane_wm, cursor_wm);
1720 enabled |= 2;
1721 }
1722
1723 /*
1724 * Calculate and update the self-refresh watermark only when one
1725 * display plane is used.
1726 */
1727 I915_WRITE(WM3_LP_ILK, 0);
1728 I915_WRITE(WM2_LP_ILK, 0);
1729 I915_WRITE(WM1_LP_ILK, 0);
1730
1731 if (!single_plane_enabled(enabled))
1732 return;
1733 enabled = ffs(enabled) - 1;
1734
1735 /* WM1 */
1736 if (!ironlake_compute_srwm(dev, 1, enabled,
1737 ILK_READ_WM1_LATENCY() * 500,
1738 &ironlake_display_srwm_info,
1739 &ironlake_cursor_srwm_info,
1740 &fbc_wm, &plane_wm, &cursor_wm))
1741 return;
1742
1743 I915_WRITE(WM1_LP_ILK,
1744 WM1_LP_SR_EN |
1745 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1746 (fbc_wm << WM1_LP_FBC_SHIFT) |
1747 (plane_wm << WM1_LP_SR_SHIFT) |
1748 cursor_wm);
1749
1750 /* WM2 */
1751 if (!ironlake_compute_srwm(dev, 2, enabled,
1752 ILK_READ_WM2_LATENCY() * 500,
1753 &ironlake_display_srwm_info,
1754 &ironlake_cursor_srwm_info,
1755 &fbc_wm, &plane_wm, &cursor_wm))
1756 return;
1757
1758 I915_WRITE(WM2_LP_ILK,
1759 WM2_LP_EN |
1760 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1761 (fbc_wm << WM1_LP_FBC_SHIFT) |
1762 (plane_wm << WM1_LP_SR_SHIFT) |
1763 cursor_wm);
1764
1765 /*
1766 * WM3 is unsupported on ILK, probably because we don't have latency
1767 * data for that power state
1768 */
1769}
1770
1fa61106 1771static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1772{
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1775 u32 val;
1776 int fbc_wm, plane_wm, cursor_wm;
1777 unsigned int enabled;
1778
1779 enabled = 0;
1780 if (g4x_compute_wm0(dev, 0,
1781 &sandybridge_display_wm_info, latency,
1782 &sandybridge_cursor_wm_info, latency,
1783 &plane_wm, &cursor_wm)) {
1784 val = I915_READ(WM0_PIPEA_ILK);
1785 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1786 I915_WRITE(WM0_PIPEA_ILK, val |
1787 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1788 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1789 " plane %d, " "cursor: %d\n",
1790 plane_wm, cursor_wm);
1791 enabled |= 1;
1792 }
1793
1794 if (g4x_compute_wm0(dev, 1,
1795 &sandybridge_display_wm_info, latency,
1796 &sandybridge_cursor_wm_info, latency,
1797 &plane_wm, &cursor_wm)) {
1798 val = I915_READ(WM0_PIPEB_ILK);
1799 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1800 I915_WRITE(WM0_PIPEB_ILK, val |
1801 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1802 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1803 " plane %d, cursor: %d\n",
1804 plane_wm, cursor_wm);
1805 enabled |= 2;
1806 }
1807
461bc9b5 1808 if ((dev_priv->num_pipe == 3) &&
b445e3b0
ED		 1809 g4x_compute_wm0(dev, 2,
1810 &sandybridge_display_wm_info, latency,
1811 &sandybridge_cursor_wm_info, latency,
1812 &plane_wm, &cursor_wm)) {
1813 val = I915_READ(WM0_PIPEC_IVB);
1814 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1815 I915_WRITE(WM0_PIPEC_IVB, val |
1816 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1817 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1818 " plane %d, cursor: %d\n",
1819 plane_wm, cursor_wm);
1820 enabled |= 3;
1821 }
1822
1823 /*
1824 * Calculate and update the self-refresh watermark only when one
1825 * display plane is used.
1826 *
1827 * SNB support 3 levels of watermark.
1828 *
1829 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1830 * and disabled in the descending order
1831 *
1832 */
1833 I915_WRITE(WM3_LP_ILK, 0);
1834 I915_WRITE(WM2_LP_ILK, 0);
1835 I915_WRITE(WM1_LP_ILK, 0);
1836
1837 if (!single_plane_enabled(enabled) ||
1838 dev_priv->sprite_scaling_enabled)
1839 return;
1840 enabled = ffs(enabled) - 1;
1841
1842 /* WM1 */
1843 if (!ironlake_compute_srwm(dev, 1, enabled,
1844 SNB_READ_WM1_LATENCY() * 500,
1845 &sandybridge_display_srwm_info,
1846 &sandybridge_cursor_srwm_info,
1847 &fbc_wm, &plane_wm, &cursor_wm))
1848 return;
1849
1850 I915_WRITE(WM1_LP_ILK,
1851 WM1_LP_SR_EN |
1852 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1853 (fbc_wm << WM1_LP_FBC_SHIFT) |
1854 (plane_wm << WM1_LP_SR_SHIFT) |
1855 cursor_wm);
1856
1857 /* WM2 */
1858 if (!ironlake_compute_srwm(dev, 2, enabled,
1859 SNB_READ_WM2_LATENCY() * 500,
1860 &sandybridge_display_srwm_info,
1861 &sandybridge_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1863 return;
1864
1865 I915_WRITE(WM2_LP_ILK,
1866 WM2_LP_EN |
1867 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1870 cursor_wm);
1871
1872 /* WM3 */
1873 if (!ironlake_compute_srwm(dev, 3, enabled,
1874 SNB_READ_WM3_LATENCY() * 500,
1875 &sandybridge_display_srwm_info,
1876 &sandybridge_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1878 return;
1879
1880 I915_WRITE(WM3_LP_ILK,
1881 WM3_LP_EN |
1882 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1885 cursor_wm);
1886}
1887
1f8eeabf
ED		 1888static void
1889haswell_update_linetime_wm(struct drm_device *dev, int pipe,
1890 struct drm_display_mode *mode)
1891{
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1893 u32 temp;
1894
1895 temp = I915_READ(PIPE_WM_LINETIME(pipe));
1896 temp &= ~PIPE_WM_LINETIME_MASK;
1897
1898 /* The WM are computed with base on how long it takes to fill a single
1899 * row at the given clock rate, multiplied by 8.
1900 * */
1901 temp |= PIPE_WM_LINETIME_TIME(
1902 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
1903
1904 /* IPS watermarks are only used by pipe A, and are ignored by
1905 * pipes B and C. They are calculated similarly to the common
1906 * linetime values, except that we are using CD clock frequency
1907 * in MHz instead of pixel rate for the division.
1908 *
1909 * This is a placeholder for the IPS watermark calculation code.
1910 */
1911
1912 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
1913}
1914
b445e3b0
ED		 1915static bool
1916sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1917 uint32_t sprite_width, int pixel_size,
1918 const struct intel_watermark_params *display,
1919 int display_latency_ns, int *sprite_wm)
1920{
1921 struct drm_crtc *crtc;
1922 int clock;
1923 int entries, tlb_miss;
1924
1925 crtc = intel_get_crtc_for_plane(dev, plane);
1926 if (crtc->fb == NULL || !crtc->enabled) {
1927 *sprite_wm = display->guard_size;
1928 return false;
1929 }
1930
1931 clock = crtc->mode.clock;
1932
1933 /* Use the small buffer method to calculate the sprite watermark */
1934 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1935 tlb_miss = display->fifo_size*display->cacheline_size -
1936 sprite_width * 8;
1937 if (tlb_miss > 0)
1938 entries += tlb_miss;
1939 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1940 *sprite_wm = entries + display->guard_size;
1941 if (*sprite_wm > (int)display->max_wm)
1942 *sprite_wm = display->max_wm;
1943
1944 return true;
1945}
1946
1947static bool
1948sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1949 uint32_t sprite_width, int pixel_size,
1950 const struct intel_watermark_params *display,
1951 int latency_ns, int *sprite_wm)
1952{
1953 struct drm_crtc *crtc;
1954 unsigned long line_time_us;
1955 int clock;
1956 int line_count, line_size;
1957 int small, large;
1958 int entries;
1959
1960 if (!latency_ns) {
1961 *sprite_wm = 0;
1962 return false;
1963 }
1964
1965 crtc = intel_get_crtc_for_plane(dev, plane);
1966 clock = crtc->mode.clock;
1967 if (!clock) {
1968 *sprite_wm = 0;
1969 return false;
1970 }
1971
1972 line_time_us = (sprite_width * 1000) / clock;
1973 if (!line_time_us) {
1974 *sprite_wm = 0;
1975 return false;
1976 }
1977
1978 line_count = (latency_ns / line_time_us + 1000) / 1000;
1979 line_size = sprite_width * pixel_size;
1980
1981 /* Use the minimum of the small and large buffer method for primary */
1982 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1983 large = line_count * line_size;
1984
1985 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1986 *sprite_wm = entries + display->guard_size;
1987
1988 return *sprite_wm > 0x3ff ? false : true;
1989}
1990
1fa61106 1991static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 1992 uint32_t sprite_width, int pixel_size)
1993{
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1996 u32 val;
1997 int sprite_wm, reg;
1998 int ret;
1999
2000 switch (pipe) {
2001 case 0:
2002 reg = WM0_PIPEA_ILK;
2003 break;
2004 case 1:
2005 reg = WM0_PIPEB_ILK;
2006 break;
2007 case 2:
2008 reg = WM0_PIPEC_IVB;
2009 break;
2010 default:
2011 return; /* bad pipe */
2012 }
2013
2014 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2015 &sandybridge_display_wm_info,
2016 latency, &sprite_wm);
2017 if (!ret) {
2018 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2019 pipe);
2020 return;
2021 }
2022
2023 val = I915_READ(reg);
2024 val &= ~WM0_PIPE_SPRITE_MASK;
2025 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2026 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2027
2028
2029 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2030 pixel_size,
2031 &sandybridge_display_srwm_info,
2032 SNB_READ_WM1_LATENCY() * 500,
2033 &sprite_wm);
2034 if (!ret) {
2035 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2036 pipe);
2037 return;
2038 }
2039 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2040
2041 /* Only IVB has two more LP watermarks for sprite */
2042 if (!IS_IVYBRIDGE(dev))
2043 return;
2044
2045 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2046 pixel_size,
2047 &sandybridge_display_srwm_info,
2048 SNB_READ_WM2_LATENCY() * 500,
2049 &sprite_wm);
2050 if (!ret) {
2051 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2052 pipe);
2053 return;
2054 }
2055 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2056
2057 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2058 pixel_size,
2059 &sandybridge_display_srwm_info,
2060 SNB_READ_WM3_LATENCY() * 500,
2061 &sprite_wm);
2062 if (!ret) {
2063 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2064 pipe);
2065 return;
2066 }
2067 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2068}
2069
2070/**
2071 * intel_update_watermarks - update FIFO watermark values based on current modes
2072 *
2073 * Calculate watermark values for the various WM regs based on current mode
2074 * and plane configuration.
2075 *
2076 * There are several cases to deal with here:
2077 * - normal (i.e. non-self-refresh)
2078 * - self-refresh (SR) mode
2079 * - lines are large relative to FIFO size (buffer can hold up to 2)
2080 * - lines are small relative to FIFO size (buffer can hold more than 2
2081 * lines), so need to account for TLB latency
2082 *
2083 * The normal calculation is:
2084 * watermark = dotclock * bytes per pixel * latency
2085 * where latency is platform & configuration dependent (we assume pessimal
2086 * values here).
2087 *
2088 * The SR calculation is:
2089 * watermark = (trunc(latency/line time)+1) * surface width *
2090 * bytes per pixel
2091 * where
2092 * line time = htotal / dotclock
2093 * surface width = hdisplay for normal plane and 64 for cursor
2094 * and latency is assumed to be high, as above.
2095 *
2096 * The final value programmed to the register should always be rounded up,
2097 * and include an extra 2 entries to account for clock crossings.
2098 *
2099 * We don't use the sprite, so we can ignore that. And on Crestline we have
2100 * to set the non-SR watermarks to 8.
2101 */
2102void intel_update_watermarks(struct drm_device *dev)
2103{
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105
2106 if (dev_priv->display.update_wm)
2107 dev_priv->display.update_wm(dev);
2108}
2109
1f8eeabf
ED		 2110void intel_update_linetime_watermarks(struct drm_device *dev,
2111 int pipe, struct drm_display_mode *mode)
2112{
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114
2115 if (dev_priv->display.update_linetime_wm)
2116 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2117}
2118
b445e3b0
ED		 2119void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2120 uint32_t sprite_width, int pixel_size)
2121{
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123
2124 if (dev_priv->display.update_sprite_wm)
2125 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2126 pixel_size);
2127}
2128
2b4e57bd
ED		 2129static struct drm_i915_gem_object *
2130intel_alloc_context_page(struct drm_device *dev)
2131{
2132 struct drm_i915_gem_object *ctx;
2133 int ret;
2134
2135 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137 ctx = i915_gem_alloc_object(dev, 4096);
2138 if (!ctx) {
2139 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2140 return NULL;
2141 }
2142
2143 ret = i915_gem_object_pin(ctx, 4096, true);
2144 if (ret) {
2145 DRM_ERROR("failed to pin power context: %d\n", ret);
2146 goto err_unref;
2147 }
2148
2149 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2150 if (ret) {
2151 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2152 goto err_unpin;
2153 }
2154
2155 return ctx;
2156
2157err_unpin:
2158 i915_gem_object_unpin(ctx);
2159err_unref:
2160 drm_gem_object_unreference(&ctx->base);
2161 mutex_unlock(&dev->struct_mutex);
2162 return NULL;
2163}
2164
2165bool ironlake_set_drps(struct drm_device *dev, u8 val)
2166{
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 u16 rgvswctl;
2169
2170 rgvswctl = I915_READ16(MEMSWCTL);
2171 if (rgvswctl & MEMCTL_CMD_STS) {
2172 DRM_DEBUG("gpu busy, RCS change rejected\n");
2173 return false; /* still busy with another command */
2174 }
2175
2176 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2177 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2178 I915_WRITE16(MEMSWCTL, rgvswctl);
2179 POSTING_READ16(MEMSWCTL);
2180
2181 rgvswctl |= MEMCTL_CMD_STS;
2182 I915_WRITE16(MEMSWCTL, rgvswctl);
2183
2184 return true;
2185}
2186
8090c6b9 2187static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2188{
2189 struct drm_i915_private *dev_priv = dev->dev_private;
2190 u32 rgvmodectl = I915_READ(MEMMODECTL);
2191 u8 fmax, fmin, fstart, vstart;
2192
2193 /* Enable temp reporting */
2194 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2195 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2196
2197 /* 100ms RC evaluation intervals */
2198 I915_WRITE(RCUPEI, 100000);
2199 I915_WRITE(RCDNEI, 100000);
2200
2201 /* Set max/min thresholds to 90ms and 80ms respectively */
2202 I915_WRITE(RCBMAXAVG, 90000);
2203 I915_WRITE(RCBMINAVG, 80000);
2204
2205 I915_WRITE(MEMIHYST, 1);
2206
2207 /* Set up min, max, and cur for interrupt handling */
2208 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2209 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2210 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2211 MEMMODE_FSTART_SHIFT;
2212
2213 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2214 PXVFREQ_PX_SHIFT;
2215
2216 dev_priv->fmax = fmax; /* IPS callback will increase this */
2217 dev_priv->fstart = fstart;
2218
2219 dev_priv->max_delay = fstart;
2220 dev_priv->min_delay = fmin;
2221 dev_priv->cur_delay = fstart;
2222
2223 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2224 fmax, fmin, fstart);
2225
2226 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2227
2228 /*
2229 * Interrupts will be enabled in ironlake_irq_postinstall
2230 */
2231
2232 I915_WRITE(VIDSTART, vstart);
2233 POSTING_READ(VIDSTART);
2234
2235 rgvmodectl |= MEMMODE_SWMODE_EN;
2236 I915_WRITE(MEMMODECTL, rgvmodectl);
2237
2238 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2239 DRM_ERROR("stuck trying to change perf mode\n");
2240 msleep(1);
2241
2242 ironlake_set_drps(dev, fstart);
2243
2244 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2245 I915_READ(0x112e0);
2246 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
2247 dev_priv->last_count2 = I915_READ(0x112f4);
2248 getrawmonotonic(&dev_priv->last_time2);
2249}
2250
8090c6b9 2251static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2252{
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254 u16 rgvswctl = I915_READ16(MEMSWCTL);
2255
2256 /* Ack interrupts, disable EFC interrupt */
2257 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2258 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2259 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2260 I915_WRITE(DEIIR, DE_PCU_EVENT);
2261 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2262
2263 /* Go back to the starting frequency */
2264 ironlake_set_drps(dev, dev_priv->fstart);
2265 msleep(1);
2266 rgvswctl |= MEMCTL_CMD_STS;
2267 I915_WRITE(MEMSWCTL, rgvswctl);
2268 msleep(1);
2269
2270}
2271
2272void gen6_set_rps(struct drm_device *dev, u8 val)
2273{
2274 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 2275 u32 limits;
2b4e57bd 2276
7b9e0ae6
CW		 2277 limits = 0;
2278 if (val >= dev_priv->max_delay)
2279 val = dev_priv->max_delay;
2280 else
2281 limits |= dev_priv->max_delay << 24;
2282
2283 if (val <= dev_priv->min_delay)
2284 val = dev_priv->min_delay;
2285 else
2286 limits |= dev_priv->min_delay << 16;
2287
2288 if (val == dev_priv->cur_delay)
2289 return;
2290
2291 I915_WRITE(GEN6_RPNSWREQ,
2292 GEN6_FREQUENCY(val) |
2293 GEN6_OFFSET(0) |
2294 GEN6_AGGRESSIVE_TURBO);
2295
2296 /* Make sure we continue to get interrupts
2297 * until we hit the minimum or maximum frequencies.
2298 */
2299 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2300
2301 dev_priv->cur_delay = val;
2b4e57bd
ED		 2302}
2303
8090c6b9 2304static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2305{
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307
88509484 2308 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2309 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2310 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2311 I915_WRITE(GEN6_PMIER, 0);
2312 /* Complete PM interrupt masking here doesn't race with the rps work
2313 * item again unmasking PM interrupts because that is using a different
2314 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2315 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2316
2317 spin_lock_irq(&dev_priv->rps_lock);
2318 dev_priv->pm_iir = 0;
2319 spin_unlock_irq(&dev_priv->rps_lock);
2320
2321 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2322}
2323
2324int intel_enable_rc6(const struct drm_device *dev)
2325{
2326 /*
2327 * Respect the kernel parameter if it is set
2328 */
2329 if (i915_enable_rc6 >= 0)
2330 return i915_enable_rc6;
2331
2332 /*
2333 * Disable RC6 on Ironlake
2334 */
2335 if (INTEL_INFO(dev)->gen == 5)
2336 return 0;
2337
4a637c2c
ED		 2338 /* On Haswell, only RC6 is available. So let's enable it by default to
2339 * provide better testing and coverage since the beginning.
2340 */
2b4e57bd 2341 if (IS_HASWELL(dev))
4a637c2c 2342 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 2343
2344 /*
2345 * Disable rc6 on Sandybridge
2346 */
2347 if (INTEL_INFO(dev)->gen == 6) {
2348 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2349 return INTEL_RC6_ENABLE;
2350 }
2351 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2352 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2353}
2354
79f5b2c7 2355static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2356{
79f5b2c7 2357 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2358 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2359 u32 rp_state_cap;
2360 u32 gt_perf_status;
2b4e57bd
ED		 2361 u32 pcu_mbox, rc6_mask = 0;
2362 u32 gtfifodbg;
2b4e57bd
ED		 2363 int rc6_mode;
2364 int i;
2365
79f5b2c7
DV		 2366 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2367
2b4e57bd
ED		 2368 /* Here begins a magic sequence of register writes to enable
2369 * auto-downclocking.
2370 *
2371 * Perhaps there might be some value in exposing these to
2372 * userspace...
2373 */
2374 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2375
2376 /* Clear the DBG now so we don't confuse earlier errors */
2377 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2378 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2379 I915_WRITE(GTFIFODBG, gtfifodbg);
2380 }
2381
2382 gen6_gt_force_wake_get(dev_priv);
2383
7b9e0ae6
CW		 2384 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2385 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2386
2387 /* In units of 100MHz */
2388 dev_priv->max_delay = rp_state_cap & 0xff;
2389 dev_priv->min_delay = (rp_state_cap & 0xff0000) >> 16;
2390 dev_priv->cur_delay = 0;
2391
2b4e57bd
ED		 2392 /* disable the counters and set deterministic thresholds */
2393 I915_WRITE(GEN6_RC_CONTROL, 0);
2394
2395 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2396 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2397 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2398 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2399 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2400
b4519513
CW		 2401 for_each_ring(ring, dev_priv, i)
2402 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2403
2404 I915_WRITE(GEN6_RC_SLEEP, 0);
2405 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2406 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2407 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2408 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2409
5a7dc92a 2410 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2411 rc6_mode = intel_enable_rc6(dev_priv->dev);
2412 if (rc6_mode & INTEL_RC6_ENABLE)
2413 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2414
5a7dc92a
ED		 2415 /* We don't use those on Haswell */
2416 if (!IS_HASWELL(dev)) {
2417 if (rc6_mode & INTEL_RC6p_ENABLE)
2418 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2419
5a7dc92a
ED		 2420 if (rc6_mode & INTEL_RC6pp_ENABLE)
2421 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2422 }
2b4e57bd
ED		 2423
2424 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2425 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2426 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2427 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2428
2429 I915_WRITE(GEN6_RC_CONTROL,
2430 rc6_mask |
2431 GEN6_RC_CTL_EI_MODE(1) |
2432 GEN6_RC_CTL_HW_ENABLE);
2433
2434 I915_WRITE(GEN6_RPNSWREQ,
2435 GEN6_FREQUENCY(10) |
2436 GEN6_OFFSET(0) |
2437 GEN6_AGGRESSIVE_TURBO);
2438 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2439 GEN6_FREQUENCY(12));
2440
2441 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2442 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7b9e0ae6
CW		 2443 dev_priv->max_delay << 24 |
2444 dev_priv->min_delay << 16);
5a7dc92a
ED		 2445
2446 if (IS_HASWELL(dev)) {
2447 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2448 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2449 I915_WRITE(GEN6_RP_UP_EI, 66000);
2450 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2451 } else {
2452 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
2453 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
2454 I915_WRITE(GEN6_RP_UP_EI, 100000);
2455 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
2456 }
2457
2b4e57bd
ED		 2458 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2459 I915_WRITE(GEN6_RP_CONTROL,
2460 GEN6_RP_MEDIA_TURBO |
89ba829e 2461 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2462 GEN6_RP_MEDIA_IS_GFX |
2463 GEN6_RP_ENABLE |
2464 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2465 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd
ED		 2466
2467 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2468 500))
2469 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2470
2471 I915_WRITE(GEN6_PCODE_DATA, 0);
2472 I915_WRITE(GEN6_PCODE_MAILBOX,
2473 GEN6_PCODE_READY |
2474 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
2475 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2476 500))
2477 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2478
2b4e57bd
ED		 2479 /* Check for overclock support */
2480 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2481 500))
2482 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
2483 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
2484 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
2485 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
2486 500))
2487 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
2488 if (pcu_mbox & (1<<31)) { /* OC supported */
7b9e0ae6 2489 dev_priv->max_delay = pcu_mbox & 0xff;
2b4e57bd
ED		 2490 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2491 }
2492
7b9e0ae6 2493 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2494
2495 /* requires MSI enabled */
2496 I915_WRITE(GEN6_PMIER,
2497 GEN6_PM_MBOX_EVENT |
2498 GEN6_PM_THERMAL_EVENT |
2499 GEN6_PM_RP_DOWN_TIMEOUT |
2500 GEN6_PM_RP_UP_THRESHOLD |
2501 GEN6_PM_RP_DOWN_THRESHOLD |
2502 GEN6_PM_RP_UP_EI_EXPIRED |
2503 GEN6_PM_RP_DOWN_EI_EXPIRED);
2504 spin_lock_irq(&dev_priv->rps_lock);
2505 WARN_ON(dev_priv->pm_iir != 0);
2506 I915_WRITE(GEN6_PMIMR, 0);
2507 spin_unlock_irq(&dev_priv->rps_lock);
2508 /* enable all PM interrupts */
2509 I915_WRITE(GEN6_PMINTRMSK, 0);
2510
2511 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2512}
2513
79f5b2c7 2514static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2515{
79f5b2c7 2516 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd
ED		 2517 int min_freq = 15;
2518 int gpu_freq, ia_freq, max_ia_freq;
2519 int scaling_factor = 180;
2520
79f5b2c7
DV		 2521 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2522
2b4e57bd
ED		 2523 max_ia_freq = cpufreq_quick_get_max(0);
2524 /*
2525 * Default to measured freq if none found, PCU will ensure we don't go
2526 * over
2527 */
2528 if (!max_ia_freq)
2529 max_ia_freq = tsc_khz;
2530
2531 /* Convert from kHz to MHz */
2532 max_ia_freq /= 1000;
2533
2b4e57bd
ED		 2534 /*
2535 * For each potential GPU frequency, load a ring frequency we'd like
2536 * to use for memory access. We do this by specifying the IA frequency
2537 * the PCU should use as a reference to determine the ring frequency.
2538 */
2539 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
2540 gpu_freq--) {
2541 int diff = dev_priv->max_delay - gpu_freq;
2542
2543 /*
2544 * For GPU frequencies less than 750MHz, just use the lowest
2545 * ring freq.
2546 */
2547 if (gpu_freq < min_freq)
2548 ia_freq = 800;
2549 else
2550 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2551 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2552
2553 I915_WRITE(GEN6_PCODE_DATA,
2554 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
2555 gpu_freq);
2556 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
2557 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
2558 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
2559 GEN6_PCODE_READY) == 0, 10)) {
2560 DRM_ERROR("pcode write of freq table timed out\n");
2561 continue;
2562 }
2563 }
2b4e57bd
ED		 2564}
2565
2566static void ironlake_teardown_rc6(struct drm_device *dev)
2567{
2568 struct drm_i915_private *dev_priv = dev->dev_private;
2569
2570 if (dev_priv->renderctx) {
2571 i915_gem_object_unpin(dev_priv->renderctx);
2572 drm_gem_object_unreference(&dev_priv->renderctx->base);
2573 dev_priv->renderctx = NULL;
2574 }
2575
2576 if (dev_priv->pwrctx) {
2577 i915_gem_object_unpin(dev_priv->pwrctx);
2578 drm_gem_object_unreference(&dev_priv->pwrctx->base);
2579 dev_priv->pwrctx = NULL;
2580 }
2581}
2582
2583void ironlake_disable_rc6(struct drm_device *dev)
2584{
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586
2587 if (I915_READ(PWRCTXA)) {
2588 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2589 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2590 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2591 50);
2592
2593 I915_WRITE(PWRCTXA, 0);
2594 POSTING_READ(PWRCTXA);
2595
2596 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2597 POSTING_READ(RSTDBYCTL);
2598 }
2599
2600 ironlake_teardown_rc6(dev);
2601}
2602
2603static int ironlake_setup_rc6(struct drm_device *dev)
2604{
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606
2607 if (dev_priv->renderctx == NULL)
2608 dev_priv->renderctx = intel_alloc_context_page(dev);
2609 if (!dev_priv->renderctx)
2610 return -ENOMEM;
2611
2612 if (dev_priv->pwrctx == NULL)
2613 dev_priv->pwrctx = intel_alloc_context_page(dev);
2614 if (!dev_priv->pwrctx) {
2615 ironlake_teardown_rc6(dev);
2616 return -ENOMEM;
2617 }
2618
2619 return 0;
2620}
2621
2622void ironlake_enable_rc6(struct drm_device *dev)
2623{
2624 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 2625 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2b4e57bd
ED		 2626 int ret;
2627
2628 /* rc6 disabled by default due to repeated reports of hanging during
2629 * boot and resume.
2630 */
2631 if (!intel_enable_rc6(dev))
2632 return;
2633
79f5b2c7
DV		 2634 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2635
2b4e57bd 2636 ret = ironlake_setup_rc6(dev);
79f5b2c7 2637 if (ret)
2b4e57bd 2638 return;
2b4e57bd
ED		 2639
2640 /*
2641 * GPU can automatically power down the render unit if given a page
2642 * to save state.
2643 */
6d90c952 2644 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 2645 if (ret) {
2646 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2647 return;
2648 }
2649
6d90c952
DV		 2650 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2651 intel_ring_emit(ring, MI_SET_CONTEXT);
2652 intel_ring_emit(ring, dev_priv->renderctx->gtt_offset |
2653 MI_MM_SPACE_GTT |
2654 MI_SAVE_EXT_STATE_EN |
2655 MI_RESTORE_EXT_STATE_EN |
2656 MI_RESTORE_INHIBIT);
2657 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2658 intel_ring_emit(ring, MI_NOOP);
2659 intel_ring_emit(ring, MI_FLUSH);
2660 intel_ring_advance(ring);
2b4e57bd
ED		 2661
2662 /*
2663 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2664 * does an implicit flush, combined with MI_FLUSH above, it should be
2665 * safe to assume that renderctx is valid
2666 */
6d90c952 2667 ret = intel_wait_ring_idle(ring);
2b4e57bd
ED		 2668 if (ret) {
2669 DRM_ERROR("failed to enable ironlake power power savings\n");
2670 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2671 return;
2672 }
2673
2674 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
2675 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 2676}
2677
dde18883
ED		 2678static unsigned long intel_pxfreq(u32 vidfreq)
2679{
2680 unsigned long freq;
2681 int div = (vidfreq & 0x3f0000) >> 16;
2682 int post = (vidfreq & 0x3000) >> 12;
2683 int pre = (vidfreq & 0x7);
2684
2685 if (!pre)
2686 return 0;
2687
2688 freq = ((div * 133333) / ((1<<post) * pre));
2689
2690 return freq;
2691}
2692
eb48eb00
DV		 2693static const struct cparams {
2694 u16 i;
2695 u16 t;
2696 u16 m;
2697 u16 c;
2698} cparams[] = {
2699 { 1, 1333, 301, 28664 },
2700 { 1, 1066, 294, 24460 },
2701 { 1, 800, 294, 25192 },
2702 { 0, 1333, 276, 27605 },
2703 { 0, 1066, 276, 27605 },
2704 { 0, 800, 231, 23784 },
2705};
2706
2707unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2708{
2709 u64 total_count, diff, ret;
2710 u32 count1, count2, count3, m = 0, c = 0;
2711 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2712 int i;
2713
2714 diff1 = now - dev_priv->last_time1;
2715
2716 /* Prevent division-by-zero if we are asking too fast.
2717 * Also, we don't get interesting results if we are polling
2718 * faster than once in 10ms, so just return the saved value
2719 * in such cases.
2720 */
2721 if (diff1 <= 10)
2722 return dev_priv->chipset_power;
2723
2724 count1 = I915_READ(DMIEC);
2725 count2 = I915_READ(DDREC);
2726 count3 = I915_READ(CSIEC);
2727
2728 total_count = count1 + count2 + count3;
2729
2730 /* FIXME: handle per-counter overflow */
2731 if (total_count < dev_priv->last_count1) {
2732 diff = ~0UL - dev_priv->last_count1;
2733 diff += total_count;
2734 } else {
2735 diff = total_count - dev_priv->last_count1;
2736 }
2737
2738 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
2739 if (cparams[i].i == dev_priv->c_m &&
2740 cparams[i].t == dev_priv->r_t) {
2741 m = cparams[i].m;
2742 c = cparams[i].c;
2743 break;
2744 }
2745 }
2746
2747 diff = div_u64(diff, diff1);
2748 ret = ((m * diff) + c);
2749 ret = div_u64(ret, 10);
2750
2751 dev_priv->last_count1 = total_count;
2752 dev_priv->last_time1 = now;
2753
2754 dev_priv->chipset_power = ret;
2755
2756 return ret;
2757}
2758
2759unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2760{
2761 unsigned long m, x, b;
2762 u32 tsfs;
2763
2764 tsfs = I915_READ(TSFS);
2765
2766 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2767 x = I915_READ8(TR1);
2768
2769 b = tsfs & TSFS_INTR_MASK;
2770
2771 return ((m * x) / 127) - b;
2772}
2773
2774static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2775{
2776 static const struct v_table {
2777 u16 vd; /* in .1 mil */
2778 u16 vm; /* in .1 mil */
2779 } v_table[] = {
2780 { 0, 0, },
2781 { 375, 0, },
2782 { 500, 0, },
2783 { 625, 0, },
2784 { 750, 0, },
2785 { 875, 0, },
2786 { 1000, 0, },
2787 { 1125, 0, },
2788 { 4125, 3000, },
2789 { 4125, 3000, },
2790 { 4125, 3000, },
2791 { 4125, 3000, },
2792 { 4125, 3000, },
2793 { 4125, 3000, },
2794 { 4125, 3000, },
2795 { 4125, 3000, },
2796 { 4125, 3000, },
2797 { 4125, 3000, },
2798 { 4125, 3000, },
2799 { 4125, 3000, },
2800 { 4125, 3000, },
2801 { 4125, 3000, },
2802 { 4125, 3000, },
2803 { 4125, 3000, },
2804 { 4125, 3000, },
2805 { 4125, 3000, },
2806 { 4125, 3000, },
2807 { 4125, 3000, },
2808 { 4125, 3000, },
2809 { 4125, 3000, },
2810 { 4125, 3000, },
2811 { 4125, 3000, },
2812 { 4250, 3125, },
2813 { 4375, 3250, },
2814 { 4500, 3375, },
2815 { 4625, 3500, },
2816 { 4750, 3625, },
2817 { 4875, 3750, },
2818 { 5000, 3875, },
2819 { 5125, 4000, },
2820 { 5250, 4125, },
2821 { 5375, 4250, },
2822 { 5500, 4375, },
2823 { 5625, 4500, },
2824 { 5750, 4625, },
2825 { 5875, 4750, },
2826 { 6000, 4875, },
2827 { 6125, 5000, },
2828 { 6250, 5125, },
2829 { 6375, 5250, },
2830 { 6500, 5375, },
2831 { 6625, 5500, },
2832 { 6750, 5625, },
2833 { 6875, 5750, },
2834 { 7000, 5875, },
2835 { 7125, 6000, },
2836 { 7250, 6125, },
2837 { 7375, 6250, },
2838 { 7500, 6375, },
2839 { 7625, 6500, },
2840 { 7750, 6625, },
2841 { 7875, 6750, },
2842 { 8000, 6875, },
2843 { 8125, 7000, },
2844 { 8250, 7125, },
2845 { 8375, 7250, },
2846 { 8500, 7375, },
2847 { 8625, 7500, },
2848 { 8750, 7625, },
2849 { 8875, 7750, },
2850 { 9000, 7875, },
2851 { 9125, 8000, },
2852 { 9250, 8125, },
2853 { 9375, 8250, },
2854 { 9500, 8375, },
2855 { 9625, 8500, },
2856 { 9750, 8625, },
2857 { 9875, 8750, },
2858 { 10000, 8875, },
2859 { 10125, 9000, },
2860 { 10250, 9125, },
2861 { 10375, 9250, },
2862 { 10500, 9375, },
2863 { 10625, 9500, },
2864 { 10750, 9625, },
2865 { 10875, 9750, },
2866 { 11000, 9875, },
2867 { 11125, 10000, },
2868 { 11250, 10125, },
2869 { 11375, 10250, },
2870 { 11500, 10375, },
2871 { 11625, 10500, },
2872 { 11750, 10625, },
2873 { 11875, 10750, },
2874 { 12000, 10875, },
2875 { 12125, 11000, },
2876 { 12250, 11125, },
2877 { 12375, 11250, },
2878 { 12500, 11375, },
2879 { 12625, 11500, },
2880 { 12750, 11625, },
2881 { 12875, 11750, },
2882 { 13000, 11875, },
2883 { 13125, 12000, },
2884 { 13250, 12125, },
2885 { 13375, 12250, },
2886 { 13500, 12375, },
2887 { 13625, 12500, },
2888 { 13750, 12625, },
2889 { 13875, 12750, },
2890 { 14000, 12875, },
2891 { 14125, 13000, },
2892 { 14250, 13125, },
2893 { 14375, 13250, },
2894 { 14500, 13375, },
2895 { 14625, 13500, },
2896 { 14750, 13625, },
2897 { 14875, 13750, },
2898 { 15000, 13875, },
2899 { 15125, 14000, },
2900 { 15250, 14125, },
2901 { 15375, 14250, },
2902 { 15500, 14375, },
2903 { 15625, 14500, },
2904 { 15750, 14625, },
2905 { 15875, 14750, },
2906 { 16000, 14875, },
2907 { 16125, 15000, },
2908 };
2909 if (dev_priv->info->is_mobile)
2910 return v_table[pxvid].vm;
2911 else
2912 return v_table[pxvid].vd;
2913}
2914
2915void i915_update_gfx_val(struct drm_i915_private *dev_priv)
2916{
2917 struct timespec now, diff1;
2918 u64 diff;
2919 unsigned long diffms;
2920 u32 count;
2921
2922 if (dev_priv->info->gen != 5)
2923 return;
2924
2925 getrawmonotonic(&now);
2926 diff1 = timespec_sub(now, dev_priv->last_time2);
2927
2928 /* Don't divide by 0 */
2929 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
2930 if (!diffms)
2931 return;
2932
2933 count = I915_READ(GFXEC);
2934
2935 if (count < dev_priv->last_count2) {
2936 diff = ~0UL - dev_priv->last_count2;
2937 diff += count;
2938 } else {
2939 diff = count - dev_priv->last_count2;
2940 }
2941
2942 dev_priv->last_count2 = count;
2943 dev_priv->last_time2 = now;
2944
2945 /* More magic constants... */
2946 diff = diff * 1181;
2947 diff = div_u64(diff, diffms * 10);
2948 dev_priv->gfx_power = diff;
2949}
2950
2951unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
2952{
2953 unsigned long t, corr, state1, corr2, state2;
2954 u32 pxvid, ext_v;
2955
2956 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
2957 pxvid = (pxvid >> 24) & 0x7f;
2958 ext_v = pvid_to_extvid(dev_priv, pxvid);
2959
2960 state1 = ext_v;
2961
2962 t = i915_mch_val(dev_priv);
2963
2964 /* Revel in the empirically derived constants */
2965
2966 /* Correction factor in 1/100000 units */
2967 if (t > 80)
2968 corr = ((t * 2349) + 135940);
2969 else if (t >= 50)
2970 corr = ((t * 964) + 29317);
2971 else /* < 50 */
2972 corr = ((t * 301) + 1004);
2973
2974 corr = corr * ((150142 * state1) / 10000 - 78642);
2975 corr /= 100000;
2976 corr2 = (corr * dev_priv->corr);
2977
2978 state2 = (corr2 * state1) / 10000;
2979 state2 /= 100; /* convert to mW */
2980
2981 i915_update_gfx_val(dev_priv);
2982
2983 return dev_priv->gfx_power + state2;
2984}
2985
2986/* Global for IPS driver to get at the current i915 device */
2987static struct drm_i915_private *i915_mch_dev;
2988/*
2989 * Lock protecting IPS related data structures
2990 * - i915_mch_dev
2991 * - dev_priv->max_delay
2992 * - dev_priv->min_delay
2993 * - dev_priv->fmax
2994 * - dev_priv->gpu_busy
2995 */
2996static DEFINE_SPINLOCK(mchdev_lock);
2997
2998/**
2999 * i915_read_mch_val - return value for IPS use
3000 *
3001 * Calculate and return a value for the IPS driver to use when deciding whether
3002 * we have thermal and power headroom to increase CPU or GPU power budget.
3003 */
3004unsigned long i915_read_mch_val(void)
3005{
3006 struct drm_i915_private *dev_priv;
3007 unsigned long chipset_val, graphics_val, ret = 0;
3008
3009 spin_lock(&mchdev_lock);
3010 if (!i915_mch_dev)
3011 goto out_unlock;
3012 dev_priv = i915_mch_dev;
3013
3014 chipset_val = i915_chipset_val(dev_priv);
3015 graphics_val = i915_gfx_val(dev_priv);
3016
3017 ret = chipset_val + graphics_val;
3018
3019out_unlock:
3020 spin_unlock(&mchdev_lock);
3021
3022 return ret;
3023}
3024EXPORT_SYMBOL_GPL(i915_read_mch_val);
3025
3026/**
3027 * i915_gpu_raise - raise GPU frequency limit
3028 *
3029 * Raise the limit; IPS indicates we have thermal headroom.
3030 */
3031bool i915_gpu_raise(void)
3032{
3033 struct drm_i915_private *dev_priv;
3034 bool ret = true;
3035
3036 spin_lock(&mchdev_lock);
3037 if (!i915_mch_dev) {
3038 ret = false;
3039 goto out_unlock;
3040 }
3041 dev_priv = i915_mch_dev;
3042
3043 if (dev_priv->max_delay > dev_priv->fmax)
3044 dev_priv->max_delay--;
3045
3046out_unlock:
3047 spin_unlock(&mchdev_lock);
3048
3049 return ret;
3050}
3051EXPORT_SYMBOL_GPL(i915_gpu_raise);
3052
3053/**
3054 * i915_gpu_lower - lower GPU frequency limit
3055 *
3056 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3057 * frequency maximum.
3058 */
3059bool i915_gpu_lower(void)
3060{
3061 struct drm_i915_private *dev_priv;
3062 bool ret = true;
3063
3064 spin_lock(&mchdev_lock);
3065 if (!i915_mch_dev) {
3066 ret = false;
3067 goto out_unlock;
3068 }
3069 dev_priv = i915_mch_dev;
3070
3071 if (dev_priv->max_delay < dev_priv->min_delay)
3072 dev_priv->max_delay++;
3073
3074out_unlock:
3075 spin_unlock(&mchdev_lock);
3076
3077 return ret;
3078}
3079EXPORT_SYMBOL_GPL(i915_gpu_lower);
3080
3081/**
3082 * i915_gpu_busy - indicate GPU business to IPS
3083 *
3084 * Tell the IPS driver whether or not the GPU is busy.
3085 */
3086bool i915_gpu_busy(void)
3087{
3088 struct drm_i915_private *dev_priv;
3089 bool ret = false;
3090
3091 spin_lock(&mchdev_lock);
3092 if (!i915_mch_dev)
3093 goto out_unlock;
3094 dev_priv = i915_mch_dev;
3095
3096 ret = dev_priv->busy;
3097
3098out_unlock:
3099 spin_unlock(&mchdev_lock);
3100
3101 return ret;
3102}
3103EXPORT_SYMBOL_GPL(i915_gpu_busy);
3104
3105/**
3106 * i915_gpu_turbo_disable - disable graphics turbo
3107 *
3108 * Disable graphics turbo by resetting the max frequency and setting the
3109 * current frequency to the default.
3110 */
3111bool i915_gpu_turbo_disable(void)
3112{
3113 struct drm_i915_private *dev_priv;
3114 bool ret = true;
3115
3116 spin_lock(&mchdev_lock);
3117 if (!i915_mch_dev) {
3118 ret = false;
3119 goto out_unlock;
3120 }
3121 dev_priv = i915_mch_dev;
3122
3123 dev_priv->max_delay = dev_priv->fstart;
3124
3125 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
3126 ret = false;
3127
3128out_unlock:
3129 spin_unlock(&mchdev_lock);
3130
3131 return ret;
3132}
3133EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3134
3135/**
3136 * Tells the intel_ips driver that the i915 driver is now loaded, if
3137 * IPS got loaded first.
3138 *
3139 * This awkward dance is so that neither module has to depend on the
3140 * other in order for IPS to do the appropriate communication of
3141 * GPU turbo limits to i915.
3142 */
3143static void
3144ips_ping_for_i915_load(void)
3145{
3146 void (*link)(void);
3147
3148 link = symbol_get(ips_link_to_i915_driver);
3149 if (link) {
3150 link();
3151 symbol_put(ips_link_to_i915_driver);
3152 }
3153}
3154
3155void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3156{
3157 spin_lock(&mchdev_lock);
3158 i915_mch_dev = dev_priv;
3159 dev_priv->mchdev_lock = &mchdev_lock;
3160 spin_unlock(&mchdev_lock);
3161
3162 ips_ping_for_i915_load();
3163}
3164
3165void intel_gpu_ips_teardown(void)
3166{
3167 spin_lock(&mchdev_lock);
3168 i915_mch_dev = NULL;
3169 spin_unlock(&mchdev_lock);
3170}
8090c6b9 3171static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3172{
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 u32 lcfuse;
3175 u8 pxw[16];
3176 int i;
3177
3178 /* Disable to program */
3179 I915_WRITE(ECR, 0);
3180 POSTING_READ(ECR);
3181
3182 /* Program energy weights for various events */
3183 I915_WRITE(SDEW, 0x15040d00);
3184 I915_WRITE(CSIEW0, 0x007f0000);
3185 I915_WRITE(CSIEW1, 0x1e220004);
3186 I915_WRITE(CSIEW2, 0x04000004);
3187
3188 for (i = 0; i < 5; i++)
3189 I915_WRITE(PEW + (i * 4), 0);
3190 for (i = 0; i < 3; i++)
3191 I915_WRITE(DEW + (i * 4), 0);
3192
3193 /* Program P-state weights to account for frequency power adjustment */
3194 for (i = 0; i < 16; i++) {
3195 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3196 unsigned long freq = intel_pxfreq(pxvidfreq);
3197 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3198 PXVFREQ_PX_SHIFT;
3199 unsigned long val;
3200
3201 val = vid * vid;
3202 val *= (freq / 1000);
3203 val *= 255;
3204 val /= (127*127*900);
3205 if (val > 0xff)
3206 DRM_ERROR("bad pxval: %ld\n", val);
3207 pxw[i] = val;
3208 }
3209 /* Render standby states get 0 weight */
3210 pxw[14] = 0;
3211 pxw[15] = 0;
3212
3213 for (i = 0; i < 4; i++) {
3214 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3215 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3216 I915_WRITE(PXW + (i * 4), val);
3217 }
3218
3219 /* Adjust magic regs to magic values (more experimental results) */
3220 I915_WRITE(OGW0, 0);
3221 I915_WRITE(OGW1, 0);
3222 I915_WRITE(EG0, 0x00007f00);
3223 I915_WRITE(EG1, 0x0000000e);
3224 I915_WRITE(EG2, 0x000e0000);
3225 I915_WRITE(EG3, 0x68000300);
3226 I915_WRITE(EG4, 0x42000000);
3227 I915_WRITE(EG5, 0x00140031);
3228 I915_WRITE(EG6, 0);
3229 I915_WRITE(EG7, 0);
3230
3231 for (i = 0; i < 8; i++)
3232 I915_WRITE(PXWL + (i * 4), 0);
3233
3234 /* Enable PMON + select events */
3235 I915_WRITE(ECR, 0x80000019);
3236
3237 lcfuse = I915_READ(LCFUSE02);
3238
3239 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
3240}
3241
8090c6b9
DV		 3242void intel_disable_gt_powersave(struct drm_device *dev)
3243{
3244 if (IS_IRONLAKE_M(dev))
3245 ironlake_disable_drps(dev);
7cf50fc8 3246 else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
8090c6b9
DV		 3247 gen6_disable_rps(dev);
3248}
3249
3250void intel_enable_gt_powersave(struct drm_device *dev)
3251{
8090c6b9
DV		 3252 if (IS_IRONLAKE_M(dev)) {
3253 ironlake_enable_drps(dev);
3254 ironlake_enable_rc6(dev);
3255 intel_init_emon(dev);
7cf50fc8 3256 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
79f5b2c7
DV		 3257 gen6_enable_rps(dev);
3258 gen6_update_ring_freq(dev);
8090c6b9
DV		 3259 }
3260}
3261
1fa61106 3262static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3263{
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3266
3267 /* Required for FBC */
3268 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
3269 DPFCRUNIT_CLOCK_GATE_DISABLE |
3270 DPFDUNIT_CLOCK_GATE_DISABLE;
3271 /* Required for CxSR */
3272 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
3273
3274 I915_WRITE(PCH_3DCGDIS0,
3275 MARIUNIT_CLOCK_GATE_DISABLE |
3276 SVSMUNIT_CLOCK_GATE_DISABLE);
3277 I915_WRITE(PCH_3DCGDIS1,
3278 VFMUNIT_CLOCK_GATE_DISABLE);
3279
3280 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3281
3282 /*
3283 * According to the spec the following bits should be set in
3284 * order to enable memory self-refresh
3285 * The bit 22/21 of 0x42004
3286 * The bit 5 of 0x42020
3287 * The bit 15 of 0x45000
3288 */
3289 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3290 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3291 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3292 I915_WRITE(ILK_DSPCLK_GATE,
3293 (I915_READ(ILK_DSPCLK_GATE) |
3294 ILK_DPARB_CLK_GATE));
3295 I915_WRITE(DISP_ARB_CTL,
3296 (I915_READ(DISP_ARB_CTL) |
3297 DISP_FBC_WM_DIS));
3298 I915_WRITE(WM3_LP_ILK, 0);
3299 I915_WRITE(WM2_LP_ILK, 0);
3300 I915_WRITE(WM1_LP_ILK, 0);
3301
3302 /*
3303 * Based on the document from hardware guys the following bits
3304 * should be set unconditionally in order to enable FBC.
3305 * The bit 22 of 0x42000
3306 * The bit 22 of 0x42004
3307 * The bit 7,8,9 of 0x42020.
3308 */
3309 if (IS_IRONLAKE_M(dev)) {
3310 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3311 I915_READ(ILK_DISPLAY_CHICKEN1) |
3312 ILK_FBCQ_DIS);
3313 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3314 I915_READ(ILK_DISPLAY_CHICKEN2) |
3315 ILK_DPARB_GATE);
3316 I915_WRITE(ILK_DSPCLK_GATE,
3317 I915_READ(ILK_DSPCLK_GATE) |
3318 ILK_DPFC_DIS1 |
3319 ILK_DPFC_DIS2 |
3320 ILK_CLK_FBC);
3321 }
3322
3323 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3324 I915_READ(ILK_DISPLAY_CHICKEN2) |
3325 ILK_ELPIN_409_SELECT);
3326 I915_WRITE(_3D_CHICKEN2,
3327 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3328 _3D_CHICKEN2_WM_READ_PIPELINED);
3329}
3330
1fa61106 3331static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3332{
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 int pipe;
3335 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3336
3337 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3338
3339 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3340 I915_READ(ILK_DISPLAY_CHICKEN2) |
3341 ILK_ELPIN_409_SELECT);
3342
3343 I915_WRITE(WM3_LP_ILK, 0);
3344 I915_WRITE(WM2_LP_ILK, 0);
3345 I915_WRITE(WM1_LP_ILK, 0);
3346
6f1d69b0 3347 I915_WRITE(CACHE_MODE_0,
50743298 3348 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3349
3350 I915_WRITE(GEN6_UCGCTL1,
3351 I915_READ(GEN6_UCGCTL1) |
3352 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3353 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3354
3355 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3356 * gating disable must be set. Failure to set it results in
3357 * flickering pixels due to Z write ordering failures after
3358 * some amount of runtime in the Mesa "fire" demo, and Unigine
3359 * Sanctuary and Tropics, and apparently anything else with
3360 * alpha test or pixel discard.
3361 *
3362 * According to the spec, bit 11 (RCCUNIT) must also be set,
3363 * but we didn't debug actual testcases to find it out.
0f846f81
JB		 3364 *
3365 * Also apply WaDisableVDSUnitClockGating and
3366 * WaDisableRCPBUnitClockGating.
6f1d69b0
ED		 3367 */
3368 I915_WRITE(GEN6_UCGCTL2,
0f846f81 3369 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 3370 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3371 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3372
3373 /* Bspec says we need to always set all mask bits. */
3374 I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
3375 _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
3376
3377 /*
3378 * According to the spec the following bits should be
3379 * set in order to enable memory self-refresh and fbc:
3380 * The bit21 and bit22 of 0x42000
3381 * The bit21 and bit22 of 0x42004
3382 * The bit5 and bit7 of 0x42020
3383 * The bit14 of 0x70180
3384 * The bit14 of 0x71180
3385 */
3386 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3387 I915_READ(ILK_DISPLAY_CHICKEN1) |
3388 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3389 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3390 I915_READ(ILK_DISPLAY_CHICKEN2) |
3391 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3392 I915_WRITE(ILK_DSPCLK_GATE,
3393 I915_READ(ILK_DSPCLK_GATE) |
3394 ILK_DPARB_CLK_GATE |
3395 ILK_DPFD_CLK_GATE);
3396
b4ae3f22
JB		 3397 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3398 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3399
6f1d69b0
ED		 3400 for_each_pipe(pipe) {
3401 I915_WRITE(DSPCNTR(pipe),
3402 I915_READ(DSPCNTR(pipe)) |
3403 DISPPLANE_TRICKLE_FEED_DISABLE);
3404 intel_flush_display_plane(dev_priv, pipe);
3405 }
3406}
3407
3408static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3409{
3410 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3411
3412 reg &= ~GEN7_FF_SCHED_MASK;
3413 reg |= GEN7_FF_TS_SCHED_HW;
3414 reg |= GEN7_FF_VS_SCHED_HW;
3415 reg |= GEN7_FF_DS_SCHED_HW;
3416
3417 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3418}
3419
cad2a2d7
ED		 3420static void haswell_init_clock_gating(struct drm_device *dev)
3421{
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 int pipe;
3424 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3425
3426 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3427
3428 I915_WRITE(WM3_LP_ILK, 0);
3429 I915_WRITE(WM2_LP_ILK, 0);
3430 I915_WRITE(WM1_LP_ILK, 0);
3431
3432 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3433 * This implements the WaDisableRCZUnitClockGating workaround.
3434 */
3435 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3436
3437 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3438
3439 I915_WRITE(IVB_CHICKEN3,
3440 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3441 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3442
3443 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3444 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3445 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3446
3447 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3448 I915_WRITE(GEN7_L3CNTLREG1,
3449 GEN7_WA_FOR_GEN7_L3_CONTROL);
3450 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3451 GEN7_WA_L3_CHICKEN_MODE);
3452
3453 /* This is required by WaCatErrorRejectionIssue */
3454 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3455 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3456 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3457
3458 for_each_pipe(pipe) {
3459 I915_WRITE(DSPCNTR(pipe),
3460 I915_READ(DSPCNTR(pipe)) |
3461 DISPPLANE_TRICKLE_FEED_DISABLE);
3462 intel_flush_display_plane(dev_priv, pipe);
3463 }
3464
3465 gen7_setup_fixed_func_scheduler(dev_priv);
3466
3467 /* WaDisable4x2SubspanOptimization */
3468 I915_WRITE(CACHE_MODE_1,
3469 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3470}
3471
1fa61106 3472static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3473{
3474 struct drm_i915_private *dev_priv = dev->dev_private;
3475 int pipe;
3476 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
20848223 3477 uint32_t snpcr;
6f1d69b0
ED		 3478
3479 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3480
3481 I915_WRITE(WM3_LP_ILK, 0);
3482 I915_WRITE(WM2_LP_ILK, 0);
3483 I915_WRITE(WM1_LP_ILK, 0);
3484
6f1d69b0
ED		 3485 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3486
3487 I915_WRITE(IVB_CHICKEN3,
3488 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3489 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3490
3491 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3492 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3493 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3494
3495 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3496 I915_WRITE(GEN7_L3CNTLREG1,
3497 GEN7_WA_FOR_GEN7_L3_CONTROL);
3498 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3499 GEN7_WA_L3_CHICKEN_MODE);
3500
0f846f81
JB		 3501 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3502 * gating disable must be set. Failure to set it results in
3503 * flickering pixels due to Z write ordering failures after
3504 * some amount of runtime in the Mesa "fire" demo, and Unigine
3505 * Sanctuary and Tropics, and apparently anything else with
3506 * alpha test or pixel discard.
3507 *
3508 * According to the spec, bit 11 (RCCUNIT) must also be set,
3509 * but we didn't debug actual testcases to find it out.
3510 *
3511 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3512 * This implements the WaDisableRCZUnitClockGating workaround.
3513 */
3514 I915_WRITE(GEN6_UCGCTL2,
3515 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3516 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3517
6f1d69b0
ED		 3518 /* This is required by WaCatErrorRejectionIssue */
3519 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3520 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3521 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3522
3523 for_each_pipe(pipe) {
3524 I915_WRITE(DSPCNTR(pipe),
3525 I915_READ(DSPCNTR(pipe)) |
3526 DISPPLANE_TRICKLE_FEED_DISABLE);
3527 intel_flush_display_plane(dev_priv, pipe);
3528 }
3529
b4ae3f22
JB		 3530 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3531 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3532
6f1d69b0 3533 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f
DV		 3534
3535 /* WaDisable4x2SubspanOptimization */
3536 I915_WRITE(CACHE_MODE_1,
3537 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 3538
3539 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3540 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3541 snpcr |= GEN6_MBC_SNPCR_MED;
3542 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6f1d69b0
ED		 3543}
3544
1fa61106 3545static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3546{
3547 struct drm_i915_private *dev_priv = dev->dev_private;
3548 int pipe;
3549 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
3550
3551 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
3552
3553 I915_WRITE(WM3_LP_ILK, 0);
3554 I915_WRITE(WM2_LP_ILK, 0);
3555 I915_WRITE(WM1_LP_ILK, 0);
3556
6f1d69b0
ED		 3557 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
3558
3559 I915_WRITE(IVB_CHICKEN3,
3560 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3561 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3562
3563 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3564 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3565 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3566
3567 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3568 I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL);
3569 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3570
3571 /* This is required by WaCatErrorRejectionIssue */
3572 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3573 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3574 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3575
b4ae3f22
JB		 3576 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3577 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3578
0f846f81
JB		 3579
3580 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3581 * gating disable must be set. Failure to set it results in
3582 * flickering pixels due to Z write ordering failures after
3583 * some amount of runtime in the Mesa "fire" demo, and Unigine
3584 * Sanctuary and Tropics, and apparently anything else with
3585 * alpha test or pixel discard.
3586 *
3587 * According to the spec, bit 11 (RCCUNIT) must also be set,
3588 * but we didn't debug actual testcases to find it out.
3589 *
3590 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3591 * This implements the WaDisableRCZUnitClockGating workaround.
3592 *
3593 * Also apply WaDisableVDSUnitClockGating and
3594 * WaDisableRCPBUnitClockGating.
3595 */
3596 I915_WRITE(GEN6_UCGCTL2,
3597 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 3598 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 3599 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3600 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3601 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3602
e3f33d46
JB		 3603 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3604
6f1d69b0
ED		 3605 for_each_pipe(pipe) {
3606 I915_WRITE(DSPCNTR(pipe),
3607 I915_READ(DSPCNTR(pipe)) |
3608 DISPPLANE_TRICKLE_FEED_DISABLE);
3609 intel_flush_display_plane(dev_priv, pipe);
3610 }
3611
6b26c86d
DV		 3612 I915_WRITE(CACHE_MODE_1,
3613 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f
JB		 3614
3615 /*
3616 * On ValleyView, the GUnit needs to signal the GT
3617 * when flip and other events complete. So enable
3618 * all the GUnit->GT interrupts here
3619 */
3620 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3621 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3622 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3623 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3624 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3625 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3626 PLANEA_FLIPDONE_INT_EN);
6f1d69b0
ED		 3627}
3628
1fa61106 3629static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3630{
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 uint32_t dspclk_gate;
3633
3634 I915_WRITE(RENCLK_GATE_D1, 0);
3635 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3636 GS_UNIT_CLOCK_GATE_DISABLE |
3637 CL_UNIT_CLOCK_GATE_DISABLE);
3638 I915_WRITE(RAMCLK_GATE_D, 0);
3639 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3640 OVRUNIT_CLOCK_GATE_DISABLE |
3641 OVCUNIT_CLOCK_GATE_DISABLE;
3642 if (IS_GM45(dev))
3643 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3644 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
3645}
3646
1fa61106 3647static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3648{
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650
3651 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3652 I915_WRITE(RENCLK_GATE_D2, 0);
3653 I915_WRITE(DSPCLK_GATE_D, 0);
3654 I915_WRITE(RAMCLK_GATE_D, 0);
3655 I915_WRITE16(DEUC, 0);
3656}
3657
1fa61106 3658static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3659{
3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661
3662 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3663 I965_RCC_CLOCK_GATE_DISABLE |
3664 I965_RCPB_CLOCK_GATE_DISABLE |
3665 I965_ISC_CLOCK_GATE_DISABLE |
3666 I965_FBC_CLOCK_GATE_DISABLE);
3667 I915_WRITE(RENCLK_GATE_D2, 0);
3668}
3669
1fa61106 3670static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3671{
3672 struct drm_i915_private *dev_priv = dev->dev_private;
3673 u32 dstate = I915_READ(D_STATE);
3674
3675 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3676 DSTATE_DOT_CLOCK_GATING;
3677 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 3678
3679 if (IS_PINEVIEW(dev))
3680 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6f1d69b0
ED		 3681}
3682
1fa61106 3683static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3684{
3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686
3687 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3688}
3689
1fa61106 3690static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3691{
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693
3694 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3695}
3696
1fa61106 3697static void ibx_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3698{
3699 struct drm_i915_private *dev_priv = dev->dev_private;
3700
3701 /*
3702 * On Ibex Peak and Cougar Point, we need to disable clock
3703 * gating for the panel power sequencer or it will fail to
3704 * start up when no ports are active.
3705 */
3706 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3707}
3708
1fa61106 3709static void cpt_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3710{
3711 struct drm_i915_private *dev_priv = dev->dev_private;
3712 int pipe;
3713
3714 /*
3715 * On Ibex Peak and Cougar Point, we need to disable clock
3716 * gating for the panel power sequencer or it will fail to
3717 * start up when no ports are active.
3718 */
3719 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3720 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3721 DPLS_EDP_PPS_FIX_DIS);
3722 /* Without this, mode sets may fail silently on FDI */
3723 for_each_pipe(pipe)
3724 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
3725}
3726
3727void intel_init_clock_gating(struct drm_device *dev)
3728{
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730
3731 dev_priv->display.init_clock_gating(dev);
3732
3733 if (dev_priv->display.init_pch_clock_gating)
3734 dev_priv->display.init_pch_clock_gating(dev);
3735}
3736
9104183d
CW		 3737static void gen6_sanitize_pm(struct drm_device *dev)
3738{
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 u32 limits, delay, old;
3741
3742 gen6_gt_force_wake_get(dev_priv);
3743
3744 old = limits = I915_READ(GEN6_RP_INTERRUPT_LIMITS);
3745 /* Make sure we continue to get interrupts
3746 * until we hit the minimum or maximum frequencies.
3747 */
3748 limits &= ~(0x3f << 16 | 0x3f << 24);
3749 delay = dev_priv->cur_delay;
3750 if (delay < dev_priv->max_delay)
3751 limits |= (dev_priv->max_delay & 0x3f) << 24;
3752 if (delay > dev_priv->min_delay)
3753 limits |= (dev_priv->min_delay & 0x3f) << 16;
3754
3755 if (old != limits) {
ef12dab7
DV		 3756 /* Note that the known failure case is to read back 0. */
3757 DRM_DEBUG_DRIVER("Power management discrepancy: GEN6_RP_INTERRUPT_LIMITS "
3758 "expected %08x, was %08x\n", limits, old);
9104183d
CW		 3759 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3760 }
3761
3762 gen6_gt_force_wake_put(dev_priv);
3763}
3764
3765void intel_sanitize_pm(struct drm_device *dev)
3766{
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768
3769 if (dev_priv->display.sanitize_pm)
3770 dev_priv->display.sanitize_pm(dev);
3771}
3772
d0d3e513
ED		 3773/* Starting with Haswell, we have different power wells for
3774 * different parts of the GPU. This attempts to enable them all.
3775 */
3776void intel_init_power_wells(struct drm_device *dev)
3777{
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779 unsigned long power_wells[] = {
3780 HSW_PWR_WELL_CTL1,
3781 HSW_PWR_WELL_CTL2,
3782 HSW_PWR_WELL_CTL4
3783 };
3784 int i;
3785
3786 if (!IS_HASWELL(dev))
3787 return;
3788
3789 mutex_lock(&dev->struct_mutex);
3790
3791 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
3792 int well = I915_READ(power_wells[i]);
3793
3794 if ((well & HSW_PWR_WELL_STATE) == 0) {
3795 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
3796 if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
3797 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
3798 }
3799 }
3800
3801 mutex_unlock(&dev->struct_mutex);
3802}
3803
1fa61106
ED		 3804/* Set up chip specific power management-related functions */
3805void intel_init_pm(struct drm_device *dev)
3806{
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808
3809 if (I915_HAS_FBC(dev)) {
3810 if (HAS_PCH_SPLIT(dev)) {
3811 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
3812 dev_priv->display.enable_fbc = ironlake_enable_fbc;
3813 dev_priv->display.disable_fbc = ironlake_disable_fbc;
3814 } else if (IS_GM45(dev)) {
3815 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
3816 dev_priv->display.enable_fbc = g4x_enable_fbc;
3817 dev_priv->display.disable_fbc = g4x_disable_fbc;
3818 } else if (IS_CRESTLINE(dev)) {
3819 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
3820 dev_priv->display.enable_fbc = i8xx_enable_fbc;
3821 dev_priv->display.disable_fbc = i8xx_disable_fbc;
3822 }
3823 /* 855GM needs testing */
3824 }
3825
c921aba8
DV		 3826 /* For cxsr */
3827 if (IS_PINEVIEW(dev))
3828 i915_pineview_get_mem_freq(dev);
3829 else if (IS_GEN5(dev))
3830 i915_ironlake_get_mem_freq(dev);
3831
1fa61106
ED		 3832 /* For FIFO watermark updates */
3833 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 3834 if (HAS_PCH_IBX(dev))
3835 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
3836 else if (HAS_PCH_CPT(dev))
3837 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
3838
3839 if (IS_GEN5(dev)) {
3840 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
3841 dev_priv->display.update_wm = ironlake_update_wm;
3842 else {
3843 DRM_DEBUG_KMS("Failed to get proper latency. "
3844 "Disable CxSR\n");
3845 dev_priv->display.update_wm = NULL;
3846 }
3847 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
3848 } else if (IS_GEN6(dev)) {
3849 if (SNB_READ_WM0_LATENCY()) {
3850 dev_priv->display.update_wm = sandybridge_update_wm;
3851 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3852 } else {
3853 DRM_DEBUG_KMS("Failed to read display plane latency. "
3854 "Disable CxSR\n");
3855 dev_priv->display.update_wm = NULL;
3856 }
3857 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
9104183d 3858 dev_priv->display.sanitize_pm = gen6_sanitize_pm;
1fa61106
ED		 3859 } else if (IS_IVYBRIDGE(dev)) {
3860 /* FIXME: detect B0+ stepping and use auto training */
3861 if (SNB_READ_WM0_LATENCY()) {
3862 dev_priv->display.update_wm = sandybridge_update_wm;
3863 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3864 } else {
3865 DRM_DEBUG_KMS("Failed to read display plane latency. "
3866 "Disable CxSR\n");
3867 dev_priv->display.update_wm = NULL;
3868 }
3869 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
9104183d 3870 dev_priv->display.sanitize_pm = gen6_sanitize_pm;
6b8a5eeb
ED		 3871 } else if (IS_HASWELL(dev)) {
3872 if (SNB_READ_WM0_LATENCY()) {
3873 dev_priv->display.update_wm = sandybridge_update_wm;
3874 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 3875 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 3876 } else {
3877 DRM_DEBUG_KMS("Failed to read display plane latency. "
3878 "Disable CxSR\n");
3879 dev_priv->display.update_wm = NULL;
3880 }
cad2a2d7 3881 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6b8a5eeb 3882 dev_priv->display.sanitize_pm = gen6_sanitize_pm;
1fa61106
ED		 3883 } else
3884 dev_priv->display.update_wm = NULL;
3885 } else if (IS_VALLEYVIEW(dev)) {
3886 dev_priv->display.update_wm = valleyview_update_wm;
3887 dev_priv->display.init_clock_gating =
3888 valleyview_init_clock_gating;
1fa61106
ED		 3889 } else if (IS_PINEVIEW(dev)) {
3890 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
3891 dev_priv->is_ddr3,
3892 dev_priv->fsb_freq,
3893 dev_priv->mem_freq)) {
3894 DRM_INFO("failed to find known CxSR latency "
3895 "(found ddr%s fsb freq %d, mem freq %d), "
3896 "disabling CxSR\n",
3897 (dev_priv->is_ddr3 == 1) ? "3" : "2",
3898 dev_priv->fsb_freq, dev_priv->mem_freq);
3899 /* Disable CxSR and never update its watermark again */
3900 pineview_disable_cxsr(dev);
3901 dev_priv->display.update_wm = NULL;
3902 } else
3903 dev_priv->display.update_wm = pineview_update_wm;
3904 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
3905 } else if (IS_G4X(dev)) {
3906 dev_priv->display.update_wm = g4x_update_wm;
3907 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
3908 } else if (IS_GEN4(dev)) {
3909 dev_priv->display.update_wm = i965_update_wm;
3910 if (IS_CRESTLINE(dev))
3911 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
3912 else if (IS_BROADWATER(dev))
3913 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
3914 } else if (IS_GEN3(dev)) {
3915 dev_priv->display.update_wm = i9xx_update_wm;
3916 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
3917 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
3918 } else if (IS_I865G(dev)) {
3919 dev_priv->display.update_wm = i830_update_wm;
3920 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
3921 dev_priv->display.get_fifo_size = i830_get_fifo_size;
3922 } else if (IS_I85X(dev)) {
3923 dev_priv->display.update_wm = i9xx_update_wm;
3924 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
3925 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
3926 } else {
3927 dev_priv->display.update_wm = i830_update_wm;
3928 dev_priv->display.init_clock_gating = i830_init_clock_gating;
3929 if (IS_845G(dev))
3930 dev_priv->display.get_fifo_size = i845_get_fifo_size;
3931 else
3932 dev_priv->display.get_fifo_size = i830_get_fifo_size;
3933 }
d0d3e513
ED		 3934
3935 /* We attempt to init the necessary power wells early in the initialization
3936 * time, so the subsystems that expect power to be enabled can work.
3937 */
3938 intel_init_power_wells(dev);
1fa61106
ED		 3939}
3940
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