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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
63c62275 255static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 256 int is_ddr3,
257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4 342 } else if (IS_I915GM(dev)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 655 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
7c5f93b0 661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 663 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
ac484963 668 cpp, latency->display_sr);
b445e3b0
ED		 669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
ac484963 678 cpp, latency->cursor_sr);
b445e3b0
ED		 679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
ac484963 687 cpp, latency->display_hpll_disable);
b445e3b0
ED		 688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
ac484963 696 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
ac484963 720 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
ac484963 738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
778 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
ac484963 806 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 826 line_size = hdisplay * cpp;
b445e3b0
ED		 827
828 /* Use the minimum of the small and large buffer method for primary */
ac484963 829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
ac484963 836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
2cb389b7
VS		 907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
ae80152d 913 POSTING_READ(DSPFW1);
0018fda1
VS		 914}
915
15665979
VS		 916#undef FW_WM_VLV
917
6eb1a681
VS		 918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 922};
923
262cd2e1
VS		 924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
ac484963 928 unsigned int cpp,
262cd2e1
VS		 929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 934 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
fac5e23e 942 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
58590c14
VS		 947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
262cd2e1
VS		 949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 963 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
936e71e3 968 if (!state->base.visible)
262cd2e1
VS		 969 return 0;
970
ac484963 971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
ac484963 987 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
54f1b6e1
VS		 994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
936e71e3 1010 if (state->base.visible) {
54f1b6e1
VS		 1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
936e71e3 1026 if (!state->base.visible) {
54f1b6e1
VS		 1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
262cd2e1
VS		 1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
26e1fe4f 1095static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
852eb00d 1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1107
1108 wm_state->num_active_planes = 0;
262cd2e1 1109
54f1b6e1 1110 vlv_compute_fifo(crtc);
262cd2e1
VS		 1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
936e71e3 1126 if (!state->base.visible)
262cd2e1
VS		 1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
5a37ed0a 1167 wm_state->wm[level].cursor;
262cd2e1
VS		 1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
58590c14 1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
54f1b6e1
VS		 1194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
262cd2e1
VS		 1284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
58590c14 1290 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
6f9c784b
VS		 1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
262cd2e1
VS		 1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
fac5e23e 1333 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
26e1fe4f 1338 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1339 vlv_merge_wm(dev, &wm);
1340
54f1b6e1
VS		 1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1344 return;
54f1b6e1 1345 }
262cd2e1
VS		 1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
852eb00d 1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1356 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1357
54f1b6e1
VS		 1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
262cd2e1
VS		 1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
852eb00d 1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1370 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1381}
1382
ae80152d
VS		 1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
46ba614c 1385static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1386{
46ba614c 1387 struct drm_device *dev = crtc->dev;
b445e3b0 1388 static const int sr_latency_ns = 12000;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
9858425c 1393 bool cxsr_enabled;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planea_wm, &cursora_wm))
51cea1f4 1399 enabled |= 1 << PIPE_A;
b445e3b0 1400
51cea1f4 1401 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1404 &planeb_wm, &cursorb_wm))
51cea1f4 1405 enabled |= 1 << PIPE_B;
b445e3b0 1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
9858425c 1413 cxsr_enabled = true;
52bd02d8 1414 } else {
9858425c 1415 cxsr_enabled = false;
5209b1f4 1416 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0 1419
a5043453
VS		 1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
f4998963
VS		 1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
b445e3b0 1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1433 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
8c919b28 1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1437 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1441}
1442
46ba614c 1443static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1444{
46ba614c 1445 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
9858425c 1450 bool cxsr_enabled;
b445e3b0
ED		 1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
124abe07 1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1458 int clock = adjusted_mode->crtc_clock;
fec8cba3 1459 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1462 unsigned long line_time_us;
1463 int entries;
1464
922044c9 1465 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1469 cpp * hdisplay;
b445e3b0
ED		 1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
9858425c 1491 cxsr_enabled = true;
b445e3b0 1492 } else {
9858425c 1493 cxsr_enabled = false;
b445e3b0 1494 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1495 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
f4998963
VS		 1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
b445e3b0 1508 /* update cursor SR watermark */
f4998963 1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1513}
1514
f4998963
VS		 1515#undef FW_WM
1516
46ba614c 1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1518{
46ba614c 1519 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1520 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
9d539105 1534 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
ac484963 1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
6e3c9717 1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
5aef6003 1547 pessimal_latency_ns);
b445e3b0 1548 enabled = crtc;
9d539105 1549 } else {
b445e3b0 1550 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
ac484963 1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
6e3c9717 1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
5aef6003 1569 pessimal_latency_ns);
b445e3b0
ED		 1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
9d539105 1574 } else {
b445e3b0 1575 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
b445e3b0
ED		 1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
2ab1bc9d 1582 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1583 struct drm_i915_gem_object *obj;
2ab1bc9d 1584
59bea882 1585 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1586
1587 /* self-refresh seems busted with untiled */
3e510a8e 1588 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1589 enabled = NULL;
1590 }
1591
b445e3b0
ED		 1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1598 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
124abe07 1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1605 int clock = adjusted_mode->crtc_clock;
fec8cba3 1606 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1609 unsigned long line_time_us;
1610 int entries;
1611
2d1b5056
VS		 1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1619 cpp * hdisplay;
b445e3b0
ED		 1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1629 else
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
5209b1f4
ID		 1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1648}
1649
feb56b93 1650static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1651{
46ba614c 1652 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1654 struct drm_crtc *crtc;
241bfc38 1655 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
6e3c9717 1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1665 &i845_wm_info,
b445e3b0 1666 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1667 4, pessimal_latency_ns);
b445e3b0
ED		 1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
8cfb3407 1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1677{
fd4daa9c 1678 uint32_t pixel_rate;
801bcfff 1679
8cfb3407 1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
8cfb3407 1685 if (pipe_config->pch_pfit.enabled) {
801bcfff 1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
801bcfff 1691
801bcfff
PZ		 1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
15126882
MR		 1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
801bcfff
PZ		 1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
37126462 1709/* latency must be in 0.1us units. */
ac484963 1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1711{
1712 uint64_t ret;
1713
3312ba65
VS		 1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
ac484963 1717 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
37126462 1723/* latency must be in 0.1us units. */
23297044 1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1725 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
3312ba65
VS		 1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
15126882
MR		 1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
3312ba65 1734
801bcfff 1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1736 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
23297044 1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1742 uint8_t cpp)
cca32e9a 1743{
15126882
MR		 1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
ac484963 1750 if (WARN_ON(!cpp))
15126882
MR		 1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
ac484963 1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1756}
1757
820c1980 1758struct ilk_wm_maximums {
cca32e9a
PZ		 1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
37126462
VS		 1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
7221fc33 1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1770 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1771 uint32_t mem_value,
1772 bool is_lp)
801bcfff 1773{
ac484963
VS		 1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1776 uint32_t method1, method2;
1777
936e71e3 1778 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1779 return 0;
1780
ac484963 1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1782
1783 if (!is_lp)
1784 return method1;
1785
7221fc33
MR		 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1788 drm_rect_width(&pstate->base.dst),
ac484963 1789 cpp, mem_value);
cca32e9a
PZ		 1790
1791 return min(method1, method2);
801bcfff
PZ		 1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1804 uint32_t method1, method2;
1805
936e71e3 1806 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1807 return 0;
1808
ac484963 1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1812 drm_rect_width(&pstate->base.dst),
ac484963 1813 cpp, mem_value);
801bcfff
PZ		 1814 return min(method1, method2);
1815}
1816
37126462
VS		 1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
7221fc33 1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1822 const struct intel_plane_state *pstate,
801bcfff
PZ		 1823 uint32_t mem_value)
1824{
b2435692
MR		 1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
936e71e3 1831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1832
b2435692 1833 if (!cstate->base.active)
801bcfff
PZ		 1834 return 0;
1835
7221fc33
MR		 1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1838 width, cpp, mem_value);
801bcfff
PZ		 1839}
1840
cca32e9a 1841/* Only for WM_LP. */
7221fc33 1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1843 const struct intel_plane_state *pstate,
1fda9882 1844 uint32_t pri_val)
cca32e9a 1845{
ac484963
VS		 1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1848
936e71e3 1849 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1850 return 0;
1851
936e71e3 1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1853}
1854
158ae64f
VS		 1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
416f4727
VS		 1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1860 return 768;
1861 else
1862 return 512;
1863}
1864
4e975081
VS		 1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
158ae64f
VS		 1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
240264f4 1902 const struct intel_wm_config *config,
158ae64f
VS		 1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1907
1908 /* if sprites aren't enabled, sprites get nothing */
240264f4 1909 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1913 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
240264f4 1925 if (config->sprites_enabled) {
158ae64f
VS		 1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
4e975081 1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1942 int level,
1943 const struct intel_wm_config *config)
158ae64f
VS		 1944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1946 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
4e975081 1950 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1951}
1952
d34ff9c6 1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1957 struct ilk_wm_maximums *max)
158ae64f 1958{
240264f4
VS		 1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1962 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1963}
1964
a3cb4048
VS		 1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
d9395655 1975static bool ilk_validate_wm_level(int level,
820c1980 1976 const struct ilk_wm_maximums *max,
d9395655 1977 struct intel_wm_level *result)
a9786a11
VS		 1978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
a9786a11
VS		 2013 return ret;
2014}
2015
d34ff9c6 2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2017 const struct intel_crtc *intel_crtc,
6f5ddd17 2018 int level,
7221fc33 2019 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
e3bddded
ML		 2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
6f5ddd17
VS		 2048 result->enable = true;
2049}
2050
801bcfff 2051static uint32_t
532f7a7f 2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2053{
532f7a7f
VS		 2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
85a02deb 2058 u32 linetime, ips_linetime;
1f8eeabf 2059
ee91a159
MR		 2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
532f7a7f 2064 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2065 return 0;
1011d8c4 2066
1f8eeabf
ED		 2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
124abe07
VS		 2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2073 intel_state->cdclk);
1f8eeabf 2074
801bcfff
PZ		 2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2077}
2078
2af30a5c 2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2080{
fac5e23e 2081 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2082
2af30a5c
PB		 2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
4f947386 2085 int ret, i;
367294be 2086 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
4e4d3814
PZ		 2129 /*
2130 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2131 * need to be disabled. We make sure to sanitize the values out
2132 * of the punit to satisfy this requirement.
2133 */
2134 for (level = 1; level <= max_level; level++) {
2135 if (wm[level] == 0) {
2136 for (i = level + 1; i <= max_level; i++)
2137 wm[i] = 0;
2138 break;
2139 }
2140 }
2141
367294be 2142 /*
6f97235b
DL		 2143 * WaWmMemoryReadLatency:skl
2144 *
367294be 2145 * punit doesn't take into account the read latency so we need
4e4d3814
PZ		 2146 * to add 2us to the various latency levels we retrieve from the
2147 * punit when level 0 response data us 0us.
367294be 2148 */
4e4d3814
PZ		 2149 if (wm[0] == 0) {
2150 wm[0] += 2;
2151 for (level = 1; level <= max_level; level++) {
2152 if (wm[level] == 0)
2153 break;
367294be 2154 wm[level] += 2;
4f947386 2155 }
4e4d3814
PZ		 2156 }
2157
2af30a5c 2158 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2159 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2160
2161 wm[0] = (sskpd >> 56) & 0xFF;
2162 if (wm[0] == 0)
2163 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2164 wm[1] = (sskpd >> 4) & 0xFF;
2165 wm[2] = (sskpd >> 12) & 0xFF;
2166 wm[3] = (sskpd >> 20) & 0x1FF;
2167 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2168 } else if (INTEL_INFO(dev)->gen >= 6) {
2169 uint32_t sskpd = I915_READ(MCH_SSKPD);
2170
2171 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2172 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2173 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2174 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2175 } else if (INTEL_INFO(dev)->gen >= 5) {
2176 uint32_t mltr = I915_READ(MLTR_ILK);
2177
2178 /* ILK primary LP0 latency is 700 ns */
2179 wm[0] = 7;
2180 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2181 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2182 }
2183}
2184
53615a5e
VS		 2185static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2186{
2187 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2188 if (IS_GEN5(dev))
53615a5e
VS		 2189 wm[0] = 13;
2190}
2191
2192static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2195 if (IS_GEN5(dev))
53615a5e
VS		 2196 wm[0] = 13;
2197
2198 /* WaDoubleCursorLP3Latency:ivb */
2199 if (IS_IVYBRIDGE(dev))
2200 wm[3] *= 2;
2201}
2202
546c81fd 2203int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2204{
26ec971e 2205 /* how many WM levels are we expecting */
b6e742f6 2206 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2207 return 7;
2208 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2209 return 4;
26ec971e 2210 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2211 return 3;
26ec971e 2212 else
ad0d6dc4
VS		 2213 return 2;
2214}
7526ed79 2215
ad0d6dc4
VS		 2216static void intel_print_wm_latency(struct drm_device *dev,
2217 const char *name,
2af30a5c 2218 const uint16_t wm[8])
ad0d6dc4
VS		 2219{
2220 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2221
2222 for (level = 0; level <= max_level; level++) {
2223 unsigned int latency = wm[level];
2224
2225 if (latency == 0) {
2226 DRM_ERROR("%s WM%d latency not provided\n",
2227 name, level);
2228 continue;
2229 }
2230
2af30a5c
PB		 2231 /*
2232 * - latencies are in us on gen9.
2233 * - before then, WM1+ latency values are in 0.5us units
2234 */
2235 if (IS_GEN9(dev))
2236 latency *= 10;
2237 else if (level > 0)
26ec971e
VS		 2238 latency *= 5;
2239
2240 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2241 name, level, wm[level],
2242 latency / 10, latency % 10);
2243 }
2244}
2245
e95a2f75
VS		 2246static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2247 uint16_t wm[5], uint16_t min)
2248{
91c8a326 2249 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2250
2251 if (wm[0] >= min)
2252 return false;
2253
2254 wm[0] = max(wm[0], min);
2255 for (level = 1; level <= max_level; level++)
2256 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2257
2258 return true;
2259}
2260
2261static void snb_wm_latency_quirk(struct drm_device *dev)
2262{
fac5e23e 2263 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2264 bool changed;
2265
2266 /*
2267 * The BIOS provided WM memory latency values are often
2268 * inadequate for high resolution displays. Adjust them.
2269 */
2270 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2271 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2272 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2273
2274 if (!changed)
2275 return;
2276
2277 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2278 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281}
2282
fa50ad61 2283static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2284{
fac5e23e 2285 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2286
2287 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2288
2289 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2292 sizeof(dev_priv->wm.pri_latency));
2293
2294 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2295 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2296
2297 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2298 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2299 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2300
2301 if (IS_GEN6(dev))
2302 snb_wm_latency_quirk(dev);
53615a5e
VS		 2303}
2304
2af30a5c
PB		 2305static void skl_setup_wm_latency(struct drm_device *dev)
2306{
fac5e23e 2307 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2308
2309 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2310 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2311}
2312
ed4a6a7c
MR		 2313static bool ilk_validate_pipe_wm(struct drm_device *dev,
2314 struct intel_pipe_wm *pipe_wm)
2315{
2316 /* LP0 watermark maximums depend on this pipe alone */
2317 const struct intel_wm_config config = {
2318 .num_pipes_active = 1,
2319 .sprites_enabled = pipe_wm->sprites_enabled,
2320 .sprites_scaled = pipe_wm->sprites_scaled,
2321 };
2322 struct ilk_wm_maximums max;
2323
2324 /* LP0 watermarks always use 1/2 DDB partitioning */
2325 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2326
2327 /* At least LP0 must be valid */
2328 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2329 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2330 return false;
2331 }
2332
2333 return true;
2334}
2335
0b2ae6d7 2336/* Compute new watermarks for the pipe */
e3bddded 2337static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2338{
e3bddded
ML		 2339 struct drm_atomic_state *state = cstate->base.state;
2340 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2341 struct intel_pipe_wm *pipe_wm;
e3bddded 2342 struct drm_device *dev = state->dev;
fac5e23e 2343 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2344 struct intel_plane *intel_plane;
86c8bbbe 2345 struct intel_plane_state *pristate = NULL;
43d59eda 2346 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2347 struct intel_plane_state *curstate = NULL;
d81f04c5 2348 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2349 struct ilk_wm_maximums max;
0b2ae6d7 2350
e8f1f02e 2351 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2352
43d59eda 2353 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2354 struct intel_plane_state *ps;
2355
2356 ps = intel_atomic_get_existing_plane_state(state,
2357 intel_plane);
2358 if (!ps)
2359 continue;
86c8bbbe
MR		 2360
2361 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2362 pristate = ps;
86c8bbbe 2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2364 sprstate = ps;
86c8bbbe 2365 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2366 curstate = ps;
43d59eda
MR		 2367 }
2368
ed4a6a7c 2369 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2370 if (sprstate) {
936e71e3
VS		 2371 pipe_wm->sprites_enabled = sprstate->base.visible;
2372 pipe_wm->sprites_scaled = sprstate->base.visible &&
2373 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2374 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2375 }
2376
d81f04c5
ML		 2377 usable_level = max_level;
2378
7b39a0b7 2379 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2380 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2381 usable_level = 1;
7b39a0b7
VS		 2382
2383 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2384 if (pipe_wm->sprites_scaled)
d81f04c5 2385 usable_level = 0;
7b39a0b7 2386
86c8bbbe 2387 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2388 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2389
2390 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2391 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2392
a42a5719 2393 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2394 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2395
ed4a6a7c 2396 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2397 return -EINVAL;
a3cb4048
VS		 2398
2399 ilk_compute_wm_reg_maximums(dev, 1, &max);
2400
2401 for (level = 1; level <= max_level; level++) {
71f0a626 2402 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2403
86c8bbbe 2404 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2405 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2406
2407 /*
2408 * Disable any watermark level that exceeds the
2409 * register maximums since such watermarks are
2410 * always invalid.
2411 */
71f0a626
ML		 2412 if (level > usable_level)
2413 continue;
2414
2415 if (ilk_validate_wm_level(level, &max, wm))
2416 pipe_wm->wm[level] = *wm;
2417 else
d81f04c5 2418 usable_level = level;
a3cb4048
VS		 2419 }
2420
86c8bbbe 2421 return 0;
0b2ae6d7
VS		 2422}
2423
ed4a6a7c
MR		 2424/*
2425 * Build a set of 'intermediate' watermark values that satisfy both the old
2426 * state and the new state. These can be programmed to the hardware
2427 * immediately.
2428 */
2429static int ilk_compute_intermediate_wm(struct drm_device *dev,
2430 struct intel_crtc *intel_crtc,
2431 struct intel_crtc_state *newstate)
2432{
e8f1f02e 2433 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2434 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2435 int level, max_level = ilk_wm_max_level(dev);
2436
2437 /*
2438 * Start with the final, target watermarks, then combine with the
2439 * currently active watermarks to get values that are safe both before
2440 * and after the vblank.
2441 */
e8f1f02e 2442 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2443 a->pipe_enabled |= b->pipe_enabled;
2444 a->sprites_enabled |= b->sprites_enabled;
2445 a->sprites_scaled |= b->sprites_scaled;
2446
2447 for (level = 0; level <= max_level; level++) {
2448 struct intel_wm_level *a_wm = &a->wm[level];
2449 const struct intel_wm_level *b_wm = &b->wm[level];
2450
2451 a_wm->enable &= b_wm->enable;
2452 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2453 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2454 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2455 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2456 }
2457
2458 /*
2459 * We need to make sure that these merged watermark values are
2460 * actually a valid configuration themselves. If they're not,
2461 * there's no safe way to transition from the old state to
2462 * the new state, so we need to fail the atomic transaction.
2463 */
2464 if (!ilk_validate_pipe_wm(dev, a))
2465 return -EINVAL;
2466
2467 /*
2468 * If our intermediate WM are identical to the final WM, then we can
2469 * omit the post-vblank programming; only update if it's different.
2470 */
e8f1f02e 2471 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2472 newstate->wm.need_postvbl_update = false;
2473
2474 return 0;
2475}
2476
0b2ae6d7
VS		 2477/*
2478 * Merge the watermarks from all active pipes for a specific level.
2479 */
2480static void ilk_merge_wm_level(struct drm_device *dev,
2481 int level,
2482 struct intel_wm_level *ret_wm)
2483{
2484 const struct intel_crtc *intel_crtc;
2485
d52fea5b
VS		 2486 ret_wm->enable = true;
2487
d3fcc808 2488 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2489 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2490 const struct intel_wm_level *wm = &active->wm[level];
2491
2492 if (!active->pipe_enabled)
2493 continue;
0b2ae6d7 2494
d52fea5b
VS		 2495 /*
2496 * The watermark values may have been used in the past,
2497 * so we must maintain them in the registers for some
2498 * time even if the level is now disabled.
2499 */
0b2ae6d7 2500 if (!wm->enable)
d52fea5b 2501 ret_wm->enable = false;
0b2ae6d7
VS		 2502
2503 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2504 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2505 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2506 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2507 }
0b2ae6d7
VS		 2508}
2509
2510/*
2511 * Merge all low power watermarks for all active pipes.
2512 */
2513static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2514 const struct intel_wm_config *config,
820c1980 2515 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2516 struct intel_pipe_wm *merged)
2517{
fac5e23e 2518 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2519 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2520 int last_enabled_level = max_level;
0b2ae6d7 2521
0ba22e26
VS		 2522 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2523 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2524 config->num_pipes_active > 1)
1204d5ba 2525 last_enabled_level = 0;
0ba22e26 2526
6c8b6c28
VS		 2527 /* ILK: FBC WM must be disabled always */
2528 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2529
2530 /* merge each WM1+ level */
2531 for (level = 1; level <= max_level; level++) {
2532 struct intel_wm_level *wm = &merged->wm[level];
2533
2534 ilk_merge_wm_level(dev, level, wm);
2535
d52fea5b
VS		 2536 if (level > last_enabled_level)
2537 wm->enable = false;
2538 else if (!ilk_validate_wm_level(level, max, wm))
2539 /* make sure all following levels get disabled */
2540 last_enabled_level = level - 1;
0b2ae6d7
VS		 2541
2542 /*
2543 * The spec says it is preferred to disable
2544 * FBC WMs instead of disabling a WM level.
2545 */
2546 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2547 if (wm->enable)
2548 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2549 wm->fbc_val = 0;
2550 }
2551 }
6c8b6c28
VS		 2552
2553 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2554 /*
2555 * FIXME this is racy. FBC might get enabled later.
2556 * What we should check here is whether FBC can be
2557 * enabled sometime later.
2558 */
7733b49b 2559 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2560 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2561 for (level = 2; level <= max_level; level++) {
2562 struct intel_wm_level *wm = &merged->wm[level];
2563
2564 wm->enable = false;
2565 }
2566 }
0b2ae6d7
VS		 2567}
2568
b380ca3c
VS		 2569static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2570{
2571 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2572 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2573}
2574
a68d68ee
VS		 2575/* The value we need to program into the WM_LPx latency field */
2576static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2577{
fac5e23e 2578 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2579
a42a5719 2580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2581 return 2 * level;
2582 else
2583 return dev_priv->wm.pri_latency[level];
2584}
2585
820c1980 2586static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2587 const struct intel_pipe_wm *merged,
609cedef 2588 enum intel_ddb_partitioning partitioning,
820c1980 2589 struct ilk_wm_values *results)
801bcfff 2590{
0b2ae6d7
VS		 2591 struct intel_crtc *intel_crtc;
2592 int level, wm_lp;
cca32e9a 2593
0362c781 2594 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2595 results->partitioning = partitioning;
cca32e9a 2596
0b2ae6d7 2597 /* LP1+ register values */
cca32e9a 2598 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2599 const struct intel_wm_level *r;
801bcfff 2600
b380ca3c 2601 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2602
0362c781 2603 r = &merged->wm[level];
cca32e9a 2604
d52fea5b
VS		 2605 /*
2606 * Maintain the watermark values even if the level is
2607 * disabled. Doing otherwise could cause underruns.
2608 */
2609 results->wm_lp[wm_lp - 1] =
a68d68ee 2610 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2611 (r->pri_val << WM1_LP_SR_SHIFT) |
2612 r->cur_val;
2613
d52fea5b
VS		 2614 if (r->enable)
2615 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2616
416f4727
VS		 2617 if (INTEL_INFO(dev)->gen >= 8)
2618 results->wm_lp[wm_lp - 1] |=
2619 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2620 else
2621 results->wm_lp[wm_lp - 1] |=
2622 r->fbc_val << WM1_LP_FBC_SHIFT;
2623
d52fea5b
VS		 2624 /*
2625 * Always set WM1S_LP_EN when spr_val != 0, even if the
2626 * level is disabled. Doing otherwise could cause underruns.
2627 */
6cef2b8a
VS		 2628 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2629 WARN_ON(wm_lp != 1);
2630 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2631 } else
2632 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2633 }
801bcfff 2634
0b2ae6d7 2635 /* LP0 register values */
d3fcc808 2636 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2637 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2638 const struct intel_wm_level *r =
2639 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2640
2641 if (WARN_ON(!r->enable))
2642 continue;
2643
ed4a6a7c 2644 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2645
0b2ae6d7
VS		 2646 results->wm_pipe[pipe] =
2647 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2648 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2649 r->cur_val;
801bcfff
PZ		 2650 }
2651}
2652
861f3389
PZ		 2653/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2654 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2655static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2656 struct intel_pipe_wm *r1,
2657 struct intel_pipe_wm *r2)
861f3389 2658{
198a1e9b
VS		 2659 int level, max_level = ilk_wm_max_level(dev);
2660 int level1 = 0, level2 = 0;
861f3389 2661
198a1e9b
VS		 2662 for (level = 1; level <= max_level; level++) {
2663 if (r1->wm[level].enable)
2664 level1 = level;
2665 if (r2->wm[level].enable)
2666 level2 = level;
861f3389
PZ		 2667 }
2668
198a1e9b
VS		 2669 if (level1 == level2) {
2670 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2671 return r2;
2672 else
2673 return r1;
198a1e9b 2674 } else if (level1 > level2) {
861f3389
PZ		 2675 return r1;
2676 } else {
2677 return r2;
2678 }
2679}
2680
49a687c4
VS		 2681/* dirty bits used to track which watermarks need changes */
2682#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2683#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2684#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2685#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2686#define WM_DIRTY_FBC (1 << 24)
2687#define WM_DIRTY_DDB (1 << 25)
2688
055e393f 2689static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2690 const struct ilk_wm_values *old,
2691 const struct ilk_wm_values *new)
49a687c4
VS		 2692{
2693 unsigned int dirty = 0;
2694 enum pipe pipe;
2695 int wm_lp;
2696
055e393f 2697 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2698 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2699 dirty |= WM_DIRTY_LINETIME(pipe);
2700 /* Must disable LP1+ watermarks too */
2701 dirty |= WM_DIRTY_LP_ALL;
2702 }
2703
2704 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2705 dirty |= WM_DIRTY_PIPE(pipe);
2706 /* Must disable LP1+ watermarks too */
2707 dirty |= WM_DIRTY_LP_ALL;
2708 }
2709 }
2710
2711 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2712 dirty |= WM_DIRTY_FBC;
2713 /* Must disable LP1+ watermarks too */
2714 dirty |= WM_DIRTY_LP_ALL;
2715 }
2716
2717 if (old->partitioning != new->partitioning) {
2718 dirty |= WM_DIRTY_DDB;
2719 /* Must disable LP1+ watermarks too */
2720 dirty |= WM_DIRTY_LP_ALL;
2721 }
2722
2723 /* LP1+ watermarks already deemed dirty, no need to continue */
2724 if (dirty & WM_DIRTY_LP_ALL)
2725 return dirty;
2726
2727 /* Find the lowest numbered LP1+ watermark in need of an update... */
2728 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2729 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2730 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2731 break;
2732 }
2733
2734 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2735 for (; wm_lp <= 3; wm_lp++)
2736 dirty |= WM_DIRTY_LP(wm_lp);
2737
2738 return dirty;
2739}
2740
8553c18e
VS		 2741static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2742 unsigned int dirty)
801bcfff 2743{
820c1980 2744 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2745 bool changed = false;
801bcfff 2746
facd619b
VS		 2747 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2748 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2749 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2750 changed = true;
facd619b
VS		 2751 }
2752 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2753 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2754 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2755 changed = true;
facd619b
VS		 2756 }
2757 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2758 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2760 changed = true;
facd619b 2761 }
801bcfff 2762
facd619b
VS		 2763 /*
2764 * Don't touch WM1S_LP_EN here.
2765 * Doing so could cause underruns.
2766 */
6cef2b8a 2767
8553c18e
VS		 2768 return changed;
2769}
2770
2771/*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
820c1980
ID		 2775static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2776 struct ilk_wm_values *results)
8553c18e 2777{
91c8a326 2778 struct drm_device *dev = &dev_priv->drm;
820c1980 2779 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2780 unsigned int dirty;
2781 uint32_t val;
2782
055e393f 2783 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2784 if (!dirty)
2785 return;
2786
2787 _ilk_disable_lp_wm(dev_priv, dirty);
2788
49a687c4 2789 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2790 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2791 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2792 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2793 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2794 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2795
49a687c4 2796 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2798 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2800 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2801 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2802
49a687c4 2803 if (dirty & WM_DIRTY_DDB) {
a42a5719 2804 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2805 val = I915_READ(WM_MISC);
2806 if (results->partitioning == INTEL_DDB_PART_1_2)
2807 val &= ~WM_MISC_DATA_PARTITION_5_6;
2808 else
2809 val |= WM_MISC_DATA_PARTITION_5_6;
2810 I915_WRITE(WM_MISC, val);
2811 } else {
2812 val = I915_READ(DISP_ARB_CTL2);
2813 if (results->partitioning == INTEL_DDB_PART_1_2)
2814 val &= ~DISP_DATA_PARTITION_5_6;
2815 else
2816 val |= DISP_DATA_PARTITION_5_6;
2817 I915_WRITE(DISP_ARB_CTL2, val);
2818 }
1011d8c4
PZ		 2819 }
2820
49a687c4 2821 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2822 val = I915_READ(DISP_ARB_CTL);
2823 if (results->enable_fbc_wm)
2824 val &= ~DISP_FBC_WM_DIS;
2825 else
2826 val |= DISP_FBC_WM_DIS;
2827 I915_WRITE(DISP_ARB_CTL, val);
2828 }
2829
954911eb
ID		 2830 if (dirty & WM_DIRTY_LP(1) &&
2831 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2832 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2833
2834 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2835 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2836 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2837 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2838 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2839 }
801bcfff 2840
facd619b 2841 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2842 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2843 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2844 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2845 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2846 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2847
2848 dev_priv->wm.hw = *results;
801bcfff
PZ		 2849}
2850
ed4a6a7c 2851bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2852{
fac5e23e 2853 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2854
2855 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2856}
2857
656d1b89 2858#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2859
024c9045
MR		 2860/*
2861 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2862 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2863 * other universal planes are in indices 1..n. Note that this may leave unused
2864 * indices between the top "sprite" plane and the cursor.
2865 */
2866static int
2867skl_wm_plane_id(const struct intel_plane *plane)
2868{
2869 switch (plane->base.type) {
2870 case DRM_PLANE_TYPE_PRIMARY:
2871 return 0;
2872 case DRM_PLANE_TYPE_CURSOR:
2873 return PLANE_CURSOR;
2874 case DRM_PLANE_TYPE_OVERLAY:
2875 return plane->plane + 1;
2876 default:
2877 MISSING_CASE(plane->base.type);
2878 return plane->plane;
2879 }
2880}
2881
6e7fdb87
PZ		 2882static bool
2883intel_has_sagv(struct drm_i915_private *dev_priv)
2884{
17777d61
PZ		 2885 if (IS_KABYLAKE(dev_priv))
2886 return true;
2887
2888 if (IS_SKYLAKE(dev_priv) &&
2889 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2890 return true;
2891
2892 return false;
6e7fdb87
PZ		 2893}
2894
656d1b89
L		 2895/*
2896 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2897 * depending on power and performance requirements. The display engine access
2898 * to system memory is blocked during the adjustment time. Because of the
2899 * blocking time, having this enabled can cause full system hangs and/or pipe
2900 * underruns if we don't meet all of the following requirements:
2901 *
2902 * - <= 1 pipe enabled
2903 * - All planes can enable watermarks for latencies >= SAGV engine block time
2904 * - We're not using an interlaced display configuration
2905 */
2906int
674f823b 2907intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2908{
2909 int ret;
2910
6e7fdb87
PZ		 2911 if (!intel_has_sagv(dev_priv))
2912 return 0;
2913
2914 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2915 return 0;
2916
2917 DRM_DEBUG_KMS("Enabling the SAGV\n");
2918 mutex_lock(&dev_priv->rps.hw_lock);
2919
2920 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2921 GEN9_SAGV_ENABLE);
2922
2923 /* We don't need to wait for the SAGV when enabling */
2924 mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926 /*
2927 * Some skl systems, pre-release machines in particular,
2928 * don't actually have an SAGV.
2929 */
17777d61 2930 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2931 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
674f823b 2932 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2933 return 0;
2934 } else if (ret < 0) {
2935 DRM_ERROR("Failed to enable the SAGV\n");
2936 return ret;
2937 }
2938
674f823b 2939 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2940 return 0;
2941}
2942
2943static int
674f823b 2944intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2945{
2946 int ret;
2947 uint32_t temp = GEN9_SAGV_DISABLE;
2948
2949 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2950 &temp);
2951 if (ret)
2952 return ret;
2953 else
2954 return temp & GEN9_SAGV_IS_DISABLED;
2955}
2956
2957int
674f823b 2958intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2959{
2960 int ret, result;
2961
6e7fdb87
PZ		 2962 if (!intel_has_sagv(dev_priv))
2963 return 0;
2964
2965 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2966 return 0;
2967
2968 DRM_DEBUG_KMS("Disabling the SAGV\n");
2969 mutex_lock(&dev_priv->rps.hw_lock);
2970
2971 /* bspec says to keep retrying for at least 1 ms */
674f823b 2972 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2973 mutex_unlock(&dev_priv->rps.hw_lock);
2974
2975 if (ret == -ETIMEDOUT) {
2976 DRM_ERROR("Request to disable SAGV timed out\n");
2977 return -ETIMEDOUT;
2978 }
2979
2980 /*
2981 * Some skl systems, pre-release machines in particular,
2982 * don't actually have an SAGV.
2983 */
17777d61 2984 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 2985 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
674f823b 2986 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2987 return 0;
2988 } else if (result < 0) {
2989 DRM_ERROR("Failed to disable the SAGV\n");
2990 return result;
2991 }
2992
674f823b 2993 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 2994 return 0;
2995}
2996
674f823b 2997bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 2998{
2999 struct drm_device *dev = state->dev;
3000 struct drm_i915_private *dev_priv = to_i915(dev);
3001 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3002 struct drm_crtc *crtc;
3003 enum pipe pipe;
3004 int level, plane;
3005
6e7fdb87
PZ		 3006 if (!intel_has_sagv(dev_priv))
3007 return false;
3008
656d1b89
L		 3009 /*
3010 * SKL workaround: bspec recommends we disable the SAGV when we have
3011 * more then one pipe enabled
3012 *
3013 * If there are no active CRTCs, no additional checks need be performed
3014 */
3015 if (hweight32(intel_state->active_crtcs) == 0)
3016 return true;
3017 else if (hweight32(intel_state->active_crtcs) > 1)
3018 return false;
3019
3020 /* Since we're now guaranteed to only have one active CRTC... */
3021 pipe = ffs(intel_state->active_crtcs) - 1;
3022 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3023
3024 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3025 return false;
3026
3027 for_each_plane(dev_priv, pipe, plane) {
3028 /* Skip this plane if it's not enabled */
3029 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3030 continue;
3031
3032 /* Find the highest enabled wm level for this plane */
3033 for (level = ilk_wm_max_level(dev);
3034 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3035 { }
3036
3037 /*
3038 * If any of the planes on this pipe don't enable wm levels
3039 * that incur memory latencies higher then 30µs we can't enable
3040 * the SAGV
3041 */
3042 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3043 return false;
3044 }
3045
3046 return true;
3047}
3048
b9cec075
DL		 3049static void
3050skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3051 const struct intel_crtc_state *cstate,
c107acfe
MR		 3052 struct skl_ddb_entry *alloc, /* out */
3053 int *num_active /* out */)
b9cec075 3054{
c107acfe
MR		 3055 struct drm_atomic_state *state = cstate->base.state;
3056 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3057 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3058 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3059 unsigned int pipe_size, ddb_size;
3060 int nth_active_pipe;
c107acfe
MR		 3061 int pipe = to_intel_crtc(for_crtc)->pipe;
3062
a6d3460e 3063 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3064 alloc->start = 0;
3065 alloc->end = 0;
a6d3460e 3066 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3067 return;
3068 }
3069
a6d3460e
MR		 3070 if (intel_state->active_pipe_changes)
3071 *num_active = hweight32(intel_state->active_crtcs);
3072 else
3073 *num_active = hweight32(dev_priv->active_crtcs);
3074
6f3fff60
D		 3075 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3076 WARN_ON(ddb_size == 0);
b9cec075
DL		 3077
3078 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3079
c107acfe 3080 /*
a6d3460e
MR		 3081 * If the state doesn't change the active CRTC's, then there's
3082 * no need to recalculate; the existing pipe allocation limits
3083 * should remain unchanged. Note that we're safe from racing
3084 * commits since any racing commit that changes the active CRTC
3085 * list would need to grab _all_ crtc locks, including the one
3086 * we currently hold.
c107acfe 3087 */
a6d3460e
MR		 3088 if (!intel_state->active_pipe_changes) {
3089 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3090 return;
c107acfe 3091 }
a6d3460e
MR		 3092
3093 nth_active_pipe = hweight32(intel_state->active_crtcs &
3094 (drm_crtc_mask(for_crtc) - 1));
3095 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3096 alloc->start = nth_active_pipe * ddb_size / *num_active;
3097 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3098}
3099
c107acfe 3100static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3101{
c107acfe 3102 if (num_active == 1)
b9cec075
DL		 3103 return 32;
3104
3105 return 8;
3106}
3107
a269c583
DL		 3108static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3109{
3110 entry->start = reg & 0x3ff;
3111 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3112 if (entry->end)
3113 entry->end += 1;
a269c583
DL		 3114}
3115
08db6652
DL		 3116void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3117 struct skl_ddb_allocation *ddb /* out */)
a269c583 3118{
a269c583
DL		 3119 enum pipe pipe;
3120 int plane;
3121 u32 val;
3122
b10f1b20
ML		 3123 memset(ddb, 0, sizeof(*ddb));
3124
a269c583 3125 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3126 enum intel_display_power_domain power_domain;
3127
3128 power_domain = POWER_DOMAIN_PIPE(pipe);
3129 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3130 continue;
3131
dd740780 3132 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3133 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3134 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3135 val);
3136 }
3137
3138 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3139 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3140 val);
4d800030
ID		 3141
3142 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3143 }
3144}
3145
9c2f7a9d
KM		 3146/*
3147 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3148 * The bspec defines downscale amount as:
3149 *
3150 * """
3151 * Horizontal down scale amount = maximum[1, Horizontal source size /
3152 * Horizontal destination size]
3153 * Vertical down scale amount = maximum[1, Vertical source size /
3154 * Vertical destination size]
3155 * Total down scale amount = Horizontal down scale amount *
3156 * Vertical down scale amount
3157 * """
3158 *
3159 * Return value is provided in 16.16 fixed point form to retain fractional part.
3160 * Caller should take care of dividing & rounding off the value.
3161 */
3162static uint32_t
3163skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3164{
3165 uint32_t downscale_h, downscale_w;
3166 uint32_t src_w, src_h, dst_w, dst_h;
3167
936e71e3 3168 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3169 return DRM_PLANE_HELPER_NO_SCALING;
3170
3171 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3172 src_w = drm_rect_width(&pstate->base.src);
3173 src_h = drm_rect_height(&pstate->base.src);
3174 dst_w = drm_rect_width(&pstate->base.dst);
3175 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3176 if (intel_rotation_90_or_270(pstate->base.rotation))
3177 swap(dst_w, dst_h);
3178
3179 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3180 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3181
3182 /* Provide result in 16.16 fixed point */
3183 return (uint64_t)downscale_w * downscale_h >> 16;
3184}
3185
b9cec075 3186static unsigned int
024c9045
MR		 3187skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3188 const struct drm_plane_state *pstate,
3189 int y)
b9cec075 3190{
a280f7dd 3191 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3192 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3193 uint32_t down_scale_amount, data_rate;
a280f7dd 3194 uint32_t width = 0, height = 0;
a1de91e5
MR		 3195 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3196
936e71e3 3197 if (!intel_pstate->base.visible)
a1de91e5
MR		 3198 return 0;
3199 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3200 return 0;
3201 if (y && format != DRM_FORMAT_NV12)
3202 return 0;
a280f7dd 3203
936e71e3
VS		 3204 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3205 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3206
3207 if (intel_rotation_90_or_270(pstate->rotation))
3208 swap(width, height);
2cd601c6
CK		 3209
3210 /* for planar format */
a1de91e5 3211 if (format == DRM_FORMAT_NV12) {
2cd601c6 3212 if (y) /* y-plane data rate */
8d19d7d9 3213 data_rate = width * height *
a1de91e5 3214 drm_format_plane_cpp(format, 0);
2cd601c6 3215 else /* uv-plane data rate */
8d19d7d9 3216 data_rate = (width / 2) * (height / 2) *
a1de91e5 3217 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3218 } else {
3219 /* for packed formats */
3220 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3221 }
3222
8d19d7d9
KM		 3223 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3224
3225 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3226}
3227
3228/*
3229 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3230 * a 8192x4096@32bpp framebuffer:
3231 * 3 * 4096 * 8192 * 4 < 2^32
3232 */
3233static unsigned int
9c74d826 3234skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3235{
9c74d826
MR		 3236 struct drm_crtc_state *cstate = &intel_cstate->base;
3237 struct drm_atomic_state *state = cstate->state;
3238 struct drm_crtc *crtc = cstate->crtc;
3239 struct drm_device *dev = crtc->dev;
3240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3241 const struct drm_plane *plane;
024c9045 3242 const struct intel_plane *intel_plane;
a6d3460e 3243 struct drm_plane_state *pstate;
a1de91e5 3244 unsigned int rate, total_data_rate = 0;
9c74d826 3245 int id;
a6d3460e
MR		 3246 int i;
3247
3248 if (WARN_ON(!state))
3249 return 0;
b9cec075 3250
a1de91e5 3251 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3252 for_each_plane_in_state(state, plane, pstate, i) {
3253 id = skl_wm_plane_id(to_intel_plane(plane));
3254 intel_plane = to_intel_plane(plane);
3255
3256 if (intel_plane->pipe != intel_crtc->pipe)
3257 continue;
3258
3259 /* packed/uv */
3260 rate = skl_plane_relative_data_rate(intel_cstate,
3261 pstate, 0);
3262 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3263
3264 /* y-plane */
3265 rate = skl_plane_relative_data_rate(intel_cstate,
3266 pstate, 1);
3267 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3268 }
024c9045 3269
a1de91e5
MR		 3270 /* Calculate CRTC's total data rate from cached values */
3271 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3272 int id = skl_wm_plane_id(intel_plane);
024c9045 3273
a1de91e5 3274 /* packed/uv */
9c74d826
MR		 3275 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3276 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3277 }
3278
3279 return total_data_rate;
3280}
3281
cbcfd14b
KM		 3282static uint16_t
3283skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3284 const int y)
3285{
3286 struct drm_framebuffer *fb = pstate->fb;
3287 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3288 uint32_t src_w, src_h;
3289 uint32_t min_scanlines = 8;
3290 uint8_t plane_bpp;
3291
3292 if (WARN_ON(!fb))
3293 return 0;
3294
3295 /* For packed formats, no y-plane, return 0 */
3296 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3297 return 0;
3298
3299 /* For Non Y-tile return 8-blocks */
3300 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3301 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3302 return 8;
3303
936e71e3
VS		 3304 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3305 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3306
3307 if (intel_rotation_90_or_270(pstate->rotation))
3308 swap(src_w, src_h);
3309
3310 /* Halve UV plane width and height for NV12 */
3311 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3312 src_w /= 2;
3313 src_h /= 2;
3314 }
3315
3316 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3317 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3318 else
3319 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3320
3321 if (intel_rotation_90_or_270(pstate->rotation)) {
3322 switch (plane_bpp) {
3323 case 1:
3324 min_scanlines = 32;
3325 break;
3326 case 2:
3327 min_scanlines = 16;
3328 break;
3329 case 4:
3330 min_scanlines = 8;
3331 break;
3332 case 8:
3333 min_scanlines = 4;
3334 break;
3335 default:
3336 WARN(1, "Unsupported pixel depth %u for rotation",
3337 plane_bpp);
3338 min_scanlines = 32;
3339 }
3340 }
3341
3342 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3343}
3344
c107acfe 3345static int
024c9045 3346skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3347 struct skl_ddb_allocation *ddb /* out */)
3348{
c107acfe 3349 struct drm_atomic_state *state = cstate->base.state;
024c9045 3350 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3351 struct drm_device *dev = crtc->dev;
3352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3353 struct intel_plane *intel_plane;
c107acfe
MR		 3354 struct drm_plane *plane;
3355 struct drm_plane_state *pstate;
b9cec075 3356 enum pipe pipe = intel_crtc->pipe;
34bb56af 3357 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3358 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3359 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3360 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3361 unsigned int total_data_rate;
c107acfe
MR		 3362 int num_active;
3363 int id, i;
b9cec075 3364
a6d3460e
MR		 3365 if (WARN_ON(!state))
3366 return 0;
3367
c107acfe
MR		 3368 if (!cstate->base.active) {
3369 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3370 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3371 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3372 return 0;
3373 }
3374
a6d3460e 3375 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3376 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3377 if (alloc_size == 0) {
3378 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3379 return 0;
b9cec075
DL		 3380 }
3381
c107acfe 3382 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3383 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3384 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3385
3386 alloc_size -= cursor_blocks;
b9cec075 3387
80958155 3388 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3389 for_each_plane_in_state(state, plane, pstate, i) {
3390 intel_plane = to_intel_plane(plane);
3391 id = skl_wm_plane_id(intel_plane);
c107acfe 3392
a6d3460e
MR		 3393 if (intel_plane->pipe != pipe)
3394 continue;
c107acfe 3395
936e71e3 3396 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3397 minimum[id] = 0;
3398 y_minimum[id] = 0;
3399 continue;
3400 }
3401 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3402 minimum[id] = 0;
3403 y_minimum[id] = 0;
3404 continue;
c107acfe 3405 }
a6d3460e 3406
cbcfd14b
KM		 3407 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3408 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3409 }
80958155 3410
c107acfe
MR		 3411 for (i = 0; i < PLANE_CURSOR; i++) {
3412 alloc_size -= minimum[i];
3413 alloc_size -= y_minimum[i];
80958155
DL		 3414 }
3415
b9cec075 3416 /*
80958155
DL		 3417 * 2. Distribute the remaining space in proportion to the amount of
3418 * data each plane needs to fetch from memory.
b9cec075
DL		 3419 *
3420 * FIXME: we may not allocate every single block here.
3421 */
024c9045 3422 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3423 if (total_data_rate == 0)
c107acfe 3424 return 0;
b9cec075 3425
34bb56af 3426 start = alloc->start;
024c9045 3427 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3428 unsigned int data_rate, y_data_rate;
3429 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3430 int id = skl_wm_plane_id(intel_plane);
b9cec075 3431
a1de91e5 3432 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3433
3434 /*
2cd601c6 3435 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3436 * promote the expression to 64 bits to avoid overflowing, the
3437 * result is < available as data_rate / total_data_rate < 1
3438 */
024c9045 3439 plane_blocks = minimum[id];
80958155
DL		 3440 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3441 total_data_rate);
b9cec075 3442
c107acfe
MR		 3443 /* Leave disabled planes at (0,0) */
3444 if (data_rate) {
3445 ddb->plane[pipe][id].start = start;
3446 ddb->plane[pipe][id].end = start + plane_blocks;
3447 }
b9cec075
DL		 3448
3449 start += plane_blocks;
2cd601c6
CK		 3450
3451 /*
3452 * allocation for y_plane part of planar format:
3453 */
a1de91e5
MR		 3454 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3455
3456 y_plane_blocks = y_minimum[id];
3457 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3458 total_data_rate);
2cd601c6 3459
c107acfe
MR		 3460 if (y_data_rate) {
3461 ddb->y_plane[pipe][id].start = start;
3462 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3463 }
a1de91e5
MR		 3464
3465 start += y_plane_blocks;
b9cec075
DL		 3466 }
3467
c107acfe 3468 return 0;
b9cec075
DL		 3469}
3470
5cec258b 3471static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3472{
3473 /* TODO: Take into account the scalers once we support them */
2d112de7 3474 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3475}
3476
3477/*
3478 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3479 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3480 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3481 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3482*/
ac484963 3483static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3484{
3485 uint32_t wm_intermediate_val, ret;
3486
3487 if (latency == 0)
3488 return UINT_MAX;
3489
ac484963 3490 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3491 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3492
3493 return ret;
3494}
3495
3496static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3497 uint32_t horiz_pixels, uint8_t cpp,
ccc10574
PZ		 3498 uint64_t tiling, uint32_t latency,
3499 uint32_t y_min_scanlines)
2d41c0b5 3500{
d4c2aa60
TU		 3501 uint32_t ret;
3502 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3503 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3504
3505 if (latency == 0)
3506 return UINT_MAX;
3507
ac484963 3508 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3509
3510 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3511 tiling == I915_FORMAT_MOD_Yf_TILED) {
ccc10574 3512 plane_bytes_per_line *= y_min_scanlines;
0fda6568 3513 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
ccc10574 3514 plane_blocks_per_line /= y_min_scanlines;
055c3ff6
MR		 3515 } else if (tiling == DRM_FORMAT_MOD_NONE) {
3516 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
0fda6568
TU		 3517 } else {
3518 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3519 }
3520
2d41c0b5
PB		 3521 wm_intermediate_val = latency * pixel_rate;
3522 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3523 plane_blocks_per_line;
2d41c0b5
PB		 3524
3525 return ret;
3526}
3527
9c2f7a9d
KM		 3528static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3529 struct intel_plane_state *pstate)
3530{
3531 uint64_t adjusted_pixel_rate;
3532 uint64_t downscale_amount;
3533 uint64_t pixel_rate;
3534
3535 /* Shouldn't reach here on disabled planes... */
936e71e3 3536 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3537 return 0;
3538
3539 /*
3540 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3541 * with additional adjustments for plane-specific scaling.
3542 */
3543 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3544 downscale_amount = skl_plane_downscale_amount(pstate);
3545
3546 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3547 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3548
3549 return pixel_rate;
3550}
3551
55994c2c
MR		 3552static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3553 struct intel_crtc_state *cstate,
3554 struct intel_plane_state *intel_pstate,
3555 uint16_t ddb_allocation,
3556 int level,
3557 uint16_t *out_blocks, /* out */
3558 uint8_t *out_lines, /* out */
3559 bool *enabled /* out */)
2d41c0b5 3560{
33815fa5
MR		 3561 struct drm_plane_state *pstate = &intel_pstate->base;
3562 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3563 uint32_t latency = dev_priv->wm.skl_latency[level];
3564 uint32_t method1, method2;
3565 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3566 uint32_t res_blocks, res_lines;
3567 uint32_t selected_result;
ac484963 3568 uint8_t cpp;
a280f7dd 3569 uint32_t width = 0, height = 0;
9c2f7a9d 3570 uint32_t plane_pixel_rate;
ccc10574 3571 uint32_t y_min_scanlines;
2d41c0b5 3572
936e71e3 3573 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3574 *enabled = false;
3575 return 0;
3576 }
2d41c0b5 3577
936e71e3
VS		 3578 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3579 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3580
33815fa5 3581 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3582 swap(width, height);
3583
ac484963 3584 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3585 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3586
ccc10574
PZ		 3587 if (intel_rotation_90_or_270(pstate->rotation)) {
3588 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3589 drm_format_plane_cpp(fb->pixel_format, 1) :
3590 drm_format_plane_cpp(fb->pixel_format, 0);
3591
3592 switch (cpp) {
3593 case 1:
3594 y_min_scanlines = 16;
3595 break;
3596 case 2:
3597 y_min_scanlines = 8;
3598 break;
3599 default:
3600 WARN(1, "Unsupported pixel depth for rotation");
3601 case 4:
3602 y_min_scanlines = 4;
3603 break;
3604 }
3605 } else {
3606 y_min_scanlines = 4;
3607 }
3608
9c2f7a9d
KM		 3609 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3610 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3611 cstate->base.adjusted_mode.crtc_htotal,
a280f7dd
KM		 3612 width,
3613 cpp,
3614 fb->modifier[0],
ccc10574
PZ		 3615 latency,
3616 y_min_scanlines);
2d41c0b5 3617
a280f7dd 3618 plane_bytes_per_line = width * cpp;
d4c2aa60 3619 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3620
024c9045
MR		 3621 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3622 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
ccc10574
PZ		 3623 uint32_t y_tile_minimum = plane_blocks_per_line *
3624 y_min_scanlines;
0fda6568
TU		 3625 selected_result = max(method2, y_tile_minimum);
3626 } else {
3627 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3628 selected_result = min(method1, method2);
3629 else
3630 selected_result = method1;
3631 }
2d41c0b5 3632
d4c2aa60
TU		 3633 res_blocks = selected_result + 1;
3634 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3635
0fda6568 3636 if (level >= 1 && level <= 7) {
024c9045
MR		 3637 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3638 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
ccc10574 3639 res_lines += y_min_scanlines;
0fda6568
TU		 3640 else
3641 res_blocks++;
3642 }
e6d66171 3643
55994c2c
MR		 3644 if (res_blocks >= ddb_allocation || res_lines > 31) {
3645 *enabled = false;
6b6bada7
MR		 3646
3647 /*
3648 * If there are no valid level 0 watermarks, then we can't
3649 * support this display configuration.
3650 */
3651 if (level) {
3652 return 0;
3653 } else {
3654 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3655 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3656 to_intel_crtc(cstate->base.crtc)->pipe,
3657 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3658 res_blocks, ddb_allocation, res_lines);
3659
3660 return -EINVAL;
3661 }
55994c2c 3662 }
e6d66171
DL		 3663
3664 *out_blocks = res_blocks;
3665 *out_lines = res_lines;
55994c2c 3666 *enabled = true;
2d41c0b5 3667
55994c2c 3668 return 0;
2d41c0b5
PB		 3669}
3670
f4a96752
MR		 3671static int
3672skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3673 struct skl_ddb_allocation *ddb,
3674 struct intel_crtc_state *cstate,
3675 int level,
3676 struct skl_wm_level *result)
2d41c0b5 3677{
f4a96752 3678 struct drm_atomic_state *state = cstate->base.state;
024c9045 3679 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3680 struct drm_plane *plane;
024c9045 3681 struct intel_plane *intel_plane;
33815fa5 3682 struct intel_plane_state *intel_pstate;
2d41c0b5 3683 uint16_t ddb_blocks;
024c9045 3684 enum pipe pipe = intel_crtc->pipe;
55994c2c 3685 int ret;
024c9045 3686
f4a96752
MR		 3687 /*
3688 * We'll only calculate watermarks for planes that are actually
3689 * enabled, so make sure all other planes are set as disabled.
3690 */
3691 memset(result, 0, sizeof(*result));
3692
91c8a326
CW		 3693 for_each_intel_plane_mask(&dev_priv->drm,
3694 intel_plane,
3695 cstate->base.plane_mask) {
024c9045 3696 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3697
f4a96752
MR		 3698 plane = &intel_plane->base;
3699 intel_pstate = NULL;
3700 if (state)
3701 intel_pstate =
3702 intel_atomic_get_existing_plane_state(state,
3703 intel_plane);
3704
3705 /*
3706 * Note: If we start supporting multiple pending atomic commits
3707 * against the same planes/CRTC's in the future, plane->state
3708 * will no longer be the correct pre-state to use for the
3709 * calculations here and we'll need to change where we get the
3710 * 'unchanged' plane data from.
3711 *
3712 * For now this is fine because we only allow one queued commit
3713 * against a CRTC. Even if the plane isn't modified by this
3714 * transaction and we don't have a plane lock, we still have
3715 * the CRTC's lock, so we know that no other transactions are
3716 * racing with us to update it.
3717 */
3718 if (!intel_pstate)
3719 intel_pstate = to_intel_plane_state(plane->state);
3720
3721 WARN_ON(!intel_pstate->base.fb);
3722
2d41c0b5
PB		 3723 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3724
55994c2c
MR		 3725 ret = skl_compute_plane_wm(dev_priv,
3726 cstate,
3727 intel_pstate,
3728 ddb_blocks,
3729 level,
3730 &result->plane_res_b[i],
3731 &result->plane_res_l[i],
3732 &result->plane_en[i]);
3733 if (ret)
3734 return ret;
2d41c0b5 3735 }
f4a96752
MR		 3736
3737 return 0;
2d41c0b5
PB		 3738}
3739
407b50f3 3740static uint32_t
024c9045 3741skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3742{
024c9045 3743 if (!cstate->base.active)
407b50f3
DL		 3744 return 0;
3745
024c9045 3746 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3747 return 0;
407b50f3 3748
024c9045
MR		 3749 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3750 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3751}
3752
024c9045 3753static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3754 struct skl_wm_level *trans_wm /* out */)
407b50f3 3755{
024c9045 3756 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3758 struct intel_plane *intel_plane;
9414f563 3759
024c9045 3760 if (!cstate->base.active)
407b50f3 3761 return;
9414f563
DL		 3762
3763 /* Until we know more, just disable transition WMs */
024c9045
MR		 3764 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3765 int i = skl_wm_plane_id(intel_plane);
3766
9414f563 3767 trans_wm->plane_en[i] = false;
024c9045 3768 }
407b50f3
DL		 3769}
3770
55994c2c
MR		 3771static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3772 struct skl_ddb_allocation *ddb,
3773 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3774{
024c9045 3775 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3776 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3777 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3778 int ret;
2d41c0b5
PB		 3779
3780 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3781 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3782 level, &pipe_wm->wm[level]);
3783 if (ret)
3784 return ret;
2d41c0b5 3785 }
024c9045 3786 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3787
024c9045 3788 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3789
3790 return 0;
2d41c0b5
PB		 3791}
3792
3793static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3794 struct skl_pipe_wm *p_wm,
3795 struct skl_wm_values *r,
3796 struct intel_crtc *intel_crtc)
3797{
3798 int level, max_level = ilk_wm_max_level(dev);
3799 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3800 uint32_t temp;
3801 int i;
2d41c0b5
PB		 3802
3803 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3804 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3805 temp = 0;
2d41c0b5
PB		 3806
3807 temp |= p_wm->wm[level].plane_res_l[i] <<
3808 PLANE_WM_LINES_SHIFT;
3809 temp |= p_wm->wm[level].plane_res_b[i];
3810 if (p_wm->wm[level].plane_en[i])
3811 temp |= PLANE_WM_EN;
3812
3813 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3814 }
3815
3816 temp = 0;
2d41c0b5 3817
4969d33e
MR		 3818 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3819 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3820
4969d33e 3821 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3822 temp |= PLANE_WM_EN;
3823
4969d33e 3824 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3825
3826 }
3827
9414f563
DL		 3828 /* transition WMs */
3829 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3830 temp = 0;
3831 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3832 temp |= p_wm->trans_wm.plane_res_b[i];
3833 if (p_wm->trans_wm.plane_en[i])
3834 temp |= PLANE_WM_EN;
3835
3836 r->plane_trans[pipe][i] = temp;
3837 }
3838
3839 temp = 0;
4969d33e
MR		 3840 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3841 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3842 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3843 temp |= PLANE_WM_EN;
3844
4969d33e 3845 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3846
2d41c0b5
PB		 3847 r->wm_linetime[pipe] = p_wm->linetime;
3848}
3849
f0f59a00
VS		 3850static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3851 i915_reg_t reg,
16160e3d
DL		 3852 const struct skl_ddb_entry *entry)
3853{
3854 if (entry->end)
3855 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3856 else
3857 I915_WRITE(reg, 0);
3858}
3859
62e0fb88
L		 3860void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3861 const struct skl_wm_values *wm,
3862 int plane)
3863{
3864 struct drm_crtc *crtc = &intel_crtc->base;
3865 struct drm_device *dev = crtc->dev;
3866 struct drm_i915_private *dev_priv = to_i915(dev);
3867 int level, max_level = ilk_wm_max_level(dev);
3868 enum pipe pipe = intel_crtc->pipe;
3869
3870 for (level = 0; level <= max_level; level++) {
3871 I915_WRITE(PLANE_WM(pipe, plane, level),
3872 wm->plane[pipe][plane][level]);
3873 }
3874 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
27082493
L		 3875
3876 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3877 &wm->ddb.plane[pipe][plane]);
3878 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3879 &wm->ddb.y_plane[pipe][plane]);
62e0fb88
L		 3880}
3881
3882void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3883 const struct skl_wm_values *wm)
3884{
3885 struct drm_crtc *crtc = &intel_crtc->base;
3886 struct drm_device *dev = crtc->dev;
3887 struct drm_i915_private *dev_priv = to_i915(dev);
3888 int level, max_level = ilk_wm_max_level(dev);
3889 enum pipe pipe = intel_crtc->pipe;
3890
3891 for (level = 0; level <= max_level; level++) {
3892 I915_WRITE(CUR_WM(pipe, level),
3893 wm->plane[pipe][PLANE_CURSOR][level]);
3894 }
3895 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3896
27082493
L		 3897 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3898 &wm->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3899}
3900
27082493
L		 3901bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3902 const struct skl_ddb_allocation *new,
3903 enum pipe pipe)
0e8fb7ba 3904{
27082493
L		 3905 return new->pipe[pipe].start == old->pipe[pipe].start &&
3906 new->pipe[pipe].end == old->pipe[pipe].end;
0e8fb7ba
DL		 3907}
3908
27082493
L		 3909static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3910 const struct skl_ddb_entry *b)
0e8fb7ba 3911{
27082493 3912 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3913}
3914
27082493
L		 3915bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3916 const struct skl_ddb_allocation *old,
3917 const struct skl_ddb_allocation *new,
3918 enum pipe pipe)
0e8fb7ba 3919{
27082493
L		 3920 struct drm_device *dev = state->dev;
3921 struct intel_crtc *intel_crtc;
3922 enum pipe otherp;
0e8fb7ba 3923
27082493
L		 3924 for_each_intel_crtc(dev, intel_crtc) {
3925 otherp = intel_crtc->pipe;
0e8fb7ba 3926
27082493 3927 if (otherp == pipe)
0e8fb7ba
DL		 3928 continue;
3929
27082493
L		 3930 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3931 &old->pipe[otherp]))
3932 return true;
0e8fb7ba
DL		 3933 }
3934
27082493 3935 return false;
0e8fb7ba
DL		 3936}
3937
55994c2c
MR		 3938static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3939 struct skl_ddb_allocation *ddb, /* out */
3940 struct skl_pipe_wm *pipe_wm, /* out */
3941 bool *changed /* out */)
2d41c0b5 3942{
f4a96752
MR		 3943 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3944 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3945 int ret;
2d41c0b5 3946
55994c2c
MR		 3947 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3948 if (ret)
3949 return ret;
2d41c0b5 3950
4e0963c7 3951 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3952 *changed = false;
3953 else
3954 *changed = true;
2d41c0b5 3955
55994c2c 3956 return 0;
2d41c0b5
PB		 3957}
3958
9b613022
MR		 3959static uint32_t
3960pipes_modified(struct drm_atomic_state *state)
3961{
3962 struct drm_crtc *crtc;
3963 struct drm_crtc_state *cstate;
3964 uint32_t i, ret = 0;
3965
3966 for_each_crtc_in_state(state, crtc, cstate, i)
3967 ret |= drm_crtc_mask(crtc);
3968
3969 return ret;
3970}
3971
98d39494
MR		 3972static int
3973skl_compute_ddb(struct drm_atomic_state *state)
3974{
3975 struct drm_device *dev = state->dev;
3976 struct drm_i915_private *dev_priv = to_i915(dev);
3977 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3978 struct intel_crtc *intel_crtc;
734fa01f 3979 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 3980 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 3981 int ret;
3982
3983 /*
3984 * If this is our first atomic update following hardware readout,
3985 * we can't trust the DDB that the BIOS programmed for us. Let's
3986 * pretend that all pipes switched active status so that we'll
3987 * ensure a full DDB recompute.
3988 */
1b54a880
MR		 3989 if (dev_priv->wm.distrust_bios_wm) {
3990 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3991 state->acquire_ctx);
3992 if (ret)
3993 return ret;
3994
98d39494
MR		 3995 intel_state->active_pipe_changes = ~0;
3996
1b54a880
MR		 3997 /*
3998 * We usually only initialize intel_state->active_crtcs if we
3999 * we're doing a modeset; make sure this field is always
4000 * initialized during the sanitization process that happens
4001 * on the first commit too.
4002 */
4003 if (!intel_state->modeset)
4004 intel_state->active_crtcs = dev_priv->active_crtcs;
4005 }
4006
98d39494
MR		 4007 /*
4008 * If the modeset changes which CRTC's are active, we need to
4009 * recompute the DDB allocation for *all* active pipes, even
4010 * those that weren't otherwise being modified in any way by this
4011 * atomic commit. Due to the shrinking of the per-pipe allocations
4012 * when new active CRTC's are added, it's possible for a pipe that
4013 * we were already using and aren't changing at all here to suddenly
4014 * become invalid if its DDB needs exceeds its new allocation.
4015 *
4016 * Note that if we wind up doing a full DDB recompute, we can't let
4017 * any other display updates race with this transaction, so we need
4018 * to grab the lock on *all* CRTC's.
4019 */
734fa01f 4020 if (intel_state->active_pipe_changes) {
98d39494 4021 realloc_pipes = ~0;
734fa01f
MR		 4022 intel_state->wm_results.dirty_pipes = ~0;
4023 }
98d39494
MR		 4024
4025 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4026 struct intel_crtc_state *cstate;
4027
4028 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4029 if (IS_ERR(cstate))
4030 return PTR_ERR(cstate);
4031
734fa01f 4032 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4033 if (ret)
4034 return ret;
05a76d3d
L		 4035
4036 ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
4037 if (ret)
4038 return ret;
98d39494
MR		 4039 }
4040
4041 return 0;
4042}
4043
2722efb9
MR		 4044static void
4045skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4046 struct skl_wm_values *src,
4047 enum pipe pipe)
4048{
4049 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4050 memcpy(dst->plane[pipe], src->plane[pipe],
4051 sizeof(dst->plane[pipe]));
4052 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4053 sizeof(dst->plane_trans[pipe]));
4054
4055 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4056 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4057 sizeof(dst->ddb.y_plane[pipe]));
4058 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4059 sizeof(dst->ddb.plane[pipe]));
4060}
4061
98d39494
MR		 4062static int
4063skl_compute_wm(struct drm_atomic_state *state)
4064{
4065 struct drm_crtc *crtc;
4066 struct drm_crtc_state *cstate;
734fa01f
MR		 4067 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4068 struct skl_wm_values *results = &intel_state->wm_results;
4069 struct skl_pipe_wm *pipe_wm;
98d39494 4070 bool changed = false;
734fa01f 4071 int ret, i;
98d39494
MR		 4072
4073 /*
4074 * If this transaction isn't actually touching any CRTC's, don't
4075 * bother with watermark calculation. Note that if we pass this
4076 * test, we're guaranteed to hold at least one CRTC state mutex,
4077 * which means we can safely use values like dev_priv->active_crtcs
4078 * since any racing commits that want to update them would need to
4079 * hold _all_ CRTC state mutexes.
4080 */
4081 for_each_crtc_in_state(state, crtc, cstate, i)
4082 changed = true;
4083 if (!changed)
4084 return 0;
4085
734fa01f
MR		 4086 /* Clear all dirty flags */
4087 results->dirty_pipes = 0;
4088
98d39494
MR		 4089 ret = skl_compute_ddb(state);
4090 if (ret)
4091 return ret;
4092
734fa01f
MR		 4093 /*
4094 * Calculate WM's for all pipes that are part of this transaction.
4095 * Note that the DDB allocation above may have added more CRTC's that
4096 * weren't otherwise being modified (and set bits in dirty_pipes) if
4097 * pipe allocations had to change.
4098 *
4099 * FIXME: Now that we're doing this in the atomic check phase, we
4100 * should allow skl_update_pipe_wm() to return failure in cases where
4101 * no suitable watermark values can be found.
4102 */
4103 for_each_crtc_in_state(state, crtc, cstate, i) {
4104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4105 struct intel_crtc_state *intel_cstate =
4106 to_intel_crtc_state(cstate);
4107
4108 pipe_wm = &intel_cstate->wm.skl.optimal;
4109 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4110 &changed);
4111 if (ret)
4112 return ret;
4113
4114 if (changed)
4115 results->dirty_pipes |= drm_crtc_mask(crtc);
4116
4117 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4118 /* This pipe's WM's did not change */
4119 continue;
4120
4121 intel_cstate->update_wm_pre = true;
4122 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4123 }
4124
98d39494
MR		 4125 return 0;
4126}
4127
2d41c0b5
PB		 4128static void skl_update_wm(struct drm_crtc *crtc)
4129{
4130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4131 struct drm_device *dev = crtc->dev;
fac5e23e 4132 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4133 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4134 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4135 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4136 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4137 enum pipe pipe = intel_crtc->pipe;
adda50b8 4138
734fa01f 4139 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4140 return;
4141
734fa01f
MR		 4142 intel_crtc->wm.active.skl = *pipe_wm;
4143
4144 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4145
2722efb9 4146 /*
27082493
L		 4147 * If this pipe isn't active already, we're going to be enabling it
4148 * very soon. Since it's safe to update a pipe's ddb allocation while
4149 * the pipe's shut off, just do so here. Already active pipes will have
4150 * their watermarks updated once we update their planes.
2722efb9 4151 */
27082493
L		 4152 if (crtc->state->active_changed) {
4153 int plane;
4154
4155 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4156 skl_write_plane_wm(intel_crtc, results, plane);
4157
4158 skl_write_cursor_wm(intel_crtc, results);
4159 }
4160
4161 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4162
4163 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4164}
4165
d890565c
VS		 4166static void ilk_compute_wm_config(struct drm_device *dev,
4167 struct intel_wm_config *config)
4168{
4169 struct intel_crtc *crtc;
4170
4171 /* Compute the currently _active_ config */
4172 for_each_intel_crtc(dev, crtc) {
4173 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4174
4175 if (!wm->pipe_enabled)
4176 continue;
4177
4178 config->sprites_enabled |= wm->sprites_enabled;
4179 config->sprites_scaled |= wm->sprites_scaled;
4180 config->num_pipes_active++;
4181 }
4182}
4183
ed4a6a7c 4184static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4185{
91c8a326 4186 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4187 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4188 struct ilk_wm_maximums max;
d890565c 4189 struct intel_wm_config config = {};
820c1980 4190 struct ilk_wm_values results = {};
77c122bc 4191 enum intel_ddb_partitioning partitioning;
261a27d1 4192
d890565c
VS		 4193 ilk_compute_wm_config(dev, &config);
4194
4195 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4196 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4197
4198 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4199 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4200 config.num_pipes_active == 1 && config.sprites_enabled) {
4201 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4202 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4203
820c1980 4204 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4205 } else {
198a1e9b 4206 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4207 }
4208
198a1e9b 4209 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4210 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4211
820c1980 4212 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4213
820c1980 4214 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4215}
4216
ed4a6a7c 4217static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4218{
ed4a6a7c
MR		 4219 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4220 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4221
ed4a6a7c 4222 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4223 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4224 ilk_program_watermarks(dev_priv);
4225 mutex_unlock(&dev_priv->wm.wm_mutex);
4226}
bf220452 4227
ed4a6a7c
MR		 4228static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4229{
4230 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4231 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4232
ed4a6a7c
MR		 4233 mutex_lock(&dev_priv->wm.wm_mutex);
4234 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4235 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4236 ilk_program_watermarks(dev_priv);
4237 }
4238 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4239}
4240
3078999f
PB		 4241static void skl_pipe_wm_active_state(uint32_t val,
4242 struct skl_pipe_wm *active,
4243 bool is_transwm,
4244 bool is_cursor,
4245 int i,
4246 int level)
4247{
4248 bool is_enabled = (val & PLANE_WM_EN) != 0;
4249
4250 if (!is_transwm) {
4251 if (!is_cursor) {
4252 active->wm[level].plane_en[i] = is_enabled;
4253 active->wm[level].plane_res_b[i] =
4254 val & PLANE_WM_BLOCKS_MASK;
4255 active->wm[level].plane_res_l[i] =
4256 (val >> PLANE_WM_LINES_SHIFT) &
4257 PLANE_WM_LINES_MASK;
4258 } else {
4969d33e
MR		 4259 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4260 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4261 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4262 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4263 (val >> PLANE_WM_LINES_SHIFT) &
4264 PLANE_WM_LINES_MASK;
4265 }
4266 } else {
4267 if (!is_cursor) {
4268 active->trans_wm.plane_en[i] = is_enabled;
4269 active->trans_wm.plane_res_b[i] =
4270 val & PLANE_WM_BLOCKS_MASK;
4271 active->trans_wm.plane_res_l[i] =
4272 (val >> PLANE_WM_LINES_SHIFT) &
4273 PLANE_WM_LINES_MASK;
4274 } else {
4969d33e
MR		 4275 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4276 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4277 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4278 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4279 (val >> PLANE_WM_LINES_SHIFT) &
4280 PLANE_WM_LINES_MASK;
4281 }
4282 }
4283}
4284
4285static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4286{
4287 struct drm_device *dev = crtc->dev;
fac5e23e 4288 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4289 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4291 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4292 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4293 enum pipe pipe = intel_crtc->pipe;
4294 int level, i, max_level;
4295 uint32_t temp;
4296
4297 max_level = ilk_wm_max_level(dev);
4298
4299 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4300
4301 for (level = 0; level <= max_level; level++) {
4302 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4303 hw->plane[pipe][i][level] =
4304 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4305 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4306 }
4307
4308 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4309 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4310 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4311
3ef00284 4312 if (!intel_crtc->active)
3078999f
PB		 4313 return;
4314
2b4b9f35 4315 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4316
4317 active->linetime = hw->wm_linetime[pipe];
4318
4319 for (level = 0; level <= max_level; level++) {
4320 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4321 temp = hw->plane[pipe][i][level];
4322 skl_pipe_wm_active_state(temp, active, false,
4323 false, i, level);
4324 }
4969d33e 4325 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4326 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4327 }
4328
4329 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4330 temp = hw->plane_trans[pipe][i];
4331 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4332 }
4333
4969d33e 4334 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4335 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4336
4337 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4338}
4339
4340void skl_wm_get_hw_state(struct drm_device *dev)
4341{
fac5e23e 4342 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4343 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4344 struct drm_crtc *crtc;
4345
a269c583 4346 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4347 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4348 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4349
279e99d7
MR		 4350 if (dev_priv->active_crtcs) {
4351 /* Fully recompute DDB on first atomic commit */
4352 dev_priv->wm.distrust_bios_wm = true;
4353 } else {
4354 /* Easy/common case; just sanitize DDB now if everything off */
4355 memset(ddb, 0, sizeof(*ddb));
4356 }
3078999f
PB		 4357}
4358
243e6a44
VS		 4359static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4360{
4361 struct drm_device *dev = crtc->dev;
fac5e23e 4362 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4363 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4365 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4366 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4367 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4368 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4369 [PIPE_A] = WM0_PIPEA_ILK,
4370 [PIPE_B] = WM0_PIPEB_ILK,
4371 [PIPE_C] = WM0_PIPEC_IVB,
4372 };
4373
4374 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4375 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4376 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4377
15606534
VS		 4378 memset(active, 0, sizeof(*active));
4379
3ef00284 4380 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4381
4382 if (active->pipe_enabled) {
243e6a44
VS		 4383 u32 tmp = hw->wm_pipe[pipe];
4384
4385 /*
4386 * For active pipes LP0 watermark is marked as
4387 * enabled, and LP1+ watermaks as disabled since
4388 * we can't really reverse compute them in case
4389 * multiple pipes are active.
4390 */
4391 active->wm[0].enable = true;
4392 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4393 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4394 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4395 active->linetime = hw->wm_linetime[pipe];
4396 } else {
4397 int level, max_level = ilk_wm_max_level(dev);
4398
4399 /*
4400 * For inactive pipes, all watermark levels
4401 * should be marked as enabled but zeroed,
4402 * which is what we'd compute them to.
4403 */
4404 for (level = 0; level <= max_level; level++)
4405 active->wm[level].enable = true;
4406 }
4e0963c7
MR		 4407
4408 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4409}
4410
6eb1a681
VS		 4411#define _FW_WM(value, plane) \
4412 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4413#define _FW_WM_VLV(value, plane) \
4414 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4415
4416static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4417 struct vlv_wm_values *wm)
4418{
4419 enum pipe pipe;
4420 uint32_t tmp;
4421
4422 for_each_pipe(dev_priv, pipe) {
4423 tmp = I915_READ(VLV_DDL(pipe));
4424
4425 wm->ddl[pipe].primary =
4426 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4427 wm->ddl[pipe].cursor =
4428 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4429 wm->ddl[pipe].sprite[0] =
4430 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4431 wm->ddl[pipe].sprite[1] =
4432 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4433 }
4434
4435 tmp = I915_READ(DSPFW1);
4436 wm->sr.plane = _FW_WM(tmp, SR);
4437 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4438 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4439 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4440
4441 tmp = I915_READ(DSPFW2);
4442 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4443 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4444 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4445
4446 tmp = I915_READ(DSPFW3);
4447 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4448
4449 if (IS_CHERRYVIEW(dev_priv)) {
4450 tmp = I915_READ(DSPFW7_CHV);
4451 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4452 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4453
4454 tmp = I915_READ(DSPFW8_CHV);
4455 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4456 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4457
4458 tmp = I915_READ(DSPFW9_CHV);
4459 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4460 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4461
4462 tmp = I915_READ(DSPHOWM);
4463 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4464 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4465 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4466 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4467 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4468 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4469 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4470 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4471 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4472 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4473 } else {
4474 tmp = I915_READ(DSPFW7);
4475 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4476 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4477
4478 tmp = I915_READ(DSPHOWM);
4479 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4480 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4481 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4482 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4483 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4484 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4485 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4486 }
4487}
4488
4489#undef _FW_WM
4490#undef _FW_WM_VLV
4491
4492void vlv_wm_get_hw_state(struct drm_device *dev)
4493{
4494 struct drm_i915_private *dev_priv = to_i915(dev);
4495 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4496 struct intel_plane *plane;
4497 enum pipe pipe;
4498 u32 val;
4499
4500 vlv_read_wm_values(dev_priv, wm);
4501
4502 for_each_intel_plane(dev, plane) {
4503 switch (plane->base.type) {
4504 int sprite;
4505 case DRM_PLANE_TYPE_CURSOR:
4506 plane->wm.fifo_size = 63;
4507 break;
4508 case DRM_PLANE_TYPE_PRIMARY:
4509 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4510 break;
4511 case DRM_PLANE_TYPE_OVERLAY:
4512 sprite = plane->plane;
4513 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4514 break;
4515 }
4516 }
4517
4518 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4519 wm->level = VLV_WM_LEVEL_PM2;
4520
4521 if (IS_CHERRYVIEW(dev_priv)) {
4522 mutex_lock(&dev_priv->rps.hw_lock);
4523
4524 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4525 if (val & DSP_MAXFIFO_PM5_ENABLE)
4526 wm->level = VLV_WM_LEVEL_PM5;
4527
58590c14
VS		 4528 /*
4529 * If DDR DVFS is disabled in the BIOS, Punit
4530 * will never ack the request. So if that happens
4531 * assume we don't have to enable/disable DDR DVFS
4532 * dynamically. To test that just set the REQ_ACK
4533 * bit to poke the Punit, but don't change the
4534 * HIGH/LOW bits so that we don't actually change
4535 * the current state.
4536 */
6eb1a681 4537 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4538 val |= FORCE_DDR_FREQ_REQ_ACK;
4539 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4540
4541 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4542 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4543 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4544 "assuming DDR DVFS is disabled\n");
4545 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4546 } else {
4547 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4548 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4549 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4550 }
6eb1a681
VS		 4551
4552 mutex_unlock(&dev_priv->rps.hw_lock);
4553 }
4554
4555 for_each_pipe(dev_priv, pipe)
4556 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4557 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4558 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4559
4560 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4561 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4562}
4563
243e6a44
VS		 4564void ilk_wm_get_hw_state(struct drm_device *dev)
4565{
fac5e23e 4566 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4567 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4568 struct drm_crtc *crtc;
4569
70e1e0ec 4570 for_each_crtc(dev, crtc)
243e6a44
VS		 4571 ilk_pipe_wm_get_hw_state(crtc);
4572
4573 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4574 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4575 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4576
4577 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4578 if (INTEL_INFO(dev)->gen >= 7) {
4579 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4580 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4581 }
243e6a44 4582
a42a5719 4583 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4584 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4585 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4586 else if (IS_IVYBRIDGE(dev))
4587 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4588 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4589
4590 hw->enable_fbc_wm =
4591 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4592}
4593
b445e3b0
ED		 4594/**
4595 * intel_update_watermarks - update FIFO watermark values based on current modes
4596 *
4597 * Calculate watermark values for the various WM regs based on current mode
4598 * and plane configuration.
4599 *
4600 * There are several cases to deal with here:
4601 * - normal (i.e. non-self-refresh)
4602 * - self-refresh (SR) mode
4603 * - lines are large relative to FIFO size (buffer can hold up to 2)
4604 * - lines are small relative to FIFO size (buffer can hold more than 2
4605 * lines), so need to account for TLB latency
4606 *
4607 * The normal calculation is:
4608 * watermark = dotclock * bytes per pixel * latency
4609 * where latency is platform & configuration dependent (we assume pessimal
4610 * values here).
4611 *
4612 * The SR calculation is:
4613 * watermark = (trunc(latency/line time)+1) * surface width *
4614 * bytes per pixel
4615 * where
4616 * line time = htotal / dotclock
4617 * surface width = hdisplay for normal plane and 64 for cursor
4618 * and latency is assumed to be high, as above.
4619 *
4620 * The final value programmed to the register should always be rounded up,
4621 * and include an extra 2 entries to account for clock crossings.
4622 *
4623 * We don't use the sprite, so we can ignore that. And on Crestline we have
4624 * to set the non-SR watermarks to 8.
4625 */
46ba614c 4626void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4627{
fac5e23e 4628 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4629
4630 if (dev_priv->display.update_wm)
46ba614c 4631 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4632}
4633
e2828914 4634/*
9270388e 4635 * Lock protecting IPS related data structures
9270388e
DV		 4636 */
4637DEFINE_SPINLOCK(mchdev_lock);
4638
4639/* Global for IPS driver to get at the current i915 device. Protected by
4640 * mchdev_lock. */
4641static struct drm_i915_private *i915_mch_dev;
4642
91d14251 4643bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4644{
2b4e57bd
ED		 4645 u16 rgvswctl;
4646
9270388e
DV		 4647 assert_spin_locked(&mchdev_lock);
4648
2b4e57bd
ED		 4649 rgvswctl = I915_READ16(MEMSWCTL);
4650 if (rgvswctl & MEMCTL_CMD_STS) {
4651 DRM_DEBUG("gpu busy, RCS change rejected\n");
4652 return false; /* still busy with another command */
4653 }
4654
4655 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4656 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4657 I915_WRITE16(MEMSWCTL, rgvswctl);
4658 POSTING_READ16(MEMSWCTL);
4659
4660 rgvswctl |= MEMCTL_CMD_STS;
4661 I915_WRITE16(MEMSWCTL, rgvswctl);
4662
4663 return true;
4664}
4665
91d14251 4666static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4667{
84f1b20f 4668 u32 rgvmodectl;
2b4e57bd
ED		 4669 u8 fmax, fmin, fstart, vstart;
4670
9270388e
DV		 4671 spin_lock_irq(&mchdev_lock);
4672
84f1b20f
TU		 4673 rgvmodectl = I915_READ(MEMMODECTL);
4674
2b4e57bd
ED		 4675 /* Enable temp reporting */
4676 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4677 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4678
4679 /* 100ms RC evaluation intervals */
4680 I915_WRITE(RCUPEI, 100000);
4681 I915_WRITE(RCDNEI, 100000);
4682
4683 /* Set max/min thresholds to 90ms and 80ms respectively */
4684 I915_WRITE(RCBMAXAVG, 90000);
4685 I915_WRITE(RCBMINAVG, 80000);
4686
4687 I915_WRITE(MEMIHYST, 1);
4688
4689 /* Set up min, max, and cur for interrupt handling */
4690 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4691 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4692 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4693 MEMMODE_FSTART_SHIFT;
4694
616847e7 4695 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4696 PXVFREQ_PX_SHIFT;
4697
20e4d407
DV		 4698 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4699 dev_priv->ips.fstart = fstart;
2b4e57bd 4700
20e4d407
DV		 4701 dev_priv->ips.max_delay = fstart;
4702 dev_priv->ips.min_delay = fmin;
4703 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4704
4705 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4706 fmax, fmin, fstart);
4707
4708 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4709
4710 /*
4711 * Interrupts will be enabled in ironlake_irq_postinstall
4712 */
4713
4714 I915_WRITE(VIDSTART, vstart);
4715 POSTING_READ(VIDSTART);
4716
4717 rgvmodectl |= MEMMODE_SWMODE_EN;
4718 I915_WRITE(MEMMODECTL, rgvmodectl);
4719
9270388e 4720 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4721 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4722 mdelay(1);
2b4e57bd 4723
91d14251 4724 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4725
7d81c3e0
VS		 4726 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4727 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4728 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4729 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4730 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4731
4732 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4733}
4734
91d14251 4735static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4736{
9270388e
DV		 4737 u16 rgvswctl;
4738
4739 spin_lock_irq(&mchdev_lock);
4740
4741 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4742
4743 /* Ack interrupts, disable EFC interrupt */
4744 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4745 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4746 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4747 I915_WRITE(DEIIR, DE_PCU_EVENT);
4748 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4749
4750 /* Go back to the starting frequency */
91d14251 4751 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4752 mdelay(1);
2b4e57bd
ED		 4753 rgvswctl |= MEMCTL_CMD_STS;
4754 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4755 mdelay(1);
2b4e57bd 4756
9270388e 4757 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4758}
4759
acbe9475
DV		 4760/* There's a funny hw issue where the hw returns all 0 when reading from
4761 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4762 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4763 * all limits and the gpu stuck at whatever frequency it is at atm).
4764 */
74ef1173 4765static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4766{
7b9e0ae6 4767 u32 limits;
2b4e57bd 4768
20b46e59
DV		 4769 /* Only set the down limit when we've reached the lowest level to avoid
4770 * getting more interrupts, otherwise leave this clear. This prevents a
4771 * race in the hw when coming out of rc6: There's a tiny window where
4772 * the hw runs at the minimal clock before selecting the desired
4773 * frequency, if the down threshold expires in that window we will not
4774 * receive a down interrupt. */
2d1fe073 4775 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4776 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4777 if (val <= dev_priv->rps.min_freq_softlimit)
4778 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4779 } else {
4780 limits = dev_priv->rps.max_freq_softlimit << 24;
4781 if (val <= dev_priv->rps.min_freq_softlimit)
4782 limits |= dev_priv->rps.min_freq_softlimit << 16;
4783 }
20b46e59
DV		 4784
4785 return limits;
4786}
4787
dd75fdc8
CW		 4788static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4789{
4790 int new_power;
8a586437
AG		 4791 u32 threshold_up = 0, threshold_down = 0; /* in % */
4792 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4793
4794 new_power = dev_priv->rps.power;
4795 switch (dev_priv->rps.power) {
4796 case LOW_POWER:
a72b5623
CW		 4797 if (val > dev_priv->rps.efficient_freq + 1 &&
4798 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4799 new_power = BETWEEN;
4800 break;
4801
4802 case BETWEEN:
a72b5623
CW		 4803 if (val <= dev_priv->rps.efficient_freq &&
4804 val < dev_priv->rps.cur_freq)
dd75fdc8 4805 new_power = LOW_POWER;
a72b5623
CW		 4806 else if (val >= dev_priv->rps.rp0_freq &&
4807 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4808 new_power = HIGH_POWER;
4809 break;
4810
4811 case HIGH_POWER:
a72b5623
CW		 4812 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4813 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4814 new_power = BETWEEN;
4815 break;
4816 }
4817 /* Max/min bins are special */
aed242ff 4818 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4819 new_power = LOW_POWER;
aed242ff 4820 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4821 new_power = HIGH_POWER;
4822 if (new_power == dev_priv->rps.power)
4823 return;
4824
4825 /* Note the units here are not exactly 1us, but 1280ns. */
4826 switch (new_power) {
4827 case LOW_POWER:
4828 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4829 ei_up = 16000;
4830 threshold_up = 95;
dd75fdc8
CW		 4831
4832 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4833 ei_down = 32000;
4834 threshold_down = 85;
dd75fdc8
CW		 4835 break;
4836
4837 case BETWEEN:
4838 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4839 ei_up = 13000;
4840 threshold_up = 90;
dd75fdc8
CW		 4841
4842 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4843 ei_down = 32000;
4844 threshold_down = 75;
dd75fdc8
CW		 4845 break;
4846
4847 case HIGH_POWER:
4848 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4849 ei_up = 10000;
4850 threshold_up = 85;
dd75fdc8
CW		 4851
4852 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4853 ei_down = 32000;
4854 threshold_down = 60;
dd75fdc8
CW		 4855 break;
4856 }
4857
8a586437 4858 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4859 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4860 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4861 GT_INTERVAL_FROM_US(dev_priv,
4862 ei_up * threshold_up / 100));
8a586437
AG		 4863
4864 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4865 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4866 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4867 GT_INTERVAL_FROM_US(dev_priv,
4868 ei_down * threshold_down / 100));
4869
4870 I915_WRITE(GEN6_RP_CONTROL,
4871 GEN6_RP_MEDIA_TURBO |
4872 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4873 GEN6_RP_MEDIA_IS_GFX |
4874 GEN6_RP_ENABLE |
4875 GEN6_RP_UP_BUSY_AVG |
4876 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4877
dd75fdc8 4878 dev_priv->rps.power = new_power;
8fb55197
CW		 4879 dev_priv->rps.up_threshold = threshold_up;
4880 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4881 dev_priv->rps.last_adj = 0;
4882}
4883
2876ce73
CW		 4884static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4885{
4886 u32 mask = 0;
4887
4888 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4889 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4890 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4891 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4892
7b3c29f6
CW		 4893 mask &= dev_priv->pm_rps_events;
4894
59d02a1f 4895 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4896}
4897
b8a5ff8d
JM		 4898/* gen6_set_rps is called to update the frequency request, but should also be
4899 * called when the range (min_delay and max_delay) is modified so that we can
4900 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4901static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4902{
23eafea6 4903 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4904 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4905 return;
4906
4fc688ce 4907 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4908 WARN_ON(val > dev_priv->rps.max_freq);
4909 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4910
eb64cad1
CW		 4911 /* min/max delay may still have been modified so be sure to
4912 * write the limits value.
4913 */
4914 if (val != dev_priv->rps.cur_freq) {
4915 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4916
dc97997a 4917 if (IS_GEN9(dev_priv))
5704195c
AG		 4918 I915_WRITE(GEN6_RPNSWREQ,
4919 GEN9_FREQUENCY(val));
dc97997a 4920 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4921 I915_WRITE(GEN6_RPNSWREQ,
4922 HSW_FREQUENCY(val));
4923 else
4924 I915_WRITE(GEN6_RPNSWREQ,
4925 GEN6_FREQUENCY(val) |
4926 GEN6_OFFSET(0) |
4927 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4928 }
7b9e0ae6 4929
7b9e0ae6
CW		 4930 /* Make sure we continue to get interrupts
4931 * until we hit the minimum or maximum frequencies.
4932 */
74ef1173 4933 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4934 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4935
d5570a72
BW		 4936 POSTING_READ(GEN6_RPNSWREQ);
4937
b39fb297 4938 dev_priv->rps.cur_freq = val;
0f94592e 4939 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4940}
4941
dc97997a 4942static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4943{
ffe02b40 4944 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4945 WARN_ON(val > dev_priv->rps.max_freq);
4946 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4947
dc97997a 4948 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4949 "Odd GPU freq value\n"))
4950 val &= ~1;
4951
cd25dd5b
D		 4952 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4953
8fb55197 4954 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4955 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4956 if (!IS_CHERRYVIEW(dev_priv))
4957 gen6_set_rps_thresholds(dev_priv, val);
4958 }
ffe02b40 4959
ffe02b40
VS		 4960 dev_priv->rps.cur_freq = val;
4961 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4962}
4963
a7f6e231 4964/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4965 *
4966 * * If Gfx is Idle, then
a7f6e231
D		 4967 * 1. Forcewake Media well.
4968 * 2. Request idle freq.
4969 * 3. Release Forcewake of Media well.
76c3552f
D		 4970*/
4971static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4972{
aed242ff 4973 u32 val = dev_priv->rps.idle_freq;
5549d25f 4974
aed242ff 4975 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4976 return;
4977
a7f6e231
D		 4978 /* Wake up the media well, as that takes a lot less
4979 * power than the Render well. */
4980 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 4981 valleyview_set_rps(dev_priv, val);
a7f6e231 4982 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4983}
4984
43cf3bf0
CW		 4985void gen6_rps_busy(struct drm_i915_private *dev_priv)
4986{
4987 mutex_lock(&dev_priv->rps.hw_lock);
4988 if (dev_priv->rps.enabled) {
4989 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4990 gen6_rps_reset_ei(dev_priv);
4991 I915_WRITE(GEN6_PMINTRMSK,
4992 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 4993
c33d247d
CW		 4994 gen6_enable_rps_interrupts(dev_priv);
4995
2b83c4c4
MW		 4996 /* Ensure we start at the user's desired frequency */
4997 intel_set_rps(dev_priv,
4998 clamp(dev_priv->rps.cur_freq,
4999 dev_priv->rps.min_freq_softlimit,
5000 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5001 }
5002 mutex_unlock(&dev_priv->rps.hw_lock);
5003}
5004
b29c19b6
CW		 5005void gen6_rps_idle(struct drm_i915_private *dev_priv)
5006{
c33d247d
CW		 5007 /* Flush our bottom-half so that it does not race with us
5008 * setting the idle frequency and so that it is bounded by
5009 * our rpm wakeref. And then disable the interrupts to stop any
5010 * futher RPS reclocking whilst we are asleep.
5011 */
5012 gen6_disable_rps_interrupts(dev_priv);
5013
b29c19b6 5014 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5015 if (dev_priv->rps.enabled) {
dc97997a 5016 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5017 vlv_set_rps_idle(dev_priv);
7526ed79 5018 else
dc97997a 5019 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5020 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5021 I915_WRITE(GEN6_PMINTRMSK,
5022 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5023 }
8d3afd7d 5024 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5025
8d3afd7d 5026 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5027 while (!list_empty(&dev_priv->rps.clients))
5028 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5029 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5030}
5031
1854d5ca 5032void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5033 struct intel_rps_client *rps,
5034 unsigned long submitted)
b29c19b6 5035{
8d3afd7d
CW		 5036 /* This is intentionally racy! We peek at the state here, then
5037 * validate inside the RPS worker.
5038 */
67d97da3 5039 if (!(dev_priv->gt.awake &&
8d3afd7d 5040 dev_priv->rps.enabled &&
29ecd78d 5041 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5042 return;
43cf3bf0 5043
e61b9958
CW		 5044 /* Force a RPS boost (and don't count it against the client) if
5045 * the GPU is severely congested.
5046 */
d0bc54f2 5047 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5048 rps = NULL;
5049
8d3afd7d
CW		 5050 spin_lock(&dev_priv->rps.client_lock);
5051 if (rps == NULL || list_empty(&rps->link)) {
5052 spin_lock_irq(&dev_priv->irq_lock);
5053 if (dev_priv->rps.interrupts_enabled) {
5054 dev_priv->rps.client_boost = true;
c33d247d 5055 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5056 }
5057 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5058
2e1b8730
CW		 5059 if (rps != NULL) {
5060 list_add(&rps->link, &dev_priv->rps.clients);
5061 rps->boosts++;
1854d5ca
CW		 5062 } else
5063 dev_priv->rps.boosts++;
c0951f0c 5064 }
8d3afd7d 5065 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5066}
5067
dc97997a 5068void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5069{
dc97997a
CW		 5070 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5071 valleyview_set_rps(dev_priv, val);
ffe02b40 5072 else
dc97997a 5073 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5074}
5075
dc97997a 5076static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5077{
20e49366 5078 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5079 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5080}
5081
dc97997a 5082static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5083{
2030d684
AG		 5084 I915_WRITE(GEN6_RP_CONTROL, 0);
5085}
5086
dc97997a 5087static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5088{
d20d4f0c 5089 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5090 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5091 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5092}
5093
dc97997a 5094static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5095{
38807746
D		 5096 I915_WRITE(GEN6_RC_CONTROL, 0);
5097}
5098
dc97997a 5099static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5100{
98a2e5f9
D		 5101 /* we're doing forcewake before Disabling RC6,
5102 * This what the BIOS expects when going into suspend */
59bad947 5103 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5104
44fc7d5c 5105 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5106
59bad947 5107 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5108}
5109
dc97997a 5110static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5111{
dc97997a 5112 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5113 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5114 mode = GEN6_RC_CTL_RC6_ENABLE;
5115 else
5116 mode = 0;
5117 }
dc97997a 5118 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5119 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5120 "RC6 %s RC6p %s RC6pp %s\n",
5121 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5122 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5123 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5124
5125 else
b99d49cc
ID		 5126 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5127 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5128}
5129
dc97997a 5130static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5131{
72e96d64 5132 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5133 bool enable_rc6 = true;
5134 unsigned long rc6_ctx_base;
fc619841
ID		 5135 u32 rc_ctl;
5136 int rc_sw_target;
5137
5138 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5139 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5140 RC_SW_TARGET_STATE_SHIFT;
5141 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5142 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5143 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5144 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5145 rc_sw_target);
274008e8
SAK		 5146
5147 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5148 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5149 enable_rc6 = false;
5150 }
5151
5152 /*
5153 * The exact context size is not known for BXT, so assume a page size
5154 * for this check.
5155 */
5156 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5157 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5158 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5159 ggtt->stolen_reserved_size))) {
b99d49cc 5160 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5161 enable_rc6 = false;
5162 }
5163
5164 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5165 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5166 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5167 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5168 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5169 enable_rc6 = false;
5170 }
5171
fc619841
ID		 5172 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5173 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5174 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5175 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5176 enable_rc6 = false;
5177 }
5178
5179 if (!I915_READ(GEN6_GFXPAUSE)) {
5180 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5181 enable_rc6 = false;
5182 }
5183
5184 if (!I915_READ(GEN8_MISC_CTRL0)) {
5185 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5186 enable_rc6 = false;
5187 }
5188
5189 return enable_rc6;
5190}
5191
dc97997a 5192int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5193{
e7d66d89 5194 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5195 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5196 return 0;
5197
274008e8
SAK		 5198 if (!enable_rc6)
5199 return 0;
5200
dc97997a 5201 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5202 DRM_INFO("RC6 disabled by BIOS\n");
5203 return 0;
5204 }
5205
456470eb 5206 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5207 if (enable_rc6 >= 0) {
5208 int mask;
5209
dc97997a 5210 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5211 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5212 INTEL_RC6pp_ENABLE;
5213 else
5214 mask = INTEL_RC6_ENABLE;
5215
5216 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5217 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5218 "(requested %d, valid %d)\n",
5219 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5220
5221 return enable_rc6 & mask;
5222 }
2b4e57bd 5223
dc97997a 5224 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5225 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5226
5227 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5228}
5229
dc97997a 5230static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5231{
5232 /* All of these values are in units of 50MHz */
773ea9a8 5233
93ee2920 5234 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5235 if (IS_BROXTON(dev_priv)) {
773ea9a8 5236 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5237 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5238 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5239 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5240 } else {
773ea9a8 5241 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5242 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5243 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5244 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5245 }
3280e8b0 5246 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5247 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5248
93ee2920 5249 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5250 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5251 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5252 u32 ddcc_status = 0;
5253
5254 if (sandybridge_pcode_read(dev_priv,
5255 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5256 &ddcc_status) == 0)
93ee2920 5257 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5258 clamp_t(u8,
5259 ((ddcc_status >> 8) & 0xff),
5260 dev_priv->rps.min_freq,
5261 dev_priv->rps.max_freq);
93ee2920
TR		 5262 }
5263
dc97997a 5264 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5265 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5266 * the natural hardware unit for SKL
5267 */
c5e0688c
AG		 5268 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5269 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5270 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5271 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5272 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5273 }
3280e8b0
BW		 5274}
5275
3a45b05c
CW		 5276static void reset_rps(struct drm_i915_private *dev_priv,
5277 void (*set)(struct drm_i915_private *, u8))
5278{
5279 u8 freq = dev_priv->rps.cur_freq;
5280
5281 /* force a reset */
5282 dev_priv->rps.power = -1;
5283 dev_priv->rps.cur_freq = -1;
5284
5285 set(dev_priv, freq);
5286}
5287
b6fef0ef 5288/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5289static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5290{
b6fef0ef
JB		 5291 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5292
23eafea6 5293 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5294 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5295 /*
5296 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5297 * clear out the Control register just to avoid inconsitency
5298 * with debugfs interface, which will show Turbo as enabled
5299 * only and that is not expected by the User after adding the
5300 * WaGsvDisableTurbo. Apart from this there is no problem even
5301 * if the Turbo is left enabled in the Control register, as the
5302 * Up/Down interrupts would remain masked.
5303 */
dc97997a 5304 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5305 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5306 return;
5307 }
5308
0beb059a
AG		 5309 /* Program defaults and thresholds for RPS*/
5310 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5311 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5312
5313 /* 1 second timeout*/
5314 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5315 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5316
b6fef0ef 5317 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5318
0beb059a
AG		 5319 /* Leaning on the below call to gen6_set_rps to program/setup the
5320 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5321 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5322 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5323
5324 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5325}
5326
dc97997a 5327static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5328{
e2f80391 5329 struct intel_engine_cs *engine;
20e49366 5330 uint32_t rc6_mask = 0;
20e49366
ZW		 5331
5332 /* 1a: Software RC state - RC0 */
5333 I915_WRITE(GEN6_RC_STATE, 0);
5334
5335 /* 1b: Get forcewake during program sequence. Although the driver
5336 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5337 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5338
5339 /* 2a: Disable RC states. */
5340 I915_WRITE(GEN6_RC_CONTROL, 0);
5341
5342 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5343
5344 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5345 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5346 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5347 else
5348 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5349 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5350 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5351 for_each_engine(engine, dev_priv)
e2f80391 5352 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5353
1a3d1898 5354 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5355 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5356
20e49366 5357 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5358
38c23527
ZW		 5359 /* 2c: Program Coarse Power Gating Policies. */
5360 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5361 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5362
20e49366 5363 /* 3a: Enable RC6 */
dc97997a 5364 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5365 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5366 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 5367 /* WaRsUseTimeoutMode */
dc97997a
CW		 5368 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5369 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5370 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5371 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5372 GEN7_RC_CTL_TO_MODE |
5373 rc6_mask);
3e7732a0
SAK		 5374 } else {
5375 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5376 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5377 GEN6_RC_CTL_EI_MODE(1) |
5378 rc6_mask);
3e7732a0 5379 }
20e49366 5380
cb07bae0
SK		 5381 /*
5382 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5383 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5384 */
dc97997a 5385 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5386 I915_WRITE(GEN9_PG_ENABLE, 0);
5387 else
5388 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5389 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5390
59bad947 5391 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5392}
5393
dc97997a 5394static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5395{
e2f80391 5396 struct intel_engine_cs *engine;
93ee2920 5397 uint32_t rc6_mask = 0;
6edee7f3
BW		 5398
5399 /* 1a: Software RC state - RC0 */
5400 I915_WRITE(GEN6_RC_STATE, 0);
5401
5402 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5403 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5404 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5405
5406 /* 2a: Disable RC states. */
5407 I915_WRITE(GEN6_RC_CONTROL, 0);
5408
6edee7f3
BW		 5409 /* 2b: Program RC6 thresholds.*/
5410 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5411 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5412 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 5413 for_each_engine(engine, dev_priv)
e2f80391 5414 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5415 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5416 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5417 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5418 else
5419 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5420
5421 /* 3: Enable RC6 */
dc97997a 5422 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5423 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5424 intel_print_rc6_info(dev_priv, rc6_mask);
5425 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5426 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5427 GEN7_RC_CTL_TO_MODE |
5428 rc6_mask);
5429 else
5430 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5431 GEN6_RC_CTL_EI_MODE(1) |
5432 rc6_mask);
6edee7f3
BW		 5433
5434 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5435 I915_WRITE(GEN6_RPNSWREQ,
5436 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5437 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5438 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5439 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5440 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5441
5442 /* Docs recommend 900MHz, and 300 MHz respectively */
5443 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5444 dev_priv->rps.max_freq_softlimit << 24 |
5445 dev_priv->rps.min_freq_softlimit << 16);
5446
5447 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5448 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5449 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5450 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5451
5452 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5453
5454 /* 5: Enable RPS */
7526ed79
DV		 5455 I915_WRITE(GEN6_RP_CONTROL,
5456 GEN6_RP_MEDIA_TURBO |
5457 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5458 GEN6_RP_MEDIA_IS_GFX |
5459 GEN6_RP_ENABLE |
5460 GEN6_RP_UP_BUSY_AVG |
5461 GEN6_RP_DOWN_IDLE_AVG);
5462
5463 /* 6: Ring frequency + overclocking (our driver does this later */
5464
3a45b05c 5465 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5466
59bad947 5467 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5468}
5469
dc97997a 5470static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5471{
e2f80391 5472 struct intel_engine_cs *engine;
99ac9612 5473 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5474 u32 gtfifodbg;
2b4e57bd 5475 int rc6_mode;
b4ac5afc 5476 int ret;
2b4e57bd 5477
4fc688ce 5478 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5479
2b4e57bd
ED		 5480 /* Here begins a magic sequence of register writes to enable
5481 * auto-downclocking.
5482 *
5483 * Perhaps there might be some value in exposing these to
5484 * userspace...
5485 */
5486 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5487
5488 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5489 gtfifodbg = I915_READ(GTFIFODBG);
5490 if (gtfifodbg) {
2b4e57bd
ED		 5491 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5492 I915_WRITE(GTFIFODBG, gtfifodbg);
5493 }
5494
59bad947 5495 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5496
5497 /* disable the counters and set deterministic thresholds */
5498 I915_WRITE(GEN6_RC_CONTROL, 0);
5499
5500 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5501 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5502 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5503 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5504 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5505
b4ac5afc 5506 for_each_engine(engine, dev_priv)
e2f80391 5507 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5508
5509 I915_WRITE(GEN6_RC_SLEEP, 0);
5510 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5511 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5512 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5513 else
5514 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5515 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5516 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5517
5a7dc92a 5518 /* Check if we are enabling RC6 */
dc97997a 5519 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5520 if (rc6_mode & INTEL_RC6_ENABLE)
5521 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5522
5a7dc92a 5523 /* We don't use those on Haswell */
dc97997a 5524 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5525 if (rc6_mode & INTEL_RC6p_ENABLE)
5526 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5527
5a7dc92a
ED		 5528 if (rc6_mode & INTEL_RC6pp_ENABLE)
5529 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5530 }
2b4e57bd 5531
dc97997a 5532 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5533
5534 I915_WRITE(GEN6_RC_CONTROL,
5535 rc6_mask |
5536 GEN6_RC_CTL_EI_MODE(1) |
5537 GEN6_RC_CTL_HW_ENABLE);
5538
dd75fdc8
CW		 5539 /* Power down if completely idle for over 50ms */
5540 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5541 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5542
42c0526c 5543 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5544 if (ret)
42c0526c 5545 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5546
3a45b05c 5547 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5548
31643d54
BW		 5549 rc6vids = 0;
5550 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5551 if (IS_GEN6(dev_priv) && ret) {
31643d54 5552 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5553 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5554 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5555 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5556 rc6vids &= 0xffff00;
5557 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5558 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5559 if (ret)
5560 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5561 }
5562
59bad947 5563 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5564}
5565
fb7404e8 5566static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5567{
5568 int min_freq = 15;
3ebecd07
CW		 5569 unsigned int gpu_freq;
5570 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5571 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5572 int scaling_factor = 180;
eda79642 5573 struct cpufreq_policy *policy;
2b4e57bd 5574
4fc688ce 5575 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5576
eda79642
BW		 5577 policy = cpufreq_cpu_get(0);
5578 if (policy) {
5579 max_ia_freq = policy->cpuinfo.max_freq;
5580 cpufreq_cpu_put(policy);
5581 } else {
5582 /*
5583 * Default to measured freq if none found, PCU will ensure we
5584 * don't go over
5585 */
2b4e57bd 5586 max_ia_freq = tsc_khz;
eda79642 5587 }
2b4e57bd
ED		 5588
5589 /* Convert from kHz to MHz */
5590 max_ia_freq /= 1000;
5591
153b4b95 5592 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5593 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5594 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5595
dc97997a 5596 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5597 /* Convert GT frequency to 50 HZ units */
5598 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5599 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5600 } else {
5601 min_gpu_freq = dev_priv->rps.min_freq;
5602 max_gpu_freq = dev_priv->rps.max_freq;
5603 }
5604
2b4e57bd
ED		 5605 /*
5606 * For each potential GPU frequency, load a ring frequency we'd like
5607 * to use for memory access. We do this by specifying the IA frequency
5608 * the PCU should use as a reference to determine the ring frequency.
5609 */
4c8c7743
AG		 5610 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5611 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5612 unsigned int ia_freq = 0, ring_freq = 0;
5613
dc97997a 5614 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5615 /*
5616 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5617 * No floor required for ring frequency on SKL.
5618 */
5619 ring_freq = gpu_freq;
dc97997a 5620 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5621 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5622 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5623 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5624 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5625 ring_freq = max(min_ring_freq, ring_freq);
5626 /* leave ia_freq as the default, chosen by cpufreq */
5627 } else {
5628 /* On older processors, there is no separate ring
5629 * clock domain, so in order to boost the bandwidth
5630 * of the ring, we need to upclock the CPU (ia_freq).
5631 *
5632 * For GPU frequencies less than 750MHz,
5633 * just use the lowest ring freq.
5634 */
5635 if (gpu_freq < min_freq)
5636 ia_freq = 800;
5637 else
5638 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5639 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5640 }
2b4e57bd 5641
42c0526c
BW		 5642 sandybridge_pcode_write(dev_priv,
5643 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5644 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5645 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5646 gpu_freq);
2b4e57bd 5647 }
2b4e57bd
ED		 5648}
5649
03af2045 5650static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5651{
5652 u32 val, rp0;
5653
5b5929cb 5654 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5655
43b67998 5656 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5657 case 8:
5658 /* (2 * 4) config */
5659 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5660 break;
5661 case 12:
5662 /* (2 * 6) config */
5663 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5664 break;
5665 case 16:
5666 /* (2 * 8) config */
5667 default:
5668 /* Setting (2 * 8) Min RP0 for any other combination */
5669 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5670 break;
095acd5f 5671 }
5b5929cb
JN		 5672
5673 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5674
2b6b3a09
D		 5675 return rp0;
5676}
5677
5678static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5679{
5680 u32 val, rpe;
5681
5682 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5683 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5684
5685 return rpe;
5686}
5687
7707df4a
D		 5688static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5689{
5690 u32 val, rp1;
5691
5b5929cb
JN		 5692 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5693 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5694
7707df4a
D		 5695 return rp1;
5696}
5697
f8f2b001
D		 5698static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5699{
5700 u32 val, rp1;
5701
5702 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5703
5704 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5705
5706 return rp1;
5707}
5708
03af2045 5709static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5710{
5711 u32 val, rp0;
5712
64936258 5713 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5714
5715 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5716 /* Clamp to max */
5717 rp0 = min_t(u32, rp0, 0xea);
5718
5719 return rp0;
5720}
5721
5722static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5723{
5724 u32 val, rpe;
5725
64936258 5726 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5727 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5728 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5729 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5730
5731 return rpe;
5732}
5733
03af2045 5734static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5735{
36146035
ID		 5736 u32 val;
5737
5738 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5739 /*
5740 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5741 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5742 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5743 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5744 * to make sure it matches what Punit accepts.
5745 */
5746 return max_t(u32, val, 0xc0);
0a073b84
JB		 5747}
5748
ae48434c
ID		 5749/* Check that the pctx buffer wasn't move under us. */
5750static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5751{
5752 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5753
5754 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5755 dev_priv->vlv_pctx->stolen->start);
5756}
5757
38807746
D		 5758
5759/* Check that the pcbr address is not empty. */
5760static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5761{
5762 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5763
5764 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5765}
5766
dc97997a 5767static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5768{
62106b4f 5769 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5770 unsigned long pctx_paddr, paddr;
38807746
D		 5771 u32 pcbr;
5772 int pctx_size = 32*1024;
5773
38807746
D		 5774 pcbr = I915_READ(VLV_PCBR);
5775 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5776 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5777 paddr = (dev_priv->mm.stolen_base +
62106b4f 5778 (ggtt->stolen_size - pctx_size));
38807746
D		 5779
5780 pctx_paddr = (paddr & (~4095));
5781 I915_WRITE(VLV_PCBR, pctx_paddr);
5782 }
ce611ef8
VS		 5783
5784 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5785}
5786
dc97997a 5787static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5788{
c9cddffc
JB		 5789 struct drm_i915_gem_object *pctx;
5790 unsigned long pctx_paddr;
5791 u32 pcbr;
5792 int pctx_size = 24*1024;
5793
5794 pcbr = I915_READ(VLV_PCBR);
5795 if (pcbr) {
5796 /* BIOS set it up already, grab the pre-alloc'd space */
5797 int pcbr_offset;
5798
5799 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5800 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5801 pcbr_offset,
190d6cd5 5802 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5803 pctx_size);
5804 goto out;
5805 }
5806
ce611ef8
VS		 5807 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5808
c9cddffc
JB		 5809 /*
5810 * From the Gunit register HAS:
5811 * The Gfx driver is expected to program this register and ensure
5812 * proper allocation within Gfx stolen memory. For example, this
5813 * register should be programmed such than the PCBR range does not
5814 * overlap with other ranges, such as the frame buffer, protected
5815 * memory, or any other relevant ranges.
5816 */
91c8a326 5817 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5818 if (!pctx) {
5819 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5820 goto out;
c9cddffc
JB		 5821 }
5822
5823 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5824 I915_WRITE(VLV_PCBR, pctx_paddr);
5825
5826out:
ce611ef8 5827 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5828 dev_priv->vlv_pctx = pctx;
5829}
5830
dc97997a 5831static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5832{
ae48434c
ID		 5833 if (WARN_ON(!dev_priv->vlv_pctx))
5834 return;
5835
34911fd3 5836 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5837 dev_priv->vlv_pctx = NULL;
5838}
5839
c30fec65
VS		 5840static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5841{
5842 dev_priv->rps.gpll_ref_freq =
5843 vlv_get_cck_clock(dev_priv, "GPLL ref",
5844 CCK_GPLL_CLOCK_CONTROL,
5845 dev_priv->czclk_freq);
5846
5847 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5848 dev_priv->rps.gpll_ref_freq);
5849}
5850
dc97997a 5851static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5852{
2bb25c17 5853 u32 val;
4e80519e 5854
dc97997a 5855 valleyview_setup_pctx(dev_priv);
4e80519e 5856
c30fec65
VS		 5857 vlv_init_gpll_ref_freq(dev_priv);
5858
2bb25c17
VS		 5859 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5860 switch ((val >> 6) & 3) {
5861 case 0:
5862 case 1:
5863 dev_priv->mem_freq = 800;
5864 break;
5865 case 2:
5866 dev_priv->mem_freq = 1066;
5867 break;
5868 case 3:
5869 dev_priv->mem_freq = 1333;
5870 break;
5871 }
80b83b62 5872 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5873
4e80519e
ID		 5874 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5875 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5876 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5877 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5878 dev_priv->rps.max_freq);
5879
5880 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5881 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5882 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5883 dev_priv->rps.efficient_freq);
5884
f8f2b001
D		 5885 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5886 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5887 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5888 dev_priv->rps.rp1_freq);
5889
4e80519e
ID		 5890 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5891 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5892 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5893 dev_priv->rps.min_freq);
4e80519e
ID		 5894}
5895
dc97997a 5896static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5897{
2bb25c17 5898 u32 val;
2b6b3a09 5899
dc97997a 5900 cherryview_setup_pctx(dev_priv);
2b6b3a09 5901
c30fec65
VS		 5902 vlv_init_gpll_ref_freq(dev_priv);
5903
a580516d 5904 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5905 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5906 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5907
2bb25c17 5908 switch ((val >> 2) & 0x7) {
2bb25c17 5909 case 3:
2bb25c17
VS		 5910 dev_priv->mem_freq = 2000;
5911 break;
bfa7df01 5912 default:
2bb25c17
VS		 5913 dev_priv->mem_freq = 1600;
5914 break;
5915 }
80b83b62 5916 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5917
2b6b3a09
D		 5918 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5919 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5920 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5921 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5922 dev_priv->rps.max_freq);
5923
5924 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5925 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5926 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5927 dev_priv->rps.efficient_freq);
5928
7707df4a
D		 5929 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5930 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5931 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5932 dev_priv->rps.rp1_freq);
5933
5b7c91b7
D		 5934 /* PUnit validated range is only [RPe, RP0] */
5935 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5936 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5937 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5938 dev_priv->rps.min_freq);
5939
1c14762d
VS		 5940 WARN_ONCE((dev_priv->rps.max_freq |
5941 dev_priv->rps.efficient_freq |
5942 dev_priv->rps.rp1_freq |
5943 dev_priv->rps.min_freq) & 1,
5944 "Odd GPU freq values\n");
38807746
D		 5945}
5946
dc97997a 5947static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5948{
dc97997a 5949 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5950}
5951
dc97997a 5952static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5953{
e2f80391 5954 struct intel_engine_cs *engine;
2b6b3a09 5955 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5956
5957 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5958
297b32ec
VS		 5959 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5960 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5961 if (gtfifodbg) {
5962 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5963 gtfifodbg);
5964 I915_WRITE(GTFIFODBG, gtfifodbg);
5965 }
5966
5967 cherryview_check_pctx(dev_priv);
5968
5969 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5970 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5971 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5972
160614a2
VS		 5973 /* Disable RC states. */
5974 I915_WRITE(GEN6_RC_CONTROL, 0);
5975
38807746
D		 5976 /* 2a: Program RC6 thresholds.*/
5977 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5978 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5979 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5980
b4ac5afc 5981 for_each_engine(engine, dev_priv)
e2f80391 5982 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5983 I915_WRITE(GEN6_RC_SLEEP, 0);
5984
f4f71c7d
D		 5985 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5986 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5987
5988 /* allows RC6 residency counter to work */
5989 I915_WRITE(VLV_COUNTER_CONTROL,
5990 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5991 VLV_MEDIA_RC6_COUNT_EN |
5992 VLV_RENDER_RC6_COUNT_EN));
5993
5994 /* For now we assume BIOS is allocating and populating the PCBR */
5995 pcbr = I915_READ(VLV_PCBR);
5996
38807746 5997 /* 3: Enable RC6 */
dc97997a
CW		 5998 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5999 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6000 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6001
6002 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6003
2b6b3a09 6004 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6005 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6006 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6007 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6008 I915_WRITE(GEN6_RP_UP_EI, 66000);
6009 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6010
6011 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6012
6013 /* 5: Enable RPS */
6014 I915_WRITE(GEN6_RP_CONTROL,
6015 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6016 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6017 GEN6_RP_ENABLE |
6018 GEN6_RP_UP_BUSY_AVG |
6019 GEN6_RP_DOWN_IDLE_AVG);
6020
3ef62342
D		 6021 /* Setting Fixed Bias */
6022 val = VLV_OVERRIDE_EN |
6023 VLV_SOC_TDP_EN |
6024 CHV_BIAS_CPU_50_SOC_50;
6025 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6026
2b6b3a09
D		 6027 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6028
8d40c3ae
VS		 6029 /* RPS code assumes GPLL is used */
6030 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6031
742f491d 6032 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6033 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6034
3a45b05c 6035 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6036
59bad947 6037 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6038}
6039
dc97997a 6040static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6041{
e2f80391 6042 struct intel_engine_cs *engine;
2a5913a8 6043 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6044
6045 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6046
ae48434c
ID		 6047 valleyview_check_pctx(dev_priv);
6048
297b32ec
VS		 6049 gtfifodbg = I915_READ(GTFIFODBG);
6050 if (gtfifodbg) {
f7d85c1e
JB		 6051 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6052 gtfifodbg);
0a073b84
JB		 6053 I915_WRITE(GTFIFODBG, gtfifodbg);
6054 }
6055
c8d9a590 6056 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6057 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6058
160614a2
VS		 6059 /* Disable RC states. */
6060 I915_WRITE(GEN6_RC_CONTROL, 0);
6061
cad725fe 6062 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6063 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6064 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6065 I915_WRITE(GEN6_RP_UP_EI, 66000);
6066 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6067
6068 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6069
6070 I915_WRITE(GEN6_RP_CONTROL,
6071 GEN6_RP_MEDIA_TURBO |
6072 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6073 GEN6_RP_MEDIA_IS_GFX |
6074 GEN6_RP_ENABLE |
6075 GEN6_RP_UP_BUSY_AVG |
6076 GEN6_RP_DOWN_IDLE_CONT);
6077
6078 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6079 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6080 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6081
b4ac5afc 6082 for_each_engine(engine, dev_priv)
e2f80391 6083 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6084
2f0aa304 6085 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6086
6087 /* allows RC6 residency counter to work */
49798eb2 6088 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6089 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6090 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6091 VLV_MEDIA_RC6_COUNT_EN |
6092 VLV_RENDER_RC6_COUNT_EN));
31685c25 6093
dc97997a 6094 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6095 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6096
dc97997a 6097 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6098
a2b23fe0 6099 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6100
3ef62342
D		 6101 /* Setting Fixed Bias */
6102 val = VLV_OVERRIDE_EN |
6103 VLV_SOC_TDP_EN |
6104 VLV_BIAS_CPU_125_SOC_875;
6105 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6106
64936258 6107 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6108
8d40c3ae
VS		 6109 /* RPS code assumes GPLL is used */
6110 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6111
742f491d 6112 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6113 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6114
3a45b05c 6115 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6116
59bad947 6117 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6118}
6119
dde18883
ED		 6120static unsigned long intel_pxfreq(u32 vidfreq)
6121{
6122 unsigned long freq;
6123 int div = (vidfreq & 0x3f0000) >> 16;
6124 int post = (vidfreq & 0x3000) >> 12;
6125 int pre = (vidfreq & 0x7);
6126
6127 if (!pre)
6128 return 0;
6129
6130 freq = ((div * 133333) / ((1<<post) * pre));
6131
6132 return freq;
6133}
6134
eb48eb00
DV		 6135static const struct cparams {
6136 u16 i;
6137 u16 t;
6138 u16 m;
6139 u16 c;
6140} cparams[] = {
6141 { 1, 1333, 301, 28664 },
6142 { 1, 1066, 294, 24460 },
6143 { 1, 800, 294, 25192 },
6144 { 0, 1333, 276, 27605 },
6145 { 0, 1066, 276, 27605 },
6146 { 0, 800, 231, 23784 },
6147};
6148
f531dcb2 6149static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6150{
6151 u64 total_count, diff, ret;
6152 u32 count1, count2, count3, m = 0, c = 0;
6153 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6154 int i;
6155
02d71956
DV		 6156 assert_spin_locked(&mchdev_lock);
6157
20e4d407 6158 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6159
6160 /* Prevent division-by-zero if we are asking too fast.
6161 * Also, we don't get interesting results if we are polling
6162 * faster than once in 10ms, so just return the saved value
6163 * in such cases.
6164 */
6165 if (diff1 <= 10)
20e4d407 6166 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6167
6168 count1 = I915_READ(DMIEC);
6169 count2 = I915_READ(DDREC);
6170 count3 = I915_READ(CSIEC);
6171
6172 total_count = count1 + count2 + count3;
6173
6174 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6175 if (total_count < dev_priv->ips.last_count1) {
6176 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6177 diff += total_count;
6178 } else {
20e4d407 6179 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6180 }
6181
6182 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6183 if (cparams[i].i == dev_priv->ips.c_m &&
6184 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6185 m = cparams[i].m;
6186 c = cparams[i].c;
6187 break;
6188 }
6189 }
6190
6191 diff = div_u64(diff, diff1);
6192 ret = ((m * diff) + c);
6193 ret = div_u64(ret, 10);
6194
20e4d407
DV		 6195 dev_priv->ips.last_count1 = total_count;
6196 dev_priv->ips.last_time1 = now;
eb48eb00 6197
20e4d407 6198 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6199
6200 return ret;
6201}
6202
f531dcb2
CW		 6203unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6204{
6205 unsigned long val;
6206
dc97997a 6207 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6208 return 0;
6209
6210 spin_lock_irq(&mchdev_lock);
6211
6212 val = __i915_chipset_val(dev_priv);
6213
6214 spin_unlock_irq(&mchdev_lock);
6215
6216 return val;
6217}
6218
eb48eb00
DV		 6219unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6220{
6221 unsigned long m, x, b;
6222 u32 tsfs;
6223
6224 tsfs = I915_READ(TSFS);
6225
6226 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6227 x = I915_READ8(TR1);
6228
6229 b = tsfs & TSFS_INTR_MASK;
6230
6231 return ((m * x) / 127) - b;
6232}
6233
d972d6ee
MK		 6234static int _pxvid_to_vd(u8 pxvid)
6235{
6236 if (pxvid == 0)
6237 return 0;
6238
6239 if (pxvid >= 8 && pxvid < 31)
6240 pxvid = 31;
6241
6242 return (pxvid + 2) * 125;
6243}
6244
6245static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6246{
d972d6ee
MK		 6247 const int vd = _pxvid_to_vd(pxvid);
6248 const int vm = vd - 1125;
6249
dc97997a 6250 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6251 return vm > 0 ? vm : 0;
6252
6253 return vd;
eb48eb00
DV		 6254}
6255
02d71956 6256static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6257{
5ed0bdf2 6258 u64 now, diff, diffms;
eb48eb00
DV		 6259 u32 count;
6260
02d71956 6261 assert_spin_locked(&mchdev_lock);
eb48eb00 6262
5ed0bdf2
TG		 6263 now = ktime_get_raw_ns();
6264 diffms = now - dev_priv->ips.last_time2;
6265 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6266
6267 /* Don't divide by 0 */
eb48eb00
DV		 6268 if (!diffms)
6269 return;
6270
6271 count = I915_READ(GFXEC);
6272
20e4d407
DV		 6273 if (count < dev_priv->ips.last_count2) {
6274 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6275 diff += count;
6276 } else {
20e4d407 6277 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6278 }
6279
20e4d407
DV		 6280 dev_priv->ips.last_count2 = count;
6281 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6282
6283 /* More magic constants... */
6284 diff = diff * 1181;
6285 diff = div_u64(diff, diffms * 10);
20e4d407 6286 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6287}
6288
02d71956
DV		 6289void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6290{
dc97997a 6291 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6292 return;
6293
9270388e 6294 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6295
6296 __i915_update_gfx_val(dev_priv);
6297
9270388e 6298 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6299}
6300
f531dcb2 6301static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6302{
6303 unsigned long t, corr, state1, corr2, state2;
6304 u32 pxvid, ext_v;
6305
02d71956
DV		 6306 assert_spin_locked(&mchdev_lock);
6307
616847e7 6308 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6309 pxvid = (pxvid >> 24) & 0x7f;
6310 ext_v = pvid_to_extvid(dev_priv, pxvid);
6311
6312 state1 = ext_v;
6313
6314 t = i915_mch_val(dev_priv);
6315
6316 /* Revel in the empirically derived constants */
6317
6318 /* Correction factor in 1/100000 units */
6319 if (t > 80)
6320 corr = ((t * 2349) + 135940);
6321 else if (t >= 50)
6322 corr = ((t * 964) + 29317);
6323 else /* < 50 */
6324 corr = ((t * 301) + 1004);
6325
6326 corr = corr * ((150142 * state1) / 10000 - 78642);
6327 corr /= 100000;
20e4d407 6328 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6329
6330 state2 = (corr2 * state1) / 10000;
6331 state2 /= 100; /* convert to mW */
6332
02d71956 6333 __i915_update_gfx_val(dev_priv);
eb48eb00 6334
20e4d407 6335 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6336}
6337
f531dcb2
CW		 6338unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6339{
6340 unsigned long val;
6341
dc97997a 6342 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6343 return 0;
6344
6345 spin_lock_irq(&mchdev_lock);
6346
6347 val = __i915_gfx_val(dev_priv);
6348
6349 spin_unlock_irq(&mchdev_lock);
6350
6351 return val;
6352}
6353
eb48eb00
DV		 6354/**
6355 * i915_read_mch_val - return value for IPS use
6356 *
6357 * Calculate and return a value for the IPS driver to use when deciding whether
6358 * we have thermal and power headroom to increase CPU or GPU power budget.
6359 */
6360unsigned long i915_read_mch_val(void)
6361{
6362 struct drm_i915_private *dev_priv;
6363 unsigned long chipset_val, graphics_val, ret = 0;
6364
9270388e 6365 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6366 if (!i915_mch_dev)
6367 goto out_unlock;
6368 dev_priv = i915_mch_dev;
6369
f531dcb2
CW		 6370 chipset_val = __i915_chipset_val(dev_priv);
6371 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6372
6373 ret = chipset_val + graphics_val;
6374
6375out_unlock:
9270388e 6376 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6377
6378 return ret;
6379}
6380EXPORT_SYMBOL_GPL(i915_read_mch_val);
6381
6382/**
6383 * i915_gpu_raise - raise GPU frequency limit
6384 *
6385 * Raise the limit; IPS indicates we have thermal headroom.
6386 */
6387bool i915_gpu_raise(void)
6388{
6389 struct drm_i915_private *dev_priv;
6390 bool ret = true;
6391
9270388e 6392 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6393 if (!i915_mch_dev) {
6394 ret = false;
6395 goto out_unlock;
6396 }
6397 dev_priv = i915_mch_dev;
6398
20e4d407
DV		 6399 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6400 dev_priv->ips.max_delay--;
eb48eb00
DV		 6401
6402out_unlock:
9270388e 6403 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6404
6405 return ret;
6406}
6407EXPORT_SYMBOL_GPL(i915_gpu_raise);
6408
6409/**
6410 * i915_gpu_lower - lower GPU frequency limit
6411 *
6412 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6413 * frequency maximum.
6414 */
6415bool i915_gpu_lower(void)
6416{
6417 struct drm_i915_private *dev_priv;
6418 bool ret = true;
6419
9270388e 6420 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6421 if (!i915_mch_dev) {
6422 ret = false;
6423 goto out_unlock;
6424 }
6425 dev_priv = i915_mch_dev;
6426
20e4d407
DV		 6427 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6428 dev_priv->ips.max_delay++;
eb48eb00
DV		 6429
6430out_unlock:
9270388e 6431 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6432
6433 return ret;
6434}
6435EXPORT_SYMBOL_GPL(i915_gpu_lower);
6436
6437/**
6438 * i915_gpu_busy - indicate GPU business to IPS
6439 *
6440 * Tell the IPS driver whether or not the GPU is busy.
6441 */
6442bool i915_gpu_busy(void)
6443{
eb48eb00
DV		 6444 bool ret = false;
6445
9270388e 6446 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6447 if (i915_mch_dev)
6448 ret = i915_mch_dev->gt.awake;
9270388e 6449 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6450
6451 return ret;
6452}
6453EXPORT_SYMBOL_GPL(i915_gpu_busy);
6454
6455/**
6456 * i915_gpu_turbo_disable - disable graphics turbo
6457 *
6458 * Disable graphics turbo by resetting the max frequency and setting the
6459 * current frequency to the default.
6460 */
6461bool i915_gpu_turbo_disable(void)
6462{
6463 struct drm_i915_private *dev_priv;
6464 bool ret = true;
6465
9270388e 6466 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6467 if (!i915_mch_dev) {
6468 ret = false;
6469 goto out_unlock;
6470 }
6471 dev_priv = i915_mch_dev;
6472
20e4d407 6473 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6474
91d14251 6475 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6476 ret = false;
6477
6478out_unlock:
9270388e 6479 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6480
6481 return ret;
6482}
6483EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6484
6485/**
6486 * Tells the intel_ips driver that the i915 driver is now loaded, if
6487 * IPS got loaded first.
6488 *
6489 * This awkward dance is so that neither module has to depend on the
6490 * other in order for IPS to do the appropriate communication of
6491 * GPU turbo limits to i915.
6492 */
6493static void
6494ips_ping_for_i915_load(void)
6495{
6496 void (*link)(void);
6497
6498 link = symbol_get(ips_link_to_i915_driver);
6499 if (link) {
6500 link();
6501 symbol_put(ips_link_to_i915_driver);
6502 }
6503}
6504
6505void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6506{
02d71956
DV		 6507 /* We only register the i915 ips part with intel-ips once everything is
6508 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6509 spin_lock_irq(&mchdev_lock);
eb48eb00 6510 i915_mch_dev = dev_priv;
9270388e 6511 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6512
6513 ips_ping_for_i915_load();
6514}
6515
6516void intel_gpu_ips_teardown(void)
6517{
9270388e 6518 spin_lock_irq(&mchdev_lock);
eb48eb00 6519 i915_mch_dev = NULL;
9270388e 6520 spin_unlock_irq(&mchdev_lock);
eb48eb00 6521}
76c3552f 6522
dc97997a 6523static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6524{
dde18883
ED		 6525 u32 lcfuse;
6526 u8 pxw[16];
6527 int i;
6528
6529 /* Disable to program */
6530 I915_WRITE(ECR, 0);
6531 POSTING_READ(ECR);
6532
6533 /* Program energy weights for various events */
6534 I915_WRITE(SDEW, 0x15040d00);
6535 I915_WRITE(CSIEW0, 0x007f0000);
6536 I915_WRITE(CSIEW1, 0x1e220004);
6537 I915_WRITE(CSIEW2, 0x04000004);
6538
6539 for (i = 0; i < 5; i++)
616847e7 6540 I915_WRITE(PEW(i), 0);
dde18883 6541 for (i = 0; i < 3; i++)
616847e7 6542 I915_WRITE(DEW(i), 0);
dde18883
ED		 6543
6544 /* Program P-state weights to account for frequency power adjustment */
6545 for (i = 0; i < 16; i++) {
616847e7 6546 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6547 unsigned long freq = intel_pxfreq(pxvidfreq);
6548 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6549 PXVFREQ_PX_SHIFT;
6550 unsigned long val;
6551
6552 val = vid * vid;
6553 val *= (freq / 1000);
6554 val *= 255;
6555 val /= (127*127*900);
6556 if (val > 0xff)
6557 DRM_ERROR("bad pxval: %ld\n", val);
6558 pxw[i] = val;
6559 }
6560 /* Render standby states get 0 weight */
6561 pxw[14] = 0;
6562 pxw[15] = 0;
6563
6564 for (i = 0; i < 4; i++) {
6565 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6566 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6567 I915_WRITE(PXW(i), val);
dde18883
ED		 6568 }
6569
6570 /* Adjust magic regs to magic values (more experimental results) */
6571 I915_WRITE(OGW0, 0);
6572 I915_WRITE(OGW1, 0);
6573 I915_WRITE(EG0, 0x00007f00);
6574 I915_WRITE(EG1, 0x0000000e);
6575 I915_WRITE(EG2, 0x000e0000);
6576 I915_WRITE(EG3, 0x68000300);
6577 I915_WRITE(EG4, 0x42000000);
6578 I915_WRITE(EG5, 0x00140031);
6579 I915_WRITE(EG6, 0);
6580 I915_WRITE(EG7, 0);
6581
6582 for (i = 0; i < 8; i++)
616847e7 6583 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6584
6585 /* Enable PMON + select events */
6586 I915_WRITE(ECR, 0x80000019);
6587
6588 lcfuse = I915_READ(LCFUSE02);
6589
20e4d407 6590 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6591}
6592
dc97997a 6593void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6594{
b268c699
ID		 6595 /*
6596 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6597 * requirement.
6598 */
6599 if (!i915.enable_rc6) {
6600 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6601 intel_runtime_pm_get(dev_priv);
6602 }
e6069ca8 6603
b5163dbb 6604 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6605 mutex_lock(&dev_priv->rps.hw_lock);
6606
6607 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6608 if (IS_CHERRYVIEW(dev_priv))
6609 cherryview_init_gt_powersave(dev_priv);
6610 else if (IS_VALLEYVIEW(dev_priv))
6611 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6612 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6613 gen6_init_rps_frequencies(dev_priv);
6614
6615 /* Derive initial user preferences/limits from the hardware limits */
6616 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6617 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6618
6619 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6620 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6621
6622 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6623 dev_priv->rps.min_freq_softlimit =
6624 max_t(int,
6625 dev_priv->rps.efficient_freq,
6626 intel_freq_opcode(dev_priv, 450));
6627
99ac9612
CW		 6628 /* After setting max-softlimit, find the overclock max freq */
6629 if (IS_GEN6(dev_priv) ||
6630 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6631 u32 params = 0;
6632
6633 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6634 if (params & BIT(31)) { /* OC supported */
6635 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6636 (dev_priv->rps.max_freq & 0xff) * 50,
6637 (params & 0xff) * 50);
6638 dev_priv->rps.max_freq = params & 0xff;
6639 }
6640 }
6641
29ecd78d
CW		 6642 /* Finally allow us to boost to max by default */
6643 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6644
773ea9a8 6645 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6646 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6647
6648 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6649}
6650
dc97997a 6651void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6652{
8dac1e1f 6653 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6654 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6655
6656 if (!i915.enable_rc6)
6657 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6658}
6659
54b4f68f
CW		 6660/**
6661 * intel_suspend_gt_powersave - suspend PM work and helper threads
6662 * @dev_priv: i915 device
6663 *
6664 * We don't want to disable RC6 or other features here, we just want
6665 * to make sure any work we've queued has finished and won't bother
6666 * us while we're suspended.
6667 */
6668void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6669{
6670 if (INTEL_GEN(dev_priv) < 6)
6671 return;
6672
6673 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6674 intel_runtime_pm_put(dev_priv);
6675
6676 /* gen6_rps_idle() will be called later to disable interrupts */
6677}
6678
b7137e0c
CW		 6679void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6680{
6681 dev_priv->rps.enabled = true; /* force disabling */
6682 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6683
6684 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6685}
6686
dc97997a 6687void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6688{
b7137e0c
CW		 6689 if (!READ_ONCE(dev_priv->rps.enabled))
6690 return;
e494837a 6691
b7137e0c 6692 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6693
b7137e0c
CW		 6694 if (INTEL_GEN(dev_priv) >= 9) {
6695 gen9_disable_rc6(dev_priv);
6696 gen9_disable_rps(dev_priv);
6697 } else if (IS_CHERRYVIEW(dev_priv)) {
6698 cherryview_disable_rps(dev_priv);
6699 } else if (IS_VALLEYVIEW(dev_priv)) {
6700 valleyview_disable_rps(dev_priv);
6701 } else if (INTEL_GEN(dev_priv) >= 6) {
6702 gen6_disable_rps(dev_priv);
6703 } else if (IS_IRONLAKE_M(dev_priv)) {
6704 ironlake_disable_drps(dev_priv);
930ebb46 6705 }
b7137e0c
CW		 6706
6707 dev_priv->rps.enabled = false;
6708 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6709}
6710
b7137e0c 6711void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6712{
54b4f68f
CW		 6713 /* We shouldn't be disabling as we submit, so this should be less
6714 * racy than it appears!
6715 */
b7137e0c
CW		 6716 if (READ_ONCE(dev_priv->rps.enabled))
6717 return;
1a01ab3b 6718
b7137e0c
CW		 6719 /* Powersaving is controlled by the host when inside a VM */
6720 if (intel_vgpu_active(dev_priv))
6721 return;
0a073b84 6722
b7137e0c 6723 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6724
6725 if (IS_CHERRYVIEW(dev_priv)) {
6726 cherryview_enable_rps(dev_priv);
6727 } else if (IS_VALLEYVIEW(dev_priv)) {
6728 valleyview_enable_rps(dev_priv);
b7137e0c 6729 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6730 gen9_enable_rc6(dev_priv);
6731 gen9_enable_rps(dev_priv);
6732 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6733 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6734 } else if (IS_BROADWELL(dev_priv)) {
6735 gen8_enable_rps(dev_priv);
fb7404e8 6736 gen6_update_ring_freq(dev_priv);
b7137e0c 6737 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6738 gen6_enable_rps(dev_priv);
fb7404e8 6739 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6740 } else if (IS_IRONLAKE_M(dev_priv)) {
6741 ironlake_enable_drps(dev_priv);
6742 intel_init_emon(dev_priv);
0a073b84 6743 }
aed242ff
CW		 6744
6745 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6746 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6747
6748 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6749 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6750
54b4f68f 6751 dev_priv->rps.enabled = true;
b7137e0c
CW		 6752 mutex_unlock(&dev_priv->rps.hw_lock);
6753}
3cc134e3 6754
54b4f68f
CW		 6755static void __intel_autoenable_gt_powersave(struct work_struct *work)
6756{
6757 struct drm_i915_private *dev_priv =
6758 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6759 struct intel_engine_cs *rcs;
6760 struct drm_i915_gem_request *req;
6761
6762 if (READ_ONCE(dev_priv->rps.enabled))
6763 goto out;
6764
6765 rcs = &dev_priv->engine[RCS];
6766 if (rcs->last_context)
6767 goto out;
6768
6769 if (!rcs->init_context)
6770 goto out;
6771
6772 mutex_lock(&dev_priv->drm.struct_mutex);
6773
6774 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6775 if (IS_ERR(req))
6776 goto unlock;
6777
6778 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6779 rcs->init_context(req);
6780
6781 /* Mark the device busy, calling intel_enable_gt_powersave() */
6782 i915_add_request_no_flush(req);
6783
6784unlock:
6785 mutex_unlock(&dev_priv->drm.struct_mutex);
6786out:
6787 intel_runtime_pm_put(dev_priv);
6788}
6789
6790void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6791{
6792 if (READ_ONCE(dev_priv->rps.enabled))
6793 return;
6794
6795 if (IS_IRONLAKE_M(dev_priv)) {
6796 ironlake_enable_drps(dev_priv);
54b4f68f 6797 intel_init_emon(dev_priv);
54b4f68f
CW		 6798 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6799 /*
6800 * PCU communication is slow and this doesn't need to be
6801 * done at any specific time, so do this out of our fast path
6802 * to make resume and init faster.
6803 *
6804 * We depend on the HW RC6 power context save/restore
6805 * mechanism when entering D3 through runtime PM suspend. So
6806 * disable RPM until RPS/RC6 is properly setup. We can only
6807 * get here via the driver load/system resume/runtime resume
6808 * paths, so the _noresume version is enough (and in case of
6809 * runtime resume it's necessary).
6810 */
6811 if (queue_delayed_work(dev_priv->wq,
6812 &dev_priv->rps.autoenable_work,
6813 round_jiffies_up_relative(HZ)))
6814 intel_runtime_pm_get_noresume(dev_priv);
6815 }
6816}
6817
3107bd48
DV		 6818static void ibx_init_clock_gating(struct drm_device *dev)
6819{
fac5e23e 6820 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6821
6822 /*
6823 * On Ibex Peak and Cougar Point, we need to disable clock
6824 * gating for the panel power sequencer or it will fail to
6825 * start up when no ports are active.
6826 */
6827 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6828}
6829
0e088b8f
VS		 6830static void g4x_disable_trickle_feed(struct drm_device *dev)
6831{
fac5e23e 6832 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6833 enum pipe pipe;
0e088b8f 6834
055e393f 6835 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6836 I915_WRITE(DSPCNTR(pipe),
6837 I915_READ(DSPCNTR(pipe)) |
6838 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6839
6840 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6841 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6842 }
6843}
6844
017636cc
VS		 6845static void ilk_init_lp_watermarks(struct drm_device *dev)
6846{
fac5e23e 6847 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6848
6849 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6850 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6851 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6852
6853 /*
6854 * Don't touch WM1S_LP_EN here.
6855 * Doing so could cause underruns.
6856 */
6857}
6858
1fa61106 6859static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6860{
fac5e23e 6861 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6862 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6863
f1e8fa56
DL		 6864 /*
6865 * Required for FBC
6866 * WaFbcDisableDpfcClockGating:ilk
6867 */
4d47e4f5
DL		 6868 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6869 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6870 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6871
6872 I915_WRITE(PCH_3DCGDIS0,
6873 MARIUNIT_CLOCK_GATE_DISABLE |
6874 SVSMUNIT_CLOCK_GATE_DISABLE);
6875 I915_WRITE(PCH_3DCGDIS1,
6876 VFMUNIT_CLOCK_GATE_DISABLE);
6877
6f1d69b0
ED		 6878 /*
6879 * According to the spec the following bits should be set in
6880 * order to enable memory self-refresh
6881 * The bit 22/21 of 0x42004
6882 * The bit 5 of 0x42020
6883 * The bit 15 of 0x45000
6884 */
6885 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6886 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6887 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6888 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6889 I915_WRITE(DISP_ARB_CTL,
6890 (I915_READ(DISP_ARB_CTL) |
6891 DISP_FBC_WM_DIS));
017636cc
VS		 6892
6893 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6894
6895 /*
6896 * Based on the document from hardware guys the following bits
6897 * should be set unconditionally in order to enable FBC.
6898 * The bit 22 of 0x42000
6899 * The bit 22 of 0x42004
6900 * The bit 7,8,9 of 0x42020.
6901 */
6902 if (IS_IRONLAKE_M(dev)) {
4bb35334 6903 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6904 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6905 I915_READ(ILK_DISPLAY_CHICKEN1) |
6906 ILK_FBCQ_DIS);
6907 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6908 I915_READ(ILK_DISPLAY_CHICKEN2) |
6909 ILK_DPARB_GATE);
6f1d69b0
ED		 6910 }
6911
4d47e4f5
DL		 6912 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6913
6f1d69b0
ED		 6914 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6915 I915_READ(ILK_DISPLAY_CHICKEN2) |
6916 ILK_ELPIN_409_SELECT);
6917 I915_WRITE(_3D_CHICKEN2,
6918 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6919 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6920
ecdb4eb7 6921 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6922 I915_WRITE(CACHE_MODE_0,
6923 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6924
4e04632e
AG		 6925 /* WaDisable_RenderCache_OperationalFlush:ilk */
6926 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6927
0e088b8f 6928 g4x_disable_trickle_feed(dev);
bdad2b2f 6929
3107bd48
DV		 6930 ibx_init_clock_gating(dev);
6931}
6932
6933static void cpt_init_clock_gating(struct drm_device *dev)
6934{
fac5e23e 6935 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6936 int pipe;
3f704fa2 6937 uint32_t val;
3107bd48
DV		 6938
6939 /*
6940 * On Ibex Peak and Cougar Point, we need to disable clock
6941 * gating for the panel power sequencer or it will fail to
6942 * start up when no ports are active.
6943 */
cd664078
JB		 6944 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6945 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6946 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6947 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6948 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6949 /* The below fixes the weird display corruption, a few pixels shifted
6950 * downward, on (only) LVDS of some HP laptops with IVY.
6951 */
055e393f 6952 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6953 val = I915_READ(TRANS_CHICKEN2(pipe));
6954 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6955 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6956 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6957 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6958 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6959 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6960 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6961 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6962 }
3107bd48 6963 /* WADP0ClockGatingDisable */
055e393f 6964 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6965 I915_WRITE(TRANS_CHICKEN1(pipe),
6966 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6967 }
6f1d69b0
ED		 6968}
6969
1d7aaa0c
DV		 6970static void gen6_check_mch_setup(struct drm_device *dev)
6971{
fac5e23e 6972 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 6973 uint32_t tmp;
6974
6975 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6976 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6977 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6978 tmp);
1d7aaa0c
DV		 6979}
6980
1fa61106 6981static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 6982{
fac5e23e 6983 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6984 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6985
231e54f6 6986 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6987
6988 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6989 I915_READ(ILK_DISPLAY_CHICKEN2) |
6990 ILK_ELPIN_409_SELECT);
6991
ecdb4eb7 6992 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6993 I915_WRITE(_3D_CHICKEN,
6994 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6995
4e04632e
AG		 6996 /* WaDisable_RenderCache_OperationalFlush:snb */
6997 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6998
8d85d272
VS		 6999 /*
7000 * BSpec recoomends 8x4 when MSAA is used,
7001 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7002 *
7003 * Note that PS/WM thread counts depend on the WIZ hashing
7004 * disable bit, which we don't touch here, but it's good
7005 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7006 */
7007 I915_WRITE(GEN6_GT_MODE,
98533251 7008 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7009
017636cc 7010 ilk_init_lp_watermarks(dev);
6f1d69b0 7011
6f1d69b0 7012 I915_WRITE(CACHE_MODE_0,
50743298 7013 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7014
7015 I915_WRITE(GEN6_UCGCTL1,
7016 I915_READ(GEN6_UCGCTL1) |
7017 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7018 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7019
7020 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7021 * gating disable must be set. Failure to set it results in
7022 * flickering pixels due to Z write ordering failures after
7023 * some amount of runtime in the Mesa "fire" demo, and Unigine
7024 * Sanctuary and Tropics, and apparently anything else with
7025 * alpha test or pixel discard.
7026 *
7027 * According to the spec, bit 11 (RCCUNIT) must also be set,
7028 * but we didn't debug actual testcases to find it out.
0f846f81 7029 *
ef59318c
VS		 7030 * WaDisableRCCUnitClockGating:snb
7031 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7032 */
7033 I915_WRITE(GEN6_UCGCTL2,
7034 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7035 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7036
5eb146dd 7037 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7038 I915_WRITE(_3D_CHICKEN3,
7039 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7040
e927ecde
VS		 7041 /*
7042 * Bspec says:
7043 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7044 * 3DSTATE_SF number of SF output attributes is more than 16."
7045 */
7046 I915_WRITE(_3D_CHICKEN3,
7047 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7048
6f1d69b0
ED		 7049 /*
7050 * According to the spec the following bits should be
7051 * set in order to enable memory self-refresh and fbc:
7052 * The bit21 and bit22 of 0x42000
7053 * The bit21 and bit22 of 0x42004
7054 * The bit5 and bit7 of 0x42020
7055 * The bit14 of 0x70180
7056 * The bit14 of 0x71180
4bb35334
DL		 7057 *
7058 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7059 */
7060 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7061 I915_READ(ILK_DISPLAY_CHICKEN1) |
7062 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7063 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7064 I915_READ(ILK_DISPLAY_CHICKEN2) |
7065 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7066 I915_WRITE(ILK_DSPCLK_GATE_D,
7067 I915_READ(ILK_DSPCLK_GATE_D) |
7068 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7069 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7070
0e088b8f 7071 g4x_disable_trickle_feed(dev);
f8f2ac9a 7072
3107bd48 7073 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7074
7075 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7076}
7077
7078static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7079{
7080 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7081
3aad9059 7082 /*
46680e0a 7083 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7084 *
7085 * This actually overrides the dispatch
7086 * mode for all thread types.
7087 */
6f1d69b0
ED		 7088 reg &= ~GEN7_FF_SCHED_MASK;
7089 reg |= GEN7_FF_TS_SCHED_HW;
7090 reg |= GEN7_FF_VS_SCHED_HW;
7091 reg |= GEN7_FF_DS_SCHED_HW;
7092
7093 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7094}
7095
17a303ec
PZ		 7096static void lpt_init_clock_gating(struct drm_device *dev)
7097{
fac5e23e 7098 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7099
7100 /*
7101 * TODO: this bit should only be enabled when really needed, then
7102 * disabled when not needed anymore in order to save power.
7103 */
c2699524 7104 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 7105 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7106 I915_READ(SOUTH_DSPCLK_GATE_D) |
7107 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7108
7109 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7110 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7111 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7112 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7113}
7114
7d708ee4
ID		 7115static void lpt_suspend_hw(struct drm_device *dev)
7116{
fac5e23e 7117 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7118
c2699524 7119 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 7120 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7121
7122 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7123 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7124 }
7125}
7126
450174fe
ID		 7127static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7128 int general_prio_credits,
7129 int high_prio_credits)
7130{
7131 u32 misccpctl;
7132
7133 /* WaTempDisableDOPClkGating:bdw */
7134 misccpctl = I915_READ(GEN7_MISCCPCTL);
7135 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7136
7137 I915_WRITE(GEN8_L3SQCREG1,
7138 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7139 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7140
7141 /*
7142 * Wait at least 100 clocks before re-enabling clock gating.
7143 * See the definition of L3SQCREG1 in BSpec.
7144 */
7145 POSTING_READ(GEN8_L3SQCREG1);
7146 udelay(1);
7147 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7148}
7149
9498dba7
MK		 7150static void kabylake_init_clock_gating(struct drm_device *dev)
7151{
9146f308 7152 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7153
b033bb6d 7154 gen9_init_clock_gating(dev);
9498dba7
MK		 7155
7156 /* WaDisableSDEUnitClockGating:kbl */
7157 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7158 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7159 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7160
7161 /* WaDisableGamClockGating:kbl */
7162 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7163 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7164 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7165
7166 /* WaFbcNukeOnHostModify:kbl */
7167 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7168 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7169}
7170
dc00b6a0
DV		 7171static void skylake_init_clock_gating(struct drm_device *dev)
7172{
c584e2d3 7173 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7174
b033bb6d 7175 gen9_init_clock_gating(dev);
44fff99f
MK		 7176
7177 /* WAC6entrylatency:skl */
7178 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7179 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7180
7181 /* WaFbcNukeOnHostModify:skl */
7182 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7183 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7184}
7185
47c2bd97 7186static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7187{
fac5e23e 7188 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7189 enum pipe pipe;
1020a5c2 7190
7ad0dbab 7191 ilk_init_lp_watermarks(dev);
50ed5fbd 7192
ab57fff1 7193 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7194 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7195
ab57fff1 7196 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7197 I915_WRITE(CHICKEN_PAR1_1,
7198 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7199
ab57fff1 7200 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7201 for_each_pipe(dev_priv, pipe) {
07d27e20 7202 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7203 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7204 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7205 }
63801f21 7206
ab57fff1
BW		 7207 /* WaVSRefCountFullforceMissDisable:bdw */
7208 /* WaDSRefCountFullforceMissDisable:bdw */
7209 I915_WRITE(GEN7_FF_THREAD_MODE,
7210 I915_READ(GEN7_FF_THREAD_MODE) &
7211 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7212
295e8bb7
VS		 7213 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7214 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7215
7216 /* WaDisableSDEUnitClockGating:bdw */
7217 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7218 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7219
450174fe
ID		 7220 /* WaProgramL3SqcReg1Default:bdw */
7221 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7222
6d50b065
VS		 7223 /*
7224 * WaGttCachingOffByDefault:bdw
7225 * GTT cache may not work with big pages, so if those
7226 * are ever enabled GTT cache may need to be disabled.
7227 */
7228 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7229
17e0adf0
MK		 7230 /* WaKVMNotificationOnConfigChange:bdw */
7231 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7232 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7233
89d6b2b8 7234 lpt_init_clock_gating(dev);
1020a5c2
BW		 7235}
7236
cad2a2d7
ED		 7237static void haswell_init_clock_gating(struct drm_device *dev)
7238{
fac5e23e 7239 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7240
017636cc 7241 ilk_init_lp_watermarks(dev);
cad2a2d7 7242
f3fc4884
FJ		 7243 /* L3 caching of data atomics doesn't work -- disable it. */
7244 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7245 I915_WRITE(HSW_ROW_CHICKEN3,
7246 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7247
ecdb4eb7 7248 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7249 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7250 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7251 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7252
e36ea7ff
VS		 7253 /* WaVSRefCountFullforceMissDisable:hsw */
7254 I915_WRITE(GEN7_FF_THREAD_MODE,
7255 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7256
4e04632e
AG		 7257 /* WaDisable_RenderCache_OperationalFlush:hsw */
7258 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7259
fe27c606
CW		 7260 /* enable HiZ Raw Stall Optimization */
7261 I915_WRITE(CACHE_MODE_0_GEN7,
7262 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7263
ecdb4eb7 7264 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7265 I915_WRITE(CACHE_MODE_1,
7266 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7267
a12c4967
VS		 7268 /*
7269 * BSpec recommends 8x4 when MSAA is used,
7270 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7271 *
7272 * Note that PS/WM thread counts depend on the WIZ hashing
7273 * disable bit, which we don't touch here, but it's good
7274 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7275 */
7276 I915_WRITE(GEN7_GT_MODE,
98533251 7277 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7278
94411593
KG		 7279 /* WaSampleCChickenBitEnable:hsw */
7280 I915_WRITE(HALF_SLICE_CHICKEN3,
7281 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7282
ecdb4eb7 7283 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7284 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7285
90a88643
PZ		 7286 /* WaRsPkgCStateDisplayPMReq:hsw */
7287 I915_WRITE(CHICKEN_PAR1_1,
7288 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7289
17a303ec 7290 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7291}
7292
1fa61106 7293static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7294{
fac5e23e 7295 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7296 uint32_t snpcr;
6f1d69b0 7297
017636cc 7298 ilk_init_lp_watermarks(dev);
6f1d69b0 7299
231e54f6 7300 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7301
ecdb4eb7 7302 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7303 I915_WRITE(_3D_CHICKEN3,
7304 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7305
ecdb4eb7 7306 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7307 I915_WRITE(IVB_CHICKEN3,
7308 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7309 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7310
ecdb4eb7 7311 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7312 if (IS_IVB_GT1(dev))
7313 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7314 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7315
4e04632e
AG		 7316 /* WaDisable_RenderCache_OperationalFlush:ivb */
7317 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7318
ecdb4eb7 7319 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7320 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7321 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7322
ecdb4eb7 7323 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7324 I915_WRITE(GEN7_L3CNTLREG1,
7325 GEN7_WA_FOR_GEN7_L3_CONTROL);
7326 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7327 GEN7_WA_L3_CHICKEN_MODE);
7328 if (IS_IVB_GT1(dev))
7329 I915_WRITE(GEN7_ROW_CHICKEN2,
7330 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7331 else {
7332 /* must write both registers */
7333 I915_WRITE(GEN7_ROW_CHICKEN2,
7334 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7335 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7336 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7337 }
6f1d69b0 7338
ecdb4eb7 7339 /* WaForceL3Serialization:ivb */
61939d97
JB		 7340 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7341 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7342
1b80a19a 7343 /*
0f846f81 7344 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7345 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7346 */
7347 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7348 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7349
ecdb4eb7 7350 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7351 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7352 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7353 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7354
0e088b8f 7355 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7356
7357 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7358
22721343
CW		 7359 if (0) { /* causes HiZ corruption on ivb:gt1 */
7360 /* enable HiZ Raw Stall Optimization */
7361 I915_WRITE(CACHE_MODE_0_GEN7,
7362 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7363 }
116f2b6d 7364
ecdb4eb7 7365 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7366 I915_WRITE(CACHE_MODE_1,
7367 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7368
a607c1a4
VS		 7369 /*
7370 * BSpec recommends 8x4 when MSAA is used,
7371 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7372 *
7373 * Note that PS/WM thread counts depend on the WIZ hashing
7374 * disable bit, which we don't touch here, but it's good
7375 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7376 */
7377 I915_WRITE(GEN7_GT_MODE,
98533251 7378 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7379
20848223
BW		 7380 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7381 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7382 snpcr |= GEN6_MBC_SNPCR_MED;
7383 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7384
ab5c608b
BW		 7385 if (!HAS_PCH_NOP(dev))
7386 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7387
7388 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7389}
7390
1fa61106 7391static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7392{
fac5e23e 7393 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7394
ecdb4eb7 7395 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7396 I915_WRITE(_3D_CHICKEN3,
7397 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7398
ecdb4eb7 7399 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7400 I915_WRITE(IVB_CHICKEN3,
7401 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7402 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7403
fad7d36e 7404 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7405 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7406 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7407 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7408 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7409
4e04632e
AG		 7410 /* WaDisable_RenderCache_OperationalFlush:vlv */
7411 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7412
ecdb4eb7 7413 /* WaForceL3Serialization:vlv */
61939d97
JB		 7414 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7415 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7416
ecdb4eb7 7417 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7418 I915_WRITE(GEN7_ROW_CHICKEN2,
7419 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7420
ecdb4eb7 7421 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7422 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7423 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7424 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7425
46680e0a
VS		 7426 gen7_setup_fixed_func_scheduler(dev_priv);
7427
3c0edaeb 7428 /*
0f846f81 7429 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7430 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7431 */
7432 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7433 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7434
c98f5062
AG		 7435 /* WaDisableL3Bank2xClockGate:vlv
7436 * Disabling L3 clock gating- MMIO 940c[25] = 1
7437 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7438 I915_WRITE(GEN7_UCGCTL4,
7439 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7440
afd58e79
VS		 7441 /*
7442 * BSpec says this must be set, even though
7443 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7444 */
6b26c86d
DV		 7445 I915_WRITE(CACHE_MODE_1,
7446 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7447
da2518f9
VS		 7448 /*
7449 * BSpec recommends 8x4 when MSAA is used,
7450 * however in practice 16x4 seems fastest.
7451 *
7452 * Note that PS/WM thread counts depend on the WIZ hashing
7453 * disable bit, which we don't touch here, but it's good
7454 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7455 */
7456 I915_WRITE(GEN7_GT_MODE,
7457 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7458
031994ee
VS		 7459 /*
7460 * WaIncreaseL3CreditsForVLVB0:vlv
7461 * This is the hardware default actually.
7462 */
7463 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7464
2d809570 7465 /*
ecdb4eb7 7466 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7467 * Disable clock gating on th GCFG unit to prevent a delay
7468 * in the reporting of vblank events.
7469 */
7a0d1eed 7470 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7471}
7472
a4565da8
VS		 7473static void cherryview_init_clock_gating(struct drm_device *dev)
7474{
fac5e23e 7475 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7476
232ce337
VS		 7477 /* WaVSRefCountFullforceMissDisable:chv */
7478 /* WaDSRefCountFullforceMissDisable:chv */
7479 I915_WRITE(GEN7_FF_THREAD_MODE,
7480 I915_READ(GEN7_FF_THREAD_MODE) &
7481 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7482
7483 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7484 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7485 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7486
7487 /* WaDisableCSUnitClockGating:chv */
7488 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7489 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7490
7491 /* WaDisableSDEUnitClockGating:chv */
7492 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7493 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7494
450174fe
ID		 7495 /*
7496 * WaProgramL3SqcReg1Default:chv
7497 * See gfxspecs/Related Documents/Performance Guide/
7498 * LSQC Setting Recommendations.
7499 */
7500 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7501
6d50b065
VS		 7502 /*
7503 * GTT cache may not work with big pages, so if those
7504 * are ever enabled GTT cache may need to be disabled.
7505 */
7506 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7507}
7508
1fa61106 7509static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7510{
fac5e23e 7511 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7512 uint32_t dspclk_gate;
7513
7514 I915_WRITE(RENCLK_GATE_D1, 0);
7515 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7516 GS_UNIT_CLOCK_GATE_DISABLE |
7517 CL_UNIT_CLOCK_GATE_DISABLE);
7518 I915_WRITE(RAMCLK_GATE_D, 0);
7519 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7520 OVRUNIT_CLOCK_GATE_DISABLE |
7521 OVCUNIT_CLOCK_GATE_DISABLE;
7522 if (IS_GM45(dev))
7523 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7524 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7525
7526 /* WaDisableRenderCachePipelinedFlush */
7527 I915_WRITE(CACHE_MODE_0,
7528 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7529
4e04632e
AG		 7530 /* WaDisable_RenderCache_OperationalFlush:g4x */
7531 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7532
0e088b8f 7533 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7534}
7535
1fa61106 7536static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7537{
fac5e23e 7538 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7539
7540 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7541 I915_WRITE(RENCLK_GATE_D2, 0);
7542 I915_WRITE(DSPCLK_GATE_D, 0);
7543 I915_WRITE(RAMCLK_GATE_D, 0);
7544 I915_WRITE16(DEUC, 0);
20f94967
VS		 7545 I915_WRITE(MI_ARB_STATE,
7546 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7547
7548 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7549 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7550}
7551
1fa61106 7552static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7553{
fac5e23e 7554 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7555
7556 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7557 I965_RCC_CLOCK_GATE_DISABLE |
7558 I965_RCPB_CLOCK_GATE_DISABLE |
7559 I965_ISC_CLOCK_GATE_DISABLE |
7560 I965_FBC_CLOCK_GATE_DISABLE);
7561 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7562 I915_WRITE(MI_ARB_STATE,
7563 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7564
7565 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7566 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7567}
7568
1fa61106 7569static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7570{
fac5e23e 7571 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7572 u32 dstate = I915_READ(D_STATE);
7573
7574 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7575 DSTATE_DOT_CLOCK_GATING;
7576 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7577
7578 if (IS_PINEVIEW(dev))
7579 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7580
7581 /* IIR "flip pending" means done if this bit is set */
7582 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7583
7584 /* interrupts should cause a wake up from C3 */
3299254f 7585 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7586
7587 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7588 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7589
7590 I915_WRITE(MI_ARB_STATE,
7591 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7592}
7593
1fa61106 7594static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7595{
fac5e23e 7596 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7597
7598 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7599
7600 /* interrupts should cause a wake up from C3 */
7601 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7602 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7603
7604 I915_WRITE(MEM_MODE,
7605 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7606}
7607
1fa61106 7608static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7609{
fac5e23e 7610 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7611
7612 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7613
7614 I915_WRITE(MEM_MODE,
7615 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7616 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7617}
7618
6f1d69b0
ED		 7619void intel_init_clock_gating(struct drm_device *dev)
7620{
fac5e23e 7621 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7622
bb400da9 7623 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7624}
7625
7d708ee4
ID		 7626void intel_suspend_hw(struct drm_device *dev)
7627{
7628 if (HAS_PCH_LPT(dev))
7629 lpt_suspend_hw(dev);
7630}
7631
bb400da9
ID		 7632static void nop_init_clock_gating(struct drm_device *dev)
7633{
7634 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7635}
7636
7637/**
7638 * intel_init_clock_gating_hooks - setup the clock gating hooks
7639 * @dev_priv: device private
7640 *
7641 * Setup the hooks that configure which clocks of a given platform can be
7642 * gated and also apply various GT and display specific workarounds for these
7643 * platforms. Note that some GT specific workarounds are applied separately
7644 * when GPU contexts or batchbuffers start their execution.
7645 */
7646void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7647{
7648 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7649 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7650 else if (IS_KABYLAKE(dev_priv))
9498dba7 7651 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7652 else if (IS_BROXTON(dev_priv))
7653 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7654 else if (IS_BROADWELL(dev_priv))
7655 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7656 else if (IS_CHERRYVIEW(dev_priv))
7657 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7658 else if (IS_HASWELL(dev_priv))
7659 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7660 else if (IS_IVYBRIDGE(dev_priv))
7661 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7662 else if (IS_VALLEYVIEW(dev_priv))
7663 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7664 else if (IS_GEN6(dev_priv))
7665 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7666 else if (IS_GEN5(dev_priv))
7667 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7668 else if (IS_G4X(dev_priv))
7669 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7670 else if (IS_CRESTLINE(dev_priv))
7671 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7672 else if (IS_BROADWATER(dev_priv))
7673 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7674 else if (IS_GEN3(dev_priv))
7675 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7676 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7677 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7678 else if (IS_GEN2(dev_priv))
7679 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7680 else {
7681 MISSING_CASE(INTEL_DEVID(dev_priv));
7682 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7683 }
7684}
7685
1fa61106
ED		 7686/* Set up chip specific power management-related functions */
7687void intel_init_pm(struct drm_device *dev)
7688{
fac5e23e 7689 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7690
7ff0ebcc 7691 intel_fbc_init(dev_priv);
1fa61106 7692
c921aba8
DV		 7693 /* For cxsr */
7694 if (IS_PINEVIEW(dev))
7695 i915_pineview_get_mem_freq(dev);
7696 else if (IS_GEN5(dev))
7697 i915_ironlake_get_mem_freq(dev);
7698
1fa61106 7699 /* For FIFO watermark updates */
f5ed50cb 7700 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7701 skl_setup_wm_latency(dev);
2d41c0b5 7702 dev_priv->display.update_wm = skl_update_wm;
98d39494 7703 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7704 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7705 ilk_setup_wm_latency(dev);
53615a5e 7706
bd602544
VS		 7707 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7708 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7709 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7710 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7711 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7712 dev_priv->display.compute_intermediate_wm =
7713 ilk_compute_intermediate_wm;
7714 dev_priv->display.initial_watermarks =
7715 ilk_initial_watermarks;
7716 dev_priv->display.optimize_watermarks =
7717 ilk_optimize_watermarks;
bd602544
VS		 7718 } else {
7719 DRM_DEBUG_KMS("Failed to read display plane latency. "
7720 "Disable CxSR\n");
7721 }
a4565da8 7722 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7723 vlv_setup_wm_latency(dev);
262cd2e1 7724 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7725 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7726 vlv_setup_wm_latency(dev);
26e1fe4f 7727 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7728 } else if (IS_PINEVIEW(dev)) {
7729 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7730 dev_priv->is_ddr3,
7731 dev_priv->fsb_freq,
7732 dev_priv->mem_freq)) {
7733 DRM_INFO("failed to find known CxSR latency "
7734 "(found ddr%s fsb freq %d, mem freq %d), "
7735 "disabling CxSR\n",
7736 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7737 dev_priv->fsb_freq, dev_priv->mem_freq);
7738 /* Disable CxSR and never update its watermark again */
5209b1f4 7739 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7740 dev_priv->display.update_wm = NULL;
7741 } else
7742 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7743 } else if (IS_G4X(dev)) {
7744 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7745 } else if (IS_GEN4(dev)) {
7746 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7747 } else if (IS_GEN3(dev)) {
7748 dev_priv->display.update_wm = i9xx_update_wm;
7749 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7750 } else if (IS_GEN2(dev)) {
7751 if (INTEL_INFO(dev)->num_pipes == 1) {
7752 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7753 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7754 } else {
7755 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7756 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7757 }
feb56b93
DV		 7758 } else {
7759 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7760 }
7761}
7762
87660502
L		 7763static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7764{
7765 uint32_t flags =
7766 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7767
7768 switch (flags) {
7769 case GEN6_PCODE_SUCCESS:
7770 return 0;
7771 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7772 case GEN6_PCODE_ILLEGAL_CMD:
7773 return -ENXIO;
7774 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7775 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7776 return -EOVERFLOW;
7777 case GEN6_PCODE_TIMEOUT:
7778 return -ETIMEDOUT;
7779 default:
7780 MISSING_CASE(flags)
7781 return 0;
7782 }
7783}
7784
7785static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7786{
7787 uint32_t flags =
7788 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7789
7790 switch (flags) {
7791 case GEN6_PCODE_SUCCESS:
7792 return 0;
7793 case GEN6_PCODE_ILLEGAL_CMD:
7794 return -ENXIO;
7795 case GEN7_PCODE_TIMEOUT:
7796 return -ETIMEDOUT;
7797 case GEN7_PCODE_ILLEGAL_DATA:
7798 return -EINVAL;
7799 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7800 return -EOVERFLOW;
7801 default:
7802 MISSING_CASE(flags);
7803 return 0;
7804 }
7805}
7806
151a49d0 7807int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7808{
87660502
L		 7809 int status;
7810
4fc688ce 7811 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7812
3f5582dd
CW		 7813 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7814 * use te fw I915_READ variants to reduce the amount of work
7815 * required when reading/writing.
7816 */
7817
7818 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7819 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7820 return -EAGAIN;
7821 }
7822
3f5582dd
CW		 7823 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7824 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7825 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7826
3f5582dd
CW		 7827 if (intel_wait_for_register_fw(dev_priv,
7828 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7829 500)) {
42c0526c
BW		 7830 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7831 return -ETIMEDOUT;
7832 }
7833
3f5582dd
CW		 7834 *val = I915_READ_FW(GEN6_PCODE_DATA);
7835 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7836
87660502
L		 7837 if (INTEL_GEN(dev_priv) > 6)
7838 status = gen7_check_mailbox_status(dev_priv);
7839 else
7840 status = gen6_check_mailbox_status(dev_priv);
7841
7842 if (status) {
7843 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7844 status);
7845 return status;
7846 }
7847
42c0526c
BW		 7848 return 0;
7849}
7850
3f5582dd 7851int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7852 u32 mbox, u32 val)
42c0526c 7853{
87660502
L		 7854 int status;
7855
4fc688ce 7856 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7857
3f5582dd
CW		 7858 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7859 * use te fw I915_READ variants to reduce the amount of work
7860 * required when reading/writing.
7861 */
7862
7863 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7864 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7865 return -EAGAIN;
7866 }
7867
3f5582dd
CW		 7868 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7869 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7870
3f5582dd
CW		 7871 if (intel_wait_for_register_fw(dev_priv,
7872 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7873 500)) {
42c0526c
BW		 7874 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7875 return -ETIMEDOUT;
7876 }
7877
3f5582dd 7878 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7879
87660502
L		 7880 if (INTEL_GEN(dev_priv) > 6)
7881 status = gen7_check_mailbox_status(dev_priv);
7882 else
7883 status = gen6_check_mailbox_status(dev_priv);
7884
7885 if (status) {
7886 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7887 status);
7888 return status;
7889 }
7890
42c0526c
BW		 7891 return 0;
7892}
a0e4e199 7893
dd06f88c
VS		 7894static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7895{
c30fec65
VS		 7896 /*
7897 * N = val - 0xb7
7898 * Slow = Fast = GPLL ref * N
7899 */
7900 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7901}
7902
b55dd647 7903static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7904{
c30fec65 7905 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7906}
7907
b55dd647 7908static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7909{
c30fec65
VS		 7910 /*
7911 * N = val / 2
7912 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7913 */
7914 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7915}
7916
b55dd647 7917static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7918{
1c14762d 7919 /* CHV needs even values */
c30fec65 7920 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7921}
7922
616bc820 7923int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7924{
2d1fe073 7925 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7926 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7927 GEN9_FREQ_SCALER);
2d1fe073 7928 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7929 return chv_gpu_freq(dev_priv, val);
2d1fe073 7930 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7931 return byt_gpu_freq(dev_priv, val);
7932 else
7933 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7934}
7935
616bc820
VS		 7936int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7937{
2d1fe073 7938 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7939 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7940 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7941 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7942 return chv_freq_opcode(dev_priv, val);
2d1fe073 7943 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7944 return byt_freq_opcode(dev_priv, val);
7945 else
500a3d2e 7946 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7947}
22b1b2f8 7948
6ad790c0
CW		 7949struct request_boost {
7950 struct work_struct work;
eed29a5b 7951 struct drm_i915_gem_request *req;
6ad790c0
CW		 7952};
7953
7954static void __intel_rps_boost_work(struct work_struct *work)
7955{
7956 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7957 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7958
f69a02c9 7959 if (!i915_gem_request_completed(req))
c033666a 7960 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7961
e8a261ea 7962 i915_gem_request_put(req);
6ad790c0
CW		 7963 kfree(boost);
7964}
7965
91d14251 7966void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7967{
7968 struct request_boost *boost;
7969
91d14251 7970 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7971 return;
7972
f69a02c9 7973 if (i915_gem_request_completed(req))
e61b9958
CW		 7974 return;
7975
6ad790c0
CW		 7976 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7977 if (boost == NULL)
7978 return;
7979
e8a261ea 7980 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7981
7982 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7983 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7984}
7985
f742a552 7986void intel_pm_setup(struct drm_device *dev)
907b28c5 7987{
fac5e23e 7988 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 7989
f742a552 7990 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7991 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7992
54b4f68f
CW		 7993 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7994 __intel_autoenable_gt_powersave);
1854d5ca 7995 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 7996
33688d95 7997 dev_priv->pm.suspended = false;
1f814dac 7998 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7999 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 8000}
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