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drm/i915: Linetime watermarks are a HSW feature
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f9dcb0df 33#include <linux/vgaarb.h>
f4db9321 34#include <drm/i915_powerwell.h>
8a187455 35#include <linux/pm_runtime.h>
85208be0 36
dc39fff7
BW		 37/**
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
f6750b3c
ED		 58/* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 61 *
f6750b3c
ED		 62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
85208be0 64 *
f6750b3c
ED		 65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
85208be0
ED		 67 */
68
1fa61106 69static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 fbc_ctl;
73
74 /* Disable compression */
75 fbc_ctl = I915_READ(FBC_CONTROL);
76 if ((fbc_ctl & FBC_CTL_EN) == 0)
77 return;
78
79 fbc_ctl &= ~FBC_CTL_EN;
80 I915_WRITE(FBC_CONTROL, fbc_ctl);
81
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
85 return;
86 }
87
88 DRM_DEBUG_KMS("disabled FBC\n");
89}
90
993495ae 91static void i8xx_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 92{
93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch;
100 int plane, i;
159f9875 101 u32 fbc_ctl;
85208be0 102
5c3fe8b0 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 104 if (fb->pitches[0] < cfb_pitch)
105 cfb_pitch = fb->pitches[0];
106
42a430f5
VS		 107 /* FBC_CTL wants 32B or 64B units */
108 if (IS_GEN2(dev))
109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else
111 cfb_pitch = (cfb_pitch / 64) - 1;
85208be0
ED		 112 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
113
114 /* Clear old tags */
115 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
116 I915_WRITE(FBC_TAG + (i * 4), 0);
117
159f9875
VS		 118 if (IS_GEN4(dev)) {
119 u32 fbc_ctl2;
120
121 /* Set it up... */
122 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
123 fbc_ctl2 |= plane;
124 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
125 I915_WRITE(FBC_FENCE_OFF, crtc->y);
126 }
85208be0
ED		 127
128 /* enable it... */
993495ae
VS		 129 fbc_ctl = I915_READ(FBC_CONTROL);
130 fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
131 fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
85208be0
ED		 132 if (IS_I945GM(dev))
133 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
134 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
85208be0
ED		 135 fbc_ctl |= obj->fence_reg;
136 I915_WRITE(FBC_CONTROL, fbc_ctl);
137
84f44ce7
VS		 138 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
139 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 140}
141
1fa61106 142static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 143{
144 struct drm_i915_private *dev_priv = dev->dev_private;
145
146 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
147}
148
993495ae 149static void g4x_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 150{
151 struct drm_device *dev = crtc->dev;
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 struct drm_framebuffer *fb = crtc->fb;
154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
155 struct drm_i915_gem_object *obj = intel_fb->obj;
156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
157 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
85208be0
ED		 158 u32 dpfc_ctl;
159
160 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
163
85208be0
ED		 164 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
165
166 /* enable it... */
167 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
168
84f44ce7 169 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 170}
171
1fa61106 172static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 173{
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 u32 dpfc_ctl;
176
177 /* Disable compression */
178 dpfc_ctl = I915_READ(DPFC_CONTROL);
179 if (dpfc_ctl & DPFC_CTL_EN) {
180 dpfc_ctl &= ~DPFC_CTL_EN;
181 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
182
183 DRM_DEBUG_KMS("disabled FBC\n");
184 }
185}
186
1fa61106 187static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 188{
189 struct drm_i915_private *dev_priv = dev->dev_private;
190
191 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
192}
193
194static void sandybridge_blit_fbc_update(struct drm_device *dev)
195{
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 u32 blt_ecoskpd;
198
199 /* Make sure blitter notifies FBC of writes */
940aece4
D		 200
201 /* Blitter is part of Media powerwell on VLV. No impact of
202 * his param in other platforms for now */
203 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
c8d9a590 204
85208be0
ED		 205 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
206 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
207 GEN6_BLITTER_LOCK_SHIFT;
208 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
209 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
210 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
211 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
212 GEN6_BLITTER_LOCK_SHIFT);
213 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
214 POSTING_READ(GEN6_BLITTER_ECOSKPD);
c8d9a590 215
940aece4 216 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
85208be0
ED		 217}
218
993495ae 219static void ironlake_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 220{
221 struct drm_device *dev = crtc->dev;
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 struct drm_framebuffer *fb = crtc->fb;
224 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
225 struct drm_i915_gem_object *obj = intel_fb->obj;
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
85208be0
ED		 228 u32 dpfc_ctl;
229
230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
231 dpfc_ctl &= DPFC_RESERVED;
232 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
233 /* Set persistent mode for front-buffer rendering, ala X. */
234 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
d629336b
VS		 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg;
85208be0
ED		 238 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
239
85208be0 240 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 241 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 242 /* enable it... */
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
244
245 if (IS_GEN6(dev)) {
246 I915_WRITE(SNB_DPFC_CTL_SA,
247 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
248 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
249 sandybridge_blit_fbc_update(dev);
250 }
251
84f44ce7 252 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 253}
254
1fa61106 255static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 u32 dpfc_ctl;
259
260 /* Disable compression */
261 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
262 if (dpfc_ctl & DPFC_CTL_EN) {
263 dpfc_ctl &= ~DPFC_CTL_EN;
264 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
265
266 DRM_DEBUG_KMS("disabled FBC\n");
267 }
268}
269
1fa61106 270static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 271{
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
275}
276
993495ae 277static void gen7_enable_fbc(struct drm_crtc *crtc)
abe959c7
RV		 278{
279 struct drm_device *dev = crtc->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct drm_framebuffer *fb = crtc->fb;
282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
283 struct drm_i915_gem_object *obj = intel_fb->obj;
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
285
f343c5f6 286 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 287
288 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
289 IVB_DPFC_CTL_FENCE_EN |
290 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291
891348b2 292 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 294 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 295 } else {
7dd23ba0 296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
298 HSW_BYPASS_FBC_QUEUE);
891348b2 299 }
b74ea102 300
abe959c7
RV		 301 I915_WRITE(SNB_DPFC_CTL_SA,
302 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
303 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
304
305 sandybridge_blit_fbc_update(dev);
306
b19870ee 307 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
abe959c7
RV		 308}
309
85208be0
ED		 310bool intel_fbc_enabled(struct drm_device *dev)
311{
312 struct drm_i915_private *dev_priv = dev->dev_private;
313
314 if (!dev_priv->display.fbc_enabled)
315 return false;
316
317 return dev_priv->display.fbc_enabled(dev);
318}
319
320static void intel_fbc_work_fn(struct work_struct *__work)
321{
322 struct intel_fbc_work *work =
323 container_of(to_delayed_work(__work),
324 struct intel_fbc_work, work);
325 struct drm_device *dev = work->crtc->dev;
326 struct drm_i915_private *dev_priv = dev->dev_private;
327
328 mutex_lock(&dev->struct_mutex);
5c3fe8b0 329 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 330 /* Double check that we haven't switched fb without cancelling
331 * the prior work.
332 */
333 if (work->crtc->fb == work->fb) {
993495ae 334 dev_priv->display.enable_fbc(work->crtc);
85208be0 335
5c3fe8b0
BW		 336 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
338 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 339 }
340
5c3fe8b0 341 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 342 }
343 mutex_unlock(&dev->struct_mutex);
344
345 kfree(work);
346}
347
348static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
349{
5c3fe8b0 350 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 351 return;
352
353 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
354
355 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 356 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 357 * entirely asynchronously.
358 */
5c3fe8b0 359 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 360 /* tasklet was killed before being run, clean up */
5c3fe8b0 361 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 362
363 /* Mark the work as no longer wanted so that if it does
364 * wake-up (because the work was already running and waiting
365 * for our mutex), it will discover that is no longer
366 * necessary to run.
367 */
5c3fe8b0 368 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 369}
370
993495ae 371static void intel_enable_fbc(struct drm_crtc *crtc)
85208be0
ED		 372{
373 struct intel_fbc_work *work;
374 struct drm_device *dev = crtc->dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376
377 if (!dev_priv->display.enable_fbc)
378 return;
379
380 intel_cancel_fbc_work(dev_priv);
381
b14c5679 382 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 383 if (work == NULL) {
6cdcb5e7 384 DRM_ERROR("Failed to allocate FBC work structure\n");
993495ae 385 dev_priv->display.enable_fbc(crtc);
85208be0
ED		 386 return;
387 }
388
389 work->crtc = crtc;
390 work->fb = crtc->fb;
85208be0
ED		 391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
ef644fda 461 const struct drm_display_mode *adjusted_mode;
37327abd 462 unsigned int max_width, max_height;
85208be0 463
29ebf90f
CW		 464 if (!I915_HAS_FBC(dev)) {
465 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 466 return;
29ebf90f 467 }
85208be0 468
29ebf90f
CW		 469 if (!i915_powersave) {
470 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
471 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 472 return;
29ebf90f 473 }
85208be0
ED		 474
475 /*
476 * If FBC is already on, we just have to verify that we can
477 * keep it that way...
478 * Need to disable if:
479 * - more than one pipe is active
480 * - changing FBC params (stride, fence, mode)
481 * - new fb is too large to fit in compressed buffer
482 * - going to an unsupported config (interlace, pixel multiply, etc.)
483 */
484 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 485 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 486 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 487 if (crtc) {
29ebf90f
CW		 488 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
489 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 490 goto out_disable;
491 }
492 crtc = tmp_crtc;
493 }
494 }
495
496 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 497 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
498 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 499 goto out_disable;
500 }
501
502 intel_crtc = to_intel_crtc(crtc);
503 fb = crtc->fb;
504 intel_fb = to_intel_framebuffer(fb);
505 obj = intel_fb->obj;
ef644fda 506 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 507
8a5729a3
DL		 508 if (i915_enable_fbc < 0 &&
509 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 510 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
511 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 512 goto out_disable;
85208be0 513 }
8a5729a3 514 if (!i915_enable_fbc) {
29ebf90f
CW		 515 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
516 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 517 goto out_disable;
518 }
ef644fda
VS		 519 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
520 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 521 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
522 DRM_DEBUG_KMS("mode incompatible with compression, "
523 "disabling\n");
85208be0
ED		 524 goto out_disable;
525 }
f85da868
PZ		 526
527 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 528 max_width = 4096;
529 max_height = 2048;
f85da868 530 } else {
37327abd
VS		 531 max_width = 2048;
532 max_height = 1536;
f85da868 533 }
37327abd
VS		 534 if (intel_crtc->config.pipe_src_w > max_width ||
535 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 536 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 538 goto out_disable;
539 }
c5a44aa0
VS		 540 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
541 intel_crtc->plane != PLANE_A) {
29ebf90f 542 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
c5a44aa0 543 DRM_DEBUG_KMS("plane not A, disabling compression\n");
85208be0
ED		 544 goto out_disable;
545 }
546
547 /* The use of a CPU fence is mandatory in order to detect writes
548 * by the CPU to the scanout and trigger updates to the FBC.
549 */
550 if (obj->tiling_mode != I915_TILING_X ||
551 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 552 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
553 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 554 goto out_disable;
555 }
556
557 /* If the kernel debugger is active, always disable compression */
558 if (in_dbg_master())
559 goto out_disable;
560
11be49eb 561 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 562 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
563 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 564 goto out_disable;
565 }
566
85208be0
ED		 567 /* If the scanout has not changed, don't modify the FBC settings.
568 * Note that we make the fundamental assumption that the fb->obj
569 * cannot be unpinned (and have its GTT offset and fence revoked)
570 * without first being decoupled from the scanout and FBC disabled.
571 */
5c3fe8b0
BW		 572 if (dev_priv->fbc.plane == intel_crtc->plane &&
573 dev_priv->fbc.fb_id == fb->base.id &&
574 dev_priv->fbc.y == crtc->y)
85208be0
ED		 575 return;
576
577 if (intel_fbc_enabled(dev)) {
578 /* We update FBC along two paths, after changing fb/crtc
579 * configuration (modeswitching) and after page-flipping
580 * finishes. For the latter, we know that not only did
581 * we disable the FBC at the start of the page-flip
582 * sequence, but also more than one vblank has passed.
583 *
584 * For the former case of modeswitching, it is possible
585 * to switch between two FBC valid configurations
586 * instantaneously so we do need to disable the FBC
587 * before we can modify its control registers. We also
588 * have to wait for the next vblank for that to take
589 * effect. However, since we delay enabling FBC we can
590 * assume that a vblank has passed since disabling and
591 * that we can safely alter the registers in the deferred
592 * callback.
593 *
594 * In the scenario that we go from a valid to invalid
595 * and then back to valid FBC configuration we have
596 * no strict enforcement that a vblank occurred since
597 * disabling the FBC. However, along all current pipe
598 * disabling paths we do need to wait for a vblank at
599 * some point. And we wait before enabling FBC anyway.
600 */
601 DRM_DEBUG_KMS("disabling active FBC for update\n");
602 intel_disable_fbc(dev);
603 }
604
993495ae 605 intel_enable_fbc(crtc);
29ebf90f 606 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 607 return;
608
609out_disable:
610 /* Multiple disables should be harmless */
611 if (intel_fbc_enabled(dev)) {
612 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
613 intel_disable_fbc(dev);
614 }
11be49eb 615 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 616}
617
c921aba8
DV		 618static void i915_pineview_get_mem_freq(struct drm_device *dev)
619{
620 drm_i915_private_t *dev_priv = dev->dev_private;
621 u32 tmp;
622
623 tmp = I915_READ(CLKCFG);
624
625 switch (tmp & CLKCFG_FSB_MASK) {
626 case CLKCFG_FSB_533:
627 dev_priv->fsb_freq = 533; /* 133*4 */
628 break;
629 case CLKCFG_FSB_800:
630 dev_priv->fsb_freq = 800; /* 200*4 */
631 break;
632 case CLKCFG_FSB_667:
633 dev_priv->fsb_freq = 667; /* 167*4 */
634 break;
635 case CLKCFG_FSB_400:
636 dev_priv->fsb_freq = 400; /* 100*4 */
637 break;
638 }
639
640 switch (tmp & CLKCFG_MEM_MASK) {
641 case CLKCFG_MEM_533:
642 dev_priv->mem_freq = 533;
643 break;
644 case CLKCFG_MEM_667:
645 dev_priv->mem_freq = 667;
646 break;
647 case CLKCFG_MEM_800:
648 dev_priv->mem_freq = 800;
649 break;
650 }
651
652 /* detect pineview DDR3 setting */
653 tmp = I915_READ(CSHRDDR3CTL);
654 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
655}
656
657static void i915_ironlake_get_mem_freq(struct drm_device *dev)
658{
659 drm_i915_private_t *dev_priv = dev->dev_private;
660 u16 ddrpll, csipll;
661
662 ddrpll = I915_READ16(DDRMPLL1);
663 csipll = I915_READ16(CSIPLL0);
664
665 switch (ddrpll & 0xff) {
666 case 0xc:
667 dev_priv->mem_freq = 800;
668 break;
669 case 0x10:
670 dev_priv->mem_freq = 1066;
671 break;
672 case 0x14:
673 dev_priv->mem_freq = 1333;
674 break;
675 case 0x18:
676 dev_priv->mem_freq = 1600;
677 break;
678 default:
679 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
680 ddrpll & 0xff);
681 dev_priv->mem_freq = 0;
682 break;
683 }
684
20e4d407 685 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 686
687 switch (csipll & 0x3ff) {
688 case 0x00c:
689 dev_priv->fsb_freq = 3200;
690 break;
691 case 0x00e:
692 dev_priv->fsb_freq = 3733;
693 break;
694 case 0x010:
695 dev_priv->fsb_freq = 4266;
696 break;
697 case 0x012:
698 dev_priv->fsb_freq = 4800;
699 break;
700 case 0x014:
701 dev_priv->fsb_freq = 5333;
702 break;
703 case 0x016:
704 dev_priv->fsb_freq = 5866;
705 break;
706 case 0x018:
707 dev_priv->fsb_freq = 6400;
708 break;
709 default:
710 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
711 csipll & 0x3ff);
712 dev_priv->fsb_freq = 0;
713 break;
714 }
715
716 if (dev_priv->fsb_freq == 3200) {
20e4d407 717 dev_priv->ips.c_m = 0;
c921aba8 718 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 719 dev_priv->ips.c_m = 1;
c921aba8 720 } else {
20e4d407 721 dev_priv->ips.c_m = 2;
c921aba8
DV		 722 }
723}
724
b445e3b0
ED		 725static const struct cxsr_latency cxsr_latency_table[] = {
726 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
727 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
728 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
729 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
730 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
731
732 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
733 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
734 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
735 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
736 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
737
738 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
739 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
740 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
741 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
742 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
743
744 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
745 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
746 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
747 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
748 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
749
750 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
751 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
752 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
753 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
754 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
755
756 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
757 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
758 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
759 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
760 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
761};
762
63c62275 763static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 764 int is_ddr3,
765 int fsb,
766 int mem)
767{
768 const struct cxsr_latency *latency;
769 int i;
770
771 if (fsb == 0 || mem == 0)
772 return NULL;
773
774 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
775 latency = &cxsr_latency_table[i];
776 if (is_desktop == latency->is_desktop &&
777 is_ddr3 == latency->is_ddr3 &&
778 fsb == latency->fsb_freq && mem == latency->mem_freq)
779 return latency;
780 }
781
782 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
783
784 return NULL;
785}
786
1fa61106 787static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790
791 /* deactivate cxsr */
792 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
793}
794
795/*
796 * Latency for FIFO fetches is dependent on several factors:
797 * - memory configuration (speed, channels)
798 * - chipset
799 * - current MCH state
800 * It can be fairly high in some situations, so here we assume a fairly
801 * pessimal value. It's a tradeoff between extra memory fetches (if we
802 * set this value too high, the FIFO will fetch frequently to stay full)
803 * and power consumption (set it too low to save power and we might see
804 * FIFO underruns and display "flicker").
805 *
806 * A value of 5us seems to be a good balance; safe for very low end
807 * platforms but not overly aggressive on lower latency configs.
808 */
809static const int latency_ns = 5000;
810
1fa61106 811static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 812{
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t dsparb = I915_READ(DSPARB);
815 int size;
816
817 size = dsparb & 0x7f;
818 if (plane)
819 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
820
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
822 plane ? "B" : "A", size);
823
824 return size;
825}
826
1fa61106 827static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 828{
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 uint32_t dsparb = I915_READ(DSPARB);
831 int size;
832
833 size = dsparb & 0x1ff;
834 if (plane)
835 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
836 size >>= 1; /* Convert to cachelines */
837
838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
839 plane ? "B" : "A", size);
840
841 return size;
842}
843
1fa61106 844static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 845{
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 uint32_t dsparb = I915_READ(DSPARB);
848 int size;
849
850 size = dsparb & 0x7f;
851 size >>= 2; /* Convert to cachelines */
852
853 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
854 plane ? "B" : "A",
855 size);
856
857 return size;
858}
859
1fa61106 860static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 861{
862 struct drm_i915_private *dev_priv = dev->dev_private;
863 uint32_t dsparb = I915_READ(DSPARB);
864 int size;
865
866 size = dsparb & 0x7f;
867 size >>= 1; /* Convert to cachelines */
868
869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
870 plane ? "B" : "A", size);
871
872 return size;
873}
874
875/* Pineview has different values for various configs */
876static const struct intel_watermark_params pineview_display_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882};
883static const struct intel_watermark_params pineview_display_hplloff_wm = {
884 PINEVIEW_DISPLAY_FIFO,
885 PINEVIEW_MAX_WM,
886 PINEVIEW_DFT_HPLLOFF_WM,
887 PINEVIEW_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE
889};
890static const struct intel_watermark_params pineview_cursor_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE,
896};
897static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
898 PINEVIEW_CURSOR_FIFO,
899 PINEVIEW_CURSOR_MAX_WM,
900 PINEVIEW_CURSOR_DFT_WM,
901 PINEVIEW_CURSOR_GUARD_WM,
902 PINEVIEW_FIFO_LINE_SIZE
903};
904static const struct intel_watermark_params g4x_wm_info = {
905 G4X_FIFO_SIZE,
906 G4X_MAX_WM,
907 G4X_MAX_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910};
911static const struct intel_watermark_params g4x_cursor_wm_info = {
912 I965_CURSOR_FIFO,
913 I965_CURSOR_MAX_WM,
914 I965_CURSOR_DFT_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917};
918static const struct intel_watermark_params valleyview_wm_info = {
919 VALLEYVIEW_FIFO_SIZE,
920 VALLEYVIEW_MAX_WM,
921 VALLEYVIEW_MAX_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924};
925static const struct intel_watermark_params valleyview_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 VALLEYVIEW_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 G4X_FIFO_LINE_SIZE,
931};
932static const struct intel_watermark_params i965_cursor_wm_info = {
933 I965_CURSOR_FIFO,
934 I965_CURSOR_MAX_WM,
935 I965_CURSOR_DFT_WM,
936 2,
937 I915_FIFO_LINE_SIZE,
938};
939static const struct intel_watermark_params i945_wm_info = {
940 I945_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945};
946static const struct intel_watermark_params i915_wm_info = {
947 I915_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I915_FIFO_LINE_SIZE
952};
953static const struct intel_watermark_params i855_wm_info = {
954 I855GM_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959};
960static const struct intel_watermark_params i830_wm_info = {
961 I830_FIFO_SIZE,
962 I915_MAX_WM,
963 1,
964 2,
965 I830_FIFO_LINE_SIZE
966};
967
968static const struct intel_watermark_params ironlake_display_wm_info = {
969 ILK_DISPLAY_FIFO,
970 ILK_DISPLAY_MAXWM,
971 ILK_DISPLAY_DFTWM,
972 2,
973 ILK_FIFO_LINE_SIZE
974};
975static const struct intel_watermark_params ironlake_cursor_wm_info = {
976 ILK_CURSOR_FIFO,
977 ILK_CURSOR_MAXWM,
978 ILK_CURSOR_DFTWM,
979 2,
980 ILK_FIFO_LINE_SIZE
981};
982static const struct intel_watermark_params ironlake_display_srwm_info = {
983 ILK_DISPLAY_SR_FIFO,
984 ILK_DISPLAY_MAX_SRWM,
985 ILK_DISPLAY_DFT_SRWM,
986 2,
987 ILK_FIFO_LINE_SIZE
988};
989static const struct intel_watermark_params ironlake_cursor_srwm_info = {
990 ILK_CURSOR_SR_FIFO,
991 ILK_CURSOR_MAX_SRWM,
992 ILK_CURSOR_DFT_SRWM,
993 2,
994 ILK_FIFO_LINE_SIZE
995};
996
997static const struct intel_watermark_params sandybridge_display_wm_info = {
998 SNB_DISPLAY_FIFO,
999 SNB_DISPLAY_MAXWM,
1000 SNB_DISPLAY_DFTWM,
1001 2,
1002 SNB_FIFO_LINE_SIZE
1003};
1004static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1005 SNB_CURSOR_FIFO,
1006 SNB_CURSOR_MAXWM,
1007 SNB_CURSOR_DFTWM,
1008 2,
1009 SNB_FIFO_LINE_SIZE
1010};
1011static const struct intel_watermark_params sandybridge_display_srwm_info = {
1012 SNB_DISPLAY_SR_FIFO,
1013 SNB_DISPLAY_MAX_SRWM,
1014 SNB_DISPLAY_DFT_SRWM,
1015 2,
1016 SNB_FIFO_LINE_SIZE
1017};
1018static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1019 SNB_CURSOR_SR_FIFO,
1020 SNB_CURSOR_MAX_SRWM,
1021 SNB_CURSOR_DFT_SRWM,
1022 2,
1023 SNB_FIFO_LINE_SIZE
1024};
1025
1026
1027/**
1028 * intel_calculate_wm - calculate watermark level
1029 * @clock_in_khz: pixel clock
1030 * @wm: chip FIFO params
1031 * @pixel_size: display pixel size
1032 * @latency_ns: memory latency for the platform
1033 *
1034 * Calculate the watermark level (the level at which the display plane will
1035 * start fetching from memory again). Each chip has a different display
1036 * FIFO size and allocation, so the caller needs to figure that out and pass
1037 * in the correct intel_watermark_params structure.
1038 *
1039 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1040 * on the pixel size. When it reaches the watermark level, it'll start
1041 * fetching FIFO line sized based chunks from memory until the FIFO fills
1042 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1043 * will occur, and a display engine hang could result.
1044 */
1045static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1046 const struct intel_watermark_params *wm,
1047 int fifo_size,
1048 int pixel_size,
1049 unsigned long latency_ns)
1050{
1051 long entries_required, wm_size;
1052
1053 /*
1054 * Note: we need to make sure we don't overflow for various clock &
1055 * latency values.
1056 * clocks go from a few thousand to several hundred thousand.
1057 * latency is usually a few thousand
1058 */
1059 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1060 1000;
1061 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1062
1063 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1064
1065 wm_size = fifo_size - (entries_required + wm->guard_size);
1066
1067 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1068
1069 /* Don't promote wm_size to unsigned... */
1070 if (wm_size > (long)wm->max_wm)
1071 wm_size = wm->max_wm;
1072 if (wm_size <= 0)
1073 wm_size = wm->default_wm;
1074 return wm_size;
1075}
1076
1077static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1078{
1079 struct drm_crtc *crtc, *enabled = NULL;
1080
1081 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1082 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1083 if (enabled)
1084 return NULL;
1085 enabled = crtc;
1086 }
1087 }
1088
1089 return enabled;
1090}
1091
46ba614c 1092static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1093{
46ba614c 1094 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct drm_crtc *crtc;
1097 const struct cxsr_latency *latency;
1098 u32 reg;
1099 unsigned long wm;
1100
1101 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1102 dev_priv->fsb_freq, dev_priv->mem_freq);
1103 if (!latency) {
1104 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1105 pineview_disable_cxsr(dev);
1106 return;
1107 }
1108
1109 crtc = single_enabled_crtc(dev);
1110 if (crtc) {
241bfc38 1111 const struct drm_display_mode *adjusted_mode;
b445e3b0 1112 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1113 int clock;
1114
1115 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1116 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1117
1118 /* Display SR */
1119 wm = intel_calculate_wm(clock, &pineview_display_wm,
1120 pineview_display_wm.fifo_size,
1121 pixel_size, latency->display_sr);
1122 reg = I915_READ(DSPFW1);
1123 reg &= ~DSPFW_SR_MASK;
1124 reg |= wm << DSPFW_SR_SHIFT;
1125 I915_WRITE(DSPFW1, reg);
1126 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1127
1128 /* cursor SR */
1129 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1130 pineview_display_wm.fifo_size,
1131 pixel_size, latency->cursor_sr);
1132 reg = I915_READ(DSPFW3);
1133 reg &= ~DSPFW_CURSOR_SR_MASK;
1134 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1135 I915_WRITE(DSPFW3, reg);
1136
1137 /* Display HPLL off SR */
1138 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1139 pineview_display_hplloff_wm.fifo_size,
1140 pixel_size, latency->display_hpll_disable);
1141 reg = I915_READ(DSPFW3);
1142 reg &= ~DSPFW_HPLL_SR_MASK;
1143 reg |= wm & DSPFW_HPLL_SR_MASK;
1144 I915_WRITE(DSPFW3, reg);
1145
1146 /* cursor HPLL off SR */
1147 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1148 pineview_display_hplloff_wm.fifo_size,
1149 pixel_size, latency->cursor_hpll_disable);
1150 reg = I915_READ(DSPFW3);
1151 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1152 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1153 I915_WRITE(DSPFW3, reg);
1154 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1155
1156 /* activate cxsr */
1157 I915_WRITE(DSPFW3,
1158 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1159 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1160 } else {
1161 pineview_disable_cxsr(dev);
1162 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1163 }
1164}
1165
1166static bool g4x_compute_wm0(struct drm_device *dev,
1167 int plane,
1168 const struct intel_watermark_params *display,
1169 int display_latency_ns,
1170 const struct intel_watermark_params *cursor,
1171 int cursor_latency_ns,
1172 int *plane_wm,
1173 int *cursor_wm)
1174{
1175 struct drm_crtc *crtc;
4fe8590a 1176 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1177 int htotal, hdisplay, clock, pixel_size;
1178 int line_time_us, line_count;
1179 int entries, tlb_miss;
1180
1181 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1182 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1183 *cursor_wm = cursor->guard_size;
1184 *plane_wm = display->guard_size;
1185 return false;
1186 }
1187
4fe8590a 1188 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1189 clock = adjusted_mode->crtc_clock;
4fe8590a 1190 htotal = adjusted_mode->htotal;
37327abd 1191 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1192 pixel_size = crtc->fb->bits_per_pixel / 8;
1193
1194 /* Use the small buffer method to calculate plane watermark */
1195 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1196 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1197 if (tlb_miss > 0)
1198 entries += tlb_miss;
1199 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1200 *plane_wm = entries + display->guard_size;
1201 if (*plane_wm > (int)display->max_wm)
1202 *plane_wm = display->max_wm;
1203
1204 /* Use the large buffer method to calculate cursor watermark */
1205 line_time_us = ((htotal * 1000) / clock);
1206 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1207 entries = line_count * 64 * pixel_size;
1208 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1209 if (tlb_miss > 0)
1210 entries += tlb_miss;
1211 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1212 *cursor_wm = entries + cursor->guard_size;
1213 if (*cursor_wm > (int)cursor->max_wm)
1214 *cursor_wm = (int)cursor->max_wm;
1215
1216 return true;
1217}
1218
1219/*
1220 * Check the wm result.
1221 *
1222 * If any calculated watermark values is larger than the maximum value that
1223 * can be programmed into the associated watermark register, that watermark
1224 * must be disabled.
1225 */
1226static bool g4x_check_srwm(struct drm_device *dev,
1227 int display_wm, int cursor_wm,
1228 const struct intel_watermark_params *display,
1229 const struct intel_watermark_params *cursor)
1230{
1231 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1232 display_wm, cursor_wm);
1233
1234 if (display_wm > display->max_wm) {
1235 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1236 display_wm, display->max_wm);
1237 return false;
1238 }
1239
1240 if (cursor_wm > cursor->max_wm) {
1241 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1242 cursor_wm, cursor->max_wm);
1243 return false;
1244 }
1245
1246 if (!(display_wm || cursor_wm)) {
1247 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1248 return false;
1249 }
1250
1251 return true;
1252}
1253
1254static bool g4x_compute_srwm(struct drm_device *dev,
1255 int plane,
1256 int latency_ns,
1257 const struct intel_watermark_params *display,
1258 const struct intel_watermark_params *cursor,
1259 int *display_wm, int *cursor_wm)
1260{
1261 struct drm_crtc *crtc;
4fe8590a 1262 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1263 int hdisplay, htotal, pixel_size, clock;
1264 unsigned long line_time_us;
1265 int line_count, line_size;
1266 int small, large;
1267 int entries;
1268
1269 if (!latency_ns) {
1270 *display_wm = *cursor_wm = 0;
1271 return false;
1272 }
1273
1274 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1275 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1276 clock = adjusted_mode->crtc_clock;
4fe8590a 1277 htotal = adjusted_mode->htotal;
37327abd 1278 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1279 pixel_size = crtc->fb->bits_per_pixel / 8;
1280
1281 line_time_us = (htotal * 1000) / clock;
1282 line_count = (latency_ns / line_time_us + 1000) / 1000;
1283 line_size = hdisplay * pixel_size;
1284
1285 /* Use the minimum of the small and large buffer method for primary */
1286 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1287 large = line_count * line_size;
1288
1289 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1290 *display_wm = entries + display->guard_size;
1291
1292 /* calculate the self-refresh watermark for display cursor */
1293 entries = line_count * pixel_size * 64;
1294 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1295 *cursor_wm = entries + cursor->guard_size;
1296
1297 return g4x_check_srwm(dev,
1298 *display_wm, *cursor_wm,
1299 display, cursor);
1300}
1301
1302static bool vlv_compute_drain_latency(struct drm_device *dev,
1303 int plane,
1304 int *plane_prec_mult,
1305 int *plane_dl,
1306 int *cursor_prec_mult,
1307 int *cursor_dl)
1308{
1309 struct drm_crtc *crtc;
1310 int clock, pixel_size;
1311 int entries;
1312
1313 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1314 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1315 return false;
1316
241bfc38 1317 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1318 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1319
1320 entries = (clock / 1000) * pixel_size;
1321 *plane_prec_mult = (entries > 256) ?
1322 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1323 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1324 pixel_size);
1325
1326 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1327 *cursor_prec_mult = (entries > 256) ?
1328 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1329 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1330
1331 return true;
1332}
1333
1334/*
1335 * Update drain latency registers of memory arbiter
1336 *
1337 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1338 * to be programmed. Each plane has a drain latency multiplier and a drain
1339 * latency value.
1340 */
1341
1342static void vlv_update_drain_latency(struct drm_device *dev)
1343{
1344 struct drm_i915_private *dev_priv = dev->dev_private;
1345 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1346 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1347 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1348 either 16 or 32 */
1349
1350 /* For plane A, Cursor A */
1351 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1352 &cursor_prec_mult, &cursora_dl)) {
1353 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1354 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1355 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1357
1358 I915_WRITE(VLV_DDL1, cursora_prec |
1359 (cursora_dl << DDL_CURSORA_SHIFT) |
1360 planea_prec | planea_dl);
1361 }
1362
1363 /* For plane B, Cursor B */
1364 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1365 &cursor_prec_mult, &cursorb_dl)) {
1366 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1367 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1368 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1369 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1370
1371 I915_WRITE(VLV_DDL2, cursorb_prec |
1372 (cursorb_dl << DDL_CURSORB_SHIFT) |
1373 planeb_prec | planeb_dl);
1374 }
1375}
1376
1377#define single_plane_enabled(mask) is_power_of_2(mask)
1378
46ba614c 1379static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1380{
46ba614c 1381 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1382 static const int sr_latency_ns = 12000;
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1384 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1385 int plane_sr, cursor_sr;
af6c4575 1386 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1387 unsigned int enabled = 0;
1388
1389 vlv_update_drain_latency(dev);
1390
51cea1f4 1391 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1392 &valleyview_wm_info, latency_ns,
1393 &valleyview_cursor_wm_info, latency_ns,
1394 &planea_wm, &cursora_wm))
51cea1f4 1395 enabled |= 1 << PIPE_A;
b445e3b0 1396
51cea1f4 1397 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1398 &valleyview_wm_info, latency_ns,
1399 &valleyview_cursor_wm_info, latency_ns,
1400 &planeb_wm, &cursorb_wm))
51cea1f4 1401 enabled |= 1 << PIPE_B;
b445e3b0 1402
b445e3b0
ED		 1403 if (single_plane_enabled(enabled) &&
1404 g4x_compute_srwm(dev, ffs(enabled) - 1,
1405 sr_latency_ns,
1406 &valleyview_wm_info,
1407 &valleyview_cursor_wm_info,
af6c4575
CW		 1408 &plane_sr, &ignore_cursor_sr) &&
1409 g4x_compute_srwm(dev, ffs(enabled) - 1,
1410 2*sr_latency_ns,
1411 &valleyview_wm_info,
1412 &valleyview_cursor_wm_info,
52bd02d8 1413 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1414 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1415 } else {
b445e3b0
ED		 1416 I915_WRITE(FW_BLC_SELF_VLV,
1417 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1418 plane_sr = cursor_sr = 0;
1419 }
b445e3b0
ED		 1420
1421 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
1427 (plane_sr << DSPFW_SR_SHIFT) |
1428 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1429 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1430 planea_wm);
1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1433 (cursora_wm << DSPFW_CURSORA_SHIFT));
1434 I915_WRITE(DSPFW3,
8c919b28
CW		 1435 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1436 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1437}
1438
46ba614c 1439static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1440{
46ba614c 1441 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1442 static const int sr_latency_ns = 12000;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1445 int plane_sr, cursor_sr;
1446 unsigned int enabled = 0;
1447
51cea1f4 1448 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1449 &g4x_wm_info, latency_ns,
1450 &g4x_cursor_wm_info, latency_ns,
1451 &planea_wm, &cursora_wm))
51cea1f4 1452 enabled |= 1 << PIPE_A;
b445e3b0 1453
51cea1f4 1454 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1455 &g4x_wm_info, latency_ns,
1456 &g4x_cursor_wm_info, latency_ns,
1457 &planeb_wm, &cursorb_wm))
51cea1f4 1458 enabled |= 1 << PIPE_B;
b445e3b0 1459
b445e3b0
ED		 1460 if (single_plane_enabled(enabled) &&
1461 g4x_compute_srwm(dev, ffs(enabled) - 1,
1462 sr_latency_ns,
1463 &g4x_wm_info,
1464 &g4x_cursor_wm_info,
52bd02d8 1465 &plane_sr, &cursor_sr)) {
b445e3b0 1466 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1467 } else {
b445e3b0
ED		 1468 I915_WRITE(FW_BLC_SELF,
1469 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1470 plane_sr = cursor_sr = 0;
1471 }
b445e3b0
ED		 1472
1473 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1474 planea_wm, cursora_wm,
1475 planeb_wm, cursorb_wm,
1476 plane_sr, cursor_sr);
1477
1478 I915_WRITE(DSPFW1,
1479 (plane_sr << DSPFW_SR_SHIFT) |
1480 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1481 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1482 planea_wm);
1483 I915_WRITE(DSPFW2,
8c919b28 1484 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1485 (cursora_wm << DSPFW_CURSORA_SHIFT));
1486 /* HPLL off in SR has some issues on G4x... disable it */
1487 I915_WRITE(DSPFW3,
8c919b28 1488 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1489 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1490}
1491
46ba614c 1492static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1493{
46ba614c 1494 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1495 struct drm_i915_private *dev_priv = dev->dev_private;
1496 struct drm_crtc *crtc;
1497 int srwm = 1;
1498 int cursor_sr = 16;
1499
1500 /* Calc sr entries for one plane configs */
1501 crtc = single_enabled_crtc(dev);
1502 if (crtc) {
1503 /* self-refresh has much higher latency */
1504 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1505 const struct drm_display_mode *adjusted_mode =
1506 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1507 int clock = adjusted_mode->crtc_clock;
4fe8590a 1508 int htotal = adjusted_mode->htotal;
37327abd 1509 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1510 int pixel_size = crtc->fb->bits_per_pixel / 8;
1511 unsigned long line_time_us;
1512 int entries;
1513
1514 line_time_us = ((htotal * 1000) / clock);
1515
1516 /* Use ns/us then divide to preserve precision */
1517 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1518 pixel_size * hdisplay;
1519 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1520 srwm = I965_FIFO_SIZE - entries;
1521 if (srwm < 0)
1522 srwm = 1;
1523 srwm &= 0x1ff;
1524 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1525 entries, srwm);
1526
1527 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1528 pixel_size * 64;
1529 entries = DIV_ROUND_UP(entries,
1530 i965_cursor_wm_info.cacheline_size);
1531 cursor_sr = i965_cursor_wm_info.fifo_size -
1532 (entries + i965_cursor_wm_info.guard_size);
1533
1534 if (cursor_sr > i965_cursor_wm_info.max_wm)
1535 cursor_sr = i965_cursor_wm_info.max_wm;
1536
1537 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1538 "cursor %d\n", srwm, cursor_sr);
1539
1540 if (IS_CRESTLINE(dev))
1541 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1542 } else {
1543 /* Turn off self refresh if both pipes are enabled */
1544 if (IS_CRESTLINE(dev))
1545 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1546 & ~FW_BLC_SELF_EN);
1547 }
1548
1549 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1550 srwm);
1551
1552 /* 965 has limitations... */
1553 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1554 (8 << 16) | (8 << 8) | (8 << 0));
1555 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1556 /* update cursor SR watermark */
1557 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1558}
1559
46ba614c 1560static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1561{
46ba614c 1562 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 const struct intel_watermark_params *wm_info;
1565 uint32_t fwater_lo;
1566 uint32_t fwater_hi;
1567 int cwm, srwm = 1;
1568 int fifo_size;
1569 int planea_wm, planeb_wm;
1570 struct drm_crtc *crtc, *enabled = NULL;
1571
1572 if (IS_I945GM(dev))
1573 wm_info = &i945_wm_info;
1574 else if (!IS_GEN2(dev))
1575 wm_info = &i915_wm_info;
1576 else
1577 wm_info = &i855_wm_info;
1578
1579 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1580 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1581 if (intel_crtc_active(crtc)) {
241bfc38 1582 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1583 int cpp = crtc->fb->bits_per_pixel / 8;
1584 if (IS_GEN2(dev))
1585 cpp = 4;
1586
241bfc38
DL		 1587 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1588 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1589 wm_info, fifo_size, cpp,
b445e3b0
ED		 1590 latency_ns);
1591 enabled = crtc;
1592 } else
1593 planea_wm = fifo_size - wm_info->guard_size;
1594
1595 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1596 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1597 if (intel_crtc_active(crtc)) {
241bfc38 1598 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1599 int cpp = crtc->fb->bits_per_pixel / 8;
1600 if (IS_GEN2(dev))
1601 cpp = 4;
1602
241bfc38
DL		 1603 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1604 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1605 wm_info, fifo_size, cpp,
b445e3b0
ED		 1606 latency_ns);
1607 if (enabled == NULL)
1608 enabled = crtc;
1609 else
1610 enabled = NULL;
1611 } else
1612 planeb_wm = fifo_size - wm_info->guard_size;
1613
1614 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1615
1616 /*
1617 * Overlay gets an aggressive default since video jitter is bad.
1618 */
1619 cwm = 2;
1620
1621 /* Play safe and disable self-refresh before adjusting watermarks. */
1622 if (IS_I945G(dev) || IS_I945GM(dev))
1623 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1624 else if (IS_I915GM(dev))
1625 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1626
1627 /* Calc sr entries for one plane configs */
1628 if (HAS_FW_BLC(dev) && enabled) {
1629 /* self-refresh has much higher latency */
1630 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1631 const struct drm_display_mode *adjusted_mode =
1632 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1633 int clock = adjusted_mode->crtc_clock;
4fe8590a 1634 int htotal = adjusted_mode->htotal;
f727b490 1635 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
b445e3b0
ED		 1636 int pixel_size = enabled->fb->bits_per_pixel / 8;
1637 unsigned long line_time_us;
1638 int entries;
1639
1640 line_time_us = (htotal * 1000) / clock;
1641
1642 /* Use ns/us then divide to preserve precision */
1643 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1644 pixel_size * hdisplay;
1645 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1646 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1647 srwm = wm_info->fifo_size - entries;
1648 if (srwm < 0)
1649 srwm = 1;
1650
1651 if (IS_I945G(dev) || IS_I945GM(dev))
1652 I915_WRITE(FW_BLC_SELF,
1653 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1654 else if (IS_I915GM(dev))
1655 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1656 }
1657
1658 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1659 planea_wm, planeb_wm, cwm, srwm);
1660
1661 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1662 fwater_hi = (cwm & 0x1f);
1663
1664 /* Set request length to 8 cachelines per fetch */
1665 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1666 fwater_hi = fwater_hi | (1 << 8);
1667
1668 I915_WRITE(FW_BLC, fwater_lo);
1669 I915_WRITE(FW_BLC2, fwater_hi);
1670
1671 if (HAS_FW_BLC(dev)) {
1672 if (enabled) {
1673 if (IS_I945G(dev) || IS_I945GM(dev))
1674 I915_WRITE(FW_BLC_SELF,
1675 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1676 else if (IS_I915GM(dev))
1677 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1678 DRM_DEBUG_KMS("memory self refresh enabled\n");
1679 } else
1680 DRM_DEBUG_KMS("memory self refresh disabled\n");
1681 }
1682}
1683
46ba614c 1684static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1685{
46ba614c 1686 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 struct drm_crtc *crtc;
241bfc38 1689 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1690 uint32_t fwater_lo;
1691 int planea_wm;
1692
1693 crtc = single_enabled_crtc(dev);
1694 if (crtc == NULL)
1695 return;
1696
241bfc38
DL		 1697 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1698 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1699 &i830_wm_info,
b445e3b0 1700 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1701 4, latency_ns);
b445e3b0
ED		 1702 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1703 fwater_lo |= (3<<8) | planea_wm;
1704
1705 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1706
1707 I915_WRITE(FW_BLC, fwater_lo);
1708}
1709
b445e3b0
ED		 1710/*
1711 * Check the wm result.
1712 *
1713 * If any calculated watermark values is larger than the maximum value that
1714 * can be programmed into the associated watermark register, that watermark
1715 * must be disabled.
1716 */
1717static bool ironlake_check_srwm(struct drm_device *dev, int level,
1718 int fbc_wm, int display_wm, int cursor_wm,
1719 const struct intel_watermark_params *display,
1720 const struct intel_watermark_params *cursor)
1721{
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723
1724 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1725 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1726
1727 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1728 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1729 fbc_wm, SNB_FBC_MAX_SRWM, level);
1730
1731 /* fbc has it's own way to disable FBC WM */
1732 I915_WRITE(DISP_ARB_CTL,
1733 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1734 return false;
615aaa5f
VS		 1735 } else if (INTEL_INFO(dev)->gen >= 6) {
1736 /* enable FBC WM (except on ILK, where it must remain off) */
1737 I915_WRITE(DISP_ARB_CTL,
1738 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1739 }
1740
1741 if (display_wm > display->max_wm) {
1742 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1743 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1744 return false;
1745 }
1746
1747 if (cursor_wm > cursor->max_wm) {
1748 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1749 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1750 return false;
1751 }
1752
1753 if (!(fbc_wm || display_wm || cursor_wm)) {
1754 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1755 return false;
1756 }
1757
1758 return true;
1759}
1760
1761/*
1762 * Compute watermark values of WM[1-3],
1763 */
1764static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1765 int latency_ns,
1766 const struct intel_watermark_params *display,
1767 const struct intel_watermark_params *cursor,
1768 int *fbc_wm, int *display_wm, int *cursor_wm)
1769{
1770 struct drm_crtc *crtc;
4fe8590a 1771 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1772 unsigned long line_time_us;
1773 int hdisplay, htotal, pixel_size, clock;
1774 int line_count, line_size;
1775 int small, large;
1776 int entries;
1777
1778 if (!latency_ns) {
1779 *fbc_wm = *display_wm = *cursor_wm = 0;
1780 return false;
1781 }
1782
1783 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1784 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1785 clock = adjusted_mode->crtc_clock;
4fe8590a 1786 htotal = adjusted_mode->htotal;
37327abd 1787 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1788 pixel_size = crtc->fb->bits_per_pixel / 8;
1789
1790 line_time_us = (htotal * 1000) / clock;
1791 line_count = (latency_ns / line_time_us + 1000) / 1000;
1792 line_size = hdisplay * pixel_size;
1793
1794 /* Use the minimum of the small and large buffer method for primary */
1795 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1796 large = line_count * line_size;
1797
1798 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1799 *display_wm = entries + display->guard_size;
1800
1801 /*
1802 * Spec says:
1803 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1804 */
1805 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1806
1807 /* calculate the self-refresh watermark for display cursor */
1808 entries = line_count * pixel_size * 64;
1809 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1810 *cursor_wm = entries + cursor->guard_size;
1811
1812 return ironlake_check_srwm(dev, level,
1813 *fbc_wm, *display_wm, *cursor_wm,
1814 display, cursor);
1815}
1816
46ba614c 1817static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1818{
46ba614c 1819 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1820 struct drm_i915_private *dev_priv = dev->dev_private;
1821 int fbc_wm, plane_wm, cursor_wm;
1822 unsigned int enabled;
1823
1824 enabled = 0;
51cea1f4 1825 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1826 &ironlake_display_wm_info,
b0aea5dc 1827 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1828 &ironlake_cursor_wm_info,
b0aea5dc 1829 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1830 &plane_wm, &cursor_wm)) {
1831 I915_WRITE(WM0_PIPEA_ILK,
1832 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1833 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1834 " plane %d, " "cursor: %d\n",
1835 plane_wm, cursor_wm);
51cea1f4 1836 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1837 }
1838
51cea1f4 1839 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1840 &ironlake_display_wm_info,
b0aea5dc 1841 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1842 &ironlake_cursor_wm_info,
b0aea5dc 1843 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1844 &plane_wm, &cursor_wm)) {
1845 I915_WRITE(WM0_PIPEB_ILK,
1846 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1847 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1848 " plane %d, cursor: %d\n",
1849 plane_wm, cursor_wm);
51cea1f4 1850 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1851 }
1852
1853 /*
1854 * Calculate and update the self-refresh watermark only when one
1855 * display plane is used.
1856 */
1857 I915_WRITE(WM3_LP_ILK, 0);
1858 I915_WRITE(WM2_LP_ILK, 0);
1859 I915_WRITE(WM1_LP_ILK, 0);
1860
1861 if (!single_plane_enabled(enabled))
1862 return;
1863 enabled = ffs(enabled) - 1;
1864
1865 /* WM1 */
1866 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1867 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1868 &ironlake_display_srwm_info,
1869 &ironlake_cursor_srwm_info,
1870 &fbc_wm, &plane_wm, &cursor_wm))
1871 return;
1872
1873 I915_WRITE(WM1_LP_ILK,
1874 WM1_LP_SR_EN |
b0aea5dc 1875 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1876 (fbc_wm << WM1_LP_FBC_SHIFT) |
1877 (plane_wm << WM1_LP_SR_SHIFT) |
1878 cursor_wm);
1879
1880 /* WM2 */
1881 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1882 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1883 &ironlake_display_srwm_info,
1884 &ironlake_cursor_srwm_info,
1885 &fbc_wm, &plane_wm, &cursor_wm))
1886 return;
1887
1888 I915_WRITE(WM2_LP_ILK,
1889 WM2_LP_EN |
b0aea5dc 1890 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1891 (fbc_wm << WM1_LP_FBC_SHIFT) |
1892 (plane_wm << WM1_LP_SR_SHIFT) |
1893 cursor_wm);
1894
1895 /*
1896 * WM3 is unsupported on ILK, probably because we don't have latency
1897 * data for that power state
1898 */
1899}
1900
46ba614c 1901static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1902{
46ba614c 1903 struct drm_device *dev = crtc->dev;
b445e3b0 1904 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1905 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1906 u32 val;
1907 int fbc_wm, plane_wm, cursor_wm;
1908 unsigned int enabled;
1909
1910 enabled = 0;
51cea1f4 1911 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1912 &sandybridge_display_wm_info, latency,
1913 &sandybridge_cursor_wm_info, latency,
1914 &plane_wm, &cursor_wm)) {
1915 val = I915_READ(WM0_PIPEA_ILK);
1916 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1917 I915_WRITE(WM0_PIPEA_ILK, val |
1918 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1919 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1920 " plane %d, " "cursor: %d\n",
1921 plane_wm, cursor_wm);
51cea1f4 1922 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1923 }
1924
51cea1f4 1925 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1926 &sandybridge_display_wm_info, latency,
1927 &sandybridge_cursor_wm_info, latency,
1928 &plane_wm, &cursor_wm)) {
1929 val = I915_READ(WM0_PIPEB_ILK);
1930 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1931 I915_WRITE(WM0_PIPEB_ILK, val |
1932 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1933 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1934 " plane %d, cursor: %d\n",
1935 plane_wm, cursor_wm);
51cea1f4 1936 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1937 }
1938
c43d0188
CW		 1939 /*
1940 * Calculate and update the self-refresh watermark only when one
1941 * display plane is used.
1942 *
1943 * SNB support 3 levels of watermark.
1944 *
1945 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1946 * and disabled in the descending order
1947 *
1948 */
1949 I915_WRITE(WM3_LP_ILK, 0);
1950 I915_WRITE(WM2_LP_ILK, 0);
1951 I915_WRITE(WM1_LP_ILK, 0);
1952
1953 if (!single_plane_enabled(enabled) ||
1954 dev_priv->sprite_scaling_enabled)
1955 return;
1956 enabled = ffs(enabled) - 1;
1957
1958 /* WM1 */
1959 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1960 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1961 &sandybridge_display_srwm_info,
1962 &sandybridge_cursor_srwm_info,
1963 &fbc_wm, &plane_wm, &cursor_wm))
1964 return;
1965
1966 I915_WRITE(WM1_LP_ILK,
1967 WM1_LP_SR_EN |
b0aea5dc 1968 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1969 (fbc_wm << WM1_LP_FBC_SHIFT) |
1970 (plane_wm << WM1_LP_SR_SHIFT) |
1971 cursor_wm);
1972
1973 /* WM2 */
1974 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1975 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1976 &sandybridge_display_srwm_info,
1977 &sandybridge_cursor_srwm_info,
1978 &fbc_wm, &plane_wm, &cursor_wm))
1979 return;
1980
1981 I915_WRITE(WM2_LP_ILK,
1982 WM2_LP_EN |
b0aea5dc 1983 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1984 (fbc_wm << WM1_LP_FBC_SHIFT) |
1985 (plane_wm << WM1_LP_SR_SHIFT) |
1986 cursor_wm);
1987
1988 /* WM3 */
1989 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1990 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1991 &sandybridge_display_srwm_info,
1992 &sandybridge_cursor_srwm_info,
1993 &fbc_wm, &plane_wm, &cursor_wm))
1994 return;
1995
1996 I915_WRITE(WM3_LP_ILK,
1997 WM3_LP_EN |
b0aea5dc 1998 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1999 (fbc_wm << WM1_LP_FBC_SHIFT) |
2000 (plane_wm << WM1_LP_SR_SHIFT) |
2001 cursor_wm);
2002}
2003
46ba614c 2004static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 2005{
46ba614c 2006 struct drm_device *dev = crtc->dev;
c43d0188 2007 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2008 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 2009 u32 val;
2010 int fbc_wm, plane_wm, cursor_wm;
2011 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2012 unsigned int enabled;
2013
2014 enabled = 0;
51cea1f4 2015 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 2016 &sandybridge_display_wm_info, latency,
2017 &sandybridge_cursor_wm_info, latency,
2018 &plane_wm, &cursor_wm)) {
2019 val = I915_READ(WM0_PIPEA_ILK);
2020 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2021 I915_WRITE(WM0_PIPEA_ILK, val |
2022 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2023 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2024 " plane %d, " "cursor: %d\n",
2025 plane_wm, cursor_wm);
51cea1f4 2026 enabled |= 1 << PIPE_A;
c43d0188
CW		 2027 }
2028
51cea1f4 2029 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2030 &sandybridge_display_wm_info, latency,
2031 &sandybridge_cursor_wm_info, latency,
2032 &plane_wm, &cursor_wm)) {
2033 val = I915_READ(WM0_PIPEB_ILK);
2034 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2035 I915_WRITE(WM0_PIPEB_ILK, val |
2036 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2037 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2038 " plane %d, cursor: %d\n",
2039 plane_wm, cursor_wm);
51cea1f4 2040 enabled |= 1 << PIPE_B;
c43d0188
CW		 2041 }
2042
51cea1f4 2043 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2044 &sandybridge_display_wm_info, latency,
2045 &sandybridge_cursor_wm_info, latency,
2046 &plane_wm, &cursor_wm)) {
2047 val = I915_READ(WM0_PIPEC_IVB);
2048 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2049 I915_WRITE(WM0_PIPEC_IVB, val |
2050 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2051 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2052 " plane %d, cursor: %d\n",
2053 plane_wm, cursor_wm);
51cea1f4 2054 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2055 }
2056
2057 /*
2058 * Calculate and update the self-refresh watermark only when one
2059 * display plane is used.
2060 *
2061 * SNB support 3 levels of watermark.
2062 *
2063 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2064 * and disabled in the descending order
2065 *
2066 */
2067 I915_WRITE(WM3_LP_ILK, 0);
2068 I915_WRITE(WM2_LP_ILK, 0);
2069 I915_WRITE(WM1_LP_ILK, 0);
2070
2071 if (!single_plane_enabled(enabled) ||
2072 dev_priv->sprite_scaling_enabled)
2073 return;
2074 enabled = ffs(enabled) - 1;
2075
2076 /* WM1 */
2077 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2078 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2079 &sandybridge_display_srwm_info,
2080 &sandybridge_cursor_srwm_info,
2081 &fbc_wm, &plane_wm, &cursor_wm))
2082 return;
2083
2084 I915_WRITE(WM1_LP_ILK,
2085 WM1_LP_SR_EN |
b0aea5dc 2086 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2087 (fbc_wm << WM1_LP_FBC_SHIFT) |
2088 (plane_wm << WM1_LP_SR_SHIFT) |
2089 cursor_wm);
2090
2091 /* WM2 */
2092 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2093 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2094 &sandybridge_display_srwm_info,
2095 &sandybridge_cursor_srwm_info,
2096 &fbc_wm, &plane_wm, &cursor_wm))
2097 return;
2098
2099 I915_WRITE(WM2_LP_ILK,
2100 WM2_LP_EN |
b0aea5dc 2101 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2102 (fbc_wm << WM1_LP_FBC_SHIFT) |
2103 (plane_wm << WM1_LP_SR_SHIFT) |
2104 cursor_wm);
2105
c43d0188 2106 /* WM3, note we have to correct the cursor latency */
b445e3b0 2107 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2108 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2109 &sandybridge_display_srwm_info,
2110 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2111 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2112 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2113 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2114 &sandybridge_display_srwm_info,
2115 &sandybridge_cursor_srwm_info,
2116 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2117 return;
2118
2119 I915_WRITE(WM3_LP_ILK,
2120 WM3_LP_EN |
b0aea5dc 2121 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2122 (fbc_wm << WM1_LP_FBC_SHIFT) |
2123 (plane_wm << WM1_LP_SR_SHIFT) |
2124 cursor_wm);
2125}
2126
3658729a
VS		 2127static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2128 struct drm_crtc *crtc)
801bcfff
PZ		 2129{
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2131 uint32_t pixel_rate;
801bcfff 2132
241bfc38 2133 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 2134
2135 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2136 * adjust the pixel_rate here. */
2137
fd4daa9c 2138 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2139 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2140 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2141
37327abd
VS		 2142 pipe_w = intel_crtc->config.pipe_src_w;
2143 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2144 pfit_w = (pfit_size >> 16) & 0xFFFF;
2145 pfit_h = pfit_size & 0xFFFF;
2146 if (pipe_w < pfit_w)
2147 pipe_w = pfit_w;
2148 if (pipe_h < pfit_h)
2149 pipe_h = pfit_h;
2150
2151 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2152 pfit_w * pfit_h);
2153 }
2154
2155 return pixel_rate;
2156}
2157
37126462 2158/* latency must be in 0.1us units. */
23297044 2159static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2160 uint32_t latency)
2161{
2162 uint64_t ret;
2163
3312ba65
VS		 2164 if (WARN(latency == 0, "Latency value missing\n"))
2165 return UINT_MAX;
2166
801bcfff
PZ		 2167 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2168 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2169
2170 return ret;
2171}
2172
37126462 2173/* latency must be in 0.1us units. */
23297044 2174static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2175 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2176 uint32_t latency)
2177{
2178 uint32_t ret;
2179
3312ba65
VS		 2180 if (WARN(latency == 0, "Latency value missing\n"))
2181 return UINT_MAX;
2182
801bcfff
PZ		 2183 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2184 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2185 ret = DIV_ROUND_UP(ret, 64) + 2;
2186 return ret;
2187}
2188
23297044 2189static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2190 uint8_t bytes_per_pixel)
2191{
2192 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2193}
2194
801bcfff
PZ		 2195struct hsw_pipe_wm_parameters {
2196 bool active;
801bcfff
PZ		 2197 uint32_t pipe_htotal;
2198 uint32_t pixel_rate;
c35426d2
VS		 2199 struct intel_plane_wm_parameters pri;
2200 struct intel_plane_wm_parameters spr;
2201 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2202};
2203
cca32e9a
PZ		 2204struct hsw_wm_maximums {
2205 uint16_t pri;
2206 uint16_t spr;
2207 uint16_t cur;
2208 uint16_t fbc;
2209};
2210
240264f4
VS		 2211/* used in computing the new watermarks state */
2212struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
240264f4
VS		 2216};
2217
37126462
VS		 2218/*
2219 * For both WM_PIPE and WM_LP.
2220 * mem_value must be in 0.1us units.
2221 */
ac830fe1 2222static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2223 uint32_t mem_value,
2224 bool is_lp)
801bcfff 2225{
cca32e9a
PZ		 2226 uint32_t method1, method2;
2227
c35426d2 2228 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2229 return 0;
2230
23297044 2231 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2232 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2233 mem_value);
2234
2235 if (!is_lp)
2236 return method1;
2237
23297044 2238 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2239 params->pipe_htotal,
c35426d2
VS		 2240 params->pri.horiz_pixels,
2241 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2242 mem_value);
2243
2244 return min(method1, method2);
801bcfff
PZ		 2245}
2246
37126462
VS		 2247/*
2248 * For both WM_PIPE and WM_LP.
2249 * mem_value must be in 0.1us units.
2250 */
ac830fe1 2251static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2252 uint32_t mem_value)
2253{
2254 uint32_t method1, method2;
2255
c35426d2 2256 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2257 return 0;
2258
23297044 2259 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2260 params->spr.bytes_per_pixel,
801bcfff 2261 mem_value);
23297044 2262 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2263 params->pipe_htotal,
c35426d2
VS		 2264 params->spr.horiz_pixels,
2265 params->spr.bytes_per_pixel,
801bcfff
PZ		 2266 mem_value);
2267 return min(method1, method2);
2268}
2269
37126462
VS		 2270/*
2271 * For both WM_PIPE and WM_LP.
2272 * mem_value must be in 0.1us units.
2273 */
ac830fe1 2274static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2275 uint32_t mem_value)
2276{
c35426d2 2277 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2278 return 0;
2279
23297044 2280 return ilk_wm_method2(params->pixel_rate,
801bcfff 2281 params->pipe_htotal,
c35426d2
VS		 2282 params->cur.horiz_pixels,
2283 params->cur.bytes_per_pixel,
801bcfff
PZ		 2284 mem_value);
2285}
2286
cca32e9a 2287/* Only for WM_LP. */
ac830fe1 2288static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2289 uint32_t pri_val)
cca32e9a 2290{
c35426d2 2291 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2292 return 0;
2293
23297044 2294 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2295 params->pri.horiz_pixels,
2296 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2297}
2298
158ae64f
VS		 2299static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2300{
416f4727
VS		 2301 if (INTEL_INFO(dev)->gen >= 8)
2302 return 3072;
2303 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2304 return 768;
2305 else
2306 return 512;
2307}
2308
2309/* Calculate the maximum primary/sprite plane watermark */
2310static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2311 int level,
240264f4 2312 const struct intel_wm_config *config,
158ae64f
VS		 2313 enum intel_ddb_partitioning ddb_partitioning,
2314 bool is_sprite)
2315{
2316 unsigned int fifo_size = ilk_display_fifo_size(dev);
2317 unsigned int max;
2318
2319 /* if sprites aren't enabled, sprites get nothing */
240264f4 2320 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2321 return 0;
2322
2323 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2324 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2325 fifo_size /= INTEL_INFO(dev)->num_pipes;
2326
2327 /*
2328 * For some reason the non self refresh
2329 * FIFO size is only half of the self
2330 * refresh FIFO size on ILK/SNB.
2331 */
2332 if (INTEL_INFO(dev)->gen <= 6)
2333 fifo_size /= 2;
2334 }
2335
240264f4 2336 if (config->sprites_enabled) {
158ae64f
VS		 2337 /* level 0 is always calculated with 1:1 split */
2338 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2339 if (is_sprite)
2340 fifo_size *= 5;
2341 fifo_size /= 6;
2342 } else {
2343 fifo_size /= 2;
2344 }
2345 }
2346
2347 /* clamp to max that the registers can hold */
416f4727
VS		 2348 if (INTEL_INFO(dev)->gen >= 8)
2349 max = level == 0 ? 255 : 2047;
2350 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 2351 /* IVB/HSW primary/sprite plane watermarks */
2352 max = level == 0 ? 127 : 1023;
2353 else if (!is_sprite)
2354 /* ILK/SNB primary plane watermarks */
2355 max = level == 0 ? 127 : 511;
2356 else
2357 /* ILK/SNB sprite plane watermarks */
2358 max = level == 0 ? 63 : 255;
2359
2360 return min(fifo_size, max);
2361}
2362
2363/* Calculate the maximum cursor plane watermark */
2364static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2365 int level,
2366 const struct intel_wm_config *config)
158ae64f
VS		 2367{
2368 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2369 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2370 return 64;
2371
2372 /* otherwise just report max that registers can hold */
2373 if (INTEL_INFO(dev)->gen >= 7)
2374 return level == 0 ? 63 : 255;
2375 else
2376 return level == 0 ? 31 : 63;
2377}
2378
2379/* Calculate the maximum FBC watermark */
416f4727 2380static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
158ae64f
VS		 2381{
2382 /* max that registers can hold */
416f4727
VS		 2383 if (INTEL_INFO(dev)->gen >= 8)
2384 return 31;
2385 else
2386 return 15;
158ae64f
VS		 2387}
2388
34982fe1
VS		 2389static void ilk_compute_wm_maximums(struct drm_device *dev,
2390 int level,
2391 const struct intel_wm_config *config,
2392 enum intel_ddb_partitioning ddb_partitioning,
2393 struct hsw_wm_maximums *max)
158ae64f 2394{
240264f4
VS		 2395 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2396 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2397 max->cur = ilk_cursor_wm_max(dev, level, config);
416f4727 2398 max->fbc = ilk_fbc_wm_max(dev);
158ae64f
VS		 2399}
2400
d9395655
VS		 2401static bool ilk_validate_wm_level(int level,
2402 const struct hsw_wm_maximums *max,
2403 struct intel_wm_level *result)
a9786a11
VS		 2404{
2405 bool ret;
2406
2407 /* already determined to be invalid? */
2408 if (!result->enable)
2409 return false;
2410
2411 result->enable = result->pri_val <= max->pri &&
2412 result->spr_val <= max->spr &&
2413 result->cur_val <= max->cur;
2414
2415 ret = result->enable;
2416
2417 /*
2418 * HACK until we can pre-compute everything,
2419 * and thus fail gracefully if LP0 watermarks
2420 * are exceeded...
2421 */
2422 if (level == 0 && !result->enable) {
2423 if (result->pri_val > max->pri)
2424 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2425 level, result->pri_val, max->pri);
2426 if (result->spr_val > max->spr)
2427 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2428 level, result->spr_val, max->spr);
2429 if (result->cur_val > max->cur)
2430 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2431 level, result->cur_val, max->cur);
2432
2433 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2434 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2435 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2436 result->enable = true;
2437 }
2438
a9786a11
VS		 2439 return ret;
2440}
2441
6f5ddd17
VS		 2442static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2443 int level,
ac830fe1 2444 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2445 struct intel_wm_level *result)
6f5ddd17
VS		 2446{
2447 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2448 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2449 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2450
2451 /* WM1+ latency values stored in 0.5us units */
2452 if (level > 0) {
2453 pri_latency *= 5;
2454 spr_latency *= 5;
2455 cur_latency *= 5;
2456 }
2457
2458 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2459 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2460 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2461 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2462 result->enable = true;
2463}
2464
801bcfff
PZ		 2465static uint32_t
2466hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2467{
2468 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2470 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2471 u32 linetime, ips_linetime;
1f8eeabf 2472
801bcfff
PZ		 2473 if (!intel_crtc_active(crtc))
2474 return 0;
1011d8c4 2475
1f8eeabf
ED		 2476 /* The WM are computed with base on how long it takes to fill a single
2477 * row at the given clock rate, multiplied by 8.
2478 * */
85a02deb
PZ		 2479 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2480 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2481 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2482
801bcfff
PZ		 2483 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2484 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2485}
2486
12b134df
VS		 2487static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2488{
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490
2491 if (IS_HASWELL(dev)) {
2492 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2493
2494 wm[0] = (sskpd >> 56) & 0xFF;
2495 if (wm[0] == 0)
2496 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2497 wm[1] = (sskpd >> 4) & 0xFF;
2498 wm[2] = (sskpd >> 12) & 0xFF;
2499 wm[3] = (sskpd >> 20) & 0x1FF;
2500 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2501 } else if (INTEL_INFO(dev)->gen >= 6) {
2502 uint32_t sskpd = I915_READ(MCH_SSKPD);
2503
2504 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2505 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2506 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2507 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2508 } else if (INTEL_INFO(dev)->gen >= 5) {
2509 uint32_t mltr = I915_READ(MLTR_ILK);
2510
2511 /* ILK primary LP0 latency is 700 ns */
2512 wm[0] = 7;
2513 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2514 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2515 }
2516}
2517
53615a5e
VS		 2518static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2519{
2520 /* ILK sprite LP0 latency is 1300 ns */
2521 if (INTEL_INFO(dev)->gen == 5)
2522 wm[0] = 13;
2523}
2524
2525static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2526{
2527 /* ILK cursor LP0 latency is 1300 ns */
2528 if (INTEL_INFO(dev)->gen == 5)
2529 wm[0] = 13;
2530
2531 /* WaDoubleCursorLP3Latency:ivb */
2532 if (IS_IVYBRIDGE(dev))
2533 wm[3] *= 2;
2534}
2535
ad0d6dc4 2536static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2537{
26ec971e
VS		 2538 /* how many WM levels are we expecting */
2539 if (IS_HASWELL(dev))
ad0d6dc4 2540 return 4;
26ec971e 2541 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2542 return 3;
26ec971e 2543 else
ad0d6dc4
VS		 2544 return 2;
2545}
2546
2547static void intel_print_wm_latency(struct drm_device *dev,
2548 const char *name,
2549 const uint16_t wm[5])
2550{
2551 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2552
2553 for (level = 0; level <= max_level; level++) {
2554 unsigned int latency = wm[level];
2555
2556 if (latency == 0) {
2557 DRM_ERROR("%s WM%d latency not provided\n",
2558 name, level);
2559 continue;
2560 }
2561
2562 /* WM1+ latency values in 0.5us units */
2563 if (level > 0)
2564 latency *= 5;
2565
2566 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2567 name, level, wm[level],
2568 latency / 10, latency % 10);
2569 }
2570}
2571
53615a5e
VS		 2572static void intel_setup_wm_latency(struct drm_device *dev)
2573{
2574 struct drm_i915_private *dev_priv = dev->dev_private;
2575
2576 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2577
2578 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2579 sizeof(dev_priv->wm.pri_latency));
2580 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2581 sizeof(dev_priv->wm.pri_latency));
2582
2583 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2584 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2585
2586 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2587 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2588 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2589}
2590
7c4a395f
VS		 2591static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2592 struct hsw_pipe_wm_parameters *p,
a485bfb8 2593 struct intel_wm_config *config)
1011d8c4 2594{
7c4a395f
VS		 2595 struct drm_device *dev = crtc->dev;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2598 struct drm_plane *plane;
1011d8c4 2599
7c4a395f
VS		 2600 p->active = intel_crtc_active(crtc);
2601 if (p->active) {
801bcfff 2602 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2603 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2604 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2605 p->cur.bytes_per_pixel = 4;
37327abd 2606 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2607 p->cur.horiz_pixels = 64;
2608 /* TODO: for now, assume primary and cursor planes are always enabled. */
2609 p->pri.enabled = true;
2610 p->cur.enabled = true;
801bcfff
PZ		 2611 }
2612
7c4a395f 2613 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2614 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2615
801bcfff
PZ		 2616 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2617 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2618
7c4a395f
VS		 2619 if (intel_plane->pipe == pipe)
2620 p->spr = intel_plane->wm;
cca32e9a 2621
a485bfb8
VS		 2622 config->sprites_enabled |= intel_plane->wm.enabled;
2623 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2624 }
801bcfff
PZ		 2625}
2626
0b2ae6d7
VS		 2627/* Compute new watermarks for the pipe */
2628static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2629 const struct hsw_pipe_wm_parameters *params,
2630 struct intel_pipe_wm *pipe_wm)
2631{
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 int level, max_level = ilk_wm_max_level(dev);
2635 /* LP0 watermark maximums depend on this pipe alone */
2636 struct intel_wm_config config = {
2637 .num_pipes_active = 1,
2638 .sprites_enabled = params->spr.enabled,
2639 .sprites_scaled = params->spr.scaled,
2640 };
2641 struct hsw_wm_maximums max;
2642
0b2ae6d7 2643 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2644 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7 2645
7b39a0b7
VS		 2646 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2647 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2648 max_level = 1;
2649
2650 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2651 if (params->spr.scaled)
2652 max_level = 0;
2653
0b2ae6d7
VS		 2654 for (level = 0; level <= max_level; level++)
2655 ilk_compute_wm_level(dev_priv, level, params,
2656 &pipe_wm->wm[level]);
2657
ce0e0713
VS		 2658 if (IS_HASWELL(dev))
2659 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7
VS		 2660
2661 /* At least LP0 must be valid */
d9395655 2662 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2663}
2664
2665/*
2666 * Merge the watermarks from all active pipes for a specific level.
2667 */
2668static void ilk_merge_wm_level(struct drm_device *dev,
2669 int level,
2670 struct intel_wm_level *ret_wm)
2671{
2672 const struct intel_crtc *intel_crtc;
2673
2674 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2675 const struct intel_wm_level *wm =
2676 &intel_crtc->wm.active.wm[level];
2677
2678 if (!wm->enable)
2679 return;
2680
2681 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2682 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2683 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2684 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2685 }
2686
2687 ret_wm->enable = true;
2688}
2689
2690/*
2691 * Merge all low power watermarks for all active pipes.
2692 */
2693static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2694 const struct intel_wm_config *config,
0b2ae6d7
VS		 2695 const struct hsw_wm_maximums *max,
2696 struct intel_pipe_wm *merged)
2697{
2698 int level, max_level = ilk_wm_max_level(dev);
2699
0ba22e26
VS		 2700 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2701 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2702 config->num_pipes_active > 1)
2703 return;
2704
6c8b6c28
VS		 2705 /* ILK: FBC WM must be disabled always */
2706 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2707
2708 /* merge each WM1+ level */
2709 for (level = 1; level <= max_level; level++) {
2710 struct intel_wm_level *wm = &merged->wm[level];
2711
2712 ilk_merge_wm_level(dev, level, wm);
2713
d9395655 2714 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2715 break;
2716
2717 /*
2718 * The spec says it is preferred to disable
2719 * FBC WMs instead of disabling a WM level.
2720 */
2721 if (wm->fbc_val > max->fbc) {
2722 merged->fbc_wm_enabled = false;
2723 wm->fbc_val = 0;
2724 }
2725 }
6c8b6c28
VS		 2726
2727 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2728 /*
2729 * FIXME this is racy. FBC might get enabled later.
2730 * What we should check here is whether FBC can be
2731 * enabled sometime later.
2732 */
2733 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2734 for (level = 2; level <= max_level; level++) {
2735 struct intel_wm_level *wm = &merged->wm[level];
2736
2737 wm->enable = false;
2738 }
2739 }
0b2ae6d7
VS		 2740}
2741
b380ca3c
VS		 2742static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2743{
2744 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2745 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2746}
2747
a68d68ee
VS		 2748/* The value we need to program into the WM_LPx latency field */
2749static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2750{
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752
2753 if (IS_HASWELL(dev))
2754 return 2 * level;
2755 else
2756 return dev_priv->wm.pri_latency[level];
2757}
2758
801bcfff 2759static void hsw_compute_wm_results(struct drm_device *dev,
0362c781 2760 const struct intel_pipe_wm *merged,
609cedef 2761 enum intel_ddb_partitioning partitioning,
801bcfff
PZ		 2762 struct hsw_wm_values *results)
2763{
0b2ae6d7
VS		 2764 struct intel_crtc *intel_crtc;
2765 int level, wm_lp;
cca32e9a 2766
0362c781 2767 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2768 results->partitioning = partitioning;
cca32e9a 2769
0b2ae6d7 2770 /* LP1+ register values */
cca32e9a 2771 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2772 const struct intel_wm_level *r;
801bcfff 2773
b380ca3c 2774 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2775
0362c781 2776 r = &merged->wm[level];
0b2ae6d7 2777 if (!r->enable)
cca32e9a
PZ		 2778 break;
2779
416f4727 2780 results->wm_lp[wm_lp - 1] = WM3_LP_EN |
a68d68ee 2781 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2782 (r->pri_val << WM1_LP_SR_SHIFT) |
2783 r->cur_val;
2784
2785 if (INTEL_INFO(dev)->gen >= 8)
2786 results->wm_lp[wm_lp - 1] |=
2787 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2788 else
2789 results->wm_lp[wm_lp - 1] |=
2790 r->fbc_val << WM1_LP_FBC_SHIFT;
2791
6cef2b8a
VS		 2792 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2793 WARN_ON(wm_lp != 1);
2794 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2795 } else
2796 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2797 }
801bcfff 2798
0b2ae6d7
VS		 2799 /* LP0 register values */
2800 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2801 enum pipe pipe = intel_crtc->pipe;
2802 const struct intel_wm_level *r =
2803 &intel_crtc->wm.active.wm[0];
2804
2805 if (WARN_ON(!r->enable))
2806 continue;
2807
2808 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2809
0b2ae6d7
VS		 2810 results->wm_pipe[pipe] =
2811 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2812 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2813 r->cur_val;
801bcfff
PZ		 2814 }
2815}
2816
861f3389
PZ		 2817/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2818 * case both are at the same level. Prefer r1 in case they're the same. */
198a1e9b
VS		 2819static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2820 struct intel_pipe_wm *r1,
2821 struct intel_pipe_wm *r2)
861f3389 2822{
198a1e9b
VS		 2823 int level, max_level = ilk_wm_max_level(dev);
2824 int level1 = 0, level2 = 0;
861f3389 2825
198a1e9b
VS		 2826 for (level = 1; level <= max_level; level++) {
2827 if (r1->wm[level].enable)
2828 level1 = level;
2829 if (r2->wm[level].enable)
2830 level2 = level;
861f3389
PZ		 2831 }
2832
198a1e9b
VS		 2833 if (level1 == level2) {
2834 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2835 return r2;
2836 else
2837 return r1;
198a1e9b 2838 } else if (level1 > level2) {
861f3389
PZ		 2839 return r1;
2840 } else {
2841 return r2;
2842 }
2843}
2844
49a687c4
VS		 2845/* dirty bits used to track which watermarks need changes */
2846#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2847#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2848#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2849#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2850#define WM_DIRTY_FBC (1 << 24)
2851#define WM_DIRTY_DDB (1 << 25)
2852
2853static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2854 const struct hsw_wm_values *old,
2855 const struct hsw_wm_values *new)
2856{
2857 unsigned int dirty = 0;
2858 enum pipe pipe;
2859 int wm_lp;
2860
2861 for_each_pipe(pipe) {
2862 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2863 dirty |= WM_DIRTY_LINETIME(pipe);
2864 /* Must disable LP1+ watermarks too */
2865 dirty |= WM_DIRTY_LP_ALL;
2866 }
2867
2868 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2869 dirty |= WM_DIRTY_PIPE(pipe);
2870 /* Must disable LP1+ watermarks too */
2871 dirty |= WM_DIRTY_LP_ALL;
2872 }
2873 }
2874
2875 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2876 dirty |= WM_DIRTY_FBC;
2877 /* Must disable LP1+ watermarks too */
2878 dirty |= WM_DIRTY_LP_ALL;
2879 }
2880
2881 if (old->partitioning != new->partitioning) {
2882 dirty |= WM_DIRTY_DDB;
2883 /* Must disable LP1+ watermarks too */
2884 dirty |= WM_DIRTY_LP_ALL;
2885 }
2886
2887 /* LP1+ watermarks already deemed dirty, no need to continue */
2888 if (dirty & WM_DIRTY_LP_ALL)
2889 return dirty;
2890
2891 /* Find the lowest numbered LP1+ watermark in need of an update... */
2892 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2893 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2894 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2895 break;
2896 }
2897
2898 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2899 for (; wm_lp <= 3; wm_lp++)
2900 dirty |= WM_DIRTY_LP(wm_lp);
2901
2902 return dirty;
2903}
2904
801bcfff
PZ		 2905/*
2906 * The spec says we shouldn't write when we don't need, because every write
2907 * causes WMs to be re-evaluated, expending some power.
2908 */
2909static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
609cedef 2910 struct hsw_wm_values *results)
801bcfff 2911{
ac9545fd 2912 struct drm_device *dev = dev_priv->dev;
243e6a44 2913 struct hsw_wm_values *previous = &dev_priv->wm.hw;
49a687c4 2914 unsigned int dirty;
801bcfff 2915 uint32_t val;
801bcfff 2916
243e6a44 2917 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
49a687c4 2918 if (!dirty)
801bcfff
PZ		 2919 return;
2920
facd619b
VS		 2921 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2922 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2923 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2924 }
2925 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2926 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2927 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2928 }
2929 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2930 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2931 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2932 }
801bcfff 2933
facd619b
VS		 2934 /*
2935 * Don't touch WM1S_LP_EN here.
2936 * Doing so could cause underruns.
2937 */
6cef2b8a 2938
49a687c4 2939 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2940 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2941 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2942 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2943 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2944 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2945
49a687c4 2946 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2947 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2948 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2949 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2950 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2951 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2952
49a687c4 2953 if (dirty & WM_DIRTY_DDB) {
ac9545fd
VS		 2954 if (IS_HASWELL(dev)) {
2955 val = I915_READ(WM_MISC);
2956 if (results->partitioning == INTEL_DDB_PART_1_2)
2957 val &= ~WM_MISC_DATA_PARTITION_5_6;
2958 else
2959 val |= WM_MISC_DATA_PARTITION_5_6;
2960 I915_WRITE(WM_MISC, val);
2961 } else {
2962 val = I915_READ(DISP_ARB_CTL2);
2963 if (results->partitioning == INTEL_DDB_PART_1_2)
2964 val &= ~DISP_DATA_PARTITION_5_6;
2965 else
2966 val |= DISP_DATA_PARTITION_5_6;
2967 I915_WRITE(DISP_ARB_CTL2, val);
2968 }
1011d8c4
PZ		 2969 }
2970
49a687c4 2971 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2972 val = I915_READ(DISP_ARB_CTL);
2973 if (results->enable_fbc_wm)
2974 val &= ~DISP_FBC_WM_DIS;
2975 else
2976 val |= DISP_FBC_WM_DIS;
2977 I915_WRITE(DISP_ARB_CTL, val);
2978 }
2979
6cef2b8a 2980 if (INTEL_INFO(dev)->gen <= 6) {
facd619b 2981 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
6cef2b8a
VS		 2982 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2983 } else {
2984 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2985 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2986 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2987 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2988 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2989 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2990 }
801bcfff 2991
facd619b 2992 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2993 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2994 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2995 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2996 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2997 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2998
2999 dev_priv->wm.hw = *results;
801bcfff
PZ		 3000}
3001
46ba614c 3002static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 3003{
7c4a395f 3004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3005 struct drm_device *dev = crtc->dev;
801bcfff 3006 struct drm_i915_private *dev_priv = dev->dev_private;
a485bfb8 3007 struct hsw_wm_maximums max;
7c4a395f 3008 struct hsw_pipe_wm_parameters params = {};
198a1e9b 3009 struct hsw_wm_values results = {};
77c122bc 3010 enum intel_ddb_partitioning partitioning;
7c4a395f 3011 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3012 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3013 struct intel_wm_config config = {};
7c4a395f 3014
a485bfb8 3015 hsw_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 3016
3017 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3018
3019 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3020 return;
861f3389 3021
7c4a395f 3022 intel_crtc->wm.active = pipe_wm;
861f3389 3023
34982fe1 3024 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3025 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3026
3027 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3028 if (INTEL_INFO(dev)->gen >= 7 &&
3029 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3030 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3031 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3032
198a1e9b 3033 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3034 } else {
198a1e9b 3035 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3036 }
3037
198a1e9b 3038 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3039 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3040
609cedef
VS		 3041 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3042
3043 hsw_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3044}
3045
adf3d35e
VS		 3046static void haswell_update_sprite_wm(struct drm_plane *plane,
3047 struct drm_crtc *crtc,
526682e9 3048 uint32_t sprite_width, int pixel_size,
bdd57d03 3049 bool enabled, bool scaled)
526682e9 3050{
adf3d35e 3051 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3052
adf3d35e
VS		 3053 intel_plane->wm.enabled = enabled;
3054 intel_plane->wm.scaled = scaled;
3055 intel_plane->wm.horiz_pixels = sprite_width;
3056 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3057
46ba614c 3058 haswell_update_wm(crtc);
526682e9
PZ		 3059}
3060
b445e3b0
ED		 3061static bool
3062sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
3063 uint32_t sprite_width, int pixel_size,
3064 const struct intel_watermark_params *display,
3065 int display_latency_ns, int *sprite_wm)
3066{
3067 struct drm_crtc *crtc;
3068 int clock;
3069 int entries, tlb_miss;
3070
3071 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 3072 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 3073 *sprite_wm = display->guard_size;
3074 return false;
3075 }
3076
241bfc38 3077 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3078
3079 /* Use the small buffer method to calculate the sprite watermark */
3080 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3081 tlb_miss = display->fifo_size*display->cacheline_size -
3082 sprite_width * 8;
3083 if (tlb_miss > 0)
3084 entries += tlb_miss;
3085 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3086 *sprite_wm = entries + display->guard_size;
3087 if (*sprite_wm > (int)display->max_wm)
3088 *sprite_wm = display->max_wm;
3089
3090 return true;
3091}
3092
3093static bool
3094sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3095 uint32_t sprite_width, int pixel_size,
3096 const struct intel_watermark_params *display,
3097 int latency_ns, int *sprite_wm)
3098{
3099 struct drm_crtc *crtc;
3100 unsigned long line_time_us;
3101 int clock;
3102 int line_count, line_size;
3103 int small, large;
3104 int entries;
3105
3106 if (!latency_ns) {
3107 *sprite_wm = 0;
3108 return false;
3109 }
3110
3111 crtc = intel_get_crtc_for_plane(dev, plane);
241bfc38 3112 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3113 if (!clock) {
3114 *sprite_wm = 0;
3115 return false;
3116 }
3117
3118 line_time_us = (sprite_width * 1000) / clock;
3119 if (!line_time_us) {
3120 *sprite_wm = 0;
3121 return false;
3122 }
3123
3124 line_count = (latency_ns / line_time_us + 1000) / 1000;
3125 line_size = sprite_width * pixel_size;
3126
3127 /* Use the minimum of the small and large buffer method for primary */
3128 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3129 large = line_count * line_size;
3130
3131 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3132 *sprite_wm = entries + display->guard_size;
3133
3134 return *sprite_wm > 0x3ff ? false : true;
3135}
3136
adf3d35e
VS		 3137static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3138 struct drm_crtc *crtc,
4c4ff43a 3139 uint32_t sprite_width, int pixel_size,
39db4a4d 3140 bool enabled, bool scaled)
b445e3b0 3141{
adf3d35e 3142 struct drm_device *dev = plane->dev;
b445e3b0 3143 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 3144 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 3145 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 3146 u32 val;
3147 int sprite_wm, reg;
3148 int ret;
3149
39db4a4d 3150 if (!enabled)
4c4ff43a
PZ		 3151 return;
3152
b445e3b0
ED		 3153 switch (pipe) {
3154 case 0:
3155 reg = WM0_PIPEA_ILK;
3156 break;
3157 case 1:
3158 reg = WM0_PIPEB_ILK;
3159 break;
3160 case 2:
3161 reg = WM0_PIPEC_IVB;
3162 break;
3163 default:
3164 return; /* bad pipe */
3165 }
3166
3167 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3168 &sandybridge_display_wm_info,
3169 latency, &sprite_wm);
3170 if (!ret) {
84f44ce7
VS		 3171 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3172 pipe_name(pipe));
b445e3b0
ED		 3173 return;
3174 }
3175
3176 val = I915_READ(reg);
3177 val &= ~WM0_PIPE_SPRITE_MASK;
3178 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3179 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3180
3181
3182 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3183 pixel_size,
3184 &sandybridge_display_srwm_info,
b0aea5dc 3185 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3186 &sprite_wm);
3187 if (!ret) {
84f44ce7
VS		 3188 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3189 pipe_name(pipe));
b445e3b0
ED		 3190 return;
3191 }
3192 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3193
3194 /* Only IVB has two more LP watermarks for sprite */
3195 if (!IS_IVYBRIDGE(dev))
3196 return;
3197
3198 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3199 pixel_size,
3200 &sandybridge_display_srwm_info,
b0aea5dc 3201 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3202 &sprite_wm);
3203 if (!ret) {
84f44ce7
VS		 3204 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3205 pipe_name(pipe));
b445e3b0
ED		 3206 return;
3207 }
3208 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3209
3210 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3211 pixel_size,
3212 &sandybridge_display_srwm_info,
b0aea5dc 3213 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3214 &sprite_wm);
3215 if (!ret) {
84f44ce7
VS		 3216 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3217 pipe_name(pipe));
b445e3b0
ED		 3218 return;
3219 }
3220 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3221}
3222
243e6a44
VS		 3223static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3224{
3225 struct drm_device *dev = crtc->dev;
3226 struct drm_i915_private *dev_priv = dev->dev_private;
3227 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3229 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3230 enum pipe pipe = intel_crtc->pipe;
3231 static const unsigned int wm0_pipe_reg[] = {
3232 [PIPE_A] = WM0_PIPEA_ILK,
3233 [PIPE_B] = WM0_PIPEB_ILK,
3234 [PIPE_C] = WM0_PIPEC_IVB,
3235 };
3236
3237 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
ce0e0713
VS		 3238 if (IS_HASWELL(dev))
3239 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44
VS		 3240
3241 if (intel_crtc_active(crtc)) {
3242 u32 tmp = hw->wm_pipe[pipe];
3243
3244 /*
3245 * For active pipes LP0 watermark is marked as
3246 * enabled, and LP1+ watermaks as disabled since
3247 * we can't really reverse compute them in case
3248 * multiple pipes are active.
3249 */
3250 active->wm[0].enable = true;
3251 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3252 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3253 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3254 active->linetime = hw->wm_linetime[pipe];
3255 } else {
3256 int level, max_level = ilk_wm_max_level(dev);
3257
3258 /*
3259 * For inactive pipes, all watermark levels
3260 * should be marked as enabled but zeroed,
3261 * which is what we'd compute them to.
3262 */
3263 for (level = 0; level <= max_level; level++)
3264 active->wm[level].enable = true;
3265 }
3266}
3267
3268void ilk_wm_get_hw_state(struct drm_device *dev)
3269{
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3272 struct drm_crtc *crtc;
3273
3274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3275 ilk_pipe_wm_get_hw_state(crtc);
3276
3277 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3278 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3279 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3280
3281 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3282 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3283 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3284
ac9545fd
VS		 3285 if (IS_HASWELL(dev))
3286 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3287 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3288 else if (IS_IVYBRIDGE(dev))
3289 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3290 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3291
3292 hw->enable_fbc_wm =
3293 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3294}
3295
b445e3b0
ED		 3296/**
3297 * intel_update_watermarks - update FIFO watermark values based on current modes
3298 *
3299 * Calculate watermark values for the various WM regs based on current mode
3300 * and plane configuration.
3301 *
3302 * There are several cases to deal with here:
3303 * - normal (i.e. non-self-refresh)
3304 * - self-refresh (SR) mode
3305 * - lines are large relative to FIFO size (buffer can hold up to 2)
3306 * - lines are small relative to FIFO size (buffer can hold more than 2
3307 * lines), so need to account for TLB latency
3308 *
3309 * The normal calculation is:
3310 * watermark = dotclock * bytes per pixel * latency
3311 * where latency is platform & configuration dependent (we assume pessimal
3312 * values here).
3313 *
3314 * The SR calculation is:
3315 * watermark = (trunc(latency/line time)+1) * surface width *
3316 * bytes per pixel
3317 * where
3318 * line time = htotal / dotclock
3319 * surface width = hdisplay for normal plane and 64 for cursor
3320 * and latency is assumed to be high, as above.
3321 *
3322 * The final value programmed to the register should always be rounded up,
3323 * and include an extra 2 entries to account for clock crossings.
3324 *
3325 * We don't use the sprite, so we can ignore that. And on Crestline we have
3326 * to set the non-SR watermarks to 8.
3327 */
46ba614c 3328void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3329{
46ba614c 3330 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3331
3332 if (dev_priv->display.update_wm)
46ba614c 3333 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3334}
3335
adf3d35e
VS		 3336void intel_update_sprite_watermarks(struct drm_plane *plane,
3337 struct drm_crtc *crtc,
4c4ff43a 3338 uint32_t sprite_width, int pixel_size,
39db4a4d 3339 bool enabled, bool scaled)
b445e3b0 3340{
adf3d35e 3341 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3342
3343 if (dev_priv->display.update_sprite_wm)
adf3d35e 3344 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3345 pixel_size, enabled, scaled);
b445e3b0
ED		 3346}
3347
2b4e57bd
ED		 3348static struct drm_i915_gem_object *
3349intel_alloc_context_page(struct drm_device *dev)
3350{
3351 struct drm_i915_gem_object *ctx;
3352 int ret;
3353
3354 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3355
3356 ctx = i915_gem_alloc_object(dev, 4096);
3357 if (!ctx) {
3358 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3359 return NULL;
3360 }
3361
c37e2204 3362 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3363 if (ret) {
3364 DRM_ERROR("failed to pin power context: %d\n", ret);
3365 goto err_unref;
3366 }
3367
3368 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3369 if (ret) {
3370 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3371 goto err_unpin;
3372 }
3373
3374 return ctx;
3375
3376err_unpin:
3377 i915_gem_object_unpin(ctx);
3378err_unref:
3379 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3380 return NULL;
3381}
3382
9270388e
DV		 3383/**
3384 * Lock protecting IPS related data structures
9270388e
DV		 3385 */
3386DEFINE_SPINLOCK(mchdev_lock);
3387
3388/* Global for IPS driver to get at the current i915 device. Protected by
3389 * mchdev_lock. */
3390static struct drm_i915_private *i915_mch_dev;
3391
2b4e57bd
ED		 3392bool ironlake_set_drps(struct drm_device *dev, u8 val)
3393{
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 u16 rgvswctl;
3396
9270388e
DV		 3397 assert_spin_locked(&mchdev_lock);
3398
2b4e57bd
ED		 3399 rgvswctl = I915_READ16(MEMSWCTL);
3400 if (rgvswctl & MEMCTL_CMD_STS) {
3401 DRM_DEBUG("gpu busy, RCS change rejected\n");
3402 return false; /* still busy with another command */
3403 }
3404
3405 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3406 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3407 I915_WRITE16(MEMSWCTL, rgvswctl);
3408 POSTING_READ16(MEMSWCTL);
3409
3410 rgvswctl |= MEMCTL_CMD_STS;
3411 I915_WRITE16(MEMSWCTL, rgvswctl);
3412
3413 return true;
3414}
3415
8090c6b9 3416static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3417{
3418 struct drm_i915_private *dev_priv = dev->dev_private;
3419 u32 rgvmodectl = I915_READ(MEMMODECTL);
3420 u8 fmax, fmin, fstart, vstart;
3421
9270388e
DV		 3422 spin_lock_irq(&mchdev_lock);
3423
2b4e57bd
ED		 3424 /* Enable temp reporting */
3425 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3426 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3427
3428 /* 100ms RC evaluation intervals */
3429 I915_WRITE(RCUPEI, 100000);
3430 I915_WRITE(RCDNEI, 100000);
3431
3432 /* Set max/min thresholds to 90ms and 80ms respectively */
3433 I915_WRITE(RCBMAXAVG, 90000);
3434 I915_WRITE(RCBMINAVG, 80000);
3435
3436 I915_WRITE(MEMIHYST, 1);
3437
3438 /* Set up min, max, and cur for interrupt handling */
3439 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3440 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3441 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3442 MEMMODE_FSTART_SHIFT;
3443
3444 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3445 PXVFREQ_PX_SHIFT;
3446
20e4d407
DV		 3447 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3448 dev_priv->ips.fstart = fstart;
2b4e57bd 3449
20e4d407
DV		 3450 dev_priv->ips.max_delay = fstart;
3451 dev_priv->ips.min_delay = fmin;
3452 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3453
3454 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3455 fmax, fmin, fstart);
3456
3457 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3458
3459 /*
3460 * Interrupts will be enabled in ironlake_irq_postinstall
3461 */
3462
3463 I915_WRITE(VIDSTART, vstart);
3464 POSTING_READ(VIDSTART);
3465
3466 rgvmodectl |= MEMMODE_SWMODE_EN;
3467 I915_WRITE(MEMMODECTL, rgvmodectl);
3468
9270388e 3469 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3470 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3471 mdelay(1);
2b4e57bd
ED		 3472
3473 ironlake_set_drps(dev, fstart);
3474
20e4d407 3475 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3476 I915_READ(0x112e0);
20e4d407
DV		 3477 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3478 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3479 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3480
3481 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3482}
3483
8090c6b9 3484static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3485{
3486 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3487 u16 rgvswctl;
3488
3489 spin_lock_irq(&mchdev_lock);
3490
3491 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3492
3493 /* Ack interrupts, disable EFC interrupt */
3494 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3495 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3496 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3497 I915_WRITE(DEIIR, DE_PCU_EVENT);
3498 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3499
3500 /* Go back to the starting frequency */
20e4d407 3501 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3502 mdelay(1);
2b4e57bd
ED		 3503 rgvswctl |= MEMCTL_CMD_STS;
3504 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3505 mdelay(1);
2b4e57bd 3506
9270388e 3507 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3508}
3509
acbe9475
DV		 3510/* There's a funny hw issue where the hw returns all 0 when reading from
3511 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3512 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3513 * all limits and the gpu stuck at whatever frequency it is at atm).
3514 */
6917c7b9 3515static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3516{
7b9e0ae6 3517 u32 limits;
2b4e57bd 3518
20b46e59
DV		 3519 /* Only set the down limit when we've reached the lowest level to avoid
3520 * getting more interrupts, otherwise leave this clear. This prevents a
3521 * race in the hw when coming out of rc6: There's a tiny window where
3522 * the hw runs at the minimal clock before selecting the desired
3523 * frequency, if the down threshold expires in that window we will not
3524 * receive a down interrupt. */
6917c7b9
CW		 3525 limits = dev_priv->rps.max_delay << 24;
3526 if (val <= dev_priv->rps.min_delay)
c6a828d3 3527 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3528
3529 return limits;
3530}
3531
dd75fdc8
CW		 3532static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3533{
3534 int new_power;
3535
3536 new_power = dev_priv->rps.power;
3537 switch (dev_priv->rps.power) {
3538 case LOW_POWER:
3539 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3540 new_power = BETWEEN;
3541 break;
3542
3543 case BETWEEN:
3544 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3545 new_power = LOW_POWER;
3546 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3547 new_power = HIGH_POWER;
3548 break;
3549
3550 case HIGH_POWER:
3551 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3552 new_power = BETWEEN;
3553 break;
3554 }
3555 /* Max/min bins are special */
3556 if (val == dev_priv->rps.min_delay)
3557 new_power = LOW_POWER;
3558 if (val == dev_priv->rps.max_delay)
3559 new_power = HIGH_POWER;
3560 if (new_power == dev_priv->rps.power)
3561 return;
3562
3563 /* Note the units here are not exactly 1us, but 1280ns. */
3564 switch (new_power) {
3565 case LOW_POWER:
3566 /* Upclock if more than 95% busy over 16ms */
3567 I915_WRITE(GEN6_RP_UP_EI, 12500);
3568 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3569
3570 /* Downclock if less than 85% busy over 32ms */
3571 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3572 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3573
3574 I915_WRITE(GEN6_RP_CONTROL,
3575 GEN6_RP_MEDIA_TURBO |
3576 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3577 GEN6_RP_MEDIA_IS_GFX |
3578 GEN6_RP_ENABLE |
3579 GEN6_RP_UP_BUSY_AVG |
3580 GEN6_RP_DOWN_IDLE_AVG);
3581 break;
3582
3583 case BETWEEN:
3584 /* Upclock if more than 90% busy over 13ms */
3585 I915_WRITE(GEN6_RP_UP_EI, 10250);
3586 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3587
3588 /* Downclock if less than 75% busy over 32ms */
3589 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3590 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3591
3592 I915_WRITE(GEN6_RP_CONTROL,
3593 GEN6_RP_MEDIA_TURBO |
3594 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3595 GEN6_RP_MEDIA_IS_GFX |
3596 GEN6_RP_ENABLE |
3597 GEN6_RP_UP_BUSY_AVG |
3598 GEN6_RP_DOWN_IDLE_AVG);
3599 break;
3600
3601 case HIGH_POWER:
3602 /* Upclock if more than 85% busy over 10ms */
3603 I915_WRITE(GEN6_RP_UP_EI, 8000);
3604 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3605
3606 /* Downclock if less than 60% busy over 32ms */
3607 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3608 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3609
3610 I915_WRITE(GEN6_RP_CONTROL,
3611 GEN6_RP_MEDIA_TURBO |
3612 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3613 GEN6_RP_MEDIA_IS_GFX |
3614 GEN6_RP_ENABLE |
3615 GEN6_RP_UP_BUSY_AVG |
3616 GEN6_RP_DOWN_IDLE_AVG);
3617 break;
3618 }
3619
3620 dev_priv->rps.power = new_power;
3621 dev_priv->rps.last_adj = 0;
3622}
3623
20b46e59
DV		 3624void gen6_set_rps(struct drm_device *dev, u8 val)
3625{
3626 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 3627
4fc688ce 3628 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3629 WARN_ON(val > dev_priv->rps.max_delay);
3630 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3631
c6a828d3 3632 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3633 return;
3634
dd75fdc8
CW		 3635 gen6_set_rps_thresholds(dev_priv, val);
3636
92bd1bf0
RV		 3637 if (IS_HASWELL(dev))
3638 I915_WRITE(GEN6_RPNSWREQ,
3639 HSW_FREQUENCY(val));
3640 else
3641 I915_WRITE(GEN6_RPNSWREQ,
3642 GEN6_FREQUENCY(val) |
3643 GEN6_OFFSET(0) |
3644 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3645
3646 /* Make sure we continue to get interrupts
3647 * until we hit the minimum or maximum frequencies.
3648 */
6917c7b9
CW		 3649 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3650 gen6_rps_limits(dev_priv, val));
7b9e0ae6 3651
d5570a72
BW		 3652 POSTING_READ(GEN6_RPNSWREQ);
3653
c6a828d3 3654 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3655
3656 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3657}
3658
b29c19b6
CW		 3659void gen6_rps_idle(struct drm_i915_private *dev_priv)
3660{
691bb717
DL		 3661 struct drm_device *dev = dev_priv->dev;
3662
b29c19b6 3663 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3664 if (dev_priv->rps.enabled) {
691bb717 3665 if (IS_VALLEYVIEW(dev))
c0951f0c
CW		 3666 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3667 else
3668 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3669 dev_priv->rps.last_adj = 0;
3670 }
b29c19b6
CW		 3671 mutex_unlock(&dev_priv->rps.hw_lock);
3672}
3673
3674void gen6_rps_boost(struct drm_i915_private *dev_priv)
3675{
691bb717
DL		 3676 struct drm_device *dev = dev_priv->dev;
3677
b29c19b6 3678 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 3679 if (dev_priv->rps.enabled) {
691bb717 3680 if (IS_VALLEYVIEW(dev))
c0951f0c
CW		 3681 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3682 else
3683 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3684 dev_priv->rps.last_adj = 0;
3685 }
b29c19b6
CW		 3686 mutex_unlock(&dev_priv->rps.hw_lock);
3687}
3688
0a073b84
JB		 3689void valleyview_set_rps(struct drm_device *dev, u8 val)
3690{
3691 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a 3692
0a073b84
JB		 3693 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3694 WARN_ON(val > dev_priv->rps.max_delay);
3695 WARN_ON(val < dev_priv->rps.min_delay);
3696
73008b98 3697 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
2ec3815f 3698 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 3699 dev_priv->rps.cur_delay,
2ec3815f 3700 vlv_gpu_freq(dev_priv, val), val);
0a073b84
JB		 3701
3702 if (val == dev_priv->rps.cur_delay)
3703 return;
3704
ae99258f 3705 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3706
80814ae4 3707 dev_priv->rps.cur_delay = val;
0a073b84 3708
2ec3815f 3709 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 3710}
3711
44fc7d5c 3712static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3713{
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715
2b4e57bd 3716 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3717 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3718 /* Complete PM interrupt masking here doesn't race with the rps work
3719 * item again unmasking PM interrupts because that is using a different
3720 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3721 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3722
59cdb63d 3723 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3724 dev_priv->rps.pm_iir = 0;
59cdb63d 3725 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3726
4848405c 3727 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3728}
3729
44fc7d5c 3730static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3731{
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733
3734 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3735 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3736
44fc7d5c
DV		 3737 gen6_disable_rps_interrupts(dev);
3738}
3739
3740static void valleyview_disable_rps(struct drm_device *dev)
3741{
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743
3744 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3745
44fc7d5c 3746 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3747
3748 if (dev_priv->vlv_pctx) {
3749 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3750 dev_priv->vlv_pctx = NULL;
3751 }
d20d4f0c
JB		 3752}
3753
dc39fff7
BW		 3754static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3755{
3756 if (IS_GEN6(dev))
3757 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3758
3759 if (IS_HASWELL(dev))
3760 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3761
3762 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3763 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3764 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3765 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3766}
3767
2b4e57bd
ED		 3768int intel_enable_rc6(const struct drm_device *dev)
3769{
eb4926e4
DL		 3770 /* No RC6 before Ironlake */
3771 if (INTEL_INFO(dev)->gen < 5)
3772 return 0;
3773
456470eb 3774 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3775 if (i915_enable_rc6 >= 0)
3776 return i915_enable_rc6;
3777
6567d748
CW		 3778 /* Disable RC6 on Ironlake */
3779 if (INTEL_INFO(dev)->gen == 5)
3780 return 0;
2b4e57bd 3781
dc39fff7 3782 if (IS_HASWELL(dev))
4a637c2c 3783 return INTEL_RC6_ENABLE;
2b4e57bd 3784
456470eb 3785 /* snb/ivb have more than one rc6 state. */
dc39fff7 3786 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3787 return INTEL_RC6_ENABLE;
456470eb 3788
2b4e57bd
ED		 3789 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3790}
3791
44fc7d5c
DV		 3792static void gen6_enable_rps_interrupts(struct drm_device *dev)
3793{
3794 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3795 u32 enabled_intrs;
44fc7d5c
DV		 3796
3797 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3798 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3799 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3800 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3801 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3802
fd547d25 3803 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3804 enabled_intrs = GEN6_PM_RPS_EVENTS;
3805
3806 /* IVB and SNB hard hangs on looping batchbuffer
3807 * if GEN6_PM_UP_EI_EXPIRED is masked.
3808 */
3809 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3810 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3811
3812 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3813}
3814
6edee7f3
BW		 3815static void gen8_enable_rps(struct drm_device *dev)
3816{
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 struct intel_ring_buffer *ring;
3819 uint32_t rc6_mask = 0, rp_state_cap;
3820 int unused;
3821
3822 /* 1a: Software RC state - RC0 */
3823 I915_WRITE(GEN6_RC_STATE, 0);
3824
3825 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3826 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
c8d9a590 3827 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3828
3829 /* 2a: Disable RC states. */
3830 I915_WRITE(GEN6_RC_CONTROL, 0);
3831
3832 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3833
3834 /* 2b: Program RC6 thresholds.*/
3835 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3836 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3837 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3838 for_each_ring(ring, dev_priv, unused)
3839 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3840 I915_WRITE(GEN6_RC_SLEEP, 0);
3841 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3842
3843 /* 3: Enable RC6 */
3844 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3845 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3846 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
3847 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3848 GEN6_RC_CTL_EI_MODE(1) |
3849 rc6_mask);
3850
3851 /* 4 Program defaults and thresholds for RPS*/
3852 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
3853 I915_WRITE(GEN6_RC_VIDEO_FREQ, HSW_FREQUENCY(12)); /* Request 600 MHz */
3854 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3855 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3856
3857 /* Docs recommend 900MHz, and 300 MHz respectively */
3858 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3859 dev_priv->rps.max_delay << 24 |
3860 dev_priv->rps.min_delay << 16);
3861
3862 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3863 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3864 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3865 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3866
3867 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3868
3869 /* 5: Enable RPS */
3870 I915_WRITE(GEN6_RP_CONTROL,
3871 GEN6_RP_MEDIA_TURBO |
3872 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3873 GEN6_RP_MEDIA_IS_GFX |
3874 GEN6_RP_ENABLE |
3875 GEN6_RP_UP_BUSY_AVG |
3876 GEN6_RP_DOWN_IDLE_AVG);
3877
3878 /* 6: Ring frequency + overclocking (our driver does this later */
3879
3880 gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3881
3882 gen6_enable_rps_interrupts(dev);
3883
c8d9a590 3884 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 3885}
3886
79f5b2c7 3887static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3888{
79f5b2c7 3889 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3890 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3891 u32 rp_state_cap;
3892 u32 gt_perf_status;
31643d54 3893 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3894 u32 gtfifodbg;
2b4e57bd 3895 int rc6_mode;
42c0526c 3896 int i, ret;
2b4e57bd 3897
4fc688ce 3898 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3899
2b4e57bd
ED		 3900 /* Here begins a magic sequence of register writes to enable
3901 * auto-downclocking.
3902 *
3903 * Perhaps there might be some value in exposing these to
3904 * userspace...
3905 */
3906 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3907
3908 /* Clear the DBG now so we don't confuse earlier errors */
3909 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3910 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3911 I915_WRITE(GTFIFODBG, gtfifodbg);
3912 }
3913
c8d9a590 3914 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 3915
7b9e0ae6
CW		 3916 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3917 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3918
31c77388
BW		 3919 /* In units of 50MHz */
3920 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3921 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3922 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3923 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3924 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3925 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3926
2b4e57bd
ED		 3927 /* disable the counters and set deterministic thresholds */
3928 I915_WRITE(GEN6_RC_CONTROL, 0);
3929
3930 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3931 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3932 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3933 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3934 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3935
b4519513
CW		 3936 for_each_ring(ring, dev_priv, i)
3937 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3938
3939 I915_WRITE(GEN6_RC_SLEEP, 0);
3940 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 3941 if (IS_IVYBRIDGE(dev))
351aa566
SM		 3942 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3943 else
3944 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3945 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3946 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3947
5a7dc92a 3948 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3949 rc6_mode = intel_enable_rc6(dev_priv->dev);
3950 if (rc6_mode & INTEL_RC6_ENABLE)
3951 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3952
5a7dc92a
ED		 3953 /* We don't use those on Haswell */
3954 if (!IS_HASWELL(dev)) {
3955 if (rc6_mode & INTEL_RC6p_ENABLE)
3956 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3957
5a7dc92a
ED		 3958 if (rc6_mode & INTEL_RC6pp_ENABLE)
3959 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3960 }
2b4e57bd 3961
dc39fff7 3962 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3963
3964 I915_WRITE(GEN6_RC_CONTROL,
3965 rc6_mask |
3966 GEN6_RC_CTL_EI_MODE(1) |
3967 GEN6_RC_CTL_HW_ENABLE);
3968
dd75fdc8
CW		 3969 /* Power down if completely idle for over 50ms */
3970 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3971 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3972
42c0526c 3973 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3974 if (!ret) {
42c0526c
BW		 3975 pcu_mbox = 0;
3976 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3977 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3978 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3979 (dev_priv->rps.max_delay & 0xff) * 50,
3980 (pcu_mbox & 0xff) * 50);
31c77388 3981 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3982 }
3983 } else {
3984 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3985 }
3986
dd75fdc8
CW		 3987 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3988 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3989
44fc7d5c 3990 gen6_enable_rps_interrupts(dev);
2b4e57bd 3991
31643d54
BW		 3992 rc6vids = 0;
3993 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3994 if (IS_GEN6(dev) && ret) {
3995 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3996 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3997 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3998 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3999 rc6vids &= 0xffff00;
4000 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4001 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4002 if (ret)
4003 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4004 }
4005
c8d9a590 4006 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4007}
4008
c67a470b 4009void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4010{
79f5b2c7 4011 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4012 int min_freq = 15;
3ebecd07
CW		 4013 unsigned int gpu_freq;
4014 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4015 int scaling_factor = 180;
eda79642 4016 struct cpufreq_policy *policy;
2b4e57bd 4017
4fc688ce 4018 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4019
eda79642
BW		 4020 policy = cpufreq_cpu_get(0);
4021 if (policy) {
4022 max_ia_freq = policy->cpuinfo.max_freq;
4023 cpufreq_cpu_put(policy);
4024 } else {
4025 /*
4026 * Default to measured freq if none found, PCU will ensure we
4027 * don't go over
4028 */
2b4e57bd 4029 max_ia_freq = tsc_khz;
eda79642 4030 }
2b4e57bd
ED		 4031
4032 /* Convert from kHz to MHz */
4033 max_ia_freq /= 1000;
4034
153b4b95 4035 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4036 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4037 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4038
2b4e57bd
ED		 4039 /*
4040 * For each potential GPU frequency, load a ring frequency we'd like
4041 * to use for memory access. We do this by specifying the IA frequency
4042 * the PCU should use as a reference to determine the ring frequency.
4043 */
c6a828d3 4044 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 4045 gpu_freq--) {
c6a828d3 4046 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 4047 unsigned int ia_freq = 0, ring_freq = 0;
4048
46c764d4
BW		 4049 if (INTEL_INFO(dev)->gen >= 8) {
4050 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4051 ring_freq = max(min_ring_freq, gpu_freq);
4052 } else if (IS_HASWELL(dev)) {
f6aca45c 4053 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4054 ring_freq = max(min_ring_freq, ring_freq);
4055 /* leave ia_freq as the default, chosen by cpufreq */
4056 } else {
4057 /* On older processors, there is no separate ring
4058 * clock domain, so in order to boost the bandwidth
4059 * of the ring, we need to upclock the CPU (ia_freq).
4060 *
4061 * For GPU frequencies less than 750MHz,
4062 * just use the lowest ring freq.
4063 */
4064 if (gpu_freq < min_freq)
4065 ia_freq = 800;
4066 else
4067 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4068 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4069 }
2b4e57bd 4070
42c0526c
BW		 4071 sandybridge_pcode_write(dev_priv,
4072 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4073 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4074 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4075 gpu_freq);
2b4e57bd 4076 }
2b4e57bd
ED		 4077}
4078
0a073b84
JB		 4079int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
4080{
4081 u32 val, rp0;
4082
64936258 4083 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 4084
4085 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4086 /* Clamp to max */
4087 rp0 = min_t(u32, rp0, 0xea);
4088
4089 return rp0;
4090}
4091
4092static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4093{
4094 u32 val, rpe;
4095
64936258 4096 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4097 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4098 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 4099 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4100
4101 return rpe;
4102}
4103
4104int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
4105{
64936258 4106 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 4107}
4108
c9cddffc
JB		 4109static void valleyview_setup_pctx(struct drm_device *dev)
4110{
4111 struct drm_i915_private *dev_priv = dev->dev_private;
4112 struct drm_i915_gem_object *pctx;
4113 unsigned long pctx_paddr;
4114 u32 pcbr;
4115 int pctx_size = 24*1024;
4116
4117 pcbr = I915_READ(VLV_PCBR);
4118 if (pcbr) {
4119 /* BIOS set it up already, grab the pre-alloc'd space */
4120 int pcbr_offset;
4121
4122 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4123 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4124 pcbr_offset,
190d6cd5 4125 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 4126 pctx_size);
4127 goto out;
4128 }
4129
4130 /*
4131 * From the Gunit register HAS:
4132 * The Gfx driver is expected to program this register and ensure
4133 * proper allocation within Gfx stolen memory. For example, this
4134 * register should be programmed such than the PCBR range does not
4135 * overlap with other ranges, such as the frame buffer, protected
4136 * memory, or any other relevant ranges.
4137 */
4138 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4139 if (!pctx) {
4140 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4141 return;
4142 }
4143
4144 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4145 I915_WRITE(VLV_PCBR, pctx_paddr);
4146
4147out:
4148 dev_priv->vlv_pctx = pctx;
4149}
4150
0a073b84
JB		 4151static void valleyview_enable_rps(struct drm_device *dev)
4152{
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_ring_buffer *ring;
a2b23fe0 4155 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4156 int i;
4157
4158 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4159
4160 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4161 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4162 gtfifodbg);
0a073b84
JB		 4163 I915_WRITE(GTFIFODBG, gtfifodbg);
4164 }
4165
c9cddffc
JB		 4166 valleyview_setup_pctx(dev);
4167
c8d9a590
D		 4168 /* If VLV, Forcewake all wells, else re-direct to regular path */
4169 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4170
4171 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4172 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4173 I915_WRITE(GEN6_RP_UP_EI, 66000);
4174 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4175
4176 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4177
4178 I915_WRITE(GEN6_RP_CONTROL,
4179 GEN6_RP_MEDIA_TURBO |
4180 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4181 GEN6_RP_MEDIA_IS_GFX |
4182 GEN6_RP_ENABLE |
4183 GEN6_RP_UP_BUSY_AVG |
4184 GEN6_RP_DOWN_IDLE_CONT);
4185
4186 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4187 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4188 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4189
4190 for_each_ring(ring, dev_priv, i)
4191 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4192
2f0aa304 4193 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 4194
4195 /* allows RC6 residency counter to work */
49798eb2
JB		 4196 I915_WRITE(VLV_COUNTER_CONTROL,
4197 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4198 VLV_MEDIA_RC6_COUNT_EN |
4199 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0 4200 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 4201 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 4202
4203 intel_print_rc6_info(dev, rc6_mode);
4204
a2b23fe0 4205 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4206
64936258 4207 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4208
4209 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4210 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4211
0a073b84 4212 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98 4213 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
2ec3815f 4214 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
73008b98 4215 dev_priv->rps.cur_delay);
0a073b84
JB		 4216
4217 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4218 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98 4219 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
2ec3815f 4220 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
73008b98 4221 dev_priv->rps.max_delay);
0a073b84 4222
73008b98
VS		 4223 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4224 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
2ec3815f 4225 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4226 dev_priv->rps.rpe_delay);
0a073b84 4227
73008b98
VS		 4228 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4229 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
2ec3815f 4230 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
73008b98 4231 dev_priv->rps.min_delay);
0a073b84 4232
73008b98 4233 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
2ec3815f 4234 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
73008b98 4235 dev_priv->rps.rpe_delay);
0a073b84 4236
73008b98 4237 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 4238
44fc7d5c 4239 gen6_enable_rps_interrupts(dev);
0a073b84 4240
c8d9a590 4241 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 4242}
4243
930ebb46 4244void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4245{
4246 struct drm_i915_private *dev_priv = dev->dev_private;
4247
3e373948
DV		 4248 if (dev_priv->ips.renderctx) {
4249 i915_gem_object_unpin(dev_priv->ips.renderctx);
4250 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4251 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4252 }
4253
3e373948
DV		 4254 if (dev_priv->ips.pwrctx) {
4255 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4256 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4257 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4258 }
4259}
4260
930ebb46 4261static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4262{
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264
4265 if (I915_READ(PWRCTXA)) {
4266 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4267 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4268 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4269 50);
4270
4271 I915_WRITE(PWRCTXA, 0);
4272 POSTING_READ(PWRCTXA);
4273
4274 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4275 POSTING_READ(RSTDBYCTL);
4276 }
2b4e57bd
ED		 4277}
4278
4279static int ironlake_setup_rc6(struct drm_device *dev)
4280{
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282
3e373948
DV		 4283 if (dev_priv->ips.renderctx == NULL)
4284 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4285 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4286 return -ENOMEM;
4287
3e373948
DV		 4288 if (dev_priv->ips.pwrctx == NULL)
4289 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4290 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4291 ironlake_teardown_rc6(dev);
4292 return -ENOMEM;
4293 }
4294
4295 return 0;
4296}
4297
930ebb46 4298static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4299{
4300 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 4301 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 4302 bool was_interruptible;
2b4e57bd
ED		 4303 int ret;
4304
4305 /* rc6 disabled by default due to repeated reports of hanging during
4306 * boot and resume.
4307 */
4308 if (!intel_enable_rc6(dev))
4309 return;
4310
79f5b2c7
DV		 4311 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4312
2b4e57bd 4313 ret = ironlake_setup_rc6(dev);
79f5b2c7 4314 if (ret)
2b4e57bd 4315 return;
2b4e57bd 4316
3e960501
CW		 4317 was_interruptible = dev_priv->mm.interruptible;
4318 dev_priv->mm.interruptible = false;
4319
2b4e57bd
ED		 4320 /*
4321 * GPU can automatically power down the render unit if given a page
4322 * to save state.
4323 */
6d90c952 4324 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4325 if (ret) {
4326 ironlake_teardown_rc6(dev);
3e960501 4327 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4328 return;
4329 }
4330
6d90c952
DV		 4331 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4332 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4333 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4334 MI_MM_SPACE_GTT |
4335 MI_SAVE_EXT_STATE_EN |
4336 MI_RESTORE_EXT_STATE_EN |
4337 MI_RESTORE_INHIBIT);
4338 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4339 intel_ring_emit(ring, MI_NOOP);
4340 intel_ring_emit(ring, MI_FLUSH);
4341 intel_ring_advance(ring);
2b4e57bd
ED		 4342
4343 /*
4344 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4345 * does an implicit flush, combined with MI_FLUSH above, it should be
4346 * safe to assume that renderctx is valid
4347 */
3e960501
CW		 4348 ret = intel_ring_idle(ring);
4349 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4350 if (ret) {
def27a58 4351 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4352 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4353 return;
4354 }
4355
f343c5f6 4356 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4357 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 4358
4359 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 4360}
4361
dde18883
ED		 4362static unsigned long intel_pxfreq(u32 vidfreq)
4363{
4364 unsigned long freq;
4365 int div = (vidfreq & 0x3f0000) >> 16;
4366 int post = (vidfreq & 0x3000) >> 12;
4367 int pre = (vidfreq & 0x7);
4368
4369 if (!pre)
4370 return 0;
4371
4372 freq = ((div * 133333) / ((1<<post) * pre));
4373
4374 return freq;
4375}
4376
eb48eb00
DV		 4377static const struct cparams {
4378 u16 i;
4379 u16 t;
4380 u16 m;
4381 u16 c;
4382} cparams[] = {
4383 { 1, 1333, 301, 28664 },
4384 { 1, 1066, 294, 24460 },
4385 { 1, 800, 294, 25192 },
4386 { 0, 1333, 276, 27605 },
4387 { 0, 1066, 276, 27605 },
4388 { 0, 800, 231, 23784 },
4389};
4390
f531dcb2 4391static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4392{
4393 u64 total_count, diff, ret;
4394 u32 count1, count2, count3, m = 0, c = 0;
4395 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4396 int i;
4397
02d71956
DV		 4398 assert_spin_locked(&mchdev_lock);
4399
20e4d407 4400 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4401
4402 /* Prevent division-by-zero if we are asking too fast.
4403 * Also, we don't get interesting results if we are polling
4404 * faster than once in 10ms, so just return the saved value
4405 * in such cases.
4406 */
4407 if (diff1 <= 10)
20e4d407 4408 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4409
4410 count1 = I915_READ(DMIEC);
4411 count2 = I915_READ(DDREC);
4412 count3 = I915_READ(CSIEC);
4413
4414 total_count = count1 + count2 + count3;
4415
4416 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4417 if (total_count < dev_priv->ips.last_count1) {
4418 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4419 diff += total_count;
4420 } else {
20e4d407 4421 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4422 }
4423
4424 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4425 if (cparams[i].i == dev_priv->ips.c_m &&
4426 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4427 m = cparams[i].m;
4428 c = cparams[i].c;
4429 break;
4430 }
4431 }
4432
4433 diff = div_u64(diff, diff1);
4434 ret = ((m * diff) + c);
4435 ret = div_u64(ret, 10);
4436
20e4d407
DV		 4437 dev_priv->ips.last_count1 = total_count;
4438 dev_priv->ips.last_time1 = now;
eb48eb00 4439
20e4d407 4440 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4441
4442 return ret;
4443}
4444
f531dcb2
CW		 4445unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4446{
4447 unsigned long val;
4448
4449 if (dev_priv->info->gen != 5)
4450 return 0;
4451
4452 spin_lock_irq(&mchdev_lock);
4453
4454 val = __i915_chipset_val(dev_priv);
4455
4456 spin_unlock_irq(&mchdev_lock);
4457
4458 return val;
4459}
4460
eb48eb00
DV		 4461unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4462{
4463 unsigned long m, x, b;
4464 u32 tsfs;
4465
4466 tsfs = I915_READ(TSFS);
4467
4468 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4469 x = I915_READ8(TR1);
4470
4471 b = tsfs & TSFS_INTR_MASK;
4472
4473 return ((m * x) / 127) - b;
4474}
4475
4476static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4477{
4478 static const struct v_table {
4479 u16 vd; /* in .1 mil */
4480 u16 vm; /* in .1 mil */
4481 } v_table[] = {
4482 { 0, 0, },
4483 { 375, 0, },
4484 { 500, 0, },
4485 { 625, 0, },
4486 { 750, 0, },
4487 { 875, 0, },
4488 { 1000, 0, },
4489 { 1125, 0, },
4490 { 4125, 3000, },
4491 { 4125, 3000, },
4492 { 4125, 3000, },
4493 { 4125, 3000, },
4494 { 4125, 3000, },
4495 { 4125, 3000, },
4496 { 4125, 3000, },
4497 { 4125, 3000, },
4498 { 4125, 3000, },
4499 { 4125, 3000, },
4500 { 4125, 3000, },
4501 { 4125, 3000, },
4502 { 4125, 3000, },
4503 { 4125, 3000, },
4504 { 4125, 3000, },
4505 { 4125, 3000, },
4506 { 4125, 3000, },
4507 { 4125, 3000, },
4508 { 4125, 3000, },
4509 { 4125, 3000, },
4510 { 4125, 3000, },
4511 { 4125, 3000, },
4512 { 4125, 3000, },
4513 { 4125, 3000, },
4514 { 4250, 3125, },
4515 { 4375, 3250, },
4516 { 4500, 3375, },
4517 { 4625, 3500, },
4518 { 4750, 3625, },
4519 { 4875, 3750, },
4520 { 5000, 3875, },
4521 { 5125, 4000, },
4522 { 5250, 4125, },
4523 { 5375, 4250, },
4524 { 5500, 4375, },
4525 { 5625, 4500, },
4526 { 5750, 4625, },
4527 { 5875, 4750, },
4528 { 6000, 4875, },
4529 { 6125, 5000, },
4530 { 6250, 5125, },
4531 { 6375, 5250, },
4532 { 6500, 5375, },
4533 { 6625, 5500, },
4534 { 6750, 5625, },
4535 { 6875, 5750, },
4536 { 7000, 5875, },
4537 { 7125, 6000, },
4538 { 7250, 6125, },
4539 { 7375, 6250, },
4540 { 7500, 6375, },
4541 { 7625, 6500, },
4542 { 7750, 6625, },
4543 { 7875, 6750, },
4544 { 8000, 6875, },
4545 { 8125, 7000, },
4546 { 8250, 7125, },
4547 { 8375, 7250, },
4548 { 8500, 7375, },
4549 { 8625, 7500, },
4550 { 8750, 7625, },
4551 { 8875, 7750, },
4552 { 9000, 7875, },
4553 { 9125, 8000, },
4554 { 9250, 8125, },
4555 { 9375, 8250, },
4556 { 9500, 8375, },
4557 { 9625, 8500, },
4558 { 9750, 8625, },
4559 { 9875, 8750, },
4560 { 10000, 8875, },
4561 { 10125, 9000, },
4562 { 10250, 9125, },
4563 { 10375, 9250, },
4564 { 10500, 9375, },
4565 { 10625, 9500, },
4566 { 10750, 9625, },
4567 { 10875, 9750, },
4568 { 11000, 9875, },
4569 { 11125, 10000, },
4570 { 11250, 10125, },
4571 { 11375, 10250, },
4572 { 11500, 10375, },
4573 { 11625, 10500, },
4574 { 11750, 10625, },
4575 { 11875, 10750, },
4576 { 12000, 10875, },
4577 { 12125, 11000, },
4578 { 12250, 11125, },
4579 { 12375, 11250, },
4580 { 12500, 11375, },
4581 { 12625, 11500, },
4582 { 12750, 11625, },
4583 { 12875, 11750, },
4584 { 13000, 11875, },
4585 { 13125, 12000, },
4586 { 13250, 12125, },
4587 { 13375, 12250, },
4588 { 13500, 12375, },
4589 { 13625, 12500, },
4590 { 13750, 12625, },
4591 { 13875, 12750, },
4592 { 14000, 12875, },
4593 { 14125, 13000, },
4594 { 14250, 13125, },
4595 { 14375, 13250, },
4596 { 14500, 13375, },
4597 { 14625, 13500, },
4598 { 14750, 13625, },
4599 { 14875, 13750, },
4600 { 15000, 13875, },
4601 { 15125, 14000, },
4602 { 15250, 14125, },
4603 { 15375, 14250, },
4604 { 15500, 14375, },
4605 { 15625, 14500, },
4606 { 15750, 14625, },
4607 { 15875, 14750, },
4608 { 16000, 14875, },
4609 { 16125, 15000, },
4610 };
4611 if (dev_priv->info->is_mobile)
4612 return v_table[pxvid].vm;
4613 else
4614 return v_table[pxvid].vd;
4615}
4616
02d71956 4617static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4618{
4619 struct timespec now, diff1;
4620 u64 diff;
4621 unsigned long diffms;
4622 u32 count;
4623
02d71956 4624 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4625
4626 getrawmonotonic(&now);
20e4d407 4627 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4628
4629 /* Don't divide by 0 */
4630 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4631 if (!diffms)
4632 return;
4633
4634 count = I915_READ(GFXEC);
4635
20e4d407
DV		 4636 if (count < dev_priv->ips.last_count2) {
4637 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4638 diff += count;
4639 } else {
20e4d407 4640 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4641 }
4642
20e4d407
DV		 4643 dev_priv->ips.last_count2 = count;
4644 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4645
4646 /* More magic constants... */
4647 diff = diff * 1181;
4648 diff = div_u64(diff, diffms * 10);
20e4d407 4649 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4650}
4651
02d71956
DV		 4652void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4653{
4654 if (dev_priv->info->gen != 5)
4655 return;
4656
9270388e 4657 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4658
4659 __i915_update_gfx_val(dev_priv);
4660
9270388e 4661 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4662}
4663
f531dcb2 4664static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4665{
4666 unsigned long t, corr, state1, corr2, state2;
4667 u32 pxvid, ext_v;
4668
02d71956
DV		 4669 assert_spin_locked(&mchdev_lock);
4670
c6a828d3 4671 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4672 pxvid = (pxvid >> 24) & 0x7f;
4673 ext_v = pvid_to_extvid(dev_priv, pxvid);
4674
4675 state1 = ext_v;
4676
4677 t = i915_mch_val(dev_priv);
4678
4679 /* Revel in the empirically derived constants */
4680
4681 /* Correction factor in 1/100000 units */
4682 if (t > 80)
4683 corr = ((t * 2349) + 135940);
4684 else if (t >= 50)
4685 corr = ((t * 964) + 29317);
4686 else /* < 50 */
4687 corr = ((t * 301) + 1004);
4688
4689 corr = corr * ((150142 * state1) / 10000 - 78642);
4690 corr /= 100000;
20e4d407 4691 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4692
4693 state2 = (corr2 * state1) / 10000;
4694 state2 /= 100; /* convert to mW */
4695
02d71956 4696 __i915_update_gfx_val(dev_priv);
eb48eb00 4697
20e4d407 4698 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4699}
4700
f531dcb2
CW		 4701unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4702{
4703 unsigned long val;
4704
4705 if (dev_priv->info->gen != 5)
4706 return 0;
4707
4708 spin_lock_irq(&mchdev_lock);
4709
4710 val = __i915_gfx_val(dev_priv);
4711
4712 spin_unlock_irq(&mchdev_lock);
4713
4714 return val;
4715}
4716
eb48eb00
DV		 4717/**
4718 * i915_read_mch_val - return value for IPS use
4719 *
4720 * Calculate and return a value for the IPS driver to use when deciding whether
4721 * we have thermal and power headroom to increase CPU or GPU power budget.
4722 */
4723unsigned long i915_read_mch_val(void)
4724{
4725 struct drm_i915_private *dev_priv;
4726 unsigned long chipset_val, graphics_val, ret = 0;
4727
9270388e 4728 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4729 if (!i915_mch_dev)
4730 goto out_unlock;
4731 dev_priv = i915_mch_dev;
4732
f531dcb2
CW		 4733 chipset_val = __i915_chipset_val(dev_priv);
4734 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4735
4736 ret = chipset_val + graphics_val;
4737
4738out_unlock:
9270388e 4739 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4740
4741 return ret;
4742}
4743EXPORT_SYMBOL_GPL(i915_read_mch_val);
4744
4745/**
4746 * i915_gpu_raise - raise GPU frequency limit
4747 *
4748 * Raise the limit; IPS indicates we have thermal headroom.
4749 */
4750bool i915_gpu_raise(void)
4751{
4752 struct drm_i915_private *dev_priv;
4753 bool ret = true;
4754
9270388e 4755 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4756 if (!i915_mch_dev) {
4757 ret = false;
4758 goto out_unlock;
4759 }
4760 dev_priv = i915_mch_dev;
4761
20e4d407
DV		 4762 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4763 dev_priv->ips.max_delay--;
eb48eb00
DV		 4764
4765out_unlock:
9270388e 4766 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4767
4768 return ret;
4769}
4770EXPORT_SYMBOL_GPL(i915_gpu_raise);
4771
4772/**
4773 * i915_gpu_lower - lower GPU frequency limit
4774 *
4775 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4776 * frequency maximum.
4777 */
4778bool i915_gpu_lower(void)
4779{
4780 struct drm_i915_private *dev_priv;
4781 bool ret = true;
4782
9270388e 4783 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4784 if (!i915_mch_dev) {
4785 ret = false;
4786 goto out_unlock;
4787 }
4788 dev_priv = i915_mch_dev;
4789
20e4d407
DV		 4790 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4791 dev_priv->ips.max_delay++;
eb48eb00
DV		 4792
4793out_unlock:
9270388e 4794 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4795
4796 return ret;
4797}
4798EXPORT_SYMBOL_GPL(i915_gpu_lower);
4799
4800/**
4801 * i915_gpu_busy - indicate GPU business to IPS
4802 *
4803 * Tell the IPS driver whether or not the GPU is busy.
4804 */
4805bool i915_gpu_busy(void)
4806{
4807 struct drm_i915_private *dev_priv;
f047e395 4808 struct intel_ring_buffer *ring;
eb48eb00 4809 bool ret = false;
f047e395 4810 int i;
eb48eb00 4811
9270388e 4812 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4813 if (!i915_mch_dev)
4814 goto out_unlock;
4815 dev_priv = i915_mch_dev;
4816
f047e395
CW		 4817 for_each_ring(ring, dev_priv, i)
4818 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4819
4820out_unlock:
9270388e 4821 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4822
4823 return ret;
4824}
4825EXPORT_SYMBOL_GPL(i915_gpu_busy);
4826
4827/**
4828 * i915_gpu_turbo_disable - disable graphics turbo
4829 *
4830 * Disable graphics turbo by resetting the max frequency and setting the
4831 * current frequency to the default.
4832 */
4833bool i915_gpu_turbo_disable(void)
4834{
4835 struct drm_i915_private *dev_priv;
4836 bool ret = true;
4837
9270388e 4838 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4839 if (!i915_mch_dev) {
4840 ret = false;
4841 goto out_unlock;
4842 }
4843 dev_priv = i915_mch_dev;
4844
20e4d407 4845 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4846
20e4d407 4847 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4848 ret = false;
4849
4850out_unlock:
9270388e 4851 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4852
4853 return ret;
4854}
4855EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4856
4857/**
4858 * Tells the intel_ips driver that the i915 driver is now loaded, if
4859 * IPS got loaded first.
4860 *
4861 * This awkward dance is so that neither module has to depend on the
4862 * other in order for IPS to do the appropriate communication of
4863 * GPU turbo limits to i915.
4864 */
4865static void
4866ips_ping_for_i915_load(void)
4867{
4868 void (*link)(void);
4869
4870 link = symbol_get(ips_link_to_i915_driver);
4871 if (link) {
4872 link();
4873 symbol_put(ips_link_to_i915_driver);
4874 }
4875}
4876
4877void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4878{
02d71956
DV		 4879 /* We only register the i915 ips part with intel-ips once everything is
4880 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4881 spin_lock_irq(&mchdev_lock);
eb48eb00 4882 i915_mch_dev = dev_priv;
9270388e 4883 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4884
4885 ips_ping_for_i915_load();
4886}
4887
4888void intel_gpu_ips_teardown(void)
4889{
9270388e 4890 spin_lock_irq(&mchdev_lock);
eb48eb00 4891 i915_mch_dev = NULL;
9270388e 4892 spin_unlock_irq(&mchdev_lock);
eb48eb00 4893}
8090c6b9 4894static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4895{
4896 struct drm_i915_private *dev_priv = dev->dev_private;
4897 u32 lcfuse;
4898 u8 pxw[16];
4899 int i;
4900
4901 /* Disable to program */
4902 I915_WRITE(ECR, 0);
4903 POSTING_READ(ECR);
4904
4905 /* Program energy weights for various events */
4906 I915_WRITE(SDEW, 0x15040d00);
4907 I915_WRITE(CSIEW0, 0x007f0000);
4908 I915_WRITE(CSIEW1, 0x1e220004);
4909 I915_WRITE(CSIEW2, 0x04000004);
4910
4911 for (i = 0; i < 5; i++)
4912 I915_WRITE(PEW + (i * 4), 0);
4913 for (i = 0; i < 3; i++)
4914 I915_WRITE(DEW + (i * 4), 0);
4915
4916 /* Program P-state weights to account for frequency power adjustment */
4917 for (i = 0; i < 16; i++) {
4918 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4919 unsigned long freq = intel_pxfreq(pxvidfreq);
4920 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4921 PXVFREQ_PX_SHIFT;
4922 unsigned long val;
4923
4924 val = vid * vid;
4925 val *= (freq / 1000);
4926 val *= 255;
4927 val /= (127*127*900);
4928 if (val > 0xff)
4929 DRM_ERROR("bad pxval: %ld\n", val);
4930 pxw[i] = val;
4931 }
4932 /* Render standby states get 0 weight */
4933 pxw[14] = 0;
4934 pxw[15] = 0;
4935
4936 for (i = 0; i < 4; i++) {
4937 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4938 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4939 I915_WRITE(PXW + (i * 4), val);
4940 }
4941
4942 /* Adjust magic regs to magic values (more experimental results) */
4943 I915_WRITE(OGW0, 0);
4944 I915_WRITE(OGW1, 0);
4945 I915_WRITE(EG0, 0x00007f00);
4946 I915_WRITE(EG1, 0x0000000e);
4947 I915_WRITE(EG2, 0x000e0000);
4948 I915_WRITE(EG3, 0x68000300);
4949 I915_WRITE(EG4, 0x42000000);
4950 I915_WRITE(EG5, 0x00140031);
4951 I915_WRITE(EG6, 0);
4952 I915_WRITE(EG7, 0);
4953
4954 for (i = 0; i < 8; i++)
4955 I915_WRITE(PXWL + (i * 4), 0);
4956
4957 /* Enable PMON + select events */
4958 I915_WRITE(ECR, 0x80000019);
4959
4960 lcfuse = I915_READ(LCFUSE02);
4961
20e4d407 4962 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4963}
4964
8090c6b9
DV		 4965void intel_disable_gt_powersave(struct drm_device *dev)
4966{
1a01ab3b
JB		 4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968
fd0c0642
DV		 4969 /* Interrupts should be disabled already to avoid re-arming. */
4970 WARN_ON(dev->irq_enabled);
4971
930ebb46 4972 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4973 ironlake_disable_drps(dev);
930ebb46 4974 ironlake_disable_rc6(dev);
0a073b84 4975 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4976 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4977 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4978 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4979 if (IS_VALLEYVIEW(dev))
4980 valleyview_disable_rps(dev);
4981 else
4982 gen6_disable_rps(dev);
c0951f0c 4983 dev_priv->rps.enabled = false;
4fc688ce 4984 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4985 }
8090c6b9
DV		 4986}
4987
1a01ab3b
JB		 4988static void intel_gen6_powersave_work(struct work_struct *work)
4989{
4990 struct drm_i915_private *dev_priv =
4991 container_of(work, struct drm_i915_private,
4992 rps.delayed_resume_work.work);
4993 struct drm_device *dev = dev_priv->dev;
4994
4fc688ce 4995 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4996
4997 if (IS_VALLEYVIEW(dev)) {
4998 valleyview_enable_rps(dev);
6edee7f3
BW		 4999 } else if (IS_BROADWELL(dev)) {
5000 gen8_enable_rps(dev);
5001 gen6_update_ring_freq(dev);
0a073b84
JB		 5002 } else {
5003 gen6_enable_rps(dev);
5004 gen6_update_ring_freq(dev);
5005 }
c0951f0c 5006 dev_priv->rps.enabled = true;
4fc688ce 5007 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 5008}
5009
8090c6b9
DV		 5010void intel_enable_gt_powersave(struct drm_device *dev)
5011{
1a01ab3b
JB		 5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013
8090c6b9
DV		 5014 if (IS_IRONLAKE_M(dev)) {
5015 ironlake_enable_drps(dev);
5016 ironlake_enable_rc6(dev);
5017 intel_init_emon(dev);
0a073b84 5018 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 5019 /*
5020 * PCU communication is slow and this doesn't need to be
5021 * done at any specific time, so do this out of our fast path
5022 * to make resume and init faster.
5023 */
5024 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5025 round_jiffies_up_relative(HZ));
8090c6b9
DV		 5026 }
5027}
5028
3107bd48
DV		 5029static void ibx_init_clock_gating(struct drm_device *dev)
5030{
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032
5033 /*
5034 * On Ibex Peak and Cougar Point, we need to disable clock
5035 * gating for the panel power sequencer or it will fail to
5036 * start up when no ports are active.
5037 */
5038 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5039}
5040
0e088b8f
VS		 5041static void g4x_disable_trickle_feed(struct drm_device *dev)
5042{
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044 int pipe;
5045
5046 for_each_pipe(pipe) {
5047 I915_WRITE(DSPCNTR(pipe),
5048 I915_READ(DSPCNTR(pipe)) |
5049 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 5050 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 5051 }
5052}
5053
1fa61106 5054static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5055{
5056 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5057 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5058
f1e8fa56
DL		 5059 /*
5060 * Required for FBC
5061 * WaFbcDisableDpfcClockGating:ilk
5062 */
4d47e4f5
DL		 5063 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5064 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5065 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5066
5067 I915_WRITE(PCH_3DCGDIS0,
5068 MARIUNIT_CLOCK_GATE_DISABLE |
5069 SVSMUNIT_CLOCK_GATE_DISABLE);
5070 I915_WRITE(PCH_3DCGDIS1,
5071 VFMUNIT_CLOCK_GATE_DISABLE);
5072
6f1d69b0
ED		 5073 /*
5074 * According to the spec the following bits should be set in
5075 * order to enable memory self-refresh
5076 * The bit 22/21 of 0x42004
5077 * The bit 5 of 0x42020
5078 * The bit 15 of 0x45000
5079 */
5080 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5081 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5082 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5083 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 5084 I915_WRITE(DISP_ARB_CTL,
5085 (I915_READ(DISP_ARB_CTL) |
5086 DISP_FBC_WM_DIS));
5087 I915_WRITE(WM3_LP_ILK, 0);
5088 I915_WRITE(WM2_LP_ILK, 0);
5089 I915_WRITE(WM1_LP_ILK, 0);
5090
5091 /*
5092 * Based on the document from hardware guys the following bits
5093 * should be set unconditionally in order to enable FBC.
5094 * The bit 22 of 0x42000
5095 * The bit 22 of 0x42004
5096 * The bit 7,8,9 of 0x42020.
5097 */
5098 if (IS_IRONLAKE_M(dev)) {
4bb35334 5099 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 5100 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5101 I915_READ(ILK_DISPLAY_CHICKEN1) |
5102 ILK_FBCQ_DIS);
5103 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5104 I915_READ(ILK_DISPLAY_CHICKEN2) |
5105 ILK_DPARB_GATE);
6f1d69b0
ED		 5106 }
5107
4d47e4f5
DL		 5108 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5109
6f1d69b0
ED		 5110 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5111 I915_READ(ILK_DISPLAY_CHICKEN2) |
5112 ILK_ELPIN_409_SELECT);
5113 I915_WRITE(_3D_CHICKEN2,
5114 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5115 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5116
ecdb4eb7 5117 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 5118 I915_WRITE(CACHE_MODE_0,
5119 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5120
0e088b8f 5121 g4x_disable_trickle_feed(dev);
bdad2b2f 5122
3107bd48
DV		 5123 ibx_init_clock_gating(dev);
5124}
5125
5126static void cpt_init_clock_gating(struct drm_device *dev)
5127{
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 int pipe;
3f704fa2 5130 uint32_t val;
3107bd48
DV		 5131
5132 /*
5133 * On Ibex Peak and Cougar Point, we need to disable clock
5134 * gating for the panel power sequencer or it will fail to
5135 * start up when no ports are active.
5136 */
cd664078
JB		 5137 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5138 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5139 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5140 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5141 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5142 /* The below fixes the weird display corruption, a few pixels shifted
5143 * downward, on (only) LVDS of some HP laptops with IVY.
5144 */
3f704fa2 5145 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5146 val = I915_READ(TRANS_CHICKEN2(pipe));
5147 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5148 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5149 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5150 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5151 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5152 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5153 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5154 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5155 }
3107bd48
DV		 5156 /* WADP0ClockGatingDisable */
5157 for_each_pipe(pipe) {
5158 I915_WRITE(TRANS_CHICKEN1(pipe),
5159 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5160 }
6f1d69b0
ED		 5161}
5162
1d7aaa0c
DV		 5163static void gen6_check_mch_setup(struct drm_device *dev)
5164{
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166 uint32_t tmp;
5167
5168 tmp = I915_READ(MCH_SSKPD);
5169 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5170 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5171 DRM_INFO("This can cause pipe underruns and display issues.\n");
5172 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5173 }
5174}
5175
1fa61106 5176static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5177{
5178 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5179 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5180
231e54f6 5181 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5182
5183 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5184 I915_READ(ILK_DISPLAY_CHICKEN2) |
5185 ILK_ELPIN_409_SELECT);
5186
ecdb4eb7 5187 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5188 I915_WRITE(_3D_CHICKEN,
5189 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5190
ecdb4eb7 5191 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5192 if (IS_SNB_GT1(dev))
5193 I915_WRITE(GEN6_GT_MODE,
5194 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5195
6f1d69b0
ED		 5196 I915_WRITE(WM3_LP_ILK, 0);
5197 I915_WRITE(WM2_LP_ILK, 0);
5198 I915_WRITE(WM1_LP_ILK, 0);
5199
6f1d69b0 5200 I915_WRITE(CACHE_MODE_0,
50743298 5201 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5202
5203 I915_WRITE(GEN6_UCGCTL1,
5204 I915_READ(GEN6_UCGCTL1) |
5205 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5206 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5207
5208 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5209 * gating disable must be set. Failure to set it results in
5210 * flickering pixels due to Z write ordering failures after
5211 * some amount of runtime in the Mesa "fire" demo, and Unigine
5212 * Sanctuary and Tropics, and apparently anything else with
5213 * alpha test or pixel discard.
5214 *
5215 * According to the spec, bit 11 (RCCUNIT) must also be set,
5216 * but we didn't debug actual testcases to find it out.
0f846f81 5217 *
ecdb4eb7
DL		 5218 * Also apply WaDisableVDSUnitClockGating:snb and
5219 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 5220 */
5221 I915_WRITE(GEN6_UCGCTL2,
0f846f81 5222 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 5223 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5224 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5225
5226 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 5227 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5228 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 5229
5230 /*
5231 * According to the spec the following bits should be
5232 * set in order to enable memory self-refresh and fbc:
5233 * The bit21 and bit22 of 0x42000
5234 * The bit21 and bit22 of 0x42004
5235 * The bit5 and bit7 of 0x42020
5236 * The bit14 of 0x70180
5237 * The bit14 of 0x71180
4bb35334
DL		 5238 *
5239 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5240 */
5241 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5242 I915_READ(ILK_DISPLAY_CHICKEN1) |
5243 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5244 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5245 I915_READ(ILK_DISPLAY_CHICKEN2) |
5246 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5247 I915_WRITE(ILK_DSPCLK_GATE_D,
5248 I915_READ(ILK_DSPCLK_GATE_D) |
5249 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5250 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5251
0e088b8f 5252 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 5253
5254 /* The default value should be 0x200 according to docs, but the two
5255 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5256 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5257 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 5258
5259 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5260
5261 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5262}
5263
5264static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5265{
5266 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5267
5268 reg &= ~GEN7_FF_SCHED_MASK;
5269 reg |= GEN7_FF_TS_SCHED_HW;
5270 reg |= GEN7_FF_VS_SCHED_HW;
5271 reg |= GEN7_FF_DS_SCHED_HW;
5272
41c0b3a8
BW		 5273 if (IS_HASWELL(dev_priv->dev))
5274 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5275
6f1d69b0
ED		 5276 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5277}
5278
17a303ec
PZ		 5279static void lpt_init_clock_gating(struct drm_device *dev)
5280{
5281 struct drm_i915_private *dev_priv = dev->dev_private;
5282
5283 /*
5284 * TODO: this bit should only be enabled when really needed, then
5285 * disabled when not needed anymore in order to save power.
5286 */
5287 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5288 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5289 I915_READ(SOUTH_DSPCLK_GATE_D) |
5290 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5291
5292 /* WADPOClockGatingDisable:hsw */
5293 I915_WRITE(_TRANSA_CHICKEN1,
5294 I915_READ(_TRANSA_CHICKEN1) |
5295 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5296}
5297
7d708ee4
ID		 5298static void lpt_suspend_hw(struct drm_device *dev)
5299{
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301
5302 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5303 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5304
5305 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5306 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5307 }
5308}
5309
1020a5c2
BW		 5310static void gen8_init_clock_gating(struct drm_device *dev)
5311{
5312 struct drm_i915_private *dev_priv = dev->dev_private;
fe4ab3ce 5313 enum pipe i;
1020a5c2
BW		 5314
5315 I915_WRITE(WM3_LP_ILK, 0);
5316 I915_WRITE(WM2_LP_ILK, 0);
5317 I915_WRITE(WM1_LP_ILK, 0);
50ed5fbd
BW		 5318
5319 /* FIXME(BDW): Check all the w/a, some might only apply to
5320 * pre-production hw. */
5321
fd392b60
BW		 5322 WARN(!i915_preliminary_hw_support,
5323 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n");
5324 I915_WRITE(HALF_SLICE_CHICKEN3,
5325 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
bf66347c
BW		 5326 I915_WRITE(HALF_SLICE_CHICKEN3,
5327 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
4afe8d33
BW		 5328 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5329
7f88da0c
BW		 5330 I915_WRITE(_3D_CHICKEN3,
5331 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5332
a75f3628
BW		 5333 I915_WRITE(COMMON_SLICE_CHICKEN2,
5334 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5335
4c2e7a5f
BW		 5336 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5337 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5338
ab57fff1 5339 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 5340 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 5341
ab57fff1 5342 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5343 I915_WRITE(CHICKEN_PAR1_1,
5344 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5345
ab57fff1 5346 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
fe4ab3ce
BW		 5347 for_each_pipe(i) {
5348 I915_WRITE(CHICKEN_PIPESL_1(i),
5349 I915_READ(CHICKEN_PIPESL_1(i) |
5350 DPRS_MASK_VBLANK_SRD));
5351 }
63801f21
BW		 5352
5353 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5354 * workaround for for a possible hang in the unlikely event a TLB
5355 * invalidation occurs during a PSD flush.
5356 */
5357 I915_WRITE(HDC_CHICKEN0,
5358 I915_READ(HDC_CHICKEN0) |
5359 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
ab57fff1
BW		 5360
5361 /* WaVSRefCountFullforceMissDisable:bdw */
5362 /* WaDSRefCountFullforceMissDisable:bdw */
5363 I915_WRITE(GEN7_FF_THREAD_MODE,
5364 I915_READ(GEN7_FF_THREAD_MODE) &
5365 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
1020a5c2
BW		 5366}
5367
cad2a2d7
ED		 5368static void haswell_init_clock_gating(struct drm_device *dev)
5369{
5370 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 5371
5372 I915_WRITE(WM3_LP_ILK, 0);
5373 I915_WRITE(WM2_LP_ILK, 0);
5374 I915_WRITE(WM1_LP_ILK, 0);
5375
5376 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5377 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 5378 */
5379 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5380
ecdb4eb7 5381 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 5382 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5383 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5384
ecdb4eb7 5385 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 5386 I915_WRITE(GEN7_L3CNTLREG1,
5387 GEN7_WA_FOR_GEN7_L3_CONTROL);
5388 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5389 GEN7_WA_L3_CHICKEN_MODE);
5390
f3fc4884
FJ		 5391 /* L3 caching of data atomics doesn't work -- disable it. */
5392 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5393 I915_WRITE(HSW_ROW_CHICKEN3,
5394 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5395
ecdb4eb7 5396 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5397 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5398 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5399 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5400
ecdb4eb7 5401 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 5402 gen7_setup_fixed_func_scheduler(dev_priv);
5403
ecdb4eb7 5404 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5405 I915_WRITE(CACHE_MODE_1,
5406 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5407
ecdb4eb7 5408 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5409 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5410
90a88643
PZ		 5411 /* WaRsPkgCStateDisplayPMReq:hsw */
5412 I915_WRITE(CHICKEN_PAR1_1,
5413 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5414
17a303ec 5415 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5416}
5417
1fa61106 5418static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5419{
5420 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5421 uint32_t snpcr;
6f1d69b0 5422
6f1d69b0
ED		 5423 I915_WRITE(WM3_LP_ILK, 0);
5424 I915_WRITE(WM2_LP_ILK, 0);
5425 I915_WRITE(WM1_LP_ILK, 0);
5426
231e54f6 5427 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5428
ecdb4eb7 5429 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5430 I915_WRITE(_3D_CHICKEN3,
5431 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5432
ecdb4eb7 5433 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5434 I915_WRITE(IVB_CHICKEN3,
5435 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5436 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5437
ecdb4eb7 5438 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5439 if (IS_IVB_GT1(dev))
5440 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5441 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5442 else
5443 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5444 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5445
ecdb4eb7 5446 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5447 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5448 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5449
ecdb4eb7 5450 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5451 I915_WRITE(GEN7_L3CNTLREG1,
5452 GEN7_WA_FOR_GEN7_L3_CONTROL);
5453 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5454 GEN7_WA_L3_CHICKEN_MODE);
5455 if (IS_IVB_GT1(dev))
5456 I915_WRITE(GEN7_ROW_CHICKEN2,
5457 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5458 else
5459 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5460 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5461
6f1d69b0 5462
ecdb4eb7 5463 /* WaForceL3Serialization:ivb */
61939d97
JB		 5464 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5465 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5466
0f846f81
JB		 5467 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5468 * gating disable must be set. Failure to set it results in
5469 * flickering pixels due to Z write ordering failures after
5470 * some amount of runtime in the Mesa "fire" demo, and Unigine
5471 * Sanctuary and Tropics, and apparently anything else with
5472 * alpha test or pixel discard.
5473 *
5474 * According to the spec, bit 11 (RCCUNIT) must also be set,
5475 * but we didn't debug actual testcases to find it out.
5476 *
5477 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5478 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5479 */
5480 I915_WRITE(GEN6_UCGCTL2,
5481 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5482 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5483
ecdb4eb7 5484 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5485 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5486 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5487 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5488
0e088b8f 5489 g4x_disable_trickle_feed(dev);
6f1d69b0 5490
ecdb4eb7 5491 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5492 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5493
ecdb4eb7 5494 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5495 I915_WRITE(CACHE_MODE_1,
5496 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5497
5498 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5499 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5500 snpcr |= GEN6_MBC_SNPCR_MED;
5501 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5502
ab5c608b
BW		 5503 if (!HAS_PCH_NOP(dev))
5504 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5505
5506 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5507}
5508
1fa61106 5509static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5510{
5511 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5512 u32 val;
5513
5514 mutex_lock(&dev_priv->rps.hw_lock);
5515 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5516 mutex_unlock(&dev_priv->rps.hw_lock);
5517 switch ((val >> 6) & 3) {
5518 case 0:
85b1d7b3
JB		 5519 dev_priv->mem_freq = 800;
5520 break;
f64a28a7 5521 case 1:
85b1d7b3
JB		 5522 dev_priv->mem_freq = 1066;
5523 break;
f64a28a7 5524 case 2:
85b1d7b3
JB		 5525 dev_priv->mem_freq = 1333;
5526 break;
f64a28a7 5527 case 3:
2325991e 5528 dev_priv->mem_freq = 1333;
f64a28a7 5529 break;
85b1d7b3
JB		 5530 }
5531 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5532
d7fe0cc0 5533 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5534
ecdb4eb7 5535 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5536 I915_WRITE(_3D_CHICKEN3,
5537 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5538
ecdb4eb7 5539 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5540 I915_WRITE(IVB_CHICKEN3,
5541 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5542 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5543
ecdb4eb7 5544 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5545 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5546 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5547 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5548
ecdb4eb7 5549 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5550 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5551 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5552
ecdb4eb7 5553 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5554 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5555 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5556
ecdb4eb7 5557 /* WaForceL3Serialization:vlv */
61939d97
JB		 5558 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5559 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5560
ecdb4eb7 5561 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5562 I915_WRITE(GEN7_ROW_CHICKEN2,
5563 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5564
ecdb4eb7 5565 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5566 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5567 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5568 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5569
0f846f81
JB		 5570 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5571 * gating disable must be set. Failure to set it results in
5572 * flickering pixels due to Z write ordering failures after
5573 * some amount of runtime in the Mesa "fire" demo, and Unigine
5574 * Sanctuary and Tropics, and apparently anything else with
5575 * alpha test or pixel discard.
5576 *
5577 * According to the spec, bit 11 (RCCUNIT) must also be set,
5578 * but we didn't debug actual testcases to find it out.
5579 *
5580 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5581 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5582 *
ecdb4eb7
DL		 5583 * Also apply WaDisableVDSUnitClockGating:vlv and
5584 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5585 */
5586 I915_WRITE(GEN6_UCGCTL2,
5587 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5588 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5589 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5590 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5591 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5592
e3f33d46
JB		 5593 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5594
e0d8d59b 5595 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5596
6b26c86d
DV		 5597 I915_WRITE(CACHE_MODE_1,
5598 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5599
2d809570 5600 /*
ecdb4eb7 5601 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5602 * Disable clock gating on th GCFG unit to prevent a delay
5603 * in the reporting of vblank events.
5604 */
4e8c84a5
JB		 5605 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5606
5607 /* Conservative clock gating settings for now */
5608 I915_WRITE(0x9400, 0xffffffff);
5609 I915_WRITE(0x9404, 0xffffffff);
5610 I915_WRITE(0x9408, 0xffffffff);
5611 I915_WRITE(0x940c, 0xffffffff);
5612 I915_WRITE(0x9410, 0xffffffff);
5613 I915_WRITE(0x9414, 0xffffffff);
5614 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5615}
5616
1fa61106 5617static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5618{
5619 struct drm_i915_private *dev_priv = dev->dev_private;
5620 uint32_t dspclk_gate;
5621
5622 I915_WRITE(RENCLK_GATE_D1, 0);
5623 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5624 GS_UNIT_CLOCK_GATE_DISABLE |
5625 CL_UNIT_CLOCK_GATE_DISABLE);
5626 I915_WRITE(RAMCLK_GATE_D, 0);
5627 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5628 OVRUNIT_CLOCK_GATE_DISABLE |
5629 OVCUNIT_CLOCK_GATE_DISABLE;
5630 if (IS_GM45(dev))
5631 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5632 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5633
5634 /* WaDisableRenderCachePipelinedFlush */
5635 I915_WRITE(CACHE_MODE_0,
5636 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5637
0e088b8f 5638 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5639}
5640
1fa61106 5641static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5642{
5643 struct drm_i915_private *dev_priv = dev->dev_private;
5644
5645 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5646 I915_WRITE(RENCLK_GATE_D2, 0);
5647 I915_WRITE(DSPCLK_GATE_D, 0);
5648 I915_WRITE(RAMCLK_GATE_D, 0);
5649 I915_WRITE16(DEUC, 0);
20f94967
VS		 5650 I915_WRITE(MI_ARB_STATE,
5651 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5652}
5653
1fa61106 5654static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5655{
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657
5658 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5659 I965_RCC_CLOCK_GATE_DISABLE |
5660 I965_RCPB_CLOCK_GATE_DISABLE |
5661 I965_ISC_CLOCK_GATE_DISABLE |
5662 I965_FBC_CLOCK_GATE_DISABLE);
5663 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5664 I915_WRITE(MI_ARB_STATE,
5665 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5666}
5667
1fa61106 5668static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5669{
5670 struct drm_i915_private *dev_priv = dev->dev_private;
5671 u32 dstate = I915_READ(D_STATE);
5672
5673 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5674 DSTATE_DOT_CLOCK_GATING;
5675 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5676
5677 if (IS_PINEVIEW(dev))
5678 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5679
5680 /* IIR "flip pending" means done if this bit is set */
5681 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5682}
5683
1fa61106 5684static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5685{
5686 struct drm_i915_private *dev_priv = dev->dev_private;
5687
5688 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5689}
5690
1fa61106 5691static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5692{
5693 struct drm_i915_private *dev_priv = dev->dev_private;
5694
5695 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5696}
5697
6f1d69b0
ED		 5698void intel_init_clock_gating(struct drm_device *dev)
5699{
5700 struct drm_i915_private *dev_priv = dev->dev_private;
5701
5702 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5703}
5704
7d708ee4
ID		 5705void intel_suspend_hw(struct drm_device *dev)
5706{
5707 if (HAS_PCH_LPT(dev))
5708 lpt_suspend_hw(dev);
5709}
5710
c1ca727f
ID		 5711#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5712 for (i = 0; \
5713 i < (power_domains)->power_well_count && \
5714 ((power_well) = &(power_domains)->power_wells[i]); \
5715 i++) \
5716 if ((power_well)->domains & (domain_mask))
5717
5718#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5719 for (i = (power_domains)->power_well_count - 1; \
5720 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5721 i--) \
5722 if ((power_well)->domains & (domain_mask))
5723
15d199ea
PZ		 5724/**
5725 * We should only use the power well if we explicitly asked the hardware to
5726 * enable it, so check if it's enabled and also check if we've requested it to
5727 * be enabled.
5728 */
c1ca727f
ID		 5729static bool hsw_power_well_enabled(struct drm_device *dev,
5730 struct i915_power_well *power_well)
5731{
5732 struct drm_i915_private *dev_priv = dev->dev_private;
5733
5734 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5735 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5736}
5737
ddf9c536
ID		 5738bool intel_display_power_enabled_sw(struct drm_device *dev,
5739 enum intel_display_power_domain domain)
5740{
5741 struct drm_i915_private *dev_priv = dev->dev_private;
5742 struct i915_power_domains *power_domains;
5743
5744 power_domains = &dev_priv->power_domains;
5745
5746 return power_domains->domain_use_count[domain];
5747}
5748
b97186f0
PZ		 5749bool intel_display_power_enabled(struct drm_device *dev,
5750 enum intel_display_power_domain domain)
15d199ea
PZ		 5751{
5752 struct drm_i915_private *dev_priv = dev->dev_private;
c1ca727f
ID		 5753 struct i915_power_domains *power_domains;
5754 struct i915_power_well *power_well;
5755 bool is_enabled;
5756 int i;
15d199ea 5757
c1ca727f
ID		 5758 power_domains = &dev_priv->power_domains;
5759
5760 is_enabled = true;
5761
5762 mutex_lock(&power_domains->lock);
5763 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6f3ef5dd
ID		 5764 if (power_well->always_on)
5765 continue;
5766
c1ca727f
ID		 5767 if (!power_well->is_enabled(dev, power_well)) {
5768 is_enabled = false;
5769 break;
5770 }
5771 }
5772 mutex_unlock(&power_domains->lock);
5773
5774 return is_enabled;
15d199ea
PZ		 5775}
5776
d5e8fdc8
PZ		 5777static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5778{
5779 struct drm_device *dev = dev_priv->dev;
5780 unsigned long irqflags;
5781
f9dcb0df
PZ		 5782 /*
5783 * After we re-enable the power well, if we touch VGA register 0x3d5
5784 * we'll get unclaimed register interrupts. This stops after we write
5785 * anything to the VGA MSR register. The vgacon module uses this
5786 * register all the time, so if we unbind our driver and, as a
5787 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5788 * console_unlock(). So make here we touch the VGA MSR register, making
5789 * sure vgacon can keep working normally without triggering interrupts
5790 * and error messages.
5791 */
5792 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5793 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5794 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5795
d5e8fdc8
PZ		 5796 if (IS_BROADWELL(dev)) {
5797 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5798 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5799 dev_priv->de_irq_mask[PIPE_B]);
5800 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5801 ~dev_priv->de_irq_mask[PIPE_B] |
5802 GEN8_PIPE_VBLANK);
5803 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5804 dev_priv->de_irq_mask[PIPE_C]);
5805 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5806 ~dev_priv->de_irq_mask[PIPE_C] |
5807 GEN8_PIPE_VBLANK);
5808 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5809 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5810 }
5811}
5812
5813static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5814{
5815 struct drm_device *dev = dev_priv->dev;
5816 enum pipe p;
5817 unsigned long irqflags;
5818
5819 /*
5820 * After this, the registers on the pipes that are part of the power
5821 * well will become zero, so we have to adjust our counters according to
5822 * that.
5823 *
5824 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5825 */
5826 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5827 for_each_pipe(p)
5828 if (p != PIPE_A)
5829 dev->vblank[p].last = 0;
5830 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5831}
5832
c1ca727f
ID		 5833static void hsw_set_power_well(struct drm_device *dev,
5834 struct i915_power_well *power_well, bool enable)
d0d3e513
ED		 5835{
5836 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5837 bool is_enabled, enable_requested;
5838 uint32_t tmp;
d0d3e513 5839
d62292c8
PZ		 5840 WARN_ON(dev_priv->pc8.enabled);
5841
fa42e23c 5842 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5843 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5844 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5845
fa42e23c
PZ		 5846 if (enable) {
5847 if (!enable_requested)
6aedd1f5
PZ		 5848 I915_WRITE(HSW_PWR_WELL_DRIVER,
5849 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5850
fa42e23c
PZ		 5851 if (!is_enabled) {
5852 DRM_DEBUG_KMS("Enabling power well\n");
5853 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5854 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5855 DRM_ERROR("Timeout enabling power well\n");
5856 }
596cc11e 5857
d5e8fdc8 5858 hsw_power_well_post_enable(dev_priv);
fa42e23c
PZ		 5859 } else {
5860 if (enable_requested) {
5861 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5862 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5863 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb 5864
d5e8fdc8 5865 hsw_power_well_post_disable(dev_priv);
d0d3e513
ED		 5866 }
5867 }
fa42e23c 5868}
d0d3e513 5869
b4ed4484
ID		 5870static void __intel_power_well_get(struct drm_device *dev,
5871 struct i915_power_well *power_well)
2d66aef5 5872{
d62292c8
PZ		 5873 struct drm_i915_private *dev_priv = dev->dev_private;
5874
5875 if (!power_well->count++ && power_well->set) {
5876 hsw_disable_package_c8(dev_priv);
c1ca727f 5877 power_well->set(dev, power_well, true);
d62292c8 5878 }
2d66aef5
VS		 5879}
5880
b4ed4484
ID		 5881static void __intel_power_well_put(struct drm_device *dev,
5882 struct i915_power_well *power_well)
2d66aef5 5883{
d62292c8
PZ		 5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885
2d66aef5 5886 WARN_ON(!power_well->count);
c1ca727f 5887
d62292c8
PZ		 5888 if (!--power_well->count && power_well->set &&
5889 i915_disable_power_well) {
c1ca727f 5890 power_well->set(dev, power_well, false);
d62292c8
PZ		 5891 hsw_enable_package_c8(dev_priv);
5892 }
2d66aef5
VS		 5893}
5894
6765625e
VS		 5895void intel_display_power_get(struct drm_device *dev,
5896 enum intel_display_power_domain domain)
5897{
5898 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5899 struct i915_power_domains *power_domains;
c1ca727f
ID		 5900 struct i915_power_well *power_well;
5901 int i;
6765625e 5902
83c00f55
ID		 5903 power_domains = &dev_priv->power_domains;
5904
5905 mutex_lock(&power_domains->lock);
1da51581 5906
c1ca727f
ID		 5907 for_each_power_well(i, power_well, BIT(domain), power_domains)
5908 __intel_power_well_get(dev, power_well);
1da51581 5909
ddf9c536
ID		 5910 power_domains->domain_use_count[domain]++;
5911
83c00f55 5912 mutex_unlock(&power_domains->lock);
6765625e
VS		 5913}
5914
5915void intel_display_power_put(struct drm_device *dev,
5916 enum intel_display_power_domain domain)
5917{
5918 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5919 struct i915_power_domains *power_domains;
c1ca727f
ID		 5920 struct i915_power_well *power_well;
5921 int i;
6765625e 5922
83c00f55
ID		 5923 power_domains = &dev_priv->power_domains;
5924
5925 mutex_lock(&power_domains->lock);
1da51581 5926
1da51581
ID		 5927 WARN_ON(!power_domains->domain_use_count[domain]);
5928 power_domains->domain_use_count[domain]--;
ddf9c536
ID		 5929
5930 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5931 __intel_power_well_put(dev, power_well);
1da51581 5932
83c00f55 5933 mutex_unlock(&power_domains->lock);
6765625e
VS		 5934}
5935
83c00f55 5936static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5937
5938/* Display audio driver power well request */
5939void i915_request_power_well(void)
5940{
b4ed4484
ID		 5941 struct drm_i915_private *dev_priv;
5942
a38911a3
WX		 5943 if (WARN_ON(!hsw_pwr))
5944 return;
5945
b4ed4484
ID		 5946 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5947 power_domains);
fbeeaa23 5948 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5949}
5950EXPORT_SYMBOL_GPL(i915_request_power_well);
5951
5952/* Display audio driver power well release */
5953void i915_release_power_well(void)
5954{
b4ed4484
ID		 5955 struct drm_i915_private *dev_priv;
5956
a38911a3
WX		 5957 if (WARN_ON(!hsw_pwr))
5958 return;
5959
b4ed4484
ID		 5960 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5961 power_domains);
fbeeaa23 5962 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
a38911a3
WX		 5963}
5964EXPORT_SYMBOL_GPL(i915_release_power_well);
5965
1c2256df
ID		 5966static struct i915_power_well i9xx_always_on_power_well[] = {
5967 {
5968 .name = "always-on",
5969 .always_on = 1,
5970 .domains = POWER_DOMAIN_MASK,
5971 },
5972};
5973
c1ca727f 5974static struct i915_power_well hsw_power_wells[] = {
6f3ef5dd
ID		 5975 {
5976 .name = "always-on",
5977 .always_on = 1,
5978 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5979 },
c1ca727f
ID		 5980 {
5981 .name = "display",
5982 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5983 .is_enabled = hsw_power_well_enabled,
5984 .set = hsw_set_power_well,
5985 },
5986};
5987
5988static struct i915_power_well bdw_power_wells[] = {
6f3ef5dd
ID		 5989 {
5990 .name = "always-on",
5991 .always_on = 1,
5992 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5993 },
c1ca727f
ID		 5994 {
5995 .name = "display",
5996 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5997 .is_enabled = hsw_power_well_enabled,
5998 .set = hsw_set_power_well,
5999 },
6000};
6001
6002#define set_power_wells(power_domains, __power_wells) ({ \
6003 (power_domains)->power_wells = (__power_wells); \
6004 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6005})
6006
ddb642fb 6007int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 6008{
6009 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 6010 struct i915_power_domains *power_domains = &dev_priv->power_domains;
c1ca727f 6011
83c00f55 6012 mutex_init(&power_domains->lock);
a38911a3 6013
c1ca727f
ID		 6014 /*
6015 * The enabling order will be from lower to higher indexed wells,
6016 * the disabling order is reversed.
6017 */
6018 if (IS_HASWELL(dev)) {
6019 set_power_wells(power_domains, hsw_power_wells);
6020 hsw_pwr = power_domains;
6021 } else if (IS_BROADWELL(dev)) {
6022 set_power_wells(power_domains, bdw_power_wells);
6023 hsw_pwr = power_domains;
6024 } else {
1c2256df 6025 set_power_wells(power_domains, i9xx_always_on_power_well);
c1ca727f 6026 }
a38911a3
WX		 6027
6028 return 0;
6029}
6030
ddb642fb 6031void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 6032{
6033 hsw_pwr = NULL;
6034}
6035
ddb642fb 6036static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 6037{
6038 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 6039 struct i915_power_domains *power_domains = &dev_priv->power_domains;
6040 struct i915_power_well *power_well;
c1ca727f 6041 int i;
9cdb826c 6042
83c00f55 6043 mutex_lock(&power_domains->lock);
c1ca727f
ID		 6044 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6045 if (power_well->set)
6046 power_well->set(dev, power_well, power_well->count > 0);
6047 }
83c00f55 6048 mutex_unlock(&power_domains->lock);
a38911a3
WX		 6049}
6050
fa42e23c
PZ		 6051/*
6052 * Starting with Haswell, we have a "Power Down Well" that can be turned off
6053 * when not needed anymore. We have 4 registers that can request the power well
6054 * to be enabled, and it will only be disabled if none of the registers is
6055 * requesting it to be enabled.
d0d3e513 6056 */
ddb642fb 6057void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 6058{
6059 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 6060
fa42e23c 6061 /* For now, we need the power well to be always enabled. */
baa70707 6062 intel_display_set_init_power(dev, true);
ddb642fb 6063 intel_power_domains_resume(dev);
d0d3e513 6064
f7243ac9
ID		 6065 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
6066 return;
6067
fa42e23c
PZ		 6068 /* We're taking over the BIOS, so clear any requests made by it since
6069 * the driver is in charge now. */
6aedd1f5 6070 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 6071 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 6072}
6073
c67a470b
PZ		 6074/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
6075void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6076{
6077 hsw_disable_package_c8(dev_priv);
6078}
6079
6080void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6081{
6082 hsw_enable_package_c8(dev_priv);
6083}
6084
8a187455
PZ		 6085void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6086{
6087 struct drm_device *dev = dev_priv->dev;
6088 struct device *device = &dev->pdev->dev;
6089
6090 if (!HAS_RUNTIME_PM(dev))
6091 return;
6092
6093 pm_runtime_get_sync(device);
6094 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6095}
6096
6097void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6098{
6099 struct drm_device *dev = dev_priv->dev;
6100 struct device *device = &dev->pdev->dev;
6101
6102 if (!HAS_RUNTIME_PM(dev))
6103 return;
6104
6105 pm_runtime_mark_last_busy(device);
6106 pm_runtime_put_autosuspend(device);
6107}
6108
6109void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6110{
6111 struct drm_device *dev = dev_priv->dev;
6112 struct device *device = &dev->pdev->dev;
6113
6114 dev_priv->pm.suspended = false;
6115
6116 if (!HAS_RUNTIME_PM(dev))
6117 return;
6118
6119 pm_runtime_set_active(device);
6120
6121 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6122 pm_runtime_mark_last_busy(device);
6123 pm_runtime_use_autosuspend(device);
6124}
6125
6126void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6127{
6128 struct drm_device *dev = dev_priv->dev;
6129 struct device *device = &dev->pdev->dev;
6130
6131 if (!HAS_RUNTIME_PM(dev))
6132 return;
6133
6134 /* Make sure we're not suspended first. */
6135 pm_runtime_get_sync(device);
6136 pm_runtime_disable(device);
6137}
6138
1fa61106
ED		 6139/* Set up chip specific power management-related functions */
6140void intel_init_pm(struct drm_device *dev)
6141{
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143
6144 if (I915_HAS_FBC(dev)) {
40045465 6145 if (INTEL_INFO(dev)->gen >= 7) {
1fa61106 6146 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
40045465
VS		 6147 dev_priv->display.enable_fbc = gen7_enable_fbc;
6148 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6149 } else if (INTEL_INFO(dev)->gen >= 5) {
6150 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6151 dev_priv->display.enable_fbc = ironlake_enable_fbc;
1fa61106
ED		 6152 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6153 } else if (IS_GM45(dev)) {
6154 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6155 dev_priv->display.enable_fbc = g4x_enable_fbc;
6156 dev_priv->display.disable_fbc = g4x_disable_fbc;
40045465 6157 } else {
1fa61106
ED		 6158 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6159 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6160 dev_priv->display.disable_fbc = i8xx_disable_fbc;
993495ae
VS		 6161
6162 /* This value was pulled out of someone's hat */
6163 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1fa61106 6164 }
1fa61106
ED		 6165 }
6166
c921aba8
DV		 6167 /* For cxsr */
6168 if (IS_PINEVIEW(dev))
6169 i915_pineview_get_mem_freq(dev);
6170 else if (IS_GEN5(dev))
6171 i915_ironlake_get_mem_freq(dev);
6172
1fa61106
ED		 6173 /* For FIFO watermark updates */
6174 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 6175 intel_setup_wm_latency(dev);
6176
1fa61106 6177 if (IS_GEN5(dev)) {
53615a5e
VS		 6178 if (dev_priv->wm.pri_latency[1] &&
6179 dev_priv->wm.spr_latency[1] &&
6180 dev_priv->wm.cur_latency[1])
1fa61106
ED		 6181 dev_priv->display.update_wm = ironlake_update_wm;
6182 else {
6183 DRM_DEBUG_KMS("Failed to get proper latency. "
6184 "Disable CxSR\n");
6185 dev_priv->display.update_wm = NULL;
6186 }
6187 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6188 } else if (IS_GEN6(dev)) {
53615a5e
VS		 6189 if (dev_priv->wm.pri_latency[0] &&
6190 dev_priv->wm.spr_latency[0] &&
6191 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 6192 dev_priv->display.update_wm = sandybridge_update_wm;
6193 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6194 } else {
6195 DRM_DEBUG_KMS("Failed to read display plane latency. "
6196 "Disable CxSR\n");
6197 dev_priv->display.update_wm = NULL;
6198 }
6199 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6200 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 6201 if (dev_priv->wm.pri_latency[0] &&
6202 dev_priv->wm.spr_latency[0] &&
6203 dev_priv->wm.cur_latency[0]) {
c43d0188 6204 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 6205 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6206 } else {
6207 DRM_DEBUG_KMS("Failed to read display plane latency. "
6208 "Disable CxSR\n");
6209 dev_priv->display.update_wm = NULL;
6210 }
6211 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 6212 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 6213 if (dev_priv->wm.pri_latency[0] &&
6214 dev_priv->wm.spr_latency[0] &&
6215 dev_priv->wm.cur_latency[0]) {
1011d8c4 6216 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 6217 dev_priv->display.update_sprite_wm =
6218 haswell_update_sprite_wm;
6b8a5eeb
ED		 6219 } else {
6220 DRM_DEBUG_KMS("Failed to read display plane latency. "
6221 "Disable CxSR\n");
6222 dev_priv->display.update_wm = NULL;
6223 }
cad2a2d7 6224 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1020a5c2
BW		 6225 } else if (INTEL_INFO(dev)->gen == 8) {
6226 dev_priv->display.init_clock_gating = gen8_init_clock_gating;
1fa61106
ED		 6227 } else
6228 dev_priv->display.update_wm = NULL;
6229 } else if (IS_VALLEYVIEW(dev)) {
6230 dev_priv->display.update_wm = valleyview_update_wm;
6231 dev_priv->display.init_clock_gating =
6232 valleyview_init_clock_gating;
1fa61106
ED		 6233 } else if (IS_PINEVIEW(dev)) {
6234 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6235 dev_priv->is_ddr3,
6236 dev_priv->fsb_freq,
6237 dev_priv->mem_freq)) {
6238 DRM_INFO("failed to find known CxSR latency "
6239 "(found ddr%s fsb freq %d, mem freq %d), "
6240 "disabling CxSR\n",
6241 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6242 dev_priv->fsb_freq, dev_priv->mem_freq);
6243 /* Disable CxSR and never update its watermark again */
6244 pineview_disable_cxsr(dev);
6245 dev_priv->display.update_wm = NULL;
6246 } else
6247 dev_priv->display.update_wm = pineview_update_wm;
6248 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6249 } else if (IS_G4X(dev)) {
6250 dev_priv->display.update_wm = g4x_update_wm;
6251 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6252 } else if (IS_GEN4(dev)) {
6253 dev_priv->display.update_wm = i965_update_wm;
6254 if (IS_CRESTLINE(dev))
6255 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6256 else if (IS_BROADWATER(dev))
6257 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6258 } else if (IS_GEN3(dev)) {
6259 dev_priv->display.update_wm = i9xx_update_wm;
6260 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6261 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6262 } else if (IS_I865G(dev)) {
6263 dev_priv->display.update_wm = i830_update_wm;
6264 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6265 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6266 } else if (IS_I85X(dev)) {
6267 dev_priv->display.update_wm = i9xx_update_wm;
6268 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6269 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6270 } else {
6271 dev_priv->display.update_wm = i830_update_wm;
6272 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6273 if (IS_845G(dev))
6274 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6275 else
6276 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6277 }
6278}
6279
42c0526c
BW		 6280int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6281{
4fc688ce 6282 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6283
6284 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6285 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6286 return -EAGAIN;
6287 }
6288
6289 I915_WRITE(GEN6_PCODE_DATA, *val);
6290 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6291
6292 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6293 500)) {
6294 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6295 return -ETIMEDOUT;
6296 }
6297
6298 *val = I915_READ(GEN6_PCODE_DATA);
6299 I915_WRITE(GEN6_PCODE_DATA, 0);
6300
6301 return 0;
6302}
6303
6304int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6305{
4fc688ce 6306 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 6307
6308 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6309 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6310 return -EAGAIN;
6311 }
6312
6313 I915_WRITE(GEN6_PCODE_DATA, val);
6314 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6315
6316 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6317 500)) {
6318 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6319 return -ETIMEDOUT;
6320 }
6321
6322 I915_WRITE(GEN6_PCODE_DATA, 0);
6323
6324 return 0;
6325}
a0e4e199 6326
2ec3815f 6327int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
855ba3be 6328{
07ab118b 6329 int div;
855ba3be 6330
07ab118b 6331 /* 4 x czclk */
2ec3815f 6332 switch (dev_priv->mem_freq) {
855ba3be 6333 case 800:
07ab118b 6334 div = 10;
855ba3be
JB		 6335 break;
6336 case 1066:
07ab118b 6337 div = 12;
855ba3be
JB		 6338 break;
6339 case 1333:
07ab118b 6340 div = 16;
855ba3be
JB		 6341 break;
6342 default:
6343 return -1;
6344 }
6345
2ec3815f 6346 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 6347}
6348
2ec3815f 6349int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6350{
07ab118b 6351 int mul;
855ba3be 6352
07ab118b 6353 /* 4 x czclk */
2ec3815f 6354 switch (dev_priv->mem_freq) {
855ba3be 6355 case 800:
07ab118b 6356 mul = 10;
855ba3be
JB		 6357 break;
6358 case 1066:
07ab118b 6359 mul = 12;
855ba3be
JB		 6360 break;
6361 case 1333:
07ab118b 6362 mul = 16;
855ba3be
JB		 6363 break;
6364 default:
6365 return -1;
6366 }
6367
2ec3815f 6368 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
855ba3be
JB		 6369}
6370
907b28c5
CW		 6371void intel_pm_init(struct drm_device *dev)
6372{
6373 struct drm_i915_private *dev_priv = dev->dev_private;
6374
6375 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6376 intel_gen6_powersave_work);
6377}
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